1 /* 2 * Low-Level PCI Support for PC -- Routing of Interrupts 3 * 4 * (c) 1999--2000 Martin Mares <mj@ucw.cz> 5 */ 6 7 #include <linux/types.h> 8 #include <linux/kernel.h> 9 #include <linux/pci.h> 10 #include <linux/init.h> 11 #include <linux/slab.h> 12 #include <linux/interrupt.h> 13 #include <linux/dmi.h> 14 #include <linux/io.h> 15 #include <linux/smp.h> 16 #include <asm/io_apic.h> 17 #include <linux/irq.h> 18 #include <linux/acpi.h> 19 #include <asm/pci_x86.h> 20 21 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) 22 #define PIRQ_VERSION 0x0100 23 24 static int broken_hp_bios_irq9; 25 static int acer_tm360_irqrouting; 26 27 static struct irq_routing_table *pirq_table; 28 29 static int pirq_enable_irq(struct pci_dev *dev); 30 31 /* 32 * Never use: 0, 1, 2 (timer, keyboard, and cascade) 33 * Avoid using: 13, 14 and 15 (FP error and IDE). 34 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse) 35 */ 36 unsigned int pcibios_irq_mask = 0xfff8; 37 38 static int pirq_penalty[16] = { 39 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000, 40 0, 0, 0, 0, 1000, 100000, 100000, 100000 41 }; 42 43 struct irq_router { 44 char *name; 45 u16 vendor, device; 46 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq); 47 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, 48 int new); 49 }; 50 51 struct irq_router_handler { 52 u16 vendor; 53 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device); 54 }; 55 56 int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL; 57 void (*pcibios_disable_irq)(struct pci_dev *dev) = NULL; 58 59 /* 60 * Check passed address for the PCI IRQ Routing Table signature 61 * and perform checksum verification. 62 */ 63 64 static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr) 65 { 66 struct irq_routing_table *rt; 67 int i; 68 u8 sum; 69 70 rt = (struct irq_routing_table *) addr; 71 if (rt->signature != PIRQ_SIGNATURE || 72 rt->version != PIRQ_VERSION || 73 rt->size % 16 || 74 rt->size < sizeof(struct irq_routing_table)) 75 return NULL; 76 sum = 0; 77 for (i = 0; i < rt->size; i++) 78 sum += addr[i]; 79 if (!sum) { 80 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n", 81 rt); 82 return rt; 83 } 84 return NULL; 85 } 86 87 88 89 /* 90 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table. 91 */ 92 93 static struct irq_routing_table * __init pirq_find_routing_table(void) 94 { 95 u8 *addr; 96 struct irq_routing_table *rt; 97 98 if (pirq_table_addr) { 99 rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr)); 100 if (rt) 101 return rt; 102 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n"); 103 } 104 for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) { 105 rt = pirq_check_routing_table(addr); 106 if (rt) 107 return rt; 108 } 109 return NULL; 110 } 111 112 /* 113 * If we have a IRQ routing table, use it to search for peer host 114 * bridges. It's a gross hack, but since there are no other known 115 * ways how to get a list of buses, we have to go this way. 116 */ 117 118 static void __init pirq_peer_trick(void) 119 { 120 struct irq_routing_table *rt = pirq_table; 121 u8 busmap[256]; 122 int i; 123 struct irq_info *e; 124 125 memset(busmap, 0, sizeof(busmap)); 126 for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) { 127 e = &rt->slots[i]; 128 #ifdef DEBUG 129 { 130 int j; 131 DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot); 132 for (j = 0; j < 4; j++) 133 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap); 134 DBG("\n"); 135 } 136 #endif 137 busmap[e->bus] = 1; 138 } 139 for (i = 1; i < 256; i++) { 140 int node; 141 if (!busmap[i] || pci_find_bus(0, i)) 142 continue; 143 node = get_mp_bus_to_node(i); 144 if (pci_scan_bus_on_node(i, &pci_root_ops, node)) 145 printk(KERN_INFO "PCI: Discovered primary peer " 146 "bus %02x [IRQ]\n", i); 147 } 148 pcibios_last_bus = -1; 149 } 150 151 /* 152 * Code for querying and setting of IRQ routes on various interrupt routers. 153 */ 154 155 void eisa_set_level_irq(unsigned int irq) 156 { 157 unsigned char mask = 1 << (irq & 7); 158 unsigned int port = 0x4d0 + (irq >> 3); 159 unsigned char val; 160 static u16 eisa_irq_mask; 161 162 if (irq >= 16 || (1 << irq) & eisa_irq_mask) 163 return; 164 165 eisa_irq_mask |= (1 << irq); 166 printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq); 167 val = inb(port); 168 if (!(val & mask)) { 169 DBG(KERN_DEBUG " -> edge"); 170 outb(val | mask, port); 171 } 172 } 173 174 /* 175 * Common IRQ routing practice: nibbles in config space, 176 * offset by some magic constant. 177 */ 178 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr) 179 { 180 u8 x; 181 unsigned reg = offset + (nr >> 1); 182 183 pci_read_config_byte(router, reg, &x); 184 return (nr & 1) ? (x >> 4) : (x & 0xf); 185 } 186 187 static void write_config_nybble(struct pci_dev *router, unsigned offset, 188 unsigned nr, unsigned int val) 189 { 190 u8 x; 191 unsigned reg = offset + (nr >> 1); 192 193 pci_read_config_byte(router, reg, &x); 194 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val); 195 pci_write_config_byte(router, reg, x); 196 } 197 198 /* 199 * ALI pirq entries are damn ugly, and completely undocumented. 200 * This has been figured out from pirq tables, and it's not a pretty 201 * picture. 202 */ 203 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 204 { 205 static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 }; 206 207 WARN_ON_ONCE(pirq > 16); 208 return irqmap[read_config_nybble(router, 0x48, pirq-1)]; 209 } 210 211 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 212 { 213 static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 }; 214 unsigned int val = irqmap[irq]; 215 216 WARN_ON_ONCE(pirq > 16); 217 if (val) { 218 write_config_nybble(router, 0x48, pirq-1, val); 219 return 1; 220 } 221 return 0; 222 } 223 224 /* 225 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is 226 * just a pointer to the config space. 227 */ 228 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 229 { 230 u8 x; 231 232 pci_read_config_byte(router, pirq, &x); 233 return (x < 16) ? x : 0; 234 } 235 236 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 237 { 238 pci_write_config_byte(router, pirq, irq); 239 return 1; 240 } 241 242 /* 243 * The VIA pirq rules are nibble-based, like ALI, 244 * but without the ugly irq number munging. 245 * However, PIRQD is in the upper instead of lower 4 bits. 246 */ 247 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 248 { 249 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq); 250 } 251 252 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 253 { 254 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq); 255 return 1; 256 } 257 258 /* 259 * The VIA pirq rules are nibble-based, like ALI, 260 * but without the ugly irq number munging. 261 * However, for 82C586, nibble map is different . 262 */ 263 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 264 { 265 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 266 267 WARN_ON_ONCE(pirq > 5); 268 return read_config_nybble(router, 0x55, pirqmap[pirq-1]); 269 } 270 271 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 272 { 273 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 274 275 WARN_ON_ONCE(pirq > 5); 276 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq); 277 return 1; 278 } 279 280 /* 281 * ITE 8330G pirq rules are nibble-based 282 * FIXME: pirqmap may be { 1, 0, 3, 2 }, 283 * 2+3 are both mapped to irq 9 on my system 284 */ 285 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 286 { 287 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 288 289 WARN_ON_ONCE(pirq > 4); 290 return read_config_nybble(router, 0x43, pirqmap[pirq-1]); 291 } 292 293 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 294 { 295 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 296 297 WARN_ON_ONCE(pirq > 4); 298 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq); 299 return 1; 300 } 301 302 /* 303 * OPTI: high four bits are nibble pointer.. 304 * I wonder what the low bits do? 305 */ 306 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 307 { 308 return read_config_nybble(router, 0xb8, pirq >> 4); 309 } 310 311 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 312 { 313 write_config_nybble(router, 0xb8, pirq >> 4, irq); 314 return 1; 315 } 316 317 /* 318 * Cyrix: nibble offset 0x5C 319 * 0x5C bits 7:4 is INTB bits 3:0 is INTA 320 * 0x5D bits 7:4 is INTD bits 3:0 is INTC 321 */ 322 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 323 { 324 return read_config_nybble(router, 0x5C, (pirq-1)^1); 325 } 326 327 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 328 { 329 write_config_nybble(router, 0x5C, (pirq-1)^1, irq); 330 return 1; 331 } 332 333 /* 334 * PIRQ routing for SiS 85C503 router used in several SiS chipsets. 335 * We have to deal with the following issues here: 336 * - vendors have different ideas about the meaning of link values 337 * - some onboard devices (integrated in the chipset) have special 338 * links and are thus routed differently (i.e. not via PCI INTA-INTD) 339 * - different revision of the router have a different layout for 340 * the routing registers, particularly for the onchip devices 341 * 342 * For all routing registers the common thing is we have one byte 343 * per routeable link which is defined as: 344 * bit 7 IRQ mapping enabled (0) or disabled (1) 345 * bits [6:4] reserved (sometimes used for onchip devices) 346 * bits [3:0] IRQ to map to 347 * allowed: 3-7, 9-12, 14-15 348 * reserved: 0, 1, 2, 8, 13 349 * 350 * The config-space registers located at 0x41/0x42/0x43/0x44 are 351 * always used to route the normal PCI INT A/B/C/D respectively. 352 * Apparently there are systems implementing PCI routing table using 353 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D. 354 * We try our best to handle both link mappings. 355 * 356 * Currently (2003-05-21) it appears most SiS chipsets follow the 357 * definition of routing registers from the SiS-5595 southbridge. 358 * According to the SiS 5595 datasheets the revision id's of the 359 * router (ISA-bridge) should be 0x01 or 0xb0. 360 * 361 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1. 362 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets. 363 * They seem to work with the current routing code. However there is 364 * some concern because of the two USB-OHCI HCs (original SiS 5595 365 * had only one). YMMV. 366 * 367 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1: 368 * 369 * 0x61: IDEIRQ: 370 * bits [6:5] must be written 01 371 * bit 4 channel-select primary (0), secondary (1) 372 * 373 * 0x62: USBIRQ: 374 * bit 6 OHCI function disabled (0), enabled (1) 375 * 376 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved 377 * 378 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved 379 * 380 * We support USBIRQ (in addition to INTA-INTD) and keep the 381 * IDE, ACPI and DAQ routing untouched as set by the BIOS. 382 * 383 * Currently the only reported exception is the new SiS 65x chipset 384 * which includes the SiS 69x southbridge. Here we have the 85C503 385 * router revision 0x04 and there are changes in the register layout 386 * mostly related to the different USB HCs with USB 2.0 support. 387 * 388 * Onchip routing for router rev-id 0x04 (try-and-error observation) 389 * 390 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs 391 * bit 6-4 are probably unused, not like 5595 392 */ 393 394 #define PIRQ_SIS_IRQ_MASK 0x0f 395 #define PIRQ_SIS_IRQ_DISABLE 0x80 396 #define PIRQ_SIS_USB_ENABLE 0x40 397 398 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 399 { 400 u8 x; 401 int reg; 402 403 reg = pirq; 404 if (reg >= 0x01 && reg <= 0x04) 405 reg += 0x40; 406 pci_read_config_byte(router, reg, &x); 407 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK); 408 } 409 410 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 411 { 412 u8 x; 413 int reg; 414 415 reg = pirq; 416 if (reg >= 0x01 && reg <= 0x04) 417 reg += 0x40; 418 pci_read_config_byte(router, reg, &x); 419 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE); 420 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE; 421 pci_write_config_byte(router, reg, x); 422 return 1; 423 } 424 425 426 /* 427 * VLSI: nibble offset 0x74 - educated guess due to routing table and 428 * config space of VLSI 82C534 PCI-bridge/router (1004:0102) 429 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard 430 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6 431 * for the busbridge to the docking station. 432 */ 433 434 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 435 { 436 WARN_ON_ONCE(pirq >= 9); 437 if (pirq > 8) { 438 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq); 439 return 0; 440 } 441 return read_config_nybble(router, 0x74, pirq-1); 442 } 443 444 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 445 { 446 WARN_ON_ONCE(pirq >= 9); 447 if (pirq > 8) { 448 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq); 449 return 0; 450 } 451 write_config_nybble(router, 0x74, pirq-1, irq); 452 return 1; 453 } 454 455 /* 456 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index 457 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register 458 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect 459 * register is a straight binary coding of desired PIC IRQ (low nibble). 460 * 461 * The 'link' value in the PIRQ table is already in the correct format 462 * for the Index register. There are some special index values: 463 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1, 464 * and 0x03 for SMBus. 465 */ 466 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 467 { 468 outb(pirq, 0xc00); 469 return inb(0xc01) & 0xf; 470 } 471 472 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, 473 int pirq, int irq) 474 { 475 outb(pirq, 0xc00); 476 outb(irq, 0xc01); 477 return 1; 478 } 479 480 /* Support for AMD756 PCI IRQ Routing 481 * Jhon H. Caicedo <jhcaiced@osso.org.co> 482 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced) 483 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced) 484 * The AMD756 pirq rules are nibble-based 485 * offset 0x56 0-3 PIRQA 4-7 PIRQB 486 * offset 0x57 0-3 PIRQC 4-7 PIRQD 487 */ 488 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 489 { 490 u8 irq; 491 irq = 0; 492 if (pirq <= 4) 493 irq = read_config_nybble(router, 0x56, pirq - 1); 494 dev_info(&dev->dev, 495 "AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d\n", 496 dev->vendor, dev->device, pirq, irq); 497 return irq; 498 } 499 500 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 501 { 502 dev_info(&dev->dev, 503 "AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d\n", 504 dev->vendor, dev->device, pirq, irq); 505 if (pirq <= 4) 506 write_config_nybble(router, 0x56, pirq - 1, irq); 507 return 1; 508 } 509 510 /* 511 * PicoPower PT86C523 512 */ 513 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 514 { 515 outb(0x10 + ((pirq - 1) >> 1), 0x24); 516 return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf); 517 } 518 519 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq, 520 int irq) 521 { 522 unsigned int x; 523 outb(0x10 + ((pirq - 1) >> 1), 0x24); 524 x = inb(0x26); 525 x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq)); 526 outb(x, 0x26); 527 return 1; 528 } 529 530 #ifdef CONFIG_PCI_BIOS 531 532 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 533 { 534 struct pci_dev *bridge; 535 int pin = pci_get_interrupt_pin(dev, &bridge); 536 return pcibios_set_irq_routing(bridge, pin - 1, irq); 537 } 538 539 #endif 540 541 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 542 { 543 static struct pci_device_id __initdata pirq_440gx[] = { 544 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) }, 545 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) }, 546 { }, 547 }; 548 549 /* 440GX has a proprietary PIRQ router -- don't use it */ 550 if (pci_dev_present(pirq_440gx)) 551 return 0; 552 553 switch (device) { 554 case PCI_DEVICE_ID_INTEL_82371FB_0: 555 case PCI_DEVICE_ID_INTEL_82371SB_0: 556 case PCI_DEVICE_ID_INTEL_82371AB_0: 557 case PCI_DEVICE_ID_INTEL_82371MX: 558 case PCI_DEVICE_ID_INTEL_82443MX_0: 559 case PCI_DEVICE_ID_INTEL_82801AA_0: 560 case PCI_DEVICE_ID_INTEL_82801AB_0: 561 case PCI_DEVICE_ID_INTEL_82801BA_0: 562 case PCI_DEVICE_ID_INTEL_82801BA_10: 563 case PCI_DEVICE_ID_INTEL_82801CA_0: 564 case PCI_DEVICE_ID_INTEL_82801CA_12: 565 case PCI_DEVICE_ID_INTEL_82801DB_0: 566 case PCI_DEVICE_ID_INTEL_82801E_0: 567 case PCI_DEVICE_ID_INTEL_82801EB_0: 568 case PCI_DEVICE_ID_INTEL_ESB_1: 569 case PCI_DEVICE_ID_INTEL_ICH6_0: 570 case PCI_DEVICE_ID_INTEL_ICH6_1: 571 case PCI_DEVICE_ID_INTEL_ICH7_0: 572 case PCI_DEVICE_ID_INTEL_ICH7_1: 573 case PCI_DEVICE_ID_INTEL_ICH7_30: 574 case PCI_DEVICE_ID_INTEL_ICH7_31: 575 case PCI_DEVICE_ID_INTEL_TGP_LPC: 576 case PCI_DEVICE_ID_INTEL_ESB2_0: 577 case PCI_DEVICE_ID_INTEL_ICH8_0: 578 case PCI_DEVICE_ID_INTEL_ICH8_1: 579 case PCI_DEVICE_ID_INTEL_ICH8_2: 580 case PCI_DEVICE_ID_INTEL_ICH8_3: 581 case PCI_DEVICE_ID_INTEL_ICH8_4: 582 case PCI_DEVICE_ID_INTEL_ICH9_0: 583 case PCI_DEVICE_ID_INTEL_ICH9_1: 584 case PCI_DEVICE_ID_INTEL_ICH9_2: 585 case PCI_DEVICE_ID_INTEL_ICH9_3: 586 case PCI_DEVICE_ID_INTEL_ICH9_4: 587 case PCI_DEVICE_ID_INTEL_ICH9_5: 588 case PCI_DEVICE_ID_INTEL_TOLAPAI_0: 589 case PCI_DEVICE_ID_INTEL_ICH10_0: 590 case PCI_DEVICE_ID_INTEL_ICH10_1: 591 case PCI_DEVICE_ID_INTEL_ICH10_2: 592 case PCI_DEVICE_ID_INTEL_ICH10_3: 593 r->name = "PIIX/ICH"; 594 r->get = pirq_piix_get; 595 r->set = pirq_piix_set; 596 return 1; 597 } 598 599 if ((device >= PCI_DEVICE_ID_INTEL_PCH_LPC_MIN) && 600 (device <= PCI_DEVICE_ID_INTEL_PCH_LPC_MAX)) { 601 r->name = "PIIX/ICH"; 602 r->get = pirq_piix_get; 603 r->set = pirq_piix_set; 604 return 1; 605 } 606 607 return 0; 608 } 609 610 static __init int via_router_probe(struct irq_router *r, 611 struct pci_dev *router, u16 device) 612 { 613 /* FIXME: We should move some of the quirk fixup stuff here */ 614 615 /* 616 * workarounds for some buggy BIOSes 617 */ 618 if (device == PCI_DEVICE_ID_VIA_82C586_0) { 619 switch (router->device) { 620 case PCI_DEVICE_ID_VIA_82C686: 621 /* 622 * Asus k7m bios wrongly reports 82C686A 623 * as 586-compatible 624 */ 625 device = PCI_DEVICE_ID_VIA_82C686; 626 break; 627 case PCI_DEVICE_ID_VIA_8235: 628 /** 629 * Asus a7v-x bios wrongly reports 8235 630 * as 586-compatible 631 */ 632 device = PCI_DEVICE_ID_VIA_8235; 633 break; 634 case PCI_DEVICE_ID_VIA_8237: 635 /** 636 * Asus a7v600 bios wrongly reports 8237 637 * as 586-compatible 638 */ 639 device = PCI_DEVICE_ID_VIA_8237; 640 break; 641 } 642 } 643 644 switch (device) { 645 case PCI_DEVICE_ID_VIA_82C586_0: 646 r->name = "VIA"; 647 r->get = pirq_via586_get; 648 r->set = pirq_via586_set; 649 return 1; 650 case PCI_DEVICE_ID_VIA_82C596: 651 case PCI_DEVICE_ID_VIA_82C686: 652 case PCI_DEVICE_ID_VIA_8231: 653 case PCI_DEVICE_ID_VIA_8233A: 654 case PCI_DEVICE_ID_VIA_8235: 655 case PCI_DEVICE_ID_VIA_8237: 656 /* FIXME: add new ones for 8233/5 */ 657 r->name = "VIA"; 658 r->get = pirq_via_get; 659 r->set = pirq_via_set; 660 return 1; 661 } 662 return 0; 663 } 664 665 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 666 { 667 switch (device) { 668 case PCI_DEVICE_ID_VLSI_82C534: 669 r->name = "VLSI 82C534"; 670 r->get = pirq_vlsi_get; 671 r->set = pirq_vlsi_set; 672 return 1; 673 } 674 return 0; 675 } 676 677 678 static __init int serverworks_router_probe(struct irq_router *r, 679 struct pci_dev *router, u16 device) 680 { 681 switch (device) { 682 case PCI_DEVICE_ID_SERVERWORKS_OSB4: 683 case PCI_DEVICE_ID_SERVERWORKS_CSB5: 684 r->name = "ServerWorks"; 685 r->get = pirq_serverworks_get; 686 r->set = pirq_serverworks_set; 687 return 1; 688 } 689 return 0; 690 } 691 692 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 693 { 694 if (device != PCI_DEVICE_ID_SI_503) 695 return 0; 696 697 r->name = "SIS"; 698 r->get = pirq_sis_get; 699 r->set = pirq_sis_set; 700 return 1; 701 } 702 703 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 704 { 705 switch (device) { 706 case PCI_DEVICE_ID_CYRIX_5520: 707 r->name = "NatSemi"; 708 r->get = pirq_cyrix_get; 709 r->set = pirq_cyrix_set; 710 return 1; 711 } 712 return 0; 713 } 714 715 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 716 { 717 switch (device) { 718 case PCI_DEVICE_ID_OPTI_82C700: 719 r->name = "OPTI"; 720 r->get = pirq_opti_get; 721 r->set = pirq_opti_set; 722 return 1; 723 } 724 return 0; 725 } 726 727 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 728 { 729 switch (device) { 730 case PCI_DEVICE_ID_ITE_IT8330G_0: 731 r->name = "ITE"; 732 r->get = pirq_ite_get; 733 r->set = pirq_ite_set; 734 return 1; 735 } 736 return 0; 737 } 738 739 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 740 { 741 switch (device) { 742 case PCI_DEVICE_ID_AL_M1533: 743 case PCI_DEVICE_ID_AL_M1563: 744 r->name = "ALI"; 745 r->get = pirq_ali_get; 746 r->set = pirq_ali_set; 747 return 1; 748 } 749 return 0; 750 } 751 752 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 753 { 754 switch (device) { 755 case PCI_DEVICE_ID_AMD_VIPER_740B: 756 r->name = "AMD756"; 757 break; 758 case PCI_DEVICE_ID_AMD_VIPER_7413: 759 r->name = "AMD766"; 760 break; 761 case PCI_DEVICE_ID_AMD_VIPER_7443: 762 r->name = "AMD768"; 763 break; 764 default: 765 return 0; 766 } 767 r->get = pirq_amd756_get; 768 r->set = pirq_amd756_set; 769 return 1; 770 } 771 772 static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 773 { 774 switch (device) { 775 case PCI_DEVICE_ID_PICOPOWER_PT86C523: 776 r->name = "PicoPower PT86C523"; 777 r->get = pirq_pico_get; 778 r->set = pirq_pico_set; 779 return 1; 780 781 case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP: 782 r->name = "PicoPower PT86C523 rev. BB+"; 783 r->get = pirq_pico_get; 784 r->set = pirq_pico_set; 785 return 1; 786 } 787 return 0; 788 } 789 790 static __initdata struct irq_router_handler pirq_routers[] = { 791 { PCI_VENDOR_ID_INTEL, intel_router_probe }, 792 { PCI_VENDOR_ID_AL, ali_router_probe }, 793 { PCI_VENDOR_ID_ITE, ite_router_probe }, 794 { PCI_VENDOR_ID_VIA, via_router_probe }, 795 { PCI_VENDOR_ID_OPTI, opti_router_probe }, 796 { PCI_VENDOR_ID_SI, sis_router_probe }, 797 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe }, 798 { PCI_VENDOR_ID_VLSI, vlsi_router_probe }, 799 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe }, 800 { PCI_VENDOR_ID_AMD, amd_router_probe }, 801 { PCI_VENDOR_ID_PICOPOWER, pico_router_probe }, 802 /* Someone with docs needs to add the ATI Radeon IGP */ 803 { 0, NULL } 804 }; 805 static struct irq_router pirq_router; 806 static struct pci_dev *pirq_router_dev; 807 808 809 /* 810 * FIXME: should we have an option to say "generic for 811 * chipset" ? 812 */ 813 814 static void __init pirq_find_router(struct irq_router *r) 815 { 816 struct irq_routing_table *rt = pirq_table; 817 struct irq_router_handler *h; 818 819 #ifdef CONFIG_PCI_BIOS 820 if (!rt->signature) { 821 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n"); 822 r->set = pirq_bios_set; 823 r->name = "BIOS"; 824 return; 825 } 826 #endif 827 828 /* Default unless a driver reloads it */ 829 r->name = "default"; 830 r->get = NULL; 831 r->set = NULL; 832 833 DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n", 834 rt->rtr_vendor, rt->rtr_device); 835 836 pirq_router_dev = pci_get_bus_and_slot(rt->rtr_bus, rt->rtr_devfn); 837 if (!pirq_router_dev) { 838 DBG(KERN_DEBUG "PCI: Interrupt router not found at " 839 "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn); 840 return; 841 } 842 843 for (h = pirq_routers; h->vendor; h++) { 844 /* First look for a router match */ 845 if (rt->rtr_vendor == h->vendor && 846 h->probe(r, pirq_router_dev, rt->rtr_device)) 847 break; 848 /* Fall back to a device match */ 849 if (pirq_router_dev->vendor == h->vendor && 850 h->probe(r, pirq_router_dev, pirq_router_dev->device)) 851 break; 852 } 853 dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x:%04x]\n", 854 pirq_router.name, 855 pirq_router_dev->vendor, pirq_router_dev->device); 856 857 /* The device remains referenced for the kernel lifetime */ 858 } 859 860 static struct irq_info *pirq_get_info(struct pci_dev *dev) 861 { 862 struct irq_routing_table *rt = pirq_table; 863 int entries = (rt->size - sizeof(struct irq_routing_table)) / 864 sizeof(struct irq_info); 865 struct irq_info *info; 866 867 for (info = rt->slots; entries--; info++) 868 if (info->bus == dev->bus->number && 869 PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn)) 870 return info; 871 return NULL; 872 } 873 874 static int pcibios_lookup_irq(struct pci_dev *dev, int assign) 875 { 876 u8 pin; 877 struct irq_info *info; 878 int i, pirq, newirq; 879 int irq = 0; 880 u32 mask; 881 struct irq_router *r = &pirq_router; 882 struct pci_dev *dev2 = NULL; 883 char *msg = NULL; 884 885 /* Find IRQ pin */ 886 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 887 if (!pin) { 888 dev_dbg(&dev->dev, "no interrupt pin\n"); 889 return 0; 890 } 891 892 /* Find IRQ routing entry */ 893 894 if (!pirq_table) 895 return 0; 896 897 info = pirq_get_info(dev); 898 if (!info) { 899 dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n", 900 'A' + pin - 1); 901 return 0; 902 } 903 pirq = info->irq[pin - 1].link; 904 mask = info->irq[pin - 1].bitmap; 905 if (!pirq) { 906 dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin - 1); 907 return 0; 908 } 909 dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x", 910 'A' + pin - 1, pirq, mask, pirq_table->exclusive_irqs); 911 mask &= pcibios_irq_mask; 912 913 /* Work around broken HP Pavilion Notebooks which assign USB to 914 IRQ 9 even though it is actually wired to IRQ 11 */ 915 916 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) { 917 dev->irq = 11; 918 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11); 919 r->set(pirq_router_dev, dev, pirq, 11); 920 } 921 922 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */ 923 if (acer_tm360_irqrouting && dev->irq == 11 && 924 dev->vendor == PCI_VENDOR_ID_O2) { 925 pirq = 0x68; 926 mask = 0x400; 927 dev->irq = r->get(pirq_router_dev, dev, pirq); 928 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 929 } 930 931 /* 932 * Find the best IRQ to assign: use the one 933 * reported by the device if possible. 934 */ 935 newirq = dev->irq; 936 if (newirq && !((1 << newirq) & mask)) { 937 if (pci_probe & PCI_USE_PIRQ_MASK) 938 newirq = 0; 939 else 940 dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask " 941 "%#x; try pci=usepirqmask\n", newirq, mask); 942 } 943 if (!newirq && assign) { 944 for (i = 0; i < 16; i++) { 945 if (!(mask & (1 << i))) 946 continue; 947 if (pirq_penalty[i] < pirq_penalty[newirq] && 948 can_request_irq(i, IRQF_SHARED)) 949 newirq = i; 950 } 951 } 952 dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + pin - 1, newirq); 953 954 /* Check if it is hardcoded */ 955 if ((pirq & 0xf0) == 0xf0) { 956 irq = pirq & 0xf; 957 msg = "hardcoded"; 958 } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \ 959 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) { 960 msg = "found"; 961 eisa_set_level_irq(irq); 962 } else if (newirq && r->set && 963 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) { 964 if (r->set(pirq_router_dev, dev, pirq, newirq)) { 965 eisa_set_level_irq(newirq); 966 msg = "assigned"; 967 irq = newirq; 968 } 969 } 970 971 if (!irq) { 972 if (newirq && mask == (1 << newirq)) { 973 msg = "guessed"; 974 irq = newirq; 975 } else { 976 dev_dbg(&dev->dev, "can't route interrupt\n"); 977 return 0; 978 } 979 } 980 dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin - 1, irq); 981 982 /* Update IRQ for all devices with the same pirq value */ 983 while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) { 984 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin); 985 if (!pin) 986 continue; 987 988 info = pirq_get_info(dev2); 989 if (!info) 990 continue; 991 if (info->irq[pin - 1].link == pirq) { 992 /* 993 * We refuse to override the dev->irq 994 * information. Give a warning! 995 */ 996 if (dev2->irq && dev2->irq != irq && \ 997 (!(pci_probe & PCI_USE_PIRQ_MASK) || \ 998 ((1 << dev2->irq) & mask))) { 999 #ifndef CONFIG_PCI_MSI 1000 dev_info(&dev2->dev, "IRQ routing conflict: " 1001 "have IRQ %d, want IRQ %d\n", 1002 dev2->irq, irq); 1003 #endif 1004 continue; 1005 } 1006 dev2->irq = irq; 1007 pirq_penalty[irq]++; 1008 if (dev != dev2) 1009 dev_info(&dev->dev, "sharing IRQ %d with %s\n", 1010 irq, pci_name(dev2)); 1011 } 1012 } 1013 return 1; 1014 } 1015 1016 static void __init pcibios_fixup_irqs(void) 1017 { 1018 struct pci_dev *dev = NULL; 1019 u8 pin; 1020 1021 DBG(KERN_DEBUG "PCI: IRQ fixup\n"); 1022 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { 1023 /* 1024 * If the BIOS has set an out of range IRQ number, just 1025 * ignore it. Also keep track of which IRQ's are 1026 * already in use. 1027 */ 1028 if (dev->irq >= 16) { 1029 dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq); 1030 dev->irq = 0; 1031 } 1032 /* 1033 * If the IRQ is already assigned to a PCI device, 1034 * ignore its ISA use penalty 1035 */ 1036 if (pirq_penalty[dev->irq] >= 100 && 1037 pirq_penalty[dev->irq] < 100000) 1038 pirq_penalty[dev->irq] = 0; 1039 pirq_penalty[dev->irq]++; 1040 } 1041 1042 dev = NULL; 1043 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { 1044 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1045 if (!pin) 1046 continue; 1047 1048 #ifdef CONFIG_X86_IO_APIC 1049 /* 1050 * Recalculate IRQ numbers if we use the I/O APIC. 1051 */ 1052 if (io_apic_assign_pci_irqs) { 1053 int irq; 1054 1055 /* 1056 * interrupt pins are numbered starting from 1 1057 */ 1058 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, 1059 PCI_SLOT(dev->devfn), pin - 1); 1060 /* 1061 * Busses behind bridges are typically not listed in the 1062 * MP-table. In this case we have to look up the IRQ 1063 * based on the parent bus, parent slot, and pin number. 1064 * The SMP code detects such bridged busses itself so we 1065 * should get into this branch reliably. 1066 */ 1067 if (irq < 0 && dev->bus->parent) { 1068 /* go back to the bridge */ 1069 struct pci_dev *bridge = dev->bus->self; 1070 int bus; 1071 1072 pin = pci_swizzle_interrupt_pin(dev, pin); 1073 bus = bridge->bus->number; 1074 irq = IO_APIC_get_PCI_irq_vector(bus, 1075 PCI_SLOT(bridge->devfn), pin - 1); 1076 if (irq >= 0) 1077 dev_warn(&dev->dev, 1078 "using bridge %s INT %c to " 1079 "get IRQ %d\n", 1080 pci_name(bridge), 1081 'A' + pin - 1, irq); 1082 } 1083 if (irq >= 0) { 1084 dev_info(&dev->dev, 1085 "PCI->APIC IRQ transform: INT %c " 1086 "-> IRQ %d\n", 1087 'A' + pin - 1, irq); 1088 dev->irq = irq; 1089 } 1090 } 1091 #endif 1092 /* 1093 * Still no IRQ? Try to lookup one... 1094 */ 1095 if (!dev->irq) 1096 pcibios_lookup_irq(dev, 0); 1097 } 1098 } 1099 1100 /* 1101 * Work around broken HP Pavilion Notebooks which assign USB to 1102 * IRQ 9 even though it is actually wired to IRQ 11 1103 */ 1104 static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d) 1105 { 1106 if (!broken_hp_bios_irq9) { 1107 broken_hp_bios_irq9 = 1; 1108 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", 1109 d->ident); 1110 } 1111 return 0; 1112 } 1113 1114 /* 1115 * Work around broken Acer TravelMate 360 Notebooks which assign 1116 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10 1117 */ 1118 static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d) 1119 { 1120 if (!acer_tm360_irqrouting) { 1121 acer_tm360_irqrouting = 1; 1122 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", 1123 d->ident); 1124 } 1125 return 0; 1126 } 1127 1128 static struct dmi_system_id __initdata pciirq_dmi_table[] = { 1129 { 1130 .callback = fix_broken_hp_bios_irq9, 1131 .ident = "HP Pavilion N5400 Series Laptop", 1132 .matches = { 1133 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1134 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"), 1135 DMI_MATCH(DMI_PRODUCT_VERSION, 1136 "HP Pavilion Notebook Model GE"), 1137 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"), 1138 }, 1139 }, 1140 { 1141 .callback = fix_acer_tm360_irqrouting, 1142 .ident = "Acer TravelMate 36x Laptop", 1143 .matches = { 1144 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1145 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"), 1146 }, 1147 }, 1148 { } 1149 }; 1150 1151 int __init pcibios_irq_init(void) 1152 { 1153 DBG(KERN_DEBUG "PCI: IRQ init\n"); 1154 1155 if (pcibios_enable_irq || raw_pci_ops == NULL) 1156 return 0; 1157 1158 dmi_check_system(pciirq_dmi_table); 1159 1160 pirq_table = pirq_find_routing_table(); 1161 1162 #ifdef CONFIG_PCI_BIOS 1163 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN)) 1164 pirq_table = pcibios_get_irq_routing_table(); 1165 #endif 1166 if (pirq_table) { 1167 pirq_peer_trick(); 1168 pirq_find_router(&pirq_router); 1169 if (pirq_table->exclusive_irqs) { 1170 int i; 1171 for (i = 0; i < 16; i++) 1172 if (!(pirq_table->exclusive_irqs & (1 << i))) 1173 pirq_penalty[i] += 100; 1174 } 1175 /* 1176 * If we're using the I/O APIC, avoid using the PCI IRQ 1177 * routing table 1178 */ 1179 if (io_apic_assign_pci_irqs) 1180 pirq_table = NULL; 1181 } 1182 1183 pcibios_enable_irq = pirq_enable_irq; 1184 1185 pcibios_fixup_irqs(); 1186 return 0; 1187 } 1188 1189 static void pirq_penalize_isa_irq(int irq, int active) 1190 { 1191 /* 1192 * If any ISAPnP device reports an IRQ in its list of possible 1193 * IRQ's, we try to avoid assigning it to PCI devices. 1194 */ 1195 if (irq < 16) { 1196 if (active) 1197 pirq_penalty[irq] += 1000; 1198 else 1199 pirq_penalty[irq] += 100; 1200 } 1201 } 1202 1203 void pcibios_penalize_isa_irq(int irq, int active) 1204 { 1205 #ifdef CONFIG_ACPI 1206 if (!acpi_noirq) 1207 acpi_penalize_isa_irq(irq, active); 1208 else 1209 #endif 1210 pirq_penalize_isa_irq(irq, active); 1211 } 1212 1213 static int pirq_enable_irq(struct pci_dev *dev) 1214 { 1215 u8 pin; 1216 struct pci_dev *temp_dev; 1217 1218 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1219 if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) { 1220 char *msg = ""; 1221 1222 if (io_apic_assign_pci_irqs) { 1223 int irq; 1224 1225 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin - 1); 1226 /* 1227 * Busses behind bridges are typically not listed in the MP-table. 1228 * In this case we have to look up the IRQ based on the parent bus, 1229 * parent slot, and pin number. The SMP code detects such bridged 1230 * busses itself so we should get into this branch reliably. 1231 */ 1232 temp_dev = dev; 1233 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */ 1234 struct pci_dev *bridge = dev->bus->self; 1235 1236 pin = pci_swizzle_interrupt_pin(dev, pin); 1237 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, 1238 PCI_SLOT(bridge->devfn), pin - 1); 1239 if (irq >= 0) 1240 dev_warn(&dev->dev, "using bridge %s " 1241 "INT %c to get IRQ %d\n", 1242 pci_name(bridge), 'A' + pin - 1, 1243 irq); 1244 dev = bridge; 1245 } 1246 dev = temp_dev; 1247 if (irq >= 0) { 1248 dev_info(&dev->dev, "PCI->APIC IRQ transform: " 1249 "INT %c -> IRQ %d\n", 'A' + pin - 1, irq); 1250 dev->irq = irq; 1251 return 0; 1252 } else 1253 msg = "; probably buggy MP table"; 1254 } else if (pci_probe & PCI_BIOS_IRQ_SCAN) 1255 msg = ""; 1256 else 1257 msg = "; please try using pci=biosirq"; 1258 1259 /* 1260 * With IDE legacy devices the IRQ lookup failure is not 1261 * a problem.. 1262 */ 1263 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && 1264 !(dev->class & 0x5)) 1265 return 0; 1266 1267 dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n", 1268 'A' + pin - 1, msg); 1269 } 1270 return 0; 1271 } 1272