1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Low-Level PCI Support for PC -- Routing of Interrupts 4 * 5 * (c) 1999--2000 Martin Mares <mj@ucw.cz> 6 */ 7 8 #include <linux/types.h> 9 #include <linux/kernel.h> 10 #include <linux/pci.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/dmi.h> 14 #include <linux/io.h> 15 #include <linux/smp.h> 16 #include <asm/io_apic.h> 17 #include <linux/irq.h> 18 #include <linux/acpi.h> 19 #include <asm/pci_x86.h> 20 21 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) 22 #define PIRQ_VERSION 0x0100 23 24 static int broken_hp_bios_irq9; 25 static int acer_tm360_irqrouting; 26 27 static struct irq_routing_table *pirq_table; 28 29 static int pirq_enable_irq(struct pci_dev *dev); 30 static void pirq_disable_irq(struct pci_dev *dev); 31 32 /* 33 * Never use: 0, 1, 2 (timer, keyboard, and cascade) 34 * Avoid using: 13, 14 and 15 (FP error and IDE). 35 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse) 36 */ 37 unsigned int pcibios_irq_mask = 0xfff8; 38 39 static int pirq_penalty[16] = { 40 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000, 41 0, 0, 0, 0, 1000, 100000, 100000, 100000 42 }; 43 44 struct irq_router { 45 char *name; 46 u16 vendor, device; 47 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq); 48 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, 49 int new); 50 }; 51 52 struct irq_router_handler { 53 u16 vendor; 54 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device); 55 }; 56 57 int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq; 58 void (*pcibios_disable_irq)(struct pci_dev *dev) = pirq_disable_irq; 59 60 /* 61 * Check passed address for the PCI IRQ Routing Table signature 62 * and perform checksum verification. 63 */ 64 65 static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr) 66 { 67 struct irq_routing_table *rt; 68 int i; 69 u8 sum; 70 71 rt = (struct irq_routing_table *) addr; 72 if (rt->signature != PIRQ_SIGNATURE || 73 rt->version != PIRQ_VERSION || 74 rt->size % 16 || 75 rt->size < sizeof(struct irq_routing_table)) 76 return NULL; 77 sum = 0; 78 for (i = 0; i < rt->size; i++) 79 sum += addr[i]; 80 if (!sum) { 81 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n", 82 rt); 83 return rt; 84 } 85 return NULL; 86 } 87 88 89 90 /* 91 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table. 92 */ 93 94 static struct irq_routing_table * __init pirq_find_routing_table(void) 95 { 96 u8 *addr; 97 struct irq_routing_table *rt; 98 99 if (pirq_table_addr) { 100 rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr)); 101 if (rt) 102 return rt; 103 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n"); 104 } 105 for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) { 106 rt = pirq_check_routing_table(addr); 107 if (rt) 108 return rt; 109 } 110 return NULL; 111 } 112 113 /* 114 * If we have a IRQ routing table, use it to search for peer host 115 * bridges. It's a gross hack, but since there are no other known 116 * ways how to get a list of buses, we have to go this way. 117 */ 118 119 static void __init pirq_peer_trick(void) 120 { 121 struct irq_routing_table *rt = pirq_table; 122 u8 busmap[256]; 123 int i; 124 struct irq_info *e; 125 126 memset(busmap, 0, sizeof(busmap)); 127 for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) { 128 e = &rt->slots[i]; 129 #ifdef DEBUG 130 { 131 int j; 132 DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot); 133 for (j = 0; j < 4; j++) 134 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap); 135 DBG("\n"); 136 } 137 #endif 138 busmap[e->bus] = 1; 139 } 140 for (i = 1; i < 256; i++) { 141 if (!busmap[i] || pci_find_bus(0, i)) 142 continue; 143 pcibios_scan_root(i); 144 } 145 pcibios_last_bus = -1; 146 } 147 148 /* 149 * Code for querying and setting of IRQ routes on various interrupt routers. 150 * PIC Edge/Level Control Registers (ELCR) 0x4d0 & 0x4d1. 151 */ 152 153 void elcr_set_level_irq(unsigned int irq) 154 { 155 unsigned char mask = 1 << (irq & 7); 156 unsigned int port = 0x4d0 + (irq >> 3); 157 unsigned char val; 158 static u16 elcr_irq_mask; 159 160 if (irq >= 16 || (1 << irq) & elcr_irq_mask) 161 return; 162 163 elcr_irq_mask |= (1 << irq); 164 printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq); 165 val = inb(port); 166 if (!(val & mask)) { 167 DBG(KERN_DEBUG " -> edge"); 168 outb(val | mask, port); 169 } 170 } 171 172 /* 173 * Common IRQ routing practice: nibbles in config space, 174 * offset by some magic constant. 175 */ 176 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr) 177 { 178 u8 x; 179 unsigned reg = offset + (nr >> 1); 180 181 pci_read_config_byte(router, reg, &x); 182 return (nr & 1) ? (x >> 4) : (x & 0xf); 183 } 184 185 static void write_config_nybble(struct pci_dev *router, unsigned offset, 186 unsigned nr, unsigned int val) 187 { 188 u8 x; 189 unsigned reg = offset + (nr >> 1); 190 191 pci_read_config_byte(router, reg, &x); 192 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val); 193 pci_write_config_byte(router, reg, x); 194 } 195 196 /* 197 * ALI pirq entries are damn ugly, and completely undocumented. 198 * This has been figured out from pirq tables, and it's not a pretty 199 * picture. 200 */ 201 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 202 { 203 static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 }; 204 205 WARN_ON_ONCE(pirq > 16); 206 return irqmap[read_config_nybble(router, 0x48, pirq-1)]; 207 } 208 209 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 210 { 211 static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 }; 212 unsigned int val = irqmap[irq]; 213 214 WARN_ON_ONCE(pirq > 16); 215 if (val) { 216 write_config_nybble(router, 0x48, pirq-1, val); 217 return 1; 218 } 219 return 0; 220 } 221 222 /* 223 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is 224 * just a pointer to the config space. 225 */ 226 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 227 { 228 u8 x; 229 230 pci_read_config_byte(router, pirq, &x); 231 return (x < 16) ? x : 0; 232 } 233 234 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 235 { 236 pci_write_config_byte(router, pirq, irq); 237 return 1; 238 } 239 240 /* 241 * The VIA pirq rules are nibble-based, like ALI, 242 * but without the ugly irq number munging. 243 * However, PIRQD is in the upper instead of lower 4 bits. 244 */ 245 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 246 { 247 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq); 248 } 249 250 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 251 { 252 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq); 253 return 1; 254 } 255 256 /* 257 * The VIA pirq rules are nibble-based, like ALI, 258 * but without the ugly irq number munging. 259 * However, for 82C586, nibble map is different . 260 */ 261 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 262 { 263 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 264 265 WARN_ON_ONCE(pirq > 5); 266 return read_config_nybble(router, 0x55, pirqmap[pirq-1]); 267 } 268 269 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 270 { 271 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 272 273 WARN_ON_ONCE(pirq > 5); 274 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq); 275 return 1; 276 } 277 278 /* 279 * ITE 8330G pirq rules are nibble-based 280 * FIXME: pirqmap may be { 1, 0, 3, 2 }, 281 * 2+3 are both mapped to irq 9 on my system 282 */ 283 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 284 { 285 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 286 287 WARN_ON_ONCE(pirq > 4); 288 return read_config_nybble(router, 0x43, pirqmap[pirq-1]); 289 } 290 291 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 292 { 293 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 294 295 WARN_ON_ONCE(pirq > 4); 296 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq); 297 return 1; 298 } 299 300 /* 301 * OPTI: high four bits are nibble pointer.. 302 * I wonder what the low bits do? 303 */ 304 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 305 { 306 return read_config_nybble(router, 0xb8, pirq >> 4); 307 } 308 309 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 310 { 311 write_config_nybble(router, 0xb8, pirq >> 4, irq); 312 return 1; 313 } 314 315 /* 316 * Cyrix: nibble offset 0x5C 317 * 0x5C bits 7:4 is INTB bits 3:0 is INTA 318 * 0x5D bits 7:4 is INTD bits 3:0 is INTC 319 */ 320 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 321 { 322 return read_config_nybble(router, 0x5C, (pirq-1)^1); 323 } 324 325 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 326 { 327 write_config_nybble(router, 0x5C, (pirq-1)^1, irq); 328 return 1; 329 } 330 331 /* 332 * PIRQ routing for SiS 85C503 router used in several SiS chipsets. 333 * We have to deal with the following issues here: 334 * - vendors have different ideas about the meaning of link values 335 * - some onboard devices (integrated in the chipset) have special 336 * links and are thus routed differently (i.e. not via PCI INTA-INTD) 337 * - different revision of the router have a different layout for 338 * the routing registers, particularly for the onchip devices 339 * 340 * For all routing registers the common thing is we have one byte 341 * per routeable link which is defined as: 342 * bit 7 IRQ mapping enabled (0) or disabled (1) 343 * bits [6:4] reserved (sometimes used for onchip devices) 344 * bits [3:0] IRQ to map to 345 * allowed: 3-7, 9-12, 14-15 346 * reserved: 0, 1, 2, 8, 13 347 * 348 * The config-space registers located at 0x41/0x42/0x43/0x44 are 349 * always used to route the normal PCI INT A/B/C/D respectively. 350 * Apparently there are systems implementing PCI routing table using 351 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D. 352 * We try our best to handle both link mappings. 353 * 354 * Currently (2003-05-21) it appears most SiS chipsets follow the 355 * definition of routing registers from the SiS-5595 southbridge. 356 * According to the SiS 5595 datasheets the revision id's of the 357 * router (ISA-bridge) should be 0x01 or 0xb0. 358 * 359 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1. 360 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets. 361 * They seem to work with the current routing code. However there is 362 * some concern because of the two USB-OHCI HCs (original SiS 5595 363 * had only one). YMMV. 364 * 365 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1: 366 * 367 * 0x61: IDEIRQ: 368 * bits [6:5] must be written 01 369 * bit 4 channel-select primary (0), secondary (1) 370 * 371 * 0x62: USBIRQ: 372 * bit 6 OHCI function disabled (0), enabled (1) 373 * 374 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved 375 * 376 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved 377 * 378 * We support USBIRQ (in addition to INTA-INTD) and keep the 379 * IDE, ACPI and DAQ routing untouched as set by the BIOS. 380 * 381 * Currently the only reported exception is the new SiS 65x chipset 382 * which includes the SiS 69x southbridge. Here we have the 85C503 383 * router revision 0x04 and there are changes in the register layout 384 * mostly related to the different USB HCs with USB 2.0 support. 385 * 386 * Onchip routing for router rev-id 0x04 (try-and-error observation) 387 * 388 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs 389 * bit 6-4 are probably unused, not like 5595 390 */ 391 392 #define PIRQ_SIS_IRQ_MASK 0x0f 393 #define PIRQ_SIS_IRQ_DISABLE 0x80 394 #define PIRQ_SIS_USB_ENABLE 0x40 395 396 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 397 { 398 u8 x; 399 int reg; 400 401 reg = pirq; 402 if (reg >= 0x01 && reg <= 0x04) 403 reg += 0x40; 404 pci_read_config_byte(router, reg, &x); 405 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK); 406 } 407 408 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 409 { 410 u8 x; 411 int reg; 412 413 reg = pirq; 414 if (reg >= 0x01 && reg <= 0x04) 415 reg += 0x40; 416 pci_read_config_byte(router, reg, &x); 417 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE); 418 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE; 419 pci_write_config_byte(router, reg, x); 420 return 1; 421 } 422 423 424 /* 425 * VLSI: nibble offset 0x74 - educated guess due to routing table and 426 * config space of VLSI 82C534 PCI-bridge/router (1004:0102) 427 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard 428 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6 429 * for the busbridge to the docking station. 430 */ 431 432 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 433 { 434 WARN_ON_ONCE(pirq >= 9); 435 if (pirq > 8) { 436 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq); 437 return 0; 438 } 439 return read_config_nybble(router, 0x74, pirq-1); 440 } 441 442 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 443 { 444 WARN_ON_ONCE(pirq >= 9); 445 if (pirq > 8) { 446 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq); 447 return 0; 448 } 449 write_config_nybble(router, 0x74, pirq-1, irq); 450 return 1; 451 } 452 453 /* 454 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index 455 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register 456 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect 457 * register is a straight binary coding of desired PIC IRQ (low nibble). 458 * 459 * The 'link' value in the PIRQ table is already in the correct format 460 * for the Index register. There are some special index values: 461 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1, 462 * and 0x03 for SMBus. 463 */ 464 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 465 { 466 outb(pirq, 0xc00); 467 return inb(0xc01) & 0xf; 468 } 469 470 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, 471 int pirq, int irq) 472 { 473 outb(pirq, 0xc00); 474 outb(irq, 0xc01); 475 return 1; 476 } 477 478 /* Support for AMD756 PCI IRQ Routing 479 * Jhon H. Caicedo <jhcaiced@osso.org.co> 480 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced) 481 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced) 482 * The AMD756 pirq rules are nibble-based 483 * offset 0x56 0-3 PIRQA 4-7 PIRQB 484 * offset 0x57 0-3 PIRQC 4-7 PIRQD 485 */ 486 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 487 { 488 u8 irq; 489 irq = 0; 490 if (pirq <= 4) 491 irq = read_config_nybble(router, 0x56, pirq - 1); 492 dev_info(&dev->dev, 493 "AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d\n", 494 dev->vendor, dev->device, pirq, irq); 495 return irq; 496 } 497 498 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 499 { 500 dev_info(&dev->dev, 501 "AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d\n", 502 dev->vendor, dev->device, pirq, irq); 503 if (pirq <= 4) 504 write_config_nybble(router, 0x56, pirq - 1, irq); 505 return 1; 506 } 507 508 /* 509 * PicoPower PT86C523 510 */ 511 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 512 { 513 outb(0x10 + ((pirq - 1) >> 1), 0x24); 514 return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf); 515 } 516 517 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq, 518 int irq) 519 { 520 unsigned int x; 521 outb(0x10 + ((pirq - 1) >> 1), 0x24); 522 x = inb(0x26); 523 x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq)); 524 outb(x, 0x26); 525 return 1; 526 } 527 528 #ifdef CONFIG_PCI_BIOS 529 530 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 531 { 532 struct pci_dev *bridge; 533 int pin = pci_get_interrupt_pin(dev, &bridge); 534 return pcibios_set_irq_routing(bridge, pin - 1, irq); 535 } 536 537 #endif 538 539 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 540 { 541 static struct pci_device_id __initdata pirq_440gx[] = { 542 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) }, 543 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) }, 544 { }, 545 }; 546 547 /* 440GX has a proprietary PIRQ router -- don't use it */ 548 if (pci_dev_present(pirq_440gx)) 549 return 0; 550 551 switch (device) { 552 case PCI_DEVICE_ID_INTEL_82371FB_0: 553 case PCI_DEVICE_ID_INTEL_82371SB_0: 554 case PCI_DEVICE_ID_INTEL_82371AB_0: 555 case PCI_DEVICE_ID_INTEL_82371MX: 556 case PCI_DEVICE_ID_INTEL_82443MX_0: 557 case PCI_DEVICE_ID_INTEL_82801AA_0: 558 case PCI_DEVICE_ID_INTEL_82801AB_0: 559 case PCI_DEVICE_ID_INTEL_82801BA_0: 560 case PCI_DEVICE_ID_INTEL_82801BA_10: 561 case PCI_DEVICE_ID_INTEL_82801CA_0: 562 case PCI_DEVICE_ID_INTEL_82801CA_12: 563 case PCI_DEVICE_ID_INTEL_82801DB_0: 564 case PCI_DEVICE_ID_INTEL_82801E_0: 565 case PCI_DEVICE_ID_INTEL_82801EB_0: 566 case PCI_DEVICE_ID_INTEL_ESB_1: 567 case PCI_DEVICE_ID_INTEL_ICH6_0: 568 case PCI_DEVICE_ID_INTEL_ICH6_1: 569 case PCI_DEVICE_ID_INTEL_ICH7_0: 570 case PCI_DEVICE_ID_INTEL_ICH7_1: 571 case PCI_DEVICE_ID_INTEL_ICH7_30: 572 case PCI_DEVICE_ID_INTEL_ICH7_31: 573 case PCI_DEVICE_ID_INTEL_TGP_LPC: 574 case PCI_DEVICE_ID_INTEL_ESB2_0: 575 case PCI_DEVICE_ID_INTEL_ICH8_0: 576 case PCI_DEVICE_ID_INTEL_ICH8_1: 577 case PCI_DEVICE_ID_INTEL_ICH8_2: 578 case PCI_DEVICE_ID_INTEL_ICH8_3: 579 case PCI_DEVICE_ID_INTEL_ICH8_4: 580 case PCI_DEVICE_ID_INTEL_ICH9_0: 581 case PCI_DEVICE_ID_INTEL_ICH9_1: 582 case PCI_DEVICE_ID_INTEL_ICH9_2: 583 case PCI_DEVICE_ID_INTEL_ICH9_3: 584 case PCI_DEVICE_ID_INTEL_ICH9_4: 585 case PCI_DEVICE_ID_INTEL_ICH9_5: 586 case PCI_DEVICE_ID_INTEL_EP80579_0: 587 case PCI_DEVICE_ID_INTEL_ICH10_0: 588 case PCI_DEVICE_ID_INTEL_ICH10_1: 589 case PCI_DEVICE_ID_INTEL_ICH10_2: 590 case PCI_DEVICE_ID_INTEL_ICH10_3: 591 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0: 592 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1: 593 r->name = "PIIX/ICH"; 594 r->get = pirq_piix_get; 595 r->set = pirq_piix_set; 596 return 1; 597 } 598 599 if ((device >= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN && 600 device <= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX) 601 || (device >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && 602 device <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) 603 || (device >= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN && 604 device <= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX) 605 || (device >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && 606 device <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) { 607 r->name = "PIIX/ICH"; 608 r->get = pirq_piix_get; 609 r->set = pirq_piix_set; 610 return 1; 611 } 612 613 return 0; 614 } 615 616 static __init int via_router_probe(struct irq_router *r, 617 struct pci_dev *router, u16 device) 618 { 619 /* FIXME: We should move some of the quirk fixup stuff here */ 620 621 /* 622 * workarounds for some buggy BIOSes 623 */ 624 if (device == PCI_DEVICE_ID_VIA_82C586_0) { 625 switch (router->device) { 626 case PCI_DEVICE_ID_VIA_82C686: 627 /* 628 * Asus k7m bios wrongly reports 82C686A 629 * as 586-compatible 630 */ 631 device = PCI_DEVICE_ID_VIA_82C686; 632 break; 633 case PCI_DEVICE_ID_VIA_8235: 634 /** 635 * Asus a7v-x bios wrongly reports 8235 636 * as 586-compatible 637 */ 638 device = PCI_DEVICE_ID_VIA_8235; 639 break; 640 case PCI_DEVICE_ID_VIA_8237: 641 /** 642 * Asus a7v600 bios wrongly reports 8237 643 * as 586-compatible 644 */ 645 device = PCI_DEVICE_ID_VIA_8237; 646 break; 647 } 648 } 649 650 switch (device) { 651 case PCI_DEVICE_ID_VIA_82C586_0: 652 r->name = "VIA"; 653 r->get = pirq_via586_get; 654 r->set = pirq_via586_set; 655 return 1; 656 case PCI_DEVICE_ID_VIA_82C596: 657 case PCI_DEVICE_ID_VIA_82C686: 658 case PCI_DEVICE_ID_VIA_8231: 659 case PCI_DEVICE_ID_VIA_8233A: 660 case PCI_DEVICE_ID_VIA_8235: 661 case PCI_DEVICE_ID_VIA_8237: 662 /* FIXME: add new ones for 8233/5 */ 663 r->name = "VIA"; 664 r->get = pirq_via_get; 665 r->set = pirq_via_set; 666 return 1; 667 } 668 return 0; 669 } 670 671 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 672 { 673 switch (device) { 674 case PCI_DEVICE_ID_VLSI_82C534: 675 r->name = "VLSI 82C534"; 676 r->get = pirq_vlsi_get; 677 r->set = pirq_vlsi_set; 678 return 1; 679 } 680 return 0; 681 } 682 683 684 static __init int serverworks_router_probe(struct irq_router *r, 685 struct pci_dev *router, u16 device) 686 { 687 switch (device) { 688 case PCI_DEVICE_ID_SERVERWORKS_OSB4: 689 case PCI_DEVICE_ID_SERVERWORKS_CSB5: 690 r->name = "ServerWorks"; 691 r->get = pirq_serverworks_get; 692 r->set = pirq_serverworks_set; 693 return 1; 694 } 695 return 0; 696 } 697 698 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 699 { 700 if (device != PCI_DEVICE_ID_SI_503) 701 return 0; 702 703 r->name = "SIS"; 704 r->get = pirq_sis_get; 705 r->set = pirq_sis_set; 706 return 1; 707 } 708 709 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 710 { 711 switch (device) { 712 case PCI_DEVICE_ID_CYRIX_5520: 713 r->name = "NatSemi"; 714 r->get = pirq_cyrix_get; 715 r->set = pirq_cyrix_set; 716 return 1; 717 } 718 return 0; 719 } 720 721 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 722 { 723 switch (device) { 724 case PCI_DEVICE_ID_OPTI_82C700: 725 r->name = "OPTI"; 726 r->get = pirq_opti_get; 727 r->set = pirq_opti_set; 728 return 1; 729 } 730 return 0; 731 } 732 733 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 734 { 735 switch (device) { 736 case PCI_DEVICE_ID_ITE_IT8330G_0: 737 r->name = "ITE"; 738 r->get = pirq_ite_get; 739 r->set = pirq_ite_set; 740 return 1; 741 } 742 return 0; 743 } 744 745 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 746 { 747 switch (device) { 748 case PCI_DEVICE_ID_AL_M1533: 749 case PCI_DEVICE_ID_AL_M1563: 750 r->name = "ALI"; 751 r->get = pirq_ali_get; 752 r->set = pirq_ali_set; 753 return 1; 754 } 755 return 0; 756 } 757 758 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 759 { 760 switch (device) { 761 case PCI_DEVICE_ID_AMD_VIPER_740B: 762 r->name = "AMD756"; 763 break; 764 case PCI_DEVICE_ID_AMD_VIPER_7413: 765 r->name = "AMD766"; 766 break; 767 case PCI_DEVICE_ID_AMD_VIPER_7443: 768 r->name = "AMD768"; 769 break; 770 default: 771 return 0; 772 } 773 r->get = pirq_amd756_get; 774 r->set = pirq_amd756_set; 775 return 1; 776 } 777 778 static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 779 { 780 switch (device) { 781 case PCI_DEVICE_ID_PICOPOWER_PT86C523: 782 r->name = "PicoPower PT86C523"; 783 r->get = pirq_pico_get; 784 r->set = pirq_pico_set; 785 return 1; 786 787 case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP: 788 r->name = "PicoPower PT86C523 rev. BB+"; 789 r->get = pirq_pico_get; 790 r->set = pirq_pico_set; 791 return 1; 792 } 793 return 0; 794 } 795 796 static __initdata struct irq_router_handler pirq_routers[] = { 797 { PCI_VENDOR_ID_INTEL, intel_router_probe }, 798 { PCI_VENDOR_ID_AL, ali_router_probe }, 799 { PCI_VENDOR_ID_ITE, ite_router_probe }, 800 { PCI_VENDOR_ID_VIA, via_router_probe }, 801 { PCI_VENDOR_ID_OPTI, opti_router_probe }, 802 { PCI_VENDOR_ID_SI, sis_router_probe }, 803 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe }, 804 { PCI_VENDOR_ID_VLSI, vlsi_router_probe }, 805 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe }, 806 { PCI_VENDOR_ID_AMD, amd_router_probe }, 807 { PCI_VENDOR_ID_PICOPOWER, pico_router_probe }, 808 /* Someone with docs needs to add the ATI Radeon IGP */ 809 { 0, NULL } 810 }; 811 static struct irq_router pirq_router; 812 static struct pci_dev *pirq_router_dev; 813 814 815 /* 816 * FIXME: should we have an option to say "generic for 817 * chipset" ? 818 */ 819 820 static void __init pirq_find_router(struct irq_router *r) 821 { 822 struct irq_routing_table *rt = pirq_table; 823 struct irq_router_handler *h; 824 825 #ifdef CONFIG_PCI_BIOS 826 if (!rt->signature) { 827 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n"); 828 r->set = pirq_bios_set; 829 r->name = "BIOS"; 830 return; 831 } 832 #endif 833 834 /* Default unless a driver reloads it */ 835 r->name = "default"; 836 r->get = NULL; 837 r->set = NULL; 838 839 DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n", 840 rt->rtr_vendor, rt->rtr_device); 841 842 pirq_router_dev = pci_get_bus_and_slot(rt->rtr_bus, rt->rtr_devfn); 843 if (!pirq_router_dev) { 844 DBG(KERN_DEBUG "PCI: Interrupt router not found at " 845 "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn); 846 return; 847 } 848 849 for (h = pirq_routers; h->vendor; h++) { 850 /* First look for a router match */ 851 if (rt->rtr_vendor == h->vendor && 852 h->probe(r, pirq_router_dev, rt->rtr_device)) 853 break; 854 /* Fall back to a device match */ 855 if (pirq_router_dev->vendor == h->vendor && 856 h->probe(r, pirq_router_dev, pirq_router_dev->device)) 857 break; 858 } 859 dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x:%04x]\n", 860 pirq_router.name, 861 pirq_router_dev->vendor, pirq_router_dev->device); 862 863 /* The device remains referenced for the kernel lifetime */ 864 } 865 866 static struct irq_info *pirq_get_info(struct pci_dev *dev) 867 { 868 struct irq_routing_table *rt = pirq_table; 869 int entries = (rt->size - sizeof(struct irq_routing_table)) / 870 sizeof(struct irq_info); 871 struct irq_info *info; 872 873 for (info = rt->slots; entries--; info++) 874 if (info->bus == dev->bus->number && 875 PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn)) 876 return info; 877 return NULL; 878 } 879 880 static int pcibios_lookup_irq(struct pci_dev *dev, int assign) 881 { 882 u8 pin; 883 struct irq_info *info; 884 int i, pirq, newirq; 885 int irq = 0; 886 u32 mask; 887 struct irq_router *r = &pirq_router; 888 struct pci_dev *dev2 = NULL; 889 char *msg = NULL; 890 891 /* Find IRQ pin */ 892 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 893 if (!pin) { 894 dev_dbg(&dev->dev, "no interrupt pin\n"); 895 return 0; 896 } 897 898 if (io_apic_assign_pci_irqs) 899 return 0; 900 901 /* Find IRQ routing entry */ 902 903 if (!pirq_table) 904 return 0; 905 906 info = pirq_get_info(dev); 907 if (!info) { 908 dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n", 909 'A' + pin - 1); 910 return 0; 911 } 912 pirq = info->irq[pin - 1].link; 913 mask = info->irq[pin - 1].bitmap; 914 if (!pirq) { 915 dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin - 1); 916 return 0; 917 } 918 dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x", 919 'A' + pin - 1, pirq, mask, pirq_table->exclusive_irqs); 920 mask &= pcibios_irq_mask; 921 922 /* Work around broken HP Pavilion Notebooks which assign USB to 923 IRQ 9 even though it is actually wired to IRQ 11 */ 924 925 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) { 926 dev->irq = 11; 927 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11); 928 r->set(pirq_router_dev, dev, pirq, 11); 929 } 930 931 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */ 932 if (acer_tm360_irqrouting && dev->irq == 11 && 933 dev->vendor == PCI_VENDOR_ID_O2) { 934 pirq = 0x68; 935 mask = 0x400; 936 dev->irq = r->get(pirq_router_dev, dev, pirq); 937 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 938 } 939 940 /* 941 * Find the best IRQ to assign: use the one 942 * reported by the device if possible. 943 */ 944 newirq = dev->irq; 945 if (newirq && !((1 << newirq) & mask)) { 946 if (pci_probe & PCI_USE_PIRQ_MASK) 947 newirq = 0; 948 else 949 dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask " 950 "%#x; try pci=usepirqmask\n", newirq, mask); 951 } 952 if (!newirq && assign) { 953 for (i = 0; i < 16; i++) { 954 if (!(mask & (1 << i))) 955 continue; 956 if (pirq_penalty[i] < pirq_penalty[newirq] && 957 can_request_irq(i, IRQF_SHARED)) 958 newirq = i; 959 } 960 } 961 dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + pin - 1, newirq); 962 963 /* Check if it is hardcoded */ 964 if ((pirq & 0xf0) == 0xf0) { 965 irq = pirq & 0xf; 966 msg = "hardcoded"; 967 } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \ 968 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) { 969 msg = "found"; 970 elcr_set_level_irq(irq); 971 } else if (newirq && r->set && 972 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) { 973 if (r->set(pirq_router_dev, dev, pirq, newirq)) { 974 elcr_set_level_irq(newirq); 975 msg = "assigned"; 976 irq = newirq; 977 } 978 } 979 980 if (!irq) { 981 if (newirq && mask == (1 << newirq)) { 982 msg = "guessed"; 983 irq = newirq; 984 } else { 985 dev_dbg(&dev->dev, "can't route interrupt\n"); 986 return 0; 987 } 988 } 989 dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin - 1, irq); 990 991 /* Update IRQ for all devices with the same pirq value */ 992 for_each_pci_dev(dev2) { 993 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin); 994 if (!pin) 995 continue; 996 997 info = pirq_get_info(dev2); 998 if (!info) 999 continue; 1000 if (info->irq[pin - 1].link == pirq) { 1001 /* 1002 * We refuse to override the dev->irq 1003 * information. Give a warning! 1004 */ 1005 if (dev2->irq && dev2->irq != irq && \ 1006 (!(pci_probe & PCI_USE_PIRQ_MASK) || \ 1007 ((1 << dev2->irq) & mask))) { 1008 #ifndef CONFIG_PCI_MSI 1009 dev_info(&dev2->dev, "IRQ routing conflict: " 1010 "have IRQ %d, want IRQ %d\n", 1011 dev2->irq, irq); 1012 #endif 1013 continue; 1014 } 1015 dev2->irq = irq; 1016 pirq_penalty[irq]++; 1017 if (dev != dev2) 1018 dev_info(&dev->dev, "sharing IRQ %d with %s\n", 1019 irq, pci_name(dev2)); 1020 } 1021 } 1022 return 1; 1023 } 1024 1025 void __init pcibios_fixup_irqs(void) 1026 { 1027 struct pci_dev *dev = NULL; 1028 u8 pin; 1029 1030 DBG(KERN_DEBUG "PCI: IRQ fixup\n"); 1031 for_each_pci_dev(dev) { 1032 /* 1033 * If the BIOS has set an out of range IRQ number, just 1034 * ignore it. Also keep track of which IRQ's are 1035 * already in use. 1036 */ 1037 if (dev->irq >= 16) { 1038 dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq); 1039 dev->irq = 0; 1040 } 1041 /* 1042 * If the IRQ is already assigned to a PCI device, 1043 * ignore its ISA use penalty 1044 */ 1045 if (pirq_penalty[dev->irq] >= 100 && 1046 pirq_penalty[dev->irq] < 100000) 1047 pirq_penalty[dev->irq] = 0; 1048 pirq_penalty[dev->irq]++; 1049 } 1050 1051 if (io_apic_assign_pci_irqs) 1052 return; 1053 1054 dev = NULL; 1055 for_each_pci_dev(dev) { 1056 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1057 if (!pin) 1058 continue; 1059 1060 /* 1061 * Still no IRQ? Try to lookup one... 1062 */ 1063 if (!dev->irq) 1064 pcibios_lookup_irq(dev, 0); 1065 } 1066 } 1067 1068 /* 1069 * Work around broken HP Pavilion Notebooks which assign USB to 1070 * IRQ 9 even though it is actually wired to IRQ 11 1071 */ 1072 static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d) 1073 { 1074 if (!broken_hp_bios_irq9) { 1075 broken_hp_bios_irq9 = 1; 1076 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", 1077 d->ident); 1078 } 1079 return 0; 1080 } 1081 1082 /* 1083 * Work around broken Acer TravelMate 360 Notebooks which assign 1084 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10 1085 */ 1086 static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d) 1087 { 1088 if (!acer_tm360_irqrouting) { 1089 acer_tm360_irqrouting = 1; 1090 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", 1091 d->ident); 1092 } 1093 return 0; 1094 } 1095 1096 static const struct dmi_system_id pciirq_dmi_table[] __initconst = { 1097 { 1098 .callback = fix_broken_hp_bios_irq9, 1099 .ident = "HP Pavilion N5400 Series Laptop", 1100 .matches = { 1101 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1102 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"), 1103 DMI_MATCH(DMI_PRODUCT_VERSION, 1104 "HP Pavilion Notebook Model GE"), 1105 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"), 1106 }, 1107 }, 1108 { 1109 .callback = fix_acer_tm360_irqrouting, 1110 .ident = "Acer TravelMate 36x Laptop", 1111 .matches = { 1112 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1113 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"), 1114 }, 1115 }, 1116 { } 1117 }; 1118 1119 void __init pcibios_irq_init(void) 1120 { 1121 DBG(KERN_DEBUG "PCI: IRQ init\n"); 1122 1123 if (raw_pci_ops == NULL) 1124 return; 1125 1126 dmi_check_system(pciirq_dmi_table); 1127 1128 pirq_table = pirq_find_routing_table(); 1129 1130 #ifdef CONFIG_PCI_BIOS 1131 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN)) 1132 pirq_table = pcibios_get_irq_routing_table(); 1133 #endif 1134 if (pirq_table) { 1135 pirq_peer_trick(); 1136 pirq_find_router(&pirq_router); 1137 if (pirq_table->exclusive_irqs) { 1138 int i; 1139 for (i = 0; i < 16; i++) 1140 if (!(pirq_table->exclusive_irqs & (1 << i))) 1141 pirq_penalty[i] += 100; 1142 } 1143 /* 1144 * If we're using the I/O APIC, avoid using the PCI IRQ 1145 * routing table 1146 */ 1147 if (io_apic_assign_pci_irqs) 1148 pirq_table = NULL; 1149 } 1150 1151 x86_init.pci.fixup_irqs(); 1152 1153 if (io_apic_assign_pci_irqs && pci_routeirq) { 1154 struct pci_dev *dev = NULL; 1155 /* 1156 * PCI IRQ routing is set up by pci_enable_device(), but we 1157 * also do it here in case there are still broken drivers that 1158 * don't use pci_enable_device(). 1159 */ 1160 printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n"); 1161 for_each_pci_dev(dev) 1162 pirq_enable_irq(dev); 1163 } 1164 } 1165 1166 static void pirq_penalize_isa_irq(int irq, int active) 1167 { 1168 /* 1169 * If any ISAPnP device reports an IRQ in its list of possible 1170 * IRQ's, we try to avoid assigning it to PCI devices. 1171 */ 1172 if (irq < 16) { 1173 if (active) 1174 pirq_penalty[irq] += 1000; 1175 else 1176 pirq_penalty[irq] += 100; 1177 } 1178 } 1179 1180 void pcibios_penalize_isa_irq(int irq, int active) 1181 { 1182 #ifdef CONFIG_ACPI 1183 if (!acpi_noirq) 1184 acpi_penalize_isa_irq(irq, active); 1185 else 1186 #endif 1187 pirq_penalize_isa_irq(irq, active); 1188 } 1189 1190 static int pirq_enable_irq(struct pci_dev *dev) 1191 { 1192 u8 pin = 0; 1193 1194 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1195 if (pin && !pcibios_lookup_irq(dev, 1)) { 1196 char *msg = ""; 1197 1198 if (!io_apic_assign_pci_irqs && dev->irq) 1199 return 0; 1200 1201 if (io_apic_assign_pci_irqs) { 1202 #ifdef CONFIG_X86_IO_APIC 1203 struct pci_dev *temp_dev; 1204 int irq; 1205 1206 if (dev->irq_managed && dev->irq > 0) 1207 return 0; 1208 1209 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, 1210 PCI_SLOT(dev->devfn), pin - 1); 1211 /* 1212 * Busses behind bridges are typically not listed in the MP-table. 1213 * In this case we have to look up the IRQ based on the parent bus, 1214 * parent slot, and pin number. The SMP code detects such bridged 1215 * busses itself so we should get into this branch reliably. 1216 */ 1217 temp_dev = dev; 1218 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */ 1219 struct pci_dev *bridge = dev->bus->self; 1220 1221 pin = pci_swizzle_interrupt_pin(dev, pin); 1222 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, 1223 PCI_SLOT(bridge->devfn), 1224 pin - 1); 1225 if (irq >= 0) 1226 dev_warn(&dev->dev, "using bridge %s " 1227 "INT %c to get IRQ %d\n", 1228 pci_name(bridge), 'A' + pin - 1, 1229 irq); 1230 dev = bridge; 1231 } 1232 dev = temp_dev; 1233 if (irq >= 0) { 1234 dev->irq_managed = 1; 1235 dev->irq = irq; 1236 dev_info(&dev->dev, "PCI->APIC IRQ transform: " 1237 "INT %c -> IRQ %d\n", 'A' + pin - 1, irq); 1238 return 0; 1239 } else 1240 msg = "; probably buggy MP table"; 1241 #endif 1242 } else if (pci_probe & PCI_BIOS_IRQ_SCAN) 1243 msg = ""; 1244 else 1245 msg = "; please try using pci=biosirq"; 1246 1247 /* 1248 * With IDE legacy devices the IRQ lookup failure is not 1249 * a problem.. 1250 */ 1251 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && 1252 !(dev->class & 0x5)) 1253 return 0; 1254 1255 dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n", 1256 'A' + pin - 1, msg); 1257 } 1258 return 0; 1259 } 1260 1261 bool mp_should_keep_irq(struct device *dev) 1262 { 1263 if (dev->power.is_prepared) 1264 return true; 1265 #ifdef CONFIG_PM 1266 if (dev->power.runtime_status == RPM_SUSPENDING) 1267 return true; 1268 #endif 1269 1270 return false; 1271 } 1272 1273 static void pirq_disable_irq(struct pci_dev *dev) 1274 { 1275 if (io_apic_assign_pci_irqs && !mp_should_keep_irq(&dev->dev) && 1276 dev->irq_managed && dev->irq) { 1277 mp_unmap_irq(dev->irq); 1278 dev->irq = 0; 1279 dev->irq_managed = 0; 1280 } 1281 } 1282