1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Low-Level PCI Support for PC -- Routing of Interrupts 4 * 5 * (c) 1999--2000 Martin Mares <mj@ucw.cz> 6 */ 7 8 #include <linux/types.h> 9 #include <linux/kernel.h> 10 #include <linux/pci.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/dmi.h> 14 #include <linux/io.h> 15 #include <linux/smp.h> 16 #include <linux/spinlock.h> 17 #include <asm/io_apic.h> 18 #include <linux/irq.h> 19 #include <linux/acpi.h> 20 21 #include <asm/i8259.h> 22 #include <asm/pc-conf-reg.h> 23 #include <asm/pci_x86.h> 24 25 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) 26 #define PIRQ_VERSION 0x0100 27 28 static int broken_hp_bios_irq9; 29 static int acer_tm360_irqrouting; 30 31 static struct irq_routing_table *pirq_table; 32 33 static int pirq_enable_irq(struct pci_dev *dev); 34 static void pirq_disable_irq(struct pci_dev *dev); 35 36 /* 37 * Never use: 0, 1, 2 (timer, keyboard, and cascade) 38 * Avoid using: 13, 14 and 15 (FP error and IDE). 39 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse) 40 */ 41 unsigned int pcibios_irq_mask = 0xfff8; 42 43 static int pirq_penalty[16] = { 44 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000, 45 0, 0, 0, 0, 1000, 100000, 100000, 100000 46 }; 47 48 struct irq_router { 49 char *name; 50 u16 vendor, device; 51 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq); 52 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, 53 int new); 54 int (*lvl)(struct pci_dev *router, struct pci_dev *dev, int pirq, 55 int irq); 56 }; 57 58 struct irq_router_handler { 59 u16 vendor; 60 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device); 61 }; 62 63 int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq; 64 void (*pcibios_disable_irq)(struct pci_dev *dev) = pirq_disable_irq; 65 66 /* 67 * Check passed address for the PCI IRQ Routing Table signature 68 * and perform checksum verification. 69 */ 70 71 static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr) 72 { 73 struct irq_routing_table *rt; 74 int i; 75 u8 sum; 76 77 rt = (struct irq_routing_table *) addr; 78 if (rt->signature != PIRQ_SIGNATURE || 79 rt->version != PIRQ_VERSION || 80 rt->size % 16 || 81 rt->size < sizeof(struct irq_routing_table)) 82 return NULL; 83 sum = 0; 84 for (i = 0; i < rt->size; i++) 85 sum += addr[i]; 86 if (!sum) { 87 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%lx\n", 88 __pa(rt)); 89 return rt; 90 } 91 return NULL; 92 } 93 94 95 96 /* 97 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table. 98 */ 99 100 static struct irq_routing_table * __init pirq_find_routing_table(void) 101 { 102 u8 *addr; 103 struct irq_routing_table *rt; 104 105 if (pirq_table_addr) { 106 rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr)); 107 if (rt) 108 return rt; 109 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n"); 110 } 111 for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) { 112 rt = pirq_check_routing_table(addr); 113 if (rt) 114 return rt; 115 } 116 return NULL; 117 } 118 119 /* 120 * If we have a IRQ routing table, use it to search for peer host 121 * bridges. It's a gross hack, but since there are no other known 122 * ways how to get a list of buses, we have to go this way. 123 */ 124 125 static void __init pirq_peer_trick(void) 126 { 127 struct irq_routing_table *rt = pirq_table; 128 u8 busmap[256]; 129 int i; 130 struct irq_info *e; 131 132 memset(busmap, 0, sizeof(busmap)); 133 for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) { 134 e = &rt->slots[i]; 135 #ifdef DEBUG 136 { 137 int j; 138 DBG(KERN_DEBUG "%02x:%02x.%x slot=%02x", 139 e->bus, e->devfn / 8, e->devfn % 8, e->slot); 140 for (j = 0; j < 4; j++) 141 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap); 142 DBG("\n"); 143 } 144 #endif 145 busmap[e->bus] = 1; 146 } 147 for (i = 1; i < 256; i++) { 148 if (!busmap[i] || pci_find_bus(0, i)) 149 continue; 150 pcibios_scan_root(i); 151 } 152 pcibios_last_bus = -1; 153 } 154 155 /* 156 * Code for querying and setting of IRQ routes on various interrupt routers. 157 * PIC Edge/Level Control Registers (ELCR) 0x4d0 & 0x4d1. 158 */ 159 160 void elcr_set_level_irq(unsigned int irq) 161 { 162 unsigned char mask = 1 << (irq & 7); 163 unsigned int port = PIC_ELCR1 + (irq >> 3); 164 unsigned char val; 165 static u16 elcr_irq_mask; 166 167 if (irq >= 16 || (1 << irq) & elcr_irq_mask) 168 return; 169 170 elcr_irq_mask |= (1 << irq); 171 printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq); 172 val = inb(port); 173 if (!(val & mask)) { 174 DBG(KERN_DEBUG " -> edge"); 175 outb(val | mask, port); 176 } 177 } 178 179 /* 180 * PIRQ routing for the M1487 ISA Bus Controller (IBC) ASIC used 181 * with the ALi FinALi 486 chipset. The IBC is not decoded in the 182 * PCI configuration space, so we identify it by the accompanying 183 * M1489 Cache-Memory PCI Controller (CMP) ASIC. 184 * 185 * There are four 4-bit mappings provided, spread across two PCI 186 * INTx Routing Table Mapping Registers, available in the port I/O 187 * space accessible indirectly via the index/data register pair at 188 * 0x22/0x23, located at indices 0x42 and 0x43 for the INT1/INT2 189 * and INT3/INT4 lines respectively. The INT1/INT3 and INT2/INT4 190 * lines are mapped in the low and the high 4-bit nibble of the 191 * corresponding register as follows: 192 * 193 * 0000 : Disabled 194 * 0001 : IRQ9 195 * 0010 : IRQ3 196 * 0011 : IRQ10 197 * 0100 : IRQ4 198 * 0101 : IRQ5 199 * 0110 : IRQ7 200 * 0111 : IRQ6 201 * 1000 : Reserved 202 * 1001 : IRQ11 203 * 1010 : Reserved 204 * 1011 : IRQ12 205 * 1100 : Reserved 206 * 1101 : IRQ14 207 * 1110 : Reserved 208 * 1111 : IRQ15 209 * 210 * In addition to the usual ELCR register pair there is a separate 211 * PCI INTx Sensitivity Register at index 0x44 in the same port I/O 212 * space, whose bits 3:0 select the trigger mode for INT[4:1] lines 213 * respectively. Any bit set to 1 causes interrupts coming on the 214 * corresponding line to be passed to ISA as edge-triggered and 215 * otherwise they are passed as level-triggered. Manufacturer's 216 * documentation says this register has to be set consistently with 217 * the relevant ELCR register. 218 * 219 * Accesses to the port I/O space concerned here need to be unlocked 220 * by writing the value of 0xc5 to the Lock Register at index 0x03 221 * beforehand. Any other value written to said register prevents 222 * further accesses from reaching the register file, except for the 223 * Lock Register being written with 0xc5 again. 224 * 225 * References: 226 * 227 * "M1489/M1487: 486 PCI Chip Set", Version 1.2, Acer Laboratories 228 * Inc., July 1997 229 */ 230 231 #define PC_CONF_FINALI_LOCK 0x03u 232 #define PC_CONF_FINALI_PCI_INTX_RT1 0x42u 233 #define PC_CONF_FINALI_PCI_INTX_RT2 0x43u 234 #define PC_CONF_FINALI_PCI_INTX_SENS 0x44u 235 236 #define PC_CONF_FINALI_LOCK_KEY 0xc5u 237 238 static u8 read_pc_conf_nybble(u8 base, u8 index) 239 { 240 u8 reg = base + (index >> 1); 241 u8 x; 242 243 x = pc_conf_get(reg); 244 return index & 1 ? x >> 4 : x & 0xf; 245 } 246 247 static void write_pc_conf_nybble(u8 base, u8 index, u8 val) 248 { 249 u8 reg = base + (index >> 1); 250 u8 x; 251 252 x = pc_conf_get(reg); 253 x = index & 1 ? (x & 0x0f) | (val << 4) : (x & 0xf0) | val; 254 pc_conf_set(reg, x); 255 } 256 257 static int pirq_finali_get(struct pci_dev *router, struct pci_dev *dev, 258 int pirq) 259 { 260 static const u8 irqmap[16] = { 261 0, 9, 3, 10, 4, 5, 7, 6, 0, 11, 0, 12, 0, 14, 0, 15 262 }; 263 unsigned long flags; 264 u8 x; 265 266 raw_spin_lock_irqsave(&pc_conf_lock, flags); 267 pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY); 268 x = irqmap[read_pc_conf_nybble(PC_CONF_FINALI_PCI_INTX_RT1, pirq - 1)]; 269 pc_conf_set(PC_CONF_FINALI_LOCK, 0); 270 raw_spin_unlock_irqrestore(&pc_conf_lock, flags); 271 return x; 272 } 273 274 static int pirq_finali_set(struct pci_dev *router, struct pci_dev *dev, 275 int pirq, int irq) 276 { 277 static const u8 irqmap[16] = { 278 0, 0, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 279 }; 280 u8 val = irqmap[irq]; 281 unsigned long flags; 282 283 if (!val) 284 return 0; 285 286 raw_spin_lock_irqsave(&pc_conf_lock, flags); 287 pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY); 288 write_pc_conf_nybble(PC_CONF_FINALI_PCI_INTX_RT1, pirq - 1, val); 289 pc_conf_set(PC_CONF_FINALI_LOCK, 0); 290 raw_spin_unlock_irqrestore(&pc_conf_lock, flags); 291 return 1; 292 } 293 294 static int pirq_finali_lvl(struct pci_dev *router, struct pci_dev *dev, 295 int pirq, int irq) 296 { 297 u8 mask = ~(1u << (pirq - 1)); 298 unsigned long flags; 299 u8 trig; 300 301 elcr_set_level_irq(irq); 302 raw_spin_lock_irqsave(&pc_conf_lock, flags); 303 pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY); 304 trig = pc_conf_get(PC_CONF_FINALI_PCI_INTX_SENS); 305 trig &= mask; 306 pc_conf_set(PC_CONF_FINALI_PCI_INTX_SENS, trig); 307 pc_conf_set(PC_CONF_FINALI_LOCK, 0); 308 raw_spin_unlock_irqrestore(&pc_conf_lock, flags); 309 return 1; 310 } 311 312 /* 313 * Common IRQ routing practice: nibbles in config space, 314 * offset by some magic constant. 315 */ 316 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr) 317 { 318 u8 x; 319 unsigned reg = offset + (nr >> 1); 320 321 pci_read_config_byte(router, reg, &x); 322 return (nr & 1) ? (x >> 4) : (x & 0xf); 323 } 324 325 static void write_config_nybble(struct pci_dev *router, unsigned offset, 326 unsigned nr, unsigned int val) 327 { 328 u8 x; 329 unsigned reg = offset + (nr >> 1); 330 331 pci_read_config_byte(router, reg, &x); 332 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val); 333 pci_write_config_byte(router, reg, x); 334 } 335 336 /* 337 * ALI pirq entries are damn ugly, and completely undocumented. 338 * This has been figured out from pirq tables, and it's not a pretty 339 * picture. 340 */ 341 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 342 { 343 static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 }; 344 345 WARN_ON_ONCE(pirq > 16); 346 return irqmap[read_config_nybble(router, 0x48, pirq-1)]; 347 } 348 349 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 350 { 351 static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 }; 352 unsigned int val = irqmap[irq]; 353 354 WARN_ON_ONCE(pirq > 16); 355 if (val) { 356 write_config_nybble(router, 0x48, pirq-1, val); 357 return 1; 358 } 359 return 0; 360 } 361 362 /* 363 * PIRQ routing for the 82374EB/82374SB EISA System Component (ESC) 364 * ASIC used with the Intel 82420 and 82430 PCIsets. The ESC is not 365 * decoded in the PCI configuration space, so we identify it by the 366 * accompanying 82375EB/82375SB PCI-EISA Bridge (PCEB) ASIC. 367 * 368 * There are four PIRQ Route Control registers, available in the 369 * port I/O space accessible indirectly via the index/data register 370 * pair at 0x22/0x23, located at indices 0x60/0x61/0x62/0x63 for the 371 * PIRQ0/1/2/3# lines respectively. The semantics is the same as 372 * with the PIIX router. 373 * 374 * Accesses to the port I/O space concerned here need to be unlocked 375 * by writing the value of 0x0f to the ESC ID Register at index 0x02 376 * beforehand. Any other value written to said register prevents 377 * further accesses from reaching the register file, except for the 378 * ESC ID Register being written with 0x0f again. 379 * 380 * References: 381 * 382 * "82374EB/82374SB EISA System Component (ESC)", Intel Corporation, 383 * Order Number: 290476-004, March 1996 384 * 385 * "82375EB/82375SB PCI-EISA Bridge (PCEB)", Intel Corporation, Order 386 * Number: 290477-004, March 1996 387 */ 388 389 #define PC_CONF_I82374_ESC_ID 0x02u 390 #define PC_CONF_I82374_PIRQ_ROUTE_CONTROL 0x60u 391 392 #define PC_CONF_I82374_ESC_ID_KEY 0x0fu 393 394 static int pirq_esc_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 395 { 396 unsigned long flags; 397 int reg; 398 u8 x; 399 400 reg = pirq; 401 if (reg >= 1 && reg <= 4) 402 reg += PC_CONF_I82374_PIRQ_ROUTE_CONTROL - 1; 403 404 raw_spin_lock_irqsave(&pc_conf_lock, flags); 405 pc_conf_set(PC_CONF_I82374_ESC_ID, PC_CONF_I82374_ESC_ID_KEY); 406 x = pc_conf_get(reg); 407 pc_conf_set(PC_CONF_I82374_ESC_ID, 0); 408 raw_spin_unlock_irqrestore(&pc_conf_lock, flags); 409 return (x < 16) ? x : 0; 410 } 411 412 static int pirq_esc_set(struct pci_dev *router, struct pci_dev *dev, int pirq, 413 int irq) 414 { 415 unsigned long flags; 416 int reg; 417 418 reg = pirq; 419 if (reg >= 1 && reg <= 4) 420 reg += PC_CONF_I82374_PIRQ_ROUTE_CONTROL - 1; 421 422 raw_spin_lock_irqsave(&pc_conf_lock, flags); 423 pc_conf_set(PC_CONF_I82374_ESC_ID, PC_CONF_I82374_ESC_ID_KEY); 424 pc_conf_set(reg, irq); 425 pc_conf_set(PC_CONF_I82374_ESC_ID, 0); 426 raw_spin_unlock_irqrestore(&pc_conf_lock, flags); 427 return 1; 428 } 429 430 /* 431 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is 432 * just a pointer to the config space. 433 */ 434 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 435 { 436 u8 x; 437 438 pci_read_config_byte(router, pirq, &x); 439 return (x < 16) ? x : 0; 440 } 441 442 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 443 { 444 pci_write_config_byte(router, pirq, irq); 445 return 1; 446 } 447 448 /* 449 * PIRQ routing for the 82426EX ISA Bridge (IB) ASIC used with the 450 * Intel 82420EX PCIset. 451 * 452 * There are only two PIRQ Route Control registers, available in the 453 * combined 82425EX/82426EX PCI configuration space, at 0x66 and 0x67 454 * for the PIRQ0# and PIRQ1# lines respectively. The semantics is 455 * the same as with the PIIX router. 456 * 457 * References: 458 * 459 * "82420EX PCIset Data Sheet, 82425EX PCI System Controller (PSC) 460 * and 82426EX ISA Bridge (IB)", Intel Corporation, Order Number: 461 * 290488-004, December 1995 462 */ 463 464 #define PCI_I82426EX_PIRQ_ROUTE_CONTROL 0x66u 465 466 static int pirq_ib_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 467 { 468 int reg; 469 u8 x; 470 471 reg = pirq; 472 if (reg >= 1 && reg <= 2) 473 reg += PCI_I82426EX_PIRQ_ROUTE_CONTROL - 1; 474 475 pci_read_config_byte(router, reg, &x); 476 return (x < 16) ? x : 0; 477 } 478 479 static int pirq_ib_set(struct pci_dev *router, struct pci_dev *dev, int pirq, 480 int irq) 481 { 482 int reg; 483 484 reg = pirq; 485 if (reg >= 1 && reg <= 2) 486 reg += PCI_I82426EX_PIRQ_ROUTE_CONTROL - 1; 487 488 pci_write_config_byte(router, reg, irq); 489 return 1; 490 } 491 492 /* 493 * The VIA pirq rules are nibble-based, like ALI, 494 * but without the ugly irq number munging. 495 * However, PIRQD is in the upper instead of lower 4 bits. 496 */ 497 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 498 { 499 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq); 500 } 501 502 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 503 { 504 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq); 505 return 1; 506 } 507 508 /* 509 * The VIA pirq rules are nibble-based, like ALI, 510 * but without the ugly irq number munging. 511 * However, for 82C586, nibble map is different . 512 */ 513 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 514 { 515 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 516 517 WARN_ON_ONCE(pirq > 5); 518 return read_config_nybble(router, 0x55, pirqmap[pirq-1]); 519 } 520 521 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 522 { 523 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 524 525 WARN_ON_ONCE(pirq > 5); 526 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq); 527 return 1; 528 } 529 530 /* 531 * ITE 8330G pirq rules are nibble-based 532 * FIXME: pirqmap may be { 1, 0, 3, 2 }, 533 * 2+3 are both mapped to irq 9 on my system 534 */ 535 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 536 { 537 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 538 539 WARN_ON_ONCE(pirq > 4); 540 return read_config_nybble(router, 0x43, pirqmap[pirq-1]); 541 } 542 543 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 544 { 545 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 546 547 WARN_ON_ONCE(pirq > 4); 548 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq); 549 return 1; 550 } 551 552 /* 553 * OPTI: high four bits are nibble pointer.. 554 * I wonder what the low bits do? 555 */ 556 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 557 { 558 return read_config_nybble(router, 0xb8, pirq >> 4); 559 } 560 561 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 562 { 563 write_config_nybble(router, 0xb8, pirq >> 4, irq); 564 return 1; 565 } 566 567 /* 568 * Cyrix: nibble offset 0x5C 569 * 0x5C bits 7:4 is INTB bits 3:0 is INTA 570 * 0x5D bits 7:4 is INTD bits 3:0 is INTC 571 */ 572 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 573 { 574 return read_config_nybble(router, 0x5C, (pirq-1)^1); 575 } 576 577 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 578 { 579 write_config_nybble(router, 0x5C, (pirq-1)^1, irq); 580 return 1; 581 } 582 583 /* 584 * PIRQ routing for SiS 85C503 router used in several SiS chipsets. 585 * We have to deal with the following issues here: 586 * - vendors have different ideas about the meaning of link values 587 * - some onboard devices (integrated in the chipset) have special 588 * links and are thus routed differently (i.e. not via PCI INTA-INTD) 589 * - different revision of the router have a different layout for 590 * the routing registers, particularly for the onchip devices 591 * 592 * For all routing registers the common thing is we have one byte 593 * per routeable link which is defined as: 594 * bit 7 IRQ mapping enabled (0) or disabled (1) 595 * bits [6:4] reserved (sometimes used for onchip devices) 596 * bits [3:0] IRQ to map to 597 * allowed: 3-7, 9-12, 14-15 598 * reserved: 0, 1, 2, 8, 13 599 * 600 * The config-space registers located at 0x41/0x42/0x43/0x44 are 601 * always used to route the normal PCI INT A/B/C/D respectively. 602 * Apparently there are systems implementing PCI routing table using 603 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D. 604 * We try our best to handle both link mappings. 605 * 606 * Currently (2003-05-21) it appears most SiS chipsets follow the 607 * definition of routing registers from the SiS-5595 southbridge. 608 * According to the SiS 5595 datasheets the revision id's of the 609 * router (ISA-bridge) should be 0x01 or 0xb0. 610 * 611 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1. 612 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets. 613 * They seem to work with the current routing code. However there is 614 * some concern because of the two USB-OHCI HCs (original SiS 5595 615 * had only one). YMMV. 616 * 617 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1: 618 * 619 * 0x61: IDEIRQ: 620 * bits [6:5] must be written 01 621 * bit 4 channel-select primary (0), secondary (1) 622 * 623 * 0x62: USBIRQ: 624 * bit 6 OHCI function disabled (0), enabled (1) 625 * 626 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved 627 * 628 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved 629 * 630 * We support USBIRQ (in addition to INTA-INTD) and keep the 631 * IDE, ACPI and DAQ routing untouched as set by the BIOS. 632 * 633 * Currently the only reported exception is the new SiS 65x chipset 634 * which includes the SiS 69x southbridge. Here we have the 85C503 635 * router revision 0x04 and there are changes in the register layout 636 * mostly related to the different USB HCs with USB 2.0 support. 637 * 638 * Onchip routing for router rev-id 0x04 (try-and-error observation) 639 * 640 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs 641 * bit 6-4 are probably unused, not like 5595 642 */ 643 644 #define PIRQ_SIS503_IRQ_MASK 0x0f 645 #define PIRQ_SIS503_IRQ_DISABLE 0x80 646 #define PIRQ_SIS503_USB_ENABLE 0x40 647 648 static int pirq_sis503_get(struct pci_dev *router, struct pci_dev *dev, 649 int pirq) 650 { 651 u8 x; 652 int reg; 653 654 reg = pirq; 655 if (reg >= 0x01 && reg <= 0x04) 656 reg += 0x40; 657 pci_read_config_byte(router, reg, &x); 658 return (x & PIRQ_SIS503_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS503_IRQ_MASK); 659 } 660 661 static int pirq_sis503_set(struct pci_dev *router, struct pci_dev *dev, 662 int pirq, int irq) 663 { 664 u8 x; 665 int reg; 666 667 reg = pirq; 668 if (reg >= 0x01 && reg <= 0x04) 669 reg += 0x40; 670 pci_read_config_byte(router, reg, &x); 671 x &= ~(PIRQ_SIS503_IRQ_MASK | PIRQ_SIS503_IRQ_DISABLE); 672 x |= irq ? irq : PIRQ_SIS503_IRQ_DISABLE; 673 pci_write_config_byte(router, reg, x); 674 return 1; 675 } 676 677 678 /* 679 * VLSI: nibble offset 0x74 - educated guess due to routing table and 680 * config space of VLSI 82C534 PCI-bridge/router (1004:0102) 681 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard 682 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6 683 * for the busbridge to the docking station. 684 */ 685 686 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 687 { 688 WARN_ON_ONCE(pirq >= 9); 689 if (pirq > 8) { 690 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq); 691 return 0; 692 } 693 return read_config_nybble(router, 0x74, pirq-1); 694 } 695 696 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 697 { 698 WARN_ON_ONCE(pirq >= 9); 699 if (pirq > 8) { 700 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq); 701 return 0; 702 } 703 write_config_nybble(router, 0x74, pirq-1, irq); 704 return 1; 705 } 706 707 /* 708 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index 709 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register 710 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect 711 * register is a straight binary coding of desired PIC IRQ (low nibble). 712 * 713 * The 'link' value in the PIRQ table is already in the correct format 714 * for the Index register. There are some special index values: 715 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1, 716 * and 0x03 for SMBus. 717 */ 718 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 719 { 720 outb(pirq, 0xc00); 721 return inb(0xc01) & 0xf; 722 } 723 724 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, 725 int pirq, int irq) 726 { 727 outb(pirq, 0xc00); 728 outb(irq, 0xc01); 729 return 1; 730 } 731 732 /* Support for AMD756 PCI IRQ Routing 733 * Jhon H. Caicedo <jhcaiced@osso.org.co> 734 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced) 735 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced) 736 * The AMD756 pirq rules are nibble-based 737 * offset 0x56 0-3 PIRQA 4-7 PIRQB 738 * offset 0x57 0-3 PIRQC 4-7 PIRQD 739 */ 740 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 741 { 742 u8 irq; 743 irq = 0; 744 if (pirq <= 4) 745 irq = read_config_nybble(router, 0x56, pirq - 1); 746 dev_info(&dev->dev, 747 "AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d\n", 748 dev->vendor, dev->device, pirq, irq); 749 return irq; 750 } 751 752 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 753 { 754 dev_info(&dev->dev, 755 "AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d\n", 756 dev->vendor, dev->device, pirq, irq); 757 if (pirq <= 4) 758 write_config_nybble(router, 0x56, pirq - 1, irq); 759 return 1; 760 } 761 762 /* 763 * PicoPower PT86C523 764 */ 765 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 766 { 767 outb(0x10 + ((pirq - 1) >> 1), 0x24); 768 return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf); 769 } 770 771 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq, 772 int irq) 773 { 774 unsigned int x; 775 outb(0x10 + ((pirq - 1) >> 1), 0x24); 776 x = inb(0x26); 777 x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq)); 778 outb(x, 0x26); 779 return 1; 780 } 781 782 #ifdef CONFIG_PCI_BIOS 783 784 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 785 { 786 struct pci_dev *bridge; 787 int pin = pci_get_interrupt_pin(dev, &bridge); 788 return pcibios_set_irq_routing(bridge, pin - 1, irq); 789 } 790 791 #endif 792 793 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 794 { 795 static struct pci_device_id __initdata pirq_440gx[] = { 796 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) }, 797 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) }, 798 { }, 799 }; 800 801 /* 440GX has a proprietary PIRQ router -- don't use it */ 802 if (pci_dev_present(pirq_440gx)) 803 return 0; 804 805 switch (device) { 806 case PCI_DEVICE_ID_INTEL_82375: 807 r->name = "PCEB/ESC"; 808 r->get = pirq_esc_get; 809 r->set = pirq_esc_set; 810 return 1; 811 case PCI_DEVICE_ID_INTEL_82371FB_0: 812 case PCI_DEVICE_ID_INTEL_82371SB_0: 813 case PCI_DEVICE_ID_INTEL_82371AB_0: 814 case PCI_DEVICE_ID_INTEL_82371MX: 815 case PCI_DEVICE_ID_INTEL_82443MX_0: 816 case PCI_DEVICE_ID_INTEL_82801AA_0: 817 case PCI_DEVICE_ID_INTEL_82801AB_0: 818 case PCI_DEVICE_ID_INTEL_82801BA_0: 819 case PCI_DEVICE_ID_INTEL_82801BA_10: 820 case PCI_DEVICE_ID_INTEL_82801CA_0: 821 case PCI_DEVICE_ID_INTEL_82801CA_12: 822 case PCI_DEVICE_ID_INTEL_82801DB_0: 823 case PCI_DEVICE_ID_INTEL_82801E_0: 824 case PCI_DEVICE_ID_INTEL_82801EB_0: 825 case PCI_DEVICE_ID_INTEL_ESB_1: 826 case PCI_DEVICE_ID_INTEL_ICH6_0: 827 case PCI_DEVICE_ID_INTEL_ICH6_1: 828 case PCI_DEVICE_ID_INTEL_ICH7_0: 829 case PCI_DEVICE_ID_INTEL_ICH7_1: 830 case PCI_DEVICE_ID_INTEL_ICH7_30: 831 case PCI_DEVICE_ID_INTEL_ICH7_31: 832 case PCI_DEVICE_ID_INTEL_TGP_LPC: 833 case PCI_DEVICE_ID_INTEL_ESB2_0: 834 case PCI_DEVICE_ID_INTEL_ICH8_0: 835 case PCI_DEVICE_ID_INTEL_ICH8_1: 836 case PCI_DEVICE_ID_INTEL_ICH8_2: 837 case PCI_DEVICE_ID_INTEL_ICH8_3: 838 case PCI_DEVICE_ID_INTEL_ICH8_4: 839 case PCI_DEVICE_ID_INTEL_ICH9_0: 840 case PCI_DEVICE_ID_INTEL_ICH9_1: 841 case PCI_DEVICE_ID_INTEL_ICH9_2: 842 case PCI_DEVICE_ID_INTEL_ICH9_3: 843 case PCI_DEVICE_ID_INTEL_ICH9_4: 844 case PCI_DEVICE_ID_INTEL_ICH9_5: 845 case PCI_DEVICE_ID_INTEL_EP80579_0: 846 case PCI_DEVICE_ID_INTEL_ICH10_0: 847 case PCI_DEVICE_ID_INTEL_ICH10_1: 848 case PCI_DEVICE_ID_INTEL_ICH10_2: 849 case PCI_DEVICE_ID_INTEL_ICH10_3: 850 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0: 851 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1: 852 r->name = "PIIX/ICH"; 853 r->get = pirq_piix_get; 854 r->set = pirq_piix_set; 855 return 1; 856 case PCI_DEVICE_ID_INTEL_82425: 857 r->name = "PSC/IB"; 858 r->get = pirq_ib_get; 859 r->set = pirq_ib_set; 860 return 1; 861 } 862 863 if ((device >= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN && 864 device <= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX) 865 || (device >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && 866 device <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) 867 || (device >= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN && 868 device <= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX) 869 || (device >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && 870 device <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) { 871 r->name = "PIIX/ICH"; 872 r->get = pirq_piix_get; 873 r->set = pirq_piix_set; 874 return 1; 875 } 876 877 return 0; 878 } 879 880 static __init int via_router_probe(struct irq_router *r, 881 struct pci_dev *router, u16 device) 882 { 883 /* FIXME: We should move some of the quirk fixup stuff here */ 884 885 /* 886 * workarounds for some buggy BIOSes 887 */ 888 if (device == PCI_DEVICE_ID_VIA_82C586_0) { 889 switch (router->device) { 890 case PCI_DEVICE_ID_VIA_82C686: 891 /* 892 * Asus k7m bios wrongly reports 82C686A 893 * as 586-compatible 894 */ 895 device = PCI_DEVICE_ID_VIA_82C686; 896 break; 897 case PCI_DEVICE_ID_VIA_8235: 898 /** 899 * Asus a7v-x bios wrongly reports 8235 900 * as 586-compatible 901 */ 902 device = PCI_DEVICE_ID_VIA_8235; 903 break; 904 case PCI_DEVICE_ID_VIA_8237: 905 /** 906 * Asus a7v600 bios wrongly reports 8237 907 * as 586-compatible 908 */ 909 device = PCI_DEVICE_ID_VIA_8237; 910 break; 911 } 912 } 913 914 switch (device) { 915 case PCI_DEVICE_ID_VIA_82C586_0: 916 r->name = "VIA"; 917 r->get = pirq_via586_get; 918 r->set = pirq_via586_set; 919 return 1; 920 case PCI_DEVICE_ID_VIA_82C596: 921 case PCI_DEVICE_ID_VIA_82C686: 922 case PCI_DEVICE_ID_VIA_8231: 923 case PCI_DEVICE_ID_VIA_8233A: 924 case PCI_DEVICE_ID_VIA_8235: 925 case PCI_DEVICE_ID_VIA_8237: 926 /* FIXME: add new ones for 8233/5 */ 927 r->name = "VIA"; 928 r->get = pirq_via_get; 929 r->set = pirq_via_set; 930 return 1; 931 } 932 return 0; 933 } 934 935 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 936 { 937 switch (device) { 938 case PCI_DEVICE_ID_VLSI_82C534: 939 r->name = "VLSI 82C534"; 940 r->get = pirq_vlsi_get; 941 r->set = pirq_vlsi_set; 942 return 1; 943 } 944 return 0; 945 } 946 947 948 static __init int serverworks_router_probe(struct irq_router *r, 949 struct pci_dev *router, u16 device) 950 { 951 switch (device) { 952 case PCI_DEVICE_ID_SERVERWORKS_OSB4: 953 case PCI_DEVICE_ID_SERVERWORKS_CSB5: 954 r->name = "ServerWorks"; 955 r->get = pirq_serverworks_get; 956 r->set = pirq_serverworks_set; 957 return 1; 958 } 959 return 0; 960 } 961 962 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 963 { 964 switch (device) { 965 case PCI_DEVICE_ID_SI_503: 966 r->name = "SiS85C503"; 967 r->get = pirq_sis503_get; 968 r->set = pirq_sis503_set; 969 return 1; 970 } 971 return 0; 972 } 973 974 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 975 { 976 switch (device) { 977 case PCI_DEVICE_ID_CYRIX_5520: 978 r->name = "NatSemi"; 979 r->get = pirq_cyrix_get; 980 r->set = pirq_cyrix_set; 981 return 1; 982 } 983 return 0; 984 } 985 986 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 987 { 988 switch (device) { 989 case PCI_DEVICE_ID_OPTI_82C700: 990 r->name = "OPTI"; 991 r->get = pirq_opti_get; 992 r->set = pirq_opti_set; 993 return 1; 994 } 995 return 0; 996 } 997 998 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 999 { 1000 switch (device) { 1001 case PCI_DEVICE_ID_ITE_IT8330G_0: 1002 r->name = "ITE"; 1003 r->get = pirq_ite_get; 1004 r->set = pirq_ite_set; 1005 return 1; 1006 } 1007 return 0; 1008 } 1009 1010 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 1011 { 1012 switch (device) { 1013 case PCI_DEVICE_ID_AL_M1489: 1014 r->name = "FinALi"; 1015 r->get = pirq_finali_get; 1016 r->set = pirq_finali_set; 1017 r->lvl = pirq_finali_lvl; 1018 return 1; 1019 case PCI_DEVICE_ID_AL_M1533: 1020 case PCI_DEVICE_ID_AL_M1563: 1021 r->name = "ALI"; 1022 r->get = pirq_ali_get; 1023 r->set = pirq_ali_set; 1024 return 1; 1025 } 1026 return 0; 1027 } 1028 1029 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 1030 { 1031 switch (device) { 1032 case PCI_DEVICE_ID_AMD_VIPER_740B: 1033 r->name = "AMD756"; 1034 break; 1035 case PCI_DEVICE_ID_AMD_VIPER_7413: 1036 r->name = "AMD766"; 1037 break; 1038 case PCI_DEVICE_ID_AMD_VIPER_7443: 1039 r->name = "AMD768"; 1040 break; 1041 default: 1042 return 0; 1043 } 1044 r->get = pirq_amd756_get; 1045 r->set = pirq_amd756_set; 1046 return 1; 1047 } 1048 1049 static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 1050 { 1051 switch (device) { 1052 case PCI_DEVICE_ID_PICOPOWER_PT86C523: 1053 r->name = "PicoPower PT86C523"; 1054 r->get = pirq_pico_get; 1055 r->set = pirq_pico_set; 1056 return 1; 1057 1058 case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP: 1059 r->name = "PicoPower PT86C523 rev. BB+"; 1060 r->get = pirq_pico_get; 1061 r->set = pirq_pico_set; 1062 return 1; 1063 } 1064 return 0; 1065 } 1066 1067 static __initdata struct irq_router_handler pirq_routers[] = { 1068 { PCI_VENDOR_ID_INTEL, intel_router_probe }, 1069 { PCI_VENDOR_ID_AL, ali_router_probe }, 1070 { PCI_VENDOR_ID_ITE, ite_router_probe }, 1071 { PCI_VENDOR_ID_VIA, via_router_probe }, 1072 { PCI_VENDOR_ID_OPTI, opti_router_probe }, 1073 { PCI_VENDOR_ID_SI, sis_router_probe }, 1074 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe }, 1075 { PCI_VENDOR_ID_VLSI, vlsi_router_probe }, 1076 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe }, 1077 { PCI_VENDOR_ID_AMD, amd_router_probe }, 1078 { PCI_VENDOR_ID_PICOPOWER, pico_router_probe }, 1079 /* Someone with docs needs to add the ATI Radeon IGP */ 1080 { 0, NULL } 1081 }; 1082 static struct irq_router pirq_router; 1083 static struct pci_dev *pirq_router_dev; 1084 1085 1086 /* 1087 * FIXME: should we have an option to say "generic for 1088 * chipset" ? 1089 */ 1090 1091 static void __init pirq_find_router(struct irq_router *r) 1092 { 1093 struct irq_routing_table *rt = pirq_table; 1094 struct irq_router_handler *h; 1095 1096 #ifdef CONFIG_PCI_BIOS 1097 if (!rt->signature) { 1098 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n"); 1099 r->set = pirq_bios_set; 1100 r->name = "BIOS"; 1101 return; 1102 } 1103 #endif 1104 1105 /* Default unless a driver reloads it */ 1106 r->name = "default"; 1107 r->get = NULL; 1108 r->set = NULL; 1109 1110 DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n", 1111 rt->rtr_vendor, rt->rtr_device); 1112 1113 pirq_router_dev = pci_get_domain_bus_and_slot(0, rt->rtr_bus, 1114 rt->rtr_devfn); 1115 if (!pirq_router_dev) { 1116 DBG(KERN_DEBUG "PCI: Interrupt router not found at " 1117 "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn); 1118 return; 1119 } 1120 1121 for (h = pirq_routers; h->vendor; h++) { 1122 /* First look for a router match */ 1123 if (rt->rtr_vendor == h->vendor && 1124 h->probe(r, pirq_router_dev, rt->rtr_device)) 1125 break; 1126 /* Fall back to a device match */ 1127 if (pirq_router_dev->vendor == h->vendor && 1128 h->probe(r, pirq_router_dev, pirq_router_dev->device)) 1129 break; 1130 } 1131 dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x:%04x]\n", 1132 pirq_router.name, 1133 pirq_router_dev->vendor, pirq_router_dev->device); 1134 1135 /* The device remains referenced for the kernel lifetime */ 1136 } 1137 1138 /* 1139 * We're supposed to match on the PCI device only and not the function, 1140 * but some BIOSes build their tables with the PCI function included 1141 * for motherboard devices, so if a complete match is found, then give 1142 * it precedence over a slot match. 1143 */ 1144 static struct irq_info *pirq_get_dev_info(struct pci_dev *dev) 1145 { 1146 struct irq_routing_table *rt = pirq_table; 1147 int entries = (rt->size - sizeof(struct irq_routing_table)) / 1148 sizeof(struct irq_info); 1149 struct irq_info *slotinfo = NULL; 1150 struct irq_info *info; 1151 1152 for (info = rt->slots; entries--; info++) 1153 if (info->bus == dev->bus->number) { 1154 if (info->devfn == dev->devfn) 1155 return info; 1156 if (!slotinfo && 1157 PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn)) 1158 slotinfo = info; 1159 } 1160 return slotinfo; 1161 } 1162 1163 /* 1164 * Buses behind bridges are typically not listed in the PIRQ routing table. 1165 * Do the usual dance then and walk the tree of bridges up adjusting the 1166 * pin number accordingly on the way until the originating root bus device 1167 * has been reached and then use its routing information. 1168 */ 1169 static struct irq_info *pirq_get_info(struct pci_dev *dev, u8 *pin) 1170 { 1171 struct pci_dev *temp_dev = dev; 1172 struct irq_info *info; 1173 u8 temp_pin = *pin; 1174 u8 dpin = temp_pin; 1175 1176 info = pirq_get_dev_info(dev); 1177 while (!info && temp_dev->bus->parent) { 1178 struct pci_dev *bridge = temp_dev->bus->self; 1179 1180 temp_pin = pci_swizzle_interrupt_pin(temp_dev, temp_pin); 1181 info = pirq_get_dev_info(bridge); 1182 if (info) 1183 dev_warn(&dev->dev, 1184 "using bridge %s INT %c to get INT %c\n", 1185 pci_name(bridge), 1186 'A' + temp_pin - 1, 'A' + dpin - 1); 1187 1188 temp_dev = bridge; 1189 } 1190 *pin = temp_pin; 1191 return info; 1192 } 1193 1194 static int pcibios_lookup_irq(struct pci_dev *dev, int assign) 1195 { 1196 struct irq_info *info; 1197 int i, pirq, newirq; 1198 u8 dpin, pin; 1199 int irq = 0; 1200 u32 mask; 1201 struct irq_router *r = &pirq_router; 1202 struct pci_dev *dev2 = NULL; 1203 char *msg = NULL; 1204 1205 /* Find IRQ pin */ 1206 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &dpin); 1207 if (!dpin) { 1208 dev_dbg(&dev->dev, "no interrupt pin\n"); 1209 return 0; 1210 } 1211 1212 if (io_apic_assign_pci_irqs) 1213 return 0; 1214 1215 /* Find IRQ routing entry */ 1216 1217 if (!pirq_table) 1218 return 0; 1219 1220 pin = dpin; 1221 info = pirq_get_info(dev, &pin); 1222 if (!info) { 1223 dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n", 1224 'A' + dpin - 1); 1225 return 0; 1226 } 1227 pirq = info->irq[pin - 1].link; 1228 mask = info->irq[pin - 1].bitmap; 1229 if (!pirq) { 1230 dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + dpin - 1); 1231 return 0; 1232 } 1233 dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x", 1234 'A' + dpin - 1, pirq, mask, pirq_table->exclusive_irqs); 1235 mask &= pcibios_irq_mask; 1236 1237 /* Work around broken HP Pavilion Notebooks which assign USB to 1238 IRQ 9 even though it is actually wired to IRQ 11 */ 1239 1240 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) { 1241 dev->irq = 11; 1242 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11); 1243 r->set(pirq_router_dev, dev, pirq, 11); 1244 } 1245 1246 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */ 1247 if (acer_tm360_irqrouting && dev->irq == 11 && 1248 dev->vendor == PCI_VENDOR_ID_O2) { 1249 pirq = 0x68; 1250 mask = 0x400; 1251 dev->irq = r->get(pirq_router_dev, dev, pirq); 1252 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 1253 } 1254 1255 /* 1256 * Find the best IRQ to assign: use the one 1257 * reported by the device if possible. 1258 */ 1259 newirq = dev->irq; 1260 if (newirq && !((1 << newirq) & mask)) { 1261 if (pci_probe & PCI_USE_PIRQ_MASK) 1262 newirq = 0; 1263 else 1264 dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask " 1265 "%#x; try pci=usepirqmask\n", newirq, mask); 1266 } 1267 if (!newirq && assign) { 1268 for (i = 0; i < 16; i++) { 1269 if (!(mask & (1 << i))) 1270 continue; 1271 if (pirq_penalty[i] < pirq_penalty[newirq] && 1272 can_request_irq(i, IRQF_SHARED)) 1273 newirq = i; 1274 } 1275 } 1276 dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + dpin - 1, newirq); 1277 1278 /* Check if it is hardcoded */ 1279 if ((pirq & 0xf0) == 0xf0) { 1280 irq = pirq & 0xf; 1281 msg = "hardcoded"; 1282 } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \ 1283 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) { 1284 msg = "found"; 1285 if (r->lvl) 1286 r->lvl(pirq_router_dev, dev, pirq, irq); 1287 else 1288 elcr_set_level_irq(irq); 1289 } else if (newirq && r->set && 1290 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) { 1291 if (r->set(pirq_router_dev, dev, pirq, newirq)) { 1292 if (r->lvl) 1293 r->lvl(pirq_router_dev, dev, pirq, newirq); 1294 else 1295 elcr_set_level_irq(newirq); 1296 msg = "assigned"; 1297 irq = newirq; 1298 } 1299 } 1300 1301 if (!irq) { 1302 if (newirq && mask == (1 << newirq)) { 1303 msg = "guessed"; 1304 irq = newirq; 1305 } else { 1306 dev_dbg(&dev->dev, "can't route interrupt\n"); 1307 return 0; 1308 } 1309 } 1310 dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", 1311 msg, 'A' + dpin - 1, irq); 1312 1313 /* Update IRQ for all devices with the same pirq value */ 1314 for_each_pci_dev(dev2) { 1315 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &dpin); 1316 if (!dpin) 1317 continue; 1318 1319 pin = dpin; 1320 info = pirq_get_info(dev2, &pin); 1321 if (!info) 1322 continue; 1323 if (info->irq[pin - 1].link == pirq) { 1324 /* 1325 * We refuse to override the dev->irq 1326 * information. Give a warning! 1327 */ 1328 if (dev2->irq && dev2->irq != irq && \ 1329 (!(pci_probe & PCI_USE_PIRQ_MASK) || \ 1330 ((1 << dev2->irq) & mask))) { 1331 #ifndef CONFIG_PCI_MSI 1332 dev_info(&dev2->dev, "IRQ routing conflict: " 1333 "have IRQ %d, want IRQ %d\n", 1334 dev2->irq, irq); 1335 #endif 1336 continue; 1337 } 1338 dev2->irq = irq; 1339 pirq_penalty[irq]++; 1340 if (dev != dev2) 1341 dev_info(&dev->dev, "sharing IRQ %d with %s\n", 1342 irq, pci_name(dev2)); 1343 } 1344 } 1345 return 1; 1346 } 1347 1348 void __init pcibios_fixup_irqs(void) 1349 { 1350 struct pci_dev *dev = NULL; 1351 u8 pin; 1352 1353 DBG(KERN_DEBUG "PCI: IRQ fixup\n"); 1354 for_each_pci_dev(dev) { 1355 /* 1356 * If the BIOS has set an out of range IRQ number, just 1357 * ignore it. Also keep track of which IRQ's are 1358 * already in use. 1359 */ 1360 if (dev->irq >= 16) { 1361 dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq); 1362 dev->irq = 0; 1363 } 1364 /* 1365 * If the IRQ is already assigned to a PCI device, 1366 * ignore its ISA use penalty 1367 */ 1368 if (pirq_penalty[dev->irq] >= 100 && 1369 pirq_penalty[dev->irq] < 100000) 1370 pirq_penalty[dev->irq] = 0; 1371 pirq_penalty[dev->irq]++; 1372 } 1373 1374 if (io_apic_assign_pci_irqs) 1375 return; 1376 1377 dev = NULL; 1378 for_each_pci_dev(dev) { 1379 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1380 if (!pin) 1381 continue; 1382 1383 /* 1384 * Still no IRQ? Try to lookup one... 1385 */ 1386 if (!dev->irq) 1387 pcibios_lookup_irq(dev, 0); 1388 } 1389 } 1390 1391 /* 1392 * Work around broken HP Pavilion Notebooks which assign USB to 1393 * IRQ 9 even though it is actually wired to IRQ 11 1394 */ 1395 static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d) 1396 { 1397 if (!broken_hp_bios_irq9) { 1398 broken_hp_bios_irq9 = 1; 1399 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", 1400 d->ident); 1401 } 1402 return 0; 1403 } 1404 1405 /* 1406 * Work around broken Acer TravelMate 360 Notebooks which assign 1407 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10 1408 */ 1409 static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d) 1410 { 1411 if (!acer_tm360_irqrouting) { 1412 acer_tm360_irqrouting = 1; 1413 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", 1414 d->ident); 1415 } 1416 return 0; 1417 } 1418 1419 static const struct dmi_system_id pciirq_dmi_table[] __initconst = { 1420 { 1421 .callback = fix_broken_hp_bios_irq9, 1422 .ident = "HP Pavilion N5400 Series Laptop", 1423 .matches = { 1424 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1425 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"), 1426 DMI_MATCH(DMI_PRODUCT_VERSION, 1427 "HP Pavilion Notebook Model GE"), 1428 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"), 1429 }, 1430 }, 1431 { 1432 .callback = fix_acer_tm360_irqrouting, 1433 .ident = "Acer TravelMate 36x Laptop", 1434 .matches = { 1435 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1436 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"), 1437 }, 1438 }, 1439 { } 1440 }; 1441 1442 void __init pcibios_irq_init(void) 1443 { 1444 struct irq_routing_table *rtable = NULL; 1445 1446 DBG(KERN_DEBUG "PCI: IRQ init\n"); 1447 1448 if (raw_pci_ops == NULL) 1449 return; 1450 1451 dmi_check_system(pciirq_dmi_table); 1452 1453 pirq_table = pirq_find_routing_table(); 1454 1455 #ifdef CONFIG_PCI_BIOS 1456 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN)) { 1457 pirq_table = pcibios_get_irq_routing_table(); 1458 rtable = pirq_table; 1459 } 1460 #endif 1461 if (pirq_table) { 1462 pirq_peer_trick(); 1463 pirq_find_router(&pirq_router); 1464 if (pirq_table->exclusive_irqs) { 1465 int i; 1466 for (i = 0; i < 16; i++) 1467 if (!(pirq_table->exclusive_irqs & (1 << i))) 1468 pirq_penalty[i] += 100; 1469 } 1470 /* 1471 * If we're using the I/O APIC, avoid using the PCI IRQ 1472 * routing table 1473 */ 1474 if (io_apic_assign_pci_irqs) { 1475 kfree(rtable); 1476 pirq_table = NULL; 1477 } 1478 } 1479 1480 x86_init.pci.fixup_irqs(); 1481 1482 if (io_apic_assign_pci_irqs && pci_routeirq) { 1483 struct pci_dev *dev = NULL; 1484 /* 1485 * PCI IRQ routing is set up by pci_enable_device(), but we 1486 * also do it here in case there are still broken drivers that 1487 * don't use pci_enable_device(). 1488 */ 1489 printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n"); 1490 for_each_pci_dev(dev) 1491 pirq_enable_irq(dev); 1492 } 1493 } 1494 1495 static void pirq_penalize_isa_irq(int irq, int active) 1496 { 1497 /* 1498 * If any ISAPnP device reports an IRQ in its list of possible 1499 * IRQ's, we try to avoid assigning it to PCI devices. 1500 */ 1501 if (irq < 16) { 1502 if (active) 1503 pirq_penalty[irq] += 1000; 1504 else 1505 pirq_penalty[irq] += 100; 1506 } 1507 } 1508 1509 void pcibios_penalize_isa_irq(int irq, int active) 1510 { 1511 #ifdef CONFIG_ACPI 1512 if (!acpi_noirq) 1513 acpi_penalize_isa_irq(irq, active); 1514 else 1515 #endif 1516 pirq_penalize_isa_irq(irq, active); 1517 } 1518 1519 static int pirq_enable_irq(struct pci_dev *dev) 1520 { 1521 u8 pin = 0; 1522 1523 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1524 if (pin && !pcibios_lookup_irq(dev, 1)) { 1525 char *msg = ""; 1526 1527 if (!io_apic_assign_pci_irqs && dev->irq) 1528 return 0; 1529 1530 if (io_apic_assign_pci_irqs) { 1531 #ifdef CONFIG_X86_IO_APIC 1532 struct pci_dev *temp_dev; 1533 int irq; 1534 1535 if (dev->irq_managed && dev->irq > 0) 1536 return 0; 1537 1538 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, 1539 PCI_SLOT(dev->devfn), pin - 1); 1540 /* 1541 * Busses behind bridges are typically not listed in the MP-table. 1542 * In this case we have to look up the IRQ based on the parent bus, 1543 * parent slot, and pin number. The SMP code detects such bridged 1544 * busses itself so we should get into this branch reliably. 1545 */ 1546 temp_dev = dev; 1547 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */ 1548 struct pci_dev *bridge = dev->bus->self; 1549 1550 pin = pci_swizzle_interrupt_pin(dev, pin); 1551 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, 1552 PCI_SLOT(bridge->devfn), 1553 pin - 1); 1554 if (irq >= 0) 1555 dev_warn(&dev->dev, "using bridge %s " 1556 "INT %c to get IRQ %d\n", 1557 pci_name(bridge), 'A' + pin - 1, 1558 irq); 1559 dev = bridge; 1560 } 1561 dev = temp_dev; 1562 if (irq >= 0) { 1563 dev->irq_managed = 1; 1564 dev->irq = irq; 1565 dev_info(&dev->dev, "PCI->APIC IRQ transform: " 1566 "INT %c -> IRQ %d\n", 'A' + pin - 1, irq); 1567 return 0; 1568 } else 1569 msg = "; probably buggy MP table"; 1570 #endif 1571 } else if (pci_probe & PCI_BIOS_IRQ_SCAN) 1572 msg = ""; 1573 else 1574 msg = "; please try using pci=biosirq"; 1575 1576 /* 1577 * With IDE legacy devices the IRQ lookup failure is not 1578 * a problem.. 1579 */ 1580 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && 1581 !(dev->class & 0x5)) 1582 return 0; 1583 1584 dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n", 1585 'A' + pin - 1, msg); 1586 } 1587 return 0; 1588 } 1589 1590 bool mp_should_keep_irq(struct device *dev) 1591 { 1592 if (dev->power.is_prepared) 1593 return true; 1594 #ifdef CONFIG_PM 1595 if (dev->power.runtime_status == RPM_SUSPENDING) 1596 return true; 1597 #endif 1598 1599 return false; 1600 } 1601 1602 static void pirq_disable_irq(struct pci_dev *dev) 1603 { 1604 if (io_apic_assign_pci_irqs && !mp_should_keep_irq(&dev->dev) && 1605 dev->irq_managed && dev->irq) { 1606 mp_unmap_irq(dev->irq); 1607 dev->irq = 0; 1608 dev->irq_managed = 0; 1609 } 1610 } 1611