1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Low-Level PCI Support for PC -- Routing of Interrupts 4 * 5 * (c) 1999--2000 Martin Mares <mj@ucw.cz> 6 */ 7 8 #include <linux/types.h> 9 #include <linux/kernel.h> 10 #include <linux/pci.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/dmi.h> 14 #include <linux/io.h> 15 #include <linux/smp.h> 16 #include <linux/spinlock.h> 17 #include <asm/io_apic.h> 18 #include <linux/irq.h> 19 #include <linux/acpi.h> 20 21 #include <asm/i8259.h> 22 #include <asm/pc-conf-reg.h> 23 #include <asm/pci_x86.h> 24 25 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) 26 #define PIRQ_VERSION 0x0100 27 28 static int broken_hp_bios_irq9; 29 static int acer_tm360_irqrouting; 30 31 static struct irq_routing_table *pirq_table; 32 33 static int pirq_enable_irq(struct pci_dev *dev); 34 static void pirq_disable_irq(struct pci_dev *dev); 35 36 /* 37 * Never use: 0, 1, 2 (timer, keyboard, and cascade) 38 * Avoid using: 13, 14 and 15 (FP error and IDE). 39 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse) 40 */ 41 unsigned int pcibios_irq_mask = 0xfff8; 42 43 static int pirq_penalty[16] = { 44 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000, 45 0, 0, 0, 0, 1000, 100000, 100000, 100000 46 }; 47 48 struct irq_router { 49 char *name; 50 u16 vendor, device; 51 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq); 52 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, 53 int new); 54 int (*lvl)(struct pci_dev *router, struct pci_dev *dev, int pirq, 55 int irq); 56 }; 57 58 struct irq_router_handler { 59 u16 vendor; 60 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device); 61 }; 62 63 int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq; 64 void (*pcibios_disable_irq)(struct pci_dev *dev) = pirq_disable_irq; 65 66 /* 67 * Check passed address for the PCI IRQ Routing Table signature 68 * and perform checksum verification. 69 */ 70 71 static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr) 72 { 73 struct irq_routing_table *rt; 74 int i; 75 u8 sum; 76 77 rt = (struct irq_routing_table *) addr; 78 if (rt->signature != PIRQ_SIGNATURE || 79 rt->version != PIRQ_VERSION || 80 rt->size % 16 || 81 rt->size < sizeof(struct irq_routing_table)) 82 return NULL; 83 sum = 0; 84 for (i = 0; i < rt->size; i++) 85 sum += addr[i]; 86 if (!sum) { 87 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n", 88 rt); 89 return rt; 90 } 91 return NULL; 92 } 93 94 95 96 /* 97 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table. 98 */ 99 100 static struct irq_routing_table * __init pirq_find_routing_table(void) 101 { 102 u8 *addr; 103 struct irq_routing_table *rt; 104 105 if (pirq_table_addr) { 106 rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr)); 107 if (rt) 108 return rt; 109 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n"); 110 } 111 for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) { 112 rt = pirq_check_routing_table(addr); 113 if (rt) 114 return rt; 115 } 116 return NULL; 117 } 118 119 /* 120 * If we have a IRQ routing table, use it to search for peer host 121 * bridges. It's a gross hack, but since there are no other known 122 * ways how to get a list of buses, we have to go this way. 123 */ 124 125 static void __init pirq_peer_trick(void) 126 { 127 struct irq_routing_table *rt = pirq_table; 128 u8 busmap[256]; 129 int i; 130 struct irq_info *e; 131 132 memset(busmap, 0, sizeof(busmap)); 133 for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) { 134 e = &rt->slots[i]; 135 #ifdef DEBUG 136 { 137 int j; 138 DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot); 139 for (j = 0; j < 4; j++) 140 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap); 141 DBG("\n"); 142 } 143 #endif 144 busmap[e->bus] = 1; 145 } 146 for (i = 1; i < 256; i++) { 147 if (!busmap[i] || pci_find_bus(0, i)) 148 continue; 149 pcibios_scan_root(i); 150 } 151 pcibios_last_bus = -1; 152 } 153 154 /* 155 * Code for querying and setting of IRQ routes on various interrupt routers. 156 * PIC Edge/Level Control Registers (ELCR) 0x4d0 & 0x4d1. 157 */ 158 159 void elcr_set_level_irq(unsigned int irq) 160 { 161 unsigned char mask = 1 << (irq & 7); 162 unsigned int port = PIC_ELCR1 + (irq >> 3); 163 unsigned char val; 164 static u16 elcr_irq_mask; 165 166 if (irq >= 16 || (1 << irq) & elcr_irq_mask) 167 return; 168 169 elcr_irq_mask |= (1 << irq); 170 printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq); 171 val = inb(port); 172 if (!(val & mask)) { 173 DBG(KERN_DEBUG " -> edge"); 174 outb(val | mask, port); 175 } 176 } 177 178 /* 179 * PIRQ routing for the M1487 ISA Bus Controller (IBC) ASIC used 180 * with the ALi FinALi 486 chipset. The IBC is not decoded in the 181 * PCI configuration space, so we identify it by the accompanying 182 * M1489 Cache-Memory PCI Controller (CMP) ASIC. 183 * 184 * There are four 4-bit mappings provided, spread across two PCI 185 * INTx Routing Table Mapping Registers, available in the port I/O 186 * space accessible indirectly via the index/data register pair at 187 * 0x22/0x23, located at indices 0x42 and 0x43 for the INT1/INT2 188 * and INT3/INT4 lines respectively. The INT1/INT3 and INT2/INT4 189 * lines are mapped in the low and the high 4-bit nibble of the 190 * corresponding register as follows: 191 * 192 * 0000 : Disabled 193 * 0001 : IRQ9 194 * 0010 : IRQ3 195 * 0011 : IRQ10 196 * 0100 : IRQ4 197 * 0101 : IRQ5 198 * 0110 : IRQ7 199 * 0111 : IRQ6 200 * 1000 : Reserved 201 * 1001 : IRQ11 202 * 1010 : Reserved 203 * 1011 : IRQ12 204 * 1100 : Reserved 205 * 1101 : IRQ14 206 * 1110 : Reserved 207 * 1111 : IRQ15 208 * 209 * In addition to the usual ELCR register pair there is a separate 210 * PCI INTx Sensitivity Register at index 0x44 in the same port I/O 211 * space, whose bits 3:0 select the trigger mode for INT[4:1] lines 212 * respectively. Any bit set to 1 causes interrupts coming on the 213 * corresponding line to be passed to ISA as edge-triggered and 214 * otherwise they are passed as level-triggered. Manufacturer's 215 * documentation says this register has to be set consistently with 216 * the relevant ELCR register. 217 * 218 * Accesses to the port I/O space concerned here need to be unlocked 219 * by writing the value of 0xc5 to the Lock Register at index 0x03 220 * beforehand. Any other value written to said register prevents 221 * further accesses from reaching the register file, except for the 222 * Lock Register being written with 0xc5 again. 223 * 224 * References: 225 * 226 * "M1489/M1487: 486 PCI Chip Set", Version 1.2, Acer Laboratories 227 * Inc., July 1997 228 */ 229 230 #define PC_CONF_FINALI_LOCK 0x03u 231 #define PC_CONF_FINALI_PCI_INTX_RT1 0x42u 232 #define PC_CONF_FINALI_PCI_INTX_RT2 0x43u 233 #define PC_CONF_FINALI_PCI_INTX_SENS 0x44u 234 235 #define PC_CONF_FINALI_LOCK_KEY 0xc5u 236 237 static u8 read_pc_conf_nybble(u8 base, u8 index) 238 { 239 u8 reg = base + (index >> 1); 240 u8 x; 241 242 x = pc_conf_get(reg); 243 return index & 1 ? x >> 4 : x & 0xf; 244 } 245 246 static void write_pc_conf_nybble(u8 base, u8 index, u8 val) 247 { 248 u8 reg = base + (index >> 1); 249 u8 x; 250 251 x = pc_conf_get(reg); 252 x = index & 1 ? (x & 0x0f) | (val << 4) : (x & 0xf0) | val; 253 pc_conf_set(reg, x); 254 } 255 256 /* 257 * FinALi pirq rules are as follows: 258 * 259 * - bit 0 selects between INTx Routing Table Mapping Registers, 260 * 261 * - bit 3 selects the nibble within the INTx Routing Table Mapping Register, 262 * 263 * - bits 7:4 map to bits 3:0 of the PCI INTx Sensitivity Register. 264 */ 265 static int pirq_finali_get(struct pci_dev *router, struct pci_dev *dev, 266 int pirq) 267 { 268 static const u8 irqmap[16] = { 269 0, 9, 3, 10, 4, 5, 7, 6, 0, 11, 0, 12, 0, 14, 0, 15 270 }; 271 unsigned long flags; 272 u8 index; 273 u8 x; 274 275 index = (pirq & 1) << 1 | (pirq & 8) >> 3; 276 raw_spin_lock_irqsave(&pc_conf_lock, flags); 277 pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY); 278 x = irqmap[read_pc_conf_nybble(PC_CONF_FINALI_PCI_INTX_RT1, index)]; 279 pc_conf_set(PC_CONF_FINALI_LOCK, 0); 280 raw_spin_unlock_irqrestore(&pc_conf_lock, flags); 281 return x; 282 } 283 284 static int pirq_finali_set(struct pci_dev *router, struct pci_dev *dev, 285 int pirq, int irq) 286 { 287 static const u8 irqmap[16] = { 288 0, 0, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 289 }; 290 u8 val = irqmap[irq]; 291 unsigned long flags; 292 u8 index; 293 294 if (!val) 295 return 0; 296 297 index = (pirq & 1) << 1 | (pirq & 8) >> 3; 298 raw_spin_lock_irqsave(&pc_conf_lock, flags); 299 pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY); 300 write_pc_conf_nybble(PC_CONF_FINALI_PCI_INTX_RT1, index, val); 301 pc_conf_set(PC_CONF_FINALI_LOCK, 0); 302 raw_spin_unlock_irqrestore(&pc_conf_lock, flags); 303 return 1; 304 } 305 306 static int pirq_finali_lvl(struct pci_dev *router, struct pci_dev *dev, 307 int pirq, int irq) 308 { 309 u8 mask = ~((pirq & 0xf0u) >> 4); 310 unsigned long flags; 311 u8 trig; 312 313 elcr_set_level_irq(irq); 314 raw_spin_lock_irqsave(&pc_conf_lock, flags); 315 pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY); 316 trig = pc_conf_get(PC_CONF_FINALI_PCI_INTX_SENS); 317 trig &= mask; 318 pc_conf_set(PC_CONF_FINALI_PCI_INTX_SENS, trig); 319 pc_conf_set(PC_CONF_FINALI_LOCK, 0); 320 raw_spin_unlock_irqrestore(&pc_conf_lock, flags); 321 return 1; 322 } 323 324 /* 325 * Common IRQ routing practice: nibbles in config space, 326 * offset by some magic constant. 327 */ 328 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr) 329 { 330 u8 x; 331 unsigned reg = offset + (nr >> 1); 332 333 pci_read_config_byte(router, reg, &x); 334 return (nr & 1) ? (x >> 4) : (x & 0xf); 335 } 336 337 static void write_config_nybble(struct pci_dev *router, unsigned offset, 338 unsigned nr, unsigned int val) 339 { 340 u8 x; 341 unsigned reg = offset + (nr >> 1); 342 343 pci_read_config_byte(router, reg, &x); 344 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val); 345 pci_write_config_byte(router, reg, x); 346 } 347 348 /* 349 * ALI pirq entries are damn ugly, and completely undocumented. 350 * This has been figured out from pirq tables, and it's not a pretty 351 * picture. 352 */ 353 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 354 { 355 static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 }; 356 357 WARN_ON_ONCE(pirq > 16); 358 return irqmap[read_config_nybble(router, 0x48, pirq-1)]; 359 } 360 361 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 362 { 363 static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 }; 364 unsigned int val = irqmap[irq]; 365 366 WARN_ON_ONCE(pirq > 16); 367 if (val) { 368 write_config_nybble(router, 0x48, pirq-1, val); 369 return 1; 370 } 371 return 0; 372 } 373 374 /* 375 * PIRQ routing for the 82374EB/82374SB EISA System Component (ESC) 376 * ASIC used with the Intel 82420 and 82430 PCIsets. The ESC is not 377 * decoded in the PCI configuration space, so we identify it by the 378 * accompanying 82375EB/82375SB PCI-EISA Bridge (PCEB) ASIC. 379 * 380 * There are four PIRQ Route Control registers, available in the 381 * port I/O space accessible indirectly via the index/data register 382 * pair at 0x22/0x23, located at indices 0x60/0x61/0x62/0x63 for the 383 * PIRQ0/1/2/3# lines respectively. The semantics is the same as 384 * with the PIIX router. 385 * 386 * Accesses to the port I/O space concerned here need to be unlocked 387 * by writing the value of 0x0f to the ESC ID Register at index 0x02 388 * beforehand. Any other value written to said register prevents 389 * further accesses from reaching the register file, except for the 390 * ESC ID Register being written with 0x0f again. 391 * 392 * References: 393 * 394 * "82374EB/82374SB EISA System Component (ESC)", Intel Corporation, 395 * Order Number: 290476-004, March 1996 396 * 397 * "82375EB/82375SB PCI-EISA Bridge (PCEB)", Intel Corporation, Order 398 * Number: 290477-004, March 1996 399 */ 400 401 #define PC_CONF_I82374_ESC_ID 0x02u 402 #define PC_CONF_I82374_PIRQ_ROUTE_CONTROL 0x60u 403 404 #define PC_CONF_I82374_ESC_ID_KEY 0x0fu 405 406 static int pirq_esc_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 407 { 408 unsigned long flags; 409 int reg; 410 u8 x; 411 412 reg = pirq; 413 if (reg >= 1 && reg <= 4) 414 reg += PC_CONF_I82374_PIRQ_ROUTE_CONTROL - 1; 415 416 raw_spin_lock_irqsave(&pc_conf_lock, flags); 417 pc_conf_set(PC_CONF_I82374_ESC_ID, PC_CONF_I82374_ESC_ID_KEY); 418 x = pc_conf_get(reg); 419 pc_conf_set(PC_CONF_I82374_ESC_ID, 0); 420 raw_spin_unlock_irqrestore(&pc_conf_lock, flags); 421 return (x < 16) ? x : 0; 422 } 423 424 static int pirq_esc_set(struct pci_dev *router, struct pci_dev *dev, int pirq, 425 int irq) 426 { 427 unsigned long flags; 428 int reg; 429 430 reg = pirq; 431 if (reg >= 1 && reg <= 4) 432 reg += PC_CONF_I82374_PIRQ_ROUTE_CONTROL - 1; 433 434 raw_spin_lock_irqsave(&pc_conf_lock, flags); 435 pc_conf_set(PC_CONF_I82374_ESC_ID, PC_CONF_I82374_ESC_ID_KEY); 436 pc_conf_set(reg, irq); 437 pc_conf_set(PC_CONF_I82374_ESC_ID, 0); 438 raw_spin_unlock_irqrestore(&pc_conf_lock, flags); 439 return 1; 440 } 441 442 /* 443 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is 444 * just a pointer to the config space. 445 */ 446 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 447 { 448 u8 x; 449 450 pci_read_config_byte(router, pirq, &x); 451 return (x < 16) ? x : 0; 452 } 453 454 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 455 { 456 pci_write_config_byte(router, pirq, irq); 457 return 1; 458 } 459 460 /* 461 * PIRQ routing for the 82426EX ISA Bridge (IB) ASIC used with the 462 * Intel 82420EX PCIset. 463 * 464 * There are only two PIRQ Route Control registers, available in the 465 * combined 82425EX/82426EX PCI configuration space, at 0x66 and 0x67 466 * for the PIRQ0# and PIRQ1# lines respectively. The semantics is 467 * the same as with the PIIX router. 468 * 469 * References: 470 * 471 * "82420EX PCIset Data Sheet, 82425EX PCI System Controller (PSC) 472 * and 82426EX ISA Bridge (IB)", Intel Corporation, Order Number: 473 * 290488-004, December 1995 474 */ 475 476 #define PCI_I82426EX_PIRQ_ROUTE_CONTROL 0x66u 477 478 static int pirq_ib_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 479 { 480 int reg; 481 u8 x; 482 483 reg = pirq; 484 if (reg >= 1 && reg <= 2) 485 reg += PCI_I82426EX_PIRQ_ROUTE_CONTROL - 1; 486 487 pci_read_config_byte(router, reg, &x); 488 return (x < 16) ? x : 0; 489 } 490 491 static int pirq_ib_set(struct pci_dev *router, struct pci_dev *dev, int pirq, 492 int irq) 493 { 494 int reg; 495 496 reg = pirq; 497 if (reg >= 1 && reg <= 2) 498 reg += PCI_I82426EX_PIRQ_ROUTE_CONTROL - 1; 499 500 pci_write_config_byte(router, reg, irq); 501 return 1; 502 } 503 504 /* 505 * The VIA pirq rules are nibble-based, like ALI, 506 * but without the ugly irq number munging. 507 * However, PIRQD is in the upper instead of lower 4 bits. 508 */ 509 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 510 { 511 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq); 512 } 513 514 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 515 { 516 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq); 517 return 1; 518 } 519 520 /* 521 * The VIA pirq rules are nibble-based, like ALI, 522 * but without the ugly irq number munging. 523 * However, for 82C586, nibble map is different . 524 */ 525 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 526 { 527 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 528 529 WARN_ON_ONCE(pirq > 5); 530 return read_config_nybble(router, 0x55, pirqmap[pirq-1]); 531 } 532 533 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 534 { 535 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 536 537 WARN_ON_ONCE(pirq > 5); 538 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq); 539 return 1; 540 } 541 542 /* 543 * ITE 8330G pirq rules are nibble-based 544 * FIXME: pirqmap may be { 1, 0, 3, 2 }, 545 * 2+3 are both mapped to irq 9 on my system 546 */ 547 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 548 { 549 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 550 551 WARN_ON_ONCE(pirq > 4); 552 return read_config_nybble(router, 0x43, pirqmap[pirq-1]); 553 } 554 555 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 556 { 557 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 558 559 WARN_ON_ONCE(pirq > 4); 560 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq); 561 return 1; 562 } 563 564 /* 565 * OPTI: high four bits are nibble pointer.. 566 * I wonder what the low bits do? 567 */ 568 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 569 { 570 return read_config_nybble(router, 0xb8, pirq >> 4); 571 } 572 573 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 574 { 575 write_config_nybble(router, 0xb8, pirq >> 4, irq); 576 return 1; 577 } 578 579 /* 580 * Cyrix: nibble offset 0x5C 581 * 0x5C bits 7:4 is INTB bits 3:0 is INTA 582 * 0x5D bits 7:4 is INTD bits 3:0 is INTC 583 */ 584 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 585 { 586 return read_config_nybble(router, 0x5C, (pirq-1)^1); 587 } 588 589 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 590 { 591 write_config_nybble(router, 0x5C, (pirq-1)^1, irq); 592 return 1; 593 } 594 595 /* 596 * PIRQ routing for SiS 85C503 router used in several SiS chipsets. 597 * We have to deal with the following issues here: 598 * - vendors have different ideas about the meaning of link values 599 * - some onboard devices (integrated in the chipset) have special 600 * links and are thus routed differently (i.e. not via PCI INTA-INTD) 601 * - different revision of the router have a different layout for 602 * the routing registers, particularly for the onchip devices 603 * 604 * For all routing registers the common thing is we have one byte 605 * per routeable link which is defined as: 606 * bit 7 IRQ mapping enabled (0) or disabled (1) 607 * bits [6:4] reserved (sometimes used for onchip devices) 608 * bits [3:0] IRQ to map to 609 * allowed: 3-7, 9-12, 14-15 610 * reserved: 0, 1, 2, 8, 13 611 * 612 * The config-space registers located at 0x41/0x42/0x43/0x44 are 613 * always used to route the normal PCI INT A/B/C/D respectively. 614 * Apparently there are systems implementing PCI routing table using 615 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D. 616 * We try our best to handle both link mappings. 617 * 618 * Currently (2003-05-21) it appears most SiS chipsets follow the 619 * definition of routing registers from the SiS-5595 southbridge. 620 * According to the SiS 5595 datasheets the revision id's of the 621 * router (ISA-bridge) should be 0x01 or 0xb0. 622 * 623 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1. 624 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets. 625 * They seem to work with the current routing code. However there is 626 * some concern because of the two USB-OHCI HCs (original SiS 5595 627 * had only one). YMMV. 628 * 629 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1: 630 * 631 * 0x61: IDEIRQ: 632 * bits [6:5] must be written 01 633 * bit 4 channel-select primary (0), secondary (1) 634 * 635 * 0x62: USBIRQ: 636 * bit 6 OHCI function disabled (0), enabled (1) 637 * 638 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved 639 * 640 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved 641 * 642 * We support USBIRQ (in addition to INTA-INTD) and keep the 643 * IDE, ACPI and DAQ routing untouched as set by the BIOS. 644 * 645 * Currently the only reported exception is the new SiS 65x chipset 646 * which includes the SiS 69x southbridge. Here we have the 85C503 647 * router revision 0x04 and there are changes in the register layout 648 * mostly related to the different USB HCs with USB 2.0 support. 649 * 650 * Onchip routing for router rev-id 0x04 (try-and-error observation) 651 * 652 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs 653 * bit 6-4 are probably unused, not like 5595 654 */ 655 656 #define PIRQ_SIS_IRQ_MASK 0x0f 657 #define PIRQ_SIS_IRQ_DISABLE 0x80 658 #define PIRQ_SIS_USB_ENABLE 0x40 659 660 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 661 { 662 u8 x; 663 int reg; 664 665 reg = pirq; 666 if (reg >= 0x01 && reg <= 0x04) 667 reg += 0x40; 668 pci_read_config_byte(router, reg, &x); 669 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK); 670 } 671 672 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 673 { 674 u8 x; 675 int reg; 676 677 reg = pirq; 678 if (reg >= 0x01 && reg <= 0x04) 679 reg += 0x40; 680 pci_read_config_byte(router, reg, &x); 681 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE); 682 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE; 683 pci_write_config_byte(router, reg, x); 684 return 1; 685 } 686 687 688 /* 689 * VLSI: nibble offset 0x74 - educated guess due to routing table and 690 * config space of VLSI 82C534 PCI-bridge/router (1004:0102) 691 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard 692 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6 693 * for the busbridge to the docking station. 694 */ 695 696 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 697 { 698 WARN_ON_ONCE(pirq >= 9); 699 if (pirq > 8) { 700 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq); 701 return 0; 702 } 703 return read_config_nybble(router, 0x74, pirq-1); 704 } 705 706 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 707 { 708 WARN_ON_ONCE(pirq >= 9); 709 if (pirq > 8) { 710 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq); 711 return 0; 712 } 713 write_config_nybble(router, 0x74, pirq-1, irq); 714 return 1; 715 } 716 717 /* 718 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index 719 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register 720 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect 721 * register is a straight binary coding of desired PIC IRQ (low nibble). 722 * 723 * The 'link' value in the PIRQ table is already in the correct format 724 * for the Index register. There are some special index values: 725 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1, 726 * and 0x03 for SMBus. 727 */ 728 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 729 { 730 outb(pirq, 0xc00); 731 return inb(0xc01) & 0xf; 732 } 733 734 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, 735 int pirq, int irq) 736 { 737 outb(pirq, 0xc00); 738 outb(irq, 0xc01); 739 return 1; 740 } 741 742 /* Support for AMD756 PCI IRQ Routing 743 * Jhon H. Caicedo <jhcaiced@osso.org.co> 744 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced) 745 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced) 746 * The AMD756 pirq rules are nibble-based 747 * offset 0x56 0-3 PIRQA 4-7 PIRQB 748 * offset 0x57 0-3 PIRQC 4-7 PIRQD 749 */ 750 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 751 { 752 u8 irq; 753 irq = 0; 754 if (pirq <= 4) 755 irq = read_config_nybble(router, 0x56, pirq - 1); 756 dev_info(&dev->dev, 757 "AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d\n", 758 dev->vendor, dev->device, pirq, irq); 759 return irq; 760 } 761 762 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 763 { 764 dev_info(&dev->dev, 765 "AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d\n", 766 dev->vendor, dev->device, pirq, irq); 767 if (pirq <= 4) 768 write_config_nybble(router, 0x56, pirq - 1, irq); 769 return 1; 770 } 771 772 /* 773 * PicoPower PT86C523 774 */ 775 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 776 { 777 outb(0x10 + ((pirq - 1) >> 1), 0x24); 778 return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf); 779 } 780 781 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq, 782 int irq) 783 { 784 unsigned int x; 785 outb(0x10 + ((pirq - 1) >> 1), 0x24); 786 x = inb(0x26); 787 x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq)); 788 outb(x, 0x26); 789 return 1; 790 } 791 792 #ifdef CONFIG_PCI_BIOS 793 794 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 795 { 796 struct pci_dev *bridge; 797 int pin = pci_get_interrupt_pin(dev, &bridge); 798 return pcibios_set_irq_routing(bridge, pin - 1, irq); 799 } 800 801 #endif 802 803 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 804 { 805 static struct pci_device_id __initdata pirq_440gx[] = { 806 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) }, 807 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) }, 808 { }, 809 }; 810 811 /* 440GX has a proprietary PIRQ router -- don't use it */ 812 if (pci_dev_present(pirq_440gx)) 813 return 0; 814 815 switch (device) { 816 case PCI_DEVICE_ID_INTEL_82375: 817 r->name = "PCEB/ESC"; 818 r->get = pirq_esc_get; 819 r->set = pirq_esc_set; 820 return 1; 821 case PCI_DEVICE_ID_INTEL_82371FB_0: 822 case PCI_DEVICE_ID_INTEL_82371SB_0: 823 case PCI_DEVICE_ID_INTEL_82371AB_0: 824 case PCI_DEVICE_ID_INTEL_82371MX: 825 case PCI_DEVICE_ID_INTEL_82443MX_0: 826 case PCI_DEVICE_ID_INTEL_82801AA_0: 827 case PCI_DEVICE_ID_INTEL_82801AB_0: 828 case PCI_DEVICE_ID_INTEL_82801BA_0: 829 case PCI_DEVICE_ID_INTEL_82801BA_10: 830 case PCI_DEVICE_ID_INTEL_82801CA_0: 831 case PCI_DEVICE_ID_INTEL_82801CA_12: 832 case PCI_DEVICE_ID_INTEL_82801DB_0: 833 case PCI_DEVICE_ID_INTEL_82801E_0: 834 case PCI_DEVICE_ID_INTEL_82801EB_0: 835 case PCI_DEVICE_ID_INTEL_ESB_1: 836 case PCI_DEVICE_ID_INTEL_ICH6_0: 837 case PCI_DEVICE_ID_INTEL_ICH6_1: 838 case PCI_DEVICE_ID_INTEL_ICH7_0: 839 case PCI_DEVICE_ID_INTEL_ICH7_1: 840 case PCI_DEVICE_ID_INTEL_ICH7_30: 841 case PCI_DEVICE_ID_INTEL_ICH7_31: 842 case PCI_DEVICE_ID_INTEL_TGP_LPC: 843 case PCI_DEVICE_ID_INTEL_ESB2_0: 844 case PCI_DEVICE_ID_INTEL_ICH8_0: 845 case PCI_DEVICE_ID_INTEL_ICH8_1: 846 case PCI_DEVICE_ID_INTEL_ICH8_2: 847 case PCI_DEVICE_ID_INTEL_ICH8_3: 848 case PCI_DEVICE_ID_INTEL_ICH8_4: 849 case PCI_DEVICE_ID_INTEL_ICH9_0: 850 case PCI_DEVICE_ID_INTEL_ICH9_1: 851 case PCI_DEVICE_ID_INTEL_ICH9_2: 852 case PCI_DEVICE_ID_INTEL_ICH9_3: 853 case PCI_DEVICE_ID_INTEL_ICH9_4: 854 case PCI_DEVICE_ID_INTEL_ICH9_5: 855 case PCI_DEVICE_ID_INTEL_EP80579_0: 856 case PCI_DEVICE_ID_INTEL_ICH10_0: 857 case PCI_DEVICE_ID_INTEL_ICH10_1: 858 case PCI_DEVICE_ID_INTEL_ICH10_2: 859 case PCI_DEVICE_ID_INTEL_ICH10_3: 860 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0: 861 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1: 862 r->name = "PIIX/ICH"; 863 r->get = pirq_piix_get; 864 r->set = pirq_piix_set; 865 return 1; 866 case PCI_DEVICE_ID_INTEL_82425: 867 r->name = "PSC/IB"; 868 r->get = pirq_ib_get; 869 r->set = pirq_ib_set; 870 return 1; 871 } 872 873 if ((device >= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN && 874 device <= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX) 875 || (device >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && 876 device <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) 877 || (device >= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN && 878 device <= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX) 879 || (device >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && 880 device <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) { 881 r->name = "PIIX/ICH"; 882 r->get = pirq_piix_get; 883 r->set = pirq_piix_set; 884 return 1; 885 } 886 887 return 0; 888 } 889 890 static __init int via_router_probe(struct irq_router *r, 891 struct pci_dev *router, u16 device) 892 { 893 /* FIXME: We should move some of the quirk fixup stuff here */ 894 895 /* 896 * workarounds for some buggy BIOSes 897 */ 898 if (device == PCI_DEVICE_ID_VIA_82C586_0) { 899 switch (router->device) { 900 case PCI_DEVICE_ID_VIA_82C686: 901 /* 902 * Asus k7m bios wrongly reports 82C686A 903 * as 586-compatible 904 */ 905 device = PCI_DEVICE_ID_VIA_82C686; 906 break; 907 case PCI_DEVICE_ID_VIA_8235: 908 /** 909 * Asus a7v-x bios wrongly reports 8235 910 * as 586-compatible 911 */ 912 device = PCI_DEVICE_ID_VIA_8235; 913 break; 914 case PCI_DEVICE_ID_VIA_8237: 915 /** 916 * Asus a7v600 bios wrongly reports 8237 917 * as 586-compatible 918 */ 919 device = PCI_DEVICE_ID_VIA_8237; 920 break; 921 } 922 } 923 924 switch (device) { 925 case PCI_DEVICE_ID_VIA_82C586_0: 926 r->name = "VIA"; 927 r->get = pirq_via586_get; 928 r->set = pirq_via586_set; 929 return 1; 930 case PCI_DEVICE_ID_VIA_82C596: 931 case PCI_DEVICE_ID_VIA_82C686: 932 case PCI_DEVICE_ID_VIA_8231: 933 case PCI_DEVICE_ID_VIA_8233A: 934 case PCI_DEVICE_ID_VIA_8235: 935 case PCI_DEVICE_ID_VIA_8237: 936 /* FIXME: add new ones for 8233/5 */ 937 r->name = "VIA"; 938 r->get = pirq_via_get; 939 r->set = pirq_via_set; 940 return 1; 941 } 942 return 0; 943 } 944 945 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 946 { 947 switch (device) { 948 case PCI_DEVICE_ID_VLSI_82C534: 949 r->name = "VLSI 82C534"; 950 r->get = pirq_vlsi_get; 951 r->set = pirq_vlsi_set; 952 return 1; 953 } 954 return 0; 955 } 956 957 958 static __init int serverworks_router_probe(struct irq_router *r, 959 struct pci_dev *router, u16 device) 960 { 961 switch (device) { 962 case PCI_DEVICE_ID_SERVERWORKS_OSB4: 963 case PCI_DEVICE_ID_SERVERWORKS_CSB5: 964 r->name = "ServerWorks"; 965 r->get = pirq_serverworks_get; 966 r->set = pirq_serverworks_set; 967 return 1; 968 } 969 return 0; 970 } 971 972 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 973 { 974 if (device != PCI_DEVICE_ID_SI_503) 975 return 0; 976 977 r->name = "SIS"; 978 r->get = pirq_sis_get; 979 r->set = pirq_sis_set; 980 return 1; 981 } 982 983 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 984 { 985 switch (device) { 986 case PCI_DEVICE_ID_CYRIX_5520: 987 r->name = "NatSemi"; 988 r->get = pirq_cyrix_get; 989 r->set = pirq_cyrix_set; 990 return 1; 991 } 992 return 0; 993 } 994 995 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 996 { 997 switch (device) { 998 case PCI_DEVICE_ID_OPTI_82C700: 999 r->name = "OPTI"; 1000 r->get = pirq_opti_get; 1001 r->set = pirq_opti_set; 1002 return 1; 1003 } 1004 return 0; 1005 } 1006 1007 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 1008 { 1009 switch (device) { 1010 case PCI_DEVICE_ID_ITE_IT8330G_0: 1011 r->name = "ITE"; 1012 r->get = pirq_ite_get; 1013 r->set = pirq_ite_set; 1014 return 1; 1015 } 1016 return 0; 1017 } 1018 1019 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 1020 { 1021 switch (device) { 1022 case PCI_DEVICE_ID_AL_M1489: 1023 r->name = "FinALi"; 1024 r->get = pirq_finali_get; 1025 r->set = pirq_finali_set; 1026 r->lvl = pirq_finali_lvl; 1027 return 1; 1028 case PCI_DEVICE_ID_AL_M1533: 1029 case PCI_DEVICE_ID_AL_M1563: 1030 r->name = "ALI"; 1031 r->get = pirq_ali_get; 1032 r->set = pirq_ali_set; 1033 return 1; 1034 } 1035 return 0; 1036 } 1037 1038 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 1039 { 1040 switch (device) { 1041 case PCI_DEVICE_ID_AMD_VIPER_740B: 1042 r->name = "AMD756"; 1043 break; 1044 case PCI_DEVICE_ID_AMD_VIPER_7413: 1045 r->name = "AMD766"; 1046 break; 1047 case PCI_DEVICE_ID_AMD_VIPER_7443: 1048 r->name = "AMD768"; 1049 break; 1050 default: 1051 return 0; 1052 } 1053 r->get = pirq_amd756_get; 1054 r->set = pirq_amd756_set; 1055 return 1; 1056 } 1057 1058 static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 1059 { 1060 switch (device) { 1061 case PCI_DEVICE_ID_PICOPOWER_PT86C523: 1062 r->name = "PicoPower PT86C523"; 1063 r->get = pirq_pico_get; 1064 r->set = pirq_pico_set; 1065 return 1; 1066 1067 case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP: 1068 r->name = "PicoPower PT86C523 rev. BB+"; 1069 r->get = pirq_pico_get; 1070 r->set = pirq_pico_set; 1071 return 1; 1072 } 1073 return 0; 1074 } 1075 1076 static __initdata struct irq_router_handler pirq_routers[] = { 1077 { PCI_VENDOR_ID_INTEL, intel_router_probe }, 1078 { PCI_VENDOR_ID_AL, ali_router_probe }, 1079 { PCI_VENDOR_ID_ITE, ite_router_probe }, 1080 { PCI_VENDOR_ID_VIA, via_router_probe }, 1081 { PCI_VENDOR_ID_OPTI, opti_router_probe }, 1082 { PCI_VENDOR_ID_SI, sis_router_probe }, 1083 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe }, 1084 { PCI_VENDOR_ID_VLSI, vlsi_router_probe }, 1085 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe }, 1086 { PCI_VENDOR_ID_AMD, amd_router_probe }, 1087 { PCI_VENDOR_ID_PICOPOWER, pico_router_probe }, 1088 /* Someone with docs needs to add the ATI Radeon IGP */ 1089 { 0, NULL } 1090 }; 1091 static struct irq_router pirq_router; 1092 static struct pci_dev *pirq_router_dev; 1093 1094 1095 /* 1096 * FIXME: should we have an option to say "generic for 1097 * chipset" ? 1098 */ 1099 1100 static void __init pirq_find_router(struct irq_router *r) 1101 { 1102 struct irq_routing_table *rt = pirq_table; 1103 struct irq_router_handler *h; 1104 1105 #ifdef CONFIG_PCI_BIOS 1106 if (!rt->signature) { 1107 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n"); 1108 r->set = pirq_bios_set; 1109 r->name = "BIOS"; 1110 return; 1111 } 1112 #endif 1113 1114 /* Default unless a driver reloads it */ 1115 r->name = "default"; 1116 r->get = NULL; 1117 r->set = NULL; 1118 1119 DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n", 1120 rt->rtr_vendor, rt->rtr_device); 1121 1122 pirq_router_dev = pci_get_domain_bus_and_slot(0, rt->rtr_bus, 1123 rt->rtr_devfn); 1124 if (!pirq_router_dev) { 1125 DBG(KERN_DEBUG "PCI: Interrupt router not found at " 1126 "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn); 1127 return; 1128 } 1129 1130 for (h = pirq_routers; h->vendor; h++) { 1131 /* First look for a router match */ 1132 if (rt->rtr_vendor == h->vendor && 1133 h->probe(r, pirq_router_dev, rt->rtr_device)) 1134 break; 1135 /* Fall back to a device match */ 1136 if (pirq_router_dev->vendor == h->vendor && 1137 h->probe(r, pirq_router_dev, pirq_router_dev->device)) 1138 break; 1139 } 1140 dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x:%04x]\n", 1141 pirq_router.name, 1142 pirq_router_dev->vendor, pirq_router_dev->device); 1143 1144 /* The device remains referenced for the kernel lifetime */ 1145 } 1146 1147 static struct irq_info *pirq_get_info(struct pci_dev *dev) 1148 { 1149 struct irq_routing_table *rt = pirq_table; 1150 int entries = (rt->size - sizeof(struct irq_routing_table)) / 1151 sizeof(struct irq_info); 1152 struct irq_info *info; 1153 1154 for (info = rt->slots; entries--; info++) 1155 if (info->bus == dev->bus->number && 1156 PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn)) 1157 return info; 1158 return NULL; 1159 } 1160 1161 static int pcibios_lookup_irq(struct pci_dev *dev, int assign) 1162 { 1163 u8 pin; 1164 struct irq_info *info; 1165 int i, pirq, newirq; 1166 int irq = 0; 1167 u32 mask; 1168 struct irq_router *r = &pirq_router; 1169 struct pci_dev *dev2 = NULL; 1170 char *msg = NULL; 1171 1172 /* Find IRQ pin */ 1173 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1174 if (!pin) { 1175 dev_dbg(&dev->dev, "no interrupt pin\n"); 1176 return 0; 1177 } 1178 1179 if (io_apic_assign_pci_irqs) 1180 return 0; 1181 1182 /* Find IRQ routing entry */ 1183 1184 if (!pirq_table) 1185 return 0; 1186 1187 info = pirq_get_info(dev); 1188 if (!info) { 1189 dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n", 1190 'A' + pin - 1); 1191 return 0; 1192 } 1193 pirq = info->irq[pin - 1].link; 1194 mask = info->irq[pin - 1].bitmap; 1195 if (!pirq) { 1196 dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin - 1); 1197 return 0; 1198 } 1199 dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x", 1200 'A' + pin - 1, pirq, mask, pirq_table->exclusive_irqs); 1201 mask &= pcibios_irq_mask; 1202 1203 /* Work around broken HP Pavilion Notebooks which assign USB to 1204 IRQ 9 even though it is actually wired to IRQ 11 */ 1205 1206 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) { 1207 dev->irq = 11; 1208 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11); 1209 r->set(pirq_router_dev, dev, pirq, 11); 1210 } 1211 1212 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */ 1213 if (acer_tm360_irqrouting && dev->irq == 11 && 1214 dev->vendor == PCI_VENDOR_ID_O2) { 1215 pirq = 0x68; 1216 mask = 0x400; 1217 dev->irq = r->get(pirq_router_dev, dev, pirq); 1218 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 1219 } 1220 1221 /* 1222 * Find the best IRQ to assign: use the one 1223 * reported by the device if possible. 1224 */ 1225 newirq = dev->irq; 1226 if (newirq && !((1 << newirq) & mask)) { 1227 if (pci_probe & PCI_USE_PIRQ_MASK) 1228 newirq = 0; 1229 else 1230 dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask " 1231 "%#x; try pci=usepirqmask\n", newirq, mask); 1232 } 1233 if (!newirq && assign) { 1234 for (i = 0; i < 16; i++) { 1235 if (!(mask & (1 << i))) 1236 continue; 1237 if (pirq_penalty[i] < pirq_penalty[newirq] && 1238 can_request_irq(i, IRQF_SHARED)) 1239 newirq = i; 1240 } 1241 } 1242 dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + pin - 1, newirq); 1243 1244 /* Check if it is hardcoded */ 1245 if ((pirq & 0xf0) == 0xf0) { 1246 irq = pirq & 0xf; 1247 msg = "hardcoded"; 1248 } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \ 1249 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) { 1250 msg = "found"; 1251 if (r->lvl) 1252 r->lvl(pirq_router_dev, dev, pirq, irq); 1253 else 1254 elcr_set_level_irq(irq); 1255 } else if (newirq && r->set && 1256 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) { 1257 if (r->set(pirq_router_dev, dev, pirq, newirq)) { 1258 if (r->lvl) 1259 r->lvl(pirq_router_dev, dev, pirq, newirq); 1260 else 1261 elcr_set_level_irq(newirq); 1262 msg = "assigned"; 1263 irq = newirq; 1264 } 1265 } 1266 1267 if (!irq) { 1268 if (newirq && mask == (1 << newirq)) { 1269 msg = "guessed"; 1270 irq = newirq; 1271 } else { 1272 dev_dbg(&dev->dev, "can't route interrupt\n"); 1273 return 0; 1274 } 1275 } 1276 dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin - 1, irq); 1277 1278 /* Update IRQ for all devices with the same pirq value */ 1279 for_each_pci_dev(dev2) { 1280 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin); 1281 if (!pin) 1282 continue; 1283 1284 info = pirq_get_info(dev2); 1285 if (!info) 1286 continue; 1287 if (info->irq[pin - 1].link == pirq) { 1288 /* 1289 * We refuse to override the dev->irq 1290 * information. Give a warning! 1291 */ 1292 if (dev2->irq && dev2->irq != irq && \ 1293 (!(pci_probe & PCI_USE_PIRQ_MASK) || \ 1294 ((1 << dev2->irq) & mask))) { 1295 #ifndef CONFIG_PCI_MSI 1296 dev_info(&dev2->dev, "IRQ routing conflict: " 1297 "have IRQ %d, want IRQ %d\n", 1298 dev2->irq, irq); 1299 #endif 1300 continue; 1301 } 1302 dev2->irq = irq; 1303 pirq_penalty[irq]++; 1304 if (dev != dev2) 1305 dev_info(&dev->dev, "sharing IRQ %d with %s\n", 1306 irq, pci_name(dev2)); 1307 } 1308 } 1309 return 1; 1310 } 1311 1312 void __init pcibios_fixup_irqs(void) 1313 { 1314 struct pci_dev *dev = NULL; 1315 u8 pin; 1316 1317 DBG(KERN_DEBUG "PCI: IRQ fixup\n"); 1318 for_each_pci_dev(dev) { 1319 /* 1320 * If the BIOS has set an out of range IRQ number, just 1321 * ignore it. Also keep track of which IRQ's are 1322 * already in use. 1323 */ 1324 if (dev->irq >= 16) { 1325 dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq); 1326 dev->irq = 0; 1327 } 1328 /* 1329 * If the IRQ is already assigned to a PCI device, 1330 * ignore its ISA use penalty 1331 */ 1332 if (pirq_penalty[dev->irq] >= 100 && 1333 pirq_penalty[dev->irq] < 100000) 1334 pirq_penalty[dev->irq] = 0; 1335 pirq_penalty[dev->irq]++; 1336 } 1337 1338 if (io_apic_assign_pci_irqs) 1339 return; 1340 1341 dev = NULL; 1342 for_each_pci_dev(dev) { 1343 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1344 if (!pin) 1345 continue; 1346 1347 /* 1348 * Still no IRQ? Try to lookup one... 1349 */ 1350 if (!dev->irq) 1351 pcibios_lookup_irq(dev, 0); 1352 } 1353 } 1354 1355 /* 1356 * Work around broken HP Pavilion Notebooks which assign USB to 1357 * IRQ 9 even though it is actually wired to IRQ 11 1358 */ 1359 static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d) 1360 { 1361 if (!broken_hp_bios_irq9) { 1362 broken_hp_bios_irq9 = 1; 1363 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", 1364 d->ident); 1365 } 1366 return 0; 1367 } 1368 1369 /* 1370 * Work around broken Acer TravelMate 360 Notebooks which assign 1371 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10 1372 */ 1373 static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d) 1374 { 1375 if (!acer_tm360_irqrouting) { 1376 acer_tm360_irqrouting = 1; 1377 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", 1378 d->ident); 1379 } 1380 return 0; 1381 } 1382 1383 static const struct dmi_system_id pciirq_dmi_table[] __initconst = { 1384 { 1385 .callback = fix_broken_hp_bios_irq9, 1386 .ident = "HP Pavilion N5400 Series Laptop", 1387 .matches = { 1388 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1389 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"), 1390 DMI_MATCH(DMI_PRODUCT_VERSION, 1391 "HP Pavilion Notebook Model GE"), 1392 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"), 1393 }, 1394 }, 1395 { 1396 .callback = fix_acer_tm360_irqrouting, 1397 .ident = "Acer TravelMate 36x Laptop", 1398 .matches = { 1399 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1400 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"), 1401 }, 1402 }, 1403 { } 1404 }; 1405 1406 void __init pcibios_irq_init(void) 1407 { 1408 struct irq_routing_table *rtable = NULL; 1409 1410 DBG(KERN_DEBUG "PCI: IRQ init\n"); 1411 1412 if (raw_pci_ops == NULL) 1413 return; 1414 1415 dmi_check_system(pciirq_dmi_table); 1416 1417 pirq_table = pirq_find_routing_table(); 1418 1419 #ifdef CONFIG_PCI_BIOS 1420 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN)) { 1421 pirq_table = pcibios_get_irq_routing_table(); 1422 rtable = pirq_table; 1423 } 1424 #endif 1425 if (pirq_table) { 1426 pirq_peer_trick(); 1427 pirq_find_router(&pirq_router); 1428 if (pirq_table->exclusive_irqs) { 1429 int i; 1430 for (i = 0; i < 16; i++) 1431 if (!(pirq_table->exclusive_irqs & (1 << i))) 1432 pirq_penalty[i] += 100; 1433 } 1434 /* 1435 * If we're using the I/O APIC, avoid using the PCI IRQ 1436 * routing table 1437 */ 1438 if (io_apic_assign_pci_irqs) { 1439 kfree(rtable); 1440 pirq_table = NULL; 1441 } 1442 } 1443 1444 x86_init.pci.fixup_irqs(); 1445 1446 if (io_apic_assign_pci_irqs && pci_routeirq) { 1447 struct pci_dev *dev = NULL; 1448 /* 1449 * PCI IRQ routing is set up by pci_enable_device(), but we 1450 * also do it here in case there are still broken drivers that 1451 * don't use pci_enable_device(). 1452 */ 1453 printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n"); 1454 for_each_pci_dev(dev) 1455 pirq_enable_irq(dev); 1456 } 1457 } 1458 1459 static void pirq_penalize_isa_irq(int irq, int active) 1460 { 1461 /* 1462 * If any ISAPnP device reports an IRQ in its list of possible 1463 * IRQ's, we try to avoid assigning it to PCI devices. 1464 */ 1465 if (irq < 16) { 1466 if (active) 1467 pirq_penalty[irq] += 1000; 1468 else 1469 pirq_penalty[irq] += 100; 1470 } 1471 } 1472 1473 void pcibios_penalize_isa_irq(int irq, int active) 1474 { 1475 #ifdef CONFIG_ACPI 1476 if (!acpi_noirq) 1477 acpi_penalize_isa_irq(irq, active); 1478 else 1479 #endif 1480 pirq_penalize_isa_irq(irq, active); 1481 } 1482 1483 static int pirq_enable_irq(struct pci_dev *dev) 1484 { 1485 u8 pin = 0; 1486 1487 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1488 if (pin && !pcibios_lookup_irq(dev, 1)) { 1489 char *msg = ""; 1490 1491 if (!io_apic_assign_pci_irqs && dev->irq) 1492 return 0; 1493 1494 if (io_apic_assign_pci_irqs) { 1495 #ifdef CONFIG_X86_IO_APIC 1496 struct pci_dev *temp_dev; 1497 int irq; 1498 1499 if (dev->irq_managed && dev->irq > 0) 1500 return 0; 1501 1502 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, 1503 PCI_SLOT(dev->devfn), pin - 1); 1504 /* 1505 * Busses behind bridges are typically not listed in the MP-table. 1506 * In this case we have to look up the IRQ based on the parent bus, 1507 * parent slot, and pin number. The SMP code detects such bridged 1508 * busses itself so we should get into this branch reliably. 1509 */ 1510 temp_dev = dev; 1511 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */ 1512 struct pci_dev *bridge = dev->bus->self; 1513 1514 pin = pci_swizzle_interrupt_pin(dev, pin); 1515 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, 1516 PCI_SLOT(bridge->devfn), 1517 pin - 1); 1518 if (irq >= 0) 1519 dev_warn(&dev->dev, "using bridge %s " 1520 "INT %c to get IRQ %d\n", 1521 pci_name(bridge), 'A' + pin - 1, 1522 irq); 1523 dev = bridge; 1524 } 1525 dev = temp_dev; 1526 if (irq >= 0) { 1527 dev->irq_managed = 1; 1528 dev->irq = irq; 1529 dev_info(&dev->dev, "PCI->APIC IRQ transform: " 1530 "INT %c -> IRQ %d\n", 'A' + pin - 1, irq); 1531 return 0; 1532 } else 1533 msg = "; probably buggy MP table"; 1534 #endif 1535 } else if (pci_probe & PCI_BIOS_IRQ_SCAN) 1536 msg = ""; 1537 else 1538 msg = "; please try using pci=biosirq"; 1539 1540 /* 1541 * With IDE legacy devices the IRQ lookup failure is not 1542 * a problem.. 1543 */ 1544 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && 1545 !(dev->class & 0x5)) 1546 return 0; 1547 1548 dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n", 1549 'A' + pin - 1, msg); 1550 } 1551 return 0; 1552 } 1553 1554 bool mp_should_keep_irq(struct device *dev) 1555 { 1556 if (dev->power.is_prepared) 1557 return true; 1558 #ifdef CONFIG_PM 1559 if (dev->power.runtime_status == RPM_SUSPENDING) 1560 return true; 1561 #endif 1562 1563 return false; 1564 } 1565 1566 static void pirq_disable_irq(struct pci_dev *dev) 1567 { 1568 if (io_apic_assign_pci_irqs && !mp_should_keep_irq(&dev->dev) && 1569 dev->irq_managed && dev->irq) { 1570 mp_unmap_irq(dev->irq); 1571 dev->irq = 0; 1572 dev->irq_managed = 0; 1573 } 1574 } 1575