1 /* 2 * Low-Level PCI Support for PC -- Routing of Interrupts 3 * 4 * (c) 1999--2000 Martin Mares <mj@ucw.cz> 5 */ 6 7 #include <linux/types.h> 8 #include <linux/kernel.h> 9 #include <linux/pci.h> 10 #include <linux/init.h> 11 #include <linux/slab.h> 12 #include <linux/interrupt.h> 13 #include <linux/dmi.h> 14 #include <asm/io.h> 15 #include <asm/smp.h> 16 #include <asm/io_apic.h> 17 #include <linux/irq.h> 18 #include <linux/acpi.h> 19 20 #include "pci.h" 21 22 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) 23 #define PIRQ_VERSION 0x0100 24 25 static int broken_hp_bios_irq9; 26 static int acer_tm360_irqrouting; 27 28 static struct irq_routing_table *pirq_table; 29 30 static int pirq_enable_irq(struct pci_dev *dev); 31 32 /* 33 * Never use: 0, 1, 2 (timer, keyboard, and cascade) 34 * Avoid using: 13, 14 and 15 (FP error and IDE). 35 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse) 36 */ 37 unsigned int pcibios_irq_mask = 0xfff8; 38 39 static int pirq_penalty[16] = { 40 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000, 41 0, 0, 0, 0, 1000, 100000, 100000, 100000 42 }; 43 44 struct irq_router { 45 char *name; 46 u16 vendor, device; 47 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq); 48 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, int new); 49 }; 50 51 struct irq_router_handler { 52 u16 vendor; 53 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device); 54 }; 55 56 int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL; 57 void (*pcibios_disable_irq)(struct pci_dev *dev) = NULL; 58 59 /* 60 * Check passed address for the PCI IRQ Routing Table signature 61 * and perform checksum verification. 62 */ 63 64 static inline struct irq_routing_table * pirq_check_routing_table(u8 *addr) 65 { 66 struct irq_routing_table *rt; 67 int i; 68 u8 sum; 69 70 rt = (struct irq_routing_table *) addr; 71 if (rt->signature != PIRQ_SIGNATURE || 72 rt->version != PIRQ_VERSION || 73 rt->size % 16 || 74 rt->size < sizeof(struct irq_routing_table)) 75 return NULL; 76 sum = 0; 77 for (i=0; i < rt->size; i++) 78 sum += addr[i]; 79 if (!sum) { 80 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n", rt); 81 return rt; 82 } 83 return NULL; 84 } 85 86 87 88 /* 89 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table. 90 */ 91 92 static struct irq_routing_table * __init pirq_find_routing_table(void) 93 { 94 u8 *addr; 95 struct irq_routing_table *rt; 96 97 if (pirq_table_addr) { 98 rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr)); 99 if (rt) 100 return rt; 101 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n"); 102 } 103 for(addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) { 104 rt = pirq_check_routing_table(addr); 105 if (rt) 106 return rt; 107 } 108 return NULL; 109 } 110 111 /* 112 * If we have a IRQ routing table, use it to search for peer host 113 * bridges. It's a gross hack, but since there are no other known 114 * ways how to get a list of buses, we have to go this way. 115 */ 116 117 static void __init pirq_peer_trick(void) 118 { 119 struct irq_routing_table *rt = pirq_table; 120 u8 busmap[256]; 121 int i; 122 struct irq_info *e; 123 124 memset(busmap, 0, sizeof(busmap)); 125 for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) { 126 e = &rt->slots[i]; 127 #ifdef DEBUG 128 { 129 int j; 130 DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot); 131 for(j=0; j<4; j++) 132 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap); 133 DBG("\n"); 134 } 135 #endif 136 busmap[e->bus] = 1; 137 } 138 for(i = 1; i < 256; i++) { 139 int node; 140 if (!busmap[i] || pci_find_bus(0, i)) 141 continue; 142 node = get_mp_bus_to_node(i); 143 if (pci_scan_bus_on_node(i, &pci_root_ops, node)) 144 printk(KERN_INFO "PCI: Discovered primary peer " 145 "bus %02x [IRQ]\n", i); 146 } 147 pcibios_last_bus = -1; 148 } 149 150 /* 151 * Code for querying and setting of IRQ routes on various interrupt routers. 152 */ 153 154 void eisa_set_level_irq(unsigned int irq) 155 { 156 unsigned char mask = 1 << (irq & 7); 157 unsigned int port = 0x4d0 + (irq >> 3); 158 unsigned char val; 159 static u16 eisa_irq_mask; 160 161 if (irq >= 16 || (1 << irq) & eisa_irq_mask) 162 return; 163 164 eisa_irq_mask |= (1 << irq); 165 printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq); 166 val = inb(port); 167 if (!(val & mask)) { 168 DBG(KERN_DEBUG " -> edge"); 169 outb(val | mask, port); 170 } 171 } 172 173 /* 174 * Common IRQ routing practice: nibbles in config space, 175 * offset by some magic constant. 176 */ 177 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr) 178 { 179 u8 x; 180 unsigned reg = offset + (nr >> 1); 181 182 pci_read_config_byte(router, reg, &x); 183 return (nr & 1) ? (x >> 4) : (x & 0xf); 184 } 185 186 static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val) 187 { 188 u8 x; 189 unsigned reg = offset + (nr >> 1); 190 191 pci_read_config_byte(router, reg, &x); 192 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val); 193 pci_write_config_byte(router, reg, x); 194 } 195 196 /* 197 * ALI pirq entries are damn ugly, and completely undocumented. 198 * This has been figured out from pirq tables, and it's not a pretty 199 * picture. 200 */ 201 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 202 { 203 static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 }; 204 205 WARN_ON_ONCE(pirq > 16); 206 return irqmap[read_config_nybble(router, 0x48, pirq-1)]; 207 } 208 209 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 210 { 211 static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 }; 212 unsigned int val = irqmap[irq]; 213 214 WARN_ON_ONCE(pirq > 16); 215 if (val) { 216 write_config_nybble(router, 0x48, pirq-1, val); 217 return 1; 218 } 219 return 0; 220 } 221 222 /* 223 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is 224 * just a pointer to the config space. 225 */ 226 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 227 { 228 u8 x; 229 230 pci_read_config_byte(router, pirq, &x); 231 return (x < 16) ? x : 0; 232 } 233 234 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 235 { 236 pci_write_config_byte(router, pirq, irq); 237 return 1; 238 } 239 240 /* 241 * The VIA pirq rules are nibble-based, like ALI, 242 * but without the ugly irq number munging. 243 * However, PIRQD is in the upper instead of lower 4 bits. 244 */ 245 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 246 { 247 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq); 248 } 249 250 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 251 { 252 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq); 253 return 1; 254 } 255 256 /* 257 * The VIA pirq rules are nibble-based, like ALI, 258 * but without the ugly irq number munging. 259 * However, for 82C586, nibble map is different . 260 */ 261 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 262 { 263 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 264 265 WARN_ON_ONCE(pirq > 5); 266 return read_config_nybble(router, 0x55, pirqmap[pirq-1]); 267 } 268 269 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 270 { 271 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 272 273 WARN_ON_ONCE(pirq > 5); 274 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq); 275 return 1; 276 } 277 278 /* 279 * ITE 8330G pirq rules are nibble-based 280 * FIXME: pirqmap may be { 1, 0, 3, 2 }, 281 * 2+3 are both mapped to irq 9 on my system 282 */ 283 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 284 { 285 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 286 287 WARN_ON_ONCE(pirq > 4); 288 return read_config_nybble(router,0x43, pirqmap[pirq-1]); 289 } 290 291 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 292 { 293 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 294 295 WARN_ON_ONCE(pirq > 4); 296 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq); 297 return 1; 298 } 299 300 /* 301 * OPTI: high four bits are nibble pointer.. 302 * I wonder what the low bits do? 303 */ 304 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 305 { 306 return read_config_nybble(router, 0xb8, pirq >> 4); 307 } 308 309 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 310 { 311 write_config_nybble(router, 0xb8, pirq >> 4, irq); 312 return 1; 313 } 314 315 /* 316 * Cyrix: nibble offset 0x5C 317 * 0x5C bits 7:4 is INTB bits 3:0 is INTA 318 * 0x5D bits 7:4 is INTD bits 3:0 is INTC 319 */ 320 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 321 { 322 return read_config_nybble(router, 0x5C, (pirq-1)^1); 323 } 324 325 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 326 { 327 write_config_nybble(router, 0x5C, (pirq-1)^1, irq); 328 return 1; 329 } 330 331 /* 332 * PIRQ routing for SiS 85C503 router used in several SiS chipsets. 333 * We have to deal with the following issues here: 334 * - vendors have different ideas about the meaning of link values 335 * - some onboard devices (integrated in the chipset) have special 336 * links and are thus routed differently (i.e. not via PCI INTA-INTD) 337 * - different revision of the router have a different layout for 338 * the routing registers, particularly for the onchip devices 339 * 340 * For all routing registers the common thing is we have one byte 341 * per routeable link which is defined as: 342 * bit 7 IRQ mapping enabled (0) or disabled (1) 343 * bits [6:4] reserved (sometimes used for onchip devices) 344 * bits [3:0] IRQ to map to 345 * allowed: 3-7, 9-12, 14-15 346 * reserved: 0, 1, 2, 8, 13 347 * 348 * The config-space registers located at 0x41/0x42/0x43/0x44 are 349 * always used to route the normal PCI INT A/B/C/D respectively. 350 * Apparently there are systems implementing PCI routing table using 351 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D. 352 * We try our best to handle both link mappings. 353 * 354 * Currently (2003-05-21) it appears most SiS chipsets follow the 355 * definition of routing registers from the SiS-5595 southbridge. 356 * According to the SiS 5595 datasheets the revision id's of the 357 * router (ISA-bridge) should be 0x01 or 0xb0. 358 * 359 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1. 360 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets. 361 * They seem to work with the current routing code. However there is 362 * some concern because of the two USB-OHCI HCs (original SiS 5595 363 * had only one). YMMV. 364 * 365 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1: 366 * 367 * 0x61: IDEIRQ: 368 * bits [6:5] must be written 01 369 * bit 4 channel-select primary (0), secondary (1) 370 * 371 * 0x62: USBIRQ: 372 * bit 6 OHCI function disabled (0), enabled (1) 373 * 374 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved 375 * 376 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved 377 * 378 * We support USBIRQ (in addition to INTA-INTD) and keep the 379 * IDE, ACPI and DAQ routing untouched as set by the BIOS. 380 * 381 * Currently the only reported exception is the new SiS 65x chipset 382 * which includes the SiS 69x southbridge. Here we have the 85C503 383 * router revision 0x04 and there are changes in the register layout 384 * mostly related to the different USB HCs with USB 2.0 support. 385 * 386 * Onchip routing for router rev-id 0x04 (try-and-error observation) 387 * 388 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs 389 * bit 6-4 are probably unused, not like 5595 390 */ 391 392 #define PIRQ_SIS_IRQ_MASK 0x0f 393 #define PIRQ_SIS_IRQ_DISABLE 0x80 394 #define PIRQ_SIS_USB_ENABLE 0x40 395 396 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 397 { 398 u8 x; 399 int reg; 400 401 reg = pirq; 402 if (reg >= 0x01 && reg <= 0x04) 403 reg += 0x40; 404 pci_read_config_byte(router, reg, &x); 405 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK); 406 } 407 408 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 409 { 410 u8 x; 411 int reg; 412 413 reg = pirq; 414 if (reg >= 0x01 && reg <= 0x04) 415 reg += 0x40; 416 pci_read_config_byte(router, reg, &x); 417 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE); 418 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE; 419 pci_write_config_byte(router, reg, x); 420 return 1; 421 } 422 423 424 /* 425 * VLSI: nibble offset 0x74 - educated guess due to routing table and 426 * config space of VLSI 82C534 PCI-bridge/router (1004:0102) 427 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard 428 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6 429 * for the busbridge to the docking station. 430 */ 431 432 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 433 { 434 WARN_ON_ONCE(pirq >= 9); 435 if (pirq > 8) { 436 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq); 437 return 0; 438 } 439 return read_config_nybble(router, 0x74, pirq-1); 440 } 441 442 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 443 { 444 WARN_ON_ONCE(pirq >= 9); 445 if (pirq > 8) { 446 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq); 447 return 0; 448 } 449 write_config_nybble(router, 0x74, pirq-1, irq); 450 return 1; 451 } 452 453 /* 454 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index 455 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register 456 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect 457 * register is a straight binary coding of desired PIC IRQ (low nibble). 458 * 459 * The 'link' value in the PIRQ table is already in the correct format 460 * for the Index register. There are some special index values: 461 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1, 462 * and 0x03 for SMBus. 463 */ 464 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 465 { 466 outb(pirq, 0xc00); 467 return inb(0xc01) & 0xf; 468 } 469 470 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 471 { 472 outb(pirq, 0xc00); 473 outb(irq, 0xc01); 474 return 1; 475 } 476 477 /* Support for AMD756 PCI IRQ Routing 478 * Jhon H. Caicedo <jhcaiced@osso.org.co> 479 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced) 480 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced) 481 * The AMD756 pirq rules are nibble-based 482 * offset 0x56 0-3 PIRQA 4-7 PIRQB 483 * offset 0x57 0-3 PIRQC 4-7 PIRQD 484 */ 485 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 486 { 487 u8 irq; 488 irq = 0; 489 if (pirq <= 4) 490 { 491 irq = read_config_nybble(router, 0x56, pirq - 1); 492 } 493 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n", 494 dev->vendor, dev->device, pirq, irq); 495 return irq; 496 } 497 498 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 499 { 500 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n", 501 dev->vendor, dev->device, pirq, irq); 502 if (pirq <= 4) 503 { 504 write_config_nybble(router, 0x56, pirq - 1, irq); 505 } 506 return 1; 507 } 508 509 /* 510 * PicoPower PT86C523 511 */ 512 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 513 { 514 outb(0x10 + ((pirq - 1) >> 1), 0x24); 515 return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf); 516 } 517 518 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq, 519 int irq) 520 { 521 unsigned int x; 522 outb(0x10 + ((pirq - 1) >> 1), 0x24); 523 x = inb(0x26); 524 x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq)); 525 outb(x, 0x26); 526 return 1; 527 } 528 529 #ifdef CONFIG_PCI_BIOS 530 531 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 532 { 533 struct pci_dev *bridge; 534 int pin = pci_get_interrupt_pin(dev, &bridge); 535 return pcibios_set_irq_routing(bridge, pin, irq); 536 } 537 538 #endif 539 540 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 541 { 542 static struct pci_device_id __initdata pirq_440gx[] = { 543 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) }, 544 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) }, 545 { }, 546 }; 547 548 /* 440GX has a proprietary PIRQ router -- don't use it */ 549 if (pci_dev_present(pirq_440gx)) 550 return 0; 551 552 switch(device) 553 { 554 case PCI_DEVICE_ID_INTEL_82371FB_0: 555 case PCI_DEVICE_ID_INTEL_82371SB_0: 556 case PCI_DEVICE_ID_INTEL_82371AB_0: 557 case PCI_DEVICE_ID_INTEL_82371MX: 558 case PCI_DEVICE_ID_INTEL_82443MX_0: 559 case PCI_DEVICE_ID_INTEL_82801AA_0: 560 case PCI_DEVICE_ID_INTEL_82801AB_0: 561 case PCI_DEVICE_ID_INTEL_82801BA_0: 562 case PCI_DEVICE_ID_INTEL_82801BA_10: 563 case PCI_DEVICE_ID_INTEL_82801CA_0: 564 case PCI_DEVICE_ID_INTEL_82801CA_12: 565 case PCI_DEVICE_ID_INTEL_82801DB_0: 566 case PCI_DEVICE_ID_INTEL_82801E_0: 567 case PCI_DEVICE_ID_INTEL_82801EB_0: 568 case PCI_DEVICE_ID_INTEL_ESB_1: 569 case PCI_DEVICE_ID_INTEL_ICH6_0: 570 case PCI_DEVICE_ID_INTEL_ICH6_1: 571 case PCI_DEVICE_ID_INTEL_ICH7_0: 572 case PCI_DEVICE_ID_INTEL_ICH7_1: 573 case PCI_DEVICE_ID_INTEL_ICH7_30: 574 case PCI_DEVICE_ID_INTEL_ICH7_31: 575 case PCI_DEVICE_ID_INTEL_ESB2_0: 576 case PCI_DEVICE_ID_INTEL_ICH8_0: 577 case PCI_DEVICE_ID_INTEL_ICH8_1: 578 case PCI_DEVICE_ID_INTEL_ICH8_2: 579 case PCI_DEVICE_ID_INTEL_ICH8_3: 580 case PCI_DEVICE_ID_INTEL_ICH8_4: 581 case PCI_DEVICE_ID_INTEL_ICH9_0: 582 case PCI_DEVICE_ID_INTEL_ICH9_1: 583 case PCI_DEVICE_ID_INTEL_ICH9_2: 584 case PCI_DEVICE_ID_INTEL_ICH9_3: 585 case PCI_DEVICE_ID_INTEL_ICH9_4: 586 case PCI_DEVICE_ID_INTEL_ICH9_5: 587 case PCI_DEVICE_ID_INTEL_TOLAPAI_0: 588 case PCI_DEVICE_ID_INTEL_ICH10_0: 589 case PCI_DEVICE_ID_INTEL_ICH10_1: 590 case PCI_DEVICE_ID_INTEL_ICH10_2: 591 case PCI_DEVICE_ID_INTEL_ICH10_3: 592 r->name = "PIIX/ICH"; 593 r->get = pirq_piix_get; 594 r->set = pirq_piix_set; 595 return 1; 596 } 597 return 0; 598 } 599 600 static __init int via_router_probe(struct irq_router *r, 601 struct pci_dev *router, u16 device) 602 { 603 /* FIXME: We should move some of the quirk fixup stuff here */ 604 605 /* 606 * workarounds for some buggy BIOSes 607 */ 608 if (device == PCI_DEVICE_ID_VIA_82C586_0) { 609 switch(router->device) { 610 case PCI_DEVICE_ID_VIA_82C686: 611 /* 612 * Asus k7m bios wrongly reports 82C686A 613 * as 586-compatible 614 */ 615 device = PCI_DEVICE_ID_VIA_82C686; 616 break; 617 case PCI_DEVICE_ID_VIA_8235: 618 /** 619 * Asus a7v-x bios wrongly reports 8235 620 * as 586-compatible 621 */ 622 device = PCI_DEVICE_ID_VIA_8235; 623 break; 624 } 625 } 626 627 switch(device) { 628 case PCI_DEVICE_ID_VIA_82C586_0: 629 r->name = "VIA"; 630 r->get = pirq_via586_get; 631 r->set = pirq_via586_set; 632 return 1; 633 case PCI_DEVICE_ID_VIA_82C596: 634 case PCI_DEVICE_ID_VIA_82C686: 635 case PCI_DEVICE_ID_VIA_8231: 636 case PCI_DEVICE_ID_VIA_8233A: 637 case PCI_DEVICE_ID_VIA_8235: 638 case PCI_DEVICE_ID_VIA_8237: 639 /* FIXME: add new ones for 8233/5 */ 640 r->name = "VIA"; 641 r->get = pirq_via_get; 642 r->set = pirq_via_set; 643 return 1; 644 } 645 return 0; 646 } 647 648 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 649 { 650 switch(device) 651 { 652 case PCI_DEVICE_ID_VLSI_82C534: 653 r->name = "VLSI 82C534"; 654 r->get = pirq_vlsi_get; 655 r->set = pirq_vlsi_set; 656 return 1; 657 } 658 return 0; 659 } 660 661 662 static __init int serverworks_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 663 { 664 switch(device) 665 { 666 case PCI_DEVICE_ID_SERVERWORKS_OSB4: 667 case PCI_DEVICE_ID_SERVERWORKS_CSB5: 668 r->name = "ServerWorks"; 669 r->get = pirq_serverworks_get; 670 r->set = pirq_serverworks_set; 671 return 1; 672 } 673 return 0; 674 } 675 676 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 677 { 678 if (device != PCI_DEVICE_ID_SI_503) 679 return 0; 680 681 r->name = "SIS"; 682 r->get = pirq_sis_get; 683 r->set = pirq_sis_set; 684 return 1; 685 } 686 687 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 688 { 689 switch(device) 690 { 691 case PCI_DEVICE_ID_CYRIX_5520: 692 r->name = "NatSemi"; 693 r->get = pirq_cyrix_get; 694 r->set = pirq_cyrix_set; 695 return 1; 696 } 697 return 0; 698 } 699 700 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 701 { 702 switch(device) 703 { 704 case PCI_DEVICE_ID_OPTI_82C700: 705 r->name = "OPTI"; 706 r->get = pirq_opti_get; 707 r->set = pirq_opti_set; 708 return 1; 709 } 710 return 0; 711 } 712 713 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 714 { 715 switch(device) 716 { 717 case PCI_DEVICE_ID_ITE_IT8330G_0: 718 r->name = "ITE"; 719 r->get = pirq_ite_get; 720 r->set = pirq_ite_set; 721 return 1; 722 } 723 return 0; 724 } 725 726 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 727 { 728 switch(device) 729 { 730 case PCI_DEVICE_ID_AL_M1533: 731 case PCI_DEVICE_ID_AL_M1563: 732 printk(KERN_DEBUG "PCI: Using ALI IRQ Router\n"); 733 r->name = "ALI"; 734 r->get = pirq_ali_get; 735 r->set = pirq_ali_set; 736 return 1; 737 } 738 return 0; 739 } 740 741 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 742 { 743 switch(device) 744 { 745 case PCI_DEVICE_ID_AMD_VIPER_740B: 746 r->name = "AMD756"; 747 break; 748 case PCI_DEVICE_ID_AMD_VIPER_7413: 749 r->name = "AMD766"; 750 break; 751 case PCI_DEVICE_ID_AMD_VIPER_7443: 752 r->name = "AMD768"; 753 break; 754 default: 755 return 0; 756 } 757 r->get = pirq_amd756_get; 758 r->set = pirq_amd756_set; 759 return 1; 760 } 761 762 static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 763 { 764 switch (device) { 765 case PCI_DEVICE_ID_PICOPOWER_PT86C523: 766 r->name = "PicoPower PT86C523"; 767 r->get = pirq_pico_get; 768 r->set = pirq_pico_set; 769 return 1; 770 771 case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP: 772 r->name = "PicoPower PT86C523 rev. BB+"; 773 r->get = pirq_pico_get; 774 r->set = pirq_pico_set; 775 return 1; 776 } 777 return 0; 778 } 779 780 static __initdata struct irq_router_handler pirq_routers[] = { 781 { PCI_VENDOR_ID_INTEL, intel_router_probe }, 782 { PCI_VENDOR_ID_AL, ali_router_probe }, 783 { PCI_VENDOR_ID_ITE, ite_router_probe }, 784 { PCI_VENDOR_ID_VIA, via_router_probe }, 785 { PCI_VENDOR_ID_OPTI, opti_router_probe }, 786 { PCI_VENDOR_ID_SI, sis_router_probe }, 787 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe }, 788 { PCI_VENDOR_ID_VLSI, vlsi_router_probe }, 789 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe }, 790 { PCI_VENDOR_ID_AMD, amd_router_probe }, 791 { PCI_VENDOR_ID_PICOPOWER, pico_router_probe }, 792 /* Someone with docs needs to add the ATI Radeon IGP */ 793 { 0, NULL } 794 }; 795 static struct irq_router pirq_router; 796 static struct pci_dev *pirq_router_dev; 797 798 799 /* 800 * FIXME: should we have an option to say "generic for 801 * chipset" ? 802 */ 803 804 static void __init pirq_find_router(struct irq_router *r) 805 { 806 struct irq_routing_table *rt = pirq_table; 807 struct irq_router_handler *h; 808 809 #ifdef CONFIG_PCI_BIOS 810 if (!rt->signature) { 811 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n"); 812 r->set = pirq_bios_set; 813 r->name = "BIOS"; 814 return; 815 } 816 #endif 817 818 /* Default unless a driver reloads it */ 819 r->name = "default"; 820 r->get = NULL; 821 r->set = NULL; 822 823 DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for %04x:%04x\n", 824 rt->rtr_vendor, rt->rtr_device); 825 826 pirq_router_dev = pci_get_bus_and_slot(rt->rtr_bus, rt->rtr_devfn); 827 if (!pirq_router_dev) { 828 DBG(KERN_DEBUG "PCI: Interrupt router not found at " 829 "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn); 830 return; 831 } 832 833 for( h = pirq_routers; h->vendor; h++) { 834 /* First look for a router match */ 835 if (rt->rtr_vendor == h->vendor && h->probe(r, pirq_router_dev, rt->rtr_device)) 836 break; 837 /* Fall back to a device match */ 838 if (pirq_router_dev->vendor == h->vendor && h->probe(r, pirq_router_dev, pirq_router_dev->device)) 839 break; 840 } 841 printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n", 842 pirq_router.name, 843 pirq_router_dev->vendor, 844 pirq_router_dev->device, 845 pci_name(pirq_router_dev)); 846 847 /* The device remains referenced for the kernel lifetime */ 848 } 849 850 static struct irq_info *pirq_get_info(struct pci_dev *dev) 851 { 852 struct irq_routing_table *rt = pirq_table; 853 int entries = (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); 854 struct irq_info *info; 855 856 for (info = rt->slots; entries--; info++) 857 if (info->bus == dev->bus->number && PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn)) 858 return info; 859 return NULL; 860 } 861 862 static int pcibios_lookup_irq(struct pci_dev *dev, int assign) 863 { 864 u8 pin; 865 struct irq_info *info; 866 int i, pirq, newirq; 867 int irq = 0; 868 u32 mask; 869 struct irq_router *r = &pirq_router; 870 struct pci_dev *dev2 = NULL; 871 char *msg = NULL; 872 873 /* Find IRQ pin */ 874 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 875 if (!pin) { 876 DBG(KERN_DEBUG " -> no interrupt pin\n"); 877 return 0; 878 } 879 pin = pin - 1; 880 881 /* Find IRQ routing entry */ 882 883 if (!pirq_table) 884 return 0; 885 886 DBG(KERN_DEBUG "IRQ for %s[%c]", pci_name(dev), 'A' + pin); 887 info = pirq_get_info(dev); 888 if (!info) { 889 DBG(" -> not found in routing table\n" KERN_DEBUG); 890 return 0; 891 } 892 pirq = info->irq[pin].link; 893 mask = info->irq[pin].bitmap; 894 if (!pirq) { 895 DBG(" -> not routed\n" KERN_DEBUG); 896 return 0; 897 } 898 DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, pirq_table->exclusive_irqs); 899 mask &= pcibios_irq_mask; 900 901 /* Work around broken HP Pavilion Notebooks which assign USB to 902 IRQ 9 even though it is actually wired to IRQ 11 */ 903 904 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) { 905 dev->irq = 11; 906 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11); 907 r->set(pirq_router_dev, dev, pirq, 11); 908 } 909 910 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */ 911 if (acer_tm360_irqrouting && dev->irq == 11 && dev->vendor == PCI_VENDOR_ID_O2) { 912 pirq = 0x68; 913 mask = 0x400; 914 dev->irq = r->get(pirq_router_dev, dev, pirq); 915 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 916 } 917 918 /* 919 * Find the best IRQ to assign: use the one 920 * reported by the device if possible. 921 */ 922 newirq = dev->irq; 923 if (newirq && !((1 << newirq) & mask)) { 924 if ( pci_probe & PCI_USE_PIRQ_MASK) newirq = 0; 925 else printk("\n" KERN_WARNING 926 "PCI: IRQ %i for device %s doesn't match PIRQ mask " 927 "- try pci=usepirqmask\n" KERN_DEBUG, newirq, 928 pci_name(dev)); 929 } 930 if (!newirq && assign) { 931 for (i = 0; i < 16; i++) { 932 if (!(mask & (1 << i))) 933 continue; 934 if (pirq_penalty[i] < pirq_penalty[newirq] && can_request_irq(i, IRQF_SHARED)) 935 newirq = i; 936 } 937 } 938 DBG(" -> newirq=%d", newirq); 939 940 /* Check if it is hardcoded */ 941 if ((pirq & 0xf0) == 0xf0) { 942 irq = pirq & 0xf; 943 DBG(" -> hardcoded IRQ %d\n", irq); 944 msg = "Hardcoded"; 945 } else if ( r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \ 946 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask)) ) { 947 DBG(" -> got IRQ %d\n", irq); 948 msg = "Found"; 949 eisa_set_level_irq(irq); 950 } else if (newirq && r->set && (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) { 951 DBG(" -> assigning IRQ %d", newirq); 952 if (r->set(pirq_router_dev, dev, pirq, newirq)) { 953 eisa_set_level_irq(newirq); 954 DBG(" ... OK\n"); 955 msg = "Assigned"; 956 irq = newirq; 957 } 958 } 959 960 if (!irq) { 961 DBG(" ... failed\n"); 962 if (newirq && mask == (1 << newirq)) { 963 msg = "Guessed"; 964 irq = newirq; 965 } else 966 return 0; 967 } 968 printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, pci_name(dev)); 969 970 /* Update IRQ for all devices with the same pirq value */ 971 while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) { 972 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin); 973 if (!pin) 974 continue; 975 pin--; 976 info = pirq_get_info(dev2); 977 if (!info) 978 continue; 979 if (info->irq[pin].link == pirq) { 980 /* We refuse to override the dev->irq information. Give a warning! */ 981 if ( dev2->irq && dev2->irq != irq && \ 982 (!(pci_probe & PCI_USE_PIRQ_MASK) || \ 983 ((1 << dev2->irq) & mask)) ) { 984 #ifndef CONFIG_PCI_MSI 985 printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n", 986 pci_name(dev2), dev2->irq, irq); 987 #endif 988 continue; 989 } 990 dev2->irq = irq; 991 pirq_penalty[irq]++; 992 if (dev != dev2) 993 printk(KERN_INFO "PCI: Sharing IRQ %d with %s\n", irq, pci_name(dev2)); 994 } 995 } 996 return 1; 997 } 998 999 static void __init pcibios_fixup_irqs(void) 1000 { 1001 struct pci_dev *dev = NULL; 1002 u8 pin; 1003 1004 DBG(KERN_DEBUG "PCI: IRQ fixup\n"); 1005 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { 1006 /* 1007 * If the BIOS has set an out of range IRQ number, just ignore it. 1008 * Also keep track of which IRQ's are already in use. 1009 */ 1010 if (dev->irq >= 16) { 1011 DBG(KERN_DEBUG "%s: ignoring bogus IRQ %d\n", pci_name(dev), dev->irq); 1012 dev->irq = 0; 1013 } 1014 /* If the IRQ is already assigned to a PCI device, ignore its ISA use penalty */ 1015 if (pirq_penalty[dev->irq] >= 100 && pirq_penalty[dev->irq] < 100000) 1016 pirq_penalty[dev->irq] = 0; 1017 pirq_penalty[dev->irq]++; 1018 } 1019 1020 dev = NULL; 1021 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { 1022 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1023 #ifdef CONFIG_X86_IO_APIC 1024 /* 1025 * Recalculate IRQ numbers if we use the I/O APIC. 1026 */ 1027 if (io_apic_assign_pci_irqs) 1028 { 1029 int irq; 1030 1031 if (pin) { 1032 pin--; /* interrupt pins are numbered starting from 1 */ 1033 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin); 1034 /* 1035 * Busses behind bridges are typically not listed in the MP-table. 1036 * In this case we have to look up the IRQ based on the parent bus, 1037 * parent slot, and pin number. The SMP code detects such bridged 1038 * busses itself so we should get into this branch reliably. 1039 */ 1040 if (irq < 0 && dev->bus->parent) { /* go back to the bridge */ 1041 struct pci_dev * bridge = dev->bus->self; 1042 1043 pin = (pin + PCI_SLOT(dev->devfn)) % 4; 1044 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, 1045 PCI_SLOT(bridge->devfn), pin); 1046 if (irq >= 0) 1047 printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n", 1048 pci_name(bridge), 'A' + pin, irq); 1049 } 1050 if (irq >= 0) { 1051 printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n", 1052 pci_name(dev), 'A' + pin, irq); 1053 dev->irq = irq; 1054 } 1055 } 1056 } 1057 #endif 1058 /* 1059 * Still no IRQ? Try to lookup one... 1060 */ 1061 if (pin && !dev->irq) 1062 pcibios_lookup_irq(dev, 0); 1063 } 1064 } 1065 1066 /* 1067 * Work around broken HP Pavilion Notebooks which assign USB to 1068 * IRQ 9 even though it is actually wired to IRQ 11 1069 */ 1070 static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d) 1071 { 1072 if (!broken_hp_bios_irq9) { 1073 broken_hp_bios_irq9 = 1; 1074 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident); 1075 } 1076 return 0; 1077 } 1078 1079 /* 1080 * Work around broken Acer TravelMate 360 Notebooks which assign 1081 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10 1082 */ 1083 static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d) 1084 { 1085 if (!acer_tm360_irqrouting) { 1086 acer_tm360_irqrouting = 1; 1087 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident); 1088 } 1089 return 0; 1090 } 1091 1092 static struct dmi_system_id __initdata pciirq_dmi_table[] = { 1093 { 1094 .callback = fix_broken_hp_bios_irq9, 1095 .ident = "HP Pavilion N5400 Series Laptop", 1096 .matches = { 1097 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1098 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"), 1099 DMI_MATCH(DMI_PRODUCT_VERSION, "HP Pavilion Notebook Model GE"), 1100 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"), 1101 }, 1102 }, 1103 { 1104 .callback = fix_acer_tm360_irqrouting, 1105 .ident = "Acer TravelMate 36x Laptop", 1106 .matches = { 1107 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1108 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"), 1109 }, 1110 }, 1111 { } 1112 }; 1113 1114 static int __init pcibios_irq_init(void) 1115 { 1116 DBG(KERN_DEBUG "PCI: IRQ init\n"); 1117 1118 if (pcibios_enable_irq || raw_pci_ops == NULL) 1119 return 0; 1120 1121 dmi_check_system(pciirq_dmi_table); 1122 1123 pirq_table = pirq_find_routing_table(); 1124 1125 #ifdef CONFIG_PCI_BIOS 1126 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN)) 1127 pirq_table = pcibios_get_irq_routing_table(); 1128 #endif 1129 if (pirq_table) { 1130 pirq_peer_trick(); 1131 pirq_find_router(&pirq_router); 1132 if (pirq_table->exclusive_irqs) { 1133 int i; 1134 for (i=0; i<16; i++) 1135 if (!(pirq_table->exclusive_irqs & (1 << i))) 1136 pirq_penalty[i] += 100; 1137 } 1138 /* If we're using the I/O APIC, avoid using the PCI IRQ routing table */ 1139 if (io_apic_assign_pci_irqs) 1140 pirq_table = NULL; 1141 } 1142 1143 pcibios_enable_irq = pirq_enable_irq; 1144 1145 pcibios_fixup_irqs(); 1146 return 0; 1147 } 1148 1149 subsys_initcall(pcibios_irq_init); 1150 1151 1152 static void pirq_penalize_isa_irq(int irq, int active) 1153 { 1154 /* 1155 * If any ISAPnP device reports an IRQ in its list of possible 1156 * IRQ's, we try to avoid assigning it to PCI devices. 1157 */ 1158 if (irq < 16) { 1159 if (active) 1160 pirq_penalty[irq] += 1000; 1161 else 1162 pirq_penalty[irq] += 100; 1163 } 1164 } 1165 1166 void pcibios_penalize_isa_irq(int irq, int active) 1167 { 1168 #ifdef CONFIG_ACPI 1169 if (!acpi_noirq) 1170 acpi_penalize_isa_irq(irq, active); 1171 else 1172 #endif 1173 pirq_penalize_isa_irq(irq, active); 1174 } 1175 1176 static int pirq_enable_irq(struct pci_dev *dev) 1177 { 1178 u8 pin; 1179 struct pci_dev *temp_dev; 1180 1181 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1182 if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) { 1183 char *msg = ""; 1184 1185 pin--; /* interrupt pins are numbered starting from 1 */ 1186 1187 if (io_apic_assign_pci_irqs) { 1188 int irq; 1189 1190 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin); 1191 /* 1192 * Busses behind bridges are typically not listed in the MP-table. 1193 * In this case we have to look up the IRQ based on the parent bus, 1194 * parent slot, and pin number. The SMP code detects such bridged 1195 * busses itself so we should get into this branch reliably. 1196 */ 1197 temp_dev = dev; 1198 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */ 1199 struct pci_dev * bridge = dev->bus->self; 1200 1201 pin = (pin + PCI_SLOT(dev->devfn)) % 4; 1202 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, 1203 PCI_SLOT(bridge->devfn), pin); 1204 if (irq >= 0) 1205 printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n", 1206 pci_name(bridge), 'A' + pin, irq); 1207 dev = bridge; 1208 } 1209 dev = temp_dev; 1210 if (irq >= 0) { 1211 printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n", 1212 pci_name(dev), 'A' + pin, irq); 1213 dev->irq = irq; 1214 return 0; 1215 } else 1216 msg = " Probably buggy MP table."; 1217 } else if (pci_probe & PCI_BIOS_IRQ_SCAN) 1218 msg = ""; 1219 else 1220 msg = " Please try using pci=biosirq."; 1221 1222 /* With IDE legacy devices the IRQ lookup failure is not a problem.. */ 1223 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && !(dev->class & 0x5)) 1224 return 0; 1225 1226 printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n", 1227 'A' + pin, pci_name(dev), msg); 1228 } 1229 return 0; 1230 } 1231