1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Low-Level PCI Support for PC -- Routing of Interrupts 4 * 5 * (c) 1999--2000 Martin Mares <mj@ucw.cz> 6 */ 7 8 #include <linux/types.h> 9 #include <linux/kernel.h> 10 #include <linux/pci.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/dmi.h> 14 #include <linux/io.h> 15 #include <linux/smp.h> 16 #include <linux/spinlock.h> 17 #include <asm/io_apic.h> 18 #include <linux/irq.h> 19 #include <linux/acpi.h> 20 21 #include <asm/pc-conf-reg.h> 22 #include <asm/pci_x86.h> 23 24 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) 25 #define PIRQ_VERSION 0x0100 26 27 static int broken_hp_bios_irq9; 28 static int acer_tm360_irqrouting; 29 30 static struct irq_routing_table *pirq_table; 31 32 static int pirq_enable_irq(struct pci_dev *dev); 33 static void pirq_disable_irq(struct pci_dev *dev); 34 35 /* 36 * Never use: 0, 1, 2 (timer, keyboard, and cascade) 37 * Avoid using: 13, 14 and 15 (FP error and IDE). 38 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse) 39 */ 40 unsigned int pcibios_irq_mask = 0xfff8; 41 42 static int pirq_penalty[16] = { 43 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000, 44 0, 0, 0, 0, 1000, 100000, 100000, 100000 45 }; 46 47 struct irq_router { 48 char *name; 49 u16 vendor, device; 50 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq); 51 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, 52 int new); 53 int (*lvl)(struct pci_dev *router, struct pci_dev *dev, int pirq, 54 int irq); 55 }; 56 57 struct irq_router_handler { 58 u16 vendor; 59 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device); 60 }; 61 62 int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq; 63 void (*pcibios_disable_irq)(struct pci_dev *dev) = pirq_disable_irq; 64 65 /* 66 * Check passed address for the PCI IRQ Routing Table signature 67 * and perform checksum verification. 68 */ 69 70 static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr) 71 { 72 struct irq_routing_table *rt; 73 int i; 74 u8 sum; 75 76 rt = (struct irq_routing_table *) addr; 77 if (rt->signature != PIRQ_SIGNATURE || 78 rt->version != PIRQ_VERSION || 79 rt->size % 16 || 80 rt->size < sizeof(struct irq_routing_table)) 81 return NULL; 82 sum = 0; 83 for (i = 0; i < rt->size; i++) 84 sum += addr[i]; 85 if (!sum) { 86 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n", 87 rt); 88 return rt; 89 } 90 return NULL; 91 } 92 93 94 95 /* 96 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table. 97 */ 98 99 static struct irq_routing_table * __init pirq_find_routing_table(void) 100 { 101 u8 *addr; 102 struct irq_routing_table *rt; 103 104 if (pirq_table_addr) { 105 rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr)); 106 if (rt) 107 return rt; 108 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n"); 109 } 110 for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) { 111 rt = pirq_check_routing_table(addr); 112 if (rt) 113 return rt; 114 } 115 return NULL; 116 } 117 118 /* 119 * If we have a IRQ routing table, use it to search for peer host 120 * bridges. It's a gross hack, but since there are no other known 121 * ways how to get a list of buses, we have to go this way. 122 */ 123 124 static void __init pirq_peer_trick(void) 125 { 126 struct irq_routing_table *rt = pirq_table; 127 u8 busmap[256]; 128 int i; 129 struct irq_info *e; 130 131 memset(busmap, 0, sizeof(busmap)); 132 for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) { 133 e = &rt->slots[i]; 134 #ifdef DEBUG 135 { 136 int j; 137 DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot); 138 for (j = 0; j < 4; j++) 139 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap); 140 DBG("\n"); 141 } 142 #endif 143 busmap[e->bus] = 1; 144 } 145 for (i = 1; i < 256; i++) { 146 if (!busmap[i] || pci_find_bus(0, i)) 147 continue; 148 pcibios_scan_root(i); 149 } 150 pcibios_last_bus = -1; 151 } 152 153 /* 154 * Code for querying and setting of IRQ routes on various interrupt routers. 155 * PIC Edge/Level Control Registers (ELCR) 0x4d0 & 0x4d1. 156 */ 157 158 void elcr_set_level_irq(unsigned int irq) 159 { 160 unsigned char mask = 1 << (irq & 7); 161 unsigned int port = 0x4d0 + (irq >> 3); 162 unsigned char val; 163 static u16 elcr_irq_mask; 164 165 if (irq >= 16 || (1 << irq) & elcr_irq_mask) 166 return; 167 168 elcr_irq_mask |= (1 << irq); 169 printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq); 170 val = inb(port); 171 if (!(val & mask)) { 172 DBG(KERN_DEBUG " -> edge"); 173 outb(val | mask, port); 174 } 175 } 176 177 /* 178 * PIRQ routing for the M1487 ISA Bus Controller (IBC) ASIC used 179 * with the ALi FinALi 486 chipset. The IBC is not decoded in the 180 * PCI configuration space, so we identify it by the accompanying 181 * M1489 Cache-Memory PCI Controller (CMP) ASIC. 182 * 183 * There are four 4-bit mappings provided, spread across two PCI 184 * INTx Routing Table Mapping Registers, available in the port I/O 185 * space accessible indirectly via the index/data register pair at 186 * 0x22/0x23, located at indices 0x42 and 0x43 for the INT1/INT2 187 * and INT3/INT4 lines respectively. The INT1/INT3 and INT2/INT4 188 * lines are mapped in the low and the high 4-bit nibble of the 189 * corresponding register as follows: 190 * 191 * 0000 : Disabled 192 * 0001 : IRQ9 193 * 0010 : IRQ3 194 * 0011 : IRQ10 195 * 0100 : IRQ4 196 * 0101 : IRQ5 197 * 0110 : IRQ7 198 * 0111 : IRQ6 199 * 1000 : Reserved 200 * 1001 : IRQ11 201 * 1010 : Reserved 202 * 1011 : IRQ12 203 * 1100 : Reserved 204 * 1101 : IRQ14 205 * 1110 : Reserved 206 * 1111 : IRQ15 207 * 208 * In addition to the usual ELCR register pair there is a separate 209 * PCI INTx Sensitivity Register at index 0x44 in the same port I/O 210 * space, whose bits 3:0 select the trigger mode for INT[4:1] lines 211 * respectively. Any bit set to 1 causes interrupts coming on the 212 * corresponding line to be passed to ISA as edge-triggered and 213 * otherwise they are passed as level-triggered. Manufacturer's 214 * documentation says this register has to be set consistently with 215 * the relevant ELCR register. 216 * 217 * Accesses to the port I/O space concerned here need to be unlocked 218 * by writing the value of 0xc5 to the Lock Register at index 0x03 219 * beforehand. Any other value written to said register prevents 220 * further accesses from reaching the register file, except for the 221 * Lock Register being written with 0xc5 again. 222 * 223 * References: 224 * 225 * "M1489/M1487: 486 PCI Chip Set", Version 1.2, Acer Laboratories 226 * Inc., July 1997 227 */ 228 229 #define PC_CONF_FINALI_LOCK 0x03u 230 #define PC_CONF_FINALI_PCI_INTX_RT1 0x42u 231 #define PC_CONF_FINALI_PCI_INTX_RT2 0x43u 232 #define PC_CONF_FINALI_PCI_INTX_SENS 0x44u 233 234 #define PC_CONF_FINALI_LOCK_KEY 0xc5u 235 236 static u8 read_pc_conf_nybble(u8 base, u8 index) 237 { 238 u8 reg = base + (index >> 1); 239 u8 x; 240 241 x = pc_conf_get(reg); 242 return index & 1 ? x >> 4 : x & 0xf; 243 } 244 245 static void write_pc_conf_nybble(u8 base, u8 index, u8 val) 246 { 247 u8 reg = base + (index >> 1); 248 u8 x; 249 250 x = pc_conf_get(reg); 251 x = index & 1 ? (x & 0x0f) | (val << 4) : (x & 0xf0) | val; 252 pc_conf_set(reg, x); 253 } 254 255 static int pirq_finali_get(struct pci_dev *router, struct pci_dev *dev, 256 int pirq) 257 { 258 static const u8 irqmap[16] = { 259 0, 9, 3, 10, 4, 5, 7, 6, 0, 11, 0, 12, 0, 14, 0, 15 260 }; 261 unsigned long flags; 262 u8 x; 263 264 raw_spin_lock_irqsave(&pc_conf_lock, flags); 265 pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY); 266 x = irqmap[read_pc_conf_nybble(PC_CONF_FINALI_PCI_INTX_RT1, pirq - 1)]; 267 pc_conf_set(PC_CONF_FINALI_LOCK, 0); 268 raw_spin_unlock_irqrestore(&pc_conf_lock, flags); 269 return x; 270 } 271 272 static int pirq_finali_set(struct pci_dev *router, struct pci_dev *dev, 273 int pirq, int irq) 274 { 275 static const u8 irqmap[16] = { 276 0, 0, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 277 }; 278 u8 val = irqmap[irq]; 279 unsigned long flags; 280 281 if (!val) 282 return 0; 283 284 raw_spin_lock_irqsave(&pc_conf_lock, flags); 285 pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY); 286 write_pc_conf_nybble(PC_CONF_FINALI_PCI_INTX_RT1, pirq - 1, val); 287 pc_conf_set(PC_CONF_FINALI_LOCK, 0); 288 raw_spin_unlock_irqrestore(&pc_conf_lock, flags); 289 return 1; 290 } 291 292 static int pirq_finali_lvl(struct pci_dev *router, struct pci_dev *dev, 293 int pirq, int irq) 294 { 295 u8 mask = ~(1u << (pirq - 1)); 296 unsigned long flags; 297 u8 trig; 298 299 elcr_set_level_irq(irq); 300 raw_spin_lock_irqsave(&pc_conf_lock, flags); 301 pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY); 302 trig = pc_conf_get(PC_CONF_FINALI_PCI_INTX_SENS); 303 trig &= mask; 304 pc_conf_set(PC_CONF_FINALI_PCI_INTX_SENS, trig); 305 pc_conf_set(PC_CONF_FINALI_LOCK, 0); 306 raw_spin_unlock_irqrestore(&pc_conf_lock, flags); 307 return 1; 308 } 309 310 /* 311 * Common IRQ routing practice: nibbles in config space, 312 * offset by some magic constant. 313 */ 314 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr) 315 { 316 u8 x; 317 unsigned reg = offset + (nr >> 1); 318 319 pci_read_config_byte(router, reg, &x); 320 return (nr & 1) ? (x >> 4) : (x & 0xf); 321 } 322 323 static void write_config_nybble(struct pci_dev *router, unsigned offset, 324 unsigned nr, unsigned int val) 325 { 326 u8 x; 327 unsigned reg = offset + (nr >> 1); 328 329 pci_read_config_byte(router, reg, &x); 330 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val); 331 pci_write_config_byte(router, reg, x); 332 } 333 334 /* 335 * ALI pirq entries are damn ugly, and completely undocumented. 336 * This has been figured out from pirq tables, and it's not a pretty 337 * picture. 338 */ 339 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 340 { 341 static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 }; 342 343 WARN_ON_ONCE(pirq > 16); 344 return irqmap[read_config_nybble(router, 0x48, pirq-1)]; 345 } 346 347 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 348 { 349 static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 }; 350 unsigned int val = irqmap[irq]; 351 352 WARN_ON_ONCE(pirq > 16); 353 if (val) { 354 write_config_nybble(router, 0x48, pirq-1, val); 355 return 1; 356 } 357 return 0; 358 } 359 360 /* 361 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is 362 * just a pointer to the config space. 363 */ 364 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 365 { 366 u8 x; 367 368 pci_read_config_byte(router, pirq, &x); 369 return (x < 16) ? x : 0; 370 } 371 372 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 373 { 374 pci_write_config_byte(router, pirq, irq); 375 return 1; 376 } 377 378 /* 379 * The VIA pirq rules are nibble-based, like ALI, 380 * but without the ugly irq number munging. 381 * However, PIRQD is in the upper instead of lower 4 bits. 382 */ 383 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 384 { 385 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq); 386 } 387 388 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 389 { 390 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq); 391 return 1; 392 } 393 394 /* 395 * The VIA pirq rules are nibble-based, like ALI, 396 * but without the ugly irq number munging. 397 * However, for 82C586, nibble map is different . 398 */ 399 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 400 { 401 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 402 403 WARN_ON_ONCE(pirq > 5); 404 return read_config_nybble(router, 0x55, pirqmap[pirq-1]); 405 } 406 407 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 408 { 409 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 410 411 WARN_ON_ONCE(pirq > 5); 412 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq); 413 return 1; 414 } 415 416 /* 417 * ITE 8330G pirq rules are nibble-based 418 * FIXME: pirqmap may be { 1, 0, 3, 2 }, 419 * 2+3 are both mapped to irq 9 on my system 420 */ 421 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 422 { 423 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 424 425 WARN_ON_ONCE(pirq > 4); 426 return read_config_nybble(router, 0x43, pirqmap[pirq-1]); 427 } 428 429 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 430 { 431 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 432 433 WARN_ON_ONCE(pirq > 4); 434 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq); 435 return 1; 436 } 437 438 /* 439 * OPTI: high four bits are nibble pointer.. 440 * I wonder what the low bits do? 441 */ 442 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 443 { 444 return read_config_nybble(router, 0xb8, pirq >> 4); 445 } 446 447 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 448 { 449 write_config_nybble(router, 0xb8, pirq >> 4, irq); 450 return 1; 451 } 452 453 /* 454 * Cyrix: nibble offset 0x5C 455 * 0x5C bits 7:4 is INTB bits 3:0 is INTA 456 * 0x5D bits 7:4 is INTD bits 3:0 is INTC 457 */ 458 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 459 { 460 return read_config_nybble(router, 0x5C, (pirq-1)^1); 461 } 462 463 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 464 { 465 write_config_nybble(router, 0x5C, (pirq-1)^1, irq); 466 return 1; 467 } 468 469 /* 470 * PIRQ routing for SiS 85C503 router used in several SiS chipsets. 471 * We have to deal with the following issues here: 472 * - vendors have different ideas about the meaning of link values 473 * - some onboard devices (integrated in the chipset) have special 474 * links and are thus routed differently (i.e. not via PCI INTA-INTD) 475 * - different revision of the router have a different layout for 476 * the routing registers, particularly for the onchip devices 477 * 478 * For all routing registers the common thing is we have one byte 479 * per routeable link which is defined as: 480 * bit 7 IRQ mapping enabled (0) or disabled (1) 481 * bits [6:4] reserved (sometimes used for onchip devices) 482 * bits [3:0] IRQ to map to 483 * allowed: 3-7, 9-12, 14-15 484 * reserved: 0, 1, 2, 8, 13 485 * 486 * The config-space registers located at 0x41/0x42/0x43/0x44 are 487 * always used to route the normal PCI INT A/B/C/D respectively. 488 * Apparently there are systems implementing PCI routing table using 489 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D. 490 * We try our best to handle both link mappings. 491 * 492 * Currently (2003-05-21) it appears most SiS chipsets follow the 493 * definition of routing registers from the SiS-5595 southbridge. 494 * According to the SiS 5595 datasheets the revision id's of the 495 * router (ISA-bridge) should be 0x01 or 0xb0. 496 * 497 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1. 498 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets. 499 * They seem to work with the current routing code. However there is 500 * some concern because of the two USB-OHCI HCs (original SiS 5595 501 * had only one). YMMV. 502 * 503 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1: 504 * 505 * 0x61: IDEIRQ: 506 * bits [6:5] must be written 01 507 * bit 4 channel-select primary (0), secondary (1) 508 * 509 * 0x62: USBIRQ: 510 * bit 6 OHCI function disabled (0), enabled (1) 511 * 512 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved 513 * 514 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved 515 * 516 * We support USBIRQ (in addition to INTA-INTD) and keep the 517 * IDE, ACPI and DAQ routing untouched as set by the BIOS. 518 * 519 * Currently the only reported exception is the new SiS 65x chipset 520 * which includes the SiS 69x southbridge. Here we have the 85C503 521 * router revision 0x04 and there are changes in the register layout 522 * mostly related to the different USB HCs with USB 2.0 support. 523 * 524 * Onchip routing for router rev-id 0x04 (try-and-error observation) 525 * 526 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs 527 * bit 6-4 are probably unused, not like 5595 528 */ 529 530 #define PIRQ_SIS_IRQ_MASK 0x0f 531 #define PIRQ_SIS_IRQ_DISABLE 0x80 532 #define PIRQ_SIS_USB_ENABLE 0x40 533 534 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 535 { 536 u8 x; 537 int reg; 538 539 reg = pirq; 540 if (reg >= 0x01 && reg <= 0x04) 541 reg += 0x40; 542 pci_read_config_byte(router, reg, &x); 543 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK); 544 } 545 546 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 547 { 548 u8 x; 549 int reg; 550 551 reg = pirq; 552 if (reg >= 0x01 && reg <= 0x04) 553 reg += 0x40; 554 pci_read_config_byte(router, reg, &x); 555 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE); 556 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE; 557 pci_write_config_byte(router, reg, x); 558 return 1; 559 } 560 561 562 /* 563 * VLSI: nibble offset 0x74 - educated guess due to routing table and 564 * config space of VLSI 82C534 PCI-bridge/router (1004:0102) 565 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard 566 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6 567 * for the busbridge to the docking station. 568 */ 569 570 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 571 { 572 WARN_ON_ONCE(pirq >= 9); 573 if (pirq > 8) { 574 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq); 575 return 0; 576 } 577 return read_config_nybble(router, 0x74, pirq-1); 578 } 579 580 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 581 { 582 WARN_ON_ONCE(pirq >= 9); 583 if (pirq > 8) { 584 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq); 585 return 0; 586 } 587 write_config_nybble(router, 0x74, pirq-1, irq); 588 return 1; 589 } 590 591 /* 592 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index 593 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register 594 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect 595 * register is a straight binary coding of desired PIC IRQ (low nibble). 596 * 597 * The 'link' value in the PIRQ table is already in the correct format 598 * for the Index register. There are some special index values: 599 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1, 600 * and 0x03 for SMBus. 601 */ 602 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 603 { 604 outb(pirq, 0xc00); 605 return inb(0xc01) & 0xf; 606 } 607 608 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, 609 int pirq, int irq) 610 { 611 outb(pirq, 0xc00); 612 outb(irq, 0xc01); 613 return 1; 614 } 615 616 /* Support for AMD756 PCI IRQ Routing 617 * Jhon H. Caicedo <jhcaiced@osso.org.co> 618 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced) 619 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced) 620 * The AMD756 pirq rules are nibble-based 621 * offset 0x56 0-3 PIRQA 4-7 PIRQB 622 * offset 0x57 0-3 PIRQC 4-7 PIRQD 623 */ 624 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 625 { 626 u8 irq; 627 irq = 0; 628 if (pirq <= 4) 629 irq = read_config_nybble(router, 0x56, pirq - 1); 630 dev_info(&dev->dev, 631 "AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d\n", 632 dev->vendor, dev->device, pirq, irq); 633 return irq; 634 } 635 636 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 637 { 638 dev_info(&dev->dev, 639 "AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d\n", 640 dev->vendor, dev->device, pirq, irq); 641 if (pirq <= 4) 642 write_config_nybble(router, 0x56, pirq - 1, irq); 643 return 1; 644 } 645 646 /* 647 * PicoPower PT86C523 648 */ 649 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 650 { 651 outb(0x10 + ((pirq - 1) >> 1), 0x24); 652 return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf); 653 } 654 655 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq, 656 int irq) 657 { 658 unsigned int x; 659 outb(0x10 + ((pirq - 1) >> 1), 0x24); 660 x = inb(0x26); 661 x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq)); 662 outb(x, 0x26); 663 return 1; 664 } 665 666 #ifdef CONFIG_PCI_BIOS 667 668 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 669 { 670 struct pci_dev *bridge; 671 int pin = pci_get_interrupt_pin(dev, &bridge); 672 return pcibios_set_irq_routing(bridge, pin - 1, irq); 673 } 674 675 #endif 676 677 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 678 { 679 static struct pci_device_id __initdata pirq_440gx[] = { 680 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) }, 681 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) }, 682 { }, 683 }; 684 685 /* 440GX has a proprietary PIRQ router -- don't use it */ 686 if (pci_dev_present(pirq_440gx)) 687 return 0; 688 689 switch (device) { 690 case PCI_DEVICE_ID_INTEL_82371FB_0: 691 case PCI_DEVICE_ID_INTEL_82371SB_0: 692 case PCI_DEVICE_ID_INTEL_82371AB_0: 693 case PCI_DEVICE_ID_INTEL_82371MX: 694 case PCI_DEVICE_ID_INTEL_82443MX_0: 695 case PCI_DEVICE_ID_INTEL_82801AA_0: 696 case PCI_DEVICE_ID_INTEL_82801AB_0: 697 case PCI_DEVICE_ID_INTEL_82801BA_0: 698 case PCI_DEVICE_ID_INTEL_82801BA_10: 699 case PCI_DEVICE_ID_INTEL_82801CA_0: 700 case PCI_DEVICE_ID_INTEL_82801CA_12: 701 case PCI_DEVICE_ID_INTEL_82801DB_0: 702 case PCI_DEVICE_ID_INTEL_82801E_0: 703 case PCI_DEVICE_ID_INTEL_82801EB_0: 704 case PCI_DEVICE_ID_INTEL_ESB_1: 705 case PCI_DEVICE_ID_INTEL_ICH6_0: 706 case PCI_DEVICE_ID_INTEL_ICH6_1: 707 case PCI_DEVICE_ID_INTEL_ICH7_0: 708 case PCI_DEVICE_ID_INTEL_ICH7_1: 709 case PCI_DEVICE_ID_INTEL_ICH7_30: 710 case PCI_DEVICE_ID_INTEL_ICH7_31: 711 case PCI_DEVICE_ID_INTEL_TGP_LPC: 712 case PCI_DEVICE_ID_INTEL_ESB2_0: 713 case PCI_DEVICE_ID_INTEL_ICH8_0: 714 case PCI_DEVICE_ID_INTEL_ICH8_1: 715 case PCI_DEVICE_ID_INTEL_ICH8_2: 716 case PCI_DEVICE_ID_INTEL_ICH8_3: 717 case PCI_DEVICE_ID_INTEL_ICH8_4: 718 case PCI_DEVICE_ID_INTEL_ICH9_0: 719 case PCI_DEVICE_ID_INTEL_ICH9_1: 720 case PCI_DEVICE_ID_INTEL_ICH9_2: 721 case PCI_DEVICE_ID_INTEL_ICH9_3: 722 case PCI_DEVICE_ID_INTEL_ICH9_4: 723 case PCI_DEVICE_ID_INTEL_ICH9_5: 724 case PCI_DEVICE_ID_INTEL_EP80579_0: 725 case PCI_DEVICE_ID_INTEL_ICH10_0: 726 case PCI_DEVICE_ID_INTEL_ICH10_1: 727 case PCI_DEVICE_ID_INTEL_ICH10_2: 728 case PCI_DEVICE_ID_INTEL_ICH10_3: 729 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0: 730 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1: 731 r->name = "PIIX/ICH"; 732 r->get = pirq_piix_get; 733 r->set = pirq_piix_set; 734 return 1; 735 } 736 737 if ((device >= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN && 738 device <= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX) 739 || (device >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && 740 device <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) 741 || (device >= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN && 742 device <= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX) 743 || (device >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && 744 device <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) { 745 r->name = "PIIX/ICH"; 746 r->get = pirq_piix_get; 747 r->set = pirq_piix_set; 748 return 1; 749 } 750 751 return 0; 752 } 753 754 static __init int via_router_probe(struct irq_router *r, 755 struct pci_dev *router, u16 device) 756 { 757 /* FIXME: We should move some of the quirk fixup stuff here */ 758 759 /* 760 * workarounds for some buggy BIOSes 761 */ 762 if (device == PCI_DEVICE_ID_VIA_82C586_0) { 763 switch (router->device) { 764 case PCI_DEVICE_ID_VIA_82C686: 765 /* 766 * Asus k7m bios wrongly reports 82C686A 767 * as 586-compatible 768 */ 769 device = PCI_DEVICE_ID_VIA_82C686; 770 break; 771 case PCI_DEVICE_ID_VIA_8235: 772 /** 773 * Asus a7v-x bios wrongly reports 8235 774 * as 586-compatible 775 */ 776 device = PCI_DEVICE_ID_VIA_8235; 777 break; 778 case PCI_DEVICE_ID_VIA_8237: 779 /** 780 * Asus a7v600 bios wrongly reports 8237 781 * as 586-compatible 782 */ 783 device = PCI_DEVICE_ID_VIA_8237; 784 break; 785 } 786 } 787 788 switch (device) { 789 case PCI_DEVICE_ID_VIA_82C586_0: 790 r->name = "VIA"; 791 r->get = pirq_via586_get; 792 r->set = pirq_via586_set; 793 return 1; 794 case PCI_DEVICE_ID_VIA_82C596: 795 case PCI_DEVICE_ID_VIA_82C686: 796 case PCI_DEVICE_ID_VIA_8231: 797 case PCI_DEVICE_ID_VIA_8233A: 798 case PCI_DEVICE_ID_VIA_8235: 799 case PCI_DEVICE_ID_VIA_8237: 800 /* FIXME: add new ones for 8233/5 */ 801 r->name = "VIA"; 802 r->get = pirq_via_get; 803 r->set = pirq_via_set; 804 return 1; 805 } 806 return 0; 807 } 808 809 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 810 { 811 switch (device) { 812 case PCI_DEVICE_ID_VLSI_82C534: 813 r->name = "VLSI 82C534"; 814 r->get = pirq_vlsi_get; 815 r->set = pirq_vlsi_set; 816 return 1; 817 } 818 return 0; 819 } 820 821 822 static __init int serverworks_router_probe(struct irq_router *r, 823 struct pci_dev *router, u16 device) 824 { 825 switch (device) { 826 case PCI_DEVICE_ID_SERVERWORKS_OSB4: 827 case PCI_DEVICE_ID_SERVERWORKS_CSB5: 828 r->name = "ServerWorks"; 829 r->get = pirq_serverworks_get; 830 r->set = pirq_serverworks_set; 831 return 1; 832 } 833 return 0; 834 } 835 836 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 837 { 838 if (device != PCI_DEVICE_ID_SI_503) 839 return 0; 840 841 r->name = "SIS"; 842 r->get = pirq_sis_get; 843 r->set = pirq_sis_set; 844 return 1; 845 } 846 847 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 848 { 849 switch (device) { 850 case PCI_DEVICE_ID_CYRIX_5520: 851 r->name = "NatSemi"; 852 r->get = pirq_cyrix_get; 853 r->set = pirq_cyrix_set; 854 return 1; 855 } 856 return 0; 857 } 858 859 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 860 { 861 switch (device) { 862 case PCI_DEVICE_ID_OPTI_82C700: 863 r->name = "OPTI"; 864 r->get = pirq_opti_get; 865 r->set = pirq_opti_set; 866 return 1; 867 } 868 return 0; 869 } 870 871 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 872 { 873 switch (device) { 874 case PCI_DEVICE_ID_ITE_IT8330G_0: 875 r->name = "ITE"; 876 r->get = pirq_ite_get; 877 r->set = pirq_ite_set; 878 return 1; 879 } 880 return 0; 881 } 882 883 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 884 { 885 switch (device) { 886 case PCI_DEVICE_ID_AL_M1489: 887 r->name = "FinALi"; 888 r->get = pirq_finali_get; 889 r->set = pirq_finali_set; 890 r->lvl = pirq_finali_lvl; 891 return 1; 892 case PCI_DEVICE_ID_AL_M1533: 893 case PCI_DEVICE_ID_AL_M1563: 894 r->name = "ALI"; 895 r->get = pirq_ali_get; 896 r->set = pirq_ali_set; 897 return 1; 898 } 899 return 0; 900 } 901 902 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 903 { 904 switch (device) { 905 case PCI_DEVICE_ID_AMD_VIPER_740B: 906 r->name = "AMD756"; 907 break; 908 case PCI_DEVICE_ID_AMD_VIPER_7413: 909 r->name = "AMD766"; 910 break; 911 case PCI_DEVICE_ID_AMD_VIPER_7443: 912 r->name = "AMD768"; 913 break; 914 default: 915 return 0; 916 } 917 r->get = pirq_amd756_get; 918 r->set = pirq_amd756_set; 919 return 1; 920 } 921 922 static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 923 { 924 switch (device) { 925 case PCI_DEVICE_ID_PICOPOWER_PT86C523: 926 r->name = "PicoPower PT86C523"; 927 r->get = pirq_pico_get; 928 r->set = pirq_pico_set; 929 return 1; 930 931 case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP: 932 r->name = "PicoPower PT86C523 rev. BB+"; 933 r->get = pirq_pico_get; 934 r->set = pirq_pico_set; 935 return 1; 936 } 937 return 0; 938 } 939 940 static __initdata struct irq_router_handler pirq_routers[] = { 941 { PCI_VENDOR_ID_INTEL, intel_router_probe }, 942 { PCI_VENDOR_ID_AL, ali_router_probe }, 943 { PCI_VENDOR_ID_ITE, ite_router_probe }, 944 { PCI_VENDOR_ID_VIA, via_router_probe }, 945 { PCI_VENDOR_ID_OPTI, opti_router_probe }, 946 { PCI_VENDOR_ID_SI, sis_router_probe }, 947 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe }, 948 { PCI_VENDOR_ID_VLSI, vlsi_router_probe }, 949 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe }, 950 { PCI_VENDOR_ID_AMD, amd_router_probe }, 951 { PCI_VENDOR_ID_PICOPOWER, pico_router_probe }, 952 /* Someone with docs needs to add the ATI Radeon IGP */ 953 { 0, NULL } 954 }; 955 static struct irq_router pirq_router; 956 static struct pci_dev *pirq_router_dev; 957 958 959 /* 960 * FIXME: should we have an option to say "generic for 961 * chipset" ? 962 */ 963 964 static void __init pirq_find_router(struct irq_router *r) 965 { 966 struct irq_routing_table *rt = pirq_table; 967 struct irq_router_handler *h; 968 969 #ifdef CONFIG_PCI_BIOS 970 if (!rt->signature) { 971 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n"); 972 r->set = pirq_bios_set; 973 r->name = "BIOS"; 974 return; 975 } 976 #endif 977 978 /* Default unless a driver reloads it */ 979 r->name = "default"; 980 r->get = NULL; 981 r->set = NULL; 982 983 DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n", 984 rt->rtr_vendor, rt->rtr_device); 985 986 pirq_router_dev = pci_get_domain_bus_and_slot(0, rt->rtr_bus, 987 rt->rtr_devfn); 988 if (!pirq_router_dev) { 989 DBG(KERN_DEBUG "PCI: Interrupt router not found at " 990 "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn); 991 return; 992 } 993 994 for (h = pirq_routers; h->vendor; h++) { 995 /* First look for a router match */ 996 if (rt->rtr_vendor == h->vendor && 997 h->probe(r, pirq_router_dev, rt->rtr_device)) 998 break; 999 /* Fall back to a device match */ 1000 if (pirq_router_dev->vendor == h->vendor && 1001 h->probe(r, pirq_router_dev, pirq_router_dev->device)) 1002 break; 1003 } 1004 dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x:%04x]\n", 1005 pirq_router.name, 1006 pirq_router_dev->vendor, pirq_router_dev->device); 1007 1008 /* The device remains referenced for the kernel lifetime */ 1009 } 1010 1011 static struct irq_info *pirq_get_info(struct pci_dev *dev) 1012 { 1013 struct irq_routing_table *rt = pirq_table; 1014 int entries = (rt->size - sizeof(struct irq_routing_table)) / 1015 sizeof(struct irq_info); 1016 struct irq_info *info; 1017 1018 for (info = rt->slots; entries--; info++) 1019 if (info->bus == dev->bus->number && 1020 PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn)) 1021 return info; 1022 return NULL; 1023 } 1024 1025 static int pcibios_lookup_irq(struct pci_dev *dev, int assign) 1026 { 1027 u8 pin; 1028 struct irq_info *info; 1029 int i, pirq, newirq; 1030 int irq = 0; 1031 u32 mask; 1032 struct irq_router *r = &pirq_router; 1033 struct pci_dev *dev2 = NULL; 1034 char *msg = NULL; 1035 1036 /* Find IRQ pin */ 1037 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1038 if (!pin) { 1039 dev_dbg(&dev->dev, "no interrupt pin\n"); 1040 return 0; 1041 } 1042 1043 if (io_apic_assign_pci_irqs) 1044 return 0; 1045 1046 /* Find IRQ routing entry */ 1047 1048 if (!pirq_table) 1049 return 0; 1050 1051 info = pirq_get_info(dev); 1052 if (!info) { 1053 dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n", 1054 'A' + pin - 1); 1055 return 0; 1056 } 1057 pirq = info->irq[pin - 1].link; 1058 mask = info->irq[pin - 1].bitmap; 1059 if (!pirq) { 1060 dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin - 1); 1061 return 0; 1062 } 1063 dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x", 1064 'A' + pin - 1, pirq, mask, pirq_table->exclusive_irqs); 1065 mask &= pcibios_irq_mask; 1066 1067 /* Work around broken HP Pavilion Notebooks which assign USB to 1068 IRQ 9 even though it is actually wired to IRQ 11 */ 1069 1070 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) { 1071 dev->irq = 11; 1072 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11); 1073 r->set(pirq_router_dev, dev, pirq, 11); 1074 } 1075 1076 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */ 1077 if (acer_tm360_irqrouting && dev->irq == 11 && 1078 dev->vendor == PCI_VENDOR_ID_O2) { 1079 pirq = 0x68; 1080 mask = 0x400; 1081 dev->irq = r->get(pirq_router_dev, dev, pirq); 1082 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 1083 } 1084 1085 /* 1086 * Find the best IRQ to assign: use the one 1087 * reported by the device if possible. 1088 */ 1089 newirq = dev->irq; 1090 if (newirq && !((1 << newirq) & mask)) { 1091 if (pci_probe & PCI_USE_PIRQ_MASK) 1092 newirq = 0; 1093 else 1094 dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask " 1095 "%#x; try pci=usepirqmask\n", newirq, mask); 1096 } 1097 if (!newirq && assign) { 1098 for (i = 0; i < 16; i++) { 1099 if (!(mask & (1 << i))) 1100 continue; 1101 if (pirq_penalty[i] < pirq_penalty[newirq] && 1102 can_request_irq(i, IRQF_SHARED)) 1103 newirq = i; 1104 } 1105 } 1106 dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + pin - 1, newirq); 1107 1108 /* Check if it is hardcoded */ 1109 if ((pirq & 0xf0) == 0xf0) { 1110 irq = pirq & 0xf; 1111 msg = "hardcoded"; 1112 } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \ 1113 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) { 1114 msg = "found"; 1115 if (r->lvl) 1116 r->lvl(pirq_router_dev, dev, pirq, irq); 1117 else 1118 elcr_set_level_irq(irq); 1119 } else if (newirq && r->set && 1120 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) { 1121 if (r->set(pirq_router_dev, dev, pirq, newirq)) { 1122 if (r->lvl) 1123 r->lvl(pirq_router_dev, dev, pirq, newirq); 1124 else 1125 elcr_set_level_irq(newirq); 1126 msg = "assigned"; 1127 irq = newirq; 1128 } 1129 } 1130 1131 if (!irq) { 1132 if (newirq && mask == (1 << newirq)) { 1133 msg = "guessed"; 1134 irq = newirq; 1135 } else { 1136 dev_dbg(&dev->dev, "can't route interrupt\n"); 1137 return 0; 1138 } 1139 } 1140 dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin - 1, irq); 1141 1142 /* Update IRQ for all devices with the same pirq value */ 1143 for_each_pci_dev(dev2) { 1144 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin); 1145 if (!pin) 1146 continue; 1147 1148 info = pirq_get_info(dev2); 1149 if (!info) 1150 continue; 1151 if (info->irq[pin - 1].link == pirq) { 1152 /* 1153 * We refuse to override the dev->irq 1154 * information. Give a warning! 1155 */ 1156 if (dev2->irq && dev2->irq != irq && \ 1157 (!(pci_probe & PCI_USE_PIRQ_MASK) || \ 1158 ((1 << dev2->irq) & mask))) { 1159 #ifndef CONFIG_PCI_MSI 1160 dev_info(&dev2->dev, "IRQ routing conflict: " 1161 "have IRQ %d, want IRQ %d\n", 1162 dev2->irq, irq); 1163 #endif 1164 continue; 1165 } 1166 dev2->irq = irq; 1167 pirq_penalty[irq]++; 1168 if (dev != dev2) 1169 dev_info(&dev->dev, "sharing IRQ %d with %s\n", 1170 irq, pci_name(dev2)); 1171 } 1172 } 1173 return 1; 1174 } 1175 1176 void __init pcibios_fixup_irqs(void) 1177 { 1178 struct pci_dev *dev = NULL; 1179 u8 pin; 1180 1181 DBG(KERN_DEBUG "PCI: IRQ fixup\n"); 1182 for_each_pci_dev(dev) { 1183 /* 1184 * If the BIOS has set an out of range IRQ number, just 1185 * ignore it. Also keep track of which IRQ's are 1186 * already in use. 1187 */ 1188 if (dev->irq >= 16) { 1189 dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq); 1190 dev->irq = 0; 1191 } 1192 /* 1193 * If the IRQ is already assigned to a PCI device, 1194 * ignore its ISA use penalty 1195 */ 1196 if (pirq_penalty[dev->irq] >= 100 && 1197 pirq_penalty[dev->irq] < 100000) 1198 pirq_penalty[dev->irq] = 0; 1199 pirq_penalty[dev->irq]++; 1200 } 1201 1202 if (io_apic_assign_pci_irqs) 1203 return; 1204 1205 dev = NULL; 1206 for_each_pci_dev(dev) { 1207 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1208 if (!pin) 1209 continue; 1210 1211 /* 1212 * Still no IRQ? Try to lookup one... 1213 */ 1214 if (!dev->irq) 1215 pcibios_lookup_irq(dev, 0); 1216 } 1217 } 1218 1219 /* 1220 * Work around broken HP Pavilion Notebooks which assign USB to 1221 * IRQ 9 even though it is actually wired to IRQ 11 1222 */ 1223 static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d) 1224 { 1225 if (!broken_hp_bios_irq9) { 1226 broken_hp_bios_irq9 = 1; 1227 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", 1228 d->ident); 1229 } 1230 return 0; 1231 } 1232 1233 /* 1234 * Work around broken Acer TravelMate 360 Notebooks which assign 1235 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10 1236 */ 1237 static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d) 1238 { 1239 if (!acer_tm360_irqrouting) { 1240 acer_tm360_irqrouting = 1; 1241 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", 1242 d->ident); 1243 } 1244 return 0; 1245 } 1246 1247 static const struct dmi_system_id pciirq_dmi_table[] __initconst = { 1248 { 1249 .callback = fix_broken_hp_bios_irq9, 1250 .ident = "HP Pavilion N5400 Series Laptop", 1251 .matches = { 1252 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1253 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"), 1254 DMI_MATCH(DMI_PRODUCT_VERSION, 1255 "HP Pavilion Notebook Model GE"), 1256 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"), 1257 }, 1258 }, 1259 { 1260 .callback = fix_acer_tm360_irqrouting, 1261 .ident = "Acer TravelMate 36x Laptop", 1262 .matches = { 1263 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1264 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"), 1265 }, 1266 }, 1267 { } 1268 }; 1269 1270 void __init pcibios_irq_init(void) 1271 { 1272 struct irq_routing_table *rtable = NULL; 1273 1274 DBG(KERN_DEBUG "PCI: IRQ init\n"); 1275 1276 if (raw_pci_ops == NULL) 1277 return; 1278 1279 dmi_check_system(pciirq_dmi_table); 1280 1281 pirq_table = pirq_find_routing_table(); 1282 1283 #ifdef CONFIG_PCI_BIOS 1284 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN)) { 1285 pirq_table = pcibios_get_irq_routing_table(); 1286 rtable = pirq_table; 1287 } 1288 #endif 1289 if (pirq_table) { 1290 pirq_peer_trick(); 1291 pirq_find_router(&pirq_router); 1292 if (pirq_table->exclusive_irqs) { 1293 int i; 1294 for (i = 0; i < 16; i++) 1295 if (!(pirq_table->exclusive_irqs & (1 << i))) 1296 pirq_penalty[i] += 100; 1297 } 1298 /* 1299 * If we're using the I/O APIC, avoid using the PCI IRQ 1300 * routing table 1301 */ 1302 if (io_apic_assign_pci_irqs) { 1303 kfree(rtable); 1304 pirq_table = NULL; 1305 } 1306 } 1307 1308 x86_init.pci.fixup_irqs(); 1309 1310 if (io_apic_assign_pci_irqs && pci_routeirq) { 1311 struct pci_dev *dev = NULL; 1312 /* 1313 * PCI IRQ routing is set up by pci_enable_device(), but we 1314 * also do it here in case there are still broken drivers that 1315 * don't use pci_enable_device(). 1316 */ 1317 printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n"); 1318 for_each_pci_dev(dev) 1319 pirq_enable_irq(dev); 1320 } 1321 } 1322 1323 static void pirq_penalize_isa_irq(int irq, int active) 1324 { 1325 /* 1326 * If any ISAPnP device reports an IRQ in its list of possible 1327 * IRQ's, we try to avoid assigning it to PCI devices. 1328 */ 1329 if (irq < 16) { 1330 if (active) 1331 pirq_penalty[irq] += 1000; 1332 else 1333 pirq_penalty[irq] += 100; 1334 } 1335 } 1336 1337 void pcibios_penalize_isa_irq(int irq, int active) 1338 { 1339 #ifdef CONFIG_ACPI 1340 if (!acpi_noirq) 1341 acpi_penalize_isa_irq(irq, active); 1342 else 1343 #endif 1344 pirq_penalize_isa_irq(irq, active); 1345 } 1346 1347 static int pirq_enable_irq(struct pci_dev *dev) 1348 { 1349 u8 pin = 0; 1350 1351 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1352 if (pin && !pcibios_lookup_irq(dev, 1)) { 1353 char *msg = ""; 1354 1355 if (!io_apic_assign_pci_irqs && dev->irq) 1356 return 0; 1357 1358 if (io_apic_assign_pci_irqs) { 1359 #ifdef CONFIG_X86_IO_APIC 1360 struct pci_dev *temp_dev; 1361 int irq; 1362 1363 if (dev->irq_managed && dev->irq > 0) 1364 return 0; 1365 1366 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, 1367 PCI_SLOT(dev->devfn), pin - 1); 1368 /* 1369 * Busses behind bridges are typically not listed in the MP-table. 1370 * In this case we have to look up the IRQ based on the parent bus, 1371 * parent slot, and pin number. The SMP code detects such bridged 1372 * busses itself so we should get into this branch reliably. 1373 */ 1374 temp_dev = dev; 1375 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */ 1376 struct pci_dev *bridge = dev->bus->self; 1377 1378 pin = pci_swizzle_interrupt_pin(dev, pin); 1379 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, 1380 PCI_SLOT(bridge->devfn), 1381 pin - 1); 1382 if (irq >= 0) 1383 dev_warn(&dev->dev, "using bridge %s " 1384 "INT %c to get IRQ %d\n", 1385 pci_name(bridge), 'A' + pin - 1, 1386 irq); 1387 dev = bridge; 1388 } 1389 dev = temp_dev; 1390 if (irq >= 0) { 1391 dev->irq_managed = 1; 1392 dev->irq = irq; 1393 dev_info(&dev->dev, "PCI->APIC IRQ transform: " 1394 "INT %c -> IRQ %d\n", 'A' + pin - 1, irq); 1395 return 0; 1396 } else 1397 msg = "; probably buggy MP table"; 1398 #endif 1399 } else if (pci_probe & PCI_BIOS_IRQ_SCAN) 1400 msg = ""; 1401 else 1402 msg = "; please try using pci=biosirq"; 1403 1404 /* 1405 * With IDE legacy devices the IRQ lookup failure is not 1406 * a problem.. 1407 */ 1408 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && 1409 !(dev->class & 0x5)) 1410 return 0; 1411 1412 dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n", 1413 'A' + pin - 1, msg); 1414 } 1415 return 0; 1416 } 1417 1418 bool mp_should_keep_irq(struct device *dev) 1419 { 1420 if (dev->power.is_prepared) 1421 return true; 1422 #ifdef CONFIG_PM 1423 if (dev->power.runtime_status == RPM_SUSPENDING) 1424 return true; 1425 #endif 1426 1427 return false; 1428 } 1429 1430 static void pirq_disable_irq(struct pci_dev *dev) 1431 { 1432 if (io_apic_assign_pci_irqs && !mp_should_keep_irq(&dev->dev) && 1433 dev->irq_managed && dev->irq) { 1434 mp_unmap_irq(dev->irq); 1435 dev->irq = 0; 1436 dev->irq_managed = 0; 1437 } 1438 } 1439