1 /* 2 * Low-Level PCI Access for i386 machines 3 * 4 * Copyright 1993, 1994 Drew Eckhardt 5 * Visionary Computing 6 * (Unix and Linux consulting and custom programming) 7 * Drew@Colorado.EDU 8 * +1 (303) 786-7975 9 * 10 * Drew's work was sponsored by: 11 * iX Multiuser Multitasking Magazine 12 * Hannover, Germany 13 * hm@ix.de 14 * 15 * Copyright 1997--2000 Martin Mares <mj@ucw.cz> 16 * 17 * For more information, please consult the following manuals (look at 18 * http://www.pcisig.com/ for how to get them): 19 * 20 * PCI BIOS Specification 21 * PCI Local Bus Specification 22 * PCI to PCI Bridge Specification 23 * PCI System Design Guide 24 * 25 */ 26 27 #include <linux/types.h> 28 #include <linux/kernel.h> 29 #include <linux/pci.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/errno.h> 33 #include <linux/bootmem.h> 34 35 #include <asm/pat.h> 36 37 #include "pci.h" 38 39 static int 40 skip_isa_ioresource_align(struct pci_dev *dev) { 41 42 if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) && 43 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 44 return 1; 45 return 0; 46 } 47 48 /* 49 * We need to avoid collisions with `mirrored' VGA ports 50 * and other strange ISA hardware, so we always want the 51 * addresses to be allocated in the 0x000-0x0ff region 52 * modulo 0x400. 53 * 54 * Why? Because some silly external IO cards only decode 55 * the low 10 bits of the IO address. The 0x00-0xff region 56 * is reserved for motherboard devices that decode all 16 57 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 58 * but we want to try to avoid allocating at 0x2900-0x2bff 59 * which might have be mirrored at 0x0100-0x03ff.. 60 */ 61 void 62 pcibios_align_resource(void *data, struct resource *res, 63 resource_size_t size, resource_size_t align) 64 { 65 struct pci_dev *dev = data; 66 67 if (res->flags & IORESOURCE_IO) { 68 resource_size_t start = res->start; 69 70 if (skip_isa_ioresource_align(dev)) 71 return; 72 if (start & 0x300) { 73 start = (start + 0x3ff) & ~0x3ff; 74 res->start = start; 75 } 76 } 77 } 78 EXPORT_SYMBOL(pcibios_align_resource); 79 80 /* 81 * Handle resources of PCI devices. If the world were perfect, we could 82 * just allocate all the resource regions and do nothing more. It isn't. 83 * On the other hand, we cannot just re-allocate all devices, as it would 84 * require us to know lots of host bridge internals. So we attempt to 85 * keep as much of the original configuration as possible, but tweak it 86 * when it's found to be wrong. 87 * 88 * Known BIOS problems we have to work around: 89 * - I/O or memory regions not configured 90 * - regions configured, but not enabled in the command register 91 * - bogus I/O addresses above 64K used 92 * - expansion ROMs left enabled (this may sound harmless, but given 93 * the fact the PCI specs explicitly allow address decoders to be 94 * shared between expansion ROMs and other resource regions, it's 95 * at least dangerous) 96 * 97 * Our solution: 98 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 99 * This gives us fixed barriers on where we can allocate. 100 * (2) Allocate resources for all enabled devices. If there is 101 * a collision, just mark the resource as unallocated. Also 102 * disable expansion ROMs during this step. 103 * (3) Try to allocate resources for disabled devices. If the 104 * resources were assigned correctly, everything goes well, 105 * if they weren't, they won't disturb allocation of other 106 * resources. 107 * (4) Assign new addresses to resources which were either 108 * not configured at all or misconfigured. If explicitly 109 * requested by the user, configure expansion ROM address 110 * as well. 111 */ 112 113 static void __init pcibios_allocate_bus_resources(struct list_head *bus_list) 114 { 115 struct pci_bus *bus; 116 struct pci_dev *dev; 117 int idx; 118 struct resource *r, *pr; 119 120 /* Depth-First Search on bus tree */ 121 list_for_each_entry(bus, bus_list, node) { 122 if ((dev = bus->self)) { 123 for (idx = PCI_BRIDGE_RESOURCES; 124 idx < PCI_NUM_RESOURCES; idx++) { 125 r = &dev->resource[idx]; 126 if (!r->flags) 127 continue; 128 pr = pci_find_parent_resource(dev, r); 129 if (!r->start || !pr || 130 request_resource(pr, r) < 0) { 131 printk(KERN_ERR "PCI: Cannot allocate " 132 "resource region %d " 133 "of bridge %s\n", 134 idx, pci_name(dev)); 135 /* 136 * Something is wrong with the region. 137 * Invalidate the resource to prevent 138 * child resource allocations in this 139 * range. 140 */ 141 r->flags = 0; 142 } 143 } 144 } 145 pcibios_allocate_bus_resources(&bus->children); 146 } 147 } 148 149 static void __init pcibios_allocate_resources(int pass) 150 { 151 struct pci_dev *dev = NULL; 152 int idx, disabled; 153 u16 command; 154 struct resource *r, *pr; 155 156 for_each_pci_dev(dev) { 157 pci_read_config_word(dev, PCI_COMMAND, &command); 158 for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) { 159 r = &dev->resource[idx]; 160 if (r->parent) /* Already allocated */ 161 continue; 162 if (!r->start) /* Address not assigned at all */ 163 continue; 164 if (r->flags & IORESOURCE_IO) 165 disabled = !(command & PCI_COMMAND_IO); 166 else 167 disabled = !(command & PCI_COMMAND_MEMORY); 168 if (pass == disabled) { 169 DBG("PCI: Resource %08lx-%08lx " 170 "(f=%lx, d=%d, p=%d)\n", 171 r->start, r->end, r->flags, disabled, pass); 172 pr = pci_find_parent_resource(dev, r); 173 if (!pr || request_resource(pr, r) < 0) { 174 printk(KERN_ERR "PCI: Cannot allocate " 175 "resource region %d " 176 "of device %s\n", 177 idx, pci_name(dev)); 178 /* We'll assign a new address later */ 179 r->end -= r->start; 180 r->start = 0; 181 } 182 } 183 } 184 if (!pass) { 185 r = &dev->resource[PCI_ROM_RESOURCE]; 186 if (r->flags & IORESOURCE_ROM_ENABLE) { 187 /* Turn the ROM off, leave the resource region, 188 * but keep it unregistered. */ 189 u32 reg; 190 DBG("PCI: Switching off ROM of %s\n", 191 pci_name(dev)); 192 r->flags &= ~IORESOURCE_ROM_ENABLE; 193 pci_read_config_dword(dev, 194 dev->rom_base_reg, ®); 195 pci_write_config_dword(dev, dev->rom_base_reg, 196 reg & ~PCI_ROM_ADDRESS_ENABLE); 197 } 198 } 199 } 200 } 201 202 static int __init pcibios_assign_resources(void) 203 { 204 struct pci_dev *dev = NULL; 205 struct resource *r, *pr; 206 207 if (!(pci_probe & PCI_ASSIGN_ROMS)) { 208 /* 209 * Try to use BIOS settings for ROMs, otherwise let 210 * pci_assign_unassigned_resources() allocate the new 211 * addresses. 212 */ 213 for_each_pci_dev(dev) { 214 r = &dev->resource[PCI_ROM_RESOURCE]; 215 if (!r->flags || !r->start) 216 continue; 217 pr = pci_find_parent_resource(dev, r); 218 if (!pr || request_resource(pr, r) < 0) { 219 r->end -= r->start; 220 r->start = 0; 221 } 222 } 223 } 224 225 pci_assign_unassigned_resources(); 226 227 return 0; 228 } 229 230 void __init pcibios_resource_survey(void) 231 { 232 DBG("PCI: Allocating resources\n"); 233 pcibios_allocate_bus_resources(&pci_root_buses); 234 pcibios_allocate_resources(0); 235 pcibios_allocate_resources(1); 236 } 237 238 /** 239 * called in fs_initcall (one below subsys_initcall), 240 * give a chance for motherboard reserve resources 241 */ 242 fs_initcall(pcibios_assign_resources); 243 244 int pcibios_enable_resources(struct pci_dev *dev, int mask) 245 { 246 u16 cmd, old_cmd; 247 int idx; 248 struct resource *r; 249 250 pci_read_config_word(dev, PCI_COMMAND, &cmd); 251 old_cmd = cmd; 252 for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) { 253 /* Only set up the requested stuff */ 254 if (!(mask & (1 << idx))) 255 continue; 256 257 r = &dev->resource[idx]; 258 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 259 continue; 260 if ((idx == PCI_ROM_RESOURCE) && 261 (!(r->flags & IORESOURCE_ROM_ENABLE))) 262 continue; 263 if (!r->start && r->end) { 264 printk(KERN_ERR "PCI: Device %s not available " 265 "because of resource %d collisions\n", 266 pci_name(dev), idx); 267 return -EINVAL; 268 } 269 if (r->flags & IORESOURCE_IO) 270 cmd |= PCI_COMMAND_IO; 271 if (r->flags & IORESOURCE_MEM) 272 cmd |= PCI_COMMAND_MEMORY; 273 } 274 if (cmd != old_cmd) { 275 printk("PCI: Enabling device %s (%04x -> %04x)\n", 276 pci_name(dev), old_cmd, cmd); 277 pci_write_config_word(dev, PCI_COMMAND, cmd); 278 } 279 return 0; 280 } 281 282 /* 283 * If we set up a device for bus mastering, we need to check the latency 284 * timer as certain crappy BIOSes forget to set it properly. 285 */ 286 unsigned int pcibios_max_latency = 255; 287 288 void pcibios_set_master(struct pci_dev *dev) 289 { 290 u8 lat; 291 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 292 if (lat < 16) 293 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 294 else if (lat > pcibios_max_latency) 295 lat = pcibios_max_latency; 296 else 297 return; 298 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", 299 pci_name(dev), lat); 300 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 301 } 302 303 static void pci_unmap_page_range(struct vm_area_struct *vma) 304 { 305 u64 addr = (u64)vma->vm_pgoff << PAGE_SHIFT; 306 free_memtype(addr, addr + vma->vm_end - vma->vm_start); 307 } 308 309 static void pci_track_mmap_page_range(struct vm_area_struct *vma) 310 { 311 u64 addr = (u64)vma->vm_pgoff << PAGE_SHIFT; 312 unsigned long flags = pgprot_val(vma->vm_page_prot) 313 & _PAGE_CACHE_MASK; 314 315 reserve_memtype(addr, addr + vma->vm_end - vma->vm_start, flags, NULL); 316 } 317 318 static struct vm_operations_struct pci_mmap_ops = { 319 .open = pci_track_mmap_page_range, 320 .close = pci_unmap_page_range, 321 }; 322 323 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 324 enum pci_mmap_state mmap_state, int write_combine) 325 { 326 unsigned long prot; 327 u64 addr = vma->vm_pgoff << PAGE_SHIFT; 328 unsigned long len = vma->vm_end - vma->vm_start; 329 unsigned long flags; 330 unsigned long new_flags; 331 int retval; 332 333 /* I/O space cannot be accessed via normal processor loads and 334 * stores on this platform. 335 */ 336 if (mmap_state == pci_mmap_io) 337 return -EINVAL; 338 339 prot = pgprot_val(vma->vm_page_prot); 340 if (pat_wc_enabled && write_combine) 341 prot |= _PAGE_CACHE_WC; 342 else if (boot_cpu_data.x86 > 3) 343 prot |= _PAGE_CACHE_UC; 344 345 vma->vm_page_prot = __pgprot(prot); 346 347 flags = pgprot_val(vma->vm_page_prot) & _PAGE_CACHE_MASK; 348 retval = reserve_memtype(addr, addr + len, flags, &new_flags); 349 if (retval) 350 return retval; 351 352 if (flags != new_flags) { 353 /* 354 * Do not fallback to certain memory types with certain 355 * requested type: 356 * - request is uncached, return cannot be write-back 357 * - request is uncached, return cannot be write-combine 358 * - request is write-combine, return cannot be write-back 359 */ 360 if ((flags == _PAGE_CACHE_UC && 361 (new_flags == _PAGE_CACHE_WB || 362 new_flags == _PAGE_CACHE_WC)) || 363 (flags == _PAGE_CACHE_WC && 364 new_flags == _PAGE_CACHE_WB)) { 365 free_memtype(addr, addr+len); 366 return -EINVAL; 367 } 368 flags = new_flags; 369 } 370 371 if (vma->vm_pgoff <= max_pfn_mapped && 372 ioremap_change_attr((unsigned long)__va(addr), len, flags)) { 373 free_memtype(addr, addr + len); 374 return -EINVAL; 375 } 376 377 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 378 vma->vm_end - vma->vm_start, 379 vma->vm_page_prot)) 380 return -EAGAIN; 381 382 vma->vm_ops = &pci_mmap_ops; 383 384 return 0; 385 } 386