1 /* 2 * Low-Level PCI Access for i386 machines 3 * 4 * Copyright 1993, 1994 Drew Eckhardt 5 * Visionary Computing 6 * (Unix and Linux consulting and custom programming) 7 * Drew@Colorado.EDU 8 * +1 (303) 786-7975 9 * 10 * Drew's work was sponsored by: 11 * iX Multiuser Multitasking Magazine 12 * Hannover, Germany 13 * hm@ix.de 14 * 15 * Copyright 1997--2000 Martin Mares <mj@ucw.cz> 16 * 17 * For more information, please consult the following manuals (look at 18 * http://www.pcisig.com/ for how to get them): 19 * 20 * PCI BIOS Specification 21 * PCI Local Bus Specification 22 * PCI to PCI Bridge Specification 23 * PCI System Design Guide 24 * 25 */ 26 27 #include <linux/types.h> 28 #include <linux/kernel.h> 29 #include <linux/pci.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/errno.h> 33 34 #include "pci.h" 35 36 static int 37 skip_isa_ioresource_align(struct pci_dev *dev) { 38 39 if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) && 40 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 41 return 1; 42 return 0; 43 } 44 45 /* 46 * We need to avoid collisions with `mirrored' VGA ports 47 * and other strange ISA hardware, so we always want the 48 * addresses to be allocated in the 0x000-0x0ff region 49 * modulo 0x400. 50 * 51 * Why? Because some silly external IO cards only decode 52 * the low 10 bits of the IO address. The 0x00-0xff region 53 * is reserved for motherboard devices that decode all 16 54 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 55 * but we want to try to avoid allocating at 0x2900-0x2bff 56 * which might have be mirrored at 0x0100-0x03ff.. 57 */ 58 void 59 pcibios_align_resource(void *data, struct resource *res, 60 resource_size_t size, resource_size_t align) 61 { 62 struct pci_dev *dev = data; 63 64 if (res->flags & IORESOURCE_IO) { 65 resource_size_t start = res->start; 66 67 if (skip_isa_ioresource_align(dev)) 68 return; 69 if (start & 0x300) { 70 start = (start + 0x3ff) & ~0x3ff; 71 res->start = start; 72 } 73 } 74 } 75 EXPORT_SYMBOL(pcibios_align_resource); 76 77 /* 78 * Handle resources of PCI devices. If the world were perfect, we could 79 * just allocate all the resource regions and do nothing more. It isn't. 80 * On the other hand, we cannot just re-allocate all devices, as it would 81 * require us to know lots of host bridge internals. So we attempt to 82 * keep as much of the original configuration as possible, but tweak it 83 * when it's found to be wrong. 84 * 85 * Known BIOS problems we have to work around: 86 * - I/O or memory regions not configured 87 * - regions configured, but not enabled in the command register 88 * - bogus I/O addresses above 64K used 89 * - expansion ROMs left enabled (this may sound harmless, but given 90 * the fact the PCI specs explicitly allow address decoders to be 91 * shared between expansion ROMs and other resource regions, it's 92 * at least dangerous) 93 * 94 * Our solution: 95 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 96 * This gives us fixed barriers on where we can allocate. 97 * (2) Allocate resources for all enabled devices. If there is 98 * a collision, just mark the resource as unallocated. Also 99 * disable expansion ROMs during this step. 100 * (3) Try to allocate resources for disabled devices. If the 101 * resources were assigned correctly, everything goes well, 102 * if they weren't, they won't disturb allocation of other 103 * resources. 104 * (4) Assign new addresses to resources which were either 105 * not configured at all or misconfigured. If explicitly 106 * requested by the user, configure expansion ROM address 107 * as well. 108 */ 109 110 static void __init pcibios_allocate_bus_resources(struct list_head *bus_list) 111 { 112 struct pci_bus *bus; 113 struct pci_dev *dev; 114 int idx; 115 struct resource *r, *pr; 116 117 /* Depth-First Search on bus tree */ 118 list_for_each_entry(bus, bus_list, node) { 119 if ((dev = bus->self)) { 120 for (idx = PCI_BRIDGE_RESOURCES; 121 idx < PCI_NUM_RESOURCES; idx++) { 122 r = &dev->resource[idx]; 123 if (!r->flags) 124 continue; 125 pr = pci_find_parent_resource(dev, r); 126 if (!r->start || !pr || 127 request_resource(pr, r) < 0) { 128 printk(KERN_ERR "PCI: Cannot allocate " 129 "resource region %d " 130 "of bridge %s\n", 131 idx, pci_name(dev)); 132 /* 133 * Something is wrong with the region. 134 * Invalidate the resource to prevent 135 * child resource allocations in this 136 * range. 137 */ 138 r->flags = 0; 139 } 140 } 141 } 142 pcibios_allocate_bus_resources(&bus->children); 143 } 144 } 145 146 static void __init pcibios_allocate_resources(int pass) 147 { 148 struct pci_dev *dev = NULL; 149 int idx, disabled; 150 u16 command; 151 struct resource *r, *pr; 152 153 for_each_pci_dev(dev) { 154 pci_read_config_word(dev, PCI_COMMAND, &command); 155 for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) { 156 r = &dev->resource[idx]; 157 if (r->parent) /* Already allocated */ 158 continue; 159 if (!r->start) /* Address not assigned at all */ 160 continue; 161 if (r->flags & IORESOURCE_IO) 162 disabled = !(command & PCI_COMMAND_IO); 163 else 164 disabled = !(command & PCI_COMMAND_MEMORY); 165 if (pass == disabled) { 166 DBG("PCI: Resource %08lx-%08lx " 167 "(f=%lx, d=%d, p=%d)\n", 168 r->start, r->end, r->flags, disabled, pass); 169 pr = pci_find_parent_resource(dev, r); 170 if (!pr || request_resource(pr, r) < 0) { 171 printk(KERN_ERR "PCI: Cannot allocate " 172 "resource region %d " 173 "of device %s\n", 174 idx, pci_name(dev)); 175 /* We'll assign a new address later */ 176 r->end -= r->start; 177 r->start = 0; 178 } 179 } 180 } 181 if (!pass) { 182 r = &dev->resource[PCI_ROM_RESOURCE]; 183 if (r->flags & IORESOURCE_ROM_ENABLE) { 184 /* Turn the ROM off, leave the resource region, 185 * but keep it unregistered. */ 186 u32 reg; 187 DBG("PCI: Switching off ROM of %s\n", 188 pci_name(dev)); 189 r->flags &= ~IORESOURCE_ROM_ENABLE; 190 pci_read_config_dword(dev, 191 dev->rom_base_reg, ®); 192 pci_write_config_dword(dev, dev->rom_base_reg, 193 reg & ~PCI_ROM_ADDRESS_ENABLE); 194 } 195 } 196 } 197 } 198 199 static int __init pcibios_assign_resources(void) 200 { 201 struct pci_dev *dev = NULL; 202 struct resource *r, *pr; 203 204 if (!(pci_probe & PCI_ASSIGN_ROMS)) { 205 /* 206 * Try to use BIOS settings for ROMs, otherwise let 207 * pci_assign_unassigned_resources() allocate the new 208 * addresses. 209 */ 210 for_each_pci_dev(dev) { 211 r = &dev->resource[PCI_ROM_RESOURCE]; 212 if (!r->flags || !r->start) 213 continue; 214 pr = pci_find_parent_resource(dev, r); 215 if (!pr || request_resource(pr, r) < 0) { 216 r->end -= r->start; 217 r->start = 0; 218 } 219 } 220 } 221 222 pci_assign_unassigned_resources(); 223 224 return 0; 225 } 226 227 void __init pcibios_resource_survey(void) 228 { 229 DBG("PCI: Allocating resources\n"); 230 pcibios_allocate_bus_resources(&pci_root_buses); 231 pcibios_allocate_resources(0); 232 pcibios_allocate_resources(1); 233 } 234 235 /** 236 * called in fs_initcall (one below subsys_initcall), 237 * give a chance for motherboard reserve resources 238 */ 239 fs_initcall(pcibios_assign_resources); 240 241 int pcibios_enable_resources(struct pci_dev *dev, int mask) 242 { 243 u16 cmd, old_cmd; 244 int idx; 245 struct resource *r; 246 247 pci_read_config_word(dev, PCI_COMMAND, &cmd); 248 old_cmd = cmd; 249 for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) { 250 /* Only set up the requested stuff */ 251 if (!(mask & (1 << idx))) 252 continue; 253 254 r = &dev->resource[idx]; 255 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 256 continue; 257 if ((idx == PCI_ROM_RESOURCE) && 258 (!(r->flags & IORESOURCE_ROM_ENABLE))) 259 continue; 260 if (!r->start && r->end) { 261 printk(KERN_ERR "PCI: Device %s not available " 262 "because of resource %d collisions\n", 263 pci_name(dev), idx); 264 return -EINVAL; 265 } 266 if (r->flags & IORESOURCE_IO) 267 cmd |= PCI_COMMAND_IO; 268 if (r->flags & IORESOURCE_MEM) 269 cmd |= PCI_COMMAND_MEMORY; 270 } 271 if (cmd != old_cmd) { 272 printk("PCI: Enabling device %s (%04x -> %04x)\n", 273 pci_name(dev), old_cmd, cmd); 274 pci_write_config_word(dev, PCI_COMMAND, cmd); 275 } 276 return 0; 277 } 278 279 /* 280 * If we set up a device for bus mastering, we need to check the latency 281 * timer as certain crappy BIOSes forget to set it properly. 282 */ 283 unsigned int pcibios_max_latency = 255; 284 285 void pcibios_set_master(struct pci_dev *dev) 286 { 287 u8 lat; 288 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 289 if (lat < 16) 290 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 291 else if (lat > pcibios_max_latency) 292 lat = pcibios_max_latency; 293 else 294 return; 295 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", 296 pci_name(dev), lat); 297 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 298 } 299 300 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 301 enum pci_mmap_state mmap_state, int write_combine) 302 { 303 unsigned long prot; 304 305 /* I/O space cannot be accessed via normal processor loads and 306 * stores on this platform. 307 */ 308 if (mmap_state == pci_mmap_io) 309 return -EINVAL; 310 311 /* Leave vm_pgoff as-is, the PCI space address is the physical 312 * address on this platform. 313 */ 314 prot = pgprot_val(vma->vm_page_prot); 315 if (boot_cpu_data.x86 > 3) 316 prot |= _PAGE_PCD | _PAGE_PWT; 317 vma->vm_page_prot = __pgprot(prot); 318 319 /* Write-combine setting is ignored, it is changed via the mtrr 320 * interfaces on this platform. 321 */ 322 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 323 vma->vm_end - vma->vm_start, 324 vma->vm_page_prot)) 325 return -EAGAIN; 326 327 return 0; 328 } 329