1 /* 2 * Low-Level PCI Access for i386 machines 3 * 4 * Copyright 1993, 1994 Drew Eckhardt 5 * Visionary Computing 6 * (Unix and Linux consulting and custom programming) 7 * Drew@Colorado.EDU 8 * +1 (303) 786-7975 9 * 10 * Drew's work was sponsored by: 11 * iX Multiuser Multitasking Magazine 12 * Hannover, Germany 13 * hm@ix.de 14 * 15 * Copyright 1997--2000 Martin Mares <mj@ucw.cz> 16 * 17 * For more information, please consult the following manuals (look at 18 * http://www.pcisig.com/ for how to get them): 19 * 20 * PCI BIOS Specification 21 * PCI Local Bus Specification 22 * PCI to PCI Bridge Specification 23 * PCI System Design Guide 24 * 25 */ 26 27 #include <linux/types.h> 28 #include <linux/kernel.h> 29 #include <linux/export.h> 30 #include <linux/pci.h> 31 #include <linux/init.h> 32 #include <linux/ioport.h> 33 #include <linux/errno.h> 34 #include <linux/bootmem.h> 35 36 #include <asm/pat.h> 37 #include <asm/e820.h> 38 #include <asm/pci_x86.h> 39 #include <asm/io_apic.h> 40 41 42 static int 43 skip_isa_ioresource_align(struct pci_dev *dev) { 44 45 if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) && 46 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 47 return 1; 48 return 0; 49 } 50 51 /* 52 * We need to avoid collisions with `mirrored' VGA ports 53 * and other strange ISA hardware, so we always want the 54 * addresses to be allocated in the 0x000-0x0ff region 55 * modulo 0x400. 56 * 57 * Why? Because some silly external IO cards only decode 58 * the low 10 bits of the IO address. The 0x00-0xff region 59 * is reserved for motherboard devices that decode all 16 60 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 61 * but we want to try to avoid allocating at 0x2900-0x2bff 62 * which might have be mirrored at 0x0100-0x03ff.. 63 */ 64 resource_size_t 65 pcibios_align_resource(void *data, const struct resource *res, 66 resource_size_t size, resource_size_t align) 67 { 68 struct pci_dev *dev = data; 69 resource_size_t start = res->start; 70 71 if (res->flags & IORESOURCE_IO) { 72 if (skip_isa_ioresource_align(dev)) 73 return start; 74 if (start & 0x300) 75 start = (start + 0x3ff) & ~0x3ff; 76 } 77 return start; 78 } 79 EXPORT_SYMBOL(pcibios_align_resource); 80 81 /* 82 * Handle resources of PCI devices. If the world were perfect, we could 83 * just allocate all the resource regions and do nothing more. It isn't. 84 * On the other hand, we cannot just re-allocate all devices, as it would 85 * require us to know lots of host bridge internals. So we attempt to 86 * keep as much of the original configuration as possible, but tweak it 87 * when it's found to be wrong. 88 * 89 * Known BIOS problems we have to work around: 90 * - I/O or memory regions not configured 91 * - regions configured, but not enabled in the command register 92 * - bogus I/O addresses above 64K used 93 * - expansion ROMs left enabled (this may sound harmless, but given 94 * the fact the PCI specs explicitly allow address decoders to be 95 * shared between expansion ROMs and other resource regions, it's 96 * at least dangerous) 97 * - bad resource sizes or overlaps with other regions 98 * 99 * Our solution: 100 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 101 * This gives us fixed barriers on where we can allocate. 102 * (2) Allocate resources for all enabled devices. If there is 103 * a collision, just mark the resource as unallocated. Also 104 * disable expansion ROMs during this step. 105 * (3) Try to allocate resources for disabled devices. If the 106 * resources were assigned correctly, everything goes well, 107 * if they weren't, they won't disturb allocation of other 108 * resources. 109 * (4) Assign new addresses to resources which were either 110 * not configured at all or misconfigured. If explicitly 111 * requested by the user, configure expansion ROM address 112 * as well. 113 */ 114 115 static void __init pcibios_allocate_bus_resources(struct list_head *bus_list) 116 { 117 struct pci_bus *bus; 118 struct pci_dev *dev; 119 int idx; 120 struct resource *r; 121 122 /* Depth-First Search on bus tree */ 123 list_for_each_entry(bus, bus_list, node) { 124 if ((dev = bus->self)) { 125 for (idx = PCI_BRIDGE_RESOURCES; 126 idx < PCI_NUM_RESOURCES; idx++) { 127 r = &dev->resource[idx]; 128 if (!r->flags) 129 continue; 130 if (!r->start || 131 pci_claim_resource(dev, idx) < 0) { 132 /* 133 * Something is wrong with the region. 134 * Invalidate the resource to prevent 135 * child resource allocations in this 136 * range. 137 */ 138 r->start = r->end = 0; 139 r->flags = 0; 140 } 141 } 142 } 143 pcibios_allocate_bus_resources(&bus->children); 144 } 145 } 146 147 struct pci_check_idx_range { 148 int start; 149 int end; 150 }; 151 152 static void __init pcibios_allocate_resources(int pass) 153 { 154 struct pci_dev *dev = NULL; 155 int idx, disabled, i; 156 u16 command; 157 struct resource *r; 158 159 struct pci_check_idx_range idx_range[] = { 160 { PCI_STD_RESOURCES, PCI_STD_RESOURCE_END }, 161 #ifdef CONFIG_PCI_IOV 162 { PCI_IOV_RESOURCES, PCI_IOV_RESOURCE_END }, 163 #endif 164 }; 165 166 for_each_pci_dev(dev) { 167 pci_read_config_word(dev, PCI_COMMAND, &command); 168 for (i = 0; i < ARRAY_SIZE(idx_range); i++) 169 for (idx = idx_range[i].start; idx <= idx_range[i].end; idx++) { 170 r = &dev->resource[idx]; 171 if (r->parent) /* Already allocated */ 172 continue; 173 if (!r->start) /* Address not assigned at all */ 174 continue; 175 if (r->flags & IORESOURCE_IO) 176 disabled = !(command & PCI_COMMAND_IO); 177 else 178 disabled = !(command & PCI_COMMAND_MEMORY); 179 if (pass == disabled) { 180 dev_dbg(&dev->dev, 181 "BAR %d: reserving %pr (d=%d, p=%d)\n", 182 idx, r, disabled, pass); 183 if (pci_claim_resource(dev, idx) < 0) { 184 /* We'll assign a new address later */ 185 dev->fw_addr[idx] = r->start; 186 r->end -= r->start; 187 r->start = 0; 188 } 189 } 190 } 191 if (!pass) { 192 r = &dev->resource[PCI_ROM_RESOURCE]; 193 if (r->flags & IORESOURCE_ROM_ENABLE) { 194 /* Turn the ROM off, leave the resource region, 195 * but keep it unregistered. */ 196 u32 reg; 197 dev_dbg(&dev->dev, "disabling ROM %pR\n", r); 198 r->flags &= ~IORESOURCE_ROM_ENABLE; 199 pci_read_config_dword(dev, 200 dev->rom_base_reg, ®); 201 pci_write_config_dword(dev, dev->rom_base_reg, 202 reg & ~PCI_ROM_ADDRESS_ENABLE); 203 } 204 } 205 } 206 } 207 208 static int __init pcibios_assign_resources(void) 209 { 210 struct pci_dev *dev = NULL; 211 struct resource *r; 212 213 if (!(pci_probe & PCI_ASSIGN_ROMS)) { 214 /* 215 * Try to use BIOS settings for ROMs, otherwise let 216 * pci_assign_unassigned_resources() allocate the new 217 * addresses. 218 */ 219 for_each_pci_dev(dev) { 220 r = &dev->resource[PCI_ROM_RESOURCE]; 221 if (!r->flags || !r->start) 222 continue; 223 if (pci_claim_resource(dev, PCI_ROM_RESOURCE) < 0) { 224 r->end -= r->start; 225 r->start = 0; 226 } 227 } 228 } 229 230 pci_assign_unassigned_resources(); 231 232 return 0; 233 } 234 235 void __init pcibios_resource_survey(void) 236 { 237 DBG("PCI: Allocating resources\n"); 238 pcibios_allocate_bus_resources(&pci_root_buses); 239 pcibios_allocate_resources(0); 240 pcibios_allocate_resources(1); 241 242 e820_reserve_resources_late(); 243 /* 244 * Insert the IO APIC resources after PCI initialization has 245 * occurred to handle IO APICS that are mapped in on a BAR in 246 * PCI space, but before trying to assign unassigned pci res. 247 */ 248 ioapic_insert_resources(); 249 } 250 251 /** 252 * called in fs_initcall (one below subsys_initcall), 253 * give a chance for motherboard reserve resources 254 */ 255 fs_initcall(pcibios_assign_resources); 256 257 static const struct vm_operations_struct pci_mmap_ops = { 258 .access = generic_access_phys, 259 }; 260 261 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 262 enum pci_mmap_state mmap_state, int write_combine) 263 { 264 unsigned long prot; 265 266 /* I/O space cannot be accessed via normal processor loads and 267 * stores on this platform. 268 */ 269 if (mmap_state == pci_mmap_io) 270 return -EINVAL; 271 272 prot = pgprot_val(vma->vm_page_prot); 273 274 /* 275 * Return error if pat is not enabled and write_combine is requested. 276 * Caller can followup with UC MINUS request and add a WC mtrr if there 277 * is a free mtrr slot. 278 */ 279 if (!pat_enabled && write_combine) 280 return -EINVAL; 281 282 if (pat_enabled && write_combine) 283 prot |= _PAGE_CACHE_WC; 284 else if (pat_enabled || boot_cpu_data.x86 > 3) 285 /* 286 * ioremap() and ioremap_nocache() defaults to UC MINUS for now. 287 * To avoid attribute conflicts, request UC MINUS here 288 * as well. 289 */ 290 prot |= _PAGE_CACHE_UC_MINUS; 291 292 prot |= _PAGE_IOMAP; /* creating a mapping for IO */ 293 294 vma->vm_page_prot = __pgprot(prot); 295 296 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 297 vma->vm_end - vma->vm_start, 298 vma->vm_page_prot)) 299 return -EAGAIN; 300 301 vma->vm_ops = &pci_mmap_ops; 302 303 return 0; 304 } 305