xref: /openbmc/linux/arch/x86/pci/fixup.c (revision d2999e1b)
1 /*
2  * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
3  */
4 
5 #include <linux/delay.h>
6 #include <linux/dmi.h>
7 #include <linux/pci.h>
8 #include <linux/vgaarb.h>
9 #include <asm/hpet.h>
10 #include <asm/pci_x86.h>
11 
12 static void pci_fixup_i450nx(struct pci_dev *d)
13 {
14 	/*
15 	 * i450NX -- Find and scan all secondary buses on all PXB's.
16 	 */
17 	int pxb, reg;
18 	u8 busno, suba, subb;
19 
20 	dev_warn(&d->dev, "Searching for i450NX host bridges\n");
21 	reg = 0xd0;
22 	for(pxb = 0; pxb < 2; pxb++) {
23 		pci_read_config_byte(d, reg++, &busno);
24 		pci_read_config_byte(d, reg++, &suba);
25 		pci_read_config_byte(d, reg++, &subb);
26 		dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno,
27 			suba, subb);
28 		if (busno)
29 			pcibios_scan_root(busno);	/* Bus A */
30 		if (suba < subb)
31 			pcibios_scan_root(suba+1);	/* Bus B */
32 	}
33 	pcibios_last_bus = -1;
34 }
35 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
36 
37 static void pci_fixup_i450gx(struct pci_dev *d)
38 {
39 	/*
40 	 * i450GX and i450KX -- Find and scan all secondary buses.
41 	 * (called separately for each PCI bridge found)
42 	 */
43 	u8 busno;
44 	pci_read_config_byte(d, 0x4a, &busno);
45 	dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno);
46 	pcibios_scan_root(busno);
47 	pcibios_last_bus = -1;
48 }
49 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);
50 
51 static void pci_fixup_umc_ide(struct pci_dev *d)
52 {
53 	/*
54 	 * UM8886BF IDE controller sets region type bits incorrectly,
55 	 * therefore they look like memory despite of them being I/O.
56 	 */
57 	int i;
58 
59 	dev_warn(&d->dev, "Fixing base address flags\n");
60 	for(i = 0; i < 4; i++)
61 		d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
62 }
63 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
64 
65 static void pci_fixup_ncr53c810(struct pci_dev *d)
66 {
67 	/*
68 	 * NCR 53C810 returns class code 0 (at least on some systems).
69 	 * Fix class to be PCI_CLASS_STORAGE_SCSI
70 	 */
71 	if (!d->class) {
72 		dev_warn(&d->dev, "Fixing NCR 53C810 class code\n");
73 		d->class = PCI_CLASS_STORAGE_SCSI << 8;
74 	}
75 }
76 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810);
77 
78 static void pci_fixup_latency(struct pci_dev *d)
79 {
80 	/*
81 	 *  SiS 5597 and 5598 chipsets require latency timer set to
82 	 *  at most 32 to avoid lockups.
83 	 */
84 	dev_dbg(&d->dev, "Setting max latency to 32\n");
85 	pcibios_max_latency = 32;
86 }
87 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
88 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
89 
90 static void pci_fixup_piix4_acpi(struct pci_dev *d)
91 {
92 	/*
93 	 * PIIX4 ACPI device: hardwired IRQ9
94 	 */
95 	d->irq = 9;
96 }
97 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi);
98 
99 /*
100  * Addresses issues with problems in the memory write queue timer in
101  * certain VIA Northbridges.  This bugfix is per VIA's specifications,
102  * except for the KL133/KM133: clearing bit 5 on those Northbridges seems
103  * to trigger a bug in its integrated ProSavage video card, which
104  * causes screen corruption.  We only clear bits 6 and 7 for that chipset,
105  * until VIA can provide us with definitive information on why screen
106  * corruption occurs, and what exactly those bits do.
107  *
108  * VIA 8363,8622,8361 Northbridges:
109  *  - bits  5, 6, 7 at offset 0x55 need to be turned off
110  * VIA 8367 (KT266x) Northbridges:
111  *  - bits  5, 6, 7 at offset 0x95 need to be turned off
112  * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
113  *  - bits     6, 7 at offset 0x55 need to be turned off
114  */
115 
116 #define VIA_8363_KL133_REVISION_ID 0x81
117 #define VIA_8363_KM133_REVISION_ID 0x84
118 
119 static void pci_fixup_via_northbridge_bug(struct pci_dev *d)
120 {
121 	u8 v;
122 	int where = 0x55;
123 	int mask = 0x1f; /* clear bits 5, 6, 7 by default */
124 
125 	if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
126 		/* fix pci bus latency issues resulted by NB bios error
127 		   it appears on bug free^Wreduced kt266x's bios forces
128 		   NB latency to zero */
129 		pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
130 
131 		where = 0x95; /* the memory write queue timer register is
132 				different for the KT266x's: 0x95 not 0x55 */
133 	} else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
134 			(d->revision == VIA_8363_KL133_REVISION_ID ||
135 			d->revision == VIA_8363_KM133_REVISION_ID)) {
136 			mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
137 					causes screen corruption on the KL133/KM133 */
138 	}
139 
140 	pci_read_config_byte(d, where, &v);
141 	if (v & ~mask) {
142 		dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
143 			d->device, d->revision, where, v, mask, v & mask);
144 		v &= mask;
145 		pci_write_config_byte(d, where, v);
146 	}
147 }
148 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
149 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
150 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
151 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
152 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
153 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
154 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
155 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
156 
157 /*
158  * For some reasons Intel decided that certain parts of their
159  * 815, 845 and some other chipsets must look like PCI-to-PCI bridges
160  * while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
161  * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
162  * to Intel terminology. These devices do forward all addresses from
163  * system to PCI bus no matter what are their window settings, so they are
164  * "transparent" (or subtractive decoding) from programmers point of view.
165  */
166 static void pci_fixup_transparent_bridge(struct pci_dev *dev)
167 {
168 	if ((dev->device & 0xff00) == 0x2400)
169 		dev->transparent = 1;
170 }
171 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
172 			 PCI_CLASS_BRIDGE_PCI, 8, pci_fixup_transparent_bridge);
173 
174 /*
175  * Fixup for C1 Halt Disconnect problem on nForce2 systems.
176  *
177  * From information provided by "Allen Martin" <AMartin@nvidia.com>:
178  *
179  * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle
180  * sequence.  Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns.
181  * This allows the state-machine and timer to return to a proper state within
182  * 80 ns of the CONNECT and probe appearing together.  Since the CPU will not
183  * issue another HALT within 80 ns of the initial HALT, the failure condition
184  * is avoided.
185  */
186 static void pci_fixup_nforce2(struct pci_dev *dev)
187 {
188 	u32 val;
189 
190 	/*
191 	 * Chip  Old value   New value
192 	 * C17   0x1F0FFF01  0x1F01FF01
193 	 * C18D  0x9F0FFF01  0x9F01FF01
194 	 *
195 	 * Northbridge chip version may be determined by
196 	 * reading the PCI revision ID (0xC1 or greater is C18D).
197 	 */
198 	pci_read_config_dword(dev, 0x6c, &val);
199 
200 	/*
201 	 * Apply fixup if needed, but don't touch disconnect state
202 	 */
203 	if ((val & 0x00FF0000) != 0x00010000) {
204 		dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n");
205 		pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
206 	}
207 }
208 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
209 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
210 
211 /* Max PCI Express root ports */
212 #define MAX_PCIEROOT	6
213 static int quirk_aspm_offset[MAX_PCIEROOT << 3];
214 
215 #define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7))
216 
217 static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
218 {
219 	return raw_pci_read(pci_domain_nr(bus), bus->number,
220 						devfn, where, size, value);
221 }
222 
223 /*
224  * Replace the original pci bus ops for write with a new one that will filter
225  * the request to insure ASPM cannot be enabled.
226  */
227 static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
228 {
229 	u8 offset;
230 
231 	offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)];
232 
233 	if ((offset) && (where == offset))
234 		value = value & ~PCI_EXP_LNKCTL_ASPMC;
235 
236 	return raw_pci_write(pci_domain_nr(bus), bus->number,
237 						devfn, where, size, value);
238 }
239 
240 static struct pci_ops quirk_pcie_aspm_ops = {
241 	.read = quirk_pcie_aspm_read,
242 	.write = quirk_pcie_aspm_write,
243 };
244 
245 /*
246  * Prevents PCI Express ASPM (Active State Power Management) being enabled.
247  *
248  * Save the register offset, where the ASPM control bits are located,
249  * for each PCI Express device that is in the device list of
250  * the root port in an array for fast indexing. Replace the bus ops
251  * with the modified one.
252  */
253 static void pcie_rootport_aspm_quirk(struct pci_dev *pdev)
254 {
255 	int i;
256 	struct pci_bus  *pbus;
257 	struct pci_dev *dev;
258 
259 	if ((pbus = pdev->subordinate) == NULL)
260 		return;
261 
262 	/*
263 	 * Check if the DID of pdev matches one of the six root ports. This
264 	 * check is needed in the case this function is called directly by the
265 	 * hot-plug driver.
266 	 */
267 	if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) ||
268 	    (pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1))
269 		return;
270 
271 	if (list_empty(&pbus->devices)) {
272 		/*
273 		 * If no device is attached to the root port at power-up or
274 		 * after hot-remove, the pbus->devices is empty and this code
275 		 * will set the offsets to zero and the bus ops to parent's bus
276 		 * ops, which is unmodified.
277 		 */
278 		for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i)
279 			quirk_aspm_offset[i] = 0;
280 
281 		pci_bus_set_ops(pbus, pbus->parent->ops);
282 	} else {
283 		/*
284 		 * If devices are attached to the root port at power-up or
285 		 * after hot-add, the code loops through the device list of
286 		 * each root port to save the register offsets and replace the
287 		 * bus ops.
288 		 */
289 		list_for_each_entry(dev, &pbus->devices, bus_list)
290 			/* There are 0 to 8 devices attached to this bus */
291 			quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)] =
292 				dev->pcie_cap + PCI_EXP_LNKCTL;
293 
294 		pci_bus_set_ops(pbus, &quirk_pcie_aspm_ops);
295 		dev_info(&pbus->dev, "writes to ASPM control bits will be ignored\n");
296 	}
297 
298 }
299 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PA,	pcie_rootport_aspm_quirk);
300 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PA1,	pcie_rootport_aspm_quirk);
301 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PB,	pcie_rootport_aspm_quirk);
302 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PB1,	pcie_rootport_aspm_quirk);
303 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PC,	pcie_rootport_aspm_quirk);
304 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PC1,	pcie_rootport_aspm_quirk);
305 
306 /*
307  * Fixup to mark boot BIOS video selected by BIOS before it changes
308  *
309  * From information provided by "Jon Smirl" <jonsmirl@gmail.com>
310  *
311  * The standard boot ROM sequence for an x86 machine uses the BIOS
312  * to select an initial video card for boot display. This boot video
313  * card will have it's BIOS copied to C0000 in system RAM.
314  * IORESOURCE_ROM_SHADOW is used to associate the boot video
315  * card with this copy. On laptops this copy has to be used since
316  * the main ROM may be compressed or combined with another image.
317  * See pci_map_rom() for use of this flag. Before marking the device
318  * with IORESOURCE_ROM_SHADOW check if a vga_default_device is already set
319  * by either arch cde or vga-arbitration, if so only apply the fixup to this
320  * already determined primary video card.
321  */
322 
323 static void pci_fixup_video(struct pci_dev *pdev)
324 {
325 	struct pci_dev *bridge;
326 	struct pci_bus *bus;
327 	u16 config;
328 
329 	/* Is VGA routed to us? */
330 	bus = pdev->bus;
331 	while (bus) {
332 		bridge = bus->self;
333 
334 		/*
335 		 * From information provided by
336 		 * "David Miller" <davem@davemloft.net>
337 		 * The bridge control register is valid for PCI header
338 		 * type BRIDGE, or CARDBUS. Host to PCI controllers use
339 		 * PCI header type NORMAL.
340 		 */
341 		if (bridge && (pci_is_bridge(bridge))) {
342 			pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
343 						&config);
344 			if (!(config & PCI_BRIDGE_CTL_VGA))
345 				return;
346 		}
347 		bus = bus->parent;
348 	}
349 	if (!vga_default_device() || pdev == vga_default_device()) {
350 		pci_read_config_word(pdev, PCI_COMMAND, &config);
351 		if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
352 			pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
353 			dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n");
354 			vga_set_default_device(pdev);
355 		}
356 	}
357 }
358 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
359 				PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video);
360 
361 
362 static const struct dmi_system_id msi_k8t_dmi_table[] = {
363 	{
364 		.ident = "MSI-K8T-Neo2Fir",
365 		.matches = {
366 			DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
367 			DMI_MATCH(DMI_PRODUCT_NAME, "MS-6702E"),
368 		},
369 	},
370 	{}
371 };
372 
373 /*
374  * The AMD-Athlon64 board MSI "K8T Neo2-FIR" disables the onboard sound
375  * card if a PCI-soundcard is added.
376  *
377  * The BIOS only gives options "DISABLED" and "AUTO". This code sets
378  * the corresponding register-value to enable the soundcard.
379  *
380  * The soundcard is only enabled, if the mainborad is identified
381  * via DMI-tables and the soundcard is detected to be off.
382  */
383 static void pci_fixup_msi_k8t_onboard_sound(struct pci_dev *dev)
384 {
385 	unsigned char val;
386 	if (!dmi_check_system(msi_k8t_dmi_table))
387 		return; /* only applies to MSI K8T Neo2-FIR */
388 
389 	pci_read_config_byte(dev, 0x50, &val);
390 	if (val & 0x40) {
391 		pci_write_config_byte(dev, 0x50, val & (~0x40));
392 
393 		/* verify the change for status output */
394 		pci_read_config_byte(dev, 0x50, &val);
395 		if (val & 0x40)
396 			dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
397 					"can't enable onboard soundcard!\n");
398 		else
399 			dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
400 					"enabled onboard soundcard\n");
401 	}
402 }
403 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
404 		pci_fixup_msi_k8t_onboard_sound);
405 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
406 		pci_fixup_msi_k8t_onboard_sound);
407 
408 /*
409  * Some Toshiba laptops need extra code to enable their TI TSB43AB22/A.
410  *
411  * We pretend to bring them out of full D3 state, and restore the proper
412  * IRQ, PCI cache line size, and BARs, otherwise the device won't function
413  * properly.  In some cases, the device will generate an interrupt on
414  * the wrong IRQ line, causing any devices sharing the line it's
415  * *supposed* to use to be disabled by the kernel's IRQ debug code.
416  */
417 static u16 toshiba_line_size;
418 
419 static const struct dmi_system_id toshiba_ohci1394_dmi_table[] = {
420 	{
421 		.ident = "Toshiba PS5 based laptop",
422 		.matches = {
423 			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
424 			DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"),
425 		},
426 	},
427 	{
428 		.ident = "Toshiba PSM4 based laptop",
429 		.matches = {
430 			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
431 			DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"),
432 		},
433 	},
434 	{
435 		.ident = "Toshiba A40 based laptop",
436 		.matches = {
437 			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
438 			DMI_MATCH(DMI_PRODUCT_VERSION, "PSA40U"),
439 		},
440 	},
441 	{ }
442 };
443 
444 static void pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev)
445 {
446 	if (!dmi_check_system(toshiba_ohci1394_dmi_table))
447 		return; /* only applies to certain Toshibas (so far) */
448 
449 	dev->current_state = PCI_D3cold;
450 	pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size);
451 }
452 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032,
453 			 pci_pre_fixup_toshiba_ohci1394);
454 
455 static void pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev)
456 {
457 	if (!dmi_check_system(toshiba_ohci1394_dmi_table))
458 		return; /* only applies to certain Toshibas (so far) */
459 
460 	/* Restore config space on Toshiba laptops */
461 	pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size);
462 	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq);
463 	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
464 			       pci_resource_start(dev, 0));
465 	pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
466 			       pci_resource_start(dev, 1));
467 }
468 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032,
469 			 pci_post_fixup_toshiba_ohci1394);
470 
471 
472 /*
473  * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device
474  * configuration space.
475  */
476 static void pci_early_fixup_cyrix_5530(struct pci_dev *dev)
477 {
478 	u8 r;
479 	/* clear 'F4 Video Configuration Trap' bit */
480 	pci_read_config_byte(dev, 0x42, &r);
481 	r &= 0xfd;
482 	pci_write_config_byte(dev, 0x42, r);
483 }
484 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
485 			pci_early_fixup_cyrix_5530);
486 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
487 			pci_early_fixup_cyrix_5530);
488 
489 /*
490  * Siemens Nixdorf AG FSC Multiprocessor Interrupt Controller:
491  * prevent update of the BAR0, which doesn't look like a normal BAR.
492  */
493 static void pci_siemens_interrupt_controller(struct pci_dev *dev)
494 {
495 	dev->resource[0].flags |= IORESOURCE_PCI_FIXED;
496 }
497 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015,
498 			  pci_siemens_interrupt_controller);
499 
500 /*
501  * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from
502  * confusing the PCI engine:
503  */
504 static void sb600_disable_hpet_bar(struct pci_dev *dev)
505 {
506 	u8 val;
507 
508 	/*
509 	 * The SB600 and SB700 both share the same device
510 	 * ID, but the PM register 0x55 does something different
511 	 * for the SB700, so make sure we are dealing with the
512 	 * SB600 before touching the bit:
513 	 */
514 
515 	pci_read_config_byte(dev, 0x08, &val);
516 
517 	if (val < 0x2F) {
518 		outb(0x55, 0xCD6);
519 		val = inb(0xCD7);
520 
521 		/* Set bit 7 in PM register 0x55 */
522 		outb(0x55, 0xCD6);
523 		outb(val | 0x80, 0xCD7);
524 	}
525 }
526 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar);
527 
528 #ifdef CONFIG_HPET_TIMER
529 static void sb600_hpet_quirk(struct pci_dev *dev)
530 {
531 	struct resource *r = &dev->resource[1];
532 
533 	if (r->flags & IORESOURCE_MEM && r->start == hpet_address) {
534 		r->flags |= IORESOURCE_PCI_FIXED;
535 		dev_info(&dev->dev, "reg 0x14 contains HPET; making it immovable\n");
536 	}
537 }
538 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4385, sb600_hpet_quirk);
539 #endif
540 
541 /*
542  * Twinhead H12Y needs us to block out a region otherwise we map devices
543  * there and any access kills the box.
544  *
545  *   See: https://bugzilla.kernel.org/show_bug.cgi?id=10231
546  *
547  * Match off the LPC and svid/sdid (older kernels lose the bridge subvendor)
548  */
549 static void twinhead_reserve_killing_zone(struct pci_dev *dev)
550 {
551         if (dev->subsystem_vendor == 0x14FF && dev->subsystem_device == 0xA003) {
552                 pr_info("Reserving memory on Twinhead H12Y\n");
553                 request_mem_region(0xFFB00000, 0x100000, "twinhead");
554         }
555 }
556 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x27B9, twinhead_reserve_killing_zone);
557