xref: /openbmc/linux/arch/x86/pci/fixup.c (revision bb0eb050)
1 /*
2  * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
3  */
4 
5 #include <linux/delay.h>
6 #include <linux/dmi.h>
7 #include <linux/pci.h>
8 #include <linux/vgaarb.h>
9 #include <asm/hpet.h>
10 #include <asm/pci_x86.h>
11 
12 static void pci_fixup_i450nx(struct pci_dev *d)
13 {
14 	/*
15 	 * i450NX -- Find and scan all secondary buses on all PXB's.
16 	 */
17 	int pxb, reg;
18 	u8 busno, suba, subb;
19 
20 	dev_warn(&d->dev, "Searching for i450NX host bridges\n");
21 	reg = 0xd0;
22 	for(pxb = 0; pxb < 2; pxb++) {
23 		pci_read_config_byte(d, reg++, &busno);
24 		pci_read_config_byte(d, reg++, &suba);
25 		pci_read_config_byte(d, reg++, &subb);
26 		dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno,
27 			suba, subb);
28 		if (busno)
29 			pcibios_scan_root(busno);	/* Bus A */
30 		if (suba < subb)
31 			pcibios_scan_root(suba+1);	/* Bus B */
32 	}
33 	pcibios_last_bus = -1;
34 }
35 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
36 
37 static void pci_fixup_i450gx(struct pci_dev *d)
38 {
39 	/*
40 	 * i450GX and i450KX -- Find and scan all secondary buses.
41 	 * (called separately for each PCI bridge found)
42 	 */
43 	u8 busno;
44 	pci_read_config_byte(d, 0x4a, &busno);
45 	dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno);
46 	pcibios_scan_root(busno);
47 	pcibios_last_bus = -1;
48 }
49 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);
50 
51 static void pci_fixup_umc_ide(struct pci_dev *d)
52 {
53 	/*
54 	 * UM8886BF IDE controller sets region type bits incorrectly,
55 	 * therefore they look like memory despite of them being I/O.
56 	 */
57 	int i;
58 
59 	dev_warn(&d->dev, "Fixing base address flags\n");
60 	for(i = 0; i < 4; i++)
61 		d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
62 }
63 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
64 
65 static void pci_fixup_latency(struct pci_dev *d)
66 {
67 	/*
68 	 *  SiS 5597 and 5598 chipsets require latency timer set to
69 	 *  at most 32 to avoid lockups.
70 	 */
71 	dev_dbg(&d->dev, "Setting max latency to 32\n");
72 	pcibios_max_latency = 32;
73 }
74 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
75 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
76 
77 static void pci_fixup_piix4_acpi(struct pci_dev *d)
78 {
79 	/*
80 	 * PIIX4 ACPI device: hardwired IRQ9
81 	 */
82 	d->irq = 9;
83 }
84 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi);
85 
86 /*
87  * Addresses issues with problems in the memory write queue timer in
88  * certain VIA Northbridges.  This bugfix is per VIA's specifications,
89  * except for the KL133/KM133: clearing bit 5 on those Northbridges seems
90  * to trigger a bug in its integrated ProSavage video card, which
91  * causes screen corruption.  We only clear bits 6 and 7 for that chipset,
92  * until VIA can provide us with definitive information on why screen
93  * corruption occurs, and what exactly those bits do.
94  *
95  * VIA 8363,8622,8361 Northbridges:
96  *  - bits  5, 6, 7 at offset 0x55 need to be turned off
97  * VIA 8367 (KT266x) Northbridges:
98  *  - bits  5, 6, 7 at offset 0x95 need to be turned off
99  * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
100  *  - bits     6, 7 at offset 0x55 need to be turned off
101  */
102 
103 #define VIA_8363_KL133_REVISION_ID 0x81
104 #define VIA_8363_KM133_REVISION_ID 0x84
105 
106 static void pci_fixup_via_northbridge_bug(struct pci_dev *d)
107 {
108 	u8 v;
109 	int where = 0x55;
110 	int mask = 0x1f; /* clear bits 5, 6, 7 by default */
111 
112 	if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
113 		/* fix pci bus latency issues resulted by NB bios error
114 		   it appears on bug free^Wreduced kt266x's bios forces
115 		   NB latency to zero */
116 		pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
117 
118 		where = 0x95; /* the memory write queue timer register is
119 				different for the KT266x's: 0x95 not 0x55 */
120 	} else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
121 			(d->revision == VIA_8363_KL133_REVISION_ID ||
122 			d->revision == VIA_8363_KM133_REVISION_ID)) {
123 			mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
124 					causes screen corruption on the KL133/KM133 */
125 	}
126 
127 	pci_read_config_byte(d, where, &v);
128 	if (v & ~mask) {
129 		dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
130 			d->device, d->revision, where, v, mask, v & mask);
131 		v &= mask;
132 		pci_write_config_byte(d, where, v);
133 	}
134 }
135 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
136 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
137 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
138 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
139 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
140 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
141 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
142 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
143 
144 /*
145  * For some reasons Intel decided that certain parts of their
146  * 815, 845 and some other chipsets must look like PCI-to-PCI bridges
147  * while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
148  * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
149  * to Intel terminology. These devices do forward all addresses from
150  * system to PCI bus no matter what are their window settings, so they are
151  * "transparent" (or subtractive decoding) from programmers point of view.
152  */
153 static void pci_fixup_transparent_bridge(struct pci_dev *dev)
154 {
155 	if ((dev->device & 0xff00) == 0x2400)
156 		dev->transparent = 1;
157 }
158 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
159 			 PCI_CLASS_BRIDGE_PCI, 8, pci_fixup_transparent_bridge);
160 
161 /*
162  * Fixup for C1 Halt Disconnect problem on nForce2 systems.
163  *
164  * From information provided by "Allen Martin" <AMartin@nvidia.com>:
165  *
166  * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle
167  * sequence.  Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns.
168  * This allows the state-machine and timer to return to a proper state within
169  * 80 ns of the CONNECT and probe appearing together.  Since the CPU will not
170  * issue another HALT within 80 ns of the initial HALT, the failure condition
171  * is avoided.
172  */
173 static void pci_fixup_nforce2(struct pci_dev *dev)
174 {
175 	u32 val;
176 
177 	/*
178 	 * Chip  Old value   New value
179 	 * C17   0x1F0FFF01  0x1F01FF01
180 	 * C18D  0x9F0FFF01  0x9F01FF01
181 	 *
182 	 * Northbridge chip version may be determined by
183 	 * reading the PCI revision ID (0xC1 or greater is C18D).
184 	 */
185 	pci_read_config_dword(dev, 0x6c, &val);
186 
187 	/*
188 	 * Apply fixup if needed, but don't touch disconnect state
189 	 */
190 	if ((val & 0x00FF0000) != 0x00010000) {
191 		dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n");
192 		pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
193 	}
194 }
195 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
196 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
197 
198 /* Max PCI Express root ports */
199 #define MAX_PCIEROOT	6
200 static int quirk_aspm_offset[MAX_PCIEROOT << 3];
201 
202 #define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7))
203 
204 static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
205 {
206 	return raw_pci_read(pci_domain_nr(bus), bus->number,
207 						devfn, where, size, value);
208 }
209 
210 /*
211  * Replace the original pci bus ops for write with a new one that will filter
212  * the request to insure ASPM cannot be enabled.
213  */
214 static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
215 {
216 	u8 offset;
217 
218 	offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)];
219 
220 	if ((offset) && (where == offset))
221 		value = value & ~PCI_EXP_LNKCTL_ASPMC;
222 
223 	return raw_pci_write(pci_domain_nr(bus), bus->number,
224 						devfn, where, size, value);
225 }
226 
227 static struct pci_ops quirk_pcie_aspm_ops = {
228 	.read = quirk_pcie_aspm_read,
229 	.write = quirk_pcie_aspm_write,
230 };
231 
232 /*
233  * Prevents PCI Express ASPM (Active State Power Management) being enabled.
234  *
235  * Save the register offset, where the ASPM control bits are located,
236  * for each PCI Express device that is in the device list of
237  * the root port in an array for fast indexing. Replace the bus ops
238  * with the modified one.
239  */
240 static void pcie_rootport_aspm_quirk(struct pci_dev *pdev)
241 {
242 	int i;
243 	struct pci_bus  *pbus;
244 	struct pci_dev *dev;
245 
246 	if ((pbus = pdev->subordinate) == NULL)
247 		return;
248 
249 	/*
250 	 * Check if the DID of pdev matches one of the six root ports. This
251 	 * check is needed in the case this function is called directly by the
252 	 * hot-plug driver.
253 	 */
254 	if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) ||
255 	    (pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1))
256 		return;
257 
258 	if (list_empty(&pbus->devices)) {
259 		/*
260 		 * If no device is attached to the root port at power-up or
261 		 * after hot-remove, the pbus->devices is empty and this code
262 		 * will set the offsets to zero and the bus ops to parent's bus
263 		 * ops, which is unmodified.
264 		 */
265 		for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i)
266 			quirk_aspm_offset[i] = 0;
267 
268 		pci_bus_set_ops(pbus, pbus->parent->ops);
269 	} else {
270 		/*
271 		 * If devices are attached to the root port at power-up or
272 		 * after hot-add, the code loops through the device list of
273 		 * each root port to save the register offsets and replace the
274 		 * bus ops.
275 		 */
276 		list_for_each_entry(dev, &pbus->devices, bus_list)
277 			/* There are 0 to 8 devices attached to this bus */
278 			quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)] =
279 				dev->pcie_cap + PCI_EXP_LNKCTL;
280 
281 		pci_bus_set_ops(pbus, &quirk_pcie_aspm_ops);
282 		dev_info(&pbus->dev, "writes to ASPM control bits will be ignored\n");
283 	}
284 
285 }
286 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PA,	pcie_rootport_aspm_quirk);
287 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PA1,	pcie_rootport_aspm_quirk);
288 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PB,	pcie_rootport_aspm_quirk);
289 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PB1,	pcie_rootport_aspm_quirk);
290 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PC,	pcie_rootport_aspm_quirk);
291 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_MCH_PC1,	pcie_rootport_aspm_quirk);
292 
293 /*
294  * Fixup to mark boot BIOS video selected by BIOS before it changes
295  *
296  * From information provided by "Jon Smirl" <jonsmirl@gmail.com>
297  *
298  * The standard boot ROM sequence for an x86 machine uses the BIOS
299  * to select an initial video card for boot display. This boot video
300  * card will have its BIOS copied to 0xC0000 in system RAM.
301  * IORESOURCE_ROM_SHADOW is used to associate the boot video
302  * card with this copy. On laptops this copy has to be used since
303  * the main ROM may be compressed or combined with another image.
304  * See pci_map_rom() for use of this flag. Before marking the device
305  * with IORESOURCE_ROM_SHADOW check if a vga_default_device is already set
306  * by either arch code or vga-arbitration; if so only apply the fixup to this
307  * already-determined primary video card.
308  */
309 
310 static void pci_fixup_video(struct pci_dev *pdev)
311 {
312 	struct pci_dev *bridge;
313 	struct pci_bus *bus;
314 	u16 config;
315 	struct resource *res;
316 
317 	/* Is VGA routed to us? */
318 	bus = pdev->bus;
319 	while (bus) {
320 		bridge = bus->self;
321 
322 		/*
323 		 * From information provided by
324 		 * "David Miller" <davem@davemloft.net>
325 		 * The bridge control register is valid for PCI header
326 		 * type BRIDGE, or CARDBUS. Host to PCI controllers use
327 		 * PCI header type NORMAL.
328 		 */
329 		if (bridge && (pci_is_bridge(bridge))) {
330 			pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
331 						&config);
332 			if (!(config & PCI_BRIDGE_CTL_VGA))
333 				return;
334 		}
335 		bus = bus->parent;
336 	}
337 	if (!vga_default_device() || pdev == vga_default_device()) {
338 		pci_read_config_word(pdev, PCI_COMMAND, &config);
339 		if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
340 			res = &pdev->resource[PCI_ROM_RESOURCE];
341 
342 			pci_disable_rom(pdev);
343 			if (res->parent)
344 				release_resource(res);
345 
346 			res->start = 0xC0000;
347 			res->end = res->start + 0x20000 - 1;
348 			res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
349 				     IORESOURCE_PCI_FIXED;
350 			dev_info(&pdev->dev, "Video device with shadowed ROM at %pR\n",
351 				 res);
352 		}
353 	}
354 }
355 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
356 				PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video);
357 
358 
359 static const struct dmi_system_id msi_k8t_dmi_table[] = {
360 	{
361 		.ident = "MSI-K8T-Neo2Fir",
362 		.matches = {
363 			DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
364 			DMI_MATCH(DMI_PRODUCT_NAME, "MS-6702E"),
365 		},
366 	},
367 	{}
368 };
369 
370 /*
371  * The AMD-Athlon64 board MSI "K8T Neo2-FIR" disables the onboard sound
372  * card if a PCI-soundcard is added.
373  *
374  * The BIOS only gives options "DISABLED" and "AUTO". This code sets
375  * the corresponding register-value to enable the soundcard.
376  *
377  * The soundcard is only enabled, if the mainborad is identified
378  * via DMI-tables and the soundcard is detected to be off.
379  */
380 static void pci_fixup_msi_k8t_onboard_sound(struct pci_dev *dev)
381 {
382 	unsigned char val;
383 	if (!dmi_check_system(msi_k8t_dmi_table))
384 		return; /* only applies to MSI K8T Neo2-FIR */
385 
386 	pci_read_config_byte(dev, 0x50, &val);
387 	if (val & 0x40) {
388 		pci_write_config_byte(dev, 0x50, val & (~0x40));
389 
390 		/* verify the change for status output */
391 		pci_read_config_byte(dev, 0x50, &val);
392 		if (val & 0x40)
393 			dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
394 					"can't enable onboard soundcard!\n");
395 		else
396 			dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
397 					"enabled onboard soundcard\n");
398 	}
399 }
400 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
401 		pci_fixup_msi_k8t_onboard_sound);
402 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
403 		pci_fixup_msi_k8t_onboard_sound);
404 
405 /*
406  * Some Toshiba laptops need extra code to enable their TI TSB43AB22/A.
407  *
408  * We pretend to bring them out of full D3 state, and restore the proper
409  * IRQ, PCI cache line size, and BARs, otherwise the device won't function
410  * properly.  In some cases, the device will generate an interrupt on
411  * the wrong IRQ line, causing any devices sharing the line it's
412  * *supposed* to use to be disabled by the kernel's IRQ debug code.
413  */
414 static u16 toshiba_line_size;
415 
416 static const struct dmi_system_id toshiba_ohci1394_dmi_table[] = {
417 	{
418 		.ident = "Toshiba PS5 based laptop",
419 		.matches = {
420 			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
421 			DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"),
422 		},
423 	},
424 	{
425 		.ident = "Toshiba PSM4 based laptop",
426 		.matches = {
427 			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
428 			DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"),
429 		},
430 	},
431 	{
432 		.ident = "Toshiba A40 based laptop",
433 		.matches = {
434 			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
435 			DMI_MATCH(DMI_PRODUCT_VERSION, "PSA40U"),
436 		},
437 	},
438 	{ }
439 };
440 
441 static void pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev)
442 {
443 	if (!dmi_check_system(toshiba_ohci1394_dmi_table))
444 		return; /* only applies to certain Toshibas (so far) */
445 
446 	dev->current_state = PCI_D3cold;
447 	pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size);
448 }
449 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032,
450 			 pci_pre_fixup_toshiba_ohci1394);
451 
452 static void pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev)
453 {
454 	if (!dmi_check_system(toshiba_ohci1394_dmi_table))
455 		return; /* only applies to certain Toshibas (so far) */
456 
457 	/* Restore config space on Toshiba laptops */
458 	pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size);
459 	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq);
460 	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
461 			       pci_resource_start(dev, 0));
462 	pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
463 			       pci_resource_start(dev, 1));
464 }
465 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032,
466 			 pci_post_fixup_toshiba_ohci1394);
467 
468 
469 /*
470  * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device
471  * configuration space.
472  */
473 static void pci_early_fixup_cyrix_5530(struct pci_dev *dev)
474 {
475 	u8 r;
476 	/* clear 'F4 Video Configuration Trap' bit */
477 	pci_read_config_byte(dev, 0x42, &r);
478 	r &= 0xfd;
479 	pci_write_config_byte(dev, 0x42, r);
480 }
481 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
482 			pci_early_fixup_cyrix_5530);
483 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
484 			pci_early_fixup_cyrix_5530);
485 
486 /*
487  * Siemens Nixdorf AG FSC Multiprocessor Interrupt Controller:
488  * prevent update of the BAR0, which doesn't look like a normal BAR.
489  */
490 static void pci_siemens_interrupt_controller(struct pci_dev *dev)
491 {
492 	dev->resource[0].flags |= IORESOURCE_PCI_FIXED;
493 }
494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015,
495 			  pci_siemens_interrupt_controller);
496 
497 /*
498  * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from
499  * confusing the PCI engine:
500  */
501 static void sb600_disable_hpet_bar(struct pci_dev *dev)
502 {
503 	u8 val;
504 
505 	/*
506 	 * The SB600 and SB700 both share the same device
507 	 * ID, but the PM register 0x55 does something different
508 	 * for the SB700, so make sure we are dealing with the
509 	 * SB600 before touching the bit:
510 	 */
511 
512 	pci_read_config_byte(dev, 0x08, &val);
513 
514 	if (val < 0x2F) {
515 		outb(0x55, 0xCD6);
516 		val = inb(0xCD7);
517 
518 		/* Set bit 7 in PM register 0x55 */
519 		outb(0x55, 0xCD6);
520 		outb(val | 0x80, 0xCD7);
521 	}
522 }
523 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar);
524 
525 #ifdef CONFIG_HPET_TIMER
526 static void sb600_hpet_quirk(struct pci_dev *dev)
527 {
528 	struct resource *r = &dev->resource[1];
529 
530 	if (r->flags & IORESOURCE_MEM && r->start == hpet_address) {
531 		r->flags |= IORESOURCE_PCI_FIXED;
532 		dev_info(&dev->dev, "reg 0x14 contains HPET; making it immovable\n");
533 	}
534 }
535 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4385, sb600_hpet_quirk);
536 #endif
537 
538 /*
539  * Twinhead H12Y needs us to block out a region otherwise we map devices
540  * there and any access kills the box.
541  *
542  *   See: https://bugzilla.kernel.org/show_bug.cgi?id=10231
543  *
544  * Match off the LPC and svid/sdid (older kernels lose the bridge subvendor)
545  */
546 static void twinhead_reserve_killing_zone(struct pci_dev *dev)
547 {
548         if (dev->subsystem_vendor == 0x14FF && dev->subsystem_device == 0xA003) {
549                 pr_info("Reserving memory on Twinhead H12Y\n");
550                 request_mem_region(0xFFB00000, 0x100000, "twinhead");
551         }
552 }
553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x27B9, twinhead_reserve_killing_zone);
554 
555 /*
556  * Device [8086:2fc0]
557  * Erratum HSE43
558  * CONFIG_TDP_NOMINAL CSR Implemented at Incorrect Offset
559  * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html
560  *
561  * Devices [8086:6f60,6fa0,6fc0]
562  * Erratum BDF2
563  * PCI BARs in the Home Agent Will Return Non-Zero Values During Enumeration
564  * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html
565  */
566 static void pci_invalid_bar(struct pci_dev *dev)
567 {
568 	dev->non_compliant_bars = 1;
569 }
570 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0, pci_invalid_bar);
571 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6f60, pci_invalid_bar);
572 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fa0, pci_invalid_bar);
573 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fc0, pci_invalid_bar);
574