1 /* 2 * Exceptions for specific devices. Usually work-arounds for fatal design flaws. 3 */ 4 5 #include <linux/delay.h> 6 #include <linux/dmi.h> 7 #include <linux/pci.h> 8 #include <linux/init.h> 9 #include <asm/pci_x86.h> 10 11 static void __devinit pci_fixup_i450nx(struct pci_dev *d) 12 { 13 /* 14 * i450NX -- Find and scan all secondary buses on all PXB's. 15 */ 16 int pxb, reg; 17 u8 busno, suba, subb; 18 19 dev_warn(&d->dev, "Searching for i450NX host bridges\n"); 20 reg = 0xd0; 21 for(pxb = 0; pxb < 2; pxb++) { 22 pci_read_config_byte(d, reg++, &busno); 23 pci_read_config_byte(d, reg++, &suba); 24 pci_read_config_byte(d, reg++, &subb); 25 dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, 26 suba, subb); 27 if (busno) 28 pci_scan_bus_with_sysdata(busno); /* Bus A */ 29 if (suba < subb) 30 pci_scan_bus_with_sysdata(suba+1); /* Bus B */ 31 } 32 pcibios_last_bus = -1; 33 } 34 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx); 35 36 static void __devinit pci_fixup_i450gx(struct pci_dev *d) 37 { 38 /* 39 * i450GX and i450KX -- Find and scan all secondary buses. 40 * (called separately for each PCI bridge found) 41 */ 42 u8 busno; 43 pci_read_config_byte(d, 0x4a, &busno); 44 dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno); 45 pci_scan_bus_with_sysdata(busno); 46 pcibios_last_bus = -1; 47 } 48 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx); 49 50 static void __devinit pci_fixup_umc_ide(struct pci_dev *d) 51 { 52 /* 53 * UM8886BF IDE controller sets region type bits incorrectly, 54 * therefore they look like memory despite of them being I/O. 55 */ 56 int i; 57 58 dev_warn(&d->dev, "Fixing base address flags\n"); 59 for(i = 0; i < 4; i++) 60 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO; 61 } 62 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide); 63 64 static void __devinit pci_fixup_ncr53c810(struct pci_dev *d) 65 { 66 /* 67 * NCR 53C810 returns class code 0 (at least on some systems). 68 * Fix class to be PCI_CLASS_STORAGE_SCSI 69 */ 70 if (!d->class) { 71 dev_warn(&d->dev, "Fixing NCR 53C810 class code\n"); 72 d->class = PCI_CLASS_STORAGE_SCSI << 8; 73 } 74 } 75 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810); 76 77 static void __devinit pci_fixup_latency(struct pci_dev *d) 78 { 79 /* 80 * SiS 5597 and 5598 chipsets require latency timer set to 81 * at most 32 to avoid lockups. 82 */ 83 dev_dbg(&d->dev, "Setting max latency to 32\n"); 84 pcibios_max_latency = 32; 85 } 86 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency); 87 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency); 88 89 static void __devinit pci_fixup_piix4_acpi(struct pci_dev *d) 90 { 91 /* 92 * PIIX4 ACPI device: hardwired IRQ9 93 */ 94 d->irq = 9; 95 } 96 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi); 97 98 /* 99 * Addresses issues with problems in the memory write queue timer in 100 * certain VIA Northbridges. This bugfix is per VIA's specifications, 101 * except for the KL133/KM133: clearing bit 5 on those Northbridges seems 102 * to trigger a bug in its integrated ProSavage video card, which 103 * causes screen corruption. We only clear bits 6 and 7 for that chipset, 104 * until VIA can provide us with definitive information on why screen 105 * corruption occurs, and what exactly those bits do. 106 * 107 * VIA 8363,8622,8361 Northbridges: 108 * - bits 5, 6, 7 at offset 0x55 need to be turned off 109 * VIA 8367 (KT266x) Northbridges: 110 * - bits 5, 6, 7 at offset 0x95 need to be turned off 111 * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges: 112 * - bits 6, 7 at offset 0x55 need to be turned off 113 */ 114 115 #define VIA_8363_KL133_REVISION_ID 0x81 116 #define VIA_8363_KM133_REVISION_ID 0x84 117 118 static void pci_fixup_via_northbridge_bug(struct pci_dev *d) 119 { 120 u8 v; 121 int where = 0x55; 122 int mask = 0x1f; /* clear bits 5, 6, 7 by default */ 123 124 if (d->device == PCI_DEVICE_ID_VIA_8367_0) { 125 /* fix pci bus latency issues resulted by NB bios error 126 it appears on bug free^Wreduced kt266x's bios forces 127 NB latency to zero */ 128 pci_write_config_byte(d, PCI_LATENCY_TIMER, 0); 129 130 where = 0x95; /* the memory write queue timer register is 131 different for the KT266x's: 0x95 not 0x55 */ 132 } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 && 133 (d->revision == VIA_8363_KL133_REVISION_ID || 134 d->revision == VIA_8363_KM133_REVISION_ID)) { 135 mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5 136 causes screen corruption on the KL133/KM133 */ 137 } 138 139 pci_read_config_byte(d, where, &v); 140 if (v & ~mask) { 141 dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \ 142 d->device, d->revision, where, v, mask, v & mask); 143 v &= mask; 144 pci_write_config_byte(d, where, v); 145 } 146 } 147 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug); 148 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug); 149 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug); 150 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug); 151 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug); 152 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug); 153 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug); 154 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug); 155 156 /* 157 * For some reasons Intel decided that certain parts of their 158 * 815, 845 and some other chipsets must look like PCI-to-PCI bridges 159 * while they are obviously not. The 82801 family (AA, AB, BAM/CAM, 160 * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according 161 * to Intel terminology. These devices do forward all addresses from 162 * system to PCI bus no matter what are their window settings, so they are 163 * "transparent" (or subtractive decoding) from programmers point of view. 164 */ 165 static void __devinit pci_fixup_transparent_bridge(struct pci_dev *dev) 166 { 167 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && 168 (dev->device & 0xff00) == 0x2400) 169 dev->transparent = 1; 170 } 171 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge); 172 173 /* 174 * Fixup for C1 Halt Disconnect problem on nForce2 systems. 175 * 176 * From information provided by "Allen Martin" <AMartin@nvidia.com>: 177 * 178 * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle 179 * sequence. Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns. 180 * This allows the state-machine and timer to return to a proper state within 181 * 80 ns of the CONNECT and probe appearing together. Since the CPU will not 182 * issue another HALT within 80 ns of the initial HALT, the failure condition 183 * is avoided. 184 */ 185 static void pci_fixup_nforce2(struct pci_dev *dev) 186 { 187 u32 val; 188 189 /* 190 * Chip Old value New value 191 * C17 0x1F0FFF01 0x1F01FF01 192 * C18D 0x9F0FFF01 0x9F01FF01 193 * 194 * Northbridge chip version may be determined by 195 * reading the PCI revision ID (0xC1 or greater is C18D). 196 */ 197 pci_read_config_dword(dev, 0x6c, &val); 198 199 /* 200 * Apply fixup if needed, but don't touch disconnect state 201 */ 202 if ((val & 0x00FF0000) != 0x00010000) { 203 dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n"); 204 pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000); 205 } 206 } 207 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2); 208 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2); 209 210 /* Max PCI Express root ports */ 211 #define MAX_PCIEROOT 6 212 static int quirk_aspm_offset[MAX_PCIEROOT << 3]; 213 214 #define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7)) 215 216 static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) 217 { 218 return raw_pci_read(pci_domain_nr(bus), bus->number, 219 devfn, where, size, value); 220 } 221 222 /* 223 * Replace the original pci bus ops for write with a new one that will filter 224 * the request to insure ASPM cannot be enabled. 225 */ 226 static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) 227 { 228 u8 offset; 229 230 offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)]; 231 232 if ((offset) && (where == offset)) 233 value = value & 0xfffffffc; 234 235 return raw_pci_write(pci_domain_nr(bus), bus->number, 236 devfn, where, size, value); 237 } 238 239 static struct pci_ops quirk_pcie_aspm_ops = { 240 .read = quirk_pcie_aspm_read, 241 .write = quirk_pcie_aspm_write, 242 }; 243 244 /* 245 * Prevents PCI Express ASPM (Active State Power Management) being enabled. 246 * 247 * Save the register offset, where the ASPM control bits are located, 248 * for each PCI Express device that is in the device list of 249 * the root port in an array for fast indexing. Replace the bus ops 250 * with the modified one. 251 */ 252 static void pcie_rootport_aspm_quirk(struct pci_dev *pdev) 253 { 254 int cap_base, i; 255 struct pci_bus *pbus; 256 struct pci_dev *dev; 257 258 if ((pbus = pdev->subordinate) == NULL) 259 return; 260 261 /* 262 * Check if the DID of pdev matches one of the six root ports. This 263 * check is needed in the case this function is called directly by the 264 * hot-plug driver. 265 */ 266 if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) || 267 (pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1)) 268 return; 269 270 if (list_empty(&pbus->devices)) { 271 /* 272 * If no device is attached to the root port at power-up or 273 * after hot-remove, the pbus->devices is empty and this code 274 * will set the offsets to zero and the bus ops to parent's bus 275 * ops, which is unmodified. 276 */ 277 for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i) 278 quirk_aspm_offset[i] = 0; 279 280 pbus->ops = pbus->parent->ops; 281 } else { 282 /* 283 * If devices are attached to the root port at power-up or 284 * after hot-add, the code loops through the device list of 285 * each root port to save the register offsets and replace the 286 * bus ops. 287 */ 288 list_for_each_entry(dev, &pbus->devices, bus_list) { 289 /* There are 0 to 8 devices attached to this bus */ 290 cap_base = pci_find_capability(dev, PCI_CAP_ID_EXP); 291 quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)] = cap_base + 0x10; 292 } 293 pbus->ops = &quirk_pcie_aspm_ops; 294 } 295 } 296 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA, pcie_rootport_aspm_quirk); 297 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA1, pcie_rootport_aspm_quirk); 298 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB, pcie_rootport_aspm_quirk); 299 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB1, pcie_rootport_aspm_quirk); 300 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC, pcie_rootport_aspm_quirk); 301 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC1, pcie_rootport_aspm_quirk); 302 303 /* 304 * Fixup to mark boot BIOS video selected by BIOS before it changes 305 * 306 * From information provided by "Jon Smirl" <jonsmirl@gmail.com> 307 * 308 * The standard boot ROM sequence for an x86 machine uses the BIOS 309 * to select an initial video card for boot display. This boot video 310 * card will have it's BIOS copied to C0000 in system RAM. 311 * IORESOURCE_ROM_SHADOW is used to associate the boot video 312 * card with this copy. On laptops this copy has to be used since 313 * the main ROM may be compressed or combined with another image. 314 * See pci_map_rom() for use of this flag. IORESOURCE_ROM_SHADOW 315 * is marked here since the boot video device will be the only enabled 316 * video device at this point. 317 */ 318 319 static void __devinit pci_fixup_video(struct pci_dev *pdev) 320 { 321 struct pci_dev *bridge; 322 struct pci_bus *bus; 323 u16 config; 324 325 if ((pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA) 326 return; 327 328 /* Is VGA routed to us? */ 329 bus = pdev->bus; 330 while (bus) { 331 bridge = bus->self; 332 333 /* 334 * From information provided by 335 * "David Miller" <davem@davemloft.net> 336 * The bridge control register is valid for PCI header 337 * type BRIDGE, or CARDBUS. Host to PCI controllers use 338 * PCI header type NORMAL. 339 */ 340 if (bridge 341 && ((bridge->hdr_type == PCI_HEADER_TYPE_BRIDGE) 342 || (bridge->hdr_type == PCI_HEADER_TYPE_CARDBUS))) { 343 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, 344 &config); 345 if (!(config & PCI_BRIDGE_CTL_VGA)) 346 return; 347 } 348 bus = bus->parent; 349 } 350 pci_read_config_word(pdev, PCI_COMMAND, &config); 351 if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { 352 pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW; 353 dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n"); 354 } 355 } 356 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video); 357 358 359 static const struct dmi_system_id __devinitconst msi_k8t_dmi_table[] = { 360 { 361 .ident = "MSI-K8T-Neo2Fir", 362 .matches = { 363 DMI_MATCH(DMI_SYS_VENDOR, "MSI"), 364 DMI_MATCH(DMI_PRODUCT_NAME, "MS-6702E"), 365 }, 366 }, 367 {} 368 }; 369 370 /* 371 * The AMD-Athlon64 board MSI "K8T Neo2-FIR" disables the onboard sound 372 * card if a PCI-soundcard is added. 373 * 374 * The BIOS only gives options "DISABLED" and "AUTO". This code sets 375 * the corresponding register-value to enable the soundcard. 376 * 377 * The soundcard is only enabled, if the mainborad is identified 378 * via DMI-tables and the soundcard is detected to be off. 379 */ 380 static void __devinit pci_fixup_msi_k8t_onboard_sound(struct pci_dev *dev) 381 { 382 unsigned char val; 383 if (!dmi_check_system(msi_k8t_dmi_table)) 384 return; /* only applies to MSI K8T Neo2-FIR */ 385 386 pci_read_config_byte(dev, 0x50, &val); 387 if (val & 0x40) { 388 pci_write_config_byte(dev, 0x50, val & (~0x40)); 389 390 /* verify the change for status output */ 391 pci_read_config_byte(dev, 0x50, &val); 392 if (val & 0x40) 393 dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; " 394 "can't enable onboard soundcard!\n"); 395 else 396 dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; " 397 "enabled onboard soundcard\n"); 398 } 399 } 400 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, 401 pci_fixup_msi_k8t_onboard_sound); 402 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, 403 pci_fixup_msi_k8t_onboard_sound); 404 405 /* 406 * Some Toshiba laptops need extra code to enable their TI TSB43AB22/A. 407 * 408 * We pretend to bring them out of full D3 state, and restore the proper 409 * IRQ, PCI cache line size, and BARs, otherwise the device won't function 410 * properly. In some cases, the device will generate an interrupt on 411 * the wrong IRQ line, causing any devices sharing the line it's 412 * *supposed* to use to be disabled by the kernel's IRQ debug code. 413 */ 414 static u16 toshiba_line_size; 415 416 static const struct dmi_system_id __devinitconst toshiba_ohci1394_dmi_table[] = { 417 { 418 .ident = "Toshiba PS5 based laptop", 419 .matches = { 420 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 421 DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"), 422 }, 423 }, 424 { 425 .ident = "Toshiba PSM4 based laptop", 426 .matches = { 427 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 428 DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"), 429 }, 430 }, 431 { 432 .ident = "Toshiba A40 based laptop", 433 .matches = { 434 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 435 DMI_MATCH(DMI_PRODUCT_VERSION, "PSA40U"), 436 }, 437 }, 438 { } 439 }; 440 441 static void __devinit pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev) 442 { 443 if (!dmi_check_system(toshiba_ohci1394_dmi_table)) 444 return; /* only applies to certain Toshibas (so far) */ 445 446 dev->current_state = PCI_D3cold; 447 pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size); 448 } 449 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032, 450 pci_pre_fixup_toshiba_ohci1394); 451 452 static void __devinit pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev) 453 { 454 if (!dmi_check_system(toshiba_ohci1394_dmi_table)) 455 return; /* only applies to certain Toshibas (so far) */ 456 457 /* Restore config space on Toshiba laptops */ 458 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size); 459 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq); 460 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 461 pci_resource_start(dev, 0)); 462 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 463 pci_resource_start(dev, 1)); 464 } 465 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032, 466 pci_post_fixup_toshiba_ohci1394); 467 468 469 /* 470 * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device 471 * configuration space. 472 */ 473 static void pci_early_fixup_cyrix_5530(struct pci_dev *dev) 474 { 475 u8 r; 476 /* clear 'F4 Video Configuration Trap' bit */ 477 pci_read_config_byte(dev, 0x42, &r); 478 r &= 0xfd; 479 pci_write_config_byte(dev, 0x42, r); 480 } 481 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, 482 pci_early_fixup_cyrix_5530); 483 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, 484 pci_early_fixup_cyrix_5530); 485 486 /* 487 * Siemens Nixdorf AG FSC Multiprocessor Interrupt Controller: 488 * prevent update of the BAR0, which doesn't look like a normal BAR. 489 */ 490 static void __devinit pci_siemens_interrupt_controller(struct pci_dev *dev) 491 { 492 dev->resource[0].flags |= IORESOURCE_PCI_FIXED; 493 } 494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015, 495 pci_siemens_interrupt_controller); 496 497 /* 498 * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from 499 * confusing the PCI engine: 500 */ 501 static void sb600_disable_hpet_bar(struct pci_dev *dev) 502 { 503 u8 val; 504 505 /* 506 * The SB600 and SB700 both share the same device 507 * ID, but the PM register 0x55 does something different 508 * for the SB700, so make sure we are dealing with the 509 * SB600 before touching the bit: 510 */ 511 512 pci_read_config_byte(dev, 0x08, &val); 513 514 if (val < 0x2F) { 515 outb(0x55, 0xCD6); 516 val = inb(0xCD7); 517 518 /* Set bit 7 in PM register 0x55 */ 519 outb(0x55, 0xCD6); 520 outb(val | 0x80, 0xCD7); 521 } 522 } 523 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar); 524