1 /* 2 * GPL LICENSE SUMMARY 3 * 4 * Copyright(c) 2010 Intel Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 * The full GNU General Public License is included in this distribution 19 * in the file called LICENSE.GPL. 20 * 21 * Contact Information: 22 * Intel Corporation 23 * 2200 Mission College Blvd. 24 * Santa Clara, CA 97052 25 * 26 * This provides access methods for PCI registers that mis-behave on 27 * the CE4100. Each register can be assigned a private init, read and 28 * write routine. The exception to this is the bridge device. The 29 * bridge device is the only device on bus zero (0) that requires any 30 * fixup so it is a special case ATM 31 */ 32 33 #include <linux/kernel.h> 34 #include <linux/pci.h> 35 #include <linux/init.h> 36 37 #include <asm/pci_x86.h> 38 39 struct sim_reg { 40 u32 value; 41 u32 mask; 42 }; 43 44 struct sim_dev_reg { 45 int dev_func; 46 int reg; 47 void (*init)(struct sim_dev_reg *reg); 48 void (*read)(struct sim_dev_reg *reg, u32 *value); 49 void (*write)(struct sim_dev_reg *reg, u32 value); 50 struct sim_reg sim_reg; 51 }; 52 53 struct sim_reg_op { 54 void (*init)(struct sim_dev_reg *reg); 55 void (*read)(struct sim_dev_reg *reg, u32 value); 56 void (*write)(struct sim_dev_reg *reg, u32 value); 57 }; 58 59 #define MB (1024 * 1024) 60 #define KB (1024) 61 #define SIZE_TO_MASK(size) (~(size - 1)) 62 63 #define DEFINE_REG(device, func, offset, size, init_op, read_op, write_op)\ 64 { PCI_DEVFN(device, func), offset, init_op, read_op, write_op,\ 65 {0, SIZE_TO_MASK(size)} }, 66 67 static void reg_init(struct sim_dev_reg *reg) 68 { 69 pci_direct_conf1.read(0, 1, reg->dev_func, reg->reg, 4, 70 ®->sim_reg.value); 71 } 72 73 static void reg_read(struct sim_dev_reg *reg, u32 *value) 74 { 75 unsigned long flags; 76 77 raw_spin_lock_irqsave(&pci_config_lock, flags); 78 *value = reg->sim_reg.value; 79 raw_spin_unlock_irqrestore(&pci_config_lock, flags); 80 } 81 82 static void reg_write(struct sim_dev_reg *reg, u32 value) 83 { 84 unsigned long flags; 85 86 raw_spin_lock_irqsave(&pci_config_lock, flags); 87 reg->sim_reg.value = (value & reg->sim_reg.mask) | 88 (reg->sim_reg.value & ~reg->sim_reg.mask); 89 raw_spin_unlock_irqrestore(&pci_config_lock, flags); 90 } 91 92 static void sata_reg_init(struct sim_dev_reg *reg) 93 { 94 pci_direct_conf1.read(0, 1, PCI_DEVFN(14, 0), 0x10, 4, 95 ®->sim_reg.value); 96 reg->sim_reg.value += 0x400; 97 } 98 99 static void ehci_reg_read(struct sim_dev_reg *reg, u32 *value) 100 { 101 reg_read(reg, value); 102 if (*value != reg->sim_reg.mask) 103 *value |= 0x100; 104 } 105 106 void sata_revid_init(struct sim_dev_reg *reg) 107 { 108 reg->sim_reg.value = 0x01060100; 109 reg->sim_reg.mask = 0; 110 } 111 112 static void sata_revid_read(struct sim_dev_reg *reg, u32 *value) 113 { 114 reg_read(reg, value); 115 } 116 117 static struct sim_dev_reg bus1_fixups[] = { 118 DEFINE_REG(2, 0, 0x10, (16*MB), reg_init, reg_read, reg_write) 119 DEFINE_REG(2, 0, 0x14, (256), reg_init, reg_read, reg_write) 120 DEFINE_REG(2, 1, 0x10, (64*KB), reg_init, reg_read, reg_write) 121 DEFINE_REG(3, 0, 0x10, (64*KB), reg_init, reg_read, reg_write) 122 DEFINE_REG(4, 0, 0x10, (128*KB), reg_init, reg_read, reg_write) 123 DEFINE_REG(4, 1, 0x10, (128*KB), reg_init, reg_read, reg_write) 124 DEFINE_REG(6, 0, 0x10, (512*KB), reg_init, reg_read, reg_write) 125 DEFINE_REG(6, 1, 0x10, (512*KB), reg_init, reg_read, reg_write) 126 DEFINE_REG(6, 2, 0x10, (64*KB), reg_init, reg_read, reg_write) 127 DEFINE_REG(8, 0, 0x10, (1*MB), reg_init, reg_read, reg_write) 128 DEFINE_REG(8, 1, 0x10, (64*KB), reg_init, reg_read, reg_write) 129 DEFINE_REG(8, 2, 0x10, (64*KB), reg_init, reg_read, reg_write) 130 DEFINE_REG(9, 0, 0x10 , (1*MB), reg_init, reg_read, reg_write) 131 DEFINE_REG(9, 0, 0x14, (64*KB), reg_init, reg_read, reg_write) 132 DEFINE_REG(10, 0, 0x10, (256), reg_init, reg_read, reg_write) 133 DEFINE_REG(10, 0, 0x14, (256*MB), reg_init, reg_read, reg_write) 134 DEFINE_REG(11, 0, 0x10, (256), reg_init, reg_read, reg_write) 135 DEFINE_REG(11, 0, 0x14, (256), reg_init, reg_read, reg_write) 136 DEFINE_REG(11, 1, 0x10, (256), reg_init, reg_read, reg_write) 137 DEFINE_REG(11, 2, 0x10, (256), reg_init, reg_read, reg_write) 138 DEFINE_REG(11, 2, 0x14, (256), reg_init, reg_read, reg_write) 139 DEFINE_REG(11, 2, 0x18, (256), reg_init, reg_read, reg_write) 140 DEFINE_REG(11, 3, 0x10, (256), reg_init, reg_read, reg_write) 141 DEFINE_REG(11, 3, 0x14, (256), reg_init, reg_read, reg_write) 142 DEFINE_REG(11, 4, 0x10, (256), reg_init, reg_read, reg_write) 143 DEFINE_REG(11, 5, 0x10, (64*KB), reg_init, reg_read, reg_write) 144 DEFINE_REG(11, 6, 0x10, (256), reg_init, reg_read, reg_write) 145 DEFINE_REG(11, 7, 0x10, (64*KB), reg_init, reg_read, reg_write) 146 DEFINE_REG(12, 0, 0x10, (128*KB), reg_init, reg_read, reg_write) 147 DEFINE_REG(12, 0, 0x14, (256), reg_init, reg_read, reg_write) 148 DEFINE_REG(12, 1, 0x10, (1024), reg_init, reg_read, reg_write) 149 DEFINE_REG(13, 0, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write) 150 DEFINE_REG(13, 1, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write) 151 DEFINE_REG(14, 0, 0x8, 0, sata_revid_init, sata_revid_read, 0) 152 DEFINE_REG(14, 0, 0x10, 0, reg_init, reg_read, reg_write) 153 DEFINE_REG(14, 0, 0x14, 0, reg_init, reg_read, reg_write) 154 DEFINE_REG(14, 0, 0x18, 0, reg_init, reg_read, reg_write) 155 DEFINE_REG(14, 0, 0x1C, 0, reg_init, reg_read, reg_write) 156 DEFINE_REG(14, 0, 0x20, 0, reg_init, reg_read, reg_write) 157 DEFINE_REG(14, 0, 0x24, (0x200), sata_reg_init, reg_read, reg_write) 158 DEFINE_REG(15, 0, 0x10, (64*KB), reg_init, reg_read, reg_write) 159 DEFINE_REG(15, 0, 0x14, (64*KB), reg_init, reg_read, reg_write) 160 DEFINE_REG(16, 0, 0x10, (64*KB), reg_init, reg_read, reg_write) 161 DEFINE_REG(16, 0, 0x14, (64*MB), reg_init, reg_read, reg_write) 162 DEFINE_REG(16, 0, 0x18, (64*MB), reg_init, reg_read, reg_write) 163 DEFINE_REG(17, 0, 0x10, (128*KB), reg_init, reg_read, reg_write) 164 DEFINE_REG(18, 0, 0x10, (1*KB), reg_init, reg_read, reg_write) 165 }; 166 167 static void __init init_sim_regs(void) 168 { 169 int i; 170 171 for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) { 172 if (bus1_fixups[i].init) 173 bus1_fixups[i].init(&bus1_fixups[i]); 174 } 175 } 176 177 static inline void extract_bytes(u32 *value, int reg, int len) 178 { 179 uint32_t mask; 180 181 *value >>= ((reg & 3) * 8); 182 mask = 0xFFFFFFFF >> ((4 - len) * 8); 183 *value &= mask; 184 } 185 186 int bridge_read(unsigned int devfn, int reg, int len, u32 *value) 187 { 188 u32 av_bridge_base, av_bridge_limit; 189 int retval = 0; 190 191 switch (reg) { 192 /* Make BARs appear to not request any memory. */ 193 case PCI_BASE_ADDRESS_0: 194 case PCI_BASE_ADDRESS_0 + 1: 195 case PCI_BASE_ADDRESS_0 + 2: 196 case PCI_BASE_ADDRESS_0 + 3: 197 *value = 0; 198 break; 199 200 /* Since subordinate bus number register is hardwired 201 * to zero and read only, so do the simulation. 202 */ 203 case PCI_PRIMARY_BUS: 204 if (len == 4) 205 *value = 0x00010100; 206 break; 207 208 case PCI_SUBORDINATE_BUS: 209 *value = 1; 210 break; 211 212 case PCI_MEMORY_BASE: 213 case PCI_MEMORY_LIMIT: 214 /* Get the A/V bridge base address. */ 215 pci_direct_conf1.read(0, 0, devfn, 216 PCI_BASE_ADDRESS_0, 4, &av_bridge_base); 217 218 av_bridge_limit = av_bridge_base + (512*MB - 1); 219 av_bridge_limit >>= 16; 220 av_bridge_limit &= 0xFFF0; 221 222 av_bridge_base >>= 16; 223 av_bridge_base &= 0xFFF0; 224 225 if (reg == PCI_MEMORY_LIMIT) 226 *value = av_bridge_limit; 227 else if (len == 2) 228 *value = av_bridge_base; 229 else 230 *value = (av_bridge_limit << 16) | av_bridge_base; 231 break; 232 /* Make prefetchable memory limit smaller than prefetchable 233 * memory base, so not claim prefetchable memory space. 234 */ 235 case PCI_PREF_MEMORY_BASE: 236 *value = 0xFFF0; 237 break; 238 case PCI_PREF_MEMORY_LIMIT: 239 *value = 0x0; 240 break; 241 /* Make IO limit smaller than IO base, so not claim IO space. */ 242 case PCI_IO_BASE: 243 *value = 0xF0; 244 break; 245 case PCI_IO_LIMIT: 246 *value = 0; 247 break; 248 default: 249 retval = 1; 250 } 251 return retval; 252 } 253 254 static int ce4100_conf_read(unsigned int seg, unsigned int bus, 255 unsigned int devfn, int reg, int len, u32 *value) 256 { 257 int i, retval = 1; 258 259 if (bus == 1) { 260 for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) { 261 if (bus1_fixups[i].dev_func == devfn && 262 bus1_fixups[i].reg == (reg & ~3) && 263 bus1_fixups[i].read) { 264 bus1_fixups[i].read(&(bus1_fixups[i]), 265 value); 266 extract_bytes(value, reg, len); 267 return 0; 268 } 269 } 270 } 271 272 if (bus == 0 && (PCI_DEVFN(1, 0) == devfn) && 273 !bridge_read(devfn, reg, len, value)) 274 return 0; 275 276 return pci_direct_conf1.read(seg, bus, devfn, reg, len, value); 277 } 278 279 static int ce4100_conf_write(unsigned int seg, unsigned int bus, 280 unsigned int devfn, int reg, int len, u32 value) 281 { 282 int i; 283 284 if (bus == 1) { 285 for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) { 286 if (bus1_fixups[i].dev_func == devfn && 287 bus1_fixups[i].reg == (reg & ~3) && 288 bus1_fixups[i].write) { 289 bus1_fixups[i].write(&(bus1_fixups[i]), 290 value); 291 return 0; 292 } 293 } 294 } 295 296 /* Discard writes to A/V bridge BAR. */ 297 if (bus == 0 && PCI_DEVFN(1, 0) == devfn && 298 ((reg & ~3) == PCI_BASE_ADDRESS_0)) 299 return 0; 300 301 return pci_direct_conf1.write(seg, bus, devfn, reg, len, value); 302 } 303 304 struct pci_raw_ops ce4100_pci_conf = { 305 .read = ce4100_conf_read, 306 .write = ce4100_conf_write, 307 }; 308 309 static int __init ce4100_pci_init(void) 310 { 311 init_sim_regs(); 312 raw_pci_ops = &ce4100_pci_conf; 313 return 0; 314 } 315 subsys_initcall(ce4100_pci_init); 316