1 /* 2 * GPL LICENSE SUMMARY 3 * 4 * Copyright(c) 2010 Intel Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 * The full GNU General Public License is included in this distribution 19 * in the file called LICENSE.GPL. 20 * 21 * Contact Information: 22 * Intel Corporation 23 * 2200 Mission College Blvd. 24 * Santa Clara, CA 97052 25 * 26 * This provides access methods for PCI registers that mis-behave on 27 * the CE4100. Each register can be assigned a private init, read and 28 * write routine. The exception to this is the bridge device. The 29 * bridge device is the only device on bus zero (0) that requires any 30 * fixup so it is a special case ATM 31 */ 32 33 #include <linux/kernel.h> 34 #include <linux/pci.h> 35 #include <linux/init.h> 36 37 #include <asm/ce4100.h> 38 #include <asm/pci_x86.h> 39 40 struct sim_reg { 41 u32 value; 42 u32 mask; 43 }; 44 45 struct sim_dev_reg { 46 int dev_func; 47 int reg; 48 void (*init)(struct sim_dev_reg *reg); 49 void (*read)(struct sim_dev_reg *reg, u32 *value); 50 void (*write)(struct sim_dev_reg *reg, u32 value); 51 struct sim_reg sim_reg; 52 }; 53 54 struct sim_reg_op { 55 void (*init)(struct sim_dev_reg *reg); 56 void (*read)(struct sim_dev_reg *reg, u32 value); 57 void (*write)(struct sim_dev_reg *reg, u32 value); 58 }; 59 60 #define MB (1024 * 1024) 61 #define KB (1024) 62 #define SIZE_TO_MASK(size) (~(size - 1)) 63 64 #define DEFINE_REG(device, func, offset, size, init_op, read_op, write_op)\ 65 { PCI_DEVFN(device, func), offset, init_op, read_op, write_op,\ 66 {0, SIZE_TO_MASK(size)} }, 67 68 /* 69 * All read/write functions are called with pci_config_lock held. 70 */ 71 static void reg_init(struct sim_dev_reg *reg) 72 { 73 pci_direct_conf1.read(0, 1, reg->dev_func, reg->reg, 4, 74 ®->sim_reg.value); 75 } 76 77 static void reg_read(struct sim_dev_reg *reg, u32 *value) 78 { 79 *value = reg->sim_reg.value; 80 } 81 82 static void reg_write(struct sim_dev_reg *reg, u32 value) 83 { 84 reg->sim_reg.value = (value & reg->sim_reg.mask) | 85 (reg->sim_reg.value & ~reg->sim_reg.mask); 86 } 87 88 static void sata_reg_init(struct sim_dev_reg *reg) 89 { 90 pci_direct_conf1.read(0, 1, PCI_DEVFN(14, 0), 0x10, 4, 91 ®->sim_reg.value); 92 reg->sim_reg.value += 0x400; 93 } 94 95 static void ehci_reg_read(struct sim_dev_reg *reg, u32 *value) 96 { 97 reg_read(reg, value); 98 if (*value != reg->sim_reg.mask) 99 *value |= 0x100; 100 } 101 102 void sata_revid_init(struct sim_dev_reg *reg) 103 { 104 reg->sim_reg.value = 0x01060100; 105 reg->sim_reg.mask = 0; 106 } 107 108 static void sata_revid_read(struct sim_dev_reg *reg, u32 *value) 109 { 110 reg_read(reg, value); 111 } 112 113 static void reg_noirq_read(struct sim_dev_reg *reg, u32 *value) 114 { 115 /* force interrupt pin value to 0 */ 116 *value = reg->sim_reg.value & 0xfff00ff; 117 } 118 119 static struct sim_dev_reg bus1_fixups[] = { 120 DEFINE_REG(2, 0, 0x10, (16*MB), reg_init, reg_read, reg_write) 121 DEFINE_REG(2, 0, 0x14, (256), reg_init, reg_read, reg_write) 122 DEFINE_REG(2, 1, 0x10, (64*KB), reg_init, reg_read, reg_write) 123 DEFINE_REG(3, 0, 0x10, (64*KB), reg_init, reg_read, reg_write) 124 DEFINE_REG(4, 0, 0x10, (128*KB), reg_init, reg_read, reg_write) 125 DEFINE_REG(4, 1, 0x10, (128*KB), reg_init, reg_read, reg_write) 126 DEFINE_REG(6, 0, 0x10, (512*KB), reg_init, reg_read, reg_write) 127 DEFINE_REG(6, 1, 0x10, (512*KB), reg_init, reg_read, reg_write) 128 DEFINE_REG(6, 2, 0x10, (64*KB), reg_init, reg_read, reg_write) 129 DEFINE_REG(8, 0, 0x10, (1*MB), reg_init, reg_read, reg_write) 130 DEFINE_REG(8, 1, 0x10, (64*KB), reg_init, reg_read, reg_write) 131 DEFINE_REG(8, 2, 0x10, (64*KB), reg_init, reg_read, reg_write) 132 DEFINE_REG(9, 0, 0x10 , (1*MB), reg_init, reg_read, reg_write) 133 DEFINE_REG(9, 0, 0x14, (64*KB), reg_init, reg_read, reg_write) 134 DEFINE_REG(10, 0, 0x10, (256), reg_init, reg_read, reg_write) 135 DEFINE_REG(10, 0, 0x14, (256*MB), reg_init, reg_read, reg_write) 136 DEFINE_REG(11, 0, 0x10, (256), reg_init, reg_read, reg_write) 137 DEFINE_REG(11, 0, 0x14, (256), reg_init, reg_read, reg_write) 138 DEFINE_REG(11, 1, 0x10, (256), reg_init, reg_read, reg_write) 139 DEFINE_REG(11, 2, 0x10, (256), reg_init, reg_read, reg_write) 140 DEFINE_REG(11, 2, 0x14, (256), reg_init, reg_read, reg_write) 141 DEFINE_REG(11, 2, 0x18, (256), reg_init, reg_read, reg_write) 142 DEFINE_REG(11, 3, 0x10, (256), reg_init, reg_read, reg_write) 143 DEFINE_REG(11, 3, 0x14, (256), reg_init, reg_read, reg_write) 144 DEFINE_REG(11, 4, 0x10, (256), reg_init, reg_read, reg_write) 145 DEFINE_REG(11, 5, 0x10, (64*KB), reg_init, reg_read, reg_write) 146 DEFINE_REG(11, 6, 0x10, (256), reg_init, reg_read, reg_write) 147 DEFINE_REG(11, 7, 0x10, (64*KB), reg_init, reg_read, reg_write) 148 DEFINE_REG(11, 7, 0x3c, 256, reg_init, reg_noirq_read, reg_write) 149 DEFINE_REG(12, 0, 0x10, (128*KB), reg_init, reg_read, reg_write) 150 DEFINE_REG(12, 0, 0x14, (256), reg_init, reg_read, reg_write) 151 DEFINE_REG(12, 1, 0x10, (1024), reg_init, reg_read, reg_write) 152 DEFINE_REG(13, 0, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write) 153 DEFINE_REG(13, 1, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write) 154 DEFINE_REG(14, 0, 0x8, 0, sata_revid_init, sata_revid_read, 0) 155 DEFINE_REG(14, 0, 0x10, 0, reg_init, reg_read, reg_write) 156 DEFINE_REG(14, 0, 0x14, 0, reg_init, reg_read, reg_write) 157 DEFINE_REG(14, 0, 0x18, 0, reg_init, reg_read, reg_write) 158 DEFINE_REG(14, 0, 0x1C, 0, reg_init, reg_read, reg_write) 159 DEFINE_REG(14, 0, 0x20, 0, reg_init, reg_read, reg_write) 160 DEFINE_REG(14, 0, 0x24, (0x200), sata_reg_init, reg_read, reg_write) 161 DEFINE_REG(15, 0, 0x10, (64*KB), reg_init, reg_read, reg_write) 162 DEFINE_REG(15, 0, 0x14, (64*KB), reg_init, reg_read, reg_write) 163 DEFINE_REG(16, 0, 0x10, (64*KB), reg_init, reg_read, reg_write) 164 DEFINE_REG(16, 0, 0x14, (64*MB), reg_init, reg_read, reg_write) 165 DEFINE_REG(16, 0, 0x18, (64*MB), reg_init, reg_read, reg_write) 166 DEFINE_REG(16, 0, 0x3c, 256, reg_init, reg_noirq_read, reg_write) 167 DEFINE_REG(17, 0, 0x10, (128*KB), reg_init, reg_read, reg_write) 168 DEFINE_REG(18, 0, 0x10, (1*KB), reg_init, reg_read, reg_write) 169 DEFINE_REG(18, 0, 0x3c, 256, reg_init, reg_noirq_read, reg_write) 170 }; 171 172 static void __init init_sim_regs(void) 173 { 174 int i; 175 176 for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) { 177 if (bus1_fixups[i].init) 178 bus1_fixups[i].init(&bus1_fixups[i]); 179 } 180 } 181 182 static inline void extract_bytes(u32 *value, int reg, int len) 183 { 184 uint32_t mask; 185 186 *value >>= ((reg & 3) * 8); 187 mask = 0xFFFFFFFF >> ((4 - len) * 8); 188 *value &= mask; 189 } 190 191 int bridge_read(unsigned int devfn, int reg, int len, u32 *value) 192 { 193 u32 av_bridge_base, av_bridge_limit; 194 int retval = 0; 195 196 switch (reg) { 197 /* Make BARs appear to not request any memory. */ 198 case PCI_BASE_ADDRESS_0: 199 case PCI_BASE_ADDRESS_0 + 1: 200 case PCI_BASE_ADDRESS_0 + 2: 201 case PCI_BASE_ADDRESS_0 + 3: 202 *value = 0; 203 break; 204 205 /* Since subordinate bus number register is hardwired 206 * to zero and read only, so do the simulation. 207 */ 208 case PCI_PRIMARY_BUS: 209 if (len == 4) 210 *value = 0x00010100; 211 break; 212 213 case PCI_SUBORDINATE_BUS: 214 *value = 1; 215 break; 216 217 case PCI_MEMORY_BASE: 218 case PCI_MEMORY_LIMIT: 219 /* Get the A/V bridge base address. */ 220 pci_direct_conf1.read(0, 0, devfn, 221 PCI_BASE_ADDRESS_0, 4, &av_bridge_base); 222 223 av_bridge_limit = av_bridge_base + (512*MB - 1); 224 av_bridge_limit >>= 16; 225 av_bridge_limit &= 0xFFF0; 226 227 av_bridge_base >>= 16; 228 av_bridge_base &= 0xFFF0; 229 230 if (reg == PCI_MEMORY_LIMIT) 231 *value = av_bridge_limit; 232 else if (len == 2) 233 *value = av_bridge_base; 234 else 235 *value = (av_bridge_limit << 16) | av_bridge_base; 236 break; 237 /* Make prefetchable memory limit smaller than prefetchable 238 * memory base, so not claim prefetchable memory space. 239 */ 240 case PCI_PREF_MEMORY_BASE: 241 *value = 0xFFF0; 242 break; 243 case PCI_PREF_MEMORY_LIMIT: 244 *value = 0x0; 245 break; 246 /* Make IO limit smaller than IO base, so not claim IO space. */ 247 case PCI_IO_BASE: 248 *value = 0xF0; 249 break; 250 case PCI_IO_LIMIT: 251 *value = 0; 252 break; 253 default: 254 retval = 1; 255 } 256 return retval; 257 } 258 259 static int ce4100_bus1_read(unsigned int devfn, int reg, int len, u32 *value) 260 { 261 unsigned long flags; 262 int i; 263 264 for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) { 265 if (bus1_fixups[i].dev_func == devfn && 266 bus1_fixups[i].reg == (reg & ~3) && 267 bus1_fixups[i].read) { 268 269 raw_spin_lock_irqsave(&pci_config_lock, flags); 270 bus1_fixups[i].read(&(bus1_fixups[i]), value); 271 raw_spin_unlock_irqrestore(&pci_config_lock, flags); 272 extract_bytes(value, reg, len); 273 return 0; 274 } 275 } 276 return -1; 277 } 278 279 static int ce4100_conf_read(unsigned int seg, unsigned int bus, 280 unsigned int devfn, int reg, int len, u32 *value) 281 { 282 WARN_ON(seg); 283 284 if (bus == 1 && !ce4100_bus1_read(devfn, reg, len, value)) 285 return 0; 286 287 if (bus == 0 && (PCI_DEVFN(1, 0) == devfn) && 288 !bridge_read(devfn, reg, len, value)) 289 return 0; 290 291 return pci_direct_conf1.read(seg, bus, devfn, reg, len, value); 292 } 293 294 static int ce4100_bus1_write(unsigned int devfn, int reg, int len, u32 value) 295 { 296 unsigned long flags; 297 int i; 298 299 for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) { 300 if (bus1_fixups[i].dev_func == devfn && 301 bus1_fixups[i].reg == (reg & ~3) && 302 bus1_fixups[i].write) { 303 304 raw_spin_lock_irqsave(&pci_config_lock, flags); 305 bus1_fixups[i].write(&(bus1_fixups[i]), value); 306 raw_spin_unlock_irqrestore(&pci_config_lock, flags); 307 return 0; 308 } 309 } 310 return -1; 311 } 312 313 static int ce4100_conf_write(unsigned int seg, unsigned int bus, 314 unsigned int devfn, int reg, int len, u32 value) 315 { 316 WARN_ON(seg); 317 318 if (bus == 1 && !ce4100_bus1_write(devfn, reg, len, value)) 319 return 0; 320 321 /* Discard writes to A/V bridge BAR. */ 322 if (bus == 0 && PCI_DEVFN(1, 0) == devfn && 323 ((reg & ~3) == PCI_BASE_ADDRESS_0)) 324 return 0; 325 326 return pci_direct_conf1.write(seg, bus, devfn, reg, len, value); 327 } 328 329 static const struct pci_raw_ops ce4100_pci_conf = { 330 .read = ce4100_conf_read, 331 .write = ce4100_conf_write, 332 }; 333 334 int __init ce4100_pci_init(void) 335 { 336 init_sim_regs(); 337 raw_pci_ops = &ce4100_pci_conf; 338 /* Indicate caller that it should invoke pci_legacy_init() */ 339 return 1; 340 } 341