1 /* 2 * Read address ranges from a Broadcom CNB20LE Host Bridge 3 * 4 * Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12 #include <linux/acpi.h> 13 #include <linux/delay.h> 14 #include <linux/dmi.h> 15 #include <linux/pci.h> 16 #include <linux/init.h> 17 #include <asm/pci_x86.h> 18 #include <asm/pci-direct.h> 19 20 #include "bus_numa.h" 21 22 static void __init cnb20le_res(u8 bus, u8 slot, u8 func) 23 { 24 struct pci_root_info *info; 25 struct resource res; 26 u16 word1, word2; 27 u8 fbus, lbus; 28 int i; 29 30 info = &pci_root_info[pci_root_num]; 31 pci_root_num++; 32 33 /* read the PCI bus numbers */ 34 fbus = read_pci_config_byte(bus, slot, func, 0x44); 35 lbus = read_pci_config_byte(bus, slot, func, 0x45); 36 info->bus_min = fbus; 37 info->bus_max = lbus; 38 39 /* 40 * Add the legacy IDE ports on bus 0 41 * 42 * These do not exist anywhere in the bridge registers, AFAICT. I do 43 * not have the datasheet, so this is the best I can do. 44 */ 45 if (fbus == 0) { 46 update_res(info, 0x01f0, 0x01f7, IORESOURCE_IO, 0); 47 update_res(info, 0x03f6, 0x03f6, IORESOURCE_IO, 0); 48 update_res(info, 0x0170, 0x0177, IORESOURCE_IO, 0); 49 update_res(info, 0x0376, 0x0376, IORESOURCE_IO, 0); 50 update_res(info, 0xffa0, 0xffaf, IORESOURCE_IO, 0); 51 } 52 53 /* read the non-prefetchable memory window */ 54 word1 = read_pci_config_16(bus, slot, func, 0xc0); 55 word2 = read_pci_config_16(bus, slot, func, 0xc2); 56 if (word1 != word2) { 57 res.start = (word1 << 16) | 0x0000; 58 res.end = (word2 << 16) | 0xffff; 59 res.flags = IORESOURCE_MEM; 60 update_res(info, res.start, res.end, res.flags, 0); 61 } 62 63 /* read the prefetchable memory window */ 64 word1 = read_pci_config_16(bus, slot, func, 0xc4); 65 word2 = read_pci_config_16(bus, slot, func, 0xc6); 66 if (word1 != word2) { 67 res.start = (word1 << 16) | 0x0000; 68 res.end = (word2 << 16) | 0xffff; 69 res.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; 70 update_res(info, res.start, res.end, res.flags, 0); 71 } 72 73 /* read the IO port window */ 74 word1 = read_pci_config_16(bus, slot, func, 0xd0); 75 word2 = read_pci_config_16(bus, slot, func, 0xd2); 76 if (word1 != word2) { 77 res.start = word1; 78 res.end = word2; 79 res.flags = IORESOURCE_IO; 80 update_res(info, res.start, res.end, res.flags, 0); 81 } 82 83 /* print information about this host bridge */ 84 res.start = fbus; 85 res.end = lbus; 86 res.flags = IORESOURCE_BUS; 87 printk(KERN_INFO "CNB20LE PCI Host Bridge (domain 0000 %pR)\n", &res); 88 89 for (i = 0; i < info->res_num; i++) 90 printk(KERN_INFO "host bridge window %pR\n", &info->res[i]); 91 } 92 93 static int __init broadcom_postcore_init(void) 94 { 95 u8 bus = 0, slot = 0; 96 u32 id; 97 u16 vendor, device; 98 99 #ifdef CONFIG_ACPI 100 /* 101 * We should get host bridge information from ACPI unless the BIOS 102 * doesn't support it. 103 */ 104 if (acpi_os_get_root_pointer()) 105 return 0; 106 #endif 107 108 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID); 109 vendor = id & 0xffff; 110 device = (id >> 16) & 0xffff; 111 112 if (vendor == PCI_VENDOR_ID_SERVERWORKS && 113 device == PCI_DEVICE_ID_SERVERWORKS_LE) { 114 cnb20le_res(bus, slot, 0); 115 cnb20le_res(bus, slot, 1); 116 } 117 return 0; 118 } 119 120 postcore_initcall(broadcom_postcore_init); 121