1 #include <linux/init.h> 2 #include <linux/pci.h> 3 #include <linux/topology.h> 4 #include <linux/cpu.h> 5 #include <asm/pci_x86.h> 6 7 #ifdef CONFIG_X86_64 8 #include <asm/pci-direct.h> 9 #include <asm/mpspec.h> 10 #include <linux/cpumask.h> 11 #endif 12 13 /* 14 * This discovers the pcibus <-> node mapping on AMD K8. 15 * also get peer root bus resource for io,mmio 16 */ 17 18 #ifdef CONFIG_X86_64 19 20 /* 21 * sub bus (transparent) will use entres from 3 to store extra from root, 22 * so need to make sure have enought slot there, increase PCI_BUS_NUM_RESOURCES? 23 */ 24 #define RES_NUM 16 25 struct pci_root_info { 26 char name[12]; 27 unsigned int res_num; 28 struct resource res[RES_NUM]; 29 int bus_min; 30 int bus_max; 31 int node; 32 int link; 33 }; 34 35 /* 4 at this time, it may become to 32 */ 36 #define PCI_ROOT_NR 4 37 static int pci_root_num; 38 static struct pci_root_info pci_root_info[PCI_ROOT_NR]; 39 40 void x86_pci_root_bus_res_quirks(struct pci_bus *b) 41 { 42 int i; 43 int j; 44 struct pci_root_info *info; 45 46 /* don't go for it if _CRS is used already */ 47 if (b->resource[0] != &ioport_resource || 48 b->resource[1] != &iomem_resource) 49 return; 50 51 /* if only one root bus, don't need to anything */ 52 if (pci_root_num < 2) 53 return; 54 55 for (i = 0; i < pci_root_num; i++) { 56 if (pci_root_info[i].bus_min == b->number) 57 break; 58 } 59 60 if (i == pci_root_num) 61 return; 62 63 printk(KERN_DEBUG "PCI: peer root bus %02x res updated from pci conf\n", 64 b->number); 65 66 info = &pci_root_info[i]; 67 for (j = 0; j < info->res_num; j++) { 68 struct resource *res; 69 struct resource *root; 70 71 res = &info->res[j]; 72 b->resource[j] = res; 73 if (res->flags & IORESOURCE_IO) 74 root = &ioport_resource; 75 else 76 root = &iomem_resource; 77 insert_resource(root, res); 78 } 79 } 80 81 #define RANGE_NUM 16 82 83 struct res_range { 84 size_t start; 85 size_t end; 86 }; 87 88 static void __init update_range(struct res_range *range, size_t start, 89 size_t end) 90 { 91 int i; 92 int j; 93 94 for (j = 0; j < RANGE_NUM; j++) { 95 if (!range[j].end) 96 continue; 97 98 if (start <= range[j].start && end >= range[j].end) { 99 range[j].start = 0; 100 range[j].end = 0; 101 continue; 102 } 103 104 if (start <= range[j].start && end < range[j].end && range[j].start < end + 1) { 105 range[j].start = end + 1; 106 continue; 107 } 108 109 110 if (start > range[j].start && end >= range[j].end && range[j].end > start - 1) { 111 range[j].end = start - 1; 112 continue; 113 } 114 115 if (start > range[j].start && end < range[j].end) { 116 /* find the new spare */ 117 for (i = 0; i < RANGE_NUM; i++) { 118 if (range[i].end == 0) 119 break; 120 } 121 if (i < RANGE_NUM) { 122 range[i].end = range[j].end; 123 range[i].start = end + 1; 124 } else { 125 printk(KERN_ERR "run of slot in ranges\n"); 126 } 127 range[j].end = start - 1; 128 continue; 129 } 130 } 131 } 132 133 static void __init update_res(struct pci_root_info *info, size_t start, 134 size_t end, unsigned long flags, int merge) 135 { 136 int i; 137 struct resource *res; 138 139 if (!merge) 140 goto addit; 141 142 /* try to merge it with old one */ 143 for (i = 0; i < info->res_num; i++) { 144 size_t final_start, final_end; 145 size_t common_start, common_end; 146 147 res = &info->res[i]; 148 if (res->flags != flags) 149 continue; 150 151 common_start = max((size_t)res->start, start); 152 common_end = min((size_t)res->end, end); 153 if (common_start > common_end + 1) 154 continue; 155 156 final_start = min((size_t)res->start, start); 157 final_end = max((size_t)res->end, end); 158 159 res->start = final_start; 160 res->end = final_end; 161 return; 162 } 163 164 addit: 165 166 /* need to add that */ 167 if (info->res_num >= RES_NUM) 168 return; 169 170 res = &info->res[info->res_num]; 171 res->name = info->name; 172 res->flags = flags; 173 res->start = start; 174 res->end = end; 175 res->child = NULL; 176 info->res_num++; 177 } 178 179 struct pci_hostbridge_probe { 180 u32 bus; 181 u32 slot; 182 u32 vendor; 183 u32 device; 184 }; 185 186 static struct pci_hostbridge_probe pci_probes[] __initdata = { 187 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 }, 188 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 }, 189 { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 }, 190 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 }, 191 }; 192 193 static u64 __initdata fam10h_mmconf_start; 194 static u64 __initdata fam10h_mmconf_end; 195 static void __init get_pci_mmcfg_amd_fam10h_range(void) 196 { 197 u32 address; 198 u64 base, msr; 199 unsigned segn_busn_bits; 200 201 /* assume all cpus from fam10h have mmconf */ 202 if (boot_cpu_data.x86 < 0x10) 203 return; 204 205 address = MSR_FAM10H_MMIO_CONF_BASE; 206 rdmsrl(address, msr); 207 208 /* mmconfig is not enable */ 209 if (!(msr & FAM10H_MMIO_CONF_ENABLE)) 210 return; 211 212 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT); 213 214 segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) & 215 FAM10H_MMIO_CONF_BUSRANGE_MASK; 216 217 fam10h_mmconf_start = base; 218 fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1; 219 } 220 221 /** 222 * early_fill_mp_bus_to_node() 223 * called before pcibios_scan_root and pci_scan_bus 224 * fills the mp_bus_to_cpumask array based according to the LDT Bus Number 225 * Registers found in the K8 northbridge 226 */ 227 static int __init early_fill_mp_bus_info(void) 228 { 229 int i; 230 int j; 231 unsigned bus; 232 unsigned slot; 233 int found; 234 int node; 235 int link; 236 int def_node; 237 int def_link; 238 struct pci_root_info *info; 239 u32 reg; 240 struct resource *res; 241 size_t start; 242 size_t end; 243 struct res_range range[RANGE_NUM]; 244 u64 val; 245 u32 address; 246 247 if (!early_pci_allowed()) 248 return -1; 249 250 found = 0; 251 for (i = 0; i < ARRAY_SIZE(pci_probes); i++) { 252 u32 id; 253 u16 device; 254 u16 vendor; 255 256 bus = pci_probes[i].bus; 257 slot = pci_probes[i].slot; 258 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID); 259 260 vendor = id & 0xffff; 261 device = (id>>16) & 0xffff; 262 if (pci_probes[i].vendor == vendor && 263 pci_probes[i].device == device) { 264 found = 1; 265 break; 266 } 267 } 268 269 if (!found) 270 return 0; 271 272 pci_root_num = 0; 273 for (i = 0; i < 4; i++) { 274 int min_bus; 275 int max_bus; 276 reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2)); 277 278 /* Check if that register is enabled for bus range */ 279 if ((reg & 7) != 3) 280 continue; 281 282 min_bus = (reg >> 16) & 0xff; 283 max_bus = (reg >> 24) & 0xff; 284 node = (reg >> 4) & 0x07; 285 #ifdef CONFIG_NUMA 286 for (j = min_bus; j <= max_bus; j++) 287 set_mp_bus_to_node(j, node); 288 #endif 289 link = (reg >> 8) & 0x03; 290 291 info = &pci_root_info[pci_root_num]; 292 info->bus_min = min_bus; 293 info->bus_max = max_bus; 294 info->node = node; 295 info->link = link; 296 sprintf(info->name, "PCI Bus #%02x", min_bus); 297 pci_root_num++; 298 } 299 300 /* get the default node and link for left over res */ 301 reg = read_pci_config(bus, slot, 0, 0x60); 302 def_node = (reg >> 8) & 0x07; 303 reg = read_pci_config(bus, slot, 0, 0x64); 304 def_link = (reg >> 8) & 0x03; 305 306 memset(range, 0, sizeof(range)); 307 range[0].end = 0xffff; 308 /* io port resource */ 309 for (i = 0; i < 4; i++) { 310 reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3)); 311 if (!(reg & 3)) 312 continue; 313 314 start = reg & 0xfff000; 315 reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3)); 316 node = reg & 0x07; 317 link = (reg >> 4) & 0x03; 318 end = (reg & 0xfff000) | 0xfff; 319 320 /* find the position */ 321 for (j = 0; j < pci_root_num; j++) { 322 info = &pci_root_info[j]; 323 if (info->node == node && info->link == link) 324 break; 325 } 326 if (j == pci_root_num) 327 continue; /* not found */ 328 329 info = &pci_root_info[j]; 330 printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n", 331 node, link, (u64)start, (u64)end); 332 333 /* kernel only handle 16 bit only */ 334 if (end > 0xffff) 335 end = 0xffff; 336 update_res(info, start, end, IORESOURCE_IO, 1); 337 update_range(range, start, end); 338 } 339 /* add left over io port range to def node/link, [0, 0xffff] */ 340 /* find the position */ 341 for (j = 0; j < pci_root_num; j++) { 342 info = &pci_root_info[j]; 343 if (info->node == def_node && info->link == def_link) 344 break; 345 } 346 if (j < pci_root_num) { 347 info = &pci_root_info[j]; 348 for (i = 0; i < RANGE_NUM; i++) { 349 if (!range[i].end) 350 continue; 351 352 update_res(info, range[i].start, range[i].end, 353 IORESOURCE_IO, 1); 354 } 355 } 356 357 memset(range, 0, sizeof(range)); 358 /* 0xfd00000000-0xffffffffff for HT */ 359 range[0].end = (0xfdULL<<32) - 1; 360 361 /* need to take out [0, TOM) for RAM*/ 362 address = MSR_K8_TOP_MEM1; 363 rdmsrl(address, val); 364 end = (val & 0xffffff800000ULL); 365 printk(KERN_INFO "TOM: %016lx aka %ldM\n", end, end>>20); 366 if (end < (1ULL<<32)) 367 update_range(range, 0, end - 1); 368 369 /* get mmconfig */ 370 get_pci_mmcfg_amd_fam10h_range(); 371 /* need to take out mmconf range */ 372 if (fam10h_mmconf_end) { 373 printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end); 374 update_range(range, fam10h_mmconf_start, fam10h_mmconf_end); 375 } 376 377 /* mmio resource */ 378 for (i = 0; i < 8; i++) { 379 reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3)); 380 if (!(reg & 3)) 381 continue; 382 383 start = reg & 0xffffff00; /* 39:16 on 31:8*/ 384 start <<= 8; 385 reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3)); 386 node = reg & 0x07; 387 link = (reg >> 4) & 0x03; 388 end = (reg & 0xffffff00); 389 end <<= 8; 390 end |= 0xffff; 391 392 /* find the position */ 393 for (j = 0; j < pci_root_num; j++) { 394 info = &pci_root_info[j]; 395 if (info->node == node && info->link == link) 396 break; 397 } 398 if (j == pci_root_num) 399 continue; /* not found */ 400 401 info = &pci_root_info[j]; 402 403 printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]", 404 node, link, (u64)start, (u64)end); 405 /* 406 * some sick allocation would have range overlap with fam10h 407 * mmconf range, so need to update start and end. 408 */ 409 if (fam10h_mmconf_end) { 410 int changed = 0; 411 u64 endx = 0; 412 if (start >= fam10h_mmconf_start && 413 start <= fam10h_mmconf_end) { 414 start = fam10h_mmconf_end + 1; 415 changed = 1; 416 } 417 418 if (end >= fam10h_mmconf_start && 419 end <= fam10h_mmconf_end) { 420 end = fam10h_mmconf_start - 1; 421 changed = 1; 422 } 423 424 if (start < fam10h_mmconf_start && 425 end > fam10h_mmconf_end) { 426 /* we got a hole */ 427 endx = fam10h_mmconf_start - 1; 428 update_res(info, start, endx, IORESOURCE_MEM, 0); 429 update_range(range, start, endx); 430 printk(KERN_CONT " ==> [%llx, %llx]", (u64)start, endx); 431 start = fam10h_mmconf_end + 1; 432 changed = 1; 433 } 434 if (changed) { 435 if (start <= end) { 436 printk(KERN_CONT " %s [%llx, %llx]", endx?"and":"==>", (u64)start, (u64)end); 437 } else { 438 printk(KERN_CONT "%s\n", endx?"":" ==> none"); 439 continue; 440 } 441 } 442 } 443 444 update_res(info, start, end, IORESOURCE_MEM, 1); 445 update_range(range, start, end); 446 printk(KERN_CONT "\n"); 447 } 448 449 /* need to take out [4G, TOM2) for RAM*/ 450 /* SYS_CFG */ 451 address = MSR_K8_SYSCFG; 452 rdmsrl(address, val); 453 /* TOP_MEM2 is enabled? */ 454 if (val & (1<<21)) { 455 /* TOP_MEM2 */ 456 address = MSR_K8_TOP_MEM2; 457 rdmsrl(address, val); 458 end = (val & 0xffffff800000ULL); 459 printk(KERN_INFO "TOM2: %016lx aka %ldM\n", end, end>>20); 460 update_range(range, 1ULL<<32, end - 1); 461 } 462 463 /* 464 * add left over mmio range to def node/link ? 465 * that is tricky, just record range in from start_min to 4G 466 */ 467 for (j = 0; j < pci_root_num; j++) { 468 info = &pci_root_info[j]; 469 if (info->node == def_node && info->link == def_link) 470 break; 471 } 472 if (j < pci_root_num) { 473 info = &pci_root_info[j]; 474 475 for (i = 0; i < RANGE_NUM; i++) { 476 if (!range[i].end) 477 continue; 478 479 update_res(info, range[i].start, range[i].end, 480 IORESOURCE_MEM, 1); 481 } 482 } 483 484 for (i = 0; i < pci_root_num; i++) { 485 int res_num; 486 int busnum; 487 488 info = &pci_root_info[i]; 489 res_num = info->res_num; 490 busnum = info->bus_min; 491 printk(KERN_DEBUG "bus: [%02x,%02x] on node %x link %x\n", 492 info->bus_min, info->bus_max, info->node, info->link); 493 for (j = 0; j < res_num; j++) { 494 res = &info->res[j]; 495 printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n", 496 busnum, j, 497 (res->flags & IORESOURCE_IO)?"io port":"mmio", 498 res->start, res->end); 499 } 500 } 501 502 return 0; 503 } 504 505 #else /* !CONFIG_X86_64 */ 506 507 static int __init early_fill_mp_bus_info(void) { return 0; } 508 509 #endif /* !CONFIG_X86_64 */ 510 511 /* common 32/64 bit code */ 512 513 #define ENABLE_CF8_EXT_CFG (1ULL << 46) 514 515 static void enable_pci_io_ecs(void *unused) 516 { 517 u64 reg; 518 rdmsrl(MSR_AMD64_NB_CFG, reg); 519 if (!(reg & ENABLE_CF8_EXT_CFG)) { 520 reg |= ENABLE_CF8_EXT_CFG; 521 wrmsrl(MSR_AMD64_NB_CFG, reg); 522 } 523 } 524 525 static int __cpuinit amd_cpu_notify(struct notifier_block *self, 526 unsigned long action, void *hcpu) 527 { 528 int cpu = (long)hcpu; 529 switch (action) { 530 case CPU_ONLINE: 531 case CPU_ONLINE_FROZEN: 532 smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0); 533 break; 534 default: 535 break; 536 } 537 return NOTIFY_OK; 538 } 539 540 static struct notifier_block __cpuinitdata amd_cpu_notifier = { 541 .notifier_call = amd_cpu_notify, 542 }; 543 544 static int __init pci_io_ecs_init(void) 545 { 546 int cpu; 547 548 /* assume all cpus from fam10h have IO ECS */ 549 if (boot_cpu_data.x86 < 0x10) 550 return 0; 551 552 register_cpu_notifier(&amd_cpu_notifier); 553 for_each_online_cpu(cpu) 554 amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE, 555 (void *)(long)cpu); 556 pci_probe |= PCI_HAS_IO_ECS; 557 558 return 0; 559 } 560 561 static int __init amd_postcore_init(void) 562 { 563 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) 564 return 0; 565 566 early_fill_mp_bus_info(); 567 pci_io_ecs_init(); 568 569 return 0; 570 } 571 572 postcore_initcall(amd_postcore_init); 573