1 #include <linux/init.h> 2 #include <linux/pci.h> 3 #include <linux/topology.h> 4 #include <linux/cpu.h> 5 #include <linux/range.h> 6 7 #include <asm/amd_nb.h> 8 #include <asm/pci_x86.h> 9 10 #include <asm/pci-direct.h> 11 12 #include "bus_numa.h" 13 14 /* 15 * This discovers the pcibus <-> node mapping on AMD K8. 16 * also get peer root bus resource for io,mmio 17 */ 18 19 struct pci_hostbridge_probe { 20 u32 bus; 21 u32 slot; 22 u32 vendor; 23 u32 device; 24 }; 25 26 static struct pci_hostbridge_probe pci_probes[] __initdata = { 27 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 }, 28 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 }, 29 { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 }, 30 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 }, 31 }; 32 33 #define RANGE_NUM 16 34 35 static struct pci_root_info __init *find_pci_root_info(int node, int link) 36 { 37 struct pci_root_info *info; 38 39 /* find the position */ 40 list_for_each_entry(info, &pci_root_infos, list) 41 if (info->node == node && info->link == link) 42 return info; 43 44 return NULL; 45 } 46 47 /** 48 * early_fill_mp_bus_to_node() 49 * called before pcibios_scan_root and pci_scan_bus 50 * fills the mp_bus_to_cpumask array based according to the LDT Bus Number 51 * Registers found in the K8 northbridge 52 */ 53 static int __init early_fill_mp_bus_info(void) 54 { 55 int i; 56 unsigned bus; 57 unsigned slot; 58 int node; 59 int link; 60 int def_node; 61 int def_link; 62 struct pci_root_info *info; 63 u32 reg; 64 u64 start; 65 u64 end; 66 struct range range[RANGE_NUM]; 67 u64 val; 68 u32 address; 69 bool found; 70 struct resource fam10h_mmconf_res, *fam10h_mmconf; 71 u64 fam10h_mmconf_start; 72 u64 fam10h_mmconf_end; 73 74 if (!early_pci_allowed()) 75 return -1; 76 77 found = false; 78 for (i = 0; i < ARRAY_SIZE(pci_probes); i++) { 79 u32 id; 80 u16 device; 81 u16 vendor; 82 83 bus = pci_probes[i].bus; 84 slot = pci_probes[i].slot; 85 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID); 86 87 vendor = id & 0xffff; 88 device = (id>>16) & 0xffff; 89 if (pci_probes[i].vendor == vendor && 90 pci_probes[i].device == device) { 91 found = true; 92 break; 93 } 94 } 95 96 if (!found) 97 return 0; 98 99 for (i = 0; i < 4; i++) { 100 int min_bus; 101 int max_bus; 102 reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2)); 103 104 /* Check if that register is enabled for bus range */ 105 if ((reg & 7) != 3) 106 continue; 107 108 min_bus = (reg >> 16) & 0xff; 109 max_bus = (reg >> 24) & 0xff; 110 node = (reg >> 4) & 0x07; 111 link = (reg >> 8) & 0x03; 112 113 info = alloc_pci_root_info(min_bus, max_bus, node, link); 114 } 115 116 /* get the default node and link for left over res */ 117 reg = read_pci_config(bus, slot, 0, 0x60); 118 def_node = (reg >> 8) & 0x07; 119 reg = read_pci_config(bus, slot, 0, 0x64); 120 def_link = (reg >> 8) & 0x03; 121 122 memset(range, 0, sizeof(range)); 123 add_range(range, RANGE_NUM, 0, 0, 0xffff + 1); 124 /* io port resource */ 125 for (i = 0; i < 4; i++) { 126 reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3)); 127 if (!(reg & 3)) 128 continue; 129 130 start = reg & 0xfff000; 131 reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3)); 132 node = reg & 0x07; 133 link = (reg >> 4) & 0x03; 134 end = (reg & 0xfff000) | 0xfff; 135 136 info = find_pci_root_info(node, link); 137 if (!info) 138 continue; /* not found */ 139 140 printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n", 141 node, link, start, end); 142 143 /* kernel only handle 16 bit only */ 144 if (end > 0xffff) 145 end = 0xffff; 146 update_res(info, start, end, IORESOURCE_IO, 1); 147 subtract_range(range, RANGE_NUM, start, end + 1); 148 } 149 /* add left over io port range to def node/link, [0, 0xffff] */ 150 /* find the position */ 151 info = find_pci_root_info(def_node, def_link); 152 if (info) { 153 for (i = 0; i < RANGE_NUM; i++) { 154 if (!range[i].end) 155 continue; 156 157 update_res(info, range[i].start, range[i].end - 1, 158 IORESOURCE_IO, 1); 159 } 160 } 161 162 memset(range, 0, sizeof(range)); 163 /* 0xfd00000000-0xffffffffff for HT */ 164 end = cap_resource((0xfdULL<<32) - 1); 165 end++; 166 add_range(range, RANGE_NUM, 0, 0, end); 167 168 /* need to take out [0, TOM) for RAM*/ 169 address = MSR_K8_TOP_MEM1; 170 rdmsrl(address, val); 171 end = (val & 0xffffff800000ULL); 172 printk(KERN_INFO "TOM: %016llx aka %lldM\n", end, end>>20); 173 if (end < (1ULL<<32)) 174 subtract_range(range, RANGE_NUM, 0, end); 175 176 /* get mmconfig */ 177 fam10h_mmconf = amd_get_mmconfig_range(&fam10h_mmconf_res); 178 /* need to take out mmconf range */ 179 if (fam10h_mmconf) { 180 printk(KERN_DEBUG "Fam 10h mmconf %pR\n", fam10h_mmconf); 181 fam10h_mmconf_start = fam10h_mmconf->start; 182 fam10h_mmconf_end = fam10h_mmconf->end; 183 subtract_range(range, RANGE_NUM, fam10h_mmconf_start, 184 fam10h_mmconf_end + 1); 185 } else { 186 fam10h_mmconf_start = 0; 187 fam10h_mmconf_end = 0; 188 } 189 190 /* mmio resource */ 191 for (i = 0; i < 8; i++) { 192 reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3)); 193 if (!(reg & 3)) 194 continue; 195 196 start = reg & 0xffffff00; /* 39:16 on 31:8*/ 197 start <<= 8; 198 reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3)); 199 node = reg & 0x07; 200 link = (reg >> 4) & 0x03; 201 end = (reg & 0xffffff00); 202 end <<= 8; 203 end |= 0xffff; 204 205 info = find_pci_root_info(node, link); 206 207 if (!info) 208 continue; 209 210 printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]", 211 node, link, start, end); 212 /* 213 * some sick allocation would have range overlap with fam10h 214 * mmconf range, so need to update start and end. 215 */ 216 if (fam10h_mmconf_end) { 217 int changed = 0; 218 u64 endx = 0; 219 if (start >= fam10h_mmconf_start && 220 start <= fam10h_mmconf_end) { 221 start = fam10h_mmconf_end + 1; 222 changed = 1; 223 } 224 225 if (end >= fam10h_mmconf_start && 226 end <= fam10h_mmconf_end) { 227 end = fam10h_mmconf_start - 1; 228 changed = 1; 229 } 230 231 if (start < fam10h_mmconf_start && 232 end > fam10h_mmconf_end) { 233 /* we got a hole */ 234 endx = fam10h_mmconf_start - 1; 235 update_res(info, start, endx, IORESOURCE_MEM, 0); 236 subtract_range(range, RANGE_NUM, start, 237 endx + 1); 238 printk(KERN_CONT " ==> [%llx, %llx]", start, endx); 239 start = fam10h_mmconf_end + 1; 240 changed = 1; 241 } 242 if (changed) { 243 if (start <= end) { 244 printk(KERN_CONT " %s [%llx, %llx]", endx ? "and" : "==>", start, end); 245 } else { 246 printk(KERN_CONT "%s\n", endx?"":" ==> none"); 247 continue; 248 } 249 } 250 } 251 252 update_res(info, cap_resource(start), cap_resource(end), 253 IORESOURCE_MEM, 1); 254 subtract_range(range, RANGE_NUM, start, end + 1); 255 printk(KERN_CONT "\n"); 256 } 257 258 /* need to take out [4G, TOM2) for RAM*/ 259 /* SYS_CFG */ 260 address = MSR_K8_SYSCFG; 261 rdmsrl(address, val); 262 /* TOP_MEM2 is enabled? */ 263 if (val & (1<<21)) { 264 /* TOP_MEM2 */ 265 address = MSR_K8_TOP_MEM2; 266 rdmsrl(address, val); 267 end = (val & 0xffffff800000ULL); 268 printk(KERN_INFO "TOM2: %016llx aka %lldM\n", end, end>>20); 269 subtract_range(range, RANGE_NUM, 1ULL<<32, end); 270 } 271 272 /* 273 * add left over mmio range to def node/link ? 274 * that is tricky, just record range in from start_min to 4G 275 */ 276 info = find_pci_root_info(def_node, def_link); 277 if (info) { 278 for (i = 0; i < RANGE_NUM; i++) { 279 if (!range[i].end) 280 continue; 281 282 update_res(info, cap_resource(range[i].start), 283 cap_resource(range[i].end - 1), 284 IORESOURCE_MEM, 1); 285 } 286 } 287 288 list_for_each_entry(info, &pci_root_infos, list) { 289 int busnum; 290 struct pci_root_res *root_res; 291 292 busnum = info->busn.start; 293 printk(KERN_DEBUG "bus: %pR on node %x link %x\n", 294 &info->busn, info->node, info->link); 295 list_for_each_entry(root_res, &info->resources, list) 296 printk(KERN_DEBUG "bus: %02x %pR\n", 297 busnum, &root_res->res); 298 } 299 300 return 0; 301 } 302 303 #define ENABLE_CF8_EXT_CFG (1ULL << 46) 304 305 static void enable_pci_io_ecs(void *unused) 306 { 307 u64 reg; 308 rdmsrl(MSR_AMD64_NB_CFG, reg); 309 if (!(reg & ENABLE_CF8_EXT_CFG)) { 310 reg |= ENABLE_CF8_EXT_CFG; 311 wrmsrl(MSR_AMD64_NB_CFG, reg); 312 } 313 } 314 315 static int amd_cpu_notify(struct notifier_block *self, unsigned long action, 316 void *hcpu) 317 { 318 int cpu = (long)hcpu; 319 switch (action) { 320 case CPU_ONLINE: 321 case CPU_ONLINE_FROZEN: 322 smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0); 323 break; 324 default: 325 break; 326 } 327 return NOTIFY_OK; 328 } 329 330 static struct notifier_block amd_cpu_notifier = { 331 .notifier_call = amd_cpu_notify, 332 }; 333 334 static void __init pci_enable_pci_io_ecs(void) 335 { 336 #ifdef CONFIG_AMD_NB 337 unsigned int i, n; 338 339 for (n = i = 0; !n && amd_nb_bus_dev_ranges[i].dev_limit; ++i) { 340 u8 bus = amd_nb_bus_dev_ranges[i].bus; 341 u8 slot = amd_nb_bus_dev_ranges[i].dev_base; 342 u8 limit = amd_nb_bus_dev_ranges[i].dev_limit; 343 344 for (; slot < limit; ++slot) { 345 u32 val = read_pci_config(bus, slot, 3, 0); 346 347 if (!early_is_amd_nb(val)) 348 continue; 349 350 val = read_pci_config(bus, slot, 3, 0x8c); 351 if (!(val & (ENABLE_CF8_EXT_CFG >> 32))) { 352 val |= ENABLE_CF8_EXT_CFG >> 32; 353 write_pci_config(bus, slot, 3, 0x8c, val); 354 } 355 ++n; 356 } 357 } 358 #endif 359 } 360 361 static int __init pci_io_ecs_init(void) 362 { 363 int cpu; 364 365 /* assume all cpus from fam10h have IO ECS */ 366 if (boot_cpu_data.x86 < 0x10) 367 return 0; 368 369 /* Try the PCI method first. */ 370 if (early_pci_allowed()) 371 pci_enable_pci_io_ecs(); 372 373 cpu_notifier_register_begin(); 374 for_each_online_cpu(cpu) 375 amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE, 376 (void *)(long)cpu); 377 __register_cpu_notifier(&amd_cpu_notifier); 378 cpu_notifier_register_done(); 379 380 pci_probe |= PCI_HAS_IO_ECS; 381 382 return 0; 383 } 384 385 static int __init amd_postcore_init(void) 386 { 387 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) 388 return 0; 389 390 early_fill_mp_bus_info(); 391 pci_io_ecs_init(); 392 393 return 0; 394 } 395 396 postcore_initcall(amd_postcore_init); 397