1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * BPF JIT compiler 4 * 5 * Copyright (C) 2011-2013 Eric Dumazet (eric.dumazet@gmail.com) 6 * Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com 7 */ 8 #include <linux/netdevice.h> 9 #include <linux/filter.h> 10 #include <linux/if_vlan.h> 11 #include <linux/bpf.h> 12 #include <linux/memory.h> 13 #include <linux/sort.h> 14 #include <asm/extable.h> 15 #include <asm/ftrace.h> 16 #include <asm/set_memory.h> 17 #include <asm/nospec-branch.h> 18 #include <asm/text-patching.h> 19 20 static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len) 21 { 22 if (len == 1) 23 *ptr = bytes; 24 else if (len == 2) 25 *(u16 *)ptr = bytes; 26 else { 27 *(u32 *)ptr = bytes; 28 barrier(); 29 } 30 return ptr + len; 31 } 32 33 #define EMIT(bytes, len) \ 34 do { prog = emit_code(prog, bytes, len); } while (0) 35 36 #define EMIT1(b1) EMIT(b1, 1) 37 #define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2) 38 #define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3) 39 #define EMIT4(b1, b2, b3, b4) EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4) 40 41 #define EMIT1_off32(b1, off) \ 42 do { EMIT1(b1); EMIT(off, 4); } while (0) 43 #define EMIT2_off32(b1, b2, off) \ 44 do { EMIT2(b1, b2); EMIT(off, 4); } while (0) 45 #define EMIT3_off32(b1, b2, b3, off) \ 46 do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0) 47 #define EMIT4_off32(b1, b2, b3, b4, off) \ 48 do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0) 49 50 #ifdef CONFIG_X86_KERNEL_IBT 51 #define EMIT_ENDBR() EMIT(gen_endbr(), 4) 52 #else 53 #define EMIT_ENDBR() 54 #endif 55 56 static bool is_imm8(int value) 57 { 58 return value <= 127 && value >= -128; 59 } 60 61 static bool is_simm32(s64 value) 62 { 63 return value == (s64)(s32)value; 64 } 65 66 static bool is_uimm32(u64 value) 67 { 68 return value == (u64)(u32)value; 69 } 70 71 /* mov dst, src */ 72 #define EMIT_mov(DST, SRC) \ 73 do { \ 74 if (DST != SRC) \ 75 EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \ 76 } while (0) 77 78 static int bpf_size_to_x86_bytes(int bpf_size) 79 { 80 if (bpf_size == BPF_W) 81 return 4; 82 else if (bpf_size == BPF_H) 83 return 2; 84 else if (bpf_size == BPF_B) 85 return 1; 86 else if (bpf_size == BPF_DW) 87 return 4; /* imm32 */ 88 else 89 return 0; 90 } 91 92 /* 93 * List of x86 cond jumps opcodes (. + s8) 94 * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32) 95 */ 96 #define X86_JB 0x72 97 #define X86_JAE 0x73 98 #define X86_JE 0x74 99 #define X86_JNE 0x75 100 #define X86_JBE 0x76 101 #define X86_JA 0x77 102 #define X86_JL 0x7C 103 #define X86_JGE 0x7D 104 #define X86_JLE 0x7E 105 #define X86_JG 0x7F 106 107 /* Pick a register outside of BPF range for JIT internal work */ 108 #define AUX_REG (MAX_BPF_JIT_REG + 1) 109 #define X86_REG_R9 (MAX_BPF_JIT_REG + 2) 110 111 /* 112 * The following table maps BPF registers to x86-64 registers. 113 * 114 * x86-64 register R12 is unused, since if used as base address 115 * register in load/store instructions, it always needs an 116 * extra byte of encoding and is callee saved. 117 * 118 * x86-64 register R9 is not used by BPF programs, but can be used by BPF 119 * trampoline. x86-64 register R10 is used for blinding (if enabled). 120 */ 121 static const int reg2hex[] = { 122 [BPF_REG_0] = 0, /* RAX */ 123 [BPF_REG_1] = 7, /* RDI */ 124 [BPF_REG_2] = 6, /* RSI */ 125 [BPF_REG_3] = 2, /* RDX */ 126 [BPF_REG_4] = 1, /* RCX */ 127 [BPF_REG_5] = 0, /* R8 */ 128 [BPF_REG_6] = 3, /* RBX callee saved */ 129 [BPF_REG_7] = 5, /* R13 callee saved */ 130 [BPF_REG_8] = 6, /* R14 callee saved */ 131 [BPF_REG_9] = 7, /* R15 callee saved */ 132 [BPF_REG_FP] = 5, /* RBP readonly */ 133 [BPF_REG_AX] = 2, /* R10 temp register */ 134 [AUX_REG] = 3, /* R11 temp register */ 135 [X86_REG_R9] = 1, /* R9 register, 6th function argument */ 136 }; 137 138 static const int reg2pt_regs[] = { 139 [BPF_REG_0] = offsetof(struct pt_regs, ax), 140 [BPF_REG_1] = offsetof(struct pt_regs, di), 141 [BPF_REG_2] = offsetof(struct pt_regs, si), 142 [BPF_REG_3] = offsetof(struct pt_regs, dx), 143 [BPF_REG_4] = offsetof(struct pt_regs, cx), 144 [BPF_REG_5] = offsetof(struct pt_regs, r8), 145 [BPF_REG_6] = offsetof(struct pt_regs, bx), 146 [BPF_REG_7] = offsetof(struct pt_regs, r13), 147 [BPF_REG_8] = offsetof(struct pt_regs, r14), 148 [BPF_REG_9] = offsetof(struct pt_regs, r15), 149 }; 150 151 /* 152 * is_ereg() == true if BPF register 'reg' maps to x86-64 r8..r15 153 * which need extra byte of encoding. 154 * rax,rcx,...,rbp have simpler encoding 155 */ 156 static bool is_ereg(u32 reg) 157 { 158 return (1 << reg) & (BIT(BPF_REG_5) | 159 BIT(AUX_REG) | 160 BIT(BPF_REG_7) | 161 BIT(BPF_REG_8) | 162 BIT(BPF_REG_9) | 163 BIT(X86_REG_R9) | 164 BIT(BPF_REG_AX)); 165 } 166 167 /* 168 * is_ereg_8l() == true if BPF register 'reg' is mapped to access x86-64 169 * lower 8-bit registers dil,sil,bpl,spl,r8b..r15b, which need extra byte 170 * of encoding. al,cl,dl,bl have simpler encoding. 171 */ 172 static bool is_ereg_8l(u32 reg) 173 { 174 return is_ereg(reg) || 175 (1 << reg) & (BIT(BPF_REG_1) | 176 BIT(BPF_REG_2) | 177 BIT(BPF_REG_FP)); 178 } 179 180 static bool is_axreg(u32 reg) 181 { 182 return reg == BPF_REG_0; 183 } 184 185 /* Add modifiers if 'reg' maps to x86-64 registers R8..R15 */ 186 static u8 add_1mod(u8 byte, u32 reg) 187 { 188 if (is_ereg(reg)) 189 byte |= 1; 190 return byte; 191 } 192 193 static u8 add_2mod(u8 byte, u32 r1, u32 r2) 194 { 195 if (is_ereg(r1)) 196 byte |= 1; 197 if (is_ereg(r2)) 198 byte |= 4; 199 return byte; 200 } 201 202 /* Encode 'dst_reg' register into x86-64 opcode 'byte' */ 203 static u8 add_1reg(u8 byte, u32 dst_reg) 204 { 205 return byte + reg2hex[dst_reg]; 206 } 207 208 /* Encode 'dst_reg' and 'src_reg' registers into x86-64 opcode 'byte' */ 209 static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg) 210 { 211 return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3); 212 } 213 214 /* Some 1-byte opcodes for binary ALU operations */ 215 static u8 simple_alu_opcodes[] = { 216 [BPF_ADD] = 0x01, 217 [BPF_SUB] = 0x29, 218 [BPF_AND] = 0x21, 219 [BPF_OR] = 0x09, 220 [BPF_XOR] = 0x31, 221 [BPF_LSH] = 0xE0, 222 [BPF_RSH] = 0xE8, 223 [BPF_ARSH] = 0xF8, 224 }; 225 226 static void jit_fill_hole(void *area, unsigned int size) 227 { 228 /* Fill whole space with INT3 instructions */ 229 memset(area, 0xcc, size); 230 } 231 232 int bpf_arch_text_invalidate(void *dst, size_t len) 233 { 234 return IS_ERR_OR_NULL(text_poke_set(dst, 0xcc, len)); 235 } 236 237 struct jit_context { 238 int cleanup_addr; /* Epilogue code offset */ 239 240 /* 241 * Program specific offsets of labels in the code; these rely on the 242 * JIT doing at least 2 passes, recording the position on the first 243 * pass, only to generate the correct offset on the second pass. 244 */ 245 int tail_call_direct_label; 246 int tail_call_indirect_label; 247 }; 248 249 /* Maximum number of bytes emitted while JITing one eBPF insn */ 250 #define BPF_MAX_INSN_SIZE 128 251 #define BPF_INSN_SAFETY 64 252 253 /* Number of bytes emit_patch() needs to generate instructions */ 254 #define X86_PATCH_SIZE 5 255 /* Number of bytes that will be skipped on tailcall */ 256 #define X86_TAIL_CALL_OFFSET (11 + ENDBR_INSN_SIZE) 257 258 static void push_callee_regs(u8 **pprog, bool *callee_regs_used) 259 { 260 u8 *prog = *pprog; 261 262 if (callee_regs_used[0]) 263 EMIT1(0x53); /* push rbx */ 264 if (callee_regs_used[1]) 265 EMIT2(0x41, 0x55); /* push r13 */ 266 if (callee_regs_used[2]) 267 EMIT2(0x41, 0x56); /* push r14 */ 268 if (callee_regs_used[3]) 269 EMIT2(0x41, 0x57); /* push r15 */ 270 *pprog = prog; 271 } 272 273 static void pop_callee_regs(u8 **pprog, bool *callee_regs_used) 274 { 275 u8 *prog = *pprog; 276 277 if (callee_regs_used[3]) 278 EMIT2(0x41, 0x5F); /* pop r15 */ 279 if (callee_regs_used[2]) 280 EMIT2(0x41, 0x5E); /* pop r14 */ 281 if (callee_regs_used[1]) 282 EMIT2(0x41, 0x5D); /* pop r13 */ 283 if (callee_regs_used[0]) 284 EMIT1(0x5B); /* pop rbx */ 285 *pprog = prog; 286 } 287 288 /* 289 * Emit x86-64 prologue code for BPF program. 290 * bpf_tail_call helper will skip the first X86_TAIL_CALL_OFFSET bytes 291 * while jumping to another program 292 */ 293 static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf, 294 bool tail_call_reachable, bool is_subprog) 295 { 296 u8 *prog = *pprog; 297 298 /* BPF trampoline can be made to work without these nops, 299 * but let's waste 5 bytes for now and optimize later 300 */ 301 EMIT_ENDBR(); 302 memcpy(prog, x86_nops[5], X86_PATCH_SIZE); 303 prog += X86_PATCH_SIZE; 304 if (!ebpf_from_cbpf) { 305 if (tail_call_reachable && !is_subprog) 306 EMIT2(0x31, 0xC0); /* xor eax, eax */ 307 else 308 EMIT2(0x66, 0x90); /* nop2 */ 309 } 310 EMIT1(0x55); /* push rbp */ 311 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */ 312 313 /* X86_TAIL_CALL_OFFSET is here */ 314 EMIT_ENDBR(); 315 316 /* sub rsp, rounded_stack_depth */ 317 if (stack_depth) 318 EMIT3_off32(0x48, 0x81, 0xEC, round_up(stack_depth, 8)); 319 if (tail_call_reachable) 320 EMIT1(0x50); /* push rax */ 321 *pprog = prog; 322 } 323 324 static int emit_patch(u8 **pprog, void *func, void *ip, u8 opcode) 325 { 326 u8 *prog = *pprog; 327 s64 offset; 328 329 offset = func - (ip + X86_PATCH_SIZE); 330 if (!is_simm32(offset)) { 331 pr_err("Target call %p is out of range\n", func); 332 return -ERANGE; 333 } 334 EMIT1_off32(opcode, offset); 335 *pprog = prog; 336 return 0; 337 } 338 339 static int emit_call(u8 **pprog, void *func, void *ip) 340 { 341 return emit_patch(pprog, func, ip, 0xE8); 342 } 343 344 static int emit_rsb_call(u8 **pprog, void *func, void *ip) 345 { 346 OPTIMIZER_HIDE_VAR(func); 347 x86_call_depth_emit_accounting(pprog, func); 348 return emit_patch(pprog, func, ip, 0xE8); 349 } 350 351 static int emit_jump(u8 **pprog, void *func, void *ip) 352 { 353 return emit_patch(pprog, func, ip, 0xE9); 354 } 355 356 static int __bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t, 357 void *old_addr, void *new_addr) 358 { 359 const u8 *nop_insn = x86_nops[5]; 360 u8 old_insn[X86_PATCH_SIZE]; 361 u8 new_insn[X86_PATCH_SIZE]; 362 u8 *prog; 363 int ret; 364 365 memcpy(old_insn, nop_insn, X86_PATCH_SIZE); 366 if (old_addr) { 367 prog = old_insn; 368 ret = t == BPF_MOD_CALL ? 369 emit_call(&prog, old_addr, ip) : 370 emit_jump(&prog, old_addr, ip); 371 if (ret) 372 return ret; 373 } 374 375 memcpy(new_insn, nop_insn, X86_PATCH_SIZE); 376 if (new_addr) { 377 prog = new_insn; 378 ret = t == BPF_MOD_CALL ? 379 emit_call(&prog, new_addr, ip) : 380 emit_jump(&prog, new_addr, ip); 381 if (ret) 382 return ret; 383 } 384 385 ret = -EBUSY; 386 mutex_lock(&text_mutex); 387 if (memcmp(ip, old_insn, X86_PATCH_SIZE)) 388 goto out; 389 ret = 1; 390 if (memcmp(ip, new_insn, X86_PATCH_SIZE)) { 391 text_poke_bp(ip, new_insn, X86_PATCH_SIZE, NULL); 392 ret = 0; 393 } 394 out: 395 mutex_unlock(&text_mutex); 396 return ret; 397 } 398 399 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t, 400 void *old_addr, void *new_addr) 401 { 402 if (!is_kernel_text((long)ip) && 403 !is_bpf_text_address((long)ip)) 404 /* BPF poking in modules is not supported */ 405 return -EINVAL; 406 407 /* 408 * See emit_prologue(), for IBT builds the trampoline hook is preceded 409 * with an ENDBR instruction. 410 */ 411 if (is_endbr(*(u32 *)ip)) 412 ip += ENDBR_INSN_SIZE; 413 414 return __bpf_arch_text_poke(ip, t, old_addr, new_addr); 415 } 416 417 #define EMIT_LFENCE() EMIT3(0x0F, 0xAE, 0xE8) 418 419 static void emit_indirect_jump(u8 **pprog, int reg, u8 *ip) 420 { 421 u8 *prog = *pprog; 422 423 if (cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) { 424 EMIT_LFENCE(); 425 EMIT2(0xFF, 0xE0 + reg); 426 } else if (cpu_feature_enabled(X86_FEATURE_RETPOLINE)) { 427 OPTIMIZER_HIDE_VAR(reg); 428 if (cpu_feature_enabled(X86_FEATURE_CALL_DEPTH)) 429 emit_jump(&prog, &__x86_indirect_jump_thunk_array[reg], ip); 430 else 431 emit_jump(&prog, &__x86_indirect_thunk_array[reg], ip); 432 } else { 433 EMIT2(0xFF, 0xE0 + reg); /* jmp *%\reg */ 434 if (IS_ENABLED(CONFIG_RETPOLINE) || IS_ENABLED(CONFIG_SLS)) 435 EMIT1(0xCC); /* int3 */ 436 } 437 438 *pprog = prog; 439 } 440 441 static void emit_return(u8 **pprog, u8 *ip) 442 { 443 u8 *prog = *pprog; 444 445 if (cpu_feature_enabled(X86_FEATURE_RETHUNK)) { 446 emit_jump(&prog, x86_return_thunk, ip); 447 } else { 448 EMIT1(0xC3); /* ret */ 449 if (IS_ENABLED(CONFIG_SLS)) 450 EMIT1(0xCC); /* int3 */ 451 } 452 453 *pprog = prog; 454 } 455 456 /* 457 * Generate the following code: 458 * 459 * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ... 460 * if (index >= array->map.max_entries) 461 * goto out; 462 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT) 463 * goto out; 464 * prog = array->ptrs[index]; 465 * if (prog == NULL) 466 * goto out; 467 * goto *(prog->bpf_func + prologue_size); 468 * out: 469 */ 470 static void emit_bpf_tail_call_indirect(u8 **pprog, bool *callee_regs_used, 471 u32 stack_depth, u8 *ip, 472 struct jit_context *ctx) 473 { 474 int tcc_off = -4 - round_up(stack_depth, 8); 475 u8 *prog = *pprog, *start = *pprog; 476 int offset; 477 478 /* 479 * rdi - pointer to ctx 480 * rsi - pointer to bpf_array 481 * rdx - index in bpf_array 482 */ 483 484 /* 485 * if (index >= array->map.max_entries) 486 * goto out; 487 */ 488 EMIT2(0x89, 0xD2); /* mov edx, edx */ 489 EMIT3(0x39, 0x56, /* cmp dword ptr [rsi + 16], edx */ 490 offsetof(struct bpf_array, map.max_entries)); 491 492 offset = ctx->tail_call_indirect_label - (prog + 2 - start); 493 EMIT2(X86_JBE, offset); /* jbe out */ 494 495 /* 496 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT) 497 * goto out; 498 */ 499 EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */ 500 EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */ 501 502 offset = ctx->tail_call_indirect_label - (prog + 2 - start); 503 EMIT2(X86_JAE, offset); /* jae out */ 504 EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */ 505 EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */ 506 507 /* prog = array->ptrs[index]; */ 508 EMIT4_off32(0x48, 0x8B, 0x8C, 0xD6, /* mov rcx, [rsi + rdx * 8 + offsetof(...)] */ 509 offsetof(struct bpf_array, ptrs)); 510 511 /* 512 * if (prog == NULL) 513 * goto out; 514 */ 515 EMIT3(0x48, 0x85, 0xC9); /* test rcx,rcx */ 516 517 offset = ctx->tail_call_indirect_label - (prog + 2 - start); 518 EMIT2(X86_JE, offset); /* je out */ 519 520 pop_callee_regs(&prog, callee_regs_used); 521 522 EMIT1(0x58); /* pop rax */ 523 if (stack_depth) 524 EMIT3_off32(0x48, 0x81, 0xC4, /* add rsp, sd */ 525 round_up(stack_depth, 8)); 526 527 /* goto *(prog->bpf_func + X86_TAIL_CALL_OFFSET); */ 528 EMIT4(0x48, 0x8B, 0x49, /* mov rcx, qword ptr [rcx + 32] */ 529 offsetof(struct bpf_prog, bpf_func)); 530 EMIT4(0x48, 0x83, 0xC1, /* add rcx, X86_TAIL_CALL_OFFSET */ 531 X86_TAIL_CALL_OFFSET); 532 /* 533 * Now we're ready to jump into next BPF program 534 * rdi == ctx (1st arg) 535 * rcx == prog->bpf_func + X86_TAIL_CALL_OFFSET 536 */ 537 emit_indirect_jump(&prog, 1 /* rcx */, ip + (prog - start)); 538 539 /* out: */ 540 ctx->tail_call_indirect_label = prog - start; 541 *pprog = prog; 542 } 543 544 static void emit_bpf_tail_call_direct(struct bpf_jit_poke_descriptor *poke, 545 u8 **pprog, u8 *ip, 546 bool *callee_regs_used, u32 stack_depth, 547 struct jit_context *ctx) 548 { 549 int tcc_off = -4 - round_up(stack_depth, 8); 550 u8 *prog = *pprog, *start = *pprog; 551 int offset; 552 553 /* 554 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT) 555 * goto out; 556 */ 557 EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */ 558 EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */ 559 560 offset = ctx->tail_call_direct_label - (prog + 2 - start); 561 EMIT2(X86_JAE, offset); /* jae out */ 562 EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */ 563 EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */ 564 565 poke->tailcall_bypass = ip + (prog - start); 566 poke->adj_off = X86_TAIL_CALL_OFFSET; 567 poke->tailcall_target = ip + ctx->tail_call_direct_label - X86_PATCH_SIZE; 568 poke->bypass_addr = (u8 *)poke->tailcall_target + X86_PATCH_SIZE; 569 570 emit_jump(&prog, (u8 *)poke->tailcall_target + X86_PATCH_SIZE, 571 poke->tailcall_bypass); 572 573 pop_callee_regs(&prog, callee_regs_used); 574 EMIT1(0x58); /* pop rax */ 575 if (stack_depth) 576 EMIT3_off32(0x48, 0x81, 0xC4, round_up(stack_depth, 8)); 577 578 memcpy(prog, x86_nops[5], X86_PATCH_SIZE); 579 prog += X86_PATCH_SIZE; 580 581 /* out: */ 582 ctx->tail_call_direct_label = prog - start; 583 584 *pprog = prog; 585 } 586 587 static void bpf_tail_call_direct_fixup(struct bpf_prog *prog) 588 { 589 struct bpf_jit_poke_descriptor *poke; 590 struct bpf_array *array; 591 struct bpf_prog *target; 592 int i, ret; 593 594 for (i = 0; i < prog->aux->size_poke_tab; i++) { 595 poke = &prog->aux->poke_tab[i]; 596 if (poke->aux && poke->aux != prog->aux) 597 continue; 598 599 WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable)); 600 601 if (poke->reason != BPF_POKE_REASON_TAIL_CALL) 602 continue; 603 604 array = container_of(poke->tail_call.map, struct bpf_array, map); 605 mutex_lock(&array->aux->poke_mutex); 606 target = array->ptrs[poke->tail_call.key]; 607 if (target) { 608 ret = __bpf_arch_text_poke(poke->tailcall_target, 609 BPF_MOD_JUMP, NULL, 610 (u8 *)target->bpf_func + 611 poke->adj_off); 612 BUG_ON(ret < 0); 613 ret = __bpf_arch_text_poke(poke->tailcall_bypass, 614 BPF_MOD_JUMP, 615 (u8 *)poke->tailcall_target + 616 X86_PATCH_SIZE, NULL); 617 BUG_ON(ret < 0); 618 } 619 WRITE_ONCE(poke->tailcall_target_stable, true); 620 mutex_unlock(&array->aux->poke_mutex); 621 } 622 } 623 624 static void emit_mov_imm32(u8 **pprog, bool sign_propagate, 625 u32 dst_reg, const u32 imm32) 626 { 627 u8 *prog = *pprog; 628 u8 b1, b2, b3; 629 630 /* 631 * Optimization: if imm32 is positive, use 'mov %eax, imm32' 632 * (which zero-extends imm32) to save 2 bytes. 633 */ 634 if (sign_propagate && (s32)imm32 < 0) { 635 /* 'mov %rax, imm32' sign extends imm32 */ 636 b1 = add_1mod(0x48, dst_reg); 637 b2 = 0xC7; 638 b3 = 0xC0; 639 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32); 640 goto done; 641 } 642 643 /* 644 * Optimization: if imm32 is zero, use 'xor %eax, %eax' 645 * to save 3 bytes. 646 */ 647 if (imm32 == 0) { 648 if (is_ereg(dst_reg)) 649 EMIT1(add_2mod(0x40, dst_reg, dst_reg)); 650 b2 = 0x31; /* xor */ 651 b3 = 0xC0; 652 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg)); 653 goto done; 654 } 655 656 /* mov %eax, imm32 */ 657 if (is_ereg(dst_reg)) 658 EMIT1(add_1mod(0x40, dst_reg)); 659 EMIT1_off32(add_1reg(0xB8, dst_reg), imm32); 660 done: 661 *pprog = prog; 662 } 663 664 static void emit_mov_imm64(u8 **pprog, u32 dst_reg, 665 const u32 imm32_hi, const u32 imm32_lo) 666 { 667 u8 *prog = *pprog; 668 669 if (is_uimm32(((u64)imm32_hi << 32) | (u32)imm32_lo)) { 670 /* 671 * For emitting plain u32, where sign bit must not be 672 * propagated LLVM tends to load imm64 over mov32 673 * directly, so save couple of bytes by just doing 674 * 'mov %eax, imm32' instead. 675 */ 676 emit_mov_imm32(&prog, false, dst_reg, imm32_lo); 677 } else { 678 /* movabsq rax, imm64 */ 679 EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg)); 680 EMIT(imm32_lo, 4); 681 EMIT(imm32_hi, 4); 682 } 683 684 *pprog = prog; 685 } 686 687 static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg) 688 { 689 u8 *prog = *pprog; 690 691 if (is64) { 692 /* mov dst, src */ 693 EMIT_mov(dst_reg, src_reg); 694 } else { 695 /* mov32 dst, src */ 696 if (is_ereg(dst_reg) || is_ereg(src_reg)) 697 EMIT1(add_2mod(0x40, dst_reg, src_reg)); 698 EMIT2(0x89, add_2reg(0xC0, dst_reg, src_reg)); 699 } 700 701 *pprog = prog; 702 } 703 704 /* Emit the suffix (ModR/M etc) for addressing *(ptr_reg + off) and val_reg */ 705 static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off) 706 { 707 u8 *prog = *pprog; 708 709 if (is_imm8(off)) { 710 /* 1-byte signed displacement. 711 * 712 * If off == 0 we could skip this and save one extra byte, but 713 * special case of x86 R13 which always needs an offset is not 714 * worth the hassle 715 */ 716 EMIT2(add_2reg(0x40, ptr_reg, val_reg), off); 717 } else { 718 /* 4-byte signed displacement */ 719 EMIT1_off32(add_2reg(0x80, ptr_reg, val_reg), off); 720 } 721 *pprog = prog; 722 } 723 724 /* 725 * Emit a REX byte if it will be necessary to address these registers 726 */ 727 static void maybe_emit_mod(u8 **pprog, u32 dst_reg, u32 src_reg, bool is64) 728 { 729 u8 *prog = *pprog; 730 731 if (is64) 732 EMIT1(add_2mod(0x48, dst_reg, src_reg)); 733 else if (is_ereg(dst_reg) || is_ereg(src_reg)) 734 EMIT1(add_2mod(0x40, dst_reg, src_reg)); 735 *pprog = prog; 736 } 737 738 /* 739 * Similar version of maybe_emit_mod() for a single register 740 */ 741 static void maybe_emit_1mod(u8 **pprog, u32 reg, bool is64) 742 { 743 u8 *prog = *pprog; 744 745 if (is64) 746 EMIT1(add_1mod(0x48, reg)); 747 else if (is_ereg(reg)) 748 EMIT1(add_1mod(0x40, reg)); 749 *pprog = prog; 750 } 751 752 /* LDX: dst_reg = *(u8*)(src_reg + off) */ 753 static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 754 { 755 u8 *prog = *pprog; 756 757 switch (size) { 758 case BPF_B: 759 /* Emit 'movzx rax, byte ptr [rax + off]' */ 760 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6); 761 break; 762 case BPF_H: 763 /* Emit 'movzx rax, word ptr [rax + off]' */ 764 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7); 765 break; 766 case BPF_W: 767 /* Emit 'mov eax, dword ptr [rax+0x14]' */ 768 if (is_ereg(dst_reg) || is_ereg(src_reg)) 769 EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B); 770 else 771 EMIT1(0x8B); 772 break; 773 case BPF_DW: 774 /* Emit 'mov rax, qword ptr [rax+0x14]' */ 775 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B); 776 break; 777 } 778 emit_insn_suffix(&prog, src_reg, dst_reg, off); 779 *pprog = prog; 780 } 781 782 /* STX: *(u8*)(dst_reg + off) = src_reg */ 783 static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 784 { 785 u8 *prog = *pprog; 786 787 switch (size) { 788 case BPF_B: 789 /* Emit 'mov byte ptr [rax + off], al' */ 790 if (is_ereg(dst_reg) || is_ereg_8l(src_reg)) 791 /* Add extra byte for eregs or SIL,DIL,BPL in src_reg */ 792 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88); 793 else 794 EMIT1(0x88); 795 break; 796 case BPF_H: 797 if (is_ereg(dst_reg) || is_ereg(src_reg)) 798 EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89); 799 else 800 EMIT2(0x66, 0x89); 801 break; 802 case BPF_W: 803 if (is_ereg(dst_reg) || is_ereg(src_reg)) 804 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89); 805 else 806 EMIT1(0x89); 807 break; 808 case BPF_DW: 809 EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89); 810 break; 811 } 812 emit_insn_suffix(&prog, dst_reg, src_reg, off); 813 *pprog = prog; 814 } 815 816 static int emit_atomic(u8 **pprog, u8 atomic_op, 817 u32 dst_reg, u32 src_reg, s16 off, u8 bpf_size) 818 { 819 u8 *prog = *pprog; 820 821 EMIT1(0xF0); /* lock prefix */ 822 823 maybe_emit_mod(&prog, dst_reg, src_reg, bpf_size == BPF_DW); 824 825 /* emit opcode */ 826 switch (atomic_op) { 827 case BPF_ADD: 828 case BPF_AND: 829 case BPF_OR: 830 case BPF_XOR: 831 /* lock *(u32/u64*)(dst_reg + off) <op>= src_reg */ 832 EMIT1(simple_alu_opcodes[atomic_op]); 833 break; 834 case BPF_ADD | BPF_FETCH: 835 /* src_reg = atomic_fetch_add(dst_reg + off, src_reg); */ 836 EMIT2(0x0F, 0xC1); 837 break; 838 case BPF_XCHG: 839 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */ 840 EMIT1(0x87); 841 break; 842 case BPF_CMPXCHG: 843 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */ 844 EMIT2(0x0F, 0xB1); 845 break; 846 default: 847 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op); 848 return -EFAULT; 849 } 850 851 emit_insn_suffix(&prog, dst_reg, src_reg, off); 852 853 *pprog = prog; 854 return 0; 855 } 856 857 bool ex_handler_bpf(const struct exception_table_entry *x, struct pt_regs *regs) 858 { 859 u32 reg = x->fixup >> 8; 860 861 /* jump over faulting load and clear dest register */ 862 *(unsigned long *)((void *)regs + reg) = 0; 863 regs->ip += x->fixup & 0xff; 864 return true; 865 } 866 867 static void detect_reg_usage(struct bpf_insn *insn, int insn_cnt, 868 bool *regs_used, bool *tail_call_seen) 869 { 870 int i; 871 872 for (i = 1; i <= insn_cnt; i++, insn++) { 873 if (insn->code == (BPF_JMP | BPF_TAIL_CALL)) 874 *tail_call_seen = true; 875 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6) 876 regs_used[0] = true; 877 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7) 878 regs_used[1] = true; 879 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8) 880 regs_used[2] = true; 881 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9) 882 regs_used[3] = true; 883 } 884 } 885 886 static void emit_nops(u8 **pprog, int len) 887 { 888 u8 *prog = *pprog; 889 int i, noplen; 890 891 while (len > 0) { 892 noplen = len; 893 894 if (noplen > ASM_NOP_MAX) 895 noplen = ASM_NOP_MAX; 896 897 for (i = 0; i < noplen; i++) 898 EMIT1(x86_nops[noplen][i]); 899 len -= noplen; 900 } 901 902 *pprog = prog; 903 } 904 905 /* emit the 3-byte VEX prefix 906 * 907 * r: same as rex.r, extra bit for ModRM reg field 908 * x: same as rex.x, extra bit for SIB index field 909 * b: same as rex.b, extra bit for ModRM r/m, or SIB base 910 * m: opcode map select, encoding escape bytes e.g. 0x0f38 911 * w: same as rex.w (32 bit or 64 bit) or opcode specific 912 * src_reg2: additional source reg (encoded as BPF reg) 913 * l: vector length (128 bit or 256 bit) or reserved 914 * pp: opcode prefix (none, 0x66, 0xf2 or 0xf3) 915 */ 916 static void emit_3vex(u8 **pprog, bool r, bool x, bool b, u8 m, 917 bool w, u8 src_reg2, bool l, u8 pp) 918 { 919 u8 *prog = *pprog; 920 const u8 b0 = 0xc4; /* first byte of 3-byte VEX prefix */ 921 u8 b1, b2; 922 u8 vvvv = reg2hex[src_reg2]; 923 924 /* reg2hex gives only the lower 3 bit of vvvv */ 925 if (is_ereg(src_reg2)) 926 vvvv |= 1 << 3; 927 928 /* 929 * 2nd byte of 3-byte VEX prefix 930 * ~ means bit inverted encoding 931 * 932 * 7 0 933 * +---+---+---+---+---+---+---+---+ 934 * |~R |~X |~B | m | 935 * +---+---+---+---+---+---+---+---+ 936 */ 937 b1 = (!r << 7) | (!x << 6) | (!b << 5) | (m & 0x1f); 938 /* 939 * 3rd byte of 3-byte VEX prefix 940 * 941 * 7 0 942 * +---+---+---+---+---+---+---+---+ 943 * | W | ~vvvv | L | pp | 944 * +---+---+---+---+---+---+---+---+ 945 */ 946 b2 = (w << 7) | ((~vvvv & 0xf) << 3) | (l << 2) | (pp & 3); 947 948 EMIT3(b0, b1, b2); 949 *pprog = prog; 950 } 951 952 /* emit BMI2 shift instruction */ 953 static void emit_shiftx(u8 **pprog, u32 dst_reg, u8 src_reg, bool is64, u8 op) 954 { 955 u8 *prog = *pprog; 956 bool r = is_ereg(dst_reg); 957 u8 m = 2; /* escape code 0f38 */ 958 959 emit_3vex(&prog, r, false, r, m, is64, src_reg, false, op); 960 EMIT2(0xf7, add_2reg(0xC0, dst_reg, dst_reg)); 961 *pprog = prog; 962 } 963 964 #define INSN_SZ_DIFF (((addrs[i] - addrs[i - 1]) - (prog - temp))) 965 966 static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image, 967 int oldproglen, struct jit_context *ctx, bool jmp_padding) 968 { 969 bool tail_call_reachable = bpf_prog->aux->tail_call_reachable; 970 struct bpf_insn *insn = bpf_prog->insnsi; 971 bool callee_regs_used[4] = {}; 972 int insn_cnt = bpf_prog->len; 973 bool tail_call_seen = false; 974 bool seen_exit = false; 975 u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY]; 976 int i, excnt = 0; 977 int ilen, proglen = 0; 978 u8 *prog = temp; 979 int err; 980 981 detect_reg_usage(insn, insn_cnt, callee_regs_used, 982 &tail_call_seen); 983 984 /* tail call's presence in current prog implies it is reachable */ 985 tail_call_reachable |= tail_call_seen; 986 987 emit_prologue(&prog, bpf_prog->aux->stack_depth, 988 bpf_prog_was_classic(bpf_prog), tail_call_reachable, 989 bpf_prog->aux->func_idx != 0); 990 push_callee_regs(&prog, callee_regs_used); 991 992 ilen = prog - temp; 993 if (rw_image) 994 memcpy(rw_image + proglen, temp, ilen); 995 proglen += ilen; 996 addrs[0] = proglen; 997 prog = temp; 998 999 for (i = 1; i <= insn_cnt; i++, insn++) { 1000 const s32 imm32 = insn->imm; 1001 u32 dst_reg = insn->dst_reg; 1002 u32 src_reg = insn->src_reg; 1003 u8 b2 = 0, b3 = 0; 1004 u8 *start_of_ldx; 1005 s64 jmp_offset; 1006 s16 insn_off; 1007 u8 jmp_cond; 1008 u8 *func; 1009 int nops; 1010 1011 switch (insn->code) { 1012 /* ALU */ 1013 case BPF_ALU | BPF_ADD | BPF_X: 1014 case BPF_ALU | BPF_SUB | BPF_X: 1015 case BPF_ALU | BPF_AND | BPF_X: 1016 case BPF_ALU | BPF_OR | BPF_X: 1017 case BPF_ALU | BPF_XOR | BPF_X: 1018 case BPF_ALU64 | BPF_ADD | BPF_X: 1019 case BPF_ALU64 | BPF_SUB | BPF_X: 1020 case BPF_ALU64 | BPF_AND | BPF_X: 1021 case BPF_ALU64 | BPF_OR | BPF_X: 1022 case BPF_ALU64 | BPF_XOR | BPF_X: 1023 maybe_emit_mod(&prog, dst_reg, src_reg, 1024 BPF_CLASS(insn->code) == BPF_ALU64); 1025 b2 = simple_alu_opcodes[BPF_OP(insn->code)]; 1026 EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg)); 1027 break; 1028 1029 case BPF_ALU64 | BPF_MOV | BPF_X: 1030 case BPF_ALU | BPF_MOV | BPF_X: 1031 emit_mov_reg(&prog, 1032 BPF_CLASS(insn->code) == BPF_ALU64, 1033 dst_reg, src_reg); 1034 break; 1035 1036 /* neg dst */ 1037 case BPF_ALU | BPF_NEG: 1038 case BPF_ALU64 | BPF_NEG: 1039 maybe_emit_1mod(&prog, dst_reg, 1040 BPF_CLASS(insn->code) == BPF_ALU64); 1041 EMIT2(0xF7, add_1reg(0xD8, dst_reg)); 1042 break; 1043 1044 case BPF_ALU | BPF_ADD | BPF_K: 1045 case BPF_ALU | BPF_SUB | BPF_K: 1046 case BPF_ALU | BPF_AND | BPF_K: 1047 case BPF_ALU | BPF_OR | BPF_K: 1048 case BPF_ALU | BPF_XOR | BPF_K: 1049 case BPF_ALU64 | BPF_ADD | BPF_K: 1050 case BPF_ALU64 | BPF_SUB | BPF_K: 1051 case BPF_ALU64 | BPF_AND | BPF_K: 1052 case BPF_ALU64 | BPF_OR | BPF_K: 1053 case BPF_ALU64 | BPF_XOR | BPF_K: 1054 maybe_emit_1mod(&prog, dst_reg, 1055 BPF_CLASS(insn->code) == BPF_ALU64); 1056 1057 /* 1058 * b3 holds 'normal' opcode, b2 short form only valid 1059 * in case dst is eax/rax. 1060 */ 1061 switch (BPF_OP(insn->code)) { 1062 case BPF_ADD: 1063 b3 = 0xC0; 1064 b2 = 0x05; 1065 break; 1066 case BPF_SUB: 1067 b3 = 0xE8; 1068 b2 = 0x2D; 1069 break; 1070 case BPF_AND: 1071 b3 = 0xE0; 1072 b2 = 0x25; 1073 break; 1074 case BPF_OR: 1075 b3 = 0xC8; 1076 b2 = 0x0D; 1077 break; 1078 case BPF_XOR: 1079 b3 = 0xF0; 1080 b2 = 0x35; 1081 break; 1082 } 1083 1084 if (is_imm8(imm32)) 1085 EMIT3(0x83, add_1reg(b3, dst_reg), imm32); 1086 else if (is_axreg(dst_reg)) 1087 EMIT1_off32(b2, imm32); 1088 else 1089 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32); 1090 break; 1091 1092 case BPF_ALU64 | BPF_MOV | BPF_K: 1093 case BPF_ALU | BPF_MOV | BPF_K: 1094 emit_mov_imm32(&prog, BPF_CLASS(insn->code) == BPF_ALU64, 1095 dst_reg, imm32); 1096 break; 1097 1098 case BPF_LD | BPF_IMM | BPF_DW: 1099 emit_mov_imm64(&prog, dst_reg, insn[1].imm, insn[0].imm); 1100 insn++; 1101 i++; 1102 break; 1103 1104 /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */ 1105 case BPF_ALU | BPF_MOD | BPF_X: 1106 case BPF_ALU | BPF_DIV | BPF_X: 1107 case BPF_ALU | BPF_MOD | BPF_K: 1108 case BPF_ALU | BPF_DIV | BPF_K: 1109 case BPF_ALU64 | BPF_MOD | BPF_X: 1110 case BPF_ALU64 | BPF_DIV | BPF_X: 1111 case BPF_ALU64 | BPF_MOD | BPF_K: 1112 case BPF_ALU64 | BPF_DIV | BPF_K: { 1113 bool is64 = BPF_CLASS(insn->code) == BPF_ALU64; 1114 1115 if (dst_reg != BPF_REG_0) 1116 EMIT1(0x50); /* push rax */ 1117 if (dst_reg != BPF_REG_3) 1118 EMIT1(0x52); /* push rdx */ 1119 1120 if (BPF_SRC(insn->code) == BPF_X) { 1121 if (src_reg == BPF_REG_0 || 1122 src_reg == BPF_REG_3) { 1123 /* mov r11, src_reg */ 1124 EMIT_mov(AUX_REG, src_reg); 1125 src_reg = AUX_REG; 1126 } 1127 } else { 1128 /* mov r11, imm32 */ 1129 EMIT3_off32(0x49, 0xC7, 0xC3, imm32); 1130 src_reg = AUX_REG; 1131 } 1132 1133 if (dst_reg != BPF_REG_0) 1134 /* mov rax, dst_reg */ 1135 emit_mov_reg(&prog, is64, BPF_REG_0, dst_reg); 1136 1137 /* 1138 * xor edx, edx 1139 * equivalent to 'xor rdx, rdx', but one byte less 1140 */ 1141 EMIT2(0x31, 0xd2); 1142 1143 /* div src_reg */ 1144 maybe_emit_1mod(&prog, src_reg, is64); 1145 EMIT2(0xF7, add_1reg(0xF0, src_reg)); 1146 1147 if (BPF_OP(insn->code) == BPF_MOD && 1148 dst_reg != BPF_REG_3) 1149 /* mov dst_reg, rdx */ 1150 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_3); 1151 else if (BPF_OP(insn->code) == BPF_DIV && 1152 dst_reg != BPF_REG_0) 1153 /* mov dst_reg, rax */ 1154 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_0); 1155 1156 if (dst_reg != BPF_REG_3) 1157 EMIT1(0x5A); /* pop rdx */ 1158 if (dst_reg != BPF_REG_0) 1159 EMIT1(0x58); /* pop rax */ 1160 break; 1161 } 1162 1163 case BPF_ALU | BPF_MUL | BPF_K: 1164 case BPF_ALU64 | BPF_MUL | BPF_K: 1165 maybe_emit_mod(&prog, dst_reg, dst_reg, 1166 BPF_CLASS(insn->code) == BPF_ALU64); 1167 1168 if (is_imm8(imm32)) 1169 /* imul dst_reg, dst_reg, imm8 */ 1170 EMIT3(0x6B, add_2reg(0xC0, dst_reg, dst_reg), 1171 imm32); 1172 else 1173 /* imul dst_reg, dst_reg, imm32 */ 1174 EMIT2_off32(0x69, 1175 add_2reg(0xC0, dst_reg, dst_reg), 1176 imm32); 1177 break; 1178 1179 case BPF_ALU | BPF_MUL | BPF_X: 1180 case BPF_ALU64 | BPF_MUL | BPF_X: 1181 maybe_emit_mod(&prog, src_reg, dst_reg, 1182 BPF_CLASS(insn->code) == BPF_ALU64); 1183 1184 /* imul dst_reg, src_reg */ 1185 EMIT3(0x0F, 0xAF, add_2reg(0xC0, src_reg, dst_reg)); 1186 break; 1187 1188 /* Shifts */ 1189 case BPF_ALU | BPF_LSH | BPF_K: 1190 case BPF_ALU | BPF_RSH | BPF_K: 1191 case BPF_ALU | BPF_ARSH | BPF_K: 1192 case BPF_ALU64 | BPF_LSH | BPF_K: 1193 case BPF_ALU64 | BPF_RSH | BPF_K: 1194 case BPF_ALU64 | BPF_ARSH | BPF_K: 1195 maybe_emit_1mod(&prog, dst_reg, 1196 BPF_CLASS(insn->code) == BPF_ALU64); 1197 1198 b3 = simple_alu_opcodes[BPF_OP(insn->code)]; 1199 if (imm32 == 1) 1200 EMIT2(0xD1, add_1reg(b3, dst_reg)); 1201 else 1202 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32); 1203 break; 1204 1205 case BPF_ALU | BPF_LSH | BPF_X: 1206 case BPF_ALU | BPF_RSH | BPF_X: 1207 case BPF_ALU | BPF_ARSH | BPF_X: 1208 case BPF_ALU64 | BPF_LSH | BPF_X: 1209 case BPF_ALU64 | BPF_RSH | BPF_X: 1210 case BPF_ALU64 | BPF_ARSH | BPF_X: 1211 /* BMI2 shifts aren't better when shift count is already in rcx */ 1212 if (boot_cpu_has(X86_FEATURE_BMI2) && src_reg != BPF_REG_4) { 1213 /* shrx/sarx/shlx dst_reg, dst_reg, src_reg */ 1214 bool w = (BPF_CLASS(insn->code) == BPF_ALU64); 1215 u8 op; 1216 1217 switch (BPF_OP(insn->code)) { 1218 case BPF_LSH: 1219 op = 1; /* prefix 0x66 */ 1220 break; 1221 case BPF_RSH: 1222 op = 3; /* prefix 0xf2 */ 1223 break; 1224 case BPF_ARSH: 1225 op = 2; /* prefix 0xf3 */ 1226 break; 1227 } 1228 1229 emit_shiftx(&prog, dst_reg, src_reg, w, op); 1230 1231 break; 1232 } 1233 1234 if (src_reg != BPF_REG_4) { /* common case */ 1235 /* Check for bad case when dst_reg == rcx */ 1236 if (dst_reg == BPF_REG_4) { 1237 /* mov r11, dst_reg */ 1238 EMIT_mov(AUX_REG, dst_reg); 1239 dst_reg = AUX_REG; 1240 } else { 1241 EMIT1(0x51); /* push rcx */ 1242 } 1243 /* mov rcx, src_reg */ 1244 EMIT_mov(BPF_REG_4, src_reg); 1245 } 1246 1247 /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */ 1248 maybe_emit_1mod(&prog, dst_reg, 1249 BPF_CLASS(insn->code) == BPF_ALU64); 1250 1251 b3 = simple_alu_opcodes[BPF_OP(insn->code)]; 1252 EMIT2(0xD3, add_1reg(b3, dst_reg)); 1253 1254 if (src_reg != BPF_REG_4) { 1255 if (insn->dst_reg == BPF_REG_4) 1256 /* mov dst_reg, r11 */ 1257 EMIT_mov(insn->dst_reg, AUX_REG); 1258 else 1259 EMIT1(0x59); /* pop rcx */ 1260 } 1261 1262 break; 1263 1264 case BPF_ALU | BPF_END | BPF_FROM_BE: 1265 switch (imm32) { 1266 case 16: 1267 /* Emit 'ror %ax, 8' to swap lower 2 bytes */ 1268 EMIT1(0x66); 1269 if (is_ereg(dst_reg)) 1270 EMIT1(0x41); 1271 EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8); 1272 1273 /* Emit 'movzwl eax, ax' */ 1274 if (is_ereg(dst_reg)) 1275 EMIT3(0x45, 0x0F, 0xB7); 1276 else 1277 EMIT2(0x0F, 0xB7); 1278 EMIT1(add_2reg(0xC0, dst_reg, dst_reg)); 1279 break; 1280 case 32: 1281 /* Emit 'bswap eax' to swap lower 4 bytes */ 1282 if (is_ereg(dst_reg)) 1283 EMIT2(0x41, 0x0F); 1284 else 1285 EMIT1(0x0F); 1286 EMIT1(add_1reg(0xC8, dst_reg)); 1287 break; 1288 case 64: 1289 /* Emit 'bswap rax' to swap 8 bytes */ 1290 EMIT3(add_1mod(0x48, dst_reg), 0x0F, 1291 add_1reg(0xC8, dst_reg)); 1292 break; 1293 } 1294 break; 1295 1296 case BPF_ALU | BPF_END | BPF_FROM_LE: 1297 switch (imm32) { 1298 case 16: 1299 /* 1300 * Emit 'movzwl eax, ax' to zero extend 16-bit 1301 * into 64 bit 1302 */ 1303 if (is_ereg(dst_reg)) 1304 EMIT3(0x45, 0x0F, 0xB7); 1305 else 1306 EMIT2(0x0F, 0xB7); 1307 EMIT1(add_2reg(0xC0, dst_reg, dst_reg)); 1308 break; 1309 case 32: 1310 /* Emit 'mov eax, eax' to clear upper 32-bits */ 1311 if (is_ereg(dst_reg)) 1312 EMIT1(0x45); 1313 EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg)); 1314 break; 1315 case 64: 1316 /* nop */ 1317 break; 1318 } 1319 break; 1320 1321 /* speculation barrier */ 1322 case BPF_ST | BPF_NOSPEC: 1323 EMIT_LFENCE(); 1324 break; 1325 1326 /* ST: *(u8*)(dst_reg + off) = imm */ 1327 case BPF_ST | BPF_MEM | BPF_B: 1328 if (is_ereg(dst_reg)) 1329 EMIT2(0x41, 0xC6); 1330 else 1331 EMIT1(0xC6); 1332 goto st; 1333 case BPF_ST | BPF_MEM | BPF_H: 1334 if (is_ereg(dst_reg)) 1335 EMIT3(0x66, 0x41, 0xC7); 1336 else 1337 EMIT2(0x66, 0xC7); 1338 goto st; 1339 case BPF_ST | BPF_MEM | BPF_W: 1340 if (is_ereg(dst_reg)) 1341 EMIT2(0x41, 0xC7); 1342 else 1343 EMIT1(0xC7); 1344 goto st; 1345 case BPF_ST | BPF_MEM | BPF_DW: 1346 EMIT2(add_1mod(0x48, dst_reg), 0xC7); 1347 1348 st: if (is_imm8(insn->off)) 1349 EMIT2(add_1reg(0x40, dst_reg), insn->off); 1350 else 1351 EMIT1_off32(add_1reg(0x80, dst_reg), insn->off); 1352 1353 EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(insn->code))); 1354 break; 1355 1356 /* STX: *(u8*)(dst_reg + off) = src_reg */ 1357 case BPF_STX | BPF_MEM | BPF_B: 1358 case BPF_STX | BPF_MEM | BPF_H: 1359 case BPF_STX | BPF_MEM | BPF_W: 1360 case BPF_STX | BPF_MEM | BPF_DW: 1361 emit_stx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off); 1362 break; 1363 1364 /* LDX: dst_reg = *(u8*)(src_reg + off) */ 1365 case BPF_LDX | BPF_MEM | BPF_B: 1366 case BPF_LDX | BPF_PROBE_MEM | BPF_B: 1367 case BPF_LDX | BPF_MEM | BPF_H: 1368 case BPF_LDX | BPF_PROBE_MEM | BPF_H: 1369 case BPF_LDX | BPF_MEM | BPF_W: 1370 case BPF_LDX | BPF_PROBE_MEM | BPF_W: 1371 case BPF_LDX | BPF_MEM | BPF_DW: 1372 case BPF_LDX | BPF_PROBE_MEM | BPF_DW: 1373 insn_off = insn->off; 1374 1375 if (BPF_MODE(insn->code) == BPF_PROBE_MEM) { 1376 /* Conservatively check that src_reg + insn->off is a kernel address: 1377 * src_reg + insn->off >= TASK_SIZE_MAX + PAGE_SIZE 1378 * src_reg is used as scratch for src_reg += insn->off and restored 1379 * after emit_ldx if necessary 1380 */ 1381 1382 u64 limit = TASK_SIZE_MAX + PAGE_SIZE; 1383 u8 *end_of_jmp; 1384 1385 /* At end of these emitted checks, insn->off will have been added 1386 * to src_reg, so no need to do relative load with insn->off offset 1387 */ 1388 insn_off = 0; 1389 1390 /* movabsq r11, limit */ 1391 EMIT2(add_1mod(0x48, AUX_REG), add_1reg(0xB8, AUX_REG)); 1392 EMIT((u32)limit, 4); 1393 EMIT(limit >> 32, 4); 1394 1395 if (insn->off) { 1396 /* add src_reg, insn->off */ 1397 maybe_emit_1mod(&prog, src_reg, true); 1398 EMIT2_off32(0x81, add_1reg(0xC0, src_reg), insn->off); 1399 } 1400 1401 /* cmp src_reg, r11 */ 1402 maybe_emit_mod(&prog, src_reg, AUX_REG, true); 1403 EMIT2(0x39, add_2reg(0xC0, src_reg, AUX_REG)); 1404 1405 /* if unsigned '>=', goto load */ 1406 EMIT2(X86_JAE, 0); 1407 end_of_jmp = prog; 1408 1409 /* xor dst_reg, dst_reg */ 1410 emit_mov_imm32(&prog, false, dst_reg, 0); 1411 /* jmp byte_after_ldx */ 1412 EMIT2(0xEB, 0); 1413 1414 /* populate jmp_offset for JAE above to jump to start_of_ldx */ 1415 start_of_ldx = prog; 1416 end_of_jmp[-1] = start_of_ldx - end_of_jmp; 1417 } 1418 emit_ldx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn_off); 1419 if (BPF_MODE(insn->code) == BPF_PROBE_MEM) { 1420 struct exception_table_entry *ex; 1421 u8 *_insn = image + proglen + (start_of_ldx - temp); 1422 s64 delta; 1423 1424 /* populate jmp_offset for JMP above */ 1425 start_of_ldx[-1] = prog - start_of_ldx; 1426 1427 if (insn->off && src_reg != dst_reg) { 1428 /* sub src_reg, insn->off 1429 * Restore src_reg after "add src_reg, insn->off" in prev 1430 * if statement. But if src_reg == dst_reg, emit_ldx 1431 * above already clobbered src_reg, so no need to restore. 1432 * If add src_reg, insn->off was unnecessary, no need to 1433 * restore either. 1434 */ 1435 maybe_emit_1mod(&prog, src_reg, true); 1436 EMIT2_off32(0x81, add_1reg(0xE8, src_reg), insn->off); 1437 } 1438 1439 if (!bpf_prog->aux->extable) 1440 break; 1441 1442 if (excnt >= bpf_prog->aux->num_exentries) { 1443 pr_err("ex gen bug\n"); 1444 return -EFAULT; 1445 } 1446 ex = &bpf_prog->aux->extable[excnt++]; 1447 1448 delta = _insn - (u8 *)&ex->insn; 1449 if (!is_simm32(delta)) { 1450 pr_err("extable->insn doesn't fit into 32-bit\n"); 1451 return -EFAULT; 1452 } 1453 /* switch ex to rw buffer for writes */ 1454 ex = (void *)rw_image + ((void *)ex - (void *)image); 1455 1456 ex->insn = delta; 1457 1458 ex->data = EX_TYPE_BPF; 1459 1460 if (dst_reg > BPF_REG_9) { 1461 pr_err("verifier error\n"); 1462 return -EFAULT; 1463 } 1464 /* 1465 * Compute size of x86 insn and its target dest x86 register. 1466 * ex_handler_bpf() will use lower 8 bits to adjust 1467 * pt_regs->ip to jump over this x86 instruction 1468 * and upper bits to figure out which pt_regs to zero out. 1469 * End result: x86 insn "mov rbx, qword ptr [rax+0x14]" 1470 * of 4 bytes will be ignored and rbx will be zero inited. 1471 */ 1472 ex->fixup = (prog - start_of_ldx) | (reg2pt_regs[dst_reg] << 8); 1473 } 1474 break; 1475 1476 case BPF_STX | BPF_ATOMIC | BPF_W: 1477 case BPF_STX | BPF_ATOMIC | BPF_DW: 1478 if (insn->imm == (BPF_AND | BPF_FETCH) || 1479 insn->imm == (BPF_OR | BPF_FETCH) || 1480 insn->imm == (BPF_XOR | BPF_FETCH)) { 1481 bool is64 = BPF_SIZE(insn->code) == BPF_DW; 1482 u32 real_src_reg = src_reg; 1483 u32 real_dst_reg = dst_reg; 1484 u8 *branch_target; 1485 1486 /* 1487 * Can't be implemented with a single x86 insn. 1488 * Need to do a CMPXCHG loop. 1489 */ 1490 1491 /* Will need RAX as a CMPXCHG operand so save R0 */ 1492 emit_mov_reg(&prog, true, BPF_REG_AX, BPF_REG_0); 1493 if (src_reg == BPF_REG_0) 1494 real_src_reg = BPF_REG_AX; 1495 if (dst_reg == BPF_REG_0) 1496 real_dst_reg = BPF_REG_AX; 1497 1498 branch_target = prog; 1499 /* Load old value */ 1500 emit_ldx(&prog, BPF_SIZE(insn->code), 1501 BPF_REG_0, real_dst_reg, insn->off); 1502 /* 1503 * Perform the (commutative) operation locally, 1504 * put the result in the AUX_REG. 1505 */ 1506 emit_mov_reg(&prog, is64, AUX_REG, BPF_REG_0); 1507 maybe_emit_mod(&prog, AUX_REG, real_src_reg, is64); 1508 EMIT2(simple_alu_opcodes[BPF_OP(insn->imm)], 1509 add_2reg(0xC0, AUX_REG, real_src_reg)); 1510 /* Attempt to swap in new value */ 1511 err = emit_atomic(&prog, BPF_CMPXCHG, 1512 real_dst_reg, AUX_REG, 1513 insn->off, 1514 BPF_SIZE(insn->code)); 1515 if (WARN_ON(err)) 1516 return err; 1517 /* 1518 * ZF tells us whether we won the race. If it's 1519 * cleared we need to try again. 1520 */ 1521 EMIT2(X86_JNE, -(prog - branch_target) - 2); 1522 /* Return the pre-modification value */ 1523 emit_mov_reg(&prog, is64, real_src_reg, BPF_REG_0); 1524 /* Restore R0 after clobbering RAX */ 1525 emit_mov_reg(&prog, true, BPF_REG_0, BPF_REG_AX); 1526 break; 1527 } 1528 1529 err = emit_atomic(&prog, insn->imm, dst_reg, src_reg, 1530 insn->off, BPF_SIZE(insn->code)); 1531 if (err) 1532 return err; 1533 break; 1534 1535 /* call */ 1536 case BPF_JMP | BPF_CALL: { 1537 int offs; 1538 1539 func = (u8 *) __bpf_call_base + imm32; 1540 if (tail_call_reachable) { 1541 /* mov rax, qword ptr [rbp - rounded_stack_depth - 8] */ 1542 EMIT3_off32(0x48, 0x8B, 0x85, 1543 -round_up(bpf_prog->aux->stack_depth, 8) - 8); 1544 if (!imm32) 1545 return -EINVAL; 1546 offs = 7 + x86_call_depth_emit_accounting(&prog, func); 1547 } else { 1548 if (!imm32) 1549 return -EINVAL; 1550 offs = x86_call_depth_emit_accounting(&prog, func); 1551 } 1552 if (emit_call(&prog, func, image + addrs[i - 1] + offs)) 1553 return -EINVAL; 1554 break; 1555 } 1556 1557 case BPF_JMP | BPF_TAIL_CALL: 1558 if (imm32) 1559 emit_bpf_tail_call_direct(&bpf_prog->aux->poke_tab[imm32 - 1], 1560 &prog, image + addrs[i - 1], 1561 callee_regs_used, 1562 bpf_prog->aux->stack_depth, 1563 ctx); 1564 else 1565 emit_bpf_tail_call_indirect(&prog, 1566 callee_regs_used, 1567 bpf_prog->aux->stack_depth, 1568 image + addrs[i - 1], 1569 ctx); 1570 break; 1571 1572 /* cond jump */ 1573 case BPF_JMP | BPF_JEQ | BPF_X: 1574 case BPF_JMP | BPF_JNE | BPF_X: 1575 case BPF_JMP | BPF_JGT | BPF_X: 1576 case BPF_JMP | BPF_JLT | BPF_X: 1577 case BPF_JMP | BPF_JGE | BPF_X: 1578 case BPF_JMP | BPF_JLE | BPF_X: 1579 case BPF_JMP | BPF_JSGT | BPF_X: 1580 case BPF_JMP | BPF_JSLT | BPF_X: 1581 case BPF_JMP | BPF_JSGE | BPF_X: 1582 case BPF_JMP | BPF_JSLE | BPF_X: 1583 case BPF_JMP32 | BPF_JEQ | BPF_X: 1584 case BPF_JMP32 | BPF_JNE | BPF_X: 1585 case BPF_JMP32 | BPF_JGT | BPF_X: 1586 case BPF_JMP32 | BPF_JLT | BPF_X: 1587 case BPF_JMP32 | BPF_JGE | BPF_X: 1588 case BPF_JMP32 | BPF_JLE | BPF_X: 1589 case BPF_JMP32 | BPF_JSGT | BPF_X: 1590 case BPF_JMP32 | BPF_JSLT | BPF_X: 1591 case BPF_JMP32 | BPF_JSGE | BPF_X: 1592 case BPF_JMP32 | BPF_JSLE | BPF_X: 1593 /* cmp dst_reg, src_reg */ 1594 maybe_emit_mod(&prog, dst_reg, src_reg, 1595 BPF_CLASS(insn->code) == BPF_JMP); 1596 EMIT2(0x39, add_2reg(0xC0, dst_reg, src_reg)); 1597 goto emit_cond_jmp; 1598 1599 case BPF_JMP | BPF_JSET | BPF_X: 1600 case BPF_JMP32 | BPF_JSET | BPF_X: 1601 /* test dst_reg, src_reg */ 1602 maybe_emit_mod(&prog, dst_reg, src_reg, 1603 BPF_CLASS(insn->code) == BPF_JMP); 1604 EMIT2(0x85, add_2reg(0xC0, dst_reg, src_reg)); 1605 goto emit_cond_jmp; 1606 1607 case BPF_JMP | BPF_JSET | BPF_K: 1608 case BPF_JMP32 | BPF_JSET | BPF_K: 1609 /* test dst_reg, imm32 */ 1610 maybe_emit_1mod(&prog, dst_reg, 1611 BPF_CLASS(insn->code) == BPF_JMP); 1612 EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32); 1613 goto emit_cond_jmp; 1614 1615 case BPF_JMP | BPF_JEQ | BPF_K: 1616 case BPF_JMP | BPF_JNE | BPF_K: 1617 case BPF_JMP | BPF_JGT | BPF_K: 1618 case BPF_JMP | BPF_JLT | BPF_K: 1619 case BPF_JMP | BPF_JGE | BPF_K: 1620 case BPF_JMP | BPF_JLE | BPF_K: 1621 case BPF_JMP | BPF_JSGT | BPF_K: 1622 case BPF_JMP | BPF_JSLT | BPF_K: 1623 case BPF_JMP | BPF_JSGE | BPF_K: 1624 case BPF_JMP | BPF_JSLE | BPF_K: 1625 case BPF_JMP32 | BPF_JEQ | BPF_K: 1626 case BPF_JMP32 | BPF_JNE | BPF_K: 1627 case BPF_JMP32 | BPF_JGT | BPF_K: 1628 case BPF_JMP32 | BPF_JLT | BPF_K: 1629 case BPF_JMP32 | BPF_JGE | BPF_K: 1630 case BPF_JMP32 | BPF_JLE | BPF_K: 1631 case BPF_JMP32 | BPF_JSGT | BPF_K: 1632 case BPF_JMP32 | BPF_JSLT | BPF_K: 1633 case BPF_JMP32 | BPF_JSGE | BPF_K: 1634 case BPF_JMP32 | BPF_JSLE | BPF_K: 1635 /* test dst_reg, dst_reg to save one extra byte */ 1636 if (imm32 == 0) { 1637 maybe_emit_mod(&prog, dst_reg, dst_reg, 1638 BPF_CLASS(insn->code) == BPF_JMP); 1639 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg)); 1640 goto emit_cond_jmp; 1641 } 1642 1643 /* cmp dst_reg, imm8/32 */ 1644 maybe_emit_1mod(&prog, dst_reg, 1645 BPF_CLASS(insn->code) == BPF_JMP); 1646 1647 if (is_imm8(imm32)) 1648 EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32); 1649 else 1650 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32); 1651 1652 emit_cond_jmp: /* Convert BPF opcode to x86 */ 1653 switch (BPF_OP(insn->code)) { 1654 case BPF_JEQ: 1655 jmp_cond = X86_JE; 1656 break; 1657 case BPF_JSET: 1658 case BPF_JNE: 1659 jmp_cond = X86_JNE; 1660 break; 1661 case BPF_JGT: 1662 /* GT is unsigned '>', JA in x86 */ 1663 jmp_cond = X86_JA; 1664 break; 1665 case BPF_JLT: 1666 /* LT is unsigned '<', JB in x86 */ 1667 jmp_cond = X86_JB; 1668 break; 1669 case BPF_JGE: 1670 /* GE is unsigned '>=', JAE in x86 */ 1671 jmp_cond = X86_JAE; 1672 break; 1673 case BPF_JLE: 1674 /* LE is unsigned '<=', JBE in x86 */ 1675 jmp_cond = X86_JBE; 1676 break; 1677 case BPF_JSGT: 1678 /* Signed '>', GT in x86 */ 1679 jmp_cond = X86_JG; 1680 break; 1681 case BPF_JSLT: 1682 /* Signed '<', LT in x86 */ 1683 jmp_cond = X86_JL; 1684 break; 1685 case BPF_JSGE: 1686 /* Signed '>=', GE in x86 */ 1687 jmp_cond = X86_JGE; 1688 break; 1689 case BPF_JSLE: 1690 /* Signed '<=', LE in x86 */ 1691 jmp_cond = X86_JLE; 1692 break; 1693 default: /* to silence GCC warning */ 1694 return -EFAULT; 1695 } 1696 jmp_offset = addrs[i + insn->off] - addrs[i]; 1697 if (is_imm8(jmp_offset)) { 1698 if (jmp_padding) { 1699 /* To keep the jmp_offset valid, the extra bytes are 1700 * padded before the jump insn, so we subtract the 1701 * 2 bytes of jmp_cond insn from INSN_SZ_DIFF. 1702 * 1703 * If the previous pass already emits an imm8 1704 * jmp_cond, then this BPF insn won't shrink, so 1705 * "nops" is 0. 1706 * 1707 * On the other hand, if the previous pass emits an 1708 * imm32 jmp_cond, the extra 4 bytes(*) is padded to 1709 * keep the image from shrinking further. 1710 * 1711 * (*) imm32 jmp_cond is 6 bytes, and imm8 jmp_cond 1712 * is 2 bytes, so the size difference is 4 bytes. 1713 */ 1714 nops = INSN_SZ_DIFF - 2; 1715 if (nops != 0 && nops != 4) { 1716 pr_err("unexpected jmp_cond padding: %d bytes\n", 1717 nops); 1718 return -EFAULT; 1719 } 1720 emit_nops(&prog, nops); 1721 } 1722 EMIT2(jmp_cond, jmp_offset); 1723 } else if (is_simm32(jmp_offset)) { 1724 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset); 1725 } else { 1726 pr_err("cond_jmp gen bug %llx\n", jmp_offset); 1727 return -EFAULT; 1728 } 1729 1730 break; 1731 1732 case BPF_JMP | BPF_JA: 1733 if (insn->off == -1) 1734 /* -1 jmp instructions will always jump 1735 * backwards two bytes. Explicitly handling 1736 * this case avoids wasting too many passes 1737 * when there are long sequences of replaced 1738 * dead code. 1739 */ 1740 jmp_offset = -2; 1741 else 1742 jmp_offset = addrs[i + insn->off] - addrs[i]; 1743 1744 if (!jmp_offset) { 1745 /* 1746 * If jmp_padding is enabled, the extra nops will 1747 * be inserted. Otherwise, optimize out nop jumps. 1748 */ 1749 if (jmp_padding) { 1750 /* There are 3 possible conditions. 1751 * (1) This BPF_JA is already optimized out in 1752 * the previous run, so there is no need 1753 * to pad any extra byte (0 byte). 1754 * (2) The previous pass emits an imm8 jmp, 1755 * so we pad 2 bytes to match the previous 1756 * insn size. 1757 * (3) Similarly, the previous pass emits an 1758 * imm32 jmp, and 5 bytes is padded. 1759 */ 1760 nops = INSN_SZ_DIFF; 1761 if (nops != 0 && nops != 2 && nops != 5) { 1762 pr_err("unexpected nop jump padding: %d bytes\n", 1763 nops); 1764 return -EFAULT; 1765 } 1766 emit_nops(&prog, nops); 1767 } 1768 break; 1769 } 1770 emit_jmp: 1771 if (is_imm8(jmp_offset)) { 1772 if (jmp_padding) { 1773 /* To avoid breaking jmp_offset, the extra bytes 1774 * are padded before the actual jmp insn, so 1775 * 2 bytes is subtracted from INSN_SZ_DIFF. 1776 * 1777 * If the previous pass already emits an imm8 1778 * jmp, there is nothing to pad (0 byte). 1779 * 1780 * If it emits an imm32 jmp (5 bytes) previously 1781 * and now an imm8 jmp (2 bytes), then we pad 1782 * (5 - 2 = 3) bytes to stop the image from 1783 * shrinking further. 1784 */ 1785 nops = INSN_SZ_DIFF - 2; 1786 if (nops != 0 && nops != 3) { 1787 pr_err("unexpected jump padding: %d bytes\n", 1788 nops); 1789 return -EFAULT; 1790 } 1791 emit_nops(&prog, INSN_SZ_DIFF - 2); 1792 } 1793 EMIT2(0xEB, jmp_offset); 1794 } else if (is_simm32(jmp_offset)) { 1795 EMIT1_off32(0xE9, jmp_offset); 1796 } else { 1797 pr_err("jmp gen bug %llx\n", jmp_offset); 1798 return -EFAULT; 1799 } 1800 break; 1801 1802 case BPF_JMP | BPF_EXIT: 1803 if (seen_exit) { 1804 jmp_offset = ctx->cleanup_addr - addrs[i]; 1805 goto emit_jmp; 1806 } 1807 seen_exit = true; 1808 /* Update cleanup_addr */ 1809 ctx->cleanup_addr = proglen; 1810 pop_callee_regs(&prog, callee_regs_used); 1811 EMIT1(0xC9); /* leave */ 1812 emit_return(&prog, image + addrs[i - 1] + (prog - temp)); 1813 break; 1814 1815 default: 1816 /* 1817 * By design x86-64 JIT should support all BPF instructions. 1818 * This error will be seen if new instruction was added 1819 * to the interpreter, but not to the JIT, or if there is 1820 * junk in bpf_prog. 1821 */ 1822 pr_err("bpf_jit: unknown opcode %02x\n", insn->code); 1823 return -EINVAL; 1824 } 1825 1826 ilen = prog - temp; 1827 if (ilen > BPF_MAX_INSN_SIZE) { 1828 pr_err("bpf_jit: fatal insn size error\n"); 1829 return -EFAULT; 1830 } 1831 1832 if (image) { 1833 /* 1834 * When populating the image, assert that: 1835 * 1836 * i) We do not write beyond the allocated space, and 1837 * ii) addrs[i] did not change from the prior run, in order 1838 * to validate assumptions made for computing branch 1839 * displacements. 1840 */ 1841 if (unlikely(proglen + ilen > oldproglen || 1842 proglen + ilen != addrs[i])) { 1843 pr_err("bpf_jit: fatal error\n"); 1844 return -EFAULT; 1845 } 1846 memcpy(rw_image + proglen, temp, ilen); 1847 } 1848 proglen += ilen; 1849 addrs[i] = proglen; 1850 prog = temp; 1851 } 1852 1853 if (image && excnt != bpf_prog->aux->num_exentries) { 1854 pr_err("extable is not populated\n"); 1855 return -EFAULT; 1856 } 1857 return proglen; 1858 } 1859 1860 static void save_regs(const struct btf_func_model *m, u8 **prog, int nr_regs, 1861 int stack_size) 1862 { 1863 int i, j, arg_size; 1864 bool next_same_struct = false; 1865 1866 /* Store function arguments to stack. 1867 * For a function that accepts two pointers the sequence will be: 1868 * mov QWORD PTR [rbp-0x10],rdi 1869 * mov QWORD PTR [rbp-0x8],rsi 1870 */ 1871 for (i = 0, j = 0; i < min(nr_regs, 6); i++) { 1872 /* The arg_size is at most 16 bytes, enforced by the verifier. */ 1873 arg_size = m->arg_size[j]; 1874 if (arg_size > 8) { 1875 arg_size = 8; 1876 next_same_struct = !next_same_struct; 1877 } 1878 1879 emit_stx(prog, bytes_to_bpf_size(arg_size), 1880 BPF_REG_FP, 1881 i == 5 ? X86_REG_R9 : BPF_REG_1 + i, 1882 -(stack_size - i * 8)); 1883 1884 j = next_same_struct ? j : j + 1; 1885 } 1886 } 1887 1888 static void restore_regs(const struct btf_func_model *m, u8 **prog, int nr_regs, 1889 int stack_size) 1890 { 1891 int i, j, arg_size; 1892 bool next_same_struct = false; 1893 1894 /* Restore function arguments from stack. 1895 * For a function that accepts two pointers the sequence will be: 1896 * EMIT4(0x48, 0x8B, 0x7D, 0xF0); mov rdi,QWORD PTR [rbp-0x10] 1897 * EMIT4(0x48, 0x8B, 0x75, 0xF8); mov rsi,QWORD PTR [rbp-0x8] 1898 */ 1899 for (i = 0, j = 0; i < min(nr_regs, 6); i++) { 1900 /* The arg_size is at most 16 bytes, enforced by the verifier. */ 1901 arg_size = m->arg_size[j]; 1902 if (arg_size > 8) { 1903 arg_size = 8; 1904 next_same_struct = !next_same_struct; 1905 } 1906 1907 emit_ldx(prog, bytes_to_bpf_size(arg_size), 1908 i == 5 ? X86_REG_R9 : BPF_REG_1 + i, 1909 BPF_REG_FP, 1910 -(stack_size - i * 8)); 1911 1912 j = next_same_struct ? j : j + 1; 1913 } 1914 } 1915 1916 static int invoke_bpf_prog(const struct btf_func_model *m, u8 **pprog, 1917 struct bpf_tramp_link *l, int stack_size, 1918 int run_ctx_off, bool save_ret) 1919 { 1920 u8 *prog = *pprog; 1921 u8 *jmp_insn; 1922 int ctx_cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie); 1923 struct bpf_prog *p = l->link.prog; 1924 u64 cookie = l->cookie; 1925 1926 /* mov rdi, cookie */ 1927 emit_mov_imm64(&prog, BPF_REG_1, (long) cookie >> 32, (u32) (long) cookie); 1928 1929 /* Prepare struct bpf_tramp_run_ctx. 1930 * 1931 * bpf_tramp_run_ctx is already preserved by 1932 * arch_prepare_bpf_trampoline(). 1933 * 1934 * mov QWORD PTR [rbp - run_ctx_off + ctx_cookie_off], rdi 1935 */ 1936 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_1, -run_ctx_off + ctx_cookie_off); 1937 1938 /* arg1: mov rdi, progs[i] */ 1939 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p); 1940 /* arg2: lea rsi, [rbp - ctx_cookie_off] */ 1941 EMIT4(0x48, 0x8D, 0x75, -run_ctx_off); 1942 1943 if (emit_rsb_call(&prog, bpf_trampoline_enter(p), prog)) 1944 return -EINVAL; 1945 /* remember prog start time returned by __bpf_prog_enter */ 1946 emit_mov_reg(&prog, true, BPF_REG_6, BPF_REG_0); 1947 1948 /* if (__bpf_prog_enter*(prog) == 0) 1949 * goto skip_exec_of_prog; 1950 */ 1951 EMIT3(0x48, 0x85, 0xC0); /* test rax,rax */ 1952 /* emit 2 nops that will be replaced with JE insn */ 1953 jmp_insn = prog; 1954 emit_nops(&prog, 2); 1955 1956 /* arg1: lea rdi, [rbp - stack_size] */ 1957 EMIT4(0x48, 0x8D, 0x7D, -stack_size); 1958 /* arg2: progs[i]->insnsi for interpreter */ 1959 if (!p->jited) 1960 emit_mov_imm64(&prog, BPF_REG_2, 1961 (long) p->insnsi >> 32, 1962 (u32) (long) p->insnsi); 1963 /* call JITed bpf program or interpreter */ 1964 if (emit_rsb_call(&prog, p->bpf_func, prog)) 1965 return -EINVAL; 1966 1967 /* 1968 * BPF_TRAMP_MODIFY_RETURN trampolines can modify the return 1969 * of the previous call which is then passed on the stack to 1970 * the next BPF program. 1971 * 1972 * BPF_TRAMP_FENTRY trampoline may need to return the return 1973 * value of BPF_PROG_TYPE_STRUCT_OPS prog. 1974 */ 1975 if (save_ret) 1976 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); 1977 1978 /* replace 2 nops with JE insn, since jmp target is known */ 1979 jmp_insn[0] = X86_JE; 1980 jmp_insn[1] = prog - jmp_insn - 2; 1981 1982 /* arg1: mov rdi, progs[i] */ 1983 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p); 1984 /* arg2: mov rsi, rbx <- start time in nsec */ 1985 emit_mov_reg(&prog, true, BPF_REG_2, BPF_REG_6); 1986 /* arg3: lea rdx, [rbp - run_ctx_off] */ 1987 EMIT4(0x48, 0x8D, 0x55, -run_ctx_off); 1988 if (emit_rsb_call(&prog, bpf_trampoline_exit(p), prog)) 1989 return -EINVAL; 1990 1991 *pprog = prog; 1992 return 0; 1993 } 1994 1995 static void emit_align(u8 **pprog, u32 align) 1996 { 1997 u8 *target, *prog = *pprog; 1998 1999 target = PTR_ALIGN(prog, align); 2000 if (target != prog) 2001 emit_nops(&prog, target - prog); 2002 2003 *pprog = prog; 2004 } 2005 2006 static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond) 2007 { 2008 u8 *prog = *pprog; 2009 s64 offset; 2010 2011 offset = func - (ip + 2 + 4); 2012 if (!is_simm32(offset)) { 2013 pr_err("Target %p is out of range\n", func); 2014 return -EINVAL; 2015 } 2016 EMIT2_off32(0x0F, jmp_cond + 0x10, offset); 2017 *pprog = prog; 2018 return 0; 2019 } 2020 2021 static int invoke_bpf(const struct btf_func_model *m, u8 **pprog, 2022 struct bpf_tramp_links *tl, int stack_size, 2023 int run_ctx_off, bool save_ret) 2024 { 2025 int i; 2026 u8 *prog = *pprog; 2027 2028 for (i = 0; i < tl->nr_links; i++) { 2029 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size, 2030 run_ctx_off, save_ret)) 2031 return -EINVAL; 2032 } 2033 *pprog = prog; 2034 return 0; 2035 } 2036 2037 static int invoke_bpf_mod_ret(const struct btf_func_model *m, u8 **pprog, 2038 struct bpf_tramp_links *tl, int stack_size, 2039 int run_ctx_off, u8 **branches) 2040 { 2041 u8 *prog = *pprog; 2042 int i; 2043 2044 /* The first fmod_ret program will receive a garbage return value. 2045 * Set this to 0 to avoid confusing the program. 2046 */ 2047 emit_mov_imm32(&prog, false, BPF_REG_0, 0); 2048 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); 2049 for (i = 0; i < tl->nr_links; i++) { 2050 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size, run_ctx_off, true)) 2051 return -EINVAL; 2052 2053 /* mod_ret prog stored return value into [rbp - 8]. Emit: 2054 * if (*(u64 *)(rbp - 8) != 0) 2055 * goto do_fexit; 2056 */ 2057 /* cmp QWORD PTR [rbp - 0x8], 0x0 */ 2058 EMIT4(0x48, 0x83, 0x7d, 0xf8); EMIT1(0x00); 2059 2060 /* Save the location of the branch and Generate 6 nops 2061 * (4 bytes for an offset and 2 bytes for the jump) These nops 2062 * are replaced with a conditional jump once do_fexit (i.e. the 2063 * start of the fexit invocation) is finalized. 2064 */ 2065 branches[i] = prog; 2066 emit_nops(&prog, 4 + 2); 2067 } 2068 2069 *pprog = prog; 2070 return 0; 2071 } 2072 2073 /* Example: 2074 * __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev); 2075 * its 'struct btf_func_model' will be nr_args=2 2076 * The assembly code when eth_type_trans is executing after trampoline: 2077 * 2078 * push rbp 2079 * mov rbp, rsp 2080 * sub rsp, 16 // space for skb and dev 2081 * push rbx // temp regs to pass start time 2082 * mov qword ptr [rbp - 16], rdi // save skb pointer to stack 2083 * mov qword ptr [rbp - 8], rsi // save dev pointer to stack 2084 * call __bpf_prog_enter // rcu_read_lock and preempt_disable 2085 * mov rbx, rax // remember start time in bpf stats are enabled 2086 * lea rdi, [rbp - 16] // R1==ctx of bpf prog 2087 * call addr_of_jited_FENTRY_prog 2088 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off 2089 * mov rsi, rbx // prog start time 2090 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math 2091 * mov rdi, qword ptr [rbp - 16] // restore skb pointer from stack 2092 * mov rsi, qword ptr [rbp - 8] // restore dev pointer from stack 2093 * pop rbx 2094 * leave 2095 * ret 2096 * 2097 * eth_type_trans has 5 byte nop at the beginning. These 5 bytes will be 2098 * replaced with 'call generated_bpf_trampoline'. When it returns 2099 * eth_type_trans will continue executing with original skb and dev pointers. 2100 * 2101 * The assembly code when eth_type_trans is called from trampoline: 2102 * 2103 * push rbp 2104 * mov rbp, rsp 2105 * sub rsp, 24 // space for skb, dev, return value 2106 * push rbx // temp regs to pass start time 2107 * mov qword ptr [rbp - 24], rdi // save skb pointer to stack 2108 * mov qword ptr [rbp - 16], rsi // save dev pointer to stack 2109 * call __bpf_prog_enter // rcu_read_lock and preempt_disable 2110 * mov rbx, rax // remember start time if bpf stats are enabled 2111 * lea rdi, [rbp - 24] // R1==ctx of bpf prog 2112 * call addr_of_jited_FENTRY_prog // bpf prog can access skb and dev 2113 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off 2114 * mov rsi, rbx // prog start time 2115 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math 2116 * mov rdi, qword ptr [rbp - 24] // restore skb pointer from stack 2117 * mov rsi, qword ptr [rbp - 16] // restore dev pointer from stack 2118 * call eth_type_trans+5 // execute body of eth_type_trans 2119 * mov qword ptr [rbp - 8], rax // save return value 2120 * call __bpf_prog_enter // rcu_read_lock and preempt_disable 2121 * mov rbx, rax // remember start time in bpf stats are enabled 2122 * lea rdi, [rbp - 24] // R1==ctx of bpf prog 2123 * call addr_of_jited_FEXIT_prog // bpf prog can access skb, dev, return value 2124 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off 2125 * mov rsi, rbx // prog start time 2126 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math 2127 * mov rax, qword ptr [rbp - 8] // restore eth_type_trans's return value 2128 * pop rbx 2129 * leave 2130 * add rsp, 8 // skip eth_type_trans's frame 2131 * ret // return to its caller 2132 */ 2133 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *image_end, 2134 const struct btf_func_model *m, u32 flags, 2135 struct bpf_tramp_links *tlinks, 2136 void *func_addr) 2137 { 2138 int i, ret, nr_regs = m->nr_args, stack_size = 0; 2139 int regs_off, nregs_off, ip_off, run_ctx_off; 2140 struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY]; 2141 struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT]; 2142 struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN]; 2143 void *orig_call = func_addr; 2144 u8 **branches = NULL; 2145 u8 *prog; 2146 bool save_ret; 2147 2148 /* extra registers for struct arguments */ 2149 for (i = 0; i < m->nr_args; i++) 2150 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG) 2151 nr_regs += (m->arg_size[i] + 7) / 8 - 1; 2152 2153 /* x86-64 supports up to 6 arguments. 7+ can be added in the future */ 2154 if (nr_regs > 6) 2155 return -ENOTSUPP; 2156 2157 /* Generated trampoline stack layout: 2158 * 2159 * RBP + 8 [ return address ] 2160 * RBP + 0 [ RBP ] 2161 * 2162 * RBP - 8 [ return value ] BPF_TRAMP_F_CALL_ORIG or 2163 * BPF_TRAMP_F_RET_FENTRY_RET flags 2164 * 2165 * [ reg_argN ] always 2166 * [ ... ] 2167 * RBP - regs_off [ reg_arg1 ] program's ctx pointer 2168 * 2169 * RBP - nregs_off [ regs count ] always 2170 * 2171 * RBP - ip_off [ traced function ] BPF_TRAMP_F_IP_ARG flag 2172 * 2173 * RBP - run_ctx_off [ bpf_tramp_run_ctx ] 2174 */ 2175 2176 /* room for return value of orig_call or fentry prog */ 2177 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET); 2178 if (save_ret) 2179 stack_size += 8; 2180 2181 stack_size += nr_regs * 8; 2182 regs_off = stack_size; 2183 2184 /* regs count */ 2185 stack_size += 8; 2186 nregs_off = stack_size; 2187 2188 if (flags & BPF_TRAMP_F_IP_ARG) 2189 stack_size += 8; /* room for IP address argument */ 2190 2191 ip_off = stack_size; 2192 2193 stack_size += (sizeof(struct bpf_tramp_run_ctx) + 7) & ~0x7; 2194 run_ctx_off = stack_size; 2195 2196 if (flags & BPF_TRAMP_F_SKIP_FRAME) { 2197 /* skip patched call instruction and point orig_call to actual 2198 * body of the kernel function. 2199 */ 2200 if (is_endbr(*(u32 *)orig_call)) 2201 orig_call += ENDBR_INSN_SIZE; 2202 orig_call += X86_PATCH_SIZE; 2203 } 2204 2205 prog = image; 2206 2207 EMIT_ENDBR(); 2208 /* 2209 * This is the direct-call trampoline, as such it needs accounting 2210 * for the __fentry__ call. 2211 */ 2212 x86_call_depth_emit_accounting(&prog, NULL); 2213 EMIT1(0x55); /* push rbp */ 2214 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */ 2215 EMIT4(0x48, 0x83, 0xEC, stack_size); /* sub rsp, stack_size */ 2216 EMIT1(0x53); /* push rbx */ 2217 2218 /* Store number of argument registers of the traced function: 2219 * mov rax, nr_regs 2220 * mov QWORD PTR [rbp - nregs_off], rax 2221 */ 2222 emit_mov_imm64(&prog, BPF_REG_0, 0, (u32) nr_regs); 2223 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -nregs_off); 2224 2225 if (flags & BPF_TRAMP_F_IP_ARG) { 2226 /* Store IP address of the traced function: 2227 * movabsq rax, func_addr 2228 * mov QWORD PTR [rbp - ip_off], rax 2229 */ 2230 emit_mov_imm64(&prog, BPF_REG_0, (long) func_addr >> 32, (u32) (long) func_addr); 2231 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -ip_off); 2232 } 2233 2234 save_regs(m, &prog, nr_regs, regs_off); 2235 2236 if (flags & BPF_TRAMP_F_CALL_ORIG) { 2237 /* arg1: mov rdi, im */ 2238 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im); 2239 if (emit_rsb_call(&prog, __bpf_tramp_enter, prog)) { 2240 ret = -EINVAL; 2241 goto cleanup; 2242 } 2243 } 2244 2245 if (fentry->nr_links) 2246 if (invoke_bpf(m, &prog, fentry, regs_off, run_ctx_off, 2247 flags & BPF_TRAMP_F_RET_FENTRY_RET)) 2248 return -EINVAL; 2249 2250 if (fmod_ret->nr_links) { 2251 branches = kcalloc(fmod_ret->nr_links, sizeof(u8 *), 2252 GFP_KERNEL); 2253 if (!branches) 2254 return -ENOMEM; 2255 2256 if (invoke_bpf_mod_ret(m, &prog, fmod_ret, regs_off, 2257 run_ctx_off, branches)) { 2258 ret = -EINVAL; 2259 goto cleanup; 2260 } 2261 } 2262 2263 if (flags & BPF_TRAMP_F_CALL_ORIG) { 2264 restore_regs(m, &prog, nr_regs, regs_off); 2265 2266 if (flags & BPF_TRAMP_F_ORIG_STACK) { 2267 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, 8); 2268 EMIT2(0xff, 0xd0); /* call *rax */ 2269 } else { 2270 /* call original function */ 2271 if (emit_rsb_call(&prog, orig_call, prog)) { 2272 ret = -EINVAL; 2273 goto cleanup; 2274 } 2275 } 2276 /* remember return value in a stack for bpf prog to access */ 2277 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); 2278 im->ip_after_call = prog; 2279 memcpy(prog, x86_nops[5], X86_PATCH_SIZE); 2280 prog += X86_PATCH_SIZE; 2281 } 2282 2283 if (fmod_ret->nr_links) { 2284 /* From Intel 64 and IA-32 Architectures Optimization 2285 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler 2286 * Coding Rule 11: All branch targets should be 16-byte 2287 * aligned. 2288 */ 2289 emit_align(&prog, 16); 2290 /* Update the branches saved in invoke_bpf_mod_ret with the 2291 * aligned address of do_fexit. 2292 */ 2293 for (i = 0; i < fmod_ret->nr_links; i++) 2294 emit_cond_near_jump(&branches[i], prog, branches[i], 2295 X86_JNE); 2296 } 2297 2298 if (fexit->nr_links) 2299 if (invoke_bpf(m, &prog, fexit, regs_off, run_ctx_off, false)) { 2300 ret = -EINVAL; 2301 goto cleanup; 2302 } 2303 2304 if (flags & BPF_TRAMP_F_RESTORE_REGS) 2305 restore_regs(m, &prog, nr_regs, regs_off); 2306 2307 /* This needs to be done regardless. If there were fmod_ret programs, 2308 * the return value is only updated on the stack and still needs to be 2309 * restored to R0. 2310 */ 2311 if (flags & BPF_TRAMP_F_CALL_ORIG) { 2312 im->ip_epilogue = prog; 2313 /* arg1: mov rdi, im */ 2314 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im); 2315 if (emit_rsb_call(&prog, __bpf_tramp_exit, prog)) { 2316 ret = -EINVAL; 2317 goto cleanup; 2318 } 2319 } 2320 /* restore return value of orig_call or fentry prog back into RAX */ 2321 if (save_ret) 2322 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, -8); 2323 2324 EMIT1(0x5B); /* pop rbx */ 2325 EMIT1(0xC9); /* leave */ 2326 if (flags & BPF_TRAMP_F_SKIP_FRAME) 2327 /* skip our return address and return to parent */ 2328 EMIT4(0x48, 0x83, 0xC4, 8); /* add rsp, 8 */ 2329 emit_return(&prog, prog); 2330 /* Make sure the trampoline generation logic doesn't overflow */ 2331 if (WARN_ON_ONCE(prog > (u8 *)image_end - BPF_INSN_SAFETY)) { 2332 ret = -EFAULT; 2333 goto cleanup; 2334 } 2335 ret = prog - (u8 *)image; 2336 2337 cleanup: 2338 kfree(branches); 2339 return ret; 2340 } 2341 2342 static int emit_bpf_dispatcher(u8 **pprog, int a, int b, s64 *progs, u8 *image, u8 *buf) 2343 { 2344 u8 *jg_reloc, *prog = *pprog; 2345 int pivot, err, jg_bytes = 1; 2346 s64 jg_offset; 2347 2348 if (a == b) { 2349 /* Leaf node of recursion, i.e. not a range of indices 2350 * anymore. 2351 */ 2352 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */ 2353 if (!is_simm32(progs[a])) 2354 return -1; 2355 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), 2356 progs[a]); 2357 err = emit_cond_near_jump(&prog, /* je func */ 2358 (void *)progs[a], image + (prog - buf), 2359 X86_JE); 2360 if (err) 2361 return err; 2362 2363 emit_indirect_jump(&prog, 2 /* rdx */, image + (prog - buf)); 2364 2365 *pprog = prog; 2366 return 0; 2367 } 2368 2369 /* Not a leaf node, so we pivot, and recursively descend into 2370 * the lower and upper ranges. 2371 */ 2372 pivot = (b - a) / 2; 2373 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */ 2374 if (!is_simm32(progs[a + pivot])) 2375 return -1; 2376 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]); 2377 2378 if (pivot > 2) { /* jg upper_part */ 2379 /* Require near jump. */ 2380 jg_bytes = 4; 2381 EMIT2_off32(0x0F, X86_JG + 0x10, 0); 2382 } else { 2383 EMIT2(X86_JG, 0); 2384 } 2385 jg_reloc = prog; 2386 2387 err = emit_bpf_dispatcher(&prog, a, a + pivot, /* emit lower_part */ 2388 progs, image, buf); 2389 if (err) 2390 return err; 2391 2392 /* From Intel 64 and IA-32 Architectures Optimization 2393 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler 2394 * Coding Rule 11: All branch targets should be 16-byte 2395 * aligned. 2396 */ 2397 emit_align(&prog, 16); 2398 jg_offset = prog - jg_reloc; 2399 emit_code(jg_reloc - jg_bytes, jg_offset, jg_bytes); 2400 2401 err = emit_bpf_dispatcher(&prog, a + pivot + 1, /* emit upper_part */ 2402 b, progs, image, buf); 2403 if (err) 2404 return err; 2405 2406 *pprog = prog; 2407 return 0; 2408 } 2409 2410 static int cmp_ips(const void *a, const void *b) 2411 { 2412 const s64 *ipa = a; 2413 const s64 *ipb = b; 2414 2415 if (*ipa > *ipb) 2416 return 1; 2417 if (*ipa < *ipb) 2418 return -1; 2419 return 0; 2420 } 2421 2422 int arch_prepare_bpf_dispatcher(void *image, void *buf, s64 *funcs, int num_funcs) 2423 { 2424 u8 *prog = buf; 2425 2426 sort(funcs, num_funcs, sizeof(funcs[0]), cmp_ips, NULL); 2427 return emit_bpf_dispatcher(&prog, 0, num_funcs - 1, funcs, image, buf); 2428 } 2429 2430 struct x64_jit_data { 2431 struct bpf_binary_header *rw_header; 2432 struct bpf_binary_header *header; 2433 int *addrs; 2434 u8 *image; 2435 int proglen; 2436 struct jit_context ctx; 2437 }; 2438 2439 #define MAX_PASSES 20 2440 #define PADDING_PASSES (MAX_PASSES - 5) 2441 2442 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog) 2443 { 2444 struct bpf_binary_header *rw_header = NULL; 2445 struct bpf_binary_header *header = NULL; 2446 struct bpf_prog *tmp, *orig_prog = prog; 2447 struct x64_jit_data *jit_data; 2448 int proglen, oldproglen = 0; 2449 struct jit_context ctx = {}; 2450 bool tmp_blinded = false; 2451 bool extra_pass = false; 2452 bool padding = false; 2453 u8 *rw_image = NULL; 2454 u8 *image = NULL; 2455 int *addrs; 2456 int pass; 2457 int i; 2458 2459 if (!prog->jit_requested) 2460 return orig_prog; 2461 2462 tmp = bpf_jit_blind_constants(prog); 2463 /* 2464 * If blinding was requested and we failed during blinding, 2465 * we must fall back to the interpreter. 2466 */ 2467 if (IS_ERR(tmp)) 2468 return orig_prog; 2469 if (tmp != prog) { 2470 tmp_blinded = true; 2471 prog = tmp; 2472 } 2473 2474 jit_data = prog->aux->jit_data; 2475 if (!jit_data) { 2476 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL); 2477 if (!jit_data) { 2478 prog = orig_prog; 2479 goto out; 2480 } 2481 prog->aux->jit_data = jit_data; 2482 } 2483 addrs = jit_data->addrs; 2484 if (addrs) { 2485 ctx = jit_data->ctx; 2486 oldproglen = jit_data->proglen; 2487 image = jit_data->image; 2488 header = jit_data->header; 2489 rw_header = jit_data->rw_header; 2490 rw_image = (void *)rw_header + ((void *)image - (void *)header); 2491 extra_pass = true; 2492 padding = true; 2493 goto skip_init_addrs; 2494 } 2495 addrs = kvmalloc_array(prog->len + 1, sizeof(*addrs), GFP_KERNEL); 2496 if (!addrs) { 2497 prog = orig_prog; 2498 goto out_addrs; 2499 } 2500 2501 /* 2502 * Before first pass, make a rough estimation of addrs[] 2503 * each BPF instruction is translated to less than 64 bytes 2504 */ 2505 for (proglen = 0, i = 0; i <= prog->len; i++) { 2506 proglen += 64; 2507 addrs[i] = proglen; 2508 } 2509 ctx.cleanup_addr = proglen; 2510 skip_init_addrs: 2511 2512 /* 2513 * JITed image shrinks with every pass and the loop iterates 2514 * until the image stops shrinking. Very large BPF programs 2515 * may converge on the last pass. In such case do one more 2516 * pass to emit the final image. 2517 */ 2518 for (pass = 0; pass < MAX_PASSES || image; pass++) { 2519 if (!padding && pass >= PADDING_PASSES) 2520 padding = true; 2521 proglen = do_jit(prog, addrs, image, rw_image, oldproglen, &ctx, padding); 2522 if (proglen <= 0) { 2523 out_image: 2524 image = NULL; 2525 if (header) { 2526 bpf_arch_text_copy(&header->size, &rw_header->size, 2527 sizeof(rw_header->size)); 2528 bpf_jit_binary_pack_free(header, rw_header); 2529 } 2530 /* Fall back to interpreter mode */ 2531 prog = orig_prog; 2532 if (extra_pass) { 2533 prog->bpf_func = NULL; 2534 prog->jited = 0; 2535 prog->jited_len = 0; 2536 } 2537 goto out_addrs; 2538 } 2539 if (image) { 2540 if (proglen != oldproglen) { 2541 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n", 2542 proglen, oldproglen); 2543 goto out_image; 2544 } 2545 break; 2546 } 2547 if (proglen == oldproglen) { 2548 /* 2549 * The number of entries in extable is the number of BPF_LDX 2550 * insns that access kernel memory via "pointer to BTF type". 2551 * The verifier changed their opcode from LDX|MEM|size 2552 * to LDX|PROBE_MEM|size to make JITing easier. 2553 */ 2554 u32 align = __alignof__(struct exception_table_entry); 2555 u32 extable_size = prog->aux->num_exentries * 2556 sizeof(struct exception_table_entry); 2557 2558 /* allocate module memory for x86 insns and extable */ 2559 header = bpf_jit_binary_pack_alloc(roundup(proglen, align) + extable_size, 2560 &image, align, &rw_header, &rw_image, 2561 jit_fill_hole); 2562 if (!header) { 2563 prog = orig_prog; 2564 goto out_addrs; 2565 } 2566 prog->aux->extable = (void *) image + roundup(proglen, align); 2567 } 2568 oldproglen = proglen; 2569 cond_resched(); 2570 } 2571 2572 if (bpf_jit_enable > 1) 2573 bpf_jit_dump(prog->len, proglen, pass + 1, rw_image); 2574 2575 if (image) { 2576 if (!prog->is_func || extra_pass) { 2577 /* 2578 * bpf_jit_binary_pack_finalize fails in two scenarios: 2579 * 1) header is not pointing to proper module memory; 2580 * 2) the arch doesn't support bpf_arch_text_copy(). 2581 * 2582 * Both cases are serious bugs and justify WARN_ON. 2583 */ 2584 if (WARN_ON(bpf_jit_binary_pack_finalize(prog, header, rw_header))) { 2585 /* header has been freed */ 2586 header = NULL; 2587 goto out_image; 2588 } 2589 2590 bpf_tail_call_direct_fixup(prog); 2591 } else { 2592 jit_data->addrs = addrs; 2593 jit_data->ctx = ctx; 2594 jit_data->proglen = proglen; 2595 jit_data->image = image; 2596 jit_data->header = header; 2597 jit_data->rw_header = rw_header; 2598 } 2599 prog->bpf_func = (void *)image; 2600 prog->jited = 1; 2601 prog->jited_len = proglen; 2602 } else { 2603 prog = orig_prog; 2604 } 2605 2606 if (!image || !prog->is_func || extra_pass) { 2607 if (image) 2608 bpf_prog_fill_jited_linfo(prog, addrs + 1); 2609 out_addrs: 2610 kvfree(addrs); 2611 kfree(jit_data); 2612 prog->aux->jit_data = NULL; 2613 } 2614 out: 2615 if (tmp_blinded) 2616 bpf_jit_prog_release_other(prog, prog == orig_prog ? 2617 tmp : orig_prog); 2618 return prog; 2619 } 2620 2621 bool bpf_jit_supports_kfunc_call(void) 2622 { 2623 return true; 2624 } 2625 2626 void *bpf_arch_text_copy(void *dst, void *src, size_t len) 2627 { 2628 if (text_poke_copy(dst, src, len) == NULL) 2629 return ERR_PTR(-EINVAL); 2630 return dst; 2631 } 2632 2633 /* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */ 2634 bool bpf_jit_supports_subprog_tailcalls(void) 2635 { 2636 return true; 2637 } 2638 2639 void bpf_jit_free(struct bpf_prog *prog) 2640 { 2641 if (prog->jited) { 2642 struct x64_jit_data *jit_data = prog->aux->jit_data; 2643 struct bpf_binary_header *hdr; 2644 2645 /* 2646 * If we fail the final pass of JIT (from jit_subprogs), 2647 * the program may not be finalized yet. Call finalize here 2648 * before freeing it. 2649 */ 2650 if (jit_data) { 2651 bpf_jit_binary_pack_finalize(prog, jit_data->header, 2652 jit_data->rw_header); 2653 kvfree(jit_data->addrs); 2654 kfree(jit_data); 2655 } 2656 hdr = bpf_jit_binary_pack_hdr(prog); 2657 bpf_jit_binary_pack_free(hdr, NULL); 2658 WARN_ON_ONCE(!bpf_prog_kallsyms_verify_off(prog)); 2659 } 2660 2661 bpf_prog_unlock_free(prog); 2662 } 2663