1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * BPF JIT compiler 4 * 5 * Copyright (C) 2011-2013 Eric Dumazet (eric.dumazet@gmail.com) 6 * Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com 7 */ 8 #include <linux/netdevice.h> 9 #include <linux/filter.h> 10 #include <linux/if_vlan.h> 11 #include <linux/bpf.h> 12 #include <linux/memory.h> 13 #include <linux/sort.h> 14 #include <asm/extable.h> 15 #include <asm/ftrace.h> 16 #include <asm/set_memory.h> 17 #include <asm/nospec-branch.h> 18 #include <asm/text-patching.h> 19 20 static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len) 21 { 22 if (len == 1) 23 *ptr = bytes; 24 else if (len == 2) 25 *(u16 *)ptr = bytes; 26 else { 27 *(u32 *)ptr = bytes; 28 barrier(); 29 } 30 return ptr + len; 31 } 32 33 #define EMIT(bytes, len) \ 34 do { prog = emit_code(prog, bytes, len); } while (0) 35 36 #define EMIT1(b1) EMIT(b1, 1) 37 #define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2) 38 #define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3) 39 #define EMIT4(b1, b2, b3, b4) EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4) 40 41 #define EMIT1_off32(b1, off) \ 42 do { EMIT1(b1); EMIT(off, 4); } while (0) 43 #define EMIT2_off32(b1, b2, off) \ 44 do { EMIT2(b1, b2); EMIT(off, 4); } while (0) 45 #define EMIT3_off32(b1, b2, b3, off) \ 46 do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0) 47 #define EMIT4_off32(b1, b2, b3, b4, off) \ 48 do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0) 49 50 #ifdef CONFIG_X86_KERNEL_IBT 51 #define EMIT_ENDBR() EMIT(gen_endbr(), 4) 52 #else 53 #define EMIT_ENDBR() 54 #endif 55 56 static bool is_imm8(int value) 57 { 58 return value <= 127 && value >= -128; 59 } 60 61 static bool is_simm32(s64 value) 62 { 63 return value == (s64)(s32)value; 64 } 65 66 static bool is_uimm32(u64 value) 67 { 68 return value == (u64)(u32)value; 69 } 70 71 /* mov dst, src */ 72 #define EMIT_mov(DST, SRC) \ 73 do { \ 74 if (DST != SRC) \ 75 EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \ 76 } while (0) 77 78 static int bpf_size_to_x86_bytes(int bpf_size) 79 { 80 if (bpf_size == BPF_W) 81 return 4; 82 else if (bpf_size == BPF_H) 83 return 2; 84 else if (bpf_size == BPF_B) 85 return 1; 86 else if (bpf_size == BPF_DW) 87 return 4; /* imm32 */ 88 else 89 return 0; 90 } 91 92 /* 93 * List of x86 cond jumps opcodes (. + s8) 94 * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32) 95 */ 96 #define X86_JB 0x72 97 #define X86_JAE 0x73 98 #define X86_JE 0x74 99 #define X86_JNE 0x75 100 #define X86_JBE 0x76 101 #define X86_JA 0x77 102 #define X86_JL 0x7C 103 #define X86_JGE 0x7D 104 #define X86_JLE 0x7E 105 #define X86_JG 0x7F 106 107 /* Pick a register outside of BPF range for JIT internal work */ 108 #define AUX_REG (MAX_BPF_JIT_REG + 1) 109 #define X86_REG_R9 (MAX_BPF_JIT_REG + 2) 110 111 /* 112 * The following table maps BPF registers to x86-64 registers. 113 * 114 * x86-64 register R12 is unused, since if used as base address 115 * register in load/store instructions, it always needs an 116 * extra byte of encoding and is callee saved. 117 * 118 * x86-64 register R9 is not used by BPF programs, but can be used by BPF 119 * trampoline. x86-64 register R10 is used for blinding (if enabled). 120 */ 121 static const int reg2hex[] = { 122 [BPF_REG_0] = 0, /* RAX */ 123 [BPF_REG_1] = 7, /* RDI */ 124 [BPF_REG_2] = 6, /* RSI */ 125 [BPF_REG_3] = 2, /* RDX */ 126 [BPF_REG_4] = 1, /* RCX */ 127 [BPF_REG_5] = 0, /* R8 */ 128 [BPF_REG_6] = 3, /* RBX callee saved */ 129 [BPF_REG_7] = 5, /* R13 callee saved */ 130 [BPF_REG_8] = 6, /* R14 callee saved */ 131 [BPF_REG_9] = 7, /* R15 callee saved */ 132 [BPF_REG_FP] = 5, /* RBP readonly */ 133 [BPF_REG_AX] = 2, /* R10 temp register */ 134 [AUX_REG] = 3, /* R11 temp register */ 135 [X86_REG_R9] = 1, /* R9 register, 6th function argument */ 136 }; 137 138 static const int reg2pt_regs[] = { 139 [BPF_REG_0] = offsetof(struct pt_regs, ax), 140 [BPF_REG_1] = offsetof(struct pt_regs, di), 141 [BPF_REG_2] = offsetof(struct pt_regs, si), 142 [BPF_REG_3] = offsetof(struct pt_regs, dx), 143 [BPF_REG_4] = offsetof(struct pt_regs, cx), 144 [BPF_REG_5] = offsetof(struct pt_regs, r8), 145 [BPF_REG_6] = offsetof(struct pt_regs, bx), 146 [BPF_REG_7] = offsetof(struct pt_regs, r13), 147 [BPF_REG_8] = offsetof(struct pt_regs, r14), 148 [BPF_REG_9] = offsetof(struct pt_regs, r15), 149 }; 150 151 /* 152 * is_ereg() == true if BPF register 'reg' maps to x86-64 r8..r15 153 * which need extra byte of encoding. 154 * rax,rcx,...,rbp have simpler encoding 155 */ 156 static bool is_ereg(u32 reg) 157 { 158 return (1 << reg) & (BIT(BPF_REG_5) | 159 BIT(AUX_REG) | 160 BIT(BPF_REG_7) | 161 BIT(BPF_REG_8) | 162 BIT(BPF_REG_9) | 163 BIT(X86_REG_R9) | 164 BIT(BPF_REG_AX)); 165 } 166 167 /* 168 * is_ereg_8l() == true if BPF register 'reg' is mapped to access x86-64 169 * lower 8-bit registers dil,sil,bpl,spl,r8b..r15b, which need extra byte 170 * of encoding. al,cl,dl,bl have simpler encoding. 171 */ 172 static bool is_ereg_8l(u32 reg) 173 { 174 return is_ereg(reg) || 175 (1 << reg) & (BIT(BPF_REG_1) | 176 BIT(BPF_REG_2) | 177 BIT(BPF_REG_FP)); 178 } 179 180 static bool is_axreg(u32 reg) 181 { 182 return reg == BPF_REG_0; 183 } 184 185 /* Add modifiers if 'reg' maps to x86-64 registers R8..R15 */ 186 static u8 add_1mod(u8 byte, u32 reg) 187 { 188 if (is_ereg(reg)) 189 byte |= 1; 190 return byte; 191 } 192 193 static u8 add_2mod(u8 byte, u32 r1, u32 r2) 194 { 195 if (is_ereg(r1)) 196 byte |= 1; 197 if (is_ereg(r2)) 198 byte |= 4; 199 return byte; 200 } 201 202 /* Encode 'dst_reg' register into x86-64 opcode 'byte' */ 203 static u8 add_1reg(u8 byte, u32 dst_reg) 204 { 205 return byte + reg2hex[dst_reg]; 206 } 207 208 /* Encode 'dst_reg' and 'src_reg' registers into x86-64 opcode 'byte' */ 209 static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg) 210 { 211 return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3); 212 } 213 214 /* Some 1-byte opcodes for binary ALU operations */ 215 static u8 simple_alu_opcodes[] = { 216 [BPF_ADD] = 0x01, 217 [BPF_SUB] = 0x29, 218 [BPF_AND] = 0x21, 219 [BPF_OR] = 0x09, 220 [BPF_XOR] = 0x31, 221 [BPF_LSH] = 0xE0, 222 [BPF_RSH] = 0xE8, 223 [BPF_ARSH] = 0xF8, 224 }; 225 226 static void jit_fill_hole(void *area, unsigned int size) 227 { 228 /* Fill whole space with INT3 instructions */ 229 memset(area, 0xcc, size); 230 } 231 232 int bpf_arch_text_invalidate(void *dst, size_t len) 233 { 234 return IS_ERR_OR_NULL(text_poke_set(dst, 0xcc, len)); 235 } 236 237 struct jit_context { 238 int cleanup_addr; /* Epilogue code offset */ 239 240 /* 241 * Program specific offsets of labels in the code; these rely on the 242 * JIT doing at least 2 passes, recording the position on the first 243 * pass, only to generate the correct offset on the second pass. 244 */ 245 int tail_call_direct_label; 246 int tail_call_indirect_label; 247 }; 248 249 /* Maximum number of bytes emitted while JITing one eBPF insn */ 250 #define BPF_MAX_INSN_SIZE 128 251 #define BPF_INSN_SAFETY 64 252 253 /* Number of bytes emit_patch() needs to generate instructions */ 254 #define X86_PATCH_SIZE 5 255 /* Number of bytes that will be skipped on tailcall */ 256 #define X86_TAIL_CALL_OFFSET (11 + ENDBR_INSN_SIZE) 257 258 static void push_callee_regs(u8 **pprog, bool *callee_regs_used) 259 { 260 u8 *prog = *pprog; 261 262 if (callee_regs_used[0]) 263 EMIT1(0x53); /* push rbx */ 264 if (callee_regs_used[1]) 265 EMIT2(0x41, 0x55); /* push r13 */ 266 if (callee_regs_used[2]) 267 EMIT2(0x41, 0x56); /* push r14 */ 268 if (callee_regs_used[3]) 269 EMIT2(0x41, 0x57); /* push r15 */ 270 *pprog = prog; 271 } 272 273 static void pop_callee_regs(u8 **pprog, bool *callee_regs_used) 274 { 275 u8 *prog = *pprog; 276 277 if (callee_regs_used[3]) 278 EMIT2(0x41, 0x5F); /* pop r15 */ 279 if (callee_regs_used[2]) 280 EMIT2(0x41, 0x5E); /* pop r14 */ 281 if (callee_regs_used[1]) 282 EMIT2(0x41, 0x5D); /* pop r13 */ 283 if (callee_regs_used[0]) 284 EMIT1(0x5B); /* pop rbx */ 285 *pprog = prog; 286 } 287 288 /* 289 * Emit x86-64 prologue code for BPF program. 290 * bpf_tail_call helper will skip the first X86_TAIL_CALL_OFFSET bytes 291 * while jumping to another program 292 */ 293 static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf, 294 bool tail_call_reachable, bool is_subprog) 295 { 296 u8 *prog = *pprog; 297 298 /* BPF trampoline can be made to work without these nops, 299 * but let's waste 5 bytes for now and optimize later 300 */ 301 EMIT_ENDBR(); 302 memcpy(prog, x86_nops[5], X86_PATCH_SIZE); 303 prog += X86_PATCH_SIZE; 304 if (!ebpf_from_cbpf) { 305 if (tail_call_reachable && !is_subprog) 306 EMIT2(0x31, 0xC0); /* xor eax, eax */ 307 else 308 EMIT2(0x66, 0x90); /* nop2 */ 309 } 310 EMIT1(0x55); /* push rbp */ 311 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */ 312 313 /* X86_TAIL_CALL_OFFSET is here */ 314 EMIT_ENDBR(); 315 316 /* sub rsp, rounded_stack_depth */ 317 if (stack_depth) 318 EMIT3_off32(0x48, 0x81, 0xEC, round_up(stack_depth, 8)); 319 if (tail_call_reachable) 320 EMIT1(0x50); /* push rax */ 321 *pprog = prog; 322 } 323 324 static int emit_patch(u8 **pprog, void *func, void *ip, u8 opcode) 325 { 326 u8 *prog = *pprog; 327 s64 offset; 328 329 offset = func - (ip + X86_PATCH_SIZE); 330 if (!is_simm32(offset)) { 331 pr_err("Target call %p is out of range\n", func); 332 return -ERANGE; 333 } 334 EMIT1_off32(opcode, offset); 335 *pprog = prog; 336 return 0; 337 } 338 339 static int emit_call(u8 **pprog, void *func, void *ip) 340 { 341 return emit_patch(pprog, func, ip, 0xE8); 342 } 343 344 static int emit_rsb_call(u8 **pprog, void *func, void *ip) 345 { 346 OPTIMIZER_HIDE_VAR(func); 347 x86_call_depth_emit_accounting(pprog, func); 348 return emit_patch(pprog, func, ip, 0xE8); 349 } 350 351 static int emit_jump(u8 **pprog, void *func, void *ip) 352 { 353 return emit_patch(pprog, func, ip, 0xE9); 354 } 355 356 static int __bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t, 357 void *old_addr, void *new_addr) 358 { 359 const u8 *nop_insn = x86_nops[5]; 360 u8 old_insn[X86_PATCH_SIZE]; 361 u8 new_insn[X86_PATCH_SIZE]; 362 u8 *prog; 363 int ret; 364 365 memcpy(old_insn, nop_insn, X86_PATCH_SIZE); 366 if (old_addr) { 367 prog = old_insn; 368 ret = t == BPF_MOD_CALL ? 369 emit_call(&prog, old_addr, ip) : 370 emit_jump(&prog, old_addr, ip); 371 if (ret) 372 return ret; 373 } 374 375 memcpy(new_insn, nop_insn, X86_PATCH_SIZE); 376 if (new_addr) { 377 prog = new_insn; 378 ret = t == BPF_MOD_CALL ? 379 emit_call(&prog, new_addr, ip) : 380 emit_jump(&prog, new_addr, ip); 381 if (ret) 382 return ret; 383 } 384 385 ret = -EBUSY; 386 mutex_lock(&text_mutex); 387 if (memcmp(ip, old_insn, X86_PATCH_SIZE)) 388 goto out; 389 ret = 1; 390 if (memcmp(ip, new_insn, X86_PATCH_SIZE)) { 391 text_poke_bp(ip, new_insn, X86_PATCH_SIZE, NULL); 392 ret = 0; 393 } 394 out: 395 mutex_unlock(&text_mutex); 396 return ret; 397 } 398 399 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t, 400 void *old_addr, void *new_addr) 401 { 402 if (!is_kernel_text((long)ip) && 403 !is_bpf_text_address((long)ip)) 404 /* BPF poking in modules is not supported */ 405 return -EINVAL; 406 407 /* 408 * See emit_prologue(), for IBT builds the trampoline hook is preceded 409 * with an ENDBR instruction. 410 */ 411 if (is_endbr(*(u32 *)ip)) 412 ip += ENDBR_INSN_SIZE; 413 414 return __bpf_arch_text_poke(ip, t, old_addr, new_addr); 415 } 416 417 #define EMIT_LFENCE() EMIT3(0x0F, 0xAE, 0xE8) 418 419 static void emit_indirect_jump(u8 **pprog, int reg, u8 *ip) 420 { 421 u8 *prog = *pprog; 422 423 if (cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) { 424 EMIT_LFENCE(); 425 EMIT2(0xFF, 0xE0 + reg); 426 } else if (cpu_feature_enabled(X86_FEATURE_RETPOLINE)) { 427 OPTIMIZER_HIDE_VAR(reg); 428 if (cpu_feature_enabled(X86_FEATURE_CALL_DEPTH)) 429 emit_jump(&prog, &__x86_indirect_jump_thunk_array[reg], ip); 430 else 431 emit_jump(&prog, &__x86_indirect_thunk_array[reg], ip); 432 } else { 433 EMIT2(0xFF, 0xE0 + reg); /* jmp *%\reg */ 434 if (IS_ENABLED(CONFIG_RETPOLINE) || IS_ENABLED(CONFIG_SLS)) 435 EMIT1(0xCC); /* int3 */ 436 } 437 438 *pprog = prog; 439 } 440 441 static void emit_return(u8 **pprog, u8 *ip) 442 { 443 u8 *prog = *pprog; 444 445 if (cpu_feature_enabled(X86_FEATURE_RETHUNK)) { 446 emit_jump(&prog, x86_return_thunk, ip); 447 } else { 448 EMIT1(0xC3); /* ret */ 449 if (IS_ENABLED(CONFIG_SLS)) 450 EMIT1(0xCC); /* int3 */ 451 } 452 453 *pprog = prog; 454 } 455 456 /* 457 * Generate the following code: 458 * 459 * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ... 460 * if (index >= array->map.max_entries) 461 * goto out; 462 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT) 463 * goto out; 464 * prog = array->ptrs[index]; 465 * if (prog == NULL) 466 * goto out; 467 * goto *(prog->bpf_func + prologue_size); 468 * out: 469 */ 470 static void emit_bpf_tail_call_indirect(u8 **pprog, bool *callee_regs_used, 471 u32 stack_depth, u8 *ip, 472 struct jit_context *ctx) 473 { 474 int tcc_off = -4 - round_up(stack_depth, 8); 475 u8 *prog = *pprog, *start = *pprog; 476 int offset; 477 478 /* 479 * rdi - pointer to ctx 480 * rsi - pointer to bpf_array 481 * rdx - index in bpf_array 482 */ 483 484 /* 485 * if (index >= array->map.max_entries) 486 * goto out; 487 */ 488 EMIT2(0x89, 0xD2); /* mov edx, edx */ 489 EMIT3(0x39, 0x56, /* cmp dword ptr [rsi + 16], edx */ 490 offsetof(struct bpf_array, map.max_entries)); 491 492 offset = ctx->tail_call_indirect_label - (prog + 2 - start); 493 EMIT2(X86_JBE, offset); /* jbe out */ 494 495 /* 496 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT) 497 * goto out; 498 */ 499 EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */ 500 EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */ 501 502 offset = ctx->tail_call_indirect_label - (prog + 2 - start); 503 EMIT2(X86_JAE, offset); /* jae out */ 504 EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */ 505 EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */ 506 507 /* prog = array->ptrs[index]; */ 508 EMIT4_off32(0x48, 0x8B, 0x8C, 0xD6, /* mov rcx, [rsi + rdx * 8 + offsetof(...)] */ 509 offsetof(struct bpf_array, ptrs)); 510 511 /* 512 * if (prog == NULL) 513 * goto out; 514 */ 515 EMIT3(0x48, 0x85, 0xC9); /* test rcx,rcx */ 516 517 offset = ctx->tail_call_indirect_label - (prog + 2 - start); 518 EMIT2(X86_JE, offset); /* je out */ 519 520 pop_callee_regs(&prog, callee_regs_used); 521 522 EMIT1(0x58); /* pop rax */ 523 if (stack_depth) 524 EMIT3_off32(0x48, 0x81, 0xC4, /* add rsp, sd */ 525 round_up(stack_depth, 8)); 526 527 /* goto *(prog->bpf_func + X86_TAIL_CALL_OFFSET); */ 528 EMIT4(0x48, 0x8B, 0x49, /* mov rcx, qword ptr [rcx + 32] */ 529 offsetof(struct bpf_prog, bpf_func)); 530 EMIT4(0x48, 0x83, 0xC1, /* add rcx, X86_TAIL_CALL_OFFSET */ 531 X86_TAIL_CALL_OFFSET); 532 /* 533 * Now we're ready to jump into next BPF program 534 * rdi == ctx (1st arg) 535 * rcx == prog->bpf_func + X86_TAIL_CALL_OFFSET 536 */ 537 emit_indirect_jump(&prog, 1 /* rcx */, ip + (prog - start)); 538 539 /* out: */ 540 ctx->tail_call_indirect_label = prog - start; 541 *pprog = prog; 542 } 543 544 static void emit_bpf_tail_call_direct(struct bpf_jit_poke_descriptor *poke, 545 u8 **pprog, u8 *ip, 546 bool *callee_regs_used, u32 stack_depth, 547 struct jit_context *ctx) 548 { 549 int tcc_off = -4 - round_up(stack_depth, 8); 550 u8 *prog = *pprog, *start = *pprog; 551 int offset; 552 553 /* 554 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT) 555 * goto out; 556 */ 557 EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */ 558 EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */ 559 560 offset = ctx->tail_call_direct_label - (prog + 2 - start); 561 EMIT2(X86_JAE, offset); /* jae out */ 562 EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */ 563 EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */ 564 565 poke->tailcall_bypass = ip + (prog - start); 566 poke->adj_off = X86_TAIL_CALL_OFFSET; 567 poke->tailcall_target = ip + ctx->tail_call_direct_label - X86_PATCH_SIZE; 568 poke->bypass_addr = (u8 *)poke->tailcall_target + X86_PATCH_SIZE; 569 570 emit_jump(&prog, (u8 *)poke->tailcall_target + X86_PATCH_SIZE, 571 poke->tailcall_bypass); 572 573 pop_callee_regs(&prog, callee_regs_used); 574 EMIT1(0x58); /* pop rax */ 575 if (stack_depth) 576 EMIT3_off32(0x48, 0x81, 0xC4, round_up(stack_depth, 8)); 577 578 memcpy(prog, x86_nops[5], X86_PATCH_SIZE); 579 prog += X86_PATCH_SIZE; 580 581 /* out: */ 582 ctx->tail_call_direct_label = prog - start; 583 584 *pprog = prog; 585 } 586 587 static void bpf_tail_call_direct_fixup(struct bpf_prog *prog) 588 { 589 struct bpf_jit_poke_descriptor *poke; 590 struct bpf_array *array; 591 struct bpf_prog *target; 592 int i, ret; 593 594 for (i = 0; i < prog->aux->size_poke_tab; i++) { 595 poke = &prog->aux->poke_tab[i]; 596 if (poke->aux && poke->aux != prog->aux) 597 continue; 598 599 WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable)); 600 601 if (poke->reason != BPF_POKE_REASON_TAIL_CALL) 602 continue; 603 604 array = container_of(poke->tail_call.map, struct bpf_array, map); 605 mutex_lock(&array->aux->poke_mutex); 606 target = array->ptrs[poke->tail_call.key]; 607 if (target) { 608 ret = __bpf_arch_text_poke(poke->tailcall_target, 609 BPF_MOD_JUMP, NULL, 610 (u8 *)target->bpf_func + 611 poke->adj_off); 612 BUG_ON(ret < 0); 613 ret = __bpf_arch_text_poke(poke->tailcall_bypass, 614 BPF_MOD_JUMP, 615 (u8 *)poke->tailcall_target + 616 X86_PATCH_SIZE, NULL); 617 BUG_ON(ret < 0); 618 } 619 WRITE_ONCE(poke->tailcall_target_stable, true); 620 mutex_unlock(&array->aux->poke_mutex); 621 } 622 } 623 624 static void emit_mov_imm32(u8 **pprog, bool sign_propagate, 625 u32 dst_reg, const u32 imm32) 626 { 627 u8 *prog = *pprog; 628 u8 b1, b2, b3; 629 630 /* 631 * Optimization: if imm32 is positive, use 'mov %eax, imm32' 632 * (which zero-extends imm32) to save 2 bytes. 633 */ 634 if (sign_propagate && (s32)imm32 < 0) { 635 /* 'mov %rax, imm32' sign extends imm32 */ 636 b1 = add_1mod(0x48, dst_reg); 637 b2 = 0xC7; 638 b3 = 0xC0; 639 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32); 640 goto done; 641 } 642 643 /* 644 * Optimization: if imm32 is zero, use 'xor %eax, %eax' 645 * to save 3 bytes. 646 */ 647 if (imm32 == 0) { 648 if (is_ereg(dst_reg)) 649 EMIT1(add_2mod(0x40, dst_reg, dst_reg)); 650 b2 = 0x31; /* xor */ 651 b3 = 0xC0; 652 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg)); 653 goto done; 654 } 655 656 /* mov %eax, imm32 */ 657 if (is_ereg(dst_reg)) 658 EMIT1(add_1mod(0x40, dst_reg)); 659 EMIT1_off32(add_1reg(0xB8, dst_reg), imm32); 660 done: 661 *pprog = prog; 662 } 663 664 static void emit_mov_imm64(u8 **pprog, u32 dst_reg, 665 const u32 imm32_hi, const u32 imm32_lo) 666 { 667 u8 *prog = *pprog; 668 669 if (is_uimm32(((u64)imm32_hi << 32) | (u32)imm32_lo)) { 670 /* 671 * For emitting plain u32, where sign bit must not be 672 * propagated LLVM tends to load imm64 over mov32 673 * directly, so save couple of bytes by just doing 674 * 'mov %eax, imm32' instead. 675 */ 676 emit_mov_imm32(&prog, false, dst_reg, imm32_lo); 677 } else { 678 /* movabsq rax, imm64 */ 679 EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg)); 680 EMIT(imm32_lo, 4); 681 EMIT(imm32_hi, 4); 682 } 683 684 *pprog = prog; 685 } 686 687 static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg) 688 { 689 u8 *prog = *pprog; 690 691 if (is64) { 692 /* mov dst, src */ 693 EMIT_mov(dst_reg, src_reg); 694 } else { 695 /* mov32 dst, src */ 696 if (is_ereg(dst_reg) || is_ereg(src_reg)) 697 EMIT1(add_2mod(0x40, dst_reg, src_reg)); 698 EMIT2(0x89, add_2reg(0xC0, dst_reg, src_reg)); 699 } 700 701 *pprog = prog; 702 } 703 704 static void emit_movsx_reg(u8 **pprog, int num_bits, bool is64, u32 dst_reg, 705 u32 src_reg) 706 { 707 u8 *prog = *pprog; 708 709 if (is64) { 710 /* movs[b,w,l]q dst, src */ 711 if (num_bits == 8) 712 EMIT4(add_2mod(0x48, src_reg, dst_reg), 0x0f, 0xbe, 713 add_2reg(0xC0, src_reg, dst_reg)); 714 else if (num_bits == 16) 715 EMIT4(add_2mod(0x48, src_reg, dst_reg), 0x0f, 0xbf, 716 add_2reg(0xC0, src_reg, dst_reg)); 717 else if (num_bits == 32) 718 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x63, 719 add_2reg(0xC0, src_reg, dst_reg)); 720 } else { 721 /* movs[b,w]l dst, src */ 722 if (num_bits == 8) { 723 EMIT4(add_2mod(0x40, src_reg, dst_reg), 0x0f, 0xbe, 724 add_2reg(0xC0, src_reg, dst_reg)); 725 } else if (num_bits == 16) { 726 if (is_ereg(dst_reg) || is_ereg(src_reg)) 727 EMIT1(add_2mod(0x40, src_reg, dst_reg)); 728 EMIT3(add_2mod(0x0f, src_reg, dst_reg), 0xbf, 729 add_2reg(0xC0, src_reg, dst_reg)); 730 } 731 } 732 733 *pprog = prog; 734 } 735 736 /* Emit the suffix (ModR/M etc) for addressing *(ptr_reg + off) and val_reg */ 737 static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off) 738 { 739 u8 *prog = *pprog; 740 741 if (is_imm8(off)) { 742 /* 1-byte signed displacement. 743 * 744 * If off == 0 we could skip this and save one extra byte, but 745 * special case of x86 R13 which always needs an offset is not 746 * worth the hassle 747 */ 748 EMIT2(add_2reg(0x40, ptr_reg, val_reg), off); 749 } else { 750 /* 4-byte signed displacement */ 751 EMIT1_off32(add_2reg(0x80, ptr_reg, val_reg), off); 752 } 753 *pprog = prog; 754 } 755 756 /* 757 * Emit a REX byte if it will be necessary to address these registers 758 */ 759 static void maybe_emit_mod(u8 **pprog, u32 dst_reg, u32 src_reg, bool is64) 760 { 761 u8 *prog = *pprog; 762 763 if (is64) 764 EMIT1(add_2mod(0x48, dst_reg, src_reg)); 765 else if (is_ereg(dst_reg) || is_ereg(src_reg)) 766 EMIT1(add_2mod(0x40, dst_reg, src_reg)); 767 *pprog = prog; 768 } 769 770 /* 771 * Similar version of maybe_emit_mod() for a single register 772 */ 773 static void maybe_emit_1mod(u8 **pprog, u32 reg, bool is64) 774 { 775 u8 *prog = *pprog; 776 777 if (is64) 778 EMIT1(add_1mod(0x48, reg)); 779 else if (is_ereg(reg)) 780 EMIT1(add_1mod(0x40, reg)); 781 *pprog = prog; 782 } 783 784 /* LDX: dst_reg = *(u8*)(src_reg + off) */ 785 static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 786 { 787 u8 *prog = *pprog; 788 789 switch (size) { 790 case BPF_B: 791 /* Emit 'movzx rax, byte ptr [rax + off]' */ 792 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6); 793 break; 794 case BPF_H: 795 /* Emit 'movzx rax, word ptr [rax + off]' */ 796 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7); 797 break; 798 case BPF_W: 799 /* Emit 'mov eax, dword ptr [rax+0x14]' */ 800 if (is_ereg(dst_reg) || is_ereg(src_reg)) 801 EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B); 802 else 803 EMIT1(0x8B); 804 break; 805 case BPF_DW: 806 /* Emit 'mov rax, qword ptr [rax+0x14]' */ 807 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B); 808 break; 809 } 810 emit_insn_suffix(&prog, src_reg, dst_reg, off); 811 *pprog = prog; 812 } 813 814 /* LDSX: dst_reg = *(s8*)(src_reg + off) */ 815 static void emit_ldsx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 816 { 817 u8 *prog = *pprog; 818 819 switch (size) { 820 case BPF_B: 821 /* Emit 'movsx rax, byte ptr [rax + off]' */ 822 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xBE); 823 break; 824 case BPF_H: 825 /* Emit 'movsx rax, word ptr [rax + off]' */ 826 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xBF); 827 break; 828 case BPF_W: 829 /* Emit 'movsx rax, dword ptr [rax+0x14]' */ 830 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x63); 831 break; 832 } 833 emit_insn_suffix(&prog, src_reg, dst_reg, off); 834 *pprog = prog; 835 } 836 837 /* STX: *(u8*)(dst_reg + off) = src_reg */ 838 static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 839 { 840 u8 *prog = *pprog; 841 842 switch (size) { 843 case BPF_B: 844 /* Emit 'mov byte ptr [rax + off], al' */ 845 if (is_ereg(dst_reg) || is_ereg_8l(src_reg)) 846 /* Add extra byte for eregs or SIL,DIL,BPL in src_reg */ 847 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88); 848 else 849 EMIT1(0x88); 850 break; 851 case BPF_H: 852 if (is_ereg(dst_reg) || is_ereg(src_reg)) 853 EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89); 854 else 855 EMIT2(0x66, 0x89); 856 break; 857 case BPF_W: 858 if (is_ereg(dst_reg) || is_ereg(src_reg)) 859 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89); 860 else 861 EMIT1(0x89); 862 break; 863 case BPF_DW: 864 EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89); 865 break; 866 } 867 emit_insn_suffix(&prog, dst_reg, src_reg, off); 868 *pprog = prog; 869 } 870 871 static int emit_atomic(u8 **pprog, u8 atomic_op, 872 u32 dst_reg, u32 src_reg, s16 off, u8 bpf_size) 873 { 874 u8 *prog = *pprog; 875 876 EMIT1(0xF0); /* lock prefix */ 877 878 maybe_emit_mod(&prog, dst_reg, src_reg, bpf_size == BPF_DW); 879 880 /* emit opcode */ 881 switch (atomic_op) { 882 case BPF_ADD: 883 case BPF_AND: 884 case BPF_OR: 885 case BPF_XOR: 886 /* lock *(u32/u64*)(dst_reg + off) <op>= src_reg */ 887 EMIT1(simple_alu_opcodes[atomic_op]); 888 break; 889 case BPF_ADD | BPF_FETCH: 890 /* src_reg = atomic_fetch_add(dst_reg + off, src_reg); */ 891 EMIT2(0x0F, 0xC1); 892 break; 893 case BPF_XCHG: 894 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */ 895 EMIT1(0x87); 896 break; 897 case BPF_CMPXCHG: 898 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */ 899 EMIT2(0x0F, 0xB1); 900 break; 901 default: 902 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op); 903 return -EFAULT; 904 } 905 906 emit_insn_suffix(&prog, dst_reg, src_reg, off); 907 908 *pprog = prog; 909 return 0; 910 } 911 912 bool ex_handler_bpf(const struct exception_table_entry *x, struct pt_regs *regs) 913 { 914 u32 reg = x->fixup >> 8; 915 916 /* jump over faulting load and clear dest register */ 917 *(unsigned long *)((void *)regs + reg) = 0; 918 regs->ip += x->fixup & 0xff; 919 return true; 920 } 921 922 static void detect_reg_usage(struct bpf_insn *insn, int insn_cnt, 923 bool *regs_used, bool *tail_call_seen) 924 { 925 int i; 926 927 for (i = 1; i <= insn_cnt; i++, insn++) { 928 if (insn->code == (BPF_JMP | BPF_TAIL_CALL)) 929 *tail_call_seen = true; 930 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6) 931 regs_used[0] = true; 932 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7) 933 regs_used[1] = true; 934 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8) 935 regs_used[2] = true; 936 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9) 937 regs_used[3] = true; 938 } 939 } 940 941 static void emit_nops(u8 **pprog, int len) 942 { 943 u8 *prog = *pprog; 944 int i, noplen; 945 946 while (len > 0) { 947 noplen = len; 948 949 if (noplen > ASM_NOP_MAX) 950 noplen = ASM_NOP_MAX; 951 952 for (i = 0; i < noplen; i++) 953 EMIT1(x86_nops[noplen][i]); 954 len -= noplen; 955 } 956 957 *pprog = prog; 958 } 959 960 /* emit the 3-byte VEX prefix 961 * 962 * r: same as rex.r, extra bit for ModRM reg field 963 * x: same as rex.x, extra bit for SIB index field 964 * b: same as rex.b, extra bit for ModRM r/m, or SIB base 965 * m: opcode map select, encoding escape bytes e.g. 0x0f38 966 * w: same as rex.w (32 bit or 64 bit) or opcode specific 967 * src_reg2: additional source reg (encoded as BPF reg) 968 * l: vector length (128 bit or 256 bit) or reserved 969 * pp: opcode prefix (none, 0x66, 0xf2 or 0xf3) 970 */ 971 static void emit_3vex(u8 **pprog, bool r, bool x, bool b, u8 m, 972 bool w, u8 src_reg2, bool l, u8 pp) 973 { 974 u8 *prog = *pprog; 975 const u8 b0 = 0xc4; /* first byte of 3-byte VEX prefix */ 976 u8 b1, b2; 977 u8 vvvv = reg2hex[src_reg2]; 978 979 /* reg2hex gives only the lower 3 bit of vvvv */ 980 if (is_ereg(src_reg2)) 981 vvvv |= 1 << 3; 982 983 /* 984 * 2nd byte of 3-byte VEX prefix 985 * ~ means bit inverted encoding 986 * 987 * 7 0 988 * +---+---+---+---+---+---+---+---+ 989 * |~R |~X |~B | m | 990 * +---+---+---+---+---+---+---+---+ 991 */ 992 b1 = (!r << 7) | (!x << 6) | (!b << 5) | (m & 0x1f); 993 /* 994 * 3rd byte of 3-byte VEX prefix 995 * 996 * 7 0 997 * +---+---+---+---+---+---+---+---+ 998 * | W | ~vvvv | L | pp | 999 * +---+---+---+---+---+---+---+---+ 1000 */ 1001 b2 = (w << 7) | ((~vvvv & 0xf) << 3) | (l << 2) | (pp & 3); 1002 1003 EMIT3(b0, b1, b2); 1004 *pprog = prog; 1005 } 1006 1007 /* emit BMI2 shift instruction */ 1008 static void emit_shiftx(u8 **pprog, u32 dst_reg, u8 src_reg, bool is64, u8 op) 1009 { 1010 u8 *prog = *pprog; 1011 bool r = is_ereg(dst_reg); 1012 u8 m = 2; /* escape code 0f38 */ 1013 1014 emit_3vex(&prog, r, false, r, m, is64, src_reg, false, op); 1015 EMIT2(0xf7, add_2reg(0xC0, dst_reg, dst_reg)); 1016 *pprog = prog; 1017 } 1018 1019 #define INSN_SZ_DIFF (((addrs[i] - addrs[i - 1]) - (prog - temp))) 1020 1021 static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image, 1022 int oldproglen, struct jit_context *ctx, bool jmp_padding) 1023 { 1024 bool tail_call_reachable = bpf_prog->aux->tail_call_reachable; 1025 struct bpf_insn *insn = bpf_prog->insnsi; 1026 bool callee_regs_used[4] = {}; 1027 int insn_cnt = bpf_prog->len; 1028 bool tail_call_seen = false; 1029 bool seen_exit = false; 1030 u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY]; 1031 int i, excnt = 0; 1032 int ilen, proglen = 0; 1033 u8 *prog = temp; 1034 int err; 1035 1036 detect_reg_usage(insn, insn_cnt, callee_regs_used, 1037 &tail_call_seen); 1038 1039 /* tail call's presence in current prog implies it is reachable */ 1040 tail_call_reachable |= tail_call_seen; 1041 1042 emit_prologue(&prog, bpf_prog->aux->stack_depth, 1043 bpf_prog_was_classic(bpf_prog), tail_call_reachable, 1044 bpf_prog->aux->func_idx != 0); 1045 push_callee_regs(&prog, callee_regs_used); 1046 1047 ilen = prog - temp; 1048 if (rw_image) 1049 memcpy(rw_image + proglen, temp, ilen); 1050 proglen += ilen; 1051 addrs[0] = proglen; 1052 prog = temp; 1053 1054 for (i = 1; i <= insn_cnt; i++, insn++) { 1055 const s32 imm32 = insn->imm; 1056 u32 dst_reg = insn->dst_reg; 1057 u32 src_reg = insn->src_reg; 1058 u8 b2 = 0, b3 = 0; 1059 u8 *start_of_ldx; 1060 s64 jmp_offset; 1061 s16 insn_off; 1062 u8 jmp_cond; 1063 u8 *func; 1064 int nops; 1065 1066 switch (insn->code) { 1067 /* ALU */ 1068 case BPF_ALU | BPF_ADD | BPF_X: 1069 case BPF_ALU | BPF_SUB | BPF_X: 1070 case BPF_ALU | BPF_AND | BPF_X: 1071 case BPF_ALU | BPF_OR | BPF_X: 1072 case BPF_ALU | BPF_XOR | BPF_X: 1073 case BPF_ALU64 | BPF_ADD | BPF_X: 1074 case BPF_ALU64 | BPF_SUB | BPF_X: 1075 case BPF_ALU64 | BPF_AND | BPF_X: 1076 case BPF_ALU64 | BPF_OR | BPF_X: 1077 case BPF_ALU64 | BPF_XOR | BPF_X: 1078 maybe_emit_mod(&prog, dst_reg, src_reg, 1079 BPF_CLASS(insn->code) == BPF_ALU64); 1080 b2 = simple_alu_opcodes[BPF_OP(insn->code)]; 1081 EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg)); 1082 break; 1083 1084 case BPF_ALU64 | BPF_MOV | BPF_X: 1085 case BPF_ALU | BPF_MOV | BPF_X: 1086 if (insn->off == 0) 1087 emit_mov_reg(&prog, 1088 BPF_CLASS(insn->code) == BPF_ALU64, 1089 dst_reg, src_reg); 1090 else 1091 emit_movsx_reg(&prog, insn->off, 1092 BPF_CLASS(insn->code) == BPF_ALU64, 1093 dst_reg, src_reg); 1094 break; 1095 1096 /* neg dst */ 1097 case BPF_ALU | BPF_NEG: 1098 case BPF_ALU64 | BPF_NEG: 1099 maybe_emit_1mod(&prog, dst_reg, 1100 BPF_CLASS(insn->code) == BPF_ALU64); 1101 EMIT2(0xF7, add_1reg(0xD8, dst_reg)); 1102 break; 1103 1104 case BPF_ALU | BPF_ADD | BPF_K: 1105 case BPF_ALU | BPF_SUB | BPF_K: 1106 case BPF_ALU | BPF_AND | BPF_K: 1107 case BPF_ALU | BPF_OR | BPF_K: 1108 case BPF_ALU | BPF_XOR | BPF_K: 1109 case BPF_ALU64 | BPF_ADD | BPF_K: 1110 case BPF_ALU64 | BPF_SUB | BPF_K: 1111 case BPF_ALU64 | BPF_AND | BPF_K: 1112 case BPF_ALU64 | BPF_OR | BPF_K: 1113 case BPF_ALU64 | BPF_XOR | BPF_K: 1114 maybe_emit_1mod(&prog, dst_reg, 1115 BPF_CLASS(insn->code) == BPF_ALU64); 1116 1117 /* 1118 * b3 holds 'normal' opcode, b2 short form only valid 1119 * in case dst is eax/rax. 1120 */ 1121 switch (BPF_OP(insn->code)) { 1122 case BPF_ADD: 1123 b3 = 0xC0; 1124 b2 = 0x05; 1125 break; 1126 case BPF_SUB: 1127 b3 = 0xE8; 1128 b2 = 0x2D; 1129 break; 1130 case BPF_AND: 1131 b3 = 0xE0; 1132 b2 = 0x25; 1133 break; 1134 case BPF_OR: 1135 b3 = 0xC8; 1136 b2 = 0x0D; 1137 break; 1138 case BPF_XOR: 1139 b3 = 0xF0; 1140 b2 = 0x35; 1141 break; 1142 } 1143 1144 if (is_imm8(imm32)) 1145 EMIT3(0x83, add_1reg(b3, dst_reg), imm32); 1146 else if (is_axreg(dst_reg)) 1147 EMIT1_off32(b2, imm32); 1148 else 1149 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32); 1150 break; 1151 1152 case BPF_ALU64 | BPF_MOV | BPF_K: 1153 case BPF_ALU | BPF_MOV | BPF_K: 1154 emit_mov_imm32(&prog, BPF_CLASS(insn->code) == BPF_ALU64, 1155 dst_reg, imm32); 1156 break; 1157 1158 case BPF_LD | BPF_IMM | BPF_DW: 1159 emit_mov_imm64(&prog, dst_reg, insn[1].imm, insn[0].imm); 1160 insn++; 1161 i++; 1162 break; 1163 1164 /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */ 1165 case BPF_ALU | BPF_MOD | BPF_X: 1166 case BPF_ALU | BPF_DIV | BPF_X: 1167 case BPF_ALU | BPF_MOD | BPF_K: 1168 case BPF_ALU | BPF_DIV | BPF_K: 1169 case BPF_ALU64 | BPF_MOD | BPF_X: 1170 case BPF_ALU64 | BPF_DIV | BPF_X: 1171 case BPF_ALU64 | BPF_MOD | BPF_K: 1172 case BPF_ALU64 | BPF_DIV | BPF_K: { 1173 bool is64 = BPF_CLASS(insn->code) == BPF_ALU64; 1174 1175 if (dst_reg != BPF_REG_0) 1176 EMIT1(0x50); /* push rax */ 1177 if (dst_reg != BPF_REG_3) 1178 EMIT1(0x52); /* push rdx */ 1179 1180 if (BPF_SRC(insn->code) == BPF_X) { 1181 if (src_reg == BPF_REG_0 || 1182 src_reg == BPF_REG_3) { 1183 /* mov r11, src_reg */ 1184 EMIT_mov(AUX_REG, src_reg); 1185 src_reg = AUX_REG; 1186 } 1187 } else { 1188 /* mov r11, imm32 */ 1189 EMIT3_off32(0x49, 0xC7, 0xC3, imm32); 1190 src_reg = AUX_REG; 1191 } 1192 1193 if (dst_reg != BPF_REG_0) 1194 /* mov rax, dst_reg */ 1195 emit_mov_reg(&prog, is64, BPF_REG_0, dst_reg); 1196 1197 /* 1198 * xor edx, edx 1199 * equivalent to 'xor rdx, rdx', but one byte less 1200 */ 1201 EMIT2(0x31, 0xd2); 1202 1203 /* div src_reg */ 1204 maybe_emit_1mod(&prog, src_reg, is64); 1205 EMIT2(0xF7, add_1reg(0xF0, src_reg)); 1206 1207 if (BPF_OP(insn->code) == BPF_MOD && 1208 dst_reg != BPF_REG_3) 1209 /* mov dst_reg, rdx */ 1210 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_3); 1211 else if (BPF_OP(insn->code) == BPF_DIV && 1212 dst_reg != BPF_REG_0) 1213 /* mov dst_reg, rax */ 1214 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_0); 1215 1216 if (dst_reg != BPF_REG_3) 1217 EMIT1(0x5A); /* pop rdx */ 1218 if (dst_reg != BPF_REG_0) 1219 EMIT1(0x58); /* pop rax */ 1220 break; 1221 } 1222 1223 case BPF_ALU | BPF_MUL | BPF_K: 1224 case BPF_ALU64 | BPF_MUL | BPF_K: 1225 maybe_emit_mod(&prog, dst_reg, dst_reg, 1226 BPF_CLASS(insn->code) == BPF_ALU64); 1227 1228 if (is_imm8(imm32)) 1229 /* imul dst_reg, dst_reg, imm8 */ 1230 EMIT3(0x6B, add_2reg(0xC0, dst_reg, dst_reg), 1231 imm32); 1232 else 1233 /* imul dst_reg, dst_reg, imm32 */ 1234 EMIT2_off32(0x69, 1235 add_2reg(0xC0, dst_reg, dst_reg), 1236 imm32); 1237 break; 1238 1239 case BPF_ALU | BPF_MUL | BPF_X: 1240 case BPF_ALU64 | BPF_MUL | BPF_X: 1241 maybe_emit_mod(&prog, src_reg, dst_reg, 1242 BPF_CLASS(insn->code) == BPF_ALU64); 1243 1244 /* imul dst_reg, src_reg */ 1245 EMIT3(0x0F, 0xAF, add_2reg(0xC0, src_reg, dst_reg)); 1246 break; 1247 1248 /* Shifts */ 1249 case BPF_ALU | BPF_LSH | BPF_K: 1250 case BPF_ALU | BPF_RSH | BPF_K: 1251 case BPF_ALU | BPF_ARSH | BPF_K: 1252 case BPF_ALU64 | BPF_LSH | BPF_K: 1253 case BPF_ALU64 | BPF_RSH | BPF_K: 1254 case BPF_ALU64 | BPF_ARSH | BPF_K: 1255 maybe_emit_1mod(&prog, dst_reg, 1256 BPF_CLASS(insn->code) == BPF_ALU64); 1257 1258 b3 = simple_alu_opcodes[BPF_OP(insn->code)]; 1259 if (imm32 == 1) 1260 EMIT2(0xD1, add_1reg(b3, dst_reg)); 1261 else 1262 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32); 1263 break; 1264 1265 case BPF_ALU | BPF_LSH | BPF_X: 1266 case BPF_ALU | BPF_RSH | BPF_X: 1267 case BPF_ALU | BPF_ARSH | BPF_X: 1268 case BPF_ALU64 | BPF_LSH | BPF_X: 1269 case BPF_ALU64 | BPF_RSH | BPF_X: 1270 case BPF_ALU64 | BPF_ARSH | BPF_X: 1271 /* BMI2 shifts aren't better when shift count is already in rcx */ 1272 if (boot_cpu_has(X86_FEATURE_BMI2) && src_reg != BPF_REG_4) { 1273 /* shrx/sarx/shlx dst_reg, dst_reg, src_reg */ 1274 bool w = (BPF_CLASS(insn->code) == BPF_ALU64); 1275 u8 op; 1276 1277 switch (BPF_OP(insn->code)) { 1278 case BPF_LSH: 1279 op = 1; /* prefix 0x66 */ 1280 break; 1281 case BPF_RSH: 1282 op = 3; /* prefix 0xf2 */ 1283 break; 1284 case BPF_ARSH: 1285 op = 2; /* prefix 0xf3 */ 1286 break; 1287 } 1288 1289 emit_shiftx(&prog, dst_reg, src_reg, w, op); 1290 1291 break; 1292 } 1293 1294 if (src_reg != BPF_REG_4) { /* common case */ 1295 /* Check for bad case when dst_reg == rcx */ 1296 if (dst_reg == BPF_REG_4) { 1297 /* mov r11, dst_reg */ 1298 EMIT_mov(AUX_REG, dst_reg); 1299 dst_reg = AUX_REG; 1300 } else { 1301 EMIT1(0x51); /* push rcx */ 1302 } 1303 /* mov rcx, src_reg */ 1304 EMIT_mov(BPF_REG_4, src_reg); 1305 } 1306 1307 /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */ 1308 maybe_emit_1mod(&prog, dst_reg, 1309 BPF_CLASS(insn->code) == BPF_ALU64); 1310 1311 b3 = simple_alu_opcodes[BPF_OP(insn->code)]; 1312 EMIT2(0xD3, add_1reg(b3, dst_reg)); 1313 1314 if (src_reg != BPF_REG_4) { 1315 if (insn->dst_reg == BPF_REG_4) 1316 /* mov dst_reg, r11 */ 1317 EMIT_mov(insn->dst_reg, AUX_REG); 1318 else 1319 EMIT1(0x59); /* pop rcx */ 1320 } 1321 1322 break; 1323 1324 case BPF_ALU | BPF_END | BPF_FROM_BE: 1325 case BPF_ALU64 | BPF_END | BPF_FROM_LE: 1326 switch (imm32) { 1327 case 16: 1328 /* Emit 'ror %ax, 8' to swap lower 2 bytes */ 1329 EMIT1(0x66); 1330 if (is_ereg(dst_reg)) 1331 EMIT1(0x41); 1332 EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8); 1333 1334 /* Emit 'movzwl eax, ax' */ 1335 if (is_ereg(dst_reg)) 1336 EMIT3(0x45, 0x0F, 0xB7); 1337 else 1338 EMIT2(0x0F, 0xB7); 1339 EMIT1(add_2reg(0xC0, dst_reg, dst_reg)); 1340 break; 1341 case 32: 1342 /* Emit 'bswap eax' to swap lower 4 bytes */ 1343 if (is_ereg(dst_reg)) 1344 EMIT2(0x41, 0x0F); 1345 else 1346 EMIT1(0x0F); 1347 EMIT1(add_1reg(0xC8, dst_reg)); 1348 break; 1349 case 64: 1350 /* Emit 'bswap rax' to swap 8 bytes */ 1351 EMIT3(add_1mod(0x48, dst_reg), 0x0F, 1352 add_1reg(0xC8, dst_reg)); 1353 break; 1354 } 1355 break; 1356 1357 case BPF_ALU | BPF_END | BPF_FROM_LE: 1358 switch (imm32) { 1359 case 16: 1360 /* 1361 * Emit 'movzwl eax, ax' to zero extend 16-bit 1362 * into 64 bit 1363 */ 1364 if (is_ereg(dst_reg)) 1365 EMIT3(0x45, 0x0F, 0xB7); 1366 else 1367 EMIT2(0x0F, 0xB7); 1368 EMIT1(add_2reg(0xC0, dst_reg, dst_reg)); 1369 break; 1370 case 32: 1371 /* Emit 'mov eax, eax' to clear upper 32-bits */ 1372 if (is_ereg(dst_reg)) 1373 EMIT1(0x45); 1374 EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg)); 1375 break; 1376 case 64: 1377 /* nop */ 1378 break; 1379 } 1380 break; 1381 1382 /* speculation barrier */ 1383 case BPF_ST | BPF_NOSPEC: 1384 EMIT_LFENCE(); 1385 break; 1386 1387 /* ST: *(u8*)(dst_reg + off) = imm */ 1388 case BPF_ST | BPF_MEM | BPF_B: 1389 if (is_ereg(dst_reg)) 1390 EMIT2(0x41, 0xC6); 1391 else 1392 EMIT1(0xC6); 1393 goto st; 1394 case BPF_ST | BPF_MEM | BPF_H: 1395 if (is_ereg(dst_reg)) 1396 EMIT3(0x66, 0x41, 0xC7); 1397 else 1398 EMIT2(0x66, 0xC7); 1399 goto st; 1400 case BPF_ST | BPF_MEM | BPF_W: 1401 if (is_ereg(dst_reg)) 1402 EMIT2(0x41, 0xC7); 1403 else 1404 EMIT1(0xC7); 1405 goto st; 1406 case BPF_ST | BPF_MEM | BPF_DW: 1407 EMIT2(add_1mod(0x48, dst_reg), 0xC7); 1408 1409 st: if (is_imm8(insn->off)) 1410 EMIT2(add_1reg(0x40, dst_reg), insn->off); 1411 else 1412 EMIT1_off32(add_1reg(0x80, dst_reg), insn->off); 1413 1414 EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(insn->code))); 1415 break; 1416 1417 /* STX: *(u8*)(dst_reg + off) = src_reg */ 1418 case BPF_STX | BPF_MEM | BPF_B: 1419 case BPF_STX | BPF_MEM | BPF_H: 1420 case BPF_STX | BPF_MEM | BPF_W: 1421 case BPF_STX | BPF_MEM | BPF_DW: 1422 emit_stx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off); 1423 break; 1424 1425 /* LDX: dst_reg = *(u8*)(src_reg + off) */ 1426 case BPF_LDX | BPF_MEM | BPF_B: 1427 case BPF_LDX | BPF_PROBE_MEM | BPF_B: 1428 case BPF_LDX | BPF_MEM | BPF_H: 1429 case BPF_LDX | BPF_PROBE_MEM | BPF_H: 1430 case BPF_LDX | BPF_MEM | BPF_W: 1431 case BPF_LDX | BPF_PROBE_MEM | BPF_W: 1432 case BPF_LDX | BPF_MEM | BPF_DW: 1433 case BPF_LDX | BPF_PROBE_MEM | BPF_DW: 1434 /* LDXS: dst_reg = *(s8*)(src_reg + off) */ 1435 case BPF_LDX | BPF_MEMSX | BPF_B: 1436 case BPF_LDX | BPF_MEMSX | BPF_H: 1437 case BPF_LDX | BPF_MEMSX | BPF_W: 1438 case BPF_LDX | BPF_PROBE_MEMSX | BPF_B: 1439 case BPF_LDX | BPF_PROBE_MEMSX | BPF_H: 1440 case BPF_LDX | BPF_PROBE_MEMSX | BPF_W: 1441 insn_off = insn->off; 1442 1443 if (BPF_MODE(insn->code) == BPF_PROBE_MEM || 1444 BPF_MODE(insn->code) == BPF_PROBE_MEMSX) { 1445 /* Conservatively check that src_reg + insn->off is a kernel address: 1446 * src_reg + insn->off >= TASK_SIZE_MAX + PAGE_SIZE 1447 * src_reg is used as scratch for src_reg += insn->off and restored 1448 * after emit_ldx if necessary 1449 */ 1450 1451 u64 limit = TASK_SIZE_MAX + PAGE_SIZE; 1452 u8 *end_of_jmp; 1453 1454 /* At end of these emitted checks, insn->off will have been added 1455 * to src_reg, so no need to do relative load with insn->off offset 1456 */ 1457 insn_off = 0; 1458 1459 /* movabsq r11, limit */ 1460 EMIT2(add_1mod(0x48, AUX_REG), add_1reg(0xB8, AUX_REG)); 1461 EMIT((u32)limit, 4); 1462 EMIT(limit >> 32, 4); 1463 1464 if (insn->off) { 1465 /* add src_reg, insn->off */ 1466 maybe_emit_1mod(&prog, src_reg, true); 1467 EMIT2_off32(0x81, add_1reg(0xC0, src_reg), insn->off); 1468 } 1469 1470 /* cmp src_reg, r11 */ 1471 maybe_emit_mod(&prog, src_reg, AUX_REG, true); 1472 EMIT2(0x39, add_2reg(0xC0, src_reg, AUX_REG)); 1473 1474 /* if unsigned '>=', goto load */ 1475 EMIT2(X86_JAE, 0); 1476 end_of_jmp = prog; 1477 1478 /* xor dst_reg, dst_reg */ 1479 emit_mov_imm32(&prog, false, dst_reg, 0); 1480 /* jmp byte_after_ldx */ 1481 EMIT2(0xEB, 0); 1482 1483 /* populate jmp_offset for JAE above to jump to start_of_ldx */ 1484 start_of_ldx = prog; 1485 end_of_jmp[-1] = start_of_ldx - end_of_jmp; 1486 } 1487 if (BPF_MODE(insn->code) == BPF_PROBE_MEMSX || 1488 BPF_MODE(insn->code) == BPF_MEMSX) 1489 emit_ldsx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn_off); 1490 else 1491 emit_ldx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn_off); 1492 if (BPF_MODE(insn->code) == BPF_PROBE_MEM || 1493 BPF_MODE(insn->code) == BPF_PROBE_MEMSX) { 1494 struct exception_table_entry *ex; 1495 u8 *_insn = image + proglen + (start_of_ldx - temp); 1496 s64 delta; 1497 1498 /* populate jmp_offset for JMP above */ 1499 start_of_ldx[-1] = prog - start_of_ldx; 1500 1501 if (insn->off && src_reg != dst_reg) { 1502 /* sub src_reg, insn->off 1503 * Restore src_reg after "add src_reg, insn->off" in prev 1504 * if statement. But if src_reg == dst_reg, emit_ldx 1505 * above already clobbered src_reg, so no need to restore. 1506 * If add src_reg, insn->off was unnecessary, no need to 1507 * restore either. 1508 */ 1509 maybe_emit_1mod(&prog, src_reg, true); 1510 EMIT2_off32(0x81, add_1reg(0xE8, src_reg), insn->off); 1511 } 1512 1513 if (!bpf_prog->aux->extable) 1514 break; 1515 1516 if (excnt >= bpf_prog->aux->num_exentries) { 1517 pr_err("ex gen bug\n"); 1518 return -EFAULT; 1519 } 1520 ex = &bpf_prog->aux->extable[excnt++]; 1521 1522 delta = _insn - (u8 *)&ex->insn; 1523 if (!is_simm32(delta)) { 1524 pr_err("extable->insn doesn't fit into 32-bit\n"); 1525 return -EFAULT; 1526 } 1527 /* switch ex to rw buffer for writes */ 1528 ex = (void *)rw_image + ((void *)ex - (void *)image); 1529 1530 ex->insn = delta; 1531 1532 ex->data = EX_TYPE_BPF; 1533 1534 if (dst_reg > BPF_REG_9) { 1535 pr_err("verifier error\n"); 1536 return -EFAULT; 1537 } 1538 /* 1539 * Compute size of x86 insn and its target dest x86 register. 1540 * ex_handler_bpf() will use lower 8 bits to adjust 1541 * pt_regs->ip to jump over this x86 instruction 1542 * and upper bits to figure out which pt_regs to zero out. 1543 * End result: x86 insn "mov rbx, qword ptr [rax+0x14]" 1544 * of 4 bytes will be ignored and rbx will be zero inited. 1545 */ 1546 ex->fixup = (prog - start_of_ldx) | (reg2pt_regs[dst_reg] << 8); 1547 } 1548 break; 1549 1550 case BPF_STX | BPF_ATOMIC | BPF_W: 1551 case BPF_STX | BPF_ATOMIC | BPF_DW: 1552 if (insn->imm == (BPF_AND | BPF_FETCH) || 1553 insn->imm == (BPF_OR | BPF_FETCH) || 1554 insn->imm == (BPF_XOR | BPF_FETCH)) { 1555 bool is64 = BPF_SIZE(insn->code) == BPF_DW; 1556 u32 real_src_reg = src_reg; 1557 u32 real_dst_reg = dst_reg; 1558 u8 *branch_target; 1559 1560 /* 1561 * Can't be implemented with a single x86 insn. 1562 * Need to do a CMPXCHG loop. 1563 */ 1564 1565 /* Will need RAX as a CMPXCHG operand so save R0 */ 1566 emit_mov_reg(&prog, true, BPF_REG_AX, BPF_REG_0); 1567 if (src_reg == BPF_REG_0) 1568 real_src_reg = BPF_REG_AX; 1569 if (dst_reg == BPF_REG_0) 1570 real_dst_reg = BPF_REG_AX; 1571 1572 branch_target = prog; 1573 /* Load old value */ 1574 emit_ldx(&prog, BPF_SIZE(insn->code), 1575 BPF_REG_0, real_dst_reg, insn->off); 1576 /* 1577 * Perform the (commutative) operation locally, 1578 * put the result in the AUX_REG. 1579 */ 1580 emit_mov_reg(&prog, is64, AUX_REG, BPF_REG_0); 1581 maybe_emit_mod(&prog, AUX_REG, real_src_reg, is64); 1582 EMIT2(simple_alu_opcodes[BPF_OP(insn->imm)], 1583 add_2reg(0xC0, AUX_REG, real_src_reg)); 1584 /* Attempt to swap in new value */ 1585 err = emit_atomic(&prog, BPF_CMPXCHG, 1586 real_dst_reg, AUX_REG, 1587 insn->off, 1588 BPF_SIZE(insn->code)); 1589 if (WARN_ON(err)) 1590 return err; 1591 /* 1592 * ZF tells us whether we won the race. If it's 1593 * cleared we need to try again. 1594 */ 1595 EMIT2(X86_JNE, -(prog - branch_target) - 2); 1596 /* Return the pre-modification value */ 1597 emit_mov_reg(&prog, is64, real_src_reg, BPF_REG_0); 1598 /* Restore R0 after clobbering RAX */ 1599 emit_mov_reg(&prog, true, BPF_REG_0, BPF_REG_AX); 1600 break; 1601 } 1602 1603 err = emit_atomic(&prog, insn->imm, dst_reg, src_reg, 1604 insn->off, BPF_SIZE(insn->code)); 1605 if (err) 1606 return err; 1607 break; 1608 1609 /* call */ 1610 case BPF_JMP | BPF_CALL: { 1611 int offs; 1612 1613 func = (u8 *) __bpf_call_base + imm32; 1614 if (tail_call_reachable) { 1615 /* mov rax, qword ptr [rbp - rounded_stack_depth - 8] */ 1616 EMIT3_off32(0x48, 0x8B, 0x85, 1617 -round_up(bpf_prog->aux->stack_depth, 8) - 8); 1618 if (!imm32) 1619 return -EINVAL; 1620 offs = 7 + x86_call_depth_emit_accounting(&prog, func); 1621 } else { 1622 if (!imm32) 1623 return -EINVAL; 1624 offs = x86_call_depth_emit_accounting(&prog, func); 1625 } 1626 if (emit_call(&prog, func, image + addrs[i - 1] + offs)) 1627 return -EINVAL; 1628 break; 1629 } 1630 1631 case BPF_JMP | BPF_TAIL_CALL: 1632 if (imm32) 1633 emit_bpf_tail_call_direct(&bpf_prog->aux->poke_tab[imm32 - 1], 1634 &prog, image + addrs[i - 1], 1635 callee_regs_used, 1636 bpf_prog->aux->stack_depth, 1637 ctx); 1638 else 1639 emit_bpf_tail_call_indirect(&prog, 1640 callee_regs_used, 1641 bpf_prog->aux->stack_depth, 1642 image + addrs[i - 1], 1643 ctx); 1644 break; 1645 1646 /* cond jump */ 1647 case BPF_JMP | BPF_JEQ | BPF_X: 1648 case BPF_JMP | BPF_JNE | BPF_X: 1649 case BPF_JMP | BPF_JGT | BPF_X: 1650 case BPF_JMP | BPF_JLT | BPF_X: 1651 case BPF_JMP | BPF_JGE | BPF_X: 1652 case BPF_JMP | BPF_JLE | BPF_X: 1653 case BPF_JMP | BPF_JSGT | BPF_X: 1654 case BPF_JMP | BPF_JSLT | BPF_X: 1655 case BPF_JMP | BPF_JSGE | BPF_X: 1656 case BPF_JMP | BPF_JSLE | BPF_X: 1657 case BPF_JMP32 | BPF_JEQ | BPF_X: 1658 case BPF_JMP32 | BPF_JNE | BPF_X: 1659 case BPF_JMP32 | BPF_JGT | BPF_X: 1660 case BPF_JMP32 | BPF_JLT | BPF_X: 1661 case BPF_JMP32 | BPF_JGE | BPF_X: 1662 case BPF_JMP32 | BPF_JLE | BPF_X: 1663 case BPF_JMP32 | BPF_JSGT | BPF_X: 1664 case BPF_JMP32 | BPF_JSLT | BPF_X: 1665 case BPF_JMP32 | BPF_JSGE | BPF_X: 1666 case BPF_JMP32 | BPF_JSLE | BPF_X: 1667 /* cmp dst_reg, src_reg */ 1668 maybe_emit_mod(&prog, dst_reg, src_reg, 1669 BPF_CLASS(insn->code) == BPF_JMP); 1670 EMIT2(0x39, add_2reg(0xC0, dst_reg, src_reg)); 1671 goto emit_cond_jmp; 1672 1673 case BPF_JMP | BPF_JSET | BPF_X: 1674 case BPF_JMP32 | BPF_JSET | BPF_X: 1675 /* test dst_reg, src_reg */ 1676 maybe_emit_mod(&prog, dst_reg, src_reg, 1677 BPF_CLASS(insn->code) == BPF_JMP); 1678 EMIT2(0x85, add_2reg(0xC0, dst_reg, src_reg)); 1679 goto emit_cond_jmp; 1680 1681 case BPF_JMP | BPF_JSET | BPF_K: 1682 case BPF_JMP32 | BPF_JSET | BPF_K: 1683 /* test dst_reg, imm32 */ 1684 maybe_emit_1mod(&prog, dst_reg, 1685 BPF_CLASS(insn->code) == BPF_JMP); 1686 EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32); 1687 goto emit_cond_jmp; 1688 1689 case BPF_JMP | BPF_JEQ | BPF_K: 1690 case BPF_JMP | BPF_JNE | BPF_K: 1691 case BPF_JMP | BPF_JGT | BPF_K: 1692 case BPF_JMP | BPF_JLT | BPF_K: 1693 case BPF_JMP | BPF_JGE | BPF_K: 1694 case BPF_JMP | BPF_JLE | BPF_K: 1695 case BPF_JMP | BPF_JSGT | BPF_K: 1696 case BPF_JMP | BPF_JSLT | BPF_K: 1697 case BPF_JMP | BPF_JSGE | BPF_K: 1698 case BPF_JMP | BPF_JSLE | BPF_K: 1699 case BPF_JMP32 | BPF_JEQ | BPF_K: 1700 case BPF_JMP32 | BPF_JNE | BPF_K: 1701 case BPF_JMP32 | BPF_JGT | BPF_K: 1702 case BPF_JMP32 | BPF_JLT | BPF_K: 1703 case BPF_JMP32 | BPF_JGE | BPF_K: 1704 case BPF_JMP32 | BPF_JLE | BPF_K: 1705 case BPF_JMP32 | BPF_JSGT | BPF_K: 1706 case BPF_JMP32 | BPF_JSLT | BPF_K: 1707 case BPF_JMP32 | BPF_JSGE | BPF_K: 1708 case BPF_JMP32 | BPF_JSLE | BPF_K: 1709 /* test dst_reg, dst_reg to save one extra byte */ 1710 if (imm32 == 0) { 1711 maybe_emit_mod(&prog, dst_reg, dst_reg, 1712 BPF_CLASS(insn->code) == BPF_JMP); 1713 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg)); 1714 goto emit_cond_jmp; 1715 } 1716 1717 /* cmp dst_reg, imm8/32 */ 1718 maybe_emit_1mod(&prog, dst_reg, 1719 BPF_CLASS(insn->code) == BPF_JMP); 1720 1721 if (is_imm8(imm32)) 1722 EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32); 1723 else 1724 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32); 1725 1726 emit_cond_jmp: /* Convert BPF opcode to x86 */ 1727 switch (BPF_OP(insn->code)) { 1728 case BPF_JEQ: 1729 jmp_cond = X86_JE; 1730 break; 1731 case BPF_JSET: 1732 case BPF_JNE: 1733 jmp_cond = X86_JNE; 1734 break; 1735 case BPF_JGT: 1736 /* GT is unsigned '>', JA in x86 */ 1737 jmp_cond = X86_JA; 1738 break; 1739 case BPF_JLT: 1740 /* LT is unsigned '<', JB in x86 */ 1741 jmp_cond = X86_JB; 1742 break; 1743 case BPF_JGE: 1744 /* GE is unsigned '>=', JAE in x86 */ 1745 jmp_cond = X86_JAE; 1746 break; 1747 case BPF_JLE: 1748 /* LE is unsigned '<=', JBE in x86 */ 1749 jmp_cond = X86_JBE; 1750 break; 1751 case BPF_JSGT: 1752 /* Signed '>', GT in x86 */ 1753 jmp_cond = X86_JG; 1754 break; 1755 case BPF_JSLT: 1756 /* Signed '<', LT in x86 */ 1757 jmp_cond = X86_JL; 1758 break; 1759 case BPF_JSGE: 1760 /* Signed '>=', GE in x86 */ 1761 jmp_cond = X86_JGE; 1762 break; 1763 case BPF_JSLE: 1764 /* Signed '<=', LE in x86 */ 1765 jmp_cond = X86_JLE; 1766 break; 1767 default: /* to silence GCC warning */ 1768 return -EFAULT; 1769 } 1770 jmp_offset = addrs[i + insn->off] - addrs[i]; 1771 if (is_imm8(jmp_offset)) { 1772 if (jmp_padding) { 1773 /* To keep the jmp_offset valid, the extra bytes are 1774 * padded before the jump insn, so we subtract the 1775 * 2 bytes of jmp_cond insn from INSN_SZ_DIFF. 1776 * 1777 * If the previous pass already emits an imm8 1778 * jmp_cond, then this BPF insn won't shrink, so 1779 * "nops" is 0. 1780 * 1781 * On the other hand, if the previous pass emits an 1782 * imm32 jmp_cond, the extra 4 bytes(*) is padded to 1783 * keep the image from shrinking further. 1784 * 1785 * (*) imm32 jmp_cond is 6 bytes, and imm8 jmp_cond 1786 * is 2 bytes, so the size difference is 4 bytes. 1787 */ 1788 nops = INSN_SZ_DIFF - 2; 1789 if (nops != 0 && nops != 4) { 1790 pr_err("unexpected jmp_cond padding: %d bytes\n", 1791 nops); 1792 return -EFAULT; 1793 } 1794 emit_nops(&prog, nops); 1795 } 1796 EMIT2(jmp_cond, jmp_offset); 1797 } else if (is_simm32(jmp_offset)) { 1798 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset); 1799 } else { 1800 pr_err("cond_jmp gen bug %llx\n", jmp_offset); 1801 return -EFAULT; 1802 } 1803 1804 break; 1805 1806 case BPF_JMP | BPF_JA: 1807 if (insn->off == -1) 1808 /* -1 jmp instructions will always jump 1809 * backwards two bytes. Explicitly handling 1810 * this case avoids wasting too many passes 1811 * when there are long sequences of replaced 1812 * dead code. 1813 */ 1814 jmp_offset = -2; 1815 else 1816 jmp_offset = addrs[i + insn->off] - addrs[i]; 1817 1818 if (!jmp_offset) { 1819 /* 1820 * If jmp_padding is enabled, the extra nops will 1821 * be inserted. Otherwise, optimize out nop jumps. 1822 */ 1823 if (jmp_padding) { 1824 /* There are 3 possible conditions. 1825 * (1) This BPF_JA is already optimized out in 1826 * the previous run, so there is no need 1827 * to pad any extra byte (0 byte). 1828 * (2) The previous pass emits an imm8 jmp, 1829 * so we pad 2 bytes to match the previous 1830 * insn size. 1831 * (3) Similarly, the previous pass emits an 1832 * imm32 jmp, and 5 bytes is padded. 1833 */ 1834 nops = INSN_SZ_DIFF; 1835 if (nops != 0 && nops != 2 && nops != 5) { 1836 pr_err("unexpected nop jump padding: %d bytes\n", 1837 nops); 1838 return -EFAULT; 1839 } 1840 emit_nops(&prog, nops); 1841 } 1842 break; 1843 } 1844 emit_jmp: 1845 if (is_imm8(jmp_offset)) { 1846 if (jmp_padding) { 1847 /* To avoid breaking jmp_offset, the extra bytes 1848 * are padded before the actual jmp insn, so 1849 * 2 bytes is subtracted from INSN_SZ_DIFF. 1850 * 1851 * If the previous pass already emits an imm8 1852 * jmp, there is nothing to pad (0 byte). 1853 * 1854 * If it emits an imm32 jmp (5 bytes) previously 1855 * and now an imm8 jmp (2 bytes), then we pad 1856 * (5 - 2 = 3) bytes to stop the image from 1857 * shrinking further. 1858 */ 1859 nops = INSN_SZ_DIFF - 2; 1860 if (nops != 0 && nops != 3) { 1861 pr_err("unexpected jump padding: %d bytes\n", 1862 nops); 1863 return -EFAULT; 1864 } 1865 emit_nops(&prog, INSN_SZ_DIFF - 2); 1866 } 1867 EMIT2(0xEB, jmp_offset); 1868 } else if (is_simm32(jmp_offset)) { 1869 EMIT1_off32(0xE9, jmp_offset); 1870 } else { 1871 pr_err("jmp gen bug %llx\n", jmp_offset); 1872 return -EFAULT; 1873 } 1874 break; 1875 1876 case BPF_JMP | BPF_EXIT: 1877 if (seen_exit) { 1878 jmp_offset = ctx->cleanup_addr - addrs[i]; 1879 goto emit_jmp; 1880 } 1881 seen_exit = true; 1882 /* Update cleanup_addr */ 1883 ctx->cleanup_addr = proglen; 1884 pop_callee_regs(&prog, callee_regs_used); 1885 EMIT1(0xC9); /* leave */ 1886 emit_return(&prog, image + addrs[i - 1] + (prog - temp)); 1887 break; 1888 1889 default: 1890 /* 1891 * By design x86-64 JIT should support all BPF instructions. 1892 * This error will be seen if new instruction was added 1893 * to the interpreter, but not to the JIT, or if there is 1894 * junk in bpf_prog. 1895 */ 1896 pr_err("bpf_jit: unknown opcode %02x\n", insn->code); 1897 return -EINVAL; 1898 } 1899 1900 ilen = prog - temp; 1901 if (ilen > BPF_MAX_INSN_SIZE) { 1902 pr_err("bpf_jit: fatal insn size error\n"); 1903 return -EFAULT; 1904 } 1905 1906 if (image) { 1907 /* 1908 * When populating the image, assert that: 1909 * 1910 * i) We do not write beyond the allocated space, and 1911 * ii) addrs[i] did not change from the prior run, in order 1912 * to validate assumptions made for computing branch 1913 * displacements. 1914 */ 1915 if (unlikely(proglen + ilen > oldproglen || 1916 proglen + ilen != addrs[i])) { 1917 pr_err("bpf_jit: fatal error\n"); 1918 return -EFAULT; 1919 } 1920 memcpy(rw_image + proglen, temp, ilen); 1921 } 1922 proglen += ilen; 1923 addrs[i] = proglen; 1924 prog = temp; 1925 } 1926 1927 if (image && excnt != bpf_prog->aux->num_exentries) { 1928 pr_err("extable is not populated\n"); 1929 return -EFAULT; 1930 } 1931 return proglen; 1932 } 1933 1934 static void clean_stack_garbage(const struct btf_func_model *m, 1935 u8 **pprog, int nr_stack_slots, 1936 int stack_size) 1937 { 1938 int arg_size, off; 1939 u8 *prog; 1940 1941 /* Generally speaking, the compiler will pass the arguments 1942 * on-stack with "push" instruction, which will take 8-byte 1943 * on the stack. In this case, there won't be garbage values 1944 * while we copy the arguments from origin stack frame to current 1945 * in BPF_DW. 1946 * 1947 * However, sometimes the compiler will only allocate 4-byte on 1948 * the stack for the arguments. For now, this case will only 1949 * happen if there is only one argument on-stack and its size 1950 * not more than 4 byte. In this case, there will be garbage 1951 * values on the upper 4-byte where we store the argument on 1952 * current stack frame. 1953 * 1954 * arguments on origin stack: 1955 * 1956 * stack_arg_1(4-byte) xxx(4-byte) 1957 * 1958 * what we copy: 1959 * 1960 * stack_arg_1(8-byte): stack_arg_1(origin) xxx 1961 * 1962 * and the xxx is the garbage values which we should clean here. 1963 */ 1964 if (nr_stack_slots != 1) 1965 return; 1966 1967 /* the size of the last argument */ 1968 arg_size = m->arg_size[m->nr_args - 1]; 1969 if (arg_size <= 4) { 1970 off = -(stack_size - 4); 1971 prog = *pprog; 1972 /* mov DWORD PTR [rbp + off], 0 */ 1973 if (!is_imm8(off)) 1974 EMIT2_off32(0xC7, 0x85, off); 1975 else 1976 EMIT3(0xC7, 0x45, off); 1977 EMIT(0, 4); 1978 *pprog = prog; 1979 } 1980 } 1981 1982 /* get the count of the regs that are used to pass arguments */ 1983 static int get_nr_used_regs(const struct btf_func_model *m) 1984 { 1985 int i, arg_regs, nr_used_regs = 0; 1986 1987 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) { 1988 arg_regs = (m->arg_size[i] + 7) / 8; 1989 if (nr_used_regs + arg_regs <= 6) 1990 nr_used_regs += arg_regs; 1991 1992 if (nr_used_regs >= 6) 1993 break; 1994 } 1995 1996 return nr_used_regs; 1997 } 1998 1999 static void save_args(const struct btf_func_model *m, u8 **prog, 2000 int stack_size, bool for_call_origin) 2001 { 2002 int arg_regs, first_off = 0, nr_regs = 0, nr_stack_slots = 0; 2003 int i, j; 2004 2005 /* Store function arguments to stack. 2006 * For a function that accepts two pointers the sequence will be: 2007 * mov QWORD PTR [rbp-0x10],rdi 2008 * mov QWORD PTR [rbp-0x8],rsi 2009 */ 2010 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) { 2011 arg_regs = (m->arg_size[i] + 7) / 8; 2012 2013 /* According to the research of Yonghong, struct members 2014 * should be all in register or all on the stack. 2015 * Meanwhile, the compiler will pass the argument on regs 2016 * if the remaining regs can hold the argument. 2017 * 2018 * Disorder of the args can happen. For example: 2019 * 2020 * struct foo_struct { 2021 * long a; 2022 * int b; 2023 * }; 2024 * int foo(char, char, char, char, char, struct foo_struct, 2025 * char); 2026 * 2027 * the arg1-5,arg7 will be passed by regs, and arg6 will 2028 * by stack. 2029 */ 2030 if (nr_regs + arg_regs > 6) { 2031 /* copy function arguments from origin stack frame 2032 * into current stack frame. 2033 * 2034 * The starting address of the arguments on-stack 2035 * is: 2036 * rbp + 8(push rbp) + 2037 * 8(return addr of origin call) + 2038 * 8(return addr of the caller) 2039 * which means: rbp + 24 2040 */ 2041 for (j = 0; j < arg_regs; j++) { 2042 emit_ldx(prog, BPF_DW, BPF_REG_0, BPF_REG_FP, 2043 nr_stack_slots * 8 + 0x18); 2044 emit_stx(prog, BPF_DW, BPF_REG_FP, BPF_REG_0, 2045 -stack_size); 2046 2047 if (!nr_stack_slots) 2048 first_off = stack_size; 2049 stack_size -= 8; 2050 nr_stack_slots++; 2051 } 2052 } else { 2053 /* Only copy the arguments on-stack to current 2054 * 'stack_size' and ignore the regs, used to 2055 * prepare the arguments on-stack for orign call. 2056 */ 2057 if (for_call_origin) { 2058 nr_regs += arg_regs; 2059 continue; 2060 } 2061 2062 /* copy the arguments from regs into stack */ 2063 for (j = 0; j < arg_regs; j++) { 2064 emit_stx(prog, BPF_DW, BPF_REG_FP, 2065 nr_regs == 5 ? X86_REG_R9 : BPF_REG_1 + nr_regs, 2066 -stack_size); 2067 stack_size -= 8; 2068 nr_regs++; 2069 } 2070 } 2071 } 2072 2073 clean_stack_garbage(m, prog, nr_stack_slots, first_off); 2074 } 2075 2076 static void restore_regs(const struct btf_func_model *m, u8 **prog, 2077 int stack_size) 2078 { 2079 int i, j, arg_regs, nr_regs = 0; 2080 2081 /* Restore function arguments from stack. 2082 * For a function that accepts two pointers the sequence will be: 2083 * EMIT4(0x48, 0x8B, 0x7D, 0xF0); mov rdi,QWORD PTR [rbp-0x10] 2084 * EMIT4(0x48, 0x8B, 0x75, 0xF8); mov rsi,QWORD PTR [rbp-0x8] 2085 * 2086 * The logic here is similar to what we do in save_args() 2087 */ 2088 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) { 2089 arg_regs = (m->arg_size[i] + 7) / 8; 2090 if (nr_regs + arg_regs <= 6) { 2091 for (j = 0; j < arg_regs; j++) { 2092 emit_ldx(prog, BPF_DW, 2093 nr_regs == 5 ? X86_REG_R9 : BPF_REG_1 + nr_regs, 2094 BPF_REG_FP, 2095 -stack_size); 2096 stack_size -= 8; 2097 nr_regs++; 2098 } 2099 } else { 2100 stack_size -= 8 * arg_regs; 2101 } 2102 2103 if (nr_regs >= 6) 2104 break; 2105 } 2106 } 2107 2108 static int invoke_bpf_prog(const struct btf_func_model *m, u8 **pprog, 2109 struct bpf_tramp_link *l, int stack_size, 2110 int run_ctx_off, bool save_ret) 2111 { 2112 u8 *prog = *pprog; 2113 u8 *jmp_insn; 2114 int ctx_cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie); 2115 struct bpf_prog *p = l->link.prog; 2116 u64 cookie = l->cookie; 2117 2118 /* mov rdi, cookie */ 2119 emit_mov_imm64(&prog, BPF_REG_1, (long) cookie >> 32, (u32) (long) cookie); 2120 2121 /* Prepare struct bpf_tramp_run_ctx. 2122 * 2123 * bpf_tramp_run_ctx is already preserved by 2124 * arch_prepare_bpf_trampoline(). 2125 * 2126 * mov QWORD PTR [rbp - run_ctx_off + ctx_cookie_off], rdi 2127 */ 2128 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_1, -run_ctx_off + ctx_cookie_off); 2129 2130 /* arg1: mov rdi, progs[i] */ 2131 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p); 2132 /* arg2: lea rsi, [rbp - ctx_cookie_off] */ 2133 if (!is_imm8(-run_ctx_off)) 2134 EMIT3_off32(0x48, 0x8D, 0xB5, -run_ctx_off); 2135 else 2136 EMIT4(0x48, 0x8D, 0x75, -run_ctx_off); 2137 2138 if (emit_rsb_call(&prog, bpf_trampoline_enter(p), prog)) 2139 return -EINVAL; 2140 /* remember prog start time returned by __bpf_prog_enter */ 2141 emit_mov_reg(&prog, true, BPF_REG_6, BPF_REG_0); 2142 2143 /* if (__bpf_prog_enter*(prog) == 0) 2144 * goto skip_exec_of_prog; 2145 */ 2146 EMIT3(0x48, 0x85, 0xC0); /* test rax,rax */ 2147 /* emit 2 nops that will be replaced with JE insn */ 2148 jmp_insn = prog; 2149 emit_nops(&prog, 2); 2150 2151 /* arg1: lea rdi, [rbp - stack_size] */ 2152 if (!is_imm8(-stack_size)) 2153 EMIT3_off32(0x48, 0x8D, 0xBD, -stack_size); 2154 else 2155 EMIT4(0x48, 0x8D, 0x7D, -stack_size); 2156 /* arg2: progs[i]->insnsi for interpreter */ 2157 if (!p->jited) 2158 emit_mov_imm64(&prog, BPF_REG_2, 2159 (long) p->insnsi >> 32, 2160 (u32) (long) p->insnsi); 2161 /* call JITed bpf program or interpreter */ 2162 if (emit_rsb_call(&prog, p->bpf_func, prog)) 2163 return -EINVAL; 2164 2165 /* 2166 * BPF_TRAMP_MODIFY_RETURN trampolines can modify the return 2167 * of the previous call which is then passed on the stack to 2168 * the next BPF program. 2169 * 2170 * BPF_TRAMP_FENTRY trampoline may need to return the return 2171 * value of BPF_PROG_TYPE_STRUCT_OPS prog. 2172 */ 2173 if (save_ret) 2174 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); 2175 2176 /* replace 2 nops with JE insn, since jmp target is known */ 2177 jmp_insn[0] = X86_JE; 2178 jmp_insn[1] = prog - jmp_insn - 2; 2179 2180 /* arg1: mov rdi, progs[i] */ 2181 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p); 2182 /* arg2: mov rsi, rbx <- start time in nsec */ 2183 emit_mov_reg(&prog, true, BPF_REG_2, BPF_REG_6); 2184 /* arg3: lea rdx, [rbp - run_ctx_off] */ 2185 if (!is_imm8(-run_ctx_off)) 2186 EMIT3_off32(0x48, 0x8D, 0x95, -run_ctx_off); 2187 else 2188 EMIT4(0x48, 0x8D, 0x55, -run_ctx_off); 2189 if (emit_rsb_call(&prog, bpf_trampoline_exit(p), prog)) 2190 return -EINVAL; 2191 2192 *pprog = prog; 2193 return 0; 2194 } 2195 2196 static void emit_align(u8 **pprog, u32 align) 2197 { 2198 u8 *target, *prog = *pprog; 2199 2200 target = PTR_ALIGN(prog, align); 2201 if (target != prog) 2202 emit_nops(&prog, target - prog); 2203 2204 *pprog = prog; 2205 } 2206 2207 static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond) 2208 { 2209 u8 *prog = *pprog; 2210 s64 offset; 2211 2212 offset = func - (ip + 2 + 4); 2213 if (!is_simm32(offset)) { 2214 pr_err("Target %p is out of range\n", func); 2215 return -EINVAL; 2216 } 2217 EMIT2_off32(0x0F, jmp_cond + 0x10, offset); 2218 *pprog = prog; 2219 return 0; 2220 } 2221 2222 static int invoke_bpf(const struct btf_func_model *m, u8 **pprog, 2223 struct bpf_tramp_links *tl, int stack_size, 2224 int run_ctx_off, bool save_ret) 2225 { 2226 int i; 2227 u8 *prog = *pprog; 2228 2229 for (i = 0; i < tl->nr_links; i++) { 2230 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size, 2231 run_ctx_off, save_ret)) 2232 return -EINVAL; 2233 } 2234 *pprog = prog; 2235 return 0; 2236 } 2237 2238 static int invoke_bpf_mod_ret(const struct btf_func_model *m, u8 **pprog, 2239 struct bpf_tramp_links *tl, int stack_size, 2240 int run_ctx_off, u8 **branches) 2241 { 2242 u8 *prog = *pprog; 2243 int i; 2244 2245 /* The first fmod_ret program will receive a garbage return value. 2246 * Set this to 0 to avoid confusing the program. 2247 */ 2248 emit_mov_imm32(&prog, false, BPF_REG_0, 0); 2249 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); 2250 for (i = 0; i < tl->nr_links; i++) { 2251 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size, run_ctx_off, true)) 2252 return -EINVAL; 2253 2254 /* mod_ret prog stored return value into [rbp - 8]. Emit: 2255 * if (*(u64 *)(rbp - 8) != 0) 2256 * goto do_fexit; 2257 */ 2258 /* cmp QWORD PTR [rbp - 0x8], 0x0 */ 2259 EMIT4(0x48, 0x83, 0x7d, 0xf8); EMIT1(0x00); 2260 2261 /* Save the location of the branch and Generate 6 nops 2262 * (4 bytes for an offset and 2 bytes for the jump) These nops 2263 * are replaced with a conditional jump once do_fexit (i.e. the 2264 * start of the fexit invocation) is finalized. 2265 */ 2266 branches[i] = prog; 2267 emit_nops(&prog, 4 + 2); 2268 } 2269 2270 *pprog = prog; 2271 return 0; 2272 } 2273 2274 /* Example: 2275 * __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev); 2276 * its 'struct btf_func_model' will be nr_args=2 2277 * The assembly code when eth_type_trans is executing after trampoline: 2278 * 2279 * push rbp 2280 * mov rbp, rsp 2281 * sub rsp, 16 // space for skb and dev 2282 * push rbx // temp regs to pass start time 2283 * mov qword ptr [rbp - 16], rdi // save skb pointer to stack 2284 * mov qword ptr [rbp - 8], rsi // save dev pointer to stack 2285 * call __bpf_prog_enter // rcu_read_lock and preempt_disable 2286 * mov rbx, rax // remember start time in bpf stats are enabled 2287 * lea rdi, [rbp - 16] // R1==ctx of bpf prog 2288 * call addr_of_jited_FENTRY_prog 2289 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off 2290 * mov rsi, rbx // prog start time 2291 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math 2292 * mov rdi, qword ptr [rbp - 16] // restore skb pointer from stack 2293 * mov rsi, qword ptr [rbp - 8] // restore dev pointer from stack 2294 * pop rbx 2295 * leave 2296 * ret 2297 * 2298 * eth_type_trans has 5 byte nop at the beginning. These 5 bytes will be 2299 * replaced with 'call generated_bpf_trampoline'. When it returns 2300 * eth_type_trans will continue executing with original skb and dev pointers. 2301 * 2302 * The assembly code when eth_type_trans is called from trampoline: 2303 * 2304 * push rbp 2305 * mov rbp, rsp 2306 * sub rsp, 24 // space for skb, dev, return value 2307 * push rbx // temp regs to pass start time 2308 * mov qword ptr [rbp - 24], rdi // save skb pointer to stack 2309 * mov qword ptr [rbp - 16], rsi // save dev pointer to stack 2310 * call __bpf_prog_enter // rcu_read_lock and preempt_disable 2311 * mov rbx, rax // remember start time if bpf stats are enabled 2312 * lea rdi, [rbp - 24] // R1==ctx of bpf prog 2313 * call addr_of_jited_FENTRY_prog // bpf prog can access skb and dev 2314 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off 2315 * mov rsi, rbx // prog start time 2316 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math 2317 * mov rdi, qword ptr [rbp - 24] // restore skb pointer from stack 2318 * mov rsi, qword ptr [rbp - 16] // restore dev pointer from stack 2319 * call eth_type_trans+5 // execute body of eth_type_trans 2320 * mov qword ptr [rbp - 8], rax // save return value 2321 * call __bpf_prog_enter // rcu_read_lock and preempt_disable 2322 * mov rbx, rax // remember start time in bpf stats are enabled 2323 * lea rdi, [rbp - 24] // R1==ctx of bpf prog 2324 * call addr_of_jited_FEXIT_prog // bpf prog can access skb, dev, return value 2325 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off 2326 * mov rsi, rbx // prog start time 2327 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math 2328 * mov rax, qword ptr [rbp - 8] // restore eth_type_trans's return value 2329 * pop rbx 2330 * leave 2331 * add rsp, 8 // skip eth_type_trans's frame 2332 * ret // return to its caller 2333 */ 2334 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *image_end, 2335 const struct btf_func_model *m, u32 flags, 2336 struct bpf_tramp_links *tlinks, 2337 void *func_addr) 2338 { 2339 int i, ret, nr_regs = m->nr_args, stack_size = 0; 2340 int regs_off, nregs_off, ip_off, run_ctx_off, arg_stack_off, rbx_off; 2341 struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY]; 2342 struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT]; 2343 struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN]; 2344 void *orig_call = func_addr; 2345 u8 **branches = NULL; 2346 u8 *prog; 2347 bool save_ret; 2348 2349 /* extra registers for struct arguments */ 2350 for (i = 0; i < m->nr_args; i++) 2351 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG) 2352 nr_regs += (m->arg_size[i] + 7) / 8 - 1; 2353 2354 /* x86-64 supports up to MAX_BPF_FUNC_ARGS arguments. 1-6 2355 * are passed through regs, the remains are through stack. 2356 */ 2357 if (nr_regs > MAX_BPF_FUNC_ARGS) 2358 return -ENOTSUPP; 2359 2360 /* Generated trampoline stack layout: 2361 * 2362 * RBP + 8 [ return address ] 2363 * RBP + 0 [ RBP ] 2364 * 2365 * RBP - 8 [ return value ] BPF_TRAMP_F_CALL_ORIG or 2366 * BPF_TRAMP_F_RET_FENTRY_RET flags 2367 * 2368 * [ reg_argN ] always 2369 * [ ... ] 2370 * RBP - regs_off [ reg_arg1 ] program's ctx pointer 2371 * 2372 * RBP - nregs_off [ regs count ] always 2373 * 2374 * RBP - ip_off [ traced function ] BPF_TRAMP_F_IP_ARG flag 2375 * 2376 * RBP - rbx_off [ rbx value ] always 2377 * 2378 * RBP - run_ctx_off [ bpf_tramp_run_ctx ] 2379 * 2380 * [ stack_argN ] BPF_TRAMP_F_CALL_ORIG 2381 * [ ... ] 2382 * [ stack_arg2 ] 2383 * RBP - arg_stack_off [ stack_arg1 ] 2384 */ 2385 2386 /* room for return value of orig_call or fentry prog */ 2387 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET); 2388 if (save_ret) 2389 stack_size += 8; 2390 2391 stack_size += nr_regs * 8; 2392 regs_off = stack_size; 2393 2394 /* regs count */ 2395 stack_size += 8; 2396 nregs_off = stack_size; 2397 2398 if (flags & BPF_TRAMP_F_IP_ARG) 2399 stack_size += 8; /* room for IP address argument */ 2400 2401 ip_off = stack_size; 2402 2403 stack_size += 8; 2404 rbx_off = stack_size; 2405 2406 stack_size += (sizeof(struct bpf_tramp_run_ctx) + 7) & ~0x7; 2407 run_ctx_off = stack_size; 2408 2409 if (nr_regs > 6 && (flags & BPF_TRAMP_F_CALL_ORIG)) { 2410 /* the space that used to pass arguments on-stack */ 2411 stack_size += (nr_regs - get_nr_used_regs(m)) * 8; 2412 /* make sure the stack pointer is 16-byte aligned if we 2413 * need pass arguments on stack, which means 2414 * [stack_size + 8(rbp) + 8(rip) + 8(origin rip)] 2415 * should be 16-byte aligned. Following code depend on 2416 * that stack_size is already 8-byte aligned. 2417 */ 2418 stack_size += (stack_size % 16) ? 0 : 8; 2419 } 2420 2421 arg_stack_off = stack_size; 2422 2423 if (flags & BPF_TRAMP_F_SKIP_FRAME) { 2424 /* skip patched call instruction and point orig_call to actual 2425 * body of the kernel function. 2426 */ 2427 if (is_endbr(*(u32 *)orig_call)) 2428 orig_call += ENDBR_INSN_SIZE; 2429 orig_call += X86_PATCH_SIZE; 2430 } 2431 2432 prog = image; 2433 2434 EMIT_ENDBR(); 2435 /* 2436 * This is the direct-call trampoline, as such it needs accounting 2437 * for the __fentry__ call. 2438 */ 2439 x86_call_depth_emit_accounting(&prog, NULL); 2440 EMIT1(0x55); /* push rbp */ 2441 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */ 2442 if (!is_imm8(stack_size)) 2443 /* sub rsp, stack_size */ 2444 EMIT3_off32(0x48, 0x81, 0xEC, stack_size); 2445 else 2446 /* sub rsp, stack_size */ 2447 EMIT4(0x48, 0x83, 0xEC, stack_size); 2448 /* mov QWORD PTR [rbp - rbx_off], rbx */ 2449 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_6, -rbx_off); 2450 2451 /* Store number of argument registers of the traced function: 2452 * mov rax, nr_regs 2453 * mov QWORD PTR [rbp - nregs_off], rax 2454 */ 2455 emit_mov_imm64(&prog, BPF_REG_0, 0, (u32) nr_regs); 2456 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -nregs_off); 2457 2458 if (flags & BPF_TRAMP_F_IP_ARG) { 2459 /* Store IP address of the traced function: 2460 * movabsq rax, func_addr 2461 * mov QWORD PTR [rbp - ip_off], rax 2462 */ 2463 emit_mov_imm64(&prog, BPF_REG_0, (long) func_addr >> 32, (u32) (long) func_addr); 2464 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -ip_off); 2465 } 2466 2467 save_args(m, &prog, regs_off, false); 2468 2469 if (flags & BPF_TRAMP_F_CALL_ORIG) { 2470 /* arg1: mov rdi, im */ 2471 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im); 2472 if (emit_rsb_call(&prog, __bpf_tramp_enter, prog)) { 2473 ret = -EINVAL; 2474 goto cleanup; 2475 } 2476 } 2477 2478 if (fentry->nr_links) 2479 if (invoke_bpf(m, &prog, fentry, regs_off, run_ctx_off, 2480 flags & BPF_TRAMP_F_RET_FENTRY_RET)) 2481 return -EINVAL; 2482 2483 if (fmod_ret->nr_links) { 2484 branches = kcalloc(fmod_ret->nr_links, sizeof(u8 *), 2485 GFP_KERNEL); 2486 if (!branches) 2487 return -ENOMEM; 2488 2489 if (invoke_bpf_mod_ret(m, &prog, fmod_ret, regs_off, 2490 run_ctx_off, branches)) { 2491 ret = -EINVAL; 2492 goto cleanup; 2493 } 2494 } 2495 2496 if (flags & BPF_TRAMP_F_CALL_ORIG) { 2497 restore_regs(m, &prog, regs_off); 2498 save_args(m, &prog, arg_stack_off, true); 2499 2500 if (flags & BPF_TRAMP_F_ORIG_STACK) { 2501 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, 8); 2502 EMIT2(0xff, 0xd0); /* call *rax */ 2503 } else { 2504 /* call original function */ 2505 if (emit_rsb_call(&prog, orig_call, prog)) { 2506 ret = -EINVAL; 2507 goto cleanup; 2508 } 2509 } 2510 /* remember return value in a stack for bpf prog to access */ 2511 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); 2512 im->ip_after_call = prog; 2513 memcpy(prog, x86_nops[5], X86_PATCH_SIZE); 2514 prog += X86_PATCH_SIZE; 2515 } 2516 2517 if (fmod_ret->nr_links) { 2518 /* From Intel 64 and IA-32 Architectures Optimization 2519 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler 2520 * Coding Rule 11: All branch targets should be 16-byte 2521 * aligned. 2522 */ 2523 emit_align(&prog, 16); 2524 /* Update the branches saved in invoke_bpf_mod_ret with the 2525 * aligned address of do_fexit. 2526 */ 2527 for (i = 0; i < fmod_ret->nr_links; i++) 2528 emit_cond_near_jump(&branches[i], prog, branches[i], 2529 X86_JNE); 2530 } 2531 2532 if (fexit->nr_links) 2533 if (invoke_bpf(m, &prog, fexit, regs_off, run_ctx_off, false)) { 2534 ret = -EINVAL; 2535 goto cleanup; 2536 } 2537 2538 if (flags & BPF_TRAMP_F_RESTORE_REGS) 2539 restore_regs(m, &prog, regs_off); 2540 2541 /* This needs to be done regardless. If there were fmod_ret programs, 2542 * the return value is only updated on the stack and still needs to be 2543 * restored to R0. 2544 */ 2545 if (flags & BPF_TRAMP_F_CALL_ORIG) { 2546 im->ip_epilogue = prog; 2547 /* arg1: mov rdi, im */ 2548 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im); 2549 if (emit_rsb_call(&prog, __bpf_tramp_exit, prog)) { 2550 ret = -EINVAL; 2551 goto cleanup; 2552 } 2553 } 2554 /* restore return value of orig_call or fentry prog back into RAX */ 2555 if (save_ret) 2556 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, -8); 2557 2558 emit_ldx(&prog, BPF_DW, BPF_REG_6, BPF_REG_FP, -rbx_off); 2559 EMIT1(0xC9); /* leave */ 2560 if (flags & BPF_TRAMP_F_SKIP_FRAME) 2561 /* skip our return address and return to parent */ 2562 EMIT4(0x48, 0x83, 0xC4, 8); /* add rsp, 8 */ 2563 emit_return(&prog, prog); 2564 /* Make sure the trampoline generation logic doesn't overflow */ 2565 if (WARN_ON_ONCE(prog > (u8 *)image_end - BPF_INSN_SAFETY)) { 2566 ret = -EFAULT; 2567 goto cleanup; 2568 } 2569 ret = prog - (u8 *)image; 2570 2571 cleanup: 2572 kfree(branches); 2573 return ret; 2574 } 2575 2576 static int emit_bpf_dispatcher(u8 **pprog, int a, int b, s64 *progs, u8 *image, u8 *buf) 2577 { 2578 u8 *jg_reloc, *prog = *pprog; 2579 int pivot, err, jg_bytes = 1; 2580 s64 jg_offset; 2581 2582 if (a == b) { 2583 /* Leaf node of recursion, i.e. not a range of indices 2584 * anymore. 2585 */ 2586 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */ 2587 if (!is_simm32(progs[a])) 2588 return -1; 2589 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), 2590 progs[a]); 2591 err = emit_cond_near_jump(&prog, /* je func */ 2592 (void *)progs[a], image + (prog - buf), 2593 X86_JE); 2594 if (err) 2595 return err; 2596 2597 emit_indirect_jump(&prog, 2 /* rdx */, image + (prog - buf)); 2598 2599 *pprog = prog; 2600 return 0; 2601 } 2602 2603 /* Not a leaf node, so we pivot, and recursively descend into 2604 * the lower and upper ranges. 2605 */ 2606 pivot = (b - a) / 2; 2607 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */ 2608 if (!is_simm32(progs[a + pivot])) 2609 return -1; 2610 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]); 2611 2612 if (pivot > 2) { /* jg upper_part */ 2613 /* Require near jump. */ 2614 jg_bytes = 4; 2615 EMIT2_off32(0x0F, X86_JG + 0x10, 0); 2616 } else { 2617 EMIT2(X86_JG, 0); 2618 } 2619 jg_reloc = prog; 2620 2621 err = emit_bpf_dispatcher(&prog, a, a + pivot, /* emit lower_part */ 2622 progs, image, buf); 2623 if (err) 2624 return err; 2625 2626 /* From Intel 64 and IA-32 Architectures Optimization 2627 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler 2628 * Coding Rule 11: All branch targets should be 16-byte 2629 * aligned. 2630 */ 2631 emit_align(&prog, 16); 2632 jg_offset = prog - jg_reloc; 2633 emit_code(jg_reloc - jg_bytes, jg_offset, jg_bytes); 2634 2635 err = emit_bpf_dispatcher(&prog, a + pivot + 1, /* emit upper_part */ 2636 b, progs, image, buf); 2637 if (err) 2638 return err; 2639 2640 *pprog = prog; 2641 return 0; 2642 } 2643 2644 static int cmp_ips(const void *a, const void *b) 2645 { 2646 const s64 *ipa = a; 2647 const s64 *ipb = b; 2648 2649 if (*ipa > *ipb) 2650 return 1; 2651 if (*ipa < *ipb) 2652 return -1; 2653 return 0; 2654 } 2655 2656 int arch_prepare_bpf_dispatcher(void *image, void *buf, s64 *funcs, int num_funcs) 2657 { 2658 u8 *prog = buf; 2659 2660 sort(funcs, num_funcs, sizeof(funcs[0]), cmp_ips, NULL); 2661 return emit_bpf_dispatcher(&prog, 0, num_funcs - 1, funcs, image, buf); 2662 } 2663 2664 struct x64_jit_data { 2665 struct bpf_binary_header *rw_header; 2666 struct bpf_binary_header *header; 2667 int *addrs; 2668 u8 *image; 2669 int proglen; 2670 struct jit_context ctx; 2671 }; 2672 2673 #define MAX_PASSES 20 2674 #define PADDING_PASSES (MAX_PASSES - 5) 2675 2676 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog) 2677 { 2678 struct bpf_binary_header *rw_header = NULL; 2679 struct bpf_binary_header *header = NULL; 2680 struct bpf_prog *tmp, *orig_prog = prog; 2681 struct x64_jit_data *jit_data; 2682 int proglen, oldproglen = 0; 2683 struct jit_context ctx = {}; 2684 bool tmp_blinded = false; 2685 bool extra_pass = false; 2686 bool padding = false; 2687 u8 *rw_image = NULL; 2688 u8 *image = NULL; 2689 int *addrs; 2690 int pass; 2691 int i; 2692 2693 if (!prog->jit_requested) 2694 return orig_prog; 2695 2696 tmp = bpf_jit_blind_constants(prog); 2697 /* 2698 * If blinding was requested and we failed during blinding, 2699 * we must fall back to the interpreter. 2700 */ 2701 if (IS_ERR(tmp)) 2702 return orig_prog; 2703 if (tmp != prog) { 2704 tmp_blinded = true; 2705 prog = tmp; 2706 } 2707 2708 jit_data = prog->aux->jit_data; 2709 if (!jit_data) { 2710 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL); 2711 if (!jit_data) { 2712 prog = orig_prog; 2713 goto out; 2714 } 2715 prog->aux->jit_data = jit_data; 2716 } 2717 addrs = jit_data->addrs; 2718 if (addrs) { 2719 ctx = jit_data->ctx; 2720 oldproglen = jit_data->proglen; 2721 image = jit_data->image; 2722 header = jit_data->header; 2723 rw_header = jit_data->rw_header; 2724 rw_image = (void *)rw_header + ((void *)image - (void *)header); 2725 extra_pass = true; 2726 padding = true; 2727 goto skip_init_addrs; 2728 } 2729 addrs = kvmalloc_array(prog->len + 1, sizeof(*addrs), GFP_KERNEL); 2730 if (!addrs) { 2731 prog = orig_prog; 2732 goto out_addrs; 2733 } 2734 2735 /* 2736 * Before first pass, make a rough estimation of addrs[] 2737 * each BPF instruction is translated to less than 64 bytes 2738 */ 2739 for (proglen = 0, i = 0; i <= prog->len; i++) { 2740 proglen += 64; 2741 addrs[i] = proglen; 2742 } 2743 ctx.cleanup_addr = proglen; 2744 skip_init_addrs: 2745 2746 /* 2747 * JITed image shrinks with every pass and the loop iterates 2748 * until the image stops shrinking. Very large BPF programs 2749 * may converge on the last pass. In such case do one more 2750 * pass to emit the final image. 2751 */ 2752 for (pass = 0; pass < MAX_PASSES || image; pass++) { 2753 if (!padding && pass >= PADDING_PASSES) 2754 padding = true; 2755 proglen = do_jit(prog, addrs, image, rw_image, oldproglen, &ctx, padding); 2756 if (proglen <= 0) { 2757 out_image: 2758 image = NULL; 2759 if (header) { 2760 bpf_arch_text_copy(&header->size, &rw_header->size, 2761 sizeof(rw_header->size)); 2762 bpf_jit_binary_pack_free(header, rw_header); 2763 } 2764 /* Fall back to interpreter mode */ 2765 prog = orig_prog; 2766 if (extra_pass) { 2767 prog->bpf_func = NULL; 2768 prog->jited = 0; 2769 prog->jited_len = 0; 2770 } 2771 goto out_addrs; 2772 } 2773 if (image) { 2774 if (proglen != oldproglen) { 2775 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n", 2776 proglen, oldproglen); 2777 goto out_image; 2778 } 2779 break; 2780 } 2781 if (proglen == oldproglen) { 2782 /* 2783 * The number of entries in extable is the number of BPF_LDX 2784 * insns that access kernel memory via "pointer to BTF type". 2785 * The verifier changed their opcode from LDX|MEM|size 2786 * to LDX|PROBE_MEM|size to make JITing easier. 2787 */ 2788 u32 align = __alignof__(struct exception_table_entry); 2789 u32 extable_size = prog->aux->num_exentries * 2790 sizeof(struct exception_table_entry); 2791 2792 /* allocate module memory for x86 insns and extable */ 2793 header = bpf_jit_binary_pack_alloc(roundup(proglen, align) + extable_size, 2794 &image, align, &rw_header, &rw_image, 2795 jit_fill_hole); 2796 if (!header) { 2797 prog = orig_prog; 2798 goto out_addrs; 2799 } 2800 prog->aux->extable = (void *) image + roundup(proglen, align); 2801 } 2802 oldproglen = proglen; 2803 cond_resched(); 2804 } 2805 2806 if (bpf_jit_enable > 1) 2807 bpf_jit_dump(prog->len, proglen, pass + 1, rw_image); 2808 2809 if (image) { 2810 if (!prog->is_func || extra_pass) { 2811 /* 2812 * bpf_jit_binary_pack_finalize fails in two scenarios: 2813 * 1) header is not pointing to proper module memory; 2814 * 2) the arch doesn't support bpf_arch_text_copy(). 2815 * 2816 * Both cases are serious bugs and justify WARN_ON. 2817 */ 2818 if (WARN_ON(bpf_jit_binary_pack_finalize(prog, header, rw_header))) { 2819 /* header has been freed */ 2820 header = NULL; 2821 goto out_image; 2822 } 2823 2824 bpf_tail_call_direct_fixup(prog); 2825 } else { 2826 jit_data->addrs = addrs; 2827 jit_data->ctx = ctx; 2828 jit_data->proglen = proglen; 2829 jit_data->image = image; 2830 jit_data->header = header; 2831 jit_data->rw_header = rw_header; 2832 } 2833 prog->bpf_func = (void *)image; 2834 prog->jited = 1; 2835 prog->jited_len = proglen; 2836 } else { 2837 prog = orig_prog; 2838 } 2839 2840 if (!image || !prog->is_func || extra_pass) { 2841 if (image) 2842 bpf_prog_fill_jited_linfo(prog, addrs + 1); 2843 out_addrs: 2844 kvfree(addrs); 2845 kfree(jit_data); 2846 prog->aux->jit_data = NULL; 2847 } 2848 out: 2849 if (tmp_blinded) 2850 bpf_jit_prog_release_other(prog, prog == orig_prog ? 2851 tmp : orig_prog); 2852 return prog; 2853 } 2854 2855 bool bpf_jit_supports_kfunc_call(void) 2856 { 2857 return true; 2858 } 2859 2860 void *bpf_arch_text_copy(void *dst, void *src, size_t len) 2861 { 2862 if (text_poke_copy(dst, src, len) == NULL) 2863 return ERR_PTR(-EINVAL); 2864 return dst; 2865 } 2866 2867 /* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */ 2868 bool bpf_jit_supports_subprog_tailcalls(void) 2869 { 2870 return true; 2871 } 2872 2873 void bpf_jit_free(struct bpf_prog *prog) 2874 { 2875 if (prog->jited) { 2876 struct x64_jit_data *jit_data = prog->aux->jit_data; 2877 struct bpf_binary_header *hdr; 2878 2879 /* 2880 * If we fail the final pass of JIT (from jit_subprogs), 2881 * the program may not be finalized yet. Call finalize here 2882 * before freeing it. 2883 */ 2884 if (jit_data) { 2885 bpf_jit_binary_pack_finalize(prog, jit_data->header, 2886 jit_data->rw_header); 2887 kvfree(jit_data->addrs); 2888 kfree(jit_data); 2889 } 2890 hdr = bpf_jit_binary_pack_hdr(prog); 2891 bpf_jit_binary_pack_free(hdr, NULL); 2892 WARN_ON_ONCE(!bpf_prog_kallsyms_verify_off(prog)); 2893 } 2894 2895 bpf_prog_unlock_free(prog); 2896 } 2897