xref: /openbmc/linux/arch/x86/mm/tlb.c (revision 1b39e7607144337d752f36c2068ed79447462f99)
1  // SPDX-License-Identifier: GPL-2.0-only
2  #include <linux/init.h>
3  
4  #include <linux/mm.h>
5  #include <linux/spinlock.h>
6  #include <linux/smp.h>
7  #include <linux/interrupt.h>
8  #include <linux/export.h>
9  #include <linux/cpu.h>
10  #include <linux/debugfs.h>
11  #include <linux/sched/smt.h>
12  #include <linux/task_work.h>
13  
14  #include <asm/tlbflush.h>
15  #include <asm/mmu_context.h>
16  #include <asm/nospec-branch.h>
17  #include <asm/cache.h>
18  #include <asm/cacheflush.h>
19  #include <asm/apic.h>
20  #include <asm/perf_event.h>
21  
22  #include "mm_internal.h"
23  
24  #ifdef CONFIG_PARAVIRT
25  # define STATIC_NOPV
26  #else
27  # define STATIC_NOPV			static
28  # define __flush_tlb_local		native_flush_tlb_local
29  # define __flush_tlb_global		native_flush_tlb_global
30  # define __flush_tlb_one_user(addr)	native_flush_tlb_one_user(addr)
31  # define __flush_tlb_multi(msk, info)	native_flush_tlb_multi(msk, info)
32  #endif
33  
34  /*
35   *	TLB flushing, formerly SMP-only
36   *		c/o Linus Torvalds.
37   *
38   *	These mean you can really definitely utterly forget about
39   *	writing to user space from interrupts. (Its not allowed anyway).
40   *
41   *	Optimizations Manfred Spraul <manfred@colorfullife.com>
42   *
43   *	More scalable flush, from Andi Kleen
44   *
45   *	Implement flush IPI by CALL_FUNCTION_VECTOR, Alex Shi
46   */
47  
48  /*
49   * Bits to mangle the TIF_SPEC_* state into the mm pointer which is
50   * stored in cpu_tlb_state.last_user_mm_spec.
51   */
52  #define LAST_USER_MM_IBPB	0x1UL
53  #define LAST_USER_MM_L1D_FLUSH	0x2UL
54  #define LAST_USER_MM_SPEC_MASK	(LAST_USER_MM_IBPB | LAST_USER_MM_L1D_FLUSH)
55  
56  /* Bits to set when tlbstate and flush is (re)initialized */
57  #define LAST_USER_MM_INIT	LAST_USER_MM_IBPB
58  
59  /*
60   * The x86 feature is called PCID (Process Context IDentifier). It is similar
61   * to what is traditionally called ASID on the RISC processors.
62   *
63   * We don't use the traditional ASID implementation, where each process/mm gets
64   * its own ASID and flush/restart when we run out of ASID space.
65   *
66   * Instead we have a small per-cpu array of ASIDs and cache the last few mm's
67   * that came by on this CPU, allowing cheaper switch_mm between processes on
68   * this CPU.
69   *
70   * We end up with different spaces for different things. To avoid confusion we
71   * use different names for each of them:
72   *
73   * ASID  - [0, TLB_NR_DYN_ASIDS-1]
74   *         the canonical identifier for an mm
75   *
76   * kPCID - [1, TLB_NR_DYN_ASIDS]
77   *         the value we write into the PCID part of CR3; corresponds to the
78   *         ASID+1, because PCID 0 is special.
79   *
80   * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS]
81   *         for KPTI each mm has two address spaces and thus needs two
82   *         PCID values, but we can still do with a single ASID denomination
83   *         for each mm. Corresponds to kPCID + 2048.
84   *
85   */
86  
87  /* There are 12 bits of space for ASIDS in CR3 */
88  #define CR3_HW_ASID_BITS		12
89  
90  /*
91   * When enabled, PAGE_TABLE_ISOLATION consumes a single bit for
92   * user/kernel switches
93   */
94  #ifdef CONFIG_PAGE_TABLE_ISOLATION
95  # define PTI_CONSUMED_PCID_BITS	1
96  #else
97  # define PTI_CONSUMED_PCID_BITS	0
98  #endif
99  
100  #define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
101  
102  /*
103   * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid.  -1 below to account
104   * for them being zero-based.  Another -1 is because PCID 0 is reserved for
105   * use by non-PCID-aware users.
106   */
107  #define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
108  
109  /*
110   * Given @asid, compute kPCID
111   */
112  static inline u16 kern_pcid(u16 asid)
113  {
114  	VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
115  
116  #ifdef CONFIG_PAGE_TABLE_ISOLATION
117  	/*
118  	 * Make sure that the dynamic ASID space does not conflict with the
119  	 * bit we are using to switch between user and kernel ASIDs.
120  	 */
121  	BUILD_BUG_ON(TLB_NR_DYN_ASIDS >= (1 << X86_CR3_PTI_PCID_USER_BIT));
122  
123  	/*
124  	 * The ASID being passed in here should have respected the
125  	 * MAX_ASID_AVAILABLE and thus never have the switch bit set.
126  	 */
127  	VM_WARN_ON_ONCE(asid & (1 << X86_CR3_PTI_PCID_USER_BIT));
128  #endif
129  	/*
130  	 * The dynamically-assigned ASIDs that get passed in are small
131  	 * (<TLB_NR_DYN_ASIDS).  They never have the high switch bit set,
132  	 * so do not bother to clear it.
133  	 *
134  	 * If PCID is on, ASID-aware code paths put the ASID+1 into the
135  	 * PCID bits.  This serves two purposes.  It prevents a nasty
136  	 * situation in which PCID-unaware code saves CR3, loads some other
137  	 * value (with PCID == 0), and then restores CR3, thus corrupting
138  	 * the TLB for ASID 0 if the saved ASID was nonzero.  It also means
139  	 * that any bugs involving loading a PCID-enabled CR3 with
140  	 * CR4.PCIDE off will trigger deterministically.
141  	 */
142  	return asid + 1;
143  }
144  
145  /*
146   * Given @asid, compute uPCID
147   */
148  static inline u16 user_pcid(u16 asid)
149  {
150  	u16 ret = kern_pcid(asid);
151  #ifdef CONFIG_PAGE_TABLE_ISOLATION
152  	ret |= 1 << X86_CR3_PTI_PCID_USER_BIT;
153  #endif
154  	return ret;
155  }
156  
157  static inline unsigned long build_cr3(pgd_t *pgd, u16 asid, unsigned long lam)
158  {
159  	unsigned long cr3 = __sme_pa(pgd) | lam;
160  
161  	if (static_cpu_has(X86_FEATURE_PCID)) {
162  		VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
163  		cr3 |= kern_pcid(asid);
164  	} else {
165  		VM_WARN_ON_ONCE(asid != 0);
166  	}
167  
168  	return cr3;
169  }
170  
171  static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid,
172  					      unsigned long lam)
173  {
174  	/*
175  	 * Use boot_cpu_has() instead of this_cpu_has() as this function
176  	 * might be called during early boot. This should work even after
177  	 * boot because all CPU's the have same capabilities:
178  	 */
179  	VM_WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_PCID));
180  	return build_cr3(pgd, asid, lam) | CR3_NOFLUSH;
181  }
182  
183  /*
184   * We get here when we do something requiring a TLB invalidation
185   * but could not go invalidate all of the contexts.  We do the
186   * necessary invalidation by clearing out the 'ctx_id' which
187   * forces a TLB flush when the context is loaded.
188   */
189  static void clear_asid_other(void)
190  {
191  	u16 asid;
192  
193  	/*
194  	 * This is only expected to be set if we have disabled
195  	 * kernel _PAGE_GLOBAL pages.
196  	 */
197  	if (!static_cpu_has(X86_FEATURE_PTI)) {
198  		WARN_ON_ONCE(1);
199  		return;
200  	}
201  
202  	for (asid = 0; asid < TLB_NR_DYN_ASIDS; asid++) {
203  		/* Do not need to flush the current asid */
204  		if (asid == this_cpu_read(cpu_tlbstate.loaded_mm_asid))
205  			continue;
206  		/*
207  		 * Make sure the next time we go to switch to
208  		 * this asid, we do a flush:
209  		 */
210  		this_cpu_write(cpu_tlbstate.ctxs[asid].ctx_id, 0);
211  	}
212  	this_cpu_write(cpu_tlbstate.invalidate_other, false);
213  }
214  
215  atomic64_t last_mm_ctx_id = ATOMIC64_INIT(1);
216  
217  
218  static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen,
219  			    u16 *new_asid, bool *need_flush)
220  {
221  	u16 asid;
222  
223  	if (!static_cpu_has(X86_FEATURE_PCID)) {
224  		*new_asid = 0;
225  		*need_flush = true;
226  		return;
227  	}
228  
229  	if (this_cpu_read(cpu_tlbstate.invalidate_other))
230  		clear_asid_other();
231  
232  	for (asid = 0; asid < TLB_NR_DYN_ASIDS; asid++) {
233  		if (this_cpu_read(cpu_tlbstate.ctxs[asid].ctx_id) !=
234  		    next->context.ctx_id)
235  			continue;
236  
237  		*new_asid = asid;
238  		*need_flush = (this_cpu_read(cpu_tlbstate.ctxs[asid].tlb_gen) <
239  			       next_tlb_gen);
240  		return;
241  	}
242  
243  	/*
244  	 * We don't currently own an ASID slot on this CPU.
245  	 * Allocate a slot.
246  	 */
247  	*new_asid = this_cpu_add_return(cpu_tlbstate.next_asid, 1) - 1;
248  	if (*new_asid >= TLB_NR_DYN_ASIDS) {
249  		*new_asid = 0;
250  		this_cpu_write(cpu_tlbstate.next_asid, 1);
251  	}
252  	*need_flush = true;
253  }
254  
255  /*
256   * Given an ASID, flush the corresponding user ASID.  We can delay this
257   * until the next time we switch to it.
258   *
259   * See SWITCH_TO_USER_CR3.
260   */
261  static inline void invalidate_user_asid(u16 asid)
262  {
263  	/* There is no user ASID if address space separation is off */
264  	if (!IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION))
265  		return;
266  
267  	/*
268  	 * We only have a single ASID if PCID is off and the CR3
269  	 * write will have flushed it.
270  	 */
271  	if (!cpu_feature_enabled(X86_FEATURE_PCID))
272  		return;
273  
274  	if (!static_cpu_has(X86_FEATURE_PTI))
275  		return;
276  
277  	__set_bit(kern_pcid(asid),
278  		  (unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask));
279  }
280  
281  static void load_new_mm_cr3(pgd_t *pgdir, u16 new_asid, unsigned long lam,
282  			    bool need_flush)
283  {
284  	unsigned long new_mm_cr3;
285  
286  	if (need_flush) {
287  		invalidate_user_asid(new_asid);
288  		new_mm_cr3 = build_cr3(pgdir, new_asid, lam);
289  	} else {
290  		new_mm_cr3 = build_cr3_noflush(pgdir, new_asid, lam);
291  	}
292  
293  	/*
294  	 * Caution: many callers of this function expect
295  	 * that load_cr3() is serializing and orders TLB
296  	 * fills with respect to the mm_cpumask writes.
297  	 */
298  	write_cr3(new_mm_cr3);
299  }
300  
301  void leave_mm(int cpu)
302  {
303  	struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
304  
305  	/*
306  	 * It's plausible that we're in lazy TLB mode while our mm is init_mm.
307  	 * If so, our callers still expect us to flush the TLB, but there
308  	 * aren't any user TLB entries in init_mm to worry about.
309  	 *
310  	 * This needs to happen before any other sanity checks due to
311  	 * intel_idle's shenanigans.
312  	 */
313  	if (loaded_mm == &init_mm)
314  		return;
315  
316  	/* Warn if we're not lazy. */
317  	WARN_ON(!this_cpu_read(cpu_tlbstate_shared.is_lazy));
318  
319  	switch_mm(NULL, &init_mm, NULL);
320  }
321  EXPORT_SYMBOL_GPL(leave_mm);
322  
323  void switch_mm(struct mm_struct *prev, struct mm_struct *next,
324  	       struct task_struct *tsk)
325  {
326  	unsigned long flags;
327  
328  	local_irq_save(flags);
329  	switch_mm_irqs_off(prev, next, tsk);
330  	local_irq_restore(flags);
331  }
332  
333  /*
334   * Invoked from return to user/guest by a task that opted-in to L1D
335   * flushing but ended up running on an SMT enabled core due to wrong
336   * affinity settings or CPU hotplug. This is part of the paranoid L1D flush
337   * contract which this task requested.
338   */
339  static void l1d_flush_force_sigbus(struct callback_head *ch)
340  {
341  	force_sig(SIGBUS);
342  }
343  
344  static void l1d_flush_evaluate(unsigned long prev_mm, unsigned long next_mm,
345  				struct task_struct *next)
346  {
347  	/* Flush L1D if the outgoing task requests it */
348  	if (prev_mm & LAST_USER_MM_L1D_FLUSH)
349  		wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
350  
351  	/* Check whether the incoming task opted in for L1D flush */
352  	if (likely(!(next_mm & LAST_USER_MM_L1D_FLUSH)))
353  		return;
354  
355  	/*
356  	 * Validate that it is not running on an SMT sibling as this would
357  	 * make the excercise pointless because the siblings share L1D. If
358  	 * it runs on a SMT sibling, notify it with SIGBUS on return to
359  	 * user/guest
360  	 */
361  	if (this_cpu_read(cpu_info.smt_active)) {
362  		clear_ti_thread_flag(&next->thread_info, TIF_SPEC_L1D_FLUSH);
363  		next->l1d_flush_kill.func = l1d_flush_force_sigbus;
364  		task_work_add(next, &next->l1d_flush_kill, TWA_RESUME);
365  	}
366  }
367  
368  static unsigned long mm_mangle_tif_spec_bits(struct task_struct *next)
369  {
370  	unsigned long next_tif = read_task_thread_flags(next);
371  	unsigned long spec_bits = (next_tif >> TIF_SPEC_IB) & LAST_USER_MM_SPEC_MASK;
372  
373  	/*
374  	 * Ensure that the bit shift above works as expected and the two flags
375  	 * end up in bit 0 and 1.
376  	 */
377  	BUILD_BUG_ON(TIF_SPEC_L1D_FLUSH != TIF_SPEC_IB + 1);
378  
379  	return (unsigned long)next->mm | spec_bits;
380  }
381  
382  static void cond_mitigation(struct task_struct *next)
383  {
384  	unsigned long prev_mm, next_mm;
385  
386  	if (!next || !next->mm)
387  		return;
388  
389  	next_mm = mm_mangle_tif_spec_bits(next);
390  	prev_mm = this_cpu_read(cpu_tlbstate.last_user_mm_spec);
391  
392  	/*
393  	 * Avoid user/user BTB poisoning by flushing the branch predictor
394  	 * when switching between processes. This stops one process from
395  	 * doing Spectre-v2 attacks on another.
396  	 *
397  	 * Both, the conditional and the always IBPB mode use the mm
398  	 * pointer to avoid the IBPB when switching between tasks of the
399  	 * same process. Using the mm pointer instead of mm->context.ctx_id
400  	 * opens a hypothetical hole vs. mm_struct reuse, which is more or
401  	 * less impossible to control by an attacker. Aside of that it
402  	 * would only affect the first schedule so the theoretically
403  	 * exposed data is not really interesting.
404  	 */
405  	if (static_branch_likely(&switch_mm_cond_ibpb)) {
406  		/*
407  		 * This is a bit more complex than the always mode because
408  		 * it has to handle two cases:
409  		 *
410  		 * 1) Switch from a user space task (potential attacker)
411  		 *    which has TIF_SPEC_IB set to a user space task
412  		 *    (potential victim) which has TIF_SPEC_IB not set.
413  		 *
414  		 * 2) Switch from a user space task (potential attacker)
415  		 *    which has TIF_SPEC_IB not set to a user space task
416  		 *    (potential victim) which has TIF_SPEC_IB set.
417  		 *
418  		 * This could be done by unconditionally issuing IBPB when
419  		 * a task which has TIF_SPEC_IB set is either scheduled in
420  		 * or out. Though that results in two flushes when:
421  		 *
422  		 * - the same user space task is scheduled out and later
423  		 *   scheduled in again and only a kernel thread ran in
424  		 *   between.
425  		 *
426  		 * - a user space task belonging to the same process is
427  		 *   scheduled in after a kernel thread ran in between
428  		 *
429  		 * - a user space task belonging to the same process is
430  		 *   scheduled in immediately.
431  		 *
432  		 * Optimize this with reasonably small overhead for the
433  		 * above cases. Mangle the TIF_SPEC_IB bit into the mm
434  		 * pointer of the incoming task which is stored in
435  		 * cpu_tlbstate.last_user_mm_spec for comparison.
436  		 *
437  		 * Issue IBPB only if the mm's are different and one or
438  		 * both have the IBPB bit set.
439  		 */
440  		if (next_mm != prev_mm &&
441  		    (next_mm | prev_mm) & LAST_USER_MM_IBPB)
442  			indirect_branch_prediction_barrier();
443  	}
444  
445  	if (static_branch_unlikely(&switch_mm_always_ibpb)) {
446  		/*
447  		 * Only flush when switching to a user space task with a
448  		 * different context than the user space task which ran
449  		 * last on this CPU.
450  		 */
451  		if ((prev_mm & ~LAST_USER_MM_SPEC_MASK) !=
452  					(unsigned long)next->mm)
453  			indirect_branch_prediction_barrier();
454  	}
455  
456  	if (static_branch_unlikely(&switch_mm_cond_l1d_flush)) {
457  		/*
458  		 * Flush L1D when the outgoing task requested it and/or
459  		 * check whether the incoming task requested L1D flushing
460  		 * and ended up on an SMT sibling.
461  		 */
462  		if (unlikely((prev_mm | next_mm) & LAST_USER_MM_L1D_FLUSH))
463  			l1d_flush_evaluate(prev_mm, next_mm, next);
464  	}
465  
466  	this_cpu_write(cpu_tlbstate.last_user_mm_spec, next_mm);
467  }
468  
469  #ifdef CONFIG_PERF_EVENTS
470  static inline void cr4_update_pce_mm(struct mm_struct *mm)
471  {
472  	if (static_branch_unlikely(&rdpmc_always_available_key) ||
473  	    (!static_branch_unlikely(&rdpmc_never_available_key) &&
474  	     atomic_read(&mm->context.perf_rdpmc_allowed))) {
475  		/*
476  		 * Clear the existing dirty counters to
477  		 * prevent the leak for an RDPMC task.
478  		 */
479  		perf_clear_dirty_counters();
480  		cr4_set_bits_irqsoff(X86_CR4_PCE);
481  	} else
482  		cr4_clear_bits_irqsoff(X86_CR4_PCE);
483  }
484  
485  void cr4_update_pce(void *ignored)
486  {
487  	cr4_update_pce_mm(this_cpu_read(cpu_tlbstate.loaded_mm));
488  }
489  
490  #else
491  static inline void cr4_update_pce_mm(struct mm_struct *mm) { }
492  #endif
493  
494  void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
495  			struct task_struct *tsk)
496  {
497  	struct mm_struct *real_prev = this_cpu_read(cpu_tlbstate.loaded_mm);
498  	u16 prev_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
499  	unsigned long new_lam = mm_lam_cr3_mask(next);
500  	bool was_lazy = this_cpu_read(cpu_tlbstate_shared.is_lazy);
501  	unsigned cpu = smp_processor_id();
502  	u64 next_tlb_gen;
503  	bool need_flush;
504  	u16 new_asid;
505  
506  	/*
507  	 * NB: The scheduler will call us with prev == next when switching
508  	 * from lazy TLB mode to normal mode if active_mm isn't changing.
509  	 * When this happens, we don't assume that CR3 (and hence
510  	 * cpu_tlbstate.loaded_mm) matches next.
511  	 *
512  	 * NB: leave_mm() calls us with prev == NULL and tsk == NULL.
513  	 */
514  
515  	/* We don't want flush_tlb_func() to run concurrently with us. */
516  	if (IS_ENABLED(CONFIG_PROVE_LOCKING))
517  		WARN_ON_ONCE(!irqs_disabled());
518  
519  	/*
520  	 * Verify that CR3 is what we think it is.  This will catch
521  	 * hypothetical buggy code that directly switches to swapper_pg_dir
522  	 * without going through leave_mm() / switch_mm_irqs_off() or that
523  	 * does something like write_cr3(read_cr3_pa()).
524  	 *
525  	 * Only do this check if CONFIG_DEBUG_VM=y because __read_cr3()
526  	 * isn't free.
527  	 */
528  #ifdef CONFIG_DEBUG_VM
529  	if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev->pgd, prev_asid,
530  						   tlbstate_lam_cr3_mask()))) {
531  		/*
532  		 * If we were to BUG here, we'd be very likely to kill
533  		 * the system so hard that we don't see the call trace.
534  		 * Try to recover instead by ignoring the error and doing
535  		 * a global flush to minimize the chance of corruption.
536  		 *
537  		 * (This is far from being a fully correct recovery.
538  		 *  Architecturally, the CPU could prefetch something
539  		 *  back into an incorrect ASID slot and leave it there
540  		 *  to cause trouble down the road.  It's better than
541  		 *  nothing, though.)
542  		 */
543  		__flush_tlb_all();
544  	}
545  #endif
546  	if (was_lazy)
547  		this_cpu_write(cpu_tlbstate_shared.is_lazy, false);
548  
549  	/*
550  	 * The membarrier system call requires a full memory barrier and
551  	 * core serialization before returning to user-space, after
552  	 * storing to rq->curr, when changing mm.  This is because
553  	 * membarrier() sends IPIs to all CPUs that are in the target mm
554  	 * to make them issue memory barriers.  However, if another CPU
555  	 * switches to/from the target mm concurrently with
556  	 * membarrier(), it can cause that CPU not to receive an IPI
557  	 * when it really should issue a memory barrier.  Writing to CR3
558  	 * provides that full memory barrier and core serializing
559  	 * instruction.
560  	 */
561  	if (real_prev == next) {
562  		/* Not actually switching mm's */
563  		VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) !=
564  			   next->context.ctx_id);
565  
566  		/*
567  		 * If this races with another thread that enables lam, 'new_lam'
568  		 * might not match tlbstate_lam_cr3_mask().
569  		 */
570  
571  		/*
572  		 * Even in lazy TLB mode, the CPU should stay set in the
573  		 * mm_cpumask. The TLB shootdown code can figure out from
574  		 * cpu_tlbstate_shared.is_lazy whether or not to send an IPI.
575  		 */
576  		if (WARN_ON_ONCE(real_prev != &init_mm &&
577  				 !cpumask_test_cpu(cpu, mm_cpumask(next))))
578  			cpumask_set_cpu(cpu, mm_cpumask(next));
579  
580  		/*
581  		 * If the CPU is not in lazy TLB mode, we are just switching
582  		 * from one thread in a process to another thread in the same
583  		 * process. No TLB flush required.
584  		 */
585  		if (!was_lazy)
586  			return;
587  
588  		/*
589  		 * Read the tlb_gen to check whether a flush is needed.
590  		 * If the TLB is up to date, just use it.
591  		 * The barrier synchronizes with the tlb_gen increment in
592  		 * the TLB shootdown code.
593  		 */
594  		smp_mb();
595  		next_tlb_gen = atomic64_read(&next->context.tlb_gen);
596  		if (this_cpu_read(cpu_tlbstate.ctxs[prev_asid].tlb_gen) ==
597  				next_tlb_gen)
598  			return;
599  
600  		/*
601  		 * TLB contents went out of date while we were in lazy
602  		 * mode. Fall through to the TLB switching code below.
603  		 */
604  		new_asid = prev_asid;
605  		need_flush = true;
606  	} else {
607  		/*
608  		 * Apply process to process speculation vulnerability
609  		 * mitigations if applicable.
610  		 */
611  		cond_mitigation(tsk);
612  
613  		/*
614  		 * Stop remote flushes for the previous mm.
615  		 * Skip kernel threads; we never send init_mm TLB flushing IPIs,
616  		 * but the bitmap manipulation can cause cache line contention.
617  		 */
618  		if (real_prev != &init_mm) {
619  			VM_WARN_ON_ONCE(!cpumask_test_cpu(cpu,
620  						mm_cpumask(real_prev)));
621  			cpumask_clear_cpu(cpu, mm_cpumask(real_prev));
622  		}
623  
624  		/*
625  		 * Start remote flushes and then read tlb_gen.
626  		 */
627  		if (next != &init_mm)
628  			cpumask_set_cpu(cpu, mm_cpumask(next));
629  		next_tlb_gen = atomic64_read(&next->context.tlb_gen);
630  
631  		choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush);
632  
633  		/* Let nmi_uaccess_okay() know that we're changing CR3. */
634  		this_cpu_write(cpu_tlbstate.loaded_mm, LOADED_MM_SWITCHING);
635  		barrier();
636  	}
637  
638  	set_tlbstate_lam_mode(next);
639  	if (need_flush) {
640  		this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id);
641  		this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen);
642  		load_new_mm_cr3(next->pgd, new_asid, new_lam, true);
643  
644  		trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
645  	} else {
646  		/* The new ASID is already up to date. */
647  		load_new_mm_cr3(next->pgd, new_asid, new_lam, false);
648  
649  		trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, 0);
650  	}
651  
652  	/* Make sure we write CR3 before loaded_mm. */
653  	barrier();
654  
655  	this_cpu_write(cpu_tlbstate.loaded_mm, next);
656  	this_cpu_write(cpu_tlbstate.loaded_mm_asid, new_asid);
657  
658  	if (next != real_prev) {
659  		cr4_update_pce_mm(next);
660  		switch_ldt(real_prev, next);
661  	}
662  }
663  
664  /*
665   * Please ignore the name of this function.  It should be called
666   * switch_to_kernel_thread().
667   *
668   * enter_lazy_tlb() is a hint from the scheduler that we are entering a
669   * kernel thread or other context without an mm.  Acceptable implementations
670   * include doing nothing whatsoever, switching to init_mm, or various clever
671   * lazy tricks to try to minimize TLB flushes.
672   *
673   * The scheduler reserves the right to call enter_lazy_tlb() several times
674   * in a row.  It will notify us that we're going back to a real mm by
675   * calling switch_mm_irqs_off().
676   */
677  void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
678  {
679  	if (this_cpu_read(cpu_tlbstate.loaded_mm) == &init_mm)
680  		return;
681  
682  	this_cpu_write(cpu_tlbstate_shared.is_lazy, true);
683  }
684  
685  /*
686   * Call this when reinitializing a CPU.  It fixes the following potential
687   * problems:
688   *
689   * - The ASID changed from what cpu_tlbstate thinks it is (most likely
690   *   because the CPU was taken down and came back up with CR3's PCID
691   *   bits clear.  CPU hotplug can do this.
692   *
693   * - The TLB contains junk in slots corresponding to inactive ASIDs.
694   *
695   * - The CPU went so far out to lunch that it may have missed a TLB
696   *   flush.
697   */
698  void initialize_tlbstate_and_flush(void)
699  {
700  	int i;
701  	struct mm_struct *mm = this_cpu_read(cpu_tlbstate.loaded_mm);
702  	u64 tlb_gen = atomic64_read(&init_mm.context.tlb_gen);
703  	unsigned long cr3 = __read_cr3();
704  
705  	/* Assert that CR3 already references the right mm. */
706  	WARN_ON((cr3 & CR3_ADDR_MASK) != __pa(mm->pgd));
707  
708  	/* LAM expected to be disabled */
709  	WARN_ON(cr3 & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57));
710  	WARN_ON(mm_lam_cr3_mask(mm));
711  
712  	/*
713  	 * Assert that CR4.PCIDE is set if needed.  (CR4.PCIDE initialization
714  	 * doesn't work like other CR4 bits because it can only be set from
715  	 * long mode.)
716  	 */
717  	WARN_ON(boot_cpu_has(X86_FEATURE_PCID) &&
718  		!(cr4_read_shadow() & X86_CR4_PCIDE));
719  
720  	/* Disable LAM, force ASID 0 and force a TLB flush. */
721  	write_cr3(build_cr3(mm->pgd, 0, 0));
722  
723  	/* Reinitialize tlbstate. */
724  	this_cpu_write(cpu_tlbstate.last_user_mm_spec, LAST_USER_MM_INIT);
725  	this_cpu_write(cpu_tlbstate.loaded_mm_asid, 0);
726  	this_cpu_write(cpu_tlbstate.next_asid, 1);
727  	this_cpu_write(cpu_tlbstate.ctxs[0].ctx_id, mm->context.ctx_id);
728  	this_cpu_write(cpu_tlbstate.ctxs[0].tlb_gen, tlb_gen);
729  	set_tlbstate_lam_mode(mm);
730  
731  	for (i = 1; i < TLB_NR_DYN_ASIDS; i++)
732  		this_cpu_write(cpu_tlbstate.ctxs[i].ctx_id, 0);
733  }
734  
735  /*
736   * flush_tlb_func()'s memory ordering requirement is that any
737   * TLB fills that happen after we flush the TLB are ordered after we
738   * read active_mm's tlb_gen.  We don't need any explicit barriers
739   * because all x86 flush operations are serializing and the
740   * atomic64_read operation won't be reordered by the compiler.
741   */
742  static void flush_tlb_func(void *info)
743  {
744  	/*
745  	 * We have three different tlb_gen values in here.  They are:
746  	 *
747  	 * - mm_tlb_gen:     the latest generation.
748  	 * - local_tlb_gen:  the generation that this CPU has already caught
749  	 *                   up to.
750  	 * - f->new_tlb_gen: the generation that the requester of the flush
751  	 *                   wants us to catch up to.
752  	 */
753  	const struct flush_tlb_info *f = info;
754  	struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
755  	u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
756  	u64 local_tlb_gen = this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen);
757  	bool local = smp_processor_id() == f->initiating_cpu;
758  	unsigned long nr_invalidate = 0;
759  	u64 mm_tlb_gen;
760  
761  	/* This code cannot presently handle being reentered. */
762  	VM_WARN_ON(!irqs_disabled());
763  
764  	if (!local) {
765  		inc_irq_stat(irq_tlb_count);
766  		count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
767  
768  		/* Can only happen on remote CPUs */
769  		if (f->mm && f->mm != loaded_mm)
770  			return;
771  	}
772  
773  	if (unlikely(loaded_mm == &init_mm))
774  		return;
775  
776  	VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].ctx_id) !=
777  		   loaded_mm->context.ctx_id);
778  
779  	if (this_cpu_read(cpu_tlbstate_shared.is_lazy)) {
780  		/*
781  		 * We're in lazy mode.  We need to at least flush our
782  		 * paging-structure cache to avoid speculatively reading
783  		 * garbage into our TLB.  Since switching to init_mm is barely
784  		 * slower than a minimal flush, just switch to init_mm.
785  		 *
786  		 * This should be rare, with native_flush_tlb_multi() skipping
787  		 * IPIs to lazy TLB mode CPUs.
788  		 */
789  		switch_mm_irqs_off(NULL, &init_mm, NULL);
790  		return;
791  	}
792  
793  	if (unlikely(f->new_tlb_gen != TLB_GENERATION_INVALID &&
794  		     f->new_tlb_gen <= local_tlb_gen)) {
795  		/*
796  		 * The TLB is already up to date in respect to f->new_tlb_gen.
797  		 * While the core might be still behind mm_tlb_gen, checking
798  		 * mm_tlb_gen unnecessarily would have negative caching effects
799  		 * so avoid it.
800  		 */
801  		return;
802  	}
803  
804  	/*
805  	 * Defer mm_tlb_gen reading as long as possible to avoid cache
806  	 * contention.
807  	 */
808  	mm_tlb_gen = atomic64_read(&loaded_mm->context.tlb_gen);
809  
810  	if (unlikely(local_tlb_gen == mm_tlb_gen)) {
811  		/*
812  		 * There's nothing to do: we're already up to date.  This can
813  		 * happen if two concurrent flushes happen -- the first flush to
814  		 * be handled can catch us all the way up, leaving no work for
815  		 * the second flush.
816  		 */
817  		goto done;
818  	}
819  
820  	WARN_ON_ONCE(local_tlb_gen > mm_tlb_gen);
821  	WARN_ON_ONCE(f->new_tlb_gen > mm_tlb_gen);
822  
823  	/*
824  	 * If we get to this point, we know that our TLB is out of date.
825  	 * This does not strictly imply that we need to flush (it's
826  	 * possible that f->new_tlb_gen <= local_tlb_gen), but we're
827  	 * going to need to flush in the very near future, so we might
828  	 * as well get it over with.
829  	 *
830  	 * The only question is whether to do a full or partial flush.
831  	 *
832  	 * We do a partial flush if requested and two extra conditions
833  	 * are met:
834  	 *
835  	 * 1. f->new_tlb_gen == local_tlb_gen + 1.  We have an invariant that
836  	 *    we've always done all needed flushes to catch up to
837  	 *    local_tlb_gen.  If, for example, local_tlb_gen == 2 and
838  	 *    f->new_tlb_gen == 3, then we know that the flush needed to bring
839  	 *    us up to date for tlb_gen 3 is the partial flush we're
840  	 *    processing.
841  	 *
842  	 *    As an example of why this check is needed, suppose that there
843  	 *    are two concurrent flushes.  The first is a full flush that
844  	 *    changes context.tlb_gen from 1 to 2.  The second is a partial
845  	 *    flush that changes context.tlb_gen from 2 to 3.  If they get
846  	 *    processed on this CPU in reverse order, we'll see
847  	 *     local_tlb_gen == 1, mm_tlb_gen == 3, and end != TLB_FLUSH_ALL.
848  	 *    If we were to use __flush_tlb_one_user() and set local_tlb_gen to
849  	 *    3, we'd be break the invariant: we'd update local_tlb_gen above
850  	 *    1 without the full flush that's needed for tlb_gen 2.
851  	 *
852  	 * 2. f->new_tlb_gen == mm_tlb_gen.  This is purely an optimization.
853  	 *    Partial TLB flushes are not all that much cheaper than full TLB
854  	 *    flushes, so it seems unlikely that it would be a performance win
855  	 *    to do a partial flush if that won't bring our TLB fully up to
856  	 *    date.  By doing a full flush instead, we can increase
857  	 *    local_tlb_gen all the way to mm_tlb_gen and we can probably
858  	 *    avoid another flush in the very near future.
859  	 */
860  	if (f->end != TLB_FLUSH_ALL &&
861  	    f->new_tlb_gen == local_tlb_gen + 1 &&
862  	    f->new_tlb_gen == mm_tlb_gen) {
863  		/* Partial flush */
864  		unsigned long addr = f->start;
865  
866  		/* Partial flush cannot have invalid generations */
867  		VM_WARN_ON(f->new_tlb_gen == TLB_GENERATION_INVALID);
868  
869  		/* Partial flush must have valid mm */
870  		VM_WARN_ON(f->mm == NULL);
871  
872  		nr_invalidate = (f->end - f->start) >> f->stride_shift;
873  
874  		while (addr < f->end) {
875  			flush_tlb_one_user(addr);
876  			addr += 1UL << f->stride_shift;
877  		}
878  		if (local)
879  			count_vm_tlb_events(NR_TLB_LOCAL_FLUSH_ONE, nr_invalidate);
880  	} else {
881  		/* Full flush. */
882  		nr_invalidate = TLB_FLUSH_ALL;
883  
884  		flush_tlb_local();
885  		if (local)
886  			count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
887  	}
888  
889  	/* Both paths above update our state to mm_tlb_gen. */
890  	this_cpu_write(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen, mm_tlb_gen);
891  
892  	/* Tracing is done in a unified manner to reduce the code size */
893  done:
894  	trace_tlb_flush(!local ? TLB_REMOTE_SHOOTDOWN :
895  				(f->mm == NULL) ? TLB_LOCAL_SHOOTDOWN :
896  						  TLB_LOCAL_MM_SHOOTDOWN,
897  			nr_invalidate);
898  }
899  
900  static bool tlb_is_not_lazy(int cpu, void *data)
901  {
902  	return !per_cpu(cpu_tlbstate_shared.is_lazy, cpu);
903  }
904  
905  DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state_shared, cpu_tlbstate_shared);
906  EXPORT_PER_CPU_SYMBOL(cpu_tlbstate_shared);
907  
908  STATIC_NOPV void native_flush_tlb_multi(const struct cpumask *cpumask,
909  					 const struct flush_tlb_info *info)
910  {
911  	/*
912  	 * Do accounting and tracing. Note that there are (and have always been)
913  	 * cases in which a remote TLB flush will be traced, but eventually
914  	 * would not happen.
915  	 */
916  	count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
917  	if (info->end == TLB_FLUSH_ALL)
918  		trace_tlb_flush(TLB_REMOTE_SEND_IPI, TLB_FLUSH_ALL);
919  	else
920  		trace_tlb_flush(TLB_REMOTE_SEND_IPI,
921  				(info->end - info->start) >> PAGE_SHIFT);
922  
923  	/*
924  	 * If no page tables were freed, we can skip sending IPIs to
925  	 * CPUs in lazy TLB mode. They will flush the CPU themselves
926  	 * at the next context switch.
927  	 *
928  	 * However, if page tables are getting freed, we need to send the
929  	 * IPI everywhere, to prevent CPUs in lazy TLB mode from tripping
930  	 * up on the new contents of what used to be page tables, while
931  	 * doing a speculative memory access.
932  	 */
933  	if (info->freed_tables)
934  		on_each_cpu_mask(cpumask, flush_tlb_func, (void *)info, true);
935  	else
936  		on_each_cpu_cond_mask(tlb_is_not_lazy, flush_tlb_func,
937  				(void *)info, 1, cpumask);
938  }
939  
940  void flush_tlb_multi(const struct cpumask *cpumask,
941  		      const struct flush_tlb_info *info)
942  {
943  	__flush_tlb_multi(cpumask, info);
944  }
945  
946  /*
947   * See Documentation/arch/x86/tlb.rst for details.  We choose 33
948   * because it is large enough to cover the vast majority (at
949   * least 95%) of allocations, and is small enough that we are
950   * confident it will not cause too much overhead.  Each single
951   * flush is about 100 ns, so this caps the maximum overhead at
952   * _about_ 3,000 ns.
953   *
954   * This is in units of pages.
955   */
956  unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;
957  
958  static DEFINE_PER_CPU_SHARED_ALIGNED(struct flush_tlb_info, flush_tlb_info);
959  
960  #ifdef CONFIG_DEBUG_VM
961  static DEFINE_PER_CPU(unsigned int, flush_tlb_info_idx);
962  #endif
963  
964  static struct flush_tlb_info *get_flush_tlb_info(struct mm_struct *mm,
965  			unsigned long start, unsigned long end,
966  			unsigned int stride_shift, bool freed_tables,
967  			u64 new_tlb_gen)
968  {
969  	struct flush_tlb_info *info = this_cpu_ptr(&flush_tlb_info);
970  
971  #ifdef CONFIG_DEBUG_VM
972  	/*
973  	 * Ensure that the following code is non-reentrant and flush_tlb_info
974  	 * is not overwritten. This means no TLB flushing is initiated by
975  	 * interrupt handlers and machine-check exception handlers.
976  	 */
977  	BUG_ON(this_cpu_inc_return(flush_tlb_info_idx) != 1);
978  #endif
979  
980  	info->start		= start;
981  	info->end		= end;
982  	info->mm		= mm;
983  	info->stride_shift	= stride_shift;
984  	info->freed_tables	= freed_tables;
985  	info->new_tlb_gen	= new_tlb_gen;
986  	info->initiating_cpu	= smp_processor_id();
987  
988  	return info;
989  }
990  
991  static void put_flush_tlb_info(void)
992  {
993  #ifdef CONFIG_DEBUG_VM
994  	/* Complete reentrancy prevention checks */
995  	barrier();
996  	this_cpu_dec(flush_tlb_info_idx);
997  #endif
998  }
999  
1000  void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
1001  				unsigned long end, unsigned int stride_shift,
1002  				bool freed_tables)
1003  {
1004  	struct flush_tlb_info *info;
1005  	u64 new_tlb_gen;
1006  	int cpu;
1007  
1008  	cpu = get_cpu();
1009  
1010  	/* Should we flush just the requested range? */
1011  	if ((end == TLB_FLUSH_ALL) ||
1012  	    ((end - start) >> stride_shift) > tlb_single_page_flush_ceiling) {
1013  		start = 0;
1014  		end = TLB_FLUSH_ALL;
1015  	}
1016  
1017  	/* This is also a barrier that synchronizes with switch_mm(). */
1018  	new_tlb_gen = inc_mm_tlb_gen(mm);
1019  
1020  	info = get_flush_tlb_info(mm, start, end, stride_shift, freed_tables,
1021  				  new_tlb_gen);
1022  
1023  	/*
1024  	 * flush_tlb_multi() is not optimized for the common case in which only
1025  	 * a local TLB flush is needed. Optimize this use-case by calling
1026  	 * flush_tlb_func_local() directly in this case.
1027  	 */
1028  	if (cpumask_any_but(mm_cpumask(mm), cpu) < nr_cpu_ids) {
1029  		flush_tlb_multi(mm_cpumask(mm), info);
1030  	} else if (mm == this_cpu_read(cpu_tlbstate.loaded_mm)) {
1031  		lockdep_assert_irqs_enabled();
1032  		local_irq_disable();
1033  		flush_tlb_func(info);
1034  		local_irq_enable();
1035  	}
1036  
1037  	put_flush_tlb_info();
1038  	put_cpu();
1039  }
1040  
1041  
1042  static void do_flush_tlb_all(void *info)
1043  {
1044  	count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
1045  	__flush_tlb_all();
1046  }
1047  
1048  void flush_tlb_all(void)
1049  {
1050  	count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
1051  	on_each_cpu(do_flush_tlb_all, NULL, 1);
1052  }
1053  
1054  static void do_kernel_range_flush(void *info)
1055  {
1056  	struct flush_tlb_info *f = info;
1057  	unsigned long addr;
1058  
1059  	/* flush range by one by one 'invlpg' */
1060  	for (addr = f->start; addr < f->end; addr += PAGE_SIZE)
1061  		flush_tlb_one_kernel(addr);
1062  }
1063  
1064  void flush_tlb_kernel_range(unsigned long start, unsigned long end)
1065  {
1066  	/* Balance as user space task's flush, a bit conservative */
1067  	if (end == TLB_FLUSH_ALL ||
1068  	    (end - start) > tlb_single_page_flush_ceiling << PAGE_SHIFT) {
1069  		on_each_cpu(do_flush_tlb_all, NULL, 1);
1070  	} else {
1071  		struct flush_tlb_info *info;
1072  
1073  		preempt_disable();
1074  		info = get_flush_tlb_info(NULL, start, end, 0, false,
1075  					  TLB_GENERATION_INVALID);
1076  
1077  		on_each_cpu(do_kernel_range_flush, info, 1);
1078  
1079  		put_flush_tlb_info();
1080  		preempt_enable();
1081  	}
1082  }
1083  
1084  /*
1085   * This can be used from process context to figure out what the value of
1086   * CR3 is without needing to do a (slow) __read_cr3().
1087   *
1088   * It's intended to be used for code like KVM that sneakily changes CR3
1089   * and needs to restore it.  It needs to be used very carefully.
1090   */
1091  unsigned long __get_current_cr3_fast(void)
1092  {
1093  	unsigned long cr3 =
1094  		build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm)->pgd,
1095  			  this_cpu_read(cpu_tlbstate.loaded_mm_asid),
1096  			  tlbstate_lam_cr3_mask());
1097  
1098  	/* For now, be very restrictive about when this can be called. */
1099  	VM_WARN_ON(in_nmi() || preemptible());
1100  
1101  	VM_BUG_ON(cr3 != __read_cr3());
1102  	return cr3;
1103  }
1104  EXPORT_SYMBOL_GPL(__get_current_cr3_fast);
1105  
1106  /*
1107   * Flush one page in the kernel mapping
1108   */
1109  void flush_tlb_one_kernel(unsigned long addr)
1110  {
1111  	count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
1112  
1113  	/*
1114  	 * If PTI is off, then __flush_tlb_one_user() is just INVLPG or its
1115  	 * paravirt equivalent.  Even with PCID, this is sufficient: we only
1116  	 * use PCID if we also use global PTEs for the kernel mapping, and
1117  	 * INVLPG flushes global translations across all address spaces.
1118  	 *
1119  	 * If PTI is on, then the kernel is mapped with non-global PTEs, and
1120  	 * __flush_tlb_one_user() will flush the given address for the current
1121  	 * kernel address space and for its usermode counterpart, but it does
1122  	 * not flush it for other address spaces.
1123  	 */
1124  	flush_tlb_one_user(addr);
1125  
1126  	if (!static_cpu_has(X86_FEATURE_PTI))
1127  		return;
1128  
1129  	/*
1130  	 * See above.  We need to propagate the flush to all other address
1131  	 * spaces.  In principle, we only need to propagate it to kernelmode
1132  	 * address spaces, but the extra bookkeeping we would need is not
1133  	 * worth it.
1134  	 */
1135  	this_cpu_write(cpu_tlbstate.invalidate_other, true);
1136  }
1137  
1138  /*
1139   * Flush one page in the user mapping
1140   */
1141  STATIC_NOPV void native_flush_tlb_one_user(unsigned long addr)
1142  {
1143  	u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
1144  
1145  	asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
1146  
1147  	if (!static_cpu_has(X86_FEATURE_PTI))
1148  		return;
1149  
1150  	/*
1151  	 * Some platforms #GP if we call invpcid(type=1/2) before CR4.PCIDE=1.
1152  	 * Just use invalidate_user_asid() in case we are called early.
1153  	 */
1154  	if (!this_cpu_has(X86_FEATURE_INVPCID_SINGLE))
1155  		invalidate_user_asid(loaded_mm_asid);
1156  	else
1157  		invpcid_flush_one(user_pcid(loaded_mm_asid), addr);
1158  }
1159  
1160  void flush_tlb_one_user(unsigned long addr)
1161  {
1162  	__flush_tlb_one_user(addr);
1163  }
1164  
1165  /*
1166   * Flush everything
1167   */
1168  STATIC_NOPV void native_flush_tlb_global(void)
1169  {
1170  	unsigned long flags;
1171  
1172  	if (static_cpu_has(X86_FEATURE_INVPCID)) {
1173  		/*
1174  		 * Using INVPCID is considerably faster than a pair of writes
1175  		 * to CR4 sandwiched inside an IRQ flag save/restore.
1176  		 *
1177  		 * Note, this works with CR4.PCIDE=0 or 1.
1178  		 */
1179  		invpcid_flush_all();
1180  		return;
1181  	}
1182  
1183  	/*
1184  	 * Read-modify-write to CR4 - protect it from preemption and
1185  	 * from interrupts. (Use the raw variant because this code can
1186  	 * be called from deep inside debugging code.)
1187  	 */
1188  	raw_local_irq_save(flags);
1189  
1190  	__native_tlb_flush_global(this_cpu_read(cpu_tlbstate.cr4));
1191  
1192  	raw_local_irq_restore(flags);
1193  }
1194  
1195  /*
1196   * Flush the entire current user mapping
1197   */
1198  STATIC_NOPV void native_flush_tlb_local(void)
1199  {
1200  	/*
1201  	 * Preemption or interrupts must be disabled to protect the access
1202  	 * to the per CPU variable and to prevent being preempted between
1203  	 * read_cr3() and write_cr3().
1204  	 */
1205  	WARN_ON_ONCE(preemptible());
1206  
1207  	invalidate_user_asid(this_cpu_read(cpu_tlbstate.loaded_mm_asid));
1208  
1209  	/* If current->mm == NULL then the read_cr3() "borrows" an mm */
1210  	native_write_cr3(__native_read_cr3());
1211  }
1212  
1213  void flush_tlb_local(void)
1214  {
1215  	__flush_tlb_local();
1216  }
1217  
1218  /*
1219   * Flush everything
1220   */
1221  void __flush_tlb_all(void)
1222  {
1223  	/*
1224  	 * This is to catch users with enabled preemption and the PGE feature
1225  	 * and don't trigger the warning in __native_flush_tlb().
1226  	 */
1227  	VM_WARN_ON_ONCE(preemptible());
1228  
1229  	if (cpu_feature_enabled(X86_FEATURE_PGE)) {
1230  		__flush_tlb_global();
1231  	} else {
1232  		/*
1233  		 * !PGE -> !PCID (setup_pcid()), thus every flush is total.
1234  		 */
1235  		flush_tlb_local();
1236  	}
1237  }
1238  EXPORT_SYMBOL_GPL(__flush_tlb_all);
1239  
1240  void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch)
1241  {
1242  	struct flush_tlb_info *info;
1243  
1244  	int cpu = get_cpu();
1245  
1246  	info = get_flush_tlb_info(NULL, 0, TLB_FLUSH_ALL, 0, false,
1247  				  TLB_GENERATION_INVALID);
1248  	/*
1249  	 * flush_tlb_multi() is not optimized for the common case in which only
1250  	 * a local TLB flush is needed. Optimize this use-case by calling
1251  	 * flush_tlb_func_local() directly in this case.
1252  	 */
1253  	if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) {
1254  		flush_tlb_multi(&batch->cpumask, info);
1255  	} else if (cpumask_test_cpu(cpu, &batch->cpumask)) {
1256  		lockdep_assert_irqs_enabled();
1257  		local_irq_disable();
1258  		flush_tlb_func(info);
1259  		local_irq_enable();
1260  	}
1261  
1262  	cpumask_clear(&batch->cpumask);
1263  
1264  	put_flush_tlb_info();
1265  	put_cpu();
1266  }
1267  
1268  /*
1269   * Blindly accessing user memory from NMI context can be dangerous
1270   * if we're in the middle of switching the current user task or
1271   * switching the loaded mm.  It can also be dangerous if we
1272   * interrupted some kernel code that was temporarily using a
1273   * different mm.
1274   */
1275  bool nmi_uaccess_okay(void)
1276  {
1277  	struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
1278  	struct mm_struct *current_mm = current->mm;
1279  
1280  	VM_WARN_ON_ONCE(!loaded_mm);
1281  
1282  	/*
1283  	 * The condition we want to check is
1284  	 * current_mm->pgd == __va(read_cr3_pa()).  This may be slow, though,
1285  	 * if we're running in a VM with shadow paging, and nmi_uaccess_okay()
1286  	 * is supposed to be reasonably fast.
1287  	 *
1288  	 * Instead, we check the almost equivalent but somewhat conservative
1289  	 * condition below, and we rely on the fact that switch_mm_irqs_off()
1290  	 * sets loaded_mm to LOADED_MM_SWITCHING before writing to CR3.
1291  	 */
1292  	if (loaded_mm != current_mm)
1293  		return false;
1294  
1295  	VM_WARN_ON_ONCE(current_mm->pgd != __va(read_cr3_pa()));
1296  
1297  	return true;
1298  }
1299  
1300  static ssize_t tlbflush_read_file(struct file *file, char __user *user_buf,
1301  			     size_t count, loff_t *ppos)
1302  {
1303  	char buf[32];
1304  	unsigned int len;
1305  
1306  	len = sprintf(buf, "%ld\n", tlb_single_page_flush_ceiling);
1307  	return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1308  }
1309  
1310  static ssize_t tlbflush_write_file(struct file *file,
1311  		 const char __user *user_buf, size_t count, loff_t *ppos)
1312  {
1313  	char buf[32];
1314  	ssize_t len;
1315  	int ceiling;
1316  
1317  	len = min(count, sizeof(buf) - 1);
1318  	if (copy_from_user(buf, user_buf, len))
1319  		return -EFAULT;
1320  
1321  	buf[len] = '\0';
1322  	if (kstrtoint(buf, 0, &ceiling))
1323  		return -EINVAL;
1324  
1325  	if (ceiling < 0)
1326  		return -EINVAL;
1327  
1328  	tlb_single_page_flush_ceiling = ceiling;
1329  	return count;
1330  }
1331  
1332  static const struct file_operations fops_tlbflush = {
1333  	.read = tlbflush_read_file,
1334  	.write = tlbflush_write_file,
1335  	.llseek = default_llseek,
1336  };
1337  
1338  static int __init create_tlb_single_page_flush_ceiling(void)
1339  {
1340  	debugfs_create_file("tlb_single_page_flush_ceiling", S_IRUSR | S_IWUSR,
1341  			    arch_debugfs_dir, NULL, &fops_tlbflush);
1342  	return 0;
1343  }
1344  late_initcall(create_tlb_single_page_flush_ceiling);
1345