1 #include <linux/gfp.h> 2 #include <linux/initrd.h> 3 #include <linux/ioport.h> 4 #include <linux/swap.h> 5 #include <linux/memblock.h> 6 #include <linux/swapfile.h> 7 #include <linux/swapops.h> 8 #include <linux/kmemleak.h> 9 #include <linux/sched/task.h> 10 11 #include <asm/set_memory.h> 12 #include <asm/cpu_device_id.h> 13 #include <asm/e820/api.h> 14 #include <asm/init.h> 15 #include <asm/page.h> 16 #include <asm/page_types.h> 17 #include <asm/sections.h> 18 #include <asm/setup.h> 19 #include <asm/tlbflush.h> 20 #include <asm/tlb.h> 21 #include <asm/proto.h> 22 #include <asm/dma.h> /* for MAX_DMA_PFN */ 23 #include <asm/microcode.h> 24 #include <asm/kaslr.h> 25 #include <asm/hypervisor.h> 26 #include <asm/cpufeature.h> 27 #include <asm/pti.h> 28 #include <asm/text-patching.h> 29 #include <asm/memtype.h> 30 #include <asm/paravirt.h> 31 32 /* 33 * We need to define the tracepoints somewhere, and tlb.c 34 * is only compiled when SMP=y. 35 */ 36 #include <trace/events/tlb.h> 37 38 #include "mm_internal.h" 39 40 /* 41 * Tables translating between page_cache_type_t and pte encoding. 42 * 43 * The default values are defined statically as minimal supported mode; 44 * WC and WT fall back to UC-. pat_init() updates these values to support 45 * more cache modes, WC and WT, when it is safe to do so. See pat_init() 46 * for the details. Note, __early_ioremap() used during early boot-time 47 * takes pgprot_t (pte encoding) and does not use these tables. 48 * 49 * Index into __cachemode2pte_tbl[] is the cachemode. 50 * 51 * Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte 52 * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2. 53 */ 54 static uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = { 55 [_PAGE_CACHE_MODE_WB ] = 0 | 0 , 56 [_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD, 57 [_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD, 58 [_PAGE_CACHE_MODE_UC ] = _PAGE_PWT | _PAGE_PCD, 59 [_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD, 60 [_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD, 61 }; 62 63 unsigned long cachemode2protval(enum page_cache_mode pcm) 64 { 65 if (likely(pcm == 0)) 66 return 0; 67 return __cachemode2pte_tbl[pcm]; 68 } 69 EXPORT_SYMBOL(cachemode2protval); 70 71 static uint8_t __pte2cachemode_tbl[8] = { 72 [__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB, 73 [__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_UC_MINUS, 74 [__pte2cm_idx( 0 | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC_MINUS, 75 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC, 76 [__pte2cm_idx( 0 | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_WB, 77 [__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS, 78 [__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS, 79 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC, 80 }; 81 82 /* 83 * Check that the write-protect PAT entry is set for write-protect. 84 * To do this without making assumptions how PAT has been set up (Xen has 85 * another layout than the kernel), translate the _PAGE_CACHE_MODE_WP cache 86 * mode via the __cachemode2pte_tbl[] into protection bits (those protection 87 * bits will select a cache mode of WP or better), and then translate the 88 * protection bits back into the cache mode using __pte2cm_idx() and the 89 * __pte2cachemode_tbl[] array. This will return the really used cache mode. 90 */ 91 bool x86_has_pat_wp(void) 92 { 93 uint16_t prot = __cachemode2pte_tbl[_PAGE_CACHE_MODE_WP]; 94 95 return __pte2cachemode_tbl[__pte2cm_idx(prot)] == _PAGE_CACHE_MODE_WP; 96 } 97 98 enum page_cache_mode pgprot2cachemode(pgprot_t pgprot) 99 { 100 unsigned long masked; 101 102 masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK; 103 if (likely(masked == 0)) 104 return 0; 105 return __pte2cachemode_tbl[__pte2cm_idx(masked)]; 106 } 107 108 static unsigned long __initdata pgt_buf_start; 109 static unsigned long __initdata pgt_buf_end; 110 static unsigned long __initdata pgt_buf_top; 111 112 static unsigned long min_pfn_mapped; 113 114 static bool __initdata can_use_brk_pgt = true; 115 116 /* 117 * Pages returned are already directly mapped. 118 * 119 * Changing that is likely to break Xen, see commit: 120 * 121 * 279b706 x86,xen: introduce x86_init.mapping.pagetable_reserve 122 * 123 * for detailed information. 124 */ 125 __ref void *alloc_low_pages(unsigned int num) 126 { 127 unsigned long pfn; 128 int i; 129 130 if (after_bootmem) { 131 unsigned int order; 132 133 order = get_order((unsigned long)num << PAGE_SHIFT); 134 return (void *)__get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 135 } 136 137 if ((pgt_buf_end + num) > pgt_buf_top || !can_use_brk_pgt) { 138 unsigned long ret = 0; 139 140 if (min_pfn_mapped < max_pfn_mapped) { 141 ret = memblock_phys_alloc_range( 142 PAGE_SIZE * num, PAGE_SIZE, 143 min_pfn_mapped << PAGE_SHIFT, 144 max_pfn_mapped << PAGE_SHIFT); 145 } 146 if (!ret && can_use_brk_pgt) 147 ret = __pa(extend_brk(PAGE_SIZE * num, PAGE_SIZE)); 148 149 if (!ret) 150 panic("alloc_low_pages: can not alloc memory"); 151 152 pfn = ret >> PAGE_SHIFT; 153 } else { 154 pfn = pgt_buf_end; 155 pgt_buf_end += num; 156 } 157 158 for (i = 0; i < num; i++) { 159 void *adr; 160 161 adr = __va((pfn + i) << PAGE_SHIFT); 162 clear_page(adr); 163 } 164 165 return __va(pfn << PAGE_SHIFT); 166 } 167 168 /* 169 * By default need to be able to allocate page tables below PGD firstly for 170 * the 0-ISA_END_ADDRESS range and secondly for the initial PMD_SIZE mapping. 171 * With KASLR memory randomization, depending on the machine e820 memory and the 172 * PUD alignment, twice that many pages may be needed when KASLR memory 173 * randomization is enabled. 174 */ 175 176 #ifndef CONFIG_X86_5LEVEL 177 #define INIT_PGD_PAGE_TABLES 3 178 #else 179 #define INIT_PGD_PAGE_TABLES 4 180 #endif 181 182 #ifndef CONFIG_RANDOMIZE_MEMORY 183 #define INIT_PGD_PAGE_COUNT (2 * INIT_PGD_PAGE_TABLES) 184 #else 185 #define INIT_PGD_PAGE_COUNT (4 * INIT_PGD_PAGE_TABLES) 186 #endif 187 188 #define INIT_PGT_BUF_SIZE (INIT_PGD_PAGE_COUNT * PAGE_SIZE) 189 RESERVE_BRK(early_pgt_alloc, INIT_PGT_BUF_SIZE); 190 void __init early_alloc_pgt_buf(void) 191 { 192 unsigned long tables = INIT_PGT_BUF_SIZE; 193 phys_addr_t base; 194 195 base = __pa(extend_brk(tables, PAGE_SIZE)); 196 197 pgt_buf_start = base >> PAGE_SHIFT; 198 pgt_buf_end = pgt_buf_start; 199 pgt_buf_top = pgt_buf_start + (tables >> PAGE_SHIFT); 200 } 201 202 int after_bootmem; 203 204 early_param_on_off("gbpages", "nogbpages", direct_gbpages, CONFIG_X86_DIRECT_GBPAGES); 205 206 struct map_range { 207 unsigned long start; 208 unsigned long end; 209 unsigned page_size_mask; 210 }; 211 212 static int page_size_mask; 213 214 /* 215 * Save some of cr4 feature set we're using (e.g. Pentium 4MB 216 * enable and PPro Global page enable), so that any CPU's that boot 217 * up after us can get the correct flags. Invoked on the boot CPU. 218 */ 219 static inline void cr4_set_bits_and_update_boot(unsigned long mask) 220 { 221 mmu_cr4_features |= mask; 222 if (trampoline_cr4_features) 223 *trampoline_cr4_features = mmu_cr4_features; 224 cr4_set_bits(mask); 225 } 226 227 static void __init probe_page_size_mask(void) 228 { 229 /* 230 * For pagealloc debugging, identity mapping will use small pages. 231 * This will simplify cpa(), which otherwise needs to support splitting 232 * large pages into small in interrupt context, etc. 233 */ 234 if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled()) 235 page_size_mask |= 1 << PG_LEVEL_2M; 236 else 237 direct_gbpages = 0; 238 239 /* Enable PSE if available */ 240 if (boot_cpu_has(X86_FEATURE_PSE)) 241 cr4_set_bits_and_update_boot(X86_CR4_PSE); 242 243 /* Enable PGE if available */ 244 __supported_pte_mask &= ~_PAGE_GLOBAL; 245 if (boot_cpu_has(X86_FEATURE_PGE)) { 246 cr4_set_bits_and_update_boot(X86_CR4_PGE); 247 __supported_pte_mask |= _PAGE_GLOBAL; 248 } 249 250 /* By the default is everything supported: */ 251 __default_kernel_pte_mask = __supported_pte_mask; 252 /* Except when with PTI where the kernel is mostly non-Global: */ 253 if (cpu_feature_enabled(X86_FEATURE_PTI)) 254 __default_kernel_pte_mask &= ~_PAGE_GLOBAL; 255 256 /* Enable 1 GB linear kernel mappings if available: */ 257 if (direct_gbpages && boot_cpu_has(X86_FEATURE_GBPAGES)) { 258 printk(KERN_INFO "Using GB pages for direct mapping\n"); 259 page_size_mask |= 1 << PG_LEVEL_1G; 260 } else { 261 direct_gbpages = 0; 262 } 263 } 264 265 #define INTEL_MATCH(_model) { .vendor = X86_VENDOR_INTEL, \ 266 .family = 6, \ 267 .model = _model, \ 268 } 269 /* 270 * INVLPG may not properly flush Global entries 271 * on these CPUs when PCIDs are enabled. 272 */ 273 static const struct x86_cpu_id invlpg_miss_ids[] = { 274 INTEL_MATCH(INTEL_FAM6_ALDERLAKE ), 275 INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ), 276 INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ), 277 INTEL_MATCH(INTEL_FAM6_RAPTORLAKE ), 278 INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P), 279 INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S), 280 {} 281 }; 282 283 static void setup_pcid(void) 284 { 285 if (!IS_ENABLED(CONFIG_X86_64)) 286 return; 287 288 if (!boot_cpu_has(X86_FEATURE_PCID)) 289 return; 290 291 if (x86_match_cpu(invlpg_miss_ids)) { 292 pr_info("Incomplete global flushes, disabling PCID"); 293 setup_clear_cpu_cap(X86_FEATURE_PCID); 294 return; 295 } 296 297 if (boot_cpu_has(X86_FEATURE_PGE)) { 298 /* 299 * This can't be cr4_set_bits_and_update_boot() -- the 300 * trampoline code can't handle CR4.PCIDE and it wouldn't 301 * do any good anyway. Despite the name, 302 * cr4_set_bits_and_update_boot() doesn't actually cause 303 * the bits in question to remain set all the way through 304 * the secondary boot asm. 305 * 306 * Instead, we brute-force it and set CR4.PCIDE manually in 307 * start_secondary(). 308 */ 309 cr4_set_bits(X86_CR4_PCIDE); 310 311 /* 312 * INVPCID's single-context modes (2/3) only work if we set 313 * X86_CR4_PCIDE, *and* we INVPCID support. It's unusable 314 * on systems that have X86_CR4_PCIDE clear, or that have 315 * no INVPCID support at all. 316 */ 317 if (boot_cpu_has(X86_FEATURE_INVPCID)) 318 setup_force_cpu_cap(X86_FEATURE_INVPCID_SINGLE); 319 } else { 320 /* 321 * flush_tlb_all(), as currently implemented, won't work if 322 * PCID is on but PGE is not. Since that combination 323 * doesn't exist on real hardware, there's no reason to try 324 * to fully support it, but it's polite to avoid corrupting 325 * data if we're on an improperly configured VM. 326 */ 327 setup_clear_cpu_cap(X86_FEATURE_PCID); 328 } 329 } 330 331 #ifdef CONFIG_X86_32 332 #define NR_RANGE_MR 3 333 #else /* CONFIG_X86_64 */ 334 #define NR_RANGE_MR 5 335 #endif 336 337 static int __meminit save_mr(struct map_range *mr, int nr_range, 338 unsigned long start_pfn, unsigned long end_pfn, 339 unsigned long page_size_mask) 340 { 341 if (start_pfn < end_pfn) { 342 if (nr_range >= NR_RANGE_MR) 343 panic("run out of range for init_memory_mapping\n"); 344 mr[nr_range].start = start_pfn<<PAGE_SHIFT; 345 mr[nr_range].end = end_pfn<<PAGE_SHIFT; 346 mr[nr_range].page_size_mask = page_size_mask; 347 nr_range++; 348 } 349 350 return nr_range; 351 } 352 353 /* 354 * adjust the page_size_mask for small range to go with 355 * big page size instead small one if nearby are ram too. 356 */ 357 static void __ref adjust_range_page_size_mask(struct map_range *mr, 358 int nr_range) 359 { 360 int i; 361 362 for (i = 0; i < nr_range; i++) { 363 if ((page_size_mask & (1<<PG_LEVEL_2M)) && 364 !(mr[i].page_size_mask & (1<<PG_LEVEL_2M))) { 365 unsigned long start = round_down(mr[i].start, PMD_SIZE); 366 unsigned long end = round_up(mr[i].end, PMD_SIZE); 367 368 #ifdef CONFIG_X86_32 369 if ((end >> PAGE_SHIFT) > max_low_pfn) 370 continue; 371 #endif 372 373 if (memblock_is_region_memory(start, end - start)) 374 mr[i].page_size_mask |= 1<<PG_LEVEL_2M; 375 } 376 if ((page_size_mask & (1<<PG_LEVEL_1G)) && 377 !(mr[i].page_size_mask & (1<<PG_LEVEL_1G))) { 378 unsigned long start = round_down(mr[i].start, PUD_SIZE); 379 unsigned long end = round_up(mr[i].end, PUD_SIZE); 380 381 if (memblock_is_region_memory(start, end - start)) 382 mr[i].page_size_mask |= 1<<PG_LEVEL_1G; 383 } 384 } 385 } 386 387 static const char *page_size_string(struct map_range *mr) 388 { 389 static const char str_1g[] = "1G"; 390 static const char str_2m[] = "2M"; 391 static const char str_4m[] = "4M"; 392 static const char str_4k[] = "4k"; 393 394 if (mr->page_size_mask & (1<<PG_LEVEL_1G)) 395 return str_1g; 396 /* 397 * 32-bit without PAE has a 4M large page size. 398 * PG_LEVEL_2M is misnamed, but we can at least 399 * print out the right size in the string. 400 */ 401 if (IS_ENABLED(CONFIG_X86_32) && 402 !IS_ENABLED(CONFIG_X86_PAE) && 403 mr->page_size_mask & (1<<PG_LEVEL_2M)) 404 return str_4m; 405 406 if (mr->page_size_mask & (1<<PG_LEVEL_2M)) 407 return str_2m; 408 409 return str_4k; 410 } 411 412 static int __meminit split_mem_range(struct map_range *mr, int nr_range, 413 unsigned long start, 414 unsigned long end) 415 { 416 unsigned long start_pfn, end_pfn, limit_pfn; 417 unsigned long pfn; 418 int i; 419 420 limit_pfn = PFN_DOWN(end); 421 422 /* head if not big page alignment ? */ 423 pfn = start_pfn = PFN_DOWN(start); 424 #ifdef CONFIG_X86_32 425 /* 426 * Don't use a large page for the first 2/4MB of memory 427 * because there are often fixed size MTRRs in there 428 * and overlapping MTRRs into large pages can cause 429 * slowdowns. 430 */ 431 if (pfn == 0) 432 end_pfn = PFN_DOWN(PMD_SIZE); 433 else 434 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 435 #else /* CONFIG_X86_64 */ 436 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 437 #endif 438 if (end_pfn > limit_pfn) 439 end_pfn = limit_pfn; 440 if (start_pfn < end_pfn) { 441 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); 442 pfn = end_pfn; 443 } 444 445 /* big page (2M) range */ 446 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 447 #ifdef CONFIG_X86_32 448 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 449 #else /* CONFIG_X86_64 */ 450 end_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE)); 451 if (end_pfn > round_down(limit_pfn, PFN_DOWN(PMD_SIZE))) 452 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 453 #endif 454 455 if (start_pfn < end_pfn) { 456 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 457 page_size_mask & (1<<PG_LEVEL_2M)); 458 pfn = end_pfn; 459 } 460 461 #ifdef CONFIG_X86_64 462 /* big page (1G) range */ 463 start_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE)); 464 end_pfn = round_down(limit_pfn, PFN_DOWN(PUD_SIZE)); 465 if (start_pfn < end_pfn) { 466 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 467 page_size_mask & 468 ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G))); 469 pfn = end_pfn; 470 } 471 472 /* tail is not big page (1G) alignment */ 473 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 474 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 475 if (start_pfn < end_pfn) { 476 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 477 page_size_mask & (1<<PG_LEVEL_2M)); 478 pfn = end_pfn; 479 } 480 #endif 481 482 /* tail is not big page (2M) alignment */ 483 start_pfn = pfn; 484 end_pfn = limit_pfn; 485 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); 486 487 if (!after_bootmem) 488 adjust_range_page_size_mask(mr, nr_range); 489 490 /* try to merge same page size and continuous */ 491 for (i = 0; nr_range > 1 && i < nr_range - 1; i++) { 492 unsigned long old_start; 493 if (mr[i].end != mr[i+1].start || 494 mr[i].page_size_mask != mr[i+1].page_size_mask) 495 continue; 496 /* move it */ 497 old_start = mr[i].start; 498 memmove(&mr[i], &mr[i+1], 499 (nr_range - 1 - i) * sizeof(struct map_range)); 500 mr[i--].start = old_start; 501 nr_range--; 502 } 503 504 for (i = 0; i < nr_range; i++) 505 pr_debug(" [mem %#010lx-%#010lx] page %s\n", 506 mr[i].start, mr[i].end - 1, 507 page_size_string(&mr[i])); 508 509 return nr_range; 510 } 511 512 struct range pfn_mapped[E820_MAX_ENTRIES]; 513 int nr_pfn_mapped; 514 515 static void add_pfn_range_mapped(unsigned long start_pfn, unsigned long end_pfn) 516 { 517 nr_pfn_mapped = add_range_with_merge(pfn_mapped, E820_MAX_ENTRIES, 518 nr_pfn_mapped, start_pfn, end_pfn); 519 nr_pfn_mapped = clean_sort_range(pfn_mapped, E820_MAX_ENTRIES); 520 521 max_pfn_mapped = max(max_pfn_mapped, end_pfn); 522 523 if (start_pfn < (1UL<<(32-PAGE_SHIFT))) 524 max_low_pfn_mapped = max(max_low_pfn_mapped, 525 min(end_pfn, 1UL<<(32-PAGE_SHIFT))); 526 } 527 528 bool pfn_range_is_mapped(unsigned long start_pfn, unsigned long end_pfn) 529 { 530 int i; 531 532 for (i = 0; i < nr_pfn_mapped; i++) 533 if ((start_pfn >= pfn_mapped[i].start) && 534 (end_pfn <= pfn_mapped[i].end)) 535 return true; 536 537 return false; 538 } 539 540 /* 541 * Setup the direct mapping of the physical memory at PAGE_OFFSET. 542 * This runs before bootmem is initialized and gets pages directly from 543 * the physical memory. To access them they are temporarily mapped. 544 */ 545 unsigned long __ref init_memory_mapping(unsigned long start, 546 unsigned long end, pgprot_t prot) 547 { 548 struct map_range mr[NR_RANGE_MR]; 549 unsigned long ret = 0; 550 int nr_range, i; 551 552 pr_debug("init_memory_mapping: [mem %#010lx-%#010lx]\n", 553 start, end - 1); 554 555 memset(mr, 0, sizeof(mr)); 556 nr_range = split_mem_range(mr, 0, start, end); 557 558 for (i = 0; i < nr_range; i++) 559 ret = kernel_physical_mapping_init(mr[i].start, mr[i].end, 560 mr[i].page_size_mask, 561 prot); 562 563 add_pfn_range_mapped(start >> PAGE_SHIFT, ret >> PAGE_SHIFT); 564 565 return ret >> PAGE_SHIFT; 566 } 567 568 /* 569 * We need to iterate through the E820 memory map and create direct mappings 570 * for only E820_TYPE_RAM and E820_KERN_RESERVED regions. We cannot simply 571 * create direct mappings for all pfns from [0 to max_low_pfn) and 572 * [4GB to max_pfn) because of possible memory holes in high addresses 573 * that cannot be marked as UC by fixed/variable range MTRRs. 574 * Depending on the alignment of E820 ranges, this may possibly result 575 * in using smaller size (i.e. 4K instead of 2M or 1G) page tables. 576 * 577 * init_mem_mapping() calls init_range_memory_mapping() with big range. 578 * That range would have hole in the middle or ends, and only ram parts 579 * will be mapped in init_range_memory_mapping(). 580 */ 581 static unsigned long __init init_range_memory_mapping( 582 unsigned long r_start, 583 unsigned long r_end) 584 { 585 unsigned long start_pfn, end_pfn; 586 unsigned long mapped_ram_size = 0; 587 int i; 588 589 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) { 590 u64 start = clamp_val(PFN_PHYS(start_pfn), r_start, r_end); 591 u64 end = clamp_val(PFN_PHYS(end_pfn), r_start, r_end); 592 if (start >= end) 593 continue; 594 595 /* 596 * if it is overlapping with brk pgt, we need to 597 * alloc pgt buf from memblock instead. 598 */ 599 can_use_brk_pgt = max(start, (u64)pgt_buf_end<<PAGE_SHIFT) >= 600 min(end, (u64)pgt_buf_top<<PAGE_SHIFT); 601 init_memory_mapping(start, end, PAGE_KERNEL); 602 mapped_ram_size += end - start; 603 can_use_brk_pgt = true; 604 } 605 606 return mapped_ram_size; 607 } 608 609 static unsigned long __init get_new_step_size(unsigned long step_size) 610 { 611 /* 612 * Initial mapped size is PMD_SIZE (2M). 613 * We can not set step_size to be PUD_SIZE (1G) yet. 614 * In worse case, when we cross the 1G boundary, and 615 * PG_LEVEL_2M is not set, we will need 1+1+512 pages (2M + 8k) 616 * to map 1G range with PTE. Hence we use one less than the 617 * difference of page table level shifts. 618 * 619 * Don't need to worry about overflow in the top-down case, on 32bit, 620 * when step_size is 0, round_down() returns 0 for start, and that 621 * turns it into 0x100000000ULL. 622 * In the bottom-up case, round_up(x, 0) returns 0 though too, which 623 * needs to be taken into consideration by the code below. 624 */ 625 return step_size << (PMD_SHIFT - PAGE_SHIFT - 1); 626 } 627 628 /** 629 * memory_map_top_down - Map [map_start, map_end) top down 630 * @map_start: start address of the target memory range 631 * @map_end: end address of the target memory range 632 * 633 * This function will setup direct mapping for memory range 634 * [map_start, map_end) in top-down. That said, the page tables 635 * will be allocated at the end of the memory, and we map the 636 * memory in top-down. 637 */ 638 static void __init memory_map_top_down(unsigned long map_start, 639 unsigned long map_end) 640 { 641 unsigned long real_end, last_start; 642 unsigned long step_size; 643 unsigned long addr; 644 unsigned long mapped_ram_size = 0; 645 646 /* 647 * Systems that have many reserved areas near top of the memory, 648 * e.g. QEMU with less than 1G RAM and EFI enabled, or Xen, will 649 * require lots of 4K mappings which may exhaust pgt_buf. 650 * Start with top-most PMD_SIZE range aligned at PMD_SIZE to ensure 651 * there is enough mapped memory that can be allocated from 652 * memblock. 653 */ 654 addr = memblock_phys_alloc_range(PMD_SIZE, PMD_SIZE, map_start, 655 map_end); 656 memblock_phys_free(addr, PMD_SIZE); 657 real_end = addr + PMD_SIZE; 658 659 /* step_size need to be small so pgt_buf from BRK could cover it */ 660 step_size = PMD_SIZE; 661 max_pfn_mapped = 0; /* will get exact value next */ 662 min_pfn_mapped = real_end >> PAGE_SHIFT; 663 last_start = real_end; 664 665 /* 666 * We start from the top (end of memory) and go to the bottom. 667 * The memblock_find_in_range() gets us a block of RAM from the 668 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages 669 * for page table. 670 */ 671 while (last_start > map_start) { 672 unsigned long start; 673 674 if (last_start > step_size) { 675 start = round_down(last_start - 1, step_size); 676 if (start < map_start) 677 start = map_start; 678 } else 679 start = map_start; 680 mapped_ram_size += init_range_memory_mapping(start, 681 last_start); 682 last_start = start; 683 min_pfn_mapped = last_start >> PAGE_SHIFT; 684 if (mapped_ram_size >= step_size) 685 step_size = get_new_step_size(step_size); 686 } 687 688 if (real_end < map_end) 689 init_range_memory_mapping(real_end, map_end); 690 } 691 692 /** 693 * memory_map_bottom_up - Map [map_start, map_end) bottom up 694 * @map_start: start address of the target memory range 695 * @map_end: end address of the target memory range 696 * 697 * This function will setup direct mapping for memory range 698 * [map_start, map_end) in bottom-up. Since we have limited the 699 * bottom-up allocation above the kernel, the page tables will 700 * be allocated just above the kernel and we map the memory 701 * in [map_start, map_end) in bottom-up. 702 */ 703 static void __init memory_map_bottom_up(unsigned long map_start, 704 unsigned long map_end) 705 { 706 unsigned long next, start; 707 unsigned long mapped_ram_size = 0; 708 /* step_size need to be small so pgt_buf from BRK could cover it */ 709 unsigned long step_size = PMD_SIZE; 710 711 start = map_start; 712 min_pfn_mapped = start >> PAGE_SHIFT; 713 714 /* 715 * We start from the bottom (@map_start) and go to the top (@map_end). 716 * The memblock_find_in_range() gets us a block of RAM from the 717 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages 718 * for page table. 719 */ 720 while (start < map_end) { 721 if (step_size && map_end - start > step_size) { 722 next = round_up(start + 1, step_size); 723 if (next > map_end) 724 next = map_end; 725 } else { 726 next = map_end; 727 } 728 729 mapped_ram_size += init_range_memory_mapping(start, next); 730 start = next; 731 732 if (mapped_ram_size >= step_size) 733 step_size = get_new_step_size(step_size); 734 } 735 } 736 737 /* 738 * The real mode trampoline, which is required for bootstrapping CPUs 739 * occupies only a small area under the low 1MB. See reserve_real_mode() 740 * for details. 741 * 742 * If KASLR is disabled the first PGD entry of the direct mapping is copied 743 * to map the real mode trampoline. 744 * 745 * If KASLR is enabled, copy only the PUD which covers the low 1MB 746 * area. This limits the randomization granularity to 1GB for both 4-level 747 * and 5-level paging. 748 */ 749 static void __init init_trampoline(void) 750 { 751 #ifdef CONFIG_X86_64 752 /* 753 * The code below will alias kernel page-tables in the user-range of the 754 * address space, including the Global bit. So global TLB entries will 755 * be created when using the trampoline page-table. 756 */ 757 if (!kaslr_memory_enabled()) 758 trampoline_pgd_entry = init_top_pgt[pgd_index(__PAGE_OFFSET)]; 759 else 760 init_trampoline_kaslr(); 761 #endif 762 } 763 764 void __init init_mem_mapping(void) 765 { 766 unsigned long end; 767 768 pti_check_boottime_disable(); 769 probe_page_size_mask(); 770 setup_pcid(); 771 772 #ifdef CONFIG_X86_64 773 end = max_pfn << PAGE_SHIFT; 774 #else 775 end = max_low_pfn << PAGE_SHIFT; 776 #endif 777 778 /* the ISA range is always mapped regardless of memory holes */ 779 init_memory_mapping(0, ISA_END_ADDRESS, PAGE_KERNEL); 780 781 /* Init the trampoline, possibly with KASLR memory offset */ 782 init_trampoline(); 783 784 /* 785 * If the allocation is in bottom-up direction, we setup direct mapping 786 * in bottom-up, otherwise we setup direct mapping in top-down. 787 */ 788 if (memblock_bottom_up()) { 789 unsigned long kernel_end = __pa_symbol(_end); 790 791 /* 792 * we need two separate calls here. This is because we want to 793 * allocate page tables above the kernel. So we first map 794 * [kernel_end, end) to make memory above the kernel be mapped 795 * as soon as possible. And then use page tables allocated above 796 * the kernel to map [ISA_END_ADDRESS, kernel_end). 797 */ 798 memory_map_bottom_up(kernel_end, end); 799 memory_map_bottom_up(ISA_END_ADDRESS, kernel_end); 800 } else { 801 memory_map_top_down(ISA_END_ADDRESS, end); 802 } 803 804 #ifdef CONFIG_X86_64 805 if (max_pfn > max_low_pfn) { 806 /* can we preserve max_low_pfn ?*/ 807 max_low_pfn = max_pfn; 808 } 809 #else 810 early_ioremap_page_table_range_init(); 811 #endif 812 813 load_cr3(swapper_pg_dir); 814 __flush_tlb_all(); 815 816 x86_init.hyper.init_mem_mapping(); 817 818 early_memtest(0, max_pfn_mapped << PAGE_SHIFT); 819 } 820 821 /* 822 * Initialize an mm_struct to be used during poking and a pointer to be used 823 * during patching. 824 */ 825 void __init poking_init(void) 826 { 827 spinlock_t *ptl; 828 pte_t *ptep; 829 830 poking_mm = mm_alloc(); 831 BUG_ON(!poking_mm); 832 833 /* Xen PV guests need the PGD to be pinned. */ 834 paravirt_enter_mmap(poking_mm); 835 836 /* 837 * Randomize the poking address, but make sure that the following page 838 * will be mapped at the same PMD. We need 2 pages, so find space for 3, 839 * and adjust the address if the PMD ends after the first one. 840 */ 841 poking_addr = TASK_UNMAPPED_BASE; 842 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 843 poking_addr += (kaslr_get_random_long("Poking") & PAGE_MASK) % 844 (TASK_SIZE - TASK_UNMAPPED_BASE - 3 * PAGE_SIZE); 845 846 if (((poking_addr + PAGE_SIZE) & ~PMD_MASK) == 0) 847 poking_addr += PAGE_SIZE; 848 849 /* 850 * We need to trigger the allocation of the page-tables that will be 851 * needed for poking now. Later, poking may be performed in an atomic 852 * section, which might cause allocation to fail. 853 */ 854 ptep = get_locked_pte(poking_mm, poking_addr, &ptl); 855 BUG_ON(!ptep); 856 pte_unmap_unlock(ptep, ptl); 857 } 858 859 /* 860 * devmem_is_allowed() checks to see if /dev/mem access to a certain address 861 * is valid. The argument is a physical page number. 862 * 863 * On x86, access has to be given to the first megabyte of RAM because that 864 * area traditionally contains BIOS code and data regions used by X, dosemu, 865 * and similar apps. Since they map the entire memory range, the whole range 866 * must be allowed (for mapping), but any areas that would otherwise be 867 * disallowed are flagged as being "zero filled" instead of rejected. 868 * Access has to be given to non-kernel-ram areas as well, these contain the 869 * PCI mmio resources as well as potential bios/acpi data regions. 870 */ 871 int devmem_is_allowed(unsigned long pagenr) 872 { 873 if (region_intersects(PFN_PHYS(pagenr), PAGE_SIZE, 874 IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE) 875 != REGION_DISJOINT) { 876 /* 877 * For disallowed memory regions in the low 1MB range, 878 * request that the page be shown as all zeros. 879 */ 880 if (pagenr < 256) 881 return 2; 882 883 return 0; 884 } 885 886 /* 887 * This must follow RAM test, since System RAM is considered a 888 * restricted resource under CONFIG_STRICT_DEVMEM. 889 */ 890 if (iomem_is_exclusive(pagenr << PAGE_SHIFT)) { 891 /* Low 1MB bypasses iomem restrictions. */ 892 if (pagenr < 256) 893 return 1; 894 895 return 0; 896 } 897 898 return 1; 899 } 900 901 void free_init_pages(const char *what, unsigned long begin, unsigned long end) 902 { 903 unsigned long begin_aligned, end_aligned; 904 905 /* Make sure boundaries are page aligned */ 906 begin_aligned = PAGE_ALIGN(begin); 907 end_aligned = end & PAGE_MASK; 908 909 if (WARN_ON(begin_aligned != begin || end_aligned != end)) { 910 begin = begin_aligned; 911 end = end_aligned; 912 } 913 914 if (begin >= end) 915 return; 916 917 /* 918 * If debugging page accesses then do not free this memory but 919 * mark them not present - any buggy init-section access will 920 * create a kernel page fault: 921 */ 922 if (debug_pagealloc_enabled()) { 923 pr_info("debug: unmapping init [mem %#010lx-%#010lx]\n", 924 begin, end - 1); 925 /* 926 * Inform kmemleak about the hole in the memory since the 927 * corresponding pages will be unmapped. 928 */ 929 kmemleak_free_part((void *)begin, end - begin); 930 set_memory_np(begin, (end - begin) >> PAGE_SHIFT); 931 } else { 932 /* 933 * We just marked the kernel text read only above, now that 934 * we are going to free part of that, we need to make that 935 * writeable and non-executable first. 936 */ 937 set_memory_nx(begin, (end - begin) >> PAGE_SHIFT); 938 set_memory_rw(begin, (end - begin) >> PAGE_SHIFT); 939 940 free_reserved_area((void *)begin, (void *)end, 941 POISON_FREE_INITMEM, what); 942 } 943 } 944 945 /* 946 * begin/end can be in the direct map or the "high kernel mapping" 947 * used for the kernel image only. free_init_pages() will do the 948 * right thing for either kind of address. 949 */ 950 void free_kernel_image_pages(const char *what, void *begin, void *end) 951 { 952 unsigned long begin_ul = (unsigned long)begin; 953 unsigned long end_ul = (unsigned long)end; 954 unsigned long len_pages = (end_ul - begin_ul) >> PAGE_SHIFT; 955 956 free_init_pages(what, begin_ul, end_ul); 957 958 /* 959 * PTI maps some of the kernel into userspace. For performance, 960 * this includes some kernel areas that do not contain secrets. 961 * Those areas might be adjacent to the parts of the kernel image 962 * being freed, which may contain secrets. Remove the "high kernel 963 * image mapping" for these freed areas, ensuring they are not even 964 * potentially vulnerable to Meltdown regardless of the specific 965 * optimizations PTI is currently using. 966 * 967 * The "noalias" prevents unmapping the direct map alias which is 968 * needed to access the freed pages. 969 * 970 * This is only valid for 64bit kernels. 32bit has only one mapping 971 * which can't be treated in this way for obvious reasons. 972 */ 973 if (IS_ENABLED(CONFIG_X86_64) && cpu_feature_enabled(X86_FEATURE_PTI)) 974 set_memory_np_noalias(begin_ul, len_pages); 975 } 976 977 void __ref free_initmem(void) 978 { 979 e820__reallocate_tables(); 980 981 mem_encrypt_free_decrypted_mem(); 982 983 free_kernel_image_pages("unused kernel image (initmem)", 984 &__init_begin, &__init_end); 985 } 986 987 #ifdef CONFIG_BLK_DEV_INITRD 988 void __init free_initrd_mem(unsigned long start, unsigned long end) 989 { 990 /* 991 * end could be not aligned, and We can not align that, 992 * decompressor could be confused by aligned initrd_end 993 * We already reserve the end partial page before in 994 * - i386_start_kernel() 995 * - x86_64_start_kernel() 996 * - relocate_initrd() 997 * So here We can do PAGE_ALIGN() safely to get partial page to be freed 998 */ 999 free_init_pages("initrd", start, PAGE_ALIGN(end)); 1000 } 1001 #endif 1002 1003 /* 1004 * Calculate the precise size of the DMA zone (first 16 MB of RAM), 1005 * and pass it to the MM layer - to help it set zone watermarks more 1006 * accurately. 1007 * 1008 * Done on 64-bit systems only for the time being, although 32-bit systems 1009 * might benefit from this as well. 1010 */ 1011 void __init memblock_find_dma_reserve(void) 1012 { 1013 #ifdef CONFIG_X86_64 1014 u64 nr_pages = 0, nr_free_pages = 0; 1015 unsigned long start_pfn, end_pfn; 1016 phys_addr_t start_addr, end_addr; 1017 int i; 1018 u64 u; 1019 1020 /* 1021 * Iterate over all memory ranges (free and reserved ones alike), 1022 * to calculate the total number of pages in the first 16 MB of RAM: 1023 */ 1024 nr_pages = 0; 1025 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) { 1026 start_pfn = min(start_pfn, MAX_DMA_PFN); 1027 end_pfn = min(end_pfn, MAX_DMA_PFN); 1028 1029 nr_pages += end_pfn - start_pfn; 1030 } 1031 1032 /* 1033 * Iterate over free memory ranges to calculate the number of free 1034 * pages in the DMA zone, while not counting potential partial 1035 * pages at the beginning or the end of the range: 1036 */ 1037 nr_free_pages = 0; 1038 for_each_free_mem_range(u, NUMA_NO_NODE, MEMBLOCK_NONE, &start_addr, &end_addr, NULL) { 1039 start_pfn = min_t(unsigned long, PFN_UP(start_addr), MAX_DMA_PFN); 1040 end_pfn = min_t(unsigned long, PFN_DOWN(end_addr), MAX_DMA_PFN); 1041 1042 if (start_pfn < end_pfn) 1043 nr_free_pages += end_pfn - start_pfn; 1044 } 1045 1046 set_dma_reserve(nr_pages - nr_free_pages); 1047 #endif 1048 } 1049 1050 void __init zone_sizes_init(void) 1051 { 1052 unsigned long max_zone_pfns[MAX_NR_ZONES]; 1053 1054 memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); 1055 1056 #ifdef CONFIG_ZONE_DMA 1057 max_zone_pfns[ZONE_DMA] = min(MAX_DMA_PFN, max_low_pfn); 1058 #endif 1059 #ifdef CONFIG_ZONE_DMA32 1060 max_zone_pfns[ZONE_DMA32] = min(MAX_DMA32_PFN, max_low_pfn); 1061 #endif 1062 max_zone_pfns[ZONE_NORMAL] = max_low_pfn; 1063 #ifdef CONFIG_HIGHMEM 1064 max_zone_pfns[ZONE_HIGHMEM] = max_pfn; 1065 #endif 1066 1067 free_area_init(max_zone_pfns); 1068 } 1069 1070 __visible DEFINE_PER_CPU_ALIGNED(struct tlb_state, cpu_tlbstate) = { 1071 .loaded_mm = &init_mm, 1072 .next_asid = 1, 1073 .cr4 = ~0UL, /* fail hard if we screw up cr4 shadow initialization */ 1074 }; 1075 1076 #ifdef CONFIG_ADDRESS_MASKING 1077 DEFINE_PER_CPU(u64, tlbstate_untag_mask); 1078 EXPORT_PER_CPU_SYMBOL(tlbstate_untag_mask); 1079 #endif 1080 1081 void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache) 1082 { 1083 /* entry 0 MUST be WB (hardwired to speed up translations) */ 1084 BUG_ON(!entry && cache != _PAGE_CACHE_MODE_WB); 1085 1086 __cachemode2pte_tbl[cache] = __cm_idx2pte(entry); 1087 __pte2cachemode_tbl[entry] = cache; 1088 } 1089 1090 #ifdef CONFIG_SWAP 1091 unsigned long arch_max_swapfile_size(void) 1092 { 1093 unsigned long pages; 1094 1095 pages = generic_max_swapfile_size(); 1096 1097 if (boot_cpu_has_bug(X86_BUG_L1TF) && l1tf_mitigation != L1TF_MITIGATION_OFF) { 1098 /* Limit the swap file size to MAX_PA/2 for L1TF workaround */ 1099 unsigned long long l1tf_limit = l1tf_pfn_limit(); 1100 /* 1101 * We encode swap offsets also with 3 bits below those for pfn 1102 * which makes the usable limit higher. 1103 */ 1104 #if CONFIG_PGTABLE_LEVELS > 2 1105 l1tf_limit <<= PAGE_SHIFT - SWP_OFFSET_FIRST_BIT; 1106 #endif 1107 pages = min_t(unsigned long long, l1tf_limit, pages); 1108 } 1109 return pages; 1110 } 1111 #endif 1112