1 #include <linux/gfp.h> 2 #include <linux/initrd.h> 3 #include <linux/ioport.h> 4 #include <linux/swap.h> 5 #include <linux/memblock.h> 6 #include <linux/swapfile.h> 7 #include <linux/swapops.h> 8 #include <linux/kmemleak.h> 9 #include <linux/sched/task.h> 10 11 #include <asm/set_memory.h> 12 #include <asm/cpu_device_id.h> 13 #include <asm/e820/api.h> 14 #include <asm/init.h> 15 #include <asm/page.h> 16 #include <asm/page_types.h> 17 #include <asm/sections.h> 18 #include <asm/setup.h> 19 #include <asm/tlbflush.h> 20 #include <asm/tlb.h> 21 #include <asm/proto.h> 22 #include <asm/dma.h> /* for MAX_DMA_PFN */ 23 #include <asm/kaslr.h> 24 #include <asm/hypervisor.h> 25 #include <asm/cpufeature.h> 26 #include <asm/pti.h> 27 #include <asm/text-patching.h> 28 #include <asm/memtype.h> 29 #include <asm/paravirt.h> 30 31 /* 32 * We need to define the tracepoints somewhere, and tlb.c 33 * is only compiled when SMP=y. 34 */ 35 #include <trace/events/tlb.h> 36 37 #include "mm_internal.h" 38 39 /* 40 * Tables translating between page_cache_type_t and pte encoding. 41 * 42 * The default values are defined statically as minimal supported mode; 43 * WC and WT fall back to UC-. pat_init() updates these values to support 44 * more cache modes, WC and WT, when it is safe to do so. See pat_init() 45 * for the details. Note, __early_ioremap() used during early boot-time 46 * takes pgprot_t (pte encoding) and does not use these tables. 47 * 48 * Index into __cachemode2pte_tbl[] is the cachemode. 49 * 50 * Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte 51 * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2. 52 */ 53 static uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = { 54 [_PAGE_CACHE_MODE_WB ] = 0 | 0 , 55 [_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD, 56 [_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD, 57 [_PAGE_CACHE_MODE_UC ] = _PAGE_PWT | _PAGE_PCD, 58 [_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD, 59 [_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD, 60 }; 61 62 unsigned long cachemode2protval(enum page_cache_mode pcm) 63 { 64 if (likely(pcm == 0)) 65 return 0; 66 return __cachemode2pte_tbl[pcm]; 67 } 68 EXPORT_SYMBOL(cachemode2protval); 69 70 static uint8_t __pte2cachemode_tbl[8] = { 71 [__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB, 72 [__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_UC_MINUS, 73 [__pte2cm_idx( 0 | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC_MINUS, 74 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC, 75 [__pte2cm_idx( 0 | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_WB, 76 [__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS, 77 [__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS, 78 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC, 79 }; 80 81 /* 82 * Check that the write-protect PAT entry is set for write-protect. 83 * To do this without making assumptions how PAT has been set up (Xen has 84 * another layout than the kernel), translate the _PAGE_CACHE_MODE_WP cache 85 * mode via the __cachemode2pte_tbl[] into protection bits (those protection 86 * bits will select a cache mode of WP or better), and then translate the 87 * protection bits back into the cache mode using __pte2cm_idx() and the 88 * __pte2cachemode_tbl[] array. This will return the really used cache mode. 89 */ 90 bool x86_has_pat_wp(void) 91 { 92 uint16_t prot = __cachemode2pte_tbl[_PAGE_CACHE_MODE_WP]; 93 94 return __pte2cachemode_tbl[__pte2cm_idx(prot)] == _PAGE_CACHE_MODE_WP; 95 } 96 97 enum page_cache_mode pgprot2cachemode(pgprot_t pgprot) 98 { 99 unsigned long masked; 100 101 masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK; 102 if (likely(masked == 0)) 103 return 0; 104 return __pte2cachemode_tbl[__pte2cm_idx(masked)]; 105 } 106 107 static unsigned long __initdata pgt_buf_start; 108 static unsigned long __initdata pgt_buf_end; 109 static unsigned long __initdata pgt_buf_top; 110 111 static unsigned long min_pfn_mapped; 112 113 static bool __initdata can_use_brk_pgt = true; 114 115 /* 116 * Pages returned are already directly mapped. 117 * 118 * Changing that is likely to break Xen, see commit: 119 * 120 * 279b706 x86,xen: introduce x86_init.mapping.pagetable_reserve 121 * 122 * for detailed information. 123 */ 124 __ref void *alloc_low_pages(unsigned int num) 125 { 126 unsigned long pfn; 127 int i; 128 129 if (after_bootmem) { 130 unsigned int order; 131 132 order = get_order((unsigned long)num << PAGE_SHIFT); 133 return (void *)__get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 134 } 135 136 if ((pgt_buf_end + num) > pgt_buf_top || !can_use_brk_pgt) { 137 unsigned long ret = 0; 138 139 if (min_pfn_mapped < max_pfn_mapped) { 140 ret = memblock_phys_alloc_range( 141 PAGE_SIZE * num, PAGE_SIZE, 142 min_pfn_mapped << PAGE_SHIFT, 143 max_pfn_mapped << PAGE_SHIFT); 144 } 145 if (!ret && can_use_brk_pgt) 146 ret = __pa(extend_brk(PAGE_SIZE * num, PAGE_SIZE)); 147 148 if (!ret) 149 panic("alloc_low_pages: can not alloc memory"); 150 151 pfn = ret >> PAGE_SHIFT; 152 } else { 153 pfn = pgt_buf_end; 154 pgt_buf_end += num; 155 } 156 157 for (i = 0; i < num; i++) { 158 void *adr; 159 160 adr = __va((pfn + i) << PAGE_SHIFT); 161 clear_page(adr); 162 } 163 164 return __va(pfn << PAGE_SHIFT); 165 } 166 167 /* 168 * By default need to be able to allocate page tables below PGD firstly for 169 * the 0-ISA_END_ADDRESS range and secondly for the initial PMD_SIZE mapping. 170 * With KASLR memory randomization, depending on the machine e820 memory and the 171 * PUD alignment, twice that many pages may be needed when KASLR memory 172 * randomization is enabled. 173 */ 174 175 #ifndef CONFIG_X86_5LEVEL 176 #define INIT_PGD_PAGE_TABLES 3 177 #else 178 #define INIT_PGD_PAGE_TABLES 4 179 #endif 180 181 #ifndef CONFIG_RANDOMIZE_MEMORY 182 #define INIT_PGD_PAGE_COUNT (2 * INIT_PGD_PAGE_TABLES) 183 #else 184 #define INIT_PGD_PAGE_COUNT (4 * INIT_PGD_PAGE_TABLES) 185 #endif 186 187 #define INIT_PGT_BUF_SIZE (INIT_PGD_PAGE_COUNT * PAGE_SIZE) 188 RESERVE_BRK(early_pgt_alloc, INIT_PGT_BUF_SIZE); 189 void __init early_alloc_pgt_buf(void) 190 { 191 unsigned long tables = INIT_PGT_BUF_SIZE; 192 phys_addr_t base; 193 194 base = __pa(extend_brk(tables, PAGE_SIZE)); 195 196 pgt_buf_start = base >> PAGE_SHIFT; 197 pgt_buf_end = pgt_buf_start; 198 pgt_buf_top = pgt_buf_start + (tables >> PAGE_SHIFT); 199 } 200 201 int after_bootmem; 202 203 early_param_on_off("gbpages", "nogbpages", direct_gbpages, CONFIG_X86_DIRECT_GBPAGES); 204 205 struct map_range { 206 unsigned long start; 207 unsigned long end; 208 unsigned page_size_mask; 209 }; 210 211 static int page_size_mask; 212 213 /* 214 * Save some of cr4 feature set we're using (e.g. Pentium 4MB 215 * enable and PPro Global page enable), so that any CPU's that boot 216 * up after us can get the correct flags. Invoked on the boot CPU. 217 */ 218 static inline void cr4_set_bits_and_update_boot(unsigned long mask) 219 { 220 mmu_cr4_features |= mask; 221 if (trampoline_cr4_features) 222 *trampoline_cr4_features = mmu_cr4_features; 223 cr4_set_bits(mask); 224 } 225 226 static void __init probe_page_size_mask(void) 227 { 228 /* 229 * For pagealloc debugging, identity mapping will use small pages. 230 * This will simplify cpa(), which otherwise needs to support splitting 231 * large pages into small in interrupt context, etc. 232 */ 233 if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled()) 234 page_size_mask |= 1 << PG_LEVEL_2M; 235 else 236 direct_gbpages = 0; 237 238 /* Enable PSE if available */ 239 if (boot_cpu_has(X86_FEATURE_PSE)) 240 cr4_set_bits_and_update_boot(X86_CR4_PSE); 241 242 /* Enable PGE if available */ 243 __supported_pte_mask &= ~_PAGE_GLOBAL; 244 if (boot_cpu_has(X86_FEATURE_PGE)) { 245 cr4_set_bits_and_update_boot(X86_CR4_PGE); 246 __supported_pte_mask |= _PAGE_GLOBAL; 247 } 248 249 /* By the default is everything supported: */ 250 __default_kernel_pte_mask = __supported_pte_mask; 251 /* Except when with PTI where the kernel is mostly non-Global: */ 252 if (cpu_feature_enabled(X86_FEATURE_PTI)) 253 __default_kernel_pte_mask &= ~_PAGE_GLOBAL; 254 255 /* Enable 1 GB linear kernel mappings if available: */ 256 if (direct_gbpages && boot_cpu_has(X86_FEATURE_GBPAGES)) { 257 printk(KERN_INFO "Using GB pages for direct mapping\n"); 258 page_size_mask |= 1 << PG_LEVEL_1G; 259 } else { 260 direct_gbpages = 0; 261 } 262 } 263 264 /* 265 * INVLPG may not properly flush Global entries 266 * on these CPUs when PCIDs are enabled. 267 */ 268 static const struct x86_cpu_id invlpg_miss_ids[] = { 269 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, 0), 270 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 0), 271 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, 0), 272 X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, 0), 273 X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, 0), 274 X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, 0), 275 {} 276 }; 277 278 static void setup_pcid(void) 279 { 280 if (!IS_ENABLED(CONFIG_X86_64)) 281 return; 282 283 if (!boot_cpu_has(X86_FEATURE_PCID)) 284 return; 285 286 if (x86_match_cpu(invlpg_miss_ids)) { 287 pr_info("Incomplete global flushes, disabling PCID"); 288 setup_clear_cpu_cap(X86_FEATURE_PCID); 289 return; 290 } 291 292 if (boot_cpu_has(X86_FEATURE_PGE)) { 293 /* 294 * This can't be cr4_set_bits_and_update_boot() -- the 295 * trampoline code can't handle CR4.PCIDE and it wouldn't 296 * do any good anyway. Despite the name, 297 * cr4_set_bits_and_update_boot() doesn't actually cause 298 * the bits in question to remain set all the way through 299 * the secondary boot asm. 300 * 301 * Instead, we brute-force it and set CR4.PCIDE manually in 302 * start_secondary(). 303 */ 304 cr4_set_bits(X86_CR4_PCIDE); 305 } else { 306 /* 307 * flush_tlb_all(), as currently implemented, won't work if 308 * PCID is on but PGE is not. Since that combination 309 * doesn't exist on real hardware, there's no reason to try 310 * to fully support it, but it's polite to avoid corrupting 311 * data if we're on an improperly configured VM. 312 */ 313 setup_clear_cpu_cap(X86_FEATURE_PCID); 314 } 315 } 316 317 #ifdef CONFIG_X86_32 318 #define NR_RANGE_MR 3 319 #else /* CONFIG_X86_64 */ 320 #define NR_RANGE_MR 5 321 #endif 322 323 static int __meminit save_mr(struct map_range *mr, int nr_range, 324 unsigned long start_pfn, unsigned long end_pfn, 325 unsigned long page_size_mask) 326 { 327 if (start_pfn < end_pfn) { 328 if (nr_range >= NR_RANGE_MR) 329 panic("run out of range for init_memory_mapping\n"); 330 mr[nr_range].start = start_pfn<<PAGE_SHIFT; 331 mr[nr_range].end = end_pfn<<PAGE_SHIFT; 332 mr[nr_range].page_size_mask = page_size_mask; 333 nr_range++; 334 } 335 336 return nr_range; 337 } 338 339 /* 340 * adjust the page_size_mask for small range to go with 341 * big page size instead small one if nearby are ram too. 342 */ 343 static void __ref adjust_range_page_size_mask(struct map_range *mr, 344 int nr_range) 345 { 346 int i; 347 348 for (i = 0; i < nr_range; i++) { 349 if ((page_size_mask & (1<<PG_LEVEL_2M)) && 350 !(mr[i].page_size_mask & (1<<PG_LEVEL_2M))) { 351 unsigned long start = round_down(mr[i].start, PMD_SIZE); 352 unsigned long end = round_up(mr[i].end, PMD_SIZE); 353 354 #ifdef CONFIG_X86_32 355 if ((end >> PAGE_SHIFT) > max_low_pfn) 356 continue; 357 #endif 358 359 if (memblock_is_region_memory(start, end - start)) 360 mr[i].page_size_mask |= 1<<PG_LEVEL_2M; 361 } 362 if ((page_size_mask & (1<<PG_LEVEL_1G)) && 363 !(mr[i].page_size_mask & (1<<PG_LEVEL_1G))) { 364 unsigned long start = round_down(mr[i].start, PUD_SIZE); 365 unsigned long end = round_up(mr[i].end, PUD_SIZE); 366 367 if (memblock_is_region_memory(start, end - start)) 368 mr[i].page_size_mask |= 1<<PG_LEVEL_1G; 369 } 370 } 371 } 372 373 static const char *page_size_string(struct map_range *mr) 374 { 375 static const char str_1g[] = "1G"; 376 static const char str_2m[] = "2M"; 377 static const char str_4m[] = "4M"; 378 static const char str_4k[] = "4k"; 379 380 if (mr->page_size_mask & (1<<PG_LEVEL_1G)) 381 return str_1g; 382 /* 383 * 32-bit without PAE has a 4M large page size. 384 * PG_LEVEL_2M is misnamed, but we can at least 385 * print out the right size in the string. 386 */ 387 if (IS_ENABLED(CONFIG_X86_32) && 388 !IS_ENABLED(CONFIG_X86_PAE) && 389 mr->page_size_mask & (1<<PG_LEVEL_2M)) 390 return str_4m; 391 392 if (mr->page_size_mask & (1<<PG_LEVEL_2M)) 393 return str_2m; 394 395 return str_4k; 396 } 397 398 static int __meminit split_mem_range(struct map_range *mr, int nr_range, 399 unsigned long start, 400 unsigned long end) 401 { 402 unsigned long start_pfn, end_pfn, limit_pfn; 403 unsigned long pfn; 404 int i; 405 406 limit_pfn = PFN_DOWN(end); 407 408 /* head if not big page alignment ? */ 409 pfn = start_pfn = PFN_DOWN(start); 410 #ifdef CONFIG_X86_32 411 /* 412 * Don't use a large page for the first 2/4MB of memory 413 * because there are often fixed size MTRRs in there 414 * and overlapping MTRRs into large pages can cause 415 * slowdowns. 416 */ 417 if (pfn == 0) 418 end_pfn = PFN_DOWN(PMD_SIZE); 419 else 420 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 421 #else /* CONFIG_X86_64 */ 422 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 423 #endif 424 if (end_pfn > limit_pfn) 425 end_pfn = limit_pfn; 426 if (start_pfn < end_pfn) { 427 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); 428 pfn = end_pfn; 429 } 430 431 /* big page (2M) range */ 432 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 433 #ifdef CONFIG_X86_32 434 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 435 #else /* CONFIG_X86_64 */ 436 end_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE)); 437 if (end_pfn > round_down(limit_pfn, PFN_DOWN(PMD_SIZE))) 438 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 439 #endif 440 441 if (start_pfn < end_pfn) { 442 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 443 page_size_mask & (1<<PG_LEVEL_2M)); 444 pfn = end_pfn; 445 } 446 447 #ifdef CONFIG_X86_64 448 /* big page (1G) range */ 449 start_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE)); 450 end_pfn = round_down(limit_pfn, PFN_DOWN(PUD_SIZE)); 451 if (start_pfn < end_pfn) { 452 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 453 page_size_mask & 454 ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G))); 455 pfn = end_pfn; 456 } 457 458 /* tail is not big page (1G) alignment */ 459 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 460 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 461 if (start_pfn < end_pfn) { 462 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 463 page_size_mask & (1<<PG_LEVEL_2M)); 464 pfn = end_pfn; 465 } 466 #endif 467 468 /* tail is not big page (2M) alignment */ 469 start_pfn = pfn; 470 end_pfn = limit_pfn; 471 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); 472 473 if (!after_bootmem) 474 adjust_range_page_size_mask(mr, nr_range); 475 476 /* try to merge same page size and continuous */ 477 for (i = 0; nr_range > 1 && i < nr_range - 1; i++) { 478 unsigned long old_start; 479 if (mr[i].end != mr[i+1].start || 480 mr[i].page_size_mask != mr[i+1].page_size_mask) 481 continue; 482 /* move it */ 483 old_start = mr[i].start; 484 memmove(&mr[i], &mr[i+1], 485 (nr_range - 1 - i) * sizeof(struct map_range)); 486 mr[i--].start = old_start; 487 nr_range--; 488 } 489 490 for (i = 0; i < nr_range; i++) 491 pr_debug(" [mem %#010lx-%#010lx] page %s\n", 492 mr[i].start, mr[i].end - 1, 493 page_size_string(&mr[i])); 494 495 return nr_range; 496 } 497 498 struct range pfn_mapped[E820_MAX_ENTRIES]; 499 int nr_pfn_mapped; 500 501 static void add_pfn_range_mapped(unsigned long start_pfn, unsigned long end_pfn) 502 { 503 nr_pfn_mapped = add_range_with_merge(pfn_mapped, E820_MAX_ENTRIES, 504 nr_pfn_mapped, start_pfn, end_pfn); 505 nr_pfn_mapped = clean_sort_range(pfn_mapped, E820_MAX_ENTRIES); 506 507 max_pfn_mapped = max(max_pfn_mapped, end_pfn); 508 509 if (start_pfn < (1UL<<(32-PAGE_SHIFT))) 510 max_low_pfn_mapped = max(max_low_pfn_mapped, 511 min(end_pfn, 1UL<<(32-PAGE_SHIFT))); 512 } 513 514 bool pfn_range_is_mapped(unsigned long start_pfn, unsigned long end_pfn) 515 { 516 int i; 517 518 for (i = 0; i < nr_pfn_mapped; i++) 519 if ((start_pfn >= pfn_mapped[i].start) && 520 (end_pfn <= pfn_mapped[i].end)) 521 return true; 522 523 return false; 524 } 525 526 /* 527 * Setup the direct mapping of the physical memory at PAGE_OFFSET. 528 * This runs before bootmem is initialized and gets pages directly from 529 * the physical memory. To access them they are temporarily mapped. 530 */ 531 unsigned long __ref init_memory_mapping(unsigned long start, 532 unsigned long end, pgprot_t prot) 533 { 534 struct map_range mr[NR_RANGE_MR]; 535 unsigned long ret = 0; 536 int nr_range, i; 537 538 pr_debug("init_memory_mapping: [mem %#010lx-%#010lx]\n", 539 start, end - 1); 540 541 memset(mr, 0, sizeof(mr)); 542 nr_range = split_mem_range(mr, 0, start, end); 543 544 for (i = 0; i < nr_range; i++) 545 ret = kernel_physical_mapping_init(mr[i].start, mr[i].end, 546 mr[i].page_size_mask, 547 prot); 548 549 add_pfn_range_mapped(start >> PAGE_SHIFT, ret >> PAGE_SHIFT); 550 551 return ret >> PAGE_SHIFT; 552 } 553 554 /* 555 * We need to iterate through the E820 memory map and create direct mappings 556 * for only E820_TYPE_RAM and E820_KERN_RESERVED regions. We cannot simply 557 * create direct mappings for all pfns from [0 to max_low_pfn) and 558 * [4GB to max_pfn) because of possible memory holes in high addresses 559 * that cannot be marked as UC by fixed/variable range MTRRs. 560 * Depending on the alignment of E820 ranges, this may possibly result 561 * in using smaller size (i.e. 4K instead of 2M or 1G) page tables. 562 * 563 * init_mem_mapping() calls init_range_memory_mapping() with big range. 564 * That range would have hole in the middle or ends, and only ram parts 565 * will be mapped in init_range_memory_mapping(). 566 */ 567 static unsigned long __init init_range_memory_mapping( 568 unsigned long r_start, 569 unsigned long r_end) 570 { 571 unsigned long start_pfn, end_pfn; 572 unsigned long mapped_ram_size = 0; 573 int i; 574 575 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) { 576 u64 start = clamp_val(PFN_PHYS(start_pfn), r_start, r_end); 577 u64 end = clamp_val(PFN_PHYS(end_pfn), r_start, r_end); 578 if (start >= end) 579 continue; 580 581 /* 582 * if it is overlapping with brk pgt, we need to 583 * alloc pgt buf from memblock instead. 584 */ 585 can_use_brk_pgt = max(start, (u64)pgt_buf_end<<PAGE_SHIFT) >= 586 min(end, (u64)pgt_buf_top<<PAGE_SHIFT); 587 init_memory_mapping(start, end, PAGE_KERNEL); 588 mapped_ram_size += end - start; 589 can_use_brk_pgt = true; 590 } 591 592 return mapped_ram_size; 593 } 594 595 static unsigned long __init get_new_step_size(unsigned long step_size) 596 { 597 /* 598 * Initial mapped size is PMD_SIZE (2M). 599 * We can not set step_size to be PUD_SIZE (1G) yet. 600 * In worse case, when we cross the 1G boundary, and 601 * PG_LEVEL_2M is not set, we will need 1+1+512 pages (2M + 8k) 602 * to map 1G range with PTE. Hence we use one less than the 603 * difference of page table level shifts. 604 * 605 * Don't need to worry about overflow in the top-down case, on 32bit, 606 * when step_size is 0, round_down() returns 0 for start, and that 607 * turns it into 0x100000000ULL. 608 * In the bottom-up case, round_up(x, 0) returns 0 though too, which 609 * needs to be taken into consideration by the code below. 610 */ 611 return step_size << (PMD_SHIFT - PAGE_SHIFT - 1); 612 } 613 614 /** 615 * memory_map_top_down - Map [map_start, map_end) top down 616 * @map_start: start address of the target memory range 617 * @map_end: end address of the target memory range 618 * 619 * This function will setup direct mapping for memory range 620 * [map_start, map_end) in top-down. That said, the page tables 621 * will be allocated at the end of the memory, and we map the 622 * memory in top-down. 623 */ 624 static void __init memory_map_top_down(unsigned long map_start, 625 unsigned long map_end) 626 { 627 unsigned long real_end, last_start; 628 unsigned long step_size; 629 unsigned long addr; 630 unsigned long mapped_ram_size = 0; 631 632 /* 633 * Systems that have many reserved areas near top of the memory, 634 * e.g. QEMU with less than 1G RAM and EFI enabled, or Xen, will 635 * require lots of 4K mappings which may exhaust pgt_buf. 636 * Start with top-most PMD_SIZE range aligned at PMD_SIZE to ensure 637 * there is enough mapped memory that can be allocated from 638 * memblock. 639 */ 640 addr = memblock_phys_alloc_range(PMD_SIZE, PMD_SIZE, map_start, 641 map_end); 642 memblock_phys_free(addr, PMD_SIZE); 643 real_end = addr + PMD_SIZE; 644 645 /* step_size need to be small so pgt_buf from BRK could cover it */ 646 step_size = PMD_SIZE; 647 max_pfn_mapped = 0; /* will get exact value next */ 648 min_pfn_mapped = real_end >> PAGE_SHIFT; 649 last_start = real_end; 650 651 /* 652 * We start from the top (end of memory) and go to the bottom. 653 * The memblock_find_in_range() gets us a block of RAM from the 654 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages 655 * for page table. 656 */ 657 while (last_start > map_start) { 658 unsigned long start; 659 660 if (last_start > step_size) { 661 start = round_down(last_start - 1, step_size); 662 if (start < map_start) 663 start = map_start; 664 } else 665 start = map_start; 666 mapped_ram_size += init_range_memory_mapping(start, 667 last_start); 668 last_start = start; 669 min_pfn_mapped = last_start >> PAGE_SHIFT; 670 if (mapped_ram_size >= step_size) 671 step_size = get_new_step_size(step_size); 672 } 673 674 if (real_end < map_end) 675 init_range_memory_mapping(real_end, map_end); 676 } 677 678 /** 679 * memory_map_bottom_up - Map [map_start, map_end) bottom up 680 * @map_start: start address of the target memory range 681 * @map_end: end address of the target memory range 682 * 683 * This function will setup direct mapping for memory range 684 * [map_start, map_end) in bottom-up. Since we have limited the 685 * bottom-up allocation above the kernel, the page tables will 686 * be allocated just above the kernel and we map the memory 687 * in [map_start, map_end) in bottom-up. 688 */ 689 static void __init memory_map_bottom_up(unsigned long map_start, 690 unsigned long map_end) 691 { 692 unsigned long next, start; 693 unsigned long mapped_ram_size = 0; 694 /* step_size need to be small so pgt_buf from BRK could cover it */ 695 unsigned long step_size = PMD_SIZE; 696 697 start = map_start; 698 min_pfn_mapped = start >> PAGE_SHIFT; 699 700 /* 701 * We start from the bottom (@map_start) and go to the top (@map_end). 702 * The memblock_find_in_range() gets us a block of RAM from the 703 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages 704 * for page table. 705 */ 706 while (start < map_end) { 707 if (step_size && map_end - start > step_size) { 708 next = round_up(start + 1, step_size); 709 if (next > map_end) 710 next = map_end; 711 } else { 712 next = map_end; 713 } 714 715 mapped_ram_size += init_range_memory_mapping(start, next); 716 start = next; 717 718 if (mapped_ram_size >= step_size) 719 step_size = get_new_step_size(step_size); 720 } 721 } 722 723 /* 724 * The real mode trampoline, which is required for bootstrapping CPUs 725 * occupies only a small area under the low 1MB. See reserve_real_mode() 726 * for details. 727 * 728 * If KASLR is disabled the first PGD entry of the direct mapping is copied 729 * to map the real mode trampoline. 730 * 731 * If KASLR is enabled, copy only the PUD which covers the low 1MB 732 * area. This limits the randomization granularity to 1GB for both 4-level 733 * and 5-level paging. 734 */ 735 static void __init init_trampoline(void) 736 { 737 #ifdef CONFIG_X86_64 738 /* 739 * The code below will alias kernel page-tables in the user-range of the 740 * address space, including the Global bit. So global TLB entries will 741 * be created when using the trampoline page-table. 742 */ 743 if (!kaslr_memory_enabled()) 744 trampoline_pgd_entry = init_top_pgt[pgd_index(__PAGE_OFFSET)]; 745 else 746 init_trampoline_kaslr(); 747 #endif 748 } 749 750 void __init init_mem_mapping(void) 751 { 752 unsigned long end; 753 754 pti_check_boottime_disable(); 755 probe_page_size_mask(); 756 setup_pcid(); 757 758 #ifdef CONFIG_X86_64 759 end = max_pfn << PAGE_SHIFT; 760 #else 761 end = max_low_pfn << PAGE_SHIFT; 762 #endif 763 764 /* the ISA range is always mapped regardless of memory holes */ 765 init_memory_mapping(0, ISA_END_ADDRESS, PAGE_KERNEL); 766 767 /* Init the trampoline, possibly with KASLR memory offset */ 768 init_trampoline(); 769 770 /* 771 * If the allocation is in bottom-up direction, we setup direct mapping 772 * in bottom-up, otherwise we setup direct mapping in top-down. 773 */ 774 if (memblock_bottom_up()) { 775 unsigned long kernel_end = __pa_symbol(_end); 776 777 /* 778 * we need two separate calls here. This is because we want to 779 * allocate page tables above the kernel. So we first map 780 * [kernel_end, end) to make memory above the kernel be mapped 781 * as soon as possible. And then use page tables allocated above 782 * the kernel to map [ISA_END_ADDRESS, kernel_end). 783 */ 784 memory_map_bottom_up(kernel_end, end); 785 memory_map_bottom_up(ISA_END_ADDRESS, kernel_end); 786 } else { 787 memory_map_top_down(ISA_END_ADDRESS, end); 788 } 789 790 #ifdef CONFIG_X86_64 791 if (max_pfn > max_low_pfn) { 792 /* can we preserve max_low_pfn ?*/ 793 max_low_pfn = max_pfn; 794 } 795 #else 796 early_ioremap_page_table_range_init(); 797 #endif 798 799 load_cr3(swapper_pg_dir); 800 __flush_tlb_all(); 801 802 x86_init.hyper.init_mem_mapping(); 803 804 early_memtest(0, max_pfn_mapped << PAGE_SHIFT); 805 } 806 807 /* 808 * Initialize an mm_struct to be used during poking and a pointer to be used 809 * during patching. 810 */ 811 void __init poking_init(void) 812 { 813 spinlock_t *ptl; 814 pte_t *ptep; 815 816 poking_mm = mm_alloc(); 817 BUG_ON(!poking_mm); 818 819 /* Xen PV guests need the PGD to be pinned. */ 820 paravirt_enter_mmap(poking_mm); 821 822 /* 823 * Randomize the poking address, but make sure that the following page 824 * will be mapped at the same PMD. We need 2 pages, so find space for 3, 825 * and adjust the address if the PMD ends after the first one. 826 */ 827 poking_addr = TASK_UNMAPPED_BASE; 828 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 829 poking_addr += (kaslr_get_random_long("Poking") & PAGE_MASK) % 830 (TASK_SIZE - TASK_UNMAPPED_BASE - 3 * PAGE_SIZE); 831 832 if (((poking_addr + PAGE_SIZE) & ~PMD_MASK) == 0) 833 poking_addr += PAGE_SIZE; 834 835 /* 836 * We need to trigger the allocation of the page-tables that will be 837 * needed for poking now. Later, poking may be performed in an atomic 838 * section, which might cause allocation to fail. 839 */ 840 ptep = get_locked_pte(poking_mm, poking_addr, &ptl); 841 BUG_ON(!ptep); 842 pte_unmap_unlock(ptep, ptl); 843 } 844 845 /* 846 * devmem_is_allowed() checks to see if /dev/mem access to a certain address 847 * is valid. The argument is a physical page number. 848 * 849 * On x86, access has to be given to the first megabyte of RAM because that 850 * area traditionally contains BIOS code and data regions used by X, dosemu, 851 * and similar apps. Since they map the entire memory range, the whole range 852 * must be allowed (for mapping), but any areas that would otherwise be 853 * disallowed are flagged as being "zero filled" instead of rejected. 854 * Access has to be given to non-kernel-ram areas as well, these contain the 855 * PCI mmio resources as well as potential bios/acpi data regions. 856 */ 857 int devmem_is_allowed(unsigned long pagenr) 858 { 859 if (region_intersects(PFN_PHYS(pagenr), PAGE_SIZE, 860 IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE) 861 != REGION_DISJOINT) { 862 /* 863 * For disallowed memory regions in the low 1MB range, 864 * request that the page be shown as all zeros. 865 */ 866 if (pagenr < 256) 867 return 2; 868 869 return 0; 870 } 871 872 /* 873 * This must follow RAM test, since System RAM is considered a 874 * restricted resource under CONFIG_STRICT_DEVMEM. 875 */ 876 if (iomem_is_exclusive(pagenr << PAGE_SHIFT)) { 877 /* Low 1MB bypasses iomem restrictions. */ 878 if (pagenr < 256) 879 return 1; 880 881 return 0; 882 } 883 884 return 1; 885 } 886 887 void free_init_pages(const char *what, unsigned long begin, unsigned long end) 888 { 889 unsigned long begin_aligned, end_aligned; 890 891 /* Make sure boundaries are page aligned */ 892 begin_aligned = PAGE_ALIGN(begin); 893 end_aligned = end & PAGE_MASK; 894 895 if (WARN_ON(begin_aligned != begin || end_aligned != end)) { 896 begin = begin_aligned; 897 end = end_aligned; 898 } 899 900 if (begin >= end) 901 return; 902 903 /* 904 * If debugging page accesses then do not free this memory but 905 * mark them not present - any buggy init-section access will 906 * create a kernel page fault: 907 */ 908 if (debug_pagealloc_enabled()) { 909 pr_info("debug: unmapping init [mem %#010lx-%#010lx]\n", 910 begin, end - 1); 911 /* 912 * Inform kmemleak about the hole in the memory since the 913 * corresponding pages will be unmapped. 914 */ 915 kmemleak_free_part((void *)begin, end - begin); 916 set_memory_np(begin, (end - begin) >> PAGE_SHIFT); 917 } else { 918 /* 919 * We just marked the kernel text read only above, now that 920 * we are going to free part of that, we need to make that 921 * writeable and non-executable first. 922 */ 923 set_memory_nx(begin, (end - begin) >> PAGE_SHIFT); 924 set_memory_rw(begin, (end - begin) >> PAGE_SHIFT); 925 926 free_reserved_area((void *)begin, (void *)end, 927 POISON_FREE_INITMEM, what); 928 } 929 } 930 931 /* 932 * begin/end can be in the direct map or the "high kernel mapping" 933 * used for the kernel image only. free_init_pages() will do the 934 * right thing for either kind of address. 935 */ 936 void free_kernel_image_pages(const char *what, void *begin, void *end) 937 { 938 unsigned long begin_ul = (unsigned long)begin; 939 unsigned long end_ul = (unsigned long)end; 940 unsigned long len_pages = (end_ul - begin_ul) >> PAGE_SHIFT; 941 942 free_init_pages(what, begin_ul, end_ul); 943 944 /* 945 * PTI maps some of the kernel into userspace. For performance, 946 * this includes some kernel areas that do not contain secrets. 947 * Those areas might be adjacent to the parts of the kernel image 948 * being freed, which may contain secrets. Remove the "high kernel 949 * image mapping" for these freed areas, ensuring they are not even 950 * potentially vulnerable to Meltdown regardless of the specific 951 * optimizations PTI is currently using. 952 * 953 * The "noalias" prevents unmapping the direct map alias which is 954 * needed to access the freed pages. 955 * 956 * This is only valid for 64bit kernels. 32bit has only one mapping 957 * which can't be treated in this way for obvious reasons. 958 */ 959 if (IS_ENABLED(CONFIG_X86_64) && cpu_feature_enabled(X86_FEATURE_PTI)) 960 set_memory_np_noalias(begin_ul, len_pages); 961 } 962 963 void __ref free_initmem(void) 964 { 965 e820__reallocate_tables(); 966 967 mem_encrypt_free_decrypted_mem(); 968 969 free_kernel_image_pages("unused kernel image (initmem)", 970 &__init_begin, &__init_end); 971 } 972 973 #ifdef CONFIG_BLK_DEV_INITRD 974 void __init free_initrd_mem(unsigned long start, unsigned long end) 975 { 976 /* 977 * end could be not aligned, and We can not align that, 978 * decompressor could be confused by aligned initrd_end 979 * We already reserve the end partial page before in 980 * - i386_start_kernel() 981 * - x86_64_start_kernel() 982 * - relocate_initrd() 983 * So here We can do PAGE_ALIGN() safely to get partial page to be freed 984 */ 985 free_init_pages("initrd", start, PAGE_ALIGN(end)); 986 } 987 #endif 988 989 /* 990 * Calculate the precise size of the DMA zone (first 16 MB of RAM), 991 * and pass it to the MM layer - to help it set zone watermarks more 992 * accurately. 993 * 994 * Done on 64-bit systems only for the time being, although 32-bit systems 995 * might benefit from this as well. 996 */ 997 void __init memblock_find_dma_reserve(void) 998 { 999 #ifdef CONFIG_X86_64 1000 u64 nr_pages = 0, nr_free_pages = 0; 1001 unsigned long start_pfn, end_pfn; 1002 phys_addr_t start_addr, end_addr; 1003 int i; 1004 u64 u; 1005 1006 /* 1007 * Iterate over all memory ranges (free and reserved ones alike), 1008 * to calculate the total number of pages in the first 16 MB of RAM: 1009 */ 1010 nr_pages = 0; 1011 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) { 1012 start_pfn = min(start_pfn, MAX_DMA_PFN); 1013 end_pfn = min(end_pfn, MAX_DMA_PFN); 1014 1015 nr_pages += end_pfn - start_pfn; 1016 } 1017 1018 /* 1019 * Iterate over free memory ranges to calculate the number of free 1020 * pages in the DMA zone, while not counting potential partial 1021 * pages at the beginning or the end of the range: 1022 */ 1023 nr_free_pages = 0; 1024 for_each_free_mem_range(u, NUMA_NO_NODE, MEMBLOCK_NONE, &start_addr, &end_addr, NULL) { 1025 start_pfn = min_t(unsigned long, PFN_UP(start_addr), MAX_DMA_PFN); 1026 end_pfn = min_t(unsigned long, PFN_DOWN(end_addr), MAX_DMA_PFN); 1027 1028 if (start_pfn < end_pfn) 1029 nr_free_pages += end_pfn - start_pfn; 1030 } 1031 1032 set_dma_reserve(nr_pages - nr_free_pages); 1033 #endif 1034 } 1035 1036 void __init zone_sizes_init(void) 1037 { 1038 unsigned long max_zone_pfns[MAX_NR_ZONES]; 1039 1040 memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); 1041 1042 #ifdef CONFIG_ZONE_DMA 1043 max_zone_pfns[ZONE_DMA] = min(MAX_DMA_PFN, max_low_pfn); 1044 #endif 1045 #ifdef CONFIG_ZONE_DMA32 1046 max_zone_pfns[ZONE_DMA32] = min(MAX_DMA32_PFN, max_low_pfn); 1047 #endif 1048 max_zone_pfns[ZONE_NORMAL] = max_low_pfn; 1049 #ifdef CONFIG_HIGHMEM 1050 max_zone_pfns[ZONE_HIGHMEM] = max_pfn; 1051 #endif 1052 1053 free_area_init(max_zone_pfns); 1054 } 1055 1056 __visible DEFINE_PER_CPU_ALIGNED(struct tlb_state, cpu_tlbstate) = { 1057 .loaded_mm = &init_mm, 1058 .next_asid = 1, 1059 .cr4 = ~0UL, /* fail hard if we screw up cr4 shadow initialization */ 1060 }; 1061 1062 #ifdef CONFIG_ADDRESS_MASKING 1063 DEFINE_PER_CPU(u64, tlbstate_untag_mask); 1064 EXPORT_PER_CPU_SYMBOL(tlbstate_untag_mask); 1065 #endif 1066 1067 void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache) 1068 { 1069 /* entry 0 MUST be WB (hardwired to speed up translations) */ 1070 BUG_ON(!entry && cache != _PAGE_CACHE_MODE_WB); 1071 1072 __cachemode2pte_tbl[cache] = __cm_idx2pte(entry); 1073 __pte2cachemode_tbl[entry] = cache; 1074 } 1075 1076 #ifdef CONFIG_SWAP 1077 unsigned long arch_max_swapfile_size(void) 1078 { 1079 unsigned long pages; 1080 1081 pages = generic_max_swapfile_size(); 1082 1083 if (boot_cpu_has_bug(X86_BUG_L1TF) && l1tf_mitigation != L1TF_MITIGATION_OFF) { 1084 /* Limit the swap file size to MAX_PA/2 for L1TF workaround */ 1085 unsigned long long l1tf_limit = l1tf_pfn_limit(); 1086 /* 1087 * We encode swap offsets also with 3 bits below those for pfn 1088 * which makes the usable limit higher. 1089 */ 1090 #if CONFIG_PGTABLE_LEVELS > 2 1091 l1tf_limit <<= PAGE_SHIFT - SWP_OFFSET_FIRST_BIT; 1092 #endif 1093 pages = min_t(unsigned long long, l1tf_limit, pages); 1094 } 1095 return pages; 1096 } 1097 #endif 1098