1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef ARCH_X86_KVM_X86_H 3 #define ARCH_X86_KVM_X86_H 4 5 #include <asm/processor.h> 6 #include <asm/mwait.h> 7 #include <linux/kvm_host.h> 8 #include <asm/pvclock.h> 9 #include "kvm_cache_regs.h" 10 11 #define MSR_IA32_CR_PAT_DEFAULT 0x0007040600070406ULL 12 13 static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu) 14 { 15 vcpu->arch.exception.pending = false; 16 vcpu->arch.exception.injected = false; 17 } 18 19 static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector, 20 bool soft) 21 { 22 vcpu->arch.interrupt.pending = true; 23 vcpu->arch.interrupt.soft = soft; 24 vcpu->arch.interrupt.nr = vector; 25 } 26 27 static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu) 28 { 29 vcpu->arch.interrupt.pending = false; 30 } 31 32 static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu) 33 { 34 return vcpu->arch.exception.injected || vcpu->arch.interrupt.pending || 35 vcpu->arch.nmi_injected; 36 } 37 38 static inline bool kvm_exception_is_soft(unsigned int nr) 39 { 40 return (nr == BP_VECTOR) || (nr == OF_VECTOR); 41 } 42 43 static inline bool is_protmode(struct kvm_vcpu *vcpu) 44 { 45 return kvm_read_cr0_bits(vcpu, X86_CR0_PE); 46 } 47 48 static inline int is_long_mode(struct kvm_vcpu *vcpu) 49 { 50 #ifdef CONFIG_X86_64 51 return vcpu->arch.efer & EFER_LMA; 52 #else 53 return 0; 54 #endif 55 } 56 57 static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu) 58 { 59 int cs_db, cs_l; 60 61 if (!is_long_mode(vcpu)) 62 return false; 63 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 64 return cs_l; 65 } 66 67 static inline bool is_la57_mode(struct kvm_vcpu *vcpu) 68 { 69 #ifdef CONFIG_X86_64 70 return (vcpu->arch.efer & EFER_LMA) && 71 kvm_read_cr4_bits(vcpu, X86_CR4_LA57); 72 #else 73 return 0; 74 #endif 75 } 76 77 static inline bool mmu_is_nested(struct kvm_vcpu *vcpu) 78 { 79 return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu; 80 } 81 82 static inline int is_pae(struct kvm_vcpu *vcpu) 83 { 84 return kvm_read_cr4_bits(vcpu, X86_CR4_PAE); 85 } 86 87 static inline int is_pse(struct kvm_vcpu *vcpu) 88 { 89 return kvm_read_cr4_bits(vcpu, X86_CR4_PSE); 90 } 91 92 static inline int is_paging(struct kvm_vcpu *vcpu) 93 { 94 return likely(kvm_read_cr0_bits(vcpu, X86_CR0_PG)); 95 } 96 97 static inline u32 bit(int bitno) 98 { 99 return 1 << (bitno & 31); 100 } 101 102 static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu) 103 { 104 return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48; 105 } 106 107 static inline u8 ctxt_virt_addr_bits(struct x86_emulate_ctxt *ctxt) 108 { 109 return (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_LA57) ? 57 : 48; 110 } 111 112 static inline u64 get_canonical(u64 la, u8 vaddr_bits) 113 { 114 return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits); 115 } 116 117 static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu) 118 { 119 #ifdef CONFIG_X86_64 120 return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la; 121 #else 122 return false; 123 #endif 124 } 125 126 static inline bool emul_is_noncanonical_address(u64 la, 127 struct x86_emulate_ctxt *ctxt) 128 { 129 #ifdef CONFIG_X86_64 130 return get_canonical(la, ctxt_virt_addr_bits(ctxt)) != la; 131 #else 132 return false; 133 #endif 134 } 135 136 static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu, 137 gva_t gva, gfn_t gfn, unsigned access) 138 { 139 /* 140 * If this is a shadow nested page table, the "GVA" is 141 * actually a nGPA. 142 */ 143 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK; 144 vcpu->arch.access = access; 145 vcpu->arch.mmio_gfn = gfn; 146 vcpu->arch.mmio_gen = kvm_memslots(vcpu->kvm)->generation; 147 } 148 149 static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu) 150 { 151 return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation; 152 } 153 154 /* 155 * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we 156 * clear all mmio cache info. 157 */ 158 #define MMIO_GVA_ANY (~(gva_t)0) 159 160 static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva) 161 { 162 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK)) 163 return; 164 165 vcpu->arch.mmio_gva = 0; 166 } 167 168 static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva) 169 { 170 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva && 171 vcpu->arch.mmio_gva == (gva & PAGE_MASK)) 172 return true; 173 174 return false; 175 } 176 177 static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa) 178 { 179 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn && 180 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT) 181 return true; 182 183 return false; 184 } 185 186 static inline unsigned long kvm_register_readl(struct kvm_vcpu *vcpu, 187 enum kvm_reg reg) 188 { 189 unsigned long val = kvm_register_read(vcpu, reg); 190 191 return is_64_bit_mode(vcpu) ? val : (u32)val; 192 } 193 194 static inline void kvm_register_writel(struct kvm_vcpu *vcpu, 195 enum kvm_reg reg, 196 unsigned long val) 197 { 198 if (!is_64_bit_mode(vcpu)) 199 val = (u32)val; 200 return kvm_register_write(vcpu, reg, val); 201 } 202 203 static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk) 204 { 205 return !(kvm->arch.disabled_quirks & quirk); 206 } 207 208 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu); 209 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu); 210 void kvm_set_pending_timer(struct kvm_vcpu *vcpu); 211 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip); 212 213 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr); 214 u64 get_kvmclock_ns(struct kvm *kvm); 215 216 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 217 gva_t addr, void *val, unsigned int bytes, 218 struct x86_exception *exception); 219 220 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 221 gva_t addr, void *val, unsigned int bytes, 222 struct x86_exception *exception); 223 224 void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu); 225 u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn); 226 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data); 227 int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data); 228 int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata); 229 bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, 230 int page_num); 231 bool kvm_vector_hashing_enabled(void); 232 233 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 234 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 235 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 236 | XFEATURE_MASK_PKRU) 237 extern u64 host_xcr0; 238 239 extern u64 kvm_supported_xcr0(void); 240 241 extern unsigned int min_timer_period_us; 242 243 extern unsigned int lapic_timer_advance_ns; 244 245 extern struct static_key kvm_no_apic_vcpu; 246 247 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) 248 { 249 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, 250 vcpu->arch.virtual_tsc_shift); 251 } 252 253 /* Same "calling convention" as do_div: 254 * - divide (n << 32) by base 255 * - put result in n 256 * - return remainder 257 */ 258 #define do_shl32_div32(n, base) \ 259 ({ \ 260 u32 __quot, __rem; \ 261 asm("divl %2" : "=a" (__quot), "=d" (__rem) \ 262 : "rm" (base), "0" (0), "1" ((u32) n)); \ 263 n = __quot; \ 264 __rem; \ 265 }) 266 267 static inline bool kvm_mwait_in_guest(void) 268 { 269 return boot_cpu_has(X86_FEATURE_MWAIT) && 270 !boot_cpu_has_bug(X86_BUG_MONITOR); 271 } 272 273 #endif 274