1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef ARCH_X86_KVM_X86_H 3 #define ARCH_X86_KVM_X86_H 4 5 #include <linux/kvm_host.h> 6 #include <asm/mce.h> 7 #include <asm/pvclock.h> 8 #include "kvm_cache_regs.h" 9 #include "kvm_emulate.h" 10 11 void kvm_spurious_fault(void); 12 13 #define KVM_NESTED_VMENTER_CONSISTENCY_CHECK(consistency_check) \ 14 ({ \ 15 bool failed = (consistency_check); \ 16 if (failed) \ 17 trace_kvm_nested_vmenter_failed(#consistency_check, 0); \ 18 failed; \ 19 }) 20 21 #define KVM_DEFAULT_PLE_GAP 128 22 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 23 #define KVM_DEFAULT_PLE_WINDOW_GROW 2 24 #define KVM_DEFAULT_PLE_WINDOW_SHRINK 0 25 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX UINT_MAX 26 #define KVM_SVM_DEFAULT_PLE_WINDOW_MAX USHRT_MAX 27 #define KVM_SVM_DEFAULT_PLE_WINDOW 3000 28 29 static inline unsigned int __grow_ple_window(unsigned int val, 30 unsigned int base, unsigned int modifier, unsigned int max) 31 { 32 u64 ret = val; 33 34 if (modifier < 1) 35 return base; 36 37 if (modifier < base) 38 ret *= modifier; 39 else 40 ret += modifier; 41 42 return min(ret, (u64)max); 43 } 44 45 static inline unsigned int __shrink_ple_window(unsigned int val, 46 unsigned int base, unsigned int modifier, unsigned int min) 47 { 48 if (modifier < 1) 49 return base; 50 51 if (modifier < base) 52 val /= modifier; 53 else 54 val -= modifier; 55 56 return max(val, min); 57 } 58 59 #define MSR_IA32_CR_PAT_DEFAULT 0x0007040600070406ULL 60 61 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu); 62 int kvm_check_nested_events(struct kvm_vcpu *vcpu); 63 64 static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu) 65 { 66 vcpu->arch.exception.pending = false; 67 vcpu->arch.exception.injected = false; 68 } 69 70 static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector, 71 bool soft) 72 { 73 vcpu->arch.interrupt.injected = true; 74 vcpu->arch.interrupt.soft = soft; 75 vcpu->arch.interrupt.nr = vector; 76 } 77 78 static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu) 79 { 80 vcpu->arch.interrupt.injected = false; 81 } 82 83 static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu) 84 { 85 return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected || 86 vcpu->arch.nmi_injected; 87 } 88 89 static inline bool kvm_exception_is_soft(unsigned int nr) 90 { 91 return (nr == BP_VECTOR) || (nr == OF_VECTOR); 92 } 93 94 static inline bool is_protmode(struct kvm_vcpu *vcpu) 95 { 96 return kvm_read_cr0_bits(vcpu, X86_CR0_PE); 97 } 98 99 static inline int is_long_mode(struct kvm_vcpu *vcpu) 100 { 101 #ifdef CONFIG_X86_64 102 return vcpu->arch.efer & EFER_LMA; 103 #else 104 return 0; 105 #endif 106 } 107 108 static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu) 109 { 110 int cs_db, cs_l; 111 112 WARN_ON_ONCE(vcpu->arch.guest_state_protected); 113 114 if (!is_long_mode(vcpu)) 115 return false; 116 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 117 return cs_l; 118 } 119 120 static inline bool is_64_bit_hypercall(struct kvm_vcpu *vcpu) 121 { 122 /* 123 * If running with protected guest state, the CS register is not 124 * accessible. The hypercall register values will have had to been 125 * provided in 64-bit mode, so assume the guest is in 64-bit. 126 */ 127 return vcpu->arch.guest_state_protected || is_64_bit_mode(vcpu); 128 } 129 130 static inline bool x86_exception_has_error_code(unsigned int vector) 131 { 132 static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) | 133 BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) | 134 BIT(PF_VECTOR) | BIT(AC_VECTOR); 135 136 return (1U << vector) & exception_has_error_code; 137 } 138 139 static inline bool mmu_is_nested(struct kvm_vcpu *vcpu) 140 { 141 return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu; 142 } 143 144 static inline int is_pae(struct kvm_vcpu *vcpu) 145 { 146 return kvm_read_cr4_bits(vcpu, X86_CR4_PAE); 147 } 148 149 static inline int is_pse(struct kvm_vcpu *vcpu) 150 { 151 return kvm_read_cr4_bits(vcpu, X86_CR4_PSE); 152 } 153 154 static inline int is_paging(struct kvm_vcpu *vcpu) 155 { 156 return likely(kvm_read_cr0_bits(vcpu, X86_CR0_PG)); 157 } 158 159 static inline bool is_pae_paging(struct kvm_vcpu *vcpu) 160 { 161 return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu); 162 } 163 164 static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu) 165 { 166 return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48; 167 } 168 169 static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu) 170 { 171 return !__is_canonical_address(la, vcpu_virt_addr_bits(vcpu)); 172 } 173 174 static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu, 175 gva_t gva, gfn_t gfn, unsigned access) 176 { 177 u64 gen = kvm_memslots(vcpu->kvm)->generation; 178 179 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS)) 180 return; 181 182 /* 183 * If this is a shadow nested page table, the "GVA" is 184 * actually a nGPA. 185 */ 186 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK; 187 vcpu->arch.mmio_access = access; 188 vcpu->arch.mmio_gfn = gfn; 189 vcpu->arch.mmio_gen = gen; 190 } 191 192 static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu) 193 { 194 return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation; 195 } 196 197 /* 198 * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we 199 * clear all mmio cache info. 200 */ 201 #define MMIO_GVA_ANY (~(gva_t)0) 202 203 static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva) 204 { 205 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK)) 206 return; 207 208 vcpu->arch.mmio_gva = 0; 209 } 210 211 static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva) 212 { 213 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva && 214 vcpu->arch.mmio_gva == (gva & PAGE_MASK)) 215 return true; 216 217 return false; 218 } 219 220 static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa) 221 { 222 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn && 223 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT) 224 return true; 225 226 return false; 227 } 228 229 static inline unsigned long kvm_register_read(struct kvm_vcpu *vcpu, int reg) 230 { 231 unsigned long val = kvm_register_read_raw(vcpu, reg); 232 233 return is_64_bit_mode(vcpu) ? val : (u32)val; 234 } 235 236 static inline void kvm_register_write(struct kvm_vcpu *vcpu, 237 int reg, unsigned long val) 238 { 239 if (!is_64_bit_mode(vcpu)) 240 val = (u32)val; 241 return kvm_register_write_raw(vcpu, reg, val); 242 } 243 244 static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk) 245 { 246 return !(kvm->arch.disabled_quirks & quirk); 247 } 248 249 static inline bool kvm_vcpu_latch_init(struct kvm_vcpu *vcpu) 250 { 251 return is_smm(vcpu) || static_call(kvm_x86_apic_init_signal_blocked)(vcpu); 252 } 253 254 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip); 255 256 u64 get_kvmclock_ns(struct kvm *kvm); 257 258 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 259 gva_t addr, void *val, unsigned int bytes, 260 struct x86_exception *exception); 261 262 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, 263 gva_t addr, void *val, unsigned int bytes, 264 struct x86_exception *exception); 265 266 int handle_ud(struct kvm_vcpu *vcpu); 267 268 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu); 269 270 void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu); 271 u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn); 272 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data); 273 int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data); 274 int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata); 275 bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, 276 int page_num); 277 bool kvm_vector_hashing_enabled(void); 278 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code); 279 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 280 void *insn, int insn_len); 281 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 282 int emulation_type, void *insn, int insn_len); 283 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu); 284 285 extern u64 host_xcr0; 286 extern u64 supported_xcr0; 287 extern u64 host_xss; 288 extern u64 supported_xss; 289 extern bool enable_pmu; 290 291 static inline bool kvm_mpx_supported(void) 292 { 293 return (supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR)) 294 == (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR); 295 } 296 297 extern unsigned int min_timer_period_us; 298 299 extern bool enable_vmware_backdoor; 300 301 extern int pi_inject_timer; 302 303 extern bool report_ignored_msrs; 304 305 extern bool eager_page_split; 306 307 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) 308 { 309 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, 310 vcpu->arch.virtual_tsc_shift); 311 } 312 313 /* Same "calling convention" as do_div: 314 * - divide (n << 32) by base 315 * - put result in n 316 * - return remainder 317 */ 318 #define do_shl32_div32(n, base) \ 319 ({ \ 320 u32 __quot, __rem; \ 321 asm("divl %2" : "=a" (__quot), "=d" (__rem) \ 322 : "rm" (base), "0" (0), "1" ((u32) n)); \ 323 n = __quot; \ 324 __rem; \ 325 }) 326 327 static inline bool kvm_mwait_in_guest(struct kvm *kvm) 328 { 329 return kvm->arch.mwait_in_guest; 330 } 331 332 static inline bool kvm_hlt_in_guest(struct kvm *kvm) 333 { 334 return kvm->arch.hlt_in_guest; 335 } 336 337 static inline bool kvm_pause_in_guest(struct kvm *kvm) 338 { 339 return kvm->arch.pause_in_guest; 340 } 341 342 static inline bool kvm_cstate_in_guest(struct kvm *kvm) 343 { 344 return kvm->arch.cstate_in_guest; 345 } 346 347 enum kvm_intr_type { 348 /* Values are arbitrary, but must be non-zero. */ 349 KVM_HANDLING_IRQ = 1, 350 KVM_HANDLING_NMI, 351 }; 352 353 static inline void kvm_before_interrupt(struct kvm_vcpu *vcpu, 354 enum kvm_intr_type intr) 355 { 356 WRITE_ONCE(vcpu->arch.handling_intr_from_guest, (u8)intr); 357 } 358 359 static inline void kvm_after_interrupt(struct kvm_vcpu *vcpu) 360 { 361 WRITE_ONCE(vcpu->arch.handling_intr_from_guest, 0); 362 } 363 364 static inline bool kvm_handling_nmi_from_guest(struct kvm_vcpu *vcpu) 365 { 366 return vcpu->arch.handling_intr_from_guest == KVM_HANDLING_NMI; 367 } 368 369 static inline bool kvm_pat_valid(u64 data) 370 { 371 if (data & 0xF8F8F8F8F8F8F8F8ull) 372 return false; 373 /* 0, 1, 4, 5, 6, 7 are valid values. */ 374 return (data | ((data & 0x0202020202020202ull) << 1)) == data; 375 } 376 377 static inline bool kvm_dr7_valid(u64 data) 378 { 379 /* Bits [63:32] are reserved */ 380 return !(data >> 32); 381 } 382 static inline bool kvm_dr6_valid(u64 data) 383 { 384 /* Bits [63:32] are reserved */ 385 return !(data >> 32); 386 } 387 388 /* 389 * Trigger machine check on the host. We assume all the MSRs are already set up 390 * by the CPU and that we still run on the same CPU as the MCE occurred on. 391 * We pass a fake environment to the machine check handler because we want 392 * the guest to be always treated like user space, no matter what context 393 * it used internally. 394 */ 395 static inline void kvm_machine_check(void) 396 { 397 #if defined(CONFIG_X86_MCE) 398 struct pt_regs regs = { 399 .cs = 3, /* Fake ring 3 no matter what the guest ran on */ 400 .flags = X86_EFLAGS_IF, 401 }; 402 403 do_machine_check(®s); 404 #endif 405 } 406 407 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu); 408 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu); 409 int kvm_spec_ctrl_test_value(u64 value); 410 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 411 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 412 struct x86_exception *e); 413 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva); 414 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type); 415 416 /* 417 * Internal error codes that are used to indicate that MSR emulation encountered 418 * an error that should result in #GP in the guest, unless userspace 419 * handles it. 420 */ 421 #define KVM_MSR_RET_INVALID 2 /* in-kernel MSR emulation #GP condition */ 422 #define KVM_MSR_RET_FILTERED 3 /* #GP due to userspace MSR filter */ 423 424 #define __cr4_reserved_bits(__cpu_has, __c) \ 425 ({ \ 426 u64 __reserved_bits = CR4_RESERVED_BITS; \ 427 \ 428 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \ 429 __reserved_bits |= X86_CR4_OSXSAVE; \ 430 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \ 431 __reserved_bits |= X86_CR4_SMEP; \ 432 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \ 433 __reserved_bits |= X86_CR4_SMAP; \ 434 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \ 435 __reserved_bits |= X86_CR4_FSGSBASE; \ 436 if (!__cpu_has(__c, X86_FEATURE_PKU)) \ 437 __reserved_bits |= X86_CR4_PKE; \ 438 if (!__cpu_has(__c, X86_FEATURE_LA57)) \ 439 __reserved_bits |= X86_CR4_LA57; \ 440 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \ 441 __reserved_bits |= X86_CR4_UMIP; \ 442 if (!__cpu_has(__c, X86_FEATURE_VMX)) \ 443 __reserved_bits |= X86_CR4_VMXE; \ 444 if (!__cpu_has(__c, X86_FEATURE_PCID)) \ 445 __reserved_bits |= X86_CR4_PCIDE; \ 446 __reserved_bits; \ 447 }) 448 449 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes, 450 void *dst); 451 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes, 452 void *dst); 453 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 454 unsigned int port, void *data, unsigned int count, 455 int in); 456 457 #endif 458