1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef ARCH_X86_KVM_X86_H 3 #define ARCH_X86_KVM_X86_H 4 5 #include <linux/kvm_host.h> 6 #include <asm/pvclock.h> 7 #include "kvm_cache_regs.h" 8 #include "kvm_emulate.h" 9 10 #define KVM_DEFAULT_PLE_GAP 128 11 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 12 #define KVM_DEFAULT_PLE_WINDOW_GROW 2 13 #define KVM_DEFAULT_PLE_WINDOW_SHRINK 0 14 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX UINT_MAX 15 #define KVM_SVM_DEFAULT_PLE_WINDOW_MAX USHRT_MAX 16 #define KVM_SVM_DEFAULT_PLE_WINDOW 3000 17 18 static inline unsigned int __grow_ple_window(unsigned int val, 19 unsigned int base, unsigned int modifier, unsigned int max) 20 { 21 u64 ret = val; 22 23 if (modifier < 1) 24 return base; 25 26 if (modifier < base) 27 ret *= modifier; 28 else 29 ret += modifier; 30 31 return min(ret, (u64)max); 32 } 33 34 static inline unsigned int __shrink_ple_window(unsigned int val, 35 unsigned int base, unsigned int modifier, unsigned int min) 36 { 37 if (modifier < 1) 38 return base; 39 40 if (modifier < base) 41 val /= modifier; 42 else 43 val -= modifier; 44 45 return max(val, min); 46 } 47 48 #define MSR_IA32_CR_PAT_DEFAULT 0x0007040600070406ULL 49 50 static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu) 51 { 52 vcpu->arch.exception.pending = false; 53 vcpu->arch.exception.injected = false; 54 } 55 56 static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector, 57 bool soft) 58 { 59 vcpu->arch.interrupt.injected = true; 60 vcpu->arch.interrupt.soft = soft; 61 vcpu->arch.interrupt.nr = vector; 62 } 63 64 static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu) 65 { 66 vcpu->arch.interrupt.injected = false; 67 } 68 69 static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu) 70 { 71 return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected || 72 vcpu->arch.nmi_injected; 73 } 74 75 static inline bool kvm_exception_is_soft(unsigned int nr) 76 { 77 return (nr == BP_VECTOR) || (nr == OF_VECTOR); 78 } 79 80 static inline bool is_protmode(struct kvm_vcpu *vcpu) 81 { 82 return kvm_read_cr0_bits(vcpu, X86_CR0_PE); 83 } 84 85 static inline int is_long_mode(struct kvm_vcpu *vcpu) 86 { 87 #ifdef CONFIG_X86_64 88 return vcpu->arch.efer & EFER_LMA; 89 #else 90 return 0; 91 #endif 92 } 93 94 static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu) 95 { 96 int cs_db, cs_l; 97 98 if (!is_long_mode(vcpu)) 99 return false; 100 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 101 return cs_l; 102 } 103 104 static inline bool is_la57_mode(struct kvm_vcpu *vcpu) 105 { 106 #ifdef CONFIG_X86_64 107 return (vcpu->arch.efer & EFER_LMA) && 108 kvm_read_cr4_bits(vcpu, X86_CR4_LA57); 109 #else 110 return 0; 111 #endif 112 } 113 114 static inline bool x86_exception_has_error_code(unsigned int vector) 115 { 116 static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) | 117 BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) | 118 BIT(PF_VECTOR) | BIT(AC_VECTOR); 119 120 return (1U << vector) & exception_has_error_code; 121 } 122 123 static inline bool mmu_is_nested(struct kvm_vcpu *vcpu) 124 { 125 return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu; 126 } 127 128 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu) 129 { 130 ++vcpu->stat.tlb_flush; 131 kvm_x86_ops.tlb_flush_current(vcpu); 132 } 133 134 static inline int is_pae(struct kvm_vcpu *vcpu) 135 { 136 return kvm_read_cr4_bits(vcpu, X86_CR4_PAE); 137 } 138 139 static inline int is_pse(struct kvm_vcpu *vcpu) 140 { 141 return kvm_read_cr4_bits(vcpu, X86_CR4_PSE); 142 } 143 144 static inline int is_paging(struct kvm_vcpu *vcpu) 145 { 146 return likely(kvm_read_cr0_bits(vcpu, X86_CR0_PG)); 147 } 148 149 static inline bool is_pae_paging(struct kvm_vcpu *vcpu) 150 { 151 return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu); 152 } 153 154 static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu) 155 { 156 return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48; 157 } 158 159 static inline u64 get_canonical(u64 la, u8 vaddr_bits) 160 { 161 return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits); 162 } 163 164 static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu) 165 { 166 return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la; 167 } 168 169 static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu, 170 gva_t gva, gfn_t gfn, unsigned access) 171 { 172 u64 gen = kvm_memslots(vcpu->kvm)->generation; 173 174 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS)) 175 return; 176 177 /* 178 * If this is a shadow nested page table, the "GVA" is 179 * actually a nGPA. 180 */ 181 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK; 182 vcpu->arch.mmio_access = access; 183 vcpu->arch.mmio_gfn = gfn; 184 vcpu->arch.mmio_gen = gen; 185 } 186 187 static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu) 188 { 189 return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation; 190 } 191 192 /* 193 * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we 194 * clear all mmio cache info. 195 */ 196 #define MMIO_GVA_ANY (~(gva_t)0) 197 198 static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva) 199 { 200 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK)) 201 return; 202 203 vcpu->arch.mmio_gva = 0; 204 } 205 206 static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva) 207 { 208 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva && 209 vcpu->arch.mmio_gva == (gva & PAGE_MASK)) 210 return true; 211 212 return false; 213 } 214 215 static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa) 216 { 217 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn && 218 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT) 219 return true; 220 221 return false; 222 } 223 224 static inline unsigned long kvm_register_readl(struct kvm_vcpu *vcpu, int reg) 225 { 226 unsigned long val = kvm_register_read(vcpu, reg); 227 228 return is_64_bit_mode(vcpu) ? val : (u32)val; 229 } 230 231 static inline void kvm_register_writel(struct kvm_vcpu *vcpu, 232 int reg, unsigned long val) 233 { 234 if (!is_64_bit_mode(vcpu)) 235 val = (u32)val; 236 return kvm_register_write(vcpu, reg, val); 237 } 238 239 static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk) 240 { 241 return !(kvm->arch.disabled_quirks & quirk); 242 } 243 244 static inline bool kvm_vcpu_latch_init(struct kvm_vcpu *vcpu) 245 { 246 return is_smm(vcpu) || kvm_x86_ops.apic_init_signal_blocked(vcpu); 247 } 248 249 void kvm_set_pending_timer(struct kvm_vcpu *vcpu); 250 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip); 251 252 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr); 253 u64 get_kvmclock_ns(struct kvm *kvm); 254 255 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 256 gva_t addr, void *val, unsigned int bytes, 257 struct x86_exception *exception); 258 259 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, 260 gva_t addr, void *val, unsigned int bytes, 261 struct x86_exception *exception); 262 263 int handle_ud(struct kvm_vcpu *vcpu); 264 265 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu); 266 267 void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu); 268 u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn); 269 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data); 270 int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data); 271 int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata); 272 bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, 273 int page_num); 274 bool kvm_vector_hashing_enabled(void); 275 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 276 int emulation_type, void *insn, int insn_len); 277 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu); 278 279 extern u64 host_xcr0; 280 extern u64 supported_xcr0; 281 extern u64 supported_xss; 282 283 static inline bool kvm_mpx_supported(void) 284 { 285 return (supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR)) 286 == (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR); 287 } 288 289 extern unsigned int min_timer_period_us; 290 291 extern bool enable_vmware_backdoor; 292 293 extern int pi_inject_timer; 294 295 extern struct static_key kvm_no_apic_vcpu; 296 297 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) 298 { 299 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, 300 vcpu->arch.virtual_tsc_shift); 301 } 302 303 /* Same "calling convention" as do_div: 304 * - divide (n << 32) by base 305 * - put result in n 306 * - return remainder 307 */ 308 #define do_shl32_div32(n, base) \ 309 ({ \ 310 u32 __quot, __rem; \ 311 asm("divl %2" : "=a" (__quot), "=d" (__rem) \ 312 : "rm" (base), "0" (0), "1" ((u32) n)); \ 313 n = __quot; \ 314 __rem; \ 315 }) 316 317 static inline bool kvm_mwait_in_guest(struct kvm *kvm) 318 { 319 return kvm->arch.mwait_in_guest; 320 } 321 322 static inline bool kvm_hlt_in_guest(struct kvm *kvm) 323 { 324 return kvm->arch.hlt_in_guest; 325 } 326 327 static inline bool kvm_pause_in_guest(struct kvm *kvm) 328 { 329 return kvm->arch.pause_in_guest; 330 } 331 332 static inline bool kvm_cstate_in_guest(struct kvm *kvm) 333 { 334 return kvm->arch.cstate_in_guest; 335 } 336 337 DECLARE_PER_CPU(struct kvm_vcpu *, current_vcpu); 338 339 static inline void kvm_before_interrupt(struct kvm_vcpu *vcpu) 340 { 341 __this_cpu_write(current_vcpu, vcpu); 342 } 343 344 static inline void kvm_after_interrupt(struct kvm_vcpu *vcpu) 345 { 346 __this_cpu_write(current_vcpu, NULL); 347 } 348 349 350 static inline bool kvm_pat_valid(u64 data) 351 { 352 if (data & 0xF8F8F8F8F8F8F8F8ull) 353 return false; 354 /* 0, 1, 4, 5, 6, 7 are valid values. */ 355 return (data | ((data & 0x0202020202020202ull) << 1)) == data; 356 } 357 358 static inline bool kvm_dr7_valid(u64 data) 359 { 360 /* Bits [63:32] are reserved */ 361 return !(data >> 32); 362 } 363 364 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu); 365 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu); 366 u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu); 367 bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu); 368 369 #endif 370