1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * derived from drivers/kvm/kvm_main.c 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright (C) 2008 Qumranet, Inc. 9 * Copyright IBM Corporation, 2008 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 11 * 12 * Authors: 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * Amit Shah <amit.shah@qumranet.com> 16 * Ben-Ami Yassour <benami@il.ibm.com> 17 */ 18 19 #include <linux/kvm_host.h> 20 #include "irq.h" 21 #include "ioapic.h" 22 #include "mmu.h" 23 #include "i8254.h" 24 #include "tss.h" 25 #include "kvm_cache_regs.h" 26 #include "kvm_emulate.h" 27 #include "x86.h" 28 #include "cpuid.h" 29 #include "pmu.h" 30 #include "hyperv.h" 31 #include "lapic.h" 32 #include "xen.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/export.h> 40 #include <linux/moduleparam.h> 41 #include <linux/mman.h> 42 #include <linux/highmem.h> 43 #include <linux/iommu.h> 44 #include <linux/intel-iommu.h> 45 #include <linux/cpufreq.h> 46 #include <linux/user-return-notifier.h> 47 #include <linux/srcu.h> 48 #include <linux/slab.h> 49 #include <linux/perf_event.h> 50 #include <linux/uaccess.h> 51 #include <linux/hash.h> 52 #include <linux/pci.h> 53 #include <linux/timekeeper_internal.h> 54 #include <linux/pvclock_gtod.h> 55 #include <linux/kvm_irqfd.h> 56 #include <linux/irqbypass.h> 57 #include <linux/sched/stat.h> 58 #include <linux/sched/isolation.h> 59 #include <linux/mem_encrypt.h> 60 #include <linux/entry-kvm.h> 61 #include <linux/suspend.h> 62 63 #include <trace/events/kvm.h> 64 65 #include <asm/debugreg.h> 66 #include <asm/msr.h> 67 #include <asm/desc.h> 68 #include <asm/mce.h> 69 #include <asm/pkru.h> 70 #include <linux/kernel_stat.h> 71 #include <asm/fpu/api.h> 72 #include <asm/fpu/xcr.h> 73 #include <asm/fpu/xstate.h> 74 #include <asm/pvclock.h> 75 #include <asm/div64.h> 76 #include <asm/irq_remapping.h> 77 #include <asm/mshyperv.h> 78 #include <asm/hypervisor.h> 79 #include <asm/tlbflush.h> 80 #include <asm/intel_pt.h> 81 #include <asm/emulate_prefix.h> 82 #include <asm/sgx.h> 83 #include <clocksource/hyperv_timer.h> 84 85 #define CREATE_TRACE_POINTS 86 #include "trace.h" 87 88 #define MAX_IO_MSRS 256 89 #define KVM_MAX_MCE_BANKS 32 90 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 91 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 92 93 #define emul_to_vcpu(ctxt) \ 94 ((struct kvm_vcpu *)(ctxt)->vcpu) 95 96 /* EFER defaults: 97 * - enable syscall per default because its emulated by KVM 98 * - enable LME and LMA per default on 64 bit KVM 99 */ 100 #ifdef CONFIG_X86_64 101 static 102 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 103 #else 104 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 105 #endif 106 107 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; 108 109 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) 110 111 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 112 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 113 114 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 115 static void process_nmi(struct kvm_vcpu *vcpu); 116 static void process_smi(struct kvm_vcpu *vcpu); 117 static void enter_smm(struct kvm_vcpu *vcpu); 118 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 119 static void store_regs(struct kvm_vcpu *vcpu); 120 static int sync_regs(struct kvm_vcpu *vcpu); 121 122 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 123 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 124 125 struct kvm_x86_ops kvm_x86_ops __read_mostly; 126 EXPORT_SYMBOL_GPL(kvm_x86_ops); 127 128 #define KVM_X86_OP(func) \ 129 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ 130 *(((struct kvm_x86_ops *)0)->func)); 131 #define KVM_X86_OP_NULL KVM_X86_OP 132 #include <asm/kvm-x86-ops.h> 133 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); 134 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); 135 EXPORT_STATIC_CALL_GPL(kvm_x86_tlb_flush_current); 136 137 static bool __read_mostly ignore_msrs = 0; 138 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 139 140 bool __read_mostly report_ignored_msrs = true; 141 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 142 EXPORT_SYMBOL_GPL(report_ignored_msrs); 143 144 unsigned int min_timer_period_us = 200; 145 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 146 147 static bool __read_mostly kvmclock_periodic_sync = true; 148 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 149 150 bool __read_mostly kvm_has_tsc_control; 151 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 152 u32 __read_mostly kvm_max_guest_tsc_khz; 153 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 154 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 155 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 156 u64 __read_mostly kvm_max_tsc_scaling_ratio; 157 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 158 u64 __read_mostly kvm_default_tsc_scaling_ratio; 159 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 160 bool __read_mostly kvm_has_bus_lock_exit; 161 EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit); 162 163 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 164 static u32 __read_mostly tsc_tolerance_ppm = 250; 165 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 166 167 /* 168 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 169 * adaptive tuning starting from default advancement of 1000ns. '0' disables 170 * advancement entirely. Any other value is used as-is and disables adaptive 171 * tuning, i.e. allows privileged userspace to set an exact advancement time. 172 */ 173 static int __read_mostly lapic_timer_advance_ns = -1; 174 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); 175 176 static bool __read_mostly vector_hashing = true; 177 module_param(vector_hashing, bool, S_IRUGO); 178 179 bool __read_mostly enable_vmware_backdoor = false; 180 module_param(enable_vmware_backdoor, bool, S_IRUGO); 181 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 182 183 static bool __read_mostly force_emulation_prefix = false; 184 module_param(force_emulation_prefix, bool, S_IRUGO); 185 186 int __read_mostly pi_inject_timer = -1; 187 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); 188 189 /* 190 * Restoring the host value for MSRs that are only consumed when running in 191 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU 192 * returns to userspace, i.e. the kernel can run with the guest's value. 193 */ 194 #define KVM_MAX_NR_USER_RETURN_MSRS 16 195 196 struct kvm_user_return_msrs { 197 struct user_return_notifier urn; 198 bool registered; 199 struct kvm_user_return_msr_values { 200 u64 host; 201 u64 curr; 202 } values[KVM_MAX_NR_USER_RETURN_MSRS]; 203 }; 204 205 u32 __read_mostly kvm_nr_uret_msrs; 206 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); 207 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; 208 static struct kvm_user_return_msrs __percpu *user_return_msrs; 209 210 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 211 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 212 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 213 | XFEATURE_MASK_PKRU) 214 215 u64 __read_mostly host_efer; 216 EXPORT_SYMBOL_GPL(host_efer); 217 218 bool __read_mostly allow_smaller_maxphyaddr = 0; 219 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); 220 221 bool __read_mostly enable_apicv = true; 222 EXPORT_SYMBOL_GPL(enable_apicv); 223 224 u64 __read_mostly host_xss; 225 EXPORT_SYMBOL_GPL(host_xss); 226 u64 __read_mostly supported_xss; 227 EXPORT_SYMBOL_GPL(supported_xss); 228 229 const struct _kvm_stats_desc kvm_vm_stats_desc[] = { 230 KVM_GENERIC_VM_STATS(), 231 STATS_DESC_COUNTER(VM, mmu_shadow_zapped), 232 STATS_DESC_COUNTER(VM, mmu_pte_write), 233 STATS_DESC_COUNTER(VM, mmu_pde_zapped), 234 STATS_DESC_COUNTER(VM, mmu_flooded), 235 STATS_DESC_COUNTER(VM, mmu_recycled), 236 STATS_DESC_COUNTER(VM, mmu_cache_miss), 237 STATS_DESC_ICOUNTER(VM, mmu_unsync), 238 STATS_DESC_ICOUNTER(VM, pages_4k), 239 STATS_DESC_ICOUNTER(VM, pages_2m), 240 STATS_DESC_ICOUNTER(VM, pages_1g), 241 STATS_DESC_ICOUNTER(VM, nx_lpage_splits), 242 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size), 243 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions) 244 }; 245 246 const struct kvm_stats_header kvm_vm_stats_header = { 247 .name_size = KVM_STATS_NAME_SIZE, 248 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), 249 .id_offset = sizeof(struct kvm_stats_header), 250 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 251 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 252 sizeof(kvm_vm_stats_desc), 253 }; 254 255 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { 256 KVM_GENERIC_VCPU_STATS(), 257 STATS_DESC_COUNTER(VCPU, pf_fixed), 258 STATS_DESC_COUNTER(VCPU, pf_guest), 259 STATS_DESC_COUNTER(VCPU, tlb_flush), 260 STATS_DESC_COUNTER(VCPU, invlpg), 261 STATS_DESC_COUNTER(VCPU, exits), 262 STATS_DESC_COUNTER(VCPU, io_exits), 263 STATS_DESC_COUNTER(VCPU, mmio_exits), 264 STATS_DESC_COUNTER(VCPU, signal_exits), 265 STATS_DESC_COUNTER(VCPU, irq_window_exits), 266 STATS_DESC_COUNTER(VCPU, nmi_window_exits), 267 STATS_DESC_COUNTER(VCPU, l1d_flush), 268 STATS_DESC_COUNTER(VCPU, halt_exits), 269 STATS_DESC_COUNTER(VCPU, request_irq_exits), 270 STATS_DESC_COUNTER(VCPU, irq_exits), 271 STATS_DESC_COUNTER(VCPU, host_state_reload), 272 STATS_DESC_COUNTER(VCPU, fpu_reload), 273 STATS_DESC_COUNTER(VCPU, insn_emulation), 274 STATS_DESC_COUNTER(VCPU, insn_emulation_fail), 275 STATS_DESC_COUNTER(VCPU, hypercalls), 276 STATS_DESC_COUNTER(VCPU, irq_injections), 277 STATS_DESC_COUNTER(VCPU, nmi_injections), 278 STATS_DESC_COUNTER(VCPU, req_event), 279 STATS_DESC_COUNTER(VCPU, nested_run), 280 STATS_DESC_COUNTER(VCPU, directed_yield_attempted), 281 STATS_DESC_COUNTER(VCPU, directed_yield_successful), 282 STATS_DESC_ICOUNTER(VCPU, guest_mode) 283 }; 284 285 const struct kvm_stats_header kvm_vcpu_stats_header = { 286 .name_size = KVM_STATS_NAME_SIZE, 287 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), 288 .id_offset = sizeof(struct kvm_stats_header), 289 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 290 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 291 sizeof(kvm_vcpu_stats_desc), 292 }; 293 294 u64 __read_mostly host_xcr0; 295 u64 __read_mostly supported_xcr0; 296 EXPORT_SYMBOL_GPL(supported_xcr0); 297 298 static struct kmem_cache *x86_emulator_cache; 299 300 /* 301 * When called, it means the previous get/set msr reached an invalid msr. 302 * Return true if we want to ignore/silent this failed msr access. 303 */ 304 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) 305 { 306 const char *op = write ? "wrmsr" : "rdmsr"; 307 308 if (ignore_msrs) { 309 if (report_ignored_msrs) 310 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", 311 op, msr, data); 312 /* Mask the error */ 313 return true; 314 } else { 315 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", 316 op, msr, data); 317 return false; 318 } 319 } 320 321 static struct kmem_cache *kvm_alloc_emulator_cache(void) 322 { 323 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); 324 unsigned int size = sizeof(struct x86_emulate_ctxt); 325 326 return kmem_cache_create_usercopy("x86_emulator", size, 327 __alignof__(struct x86_emulate_ctxt), 328 SLAB_ACCOUNT, useroffset, 329 size - useroffset, NULL); 330 } 331 332 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 333 334 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 335 { 336 int i; 337 for (i = 0; i < ASYNC_PF_PER_VCPU; i++) 338 vcpu->arch.apf.gfns[i] = ~0; 339 } 340 341 static void kvm_on_user_return(struct user_return_notifier *urn) 342 { 343 unsigned slot; 344 struct kvm_user_return_msrs *msrs 345 = container_of(urn, struct kvm_user_return_msrs, urn); 346 struct kvm_user_return_msr_values *values; 347 unsigned long flags; 348 349 /* 350 * Disabling irqs at this point since the following code could be 351 * interrupted and executed through kvm_arch_hardware_disable() 352 */ 353 local_irq_save(flags); 354 if (msrs->registered) { 355 msrs->registered = false; 356 user_return_notifier_unregister(urn); 357 } 358 local_irq_restore(flags); 359 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { 360 values = &msrs->values[slot]; 361 if (values->host != values->curr) { 362 wrmsrl(kvm_uret_msrs_list[slot], values->host); 363 values->curr = values->host; 364 } 365 } 366 } 367 368 static int kvm_probe_user_return_msr(u32 msr) 369 { 370 u64 val; 371 int ret; 372 373 preempt_disable(); 374 ret = rdmsrl_safe(msr, &val); 375 if (ret) 376 goto out; 377 ret = wrmsrl_safe(msr, val); 378 out: 379 preempt_enable(); 380 return ret; 381 } 382 383 int kvm_add_user_return_msr(u32 msr) 384 { 385 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); 386 387 if (kvm_probe_user_return_msr(msr)) 388 return -1; 389 390 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; 391 return kvm_nr_uret_msrs++; 392 } 393 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); 394 395 int kvm_find_user_return_msr(u32 msr) 396 { 397 int i; 398 399 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 400 if (kvm_uret_msrs_list[i] == msr) 401 return i; 402 } 403 return -1; 404 } 405 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); 406 407 static void kvm_user_return_msr_cpu_online(void) 408 { 409 unsigned int cpu = smp_processor_id(); 410 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 411 u64 value; 412 int i; 413 414 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 415 rdmsrl_safe(kvm_uret_msrs_list[i], &value); 416 msrs->values[i].host = value; 417 msrs->values[i].curr = value; 418 } 419 } 420 421 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) 422 { 423 unsigned int cpu = smp_processor_id(); 424 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 425 int err; 426 427 value = (value & mask) | (msrs->values[slot].host & ~mask); 428 if (value == msrs->values[slot].curr) 429 return 0; 430 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); 431 if (err) 432 return 1; 433 434 msrs->values[slot].curr = value; 435 if (!msrs->registered) { 436 msrs->urn.on_user_return = kvm_on_user_return; 437 user_return_notifier_register(&msrs->urn); 438 msrs->registered = true; 439 } 440 return 0; 441 } 442 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); 443 444 static void drop_user_return_notifiers(void) 445 { 446 unsigned int cpu = smp_processor_id(); 447 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 448 449 if (msrs->registered) 450 kvm_on_user_return(&msrs->urn); 451 } 452 453 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 454 { 455 return vcpu->arch.apic_base; 456 } 457 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 458 459 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 460 { 461 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 462 } 463 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 464 465 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 466 { 467 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 468 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 469 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | 470 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 471 472 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 473 return 1; 474 if (!msr_info->host_initiated) { 475 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 476 return 1; 477 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 478 return 1; 479 } 480 481 kvm_lapic_set_base(vcpu, msr_info->data); 482 kvm_recalculate_apic_map(vcpu->kvm); 483 return 0; 484 } 485 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 486 487 /* 488 * Handle a fault on a hardware virtualization (VMX or SVM) instruction. 489 * 490 * Hardware virtualization extension instructions may fault if a reboot turns 491 * off virtualization while processes are running. Usually after catching the 492 * fault we just panic; during reboot instead the instruction is ignored. 493 */ 494 noinstr void kvm_spurious_fault(void) 495 { 496 /* Fault while not rebooting. We want the trace. */ 497 BUG_ON(!kvm_rebooting); 498 } 499 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 500 501 #define EXCPT_BENIGN 0 502 #define EXCPT_CONTRIBUTORY 1 503 #define EXCPT_PF 2 504 505 static int exception_class(int vector) 506 { 507 switch (vector) { 508 case PF_VECTOR: 509 return EXCPT_PF; 510 case DE_VECTOR: 511 case TS_VECTOR: 512 case NP_VECTOR: 513 case SS_VECTOR: 514 case GP_VECTOR: 515 return EXCPT_CONTRIBUTORY; 516 default: 517 break; 518 } 519 return EXCPT_BENIGN; 520 } 521 522 #define EXCPT_FAULT 0 523 #define EXCPT_TRAP 1 524 #define EXCPT_ABORT 2 525 #define EXCPT_INTERRUPT 3 526 527 static int exception_type(int vector) 528 { 529 unsigned int mask; 530 531 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 532 return EXCPT_INTERRUPT; 533 534 mask = 1 << vector; 535 536 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 537 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 538 return EXCPT_TRAP; 539 540 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 541 return EXCPT_ABORT; 542 543 /* Reserved exceptions will result in fault */ 544 return EXCPT_FAULT; 545 } 546 547 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 548 { 549 unsigned nr = vcpu->arch.exception.nr; 550 bool has_payload = vcpu->arch.exception.has_payload; 551 unsigned long payload = vcpu->arch.exception.payload; 552 553 if (!has_payload) 554 return; 555 556 switch (nr) { 557 case DB_VECTOR: 558 /* 559 * "Certain debug exceptions may clear bit 0-3. The 560 * remaining contents of the DR6 register are never 561 * cleared by the processor". 562 */ 563 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 564 /* 565 * In order to reflect the #DB exception payload in guest 566 * dr6, three components need to be considered: active low 567 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, 568 * DR6_BS and DR6_BT) 569 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. 570 * In the target guest dr6: 571 * FIXED_1 bits should always be set. 572 * Active low bits should be cleared if 1-setting in payload. 573 * Active high bits should be set if 1-setting in payload. 574 * 575 * Note, the payload is compatible with the pending debug 576 * exceptions/exit qualification under VMX, that active_low bits 577 * are active high in payload. 578 * So they need to be flipped for DR6. 579 */ 580 vcpu->arch.dr6 |= DR6_ACTIVE_LOW; 581 vcpu->arch.dr6 |= payload; 582 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; 583 584 /* 585 * The #DB payload is defined as compatible with the 'pending 586 * debug exceptions' field under VMX, not DR6. While bit 12 is 587 * defined in the 'pending debug exceptions' field (enabled 588 * breakpoint), it is reserved and must be zero in DR6. 589 */ 590 vcpu->arch.dr6 &= ~BIT(12); 591 break; 592 case PF_VECTOR: 593 vcpu->arch.cr2 = payload; 594 break; 595 } 596 597 vcpu->arch.exception.has_payload = false; 598 vcpu->arch.exception.payload = 0; 599 } 600 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 601 602 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 603 unsigned nr, bool has_error, u32 error_code, 604 bool has_payload, unsigned long payload, bool reinject) 605 { 606 u32 prev_nr; 607 int class1, class2; 608 609 kvm_make_request(KVM_REQ_EVENT, vcpu); 610 611 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 612 queue: 613 if (reinject) { 614 /* 615 * On vmentry, vcpu->arch.exception.pending is only 616 * true if an event injection was blocked by 617 * nested_run_pending. In that case, however, 618 * vcpu_enter_guest requests an immediate exit, 619 * and the guest shouldn't proceed far enough to 620 * need reinjection. 621 */ 622 WARN_ON_ONCE(vcpu->arch.exception.pending); 623 vcpu->arch.exception.injected = true; 624 if (WARN_ON_ONCE(has_payload)) { 625 /* 626 * A reinjected event has already 627 * delivered its payload. 628 */ 629 has_payload = false; 630 payload = 0; 631 } 632 } else { 633 vcpu->arch.exception.pending = true; 634 vcpu->arch.exception.injected = false; 635 } 636 vcpu->arch.exception.has_error_code = has_error; 637 vcpu->arch.exception.nr = nr; 638 vcpu->arch.exception.error_code = error_code; 639 vcpu->arch.exception.has_payload = has_payload; 640 vcpu->arch.exception.payload = payload; 641 if (!is_guest_mode(vcpu)) 642 kvm_deliver_exception_payload(vcpu); 643 return; 644 } 645 646 /* to check exception */ 647 prev_nr = vcpu->arch.exception.nr; 648 if (prev_nr == DF_VECTOR) { 649 /* triple fault -> shutdown */ 650 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 651 return; 652 } 653 class1 = exception_class(prev_nr); 654 class2 = exception_class(nr); 655 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 656 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 657 /* 658 * Generate double fault per SDM Table 5-5. Set 659 * exception.pending = true so that the double fault 660 * can trigger a nested vmexit. 661 */ 662 vcpu->arch.exception.pending = true; 663 vcpu->arch.exception.injected = false; 664 vcpu->arch.exception.has_error_code = true; 665 vcpu->arch.exception.nr = DF_VECTOR; 666 vcpu->arch.exception.error_code = 0; 667 vcpu->arch.exception.has_payload = false; 668 vcpu->arch.exception.payload = 0; 669 } else 670 /* replace previous exception with a new one in a hope 671 that instruction re-execution will regenerate lost 672 exception */ 673 goto queue; 674 } 675 676 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 677 { 678 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 679 } 680 EXPORT_SYMBOL_GPL(kvm_queue_exception); 681 682 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 683 { 684 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 685 } 686 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 687 688 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 689 unsigned long payload) 690 { 691 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 692 } 693 EXPORT_SYMBOL_GPL(kvm_queue_exception_p); 694 695 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 696 u32 error_code, unsigned long payload) 697 { 698 kvm_multiple_exception(vcpu, nr, true, error_code, 699 true, payload, false); 700 } 701 702 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 703 { 704 if (err) 705 kvm_inject_gp(vcpu, 0); 706 else 707 return kvm_skip_emulated_instruction(vcpu); 708 709 return 1; 710 } 711 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 712 713 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 714 { 715 ++vcpu->stat.pf_guest; 716 vcpu->arch.exception.nested_apf = 717 is_guest_mode(vcpu) && fault->async_page_fault; 718 if (vcpu->arch.exception.nested_apf) { 719 vcpu->arch.apf.nested_apf_token = fault->address; 720 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 721 } else { 722 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 723 fault->address); 724 } 725 } 726 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 727 728 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 729 struct x86_exception *fault) 730 { 731 struct kvm_mmu *fault_mmu; 732 WARN_ON_ONCE(fault->vector != PF_VECTOR); 733 734 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : 735 vcpu->arch.walk_mmu; 736 737 /* 738 * Invalidate the TLB entry for the faulting address, if it exists, 739 * else the access will fault indefinitely (and to emulate hardware). 740 */ 741 if ((fault->error_code & PFERR_PRESENT_MASK) && 742 !(fault->error_code & PFERR_RSVD_MASK)) 743 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, 744 fault_mmu->root_hpa); 745 746 fault_mmu->inject_page_fault(vcpu, fault); 747 return fault->nested_page_fault; 748 } 749 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); 750 751 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 752 { 753 atomic_inc(&vcpu->arch.nmi_queued); 754 kvm_make_request(KVM_REQ_NMI, vcpu); 755 } 756 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 757 758 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 759 { 760 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 761 } 762 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 763 764 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 765 { 766 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 767 } 768 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 769 770 /* 771 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 772 * a #GP and return false. 773 */ 774 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 775 { 776 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) 777 return true; 778 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 779 return false; 780 } 781 EXPORT_SYMBOL_GPL(kvm_require_cpl); 782 783 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 784 { 785 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 786 return true; 787 788 kvm_queue_exception(vcpu, UD_VECTOR); 789 return false; 790 } 791 EXPORT_SYMBOL_GPL(kvm_require_dr); 792 793 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) 794 { 795 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); 796 } 797 798 /* 799 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. 800 */ 801 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 802 { 803 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 804 gpa_t real_gpa; 805 int i; 806 int ret; 807 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 808 809 /* 810 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated 811 * to an L1 GPA. 812 */ 813 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(pdpt_gfn), 814 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL); 815 if (real_gpa == UNMAPPED_GVA) 816 return 0; 817 818 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */ 819 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte, 820 cr3 & GENMASK(11, 5), sizeof(pdpte)); 821 if (ret < 0) 822 return 0; 823 824 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 825 if ((pdpte[i] & PT_PRESENT_MASK) && 826 (pdpte[i] & pdptr_rsvd_bits(vcpu))) { 827 return 0; 828 } 829 } 830 831 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 832 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 833 vcpu->arch.pdptrs_from_userspace = false; 834 835 return 1; 836 } 837 EXPORT_SYMBOL_GPL(load_pdptrs); 838 839 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) 840 { 841 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 842 kvm_clear_async_pf_completion_queue(vcpu); 843 kvm_async_pf_hash_reset(vcpu); 844 } 845 846 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS) 847 kvm_mmu_reset_context(vcpu); 848 849 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 850 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 851 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 852 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 853 } 854 EXPORT_SYMBOL_GPL(kvm_post_set_cr0); 855 856 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 857 { 858 unsigned long old_cr0 = kvm_read_cr0(vcpu); 859 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; 860 861 cr0 |= X86_CR0_ET; 862 863 #ifdef CONFIG_X86_64 864 if (cr0 & 0xffffffff00000000UL) 865 return 1; 866 #endif 867 868 cr0 &= ~CR0_RESERVED_BITS; 869 870 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 871 return 1; 872 873 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 874 return 1; 875 876 #ifdef CONFIG_X86_64 877 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && 878 (cr0 & X86_CR0_PG)) { 879 int cs_db, cs_l; 880 881 if (!is_pae(vcpu)) 882 return 1; 883 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 884 if (cs_l) 885 return 1; 886 } 887 #endif 888 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && 889 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && 890 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) 891 return 1; 892 893 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 894 return 1; 895 896 static_call(kvm_x86_set_cr0)(vcpu, cr0); 897 898 kvm_post_set_cr0(vcpu, old_cr0, cr0); 899 900 return 0; 901 } 902 EXPORT_SYMBOL_GPL(kvm_set_cr0); 903 904 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 905 { 906 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 907 } 908 EXPORT_SYMBOL_GPL(kvm_lmsw); 909 910 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) 911 { 912 if (vcpu->arch.guest_state_protected) 913 return; 914 915 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 916 917 if (vcpu->arch.xcr0 != host_xcr0) 918 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 919 920 if (vcpu->arch.xsaves_enabled && 921 vcpu->arch.ia32_xss != host_xss) 922 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 923 } 924 925 if (static_cpu_has(X86_FEATURE_PKU) && 926 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 927 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && 928 vcpu->arch.pkru != vcpu->arch.host_pkru) 929 write_pkru(vcpu->arch.pkru); 930 } 931 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); 932 933 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) 934 { 935 if (vcpu->arch.guest_state_protected) 936 return; 937 938 if (static_cpu_has(X86_FEATURE_PKU) && 939 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 940 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { 941 vcpu->arch.pkru = rdpkru(); 942 if (vcpu->arch.pkru != vcpu->arch.host_pkru) 943 write_pkru(vcpu->arch.host_pkru); 944 } 945 946 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 947 948 if (vcpu->arch.xcr0 != host_xcr0) 949 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 950 951 if (vcpu->arch.xsaves_enabled && 952 vcpu->arch.ia32_xss != host_xss) 953 wrmsrl(MSR_IA32_XSS, host_xss); 954 } 955 956 } 957 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); 958 959 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 960 { 961 u64 xcr0 = xcr; 962 u64 old_xcr0 = vcpu->arch.xcr0; 963 u64 valid_bits; 964 965 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 966 if (index != XCR_XFEATURE_ENABLED_MASK) 967 return 1; 968 if (!(xcr0 & XFEATURE_MASK_FP)) 969 return 1; 970 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 971 return 1; 972 973 /* 974 * Do not allow the guest to set bits that we do not support 975 * saving. However, xcr0 bit 0 is always set, even if the 976 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()). 977 */ 978 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 979 if (xcr0 & ~valid_bits) 980 return 1; 981 982 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 983 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 984 return 1; 985 986 if (xcr0 & XFEATURE_MASK_AVX512) { 987 if (!(xcr0 & XFEATURE_MASK_YMM)) 988 return 1; 989 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 990 return 1; 991 } 992 vcpu->arch.xcr0 = xcr0; 993 994 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 995 kvm_update_cpuid_runtime(vcpu); 996 return 0; 997 } 998 999 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) 1000 { 1001 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || 1002 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { 1003 kvm_inject_gp(vcpu, 0); 1004 return 1; 1005 } 1006 1007 return kvm_skip_emulated_instruction(vcpu); 1008 } 1009 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); 1010 1011 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1012 { 1013 if (cr4 & cr4_reserved_bits) 1014 return false; 1015 1016 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) 1017 return false; 1018 1019 return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); 1020 } 1021 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); 1022 1023 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) 1024 { 1025 /* 1026 * If any role bit is changed, the MMU needs to be reset. 1027 * 1028 * If CR4.PCIDE is changed 1 -> 0, the guest TLB must be flushed. 1029 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB 1030 * according to the SDM; however, stale prev_roots could be reused 1031 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we 1032 * free them all. KVM_REQ_MMU_RELOAD is fit for the both cases; it 1033 * is slow, but changing CR4.PCIDE is a rare case. 1034 * 1035 * If CR4.PGE is changed, the guest TLB must be flushed. 1036 * 1037 * Note: resetting MMU is a superset of KVM_REQ_MMU_RELOAD and 1038 * KVM_REQ_MMU_RELOAD is a superset of KVM_REQ_TLB_FLUSH_GUEST, hence 1039 * the usage of "else if". 1040 */ 1041 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) 1042 kvm_mmu_reset_context(vcpu); 1043 else if ((cr4 ^ old_cr4) & X86_CR4_PCIDE) 1044 kvm_make_request(KVM_REQ_MMU_RELOAD, vcpu); 1045 else if ((cr4 ^ old_cr4) & X86_CR4_PGE) 1046 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1047 } 1048 EXPORT_SYMBOL_GPL(kvm_post_set_cr4); 1049 1050 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1051 { 1052 unsigned long old_cr4 = kvm_read_cr4(vcpu); 1053 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 1054 X86_CR4_SMEP; 1055 1056 if (!kvm_is_valid_cr4(vcpu, cr4)) 1057 return 1; 1058 1059 if (is_long_mode(vcpu)) { 1060 if (!(cr4 & X86_CR4_PAE)) 1061 return 1; 1062 if ((cr4 ^ old_cr4) & X86_CR4_LA57) 1063 return 1; 1064 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 1065 && ((cr4 ^ old_cr4) & pdptr_bits) 1066 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 1067 kvm_read_cr3(vcpu))) 1068 return 1; 1069 1070 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 1071 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 1072 return 1; 1073 1074 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 1075 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 1076 return 1; 1077 } 1078 1079 static_call(kvm_x86_set_cr4)(vcpu, cr4); 1080 1081 kvm_post_set_cr4(vcpu, old_cr4, cr4); 1082 1083 return 0; 1084 } 1085 EXPORT_SYMBOL_GPL(kvm_set_cr4); 1086 1087 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) 1088 { 1089 struct kvm_mmu *mmu = vcpu->arch.mmu; 1090 unsigned long roots_to_free = 0; 1091 int i; 1092 1093 /* 1094 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but 1095 * this is reachable when running EPT=1 and unrestricted_guest=0, and 1096 * also via the emulator. KVM's TDP page tables are not in the scope of 1097 * the invalidation, but the guest's TLB entries need to be flushed as 1098 * the CPU may have cached entries in its TLB for the target PCID. 1099 */ 1100 if (unlikely(tdp_enabled)) { 1101 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1102 return; 1103 } 1104 1105 /* 1106 * If neither the current CR3 nor any of the prev_roots use the given 1107 * PCID, then nothing needs to be done here because a resync will 1108 * happen anyway before switching to any other CR3. 1109 */ 1110 if (kvm_get_active_pcid(vcpu) == pcid) { 1111 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); 1112 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1113 } 1114 1115 /* 1116 * If PCID is disabled, there is no need to free prev_roots even if the 1117 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB 1118 * with PCIDE=0. 1119 */ 1120 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 1121 return; 1122 1123 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 1124 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid) 1125 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 1126 1127 kvm_mmu_free_roots(vcpu, mmu, roots_to_free); 1128 } 1129 1130 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 1131 { 1132 bool skip_tlb_flush = false; 1133 unsigned long pcid = 0; 1134 #ifdef CONFIG_X86_64 1135 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 1136 1137 if (pcid_enabled) { 1138 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 1139 cr3 &= ~X86_CR3_PCID_NOFLUSH; 1140 pcid = cr3 & X86_CR3_PCID_MASK; 1141 } 1142 #endif 1143 1144 /* PDPTRs are always reloaded for PAE paging. */ 1145 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) 1146 goto handle_tlb_flush; 1147 1148 /* 1149 * Do not condition the GPA check on long mode, this helper is used to 1150 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that 1151 * the current vCPU mode is accurate. 1152 */ 1153 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) 1154 return 1; 1155 1156 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 1157 return 1; 1158 1159 if (cr3 != kvm_read_cr3(vcpu)) 1160 kvm_mmu_new_pgd(vcpu, cr3); 1161 1162 vcpu->arch.cr3 = cr3; 1163 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 1164 1165 handle_tlb_flush: 1166 /* 1167 * A load of CR3 that flushes the TLB flushes only the current PCID, 1168 * even if PCID is disabled, in which case PCID=0 is flushed. It's a 1169 * moot point in the end because _disabling_ PCID will flush all PCIDs, 1170 * and it's impossible to use a non-zero PCID when PCID is disabled, 1171 * i.e. only PCID=0 can be relevant. 1172 */ 1173 if (!skip_tlb_flush) 1174 kvm_invalidate_pcid(vcpu, pcid); 1175 1176 return 0; 1177 } 1178 EXPORT_SYMBOL_GPL(kvm_set_cr3); 1179 1180 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 1181 { 1182 if (cr8 & CR8_RESERVED_BITS) 1183 return 1; 1184 if (lapic_in_kernel(vcpu)) 1185 kvm_lapic_set_tpr(vcpu, cr8); 1186 else 1187 vcpu->arch.cr8 = cr8; 1188 return 0; 1189 } 1190 EXPORT_SYMBOL_GPL(kvm_set_cr8); 1191 1192 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 1193 { 1194 if (lapic_in_kernel(vcpu)) 1195 return kvm_lapic_get_cr8(vcpu); 1196 else 1197 return vcpu->arch.cr8; 1198 } 1199 EXPORT_SYMBOL_GPL(kvm_get_cr8); 1200 1201 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 1202 { 1203 int i; 1204 1205 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1206 for (i = 0; i < KVM_NR_DB_REGS; i++) 1207 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1208 } 1209 } 1210 1211 void kvm_update_dr7(struct kvm_vcpu *vcpu) 1212 { 1213 unsigned long dr7; 1214 1215 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1216 dr7 = vcpu->arch.guest_debug_dr7; 1217 else 1218 dr7 = vcpu->arch.dr7; 1219 static_call(kvm_x86_set_dr7)(vcpu, dr7); 1220 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1221 if (dr7 & DR7_BP_EN_MASK) 1222 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1223 } 1224 EXPORT_SYMBOL_GPL(kvm_update_dr7); 1225 1226 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1227 { 1228 u64 fixed = DR6_FIXED_1; 1229 1230 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1231 fixed |= DR6_RTM; 1232 1233 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) 1234 fixed |= DR6_BUS_LOCK; 1235 return fixed; 1236 } 1237 1238 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1239 { 1240 size_t size = ARRAY_SIZE(vcpu->arch.db); 1241 1242 switch (dr) { 1243 case 0 ... 3: 1244 vcpu->arch.db[array_index_nospec(dr, size)] = val; 1245 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1246 vcpu->arch.eff_db[dr] = val; 1247 break; 1248 case 4: 1249 case 6: 1250 if (!kvm_dr6_valid(val)) 1251 return 1; /* #GP */ 1252 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1253 break; 1254 case 5: 1255 default: /* 7 */ 1256 if (!kvm_dr7_valid(val)) 1257 return 1; /* #GP */ 1258 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1259 kvm_update_dr7(vcpu); 1260 break; 1261 } 1262 1263 return 0; 1264 } 1265 EXPORT_SYMBOL_GPL(kvm_set_dr); 1266 1267 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1268 { 1269 size_t size = ARRAY_SIZE(vcpu->arch.db); 1270 1271 switch (dr) { 1272 case 0 ... 3: 1273 *val = vcpu->arch.db[array_index_nospec(dr, size)]; 1274 break; 1275 case 4: 1276 case 6: 1277 *val = vcpu->arch.dr6; 1278 break; 1279 case 5: 1280 default: /* 7 */ 1281 *val = vcpu->arch.dr7; 1282 break; 1283 } 1284 } 1285 EXPORT_SYMBOL_GPL(kvm_get_dr); 1286 1287 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) 1288 { 1289 u32 ecx = kvm_rcx_read(vcpu); 1290 u64 data; 1291 1292 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { 1293 kvm_inject_gp(vcpu, 0); 1294 return 1; 1295 } 1296 1297 kvm_rax_write(vcpu, (u32)data); 1298 kvm_rdx_write(vcpu, data >> 32); 1299 return kvm_skip_emulated_instruction(vcpu); 1300 } 1301 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); 1302 1303 /* 1304 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1305 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1306 * 1307 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) 1308 * extract the supported MSRs from the related const lists. 1309 * msrs_to_save is selected from the msrs_to_save_all to reflect the 1310 * capabilities of the host cpu. This capabilities test skips MSRs that are 1311 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs 1312 * may depend on host virtualization features rather than host cpu features. 1313 */ 1314 1315 static const u32 msrs_to_save_all[] = { 1316 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1317 MSR_STAR, 1318 #ifdef CONFIG_X86_64 1319 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1320 #endif 1321 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1322 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1323 MSR_IA32_SPEC_CTRL, 1324 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1325 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1326 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1327 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1328 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1329 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1330 MSR_IA32_UMWAIT_CONTROL, 1331 1332 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, 1333 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, 1334 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, 1335 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 1336 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, 1337 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, 1338 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, 1339 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, 1340 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, 1341 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, 1342 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, 1343 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, 1344 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, 1345 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, 1346 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, 1347 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, 1348 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, 1349 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, 1350 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, 1351 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, 1352 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, 1353 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, 1354 1355 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3, 1356 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3, 1357 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2, 1358 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, 1359 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, 1360 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, 1361 }; 1362 1363 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; 1364 static unsigned num_msrs_to_save; 1365 1366 static const u32 emulated_msrs_all[] = { 1367 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1368 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1369 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1370 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1371 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1372 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1373 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1374 HV_X64_MSR_RESET, 1375 HV_X64_MSR_VP_INDEX, 1376 HV_X64_MSR_VP_RUNTIME, 1377 HV_X64_MSR_SCONTROL, 1378 HV_X64_MSR_STIMER0_CONFIG, 1379 HV_X64_MSR_VP_ASSIST_PAGE, 1380 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1381 HV_X64_MSR_TSC_EMULATION_STATUS, 1382 HV_X64_MSR_SYNDBG_OPTIONS, 1383 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, 1384 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, 1385 HV_X64_MSR_SYNDBG_PENDING_BUFFER, 1386 1387 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1388 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, 1389 1390 MSR_IA32_TSC_ADJUST, 1391 MSR_IA32_TSC_DEADLINE, 1392 MSR_IA32_ARCH_CAPABILITIES, 1393 MSR_IA32_PERF_CAPABILITIES, 1394 MSR_IA32_MISC_ENABLE, 1395 MSR_IA32_MCG_STATUS, 1396 MSR_IA32_MCG_CTL, 1397 MSR_IA32_MCG_EXT_CTL, 1398 MSR_IA32_SMBASE, 1399 MSR_SMI_COUNT, 1400 MSR_PLATFORM_INFO, 1401 MSR_MISC_FEATURES_ENABLES, 1402 MSR_AMD64_VIRT_SPEC_CTRL, 1403 MSR_AMD64_TSC_RATIO, 1404 MSR_IA32_POWER_CTL, 1405 MSR_IA32_UCODE_REV, 1406 1407 /* 1408 * The following list leaves out MSRs whose values are determined 1409 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. 1410 * We always support the "true" VMX control MSRs, even if the host 1411 * processor does not, so I am putting these registers here rather 1412 * than in msrs_to_save_all. 1413 */ 1414 MSR_IA32_VMX_BASIC, 1415 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1416 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1417 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1418 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1419 MSR_IA32_VMX_MISC, 1420 MSR_IA32_VMX_CR0_FIXED0, 1421 MSR_IA32_VMX_CR4_FIXED0, 1422 MSR_IA32_VMX_VMCS_ENUM, 1423 MSR_IA32_VMX_PROCBASED_CTLS2, 1424 MSR_IA32_VMX_EPT_VPID_CAP, 1425 MSR_IA32_VMX_VMFUNC, 1426 1427 MSR_K7_HWCR, 1428 MSR_KVM_POLL_CONTROL, 1429 }; 1430 1431 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; 1432 static unsigned num_emulated_msrs; 1433 1434 /* 1435 * List of msr numbers which are used to expose MSR-based features that 1436 * can be used by a hypervisor to validate requested CPU features. 1437 */ 1438 static const u32 msr_based_features_all[] = { 1439 MSR_IA32_VMX_BASIC, 1440 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1441 MSR_IA32_VMX_PINBASED_CTLS, 1442 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1443 MSR_IA32_VMX_PROCBASED_CTLS, 1444 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1445 MSR_IA32_VMX_EXIT_CTLS, 1446 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1447 MSR_IA32_VMX_ENTRY_CTLS, 1448 MSR_IA32_VMX_MISC, 1449 MSR_IA32_VMX_CR0_FIXED0, 1450 MSR_IA32_VMX_CR0_FIXED1, 1451 MSR_IA32_VMX_CR4_FIXED0, 1452 MSR_IA32_VMX_CR4_FIXED1, 1453 MSR_IA32_VMX_VMCS_ENUM, 1454 MSR_IA32_VMX_PROCBASED_CTLS2, 1455 MSR_IA32_VMX_EPT_VPID_CAP, 1456 MSR_IA32_VMX_VMFUNC, 1457 1458 MSR_F10H_DECFG, 1459 MSR_IA32_UCODE_REV, 1460 MSR_IA32_ARCH_CAPABILITIES, 1461 MSR_IA32_PERF_CAPABILITIES, 1462 }; 1463 1464 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; 1465 static unsigned int num_msr_based_features; 1466 1467 static u64 kvm_get_arch_capabilities(void) 1468 { 1469 u64 data = 0; 1470 1471 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1472 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); 1473 1474 /* 1475 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that 1476 * the nested hypervisor runs with NX huge pages. If it is not, 1477 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other 1478 * L1 guests, so it need not worry about its own (L2) guests. 1479 */ 1480 data |= ARCH_CAP_PSCHANGE_MC_NO; 1481 1482 /* 1483 * If we're doing cache flushes (either "always" or "cond") 1484 * we will do one whenever the guest does a vmlaunch/vmresume. 1485 * If an outer hypervisor is doing the cache flush for us 1486 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1487 * capability to the guest too, and if EPT is disabled we're not 1488 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1489 * require a nested hypervisor to do a flush of its own. 1490 */ 1491 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1492 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1493 1494 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) 1495 data |= ARCH_CAP_RDCL_NO; 1496 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1497 data |= ARCH_CAP_SSB_NO; 1498 if (!boot_cpu_has_bug(X86_BUG_MDS)) 1499 data |= ARCH_CAP_MDS_NO; 1500 1501 if (!boot_cpu_has(X86_FEATURE_RTM)) { 1502 /* 1503 * If RTM=0 because the kernel has disabled TSX, the host might 1504 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 1505 * and therefore knows that there cannot be TAA) but keep 1506 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, 1507 * and we want to allow migrating those guests to tsx=off hosts. 1508 */ 1509 data &= ~ARCH_CAP_TAA_NO; 1510 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { 1511 data |= ARCH_CAP_TAA_NO; 1512 } else { 1513 /* 1514 * Nothing to do here; we emulate TSX_CTRL if present on the 1515 * host so the guest can choose between disabling TSX or 1516 * using VERW to clear CPU buffers. 1517 */ 1518 } 1519 1520 return data; 1521 } 1522 1523 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1524 { 1525 switch (msr->index) { 1526 case MSR_IA32_ARCH_CAPABILITIES: 1527 msr->data = kvm_get_arch_capabilities(); 1528 break; 1529 case MSR_IA32_UCODE_REV: 1530 rdmsrl_safe(msr->index, &msr->data); 1531 break; 1532 default: 1533 return static_call(kvm_x86_get_msr_feature)(msr); 1534 } 1535 return 0; 1536 } 1537 1538 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1539 { 1540 struct kvm_msr_entry msr; 1541 int r; 1542 1543 msr.index = index; 1544 r = kvm_get_msr_feature(&msr); 1545 1546 if (r == KVM_MSR_RET_INVALID) { 1547 /* Unconditionally clear the output for simplicity */ 1548 *data = 0; 1549 if (kvm_msr_ignored_check(index, 0, false)) 1550 r = 0; 1551 } 1552 1553 if (r) 1554 return r; 1555 1556 *data = msr.data; 1557 1558 return 0; 1559 } 1560 1561 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1562 { 1563 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1564 return false; 1565 1566 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1567 return false; 1568 1569 if (efer & (EFER_LME | EFER_LMA) && 1570 !guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1571 return false; 1572 1573 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) 1574 return false; 1575 1576 return true; 1577 1578 } 1579 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1580 { 1581 if (efer & efer_reserved_bits) 1582 return false; 1583 1584 return __kvm_valid_efer(vcpu, efer); 1585 } 1586 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1587 1588 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1589 { 1590 u64 old_efer = vcpu->arch.efer; 1591 u64 efer = msr_info->data; 1592 int r; 1593 1594 if (efer & efer_reserved_bits) 1595 return 1; 1596 1597 if (!msr_info->host_initiated) { 1598 if (!__kvm_valid_efer(vcpu, efer)) 1599 return 1; 1600 1601 if (is_paging(vcpu) && 1602 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1603 return 1; 1604 } 1605 1606 efer &= ~EFER_LMA; 1607 efer |= vcpu->arch.efer & EFER_LMA; 1608 1609 r = static_call(kvm_x86_set_efer)(vcpu, efer); 1610 if (r) { 1611 WARN_ON(r > 0); 1612 return r; 1613 } 1614 1615 /* Update reserved bits */ 1616 if ((efer ^ old_efer) & EFER_NX) 1617 kvm_mmu_reset_context(vcpu); 1618 1619 return 0; 1620 } 1621 1622 void kvm_enable_efer_bits(u64 mask) 1623 { 1624 efer_reserved_bits &= ~mask; 1625 } 1626 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1627 1628 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) 1629 { 1630 struct kvm_x86_msr_filter *msr_filter; 1631 struct msr_bitmap_range *ranges; 1632 struct kvm *kvm = vcpu->kvm; 1633 bool allowed; 1634 int idx; 1635 u32 i; 1636 1637 /* x2APIC MSRs do not support filtering. */ 1638 if (index >= 0x800 && index <= 0x8ff) 1639 return true; 1640 1641 idx = srcu_read_lock(&kvm->srcu); 1642 1643 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); 1644 if (!msr_filter) { 1645 allowed = true; 1646 goto out; 1647 } 1648 1649 allowed = msr_filter->default_allow; 1650 ranges = msr_filter->ranges; 1651 1652 for (i = 0; i < msr_filter->count; i++) { 1653 u32 start = ranges[i].base; 1654 u32 end = start + ranges[i].nmsrs; 1655 u32 flags = ranges[i].flags; 1656 unsigned long *bitmap = ranges[i].bitmap; 1657 1658 if ((index >= start) && (index < end) && (flags & type)) { 1659 allowed = !!test_bit(index - start, bitmap); 1660 break; 1661 } 1662 } 1663 1664 out: 1665 srcu_read_unlock(&kvm->srcu, idx); 1666 1667 return allowed; 1668 } 1669 EXPORT_SYMBOL_GPL(kvm_msr_allowed); 1670 1671 /* 1672 * Write @data into the MSR specified by @index. Select MSR specific fault 1673 * checks are bypassed if @host_initiated is %true. 1674 * Returns 0 on success, non-0 otherwise. 1675 * Assumes vcpu_load() was already called. 1676 */ 1677 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, 1678 bool host_initiated) 1679 { 1680 struct msr_data msr; 1681 1682 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) 1683 return KVM_MSR_RET_FILTERED; 1684 1685 switch (index) { 1686 case MSR_FS_BASE: 1687 case MSR_GS_BASE: 1688 case MSR_KERNEL_GS_BASE: 1689 case MSR_CSTAR: 1690 case MSR_LSTAR: 1691 if (is_noncanonical_address(data, vcpu)) 1692 return 1; 1693 break; 1694 case MSR_IA32_SYSENTER_EIP: 1695 case MSR_IA32_SYSENTER_ESP: 1696 /* 1697 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1698 * non-canonical address is written on Intel but not on 1699 * AMD (which ignores the top 32-bits, because it does 1700 * not implement 64-bit SYSENTER). 1701 * 1702 * 64-bit code should hence be able to write a non-canonical 1703 * value on AMD. Making the address canonical ensures that 1704 * vmentry does not fail on Intel after writing a non-canonical 1705 * value, and that something deterministic happens if the guest 1706 * invokes 64-bit SYSENTER. 1707 */ 1708 data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); 1709 break; 1710 case MSR_TSC_AUX: 1711 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1712 return 1; 1713 1714 if (!host_initiated && 1715 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1716 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1717 return 1; 1718 1719 /* 1720 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has 1721 * incomplete and conflicting architectural behavior. Current 1722 * AMD CPUs completely ignore bits 63:32, i.e. they aren't 1723 * reserved and always read as zeros. Enforce Intel's reserved 1724 * bits check if and only if the guest CPU is Intel, and clear 1725 * the bits in all other cases. This ensures cross-vendor 1726 * migration will provide consistent behavior for the guest. 1727 */ 1728 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) 1729 return 1; 1730 1731 data = (u32)data; 1732 break; 1733 } 1734 1735 msr.data = data; 1736 msr.index = index; 1737 msr.host_initiated = host_initiated; 1738 1739 return static_call(kvm_x86_set_msr)(vcpu, &msr); 1740 } 1741 1742 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, 1743 u32 index, u64 data, bool host_initiated) 1744 { 1745 int ret = __kvm_set_msr(vcpu, index, data, host_initiated); 1746 1747 if (ret == KVM_MSR_RET_INVALID) 1748 if (kvm_msr_ignored_check(index, data, true)) 1749 ret = 0; 1750 1751 return ret; 1752 } 1753 1754 /* 1755 * Read the MSR specified by @index into @data. Select MSR specific fault 1756 * checks are bypassed if @host_initiated is %true. 1757 * Returns 0 on success, non-0 otherwise. 1758 * Assumes vcpu_load() was already called. 1759 */ 1760 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1761 bool host_initiated) 1762 { 1763 struct msr_data msr; 1764 int ret; 1765 1766 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) 1767 return KVM_MSR_RET_FILTERED; 1768 1769 switch (index) { 1770 case MSR_TSC_AUX: 1771 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1772 return 1; 1773 1774 if (!host_initiated && 1775 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1776 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1777 return 1; 1778 break; 1779 } 1780 1781 msr.index = index; 1782 msr.host_initiated = host_initiated; 1783 1784 ret = static_call(kvm_x86_get_msr)(vcpu, &msr); 1785 if (!ret) 1786 *data = msr.data; 1787 return ret; 1788 } 1789 1790 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, 1791 u32 index, u64 *data, bool host_initiated) 1792 { 1793 int ret = __kvm_get_msr(vcpu, index, data, host_initiated); 1794 1795 if (ret == KVM_MSR_RET_INVALID) { 1796 /* Unconditionally clear *data for simplicity */ 1797 *data = 0; 1798 if (kvm_msr_ignored_check(index, 0, false)) 1799 ret = 0; 1800 } 1801 1802 return ret; 1803 } 1804 1805 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1806 { 1807 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1808 } 1809 EXPORT_SYMBOL_GPL(kvm_get_msr); 1810 1811 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) 1812 { 1813 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1814 } 1815 EXPORT_SYMBOL_GPL(kvm_set_msr); 1816 1817 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) 1818 { 1819 int err = vcpu->run->msr.error; 1820 if (!err) { 1821 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); 1822 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); 1823 } 1824 1825 return static_call(kvm_x86_complete_emulated_msr)(vcpu, err); 1826 } 1827 1828 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu) 1829 { 1830 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); 1831 } 1832 1833 static u64 kvm_msr_reason(int r) 1834 { 1835 switch (r) { 1836 case KVM_MSR_RET_INVALID: 1837 return KVM_MSR_EXIT_REASON_UNKNOWN; 1838 case KVM_MSR_RET_FILTERED: 1839 return KVM_MSR_EXIT_REASON_FILTER; 1840 default: 1841 return KVM_MSR_EXIT_REASON_INVAL; 1842 } 1843 } 1844 1845 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, 1846 u32 exit_reason, u64 data, 1847 int (*completion)(struct kvm_vcpu *vcpu), 1848 int r) 1849 { 1850 u64 msr_reason = kvm_msr_reason(r); 1851 1852 /* Check if the user wanted to know about this MSR fault */ 1853 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) 1854 return 0; 1855 1856 vcpu->run->exit_reason = exit_reason; 1857 vcpu->run->msr.error = 0; 1858 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); 1859 vcpu->run->msr.reason = msr_reason; 1860 vcpu->run->msr.index = index; 1861 vcpu->run->msr.data = data; 1862 vcpu->arch.complete_userspace_io = completion; 1863 1864 return 1; 1865 } 1866 1867 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r) 1868 { 1869 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0, 1870 complete_emulated_rdmsr, r); 1871 } 1872 1873 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r) 1874 { 1875 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data, 1876 complete_emulated_wrmsr, r); 1877 } 1878 1879 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) 1880 { 1881 u32 ecx = kvm_rcx_read(vcpu); 1882 u64 data; 1883 int r; 1884 1885 r = kvm_get_msr(vcpu, ecx, &data); 1886 1887 /* MSR read failed? See if we should ask user space */ 1888 if (r && kvm_get_msr_user_space(vcpu, ecx, r)) { 1889 /* Bounce to user space */ 1890 return 0; 1891 } 1892 1893 if (!r) { 1894 trace_kvm_msr_read(ecx, data); 1895 1896 kvm_rax_write(vcpu, data & -1u); 1897 kvm_rdx_write(vcpu, (data >> 32) & -1u); 1898 } else { 1899 trace_kvm_msr_read_ex(ecx); 1900 } 1901 1902 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1903 } 1904 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); 1905 1906 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) 1907 { 1908 u32 ecx = kvm_rcx_read(vcpu); 1909 u64 data = kvm_read_edx_eax(vcpu); 1910 int r; 1911 1912 r = kvm_set_msr(vcpu, ecx, data); 1913 1914 /* MSR write failed? See if we should ask user space */ 1915 if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) 1916 /* Bounce to user space */ 1917 return 0; 1918 1919 /* Signal all other negative errors to userspace */ 1920 if (r < 0) 1921 return r; 1922 1923 if (!r) 1924 trace_kvm_msr_write(ecx, data); 1925 else 1926 trace_kvm_msr_write_ex(ecx, data); 1927 1928 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1929 } 1930 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); 1931 1932 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) 1933 { 1934 return kvm_skip_emulated_instruction(vcpu); 1935 } 1936 EXPORT_SYMBOL_GPL(kvm_emulate_as_nop); 1937 1938 int kvm_emulate_invd(struct kvm_vcpu *vcpu) 1939 { 1940 /* Treat an INVD instruction as a NOP and just skip it. */ 1941 return kvm_emulate_as_nop(vcpu); 1942 } 1943 EXPORT_SYMBOL_GPL(kvm_emulate_invd); 1944 1945 int kvm_emulate_mwait(struct kvm_vcpu *vcpu) 1946 { 1947 pr_warn_once("kvm: MWAIT instruction emulated as NOP!\n"); 1948 return kvm_emulate_as_nop(vcpu); 1949 } 1950 EXPORT_SYMBOL_GPL(kvm_emulate_mwait); 1951 1952 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) 1953 { 1954 kvm_queue_exception(vcpu, UD_VECTOR); 1955 return 1; 1956 } 1957 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); 1958 1959 int kvm_emulate_monitor(struct kvm_vcpu *vcpu) 1960 { 1961 pr_warn_once("kvm: MONITOR instruction emulated as NOP!\n"); 1962 return kvm_emulate_as_nop(vcpu); 1963 } 1964 EXPORT_SYMBOL_GPL(kvm_emulate_monitor); 1965 1966 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) 1967 { 1968 xfer_to_guest_mode_prepare(); 1969 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || 1970 xfer_to_guest_mode_work_pending(); 1971 } 1972 1973 /* 1974 * The fast path for frequent and performance sensitive wrmsr emulation, 1975 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces 1976 * the latency of virtual IPI by avoiding the expensive bits of transitioning 1977 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the 1978 * other cases which must be called after interrupts are enabled on the host. 1979 */ 1980 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) 1981 { 1982 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) 1983 return 1; 1984 1985 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && 1986 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && 1987 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && 1988 ((u32)(data >> 32) != X2APIC_BROADCAST)) { 1989 1990 data &= ~(1 << 12); 1991 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); 1992 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); 1993 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); 1994 trace_kvm_apic_write(APIC_ICR, (u32)data); 1995 return 0; 1996 } 1997 1998 return 1; 1999 } 2000 2001 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) 2002 { 2003 if (!kvm_can_use_hv_timer(vcpu)) 2004 return 1; 2005 2006 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2007 return 0; 2008 } 2009 2010 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) 2011 { 2012 u32 msr = kvm_rcx_read(vcpu); 2013 u64 data; 2014 fastpath_t ret = EXIT_FASTPATH_NONE; 2015 2016 switch (msr) { 2017 case APIC_BASE_MSR + (APIC_ICR >> 4): 2018 data = kvm_read_edx_eax(vcpu); 2019 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { 2020 kvm_skip_emulated_instruction(vcpu); 2021 ret = EXIT_FASTPATH_EXIT_HANDLED; 2022 } 2023 break; 2024 case MSR_IA32_TSC_DEADLINE: 2025 data = kvm_read_edx_eax(vcpu); 2026 if (!handle_fastpath_set_tscdeadline(vcpu, data)) { 2027 kvm_skip_emulated_instruction(vcpu); 2028 ret = EXIT_FASTPATH_REENTER_GUEST; 2029 } 2030 break; 2031 default: 2032 break; 2033 } 2034 2035 if (ret != EXIT_FASTPATH_NONE) 2036 trace_kvm_msr_write(msr, data); 2037 2038 return ret; 2039 } 2040 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); 2041 2042 /* 2043 * Adapt set_msr() to msr_io()'s calling convention 2044 */ 2045 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2046 { 2047 return kvm_get_msr_ignored_check(vcpu, index, data, true); 2048 } 2049 2050 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2051 { 2052 return kvm_set_msr_ignored_check(vcpu, index, *data, true); 2053 } 2054 2055 #ifdef CONFIG_X86_64 2056 struct pvclock_clock { 2057 int vclock_mode; 2058 u64 cycle_last; 2059 u64 mask; 2060 u32 mult; 2061 u32 shift; 2062 u64 base_cycles; 2063 u64 offset; 2064 }; 2065 2066 struct pvclock_gtod_data { 2067 seqcount_t seq; 2068 2069 struct pvclock_clock clock; /* extract of a clocksource struct */ 2070 struct pvclock_clock raw_clock; /* extract of a clocksource struct */ 2071 2072 ktime_t offs_boot; 2073 u64 wall_time_sec; 2074 }; 2075 2076 static struct pvclock_gtod_data pvclock_gtod_data; 2077 2078 static void update_pvclock_gtod(struct timekeeper *tk) 2079 { 2080 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 2081 2082 write_seqcount_begin(&vdata->seq); 2083 2084 /* copy pvclock gtod data */ 2085 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; 2086 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 2087 vdata->clock.mask = tk->tkr_mono.mask; 2088 vdata->clock.mult = tk->tkr_mono.mult; 2089 vdata->clock.shift = tk->tkr_mono.shift; 2090 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 2091 vdata->clock.offset = tk->tkr_mono.base; 2092 2093 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; 2094 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; 2095 vdata->raw_clock.mask = tk->tkr_raw.mask; 2096 vdata->raw_clock.mult = tk->tkr_raw.mult; 2097 vdata->raw_clock.shift = tk->tkr_raw.shift; 2098 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; 2099 vdata->raw_clock.offset = tk->tkr_raw.base; 2100 2101 vdata->wall_time_sec = tk->xtime_sec; 2102 2103 vdata->offs_boot = tk->offs_boot; 2104 2105 write_seqcount_end(&vdata->seq); 2106 } 2107 2108 static s64 get_kvmclock_base_ns(void) 2109 { 2110 /* Count up from boot time, but with the frequency of the raw clock. */ 2111 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); 2112 } 2113 #else 2114 static s64 get_kvmclock_base_ns(void) 2115 { 2116 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ 2117 return ktime_get_boottime_ns(); 2118 } 2119 #endif 2120 2121 void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) 2122 { 2123 int version; 2124 int r; 2125 struct pvclock_wall_clock wc; 2126 u32 wc_sec_hi; 2127 u64 wall_nsec; 2128 2129 if (!wall_clock) 2130 return; 2131 2132 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 2133 if (r) 2134 return; 2135 2136 if (version & 1) 2137 ++version; /* first time write, random junk */ 2138 2139 ++version; 2140 2141 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 2142 return; 2143 2144 /* 2145 * The guest calculates current wall clock time by adding 2146 * system time (updated by kvm_guest_time_update below) to the 2147 * wall clock specified here. We do the reverse here. 2148 */ 2149 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); 2150 2151 wc.nsec = do_div(wall_nsec, 1000000000); 2152 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ 2153 wc.version = version; 2154 2155 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 2156 2157 if (sec_hi_ofs) { 2158 wc_sec_hi = wall_nsec >> 32; 2159 kvm_write_guest(kvm, wall_clock + sec_hi_ofs, 2160 &wc_sec_hi, sizeof(wc_sec_hi)); 2161 } 2162 2163 version++; 2164 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 2165 } 2166 2167 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, 2168 bool old_msr, bool host_initiated) 2169 { 2170 struct kvm_arch *ka = &vcpu->kvm->arch; 2171 2172 if (vcpu->vcpu_id == 0 && !host_initiated) { 2173 if (ka->boot_vcpu_runs_old_kvmclock != old_msr) 2174 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2175 2176 ka->boot_vcpu_runs_old_kvmclock = old_msr; 2177 } 2178 2179 vcpu->arch.time = system_time; 2180 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2181 2182 /* we verify if the enable bit is set... */ 2183 vcpu->arch.pv_time_enabled = false; 2184 if (!(system_time & 1)) 2185 return; 2186 2187 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, 2188 &vcpu->arch.pv_time, system_time & ~1ULL, 2189 sizeof(struct pvclock_vcpu_time_info))) 2190 vcpu->arch.pv_time_enabled = true; 2191 2192 return; 2193 } 2194 2195 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 2196 { 2197 do_shl32_div32(dividend, divisor); 2198 return dividend; 2199 } 2200 2201 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 2202 s8 *pshift, u32 *pmultiplier) 2203 { 2204 uint64_t scaled64; 2205 int32_t shift = 0; 2206 uint64_t tps64; 2207 uint32_t tps32; 2208 2209 tps64 = base_hz; 2210 scaled64 = scaled_hz; 2211 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 2212 tps64 >>= 1; 2213 shift--; 2214 } 2215 2216 tps32 = (uint32_t)tps64; 2217 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 2218 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 2219 scaled64 >>= 1; 2220 else 2221 tps32 <<= 1; 2222 shift++; 2223 } 2224 2225 *pshift = shift; 2226 *pmultiplier = div_frac(scaled64, tps32); 2227 } 2228 2229 #ifdef CONFIG_X86_64 2230 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 2231 #endif 2232 2233 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 2234 static unsigned long max_tsc_khz; 2235 2236 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 2237 { 2238 u64 v = (u64)khz * (1000000 + ppm); 2239 do_div(v, 1000000); 2240 return v; 2241 } 2242 2243 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier); 2244 2245 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 2246 { 2247 u64 ratio; 2248 2249 /* Guest TSC same frequency as host TSC? */ 2250 if (!scale) { 2251 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); 2252 return 0; 2253 } 2254 2255 /* TSC scaling supported? */ 2256 if (!kvm_has_tsc_control) { 2257 if (user_tsc_khz > tsc_khz) { 2258 vcpu->arch.tsc_catchup = 1; 2259 vcpu->arch.tsc_always_catchup = 1; 2260 return 0; 2261 } else { 2262 pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); 2263 return -1; 2264 } 2265 } 2266 2267 /* TSC scaling required - calculate ratio */ 2268 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 2269 user_tsc_khz, tsc_khz); 2270 2271 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 2272 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 2273 user_tsc_khz); 2274 return -1; 2275 } 2276 2277 kvm_vcpu_write_tsc_multiplier(vcpu, ratio); 2278 return 0; 2279 } 2280 2281 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 2282 { 2283 u32 thresh_lo, thresh_hi; 2284 int use_scaling = 0; 2285 2286 /* tsc_khz can be zero if TSC calibration fails */ 2287 if (user_tsc_khz == 0) { 2288 /* set tsc_scaling_ratio to a safe value */ 2289 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); 2290 return -1; 2291 } 2292 2293 /* Compute a scale to convert nanoseconds in TSC cycles */ 2294 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 2295 &vcpu->arch.virtual_tsc_shift, 2296 &vcpu->arch.virtual_tsc_mult); 2297 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 2298 2299 /* 2300 * Compute the variation in TSC rate which is acceptable 2301 * within the range of tolerance and decide if the 2302 * rate being applied is within that bounds of the hardware 2303 * rate. If so, no scaling or compensation need be done. 2304 */ 2305 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 2306 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 2307 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 2308 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 2309 use_scaling = 1; 2310 } 2311 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 2312 } 2313 2314 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 2315 { 2316 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 2317 vcpu->arch.virtual_tsc_mult, 2318 vcpu->arch.virtual_tsc_shift); 2319 tsc += vcpu->arch.this_tsc_write; 2320 return tsc; 2321 } 2322 2323 static inline int gtod_is_based_on_tsc(int mode) 2324 { 2325 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; 2326 } 2327 2328 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 2329 { 2330 #ifdef CONFIG_X86_64 2331 bool vcpus_matched; 2332 struct kvm_arch *ka = &vcpu->kvm->arch; 2333 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2334 2335 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2336 atomic_read(&vcpu->kvm->online_vcpus)); 2337 2338 /* 2339 * Once the masterclock is enabled, always perform request in 2340 * order to update it. 2341 * 2342 * In order to enable masterclock, the host clocksource must be TSC 2343 * and the vcpus need to have matched TSCs. When that happens, 2344 * perform request to enable masterclock. 2345 */ 2346 if (ka->use_master_clock || 2347 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 2348 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2349 2350 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 2351 atomic_read(&vcpu->kvm->online_vcpus), 2352 ka->use_master_clock, gtod->clock.vclock_mode); 2353 #endif 2354 } 2355 2356 /* 2357 * Multiply tsc by a fixed point number represented by ratio. 2358 * 2359 * The most significant 64-N bits (mult) of ratio represent the 2360 * integral part of the fixed point number; the remaining N bits 2361 * (frac) represent the fractional part, ie. ratio represents a fixed 2362 * point number (mult + frac * 2^(-N)). 2363 * 2364 * N equals to kvm_tsc_scaling_ratio_frac_bits. 2365 */ 2366 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 2367 { 2368 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 2369 } 2370 2371 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc, u64 ratio) 2372 { 2373 u64 _tsc = tsc; 2374 2375 if (ratio != kvm_default_tsc_scaling_ratio) 2376 _tsc = __scale_tsc(ratio, tsc); 2377 2378 return _tsc; 2379 } 2380 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 2381 2382 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 2383 { 2384 u64 tsc; 2385 2386 tsc = kvm_scale_tsc(vcpu, rdtsc(), vcpu->arch.l1_tsc_scaling_ratio); 2387 2388 return target_tsc - tsc; 2389 } 2390 2391 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 2392 { 2393 return vcpu->arch.l1_tsc_offset + 2394 kvm_scale_tsc(vcpu, host_tsc, vcpu->arch.l1_tsc_scaling_ratio); 2395 } 2396 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 2397 2398 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier) 2399 { 2400 u64 nested_offset; 2401 2402 if (l2_multiplier == kvm_default_tsc_scaling_ratio) 2403 nested_offset = l1_offset; 2404 else 2405 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier, 2406 kvm_tsc_scaling_ratio_frac_bits); 2407 2408 nested_offset += l2_offset; 2409 return nested_offset; 2410 } 2411 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset); 2412 2413 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier) 2414 { 2415 if (l2_multiplier != kvm_default_tsc_scaling_ratio) 2416 return mul_u64_u64_shr(l1_multiplier, l2_multiplier, 2417 kvm_tsc_scaling_ratio_frac_bits); 2418 2419 return l1_multiplier; 2420 } 2421 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier); 2422 2423 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset) 2424 { 2425 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 2426 vcpu->arch.l1_tsc_offset, 2427 l1_offset); 2428 2429 vcpu->arch.l1_tsc_offset = l1_offset; 2430 2431 /* 2432 * If we are here because L1 chose not to trap WRMSR to TSC then 2433 * according to the spec this should set L1's TSC (as opposed to 2434 * setting L1's offset for L2). 2435 */ 2436 if (is_guest_mode(vcpu)) 2437 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( 2438 l1_offset, 2439 static_call(kvm_x86_get_l2_tsc_offset)(vcpu), 2440 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2441 else 2442 vcpu->arch.tsc_offset = l1_offset; 2443 2444 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset); 2445 } 2446 2447 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier) 2448 { 2449 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier; 2450 2451 /* Userspace is changing the multiplier while L2 is active */ 2452 if (is_guest_mode(vcpu)) 2453 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( 2454 l1_multiplier, 2455 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2456 else 2457 vcpu->arch.tsc_scaling_ratio = l1_multiplier; 2458 2459 if (kvm_has_tsc_control) 2460 static_call(kvm_x86_write_tsc_multiplier)( 2461 vcpu, vcpu->arch.tsc_scaling_ratio); 2462 } 2463 2464 static inline bool kvm_check_tsc_unstable(void) 2465 { 2466 #ifdef CONFIG_X86_64 2467 /* 2468 * TSC is marked unstable when we're running on Hyper-V, 2469 * 'TSC page' clocksource is good. 2470 */ 2471 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) 2472 return false; 2473 #endif 2474 return check_tsc_unstable(); 2475 } 2476 2477 /* 2478 * Infers attempts to synchronize the guest's tsc from host writes. Sets the 2479 * offset for the vcpu and tracks the TSC matching generation that the vcpu 2480 * participates in. 2481 */ 2482 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc, 2483 u64 ns, bool matched) 2484 { 2485 struct kvm *kvm = vcpu->kvm; 2486 2487 lockdep_assert_held(&kvm->arch.tsc_write_lock); 2488 2489 /* 2490 * We also track th most recent recorded KHZ, write and time to 2491 * allow the matching interval to be extended at each write. 2492 */ 2493 kvm->arch.last_tsc_nsec = ns; 2494 kvm->arch.last_tsc_write = tsc; 2495 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 2496 kvm->arch.last_tsc_offset = offset; 2497 2498 vcpu->arch.last_guest_tsc = tsc; 2499 2500 kvm_vcpu_write_tsc_offset(vcpu, offset); 2501 2502 if (!matched) { 2503 /* 2504 * We split periods of matched TSC writes into generations. 2505 * For each generation, we track the original measured 2506 * nanosecond time, offset, and write, so if TSCs are in 2507 * sync, we can match exact offset, and if not, we can match 2508 * exact software computation in compute_guest_tsc() 2509 * 2510 * These values are tracked in kvm->arch.cur_xxx variables. 2511 */ 2512 kvm->arch.cur_tsc_generation++; 2513 kvm->arch.cur_tsc_nsec = ns; 2514 kvm->arch.cur_tsc_write = tsc; 2515 kvm->arch.cur_tsc_offset = offset; 2516 kvm->arch.nr_vcpus_matched_tsc = 0; 2517 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) { 2518 kvm->arch.nr_vcpus_matched_tsc++; 2519 } 2520 2521 /* Keep track of which generation this VCPU has synchronized to */ 2522 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 2523 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 2524 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 2525 2526 kvm_track_tsc_matching(vcpu); 2527 } 2528 2529 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) 2530 { 2531 struct kvm *kvm = vcpu->kvm; 2532 u64 offset, ns, elapsed; 2533 unsigned long flags; 2534 bool matched = false; 2535 bool synchronizing = false; 2536 2537 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 2538 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2539 ns = get_kvmclock_base_ns(); 2540 elapsed = ns - kvm->arch.last_tsc_nsec; 2541 2542 if (vcpu->arch.virtual_tsc_khz) { 2543 if (data == 0) { 2544 /* 2545 * detection of vcpu initialization -- need to sync 2546 * with other vCPUs. This particularly helps to keep 2547 * kvm_clock stable after CPU hotplug 2548 */ 2549 synchronizing = true; 2550 } else { 2551 u64 tsc_exp = kvm->arch.last_tsc_write + 2552 nsec_to_cycles(vcpu, elapsed); 2553 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 2554 /* 2555 * Special case: TSC write with a small delta (1 second) 2556 * of virtual cycle time against real time is 2557 * interpreted as an attempt to synchronize the CPU. 2558 */ 2559 synchronizing = data < tsc_exp + tsc_hz && 2560 data + tsc_hz > tsc_exp; 2561 } 2562 } 2563 2564 /* 2565 * For a reliable TSC, we can match TSC offsets, and for an unstable 2566 * TSC, we add elapsed time in this computation. We could let the 2567 * compensation code attempt to catch up if we fall behind, but 2568 * it's better to try to match offsets from the beginning. 2569 */ 2570 if (synchronizing && 2571 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 2572 if (!kvm_check_tsc_unstable()) { 2573 offset = kvm->arch.cur_tsc_offset; 2574 } else { 2575 u64 delta = nsec_to_cycles(vcpu, elapsed); 2576 data += delta; 2577 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2578 } 2579 matched = true; 2580 } 2581 2582 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched); 2583 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 2584 } 2585 2586 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 2587 s64 adjustment) 2588 { 2589 u64 tsc_offset = vcpu->arch.l1_tsc_offset; 2590 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 2591 } 2592 2593 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 2594 { 2595 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 2596 WARN_ON(adjustment < 0); 2597 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment, 2598 vcpu->arch.l1_tsc_scaling_ratio); 2599 adjust_tsc_offset_guest(vcpu, adjustment); 2600 } 2601 2602 #ifdef CONFIG_X86_64 2603 2604 static u64 read_tsc(void) 2605 { 2606 u64 ret = (u64)rdtsc_ordered(); 2607 u64 last = pvclock_gtod_data.clock.cycle_last; 2608 2609 if (likely(ret >= last)) 2610 return ret; 2611 2612 /* 2613 * GCC likes to generate cmov here, but this branch is extremely 2614 * predictable (it's just a function of time and the likely is 2615 * very likely) and there's a data dependence, so force GCC 2616 * to generate a branch instead. I don't barrier() because 2617 * we don't actually need a barrier, and if this function 2618 * ever gets inlined it will generate worse code. 2619 */ 2620 asm volatile (""); 2621 return last; 2622 } 2623 2624 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, 2625 int *mode) 2626 { 2627 long v; 2628 u64 tsc_pg_val; 2629 2630 switch (clock->vclock_mode) { 2631 case VDSO_CLOCKMODE_HVCLOCK: 2632 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 2633 tsc_timestamp); 2634 if (tsc_pg_val != U64_MAX) { 2635 /* TSC page valid */ 2636 *mode = VDSO_CLOCKMODE_HVCLOCK; 2637 v = (tsc_pg_val - clock->cycle_last) & 2638 clock->mask; 2639 } else { 2640 /* TSC page invalid */ 2641 *mode = VDSO_CLOCKMODE_NONE; 2642 } 2643 break; 2644 case VDSO_CLOCKMODE_TSC: 2645 *mode = VDSO_CLOCKMODE_TSC; 2646 *tsc_timestamp = read_tsc(); 2647 v = (*tsc_timestamp - clock->cycle_last) & 2648 clock->mask; 2649 break; 2650 default: 2651 *mode = VDSO_CLOCKMODE_NONE; 2652 } 2653 2654 if (*mode == VDSO_CLOCKMODE_NONE) 2655 *tsc_timestamp = v = 0; 2656 2657 return v * clock->mult; 2658 } 2659 2660 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) 2661 { 2662 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2663 unsigned long seq; 2664 int mode; 2665 u64 ns; 2666 2667 do { 2668 seq = read_seqcount_begin(>od->seq); 2669 ns = gtod->raw_clock.base_cycles; 2670 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); 2671 ns >>= gtod->raw_clock.shift; 2672 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); 2673 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2674 *t = ns; 2675 2676 return mode; 2677 } 2678 2679 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 2680 { 2681 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2682 unsigned long seq; 2683 int mode; 2684 u64 ns; 2685 2686 do { 2687 seq = read_seqcount_begin(>od->seq); 2688 ts->tv_sec = gtod->wall_time_sec; 2689 ns = gtod->clock.base_cycles; 2690 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2691 ns >>= gtod->clock.shift; 2692 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2693 2694 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 2695 ts->tv_nsec = ns; 2696 2697 return mode; 2698 } 2699 2700 /* returns true if host is using TSC based clocksource */ 2701 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2702 { 2703 /* checked again under seqlock below */ 2704 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2705 return false; 2706 2707 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, 2708 tsc_timestamp)); 2709 } 2710 2711 /* returns true if host is using TSC based clocksource */ 2712 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 2713 u64 *tsc_timestamp) 2714 { 2715 /* checked again under seqlock below */ 2716 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2717 return false; 2718 2719 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 2720 } 2721 #endif 2722 2723 /* 2724 * 2725 * Assuming a stable TSC across physical CPUS, and a stable TSC 2726 * across virtual CPUs, the following condition is possible. 2727 * Each numbered line represents an event visible to both 2728 * CPUs at the next numbered event. 2729 * 2730 * "timespecX" represents host monotonic time. "tscX" represents 2731 * RDTSC value. 2732 * 2733 * VCPU0 on CPU0 | VCPU1 on CPU1 2734 * 2735 * 1. read timespec0,tsc0 2736 * 2. | timespec1 = timespec0 + N 2737 * | tsc1 = tsc0 + M 2738 * 3. transition to guest | transition to guest 2739 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 2740 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 2741 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 2742 * 2743 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 2744 * 2745 * - ret0 < ret1 2746 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 2747 * ... 2748 * - 0 < N - M => M < N 2749 * 2750 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 2751 * always the case (the difference between two distinct xtime instances 2752 * might be smaller then the difference between corresponding TSC reads, 2753 * when updating guest vcpus pvclock areas). 2754 * 2755 * To avoid that problem, do not allow visibility of distinct 2756 * system_timestamp/tsc_timestamp values simultaneously: use a master 2757 * copy of host monotonic time values. Update that master copy 2758 * in lockstep. 2759 * 2760 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2761 * 2762 */ 2763 2764 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2765 { 2766 #ifdef CONFIG_X86_64 2767 struct kvm_arch *ka = &kvm->arch; 2768 int vclock_mode; 2769 bool host_tsc_clocksource, vcpus_matched; 2770 2771 lockdep_assert_held(&kvm->arch.tsc_write_lock); 2772 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2773 atomic_read(&kvm->online_vcpus)); 2774 2775 /* 2776 * If the host uses TSC clock, then passthrough TSC as stable 2777 * to the guest. 2778 */ 2779 host_tsc_clocksource = kvm_get_time_and_clockread( 2780 &ka->master_kernel_ns, 2781 &ka->master_cycle_now); 2782 2783 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2784 && !ka->backwards_tsc_observed 2785 && !ka->boot_vcpu_runs_old_kvmclock; 2786 2787 if (ka->use_master_clock) 2788 atomic_set(&kvm_guest_has_master_clock, 1); 2789 2790 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2791 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2792 vcpus_matched); 2793 #endif 2794 } 2795 2796 static void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2797 { 2798 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2799 } 2800 2801 static void __kvm_start_pvclock_update(struct kvm *kvm) 2802 { 2803 raw_spin_lock_irq(&kvm->arch.tsc_write_lock); 2804 write_seqcount_begin(&kvm->arch.pvclock_sc); 2805 } 2806 2807 static void kvm_start_pvclock_update(struct kvm *kvm) 2808 { 2809 kvm_make_mclock_inprogress_request(kvm); 2810 2811 /* no guest entries from this point */ 2812 __kvm_start_pvclock_update(kvm); 2813 } 2814 2815 static void kvm_end_pvclock_update(struct kvm *kvm) 2816 { 2817 struct kvm_arch *ka = &kvm->arch; 2818 struct kvm_vcpu *vcpu; 2819 int i; 2820 2821 write_seqcount_end(&ka->pvclock_sc); 2822 raw_spin_unlock_irq(&ka->tsc_write_lock); 2823 kvm_for_each_vcpu(i, vcpu, kvm) 2824 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2825 2826 /* guest entries allowed */ 2827 kvm_for_each_vcpu(i, vcpu, kvm) 2828 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2829 } 2830 2831 static void kvm_update_masterclock(struct kvm *kvm) 2832 { 2833 kvm_hv_invalidate_tsc_page(kvm); 2834 kvm_start_pvclock_update(kvm); 2835 pvclock_update_vm_gtod_copy(kvm); 2836 kvm_end_pvclock_update(kvm); 2837 } 2838 2839 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */ 2840 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) 2841 { 2842 struct kvm_arch *ka = &kvm->arch; 2843 struct pvclock_vcpu_time_info hv_clock; 2844 2845 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2846 get_cpu(); 2847 2848 data->flags = 0; 2849 if (ka->use_master_clock && __this_cpu_read(cpu_tsc_khz)) { 2850 #ifdef CONFIG_X86_64 2851 struct timespec64 ts; 2852 2853 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) { 2854 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec; 2855 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC; 2856 } else 2857 #endif 2858 data->host_tsc = rdtsc(); 2859 2860 data->flags |= KVM_CLOCK_TSC_STABLE; 2861 hv_clock.tsc_timestamp = ka->master_cycle_now; 2862 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2863 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2864 &hv_clock.tsc_shift, 2865 &hv_clock.tsc_to_system_mul); 2866 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc); 2867 } else { 2868 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset; 2869 } 2870 2871 put_cpu(); 2872 } 2873 2874 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) 2875 { 2876 struct kvm_arch *ka = &kvm->arch; 2877 unsigned seq; 2878 2879 do { 2880 seq = read_seqcount_begin(&ka->pvclock_sc); 2881 __get_kvmclock(kvm, data); 2882 } while (read_seqcount_retry(&ka->pvclock_sc, seq)); 2883 } 2884 2885 u64 get_kvmclock_ns(struct kvm *kvm) 2886 { 2887 struct kvm_clock_data data; 2888 2889 get_kvmclock(kvm, &data); 2890 return data.clock; 2891 } 2892 2893 static void kvm_setup_pvclock_page(struct kvm_vcpu *v, 2894 struct gfn_to_hva_cache *cache, 2895 unsigned int offset) 2896 { 2897 struct kvm_vcpu_arch *vcpu = &v->arch; 2898 struct pvclock_vcpu_time_info guest_hv_clock; 2899 2900 if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache, 2901 &guest_hv_clock, offset, sizeof(guest_hv_clock)))) 2902 return; 2903 2904 /* This VCPU is paused, but it's legal for a guest to read another 2905 * VCPU's kvmclock, so we really have to follow the specification where 2906 * it says that version is odd if data is being modified, and even after 2907 * it is consistent. 2908 * 2909 * Version field updates must be kept separate. This is because 2910 * kvm_write_guest_cached might use a "rep movs" instruction, and 2911 * writes within a string instruction are weakly ordered. So there 2912 * are three writes overall. 2913 * 2914 * As a small optimization, only write the version field in the first 2915 * and third write. The vcpu->pv_time cache is still valid, because the 2916 * version field is the first in the struct. 2917 */ 2918 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 2919 2920 if (guest_hv_clock.version & 1) 2921 ++guest_hv_clock.version; /* first time write, random junk */ 2922 2923 vcpu->hv_clock.version = guest_hv_clock.version + 1; 2924 kvm_write_guest_offset_cached(v->kvm, cache, 2925 &vcpu->hv_clock, offset, 2926 sizeof(vcpu->hv_clock.version)); 2927 2928 smp_wmb(); 2929 2930 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 2931 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 2932 2933 if (vcpu->pvclock_set_guest_stopped_request) { 2934 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 2935 vcpu->pvclock_set_guest_stopped_request = false; 2936 } 2937 2938 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 2939 2940 kvm_write_guest_offset_cached(v->kvm, cache, 2941 &vcpu->hv_clock, offset, 2942 sizeof(vcpu->hv_clock)); 2943 2944 smp_wmb(); 2945 2946 vcpu->hv_clock.version++; 2947 kvm_write_guest_offset_cached(v->kvm, cache, 2948 &vcpu->hv_clock, offset, 2949 sizeof(vcpu->hv_clock.version)); 2950 } 2951 2952 static int kvm_guest_time_update(struct kvm_vcpu *v) 2953 { 2954 unsigned long flags, tgt_tsc_khz; 2955 unsigned seq; 2956 struct kvm_vcpu_arch *vcpu = &v->arch; 2957 struct kvm_arch *ka = &v->kvm->arch; 2958 s64 kernel_ns; 2959 u64 tsc_timestamp, host_tsc; 2960 u8 pvclock_flags; 2961 bool use_master_clock; 2962 2963 kernel_ns = 0; 2964 host_tsc = 0; 2965 2966 /* 2967 * If the host uses TSC clock, then passthrough TSC as stable 2968 * to the guest. 2969 */ 2970 do { 2971 seq = read_seqcount_begin(&ka->pvclock_sc); 2972 use_master_clock = ka->use_master_clock; 2973 if (use_master_clock) { 2974 host_tsc = ka->master_cycle_now; 2975 kernel_ns = ka->master_kernel_ns; 2976 } 2977 } while (read_seqcount_retry(&ka->pvclock_sc, seq)); 2978 2979 /* Keep irq disabled to prevent changes to the clock */ 2980 local_irq_save(flags); 2981 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 2982 if (unlikely(tgt_tsc_khz == 0)) { 2983 local_irq_restore(flags); 2984 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2985 return 1; 2986 } 2987 if (!use_master_clock) { 2988 host_tsc = rdtsc(); 2989 kernel_ns = get_kvmclock_base_ns(); 2990 } 2991 2992 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 2993 2994 /* 2995 * We may have to catch up the TSC to match elapsed wall clock 2996 * time for two reasons, even if kvmclock is used. 2997 * 1) CPU could have been running below the maximum TSC rate 2998 * 2) Broken TSC compensation resets the base at each VCPU 2999 * entry to avoid unknown leaps of TSC even when running 3000 * again on the same CPU. This may cause apparent elapsed 3001 * time to disappear, and the guest to stand still or run 3002 * very slowly. 3003 */ 3004 if (vcpu->tsc_catchup) { 3005 u64 tsc = compute_guest_tsc(v, kernel_ns); 3006 if (tsc > tsc_timestamp) { 3007 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 3008 tsc_timestamp = tsc; 3009 } 3010 } 3011 3012 local_irq_restore(flags); 3013 3014 /* With all the info we got, fill in the values */ 3015 3016 if (kvm_has_tsc_control) 3017 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz, 3018 v->arch.l1_tsc_scaling_ratio); 3019 3020 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 3021 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 3022 &vcpu->hv_clock.tsc_shift, 3023 &vcpu->hv_clock.tsc_to_system_mul); 3024 vcpu->hw_tsc_khz = tgt_tsc_khz; 3025 } 3026 3027 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 3028 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 3029 vcpu->last_guest_tsc = tsc_timestamp; 3030 3031 /* If the host uses TSC clocksource, then it is stable */ 3032 pvclock_flags = 0; 3033 if (use_master_clock) 3034 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 3035 3036 vcpu->hv_clock.flags = pvclock_flags; 3037 3038 if (vcpu->pv_time_enabled) 3039 kvm_setup_pvclock_page(v, &vcpu->pv_time, 0); 3040 if (vcpu->xen.vcpu_info_set) 3041 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache, 3042 offsetof(struct compat_vcpu_info, time)); 3043 if (vcpu->xen.vcpu_time_info_set) 3044 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0); 3045 if (!v->vcpu_idx) 3046 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 3047 return 0; 3048 } 3049 3050 /* 3051 * kvmclock updates which are isolated to a given vcpu, such as 3052 * vcpu->cpu migration, should not allow system_timestamp from 3053 * the rest of the vcpus to remain static. Otherwise ntp frequency 3054 * correction applies to one vcpu's system_timestamp but not 3055 * the others. 3056 * 3057 * So in those cases, request a kvmclock update for all vcpus. 3058 * We need to rate-limit these requests though, as they can 3059 * considerably slow guests that have a large number of vcpus. 3060 * The time for a remote vcpu to update its kvmclock is bound 3061 * by the delay we use to rate-limit the updates. 3062 */ 3063 3064 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 3065 3066 static void kvmclock_update_fn(struct work_struct *work) 3067 { 3068 int i; 3069 struct delayed_work *dwork = to_delayed_work(work); 3070 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3071 kvmclock_update_work); 3072 struct kvm *kvm = container_of(ka, struct kvm, arch); 3073 struct kvm_vcpu *vcpu; 3074 3075 kvm_for_each_vcpu(i, vcpu, kvm) { 3076 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3077 kvm_vcpu_kick(vcpu); 3078 } 3079 } 3080 3081 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 3082 { 3083 struct kvm *kvm = v->kvm; 3084 3085 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 3086 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 3087 KVMCLOCK_UPDATE_DELAY); 3088 } 3089 3090 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 3091 3092 static void kvmclock_sync_fn(struct work_struct *work) 3093 { 3094 struct delayed_work *dwork = to_delayed_work(work); 3095 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3096 kvmclock_sync_work); 3097 struct kvm *kvm = container_of(ka, struct kvm, arch); 3098 3099 if (!kvmclock_periodic_sync) 3100 return; 3101 3102 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 3103 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 3104 KVMCLOCK_SYNC_PERIOD); 3105 } 3106 3107 /* 3108 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 3109 */ 3110 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 3111 { 3112 /* McStatusWrEn enabled? */ 3113 if (guest_cpuid_is_amd_or_hygon(vcpu)) 3114 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 3115 3116 return false; 3117 } 3118 3119 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3120 { 3121 u64 mcg_cap = vcpu->arch.mcg_cap; 3122 unsigned bank_num = mcg_cap & 0xff; 3123 u32 msr = msr_info->index; 3124 u64 data = msr_info->data; 3125 3126 switch (msr) { 3127 case MSR_IA32_MCG_STATUS: 3128 vcpu->arch.mcg_status = data; 3129 break; 3130 case MSR_IA32_MCG_CTL: 3131 if (!(mcg_cap & MCG_CTL_P) && 3132 (data || !msr_info->host_initiated)) 3133 return 1; 3134 if (data != 0 && data != ~(u64)0) 3135 return 1; 3136 vcpu->arch.mcg_ctl = data; 3137 break; 3138 default: 3139 if (msr >= MSR_IA32_MC0_CTL && 3140 msr < MSR_IA32_MCx_CTL(bank_num)) { 3141 u32 offset = array_index_nospec( 3142 msr - MSR_IA32_MC0_CTL, 3143 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3144 3145 /* only 0 or all 1s can be written to IA32_MCi_CTL 3146 * some Linux kernels though clear bit 10 in bank 4 to 3147 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 3148 * this to avoid an uncatched #GP in the guest 3149 */ 3150 if ((offset & 0x3) == 0 && 3151 data != 0 && (data | (1 << 10)) != ~(u64)0) 3152 return -1; 3153 3154 /* MCi_STATUS */ 3155 if (!msr_info->host_initiated && 3156 (offset & 0x3) == 1 && data != 0) { 3157 if (!can_set_mci_status(vcpu)) 3158 return -1; 3159 } 3160 3161 vcpu->arch.mce_banks[offset] = data; 3162 break; 3163 } 3164 return 1; 3165 } 3166 return 0; 3167 } 3168 3169 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) 3170 { 3171 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; 3172 3173 return (vcpu->arch.apf.msr_en_val & mask) == mask; 3174 } 3175 3176 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 3177 { 3178 gpa_t gpa = data & ~0x3f; 3179 3180 /* Bits 4:5 are reserved, Should be zero */ 3181 if (data & 0x30) 3182 return 1; 3183 3184 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && 3185 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) 3186 return 1; 3187 3188 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && 3189 (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) 3190 return 1; 3191 3192 if (!lapic_in_kernel(vcpu)) 3193 return data ? 1 : 0; 3194 3195 vcpu->arch.apf.msr_en_val = data; 3196 3197 if (!kvm_pv_async_pf_enabled(vcpu)) { 3198 kvm_clear_async_pf_completion_queue(vcpu); 3199 kvm_async_pf_hash_reset(vcpu); 3200 return 0; 3201 } 3202 3203 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 3204 sizeof(u64))) 3205 return 1; 3206 3207 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 3208 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 3209 3210 kvm_async_pf_wakeup_all(vcpu); 3211 3212 return 0; 3213 } 3214 3215 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) 3216 { 3217 /* Bits 8-63 are reserved */ 3218 if (data >> 8) 3219 return 1; 3220 3221 if (!lapic_in_kernel(vcpu)) 3222 return 1; 3223 3224 vcpu->arch.apf.msr_int_val = data; 3225 3226 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; 3227 3228 return 0; 3229 } 3230 3231 static void kvmclock_reset(struct kvm_vcpu *vcpu) 3232 { 3233 vcpu->arch.pv_time_enabled = false; 3234 vcpu->arch.time = 0; 3235 } 3236 3237 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) 3238 { 3239 ++vcpu->stat.tlb_flush; 3240 static_call(kvm_x86_tlb_flush_all)(vcpu); 3241 } 3242 3243 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) 3244 { 3245 ++vcpu->stat.tlb_flush; 3246 3247 if (!tdp_enabled) { 3248 /* 3249 * A TLB flush on behalf of the guest is equivalent to 3250 * INVPCID(all), toggling CR4.PGE, etc., which requires 3251 * a forced sync of the shadow page tables. Ensure all the 3252 * roots are synced and the guest TLB in hardware is clean. 3253 */ 3254 kvm_mmu_sync_roots(vcpu); 3255 kvm_mmu_sync_prev_roots(vcpu); 3256 } 3257 3258 static_call(kvm_x86_tlb_flush_guest)(vcpu); 3259 } 3260 3261 static void record_steal_time(struct kvm_vcpu *vcpu) 3262 { 3263 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; 3264 struct kvm_steal_time __user *st; 3265 struct kvm_memslots *slots; 3266 u64 steal; 3267 u32 version; 3268 3269 if (kvm_xen_msr_enabled(vcpu->kvm)) { 3270 kvm_xen_runstate_set_running(vcpu); 3271 return; 3272 } 3273 3274 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3275 return; 3276 3277 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm)) 3278 return; 3279 3280 slots = kvm_memslots(vcpu->kvm); 3281 3282 if (unlikely(slots->generation != ghc->generation || 3283 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) { 3284 gfn_t gfn = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; 3285 3286 /* We rely on the fact that it fits in a single page. */ 3287 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS); 3288 3289 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gfn, sizeof(*st)) || 3290 kvm_is_error_hva(ghc->hva) || !ghc->memslot) 3291 return; 3292 } 3293 3294 st = (struct kvm_steal_time __user *)ghc->hva; 3295 /* 3296 * Doing a TLB flush here, on the guest's behalf, can avoid 3297 * expensive IPIs. 3298 */ 3299 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { 3300 u8 st_preempted = 0; 3301 int err = -EFAULT; 3302 3303 if (!user_access_begin(st, sizeof(*st))) 3304 return; 3305 3306 asm volatile("1: xchgb %0, %2\n" 3307 "xor %1, %1\n" 3308 "2:\n" 3309 _ASM_EXTABLE_UA(1b, 2b) 3310 : "+r" (st_preempted), 3311 "+&r" (err) 3312 : "m" (st->preempted)); 3313 if (err) 3314 goto out; 3315 3316 user_access_end(); 3317 3318 vcpu->arch.st.preempted = 0; 3319 3320 trace_kvm_pv_tlb_flush(vcpu->vcpu_id, 3321 st_preempted & KVM_VCPU_FLUSH_TLB); 3322 if (st_preempted & KVM_VCPU_FLUSH_TLB) 3323 kvm_vcpu_flush_tlb_guest(vcpu); 3324 3325 if (!user_access_begin(st, sizeof(*st))) 3326 goto dirty; 3327 } else { 3328 if (!user_access_begin(st, sizeof(*st))) 3329 return; 3330 3331 unsafe_put_user(0, &st->preempted, out); 3332 vcpu->arch.st.preempted = 0; 3333 } 3334 3335 unsafe_get_user(version, &st->version, out); 3336 if (version & 1) 3337 version += 1; /* first time write, random junk */ 3338 3339 version += 1; 3340 unsafe_put_user(version, &st->version, out); 3341 3342 smp_wmb(); 3343 3344 unsafe_get_user(steal, &st->steal, out); 3345 steal += current->sched_info.run_delay - 3346 vcpu->arch.st.last_steal; 3347 vcpu->arch.st.last_steal = current->sched_info.run_delay; 3348 unsafe_put_user(steal, &st->steal, out); 3349 3350 version += 1; 3351 unsafe_put_user(version, &st->version, out); 3352 3353 out: 3354 user_access_end(); 3355 dirty: 3356 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 3357 } 3358 3359 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3360 { 3361 bool pr = false; 3362 u32 msr = msr_info->index; 3363 u64 data = msr_info->data; 3364 3365 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) 3366 return kvm_xen_write_hypercall_page(vcpu, data); 3367 3368 switch (msr) { 3369 case MSR_AMD64_NB_CFG: 3370 case MSR_IA32_UCODE_WRITE: 3371 case MSR_VM_HSAVE_PA: 3372 case MSR_AMD64_PATCH_LOADER: 3373 case MSR_AMD64_BU_CFG2: 3374 case MSR_AMD64_DC_CFG: 3375 case MSR_F15H_EX_CFG: 3376 break; 3377 3378 case MSR_IA32_UCODE_REV: 3379 if (msr_info->host_initiated) 3380 vcpu->arch.microcode_version = data; 3381 break; 3382 case MSR_IA32_ARCH_CAPABILITIES: 3383 if (!msr_info->host_initiated) 3384 return 1; 3385 vcpu->arch.arch_capabilities = data; 3386 break; 3387 case MSR_IA32_PERF_CAPABILITIES: { 3388 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; 3389 3390 if (!msr_info->host_initiated) 3391 return 1; 3392 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent)) 3393 return 1; 3394 if (data & ~msr_ent.data) 3395 return 1; 3396 3397 vcpu->arch.perf_capabilities = data; 3398 3399 return 0; 3400 } 3401 case MSR_EFER: 3402 return set_efer(vcpu, msr_info); 3403 case MSR_K7_HWCR: 3404 data &= ~(u64)0x40; /* ignore flush filter disable */ 3405 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 3406 data &= ~(u64)0x8; /* ignore TLB cache disable */ 3407 3408 /* Handle McStatusWrEn */ 3409 if (data == BIT_ULL(18)) { 3410 vcpu->arch.msr_hwcr = data; 3411 } else if (data != 0) { 3412 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 3413 data); 3414 return 1; 3415 } 3416 break; 3417 case MSR_FAM10H_MMIO_CONF_BASE: 3418 if (data != 0) { 3419 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 3420 "0x%llx\n", data); 3421 return 1; 3422 } 3423 break; 3424 case 0x200 ... 0x2ff: 3425 return kvm_mtrr_set_msr(vcpu, msr, data); 3426 case MSR_IA32_APICBASE: 3427 return kvm_set_apic_base(vcpu, msr_info); 3428 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3429 return kvm_x2apic_msr_write(vcpu, msr, data); 3430 case MSR_IA32_TSC_DEADLINE: 3431 kvm_set_lapic_tscdeadline_msr(vcpu, data); 3432 break; 3433 case MSR_IA32_TSC_ADJUST: 3434 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 3435 if (!msr_info->host_initiated) { 3436 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 3437 adjust_tsc_offset_guest(vcpu, adj); 3438 /* Before back to guest, tsc_timestamp must be adjusted 3439 * as well, otherwise guest's percpu pvclock time could jump. 3440 */ 3441 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3442 } 3443 vcpu->arch.ia32_tsc_adjust_msr = data; 3444 } 3445 break; 3446 case MSR_IA32_MISC_ENABLE: 3447 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && 3448 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { 3449 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) 3450 return 1; 3451 vcpu->arch.ia32_misc_enable_msr = data; 3452 kvm_update_cpuid_runtime(vcpu); 3453 } else { 3454 vcpu->arch.ia32_misc_enable_msr = data; 3455 } 3456 break; 3457 case MSR_IA32_SMBASE: 3458 if (!msr_info->host_initiated) 3459 return 1; 3460 vcpu->arch.smbase = data; 3461 break; 3462 case MSR_IA32_POWER_CTL: 3463 vcpu->arch.msr_ia32_power_ctl = data; 3464 break; 3465 case MSR_IA32_TSC: 3466 if (msr_info->host_initiated) { 3467 kvm_synchronize_tsc(vcpu, data); 3468 } else { 3469 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; 3470 adjust_tsc_offset_guest(vcpu, adj); 3471 vcpu->arch.ia32_tsc_adjust_msr += adj; 3472 } 3473 break; 3474 case MSR_IA32_XSS: 3475 if (!msr_info->host_initiated && 3476 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3477 return 1; 3478 /* 3479 * KVM supports exposing PT to the guest, but does not support 3480 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than 3481 * XSAVES/XRSTORS to save/restore PT MSRs. 3482 */ 3483 if (data & ~supported_xss) 3484 return 1; 3485 vcpu->arch.ia32_xss = data; 3486 break; 3487 case MSR_SMI_COUNT: 3488 if (!msr_info->host_initiated) 3489 return 1; 3490 vcpu->arch.smi_count = data; 3491 break; 3492 case MSR_KVM_WALL_CLOCK_NEW: 3493 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3494 return 1; 3495 3496 vcpu->kvm->arch.wall_clock = data; 3497 kvm_write_wall_clock(vcpu->kvm, data, 0); 3498 break; 3499 case MSR_KVM_WALL_CLOCK: 3500 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3501 return 1; 3502 3503 vcpu->kvm->arch.wall_clock = data; 3504 kvm_write_wall_clock(vcpu->kvm, data, 0); 3505 break; 3506 case MSR_KVM_SYSTEM_TIME_NEW: 3507 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3508 return 1; 3509 3510 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); 3511 break; 3512 case MSR_KVM_SYSTEM_TIME: 3513 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3514 return 1; 3515 3516 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); 3517 break; 3518 case MSR_KVM_ASYNC_PF_EN: 3519 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3520 return 1; 3521 3522 if (kvm_pv_enable_async_pf(vcpu, data)) 3523 return 1; 3524 break; 3525 case MSR_KVM_ASYNC_PF_INT: 3526 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3527 return 1; 3528 3529 if (kvm_pv_enable_async_pf_int(vcpu, data)) 3530 return 1; 3531 break; 3532 case MSR_KVM_ASYNC_PF_ACK: 3533 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3534 return 1; 3535 if (data & 0x1) { 3536 vcpu->arch.apf.pageready_pending = false; 3537 kvm_check_async_pf_completion(vcpu); 3538 } 3539 break; 3540 case MSR_KVM_STEAL_TIME: 3541 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3542 return 1; 3543 3544 if (unlikely(!sched_info_on())) 3545 return 1; 3546 3547 if (data & KVM_STEAL_RESERVED_MASK) 3548 return 1; 3549 3550 vcpu->arch.st.msr_val = data; 3551 3552 if (!(data & KVM_MSR_ENABLED)) 3553 break; 3554 3555 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3556 3557 break; 3558 case MSR_KVM_PV_EOI_EN: 3559 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3560 return 1; 3561 3562 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8))) 3563 return 1; 3564 break; 3565 3566 case MSR_KVM_POLL_CONTROL: 3567 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3568 return 1; 3569 3570 /* only enable bit supported */ 3571 if (data & (-1ULL << 1)) 3572 return 1; 3573 3574 vcpu->arch.msr_kvm_poll_control = data; 3575 break; 3576 3577 case MSR_IA32_MCG_CTL: 3578 case MSR_IA32_MCG_STATUS: 3579 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3580 return set_msr_mce(vcpu, msr_info); 3581 3582 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3583 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3584 pr = true; 3585 fallthrough; 3586 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3587 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3588 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3589 return kvm_pmu_set_msr(vcpu, msr_info); 3590 3591 if (pr || data != 0) 3592 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 3593 "0x%x data 0x%llx\n", msr, data); 3594 break; 3595 case MSR_K7_CLK_CTL: 3596 /* 3597 * Ignore all writes to this no longer documented MSR. 3598 * Writes are only relevant for old K7 processors, 3599 * all pre-dating SVM, but a recommended workaround from 3600 * AMD for these chips. It is possible to specify the 3601 * affected processor models on the command line, hence 3602 * the need to ignore the workaround. 3603 */ 3604 break; 3605 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3606 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3607 case HV_X64_MSR_SYNDBG_OPTIONS: 3608 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3609 case HV_X64_MSR_CRASH_CTL: 3610 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3611 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3612 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3613 case HV_X64_MSR_TSC_EMULATION_STATUS: 3614 return kvm_hv_set_msr_common(vcpu, msr, data, 3615 msr_info->host_initiated); 3616 case MSR_IA32_BBL_CR_CTL3: 3617 /* Drop writes to this legacy MSR -- see rdmsr 3618 * counterpart for further detail. 3619 */ 3620 if (report_ignored_msrs) 3621 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 3622 msr, data); 3623 break; 3624 case MSR_AMD64_OSVW_ID_LENGTH: 3625 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3626 return 1; 3627 vcpu->arch.osvw.length = data; 3628 break; 3629 case MSR_AMD64_OSVW_STATUS: 3630 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3631 return 1; 3632 vcpu->arch.osvw.status = data; 3633 break; 3634 case MSR_PLATFORM_INFO: 3635 if (!msr_info->host_initiated || 3636 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 3637 cpuid_fault_enabled(vcpu))) 3638 return 1; 3639 vcpu->arch.msr_platform_info = data; 3640 break; 3641 case MSR_MISC_FEATURES_ENABLES: 3642 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 3643 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3644 !supports_cpuid_fault(vcpu))) 3645 return 1; 3646 vcpu->arch.msr_misc_features_enables = data; 3647 break; 3648 default: 3649 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3650 return kvm_pmu_set_msr(vcpu, msr_info); 3651 return KVM_MSR_RET_INVALID; 3652 } 3653 return 0; 3654 } 3655 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 3656 3657 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 3658 { 3659 u64 data; 3660 u64 mcg_cap = vcpu->arch.mcg_cap; 3661 unsigned bank_num = mcg_cap & 0xff; 3662 3663 switch (msr) { 3664 case MSR_IA32_P5_MC_ADDR: 3665 case MSR_IA32_P5_MC_TYPE: 3666 data = 0; 3667 break; 3668 case MSR_IA32_MCG_CAP: 3669 data = vcpu->arch.mcg_cap; 3670 break; 3671 case MSR_IA32_MCG_CTL: 3672 if (!(mcg_cap & MCG_CTL_P) && !host) 3673 return 1; 3674 data = vcpu->arch.mcg_ctl; 3675 break; 3676 case MSR_IA32_MCG_STATUS: 3677 data = vcpu->arch.mcg_status; 3678 break; 3679 default: 3680 if (msr >= MSR_IA32_MC0_CTL && 3681 msr < MSR_IA32_MCx_CTL(bank_num)) { 3682 u32 offset = array_index_nospec( 3683 msr - MSR_IA32_MC0_CTL, 3684 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3685 3686 data = vcpu->arch.mce_banks[offset]; 3687 break; 3688 } 3689 return 1; 3690 } 3691 *pdata = data; 3692 return 0; 3693 } 3694 3695 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3696 { 3697 switch (msr_info->index) { 3698 case MSR_IA32_PLATFORM_ID: 3699 case MSR_IA32_EBL_CR_POWERON: 3700 case MSR_IA32_LASTBRANCHFROMIP: 3701 case MSR_IA32_LASTBRANCHTOIP: 3702 case MSR_IA32_LASTINTFROMIP: 3703 case MSR_IA32_LASTINTTOIP: 3704 case MSR_AMD64_SYSCFG: 3705 case MSR_K8_TSEG_ADDR: 3706 case MSR_K8_TSEG_MASK: 3707 case MSR_VM_HSAVE_PA: 3708 case MSR_K8_INT_PENDING_MSG: 3709 case MSR_AMD64_NB_CFG: 3710 case MSR_FAM10H_MMIO_CONF_BASE: 3711 case MSR_AMD64_BU_CFG2: 3712 case MSR_IA32_PERF_CTL: 3713 case MSR_AMD64_DC_CFG: 3714 case MSR_F15H_EX_CFG: 3715 /* 3716 * Intel Sandy Bridge CPUs must support the RAPL (running average power 3717 * limit) MSRs. Just return 0, as we do not want to expose the host 3718 * data here. Do not conditionalize this on CPUID, as KVM does not do 3719 * so for existing CPU-specific MSRs. 3720 */ 3721 case MSR_RAPL_POWER_UNIT: 3722 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ 3723 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ 3724 case MSR_PKG_ENERGY_STATUS: /* Total package */ 3725 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ 3726 msr_info->data = 0; 3727 break; 3728 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3729 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3730 return kvm_pmu_get_msr(vcpu, msr_info); 3731 if (!msr_info->host_initiated) 3732 return 1; 3733 msr_info->data = 0; 3734 break; 3735 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3736 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3737 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3738 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3739 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3740 return kvm_pmu_get_msr(vcpu, msr_info); 3741 msr_info->data = 0; 3742 break; 3743 case MSR_IA32_UCODE_REV: 3744 msr_info->data = vcpu->arch.microcode_version; 3745 break; 3746 case MSR_IA32_ARCH_CAPABILITIES: 3747 if (!msr_info->host_initiated && 3748 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 3749 return 1; 3750 msr_info->data = vcpu->arch.arch_capabilities; 3751 break; 3752 case MSR_IA32_PERF_CAPABILITIES: 3753 if (!msr_info->host_initiated && 3754 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) 3755 return 1; 3756 msr_info->data = vcpu->arch.perf_capabilities; 3757 break; 3758 case MSR_IA32_POWER_CTL: 3759 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 3760 break; 3761 case MSR_IA32_TSC: { 3762 /* 3763 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset 3764 * even when not intercepted. AMD manual doesn't explicitly 3765 * state this but appears to behave the same. 3766 * 3767 * On userspace reads and writes, however, we unconditionally 3768 * return L1's TSC value to ensure backwards-compatible 3769 * behavior for migration. 3770 */ 3771 u64 offset, ratio; 3772 3773 if (msr_info->host_initiated) { 3774 offset = vcpu->arch.l1_tsc_offset; 3775 ratio = vcpu->arch.l1_tsc_scaling_ratio; 3776 } else { 3777 offset = vcpu->arch.tsc_offset; 3778 ratio = vcpu->arch.tsc_scaling_ratio; 3779 } 3780 3781 msr_info->data = kvm_scale_tsc(vcpu, rdtsc(), ratio) + offset; 3782 break; 3783 } 3784 case MSR_MTRRcap: 3785 case 0x200 ... 0x2ff: 3786 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 3787 case 0xcd: /* fsb frequency */ 3788 msr_info->data = 3; 3789 break; 3790 /* 3791 * MSR_EBC_FREQUENCY_ID 3792 * Conservative value valid for even the basic CPU models. 3793 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 3794 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 3795 * and 266MHz for model 3, or 4. Set Core Clock 3796 * Frequency to System Bus Frequency Ratio to 1 (bits 3797 * 31:24) even though these are only valid for CPU 3798 * models > 2, however guests may end up dividing or 3799 * multiplying by zero otherwise. 3800 */ 3801 case MSR_EBC_FREQUENCY_ID: 3802 msr_info->data = 1 << 24; 3803 break; 3804 case MSR_IA32_APICBASE: 3805 msr_info->data = kvm_get_apic_base(vcpu); 3806 break; 3807 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3808 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 3809 case MSR_IA32_TSC_DEADLINE: 3810 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 3811 break; 3812 case MSR_IA32_TSC_ADJUST: 3813 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 3814 break; 3815 case MSR_IA32_MISC_ENABLE: 3816 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 3817 break; 3818 case MSR_IA32_SMBASE: 3819 if (!msr_info->host_initiated) 3820 return 1; 3821 msr_info->data = vcpu->arch.smbase; 3822 break; 3823 case MSR_SMI_COUNT: 3824 msr_info->data = vcpu->arch.smi_count; 3825 break; 3826 case MSR_IA32_PERF_STATUS: 3827 /* TSC increment by tick */ 3828 msr_info->data = 1000ULL; 3829 /* CPU multiplier */ 3830 msr_info->data |= (((uint64_t)4ULL) << 40); 3831 break; 3832 case MSR_EFER: 3833 msr_info->data = vcpu->arch.efer; 3834 break; 3835 case MSR_KVM_WALL_CLOCK: 3836 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3837 return 1; 3838 3839 msr_info->data = vcpu->kvm->arch.wall_clock; 3840 break; 3841 case MSR_KVM_WALL_CLOCK_NEW: 3842 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3843 return 1; 3844 3845 msr_info->data = vcpu->kvm->arch.wall_clock; 3846 break; 3847 case MSR_KVM_SYSTEM_TIME: 3848 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3849 return 1; 3850 3851 msr_info->data = vcpu->arch.time; 3852 break; 3853 case MSR_KVM_SYSTEM_TIME_NEW: 3854 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3855 return 1; 3856 3857 msr_info->data = vcpu->arch.time; 3858 break; 3859 case MSR_KVM_ASYNC_PF_EN: 3860 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3861 return 1; 3862 3863 msr_info->data = vcpu->arch.apf.msr_en_val; 3864 break; 3865 case MSR_KVM_ASYNC_PF_INT: 3866 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3867 return 1; 3868 3869 msr_info->data = vcpu->arch.apf.msr_int_val; 3870 break; 3871 case MSR_KVM_ASYNC_PF_ACK: 3872 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3873 return 1; 3874 3875 msr_info->data = 0; 3876 break; 3877 case MSR_KVM_STEAL_TIME: 3878 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3879 return 1; 3880 3881 msr_info->data = vcpu->arch.st.msr_val; 3882 break; 3883 case MSR_KVM_PV_EOI_EN: 3884 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3885 return 1; 3886 3887 msr_info->data = vcpu->arch.pv_eoi.msr_val; 3888 break; 3889 case MSR_KVM_POLL_CONTROL: 3890 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3891 return 1; 3892 3893 msr_info->data = vcpu->arch.msr_kvm_poll_control; 3894 break; 3895 case MSR_IA32_P5_MC_ADDR: 3896 case MSR_IA32_P5_MC_TYPE: 3897 case MSR_IA32_MCG_CAP: 3898 case MSR_IA32_MCG_CTL: 3899 case MSR_IA32_MCG_STATUS: 3900 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3901 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 3902 msr_info->host_initiated); 3903 case MSR_IA32_XSS: 3904 if (!msr_info->host_initiated && 3905 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3906 return 1; 3907 msr_info->data = vcpu->arch.ia32_xss; 3908 break; 3909 case MSR_K7_CLK_CTL: 3910 /* 3911 * Provide expected ramp-up count for K7. All other 3912 * are set to zero, indicating minimum divisors for 3913 * every field. 3914 * 3915 * This prevents guest kernels on AMD host with CPU 3916 * type 6, model 8 and higher from exploding due to 3917 * the rdmsr failing. 3918 */ 3919 msr_info->data = 0x20000000; 3920 break; 3921 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3922 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3923 case HV_X64_MSR_SYNDBG_OPTIONS: 3924 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3925 case HV_X64_MSR_CRASH_CTL: 3926 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3927 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3928 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3929 case HV_X64_MSR_TSC_EMULATION_STATUS: 3930 return kvm_hv_get_msr_common(vcpu, 3931 msr_info->index, &msr_info->data, 3932 msr_info->host_initiated); 3933 case MSR_IA32_BBL_CR_CTL3: 3934 /* This legacy MSR exists but isn't fully documented in current 3935 * silicon. It is however accessed by winxp in very narrow 3936 * scenarios where it sets bit #19, itself documented as 3937 * a "reserved" bit. Best effort attempt to source coherent 3938 * read data here should the balance of the register be 3939 * interpreted by the guest: 3940 * 3941 * L2 cache control register 3: 64GB range, 256KB size, 3942 * enabled, latency 0x1, configured 3943 */ 3944 msr_info->data = 0xbe702111; 3945 break; 3946 case MSR_AMD64_OSVW_ID_LENGTH: 3947 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3948 return 1; 3949 msr_info->data = vcpu->arch.osvw.length; 3950 break; 3951 case MSR_AMD64_OSVW_STATUS: 3952 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3953 return 1; 3954 msr_info->data = vcpu->arch.osvw.status; 3955 break; 3956 case MSR_PLATFORM_INFO: 3957 if (!msr_info->host_initiated && 3958 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 3959 return 1; 3960 msr_info->data = vcpu->arch.msr_platform_info; 3961 break; 3962 case MSR_MISC_FEATURES_ENABLES: 3963 msr_info->data = vcpu->arch.msr_misc_features_enables; 3964 break; 3965 case MSR_K7_HWCR: 3966 msr_info->data = vcpu->arch.msr_hwcr; 3967 break; 3968 default: 3969 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3970 return kvm_pmu_get_msr(vcpu, msr_info); 3971 return KVM_MSR_RET_INVALID; 3972 } 3973 return 0; 3974 } 3975 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 3976 3977 /* 3978 * Read or write a bunch of msrs. All parameters are kernel addresses. 3979 * 3980 * @return number of msrs set successfully. 3981 */ 3982 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 3983 struct kvm_msr_entry *entries, 3984 int (*do_msr)(struct kvm_vcpu *vcpu, 3985 unsigned index, u64 *data)) 3986 { 3987 int i; 3988 3989 for (i = 0; i < msrs->nmsrs; ++i) 3990 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 3991 break; 3992 3993 return i; 3994 } 3995 3996 /* 3997 * Read or write a bunch of msrs. Parameters are user addresses. 3998 * 3999 * @return number of msrs set successfully. 4000 */ 4001 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 4002 int (*do_msr)(struct kvm_vcpu *vcpu, 4003 unsigned index, u64 *data), 4004 int writeback) 4005 { 4006 struct kvm_msrs msrs; 4007 struct kvm_msr_entry *entries; 4008 int r, n; 4009 unsigned size; 4010 4011 r = -EFAULT; 4012 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 4013 goto out; 4014 4015 r = -E2BIG; 4016 if (msrs.nmsrs >= MAX_IO_MSRS) 4017 goto out; 4018 4019 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 4020 entries = memdup_user(user_msrs->entries, size); 4021 if (IS_ERR(entries)) { 4022 r = PTR_ERR(entries); 4023 goto out; 4024 } 4025 4026 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 4027 if (r < 0) 4028 goto out_free; 4029 4030 r = -EFAULT; 4031 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 4032 goto out_free; 4033 4034 r = n; 4035 4036 out_free: 4037 kfree(entries); 4038 out: 4039 return r; 4040 } 4041 4042 static inline bool kvm_can_mwait_in_guest(void) 4043 { 4044 return boot_cpu_has(X86_FEATURE_MWAIT) && 4045 !boot_cpu_has_bug(X86_BUG_MONITOR) && 4046 boot_cpu_has(X86_FEATURE_ARAT); 4047 } 4048 4049 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, 4050 struct kvm_cpuid2 __user *cpuid_arg) 4051 { 4052 struct kvm_cpuid2 cpuid; 4053 int r; 4054 4055 r = -EFAULT; 4056 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4057 return r; 4058 4059 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); 4060 if (r) 4061 return r; 4062 4063 r = -EFAULT; 4064 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4065 return r; 4066 4067 return 0; 4068 } 4069 4070 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 4071 { 4072 int r = 0; 4073 4074 switch (ext) { 4075 case KVM_CAP_IRQCHIP: 4076 case KVM_CAP_HLT: 4077 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 4078 case KVM_CAP_SET_TSS_ADDR: 4079 case KVM_CAP_EXT_CPUID: 4080 case KVM_CAP_EXT_EMUL_CPUID: 4081 case KVM_CAP_CLOCKSOURCE: 4082 case KVM_CAP_PIT: 4083 case KVM_CAP_NOP_IO_DELAY: 4084 case KVM_CAP_MP_STATE: 4085 case KVM_CAP_SYNC_MMU: 4086 case KVM_CAP_USER_NMI: 4087 case KVM_CAP_REINJECT_CONTROL: 4088 case KVM_CAP_IRQ_INJECT_STATUS: 4089 case KVM_CAP_IOEVENTFD: 4090 case KVM_CAP_IOEVENTFD_NO_LENGTH: 4091 case KVM_CAP_PIT2: 4092 case KVM_CAP_PIT_STATE2: 4093 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 4094 case KVM_CAP_VCPU_EVENTS: 4095 case KVM_CAP_HYPERV: 4096 case KVM_CAP_HYPERV_VAPIC: 4097 case KVM_CAP_HYPERV_SPIN: 4098 case KVM_CAP_HYPERV_SYNIC: 4099 case KVM_CAP_HYPERV_SYNIC2: 4100 case KVM_CAP_HYPERV_VP_INDEX: 4101 case KVM_CAP_HYPERV_EVENTFD: 4102 case KVM_CAP_HYPERV_TLBFLUSH: 4103 case KVM_CAP_HYPERV_SEND_IPI: 4104 case KVM_CAP_HYPERV_CPUID: 4105 case KVM_CAP_HYPERV_ENFORCE_CPUID: 4106 case KVM_CAP_SYS_HYPERV_CPUID: 4107 case KVM_CAP_PCI_SEGMENT: 4108 case KVM_CAP_DEBUGREGS: 4109 case KVM_CAP_X86_ROBUST_SINGLESTEP: 4110 case KVM_CAP_XSAVE: 4111 case KVM_CAP_ASYNC_PF: 4112 case KVM_CAP_ASYNC_PF_INT: 4113 case KVM_CAP_GET_TSC_KHZ: 4114 case KVM_CAP_KVMCLOCK_CTRL: 4115 case KVM_CAP_READONLY_MEM: 4116 case KVM_CAP_HYPERV_TIME: 4117 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 4118 case KVM_CAP_TSC_DEADLINE_TIMER: 4119 case KVM_CAP_DISABLE_QUIRKS: 4120 case KVM_CAP_SET_BOOT_CPU_ID: 4121 case KVM_CAP_SPLIT_IRQCHIP: 4122 case KVM_CAP_IMMEDIATE_EXIT: 4123 case KVM_CAP_PMU_EVENT_FILTER: 4124 case KVM_CAP_GET_MSR_FEATURES: 4125 case KVM_CAP_MSR_PLATFORM_INFO: 4126 case KVM_CAP_EXCEPTION_PAYLOAD: 4127 case KVM_CAP_SET_GUEST_DEBUG: 4128 case KVM_CAP_LAST_CPU: 4129 case KVM_CAP_X86_USER_SPACE_MSR: 4130 case KVM_CAP_X86_MSR_FILTER: 4131 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 4132 #ifdef CONFIG_X86_SGX_KVM 4133 case KVM_CAP_SGX_ATTRIBUTE: 4134 #endif 4135 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 4136 case KVM_CAP_SREGS2: 4137 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 4138 case KVM_CAP_VCPU_ATTRIBUTES: 4139 r = 1; 4140 break; 4141 case KVM_CAP_EXIT_HYPERCALL: 4142 r = KVM_EXIT_HYPERCALL_VALID_MASK; 4143 break; 4144 case KVM_CAP_SET_GUEST_DEBUG2: 4145 return KVM_GUESTDBG_VALID_MASK; 4146 #ifdef CONFIG_KVM_XEN 4147 case KVM_CAP_XEN_HVM: 4148 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | 4149 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | 4150 KVM_XEN_HVM_CONFIG_SHARED_INFO; 4151 if (sched_info_on()) 4152 r |= KVM_XEN_HVM_CONFIG_RUNSTATE; 4153 break; 4154 #endif 4155 case KVM_CAP_SYNC_REGS: 4156 r = KVM_SYNC_X86_VALID_FIELDS; 4157 break; 4158 case KVM_CAP_ADJUST_CLOCK: 4159 r = KVM_CLOCK_VALID_FLAGS; 4160 break; 4161 case KVM_CAP_X86_DISABLE_EXITS: 4162 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | 4163 KVM_X86_DISABLE_EXITS_CSTATE; 4164 if(kvm_can_mwait_in_guest()) 4165 r |= KVM_X86_DISABLE_EXITS_MWAIT; 4166 break; 4167 case KVM_CAP_X86_SMM: 4168 /* SMBASE is usually relocated above 1M on modern chipsets, 4169 * and SMM handlers might indeed rely on 4G segment limits, 4170 * so do not report SMM to be available if real mode is 4171 * emulated via vm86 mode. Still, do not go to great lengths 4172 * to avoid userspace's usage of the feature, because it is a 4173 * fringe case that is not enabled except via specific settings 4174 * of the module parameters. 4175 */ 4176 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); 4177 break; 4178 case KVM_CAP_VAPIC: 4179 r = !static_call(kvm_x86_cpu_has_accelerated_tpr)(); 4180 break; 4181 case KVM_CAP_NR_VCPUS: 4182 r = num_online_cpus(); 4183 break; 4184 case KVM_CAP_MAX_VCPUS: 4185 r = KVM_MAX_VCPUS; 4186 break; 4187 case KVM_CAP_MAX_VCPU_ID: 4188 r = KVM_MAX_VCPU_IDS; 4189 break; 4190 case KVM_CAP_PV_MMU: /* obsolete */ 4191 r = 0; 4192 break; 4193 case KVM_CAP_MCE: 4194 r = KVM_MAX_MCE_BANKS; 4195 break; 4196 case KVM_CAP_XCRS: 4197 r = boot_cpu_has(X86_FEATURE_XSAVE); 4198 break; 4199 case KVM_CAP_TSC_CONTROL: 4200 r = kvm_has_tsc_control; 4201 break; 4202 case KVM_CAP_X2APIC_API: 4203 r = KVM_X2APIC_API_VALID_FLAGS; 4204 break; 4205 case KVM_CAP_NESTED_STATE: 4206 r = kvm_x86_ops.nested_ops->get_state ? 4207 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; 4208 break; 4209 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4210 r = kvm_x86_ops.enable_direct_tlbflush != NULL; 4211 break; 4212 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4213 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; 4214 break; 4215 case KVM_CAP_SMALLER_MAXPHYADDR: 4216 r = (int) allow_smaller_maxphyaddr; 4217 break; 4218 case KVM_CAP_STEAL_TIME: 4219 r = sched_info_on(); 4220 break; 4221 case KVM_CAP_X86_BUS_LOCK_EXIT: 4222 if (kvm_has_bus_lock_exit) 4223 r = KVM_BUS_LOCK_DETECTION_OFF | 4224 KVM_BUS_LOCK_DETECTION_EXIT; 4225 else 4226 r = 0; 4227 break; 4228 default: 4229 break; 4230 } 4231 return r; 4232 4233 } 4234 4235 long kvm_arch_dev_ioctl(struct file *filp, 4236 unsigned int ioctl, unsigned long arg) 4237 { 4238 void __user *argp = (void __user *)arg; 4239 long r; 4240 4241 switch (ioctl) { 4242 case KVM_GET_MSR_INDEX_LIST: { 4243 struct kvm_msr_list __user *user_msr_list = argp; 4244 struct kvm_msr_list msr_list; 4245 unsigned n; 4246 4247 r = -EFAULT; 4248 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4249 goto out; 4250 n = msr_list.nmsrs; 4251 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 4252 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4253 goto out; 4254 r = -E2BIG; 4255 if (n < msr_list.nmsrs) 4256 goto out; 4257 r = -EFAULT; 4258 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 4259 num_msrs_to_save * sizeof(u32))) 4260 goto out; 4261 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 4262 &emulated_msrs, 4263 num_emulated_msrs * sizeof(u32))) 4264 goto out; 4265 r = 0; 4266 break; 4267 } 4268 case KVM_GET_SUPPORTED_CPUID: 4269 case KVM_GET_EMULATED_CPUID: { 4270 struct kvm_cpuid2 __user *cpuid_arg = argp; 4271 struct kvm_cpuid2 cpuid; 4272 4273 r = -EFAULT; 4274 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4275 goto out; 4276 4277 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 4278 ioctl); 4279 if (r) 4280 goto out; 4281 4282 r = -EFAULT; 4283 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4284 goto out; 4285 r = 0; 4286 break; 4287 } 4288 case KVM_X86_GET_MCE_CAP_SUPPORTED: 4289 r = -EFAULT; 4290 if (copy_to_user(argp, &kvm_mce_cap_supported, 4291 sizeof(kvm_mce_cap_supported))) 4292 goto out; 4293 r = 0; 4294 break; 4295 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 4296 struct kvm_msr_list __user *user_msr_list = argp; 4297 struct kvm_msr_list msr_list; 4298 unsigned int n; 4299 4300 r = -EFAULT; 4301 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4302 goto out; 4303 n = msr_list.nmsrs; 4304 msr_list.nmsrs = num_msr_based_features; 4305 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4306 goto out; 4307 r = -E2BIG; 4308 if (n < msr_list.nmsrs) 4309 goto out; 4310 r = -EFAULT; 4311 if (copy_to_user(user_msr_list->indices, &msr_based_features, 4312 num_msr_based_features * sizeof(u32))) 4313 goto out; 4314 r = 0; 4315 break; 4316 } 4317 case KVM_GET_MSRS: 4318 r = msr_io(NULL, argp, do_get_msr_feature, 1); 4319 break; 4320 case KVM_GET_SUPPORTED_HV_CPUID: 4321 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); 4322 break; 4323 default: 4324 r = -EINVAL; 4325 break; 4326 } 4327 out: 4328 return r; 4329 } 4330 4331 static void wbinvd_ipi(void *garbage) 4332 { 4333 wbinvd(); 4334 } 4335 4336 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 4337 { 4338 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 4339 } 4340 4341 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 4342 { 4343 /* Address WBINVD may be executed by guest */ 4344 if (need_emulate_wbinvd(vcpu)) { 4345 if (static_call(kvm_x86_has_wbinvd_exit)()) 4346 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4347 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 4348 smp_call_function_single(vcpu->cpu, 4349 wbinvd_ipi, NULL, 1); 4350 } 4351 4352 static_call(kvm_x86_vcpu_load)(vcpu, cpu); 4353 4354 /* Save host pkru register if supported */ 4355 vcpu->arch.host_pkru = read_pkru(); 4356 4357 /* Apply any externally detected TSC adjustments (due to suspend) */ 4358 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 4359 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 4360 vcpu->arch.tsc_offset_adjustment = 0; 4361 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4362 } 4363 4364 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 4365 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 4366 rdtsc() - vcpu->arch.last_host_tsc; 4367 if (tsc_delta < 0) 4368 mark_tsc_unstable("KVM discovered backwards TSC"); 4369 4370 if (kvm_check_tsc_unstable()) { 4371 u64 offset = kvm_compute_l1_tsc_offset(vcpu, 4372 vcpu->arch.last_guest_tsc); 4373 kvm_vcpu_write_tsc_offset(vcpu, offset); 4374 vcpu->arch.tsc_catchup = 1; 4375 } 4376 4377 if (kvm_lapic_hv_timer_in_use(vcpu)) 4378 kvm_lapic_restart_hv_timer(vcpu); 4379 4380 /* 4381 * On a host with synchronized TSC, there is no need to update 4382 * kvmclock on vcpu->cpu migration 4383 */ 4384 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 4385 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 4386 if (vcpu->cpu != cpu) 4387 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 4388 vcpu->cpu = cpu; 4389 } 4390 4391 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 4392 } 4393 4394 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 4395 { 4396 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; 4397 struct kvm_steal_time __user *st; 4398 struct kvm_memslots *slots; 4399 static const u8 preempted = KVM_VCPU_PREEMPTED; 4400 4401 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 4402 return; 4403 4404 if (vcpu->arch.st.preempted) 4405 return; 4406 4407 /* This happens on process exit */ 4408 if (unlikely(current->mm != vcpu->kvm->mm)) 4409 return; 4410 4411 slots = kvm_memslots(vcpu->kvm); 4412 4413 if (unlikely(slots->generation != ghc->generation || 4414 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) 4415 return; 4416 4417 st = (struct kvm_steal_time __user *)ghc->hva; 4418 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted)); 4419 4420 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted))) 4421 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 4422 4423 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 4424 } 4425 4426 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 4427 { 4428 int idx; 4429 4430 if (vcpu->preempted && !vcpu->arch.guest_state_protected) 4431 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); 4432 4433 /* 4434 * Take the srcu lock as memslots will be accessed to check the gfn 4435 * cache generation against the memslots generation. 4436 */ 4437 idx = srcu_read_lock(&vcpu->kvm->srcu); 4438 if (kvm_xen_msr_enabled(vcpu->kvm)) 4439 kvm_xen_runstate_set_preempted(vcpu); 4440 else 4441 kvm_steal_time_set_preempted(vcpu); 4442 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4443 4444 static_call(kvm_x86_vcpu_put)(vcpu); 4445 vcpu->arch.last_host_tsc = rdtsc(); 4446 } 4447 4448 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 4449 struct kvm_lapic_state *s) 4450 { 4451 if (vcpu->arch.apicv_active) 4452 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 4453 4454 return kvm_apic_get_state(vcpu, s); 4455 } 4456 4457 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 4458 struct kvm_lapic_state *s) 4459 { 4460 int r; 4461 4462 r = kvm_apic_set_state(vcpu, s); 4463 if (r) 4464 return r; 4465 update_cr8_intercept(vcpu); 4466 4467 return 0; 4468 } 4469 4470 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 4471 { 4472 /* 4473 * We can accept userspace's request for interrupt injection 4474 * as long as we have a place to store the interrupt number. 4475 * The actual injection will happen when the CPU is able to 4476 * deliver the interrupt. 4477 */ 4478 if (kvm_cpu_has_extint(vcpu)) 4479 return false; 4480 4481 /* Acknowledging ExtINT does not happen if LINT0 is masked. */ 4482 return (!lapic_in_kernel(vcpu) || 4483 kvm_apic_accept_pic_intr(vcpu)); 4484 } 4485 4486 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 4487 { 4488 /* 4489 * Do not cause an interrupt window exit if an exception 4490 * is pending or an event needs reinjection; userspace 4491 * might want to inject the interrupt manually using KVM_SET_REGS 4492 * or KVM_SET_SREGS. For that to work, we must be at an 4493 * instruction boundary and with no events half-injected. 4494 */ 4495 return (kvm_arch_interrupt_allowed(vcpu) && 4496 kvm_cpu_accept_dm_intr(vcpu) && 4497 !kvm_event_needs_reinjection(vcpu) && 4498 !vcpu->arch.exception.pending); 4499 } 4500 4501 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 4502 struct kvm_interrupt *irq) 4503 { 4504 if (irq->irq >= KVM_NR_INTERRUPTS) 4505 return -EINVAL; 4506 4507 if (!irqchip_in_kernel(vcpu->kvm)) { 4508 kvm_queue_interrupt(vcpu, irq->irq, false); 4509 kvm_make_request(KVM_REQ_EVENT, vcpu); 4510 return 0; 4511 } 4512 4513 /* 4514 * With in-kernel LAPIC, we only use this to inject EXTINT, so 4515 * fail for in-kernel 8259. 4516 */ 4517 if (pic_in_kernel(vcpu->kvm)) 4518 return -ENXIO; 4519 4520 if (vcpu->arch.pending_external_vector != -1) 4521 return -EEXIST; 4522 4523 vcpu->arch.pending_external_vector = irq->irq; 4524 kvm_make_request(KVM_REQ_EVENT, vcpu); 4525 return 0; 4526 } 4527 4528 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 4529 { 4530 kvm_inject_nmi(vcpu); 4531 4532 return 0; 4533 } 4534 4535 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 4536 { 4537 kvm_make_request(KVM_REQ_SMI, vcpu); 4538 4539 return 0; 4540 } 4541 4542 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 4543 struct kvm_tpr_access_ctl *tac) 4544 { 4545 if (tac->flags) 4546 return -EINVAL; 4547 vcpu->arch.tpr_access_reporting = !!tac->enabled; 4548 return 0; 4549 } 4550 4551 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 4552 u64 mcg_cap) 4553 { 4554 int r; 4555 unsigned bank_num = mcg_cap & 0xff, bank; 4556 4557 r = -EINVAL; 4558 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) 4559 goto out; 4560 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 4561 goto out; 4562 r = 0; 4563 vcpu->arch.mcg_cap = mcg_cap; 4564 /* Init IA32_MCG_CTL to all 1s */ 4565 if (mcg_cap & MCG_CTL_P) 4566 vcpu->arch.mcg_ctl = ~(u64)0; 4567 /* Init IA32_MCi_CTL to all 1s */ 4568 for (bank = 0; bank < bank_num; bank++) 4569 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 4570 4571 static_call(kvm_x86_setup_mce)(vcpu); 4572 out: 4573 return r; 4574 } 4575 4576 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 4577 struct kvm_x86_mce *mce) 4578 { 4579 u64 mcg_cap = vcpu->arch.mcg_cap; 4580 unsigned bank_num = mcg_cap & 0xff; 4581 u64 *banks = vcpu->arch.mce_banks; 4582 4583 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 4584 return -EINVAL; 4585 /* 4586 * if IA32_MCG_CTL is not all 1s, the uncorrected error 4587 * reporting is disabled 4588 */ 4589 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 4590 vcpu->arch.mcg_ctl != ~(u64)0) 4591 return 0; 4592 banks += 4 * mce->bank; 4593 /* 4594 * if IA32_MCi_CTL is not all 1s, the uncorrected error 4595 * reporting is disabled for the bank 4596 */ 4597 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 4598 return 0; 4599 if (mce->status & MCI_STATUS_UC) { 4600 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 4601 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 4602 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 4603 return 0; 4604 } 4605 if (banks[1] & MCI_STATUS_VAL) 4606 mce->status |= MCI_STATUS_OVER; 4607 banks[2] = mce->addr; 4608 banks[3] = mce->misc; 4609 vcpu->arch.mcg_status = mce->mcg_status; 4610 banks[1] = mce->status; 4611 kvm_queue_exception(vcpu, MC_VECTOR); 4612 } else if (!(banks[1] & MCI_STATUS_VAL) 4613 || !(banks[1] & MCI_STATUS_UC)) { 4614 if (banks[1] & MCI_STATUS_VAL) 4615 mce->status |= MCI_STATUS_OVER; 4616 banks[2] = mce->addr; 4617 banks[3] = mce->misc; 4618 banks[1] = mce->status; 4619 } else 4620 banks[1] |= MCI_STATUS_OVER; 4621 return 0; 4622 } 4623 4624 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 4625 struct kvm_vcpu_events *events) 4626 { 4627 process_nmi(vcpu); 4628 4629 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 4630 process_smi(vcpu); 4631 4632 /* 4633 * In guest mode, payload delivery should be deferred, 4634 * so that the L1 hypervisor can intercept #PF before 4635 * CR2 is modified (or intercept #DB before DR6 is 4636 * modified under nVMX). Unless the per-VM capability, 4637 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of 4638 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we 4639 * opportunistically defer the exception payload, deliver it if the 4640 * capability hasn't been requested before processing a 4641 * KVM_GET_VCPU_EVENTS. 4642 */ 4643 if (!vcpu->kvm->arch.exception_payload_enabled && 4644 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) 4645 kvm_deliver_exception_payload(vcpu); 4646 4647 /* 4648 * The API doesn't provide the instruction length for software 4649 * exceptions, so don't report them. As long as the guest RIP 4650 * isn't advanced, we should expect to encounter the exception 4651 * again. 4652 */ 4653 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 4654 events->exception.injected = 0; 4655 events->exception.pending = 0; 4656 } else { 4657 events->exception.injected = vcpu->arch.exception.injected; 4658 events->exception.pending = vcpu->arch.exception.pending; 4659 /* 4660 * For ABI compatibility, deliberately conflate 4661 * pending and injected exceptions when 4662 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 4663 */ 4664 if (!vcpu->kvm->arch.exception_payload_enabled) 4665 events->exception.injected |= 4666 vcpu->arch.exception.pending; 4667 } 4668 events->exception.nr = vcpu->arch.exception.nr; 4669 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 4670 events->exception.error_code = vcpu->arch.exception.error_code; 4671 events->exception_has_payload = vcpu->arch.exception.has_payload; 4672 events->exception_payload = vcpu->arch.exception.payload; 4673 4674 events->interrupt.injected = 4675 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 4676 events->interrupt.nr = vcpu->arch.interrupt.nr; 4677 events->interrupt.soft = 0; 4678 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 4679 4680 events->nmi.injected = vcpu->arch.nmi_injected; 4681 events->nmi.pending = vcpu->arch.nmi_pending != 0; 4682 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); 4683 events->nmi.pad = 0; 4684 4685 events->sipi_vector = 0; /* never valid when reporting to user space */ 4686 4687 events->smi.smm = is_smm(vcpu); 4688 events->smi.pending = vcpu->arch.smi_pending; 4689 events->smi.smm_inside_nmi = 4690 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 4691 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 4692 4693 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 4694 | KVM_VCPUEVENT_VALID_SHADOW 4695 | KVM_VCPUEVENT_VALID_SMM); 4696 if (vcpu->kvm->arch.exception_payload_enabled) 4697 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 4698 4699 memset(&events->reserved, 0, sizeof(events->reserved)); 4700 } 4701 4702 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm); 4703 4704 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 4705 struct kvm_vcpu_events *events) 4706 { 4707 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 4708 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 4709 | KVM_VCPUEVENT_VALID_SHADOW 4710 | KVM_VCPUEVENT_VALID_SMM 4711 | KVM_VCPUEVENT_VALID_PAYLOAD)) 4712 return -EINVAL; 4713 4714 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 4715 if (!vcpu->kvm->arch.exception_payload_enabled) 4716 return -EINVAL; 4717 if (events->exception.pending) 4718 events->exception.injected = 0; 4719 else 4720 events->exception_has_payload = 0; 4721 } else { 4722 events->exception.pending = 0; 4723 events->exception_has_payload = 0; 4724 } 4725 4726 if ((events->exception.injected || events->exception.pending) && 4727 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 4728 return -EINVAL; 4729 4730 /* INITs are latched while in SMM */ 4731 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 4732 (events->smi.smm || events->smi.pending) && 4733 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 4734 return -EINVAL; 4735 4736 process_nmi(vcpu); 4737 vcpu->arch.exception.injected = events->exception.injected; 4738 vcpu->arch.exception.pending = events->exception.pending; 4739 vcpu->arch.exception.nr = events->exception.nr; 4740 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 4741 vcpu->arch.exception.error_code = events->exception.error_code; 4742 vcpu->arch.exception.has_payload = events->exception_has_payload; 4743 vcpu->arch.exception.payload = events->exception_payload; 4744 4745 vcpu->arch.interrupt.injected = events->interrupt.injected; 4746 vcpu->arch.interrupt.nr = events->interrupt.nr; 4747 vcpu->arch.interrupt.soft = events->interrupt.soft; 4748 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 4749 static_call(kvm_x86_set_interrupt_shadow)(vcpu, 4750 events->interrupt.shadow); 4751 4752 vcpu->arch.nmi_injected = events->nmi.injected; 4753 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 4754 vcpu->arch.nmi_pending = events->nmi.pending; 4755 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); 4756 4757 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 4758 lapic_in_kernel(vcpu)) 4759 vcpu->arch.apic->sipi_vector = events->sipi_vector; 4760 4761 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 4762 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) 4763 kvm_smm_changed(vcpu, events->smi.smm); 4764 4765 vcpu->arch.smi_pending = events->smi.pending; 4766 4767 if (events->smi.smm) { 4768 if (events->smi.smm_inside_nmi) 4769 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 4770 else 4771 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 4772 } 4773 4774 if (lapic_in_kernel(vcpu)) { 4775 if (events->smi.latched_init) 4776 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4777 else 4778 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4779 } 4780 } 4781 4782 kvm_make_request(KVM_REQ_EVENT, vcpu); 4783 4784 return 0; 4785 } 4786 4787 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 4788 struct kvm_debugregs *dbgregs) 4789 { 4790 unsigned long val; 4791 4792 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 4793 kvm_get_dr(vcpu, 6, &val); 4794 dbgregs->dr6 = val; 4795 dbgregs->dr7 = vcpu->arch.dr7; 4796 dbgregs->flags = 0; 4797 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 4798 } 4799 4800 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 4801 struct kvm_debugregs *dbgregs) 4802 { 4803 if (dbgregs->flags) 4804 return -EINVAL; 4805 4806 if (!kvm_dr6_valid(dbgregs->dr6)) 4807 return -EINVAL; 4808 if (!kvm_dr7_valid(dbgregs->dr7)) 4809 return -EINVAL; 4810 4811 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 4812 kvm_update_dr0123(vcpu); 4813 vcpu->arch.dr6 = dbgregs->dr6; 4814 vcpu->arch.dr7 = dbgregs->dr7; 4815 kvm_update_dr7(vcpu); 4816 4817 return 0; 4818 } 4819 4820 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 4821 struct kvm_xsave *guest_xsave) 4822 { 4823 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 4824 return; 4825 4826 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, 4827 guest_xsave->region, 4828 sizeof(guest_xsave->region), 4829 vcpu->arch.pkru); 4830 } 4831 4832 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 4833 struct kvm_xsave *guest_xsave) 4834 { 4835 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 4836 return 0; 4837 4838 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu, 4839 guest_xsave->region, 4840 supported_xcr0, &vcpu->arch.pkru); 4841 } 4842 4843 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 4844 struct kvm_xcrs *guest_xcrs) 4845 { 4846 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 4847 guest_xcrs->nr_xcrs = 0; 4848 return; 4849 } 4850 4851 guest_xcrs->nr_xcrs = 1; 4852 guest_xcrs->flags = 0; 4853 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 4854 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 4855 } 4856 4857 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 4858 struct kvm_xcrs *guest_xcrs) 4859 { 4860 int i, r = 0; 4861 4862 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 4863 return -EINVAL; 4864 4865 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 4866 return -EINVAL; 4867 4868 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 4869 /* Only support XCR0 currently */ 4870 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 4871 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 4872 guest_xcrs->xcrs[i].value); 4873 break; 4874 } 4875 if (r) 4876 r = -EINVAL; 4877 return r; 4878 } 4879 4880 /* 4881 * kvm_set_guest_paused() indicates to the guest kernel that it has been 4882 * stopped by the hypervisor. This function will be called from the host only. 4883 * EINVAL is returned when the host attempts to set the flag for a guest that 4884 * does not support pv clocks. 4885 */ 4886 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 4887 { 4888 if (!vcpu->arch.pv_time_enabled) 4889 return -EINVAL; 4890 vcpu->arch.pvclock_set_guest_stopped_request = true; 4891 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4892 return 0; 4893 } 4894 4895 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu, 4896 struct kvm_device_attr *attr) 4897 { 4898 int r; 4899 4900 switch (attr->attr) { 4901 case KVM_VCPU_TSC_OFFSET: 4902 r = 0; 4903 break; 4904 default: 4905 r = -ENXIO; 4906 } 4907 4908 return r; 4909 } 4910 4911 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu, 4912 struct kvm_device_attr *attr) 4913 { 4914 u64 __user *uaddr = (u64 __user *)(unsigned long)attr->addr; 4915 int r; 4916 4917 if ((u64)(unsigned long)uaddr != attr->addr) 4918 return -EFAULT; 4919 4920 switch (attr->attr) { 4921 case KVM_VCPU_TSC_OFFSET: 4922 r = -EFAULT; 4923 if (put_user(vcpu->arch.l1_tsc_offset, uaddr)) 4924 break; 4925 r = 0; 4926 break; 4927 default: 4928 r = -ENXIO; 4929 } 4930 4931 return r; 4932 } 4933 4934 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu, 4935 struct kvm_device_attr *attr) 4936 { 4937 u64 __user *uaddr = (u64 __user *)(unsigned long)attr->addr; 4938 struct kvm *kvm = vcpu->kvm; 4939 int r; 4940 4941 if ((u64)(unsigned long)uaddr != attr->addr) 4942 return -EFAULT; 4943 4944 switch (attr->attr) { 4945 case KVM_VCPU_TSC_OFFSET: { 4946 u64 offset, tsc, ns; 4947 unsigned long flags; 4948 bool matched; 4949 4950 r = -EFAULT; 4951 if (get_user(offset, uaddr)) 4952 break; 4953 4954 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 4955 4956 matched = (vcpu->arch.virtual_tsc_khz && 4957 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz && 4958 kvm->arch.last_tsc_offset == offset); 4959 4960 tsc = kvm_scale_tsc(vcpu, rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset; 4961 ns = get_kvmclock_base_ns(); 4962 4963 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched); 4964 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 4965 4966 r = 0; 4967 break; 4968 } 4969 default: 4970 r = -ENXIO; 4971 } 4972 4973 return r; 4974 } 4975 4976 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu, 4977 unsigned int ioctl, 4978 void __user *argp) 4979 { 4980 struct kvm_device_attr attr; 4981 int r; 4982 4983 if (copy_from_user(&attr, argp, sizeof(attr))) 4984 return -EFAULT; 4985 4986 if (attr.group != KVM_VCPU_TSC_CTRL) 4987 return -ENXIO; 4988 4989 switch (ioctl) { 4990 case KVM_HAS_DEVICE_ATTR: 4991 r = kvm_arch_tsc_has_attr(vcpu, &attr); 4992 break; 4993 case KVM_GET_DEVICE_ATTR: 4994 r = kvm_arch_tsc_get_attr(vcpu, &attr); 4995 break; 4996 case KVM_SET_DEVICE_ATTR: 4997 r = kvm_arch_tsc_set_attr(vcpu, &attr); 4998 break; 4999 } 5000 5001 return r; 5002 } 5003 5004 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 5005 struct kvm_enable_cap *cap) 5006 { 5007 int r; 5008 uint16_t vmcs_version; 5009 void __user *user_ptr; 5010 5011 if (cap->flags) 5012 return -EINVAL; 5013 5014 switch (cap->cap) { 5015 case KVM_CAP_HYPERV_SYNIC2: 5016 if (cap->args[0]) 5017 return -EINVAL; 5018 fallthrough; 5019 5020 case KVM_CAP_HYPERV_SYNIC: 5021 if (!irqchip_in_kernel(vcpu->kvm)) 5022 return -EINVAL; 5023 return kvm_hv_activate_synic(vcpu, cap->cap == 5024 KVM_CAP_HYPERV_SYNIC2); 5025 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 5026 if (!kvm_x86_ops.nested_ops->enable_evmcs) 5027 return -ENOTTY; 5028 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); 5029 if (!r) { 5030 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 5031 if (copy_to_user(user_ptr, &vmcs_version, 5032 sizeof(vmcs_version))) 5033 r = -EFAULT; 5034 } 5035 return r; 5036 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 5037 if (!kvm_x86_ops.enable_direct_tlbflush) 5038 return -ENOTTY; 5039 5040 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); 5041 5042 case KVM_CAP_HYPERV_ENFORCE_CPUID: 5043 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]); 5044 5045 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 5046 vcpu->arch.pv_cpuid.enforce = cap->args[0]; 5047 if (vcpu->arch.pv_cpuid.enforce) 5048 kvm_update_pv_runtime(vcpu); 5049 5050 return 0; 5051 default: 5052 return -EINVAL; 5053 } 5054 } 5055 5056 long kvm_arch_vcpu_ioctl(struct file *filp, 5057 unsigned int ioctl, unsigned long arg) 5058 { 5059 struct kvm_vcpu *vcpu = filp->private_data; 5060 void __user *argp = (void __user *)arg; 5061 int r; 5062 union { 5063 struct kvm_sregs2 *sregs2; 5064 struct kvm_lapic_state *lapic; 5065 struct kvm_xsave *xsave; 5066 struct kvm_xcrs *xcrs; 5067 void *buffer; 5068 } u; 5069 5070 vcpu_load(vcpu); 5071 5072 u.buffer = NULL; 5073 switch (ioctl) { 5074 case KVM_GET_LAPIC: { 5075 r = -EINVAL; 5076 if (!lapic_in_kernel(vcpu)) 5077 goto out; 5078 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 5079 GFP_KERNEL_ACCOUNT); 5080 5081 r = -ENOMEM; 5082 if (!u.lapic) 5083 goto out; 5084 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 5085 if (r) 5086 goto out; 5087 r = -EFAULT; 5088 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 5089 goto out; 5090 r = 0; 5091 break; 5092 } 5093 case KVM_SET_LAPIC: { 5094 r = -EINVAL; 5095 if (!lapic_in_kernel(vcpu)) 5096 goto out; 5097 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 5098 if (IS_ERR(u.lapic)) { 5099 r = PTR_ERR(u.lapic); 5100 goto out_nofree; 5101 } 5102 5103 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 5104 break; 5105 } 5106 case KVM_INTERRUPT: { 5107 struct kvm_interrupt irq; 5108 5109 r = -EFAULT; 5110 if (copy_from_user(&irq, argp, sizeof(irq))) 5111 goto out; 5112 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 5113 break; 5114 } 5115 case KVM_NMI: { 5116 r = kvm_vcpu_ioctl_nmi(vcpu); 5117 break; 5118 } 5119 case KVM_SMI: { 5120 r = kvm_vcpu_ioctl_smi(vcpu); 5121 break; 5122 } 5123 case KVM_SET_CPUID: { 5124 struct kvm_cpuid __user *cpuid_arg = argp; 5125 struct kvm_cpuid cpuid; 5126 5127 r = -EFAULT; 5128 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5129 goto out; 5130 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 5131 break; 5132 } 5133 case KVM_SET_CPUID2: { 5134 struct kvm_cpuid2 __user *cpuid_arg = argp; 5135 struct kvm_cpuid2 cpuid; 5136 5137 r = -EFAULT; 5138 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5139 goto out; 5140 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 5141 cpuid_arg->entries); 5142 break; 5143 } 5144 case KVM_GET_CPUID2: { 5145 struct kvm_cpuid2 __user *cpuid_arg = argp; 5146 struct kvm_cpuid2 cpuid; 5147 5148 r = -EFAULT; 5149 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5150 goto out; 5151 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 5152 cpuid_arg->entries); 5153 if (r) 5154 goto out; 5155 r = -EFAULT; 5156 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 5157 goto out; 5158 r = 0; 5159 break; 5160 } 5161 case KVM_GET_MSRS: { 5162 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5163 r = msr_io(vcpu, argp, do_get_msr, 1); 5164 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5165 break; 5166 } 5167 case KVM_SET_MSRS: { 5168 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5169 r = msr_io(vcpu, argp, do_set_msr, 0); 5170 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5171 break; 5172 } 5173 case KVM_TPR_ACCESS_REPORTING: { 5174 struct kvm_tpr_access_ctl tac; 5175 5176 r = -EFAULT; 5177 if (copy_from_user(&tac, argp, sizeof(tac))) 5178 goto out; 5179 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 5180 if (r) 5181 goto out; 5182 r = -EFAULT; 5183 if (copy_to_user(argp, &tac, sizeof(tac))) 5184 goto out; 5185 r = 0; 5186 break; 5187 }; 5188 case KVM_SET_VAPIC_ADDR: { 5189 struct kvm_vapic_addr va; 5190 int idx; 5191 5192 r = -EINVAL; 5193 if (!lapic_in_kernel(vcpu)) 5194 goto out; 5195 r = -EFAULT; 5196 if (copy_from_user(&va, argp, sizeof(va))) 5197 goto out; 5198 idx = srcu_read_lock(&vcpu->kvm->srcu); 5199 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 5200 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5201 break; 5202 } 5203 case KVM_X86_SETUP_MCE: { 5204 u64 mcg_cap; 5205 5206 r = -EFAULT; 5207 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 5208 goto out; 5209 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 5210 break; 5211 } 5212 case KVM_X86_SET_MCE: { 5213 struct kvm_x86_mce mce; 5214 5215 r = -EFAULT; 5216 if (copy_from_user(&mce, argp, sizeof(mce))) 5217 goto out; 5218 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 5219 break; 5220 } 5221 case KVM_GET_VCPU_EVENTS: { 5222 struct kvm_vcpu_events events; 5223 5224 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 5225 5226 r = -EFAULT; 5227 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 5228 break; 5229 r = 0; 5230 break; 5231 } 5232 case KVM_SET_VCPU_EVENTS: { 5233 struct kvm_vcpu_events events; 5234 5235 r = -EFAULT; 5236 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 5237 break; 5238 5239 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 5240 break; 5241 } 5242 case KVM_GET_DEBUGREGS: { 5243 struct kvm_debugregs dbgregs; 5244 5245 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 5246 5247 r = -EFAULT; 5248 if (copy_to_user(argp, &dbgregs, 5249 sizeof(struct kvm_debugregs))) 5250 break; 5251 r = 0; 5252 break; 5253 } 5254 case KVM_SET_DEBUGREGS: { 5255 struct kvm_debugregs dbgregs; 5256 5257 r = -EFAULT; 5258 if (copy_from_user(&dbgregs, argp, 5259 sizeof(struct kvm_debugregs))) 5260 break; 5261 5262 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 5263 break; 5264 } 5265 case KVM_GET_XSAVE: { 5266 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 5267 r = -ENOMEM; 5268 if (!u.xsave) 5269 break; 5270 5271 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 5272 5273 r = -EFAULT; 5274 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 5275 break; 5276 r = 0; 5277 break; 5278 } 5279 case KVM_SET_XSAVE: { 5280 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 5281 if (IS_ERR(u.xsave)) { 5282 r = PTR_ERR(u.xsave); 5283 goto out_nofree; 5284 } 5285 5286 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 5287 break; 5288 } 5289 case KVM_GET_XCRS: { 5290 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 5291 r = -ENOMEM; 5292 if (!u.xcrs) 5293 break; 5294 5295 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 5296 5297 r = -EFAULT; 5298 if (copy_to_user(argp, u.xcrs, 5299 sizeof(struct kvm_xcrs))) 5300 break; 5301 r = 0; 5302 break; 5303 } 5304 case KVM_SET_XCRS: { 5305 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 5306 if (IS_ERR(u.xcrs)) { 5307 r = PTR_ERR(u.xcrs); 5308 goto out_nofree; 5309 } 5310 5311 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 5312 break; 5313 } 5314 case KVM_SET_TSC_KHZ: { 5315 u32 user_tsc_khz; 5316 5317 r = -EINVAL; 5318 user_tsc_khz = (u32)arg; 5319 5320 if (kvm_has_tsc_control && 5321 user_tsc_khz >= kvm_max_guest_tsc_khz) 5322 goto out; 5323 5324 if (user_tsc_khz == 0) 5325 user_tsc_khz = tsc_khz; 5326 5327 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 5328 r = 0; 5329 5330 goto out; 5331 } 5332 case KVM_GET_TSC_KHZ: { 5333 r = vcpu->arch.virtual_tsc_khz; 5334 goto out; 5335 } 5336 case KVM_KVMCLOCK_CTRL: { 5337 r = kvm_set_guest_paused(vcpu); 5338 goto out; 5339 } 5340 case KVM_ENABLE_CAP: { 5341 struct kvm_enable_cap cap; 5342 5343 r = -EFAULT; 5344 if (copy_from_user(&cap, argp, sizeof(cap))) 5345 goto out; 5346 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 5347 break; 5348 } 5349 case KVM_GET_NESTED_STATE: { 5350 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5351 u32 user_data_size; 5352 5353 r = -EINVAL; 5354 if (!kvm_x86_ops.nested_ops->get_state) 5355 break; 5356 5357 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 5358 r = -EFAULT; 5359 if (get_user(user_data_size, &user_kvm_nested_state->size)) 5360 break; 5361 5362 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, 5363 user_data_size); 5364 if (r < 0) 5365 break; 5366 5367 if (r > user_data_size) { 5368 if (put_user(r, &user_kvm_nested_state->size)) 5369 r = -EFAULT; 5370 else 5371 r = -E2BIG; 5372 break; 5373 } 5374 5375 r = 0; 5376 break; 5377 } 5378 case KVM_SET_NESTED_STATE: { 5379 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5380 struct kvm_nested_state kvm_state; 5381 int idx; 5382 5383 r = -EINVAL; 5384 if (!kvm_x86_ops.nested_ops->set_state) 5385 break; 5386 5387 r = -EFAULT; 5388 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 5389 break; 5390 5391 r = -EINVAL; 5392 if (kvm_state.size < sizeof(kvm_state)) 5393 break; 5394 5395 if (kvm_state.flags & 5396 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 5397 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING 5398 | KVM_STATE_NESTED_GIF_SET)) 5399 break; 5400 5401 /* nested_run_pending implies guest_mode. */ 5402 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 5403 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 5404 break; 5405 5406 idx = srcu_read_lock(&vcpu->kvm->srcu); 5407 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); 5408 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5409 break; 5410 } 5411 case KVM_GET_SUPPORTED_HV_CPUID: 5412 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); 5413 break; 5414 #ifdef CONFIG_KVM_XEN 5415 case KVM_XEN_VCPU_GET_ATTR: { 5416 struct kvm_xen_vcpu_attr xva; 5417 5418 r = -EFAULT; 5419 if (copy_from_user(&xva, argp, sizeof(xva))) 5420 goto out; 5421 r = kvm_xen_vcpu_get_attr(vcpu, &xva); 5422 if (!r && copy_to_user(argp, &xva, sizeof(xva))) 5423 r = -EFAULT; 5424 break; 5425 } 5426 case KVM_XEN_VCPU_SET_ATTR: { 5427 struct kvm_xen_vcpu_attr xva; 5428 5429 r = -EFAULT; 5430 if (copy_from_user(&xva, argp, sizeof(xva))) 5431 goto out; 5432 r = kvm_xen_vcpu_set_attr(vcpu, &xva); 5433 break; 5434 } 5435 #endif 5436 case KVM_GET_SREGS2: { 5437 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL); 5438 r = -ENOMEM; 5439 if (!u.sregs2) 5440 goto out; 5441 __get_sregs2(vcpu, u.sregs2); 5442 r = -EFAULT; 5443 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2))) 5444 goto out; 5445 r = 0; 5446 break; 5447 } 5448 case KVM_SET_SREGS2: { 5449 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2)); 5450 if (IS_ERR(u.sregs2)) { 5451 r = PTR_ERR(u.sregs2); 5452 u.sregs2 = NULL; 5453 goto out; 5454 } 5455 r = __set_sregs2(vcpu, u.sregs2); 5456 break; 5457 } 5458 case KVM_HAS_DEVICE_ATTR: 5459 case KVM_GET_DEVICE_ATTR: 5460 case KVM_SET_DEVICE_ATTR: 5461 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp); 5462 break; 5463 default: 5464 r = -EINVAL; 5465 } 5466 out: 5467 kfree(u.buffer); 5468 out_nofree: 5469 vcpu_put(vcpu); 5470 return r; 5471 } 5472 5473 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 5474 { 5475 return VM_FAULT_SIGBUS; 5476 } 5477 5478 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 5479 { 5480 int ret; 5481 5482 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 5483 return -EINVAL; 5484 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); 5485 return ret; 5486 } 5487 5488 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 5489 u64 ident_addr) 5490 { 5491 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); 5492 } 5493 5494 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 5495 unsigned long kvm_nr_mmu_pages) 5496 { 5497 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 5498 return -EINVAL; 5499 5500 mutex_lock(&kvm->slots_lock); 5501 5502 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 5503 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 5504 5505 mutex_unlock(&kvm->slots_lock); 5506 return 0; 5507 } 5508 5509 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 5510 { 5511 return kvm->arch.n_max_mmu_pages; 5512 } 5513 5514 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5515 { 5516 struct kvm_pic *pic = kvm->arch.vpic; 5517 int r; 5518 5519 r = 0; 5520 switch (chip->chip_id) { 5521 case KVM_IRQCHIP_PIC_MASTER: 5522 memcpy(&chip->chip.pic, &pic->pics[0], 5523 sizeof(struct kvm_pic_state)); 5524 break; 5525 case KVM_IRQCHIP_PIC_SLAVE: 5526 memcpy(&chip->chip.pic, &pic->pics[1], 5527 sizeof(struct kvm_pic_state)); 5528 break; 5529 case KVM_IRQCHIP_IOAPIC: 5530 kvm_get_ioapic(kvm, &chip->chip.ioapic); 5531 break; 5532 default: 5533 r = -EINVAL; 5534 break; 5535 } 5536 return r; 5537 } 5538 5539 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5540 { 5541 struct kvm_pic *pic = kvm->arch.vpic; 5542 int r; 5543 5544 r = 0; 5545 switch (chip->chip_id) { 5546 case KVM_IRQCHIP_PIC_MASTER: 5547 spin_lock(&pic->lock); 5548 memcpy(&pic->pics[0], &chip->chip.pic, 5549 sizeof(struct kvm_pic_state)); 5550 spin_unlock(&pic->lock); 5551 break; 5552 case KVM_IRQCHIP_PIC_SLAVE: 5553 spin_lock(&pic->lock); 5554 memcpy(&pic->pics[1], &chip->chip.pic, 5555 sizeof(struct kvm_pic_state)); 5556 spin_unlock(&pic->lock); 5557 break; 5558 case KVM_IRQCHIP_IOAPIC: 5559 kvm_set_ioapic(kvm, &chip->chip.ioapic); 5560 break; 5561 default: 5562 r = -EINVAL; 5563 break; 5564 } 5565 kvm_pic_update_irq(pic); 5566 return r; 5567 } 5568 5569 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5570 { 5571 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 5572 5573 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 5574 5575 mutex_lock(&kps->lock); 5576 memcpy(ps, &kps->channels, sizeof(*ps)); 5577 mutex_unlock(&kps->lock); 5578 return 0; 5579 } 5580 5581 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5582 { 5583 int i; 5584 struct kvm_pit *pit = kvm->arch.vpit; 5585 5586 mutex_lock(&pit->pit_state.lock); 5587 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 5588 for (i = 0; i < 3; i++) 5589 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 5590 mutex_unlock(&pit->pit_state.lock); 5591 return 0; 5592 } 5593 5594 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5595 { 5596 mutex_lock(&kvm->arch.vpit->pit_state.lock); 5597 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 5598 sizeof(ps->channels)); 5599 ps->flags = kvm->arch.vpit->pit_state.flags; 5600 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 5601 memset(&ps->reserved, 0, sizeof(ps->reserved)); 5602 return 0; 5603 } 5604 5605 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5606 { 5607 int start = 0; 5608 int i; 5609 u32 prev_legacy, cur_legacy; 5610 struct kvm_pit *pit = kvm->arch.vpit; 5611 5612 mutex_lock(&pit->pit_state.lock); 5613 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 5614 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 5615 if (!prev_legacy && cur_legacy) 5616 start = 1; 5617 memcpy(&pit->pit_state.channels, &ps->channels, 5618 sizeof(pit->pit_state.channels)); 5619 pit->pit_state.flags = ps->flags; 5620 for (i = 0; i < 3; i++) 5621 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 5622 start && i == 0); 5623 mutex_unlock(&pit->pit_state.lock); 5624 return 0; 5625 } 5626 5627 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 5628 struct kvm_reinject_control *control) 5629 { 5630 struct kvm_pit *pit = kvm->arch.vpit; 5631 5632 /* pit->pit_state.lock was overloaded to prevent userspace from getting 5633 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 5634 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 5635 */ 5636 mutex_lock(&pit->pit_state.lock); 5637 kvm_pit_set_reinject(pit, control->pit_reinject); 5638 mutex_unlock(&pit->pit_state.lock); 5639 5640 return 0; 5641 } 5642 5643 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 5644 { 5645 5646 /* 5647 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called 5648 * before reporting dirty_bitmap to userspace. KVM flushes the buffers 5649 * on all VM-Exits, thus we only need to kick running vCPUs to force a 5650 * VM-Exit. 5651 */ 5652 struct kvm_vcpu *vcpu; 5653 int i; 5654 5655 kvm_for_each_vcpu(i, vcpu, kvm) 5656 kvm_vcpu_kick(vcpu); 5657 } 5658 5659 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 5660 bool line_status) 5661 { 5662 if (!irqchip_in_kernel(kvm)) 5663 return -ENXIO; 5664 5665 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 5666 irq_event->irq, irq_event->level, 5667 line_status); 5668 return 0; 5669 } 5670 5671 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 5672 struct kvm_enable_cap *cap) 5673 { 5674 int r; 5675 5676 if (cap->flags) 5677 return -EINVAL; 5678 5679 switch (cap->cap) { 5680 case KVM_CAP_DISABLE_QUIRKS: 5681 kvm->arch.disabled_quirks = cap->args[0]; 5682 r = 0; 5683 break; 5684 case KVM_CAP_SPLIT_IRQCHIP: { 5685 mutex_lock(&kvm->lock); 5686 r = -EINVAL; 5687 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 5688 goto split_irqchip_unlock; 5689 r = -EEXIST; 5690 if (irqchip_in_kernel(kvm)) 5691 goto split_irqchip_unlock; 5692 if (kvm->created_vcpus) 5693 goto split_irqchip_unlock; 5694 r = kvm_setup_empty_irq_routing(kvm); 5695 if (r) 5696 goto split_irqchip_unlock; 5697 /* Pairs with irqchip_in_kernel. */ 5698 smp_wmb(); 5699 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 5700 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 5701 r = 0; 5702 split_irqchip_unlock: 5703 mutex_unlock(&kvm->lock); 5704 break; 5705 } 5706 case KVM_CAP_X2APIC_API: 5707 r = -EINVAL; 5708 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 5709 break; 5710 5711 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 5712 kvm->arch.x2apic_format = true; 5713 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 5714 kvm->arch.x2apic_broadcast_quirk_disabled = true; 5715 5716 r = 0; 5717 break; 5718 case KVM_CAP_X86_DISABLE_EXITS: 5719 r = -EINVAL; 5720 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 5721 break; 5722 5723 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 5724 kvm_can_mwait_in_guest()) 5725 kvm->arch.mwait_in_guest = true; 5726 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 5727 kvm->arch.hlt_in_guest = true; 5728 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 5729 kvm->arch.pause_in_guest = true; 5730 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) 5731 kvm->arch.cstate_in_guest = true; 5732 r = 0; 5733 break; 5734 case KVM_CAP_MSR_PLATFORM_INFO: 5735 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 5736 r = 0; 5737 break; 5738 case KVM_CAP_EXCEPTION_PAYLOAD: 5739 kvm->arch.exception_payload_enabled = cap->args[0]; 5740 r = 0; 5741 break; 5742 case KVM_CAP_X86_USER_SPACE_MSR: 5743 kvm->arch.user_space_msr_mask = cap->args[0]; 5744 r = 0; 5745 break; 5746 case KVM_CAP_X86_BUS_LOCK_EXIT: 5747 r = -EINVAL; 5748 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) 5749 break; 5750 5751 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && 5752 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) 5753 break; 5754 5755 if (kvm_has_bus_lock_exit && 5756 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) 5757 kvm->arch.bus_lock_detection_enabled = true; 5758 r = 0; 5759 break; 5760 #ifdef CONFIG_X86_SGX_KVM 5761 case KVM_CAP_SGX_ATTRIBUTE: { 5762 unsigned long allowed_attributes = 0; 5763 5764 r = sgx_set_attribute(&allowed_attributes, cap->args[0]); 5765 if (r) 5766 break; 5767 5768 /* KVM only supports the PROVISIONKEY privileged attribute. */ 5769 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && 5770 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) 5771 kvm->arch.sgx_provisioning_allowed = true; 5772 else 5773 r = -EINVAL; 5774 break; 5775 } 5776 #endif 5777 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 5778 r = -EINVAL; 5779 if (kvm_x86_ops.vm_copy_enc_context_from) 5780 r = kvm_x86_ops.vm_copy_enc_context_from(kvm, cap->args[0]); 5781 return r; 5782 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: 5783 r = -EINVAL; 5784 if (kvm_x86_ops.vm_move_enc_context_from) 5785 r = kvm_x86_ops.vm_move_enc_context_from( 5786 kvm, cap->args[0]); 5787 return r; 5788 case KVM_CAP_EXIT_HYPERCALL: 5789 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) { 5790 r = -EINVAL; 5791 break; 5792 } 5793 kvm->arch.hypercall_exit_enabled = cap->args[0]; 5794 r = 0; 5795 break; 5796 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 5797 r = -EINVAL; 5798 if (cap->args[0] & ~1) 5799 break; 5800 kvm->arch.exit_on_emulation_error = cap->args[0]; 5801 r = 0; 5802 break; 5803 default: 5804 r = -EINVAL; 5805 break; 5806 } 5807 return r; 5808 } 5809 5810 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) 5811 { 5812 struct kvm_x86_msr_filter *msr_filter; 5813 5814 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); 5815 if (!msr_filter) 5816 return NULL; 5817 5818 msr_filter->default_allow = default_allow; 5819 return msr_filter; 5820 } 5821 5822 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) 5823 { 5824 u32 i; 5825 5826 if (!msr_filter) 5827 return; 5828 5829 for (i = 0; i < msr_filter->count; i++) 5830 kfree(msr_filter->ranges[i].bitmap); 5831 5832 kfree(msr_filter); 5833 } 5834 5835 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, 5836 struct kvm_msr_filter_range *user_range) 5837 { 5838 unsigned long *bitmap = NULL; 5839 size_t bitmap_size; 5840 5841 if (!user_range->nmsrs) 5842 return 0; 5843 5844 if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) 5845 return -EINVAL; 5846 5847 if (!user_range->flags) 5848 return -EINVAL; 5849 5850 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); 5851 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) 5852 return -EINVAL; 5853 5854 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); 5855 if (IS_ERR(bitmap)) 5856 return PTR_ERR(bitmap); 5857 5858 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { 5859 .flags = user_range->flags, 5860 .base = user_range->base, 5861 .nmsrs = user_range->nmsrs, 5862 .bitmap = bitmap, 5863 }; 5864 5865 msr_filter->count++; 5866 return 0; 5867 } 5868 5869 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) 5870 { 5871 struct kvm_msr_filter __user *user_msr_filter = argp; 5872 struct kvm_x86_msr_filter *new_filter, *old_filter; 5873 struct kvm_msr_filter filter; 5874 bool default_allow; 5875 bool empty = true; 5876 int r = 0; 5877 u32 i; 5878 5879 if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) 5880 return -EFAULT; 5881 5882 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) 5883 empty &= !filter.ranges[i].nmsrs; 5884 5885 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); 5886 if (empty && !default_allow) 5887 return -EINVAL; 5888 5889 new_filter = kvm_alloc_msr_filter(default_allow); 5890 if (!new_filter) 5891 return -ENOMEM; 5892 5893 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { 5894 r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); 5895 if (r) { 5896 kvm_free_msr_filter(new_filter); 5897 return r; 5898 } 5899 } 5900 5901 mutex_lock(&kvm->lock); 5902 5903 /* The per-VM filter is protected by kvm->lock... */ 5904 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1); 5905 5906 rcu_assign_pointer(kvm->arch.msr_filter, new_filter); 5907 synchronize_srcu(&kvm->srcu); 5908 5909 kvm_free_msr_filter(old_filter); 5910 5911 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); 5912 mutex_unlock(&kvm->lock); 5913 5914 return 0; 5915 } 5916 5917 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER 5918 static int kvm_arch_suspend_notifier(struct kvm *kvm) 5919 { 5920 struct kvm_vcpu *vcpu; 5921 int i, ret = 0; 5922 5923 mutex_lock(&kvm->lock); 5924 kvm_for_each_vcpu(i, vcpu, kvm) { 5925 if (!vcpu->arch.pv_time_enabled) 5926 continue; 5927 5928 ret = kvm_set_guest_paused(vcpu); 5929 if (ret) { 5930 kvm_err("Failed to pause guest VCPU%d: %d\n", 5931 vcpu->vcpu_id, ret); 5932 break; 5933 } 5934 } 5935 mutex_unlock(&kvm->lock); 5936 5937 return ret ? NOTIFY_BAD : NOTIFY_DONE; 5938 } 5939 5940 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state) 5941 { 5942 switch (state) { 5943 case PM_HIBERNATION_PREPARE: 5944 case PM_SUSPEND_PREPARE: 5945 return kvm_arch_suspend_notifier(kvm); 5946 } 5947 5948 return NOTIFY_DONE; 5949 } 5950 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */ 5951 5952 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp) 5953 { 5954 struct kvm_clock_data data = { 0 }; 5955 5956 get_kvmclock(kvm, &data); 5957 if (copy_to_user(argp, &data, sizeof(data))) 5958 return -EFAULT; 5959 5960 return 0; 5961 } 5962 5963 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp) 5964 { 5965 struct kvm_arch *ka = &kvm->arch; 5966 struct kvm_clock_data data; 5967 u64 now_raw_ns; 5968 5969 if (copy_from_user(&data, argp, sizeof(data))) 5970 return -EFAULT; 5971 5972 /* 5973 * Only KVM_CLOCK_REALTIME is used, but allow passing the 5974 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK. 5975 */ 5976 if (data.flags & ~KVM_CLOCK_VALID_FLAGS) 5977 return -EINVAL; 5978 5979 kvm_hv_invalidate_tsc_page(kvm); 5980 kvm_start_pvclock_update(kvm); 5981 pvclock_update_vm_gtod_copy(kvm); 5982 5983 /* 5984 * This pairs with kvm_guest_time_update(): when masterclock is 5985 * in use, we use master_kernel_ns + kvmclock_offset to set 5986 * unsigned 'system_time' so if we use get_kvmclock_ns() (which 5987 * is slightly ahead) here we risk going negative on unsigned 5988 * 'system_time' when 'data.clock' is very small. 5989 */ 5990 if (data.flags & KVM_CLOCK_REALTIME) { 5991 u64 now_real_ns = ktime_get_real_ns(); 5992 5993 /* 5994 * Avoid stepping the kvmclock backwards. 5995 */ 5996 if (now_real_ns > data.realtime) 5997 data.clock += now_real_ns - data.realtime; 5998 } 5999 6000 if (ka->use_master_clock) 6001 now_raw_ns = ka->master_kernel_ns; 6002 else 6003 now_raw_ns = get_kvmclock_base_ns(); 6004 ka->kvmclock_offset = data.clock - now_raw_ns; 6005 kvm_end_pvclock_update(kvm); 6006 return 0; 6007 } 6008 6009 long kvm_arch_vm_ioctl(struct file *filp, 6010 unsigned int ioctl, unsigned long arg) 6011 { 6012 struct kvm *kvm = filp->private_data; 6013 void __user *argp = (void __user *)arg; 6014 int r = -ENOTTY; 6015 /* 6016 * This union makes it completely explicit to gcc-3.x 6017 * that these two variables' stack usage should be 6018 * combined, not added together. 6019 */ 6020 union { 6021 struct kvm_pit_state ps; 6022 struct kvm_pit_state2 ps2; 6023 struct kvm_pit_config pit_config; 6024 } u; 6025 6026 switch (ioctl) { 6027 case KVM_SET_TSS_ADDR: 6028 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 6029 break; 6030 case KVM_SET_IDENTITY_MAP_ADDR: { 6031 u64 ident_addr; 6032 6033 mutex_lock(&kvm->lock); 6034 r = -EINVAL; 6035 if (kvm->created_vcpus) 6036 goto set_identity_unlock; 6037 r = -EFAULT; 6038 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 6039 goto set_identity_unlock; 6040 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 6041 set_identity_unlock: 6042 mutex_unlock(&kvm->lock); 6043 break; 6044 } 6045 case KVM_SET_NR_MMU_PAGES: 6046 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 6047 break; 6048 case KVM_GET_NR_MMU_PAGES: 6049 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 6050 break; 6051 case KVM_CREATE_IRQCHIP: { 6052 mutex_lock(&kvm->lock); 6053 6054 r = -EEXIST; 6055 if (irqchip_in_kernel(kvm)) 6056 goto create_irqchip_unlock; 6057 6058 r = -EINVAL; 6059 if (kvm->created_vcpus) 6060 goto create_irqchip_unlock; 6061 6062 r = kvm_pic_init(kvm); 6063 if (r) 6064 goto create_irqchip_unlock; 6065 6066 r = kvm_ioapic_init(kvm); 6067 if (r) { 6068 kvm_pic_destroy(kvm); 6069 goto create_irqchip_unlock; 6070 } 6071 6072 r = kvm_setup_default_irq_routing(kvm); 6073 if (r) { 6074 kvm_ioapic_destroy(kvm); 6075 kvm_pic_destroy(kvm); 6076 goto create_irqchip_unlock; 6077 } 6078 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 6079 smp_wmb(); 6080 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 6081 create_irqchip_unlock: 6082 mutex_unlock(&kvm->lock); 6083 break; 6084 } 6085 case KVM_CREATE_PIT: 6086 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 6087 goto create_pit; 6088 case KVM_CREATE_PIT2: 6089 r = -EFAULT; 6090 if (copy_from_user(&u.pit_config, argp, 6091 sizeof(struct kvm_pit_config))) 6092 goto out; 6093 create_pit: 6094 mutex_lock(&kvm->lock); 6095 r = -EEXIST; 6096 if (kvm->arch.vpit) 6097 goto create_pit_unlock; 6098 r = -ENOMEM; 6099 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 6100 if (kvm->arch.vpit) 6101 r = 0; 6102 create_pit_unlock: 6103 mutex_unlock(&kvm->lock); 6104 break; 6105 case KVM_GET_IRQCHIP: { 6106 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 6107 struct kvm_irqchip *chip; 6108 6109 chip = memdup_user(argp, sizeof(*chip)); 6110 if (IS_ERR(chip)) { 6111 r = PTR_ERR(chip); 6112 goto out; 6113 } 6114 6115 r = -ENXIO; 6116 if (!irqchip_kernel(kvm)) 6117 goto get_irqchip_out; 6118 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 6119 if (r) 6120 goto get_irqchip_out; 6121 r = -EFAULT; 6122 if (copy_to_user(argp, chip, sizeof(*chip))) 6123 goto get_irqchip_out; 6124 r = 0; 6125 get_irqchip_out: 6126 kfree(chip); 6127 break; 6128 } 6129 case KVM_SET_IRQCHIP: { 6130 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 6131 struct kvm_irqchip *chip; 6132 6133 chip = memdup_user(argp, sizeof(*chip)); 6134 if (IS_ERR(chip)) { 6135 r = PTR_ERR(chip); 6136 goto out; 6137 } 6138 6139 r = -ENXIO; 6140 if (!irqchip_kernel(kvm)) 6141 goto set_irqchip_out; 6142 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 6143 set_irqchip_out: 6144 kfree(chip); 6145 break; 6146 } 6147 case KVM_GET_PIT: { 6148 r = -EFAULT; 6149 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 6150 goto out; 6151 r = -ENXIO; 6152 if (!kvm->arch.vpit) 6153 goto out; 6154 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 6155 if (r) 6156 goto out; 6157 r = -EFAULT; 6158 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 6159 goto out; 6160 r = 0; 6161 break; 6162 } 6163 case KVM_SET_PIT: { 6164 r = -EFAULT; 6165 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 6166 goto out; 6167 mutex_lock(&kvm->lock); 6168 r = -ENXIO; 6169 if (!kvm->arch.vpit) 6170 goto set_pit_out; 6171 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 6172 set_pit_out: 6173 mutex_unlock(&kvm->lock); 6174 break; 6175 } 6176 case KVM_GET_PIT2: { 6177 r = -ENXIO; 6178 if (!kvm->arch.vpit) 6179 goto out; 6180 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 6181 if (r) 6182 goto out; 6183 r = -EFAULT; 6184 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 6185 goto out; 6186 r = 0; 6187 break; 6188 } 6189 case KVM_SET_PIT2: { 6190 r = -EFAULT; 6191 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 6192 goto out; 6193 mutex_lock(&kvm->lock); 6194 r = -ENXIO; 6195 if (!kvm->arch.vpit) 6196 goto set_pit2_out; 6197 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 6198 set_pit2_out: 6199 mutex_unlock(&kvm->lock); 6200 break; 6201 } 6202 case KVM_REINJECT_CONTROL: { 6203 struct kvm_reinject_control control; 6204 r = -EFAULT; 6205 if (copy_from_user(&control, argp, sizeof(control))) 6206 goto out; 6207 r = -ENXIO; 6208 if (!kvm->arch.vpit) 6209 goto out; 6210 r = kvm_vm_ioctl_reinject(kvm, &control); 6211 break; 6212 } 6213 case KVM_SET_BOOT_CPU_ID: 6214 r = 0; 6215 mutex_lock(&kvm->lock); 6216 if (kvm->created_vcpus) 6217 r = -EBUSY; 6218 else 6219 kvm->arch.bsp_vcpu_id = arg; 6220 mutex_unlock(&kvm->lock); 6221 break; 6222 #ifdef CONFIG_KVM_XEN 6223 case KVM_XEN_HVM_CONFIG: { 6224 struct kvm_xen_hvm_config xhc; 6225 r = -EFAULT; 6226 if (copy_from_user(&xhc, argp, sizeof(xhc))) 6227 goto out; 6228 r = kvm_xen_hvm_config(kvm, &xhc); 6229 break; 6230 } 6231 case KVM_XEN_HVM_GET_ATTR: { 6232 struct kvm_xen_hvm_attr xha; 6233 6234 r = -EFAULT; 6235 if (copy_from_user(&xha, argp, sizeof(xha))) 6236 goto out; 6237 r = kvm_xen_hvm_get_attr(kvm, &xha); 6238 if (!r && copy_to_user(argp, &xha, sizeof(xha))) 6239 r = -EFAULT; 6240 break; 6241 } 6242 case KVM_XEN_HVM_SET_ATTR: { 6243 struct kvm_xen_hvm_attr xha; 6244 6245 r = -EFAULT; 6246 if (copy_from_user(&xha, argp, sizeof(xha))) 6247 goto out; 6248 r = kvm_xen_hvm_set_attr(kvm, &xha); 6249 break; 6250 } 6251 #endif 6252 case KVM_SET_CLOCK: 6253 r = kvm_vm_ioctl_set_clock(kvm, argp); 6254 break; 6255 case KVM_GET_CLOCK: 6256 r = kvm_vm_ioctl_get_clock(kvm, argp); 6257 break; 6258 case KVM_MEMORY_ENCRYPT_OP: { 6259 r = -ENOTTY; 6260 if (kvm_x86_ops.mem_enc_op) 6261 r = static_call(kvm_x86_mem_enc_op)(kvm, argp); 6262 break; 6263 } 6264 case KVM_MEMORY_ENCRYPT_REG_REGION: { 6265 struct kvm_enc_region region; 6266 6267 r = -EFAULT; 6268 if (copy_from_user(®ion, argp, sizeof(region))) 6269 goto out; 6270 6271 r = -ENOTTY; 6272 if (kvm_x86_ops.mem_enc_reg_region) 6273 r = static_call(kvm_x86_mem_enc_reg_region)(kvm, ®ion); 6274 break; 6275 } 6276 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 6277 struct kvm_enc_region region; 6278 6279 r = -EFAULT; 6280 if (copy_from_user(®ion, argp, sizeof(region))) 6281 goto out; 6282 6283 r = -ENOTTY; 6284 if (kvm_x86_ops.mem_enc_unreg_region) 6285 r = static_call(kvm_x86_mem_enc_unreg_region)(kvm, ®ion); 6286 break; 6287 } 6288 case KVM_HYPERV_EVENTFD: { 6289 struct kvm_hyperv_eventfd hvevfd; 6290 6291 r = -EFAULT; 6292 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 6293 goto out; 6294 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 6295 break; 6296 } 6297 case KVM_SET_PMU_EVENT_FILTER: 6298 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); 6299 break; 6300 case KVM_X86_SET_MSR_FILTER: 6301 r = kvm_vm_ioctl_set_msr_filter(kvm, argp); 6302 break; 6303 default: 6304 r = -ENOTTY; 6305 } 6306 out: 6307 return r; 6308 } 6309 6310 static void kvm_init_msr_list(void) 6311 { 6312 struct x86_pmu_capability x86_pmu; 6313 u32 dummy[2]; 6314 unsigned i; 6315 6316 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, 6317 "Please update the fixed PMCs in msrs_to_saved_all[]"); 6318 6319 perf_get_x86_pmu_capability(&x86_pmu); 6320 6321 num_msrs_to_save = 0; 6322 num_emulated_msrs = 0; 6323 num_msr_based_features = 0; 6324 6325 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { 6326 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) 6327 continue; 6328 6329 /* 6330 * Even MSRs that are valid in the host may not be exposed 6331 * to the guests in some cases. 6332 */ 6333 switch (msrs_to_save_all[i]) { 6334 case MSR_IA32_BNDCFGS: 6335 if (!kvm_mpx_supported()) 6336 continue; 6337 break; 6338 case MSR_TSC_AUX: 6339 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && 6340 !kvm_cpu_cap_has(X86_FEATURE_RDPID)) 6341 continue; 6342 break; 6343 case MSR_IA32_UMWAIT_CONTROL: 6344 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) 6345 continue; 6346 break; 6347 case MSR_IA32_RTIT_CTL: 6348 case MSR_IA32_RTIT_STATUS: 6349 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) 6350 continue; 6351 break; 6352 case MSR_IA32_RTIT_CR3_MATCH: 6353 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6354 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 6355 continue; 6356 break; 6357 case MSR_IA32_RTIT_OUTPUT_BASE: 6358 case MSR_IA32_RTIT_OUTPUT_MASK: 6359 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6360 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 6361 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 6362 continue; 6363 break; 6364 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 6365 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6366 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= 6367 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 6368 continue; 6369 break; 6370 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: 6371 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= 6372 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 6373 continue; 6374 break; 6375 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: 6376 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= 6377 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 6378 continue; 6379 break; 6380 default: 6381 break; 6382 } 6383 6384 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; 6385 } 6386 6387 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { 6388 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) 6389 continue; 6390 6391 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; 6392 } 6393 6394 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { 6395 struct kvm_msr_entry msr; 6396 6397 msr.index = msr_based_features_all[i]; 6398 if (kvm_get_msr_feature(&msr)) 6399 continue; 6400 6401 msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; 6402 } 6403 } 6404 6405 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 6406 const void *v) 6407 { 6408 int handled = 0; 6409 int n; 6410 6411 do { 6412 n = min(len, 8); 6413 if (!(lapic_in_kernel(vcpu) && 6414 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 6415 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 6416 break; 6417 handled += n; 6418 addr += n; 6419 len -= n; 6420 v += n; 6421 } while (len); 6422 6423 return handled; 6424 } 6425 6426 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 6427 { 6428 int handled = 0; 6429 int n; 6430 6431 do { 6432 n = min(len, 8); 6433 if (!(lapic_in_kernel(vcpu) && 6434 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 6435 addr, n, v)) 6436 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 6437 break; 6438 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 6439 handled += n; 6440 addr += n; 6441 len -= n; 6442 v += n; 6443 } while (len); 6444 6445 return handled; 6446 } 6447 6448 static void kvm_set_segment(struct kvm_vcpu *vcpu, 6449 struct kvm_segment *var, int seg) 6450 { 6451 static_call(kvm_x86_set_segment)(vcpu, var, seg); 6452 } 6453 6454 void kvm_get_segment(struct kvm_vcpu *vcpu, 6455 struct kvm_segment *var, int seg) 6456 { 6457 static_call(kvm_x86_get_segment)(vcpu, var, seg); 6458 } 6459 6460 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 6461 struct x86_exception *exception) 6462 { 6463 gpa_t t_gpa; 6464 6465 BUG_ON(!mmu_is_nested(vcpu)); 6466 6467 /* NPT walks are always user-walks */ 6468 access |= PFERR_USER_MASK; 6469 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); 6470 6471 return t_gpa; 6472 } 6473 6474 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 6475 struct x86_exception *exception) 6476 { 6477 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6478 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6479 } 6480 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); 6481 6482 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 6483 struct x86_exception *exception) 6484 { 6485 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6486 access |= PFERR_FETCH_MASK; 6487 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6488 } 6489 6490 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 6491 struct x86_exception *exception) 6492 { 6493 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6494 access |= PFERR_WRITE_MASK; 6495 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6496 } 6497 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); 6498 6499 /* uses this to access any guest's mapped memory without checking CPL */ 6500 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 6501 struct x86_exception *exception) 6502 { 6503 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 6504 } 6505 6506 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6507 struct kvm_vcpu *vcpu, u32 access, 6508 struct x86_exception *exception) 6509 { 6510 void *data = val; 6511 int r = X86EMUL_CONTINUE; 6512 6513 while (bytes) { 6514 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 6515 exception); 6516 unsigned offset = addr & (PAGE_SIZE-1); 6517 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 6518 int ret; 6519 6520 if (gpa == UNMAPPED_GVA) 6521 return X86EMUL_PROPAGATE_FAULT; 6522 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 6523 offset, toread); 6524 if (ret < 0) { 6525 r = X86EMUL_IO_NEEDED; 6526 goto out; 6527 } 6528 6529 bytes -= toread; 6530 data += toread; 6531 addr += toread; 6532 } 6533 out: 6534 return r; 6535 } 6536 6537 /* used for instruction fetching */ 6538 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 6539 gva_t addr, void *val, unsigned int bytes, 6540 struct x86_exception *exception) 6541 { 6542 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6543 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6544 unsigned offset; 6545 int ret; 6546 6547 /* Inline kvm_read_guest_virt_helper for speed. */ 6548 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 6549 exception); 6550 if (unlikely(gpa == UNMAPPED_GVA)) 6551 return X86EMUL_PROPAGATE_FAULT; 6552 6553 offset = addr & (PAGE_SIZE-1); 6554 if (WARN_ON(offset + bytes > PAGE_SIZE)) 6555 bytes = (unsigned)PAGE_SIZE - offset; 6556 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 6557 offset, bytes); 6558 if (unlikely(ret < 0)) 6559 return X86EMUL_IO_NEEDED; 6560 6561 return X86EMUL_CONTINUE; 6562 } 6563 6564 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 6565 gva_t addr, void *val, unsigned int bytes, 6566 struct x86_exception *exception) 6567 { 6568 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6569 6570 /* 6571 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 6572 * is returned, but our callers are not ready for that and they blindly 6573 * call kvm_inject_page_fault. Ensure that they at least do not leak 6574 * uninitialized kernel stack memory into cr2 and error code. 6575 */ 6576 memset(exception, 0, sizeof(*exception)); 6577 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 6578 exception); 6579 } 6580 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 6581 6582 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 6583 gva_t addr, void *val, unsigned int bytes, 6584 struct x86_exception *exception, bool system) 6585 { 6586 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6587 u32 access = 0; 6588 6589 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6590 access |= PFERR_USER_MASK; 6591 6592 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 6593 } 6594 6595 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 6596 unsigned long addr, void *val, unsigned int bytes) 6597 { 6598 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6599 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 6600 6601 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 6602 } 6603 6604 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6605 struct kvm_vcpu *vcpu, u32 access, 6606 struct x86_exception *exception) 6607 { 6608 void *data = val; 6609 int r = X86EMUL_CONTINUE; 6610 6611 while (bytes) { 6612 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 6613 access, 6614 exception); 6615 unsigned offset = addr & (PAGE_SIZE-1); 6616 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 6617 int ret; 6618 6619 if (gpa == UNMAPPED_GVA) 6620 return X86EMUL_PROPAGATE_FAULT; 6621 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 6622 if (ret < 0) { 6623 r = X86EMUL_IO_NEEDED; 6624 goto out; 6625 } 6626 6627 bytes -= towrite; 6628 data += towrite; 6629 addr += towrite; 6630 } 6631 out: 6632 return r; 6633 } 6634 6635 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 6636 unsigned int bytes, struct x86_exception *exception, 6637 bool system) 6638 { 6639 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6640 u32 access = PFERR_WRITE_MASK; 6641 6642 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6643 access |= PFERR_USER_MASK; 6644 6645 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6646 access, exception); 6647 } 6648 6649 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 6650 unsigned int bytes, struct x86_exception *exception) 6651 { 6652 /* kvm_write_guest_virt_system can pull in tons of pages. */ 6653 vcpu->arch.l1tf_flush_l1d = true; 6654 6655 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6656 PFERR_WRITE_MASK, exception); 6657 } 6658 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 6659 6660 int handle_ud(struct kvm_vcpu *vcpu) 6661 { 6662 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; 6663 int emul_type = EMULTYPE_TRAP_UD; 6664 char sig[5]; /* ud2; .ascii "kvm" */ 6665 struct x86_exception e; 6666 6667 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, NULL, 0))) 6668 return 1; 6669 6670 if (force_emulation_prefix && 6671 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 6672 sig, sizeof(sig), &e) == 0 && 6673 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { 6674 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 6675 emul_type = EMULTYPE_TRAP_UD_FORCED; 6676 } 6677 6678 return kvm_emulate_instruction(vcpu, emul_type); 6679 } 6680 EXPORT_SYMBOL_GPL(handle_ud); 6681 6682 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6683 gpa_t gpa, bool write) 6684 { 6685 /* For APIC access vmexit */ 6686 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 6687 return 1; 6688 6689 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 6690 trace_vcpu_match_mmio(gva, gpa, write, true); 6691 return 1; 6692 } 6693 6694 return 0; 6695 } 6696 6697 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6698 gpa_t *gpa, struct x86_exception *exception, 6699 bool write) 6700 { 6701 u32 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) 6702 | (write ? PFERR_WRITE_MASK : 0); 6703 6704 /* 6705 * currently PKRU is only applied to ept enabled guest so 6706 * there is no pkey in EPT page table for L1 guest or EPT 6707 * shadow page table for L2 guest. 6708 */ 6709 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) || 6710 !permission_fault(vcpu, vcpu->arch.walk_mmu, 6711 vcpu->arch.mmio_access, 0, access))) { 6712 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 6713 (gva & (PAGE_SIZE - 1)); 6714 trace_vcpu_match_mmio(gva, *gpa, write, false); 6715 return 1; 6716 } 6717 6718 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6719 6720 if (*gpa == UNMAPPED_GVA) 6721 return -1; 6722 6723 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 6724 } 6725 6726 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 6727 const void *val, int bytes) 6728 { 6729 int ret; 6730 6731 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 6732 if (ret < 0) 6733 return 0; 6734 kvm_page_track_write(vcpu, gpa, val, bytes); 6735 return 1; 6736 } 6737 6738 struct read_write_emulator_ops { 6739 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 6740 int bytes); 6741 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 6742 void *val, int bytes); 6743 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6744 int bytes, void *val); 6745 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6746 void *val, int bytes); 6747 bool write; 6748 }; 6749 6750 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 6751 { 6752 if (vcpu->mmio_read_completed) { 6753 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 6754 vcpu->mmio_fragments[0].gpa, val); 6755 vcpu->mmio_read_completed = 0; 6756 return 1; 6757 } 6758 6759 return 0; 6760 } 6761 6762 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6763 void *val, int bytes) 6764 { 6765 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 6766 } 6767 6768 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6769 void *val, int bytes) 6770 { 6771 return emulator_write_phys(vcpu, gpa, val, bytes); 6772 } 6773 6774 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 6775 { 6776 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 6777 return vcpu_mmio_write(vcpu, gpa, bytes, val); 6778 } 6779 6780 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6781 void *val, int bytes) 6782 { 6783 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 6784 return X86EMUL_IO_NEEDED; 6785 } 6786 6787 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6788 void *val, int bytes) 6789 { 6790 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 6791 6792 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 6793 return X86EMUL_CONTINUE; 6794 } 6795 6796 static const struct read_write_emulator_ops read_emultor = { 6797 .read_write_prepare = read_prepare, 6798 .read_write_emulate = read_emulate, 6799 .read_write_mmio = vcpu_mmio_read, 6800 .read_write_exit_mmio = read_exit_mmio, 6801 }; 6802 6803 static const struct read_write_emulator_ops write_emultor = { 6804 .read_write_emulate = write_emulate, 6805 .read_write_mmio = write_mmio, 6806 .read_write_exit_mmio = write_exit_mmio, 6807 .write = true, 6808 }; 6809 6810 static int emulator_read_write_onepage(unsigned long addr, void *val, 6811 unsigned int bytes, 6812 struct x86_exception *exception, 6813 struct kvm_vcpu *vcpu, 6814 const struct read_write_emulator_ops *ops) 6815 { 6816 gpa_t gpa; 6817 int handled, ret; 6818 bool write = ops->write; 6819 struct kvm_mmio_fragment *frag; 6820 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6821 6822 /* 6823 * If the exit was due to a NPF we may already have a GPA. 6824 * If the GPA is present, use it to avoid the GVA to GPA table walk. 6825 * Note, this cannot be used on string operations since string 6826 * operation using rep will only have the initial GPA from the NPF 6827 * occurred. 6828 */ 6829 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && 6830 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { 6831 gpa = ctxt->gpa_val; 6832 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 6833 } else { 6834 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 6835 if (ret < 0) 6836 return X86EMUL_PROPAGATE_FAULT; 6837 } 6838 6839 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 6840 return X86EMUL_CONTINUE; 6841 6842 /* 6843 * Is this MMIO handled locally? 6844 */ 6845 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 6846 if (handled == bytes) 6847 return X86EMUL_CONTINUE; 6848 6849 gpa += handled; 6850 bytes -= handled; 6851 val += handled; 6852 6853 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 6854 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 6855 frag->gpa = gpa; 6856 frag->data = val; 6857 frag->len = bytes; 6858 return X86EMUL_CONTINUE; 6859 } 6860 6861 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 6862 unsigned long addr, 6863 void *val, unsigned int bytes, 6864 struct x86_exception *exception, 6865 const struct read_write_emulator_ops *ops) 6866 { 6867 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6868 gpa_t gpa; 6869 int rc; 6870 6871 if (ops->read_write_prepare && 6872 ops->read_write_prepare(vcpu, val, bytes)) 6873 return X86EMUL_CONTINUE; 6874 6875 vcpu->mmio_nr_fragments = 0; 6876 6877 /* Crossing a page boundary? */ 6878 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 6879 int now; 6880 6881 now = -addr & ~PAGE_MASK; 6882 rc = emulator_read_write_onepage(addr, val, now, exception, 6883 vcpu, ops); 6884 6885 if (rc != X86EMUL_CONTINUE) 6886 return rc; 6887 addr += now; 6888 if (ctxt->mode != X86EMUL_MODE_PROT64) 6889 addr = (u32)addr; 6890 val += now; 6891 bytes -= now; 6892 } 6893 6894 rc = emulator_read_write_onepage(addr, val, bytes, exception, 6895 vcpu, ops); 6896 if (rc != X86EMUL_CONTINUE) 6897 return rc; 6898 6899 if (!vcpu->mmio_nr_fragments) 6900 return rc; 6901 6902 gpa = vcpu->mmio_fragments[0].gpa; 6903 6904 vcpu->mmio_needed = 1; 6905 vcpu->mmio_cur_fragment = 0; 6906 6907 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 6908 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 6909 vcpu->run->exit_reason = KVM_EXIT_MMIO; 6910 vcpu->run->mmio.phys_addr = gpa; 6911 6912 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 6913 } 6914 6915 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 6916 unsigned long addr, 6917 void *val, 6918 unsigned int bytes, 6919 struct x86_exception *exception) 6920 { 6921 return emulator_read_write(ctxt, addr, val, bytes, 6922 exception, &read_emultor); 6923 } 6924 6925 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 6926 unsigned long addr, 6927 const void *val, 6928 unsigned int bytes, 6929 struct x86_exception *exception) 6930 { 6931 return emulator_read_write(ctxt, addr, (void *)val, bytes, 6932 exception, &write_emultor); 6933 } 6934 6935 #define CMPXCHG_TYPE(t, ptr, old, new) \ 6936 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 6937 6938 #ifdef CONFIG_X86_64 6939 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 6940 #else 6941 # define CMPXCHG64(ptr, old, new) \ 6942 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 6943 #endif 6944 6945 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 6946 unsigned long addr, 6947 const void *old, 6948 const void *new, 6949 unsigned int bytes, 6950 struct x86_exception *exception) 6951 { 6952 struct kvm_host_map map; 6953 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6954 u64 page_line_mask; 6955 gpa_t gpa; 6956 char *kaddr; 6957 bool exchanged; 6958 6959 /* guests cmpxchg8b have to be emulated atomically */ 6960 if (bytes > 8 || (bytes & (bytes - 1))) 6961 goto emul_write; 6962 6963 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 6964 6965 if (gpa == UNMAPPED_GVA || 6966 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 6967 goto emul_write; 6968 6969 /* 6970 * Emulate the atomic as a straight write to avoid #AC if SLD is 6971 * enabled in the host and the access splits a cache line. 6972 */ 6973 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 6974 page_line_mask = ~(cache_line_size() - 1); 6975 else 6976 page_line_mask = PAGE_MASK; 6977 6978 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) 6979 goto emul_write; 6980 6981 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) 6982 goto emul_write; 6983 6984 kaddr = map.hva + offset_in_page(gpa); 6985 6986 switch (bytes) { 6987 case 1: 6988 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 6989 break; 6990 case 2: 6991 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 6992 break; 6993 case 4: 6994 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 6995 break; 6996 case 8: 6997 exchanged = CMPXCHG64(kaddr, old, new); 6998 break; 6999 default: 7000 BUG(); 7001 } 7002 7003 kvm_vcpu_unmap(vcpu, &map, true); 7004 7005 if (!exchanged) 7006 return X86EMUL_CMPXCHG_FAILED; 7007 7008 kvm_page_track_write(vcpu, gpa, new, bytes); 7009 7010 return X86EMUL_CONTINUE; 7011 7012 emul_write: 7013 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 7014 7015 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 7016 } 7017 7018 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 7019 { 7020 int r = 0, i; 7021 7022 for (i = 0; i < vcpu->arch.pio.count; i++) { 7023 if (vcpu->arch.pio.in) 7024 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 7025 vcpu->arch.pio.size, pd); 7026 else 7027 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 7028 vcpu->arch.pio.port, vcpu->arch.pio.size, 7029 pd); 7030 if (r) 7031 break; 7032 pd += vcpu->arch.pio.size; 7033 } 7034 return r; 7035 } 7036 7037 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 7038 unsigned short port, 7039 unsigned int count, bool in) 7040 { 7041 vcpu->arch.pio.port = port; 7042 vcpu->arch.pio.in = in; 7043 vcpu->arch.pio.count = count; 7044 vcpu->arch.pio.size = size; 7045 7046 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) 7047 return 1; 7048 7049 vcpu->run->exit_reason = KVM_EXIT_IO; 7050 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 7051 vcpu->run->io.size = size; 7052 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 7053 vcpu->run->io.count = count; 7054 vcpu->run->io.port = port; 7055 7056 return 0; 7057 } 7058 7059 static int __emulator_pio_in(struct kvm_vcpu *vcpu, int size, 7060 unsigned short port, unsigned int count) 7061 { 7062 WARN_ON(vcpu->arch.pio.count); 7063 memset(vcpu->arch.pio_data, 0, size * count); 7064 return emulator_pio_in_out(vcpu, size, port, count, true); 7065 } 7066 7067 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val) 7068 { 7069 int size = vcpu->arch.pio.size; 7070 unsigned count = vcpu->arch.pio.count; 7071 memcpy(val, vcpu->arch.pio_data, size * count); 7072 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data); 7073 vcpu->arch.pio.count = 0; 7074 } 7075 7076 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, 7077 unsigned short port, void *val, unsigned int count) 7078 { 7079 if (vcpu->arch.pio.count) { 7080 /* Complete previous iteration. */ 7081 } else { 7082 int r = __emulator_pio_in(vcpu, size, port, count); 7083 if (!r) 7084 return r; 7085 7086 /* Results already available, fall through. */ 7087 } 7088 7089 WARN_ON(count != vcpu->arch.pio.count); 7090 complete_emulator_pio_in(vcpu, val); 7091 return 1; 7092 } 7093 7094 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 7095 int size, unsigned short port, void *val, 7096 unsigned int count) 7097 { 7098 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); 7099 7100 } 7101 7102 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, 7103 unsigned short port, const void *val, 7104 unsigned int count) 7105 { 7106 int ret; 7107 7108 memcpy(vcpu->arch.pio_data, val, size * count); 7109 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 7110 ret = emulator_pio_in_out(vcpu, size, port, count, false); 7111 if (ret) 7112 vcpu->arch.pio.count = 0; 7113 7114 return ret; 7115 } 7116 7117 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 7118 int size, unsigned short port, 7119 const void *val, unsigned int count) 7120 { 7121 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); 7122 } 7123 7124 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 7125 { 7126 return static_call(kvm_x86_get_segment_base)(vcpu, seg); 7127 } 7128 7129 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 7130 { 7131 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 7132 } 7133 7134 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 7135 { 7136 if (!need_emulate_wbinvd(vcpu)) 7137 return X86EMUL_CONTINUE; 7138 7139 if (static_call(kvm_x86_has_wbinvd_exit)()) { 7140 int cpu = get_cpu(); 7141 7142 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 7143 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, 7144 wbinvd_ipi, NULL, 1); 7145 put_cpu(); 7146 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 7147 } else 7148 wbinvd(); 7149 return X86EMUL_CONTINUE; 7150 } 7151 7152 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 7153 { 7154 kvm_emulate_wbinvd_noskip(vcpu); 7155 return kvm_skip_emulated_instruction(vcpu); 7156 } 7157 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 7158 7159 7160 7161 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 7162 { 7163 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 7164 } 7165 7166 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 7167 unsigned long *dest) 7168 { 7169 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 7170 } 7171 7172 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 7173 unsigned long value) 7174 { 7175 7176 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 7177 } 7178 7179 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 7180 { 7181 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 7182 } 7183 7184 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 7185 { 7186 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7187 unsigned long value; 7188 7189 switch (cr) { 7190 case 0: 7191 value = kvm_read_cr0(vcpu); 7192 break; 7193 case 2: 7194 value = vcpu->arch.cr2; 7195 break; 7196 case 3: 7197 value = kvm_read_cr3(vcpu); 7198 break; 7199 case 4: 7200 value = kvm_read_cr4(vcpu); 7201 break; 7202 case 8: 7203 value = kvm_get_cr8(vcpu); 7204 break; 7205 default: 7206 kvm_err("%s: unexpected cr %u\n", __func__, cr); 7207 return 0; 7208 } 7209 7210 return value; 7211 } 7212 7213 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 7214 { 7215 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7216 int res = 0; 7217 7218 switch (cr) { 7219 case 0: 7220 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 7221 break; 7222 case 2: 7223 vcpu->arch.cr2 = val; 7224 break; 7225 case 3: 7226 res = kvm_set_cr3(vcpu, val); 7227 break; 7228 case 4: 7229 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 7230 break; 7231 case 8: 7232 res = kvm_set_cr8(vcpu, val); 7233 break; 7234 default: 7235 kvm_err("%s: unexpected cr %u\n", __func__, cr); 7236 res = -1; 7237 } 7238 7239 return res; 7240 } 7241 7242 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 7243 { 7244 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); 7245 } 7246 7247 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7248 { 7249 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); 7250 } 7251 7252 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7253 { 7254 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); 7255 } 7256 7257 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7258 { 7259 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); 7260 } 7261 7262 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7263 { 7264 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); 7265 } 7266 7267 static unsigned long emulator_get_cached_segment_base( 7268 struct x86_emulate_ctxt *ctxt, int seg) 7269 { 7270 return get_segment_base(emul_to_vcpu(ctxt), seg); 7271 } 7272 7273 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 7274 struct desc_struct *desc, u32 *base3, 7275 int seg) 7276 { 7277 struct kvm_segment var; 7278 7279 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 7280 *selector = var.selector; 7281 7282 if (var.unusable) { 7283 memset(desc, 0, sizeof(*desc)); 7284 if (base3) 7285 *base3 = 0; 7286 return false; 7287 } 7288 7289 if (var.g) 7290 var.limit >>= 12; 7291 set_desc_limit(desc, var.limit); 7292 set_desc_base(desc, (unsigned long)var.base); 7293 #ifdef CONFIG_X86_64 7294 if (base3) 7295 *base3 = var.base >> 32; 7296 #endif 7297 desc->type = var.type; 7298 desc->s = var.s; 7299 desc->dpl = var.dpl; 7300 desc->p = var.present; 7301 desc->avl = var.avl; 7302 desc->l = var.l; 7303 desc->d = var.db; 7304 desc->g = var.g; 7305 7306 return true; 7307 } 7308 7309 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 7310 struct desc_struct *desc, u32 base3, 7311 int seg) 7312 { 7313 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7314 struct kvm_segment var; 7315 7316 var.selector = selector; 7317 var.base = get_desc_base(desc); 7318 #ifdef CONFIG_X86_64 7319 var.base |= ((u64)base3) << 32; 7320 #endif 7321 var.limit = get_desc_limit(desc); 7322 if (desc->g) 7323 var.limit = (var.limit << 12) | 0xfff; 7324 var.type = desc->type; 7325 var.dpl = desc->dpl; 7326 var.db = desc->d; 7327 var.s = desc->s; 7328 var.l = desc->l; 7329 var.g = desc->g; 7330 var.avl = desc->avl; 7331 var.present = desc->p; 7332 var.unusable = !var.present; 7333 var.padding = 0; 7334 7335 kvm_set_segment(vcpu, &var, seg); 7336 return; 7337 } 7338 7339 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 7340 u32 msr_index, u64 *pdata) 7341 { 7342 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7343 int r; 7344 7345 r = kvm_get_msr(vcpu, msr_index, pdata); 7346 7347 if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) { 7348 /* Bounce to user space */ 7349 return X86EMUL_IO_NEEDED; 7350 } 7351 7352 return r; 7353 } 7354 7355 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 7356 u32 msr_index, u64 data) 7357 { 7358 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7359 int r; 7360 7361 r = kvm_set_msr(vcpu, msr_index, data); 7362 7363 if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) { 7364 /* Bounce to user space */ 7365 return X86EMUL_IO_NEEDED; 7366 } 7367 7368 return r; 7369 } 7370 7371 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 7372 { 7373 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7374 7375 return vcpu->arch.smbase; 7376 } 7377 7378 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 7379 { 7380 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7381 7382 vcpu->arch.smbase = smbase; 7383 } 7384 7385 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 7386 u32 pmc) 7387 { 7388 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc)) 7389 return 0; 7390 return -EINVAL; 7391 } 7392 7393 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 7394 u32 pmc, u64 *pdata) 7395 { 7396 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 7397 } 7398 7399 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 7400 { 7401 emul_to_vcpu(ctxt)->arch.halt_request = 1; 7402 } 7403 7404 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 7405 struct x86_instruction_info *info, 7406 enum x86_intercept_stage stage) 7407 { 7408 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, 7409 &ctxt->exception); 7410 } 7411 7412 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 7413 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, 7414 bool exact_only) 7415 { 7416 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); 7417 } 7418 7419 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) 7420 { 7421 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); 7422 } 7423 7424 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) 7425 { 7426 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); 7427 } 7428 7429 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) 7430 { 7431 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); 7432 } 7433 7434 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 7435 { 7436 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); 7437 } 7438 7439 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 7440 { 7441 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); 7442 } 7443 7444 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 7445 { 7446 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); 7447 } 7448 7449 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 7450 { 7451 return emul_to_vcpu(ctxt)->arch.hflags; 7452 } 7453 7454 static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt) 7455 { 7456 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7457 7458 kvm_smm_changed(vcpu, false); 7459 } 7460 7461 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt, 7462 const char *smstate) 7463 { 7464 return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate); 7465 } 7466 7467 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) 7468 { 7469 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); 7470 } 7471 7472 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) 7473 { 7474 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); 7475 } 7476 7477 static const struct x86_emulate_ops emulate_ops = { 7478 .read_gpr = emulator_read_gpr, 7479 .write_gpr = emulator_write_gpr, 7480 .read_std = emulator_read_std, 7481 .write_std = emulator_write_std, 7482 .read_phys = kvm_read_guest_phys_system, 7483 .fetch = kvm_fetch_guest_virt, 7484 .read_emulated = emulator_read_emulated, 7485 .write_emulated = emulator_write_emulated, 7486 .cmpxchg_emulated = emulator_cmpxchg_emulated, 7487 .invlpg = emulator_invlpg, 7488 .pio_in_emulated = emulator_pio_in_emulated, 7489 .pio_out_emulated = emulator_pio_out_emulated, 7490 .get_segment = emulator_get_segment, 7491 .set_segment = emulator_set_segment, 7492 .get_cached_segment_base = emulator_get_cached_segment_base, 7493 .get_gdt = emulator_get_gdt, 7494 .get_idt = emulator_get_idt, 7495 .set_gdt = emulator_set_gdt, 7496 .set_idt = emulator_set_idt, 7497 .get_cr = emulator_get_cr, 7498 .set_cr = emulator_set_cr, 7499 .cpl = emulator_get_cpl, 7500 .get_dr = emulator_get_dr, 7501 .set_dr = emulator_set_dr, 7502 .get_smbase = emulator_get_smbase, 7503 .set_smbase = emulator_set_smbase, 7504 .set_msr = emulator_set_msr, 7505 .get_msr = emulator_get_msr, 7506 .check_pmc = emulator_check_pmc, 7507 .read_pmc = emulator_read_pmc, 7508 .halt = emulator_halt, 7509 .wbinvd = emulator_wbinvd, 7510 .fix_hypercall = emulator_fix_hypercall, 7511 .intercept = emulator_intercept, 7512 .get_cpuid = emulator_get_cpuid, 7513 .guest_has_long_mode = emulator_guest_has_long_mode, 7514 .guest_has_movbe = emulator_guest_has_movbe, 7515 .guest_has_fxsr = emulator_guest_has_fxsr, 7516 .set_nmi_mask = emulator_set_nmi_mask, 7517 .get_hflags = emulator_get_hflags, 7518 .exiting_smm = emulator_exiting_smm, 7519 .leave_smm = emulator_leave_smm, 7520 .triple_fault = emulator_triple_fault, 7521 .set_xcr = emulator_set_xcr, 7522 }; 7523 7524 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 7525 { 7526 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 7527 /* 7528 * an sti; sti; sequence only disable interrupts for the first 7529 * instruction. So, if the last instruction, be it emulated or 7530 * not, left the system with the INT_STI flag enabled, it 7531 * means that the last instruction is an sti. We should not 7532 * leave the flag on in this case. The same goes for mov ss 7533 */ 7534 if (int_shadow & mask) 7535 mask = 0; 7536 if (unlikely(int_shadow || mask)) { 7537 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); 7538 if (!mask) 7539 kvm_make_request(KVM_REQ_EVENT, vcpu); 7540 } 7541 } 7542 7543 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 7544 { 7545 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7546 if (ctxt->exception.vector == PF_VECTOR) 7547 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); 7548 7549 if (ctxt->exception.error_code_valid) 7550 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 7551 ctxt->exception.error_code); 7552 else 7553 kvm_queue_exception(vcpu, ctxt->exception.vector); 7554 return false; 7555 } 7556 7557 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) 7558 { 7559 struct x86_emulate_ctxt *ctxt; 7560 7561 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); 7562 if (!ctxt) { 7563 pr_err("kvm: failed to allocate vcpu's emulator\n"); 7564 return NULL; 7565 } 7566 7567 ctxt->vcpu = vcpu; 7568 ctxt->ops = &emulate_ops; 7569 vcpu->arch.emulate_ctxt = ctxt; 7570 7571 return ctxt; 7572 } 7573 7574 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 7575 { 7576 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7577 int cs_db, cs_l; 7578 7579 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 7580 7581 ctxt->gpa_available = false; 7582 ctxt->eflags = kvm_get_rflags(vcpu); 7583 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 7584 7585 ctxt->eip = kvm_rip_read(vcpu); 7586 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 7587 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 7588 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 7589 cs_db ? X86EMUL_MODE_PROT32 : 7590 X86EMUL_MODE_PROT16; 7591 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 7592 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 7593 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 7594 7595 ctxt->interruptibility = 0; 7596 ctxt->have_exception = false; 7597 ctxt->exception.vector = -1; 7598 ctxt->perm_ok = false; 7599 7600 init_decode_cache(ctxt); 7601 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 7602 } 7603 7604 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 7605 { 7606 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7607 int ret; 7608 7609 init_emulate_ctxt(vcpu); 7610 7611 ctxt->op_bytes = 2; 7612 ctxt->ad_bytes = 2; 7613 ctxt->_eip = ctxt->eip + inc_eip; 7614 ret = emulate_int_real(ctxt, irq); 7615 7616 if (ret != X86EMUL_CONTINUE) { 7617 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 7618 } else { 7619 ctxt->eip = ctxt->_eip; 7620 kvm_rip_write(vcpu, ctxt->eip); 7621 kvm_set_rflags(vcpu, ctxt->eflags); 7622 } 7623 } 7624 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 7625 7626 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, 7627 u8 ndata, u8 *insn_bytes, u8 insn_size) 7628 { 7629 struct kvm_run *run = vcpu->run; 7630 u64 info[5]; 7631 u8 info_start; 7632 7633 /* 7634 * Zero the whole array used to retrieve the exit info, as casting to 7635 * u32 for select entries will leave some chunks uninitialized. 7636 */ 7637 memset(&info, 0, sizeof(info)); 7638 7639 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1], 7640 &info[2], (u32 *)&info[3], 7641 (u32 *)&info[4]); 7642 7643 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 7644 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION; 7645 7646 /* 7647 * There's currently space for 13 entries, but 5 are used for the exit 7648 * reason and info. Restrict to 4 to reduce the maintenance burden 7649 * when expanding kvm_run.emulation_failure in the future. 7650 */ 7651 if (WARN_ON_ONCE(ndata > 4)) 7652 ndata = 4; 7653 7654 /* Always include the flags as a 'data' entry. */ 7655 info_start = 1; 7656 run->emulation_failure.flags = 0; 7657 7658 if (insn_size) { 7659 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) + 7660 sizeof(run->emulation_failure.insn_bytes) != 16)); 7661 info_start += 2; 7662 run->emulation_failure.flags |= 7663 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES; 7664 run->emulation_failure.insn_size = insn_size; 7665 memset(run->emulation_failure.insn_bytes, 0x90, 7666 sizeof(run->emulation_failure.insn_bytes)); 7667 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size); 7668 } 7669 7670 memcpy(&run->internal.data[info_start], info, sizeof(info)); 7671 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data, 7672 ndata * sizeof(data[0])); 7673 7674 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata; 7675 } 7676 7677 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu) 7678 { 7679 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7680 7681 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data, 7682 ctxt->fetch.end - ctxt->fetch.data); 7683 } 7684 7685 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, 7686 u8 ndata) 7687 { 7688 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0); 7689 } 7690 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit); 7691 7692 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu) 7693 { 7694 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0); 7695 } 7696 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit); 7697 7698 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 7699 { 7700 struct kvm *kvm = vcpu->kvm; 7701 7702 ++vcpu->stat.insn_emulation_fail; 7703 trace_kvm_emulate_insn_failed(vcpu); 7704 7705 if (emulation_type & EMULTYPE_VMWARE_GP) { 7706 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 7707 return 1; 7708 } 7709 7710 if (kvm->arch.exit_on_emulation_error || 7711 (emulation_type & EMULTYPE_SKIP)) { 7712 prepare_emulation_ctxt_failure_exit(vcpu); 7713 return 0; 7714 } 7715 7716 kvm_queue_exception(vcpu, UD_VECTOR); 7717 7718 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { 7719 prepare_emulation_ctxt_failure_exit(vcpu); 7720 return 0; 7721 } 7722 7723 return 1; 7724 } 7725 7726 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 7727 bool write_fault_to_shadow_pgtable, 7728 int emulation_type) 7729 { 7730 gpa_t gpa = cr2_or_gpa; 7731 kvm_pfn_t pfn; 7732 7733 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7734 return false; 7735 7736 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7737 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7738 return false; 7739 7740 if (!vcpu->arch.mmu->direct_map) { 7741 /* 7742 * Write permission should be allowed since only 7743 * write access need to be emulated. 7744 */ 7745 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 7746 7747 /* 7748 * If the mapping is invalid in guest, let cpu retry 7749 * it to generate fault. 7750 */ 7751 if (gpa == UNMAPPED_GVA) 7752 return true; 7753 } 7754 7755 /* 7756 * Do not retry the unhandleable instruction if it faults on the 7757 * readonly host memory, otherwise it will goto a infinite loop: 7758 * retry instruction -> write #PF -> emulation fail -> retry 7759 * instruction -> ... 7760 */ 7761 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 7762 7763 /* 7764 * If the instruction failed on the error pfn, it can not be fixed, 7765 * report the error to userspace. 7766 */ 7767 if (is_error_noslot_pfn(pfn)) 7768 return false; 7769 7770 kvm_release_pfn_clean(pfn); 7771 7772 /* The instructions are well-emulated on direct mmu. */ 7773 if (vcpu->arch.mmu->direct_map) { 7774 unsigned int indirect_shadow_pages; 7775 7776 write_lock(&vcpu->kvm->mmu_lock); 7777 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 7778 write_unlock(&vcpu->kvm->mmu_lock); 7779 7780 if (indirect_shadow_pages) 7781 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7782 7783 return true; 7784 } 7785 7786 /* 7787 * if emulation was due to access to shadowed page table 7788 * and it failed try to unshadow page and re-enter the 7789 * guest to let CPU execute the instruction. 7790 */ 7791 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7792 7793 /* 7794 * If the access faults on its page table, it can not 7795 * be fixed by unprotecting shadow page and it should 7796 * be reported to userspace. 7797 */ 7798 return !write_fault_to_shadow_pgtable; 7799 } 7800 7801 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 7802 gpa_t cr2_or_gpa, int emulation_type) 7803 { 7804 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7805 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; 7806 7807 last_retry_eip = vcpu->arch.last_retry_eip; 7808 last_retry_addr = vcpu->arch.last_retry_addr; 7809 7810 /* 7811 * If the emulation is caused by #PF and it is non-page_table 7812 * writing instruction, it means the VM-EXIT is caused by shadow 7813 * page protected, we can zap the shadow page and retry this 7814 * instruction directly. 7815 * 7816 * Note: if the guest uses a non-page-table modifying instruction 7817 * on the PDE that points to the instruction, then we will unmap 7818 * the instruction and go to an infinite loop. So, we cache the 7819 * last retried eip and the last fault address, if we meet the eip 7820 * and the address again, we can break out of the potential infinite 7821 * loop. 7822 */ 7823 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 7824 7825 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7826 return false; 7827 7828 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7829 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7830 return false; 7831 7832 if (x86_page_table_writing_insn(ctxt)) 7833 return false; 7834 7835 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) 7836 return false; 7837 7838 vcpu->arch.last_retry_eip = ctxt->eip; 7839 vcpu->arch.last_retry_addr = cr2_or_gpa; 7840 7841 if (!vcpu->arch.mmu->direct_map) 7842 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 7843 7844 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7845 7846 return true; 7847 } 7848 7849 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 7850 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 7851 7852 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm) 7853 { 7854 trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm); 7855 7856 if (entering_smm) { 7857 vcpu->arch.hflags |= HF_SMM_MASK; 7858 } else { 7859 vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK); 7860 7861 /* Process a latched INIT or SMI, if any. */ 7862 kvm_make_request(KVM_REQ_EVENT, vcpu); 7863 7864 /* 7865 * Even if KVM_SET_SREGS2 loaded PDPTRs out of band, 7866 * on SMM exit we still need to reload them from 7867 * guest memory 7868 */ 7869 vcpu->arch.pdptrs_from_userspace = false; 7870 } 7871 7872 kvm_mmu_reset_context(vcpu); 7873 } 7874 7875 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 7876 unsigned long *db) 7877 { 7878 u32 dr6 = 0; 7879 int i; 7880 u32 enable, rwlen; 7881 7882 enable = dr7; 7883 rwlen = dr7 >> 16; 7884 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 7885 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 7886 dr6 |= (1 << i); 7887 return dr6; 7888 } 7889 7890 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) 7891 { 7892 struct kvm_run *kvm_run = vcpu->run; 7893 7894 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 7895 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; 7896 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); 7897 kvm_run->debug.arch.exception = DB_VECTOR; 7898 kvm_run->exit_reason = KVM_EXIT_DEBUG; 7899 return 0; 7900 } 7901 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 7902 return 1; 7903 } 7904 7905 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 7906 { 7907 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 7908 int r; 7909 7910 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); 7911 if (unlikely(!r)) 7912 return 0; 7913 7914 /* 7915 * rflags is the old, "raw" value of the flags. The new value has 7916 * not been saved yet. 7917 * 7918 * This is correct even for TF set by the guest, because "the 7919 * processor will not generate this exception after the instruction 7920 * that sets the TF flag". 7921 */ 7922 if (unlikely(rflags & X86_EFLAGS_TF)) 7923 r = kvm_vcpu_do_singlestep(vcpu); 7924 return r; 7925 } 7926 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 7927 7928 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 7929 { 7930 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 7931 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 7932 struct kvm_run *kvm_run = vcpu->run; 7933 unsigned long eip = kvm_get_linear_rip(vcpu); 7934 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 7935 vcpu->arch.guest_debug_dr7, 7936 vcpu->arch.eff_db); 7937 7938 if (dr6 != 0) { 7939 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; 7940 kvm_run->debug.arch.pc = eip; 7941 kvm_run->debug.arch.exception = DB_VECTOR; 7942 kvm_run->exit_reason = KVM_EXIT_DEBUG; 7943 *r = 0; 7944 return true; 7945 } 7946 } 7947 7948 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 7949 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 7950 unsigned long eip = kvm_get_linear_rip(vcpu); 7951 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 7952 vcpu->arch.dr7, 7953 vcpu->arch.db); 7954 7955 if (dr6 != 0) { 7956 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); 7957 *r = 1; 7958 return true; 7959 } 7960 } 7961 7962 return false; 7963 } 7964 7965 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 7966 { 7967 switch (ctxt->opcode_len) { 7968 case 1: 7969 switch (ctxt->b) { 7970 case 0xe4: /* IN */ 7971 case 0xe5: 7972 case 0xec: 7973 case 0xed: 7974 case 0xe6: /* OUT */ 7975 case 0xe7: 7976 case 0xee: 7977 case 0xef: 7978 case 0x6c: /* INS */ 7979 case 0x6d: 7980 case 0x6e: /* OUTS */ 7981 case 0x6f: 7982 return true; 7983 } 7984 break; 7985 case 2: 7986 switch (ctxt->b) { 7987 case 0x33: /* RDPMC */ 7988 return true; 7989 } 7990 break; 7991 } 7992 7993 return false; 7994 } 7995 7996 /* 7997 * Decode to be emulated instruction. Return EMULATION_OK if success. 7998 */ 7999 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 8000 void *insn, int insn_len) 8001 { 8002 int r = EMULATION_OK; 8003 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8004 8005 init_emulate_ctxt(vcpu); 8006 8007 /* 8008 * We will reenter on the same instruction since we do not set 8009 * complete_userspace_io. This does not handle watchpoints yet, 8010 * those would be handled in the emulate_ops. 8011 */ 8012 if (!(emulation_type & EMULTYPE_SKIP) && 8013 kvm_vcpu_check_breakpoint(vcpu, &r)) 8014 return r; 8015 8016 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); 8017 8018 trace_kvm_emulate_insn_start(vcpu); 8019 ++vcpu->stat.insn_emulation; 8020 8021 return r; 8022 } 8023 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); 8024 8025 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 8026 int emulation_type, void *insn, int insn_len) 8027 { 8028 int r; 8029 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8030 bool writeback = true; 8031 bool write_fault_to_spt; 8032 8033 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, insn, insn_len))) 8034 return 1; 8035 8036 vcpu->arch.l1tf_flush_l1d = true; 8037 8038 /* 8039 * Clear write_fault_to_shadow_pgtable here to ensure it is 8040 * never reused. 8041 */ 8042 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 8043 vcpu->arch.write_fault_to_shadow_pgtable = false; 8044 8045 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 8046 kvm_clear_exception_queue(vcpu); 8047 8048 r = x86_decode_emulated_instruction(vcpu, emulation_type, 8049 insn, insn_len); 8050 if (r != EMULATION_OK) { 8051 if ((emulation_type & EMULTYPE_TRAP_UD) || 8052 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { 8053 kvm_queue_exception(vcpu, UD_VECTOR); 8054 return 1; 8055 } 8056 if (reexecute_instruction(vcpu, cr2_or_gpa, 8057 write_fault_to_spt, 8058 emulation_type)) 8059 return 1; 8060 if (ctxt->have_exception) { 8061 /* 8062 * #UD should result in just EMULATION_FAILED, and trap-like 8063 * exception should not be encountered during decode. 8064 */ 8065 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || 8066 exception_type(ctxt->exception.vector) == EXCPT_TRAP); 8067 inject_emulated_exception(vcpu); 8068 return 1; 8069 } 8070 return handle_emulation_failure(vcpu, emulation_type); 8071 } 8072 } 8073 8074 if ((emulation_type & EMULTYPE_VMWARE_GP) && 8075 !is_vmware_backdoor_opcode(ctxt)) { 8076 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 8077 return 1; 8078 } 8079 8080 /* 8081 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks 8082 * for kvm_skip_emulated_instruction(). The caller is responsible for 8083 * updating interruptibility state and injecting single-step #DBs. 8084 */ 8085 if (emulation_type & EMULTYPE_SKIP) { 8086 kvm_rip_write(vcpu, ctxt->_eip); 8087 if (ctxt->eflags & X86_EFLAGS_RF) 8088 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 8089 return 1; 8090 } 8091 8092 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) 8093 return 1; 8094 8095 /* this is needed for vmware backdoor interface to work since it 8096 changes registers values during IO operation */ 8097 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 8098 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 8099 emulator_invalidate_register_cache(ctxt); 8100 } 8101 8102 restart: 8103 if (emulation_type & EMULTYPE_PF) { 8104 /* Save the faulting GPA (cr2) in the address field */ 8105 ctxt->exception.address = cr2_or_gpa; 8106 8107 /* With shadow page tables, cr2 contains a GVA or nGPA. */ 8108 if (vcpu->arch.mmu->direct_map) { 8109 ctxt->gpa_available = true; 8110 ctxt->gpa_val = cr2_or_gpa; 8111 } 8112 } else { 8113 /* Sanitize the address out of an abundance of paranoia. */ 8114 ctxt->exception.address = 0; 8115 } 8116 8117 r = x86_emulate_insn(ctxt); 8118 8119 if (r == EMULATION_INTERCEPTED) 8120 return 1; 8121 8122 if (r == EMULATION_FAILED) { 8123 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, 8124 emulation_type)) 8125 return 1; 8126 8127 return handle_emulation_failure(vcpu, emulation_type); 8128 } 8129 8130 if (ctxt->have_exception) { 8131 r = 1; 8132 if (inject_emulated_exception(vcpu)) 8133 return r; 8134 } else if (vcpu->arch.pio.count) { 8135 if (!vcpu->arch.pio.in) { 8136 /* FIXME: return into emulator if single-stepping. */ 8137 vcpu->arch.pio.count = 0; 8138 } else { 8139 writeback = false; 8140 vcpu->arch.complete_userspace_io = complete_emulated_pio; 8141 } 8142 r = 0; 8143 } else if (vcpu->mmio_needed) { 8144 ++vcpu->stat.mmio_exits; 8145 8146 if (!vcpu->mmio_is_write) 8147 writeback = false; 8148 r = 0; 8149 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 8150 } else if (r == EMULATION_RESTART) 8151 goto restart; 8152 else 8153 r = 1; 8154 8155 if (writeback) { 8156 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 8157 toggle_interruptibility(vcpu, ctxt->interruptibility); 8158 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 8159 if (!ctxt->have_exception || 8160 exception_type(ctxt->exception.vector) == EXCPT_TRAP) { 8161 kvm_rip_write(vcpu, ctxt->eip); 8162 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 8163 r = kvm_vcpu_do_singlestep(vcpu); 8164 if (kvm_x86_ops.update_emulated_instruction) 8165 static_call(kvm_x86_update_emulated_instruction)(vcpu); 8166 __kvm_set_rflags(vcpu, ctxt->eflags); 8167 } 8168 8169 /* 8170 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 8171 * do nothing, and it will be requested again as soon as 8172 * the shadow expires. But we still need to check here, 8173 * because POPF has no interrupt shadow. 8174 */ 8175 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 8176 kvm_make_request(KVM_REQ_EVENT, vcpu); 8177 } else 8178 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 8179 8180 return r; 8181 } 8182 8183 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 8184 { 8185 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 8186 } 8187 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 8188 8189 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 8190 void *insn, int insn_len) 8191 { 8192 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 8193 } 8194 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 8195 8196 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 8197 { 8198 vcpu->arch.pio.count = 0; 8199 return 1; 8200 } 8201 8202 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 8203 { 8204 vcpu->arch.pio.count = 0; 8205 8206 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 8207 return 1; 8208 8209 return kvm_skip_emulated_instruction(vcpu); 8210 } 8211 8212 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 8213 unsigned short port) 8214 { 8215 unsigned long val = kvm_rax_read(vcpu); 8216 int ret = emulator_pio_out(vcpu, size, port, &val, 1); 8217 8218 if (ret) 8219 return ret; 8220 8221 /* 8222 * Workaround userspace that relies on old KVM behavior of %rip being 8223 * incremented prior to exiting to userspace to handle "OUT 0x7e". 8224 */ 8225 if (port == 0x7e && 8226 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 8227 vcpu->arch.complete_userspace_io = 8228 complete_fast_pio_out_port_0x7e; 8229 kvm_skip_emulated_instruction(vcpu); 8230 } else { 8231 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 8232 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 8233 } 8234 return 0; 8235 } 8236 8237 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 8238 { 8239 unsigned long val; 8240 8241 /* We should only ever be called with arch.pio.count equal to 1 */ 8242 BUG_ON(vcpu->arch.pio.count != 1); 8243 8244 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 8245 vcpu->arch.pio.count = 0; 8246 return 1; 8247 } 8248 8249 /* For size less than 4 we merge, else we zero extend */ 8250 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 8251 8252 /* 8253 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform 8254 * the copy and tracing 8255 */ 8256 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); 8257 kvm_rax_write(vcpu, val); 8258 8259 return kvm_skip_emulated_instruction(vcpu); 8260 } 8261 8262 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 8263 unsigned short port) 8264 { 8265 unsigned long val; 8266 int ret; 8267 8268 /* For size less than 4 we merge, else we zero extend */ 8269 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 8270 8271 ret = emulator_pio_in(vcpu, size, port, &val, 1); 8272 if (ret) { 8273 kvm_rax_write(vcpu, val); 8274 return ret; 8275 } 8276 8277 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 8278 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 8279 8280 return 0; 8281 } 8282 8283 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 8284 { 8285 int ret; 8286 8287 if (in) 8288 ret = kvm_fast_pio_in(vcpu, size, port); 8289 else 8290 ret = kvm_fast_pio_out(vcpu, size, port); 8291 return ret && kvm_skip_emulated_instruction(vcpu); 8292 } 8293 EXPORT_SYMBOL_GPL(kvm_fast_pio); 8294 8295 static int kvmclock_cpu_down_prep(unsigned int cpu) 8296 { 8297 __this_cpu_write(cpu_tsc_khz, 0); 8298 return 0; 8299 } 8300 8301 static void tsc_khz_changed(void *data) 8302 { 8303 struct cpufreq_freqs *freq = data; 8304 unsigned long khz = 0; 8305 8306 if (data) 8307 khz = freq->new; 8308 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 8309 khz = cpufreq_quick_get(raw_smp_processor_id()); 8310 if (!khz) 8311 khz = tsc_khz; 8312 __this_cpu_write(cpu_tsc_khz, khz); 8313 } 8314 8315 #ifdef CONFIG_X86_64 8316 static void kvm_hyperv_tsc_notifier(void) 8317 { 8318 struct kvm *kvm; 8319 int cpu; 8320 8321 mutex_lock(&kvm_lock); 8322 list_for_each_entry(kvm, &vm_list, vm_list) 8323 kvm_make_mclock_inprogress_request(kvm); 8324 8325 /* no guest entries from this point */ 8326 hyperv_stop_tsc_emulation(); 8327 8328 /* TSC frequency always matches when on Hyper-V */ 8329 for_each_present_cpu(cpu) 8330 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 8331 kvm_max_guest_tsc_khz = tsc_khz; 8332 8333 list_for_each_entry(kvm, &vm_list, vm_list) { 8334 __kvm_start_pvclock_update(kvm); 8335 pvclock_update_vm_gtod_copy(kvm); 8336 kvm_end_pvclock_update(kvm); 8337 } 8338 8339 mutex_unlock(&kvm_lock); 8340 } 8341 #endif 8342 8343 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 8344 { 8345 struct kvm *kvm; 8346 struct kvm_vcpu *vcpu; 8347 int i, send_ipi = 0; 8348 8349 /* 8350 * We allow guests to temporarily run on slowing clocks, 8351 * provided we notify them after, or to run on accelerating 8352 * clocks, provided we notify them before. Thus time never 8353 * goes backwards. 8354 * 8355 * However, we have a problem. We can't atomically update 8356 * the frequency of a given CPU from this function; it is 8357 * merely a notifier, which can be called from any CPU. 8358 * Changing the TSC frequency at arbitrary points in time 8359 * requires a recomputation of local variables related to 8360 * the TSC for each VCPU. We must flag these local variables 8361 * to be updated and be sure the update takes place with the 8362 * new frequency before any guests proceed. 8363 * 8364 * Unfortunately, the combination of hotplug CPU and frequency 8365 * change creates an intractable locking scenario; the order 8366 * of when these callouts happen is undefined with respect to 8367 * CPU hotplug, and they can race with each other. As such, 8368 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 8369 * undefined; you can actually have a CPU frequency change take 8370 * place in between the computation of X and the setting of the 8371 * variable. To protect against this problem, all updates of 8372 * the per_cpu tsc_khz variable are done in an interrupt 8373 * protected IPI, and all callers wishing to update the value 8374 * must wait for a synchronous IPI to complete (which is trivial 8375 * if the caller is on the CPU already). This establishes the 8376 * necessary total order on variable updates. 8377 * 8378 * Note that because a guest time update may take place 8379 * anytime after the setting of the VCPU's request bit, the 8380 * correct TSC value must be set before the request. However, 8381 * to ensure the update actually makes it to any guest which 8382 * starts running in hardware virtualization between the set 8383 * and the acquisition of the spinlock, we must also ping the 8384 * CPU after setting the request bit. 8385 * 8386 */ 8387 8388 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 8389 8390 mutex_lock(&kvm_lock); 8391 list_for_each_entry(kvm, &vm_list, vm_list) { 8392 kvm_for_each_vcpu(i, vcpu, kvm) { 8393 if (vcpu->cpu != cpu) 8394 continue; 8395 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 8396 if (vcpu->cpu != raw_smp_processor_id()) 8397 send_ipi = 1; 8398 } 8399 } 8400 mutex_unlock(&kvm_lock); 8401 8402 if (freq->old < freq->new && send_ipi) { 8403 /* 8404 * We upscale the frequency. Must make the guest 8405 * doesn't see old kvmclock values while running with 8406 * the new frequency, otherwise we risk the guest sees 8407 * time go backwards. 8408 * 8409 * In case we update the frequency for another cpu 8410 * (which might be in guest context) send an interrupt 8411 * to kick the cpu out of guest context. Next time 8412 * guest context is entered kvmclock will be updated, 8413 * so the guest will not see stale values. 8414 */ 8415 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 8416 } 8417 } 8418 8419 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 8420 void *data) 8421 { 8422 struct cpufreq_freqs *freq = data; 8423 int cpu; 8424 8425 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 8426 return 0; 8427 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 8428 return 0; 8429 8430 for_each_cpu(cpu, freq->policy->cpus) 8431 __kvmclock_cpufreq_notifier(freq, cpu); 8432 8433 return 0; 8434 } 8435 8436 static struct notifier_block kvmclock_cpufreq_notifier_block = { 8437 .notifier_call = kvmclock_cpufreq_notifier 8438 }; 8439 8440 static int kvmclock_cpu_online(unsigned int cpu) 8441 { 8442 tsc_khz_changed(NULL); 8443 return 0; 8444 } 8445 8446 static void kvm_timer_init(void) 8447 { 8448 max_tsc_khz = tsc_khz; 8449 8450 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 8451 #ifdef CONFIG_CPU_FREQ 8452 struct cpufreq_policy *policy; 8453 int cpu; 8454 8455 cpu = get_cpu(); 8456 policy = cpufreq_cpu_get(cpu); 8457 if (policy) { 8458 if (policy->cpuinfo.max_freq) 8459 max_tsc_khz = policy->cpuinfo.max_freq; 8460 cpufreq_cpu_put(policy); 8461 } 8462 put_cpu(); 8463 #endif 8464 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 8465 CPUFREQ_TRANSITION_NOTIFIER); 8466 } 8467 8468 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 8469 kvmclock_cpu_online, kvmclock_cpu_down_prep); 8470 } 8471 8472 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 8473 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); 8474 8475 int kvm_is_in_guest(void) 8476 { 8477 return __this_cpu_read(current_vcpu) != NULL; 8478 } 8479 8480 static int kvm_is_user_mode(void) 8481 { 8482 int user_mode = 3; 8483 8484 if (__this_cpu_read(current_vcpu)) 8485 user_mode = static_call(kvm_x86_get_cpl)(__this_cpu_read(current_vcpu)); 8486 8487 return user_mode != 0; 8488 } 8489 8490 static unsigned long kvm_get_guest_ip(void) 8491 { 8492 unsigned long ip = 0; 8493 8494 if (__this_cpu_read(current_vcpu)) 8495 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 8496 8497 return ip; 8498 } 8499 8500 static void kvm_handle_intel_pt_intr(void) 8501 { 8502 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); 8503 8504 kvm_make_request(KVM_REQ_PMI, vcpu); 8505 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, 8506 (unsigned long *)&vcpu->arch.pmu.global_status); 8507 } 8508 8509 static struct perf_guest_info_callbacks kvm_guest_cbs = { 8510 .is_in_guest = kvm_is_in_guest, 8511 .is_user_mode = kvm_is_user_mode, 8512 .get_guest_ip = kvm_get_guest_ip, 8513 .handle_intel_pt_intr = kvm_handle_intel_pt_intr, 8514 }; 8515 8516 #ifdef CONFIG_X86_64 8517 static void pvclock_gtod_update_fn(struct work_struct *work) 8518 { 8519 struct kvm *kvm; 8520 8521 struct kvm_vcpu *vcpu; 8522 int i; 8523 8524 mutex_lock(&kvm_lock); 8525 list_for_each_entry(kvm, &vm_list, vm_list) 8526 kvm_for_each_vcpu(i, vcpu, kvm) 8527 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 8528 atomic_set(&kvm_guest_has_master_clock, 0); 8529 mutex_unlock(&kvm_lock); 8530 } 8531 8532 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 8533 8534 /* 8535 * Indirection to move queue_work() out of the tk_core.seq write held 8536 * region to prevent possible deadlocks against time accessors which 8537 * are invoked with work related locks held. 8538 */ 8539 static void pvclock_irq_work_fn(struct irq_work *w) 8540 { 8541 queue_work(system_long_wq, &pvclock_gtod_work); 8542 } 8543 8544 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); 8545 8546 /* 8547 * Notification about pvclock gtod data update. 8548 */ 8549 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 8550 void *priv) 8551 { 8552 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 8553 struct timekeeper *tk = priv; 8554 8555 update_pvclock_gtod(tk); 8556 8557 /* 8558 * Disable master clock if host does not trust, or does not use, 8559 * TSC based clocksource. Delegate queue_work() to irq_work as 8560 * this is invoked with tk_core.seq write held. 8561 */ 8562 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 8563 atomic_read(&kvm_guest_has_master_clock) != 0) 8564 irq_work_queue(&pvclock_irq_work); 8565 return 0; 8566 } 8567 8568 static struct notifier_block pvclock_gtod_notifier = { 8569 .notifier_call = pvclock_gtod_notify, 8570 }; 8571 #endif 8572 8573 int kvm_arch_init(void *opaque) 8574 { 8575 struct kvm_x86_init_ops *ops = opaque; 8576 int r; 8577 8578 if (kvm_x86_ops.hardware_enable) { 8579 pr_err("kvm: already loaded vendor module '%s'\n", kvm_x86_ops.name); 8580 r = -EEXIST; 8581 goto out; 8582 } 8583 8584 if (!ops->cpu_has_kvm_support()) { 8585 pr_err_ratelimited("kvm: no hardware support for '%s'\n", 8586 ops->runtime_ops->name); 8587 r = -EOPNOTSUPP; 8588 goto out; 8589 } 8590 if (ops->disabled_by_bios()) { 8591 pr_err_ratelimited("kvm: support for '%s' disabled by bios\n", 8592 ops->runtime_ops->name); 8593 r = -EOPNOTSUPP; 8594 goto out; 8595 } 8596 8597 /* 8598 * KVM explicitly assumes that the guest has an FPU and 8599 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 8600 * vCPU's FPU state as a fxregs_state struct. 8601 */ 8602 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 8603 printk(KERN_ERR "kvm: inadequate fpu\n"); 8604 r = -EOPNOTSUPP; 8605 goto out; 8606 } 8607 8608 r = -ENOMEM; 8609 8610 x86_emulator_cache = kvm_alloc_emulator_cache(); 8611 if (!x86_emulator_cache) { 8612 pr_err("kvm: failed to allocate cache for x86 emulator\n"); 8613 goto out; 8614 } 8615 8616 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); 8617 if (!user_return_msrs) { 8618 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); 8619 goto out_free_x86_emulator_cache; 8620 } 8621 kvm_nr_uret_msrs = 0; 8622 8623 r = kvm_mmu_module_init(); 8624 if (r) 8625 goto out_free_percpu; 8626 8627 kvm_timer_init(); 8628 8629 perf_register_guest_info_callbacks(&kvm_guest_cbs); 8630 8631 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 8632 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 8633 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; 8634 } 8635 8636 if (pi_inject_timer == -1) 8637 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); 8638 #ifdef CONFIG_X86_64 8639 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 8640 8641 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8642 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 8643 #endif 8644 8645 return 0; 8646 8647 out_free_percpu: 8648 free_percpu(user_return_msrs); 8649 out_free_x86_emulator_cache: 8650 kmem_cache_destroy(x86_emulator_cache); 8651 out: 8652 return r; 8653 } 8654 8655 void kvm_arch_exit(void) 8656 { 8657 #ifdef CONFIG_X86_64 8658 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8659 clear_hv_tscchange_cb(); 8660 #endif 8661 kvm_lapic_exit(); 8662 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 8663 8664 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 8665 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 8666 CPUFREQ_TRANSITION_NOTIFIER); 8667 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 8668 #ifdef CONFIG_X86_64 8669 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 8670 irq_work_sync(&pvclock_irq_work); 8671 cancel_work_sync(&pvclock_gtod_work); 8672 #endif 8673 kvm_x86_ops.hardware_enable = NULL; 8674 kvm_mmu_module_exit(); 8675 free_percpu(user_return_msrs); 8676 kmem_cache_destroy(x86_emulator_cache); 8677 #ifdef CONFIG_KVM_XEN 8678 static_key_deferred_flush(&kvm_xen_enabled); 8679 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); 8680 #endif 8681 } 8682 8683 static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason) 8684 { 8685 ++vcpu->stat.halt_exits; 8686 if (lapic_in_kernel(vcpu)) { 8687 vcpu->arch.mp_state = state; 8688 return 1; 8689 } else { 8690 vcpu->run->exit_reason = reason; 8691 return 0; 8692 } 8693 } 8694 8695 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 8696 { 8697 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); 8698 } 8699 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 8700 8701 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 8702 { 8703 int ret = kvm_skip_emulated_instruction(vcpu); 8704 /* 8705 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 8706 * KVM_EXIT_DEBUG here. 8707 */ 8708 return kvm_vcpu_halt(vcpu) && ret; 8709 } 8710 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 8711 8712 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) 8713 { 8714 int ret = kvm_skip_emulated_instruction(vcpu); 8715 8716 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret; 8717 } 8718 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); 8719 8720 #ifdef CONFIG_X86_64 8721 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 8722 unsigned long clock_type) 8723 { 8724 struct kvm_clock_pairing clock_pairing; 8725 struct timespec64 ts; 8726 u64 cycle; 8727 int ret; 8728 8729 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 8730 return -KVM_EOPNOTSUPP; 8731 8732 if (!kvm_get_walltime_and_clockread(&ts, &cycle)) 8733 return -KVM_EOPNOTSUPP; 8734 8735 clock_pairing.sec = ts.tv_sec; 8736 clock_pairing.nsec = ts.tv_nsec; 8737 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 8738 clock_pairing.flags = 0; 8739 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 8740 8741 ret = 0; 8742 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 8743 sizeof(struct kvm_clock_pairing))) 8744 ret = -KVM_EFAULT; 8745 8746 return ret; 8747 } 8748 #endif 8749 8750 /* 8751 * kvm_pv_kick_cpu_op: Kick a vcpu. 8752 * 8753 * @apicid - apicid of vcpu to be kicked. 8754 */ 8755 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 8756 { 8757 struct kvm_lapic_irq lapic_irq; 8758 8759 lapic_irq.shorthand = APIC_DEST_NOSHORT; 8760 lapic_irq.dest_mode = APIC_DEST_PHYSICAL; 8761 lapic_irq.level = 0; 8762 lapic_irq.dest_id = apicid; 8763 lapic_irq.msi_redir_hint = false; 8764 8765 lapic_irq.delivery_mode = APIC_DM_REMRD; 8766 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 8767 } 8768 8769 bool kvm_apicv_activated(struct kvm *kvm) 8770 { 8771 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); 8772 } 8773 EXPORT_SYMBOL_GPL(kvm_apicv_activated); 8774 8775 static void kvm_apicv_init(struct kvm *kvm) 8776 { 8777 init_rwsem(&kvm->arch.apicv_update_lock); 8778 8779 if (enable_apicv) 8780 clear_bit(APICV_INHIBIT_REASON_DISABLE, 8781 &kvm->arch.apicv_inhibit_reasons); 8782 else 8783 set_bit(APICV_INHIBIT_REASON_DISABLE, 8784 &kvm->arch.apicv_inhibit_reasons); 8785 } 8786 8787 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) 8788 { 8789 struct kvm_vcpu *target = NULL; 8790 struct kvm_apic_map *map; 8791 8792 vcpu->stat.directed_yield_attempted++; 8793 8794 if (single_task_running()) 8795 goto no_yield; 8796 8797 rcu_read_lock(); 8798 map = rcu_dereference(vcpu->kvm->arch.apic_map); 8799 8800 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 8801 target = map->phys_map[dest_id]->vcpu; 8802 8803 rcu_read_unlock(); 8804 8805 if (!target || !READ_ONCE(target->ready)) 8806 goto no_yield; 8807 8808 /* Ignore requests to yield to self */ 8809 if (vcpu == target) 8810 goto no_yield; 8811 8812 if (kvm_vcpu_yield_to(target) <= 0) 8813 goto no_yield; 8814 8815 vcpu->stat.directed_yield_successful++; 8816 8817 no_yield: 8818 return; 8819 } 8820 8821 static int complete_hypercall_exit(struct kvm_vcpu *vcpu) 8822 { 8823 u64 ret = vcpu->run->hypercall.ret; 8824 8825 if (!is_64_bit_mode(vcpu)) 8826 ret = (u32)ret; 8827 kvm_rax_write(vcpu, ret); 8828 ++vcpu->stat.hypercalls; 8829 return kvm_skip_emulated_instruction(vcpu); 8830 } 8831 8832 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 8833 { 8834 unsigned long nr, a0, a1, a2, a3, ret; 8835 int op_64_bit; 8836 8837 if (kvm_xen_hypercall_enabled(vcpu->kvm)) 8838 return kvm_xen_hypercall(vcpu); 8839 8840 if (kvm_hv_hypercall_enabled(vcpu)) 8841 return kvm_hv_hypercall(vcpu); 8842 8843 nr = kvm_rax_read(vcpu); 8844 a0 = kvm_rbx_read(vcpu); 8845 a1 = kvm_rcx_read(vcpu); 8846 a2 = kvm_rdx_read(vcpu); 8847 a3 = kvm_rsi_read(vcpu); 8848 8849 trace_kvm_hypercall(nr, a0, a1, a2, a3); 8850 8851 op_64_bit = is_64_bit_mode(vcpu); 8852 if (!op_64_bit) { 8853 nr &= 0xFFFFFFFF; 8854 a0 &= 0xFFFFFFFF; 8855 a1 &= 0xFFFFFFFF; 8856 a2 &= 0xFFFFFFFF; 8857 a3 &= 0xFFFFFFFF; 8858 } 8859 8860 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { 8861 ret = -KVM_EPERM; 8862 goto out; 8863 } 8864 8865 ret = -KVM_ENOSYS; 8866 8867 switch (nr) { 8868 case KVM_HC_VAPIC_POLL_IRQ: 8869 ret = 0; 8870 break; 8871 case KVM_HC_KICK_CPU: 8872 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) 8873 break; 8874 8875 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 8876 kvm_sched_yield(vcpu, a1); 8877 ret = 0; 8878 break; 8879 #ifdef CONFIG_X86_64 8880 case KVM_HC_CLOCK_PAIRING: 8881 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 8882 break; 8883 #endif 8884 case KVM_HC_SEND_IPI: 8885 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) 8886 break; 8887 8888 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 8889 break; 8890 case KVM_HC_SCHED_YIELD: 8891 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) 8892 break; 8893 8894 kvm_sched_yield(vcpu, a0); 8895 ret = 0; 8896 break; 8897 case KVM_HC_MAP_GPA_RANGE: { 8898 u64 gpa = a0, npages = a1, attrs = a2; 8899 8900 ret = -KVM_ENOSYS; 8901 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE))) 8902 break; 8903 8904 if (!PAGE_ALIGNED(gpa) || !npages || 8905 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) { 8906 ret = -KVM_EINVAL; 8907 break; 8908 } 8909 8910 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL; 8911 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE; 8912 vcpu->run->hypercall.args[0] = gpa; 8913 vcpu->run->hypercall.args[1] = npages; 8914 vcpu->run->hypercall.args[2] = attrs; 8915 vcpu->run->hypercall.longmode = op_64_bit; 8916 vcpu->arch.complete_userspace_io = complete_hypercall_exit; 8917 return 0; 8918 } 8919 default: 8920 ret = -KVM_ENOSYS; 8921 break; 8922 } 8923 out: 8924 if (!op_64_bit) 8925 ret = (u32)ret; 8926 kvm_rax_write(vcpu, ret); 8927 8928 ++vcpu->stat.hypercalls; 8929 return kvm_skip_emulated_instruction(vcpu); 8930 } 8931 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 8932 8933 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 8934 { 8935 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8936 char instruction[3]; 8937 unsigned long rip = kvm_rip_read(vcpu); 8938 8939 static_call(kvm_x86_patch_hypercall)(vcpu, instruction); 8940 8941 return emulator_write_emulated(ctxt, rip, instruction, 3, 8942 &ctxt->exception); 8943 } 8944 8945 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 8946 { 8947 return vcpu->run->request_interrupt_window && 8948 likely(!pic_in_kernel(vcpu->kvm)); 8949 } 8950 8951 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 8952 { 8953 struct kvm_run *kvm_run = vcpu->run; 8954 8955 /* 8956 * if_flag is obsolete and useless, so do not bother 8957 * setting it for SEV-ES guests. Userspace can just 8958 * use kvm_run->ready_for_interrupt_injection. 8959 */ 8960 kvm_run->if_flag = !vcpu->arch.guest_state_protected 8961 && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 8962 8963 kvm_run->cr8 = kvm_get_cr8(vcpu); 8964 kvm_run->apic_base = kvm_get_apic_base(vcpu); 8965 8966 /* 8967 * The call to kvm_ready_for_interrupt_injection() may end up in 8968 * kvm_xen_has_interrupt() which may require the srcu lock to be 8969 * held, to protect against changes in the vcpu_info address. 8970 */ 8971 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 8972 kvm_run->ready_for_interrupt_injection = 8973 pic_in_kernel(vcpu->kvm) || 8974 kvm_vcpu_ready_for_interrupt_injection(vcpu); 8975 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 8976 8977 if (is_smm(vcpu)) 8978 kvm_run->flags |= KVM_RUN_X86_SMM; 8979 } 8980 8981 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 8982 { 8983 int max_irr, tpr; 8984 8985 if (!kvm_x86_ops.update_cr8_intercept) 8986 return; 8987 8988 if (!lapic_in_kernel(vcpu)) 8989 return; 8990 8991 if (vcpu->arch.apicv_active) 8992 return; 8993 8994 if (!vcpu->arch.apic->vapic_addr) 8995 max_irr = kvm_lapic_find_highest_irr(vcpu); 8996 else 8997 max_irr = -1; 8998 8999 if (max_irr != -1) 9000 max_irr >>= 4; 9001 9002 tpr = kvm_lapic_get_cr8(vcpu); 9003 9004 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); 9005 } 9006 9007 9008 int kvm_check_nested_events(struct kvm_vcpu *vcpu) 9009 { 9010 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 9011 kvm_x86_ops.nested_ops->triple_fault(vcpu); 9012 return 1; 9013 } 9014 9015 return kvm_x86_ops.nested_ops->check_events(vcpu); 9016 } 9017 9018 static void kvm_inject_exception(struct kvm_vcpu *vcpu) 9019 { 9020 if (vcpu->arch.exception.error_code && !is_protmode(vcpu)) 9021 vcpu->arch.exception.error_code = false; 9022 static_call(kvm_x86_queue_exception)(vcpu); 9023 } 9024 9025 static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) 9026 { 9027 int r; 9028 bool can_inject = true; 9029 9030 /* try to reinject previous events if any */ 9031 9032 if (vcpu->arch.exception.injected) { 9033 kvm_inject_exception(vcpu); 9034 can_inject = false; 9035 } 9036 /* 9037 * Do not inject an NMI or interrupt if there is a pending 9038 * exception. Exceptions and interrupts are recognized at 9039 * instruction boundaries, i.e. the start of an instruction. 9040 * Trap-like exceptions, e.g. #DB, have higher priority than 9041 * NMIs and interrupts, i.e. traps are recognized before an 9042 * NMI/interrupt that's pending on the same instruction. 9043 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 9044 * priority, but are only generated (pended) during instruction 9045 * execution, i.e. a pending fault-like exception means the 9046 * fault occurred on the *previous* instruction and must be 9047 * serviced prior to recognizing any new events in order to 9048 * fully complete the previous instruction. 9049 */ 9050 else if (!vcpu->arch.exception.pending) { 9051 if (vcpu->arch.nmi_injected) { 9052 static_call(kvm_x86_set_nmi)(vcpu); 9053 can_inject = false; 9054 } else if (vcpu->arch.interrupt.injected) { 9055 static_call(kvm_x86_set_irq)(vcpu); 9056 can_inject = false; 9057 } 9058 } 9059 9060 WARN_ON_ONCE(vcpu->arch.exception.injected && 9061 vcpu->arch.exception.pending); 9062 9063 /* 9064 * Call check_nested_events() even if we reinjected a previous event 9065 * in order for caller to determine if it should require immediate-exit 9066 * from L2 to L1 due to pending L1 events which require exit 9067 * from L2 to L1. 9068 */ 9069 if (is_guest_mode(vcpu)) { 9070 r = kvm_check_nested_events(vcpu); 9071 if (r < 0) 9072 goto out; 9073 } 9074 9075 /* try to inject new event if pending */ 9076 if (vcpu->arch.exception.pending) { 9077 trace_kvm_inj_exception(vcpu->arch.exception.nr, 9078 vcpu->arch.exception.has_error_code, 9079 vcpu->arch.exception.error_code); 9080 9081 vcpu->arch.exception.pending = false; 9082 vcpu->arch.exception.injected = true; 9083 9084 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 9085 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 9086 X86_EFLAGS_RF); 9087 9088 if (vcpu->arch.exception.nr == DB_VECTOR) { 9089 kvm_deliver_exception_payload(vcpu); 9090 if (vcpu->arch.dr7 & DR7_GD) { 9091 vcpu->arch.dr7 &= ~DR7_GD; 9092 kvm_update_dr7(vcpu); 9093 } 9094 } 9095 9096 kvm_inject_exception(vcpu); 9097 can_inject = false; 9098 } 9099 9100 /* Don't inject interrupts if the user asked to avoid doing so */ 9101 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) 9102 return 0; 9103 9104 /* 9105 * Finally, inject interrupt events. If an event cannot be injected 9106 * due to architectural conditions (e.g. IF=0) a window-open exit 9107 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending 9108 * and can architecturally be injected, but we cannot do it right now: 9109 * an interrupt could have arrived just now and we have to inject it 9110 * as a vmexit, or there could already an event in the queue, which is 9111 * indicated by can_inject. In that case we request an immediate exit 9112 * in order to make progress and get back here for another iteration. 9113 * The kvm_x86_ops hooks communicate this by returning -EBUSY. 9114 */ 9115 if (vcpu->arch.smi_pending) { 9116 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; 9117 if (r < 0) 9118 goto out; 9119 if (r) { 9120 vcpu->arch.smi_pending = false; 9121 ++vcpu->arch.smi_count; 9122 enter_smm(vcpu); 9123 can_inject = false; 9124 } else 9125 static_call(kvm_x86_enable_smi_window)(vcpu); 9126 } 9127 9128 if (vcpu->arch.nmi_pending) { 9129 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; 9130 if (r < 0) 9131 goto out; 9132 if (r) { 9133 --vcpu->arch.nmi_pending; 9134 vcpu->arch.nmi_injected = true; 9135 static_call(kvm_x86_set_nmi)(vcpu); 9136 can_inject = false; 9137 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); 9138 } 9139 if (vcpu->arch.nmi_pending) 9140 static_call(kvm_x86_enable_nmi_window)(vcpu); 9141 } 9142 9143 if (kvm_cpu_has_injectable_intr(vcpu)) { 9144 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; 9145 if (r < 0) 9146 goto out; 9147 if (r) { 9148 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); 9149 static_call(kvm_x86_set_irq)(vcpu); 9150 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); 9151 } 9152 if (kvm_cpu_has_injectable_intr(vcpu)) 9153 static_call(kvm_x86_enable_irq_window)(vcpu); 9154 } 9155 9156 if (is_guest_mode(vcpu) && 9157 kvm_x86_ops.nested_ops->hv_timer_pending && 9158 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 9159 *req_immediate_exit = true; 9160 9161 WARN_ON(vcpu->arch.exception.pending); 9162 return 0; 9163 9164 out: 9165 if (r == -EBUSY) { 9166 *req_immediate_exit = true; 9167 r = 0; 9168 } 9169 return r; 9170 } 9171 9172 static void process_nmi(struct kvm_vcpu *vcpu) 9173 { 9174 unsigned limit = 2; 9175 9176 /* 9177 * x86 is limited to one NMI running, and one NMI pending after it. 9178 * If an NMI is already in progress, limit further NMIs to just one. 9179 * Otherwise, allow two (and we'll inject the first one immediately). 9180 */ 9181 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) 9182 limit = 1; 9183 9184 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 9185 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 9186 kvm_make_request(KVM_REQ_EVENT, vcpu); 9187 } 9188 9189 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 9190 { 9191 u32 flags = 0; 9192 flags |= seg->g << 23; 9193 flags |= seg->db << 22; 9194 flags |= seg->l << 21; 9195 flags |= seg->avl << 20; 9196 flags |= seg->present << 15; 9197 flags |= seg->dpl << 13; 9198 flags |= seg->s << 12; 9199 flags |= seg->type << 8; 9200 return flags; 9201 } 9202 9203 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 9204 { 9205 struct kvm_segment seg; 9206 int offset; 9207 9208 kvm_get_segment(vcpu, &seg, n); 9209 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 9210 9211 if (n < 3) 9212 offset = 0x7f84 + n * 12; 9213 else 9214 offset = 0x7f2c + (n - 3) * 12; 9215 9216 put_smstate(u32, buf, offset + 8, seg.base); 9217 put_smstate(u32, buf, offset + 4, seg.limit); 9218 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 9219 } 9220 9221 #ifdef CONFIG_X86_64 9222 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 9223 { 9224 struct kvm_segment seg; 9225 int offset; 9226 u16 flags; 9227 9228 kvm_get_segment(vcpu, &seg, n); 9229 offset = 0x7e00 + n * 16; 9230 9231 flags = enter_smm_get_segment_flags(&seg) >> 8; 9232 put_smstate(u16, buf, offset, seg.selector); 9233 put_smstate(u16, buf, offset + 2, flags); 9234 put_smstate(u32, buf, offset + 4, seg.limit); 9235 put_smstate(u64, buf, offset + 8, seg.base); 9236 } 9237 #endif 9238 9239 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 9240 { 9241 struct desc_ptr dt; 9242 struct kvm_segment seg; 9243 unsigned long val; 9244 int i; 9245 9246 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 9247 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 9248 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 9249 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 9250 9251 for (i = 0; i < 8; i++) 9252 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i)); 9253 9254 kvm_get_dr(vcpu, 6, &val); 9255 put_smstate(u32, buf, 0x7fcc, (u32)val); 9256 kvm_get_dr(vcpu, 7, &val); 9257 put_smstate(u32, buf, 0x7fc8, (u32)val); 9258 9259 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 9260 put_smstate(u32, buf, 0x7fc4, seg.selector); 9261 put_smstate(u32, buf, 0x7f64, seg.base); 9262 put_smstate(u32, buf, 0x7f60, seg.limit); 9263 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 9264 9265 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 9266 put_smstate(u32, buf, 0x7fc0, seg.selector); 9267 put_smstate(u32, buf, 0x7f80, seg.base); 9268 put_smstate(u32, buf, 0x7f7c, seg.limit); 9269 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 9270 9271 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9272 put_smstate(u32, buf, 0x7f74, dt.address); 9273 put_smstate(u32, buf, 0x7f70, dt.size); 9274 9275 static_call(kvm_x86_get_idt)(vcpu, &dt); 9276 put_smstate(u32, buf, 0x7f58, dt.address); 9277 put_smstate(u32, buf, 0x7f54, dt.size); 9278 9279 for (i = 0; i < 6; i++) 9280 enter_smm_save_seg_32(vcpu, buf, i); 9281 9282 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 9283 9284 /* revision id */ 9285 put_smstate(u32, buf, 0x7efc, 0x00020000); 9286 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 9287 } 9288 9289 #ifdef CONFIG_X86_64 9290 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 9291 { 9292 struct desc_ptr dt; 9293 struct kvm_segment seg; 9294 unsigned long val; 9295 int i; 9296 9297 for (i = 0; i < 16; i++) 9298 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i)); 9299 9300 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 9301 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 9302 9303 kvm_get_dr(vcpu, 6, &val); 9304 put_smstate(u64, buf, 0x7f68, val); 9305 kvm_get_dr(vcpu, 7, &val); 9306 put_smstate(u64, buf, 0x7f60, val); 9307 9308 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 9309 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 9310 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 9311 9312 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 9313 9314 /* revision id */ 9315 put_smstate(u32, buf, 0x7efc, 0x00020064); 9316 9317 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 9318 9319 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 9320 put_smstate(u16, buf, 0x7e90, seg.selector); 9321 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 9322 put_smstate(u32, buf, 0x7e94, seg.limit); 9323 put_smstate(u64, buf, 0x7e98, seg.base); 9324 9325 static_call(kvm_x86_get_idt)(vcpu, &dt); 9326 put_smstate(u32, buf, 0x7e84, dt.size); 9327 put_smstate(u64, buf, 0x7e88, dt.address); 9328 9329 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 9330 put_smstate(u16, buf, 0x7e70, seg.selector); 9331 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 9332 put_smstate(u32, buf, 0x7e74, seg.limit); 9333 put_smstate(u64, buf, 0x7e78, seg.base); 9334 9335 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9336 put_smstate(u32, buf, 0x7e64, dt.size); 9337 put_smstate(u64, buf, 0x7e68, dt.address); 9338 9339 for (i = 0; i < 6; i++) 9340 enter_smm_save_seg_64(vcpu, buf, i); 9341 } 9342 #endif 9343 9344 static void enter_smm(struct kvm_vcpu *vcpu) 9345 { 9346 struct kvm_segment cs, ds; 9347 struct desc_ptr dt; 9348 unsigned long cr0; 9349 char buf[512]; 9350 9351 memset(buf, 0, 512); 9352 #ifdef CONFIG_X86_64 9353 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 9354 enter_smm_save_state_64(vcpu, buf); 9355 else 9356 #endif 9357 enter_smm_save_state_32(vcpu, buf); 9358 9359 /* 9360 * Give enter_smm() a chance to make ISA-specific changes to the vCPU 9361 * state (e.g. leave guest mode) after we've saved the state into the 9362 * SMM state-save area. 9363 */ 9364 static_call(kvm_x86_enter_smm)(vcpu, buf); 9365 9366 kvm_smm_changed(vcpu, true); 9367 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 9368 9369 if (static_call(kvm_x86_get_nmi_mask)(vcpu)) 9370 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 9371 else 9372 static_call(kvm_x86_set_nmi_mask)(vcpu, true); 9373 9374 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 9375 kvm_rip_write(vcpu, 0x8000); 9376 9377 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 9378 static_call(kvm_x86_set_cr0)(vcpu, cr0); 9379 vcpu->arch.cr0 = cr0; 9380 9381 static_call(kvm_x86_set_cr4)(vcpu, 0); 9382 9383 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 9384 dt.address = dt.size = 0; 9385 static_call(kvm_x86_set_idt)(vcpu, &dt); 9386 9387 kvm_set_dr(vcpu, 7, DR7_FIXED_1); 9388 9389 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 9390 cs.base = vcpu->arch.smbase; 9391 9392 ds.selector = 0; 9393 ds.base = 0; 9394 9395 cs.limit = ds.limit = 0xffffffff; 9396 cs.type = ds.type = 0x3; 9397 cs.dpl = ds.dpl = 0; 9398 cs.db = ds.db = 0; 9399 cs.s = ds.s = 1; 9400 cs.l = ds.l = 0; 9401 cs.g = ds.g = 1; 9402 cs.avl = ds.avl = 0; 9403 cs.present = ds.present = 1; 9404 cs.unusable = ds.unusable = 0; 9405 cs.padding = ds.padding = 0; 9406 9407 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 9408 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 9409 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 9410 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 9411 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 9412 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 9413 9414 #ifdef CONFIG_X86_64 9415 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 9416 static_call(kvm_x86_set_efer)(vcpu, 0); 9417 #endif 9418 9419 kvm_update_cpuid_runtime(vcpu); 9420 kvm_mmu_reset_context(vcpu); 9421 } 9422 9423 static void process_smi(struct kvm_vcpu *vcpu) 9424 { 9425 vcpu->arch.smi_pending = true; 9426 kvm_make_request(KVM_REQ_EVENT, vcpu); 9427 } 9428 9429 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 9430 unsigned long *vcpu_bitmap) 9431 { 9432 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap); 9433 } 9434 9435 void kvm_make_scan_ioapic_request(struct kvm *kvm) 9436 { 9437 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 9438 } 9439 9440 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 9441 { 9442 bool activate; 9443 9444 if (!lapic_in_kernel(vcpu)) 9445 return; 9446 9447 down_read(&vcpu->kvm->arch.apicv_update_lock); 9448 9449 activate = kvm_apicv_activated(vcpu->kvm); 9450 if (vcpu->arch.apicv_active == activate) 9451 goto out; 9452 9453 vcpu->arch.apicv_active = activate; 9454 kvm_apic_update_apicv(vcpu); 9455 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); 9456 9457 /* 9458 * When APICv gets disabled, we may still have injected interrupts 9459 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was 9460 * still active when the interrupt got accepted. Make sure 9461 * inject_pending_event() is called to check for that. 9462 */ 9463 if (!vcpu->arch.apicv_active) 9464 kvm_make_request(KVM_REQ_EVENT, vcpu); 9465 9466 out: 9467 up_read(&vcpu->kvm->arch.apicv_update_lock); 9468 } 9469 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); 9470 9471 void __kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) 9472 { 9473 unsigned long old, new; 9474 9475 lockdep_assert_held_write(&kvm->arch.apicv_update_lock); 9476 9477 if (!kvm_x86_ops.check_apicv_inhibit_reasons || 9478 !static_call(kvm_x86_check_apicv_inhibit_reasons)(bit)) 9479 return; 9480 9481 old = new = kvm->arch.apicv_inhibit_reasons; 9482 9483 if (activate) 9484 __clear_bit(bit, &new); 9485 else 9486 __set_bit(bit, &new); 9487 9488 if (!!old != !!new) { 9489 trace_kvm_apicv_update_request(activate, bit); 9490 /* 9491 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid 9492 * false positives in the sanity check WARN in svm_vcpu_run(). 9493 * This task will wait for all vCPUs to ack the kick IRQ before 9494 * updating apicv_inhibit_reasons, and all other vCPUs will 9495 * block on acquiring apicv_update_lock so that vCPUs can't 9496 * redo svm_vcpu_run() without seeing the new inhibit state. 9497 * 9498 * Note, holding apicv_update_lock and taking it in the read 9499 * side (handling the request) also prevents other vCPUs from 9500 * servicing the request with a stale apicv_inhibit_reasons. 9501 */ 9502 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); 9503 kvm->arch.apicv_inhibit_reasons = new; 9504 if (new) { 9505 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE); 9506 kvm_zap_gfn_range(kvm, gfn, gfn+1); 9507 } 9508 } else 9509 kvm->arch.apicv_inhibit_reasons = new; 9510 } 9511 EXPORT_SYMBOL_GPL(__kvm_request_apicv_update); 9512 9513 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) 9514 { 9515 down_write(&kvm->arch.apicv_update_lock); 9516 __kvm_request_apicv_update(kvm, activate, bit); 9517 up_write(&kvm->arch.apicv_update_lock); 9518 } 9519 EXPORT_SYMBOL_GPL(kvm_request_apicv_update); 9520 9521 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 9522 { 9523 if (!kvm_apic_present(vcpu)) 9524 return; 9525 9526 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 9527 9528 if (irqchip_split(vcpu->kvm)) 9529 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 9530 else { 9531 if (vcpu->arch.apicv_active) 9532 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 9533 if (ioapic_in_kernel(vcpu->kvm)) 9534 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 9535 } 9536 9537 if (is_guest_mode(vcpu)) 9538 vcpu->arch.load_eoi_exitmap_pending = true; 9539 else 9540 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 9541 } 9542 9543 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 9544 { 9545 u64 eoi_exit_bitmap[4]; 9546 9547 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 9548 return; 9549 9550 if (to_hv_vcpu(vcpu)) 9551 bitmap_or((ulong *)eoi_exit_bitmap, 9552 vcpu->arch.ioapic_handled_vectors, 9553 to_hv_synic(vcpu)->vec_bitmap, 256); 9554 9555 static_call(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); 9556 } 9557 9558 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 9559 unsigned long start, unsigned long end) 9560 { 9561 unsigned long apic_address; 9562 9563 /* 9564 * The physical address of apic access page is stored in the VMCS. 9565 * Update it when it becomes invalid. 9566 */ 9567 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 9568 if (start <= apic_address && apic_address < end) 9569 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 9570 } 9571 9572 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 9573 { 9574 if (!lapic_in_kernel(vcpu)) 9575 return; 9576 9577 if (!kvm_x86_ops.set_apic_access_page_addr) 9578 return; 9579 9580 static_call(kvm_x86_set_apic_access_page_addr)(vcpu); 9581 } 9582 9583 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 9584 { 9585 smp_send_reschedule(vcpu->cpu); 9586 } 9587 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 9588 9589 /* 9590 * Returns 1 to let vcpu_run() continue the guest execution loop without 9591 * exiting to the userspace. Otherwise, the value will be returned to the 9592 * userspace. 9593 */ 9594 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 9595 { 9596 int r; 9597 bool req_int_win = 9598 dm_request_for_irq_injection(vcpu) && 9599 kvm_cpu_accept_dm_intr(vcpu); 9600 fastpath_t exit_fastpath; 9601 9602 bool req_immediate_exit = false; 9603 9604 /* Forbid vmenter if vcpu dirty ring is soft-full */ 9605 if (unlikely(vcpu->kvm->dirty_ring_size && 9606 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { 9607 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; 9608 trace_kvm_dirty_ring_exit(vcpu); 9609 r = 0; 9610 goto out; 9611 } 9612 9613 if (kvm_request_pending(vcpu)) { 9614 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) { 9615 r = -EIO; 9616 goto out; 9617 } 9618 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { 9619 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { 9620 r = 0; 9621 goto out; 9622 } 9623 } 9624 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 9625 kvm_mmu_unload(vcpu); 9626 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 9627 __kvm_migrate_timers(vcpu); 9628 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 9629 kvm_update_masterclock(vcpu->kvm); 9630 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 9631 kvm_gen_kvmclock_update(vcpu); 9632 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 9633 r = kvm_guest_time_update(vcpu); 9634 if (unlikely(r)) 9635 goto out; 9636 } 9637 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 9638 kvm_mmu_sync_roots(vcpu); 9639 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) 9640 kvm_mmu_load_pgd(vcpu); 9641 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { 9642 kvm_vcpu_flush_tlb_all(vcpu); 9643 9644 /* Flushing all ASIDs flushes the current ASID... */ 9645 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 9646 } 9647 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) 9648 kvm_vcpu_flush_tlb_current(vcpu); 9649 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu)) 9650 kvm_vcpu_flush_tlb_guest(vcpu); 9651 9652 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 9653 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 9654 r = 0; 9655 goto out; 9656 } 9657 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 9658 if (is_guest_mode(vcpu)) { 9659 kvm_x86_ops.nested_ops->triple_fault(vcpu); 9660 } else { 9661 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 9662 vcpu->mmio_needed = 0; 9663 r = 0; 9664 goto out; 9665 } 9666 } 9667 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 9668 /* Page is swapped out. Do synthetic halt */ 9669 vcpu->arch.apf.halted = true; 9670 r = 1; 9671 goto out; 9672 } 9673 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 9674 record_steal_time(vcpu); 9675 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 9676 process_smi(vcpu); 9677 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 9678 process_nmi(vcpu); 9679 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 9680 kvm_pmu_handle_event(vcpu); 9681 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 9682 kvm_pmu_deliver_pmi(vcpu); 9683 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 9684 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 9685 if (test_bit(vcpu->arch.pending_ioapic_eoi, 9686 vcpu->arch.ioapic_handled_vectors)) { 9687 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 9688 vcpu->run->eoi.vector = 9689 vcpu->arch.pending_ioapic_eoi; 9690 r = 0; 9691 goto out; 9692 } 9693 } 9694 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 9695 vcpu_scan_ioapic(vcpu); 9696 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 9697 vcpu_load_eoi_exitmap(vcpu); 9698 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 9699 kvm_vcpu_reload_apic_access_page(vcpu); 9700 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 9701 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 9702 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 9703 r = 0; 9704 goto out; 9705 } 9706 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 9707 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 9708 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 9709 r = 0; 9710 goto out; 9711 } 9712 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 9713 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); 9714 9715 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 9716 vcpu->run->hyperv = hv_vcpu->exit; 9717 r = 0; 9718 goto out; 9719 } 9720 9721 /* 9722 * KVM_REQ_HV_STIMER has to be processed after 9723 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 9724 * depend on the guest clock being up-to-date 9725 */ 9726 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 9727 kvm_hv_process_stimers(vcpu); 9728 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 9729 kvm_vcpu_update_apicv(vcpu); 9730 if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) 9731 kvm_check_async_pf_completion(vcpu); 9732 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) 9733 static_call(kvm_x86_msr_filter_changed)(vcpu); 9734 9735 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) 9736 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); 9737 } 9738 9739 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || 9740 kvm_xen_has_interrupt(vcpu)) { 9741 ++vcpu->stat.req_event; 9742 r = kvm_apic_accept_events(vcpu); 9743 if (r < 0) { 9744 r = 0; 9745 goto out; 9746 } 9747 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 9748 r = 1; 9749 goto out; 9750 } 9751 9752 r = inject_pending_event(vcpu, &req_immediate_exit); 9753 if (r < 0) { 9754 r = 0; 9755 goto out; 9756 } 9757 if (req_int_win) 9758 static_call(kvm_x86_enable_irq_window)(vcpu); 9759 9760 if (kvm_lapic_enabled(vcpu)) { 9761 update_cr8_intercept(vcpu); 9762 kvm_lapic_sync_to_vapic(vcpu); 9763 } 9764 } 9765 9766 r = kvm_mmu_reload(vcpu); 9767 if (unlikely(r)) { 9768 goto cancel_injection; 9769 } 9770 9771 preempt_disable(); 9772 9773 static_call(kvm_x86_prepare_guest_switch)(vcpu); 9774 9775 /* 9776 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 9777 * IPI are then delayed after guest entry, which ensures that they 9778 * result in virtual interrupt delivery. 9779 */ 9780 local_irq_disable(); 9781 vcpu->mode = IN_GUEST_MODE; 9782 9783 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 9784 9785 /* 9786 * 1) We should set ->mode before checking ->requests. Please see 9787 * the comment in kvm_vcpu_exiting_guest_mode(). 9788 * 9789 * 2) For APICv, we should set ->mode before checking PID.ON. This 9790 * pairs with the memory barrier implicit in pi_test_and_set_on 9791 * (see vmx_deliver_posted_interrupt). 9792 * 9793 * 3) This also orders the write to mode from any reads to the page 9794 * tables done while the VCPU is running. Please see the comment 9795 * in kvm_flush_remote_tlbs. 9796 */ 9797 smp_mb__after_srcu_read_unlock(); 9798 9799 /* 9800 * This handles the case where a posted interrupt was 9801 * notified with kvm_vcpu_kick. 9802 */ 9803 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) 9804 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 9805 9806 if (kvm_vcpu_exit_request(vcpu)) { 9807 vcpu->mode = OUTSIDE_GUEST_MODE; 9808 smp_wmb(); 9809 local_irq_enable(); 9810 preempt_enable(); 9811 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9812 r = 1; 9813 goto cancel_injection; 9814 } 9815 9816 if (req_immediate_exit) { 9817 kvm_make_request(KVM_REQ_EVENT, vcpu); 9818 static_call(kvm_x86_request_immediate_exit)(vcpu); 9819 } 9820 9821 fpregs_assert_state_consistent(); 9822 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 9823 switch_fpu_return(); 9824 9825 if (unlikely(vcpu->arch.switch_db_regs)) { 9826 set_debugreg(0, 7); 9827 set_debugreg(vcpu->arch.eff_db[0], 0); 9828 set_debugreg(vcpu->arch.eff_db[1], 1); 9829 set_debugreg(vcpu->arch.eff_db[2], 2); 9830 set_debugreg(vcpu->arch.eff_db[3], 3); 9831 } else if (unlikely(hw_breakpoint_active())) { 9832 set_debugreg(0, 7); 9833 } 9834 9835 for (;;) { 9836 /* 9837 * Assert that vCPU vs. VM APICv state is consistent. An APICv 9838 * update must kick and wait for all vCPUs before toggling the 9839 * per-VM state, and responsing vCPUs must wait for the update 9840 * to complete before servicing KVM_REQ_APICV_UPDATE. 9841 */ 9842 WARN_ON_ONCE(kvm_apicv_activated(vcpu->kvm) != kvm_vcpu_apicv_active(vcpu)); 9843 9844 exit_fastpath = static_call(kvm_x86_run)(vcpu); 9845 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) 9846 break; 9847 9848 if (vcpu->arch.apicv_active) 9849 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 9850 9851 if (unlikely(kvm_vcpu_exit_request(vcpu))) { 9852 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; 9853 break; 9854 } 9855 } 9856 9857 /* 9858 * Do this here before restoring debug registers on the host. And 9859 * since we do this before handling the vmexit, a DR access vmexit 9860 * can (a) read the correct value of the debug registers, (b) set 9861 * KVM_DEBUGREG_WONT_EXIT again. 9862 */ 9863 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 9864 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 9865 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); 9866 kvm_update_dr0123(vcpu); 9867 kvm_update_dr7(vcpu); 9868 } 9869 9870 /* 9871 * If the guest has used debug registers, at least dr7 9872 * will be disabled while returning to the host. 9873 * If we don't have active breakpoints in the host, we don't 9874 * care about the messed up debug address registers. But if 9875 * we have some of them active, restore the old state. 9876 */ 9877 if (hw_breakpoint_active()) 9878 hw_breakpoint_restore(); 9879 9880 vcpu->arch.last_vmentry_cpu = vcpu->cpu; 9881 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 9882 9883 vcpu->mode = OUTSIDE_GUEST_MODE; 9884 smp_wmb(); 9885 9886 static_call(kvm_x86_handle_exit_irqoff)(vcpu); 9887 9888 /* 9889 * Consume any pending interrupts, including the possible source of 9890 * VM-Exit on SVM and any ticks that occur between VM-Exit and now. 9891 * An instruction is required after local_irq_enable() to fully unblock 9892 * interrupts on processors that implement an interrupt shadow, the 9893 * stat.exits increment will do nicely. 9894 */ 9895 kvm_before_interrupt(vcpu); 9896 local_irq_enable(); 9897 ++vcpu->stat.exits; 9898 local_irq_disable(); 9899 kvm_after_interrupt(vcpu); 9900 9901 /* 9902 * Wait until after servicing IRQs to account guest time so that any 9903 * ticks that occurred while running the guest are properly accounted 9904 * to the guest. Waiting until IRQs are enabled degrades the accuracy 9905 * of accounting via context tracking, but the loss of accuracy is 9906 * acceptable for all known use cases. 9907 */ 9908 vtime_account_guest_exit(); 9909 9910 if (lapic_in_kernel(vcpu)) { 9911 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; 9912 if (delta != S64_MIN) { 9913 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); 9914 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; 9915 } 9916 } 9917 9918 local_irq_enable(); 9919 preempt_enable(); 9920 9921 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9922 9923 /* 9924 * Profile KVM exit RIPs: 9925 */ 9926 if (unlikely(prof_on == KVM_PROFILING)) { 9927 unsigned long rip = kvm_rip_read(vcpu); 9928 profile_hit(KVM_PROFILING, (void *)rip); 9929 } 9930 9931 if (unlikely(vcpu->arch.tsc_always_catchup)) 9932 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 9933 9934 if (vcpu->arch.apic_attention) 9935 kvm_lapic_sync_from_vapic(vcpu); 9936 9937 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); 9938 return r; 9939 9940 cancel_injection: 9941 if (req_immediate_exit) 9942 kvm_make_request(KVM_REQ_EVENT, vcpu); 9943 static_call(kvm_x86_cancel_injection)(vcpu); 9944 if (unlikely(vcpu->arch.apic_attention)) 9945 kvm_lapic_sync_from_vapic(vcpu); 9946 out: 9947 return r; 9948 } 9949 9950 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 9951 { 9952 if (!kvm_arch_vcpu_runnable(vcpu) && 9953 (!kvm_x86_ops.pre_block || static_call(kvm_x86_pre_block)(vcpu) == 0)) { 9954 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9955 kvm_vcpu_block(vcpu); 9956 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9957 9958 if (kvm_x86_ops.post_block) 9959 static_call(kvm_x86_post_block)(vcpu); 9960 9961 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 9962 return 1; 9963 } 9964 9965 if (kvm_apic_accept_events(vcpu) < 0) 9966 return 0; 9967 switch(vcpu->arch.mp_state) { 9968 case KVM_MP_STATE_HALTED: 9969 case KVM_MP_STATE_AP_RESET_HOLD: 9970 vcpu->arch.pv.pv_unhalted = false; 9971 vcpu->arch.mp_state = 9972 KVM_MP_STATE_RUNNABLE; 9973 fallthrough; 9974 case KVM_MP_STATE_RUNNABLE: 9975 vcpu->arch.apf.halted = false; 9976 break; 9977 case KVM_MP_STATE_INIT_RECEIVED: 9978 break; 9979 default: 9980 return -EINTR; 9981 } 9982 return 1; 9983 } 9984 9985 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 9986 { 9987 if (is_guest_mode(vcpu)) 9988 kvm_check_nested_events(vcpu); 9989 9990 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 9991 !vcpu->arch.apf.halted); 9992 } 9993 9994 static int vcpu_run(struct kvm_vcpu *vcpu) 9995 { 9996 int r; 9997 struct kvm *kvm = vcpu->kvm; 9998 9999 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 10000 vcpu->arch.l1tf_flush_l1d = true; 10001 10002 for (;;) { 10003 if (kvm_vcpu_running(vcpu)) { 10004 r = vcpu_enter_guest(vcpu); 10005 } else { 10006 r = vcpu_block(kvm, vcpu); 10007 } 10008 10009 if (r <= 0) 10010 break; 10011 10012 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); 10013 if (kvm_cpu_has_pending_timer(vcpu)) 10014 kvm_inject_pending_timer_irqs(vcpu); 10015 10016 if (dm_request_for_irq_injection(vcpu) && 10017 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 10018 r = 0; 10019 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 10020 ++vcpu->stat.request_irq_exits; 10021 break; 10022 } 10023 10024 if (__xfer_to_guest_mode_work_pending()) { 10025 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 10026 r = xfer_to_guest_mode_handle_work(vcpu); 10027 if (r) 10028 return r; 10029 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 10030 } 10031 } 10032 10033 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 10034 10035 return r; 10036 } 10037 10038 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 10039 { 10040 int r; 10041 10042 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 10043 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 10044 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 10045 return r; 10046 } 10047 10048 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 10049 { 10050 BUG_ON(!vcpu->arch.pio.count); 10051 10052 return complete_emulated_io(vcpu); 10053 } 10054 10055 /* 10056 * Implements the following, as a state machine: 10057 * 10058 * read: 10059 * for each fragment 10060 * for each mmio piece in the fragment 10061 * write gpa, len 10062 * exit 10063 * copy data 10064 * execute insn 10065 * 10066 * write: 10067 * for each fragment 10068 * for each mmio piece in the fragment 10069 * write gpa, len 10070 * copy data 10071 * exit 10072 */ 10073 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 10074 { 10075 struct kvm_run *run = vcpu->run; 10076 struct kvm_mmio_fragment *frag; 10077 unsigned len; 10078 10079 BUG_ON(!vcpu->mmio_needed); 10080 10081 /* Complete previous fragment */ 10082 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 10083 len = min(8u, frag->len); 10084 if (!vcpu->mmio_is_write) 10085 memcpy(frag->data, run->mmio.data, len); 10086 10087 if (frag->len <= 8) { 10088 /* Switch to the next fragment. */ 10089 frag++; 10090 vcpu->mmio_cur_fragment++; 10091 } else { 10092 /* Go forward to the next mmio piece. */ 10093 frag->data += len; 10094 frag->gpa += len; 10095 frag->len -= len; 10096 } 10097 10098 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 10099 vcpu->mmio_needed = 0; 10100 10101 /* FIXME: return into emulator if single-stepping. */ 10102 if (vcpu->mmio_is_write) 10103 return 1; 10104 vcpu->mmio_read_completed = 1; 10105 return complete_emulated_io(vcpu); 10106 } 10107 10108 run->exit_reason = KVM_EXIT_MMIO; 10109 run->mmio.phys_addr = frag->gpa; 10110 if (vcpu->mmio_is_write) 10111 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 10112 run->mmio.len = min(8u, frag->len); 10113 run->mmio.is_write = vcpu->mmio_is_write; 10114 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 10115 return 0; 10116 } 10117 10118 /* Swap (qemu) user FPU context for the guest FPU context. */ 10119 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 10120 { 10121 /* 10122 * Exclude PKRU from restore as restored separately in 10123 * kvm_x86_ops.run(). 10124 */ 10125 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true); 10126 trace_kvm_fpu(1); 10127 } 10128 10129 /* When vcpu_run ends, restore user space FPU context. */ 10130 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 10131 { 10132 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false); 10133 ++vcpu->stat.fpu_reload; 10134 trace_kvm_fpu(0); 10135 } 10136 10137 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 10138 { 10139 struct kvm_run *kvm_run = vcpu->run; 10140 int r; 10141 10142 vcpu_load(vcpu); 10143 kvm_sigset_activate(vcpu); 10144 kvm_run->flags = 0; 10145 kvm_load_guest_fpu(vcpu); 10146 10147 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 10148 if (kvm_run->immediate_exit) { 10149 r = -EINTR; 10150 goto out; 10151 } 10152 kvm_vcpu_block(vcpu); 10153 if (kvm_apic_accept_events(vcpu) < 0) { 10154 r = 0; 10155 goto out; 10156 } 10157 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 10158 r = -EAGAIN; 10159 if (signal_pending(current)) { 10160 r = -EINTR; 10161 kvm_run->exit_reason = KVM_EXIT_INTR; 10162 ++vcpu->stat.signal_exits; 10163 } 10164 goto out; 10165 } 10166 10167 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) || 10168 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) { 10169 r = -EINVAL; 10170 goto out; 10171 } 10172 10173 if (kvm_run->kvm_dirty_regs) { 10174 r = sync_regs(vcpu); 10175 if (r != 0) 10176 goto out; 10177 } 10178 10179 /* re-sync apic's tpr */ 10180 if (!lapic_in_kernel(vcpu)) { 10181 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 10182 r = -EINVAL; 10183 goto out; 10184 } 10185 } 10186 10187 if (unlikely(vcpu->arch.complete_userspace_io)) { 10188 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 10189 vcpu->arch.complete_userspace_io = NULL; 10190 r = cui(vcpu); 10191 if (r <= 0) 10192 goto out; 10193 } else 10194 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 10195 10196 if (kvm_run->immediate_exit) 10197 r = -EINTR; 10198 else 10199 r = vcpu_run(vcpu); 10200 10201 out: 10202 kvm_put_guest_fpu(vcpu); 10203 if (kvm_run->kvm_valid_regs) 10204 store_regs(vcpu); 10205 post_kvm_run_save(vcpu); 10206 kvm_sigset_deactivate(vcpu); 10207 10208 vcpu_put(vcpu); 10209 return r; 10210 } 10211 10212 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10213 { 10214 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 10215 /* 10216 * We are here if userspace calls get_regs() in the middle of 10217 * instruction emulation. Registers state needs to be copied 10218 * back from emulation context to vcpu. Userspace shouldn't do 10219 * that usually, but some bad designed PV devices (vmware 10220 * backdoor interface) need this to work 10221 */ 10222 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); 10223 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 10224 } 10225 regs->rax = kvm_rax_read(vcpu); 10226 regs->rbx = kvm_rbx_read(vcpu); 10227 regs->rcx = kvm_rcx_read(vcpu); 10228 regs->rdx = kvm_rdx_read(vcpu); 10229 regs->rsi = kvm_rsi_read(vcpu); 10230 regs->rdi = kvm_rdi_read(vcpu); 10231 regs->rsp = kvm_rsp_read(vcpu); 10232 regs->rbp = kvm_rbp_read(vcpu); 10233 #ifdef CONFIG_X86_64 10234 regs->r8 = kvm_r8_read(vcpu); 10235 regs->r9 = kvm_r9_read(vcpu); 10236 regs->r10 = kvm_r10_read(vcpu); 10237 regs->r11 = kvm_r11_read(vcpu); 10238 regs->r12 = kvm_r12_read(vcpu); 10239 regs->r13 = kvm_r13_read(vcpu); 10240 regs->r14 = kvm_r14_read(vcpu); 10241 regs->r15 = kvm_r15_read(vcpu); 10242 #endif 10243 10244 regs->rip = kvm_rip_read(vcpu); 10245 regs->rflags = kvm_get_rflags(vcpu); 10246 } 10247 10248 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10249 { 10250 vcpu_load(vcpu); 10251 __get_regs(vcpu, regs); 10252 vcpu_put(vcpu); 10253 return 0; 10254 } 10255 10256 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10257 { 10258 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 10259 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 10260 10261 kvm_rax_write(vcpu, regs->rax); 10262 kvm_rbx_write(vcpu, regs->rbx); 10263 kvm_rcx_write(vcpu, regs->rcx); 10264 kvm_rdx_write(vcpu, regs->rdx); 10265 kvm_rsi_write(vcpu, regs->rsi); 10266 kvm_rdi_write(vcpu, regs->rdi); 10267 kvm_rsp_write(vcpu, regs->rsp); 10268 kvm_rbp_write(vcpu, regs->rbp); 10269 #ifdef CONFIG_X86_64 10270 kvm_r8_write(vcpu, regs->r8); 10271 kvm_r9_write(vcpu, regs->r9); 10272 kvm_r10_write(vcpu, regs->r10); 10273 kvm_r11_write(vcpu, regs->r11); 10274 kvm_r12_write(vcpu, regs->r12); 10275 kvm_r13_write(vcpu, regs->r13); 10276 kvm_r14_write(vcpu, regs->r14); 10277 kvm_r15_write(vcpu, regs->r15); 10278 #endif 10279 10280 kvm_rip_write(vcpu, regs->rip); 10281 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 10282 10283 vcpu->arch.exception.pending = false; 10284 10285 kvm_make_request(KVM_REQ_EVENT, vcpu); 10286 } 10287 10288 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10289 { 10290 vcpu_load(vcpu); 10291 __set_regs(vcpu, regs); 10292 vcpu_put(vcpu); 10293 return 0; 10294 } 10295 10296 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 10297 { 10298 struct kvm_segment cs; 10299 10300 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 10301 *db = cs.db; 10302 *l = cs.l; 10303 } 10304 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 10305 10306 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10307 { 10308 struct desc_ptr dt; 10309 10310 if (vcpu->arch.guest_state_protected) 10311 goto skip_protected_regs; 10312 10313 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 10314 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 10315 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 10316 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 10317 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 10318 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 10319 10320 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 10321 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 10322 10323 static_call(kvm_x86_get_idt)(vcpu, &dt); 10324 sregs->idt.limit = dt.size; 10325 sregs->idt.base = dt.address; 10326 static_call(kvm_x86_get_gdt)(vcpu, &dt); 10327 sregs->gdt.limit = dt.size; 10328 sregs->gdt.base = dt.address; 10329 10330 sregs->cr2 = vcpu->arch.cr2; 10331 sregs->cr3 = kvm_read_cr3(vcpu); 10332 10333 skip_protected_regs: 10334 sregs->cr0 = kvm_read_cr0(vcpu); 10335 sregs->cr4 = kvm_read_cr4(vcpu); 10336 sregs->cr8 = kvm_get_cr8(vcpu); 10337 sregs->efer = vcpu->arch.efer; 10338 sregs->apic_base = kvm_get_apic_base(vcpu); 10339 } 10340 10341 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10342 { 10343 __get_sregs_common(vcpu, sregs); 10344 10345 if (vcpu->arch.guest_state_protected) 10346 return; 10347 10348 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 10349 set_bit(vcpu->arch.interrupt.nr, 10350 (unsigned long *)sregs->interrupt_bitmap); 10351 } 10352 10353 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 10354 { 10355 int i; 10356 10357 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2); 10358 10359 if (vcpu->arch.guest_state_protected) 10360 return; 10361 10362 if (is_pae_paging(vcpu)) { 10363 for (i = 0 ; i < 4 ; i++) 10364 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i); 10365 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; 10366 } 10367 } 10368 10369 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 10370 struct kvm_sregs *sregs) 10371 { 10372 vcpu_load(vcpu); 10373 __get_sregs(vcpu, sregs); 10374 vcpu_put(vcpu); 10375 return 0; 10376 } 10377 10378 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 10379 struct kvm_mp_state *mp_state) 10380 { 10381 int r; 10382 10383 vcpu_load(vcpu); 10384 if (kvm_mpx_supported()) 10385 kvm_load_guest_fpu(vcpu); 10386 10387 r = kvm_apic_accept_events(vcpu); 10388 if (r < 0) 10389 goto out; 10390 r = 0; 10391 10392 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || 10393 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && 10394 vcpu->arch.pv.pv_unhalted) 10395 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 10396 else 10397 mp_state->mp_state = vcpu->arch.mp_state; 10398 10399 out: 10400 if (kvm_mpx_supported()) 10401 kvm_put_guest_fpu(vcpu); 10402 vcpu_put(vcpu); 10403 return r; 10404 } 10405 10406 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 10407 struct kvm_mp_state *mp_state) 10408 { 10409 int ret = -EINVAL; 10410 10411 vcpu_load(vcpu); 10412 10413 if (!lapic_in_kernel(vcpu) && 10414 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 10415 goto out; 10416 10417 /* 10418 * KVM_MP_STATE_INIT_RECEIVED means the processor is in 10419 * INIT state; latched init should be reported using 10420 * KVM_SET_VCPU_EVENTS, so reject it here. 10421 */ 10422 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && 10423 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 10424 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 10425 goto out; 10426 10427 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 10428 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 10429 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 10430 } else 10431 vcpu->arch.mp_state = mp_state->mp_state; 10432 kvm_make_request(KVM_REQ_EVENT, vcpu); 10433 10434 ret = 0; 10435 out: 10436 vcpu_put(vcpu); 10437 return ret; 10438 } 10439 10440 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 10441 int reason, bool has_error_code, u32 error_code) 10442 { 10443 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 10444 int ret; 10445 10446 init_emulate_ctxt(vcpu); 10447 10448 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 10449 has_error_code, error_code); 10450 if (ret) { 10451 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 10452 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 10453 vcpu->run->internal.ndata = 0; 10454 return 0; 10455 } 10456 10457 kvm_rip_write(vcpu, ctxt->eip); 10458 kvm_set_rflags(vcpu, ctxt->eflags); 10459 return 1; 10460 } 10461 EXPORT_SYMBOL_GPL(kvm_task_switch); 10462 10463 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10464 { 10465 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 10466 /* 10467 * When EFER.LME and CR0.PG are set, the processor is in 10468 * 64-bit mode (though maybe in a 32-bit code segment). 10469 * CR4.PAE and EFER.LMA must be set. 10470 */ 10471 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) 10472 return false; 10473 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) 10474 return false; 10475 } else { 10476 /* 10477 * Not in 64-bit mode: EFER.LMA is clear and the code 10478 * segment cannot be 64-bit. 10479 */ 10480 if (sregs->efer & EFER_LMA || sregs->cs.l) 10481 return false; 10482 } 10483 10484 return kvm_is_valid_cr4(vcpu, sregs->cr4); 10485 } 10486 10487 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs, 10488 int *mmu_reset_needed, bool update_pdptrs) 10489 { 10490 struct msr_data apic_base_msr; 10491 int idx; 10492 struct desc_ptr dt; 10493 10494 if (!kvm_is_valid_sregs(vcpu, sregs)) 10495 return -EINVAL; 10496 10497 apic_base_msr.data = sregs->apic_base; 10498 apic_base_msr.host_initiated = true; 10499 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 10500 return -EINVAL; 10501 10502 if (vcpu->arch.guest_state_protected) 10503 return 0; 10504 10505 dt.size = sregs->idt.limit; 10506 dt.address = sregs->idt.base; 10507 static_call(kvm_x86_set_idt)(vcpu, &dt); 10508 dt.size = sregs->gdt.limit; 10509 dt.address = sregs->gdt.base; 10510 static_call(kvm_x86_set_gdt)(vcpu, &dt); 10511 10512 vcpu->arch.cr2 = sregs->cr2; 10513 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 10514 vcpu->arch.cr3 = sregs->cr3; 10515 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 10516 10517 kvm_set_cr8(vcpu, sregs->cr8); 10518 10519 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 10520 static_call(kvm_x86_set_efer)(vcpu, sregs->efer); 10521 10522 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 10523 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); 10524 vcpu->arch.cr0 = sregs->cr0; 10525 10526 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 10527 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); 10528 10529 if (update_pdptrs) { 10530 idx = srcu_read_lock(&vcpu->kvm->srcu); 10531 if (is_pae_paging(vcpu)) { 10532 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 10533 *mmu_reset_needed = 1; 10534 } 10535 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10536 } 10537 10538 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 10539 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 10540 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 10541 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 10542 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 10543 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 10544 10545 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 10546 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 10547 10548 update_cr8_intercept(vcpu); 10549 10550 /* Older userspace won't unhalt the vcpu on reset. */ 10551 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 10552 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 10553 !is_protmode(vcpu)) 10554 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 10555 10556 return 0; 10557 } 10558 10559 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10560 { 10561 int pending_vec, max_bits; 10562 int mmu_reset_needed = 0; 10563 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true); 10564 10565 if (ret) 10566 return ret; 10567 10568 if (mmu_reset_needed) 10569 kvm_mmu_reset_context(vcpu); 10570 10571 max_bits = KVM_NR_INTERRUPTS; 10572 pending_vec = find_first_bit( 10573 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 10574 10575 if (pending_vec < max_bits) { 10576 kvm_queue_interrupt(vcpu, pending_vec, false); 10577 pr_debug("Set back pending irq %d\n", pending_vec); 10578 kvm_make_request(KVM_REQ_EVENT, vcpu); 10579 } 10580 return 0; 10581 } 10582 10583 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 10584 { 10585 int mmu_reset_needed = 0; 10586 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; 10587 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) && 10588 !(sregs2->efer & EFER_LMA); 10589 int i, ret; 10590 10591 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID) 10592 return -EINVAL; 10593 10594 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected)) 10595 return -EINVAL; 10596 10597 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2, 10598 &mmu_reset_needed, !valid_pdptrs); 10599 if (ret) 10600 return ret; 10601 10602 if (valid_pdptrs) { 10603 for (i = 0; i < 4 ; i++) 10604 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]); 10605 10606 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 10607 mmu_reset_needed = 1; 10608 vcpu->arch.pdptrs_from_userspace = true; 10609 } 10610 if (mmu_reset_needed) 10611 kvm_mmu_reset_context(vcpu); 10612 return 0; 10613 } 10614 10615 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 10616 struct kvm_sregs *sregs) 10617 { 10618 int ret; 10619 10620 vcpu_load(vcpu); 10621 ret = __set_sregs(vcpu, sregs); 10622 vcpu_put(vcpu); 10623 return ret; 10624 } 10625 10626 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm) 10627 { 10628 bool inhibit = false; 10629 struct kvm_vcpu *vcpu; 10630 int i; 10631 10632 down_write(&kvm->arch.apicv_update_lock); 10633 10634 kvm_for_each_vcpu(i, vcpu, kvm) { 10635 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) { 10636 inhibit = true; 10637 break; 10638 } 10639 } 10640 __kvm_request_apicv_update(kvm, !inhibit, APICV_INHIBIT_REASON_BLOCKIRQ); 10641 up_write(&kvm->arch.apicv_update_lock); 10642 } 10643 10644 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 10645 struct kvm_guest_debug *dbg) 10646 { 10647 unsigned long rflags; 10648 int i, r; 10649 10650 if (vcpu->arch.guest_state_protected) 10651 return -EINVAL; 10652 10653 vcpu_load(vcpu); 10654 10655 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 10656 r = -EBUSY; 10657 if (vcpu->arch.exception.pending) 10658 goto out; 10659 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 10660 kvm_queue_exception(vcpu, DB_VECTOR); 10661 else 10662 kvm_queue_exception(vcpu, BP_VECTOR); 10663 } 10664 10665 /* 10666 * Read rflags as long as potentially injected trace flags are still 10667 * filtered out. 10668 */ 10669 rflags = kvm_get_rflags(vcpu); 10670 10671 vcpu->guest_debug = dbg->control; 10672 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 10673 vcpu->guest_debug = 0; 10674 10675 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 10676 for (i = 0; i < KVM_NR_DB_REGS; ++i) 10677 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 10678 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 10679 } else { 10680 for (i = 0; i < KVM_NR_DB_REGS; i++) 10681 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 10682 } 10683 kvm_update_dr7(vcpu); 10684 10685 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 10686 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); 10687 10688 /* 10689 * Trigger an rflags update that will inject or remove the trace 10690 * flags. 10691 */ 10692 kvm_set_rflags(vcpu, rflags); 10693 10694 static_call(kvm_x86_update_exception_bitmap)(vcpu); 10695 10696 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm); 10697 10698 r = 0; 10699 10700 out: 10701 vcpu_put(vcpu); 10702 return r; 10703 } 10704 10705 /* 10706 * Translate a guest virtual address to a guest physical address. 10707 */ 10708 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 10709 struct kvm_translation *tr) 10710 { 10711 unsigned long vaddr = tr->linear_address; 10712 gpa_t gpa; 10713 int idx; 10714 10715 vcpu_load(vcpu); 10716 10717 idx = srcu_read_lock(&vcpu->kvm->srcu); 10718 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 10719 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10720 tr->physical_address = gpa; 10721 tr->valid = gpa != UNMAPPED_GVA; 10722 tr->writeable = 1; 10723 tr->usermode = 0; 10724 10725 vcpu_put(vcpu); 10726 return 0; 10727 } 10728 10729 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 10730 { 10731 struct fxregs_state *fxsave; 10732 10733 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 10734 return 0; 10735 10736 vcpu_load(vcpu); 10737 10738 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 10739 memcpy(fpu->fpr, fxsave->st_space, 128); 10740 fpu->fcw = fxsave->cwd; 10741 fpu->fsw = fxsave->swd; 10742 fpu->ftwx = fxsave->twd; 10743 fpu->last_opcode = fxsave->fop; 10744 fpu->last_ip = fxsave->rip; 10745 fpu->last_dp = fxsave->rdp; 10746 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 10747 10748 vcpu_put(vcpu); 10749 return 0; 10750 } 10751 10752 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 10753 { 10754 struct fxregs_state *fxsave; 10755 10756 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 10757 return 0; 10758 10759 vcpu_load(vcpu); 10760 10761 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 10762 10763 memcpy(fxsave->st_space, fpu->fpr, 128); 10764 fxsave->cwd = fpu->fcw; 10765 fxsave->swd = fpu->fsw; 10766 fxsave->twd = fpu->ftwx; 10767 fxsave->fop = fpu->last_opcode; 10768 fxsave->rip = fpu->last_ip; 10769 fxsave->rdp = fpu->last_dp; 10770 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 10771 10772 vcpu_put(vcpu); 10773 return 0; 10774 } 10775 10776 static void store_regs(struct kvm_vcpu *vcpu) 10777 { 10778 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 10779 10780 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 10781 __get_regs(vcpu, &vcpu->run->s.regs.regs); 10782 10783 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 10784 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 10785 10786 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 10787 kvm_vcpu_ioctl_x86_get_vcpu_events( 10788 vcpu, &vcpu->run->s.regs.events); 10789 } 10790 10791 static int sync_regs(struct kvm_vcpu *vcpu) 10792 { 10793 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 10794 __set_regs(vcpu, &vcpu->run->s.regs.regs); 10795 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 10796 } 10797 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 10798 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 10799 return -EINVAL; 10800 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 10801 } 10802 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 10803 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 10804 vcpu, &vcpu->run->s.regs.events)) 10805 return -EINVAL; 10806 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 10807 } 10808 10809 return 0; 10810 } 10811 10812 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 10813 { 10814 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 10815 pr_warn_once("kvm: SMP vm created on host with unstable TSC; " 10816 "guest TSC will not be reliable\n"); 10817 10818 return 0; 10819 } 10820 10821 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 10822 { 10823 struct page *page; 10824 int r; 10825 10826 vcpu->arch.last_vmentry_cpu = -1; 10827 vcpu->arch.regs_avail = ~0; 10828 vcpu->arch.regs_dirty = ~0; 10829 10830 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 10831 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 10832 else 10833 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 10834 10835 r = kvm_mmu_create(vcpu); 10836 if (r < 0) 10837 return r; 10838 10839 if (irqchip_in_kernel(vcpu->kvm)) { 10840 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 10841 if (r < 0) 10842 goto fail_mmu_destroy; 10843 if (kvm_apicv_activated(vcpu->kvm)) 10844 vcpu->arch.apicv_active = true; 10845 } else 10846 static_branch_inc(&kvm_has_noapic_vcpu); 10847 10848 r = -ENOMEM; 10849 10850 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 10851 if (!page) 10852 goto fail_free_lapic; 10853 vcpu->arch.pio_data = page_address(page); 10854 10855 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 10856 GFP_KERNEL_ACCOUNT); 10857 if (!vcpu->arch.mce_banks) 10858 goto fail_free_pio_data; 10859 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 10860 10861 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 10862 GFP_KERNEL_ACCOUNT)) 10863 goto fail_free_mce_banks; 10864 10865 if (!alloc_emulate_ctxt(vcpu)) 10866 goto free_wbinvd_dirty_mask; 10867 10868 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) { 10869 pr_err("kvm: failed to allocate vcpu's fpu\n"); 10870 goto free_emulate_ctxt; 10871 } 10872 10873 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 10874 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 10875 10876 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 10877 10878 kvm_async_pf_hash_reset(vcpu); 10879 kvm_pmu_init(vcpu); 10880 10881 vcpu->arch.pending_external_vector = -1; 10882 vcpu->arch.preempted_in_kernel = false; 10883 10884 #if IS_ENABLED(CONFIG_HYPERV) 10885 vcpu->arch.hv_root_tdp = INVALID_PAGE; 10886 #endif 10887 10888 r = static_call(kvm_x86_vcpu_create)(vcpu); 10889 if (r) 10890 goto free_guest_fpu; 10891 10892 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 10893 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 10894 kvm_vcpu_mtrr_init(vcpu); 10895 vcpu_load(vcpu); 10896 kvm_set_tsc_khz(vcpu, max_tsc_khz); 10897 kvm_vcpu_reset(vcpu, false); 10898 kvm_init_mmu(vcpu); 10899 vcpu_put(vcpu); 10900 return 0; 10901 10902 free_guest_fpu: 10903 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 10904 free_emulate_ctxt: 10905 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 10906 free_wbinvd_dirty_mask: 10907 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 10908 fail_free_mce_banks: 10909 kfree(vcpu->arch.mce_banks); 10910 fail_free_pio_data: 10911 free_page((unsigned long)vcpu->arch.pio_data); 10912 fail_free_lapic: 10913 kvm_free_lapic(vcpu); 10914 fail_mmu_destroy: 10915 kvm_mmu_destroy(vcpu); 10916 return r; 10917 } 10918 10919 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 10920 { 10921 struct kvm *kvm = vcpu->kvm; 10922 10923 if (mutex_lock_killable(&vcpu->mutex)) 10924 return; 10925 vcpu_load(vcpu); 10926 kvm_synchronize_tsc(vcpu, 0); 10927 vcpu_put(vcpu); 10928 10929 /* poll control enabled by default */ 10930 vcpu->arch.msr_kvm_poll_control = 1; 10931 10932 mutex_unlock(&vcpu->mutex); 10933 10934 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) 10935 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 10936 KVMCLOCK_SYNC_PERIOD); 10937 } 10938 10939 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 10940 { 10941 int idx; 10942 10943 kvmclock_reset(vcpu); 10944 10945 static_call(kvm_x86_vcpu_free)(vcpu); 10946 10947 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 10948 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 10949 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 10950 10951 kvm_hv_vcpu_uninit(vcpu); 10952 kvm_pmu_destroy(vcpu); 10953 kfree(vcpu->arch.mce_banks); 10954 kvm_free_lapic(vcpu); 10955 idx = srcu_read_lock(&vcpu->kvm->srcu); 10956 kvm_mmu_destroy(vcpu); 10957 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10958 free_page((unsigned long)vcpu->arch.pio_data); 10959 kvfree(vcpu->arch.cpuid_entries); 10960 if (!lapic_in_kernel(vcpu)) 10961 static_branch_dec(&kvm_has_noapic_vcpu); 10962 } 10963 10964 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 10965 { 10966 struct kvm_cpuid_entry2 *cpuid_0x1; 10967 unsigned long old_cr0 = kvm_read_cr0(vcpu); 10968 unsigned long new_cr0; 10969 10970 /* 10971 * Several of the "set" flows, e.g. ->set_cr0(), read other registers 10972 * to handle side effects. RESET emulation hits those flows and relies 10973 * on emulated/virtualized registers, including those that are loaded 10974 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel 10975 * to detect improper or missing initialization. 10976 */ 10977 WARN_ON_ONCE(!init_event && 10978 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu))); 10979 10980 kvm_lapic_reset(vcpu, init_event); 10981 10982 vcpu->arch.hflags = 0; 10983 10984 vcpu->arch.smi_pending = 0; 10985 vcpu->arch.smi_count = 0; 10986 atomic_set(&vcpu->arch.nmi_queued, 0); 10987 vcpu->arch.nmi_pending = 0; 10988 vcpu->arch.nmi_injected = false; 10989 kvm_clear_interrupt_queue(vcpu); 10990 kvm_clear_exception_queue(vcpu); 10991 10992 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 10993 kvm_update_dr0123(vcpu); 10994 vcpu->arch.dr6 = DR6_ACTIVE_LOW; 10995 vcpu->arch.dr7 = DR7_FIXED_1; 10996 kvm_update_dr7(vcpu); 10997 10998 vcpu->arch.cr2 = 0; 10999 11000 kvm_make_request(KVM_REQ_EVENT, vcpu); 11001 vcpu->arch.apf.msr_en_val = 0; 11002 vcpu->arch.apf.msr_int_val = 0; 11003 vcpu->arch.st.msr_val = 0; 11004 11005 kvmclock_reset(vcpu); 11006 11007 kvm_clear_async_pf_completion_queue(vcpu); 11008 kvm_async_pf_hash_reset(vcpu); 11009 vcpu->arch.apf.halted = false; 11010 11011 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) { 11012 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate; 11013 11014 /* 11015 * To avoid have the INIT path from kvm_apic_has_events() that be 11016 * called with loaded FPU and does not let userspace fix the state. 11017 */ 11018 if (init_event) 11019 kvm_put_guest_fpu(vcpu); 11020 11021 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS); 11022 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR); 11023 11024 if (init_event) 11025 kvm_load_guest_fpu(vcpu); 11026 } 11027 11028 if (!init_event) { 11029 kvm_pmu_reset(vcpu); 11030 vcpu->arch.smbase = 0x30000; 11031 11032 vcpu->arch.msr_misc_features_enables = 0; 11033 11034 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 11035 } 11036 11037 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */ 11038 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 11039 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP); 11040 11041 /* 11042 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon) 11043 * if no CPUID match is found. Note, it's impossible to get a match at 11044 * RESET since KVM emulates RESET before exposing the vCPU to userspace, 11045 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry 11046 * on RESET. But, go through the motions in case that's ever remedied. 11047 */ 11048 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1, 0); 11049 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600); 11050 11051 vcpu->arch.ia32_xss = 0; 11052 11053 static_call(kvm_x86_vcpu_reset)(vcpu, init_event); 11054 11055 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 11056 kvm_rip_write(vcpu, 0xfff0); 11057 11058 vcpu->arch.cr3 = 0; 11059 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 11060 11061 /* 11062 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions 11063 * of Intel's SDM list CD/NW as being set on INIT, but they contradict 11064 * (or qualify) that with a footnote stating that CD/NW are preserved. 11065 */ 11066 new_cr0 = X86_CR0_ET; 11067 if (init_event) 11068 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD)); 11069 else 11070 new_cr0 |= X86_CR0_NW | X86_CR0_CD; 11071 11072 static_call(kvm_x86_set_cr0)(vcpu, new_cr0); 11073 static_call(kvm_x86_set_cr4)(vcpu, 0); 11074 static_call(kvm_x86_set_efer)(vcpu, 0); 11075 static_call(kvm_x86_update_exception_bitmap)(vcpu); 11076 11077 /* 11078 * Reset the MMU context if paging was enabled prior to INIT (which is 11079 * implied if CR0.PG=1 as CR0 will be '0' prior to RESET). Unlike the 11080 * standard CR0/CR4/EFER modification paths, only CR0.PG needs to be 11081 * checked because it is unconditionally cleared on INIT and all other 11082 * paging related bits are ignored if paging is disabled, i.e. CR0.WP, 11083 * CR4, and EFER changes are all irrelevant if CR0.PG was '0'. 11084 */ 11085 if (old_cr0 & X86_CR0_PG) 11086 kvm_mmu_reset_context(vcpu); 11087 11088 /* 11089 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's 11090 * APM states the TLBs are untouched by INIT, but it also states that 11091 * the TLBs are flushed on "External initialization of the processor." 11092 * Flush the guest TLB regardless of vendor, there is no meaningful 11093 * benefit in relying on the guest to flush the TLB immediately after 11094 * INIT. A spurious TLB flush is benign and likely negligible from a 11095 * performance perspective. 11096 */ 11097 if (init_event) 11098 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 11099 } 11100 EXPORT_SYMBOL_GPL(kvm_vcpu_reset); 11101 11102 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 11103 { 11104 struct kvm_segment cs; 11105 11106 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 11107 cs.selector = vector << 8; 11108 cs.base = vector << 12; 11109 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 11110 kvm_rip_write(vcpu, 0); 11111 } 11112 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); 11113 11114 int kvm_arch_hardware_enable(void) 11115 { 11116 struct kvm *kvm; 11117 struct kvm_vcpu *vcpu; 11118 int i; 11119 int ret; 11120 u64 local_tsc; 11121 u64 max_tsc = 0; 11122 bool stable, backwards_tsc = false; 11123 11124 kvm_user_return_msr_cpu_online(); 11125 ret = static_call(kvm_x86_hardware_enable)(); 11126 if (ret != 0) 11127 return ret; 11128 11129 local_tsc = rdtsc(); 11130 stable = !kvm_check_tsc_unstable(); 11131 list_for_each_entry(kvm, &vm_list, vm_list) { 11132 kvm_for_each_vcpu(i, vcpu, kvm) { 11133 if (!stable && vcpu->cpu == smp_processor_id()) 11134 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 11135 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 11136 backwards_tsc = true; 11137 if (vcpu->arch.last_host_tsc > max_tsc) 11138 max_tsc = vcpu->arch.last_host_tsc; 11139 } 11140 } 11141 } 11142 11143 /* 11144 * Sometimes, even reliable TSCs go backwards. This happens on 11145 * platforms that reset TSC during suspend or hibernate actions, but 11146 * maintain synchronization. We must compensate. Fortunately, we can 11147 * detect that condition here, which happens early in CPU bringup, 11148 * before any KVM threads can be running. Unfortunately, we can't 11149 * bring the TSCs fully up to date with real time, as we aren't yet far 11150 * enough into CPU bringup that we know how much real time has actually 11151 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot 11152 * variables that haven't been updated yet. 11153 * 11154 * So we simply find the maximum observed TSC above, then record the 11155 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 11156 * the adjustment will be applied. Note that we accumulate 11157 * adjustments, in case multiple suspend cycles happen before some VCPU 11158 * gets a chance to run again. In the event that no KVM threads get a 11159 * chance to run, we will miss the entire elapsed period, as we'll have 11160 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 11161 * loose cycle time. This isn't too big a deal, since the loss will be 11162 * uniform across all VCPUs (not to mention the scenario is extremely 11163 * unlikely). It is possible that a second hibernate recovery happens 11164 * much faster than a first, causing the observed TSC here to be 11165 * smaller; this would require additional padding adjustment, which is 11166 * why we set last_host_tsc to the local tsc observed here. 11167 * 11168 * N.B. - this code below runs only on platforms with reliable TSC, 11169 * as that is the only way backwards_tsc is set above. Also note 11170 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 11171 * have the same delta_cyc adjustment applied if backwards_tsc 11172 * is detected. Note further, this adjustment is only done once, 11173 * as we reset last_host_tsc on all VCPUs to stop this from being 11174 * called multiple times (one for each physical CPU bringup). 11175 * 11176 * Platforms with unreliable TSCs don't have to deal with this, they 11177 * will be compensated by the logic in vcpu_load, which sets the TSC to 11178 * catchup mode. This will catchup all VCPUs to real time, but cannot 11179 * guarantee that they stay in perfect synchronization. 11180 */ 11181 if (backwards_tsc) { 11182 u64 delta_cyc = max_tsc - local_tsc; 11183 list_for_each_entry(kvm, &vm_list, vm_list) { 11184 kvm->arch.backwards_tsc_observed = true; 11185 kvm_for_each_vcpu(i, vcpu, kvm) { 11186 vcpu->arch.tsc_offset_adjustment += delta_cyc; 11187 vcpu->arch.last_host_tsc = local_tsc; 11188 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 11189 } 11190 11191 /* 11192 * We have to disable TSC offset matching.. if you were 11193 * booting a VM while issuing an S4 host suspend.... 11194 * you may have some problem. Solving this issue is 11195 * left as an exercise to the reader. 11196 */ 11197 kvm->arch.last_tsc_nsec = 0; 11198 kvm->arch.last_tsc_write = 0; 11199 } 11200 11201 } 11202 return 0; 11203 } 11204 11205 void kvm_arch_hardware_disable(void) 11206 { 11207 static_call(kvm_x86_hardware_disable)(); 11208 drop_user_return_notifiers(); 11209 } 11210 11211 int kvm_arch_hardware_setup(void *opaque) 11212 { 11213 struct kvm_x86_init_ops *ops = opaque; 11214 int r; 11215 11216 rdmsrl_safe(MSR_EFER, &host_efer); 11217 11218 if (boot_cpu_has(X86_FEATURE_XSAVES)) 11219 rdmsrl(MSR_IA32_XSS, host_xss); 11220 11221 r = ops->hardware_setup(); 11222 if (r != 0) 11223 return r; 11224 11225 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); 11226 kvm_ops_static_call_update(); 11227 11228 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) 11229 supported_xss = 0; 11230 11231 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) 11232 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); 11233 #undef __kvm_cpu_cap_has 11234 11235 if (kvm_has_tsc_control) { 11236 /* 11237 * Make sure the user can only configure tsc_khz values that 11238 * fit into a signed integer. 11239 * A min value is not calculated because it will always 11240 * be 1 on all machines. 11241 */ 11242 u64 max = min(0x7fffffffULL, 11243 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 11244 kvm_max_guest_tsc_khz = max; 11245 11246 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 11247 } 11248 11249 kvm_init_msr_list(); 11250 return 0; 11251 } 11252 11253 void kvm_arch_hardware_unsetup(void) 11254 { 11255 static_call(kvm_x86_hardware_unsetup)(); 11256 } 11257 11258 int kvm_arch_check_processor_compat(void *opaque) 11259 { 11260 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 11261 struct kvm_x86_init_ops *ops = opaque; 11262 11263 WARN_ON(!irqs_disabled()); 11264 11265 if (__cr4_reserved_bits(cpu_has, c) != 11266 __cr4_reserved_bits(cpu_has, &boot_cpu_data)) 11267 return -EIO; 11268 11269 return ops->check_processor_compatibility(); 11270 } 11271 11272 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 11273 { 11274 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 11275 } 11276 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 11277 11278 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 11279 { 11280 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 11281 } 11282 11283 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); 11284 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); 11285 11286 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 11287 { 11288 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 11289 11290 vcpu->arch.l1tf_flush_l1d = true; 11291 if (pmu->version && unlikely(pmu->event_count)) { 11292 pmu->need_cleanup = true; 11293 kvm_make_request(KVM_REQ_PMU, vcpu); 11294 } 11295 static_call(kvm_x86_sched_in)(vcpu, cpu); 11296 } 11297 11298 void kvm_arch_free_vm(struct kvm *kvm) 11299 { 11300 kfree(to_kvm_hv(kvm)->hv_pa_pg); 11301 __kvm_arch_free_vm(kvm); 11302 } 11303 11304 11305 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 11306 { 11307 int ret; 11308 unsigned long flags; 11309 11310 if (type) 11311 return -EINVAL; 11312 11313 ret = kvm_page_track_init(kvm); 11314 if (ret) 11315 return ret; 11316 11317 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 11318 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 11319 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 11320 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); 11321 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 11322 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 11323 11324 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 11325 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 11326 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 11327 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 11328 &kvm->arch.irq_sources_bitmap); 11329 11330 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 11331 mutex_init(&kvm->arch.apic_map_lock); 11332 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock); 11333 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); 11334 11335 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 11336 pvclock_update_vm_gtod_copy(kvm); 11337 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 11338 11339 kvm->arch.guest_can_read_msr_platform_info = true; 11340 11341 #if IS_ENABLED(CONFIG_HYPERV) 11342 spin_lock_init(&kvm->arch.hv_root_tdp_lock); 11343 kvm->arch.hv_root_tdp = INVALID_PAGE; 11344 #endif 11345 11346 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 11347 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 11348 11349 kvm_apicv_init(kvm); 11350 kvm_hv_init_vm(kvm); 11351 kvm_mmu_init_vm(kvm); 11352 kvm_xen_init_vm(kvm); 11353 11354 return static_call(kvm_x86_vm_init)(kvm); 11355 } 11356 11357 int kvm_arch_post_init_vm(struct kvm *kvm) 11358 { 11359 return kvm_mmu_post_init_vm(kvm); 11360 } 11361 11362 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 11363 { 11364 vcpu_load(vcpu); 11365 kvm_mmu_unload(vcpu); 11366 vcpu_put(vcpu); 11367 } 11368 11369 static void kvm_free_vcpus(struct kvm *kvm) 11370 { 11371 unsigned int i; 11372 struct kvm_vcpu *vcpu; 11373 11374 /* 11375 * Unpin any mmu pages first. 11376 */ 11377 kvm_for_each_vcpu(i, vcpu, kvm) { 11378 kvm_clear_async_pf_completion_queue(vcpu); 11379 kvm_unload_vcpu_mmu(vcpu); 11380 } 11381 kvm_for_each_vcpu(i, vcpu, kvm) 11382 kvm_vcpu_destroy(vcpu); 11383 11384 mutex_lock(&kvm->lock); 11385 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 11386 kvm->vcpus[i] = NULL; 11387 11388 atomic_set(&kvm->online_vcpus, 0); 11389 mutex_unlock(&kvm->lock); 11390 } 11391 11392 void kvm_arch_sync_events(struct kvm *kvm) 11393 { 11394 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 11395 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 11396 kvm_free_pit(kvm); 11397 } 11398 11399 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) 11400 11401 /** 11402 * __x86_set_memory_region: Setup KVM internal memory slot 11403 * 11404 * @kvm: the kvm pointer to the VM. 11405 * @id: the slot ID to setup. 11406 * @gpa: the GPA to install the slot (unused when @size == 0). 11407 * @size: the size of the slot. Set to zero to uninstall a slot. 11408 * 11409 * This function helps to setup a KVM internal memory slot. Specify 11410 * @size > 0 to install a new slot, while @size == 0 to uninstall a 11411 * slot. The return code can be one of the following: 11412 * 11413 * HVA: on success (uninstall will return a bogus HVA) 11414 * -errno: on error 11415 * 11416 * The caller should always use IS_ERR() to check the return value 11417 * before use. Note, the KVM internal memory slots are guaranteed to 11418 * remain valid and unchanged until the VM is destroyed, i.e., the 11419 * GPA->HVA translation will not change. However, the HVA is a user 11420 * address, i.e. its accessibility is not guaranteed, and must be 11421 * accessed via __copy_{to,from}_user(). 11422 */ 11423 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, 11424 u32 size) 11425 { 11426 int i, r; 11427 unsigned long hva, old_npages; 11428 struct kvm_memslots *slots = kvm_memslots(kvm); 11429 struct kvm_memory_slot *slot; 11430 11431 /* Called with kvm->slots_lock held. */ 11432 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 11433 return ERR_PTR_USR(-EINVAL); 11434 11435 slot = id_to_memslot(slots, id); 11436 if (size) { 11437 if (slot && slot->npages) 11438 return ERR_PTR_USR(-EEXIST); 11439 11440 /* 11441 * MAP_SHARED to prevent internal slot pages from being moved 11442 * by fork()/COW. 11443 */ 11444 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 11445 MAP_SHARED | MAP_ANONYMOUS, 0); 11446 if (IS_ERR((void *)hva)) 11447 return (void __user *)hva; 11448 } else { 11449 if (!slot || !slot->npages) 11450 return NULL; 11451 11452 old_npages = slot->npages; 11453 hva = slot->userspace_addr; 11454 } 11455 11456 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 11457 struct kvm_userspace_memory_region m; 11458 11459 m.slot = id | (i << 16); 11460 m.flags = 0; 11461 m.guest_phys_addr = gpa; 11462 m.userspace_addr = hva; 11463 m.memory_size = size; 11464 r = __kvm_set_memory_region(kvm, &m); 11465 if (r < 0) 11466 return ERR_PTR_USR(r); 11467 } 11468 11469 if (!size) 11470 vm_munmap(hva, old_npages * PAGE_SIZE); 11471 11472 return (void __user *)hva; 11473 } 11474 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 11475 11476 void kvm_arch_pre_destroy_vm(struct kvm *kvm) 11477 { 11478 kvm_mmu_pre_destroy_vm(kvm); 11479 } 11480 11481 void kvm_arch_destroy_vm(struct kvm *kvm) 11482 { 11483 if (current->mm == kvm->mm) { 11484 /* 11485 * Free memory regions allocated on behalf of userspace, 11486 * unless the the memory map has changed due to process exit 11487 * or fd copying. 11488 */ 11489 mutex_lock(&kvm->slots_lock); 11490 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 11491 0, 0); 11492 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 11493 0, 0); 11494 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 11495 mutex_unlock(&kvm->slots_lock); 11496 } 11497 static_call_cond(kvm_x86_vm_destroy)(kvm); 11498 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); 11499 kvm_pic_destroy(kvm); 11500 kvm_ioapic_destroy(kvm); 11501 kvm_free_vcpus(kvm); 11502 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 11503 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); 11504 kvm_mmu_uninit_vm(kvm); 11505 kvm_page_track_cleanup(kvm); 11506 kvm_xen_destroy_vm(kvm); 11507 kvm_hv_destroy_vm(kvm); 11508 } 11509 11510 static void memslot_rmap_free(struct kvm_memory_slot *slot) 11511 { 11512 int i; 11513 11514 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 11515 kvfree(slot->arch.rmap[i]); 11516 slot->arch.rmap[i] = NULL; 11517 } 11518 } 11519 11520 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) 11521 { 11522 int i; 11523 11524 memslot_rmap_free(slot); 11525 11526 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 11527 kvfree(slot->arch.lpage_info[i - 1]); 11528 slot->arch.lpage_info[i - 1] = NULL; 11529 } 11530 11531 kvm_page_track_free_memslot(slot); 11532 } 11533 11534 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages) 11535 { 11536 const int sz = sizeof(*slot->arch.rmap[0]); 11537 int i; 11538 11539 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 11540 int level = i + 1; 11541 int lpages = __kvm_mmu_slot_lpages(slot, npages, level); 11542 11543 if (slot->arch.rmap[i]) 11544 continue; 11545 11546 slot->arch.rmap[i] = kvcalloc(lpages, sz, GFP_KERNEL_ACCOUNT); 11547 if (!slot->arch.rmap[i]) { 11548 memslot_rmap_free(slot); 11549 return -ENOMEM; 11550 } 11551 } 11552 11553 return 0; 11554 } 11555 11556 static int kvm_alloc_memslot_metadata(struct kvm *kvm, 11557 struct kvm_memory_slot *slot, 11558 unsigned long npages) 11559 { 11560 int i, r; 11561 11562 /* 11563 * Clear out the previous array pointers for the KVM_MR_MOVE case. The 11564 * old arrays will be freed by __kvm_set_memory_region() if installing 11565 * the new memslot is successful. 11566 */ 11567 memset(&slot->arch, 0, sizeof(slot->arch)); 11568 11569 if (kvm_memslots_have_rmaps(kvm)) { 11570 r = memslot_rmap_alloc(slot, npages); 11571 if (r) 11572 return r; 11573 } 11574 11575 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 11576 struct kvm_lpage_info *linfo; 11577 unsigned long ugfn; 11578 int lpages; 11579 int level = i + 1; 11580 11581 lpages = __kvm_mmu_slot_lpages(slot, npages, level); 11582 11583 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 11584 if (!linfo) 11585 goto out_free; 11586 11587 slot->arch.lpage_info[i - 1] = linfo; 11588 11589 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 11590 linfo[0].disallow_lpage = 1; 11591 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 11592 linfo[lpages - 1].disallow_lpage = 1; 11593 ugfn = slot->userspace_addr >> PAGE_SHIFT; 11594 /* 11595 * If the gfn and userspace address are not aligned wrt each 11596 * other, disable large page support for this slot. 11597 */ 11598 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { 11599 unsigned long j; 11600 11601 for (j = 0; j < lpages; ++j) 11602 linfo[j].disallow_lpage = 1; 11603 } 11604 } 11605 11606 if (kvm_page_track_create_memslot(kvm, slot, npages)) 11607 goto out_free; 11608 11609 return 0; 11610 11611 out_free: 11612 memslot_rmap_free(slot); 11613 11614 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 11615 kvfree(slot->arch.lpage_info[i - 1]); 11616 slot->arch.lpage_info[i - 1] = NULL; 11617 } 11618 return -ENOMEM; 11619 } 11620 11621 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 11622 { 11623 struct kvm_vcpu *vcpu; 11624 int i; 11625 11626 /* 11627 * memslots->generation has been incremented. 11628 * mmio generation may have reached its maximum value. 11629 */ 11630 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 11631 11632 /* Force re-initialization of steal_time cache */ 11633 kvm_for_each_vcpu(i, vcpu, kvm) 11634 kvm_vcpu_kick(vcpu); 11635 } 11636 11637 int kvm_arch_prepare_memory_region(struct kvm *kvm, 11638 struct kvm_memory_slot *memslot, 11639 const struct kvm_userspace_memory_region *mem, 11640 enum kvm_mr_change change) 11641 { 11642 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) 11643 return kvm_alloc_memslot_metadata(kvm, memslot, 11644 mem->memory_size >> PAGE_SHIFT); 11645 return 0; 11646 } 11647 11648 11649 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) 11650 { 11651 struct kvm_arch *ka = &kvm->arch; 11652 11653 if (!kvm_x86_ops.cpu_dirty_log_size) 11654 return; 11655 11656 if ((enable && ++ka->cpu_dirty_logging_count == 1) || 11657 (!enable && --ka->cpu_dirty_logging_count == 0)) 11658 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); 11659 11660 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); 11661 } 11662 11663 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 11664 struct kvm_memory_slot *old, 11665 const struct kvm_memory_slot *new, 11666 enum kvm_mr_change change) 11667 { 11668 bool log_dirty_pages = new->flags & KVM_MEM_LOG_DIRTY_PAGES; 11669 11670 /* 11671 * Update CPU dirty logging if dirty logging is being toggled. This 11672 * applies to all operations. 11673 */ 11674 if ((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES) 11675 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); 11676 11677 /* 11678 * Nothing more to do for RO slots (which can't be dirtied and can't be 11679 * made writable) or CREATE/MOVE/DELETE of a slot. 11680 * 11681 * For a memslot with dirty logging disabled: 11682 * CREATE: No dirty mappings will already exist. 11683 * MOVE/DELETE: The old mappings will already have been cleaned up by 11684 * kvm_arch_flush_shadow_memslot() 11685 * 11686 * For a memslot with dirty logging enabled: 11687 * CREATE: No shadow pages exist, thus nothing to write-protect 11688 * and no dirty bits to clear. 11689 * MOVE/DELETE: The old mappings will already have been cleaned up by 11690 * kvm_arch_flush_shadow_memslot(). 11691 */ 11692 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) 11693 return; 11694 11695 /* 11696 * READONLY and non-flags changes were filtered out above, and the only 11697 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty 11698 * logging isn't being toggled on or off. 11699 */ 11700 if (WARN_ON_ONCE(!((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES))) 11701 return; 11702 11703 if (!log_dirty_pages) { 11704 /* 11705 * Dirty logging tracks sptes in 4k granularity, meaning that 11706 * large sptes have to be split. If live migration succeeds, 11707 * the guest in the source machine will be destroyed and large 11708 * sptes will be created in the destination. However, if the 11709 * guest continues to run in the source machine (for example if 11710 * live migration fails), small sptes will remain around and 11711 * cause bad performance. 11712 * 11713 * Scan sptes if dirty logging has been stopped, dropping those 11714 * which can be collapsed into a single large-page spte. Later 11715 * page faults will create the large-page sptes. 11716 */ 11717 kvm_mmu_zap_collapsible_sptes(kvm, new); 11718 } else { 11719 /* 11720 * Initially-all-set does not require write protecting any page, 11721 * because they're all assumed to be dirty. 11722 */ 11723 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) 11724 return; 11725 11726 if (kvm_x86_ops.cpu_dirty_log_size) { 11727 kvm_mmu_slot_leaf_clear_dirty(kvm, new); 11728 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M); 11729 } else { 11730 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K); 11731 } 11732 } 11733 } 11734 11735 void kvm_arch_commit_memory_region(struct kvm *kvm, 11736 const struct kvm_userspace_memory_region *mem, 11737 struct kvm_memory_slot *old, 11738 const struct kvm_memory_slot *new, 11739 enum kvm_mr_change change) 11740 { 11741 if (!kvm->arch.n_requested_mmu_pages) 11742 kvm_mmu_change_mmu_pages(kvm, 11743 kvm_mmu_calculate_default_mmu_pages(kvm)); 11744 11745 kvm_mmu_slot_apply_flags(kvm, old, new, change); 11746 11747 /* Free the arrays associated with the old memslot. */ 11748 if (change == KVM_MR_MOVE) 11749 kvm_arch_free_memslot(kvm, old); 11750 } 11751 11752 void kvm_arch_flush_shadow_all(struct kvm *kvm) 11753 { 11754 kvm_mmu_zap_all(kvm); 11755 } 11756 11757 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 11758 struct kvm_memory_slot *slot) 11759 { 11760 kvm_page_track_flush_slot(kvm, slot); 11761 } 11762 11763 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 11764 { 11765 return (is_guest_mode(vcpu) && 11766 kvm_x86_ops.guest_apic_has_interrupt && 11767 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); 11768 } 11769 11770 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 11771 { 11772 if (!list_empty_careful(&vcpu->async_pf.done)) 11773 return true; 11774 11775 if (kvm_apic_has_events(vcpu)) 11776 return true; 11777 11778 if (vcpu->arch.pv.pv_unhalted) 11779 return true; 11780 11781 if (vcpu->arch.exception.pending) 11782 return true; 11783 11784 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 11785 (vcpu->arch.nmi_pending && 11786 static_call(kvm_x86_nmi_allowed)(vcpu, false))) 11787 return true; 11788 11789 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 11790 (vcpu->arch.smi_pending && 11791 static_call(kvm_x86_smi_allowed)(vcpu, false))) 11792 return true; 11793 11794 if (kvm_arch_interrupt_allowed(vcpu) && 11795 (kvm_cpu_has_interrupt(vcpu) || 11796 kvm_guest_apic_has_interrupt(vcpu))) 11797 return true; 11798 11799 if (kvm_hv_has_stimer_pending(vcpu)) 11800 return true; 11801 11802 if (is_guest_mode(vcpu) && 11803 kvm_x86_ops.nested_ops->hv_timer_pending && 11804 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 11805 return true; 11806 11807 return false; 11808 } 11809 11810 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 11811 { 11812 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 11813 } 11814 11815 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) 11816 { 11817 if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) 11818 return true; 11819 11820 return false; 11821 } 11822 11823 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) 11824 { 11825 if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) 11826 return true; 11827 11828 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 11829 kvm_test_request(KVM_REQ_SMI, vcpu) || 11830 kvm_test_request(KVM_REQ_EVENT, vcpu)) 11831 return true; 11832 11833 return kvm_arch_dy_has_pending_interrupt(vcpu); 11834 } 11835 11836 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 11837 { 11838 if (vcpu->arch.guest_state_protected) 11839 return true; 11840 11841 return vcpu->arch.preempted_in_kernel; 11842 } 11843 11844 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 11845 { 11846 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 11847 } 11848 11849 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 11850 { 11851 return static_call(kvm_x86_interrupt_allowed)(vcpu, false); 11852 } 11853 11854 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 11855 { 11856 /* Can't read the RIP when guest state is protected, just return 0 */ 11857 if (vcpu->arch.guest_state_protected) 11858 return 0; 11859 11860 if (is_64_bit_mode(vcpu)) 11861 return kvm_rip_read(vcpu); 11862 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 11863 kvm_rip_read(vcpu)); 11864 } 11865 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 11866 11867 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 11868 { 11869 return kvm_get_linear_rip(vcpu) == linear_rip; 11870 } 11871 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 11872 11873 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 11874 { 11875 unsigned long rflags; 11876 11877 rflags = static_call(kvm_x86_get_rflags)(vcpu); 11878 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 11879 rflags &= ~X86_EFLAGS_TF; 11880 return rflags; 11881 } 11882 EXPORT_SYMBOL_GPL(kvm_get_rflags); 11883 11884 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 11885 { 11886 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 11887 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 11888 rflags |= X86_EFLAGS_TF; 11889 static_call(kvm_x86_set_rflags)(vcpu, rflags); 11890 } 11891 11892 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 11893 { 11894 __kvm_set_rflags(vcpu, rflags); 11895 kvm_make_request(KVM_REQ_EVENT, vcpu); 11896 } 11897 EXPORT_SYMBOL_GPL(kvm_set_rflags); 11898 11899 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 11900 { 11901 int r; 11902 11903 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || 11904 work->wakeup_all) 11905 return; 11906 11907 r = kvm_mmu_reload(vcpu); 11908 if (unlikely(r)) 11909 return; 11910 11911 if (!vcpu->arch.mmu->direct_map && 11912 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) 11913 return; 11914 11915 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); 11916 } 11917 11918 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 11919 { 11920 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); 11921 11922 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 11923 } 11924 11925 static inline u32 kvm_async_pf_next_probe(u32 key) 11926 { 11927 return (key + 1) & (ASYNC_PF_PER_VCPU - 1); 11928 } 11929 11930 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11931 { 11932 u32 key = kvm_async_pf_hash_fn(gfn); 11933 11934 while (vcpu->arch.apf.gfns[key] != ~0) 11935 key = kvm_async_pf_next_probe(key); 11936 11937 vcpu->arch.apf.gfns[key] = gfn; 11938 } 11939 11940 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 11941 { 11942 int i; 11943 u32 key = kvm_async_pf_hash_fn(gfn); 11944 11945 for (i = 0; i < ASYNC_PF_PER_VCPU && 11946 (vcpu->arch.apf.gfns[key] != gfn && 11947 vcpu->arch.apf.gfns[key] != ~0); i++) 11948 key = kvm_async_pf_next_probe(key); 11949 11950 return key; 11951 } 11952 11953 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11954 { 11955 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 11956 } 11957 11958 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11959 { 11960 u32 i, j, k; 11961 11962 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 11963 11964 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) 11965 return; 11966 11967 while (true) { 11968 vcpu->arch.apf.gfns[i] = ~0; 11969 do { 11970 j = kvm_async_pf_next_probe(j); 11971 if (vcpu->arch.apf.gfns[j] == ~0) 11972 return; 11973 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 11974 /* 11975 * k lies cyclically in ]i,j] 11976 * | i.k.j | 11977 * |....j i.k.| or |.k..j i...| 11978 */ 11979 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 11980 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 11981 i = j; 11982 } 11983 } 11984 11985 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) 11986 { 11987 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; 11988 11989 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, 11990 sizeof(reason)); 11991 } 11992 11993 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) 11994 { 11995 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 11996 11997 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 11998 &token, offset, sizeof(token)); 11999 } 12000 12001 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) 12002 { 12003 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 12004 u32 val; 12005 12006 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 12007 &val, offset, sizeof(val))) 12008 return false; 12009 12010 return !val; 12011 } 12012 12013 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) 12014 { 12015 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) 12016 return false; 12017 12018 if (!kvm_pv_async_pf_enabled(vcpu) || 12019 (vcpu->arch.apf.send_user_only && static_call(kvm_x86_get_cpl)(vcpu) == 0)) 12020 return false; 12021 12022 return true; 12023 } 12024 12025 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) 12026 { 12027 if (unlikely(!lapic_in_kernel(vcpu) || 12028 kvm_event_needs_reinjection(vcpu) || 12029 vcpu->arch.exception.pending)) 12030 return false; 12031 12032 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) 12033 return false; 12034 12035 /* 12036 * If interrupts are off we cannot even use an artificial 12037 * halt state. 12038 */ 12039 return kvm_arch_interrupt_allowed(vcpu); 12040 } 12041 12042 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 12043 struct kvm_async_pf *work) 12044 { 12045 struct x86_exception fault; 12046 12047 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); 12048 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 12049 12050 if (kvm_can_deliver_async_pf(vcpu) && 12051 !apf_put_user_notpresent(vcpu)) { 12052 fault.vector = PF_VECTOR; 12053 fault.error_code_valid = true; 12054 fault.error_code = 0; 12055 fault.nested_page_fault = false; 12056 fault.address = work->arch.token; 12057 fault.async_page_fault = true; 12058 kvm_inject_page_fault(vcpu, &fault); 12059 return true; 12060 } else { 12061 /* 12062 * It is not possible to deliver a paravirtualized asynchronous 12063 * page fault, but putting the guest in an artificial halt state 12064 * can be beneficial nevertheless: if an interrupt arrives, we 12065 * can deliver it timely and perhaps the guest will schedule 12066 * another process. When the instruction that triggered a page 12067 * fault is retried, hopefully the page will be ready in the host. 12068 */ 12069 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 12070 return false; 12071 } 12072 } 12073 12074 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 12075 struct kvm_async_pf *work) 12076 { 12077 struct kvm_lapic_irq irq = { 12078 .delivery_mode = APIC_DM_FIXED, 12079 .vector = vcpu->arch.apf.vec 12080 }; 12081 12082 if (work->wakeup_all) 12083 work->arch.token = ~0; /* broadcast wakeup */ 12084 else 12085 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 12086 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); 12087 12088 if ((work->wakeup_all || work->notpresent_injected) && 12089 kvm_pv_async_pf_enabled(vcpu) && 12090 !apf_put_user_ready(vcpu, work->arch.token)) { 12091 vcpu->arch.apf.pageready_pending = true; 12092 kvm_apic_set_irq(vcpu, &irq, NULL); 12093 } 12094 12095 vcpu->arch.apf.halted = false; 12096 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 12097 } 12098 12099 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) 12100 { 12101 kvm_make_request(KVM_REQ_APF_READY, vcpu); 12102 if (!vcpu->arch.apf.pageready_pending) 12103 kvm_vcpu_kick(vcpu); 12104 } 12105 12106 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) 12107 { 12108 if (!kvm_pv_async_pf_enabled(vcpu)) 12109 return true; 12110 else 12111 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); 12112 } 12113 12114 void kvm_arch_start_assignment(struct kvm *kvm) 12115 { 12116 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) 12117 static_call_cond(kvm_x86_start_assignment)(kvm); 12118 } 12119 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 12120 12121 void kvm_arch_end_assignment(struct kvm *kvm) 12122 { 12123 atomic_dec(&kvm->arch.assigned_device_count); 12124 } 12125 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 12126 12127 bool kvm_arch_has_assigned_device(struct kvm *kvm) 12128 { 12129 return atomic_read(&kvm->arch.assigned_device_count); 12130 } 12131 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 12132 12133 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 12134 { 12135 atomic_inc(&kvm->arch.noncoherent_dma_count); 12136 } 12137 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 12138 12139 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 12140 { 12141 atomic_dec(&kvm->arch.noncoherent_dma_count); 12142 } 12143 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 12144 12145 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 12146 { 12147 return atomic_read(&kvm->arch.noncoherent_dma_count); 12148 } 12149 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 12150 12151 bool kvm_arch_has_irq_bypass(void) 12152 { 12153 return true; 12154 } 12155 12156 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 12157 struct irq_bypass_producer *prod) 12158 { 12159 struct kvm_kernel_irqfd *irqfd = 12160 container_of(cons, struct kvm_kernel_irqfd, consumer); 12161 int ret; 12162 12163 irqfd->producer = prod; 12164 kvm_arch_start_assignment(irqfd->kvm); 12165 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, 12166 prod->irq, irqfd->gsi, 1); 12167 12168 if (ret) 12169 kvm_arch_end_assignment(irqfd->kvm); 12170 12171 return ret; 12172 } 12173 12174 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 12175 struct irq_bypass_producer *prod) 12176 { 12177 int ret; 12178 struct kvm_kernel_irqfd *irqfd = 12179 container_of(cons, struct kvm_kernel_irqfd, consumer); 12180 12181 WARN_ON(irqfd->producer != prod); 12182 irqfd->producer = NULL; 12183 12184 /* 12185 * When producer of consumer is unregistered, we change back to 12186 * remapped mode, so we can re-use the current implementation 12187 * when the irq is masked/disabled or the consumer side (KVM 12188 * int this case doesn't want to receive the interrupts. 12189 */ 12190 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); 12191 if (ret) 12192 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 12193 " fails: %d\n", irqfd->consumer.token, ret); 12194 12195 kvm_arch_end_assignment(irqfd->kvm); 12196 } 12197 12198 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 12199 uint32_t guest_irq, bool set) 12200 { 12201 return static_call(kvm_x86_update_pi_irte)(kvm, host_irq, guest_irq, set); 12202 } 12203 12204 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old, 12205 struct kvm_kernel_irq_routing_entry *new) 12206 { 12207 if (new->type != KVM_IRQ_ROUTING_MSI) 12208 return true; 12209 12210 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi)); 12211 } 12212 12213 bool kvm_vector_hashing_enabled(void) 12214 { 12215 return vector_hashing; 12216 } 12217 12218 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) 12219 { 12220 return (vcpu->arch.msr_kvm_poll_control & 1) == 0; 12221 } 12222 EXPORT_SYMBOL_GPL(kvm_arch_no_poll); 12223 12224 12225 int kvm_spec_ctrl_test_value(u64 value) 12226 { 12227 /* 12228 * test that setting IA32_SPEC_CTRL to given value 12229 * is allowed by the host processor 12230 */ 12231 12232 u64 saved_value; 12233 unsigned long flags; 12234 int ret = 0; 12235 12236 local_irq_save(flags); 12237 12238 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) 12239 ret = 1; 12240 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) 12241 ret = 1; 12242 else 12243 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); 12244 12245 local_irq_restore(flags); 12246 12247 return ret; 12248 } 12249 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); 12250 12251 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) 12252 { 12253 struct x86_exception fault; 12254 u32 access = error_code & 12255 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); 12256 12257 if (!(error_code & PFERR_PRESENT_MASK) || 12258 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) { 12259 /* 12260 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page 12261 * tables probably do not match the TLB. Just proceed 12262 * with the error code that the processor gave. 12263 */ 12264 fault.vector = PF_VECTOR; 12265 fault.error_code_valid = true; 12266 fault.error_code = error_code; 12267 fault.nested_page_fault = false; 12268 fault.address = gva; 12269 } 12270 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); 12271 } 12272 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); 12273 12274 /* 12275 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns 12276 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value 12277 * indicates whether exit to userspace is needed. 12278 */ 12279 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 12280 struct x86_exception *e) 12281 { 12282 if (r == X86EMUL_PROPAGATE_FAULT) { 12283 kvm_inject_emulated_page_fault(vcpu, e); 12284 return 1; 12285 } 12286 12287 /* 12288 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED 12289 * while handling a VMX instruction KVM could've handled the request 12290 * correctly by exiting to userspace and performing I/O but there 12291 * doesn't seem to be a real use-case behind such requests, just return 12292 * KVM_EXIT_INTERNAL_ERROR for now. 12293 */ 12294 kvm_prepare_emulation_failure_exit(vcpu); 12295 12296 return 0; 12297 } 12298 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); 12299 12300 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) 12301 { 12302 bool pcid_enabled; 12303 struct x86_exception e; 12304 struct { 12305 u64 pcid; 12306 u64 gla; 12307 } operand; 12308 int r; 12309 12310 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 12311 if (r != X86EMUL_CONTINUE) 12312 return kvm_handle_memory_failure(vcpu, r, &e); 12313 12314 if (operand.pcid >> 12 != 0) { 12315 kvm_inject_gp(vcpu, 0); 12316 return 1; 12317 } 12318 12319 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 12320 12321 switch (type) { 12322 case INVPCID_TYPE_INDIV_ADDR: 12323 if ((!pcid_enabled && (operand.pcid != 0)) || 12324 is_noncanonical_address(operand.gla, vcpu)) { 12325 kvm_inject_gp(vcpu, 0); 12326 return 1; 12327 } 12328 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 12329 return kvm_skip_emulated_instruction(vcpu); 12330 12331 case INVPCID_TYPE_SINGLE_CTXT: 12332 if (!pcid_enabled && (operand.pcid != 0)) { 12333 kvm_inject_gp(vcpu, 0); 12334 return 1; 12335 } 12336 12337 kvm_invalidate_pcid(vcpu, operand.pcid); 12338 return kvm_skip_emulated_instruction(vcpu); 12339 12340 case INVPCID_TYPE_ALL_NON_GLOBAL: 12341 /* 12342 * Currently, KVM doesn't mark global entries in the shadow 12343 * page tables, so a non-global flush just degenerates to a 12344 * global flush. If needed, we could optimize this later by 12345 * keeping track of global entries in shadow page tables. 12346 */ 12347 12348 fallthrough; 12349 case INVPCID_TYPE_ALL_INCL_GLOBAL: 12350 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 12351 return kvm_skip_emulated_instruction(vcpu); 12352 12353 default: 12354 kvm_inject_gp(vcpu, 0); 12355 return 1; 12356 } 12357 } 12358 EXPORT_SYMBOL_GPL(kvm_handle_invpcid); 12359 12360 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) 12361 { 12362 struct kvm_run *run = vcpu->run; 12363 struct kvm_mmio_fragment *frag; 12364 unsigned int len; 12365 12366 BUG_ON(!vcpu->mmio_needed); 12367 12368 /* Complete previous fragment */ 12369 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 12370 len = min(8u, frag->len); 12371 if (!vcpu->mmio_is_write) 12372 memcpy(frag->data, run->mmio.data, len); 12373 12374 if (frag->len <= 8) { 12375 /* Switch to the next fragment. */ 12376 frag++; 12377 vcpu->mmio_cur_fragment++; 12378 } else { 12379 /* Go forward to the next mmio piece. */ 12380 frag->data += len; 12381 frag->gpa += len; 12382 frag->len -= len; 12383 } 12384 12385 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 12386 vcpu->mmio_needed = 0; 12387 12388 // VMG change, at this point, we're always done 12389 // RIP has already been advanced 12390 return 1; 12391 } 12392 12393 // More MMIO is needed 12394 run->mmio.phys_addr = frag->gpa; 12395 run->mmio.len = min(8u, frag->len); 12396 run->mmio.is_write = vcpu->mmio_is_write; 12397 if (run->mmio.is_write) 12398 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 12399 run->exit_reason = KVM_EXIT_MMIO; 12400 12401 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12402 12403 return 0; 12404 } 12405 12406 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 12407 void *data) 12408 { 12409 int handled; 12410 struct kvm_mmio_fragment *frag; 12411 12412 if (!data) 12413 return -EINVAL; 12414 12415 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); 12416 if (handled == bytes) 12417 return 1; 12418 12419 bytes -= handled; 12420 gpa += handled; 12421 data += handled; 12422 12423 /*TODO: Check if need to increment number of frags */ 12424 frag = vcpu->mmio_fragments; 12425 vcpu->mmio_nr_fragments = 1; 12426 frag->len = bytes; 12427 frag->gpa = gpa; 12428 frag->data = data; 12429 12430 vcpu->mmio_needed = 1; 12431 vcpu->mmio_cur_fragment = 0; 12432 12433 vcpu->run->mmio.phys_addr = gpa; 12434 vcpu->run->mmio.len = min(8u, frag->len); 12435 vcpu->run->mmio.is_write = 1; 12436 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 12437 vcpu->run->exit_reason = KVM_EXIT_MMIO; 12438 12439 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12440 12441 return 0; 12442 } 12443 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); 12444 12445 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 12446 void *data) 12447 { 12448 int handled; 12449 struct kvm_mmio_fragment *frag; 12450 12451 if (!data) 12452 return -EINVAL; 12453 12454 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); 12455 if (handled == bytes) 12456 return 1; 12457 12458 bytes -= handled; 12459 gpa += handled; 12460 data += handled; 12461 12462 /*TODO: Check if need to increment number of frags */ 12463 frag = vcpu->mmio_fragments; 12464 vcpu->mmio_nr_fragments = 1; 12465 frag->len = bytes; 12466 frag->gpa = gpa; 12467 frag->data = data; 12468 12469 vcpu->mmio_needed = 1; 12470 vcpu->mmio_cur_fragment = 0; 12471 12472 vcpu->run->mmio.phys_addr = gpa; 12473 vcpu->run->mmio.len = min(8u, frag->len); 12474 vcpu->run->mmio.is_write = 0; 12475 vcpu->run->exit_reason = KVM_EXIT_MMIO; 12476 12477 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12478 12479 return 0; 12480 } 12481 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); 12482 12483 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 12484 unsigned int port); 12485 12486 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu) 12487 { 12488 int size = vcpu->arch.pio.size; 12489 int port = vcpu->arch.pio.port; 12490 12491 vcpu->arch.pio.count = 0; 12492 if (vcpu->arch.sev_pio_count) 12493 return kvm_sev_es_outs(vcpu, size, port); 12494 return 1; 12495 } 12496 12497 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 12498 unsigned int port) 12499 { 12500 for (;;) { 12501 unsigned int count = 12502 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 12503 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count); 12504 12505 /* memcpy done already by emulator_pio_out. */ 12506 vcpu->arch.sev_pio_count -= count; 12507 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size; 12508 if (!ret) 12509 break; 12510 12511 /* Emulation done by the kernel. */ 12512 if (!vcpu->arch.sev_pio_count) 12513 return 1; 12514 } 12515 12516 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs; 12517 return 0; 12518 } 12519 12520 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 12521 unsigned int port); 12522 12523 static void advance_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 12524 { 12525 unsigned count = vcpu->arch.pio.count; 12526 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data); 12527 vcpu->arch.sev_pio_count -= count; 12528 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size; 12529 } 12530 12531 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 12532 { 12533 int size = vcpu->arch.pio.size; 12534 int port = vcpu->arch.pio.port; 12535 12536 advance_sev_es_emulated_ins(vcpu); 12537 if (vcpu->arch.sev_pio_count) 12538 return kvm_sev_es_ins(vcpu, size, port); 12539 return 1; 12540 } 12541 12542 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 12543 unsigned int port) 12544 { 12545 for (;;) { 12546 unsigned int count = 12547 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 12548 if (!__emulator_pio_in(vcpu, size, port, count)) 12549 break; 12550 12551 /* Emulation done by the kernel. */ 12552 advance_sev_es_emulated_ins(vcpu); 12553 if (!vcpu->arch.sev_pio_count) 12554 return 1; 12555 } 12556 12557 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; 12558 return 0; 12559 } 12560 12561 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 12562 unsigned int port, void *data, unsigned int count, 12563 int in) 12564 { 12565 vcpu->arch.sev_pio_data = data; 12566 vcpu->arch.sev_pio_count = count; 12567 return in ? kvm_sev_es_ins(vcpu, size, port) 12568 : kvm_sev_es_outs(vcpu, size, port); 12569 } 12570 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); 12571 12572 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); 12573 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 12574 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 12575 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 12576 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 12577 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 12578 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 12579 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 12580 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 12581 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 12582 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 12583 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); 12584 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 12585 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 12586 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 12587 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 12588 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); 12589 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 12590 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 12591 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 12592 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 12593 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); 12594 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); 12595 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); 12596 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); 12597 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); 12598 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); 12599