1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "pmu.h" 31 #include "hyperv.h" 32 33 #include <linux/clocksource.h> 34 #include <linux/interrupt.h> 35 #include <linux/kvm.h> 36 #include <linux/fs.h> 37 #include <linux/vmalloc.h> 38 #include <linux/export.h> 39 #include <linux/moduleparam.h> 40 #include <linux/mman.h> 41 #include <linux/highmem.h> 42 #include <linux/iommu.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/cpufreq.h> 45 #include <linux/user-return-notifier.h> 46 #include <linux/srcu.h> 47 #include <linux/slab.h> 48 #include <linux/perf_event.h> 49 #include <linux/uaccess.h> 50 #include <linux/hash.h> 51 #include <linux/pci.h> 52 #include <linux/timekeeper_internal.h> 53 #include <linux/pvclock_gtod.h> 54 #include <linux/kvm_irqfd.h> 55 #include <linux/irqbypass.h> 56 #include <linux/sched/stat.h> 57 #include <linux/mem_encrypt.h> 58 59 #include <trace/events/kvm.h> 60 61 #include <asm/debugreg.h> 62 #include <asm/msr.h> 63 #include <asm/desc.h> 64 #include <asm/mce.h> 65 #include <linux/kernel_stat.h> 66 #include <asm/fpu/internal.h> /* Ugh! */ 67 #include <asm/pvclock.h> 68 #include <asm/div64.h> 69 #include <asm/irq_remapping.h> 70 71 #define CREATE_TRACE_POINTS 72 #include "trace.h" 73 74 #define MAX_IO_MSRS 256 75 #define KVM_MAX_MCE_BANKS 32 76 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 77 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 78 79 #define emul_to_vcpu(ctxt) \ 80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 81 82 /* EFER defaults: 83 * - enable syscall per default because its emulated by KVM 84 * - enable LME and LMA per default on 64 bit KVM 85 */ 86 #ifdef CONFIG_X86_64 87 static 88 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 89 #else 90 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 91 #endif 92 93 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 94 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 95 96 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 98 99 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 100 static void process_nmi(struct kvm_vcpu *vcpu); 101 static void enter_smm(struct kvm_vcpu *vcpu); 102 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 103 104 struct kvm_x86_ops *kvm_x86_ops __read_mostly; 105 EXPORT_SYMBOL_GPL(kvm_x86_ops); 106 107 static bool __read_mostly ignore_msrs = 0; 108 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 109 110 static bool __read_mostly report_ignored_msrs = true; 111 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 112 113 unsigned int min_timer_period_us = 500; 114 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 115 116 static bool __read_mostly kvmclock_periodic_sync = true; 117 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 118 119 bool __read_mostly kvm_has_tsc_control; 120 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 121 u32 __read_mostly kvm_max_guest_tsc_khz; 122 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 123 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 124 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 125 u64 __read_mostly kvm_max_tsc_scaling_ratio; 126 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 127 u64 __read_mostly kvm_default_tsc_scaling_ratio; 128 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 129 130 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 131 static u32 __read_mostly tsc_tolerance_ppm = 250; 132 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 133 134 /* lapic timer advance (tscdeadline mode only) in nanoseconds */ 135 unsigned int __read_mostly lapic_timer_advance_ns = 0; 136 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 137 138 static bool __read_mostly vector_hashing = true; 139 module_param(vector_hashing, bool, S_IRUGO); 140 141 #define KVM_NR_SHARED_MSRS 16 142 143 struct kvm_shared_msrs_global { 144 int nr; 145 u32 msrs[KVM_NR_SHARED_MSRS]; 146 }; 147 148 struct kvm_shared_msrs { 149 struct user_return_notifier urn; 150 bool registered; 151 struct kvm_shared_msr_values { 152 u64 host; 153 u64 curr; 154 } values[KVM_NR_SHARED_MSRS]; 155 }; 156 157 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 158 static struct kvm_shared_msrs __percpu *shared_msrs; 159 160 struct kvm_stats_debugfs_item debugfs_entries[] = { 161 { "pf_fixed", VCPU_STAT(pf_fixed) }, 162 { "pf_guest", VCPU_STAT(pf_guest) }, 163 { "tlb_flush", VCPU_STAT(tlb_flush) }, 164 { "invlpg", VCPU_STAT(invlpg) }, 165 { "exits", VCPU_STAT(exits) }, 166 { "io_exits", VCPU_STAT(io_exits) }, 167 { "mmio_exits", VCPU_STAT(mmio_exits) }, 168 { "signal_exits", VCPU_STAT(signal_exits) }, 169 { "irq_window", VCPU_STAT(irq_window_exits) }, 170 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 171 { "halt_exits", VCPU_STAT(halt_exits) }, 172 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 173 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 174 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, 175 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 176 { "hypercalls", VCPU_STAT(hypercalls) }, 177 { "request_irq", VCPU_STAT(request_irq_exits) }, 178 { "irq_exits", VCPU_STAT(irq_exits) }, 179 { "host_state_reload", VCPU_STAT(host_state_reload) }, 180 { "efer_reload", VCPU_STAT(efer_reload) }, 181 { "fpu_reload", VCPU_STAT(fpu_reload) }, 182 { "insn_emulation", VCPU_STAT(insn_emulation) }, 183 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 184 { "irq_injections", VCPU_STAT(irq_injections) }, 185 { "nmi_injections", VCPU_STAT(nmi_injections) }, 186 { "req_event", VCPU_STAT(req_event) }, 187 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 188 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 189 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 190 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 191 { "mmu_flooded", VM_STAT(mmu_flooded) }, 192 { "mmu_recycled", VM_STAT(mmu_recycled) }, 193 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 194 { "mmu_unsync", VM_STAT(mmu_unsync) }, 195 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 196 { "largepages", VM_STAT(lpages) }, 197 { "max_mmu_page_hash_collisions", 198 VM_STAT(max_mmu_page_hash_collisions) }, 199 { NULL } 200 }; 201 202 u64 __read_mostly host_xcr0; 203 204 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 205 206 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 207 { 208 int i; 209 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 210 vcpu->arch.apf.gfns[i] = ~0; 211 } 212 213 static void kvm_on_user_return(struct user_return_notifier *urn) 214 { 215 unsigned slot; 216 struct kvm_shared_msrs *locals 217 = container_of(urn, struct kvm_shared_msrs, urn); 218 struct kvm_shared_msr_values *values; 219 unsigned long flags; 220 221 /* 222 * Disabling irqs at this point since the following code could be 223 * interrupted and executed through kvm_arch_hardware_disable() 224 */ 225 local_irq_save(flags); 226 if (locals->registered) { 227 locals->registered = false; 228 user_return_notifier_unregister(urn); 229 } 230 local_irq_restore(flags); 231 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 232 values = &locals->values[slot]; 233 if (values->host != values->curr) { 234 wrmsrl(shared_msrs_global.msrs[slot], values->host); 235 values->curr = values->host; 236 } 237 } 238 } 239 240 static void shared_msr_update(unsigned slot, u32 msr) 241 { 242 u64 value; 243 unsigned int cpu = smp_processor_id(); 244 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 245 246 /* only read, and nobody should modify it at this time, 247 * so don't need lock */ 248 if (slot >= shared_msrs_global.nr) { 249 printk(KERN_ERR "kvm: invalid MSR slot!"); 250 return; 251 } 252 rdmsrl_safe(msr, &value); 253 smsr->values[slot].host = value; 254 smsr->values[slot].curr = value; 255 } 256 257 void kvm_define_shared_msr(unsigned slot, u32 msr) 258 { 259 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 260 shared_msrs_global.msrs[slot] = msr; 261 if (slot >= shared_msrs_global.nr) 262 shared_msrs_global.nr = slot + 1; 263 } 264 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 265 266 static void kvm_shared_msr_cpu_online(void) 267 { 268 unsigned i; 269 270 for (i = 0; i < shared_msrs_global.nr; ++i) 271 shared_msr_update(i, shared_msrs_global.msrs[i]); 272 } 273 274 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 275 { 276 unsigned int cpu = smp_processor_id(); 277 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 278 int err; 279 280 if (((value ^ smsr->values[slot].curr) & mask) == 0) 281 return 0; 282 smsr->values[slot].curr = value; 283 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 284 if (err) 285 return 1; 286 287 if (!smsr->registered) { 288 smsr->urn.on_user_return = kvm_on_user_return; 289 user_return_notifier_register(&smsr->urn); 290 smsr->registered = true; 291 } 292 return 0; 293 } 294 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 295 296 static void drop_user_return_notifiers(void) 297 { 298 unsigned int cpu = smp_processor_id(); 299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 300 301 if (smsr->registered) 302 kvm_on_user_return(&smsr->urn); 303 } 304 305 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 306 { 307 return vcpu->arch.apic_base; 308 } 309 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 310 311 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 312 { 313 u64 old_state = vcpu->arch.apic_base & 314 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 315 u64 new_state = msr_info->data & 316 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 317 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | 318 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 319 320 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE) 321 return 1; 322 if (!msr_info->host_initiated && 323 ((new_state == MSR_IA32_APICBASE_ENABLE && 324 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 325 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 326 old_state == 0))) 327 return 1; 328 329 kvm_lapic_set_base(vcpu, msr_info->data); 330 return 0; 331 } 332 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 333 334 asmlinkage __visible void kvm_spurious_fault(void) 335 { 336 /* Fault while not rebooting. We want the trace. */ 337 BUG(); 338 } 339 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 340 341 #define EXCPT_BENIGN 0 342 #define EXCPT_CONTRIBUTORY 1 343 #define EXCPT_PF 2 344 345 static int exception_class(int vector) 346 { 347 switch (vector) { 348 case PF_VECTOR: 349 return EXCPT_PF; 350 case DE_VECTOR: 351 case TS_VECTOR: 352 case NP_VECTOR: 353 case SS_VECTOR: 354 case GP_VECTOR: 355 return EXCPT_CONTRIBUTORY; 356 default: 357 break; 358 } 359 return EXCPT_BENIGN; 360 } 361 362 #define EXCPT_FAULT 0 363 #define EXCPT_TRAP 1 364 #define EXCPT_ABORT 2 365 #define EXCPT_INTERRUPT 3 366 367 static int exception_type(int vector) 368 { 369 unsigned int mask; 370 371 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 372 return EXCPT_INTERRUPT; 373 374 mask = 1 << vector; 375 376 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 377 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 378 return EXCPT_TRAP; 379 380 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 381 return EXCPT_ABORT; 382 383 /* Reserved exceptions will result in fault */ 384 return EXCPT_FAULT; 385 } 386 387 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 388 unsigned nr, bool has_error, u32 error_code, 389 bool reinject) 390 { 391 u32 prev_nr; 392 int class1, class2; 393 394 kvm_make_request(KVM_REQ_EVENT, vcpu); 395 396 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 397 queue: 398 if (has_error && !is_protmode(vcpu)) 399 has_error = false; 400 if (reinject) { 401 /* 402 * On vmentry, vcpu->arch.exception.pending is only 403 * true if an event injection was blocked by 404 * nested_run_pending. In that case, however, 405 * vcpu_enter_guest requests an immediate exit, 406 * and the guest shouldn't proceed far enough to 407 * need reinjection. 408 */ 409 WARN_ON_ONCE(vcpu->arch.exception.pending); 410 vcpu->arch.exception.injected = true; 411 } else { 412 vcpu->arch.exception.pending = true; 413 vcpu->arch.exception.injected = false; 414 } 415 vcpu->arch.exception.has_error_code = has_error; 416 vcpu->arch.exception.nr = nr; 417 vcpu->arch.exception.error_code = error_code; 418 return; 419 } 420 421 /* to check exception */ 422 prev_nr = vcpu->arch.exception.nr; 423 if (prev_nr == DF_VECTOR) { 424 /* triple fault -> shutdown */ 425 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 426 return; 427 } 428 class1 = exception_class(prev_nr); 429 class2 = exception_class(nr); 430 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 431 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 432 /* 433 * Generate double fault per SDM Table 5-5. Set 434 * exception.pending = true so that the double fault 435 * can trigger a nested vmexit. 436 */ 437 vcpu->arch.exception.pending = true; 438 vcpu->arch.exception.injected = false; 439 vcpu->arch.exception.has_error_code = true; 440 vcpu->arch.exception.nr = DF_VECTOR; 441 vcpu->arch.exception.error_code = 0; 442 } else 443 /* replace previous exception with a new one in a hope 444 that instruction re-execution will regenerate lost 445 exception */ 446 goto queue; 447 } 448 449 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 450 { 451 kvm_multiple_exception(vcpu, nr, false, 0, false); 452 } 453 EXPORT_SYMBOL_GPL(kvm_queue_exception); 454 455 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 456 { 457 kvm_multiple_exception(vcpu, nr, false, 0, true); 458 } 459 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 460 461 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 462 { 463 if (err) 464 kvm_inject_gp(vcpu, 0); 465 else 466 return kvm_skip_emulated_instruction(vcpu); 467 468 return 1; 469 } 470 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 471 472 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 473 { 474 ++vcpu->stat.pf_guest; 475 vcpu->arch.exception.nested_apf = 476 is_guest_mode(vcpu) && fault->async_page_fault; 477 if (vcpu->arch.exception.nested_apf) 478 vcpu->arch.apf.nested_apf_token = fault->address; 479 else 480 vcpu->arch.cr2 = fault->address; 481 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 482 } 483 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 484 485 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 486 { 487 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 488 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 489 else 490 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 491 492 return fault->nested_page_fault; 493 } 494 495 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 496 { 497 atomic_inc(&vcpu->arch.nmi_queued); 498 kvm_make_request(KVM_REQ_NMI, vcpu); 499 } 500 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 501 502 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 503 { 504 kvm_multiple_exception(vcpu, nr, true, error_code, false); 505 } 506 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 507 508 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 509 { 510 kvm_multiple_exception(vcpu, nr, true, error_code, true); 511 } 512 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 513 514 /* 515 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 516 * a #GP and return false. 517 */ 518 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 519 { 520 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 521 return true; 522 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 523 return false; 524 } 525 EXPORT_SYMBOL_GPL(kvm_require_cpl); 526 527 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 528 { 529 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 530 return true; 531 532 kvm_queue_exception(vcpu, UD_VECTOR); 533 return false; 534 } 535 EXPORT_SYMBOL_GPL(kvm_require_dr); 536 537 /* 538 * This function will be used to read from the physical memory of the currently 539 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 540 * can read from guest physical or from the guest's guest physical memory. 541 */ 542 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 543 gfn_t ngfn, void *data, int offset, int len, 544 u32 access) 545 { 546 struct x86_exception exception; 547 gfn_t real_gfn; 548 gpa_t ngpa; 549 550 ngpa = gfn_to_gpa(ngfn); 551 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 552 if (real_gfn == UNMAPPED_GVA) 553 return -EFAULT; 554 555 real_gfn = gpa_to_gfn(real_gfn); 556 557 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 558 } 559 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 560 561 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 562 void *data, int offset, int len, u32 access) 563 { 564 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 565 data, offset, len, access); 566 } 567 568 /* 569 * Load the pae pdptrs. Return true is they are all valid. 570 */ 571 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 572 { 573 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 574 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 575 int i; 576 int ret; 577 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 578 579 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 580 offset * sizeof(u64), sizeof(pdpte), 581 PFERR_USER_MASK|PFERR_WRITE_MASK); 582 if (ret < 0) { 583 ret = 0; 584 goto out; 585 } 586 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 587 if ((pdpte[i] & PT_PRESENT_MASK) && 588 (pdpte[i] & 589 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) { 590 ret = 0; 591 goto out; 592 } 593 } 594 ret = 1; 595 596 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 597 __set_bit(VCPU_EXREG_PDPTR, 598 (unsigned long *)&vcpu->arch.regs_avail); 599 __set_bit(VCPU_EXREG_PDPTR, 600 (unsigned long *)&vcpu->arch.regs_dirty); 601 out: 602 603 return ret; 604 } 605 EXPORT_SYMBOL_GPL(load_pdptrs); 606 607 bool pdptrs_changed(struct kvm_vcpu *vcpu) 608 { 609 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 610 bool changed = true; 611 int offset; 612 gfn_t gfn; 613 int r; 614 615 if (is_long_mode(vcpu) || !is_pae(vcpu)) 616 return false; 617 618 if (!test_bit(VCPU_EXREG_PDPTR, 619 (unsigned long *)&vcpu->arch.regs_avail)) 620 return true; 621 622 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; 623 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); 624 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 625 PFERR_USER_MASK | PFERR_WRITE_MASK); 626 if (r < 0) 627 goto out; 628 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 629 out: 630 631 return changed; 632 } 633 EXPORT_SYMBOL_GPL(pdptrs_changed); 634 635 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 636 { 637 unsigned long old_cr0 = kvm_read_cr0(vcpu); 638 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 639 640 cr0 |= X86_CR0_ET; 641 642 #ifdef CONFIG_X86_64 643 if (cr0 & 0xffffffff00000000UL) 644 return 1; 645 #endif 646 647 cr0 &= ~CR0_RESERVED_BITS; 648 649 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 650 return 1; 651 652 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 653 return 1; 654 655 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 656 #ifdef CONFIG_X86_64 657 if ((vcpu->arch.efer & EFER_LME)) { 658 int cs_db, cs_l; 659 660 if (!is_pae(vcpu)) 661 return 1; 662 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 663 if (cs_l) 664 return 1; 665 } else 666 #endif 667 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 668 kvm_read_cr3(vcpu))) 669 return 1; 670 } 671 672 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 673 return 1; 674 675 kvm_x86_ops->set_cr0(vcpu, cr0); 676 677 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 678 kvm_clear_async_pf_completion_queue(vcpu); 679 kvm_async_pf_hash_reset(vcpu); 680 } 681 682 if ((cr0 ^ old_cr0) & update_bits) 683 kvm_mmu_reset_context(vcpu); 684 685 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 686 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 687 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 688 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 689 690 return 0; 691 } 692 EXPORT_SYMBOL_GPL(kvm_set_cr0); 693 694 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 695 { 696 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 697 } 698 EXPORT_SYMBOL_GPL(kvm_lmsw); 699 700 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 701 { 702 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 703 !vcpu->guest_xcr0_loaded) { 704 /* kvm_set_xcr() also depends on this */ 705 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 706 vcpu->guest_xcr0_loaded = 1; 707 } 708 } 709 710 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 711 { 712 if (vcpu->guest_xcr0_loaded) { 713 if (vcpu->arch.xcr0 != host_xcr0) 714 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 715 vcpu->guest_xcr0_loaded = 0; 716 } 717 } 718 719 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 720 { 721 u64 xcr0 = xcr; 722 u64 old_xcr0 = vcpu->arch.xcr0; 723 u64 valid_bits; 724 725 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 726 if (index != XCR_XFEATURE_ENABLED_MASK) 727 return 1; 728 if (!(xcr0 & XFEATURE_MASK_FP)) 729 return 1; 730 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 731 return 1; 732 733 /* 734 * Do not allow the guest to set bits that we do not support 735 * saving. However, xcr0 bit 0 is always set, even if the 736 * emulated CPU does not support XSAVE (see fx_init). 737 */ 738 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 739 if (xcr0 & ~valid_bits) 740 return 1; 741 742 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 743 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 744 return 1; 745 746 if (xcr0 & XFEATURE_MASK_AVX512) { 747 if (!(xcr0 & XFEATURE_MASK_YMM)) 748 return 1; 749 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 750 return 1; 751 } 752 vcpu->arch.xcr0 = xcr0; 753 754 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 755 kvm_update_cpuid(vcpu); 756 return 0; 757 } 758 759 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 760 { 761 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 762 __kvm_set_xcr(vcpu, index, xcr)) { 763 kvm_inject_gp(vcpu, 0); 764 return 1; 765 } 766 return 0; 767 } 768 EXPORT_SYMBOL_GPL(kvm_set_xcr); 769 770 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 771 { 772 unsigned long old_cr4 = kvm_read_cr4(vcpu); 773 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 774 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 775 776 if (cr4 & CR4_RESERVED_BITS) 777 return 1; 778 779 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE)) 780 return 1; 781 782 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP)) 783 return 1; 784 785 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP)) 786 return 1; 787 788 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE)) 789 return 1; 790 791 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE)) 792 return 1; 793 794 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57)) 795 return 1; 796 797 if (is_long_mode(vcpu)) { 798 if (!(cr4 & X86_CR4_PAE)) 799 return 1; 800 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 801 && ((cr4 ^ old_cr4) & pdptr_bits) 802 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 803 kvm_read_cr3(vcpu))) 804 return 1; 805 806 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 807 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 808 return 1; 809 810 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 811 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 812 return 1; 813 } 814 815 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 816 return 1; 817 818 if (((cr4 ^ old_cr4) & pdptr_bits) || 819 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 820 kvm_mmu_reset_context(vcpu); 821 822 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 823 kvm_update_cpuid(vcpu); 824 825 return 0; 826 } 827 EXPORT_SYMBOL_GPL(kvm_set_cr4); 828 829 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 830 { 831 #ifdef CONFIG_X86_64 832 cr3 &= ~CR3_PCID_INVD; 833 #endif 834 835 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 836 kvm_mmu_sync_roots(vcpu); 837 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 838 return 0; 839 } 840 841 if (is_long_mode(vcpu) && 842 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62))) 843 return 1; 844 else if (is_pae(vcpu) && is_paging(vcpu) && 845 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 846 return 1; 847 848 vcpu->arch.cr3 = cr3; 849 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 850 kvm_mmu_new_cr3(vcpu); 851 return 0; 852 } 853 EXPORT_SYMBOL_GPL(kvm_set_cr3); 854 855 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 856 { 857 if (cr8 & CR8_RESERVED_BITS) 858 return 1; 859 if (lapic_in_kernel(vcpu)) 860 kvm_lapic_set_tpr(vcpu, cr8); 861 else 862 vcpu->arch.cr8 = cr8; 863 return 0; 864 } 865 EXPORT_SYMBOL_GPL(kvm_set_cr8); 866 867 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 868 { 869 if (lapic_in_kernel(vcpu)) 870 return kvm_lapic_get_cr8(vcpu); 871 else 872 return vcpu->arch.cr8; 873 } 874 EXPORT_SYMBOL_GPL(kvm_get_cr8); 875 876 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 877 { 878 int i; 879 880 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 881 for (i = 0; i < KVM_NR_DB_REGS; i++) 882 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 883 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 884 } 885 } 886 887 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 888 { 889 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 890 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 891 } 892 893 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 894 { 895 unsigned long dr7; 896 897 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 898 dr7 = vcpu->arch.guest_debug_dr7; 899 else 900 dr7 = vcpu->arch.dr7; 901 kvm_x86_ops->set_dr7(vcpu, dr7); 902 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 903 if (dr7 & DR7_BP_EN_MASK) 904 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 905 } 906 907 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 908 { 909 u64 fixed = DR6_FIXED_1; 910 911 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 912 fixed |= DR6_RTM; 913 return fixed; 914 } 915 916 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 917 { 918 switch (dr) { 919 case 0 ... 3: 920 vcpu->arch.db[dr] = val; 921 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 922 vcpu->arch.eff_db[dr] = val; 923 break; 924 case 4: 925 /* fall through */ 926 case 6: 927 if (val & 0xffffffff00000000ULL) 928 return -1; /* #GP */ 929 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 930 kvm_update_dr6(vcpu); 931 break; 932 case 5: 933 /* fall through */ 934 default: /* 7 */ 935 if (val & 0xffffffff00000000ULL) 936 return -1; /* #GP */ 937 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 938 kvm_update_dr7(vcpu); 939 break; 940 } 941 942 return 0; 943 } 944 945 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 946 { 947 if (__kvm_set_dr(vcpu, dr, val)) { 948 kvm_inject_gp(vcpu, 0); 949 return 1; 950 } 951 return 0; 952 } 953 EXPORT_SYMBOL_GPL(kvm_set_dr); 954 955 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 956 { 957 switch (dr) { 958 case 0 ... 3: 959 *val = vcpu->arch.db[dr]; 960 break; 961 case 4: 962 /* fall through */ 963 case 6: 964 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 965 *val = vcpu->arch.dr6; 966 else 967 *val = kvm_x86_ops->get_dr6(vcpu); 968 break; 969 case 5: 970 /* fall through */ 971 default: /* 7 */ 972 *val = vcpu->arch.dr7; 973 break; 974 } 975 return 0; 976 } 977 EXPORT_SYMBOL_GPL(kvm_get_dr); 978 979 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 980 { 981 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 982 u64 data; 983 int err; 984 985 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 986 if (err) 987 return err; 988 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 989 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 990 return err; 991 } 992 EXPORT_SYMBOL_GPL(kvm_rdpmc); 993 994 /* 995 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 996 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 997 * 998 * This list is modified at module load time to reflect the 999 * capabilities of the host cpu. This capabilities test skips MSRs that are 1000 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs 1001 * may depend on host virtualization features rather than host cpu features. 1002 */ 1003 1004 static u32 msrs_to_save[] = { 1005 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1006 MSR_STAR, 1007 #ifdef CONFIG_X86_64 1008 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1009 #endif 1010 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1011 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1012 }; 1013 1014 static unsigned num_msrs_to_save; 1015 1016 static u32 emulated_msrs[] = { 1017 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1018 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1019 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1020 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1021 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1022 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1023 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1024 HV_X64_MSR_RESET, 1025 HV_X64_MSR_VP_INDEX, 1026 HV_X64_MSR_VP_RUNTIME, 1027 HV_X64_MSR_SCONTROL, 1028 HV_X64_MSR_STIMER0_CONFIG, 1029 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1030 MSR_KVM_PV_EOI_EN, 1031 1032 MSR_IA32_TSC_ADJUST, 1033 MSR_IA32_TSCDEADLINE, 1034 MSR_IA32_MISC_ENABLE, 1035 MSR_IA32_MCG_STATUS, 1036 MSR_IA32_MCG_CTL, 1037 MSR_IA32_MCG_EXT_CTL, 1038 MSR_IA32_SMBASE, 1039 MSR_PLATFORM_INFO, 1040 MSR_MISC_FEATURES_ENABLES, 1041 }; 1042 1043 static unsigned num_emulated_msrs; 1044 1045 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1046 { 1047 if (efer & efer_reserved_bits) 1048 return false; 1049 1050 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1051 return false; 1052 1053 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1054 return false; 1055 1056 return true; 1057 } 1058 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1059 1060 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 1061 { 1062 u64 old_efer = vcpu->arch.efer; 1063 1064 if (!kvm_valid_efer(vcpu, efer)) 1065 return 1; 1066 1067 if (is_paging(vcpu) 1068 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1069 return 1; 1070 1071 efer &= ~EFER_LMA; 1072 efer |= vcpu->arch.efer & EFER_LMA; 1073 1074 kvm_x86_ops->set_efer(vcpu, efer); 1075 1076 /* Update reserved bits */ 1077 if ((efer ^ old_efer) & EFER_NX) 1078 kvm_mmu_reset_context(vcpu); 1079 1080 return 0; 1081 } 1082 1083 void kvm_enable_efer_bits(u64 mask) 1084 { 1085 efer_reserved_bits &= ~mask; 1086 } 1087 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1088 1089 /* 1090 * Writes msr value into into the appropriate "register". 1091 * Returns 0 on success, non-0 otherwise. 1092 * Assumes vcpu_load() was already called. 1093 */ 1094 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1095 { 1096 switch (msr->index) { 1097 case MSR_FS_BASE: 1098 case MSR_GS_BASE: 1099 case MSR_KERNEL_GS_BASE: 1100 case MSR_CSTAR: 1101 case MSR_LSTAR: 1102 if (is_noncanonical_address(msr->data, vcpu)) 1103 return 1; 1104 break; 1105 case MSR_IA32_SYSENTER_EIP: 1106 case MSR_IA32_SYSENTER_ESP: 1107 /* 1108 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1109 * non-canonical address is written on Intel but not on 1110 * AMD (which ignores the top 32-bits, because it does 1111 * not implement 64-bit SYSENTER). 1112 * 1113 * 64-bit code should hence be able to write a non-canonical 1114 * value on AMD. Making the address canonical ensures that 1115 * vmentry does not fail on Intel after writing a non-canonical 1116 * value, and that something deterministic happens if the guest 1117 * invokes 64-bit SYSENTER. 1118 */ 1119 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu)); 1120 } 1121 return kvm_x86_ops->set_msr(vcpu, msr); 1122 } 1123 EXPORT_SYMBOL_GPL(kvm_set_msr); 1124 1125 /* 1126 * Adapt set_msr() to msr_io()'s calling convention 1127 */ 1128 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1129 { 1130 struct msr_data msr; 1131 int r; 1132 1133 msr.index = index; 1134 msr.host_initiated = true; 1135 r = kvm_get_msr(vcpu, &msr); 1136 if (r) 1137 return r; 1138 1139 *data = msr.data; 1140 return 0; 1141 } 1142 1143 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1144 { 1145 struct msr_data msr; 1146 1147 msr.data = *data; 1148 msr.index = index; 1149 msr.host_initiated = true; 1150 return kvm_set_msr(vcpu, &msr); 1151 } 1152 1153 #ifdef CONFIG_X86_64 1154 struct pvclock_gtod_data { 1155 seqcount_t seq; 1156 1157 struct { /* extract of a clocksource struct */ 1158 int vclock_mode; 1159 u64 cycle_last; 1160 u64 mask; 1161 u32 mult; 1162 u32 shift; 1163 } clock; 1164 1165 u64 boot_ns; 1166 u64 nsec_base; 1167 u64 wall_time_sec; 1168 }; 1169 1170 static struct pvclock_gtod_data pvclock_gtod_data; 1171 1172 static void update_pvclock_gtod(struct timekeeper *tk) 1173 { 1174 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1175 u64 boot_ns; 1176 1177 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1178 1179 write_seqcount_begin(&vdata->seq); 1180 1181 /* copy pvclock gtod data */ 1182 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1183 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1184 vdata->clock.mask = tk->tkr_mono.mask; 1185 vdata->clock.mult = tk->tkr_mono.mult; 1186 vdata->clock.shift = tk->tkr_mono.shift; 1187 1188 vdata->boot_ns = boot_ns; 1189 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1190 1191 vdata->wall_time_sec = tk->xtime_sec; 1192 1193 write_seqcount_end(&vdata->seq); 1194 } 1195 #endif 1196 1197 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1198 { 1199 /* 1200 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1201 * vcpu_enter_guest. This function is only called from 1202 * the physical CPU that is running vcpu. 1203 */ 1204 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1205 } 1206 1207 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1208 { 1209 int version; 1210 int r; 1211 struct pvclock_wall_clock wc; 1212 struct timespec64 boot; 1213 1214 if (!wall_clock) 1215 return; 1216 1217 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1218 if (r) 1219 return; 1220 1221 if (version & 1) 1222 ++version; /* first time write, random junk */ 1223 1224 ++version; 1225 1226 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1227 return; 1228 1229 /* 1230 * The guest calculates current wall clock time by adding 1231 * system time (updated by kvm_guest_time_update below) to the 1232 * wall clock specified here. guest system time equals host 1233 * system time for us, thus we must fill in host boot time here. 1234 */ 1235 getboottime64(&boot); 1236 1237 if (kvm->arch.kvmclock_offset) { 1238 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset); 1239 boot = timespec64_sub(boot, ts); 1240 } 1241 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */ 1242 wc.nsec = boot.tv_nsec; 1243 wc.version = version; 1244 1245 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1246 1247 version++; 1248 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1249 } 1250 1251 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1252 { 1253 do_shl32_div32(dividend, divisor); 1254 return dividend; 1255 } 1256 1257 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 1258 s8 *pshift, u32 *pmultiplier) 1259 { 1260 uint64_t scaled64; 1261 int32_t shift = 0; 1262 uint64_t tps64; 1263 uint32_t tps32; 1264 1265 tps64 = base_hz; 1266 scaled64 = scaled_hz; 1267 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1268 tps64 >>= 1; 1269 shift--; 1270 } 1271 1272 tps32 = (uint32_t)tps64; 1273 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1274 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1275 scaled64 >>= 1; 1276 else 1277 tps32 <<= 1; 1278 shift++; 1279 } 1280 1281 *pshift = shift; 1282 *pmultiplier = div_frac(scaled64, tps32); 1283 1284 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n", 1285 __func__, base_hz, scaled_hz, shift, *pmultiplier); 1286 } 1287 1288 #ifdef CONFIG_X86_64 1289 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1290 #endif 1291 1292 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1293 static unsigned long max_tsc_khz; 1294 1295 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1296 { 1297 u64 v = (u64)khz * (1000000 + ppm); 1298 do_div(v, 1000000); 1299 return v; 1300 } 1301 1302 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 1303 { 1304 u64 ratio; 1305 1306 /* Guest TSC same frequency as host TSC? */ 1307 if (!scale) { 1308 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1309 return 0; 1310 } 1311 1312 /* TSC scaling supported? */ 1313 if (!kvm_has_tsc_control) { 1314 if (user_tsc_khz > tsc_khz) { 1315 vcpu->arch.tsc_catchup = 1; 1316 vcpu->arch.tsc_always_catchup = 1; 1317 return 0; 1318 } else { 1319 WARN(1, "user requested TSC rate below hardware speed\n"); 1320 return -1; 1321 } 1322 } 1323 1324 /* TSC scaling required - calculate ratio */ 1325 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 1326 user_tsc_khz, tsc_khz); 1327 1328 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 1329 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 1330 user_tsc_khz); 1331 return -1; 1332 } 1333 1334 vcpu->arch.tsc_scaling_ratio = ratio; 1335 return 0; 1336 } 1337 1338 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 1339 { 1340 u32 thresh_lo, thresh_hi; 1341 int use_scaling = 0; 1342 1343 /* tsc_khz can be zero if TSC calibration fails */ 1344 if (user_tsc_khz == 0) { 1345 /* set tsc_scaling_ratio to a safe value */ 1346 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1347 return -1; 1348 } 1349 1350 /* Compute a scale to convert nanoseconds in TSC cycles */ 1351 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 1352 &vcpu->arch.virtual_tsc_shift, 1353 &vcpu->arch.virtual_tsc_mult); 1354 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 1355 1356 /* 1357 * Compute the variation in TSC rate which is acceptable 1358 * within the range of tolerance and decide if the 1359 * rate being applied is within that bounds of the hardware 1360 * rate. If so, no scaling or compensation need be done. 1361 */ 1362 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1363 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1364 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 1365 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 1366 use_scaling = 1; 1367 } 1368 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 1369 } 1370 1371 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1372 { 1373 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1374 vcpu->arch.virtual_tsc_mult, 1375 vcpu->arch.virtual_tsc_shift); 1376 tsc += vcpu->arch.this_tsc_write; 1377 return tsc; 1378 } 1379 1380 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1381 { 1382 #ifdef CONFIG_X86_64 1383 bool vcpus_matched; 1384 struct kvm_arch *ka = &vcpu->kvm->arch; 1385 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1386 1387 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1388 atomic_read(&vcpu->kvm->online_vcpus)); 1389 1390 /* 1391 * Once the masterclock is enabled, always perform request in 1392 * order to update it. 1393 * 1394 * In order to enable masterclock, the host clocksource must be TSC 1395 * and the vcpus need to have matched TSCs. When that happens, 1396 * perform request to enable masterclock. 1397 */ 1398 if (ka->use_master_clock || 1399 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) 1400 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1401 1402 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1403 atomic_read(&vcpu->kvm->online_vcpus), 1404 ka->use_master_clock, gtod->clock.vclock_mode); 1405 #endif 1406 } 1407 1408 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1409 { 1410 u64 curr_offset = vcpu->arch.tsc_offset; 1411 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1412 } 1413 1414 /* 1415 * Multiply tsc by a fixed point number represented by ratio. 1416 * 1417 * The most significant 64-N bits (mult) of ratio represent the 1418 * integral part of the fixed point number; the remaining N bits 1419 * (frac) represent the fractional part, ie. ratio represents a fixed 1420 * point number (mult + frac * 2^(-N)). 1421 * 1422 * N equals to kvm_tsc_scaling_ratio_frac_bits. 1423 */ 1424 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 1425 { 1426 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 1427 } 1428 1429 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 1430 { 1431 u64 _tsc = tsc; 1432 u64 ratio = vcpu->arch.tsc_scaling_ratio; 1433 1434 if (ratio != kvm_default_tsc_scaling_ratio) 1435 _tsc = __scale_tsc(ratio, tsc); 1436 1437 return _tsc; 1438 } 1439 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 1440 1441 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 1442 { 1443 u64 tsc; 1444 1445 tsc = kvm_scale_tsc(vcpu, rdtsc()); 1446 1447 return target_tsc - tsc; 1448 } 1449 1450 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 1451 { 1452 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc); 1453 } 1454 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 1455 1456 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1457 { 1458 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1459 vcpu->arch.tsc_offset = offset; 1460 } 1461 1462 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1463 { 1464 struct kvm *kvm = vcpu->kvm; 1465 u64 offset, ns, elapsed; 1466 unsigned long flags; 1467 bool matched; 1468 bool already_matched; 1469 u64 data = msr->data; 1470 bool synchronizing = false; 1471 1472 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1473 offset = kvm_compute_tsc_offset(vcpu, data); 1474 ns = ktime_get_boot_ns(); 1475 elapsed = ns - kvm->arch.last_tsc_nsec; 1476 1477 if (vcpu->arch.virtual_tsc_khz) { 1478 if (data == 0 && msr->host_initiated) { 1479 /* 1480 * detection of vcpu initialization -- need to sync 1481 * with other vCPUs. This particularly helps to keep 1482 * kvm_clock stable after CPU hotplug 1483 */ 1484 synchronizing = true; 1485 } else { 1486 u64 tsc_exp = kvm->arch.last_tsc_write + 1487 nsec_to_cycles(vcpu, elapsed); 1488 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 1489 /* 1490 * Special case: TSC write with a small delta (1 second) 1491 * of virtual cycle time against real time is 1492 * interpreted as an attempt to synchronize the CPU. 1493 */ 1494 synchronizing = data < tsc_exp + tsc_hz && 1495 data + tsc_hz > tsc_exp; 1496 } 1497 } 1498 1499 /* 1500 * For a reliable TSC, we can match TSC offsets, and for an unstable 1501 * TSC, we add elapsed time in this computation. We could let the 1502 * compensation code attempt to catch up if we fall behind, but 1503 * it's better to try to match offsets from the beginning. 1504 */ 1505 if (synchronizing && 1506 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1507 if (!check_tsc_unstable()) { 1508 offset = kvm->arch.cur_tsc_offset; 1509 pr_debug("kvm: matched tsc offset for %llu\n", data); 1510 } else { 1511 u64 delta = nsec_to_cycles(vcpu, elapsed); 1512 data += delta; 1513 offset = kvm_compute_tsc_offset(vcpu, data); 1514 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1515 } 1516 matched = true; 1517 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1518 } else { 1519 /* 1520 * We split periods of matched TSC writes into generations. 1521 * For each generation, we track the original measured 1522 * nanosecond time, offset, and write, so if TSCs are in 1523 * sync, we can match exact offset, and if not, we can match 1524 * exact software computation in compute_guest_tsc() 1525 * 1526 * These values are tracked in kvm->arch.cur_xxx variables. 1527 */ 1528 kvm->arch.cur_tsc_generation++; 1529 kvm->arch.cur_tsc_nsec = ns; 1530 kvm->arch.cur_tsc_write = data; 1531 kvm->arch.cur_tsc_offset = offset; 1532 matched = false; 1533 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1534 kvm->arch.cur_tsc_generation, data); 1535 } 1536 1537 /* 1538 * We also track th most recent recorded KHZ, write and time to 1539 * allow the matching interval to be extended at each write. 1540 */ 1541 kvm->arch.last_tsc_nsec = ns; 1542 kvm->arch.last_tsc_write = data; 1543 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1544 1545 vcpu->arch.last_guest_tsc = data; 1546 1547 /* Keep track of which generation this VCPU has synchronized to */ 1548 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1549 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1550 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1551 1552 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) 1553 update_ia32_tsc_adjust_msr(vcpu, offset); 1554 1555 kvm_vcpu_write_tsc_offset(vcpu, offset); 1556 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1557 1558 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1559 if (!matched) { 1560 kvm->arch.nr_vcpus_matched_tsc = 0; 1561 } else if (!already_matched) { 1562 kvm->arch.nr_vcpus_matched_tsc++; 1563 } 1564 1565 kvm_track_tsc_matching(vcpu); 1566 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1567 } 1568 1569 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1570 1571 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 1572 s64 adjustment) 1573 { 1574 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment); 1575 } 1576 1577 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 1578 { 1579 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 1580 WARN_ON(adjustment < 0); 1581 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 1582 adjust_tsc_offset_guest(vcpu, adjustment); 1583 } 1584 1585 #ifdef CONFIG_X86_64 1586 1587 static u64 read_tsc(void) 1588 { 1589 u64 ret = (u64)rdtsc_ordered(); 1590 u64 last = pvclock_gtod_data.clock.cycle_last; 1591 1592 if (likely(ret >= last)) 1593 return ret; 1594 1595 /* 1596 * GCC likes to generate cmov here, but this branch is extremely 1597 * predictable (it's just a function of time and the likely is 1598 * very likely) and there's a data dependence, so force GCC 1599 * to generate a branch instead. I don't barrier() because 1600 * we don't actually need a barrier, and if this function 1601 * ever gets inlined it will generate worse code. 1602 */ 1603 asm volatile (""); 1604 return last; 1605 } 1606 1607 static inline u64 vgettsc(u64 *cycle_now) 1608 { 1609 long v; 1610 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1611 1612 *cycle_now = read_tsc(); 1613 1614 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; 1615 return v * gtod->clock.mult; 1616 } 1617 1618 static int do_monotonic_boot(s64 *t, u64 *cycle_now) 1619 { 1620 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1621 unsigned long seq; 1622 int mode; 1623 u64 ns; 1624 1625 do { 1626 seq = read_seqcount_begin(>od->seq); 1627 mode = gtod->clock.vclock_mode; 1628 ns = gtod->nsec_base; 1629 ns += vgettsc(cycle_now); 1630 ns >>= gtod->clock.shift; 1631 ns += gtod->boot_ns; 1632 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1633 *t = ns; 1634 1635 return mode; 1636 } 1637 1638 static int do_realtime(struct timespec *ts, u64 *cycle_now) 1639 { 1640 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1641 unsigned long seq; 1642 int mode; 1643 u64 ns; 1644 1645 do { 1646 seq = read_seqcount_begin(>od->seq); 1647 mode = gtod->clock.vclock_mode; 1648 ts->tv_sec = gtod->wall_time_sec; 1649 ns = gtod->nsec_base; 1650 ns += vgettsc(cycle_now); 1651 ns >>= gtod->clock.shift; 1652 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1653 1654 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 1655 ts->tv_nsec = ns; 1656 1657 return mode; 1658 } 1659 1660 /* returns true if host is using tsc clocksource */ 1661 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now) 1662 { 1663 /* checked again under seqlock below */ 1664 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) 1665 return false; 1666 1667 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; 1668 } 1669 1670 /* returns true if host is using tsc clocksource */ 1671 static bool kvm_get_walltime_and_clockread(struct timespec *ts, 1672 u64 *cycle_now) 1673 { 1674 /* checked again under seqlock below */ 1675 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) 1676 return false; 1677 1678 return do_realtime(ts, cycle_now) == VCLOCK_TSC; 1679 } 1680 #endif 1681 1682 /* 1683 * 1684 * Assuming a stable TSC across physical CPUS, and a stable TSC 1685 * across virtual CPUs, the following condition is possible. 1686 * Each numbered line represents an event visible to both 1687 * CPUs at the next numbered event. 1688 * 1689 * "timespecX" represents host monotonic time. "tscX" represents 1690 * RDTSC value. 1691 * 1692 * VCPU0 on CPU0 | VCPU1 on CPU1 1693 * 1694 * 1. read timespec0,tsc0 1695 * 2. | timespec1 = timespec0 + N 1696 * | tsc1 = tsc0 + M 1697 * 3. transition to guest | transition to guest 1698 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1699 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1700 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1701 * 1702 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1703 * 1704 * - ret0 < ret1 1705 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1706 * ... 1707 * - 0 < N - M => M < N 1708 * 1709 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1710 * always the case (the difference between two distinct xtime instances 1711 * might be smaller then the difference between corresponding TSC reads, 1712 * when updating guest vcpus pvclock areas). 1713 * 1714 * To avoid that problem, do not allow visibility of distinct 1715 * system_timestamp/tsc_timestamp values simultaneously: use a master 1716 * copy of host monotonic time values. Update that master copy 1717 * in lockstep. 1718 * 1719 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1720 * 1721 */ 1722 1723 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1724 { 1725 #ifdef CONFIG_X86_64 1726 struct kvm_arch *ka = &kvm->arch; 1727 int vclock_mode; 1728 bool host_tsc_clocksource, vcpus_matched; 1729 1730 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1731 atomic_read(&kvm->online_vcpus)); 1732 1733 /* 1734 * If the host uses TSC clock, then passthrough TSC as stable 1735 * to the guest. 1736 */ 1737 host_tsc_clocksource = kvm_get_time_and_clockread( 1738 &ka->master_kernel_ns, 1739 &ka->master_cycle_now); 1740 1741 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 1742 && !ka->backwards_tsc_observed 1743 && !ka->boot_vcpu_runs_old_kvmclock; 1744 1745 if (ka->use_master_clock) 1746 atomic_set(&kvm_guest_has_master_clock, 1); 1747 1748 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1749 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1750 vcpus_matched); 1751 #endif 1752 } 1753 1754 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 1755 { 1756 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 1757 } 1758 1759 static void kvm_gen_update_masterclock(struct kvm *kvm) 1760 { 1761 #ifdef CONFIG_X86_64 1762 int i; 1763 struct kvm_vcpu *vcpu; 1764 struct kvm_arch *ka = &kvm->arch; 1765 1766 spin_lock(&ka->pvclock_gtod_sync_lock); 1767 kvm_make_mclock_inprogress_request(kvm); 1768 /* no guest entries from this point */ 1769 pvclock_update_vm_gtod_copy(kvm); 1770 1771 kvm_for_each_vcpu(i, vcpu, kvm) 1772 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1773 1774 /* guest entries allowed */ 1775 kvm_for_each_vcpu(i, vcpu, kvm) 1776 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 1777 1778 spin_unlock(&ka->pvclock_gtod_sync_lock); 1779 #endif 1780 } 1781 1782 u64 get_kvmclock_ns(struct kvm *kvm) 1783 { 1784 struct kvm_arch *ka = &kvm->arch; 1785 struct pvclock_vcpu_time_info hv_clock; 1786 u64 ret; 1787 1788 spin_lock(&ka->pvclock_gtod_sync_lock); 1789 if (!ka->use_master_clock) { 1790 spin_unlock(&ka->pvclock_gtod_sync_lock); 1791 return ktime_get_boot_ns() + ka->kvmclock_offset; 1792 } 1793 1794 hv_clock.tsc_timestamp = ka->master_cycle_now; 1795 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 1796 spin_unlock(&ka->pvclock_gtod_sync_lock); 1797 1798 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 1799 get_cpu(); 1800 1801 if (__this_cpu_read(cpu_tsc_khz)) { 1802 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 1803 &hv_clock.tsc_shift, 1804 &hv_clock.tsc_to_system_mul); 1805 ret = __pvclock_read_cycles(&hv_clock, rdtsc()); 1806 } else 1807 ret = ktime_get_boot_ns() + ka->kvmclock_offset; 1808 1809 put_cpu(); 1810 1811 return ret; 1812 } 1813 1814 static void kvm_setup_pvclock_page(struct kvm_vcpu *v) 1815 { 1816 struct kvm_vcpu_arch *vcpu = &v->arch; 1817 struct pvclock_vcpu_time_info guest_hv_clock; 1818 1819 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1820 &guest_hv_clock, sizeof(guest_hv_clock)))) 1821 return; 1822 1823 /* This VCPU is paused, but it's legal for a guest to read another 1824 * VCPU's kvmclock, so we really have to follow the specification where 1825 * it says that version is odd if data is being modified, and even after 1826 * it is consistent. 1827 * 1828 * Version field updates must be kept separate. This is because 1829 * kvm_write_guest_cached might use a "rep movs" instruction, and 1830 * writes within a string instruction are weakly ordered. So there 1831 * are three writes overall. 1832 * 1833 * As a small optimization, only write the version field in the first 1834 * and third write. The vcpu->pv_time cache is still valid, because the 1835 * version field is the first in the struct. 1836 */ 1837 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 1838 1839 if (guest_hv_clock.version & 1) 1840 ++guest_hv_clock.version; /* first time write, random junk */ 1841 1842 vcpu->hv_clock.version = guest_hv_clock.version + 1; 1843 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1844 &vcpu->hv_clock, 1845 sizeof(vcpu->hv_clock.version)); 1846 1847 smp_wmb(); 1848 1849 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1850 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1851 1852 if (vcpu->pvclock_set_guest_stopped_request) { 1853 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 1854 vcpu->pvclock_set_guest_stopped_request = false; 1855 } 1856 1857 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 1858 1859 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1860 &vcpu->hv_clock, 1861 sizeof(vcpu->hv_clock)); 1862 1863 smp_wmb(); 1864 1865 vcpu->hv_clock.version++; 1866 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1867 &vcpu->hv_clock, 1868 sizeof(vcpu->hv_clock.version)); 1869 } 1870 1871 static int kvm_guest_time_update(struct kvm_vcpu *v) 1872 { 1873 unsigned long flags, tgt_tsc_khz; 1874 struct kvm_vcpu_arch *vcpu = &v->arch; 1875 struct kvm_arch *ka = &v->kvm->arch; 1876 s64 kernel_ns; 1877 u64 tsc_timestamp, host_tsc; 1878 u8 pvclock_flags; 1879 bool use_master_clock; 1880 1881 kernel_ns = 0; 1882 host_tsc = 0; 1883 1884 /* 1885 * If the host uses TSC clock, then passthrough TSC as stable 1886 * to the guest. 1887 */ 1888 spin_lock(&ka->pvclock_gtod_sync_lock); 1889 use_master_clock = ka->use_master_clock; 1890 if (use_master_clock) { 1891 host_tsc = ka->master_cycle_now; 1892 kernel_ns = ka->master_kernel_ns; 1893 } 1894 spin_unlock(&ka->pvclock_gtod_sync_lock); 1895 1896 /* Keep irq disabled to prevent changes to the clock */ 1897 local_irq_save(flags); 1898 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 1899 if (unlikely(tgt_tsc_khz == 0)) { 1900 local_irq_restore(flags); 1901 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1902 return 1; 1903 } 1904 if (!use_master_clock) { 1905 host_tsc = rdtsc(); 1906 kernel_ns = ktime_get_boot_ns(); 1907 } 1908 1909 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 1910 1911 /* 1912 * We may have to catch up the TSC to match elapsed wall clock 1913 * time for two reasons, even if kvmclock is used. 1914 * 1) CPU could have been running below the maximum TSC rate 1915 * 2) Broken TSC compensation resets the base at each VCPU 1916 * entry to avoid unknown leaps of TSC even when running 1917 * again on the same CPU. This may cause apparent elapsed 1918 * time to disappear, and the guest to stand still or run 1919 * very slowly. 1920 */ 1921 if (vcpu->tsc_catchup) { 1922 u64 tsc = compute_guest_tsc(v, kernel_ns); 1923 if (tsc > tsc_timestamp) { 1924 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 1925 tsc_timestamp = tsc; 1926 } 1927 } 1928 1929 local_irq_restore(flags); 1930 1931 /* With all the info we got, fill in the values */ 1932 1933 if (kvm_has_tsc_control) 1934 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 1935 1936 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 1937 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 1938 &vcpu->hv_clock.tsc_shift, 1939 &vcpu->hv_clock.tsc_to_system_mul); 1940 vcpu->hw_tsc_khz = tgt_tsc_khz; 1941 } 1942 1943 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 1944 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 1945 vcpu->last_guest_tsc = tsc_timestamp; 1946 1947 /* If the host uses TSC clocksource, then it is stable */ 1948 pvclock_flags = 0; 1949 if (use_master_clock) 1950 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 1951 1952 vcpu->hv_clock.flags = pvclock_flags; 1953 1954 if (vcpu->pv_time_enabled) 1955 kvm_setup_pvclock_page(v); 1956 if (v == kvm_get_vcpu(v->kvm, 0)) 1957 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 1958 return 0; 1959 } 1960 1961 /* 1962 * kvmclock updates which are isolated to a given vcpu, such as 1963 * vcpu->cpu migration, should not allow system_timestamp from 1964 * the rest of the vcpus to remain static. Otherwise ntp frequency 1965 * correction applies to one vcpu's system_timestamp but not 1966 * the others. 1967 * 1968 * So in those cases, request a kvmclock update for all vcpus. 1969 * We need to rate-limit these requests though, as they can 1970 * considerably slow guests that have a large number of vcpus. 1971 * The time for a remote vcpu to update its kvmclock is bound 1972 * by the delay we use to rate-limit the updates. 1973 */ 1974 1975 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 1976 1977 static void kvmclock_update_fn(struct work_struct *work) 1978 { 1979 int i; 1980 struct delayed_work *dwork = to_delayed_work(work); 1981 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1982 kvmclock_update_work); 1983 struct kvm *kvm = container_of(ka, struct kvm, arch); 1984 struct kvm_vcpu *vcpu; 1985 1986 kvm_for_each_vcpu(i, vcpu, kvm) { 1987 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1988 kvm_vcpu_kick(vcpu); 1989 } 1990 } 1991 1992 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 1993 { 1994 struct kvm *kvm = v->kvm; 1995 1996 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1997 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 1998 KVMCLOCK_UPDATE_DELAY); 1999 } 2000 2001 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 2002 2003 static void kvmclock_sync_fn(struct work_struct *work) 2004 { 2005 struct delayed_work *dwork = to_delayed_work(work); 2006 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2007 kvmclock_sync_work); 2008 struct kvm *kvm = container_of(ka, struct kvm, arch); 2009 2010 if (!kvmclock_periodic_sync) 2011 return; 2012 2013 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 2014 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 2015 KVMCLOCK_SYNC_PERIOD); 2016 } 2017 2018 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2019 { 2020 u64 mcg_cap = vcpu->arch.mcg_cap; 2021 unsigned bank_num = mcg_cap & 0xff; 2022 u32 msr = msr_info->index; 2023 u64 data = msr_info->data; 2024 2025 switch (msr) { 2026 case MSR_IA32_MCG_STATUS: 2027 vcpu->arch.mcg_status = data; 2028 break; 2029 case MSR_IA32_MCG_CTL: 2030 if (!(mcg_cap & MCG_CTL_P)) 2031 return 1; 2032 if (data != 0 && data != ~(u64)0) 2033 return -1; 2034 vcpu->arch.mcg_ctl = data; 2035 break; 2036 default: 2037 if (msr >= MSR_IA32_MC0_CTL && 2038 msr < MSR_IA32_MCx_CTL(bank_num)) { 2039 u32 offset = msr - MSR_IA32_MC0_CTL; 2040 /* only 0 or all 1s can be written to IA32_MCi_CTL 2041 * some Linux kernels though clear bit 10 in bank 4 to 2042 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 2043 * this to avoid an uncatched #GP in the guest 2044 */ 2045 if ((offset & 0x3) == 0 && 2046 data != 0 && (data | (1 << 10)) != ~(u64)0) 2047 return -1; 2048 if (!msr_info->host_initiated && 2049 (offset & 0x3) == 1 && data != 0) 2050 return -1; 2051 vcpu->arch.mce_banks[offset] = data; 2052 break; 2053 } 2054 return 1; 2055 } 2056 return 0; 2057 } 2058 2059 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 2060 { 2061 struct kvm *kvm = vcpu->kvm; 2062 int lm = is_long_mode(vcpu); 2063 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 2064 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 2065 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 2066 : kvm->arch.xen_hvm_config.blob_size_32; 2067 u32 page_num = data & ~PAGE_MASK; 2068 u64 page_addr = data & PAGE_MASK; 2069 u8 *page; 2070 int r; 2071 2072 r = -E2BIG; 2073 if (page_num >= blob_size) 2074 goto out; 2075 r = -ENOMEM; 2076 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 2077 if (IS_ERR(page)) { 2078 r = PTR_ERR(page); 2079 goto out; 2080 } 2081 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 2082 goto out_free; 2083 r = 0; 2084 out_free: 2085 kfree(page); 2086 out: 2087 return r; 2088 } 2089 2090 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2091 { 2092 gpa_t gpa = data & ~0x3f; 2093 2094 /* Bits 3:5 are reserved, Should be zero */ 2095 if (data & 0x38) 2096 return 1; 2097 2098 vcpu->arch.apf.msr_val = data; 2099 2100 if (!(data & KVM_ASYNC_PF_ENABLED)) { 2101 kvm_clear_async_pf_completion_queue(vcpu); 2102 kvm_async_pf_hash_reset(vcpu); 2103 return 0; 2104 } 2105 2106 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2107 sizeof(u32))) 2108 return 1; 2109 2110 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2111 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 2112 kvm_async_pf_wakeup_all(vcpu); 2113 return 0; 2114 } 2115 2116 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2117 { 2118 vcpu->arch.pv_time_enabled = false; 2119 } 2120 2121 static void record_steal_time(struct kvm_vcpu *vcpu) 2122 { 2123 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2124 return; 2125 2126 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2127 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2128 return; 2129 2130 vcpu->arch.st.steal.preempted = 0; 2131 2132 if (vcpu->arch.st.steal.version & 1) 2133 vcpu->arch.st.steal.version += 1; /* first time write, random junk */ 2134 2135 vcpu->arch.st.steal.version += 1; 2136 2137 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2138 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2139 2140 smp_wmb(); 2141 2142 vcpu->arch.st.steal.steal += current->sched_info.run_delay - 2143 vcpu->arch.st.last_steal; 2144 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2145 2146 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2147 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2148 2149 smp_wmb(); 2150 2151 vcpu->arch.st.steal.version += 1; 2152 2153 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2154 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2155 } 2156 2157 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2158 { 2159 bool pr = false; 2160 u32 msr = msr_info->index; 2161 u64 data = msr_info->data; 2162 2163 switch (msr) { 2164 case MSR_AMD64_NB_CFG: 2165 case MSR_IA32_UCODE_REV: 2166 case MSR_IA32_UCODE_WRITE: 2167 case MSR_VM_HSAVE_PA: 2168 case MSR_AMD64_PATCH_LOADER: 2169 case MSR_AMD64_BU_CFG2: 2170 case MSR_AMD64_DC_CFG: 2171 break; 2172 2173 case MSR_EFER: 2174 return set_efer(vcpu, data); 2175 case MSR_K7_HWCR: 2176 data &= ~(u64)0x40; /* ignore flush filter disable */ 2177 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2178 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2179 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2180 if (data != 0) { 2181 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2182 data); 2183 return 1; 2184 } 2185 break; 2186 case MSR_FAM10H_MMIO_CONF_BASE: 2187 if (data != 0) { 2188 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2189 "0x%llx\n", data); 2190 return 1; 2191 } 2192 break; 2193 case MSR_IA32_DEBUGCTLMSR: 2194 if (!data) { 2195 /* We support the non-activated case already */ 2196 break; 2197 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2198 /* Values other than LBR and BTF are vendor-specific, 2199 thus reserved and should throw a #GP */ 2200 return 1; 2201 } 2202 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2203 __func__, data); 2204 break; 2205 case 0x200 ... 0x2ff: 2206 return kvm_mtrr_set_msr(vcpu, msr, data); 2207 case MSR_IA32_APICBASE: 2208 return kvm_set_apic_base(vcpu, msr_info); 2209 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2210 return kvm_x2apic_msr_write(vcpu, msr, data); 2211 case MSR_IA32_TSCDEADLINE: 2212 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2213 break; 2214 case MSR_IA32_TSC_ADJUST: 2215 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 2216 if (!msr_info->host_initiated) { 2217 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2218 adjust_tsc_offset_guest(vcpu, adj); 2219 } 2220 vcpu->arch.ia32_tsc_adjust_msr = data; 2221 } 2222 break; 2223 case MSR_IA32_MISC_ENABLE: 2224 vcpu->arch.ia32_misc_enable_msr = data; 2225 break; 2226 case MSR_IA32_SMBASE: 2227 if (!msr_info->host_initiated) 2228 return 1; 2229 vcpu->arch.smbase = data; 2230 break; 2231 case MSR_KVM_WALL_CLOCK_NEW: 2232 case MSR_KVM_WALL_CLOCK: 2233 vcpu->kvm->arch.wall_clock = data; 2234 kvm_write_wall_clock(vcpu->kvm, data); 2235 break; 2236 case MSR_KVM_SYSTEM_TIME_NEW: 2237 case MSR_KVM_SYSTEM_TIME: { 2238 struct kvm_arch *ka = &vcpu->kvm->arch; 2239 2240 kvmclock_reset(vcpu); 2241 2242 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2243 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2244 2245 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2246 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2247 2248 ka->boot_vcpu_runs_old_kvmclock = tmp; 2249 } 2250 2251 vcpu->arch.time = data; 2252 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2253 2254 /* we verify if the enable bit is set... */ 2255 if (!(data & 1)) 2256 break; 2257 2258 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2259 &vcpu->arch.pv_time, data & ~1ULL, 2260 sizeof(struct pvclock_vcpu_time_info))) 2261 vcpu->arch.pv_time_enabled = false; 2262 else 2263 vcpu->arch.pv_time_enabled = true; 2264 2265 break; 2266 } 2267 case MSR_KVM_ASYNC_PF_EN: 2268 if (kvm_pv_enable_async_pf(vcpu, data)) 2269 return 1; 2270 break; 2271 case MSR_KVM_STEAL_TIME: 2272 2273 if (unlikely(!sched_info_on())) 2274 return 1; 2275 2276 if (data & KVM_STEAL_RESERVED_MASK) 2277 return 1; 2278 2279 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2280 data & KVM_STEAL_VALID_BITS, 2281 sizeof(struct kvm_steal_time))) 2282 return 1; 2283 2284 vcpu->arch.st.msr_val = data; 2285 2286 if (!(data & KVM_MSR_ENABLED)) 2287 break; 2288 2289 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2290 2291 break; 2292 case MSR_KVM_PV_EOI_EN: 2293 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2294 return 1; 2295 break; 2296 2297 case MSR_IA32_MCG_CTL: 2298 case MSR_IA32_MCG_STATUS: 2299 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2300 return set_msr_mce(vcpu, msr_info); 2301 2302 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2303 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2304 pr = true; /* fall through */ 2305 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2306 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2307 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2308 return kvm_pmu_set_msr(vcpu, msr_info); 2309 2310 if (pr || data != 0) 2311 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2312 "0x%x data 0x%llx\n", msr, data); 2313 break; 2314 case MSR_K7_CLK_CTL: 2315 /* 2316 * Ignore all writes to this no longer documented MSR. 2317 * Writes are only relevant for old K7 processors, 2318 * all pre-dating SVM, but a recommended workaround from 2319 * AMD for these chips. It is possible to specify the 2320 * affected processor models on the command line, hence 2321 * the need to ignore the workaround. 2322 */ 2323 break; 2324 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2325 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2326 case HV_X64_MSR_CRASH_CTL: 2327 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2328 return kvm_hv_set_msr_common(vcpu, msr, data, 2329 msr_info->host_initiated); 2330 case MSR_IA32_BBL_CR_CTL3: 2331 /* Drop writes to this legacy MSR -- see rdmsr 2332 * counterpart for further detail. 2333 */ 2334 if (report_ignored_msrs) 2335 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 2336 msr, data); 2337 break; 2338 case MSR_AMD64_OSVW_ID_LENGTH: 2339 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2340 return 1; 2341 vcpu->arch.osvw.length = data; 2342 break; 2343 case MSR_AMD64_OSVW_STATUS: 2344 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2345 return 1; 2346 vcpu->arch.osvw.status = data; 2347 break; 2348 case MSR_PLATFORM_INFO: 2349 if (!msr_info->host_initiated || 2350 data & ~MSR_PLATFORM_INFO_CPUID_FAULT || 2351 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 2352 cpuid_fault_enabled(vcpu))) 2353 return 1; 2354 vcpu->arch.msr_platform_info = data; 2355 break; 2356 case MSR_MISC_FEATURES_ENABLES: 2357 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 2358 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 2359 !supports_cpuid_fault(vcpu))) 2360 return 1; 2361 vcpu->arch.msr_misc_features_enables = data; 2362 break; 2363 default: 2364 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2365 return xen_hvm_config(vcpu, data); 2366 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2367 return kvm_pmu_set_msr(vcpu, msr_info); 2368 if (!ignore_msrs) { 2369 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n", 2370 msr, data); 2371 return 1; 2372 } else { 2373 if (report_ignored_msrs) 2374 vcpu_unimpl(vcpu, 2375 "ignored wrmsr: 0x%x data 0x%llx\n", 2376 msr, data); 2377 break; 2378 } 2379 } 2380 return 0; 2381 } 2382 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2383 2384 2385 /* 2386 * Reads an msr value (of 'msr_index') into 'pdata'. 2387 * Returns 0 on success, non-0 otherwise. 2388 * Assumes vcpu_load() was already called. 2389 */ 2390 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 2391 { 2392 return kvm_x86_ops->get_msr(vcpu, msr); 2393 } 2394 EXPORT_SYMBOL_GPL(kvm_get_msr); 2395 2396 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2397 { 2398 u64 data; 2399 u64 mcg_cap = vcpu->arch.mcg_cap; 2400 unsigned bank_num = mcg_cap & 0xff; 2401 2402 switch (msr) { 2403 case MSR_IA32_P5_MC_ADDR: 2404 case MSR_IA32_P5_MC_TYPE: 2405 data = 0; 2406 break; 2407 case MSR_IA32_MCG_CAP: 2408 data = vcpu->arch.mcg_cap; 2409 break; 2410 case MSR_IA32_MCG_CTL: 2411 if (!(mcg_cap & MCG_CTL_P)) 2412 return 1; 2413 data = vcpu->arch.mcg_ctl; 2414 break; 2415 case MSR_IA32_MCG_STATUS: 2416 data = vcpu->arch.mcg_status; 2417 break; 2418 default: 2419 if (msr >= MSR_IA32_MC0_CTL && 2420 msr < MSR_IA32_MCx_CTL(bank_num)) { 2421 u32 offset = msr - MSR_IA32_MC0_CTL; 2422 data = vcpu->arch.mce_banks[offset]; 2423 break; 2424 } 2425 return 1; 2426 } 2427 *pdata = data; 2428 return 0; 2429 } 2430 2431 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2432 { 2433 switch (msr_info->index) { 2434 case MSR_IA32_PLATFORM_ID: 2435 case MSR_IA32_EBL_CR_POWERON: 2436 case MSR_IA32_DEBUGCTLMSR: 2437 case MSR_IA32_LASTBRANCHFROMIP: 2438 case MSR_IA32_LASTBRANCHTOIP: 2439 case MSR_IA32_LASTINTFROMIP: 2440 case MSR_IA32_LASTINTTOIP: 2441 case MSR_K8_SYSCFG: 2442 case MSR_K8_TSEG_ADDR: 2443 case MSR_K8_TSEG_MASK: 2444 case MSR_K7_HWCR: 2445 case MSR_VM_HSAVE_PA: 2446 case MSR_K8_INT_PENDING_MSG: 2447 case MSR_AMD64_NB_CFG: 2448 case MSR_FAM10H_MMIO_CONF_BASE: 2449 case MSR_AMD64_BU_CFG2: 2450 case MSR_IA32_PERF_CTL: 2451 case MSR_AMD64_DC_CFG: 2452 msr_info->data = 0; 2453 break; 2454 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2455 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2456 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2457 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2458 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2459 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2460 msr_info->data = 0; 2461 break; 2462 case MSR_IA32_UCODE_REV: 2463 msr_info->data = 0x100000000ULL; 2464 break; 2465 case MSR_MTRRcap: 2466 case 0x200 ... 0x2ff: 2467 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 2468 case 0xcd: /* fsb frequency */ 2469 msr_info->data = 3; 2470 break; 2471 /* 2472 * MSR_EBC_FREQUENCY_ID 2473 * Conservative value valid for even the basic CPU models. 2474 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2475 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2476 * and 266MHz for model 3, or 4. Set Core Clock 2477 * Frequency to System Bus Frequency Ratio to 1 (bits 2478 * 31:24) even though these are only valid for CPU 2479 * models > 2, however guests may end up dividing or 2480 * multiplying by zero otherwise. 2481 */ 2482 case MSR_EBC_FREQUENCY_ID: 2483 msr_info->data = 1 << 24; 2484 break; 2485 case MSR_IA32_APICBASE: 2486 msr_info->data = kvm_get_apic_base(vcpu); 2487 break; 2488 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2489 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 2490 break; 2491 case MSR_IA32_TSCDEADLINE: 2492 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 2493 break; 2494 case MSR_IA32_TSC_ADJUST: 2495 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2496 break; 2497 case MSR_IA32_MISC_ENABLE: 2498 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 2499 break; 2500 case MSR_IA32_SMBASE: 2501 if (!msr_info->host_initiated) 2502 return 1; 2503 msr_info->data = vcpu->arch.smbase; 2504 break; 2505 case MSR_IA32_PERF_STATUS: 2506 /* TSC increment by tick */ 2507 msr_info->data = 1000ULL; 2508 /* CPU multiplier */ 2509 msr_info->data |= (((uint64_t)4ULL) << 40); 2510 break; 2511 case MSR_EFER: 2512 msr_info->data = vcpu->arch.efer; 2513 break; 2514 case MSR_KVM_WALL_CLOCK: 2515 case MSR_KVM_WALL_CLOCK_NEW: 2516 msr_info->data = vcpu->kvm->arch.wall_clock; 2517 break; 2518 case MSR_KVM_SYSTEM_TIME: 2519 case MSR_KVM_SYSTEM_TIME_NEW: 2520 msr_info->data = vcpu->arch.time; 2521 break; 2522 case MSR_KVM_ASYNC_PF_EN: 2523 msr_info->data = vcpu->arch.apf.msr_val; 2524 break; 2525 case MSR_KVM_STEAL_TIME: 2526 msr_info->data = vcpu->arch.st.msr_val; 2527 break; 2528 case MSR_KVM_PV_EOI_EN: 2529 msr_info->data = vcpu->arch.pv_eoi.msr_val; 2530 break; 2531 case MSR_IA32_P5_MC_ADDR: 2532 case MSR_IA32_P5_MC_TYPE: 2533 case MSR_IA32_MCG_CAP: 2534 case MSR_IA32_MCG_CTL: 2535 case MSR_IA32_MCG_STATUS: 2536 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2537 return get_msr_mce(vcpu, msr_info->index, &msr_info->data); 2538 case MSR_K7_CLK_CTL: 2539 /* 2540 * Provide expected ramp-up count for K7. All other 2541 * are set to zero, indicating minimum divisors for 2542 * every field. 2543 * 2544 * This prevents guest kernels on AMD host with CPU 2545 * type 6, model 8 and higher from exploding due to 2546 * the rdmsr failing. 2547 */ 2548 msr_info->data = 0x20000000; 2549 break; 2550 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2551 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2552 case HV_X64_MSR_CRASH_CTL: 2553 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2554 return kvm_hv_get_msr_common(vcpu, 2555 msr_info->index, &msr_info->data); 2556 break; 2557 case MSR_IA32_BBL_CR_CTL3: 2558 /* This legacy MSR exists but isn't fully documented in current 2559 * silicon. It is however accessed by winxp in very narrow 2560 * scenarios where it sets bit #19, itself documented as 2561 * a "reserved" bit. Best effort attempt to source coherent 2562 * read data here should the balance of the register be 2563 * interpreted by the guest: 2564 * 2565 * L2 cache control register 3: 64GB range, 256KB size, 2566 * enabled, latency 0x1, configured 2567 */ 2568 msr_info->data = 0xbe702111; 2569 break; 2570 case MSR_AMD64_OSVW_ID_LENGTH: 2571 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2572 return 1; 2573 msr_info->data = vcpu->arch.osvw.length; 2574 break; 2575 case MSR_AMD64_OSVW_STATUS: 2576 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2577 return 1; 2578 msr_info->data = vcpu->arch.osvw.status; 2579 break; 2580 case MSR_PLATFORM_INFO: 2581 msr_info->data = vcpu->arch.msr_platform_info; 2582 break; 2583 case MSR_MISC_FEATURES_ENABLES: 2584 msr_info->data = vcpu->arch.msr_misc_features_enables; 2585 break; 2586 default: 2587 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2588 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2589 if (!ignore_msrs) { 2590 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n", 2591 msr_info->index); 2592 return 1; 2593 } else { 2594 if (report_ignored_msrs) 2595 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", 2596 msr_info->index); 2597 msr_info->data = 0; 2598 } 2599 break; 2600 } 2601 return 0; 2602 } 2603 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2604 2605 /* 2606 * Read or write a bunch of msrs. All parameters are kernel addresses. 2607 * 2608 * @return number of msrs set successfully. 2609 */ 2610 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2611 struct kvm_msr_entry *entries, 2612 int (*do_msr)(struct kvm_vcpu *vcpu, 2613 unsigned index, u64 *data)) 2614 { 2615 int i, idx; 2616 2617 idx = srcu_read_lock(&vcpu->kvm->srcu); 2618 for (i = 0; i < msrs->nmsrs; ++i) 2619 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2620 break; 2621 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2622 2623 return i; 2624 } 2625 2626 /* 2627 * Read or write a bunch of msrs. Parameters are user addresses. 2628 * 2629 * @return number of msrs set successfully. 2630 */ 2631 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2632 int (*do_msr)(struct kvm_vcpu *vcpu, 2633 unsigned index, u64 *data), 2634 int writeback) 2635 { 2636 struct kvm_msrs msrs; 2637 struct kvm_msr_entry *entries; 2638 int r, n; 2639 unsigned size; 2640 2641 r = -EFAULT; 2642 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2643 goto out; 2644 2645 r = -E2BIG; 2646 if (msrs.nmsrs >= MAX_IO_MSRS) 2647 goto out; 2648 2649 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2650 entries = memdup_user(user_msrs->entries, size); 2651 if (IS_ERR(entries)) { 2652 r = PTR_ERR(entries); 2653 goto out; 2654 } 2655 2656 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2657 if (r < 0) 2658 goto out_free; 2659 2660 r = -EFAULT; 2661 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2662 goto out_free; 2663 2664 r = n; 2665 2666 out_free: 2667 kfree(entries); 2668 out: 2669 return r; 2670 } 2671 2672 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2673 { 2674 int r; 2675 2676 switch (ext) { 2677 case KVM_CAP_IRQCHIP: 2678 case KVM_CAP_HLT: 2679 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2680 case KVM_CAP_SET_TSS_ADDR: 2681 case KVM_CAP_EXT_CPUID: 2682 case KVM_CAP_EXT_EMUL_CPUID: 2683 case KVM_CAP_CLOCKSOURCE: 2684 case KVM_CAP_PIT: 2685 case KVM_CAP_NOP_IO_DELAY: 2686 case KVM_CAP_MP_STATE: 2687 case KVM_CAP_SYNC_MMU: 2688 case KVM_CAP_USER_NMI: 2689 case KVM_CAP_REINJECT_CONTROL: 2690 case KVM_CAP_IRQ_INJECT_STATUS: 2691 case KVM_CAP_IOEVENTFD: 2692 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2693 case KVM_CAP_PIT2: 2694 case KVM_CAP_PIT_STATE2: 2695 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2696 case KVM_CAP_XEN_HVM: 2697 case KVM_CAP_VCPU_EVENTS: 2698 case KVM_CAP_HYPERV: 2699 case KVM_CAP_HYPERV_VAPIC: 2700 case KVM_CAP_HYPERV_SPIN: 2701 case KVM_CAP_HYPERV_SYNIC: 2702 case KVM_CAP_HYPERV_SYNIC2: 2703 case KVM_CAP_HYPERV_VP_INDEX: 2704 case KVM_CAP_PCI_SEGMENT: 2705 case KVM_CAP_DEBUGREGS: 2706 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2707 case KVM_CAP_XSAVE: 2708 case KVM_CAP_ASYNC_PF: 2709 case KVM_CAP_GET_TSC_KHZ: 2710 case KVM_CAP_KVMCLOCK_CTRL: 2711 case KVM_CAP_READONLY_MEM: 2712 case KVM_CAP_HYPERV_TIME: 2713 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2714 case KVM_CAP_TSC_DEADLINE_TIMER: 2715 case KVM_CAP_ENABLE_CAP_VM: 2716 case KVM_CAP_DISABLE_QUIRKS: 2717 case KVM_CAP_SET_BOOT_CPU_ID: 2718 case KVM_CAP_SPLIT_IRQCHIP: 2719 case KVM_CAP_IMMEDIATE_EXIT: 2720 r = 1; 2721 break; 2722 case KVM_CAP_ADJUST_CLOCK: 2723 r = KVM_CLOCK_TSC_STABLE; 2724 break; 2725 case KVM_CAP_X86_GUEST_MWAIT: 2726 r = kvm_mwait_in_guest(); 2727 break; 2728 case KVM_CAP_X86_SMM: 2729 /* SMBASE is usually relocated above 1M on modern chipsets, 2730 * and SMM handlers might indeed rely on 4G segment limits, 2731 * so do not report SMM to be available if real mode is 2732 * emulated via vm86 mode. Still, do not go to great lengths 2733 * to avoid userspace's usage of the feature, because it is a 2734 * fringe case that is not enabled except via specific settings 2735 * of the module parameters. 2736 */ 2737 r = kvm_x86_ops->cpu_has_high_real_mode_segbase(); 2738 break; 2739 case KVM_CAP_VAPIC: 2740 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2741 break; 2742 case KVM_CAP_NR_VCPUS: 2743 r = KVM_SOFT_MAX_VCPUS; 2744 break; 2745 case KVM_CAP_MAX_VCPUS: 2746 r = KVM_MAX_VCPUS; 2747 break; 2748 case KVM_CAP_NR_MEMSLOTS: 2749 r = KVM_USER_MEM_SLOTS; 2750 break; 2751 case KVM_CAP_PV_MMU: /* obsolete */ 2752 r = 0; 2753 break; 2754 case KVM_CAP_MCE: 2755 r = KVM_MAX_MCE_BANKS; 2756 break; 2757 case KVM_CAP_XCRS: 2758 r = boot_cpu_has(X86_FEATURE_XSAVE); 2759 break; 2760 case KVM_CAP_TSC_CONTROL: 2761 r = kvm_has_tsc_control; 2762 break; 2763 case KVM_CAP_X2APIC_API: 2764 r = KVM_X2APIC_API_VALID_FLAGS; 2765 break; 2766 default: 2767 r = 0; 2768 break; 2769 } 2770 return r; 2771 2772 } 2773 2774 long kvm_arch_dev_ioctl(struct file *filp, 2775 unsigned int ioctl, unsigned long arg) 2776 { 2777 void __user *argp = (void __user *)arg; 2778 long r; 2779 2780 switch (ioctl) { 2781 case KVM_GET_MSR_INDEX_LIST: { 2782 struct kvm_msr_list __user *user_msr_list = argp; 2783 struct kvm_msr_list msr_list; 2784 unsigned n; 2785 2786 r = -EFAULT; 2787 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2788 goto out; 2789 n = msr_list.nmsrs; 2790 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 2791 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2792 goto out; 2793 r = -E2BIG; 2794 if (n < msr_list.nmsrs) 2795 goto out; 2796 r = -EFAULT; 2797 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2798 num_msrs_to_save * sizeof(u32))) 2799 goto out; 2800 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2801 &emulated_msrs, 2802 num_emulated_msrs * sizeof(u32))) 2803 goto out; 2804 r = 0; 2805 break; 2806 } 2807 case KVM_GET_SUPPORTED_CPUID: 2808 case KVM_GET_EMULATED_CPUID: { 2809 struct kvm_cpuid2 __user *cpuid_arg = argp; 2810 struct kvm_cpuid2 cpuid; 2811 2812 r = -EFAULT; 2813 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2814 goto out; 2815 2816 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2817 ioctl); 2818 if (r) 2819 goto out; 2820 2821 r = -EFAULT; 2822 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2823 goto out; 2824 r = 0; 2825 break; 2826 } 2827 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2828 r = -EFAULT; 2829 if (copy_to_user(argp, &kvm_mce_cap_supported, 2830 sizeof(kvm_mce_cap_supported))) 2831 goto out; 2832 r = 0; 2833 break; 2834 } 2835 default: 2836 r = -EINVAL; 2837 } 2838 out: 2839 return r; 2840 } 2841 2842 static void wbinvd_ipi(void *garbage) 2843 { 2844 wbinvd(); 2845 } 2846 2847 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 2848 { 2849 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 2850 } 2851 2852 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 2853 { 2854 /* Address WBINVD may be executed by guest */ 2855 if (need_emulate_wbinvd(vcpu)) { 2856 if (kvm_x86_ops->has_wbinvd_exit()) 2857 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 2858 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 2859 smp_call_function_single(vcpu->cpu, 2860 wbinvd_ipi, NULL, 1); 2861 } 2862 2863 kvm_x86_ops->vcpu_load(vcpu, cpu); 2864 2865 /* Apply any externally detected TSC adjustments (due to suspend) */ 2866 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 2867 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 2868 vcpu->arch.tsc_offset_adjustment = 0; 2869 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2870 } 2871 2872 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { 2873 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 2874 rdtsc() - vcpu->arch.last_host_tsc; 2875 if (tsc_delta < 0) 2876 mark_tsc_unstable("KVM discovered backwards TSC"); 2877 2878 if (check_tsc_unstable()) { 2879 u64 offset = kvm_compute_tsc_offset(vcpu, 2880 vcpu->arch.last_guest_tsc); 2881 kvm_vcpu_write_tsc_offset(vcpu, offset); 2882 vcpu->arch.tsc_catchup = 1; 2883 } 2884 2885 if (kvm_lapic_hv_timer_in_use(vcpu)) 2886 kvm_lapic_restart_hv_timer(vcpu); 2887 2888 /* 2889 * On a host with synchronized TSC, there is no need to update 2890 * kvmclock on vcpu->cpu migration 2891 */ 2892 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 2893 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2894 if (vcpu->cpu != cpu) 2895 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 2896 vcpu->cpu = cpu; 2897 } 2898 2899 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2900 } 2901 2902 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 2903 { 2904 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2905 return; 2906 2907 vcpu->arch.st.steal.preempted = 1; 2908 2909 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime, 2910 &vcpu->arch.st.steal.preempted, 2911 offsetof(struct kvm_steal_time, preempted), 2912 sizeof(vcpu->arch.st.steal.preempted)); 2913 } 2914 2915 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 2916 { 2917 int idx; 2918 2919 if (vcpu->preempted) 2920 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu); 2921 2922 /* 2923 * Disable page faults because we're in atomic context here. 2924 * kvm_write_guest_offset_cached() would call might_fault() 2925 * that relies on pagefault_disable() to tell if there's a 2926 * bug. NOTE: the write to guest memory may not go through if 2927 * during postcopy live migration or if there's heavy guest 2928 * paging. 2929 */ 2930 pagefault_disable(); 2931 /* 2932 * kvm_memslots() will be called by 2933 * kvm_write_guest_offset_cached() so take the srcu lock. 2934 */ 2935 idx = srcu_read_lock(&vcpu->kvm->srcu); 2936 kvm_steal_time_set_preempted(vcpu); 2937 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2938 pagefault_enable(); 2939 kvm_x86_ops->vcpu_put(vcpu); 2940 kvm_put_guest_fpu(vcpu); 2941 vcpu->arch.last_host_tsc = rdtsc(); 2942 } 2943 2944 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 2945 struct kvm_lapic_state *s) 2946 { 2947 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active) 2948 kvm_x86_ops->sync_pir_to_irr(vcpu); 2949 2950 return kvm_apic_get_state(vcpu, s); 2951 } 2952 2953 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 2954 struct kvm_lapic_state *s) 2955 { 2956 int r; 2957 2958 r = kvm_apic_set_state(vcpu, s); 2959 if (r) 2960 return r; 2961 update_cr8_intercept(vcpu); 2962 2963 return 0; 2964 } 2965 2966 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 2967 { 2968 return (!lapic_in_kernel(vcpu) || 2969 kvm_apic_accept_pic_intr(vcpu)); 2970 } 2971 2972 /* 2973 * if userspace requested an interrupt window, check that the 2974 * interrupt window is open. 2975 * 2976 * No need to exit to userspace if we already have an interrupt queued. 2977 */ 2978 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 2979 { 2980 return kvm_arch_interrupt_allowed(vcpu) && 2981 !kvm_cpu_has_interrupt(vcpu) && 2982 !kvm_event_needs_reinjection(vcpu) && 2983 kvm_cpu_accept_dm_intr(vcpu); 2984 } 2985 2986 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 2987 struct kvm_interrupt *irq) 2988 { 2989 if (irq->irq >= KVM_NR_INTERRUPTS) 2990 return -EINVAL; 2991 2992 if (!irqchip_in_kernel(vcpu->kvm)) { 2993 kvm_queue_interrupt(vcpu, irq->irq, false); 2994 kvm_make_request(KVM_REQ_EVENT, vcpu); 2995 return 0; 2996 } 2997 2998 /* 2999 * With in-kernel LAPIC, we only use this to inject EXTINT, so 3000 * fail for in-kernel 8259. 3001 */ 3002 if (pic_in_kernel(vcpu->kvm)) 3003 return -ENXIO; 3004 3005 if (vcpu->arch.pending_external_vector != -1) 3006 return -EEXIST; 3007 3008 vcpu->arch.pending_external_vector = irq->irq; 3009 kvm_make_request(KVM_REQ_EVENT, vcpu); 3010 return 0; 3011 } 3012 3013 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 3014 { 3015 kvm_inject_nmi(vcpu); 3016 3017 return 0; 3018 } 3019 3020 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 3021 { 3022 kvm_make_request(KVM_REQ_SMI, vcpu); 3023 3024 return 0; 3025 } 3026 3027 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 3028 struct kvm_tpr_access_ctl *tac) 3029 { 3030 if (tac->flags) 3031 return -EINVAL; 3032 vcpu->arch.tpr_access_reporting = !!tac->enabled; 3033 return 0; 3034 } 3035 3036 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 3037 u64 mcg_cap) 3038 { 3039 int r; 3040 unsigned bank_num = mcg_cap & 0xff, bank; 3041 3042 r = -EINVAL; 3043 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 3044 goto out; 3045 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 3046 goto out; 3047 r = 0; 3048 vcpu->arch.mcg_cap = mcg_cap; 3049 /* Init IA32_MCG_CTL to all 1s */ 3050 if (mcg_cap & MCG_CTL_P) 3051 vcpu->arch.mcg_ctl = ~(u64)0; 3052 /* Init IA32_MCi_CTL to all 1s */ 3053 for (bank = 0; bank < bank_num; bank++) 3054 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 3055 3056 if (kvm_x86_ops->setup_mce) 3057 kvm_x86_ops->setup_mce(vcpu); 3058 out: 3059 return r; 3060 } 3061 3062 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 3063 struct kvm_x86_mce *mce) 3064 { 3065 u64 mcg_cap = vcpu->arch.mcg_cap; 3066 unsigned bank_num = mcg_cap & 0xff; 3067 u64 *banks = vcpu->arch.mce_banks; 3068 3069 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 3070 return -EINVAL; 3071 /* 3072 * if IA32_MCG_CTL is not all 1s, the uncorrected error 3073 * reporting is disabled 3074 */ 3075 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 3076 vcpu->arch.mcg_ctl != ~(u64)0) 3077 return 0; 3078 banks += 4 * mce->bank; 3079 /* 3080 * if IA32_MCi_CTL is not all 1s, the uncorrected error 3081 * reporting is disabled for the bank 3082 */ 3083 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 3084 return 0; 3085 if (mce->status & MCI_STATUS_UC) { 3086 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 3087 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 3088 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 3089 return 0; 3090 } 3091 if (banks[1] & MCI_STATUS_VAL) 3092 mce->status |= MCI_STATUS_OVER; 3093 banks[2] = mce->addr; 3094 banks[3] = mce->misc; 3095 vcpu->arch.mcg_status = mce->mcg_status; 3096 banks[1] = mce->status; 3097 kvm_queue_exception(vcpu, MC_VECTOR); 3098 } else if (!(banks[1] & MCI_STATUS_VAL) 3099 || !(banks[1] & MCI_STATUS_UC)) { 3100 if (banks[1] & MCI_STATUS_VAL) 3101 mce->status |= MCI_STATUS_OVER; 3102 banks[2] = mce->addr; 3103 banks[3] = mce->misc; 3104 banks[1] = mce->status; 3105 } else 3106 banks[1] |= MCI_STATUS_OVER; 3107 return 0; 3108 } 3109 3110 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 3111 struct kvm_vcpu_events *events) 3112 { 3113 process_nmi(vcpu); 3114 /* 3115 * FIXME: pass injected and pending separately. This is only 3116 * needed for nested virtualization, whose state cannot be 3117 * migrated yet. For now we can combine them. 3118 */ 3119 events->exception.injected = 3120 (vcpu->arch.exception.pending || 3121 vcpu->arch.exception.injected) && 3122 !kvm_exception_is_soft(vcpu->arch.exception.nr); 3123 events->exception.nr = vcpu->arch.exception.nr; 3124 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 3125 events->exception.pad = 0; 3126 events->exception.error_code = vcpu->arch.exception.error_code; 3127 3128 events->interrupt.injected = 3129 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; 3130 events->interrupt.nr = vcpu->arch.interrupt.nr; 3131 events->interrupt.soft = 0; 3132 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 3133 3134 events->nmi.injected = vcpu->arch.nmi_injected; 3135 events->nmi.pending = vcpu->arch.nmi_pending != 0; 3136 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 3137 events->nmi.pad = 0; 3138 3139 events->sipi_vector = 0; /* never valid when reporting to user space */ 3140 3141 events->smi.smm = is_smm(vcpu); 3142 events->smi.pending = vcpu->arch.smi_pending; 3143 events->smi.smm_inside_nmi = 3144 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 3145 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 3146 3147 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 3148 | KVM_VCPUEVENT_VALID_SHADOW 3149 | KVM_VCPUEVENT_VALID_SMM); 3150 memset(&events->reserved, 0, sizeof(events->reserved)); 3151 } 3152 3153 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags); 3154 3155 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 3156 struct kvm_vcpu_events *events) 3157 { 3158 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 3159 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 3160 | KVM_VCPUEVENT_VALID_SHADOW 3161 | KVM_VCPUEVENT_VALID_SMM)) 3162 return -EINVAL; 3163 3164 if (events->exception.injected && 3165 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR || 3166 is_guest_mode(vcpu))) 3167 return -EINVAL; 3168 3169 /* INITs are latched while in SMM */ 3170 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 3171 (events->smi.smm || events->smi.pending) && 3172 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 3173 return -EINVAL; 3174 3175 process_nmi(vcpu); 3176 vcpu->arch.exception.injected = false; 3177 vcpu->arch.exception.pending = events->exception.injected; 3178 vcpu->arch.exception.nr = events->exception.nr; 3179 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 3180 vcpu->arch.exception.error_code = events->exception.error_code; 3181 3182 vcpu->arch.interrupt.pending = events->interrupt.injected; 3183 vcpu->arch.interrupt.nr = events->interrupt.nr; 3184 vcpu->arch.interrupt.soft = events->interrupt.soft; 3185 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3186 kvm_x86_ops->set_interrupt_shadow(vcpu, 3187 events->interrupt.shadow); 3188 3189 vcpu->arch.nmi_injected = events->nmi.injected; 3190 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3191 vcpu->arch.nmi_pending = events->nmi.pending; 3192 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 3193 3194 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3195 lapic_in_kernel(vcpu)) 3196 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3197 3198 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 3199 u32 hflags = vcpu->arch.hflags; 3200 if (events->smi.smm) 3201 hflags |= HF_SMM_MASK; 3202 else 3203 hflags &= ~HF_SMM_MASK; 3204 kvm_set_hflags(vcpu, hflags); 3205 3206 vcpu->arch.smi_pending = events->smi.pending; 3207 3208 if (events->smi.smm) { 3209 if (events->smi.smm_inside_nmi) 3210 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 3211 else 3212 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 3213 if (lapic_in_kernel(vcpu)) { 3214 if (events->smi.latched_init) 3215 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3216 else 3217 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3218 } 3219 } 3220 } 3221 3222 kvm_make_request(KVM_REQ_EVENT, vcpu); 3223 3224 return 0; 3225 } 3226 3227 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3228 struct kvm_debugregs *dbgregs) 3229 { 3230 unsigned long val; 3231 3232 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3233 kvm_get_dr(vcpu, 6, &val); 3234 dbgregs->dr6 = val; 3235 dbgregs->dr7 = vcpu->arch.dr7; 3236 dbgregs->flags = 0; 3237 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3238 } 3239 3240 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3241 struct kvm_debugregs *dbgregs) 3242 { 3243 if (dbgregs->flags) 3244 return -EINVAL; 3245 3246 if (dbgregs->dr6 & ~0xffffffffull) 3247 return -EINVAL; 3248 if (dbgregs->dr7 & ~0xffffffffull) 3249 return -EINVAL; 3250 3251 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3252 kvm_update_dr0123(vcpu); 3253 vcpu->arch.dr6 = dbgregs->dr6; 3254 kvm_update_dr6(vcpu); 3255 vcpu->arch.dr7 = dbgregs->dr7; 3256 kvm_update_dr7(vcpu); 3257 3258 return 0; 3259 } 3260 3261 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3262 3263 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3264 { 3265 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3266 u64 xstate_bv = xsave->header.xfeatures; 3267 u64 valid; 3268 3269 /* 3270 * Copy legacy XSAVE area, to avoid complications with CPUID 3271 * leaves 0 and 1 in the loop below. 3272 */ 3273 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3274 3275 /* Set XSTATE_BV */ 3276 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; 3277 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3278 3279 /* 3280 * Copy each region from the possibly compacted offset to the 3281 * non-compacted offset. 3282 */ 3283 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3284 while (valid) { 3285 u64 feature = valid & -valid; 3286 int index = fls64(feature) - 1; 3287 void *src = get_xsave_addr(xsave, feature); 3288 3289 if (src) { 3290 u32 size, offset, ecx, edx; 3291 cpuid_count(XSTATE_CPUID, index, 3292 &size, &offset, &ecx, &edx); 3293 if (feature == XFEATURE_MASK_PKRU) 3294 memcpy(dest + offset, &vcpu->arch.pkru, 3295 sizeof(vcpu->arch.pkru)); 3296 else 3297 memcpy(dest + offset, src, size); 3298 3299 } 3300 3301 valid -= feature; 3302 } 3303 } 3304 3305 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3306 { 3307 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3308 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3309 u64 valid; 3310 3311 /* 3312 * Copy legacy XSAVE area, to avoid complications with CPUID 3313 * leaves 0 and 1 in the loop below. 3314 */ 3315 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3316 3317 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3318 xsave->header.xfeatures = xstate_bv; 3319 if (boot_cpu_has(X86_FEATURE_XSAVES)) 3320 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3321 3322 /* 3323 * Copy each region from the non-compacted offset to the 3324 * possibly compacted offset. 3325 */ 3326 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3327 while (valid) { 3328 u64 feature = valid & -valid; 3329 int index = fls64(feature) - 1; 3330 void *dest = get_xsave_addr(xsave, feature); 3331 3332 if (dest) { 3333 u32 size, offset, ecx, edx; 3334 cpuid_count(XSTATE_CPUID, index, 3335 &size, &offset, &ecx, &edx); 3336 if (feature == XFEATURE_MASK_PKRU) 3337 memcpy(&vcpu->arch.pkru, src + offset, 3338 sizeof(vcpu->arch.pkru)); 3339 else 3340 memcpy(dest, src + offset, size); 3341 } 3342 3343 valid -= feature; 3344 } 3345 } 3346 3347 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3348 struct kvm_xsave *guest_xsave) 3349 { 3350 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3351 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3352 fill_xsave((u8 *) guest_xsave->region, vcpu); 3353 } else { 3354 memcpy(guest_xsave->region, 3355 &vcpu->arch.guest_fpu.state.fxsave, 3356 sizeof(struct fxregs_state)); 3357 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3358 XFEATURE_MASK_FPSSE; 3359 } 3360 } 3361 3362 #define XSAVE_MXCSR_OFFSET 24 3363 3364 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3365 struct kvm_xsave *guest_xsave) 3366 { 3367 u64 xstate_bv = 3368 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3369 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; 3370 3371 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3372 /* 3373 * Here we allow setting states that are not present in 3374 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3375 * with old userspace. 3376 */ 3377 if (xstate_bv & ~kvm_supported_xcr0() || 3378 mxcsr & ~mxcsr_feature_mask) 3379 return -EINVAL; 3380 load_xsave(vcpu, (u8 *)guest_xsave->region); 3381 } else { 3382 if (xstate_bv & ~XFEATURE_MASK_FPSSE || 3383 mxcsr & ~mxcsr_feature_mask) 3384 return -EINVAL; 3385 memcpy(&vcpu->arch.guest_fpu.state.fxsave, 3386 guest_xsave->region, sizeof(struct fxregs_state)); 3387 } 3388 return 0; 3389 } 3390 3391 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3392 struct kvm_xcrs *guest_xcrs) 3393 { 3394 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 3395 guest_xcrs->nr_xcrs = 0; 3396 return; 3397 } 3398 3399 guest_xcrs->nr_xcrs = 1; 3400 guest_xcrs->flags = 0; 3401 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3402 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3403 } 3404 3405 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3406 struct kvm_xcrs *guest_xcrs) 3407 { 3408 int i, r = 0; 3409 3410 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 3411 return -EINVAL; 3412 3413 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3414 return -EINVAL; 3415 3416 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3417 /* Only support XCR0 currently */ 3418 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3419 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3420 guest_xcrs->xcrs[i].value); 3421 break; 3422 } 3423 if (r) 3424 r = -EINVAL; 3425 return r; 3426 } 3427 3428 /* 3429 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3430 * stopped by the hypervisor. This function will be called from the host only. 3431 * EINVAL is returned when the host attempts to set the flag for a guest that 3432 * does not support pv clocks. 3433 */ 3434 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3435 { 3436 if (!vcpu->arch.pv_time_enabled) 3437 return -EINVAL; 3438 vcpu->arch.pvclock_set_guest_stopped_request = true; 3439 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3440 return 0; 3441 } 3442 3443 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 3444 struct kvm_enable_cap *cap) 3445 { 3446 if (cap->flags) 3447 return -EINVAL; 3448 3449 switch (cap->cap) { 3450 case KVM_CAP_HYPERV_SYNIC2: 3451 if (cap->args[0]) 3452 return -EINVAL; 3453 case KVM_CAP_HYPERV_SYNIC: 3454 if (!irqchip_in_kernel(vcpu->kvm)) 3455 return -EINVAL; 3456 return kvm_hv_activate_synic(vcpu, cap->cap == 3457 KVM_CAP_HYPERV_SYNIC2); 3458 default: 3459 return -EINVAL; 3460 } 3461 } 3462 3463 long kvm_arch_vcpu_ioctl(struct file *filp, 3464 unsigned int ioctl, unsigned long arg) 3465 { 3466 struct kvm_vcpu *vcpu = filp->private_data; 3467 void __user *argp = (void __user *)arg; 3468 int r; 3469 union { 3470 struct kvm_lapic_state *lapic; 3471 struct kvm_xsave *xsave; 3472 struct kvm_xcrs *xcrs; 3473 void *buffer; 3474 } u; 3475 3476 u.buffer = NULL; 3477 switch (ioctl) { 3478 case KVM_GET_LAPIC: { 3479 r = -EINVAL; 3480 if (!lapic_in_kernel(vcpu)) 3481 goto out; 3482 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3483 3484 r = -ENOMEM; 3485 if (!u.lapic) 3486 goto out; 3487 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3488 if (r) 3489 goto out; 3490 r = -EFAULT; 3491 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3492 goto out; 3493 r = 0; 3494 break; 3495 } 3496 case KVM_SET_LAPIC: { 3497 r = -EINVAL; 3498 if (!lapic_in_kernel(vcpu)) 3499 goto out; 3500 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3501 if (IS_ERR(u.lapic)) 3502 return PTR_ERR(u.lapic); 3503 3504 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3505 break; 3506 } 3507 case KVM_INTERRUPT: { 3508 struct kvm_interrupt irq; 3509 3510 r = -EFAULT; 3511 if (copy_from_user(&irq, argp, sizeof irq)) 3512 goto out; 3513 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3514 break; 3515 } 3516 case KVM_NMI: { 3517 r = kvm_vcpu_ioctl_nmi(vcpu); 3518 break; 3519 } 3520 case KVM_SMI: { 3521 r = kvm_vcpu_ioctl_smi(vcpu); 3522 break; 3523 } 3524 case KVM_SET_CPUID: { 3525 struct kvm_cpuid __user *cpuid_arg = argp; 3526 struct kvm_cpuid cpuid; 3527 3528 r = -EFAULT; 3529 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3530 goto out; 3531 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3532 break; 3533 } 3534 case KVM_SET_CPUID2: { 3535 struct kvm_cpuid2 __user *cpuid_arg = argp; 3536 struct kvm_cpuid2 cpuid; 3537 3538 r = -EFAULT; 3539 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3540 goto out; 3541 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3542 cpuid_arg->entries); 3543 break; 3544 } 3545 case KVM_GET_CPUID2: { 3546 struct kvm_cpuid2 __user *cpuid_arg = argp; 3547 struct kvm_cpuid2 cpuid; 3548 3549 r = -EFAULT; 3550 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3551 goto out; 3552 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3553 cpuid_arg->entries); 3554 if (r) 3555 goto out; 3556 r = -EFAULT; 3557 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3558 goto out; 3559 r = 0; 3560 break; 3561 } 3562 case KVM_GET_MSRS: 3563 r = msr_io(vcpu, argp, do_get_msr, 1); 3564 break; 3565 case KVM_SET_MSRS: 3566 r = msr_io(vcpu, argp, do_set_msr, 0); 3567 break; 3568 case KVM_TPR_ACCESS_REPORTING: { 3569 struct kvm_tpr_access_ctl tac; 3570 3571 r = -EFAULT; 3572 if (copy_from_user(&tac, argp, sizeof tac)) 3573 goto out; 3574 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3575 if (r) 3576 goto out; 3577 r = -EFAULT; 3578 if (copy_to_user(argp, &tac, sizeof tac)) 3579 goto out; 3580 r = 0; 3581 break; 3582 }; 3583 case KVM_SET_VAPIC_ADDR: { 3584 struct kvm_vapic_addr va; 3585 int idx; 3586 3587 r = -EINVAL; 3588 if (!lapic_in_kernel(vcpu)) 3589 goto out; 3590 r = -EFAULT; 3591 if (copy_from_user(&va, argp, sizeof va)) 3592 goto out; 3593 idx = srcu_read_lock(&vcpu->kvm->srcu); 3594 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3595 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3596 break; 3597 } 3598 case KVM_X86_SETUP_MCE: { 3599 u64 mcg_cap; 3600 3601 r = -EFAULT; 3602 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3603 goto out; 3604 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3605 break; 3606 } 3607 case KVM_X86_SET_MCE: { 3608 struct kvm_x86_mce mce; 3609 3610 r = -EFAULT; 3611 if (copy_from_user(&mce, argp, sizeof mce)) 3612 goto out; 3613 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3614 break; 3615 } 3616 case KVM_GET_VCPU_EVENTS: { 3617 struct kvm_vcpu_events events; 3618 3619 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3620 3621 r = -EFAULT; 3622 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3623 break; 3624 r = 0; 3625 break; 3626 } 3627 case KVM_SET_VCPU_EVENTS: { 3628 struct kvm_vcpu_events events; 3629 3630 r = -EFAULT; 3631 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3632 break; 3633 3634 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3635 break; 3636 } 3637 case KVM_GET_DEBUGREGS: { 3638 struct kvm_debugregs dbgregs; 3639 3640 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3641 3642 r = -EFAULT; 3643 if (copy_to_user(argp, &dbgregs, 3644 sizeof(struct kvm_debugregs))) 3645 break; 3646 r = 0; 3647 break; 3648 } 3649 case KVM_SET_DEBUGREGS: { 3650 struct kvm_debugregs dbgregs; 3651 3652 r = -EFAULT; 3653 if (copy_from_user(&dbgregs, argp, 3654 sizeof(struct kvm_debugregs))) 3655 break; 3656 3657 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3658 break; 3659 } 3660 case KVM_GET_XSAVE: { 3661 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3662 r = -ENOMEM; 3663 if (!u.xsave) 3664 break; 3665 3666 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3667 3668 r = -EFAULT; 3669 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3670 break; 3671 r = 0; 3672 break; 3673 } 3674 case KVM_SET_XSAVE: { 3675 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3676 if (IS_ERR(u.xsave)) 3677 return PTR_ERR(u.xsave); 3678 3679 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3680 break; 3681 } 3682 case KVM_GET_XCRS: { 3683 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3684 r = -ENOMEM; 3685 if (!u.xcrs) 3686 break; 3687 3688 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3689 3690 r = -EFAULT; 3691 if (copy_to_user(argp, u.xcrs, 3692 sizeof(struct kvm_xcrs))) 3693 break; 3694 r = 0; 3695 break; 3696 } 3697 case KVM_SET_XCRS: { 3698 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3699 if (IS_ERR(u.xcrs)) 3700 return PTR_ERR(u.xcrs); 3701 3702 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3703 break; 3704 } 3705 case KVM_SET_TSC_KHZ: { 3706 u32 user_tsc_khz; 3707 3708 r = -EINVAL; 3709 user_tsc_khz = (u32)arg; 3710 3711 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3712 goto out; 3713 3714 if (user_tsc_khz == 0) 3715 user_tsc_khz = tsc_khz; 3716 3717 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 3718 r = 0; 3719 3720 goto out; 3721 } 3722 case KVM_GET_TSC_KHZ: { 3723 r = vcpu->arch.virtual_tsc_khz; 3724 goto out; 3725 } 3726 case KVM_KVMCLOCK_CTRL: { 3727 r = kvm_set_guest_paused(vcpu); 3728 goto out; 3729 } 3730 case KVM_ENABLE_CAP: { 3731 struct kvm_enable_cap cap; 3732 3733 r = -EFAULT; 3734 if (copy_from_user(&cap, argp, sizeof(cap))) 3735 goto out; 3736 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 3737 break; 3738 } 3739 default: 3740 r = -EINVAL; 3741 } 3742 out: 3743 kfree(u.buffer); 3744 return r; 3745 } 3746 3747 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3748 { 3749 return VM_FAULT_SIGBUS; 3750 } 3751 3752 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3753 { 3754 int ret; 3755 3756 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3757 return -EINVAL; 3758 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3759 return ret; 3760 } 3761 3762 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3763 u64 ident_addr) 3764 { 3765 kvm->arch.ept_identity_map_addr = ident_addr; 3766 return 0; 3767 } 3768 3769 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3770 u32 kvm_nr_mmu_pages) 3771 { 3772 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3773 return -EINVAL; 3774 3775 mutex_lock(&kvm->slots_lock); 3776 3777 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3778 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3779 3780 mutex_unlock(&kvm->slots_lock); 3781 return 0; 3782 } 3783 3784 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 3785 { 3786 return kvm->arch.n_max_mmu_pages; 3787 } 3788 3789 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3790 { 3791 struct kvm_pic *pic = kvm->arch.vpic; 3792 int r; 3793 3794 r = 0; 3795 switch (chip->chip_id) { 3796 case KVM_IRQCHIP_PIC_MASTER: 3797 memcpy(&chip->chip.pic, &pic->pics[0], 3798 sizeof(struct kvm_pic_state)); 3799 break; 3800 case KVM_IRQCHIP_PIC_SLAVE: 3801 memcpy(&chip->chip.pic, &pic->pics[1], 3802 sizeof(struct kvm_pic_state)); 3803 break; 3804 case KVM_IRQCHIP_IOAPIC: 3805 kvm_get_ioapic(kvm, &chip->chip.ioapic); 3806 break; 3807 default: 3808 r = -EINVAL; 3809 break; 3810 } 3811 return r; 3812 } 3813 3814 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3815 { 3816 struct kvm_pic *pic = kvm->arch.vpic; 3817 int r; 3818 3819 r = 0; 3820 switch (chip->chip_id) { 3821 case KVM_IRQCHIP_PIC_MASTER: 3822 spin_lock(&pic->lock); 3823 memcpy(&pic->pics[0], &chip->chip.pic, 3824 sizeof(struct kvm_pic_state)); 3825 spin_unlock(&pic->lock); 3826 break; 3827 case KVM_IRQCHIP_PIC_SLAVE: 3828 spin_lock(&pic->lock); 3829 memcpy(&pic->pics[1], &chip->chip.pic, 3830 sizeof(struct kvm_pic_state)); 3831 spin_unlock(&pic->lock); 3832 break; 3833 case KVM_IRQCHIP_IOAPIC: 3834 kvm_set_ioapic(kvm, &chip->chip.ioapic); 3835 break; 3836 default: 3837 r = -EINVAL; 3838 break; 3839 } 3840 kvm_pic_update_irq(pic); 3841 return r; 3842 } 3843 3844 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3845 { 3846 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 3847 3848 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 3849 3850 mutex_lock(&kps->lock); 3851 memcpy(ps, &kps->channels, sizeof(*ps)); 3852 mutex_unlock(&kps->lock); 3853 return 0; 3854 } 3855 3856 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3857 { 3858 int i; 3859 struct kvm_pit *pit = kvm->arch.vpit; 3860 3861 mutex_lock(&pit->pit_state.lock); 3862 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 3863 for (i = 0; i < 3; i++) 3864 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 3865 mutex_unlock(&pit->pit_state.lock); 3866 return 0; 3867 } 3868 3869 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3870 { 3871 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3872 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 3873 sizeof(ps->channels)); 3874 ps->flags = kvm->arch.vpit->pit_state.flags; 3875 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3876 memset(&ps->reserved, 0, sizeof(ps->reserved)); 3877 return 0; 3878 } 3879 3880 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3881 { 3882 int start = 0; 3883 int i; 3884 u32 prev_legacy, cur_legacy; 3885 struct kvm_pit *pit = kvm->arch.vpit; 3886 3887 mutex_lock(&pit->pit_state.lock); 3888 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 3889 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 3890 if (!prev_legacy && cur_legacy) 3891 start = 1; 3892 memcpy(&pit->pit_state.channels, &ps->channels, 3893 sizeof(pit->pit_state.channels)); 3894 pit->pit_state.flags = ps->flags; 3895 for (i = 0; i < 3; i++) 3896 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 3897 start && i == 0); 3898 mutex_unlock(&pit->pit_state.lock); 3899 return 0; 3900 } 3901 3902 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 3903 struct kvm_reinject_control *control) 3904 { 3905 struct kvm_pit *pit = kvm->arch.vpit; 3906 3907 if (!pit) 3908 return -ENXIO; 3909 3910 /* pit->pit_state.lock was overloaded to prevent userspace from getting 3911 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 3912 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 3913 */ 3914 mutex_lock(&pit->pit_state.lock); 3915 kvm_pit_set_reinject(pit, control->pit_reinject); 3916 mutex_unlock(&pit->pit_state.lock); 3917 3918 return 0; 3919 } 3920 3921 /** 3922 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 3923 * @kvm: kvm instance 3924 * @log: slot id and address to which we copy the log 3925 * 3926 * Steps 1-4 below provide general overview of dirty page logging. See 3927 * kvm_get_dirty_log_protect() function description for additional details. 3928 * 3929 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 3930 * always flush the TLB (step 4) even if previous step failed and the dirty 3931 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 3932 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 3933 * writes will be marked dirty for next log read. 3934 * 3935 * 1. Take a snapshot of the bit and clear it if needed. 3936 * 2. Write protect the corresponding page. 3937 * 3. Copy the snapshot to the userspace. 3938 * 4. Flush TLB's if needed. 3939 */ 3940 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 3941 { 3942 bool is_dirty = false; 3943 int r; 3944 3945 mutex_lock(&kvm->slots_lock); 3946 3947 /* 3948 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 3949 */ 3950 if (kvm_x86_ops->flush_log_dirty) 3951 kvm_x86_ops->flush_log_dirty(kvm); 3952 3953 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 3954 3955 /* 3956 * All the TLBs can be flushed out of mmu lock, see the comments in 3957 * kvm_mmu_slot_remove_write_access(). 3958 */ 3959 lockdep_assert_held(&kvm->slots_lock); 3960 if (is_dirty) 3961 kvm_flush_remote_tlbs(kvm); 3962 3963 mutex_unlock(&kvm->slots_lock); 3964 return r; 3965 } 3966 3967 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 3968 bool line_status) 3969 { 3970 if (!irqchip_in_kernel(kvm)) 3971 return -ENXIO; 3972 3973 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 3974 irq_event->irq, irq_event->level, 3975 line_status); 3976 return 0; 3977 } 3978 3979 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 3980 struct kvm_enable_cap *cap) 3981 { 3982 int r; 3983 3984 if (cap->flags) 3985 return -EINVAL; 3986 3987 switch (cap->cap) { 3988 case KVM_CAP_DISABLE_QUIRKS: 3989 kvm->arch.disabled_quirks = cap->args[0]; 3990 r = 0; 3991 break; 3992 case KVM_CAP_SPLIT_IRQCHIP: { 3993 mutex_lock(&kvm->lock); 3994 r = -EINVAL; 3995 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 3996 goto split_irqchip_unlock; 3997 r = -EEXIST; 3998 if (irqchip_in_kernel(kvm)) 3999 goto split_irqchip_unlock; 4000 if (kvm->created_vcpus) 4001 goto split_irqchip_unlock; 4002 r = kvm_setup_empty_irq_routing(kvm); 4003 if (r) 4004 goto split_irqchip_unlock; 4005 /* Pairs with irqchip_in_kernel. */ 4006 smp_wmb(); 4007 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 4008 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 4009 r = 0; 4010 split_irqchip_unlock: 4011 mutex_unlock(&kvm->lock); 4012 break; 4013 } 4014 case KVM_CAP_X2APIC_API: 4015 r = -EINVAL; 4016 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 4017 break; 4018 4019 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 4020 kvm->arch.x2apic_format = true; 4021 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 4022 kvm->arch.x2apic_broadcast_quirk_disabled = true; 4023 4024 r = 0; 4025 break; 4026 default: 4027 r = -EINVAL; 4028 break; 4029 } 4030 return r; 4031 } 4032 4033 long kvm_arch_vm_ioctl(struct file *filp, 4034 unsigned int ioctl, unsigned long arg) 4035 { 4036 struct kvm *kvm = filp->private_data; 4037 void __user *argp = (void __user *)arg; 4038 int r = -ENOTTY; 4039 /* 4040 * This union makes it completely explicit to gcc-3.x 4041 * that these two variables' stack usage should be 4042 * combined, not added together. 4043 */ 4044 union { 4045 struct kvm_pit_state ps; 4046 struct kvm_pit_state2 ps2; 4047 struct kvm_pit_config pit_config; 4048 } u; 4049 4050 switch (ioctl) { 4051 case KVM_SET_TSS_ADDR: 4052 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 4053 break; 4054 case KVM_SET_IDENTITY_MAP_ADDR: { 4055 u64 ident_addr; 4056 4057 mutex_lock(&kvm->lock); 4058 r = -EINVAL; 4059 if (kvm->created_vcpus) 4060 goto set_identity_unlock; 4061 r = -EFAULT; 4062 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 4063 goto set_identity_unlock; 4064 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 4065 set_identity_unlock: 4066 mutex_unlock(&kvm->lock); 4067 break; 4068 } 4069 case KVM_SET_NR_MMU_PAGES: 4070 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 4071 break; 4072 case KVM_GET_NR_MMU_PAGES: 4073 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 4074 break; 4075 case KVM_CREATE_IRQCHIP: { 4076 mutex_lock(&kvm->lock); 4077 4078 r = -EEXIST; 4079 if (irqchip_in_kernel(kvm)) 4080 goto create_irqchip_unlock; 4081 4082 r = -EINVAL; 4083 if (kvm->created_vcpus) 4084 goto create_irqchip_unlock; 4085 4086 r = kvm_pic_init(kvm); 4087 if (r) 4088 goto create_irqchip_unlock; 4089 4090 r = kvm_ioapic_init(kvm); 4091 if (r) { 4092 kvm_pic_destroy(kvm); 4093 goto create_irqchip_unlock; 4094 } 4095 4096 r = kvm_setup_default_irq_routing(kvm); 4097 if (r) { 4098 kvm_ioapic_destroy(kvm); 4099 kvm_pic_destroy(kvm); 4100 goto create_irqchip_unlock; 4101 } 4102 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 4103 smp_wmb(); 4104 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 4105 create_irqchip_unlock: 4106 mutex_unlock(&kvm->lock); 4107 break; 4108 } 4109 case KVM_CREATE_PIT: 4110 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 4111 goto create_pit; 4112 case KVM_CREATE_PIT2: 4113 r = -EFAULT; 4114 if (copy_from_user(&u.pit_config, argp, 4115 sizeof(struct kvm_pit_config))) 4116 goto out; 4117 create_pit: 4118 mutex_lock(&kvm->lock); 4119 r = -EEXIST; 4120 if (kvm->arch.vpit) 4121 goto create_pit_unlock; 4122 r = -ENOMEM; 4123 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 4124 if (kvm->arch.vpit) 4125 r = 0; 4126 create_pit_unlock: 4127 mutex_unlock(&kvm->lock); 4128 break; 4129 case KVM_GET_IRQCHIP: { 4130 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4131 struct kvm_irqchip *chip; 4132 4133 chip = memdup_user(argp, sizeof(*chip)); 4134 if (IS_ERR(chip)) { 4135 r = PTR_ERR(chip); 4136 goto out; 4137 } 4138 4139 r = -ENXIO; 4140 if (!irqchip_kernel(kvm)) 4141 goto get_irqchip_out; 4142 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 4143 if (r) 4144 goto get_irqchip_out; 4145 r = -EFAULT; 4146 if (copy_to_user(argp, chip, sizeof *chip)) 4147 goto get_irqchip_out; 4148 r = 0; 4149 get_irqchip_out: 4150 kfree(chip); 4151 break; 4152 } 4153 case KVM_SET_IRQCHIP: { 4154 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4155 struct kvm_irqchip *chip; 4156 4157 chip = memdup_user(argp, sizeof(*chip)); 4158 if (IS_ERR(chip)) { 4159 r = PTR_ERR(chip); 4160 goto out; 4161 } 4162 4163 r = -ENXIO; 4164 if (!irqchip_kernel(kvm)) 4165 goto set_irqchip_out; 4166 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 4167 if (r) 4168 goto set_irqchip_out; 4169 r = 0; 4170 set_irqchip_out: 4171 kfree(chip); 4172 break; 4173 } 4174 case KVM_GET_PIT: { 4175 r = -EFAULT; 4176 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 4177 goto out; 4178 r = -ENXIO; 4179 if (!kvm->arch.vpit) 4180 goto out; 4181 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 4182 if (r) 4183 goto out; 4184 r = -EFAULT; 4185 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 4186 goto out; 4187 r = 0; 4188 break; 4189 } 4190 case KVM_SET_PIT: { 4191 r = -EFAULT; 4192 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 4193 goto out; 4194 r = -ENXIO; 4195 if (!kvm->arch.vpit) 4196 goto out; 4197 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 4198 break; 4199 } 4200 case KVM_GET_PIT2: { 4201 r = -ENXIO; 4202 if (!kvm->arch.vpit) 4203 goto out; 4204 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 4205 if (r) 4206 goto out; 4207 r = -EFAULT; 4208 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 4209 goto out; 4210 r = 0; 4211 break; 4212 } 4213 case KVM_SET_PIT2: { 4214 r = -EFAULT; 4215 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 4216 goto out; 4217 r = -ENXIO; 4218 if (!kvm->arch.vpit) 4219 goto out; 4220 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 4221 break; 4222 } 4223 case KVM_REINJECT_CONTROL: { 4224 struct kvm_reinject_control control; 4225 r = -EFAULT; 4226 if (copy_from_user(&control, argp, sizeof(control))) 4227 goto out; 4228 r = kvm_vm_ioctl_reinject(kvm, &control); 4229 break; 4230 } 4231 case KVM_SET_BOOT_CPU_ID: 4232 r = 0; 4233 mutex_lock(&kvm->lock); 4234 if (kvm->created_vcpus) 4235 r = -EBUSY; 4236 else 4237 kvm->arch.bsp_vcpu_id = arg; 4238 mutex_unlock(&kvm->lock); 4239 break; 4240 case KVM_XEN_HVM_CONFIG: { 4241 r = -EFAULT; 4242 if (copy_from_user(&kvm->arch.xen_hvm_config, argp, 4243 sizeof(struct kvm_xen_hvm_config))) 4244 goto out; 4245 r = -EINVAL; 4246 if (kvm->arch.xen_hvm_config.flags) 4247 goto out; 4248 r = 0; 4249 break; 4250 } 4251 case KVM_SET_CLOCK: { 4252 struct kvm_clock_data user_ns; 4253 u64 now_ns; 4254 4255 r = -EFAULT; 4256 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 4257 goto out; 4258 4259 r = -EINVAL; 4260 if (user_ns.flags) 4261 goto out; 4262 4263 r = 0; 4264 /* 4265 * TODO: userspace has to take care of races with VCPU_RUN, so 4266 * kvm_gen_update_masterclock() can be cut down to locked 4267 * pvclock_update_vm_gtod_copy(). 4268 */ 4269 kvm_gen_update_masterclock(kvm); 4270 now_ns = get_kvmclock_ns(kvm); 4271 kvm->arch.kvmclock_offset += user_ns.clock - now_ns; 4272 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); 4273 break; 4274 } 4275 case KVM_GET_CLOCK: { 4276 struct kvm_clock_data user_ns; 4277 u64 now_ns; 4278 4279 now_ns = get_kvmclock_ns(kvm); 4280 user_ns.clock = now_ns; 4281 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 4282 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 4283 4284 r = -EFAULT; 4285 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 4286 goto out; 4287 r = 0; 4288 break; 4289 } 4290 case KVM_ENABLE_CAP: { 4291 struct kvm_enable_cap cap; 4292 4293 r = -EFAULT; 4294 if (copy_from_user(&cap, argp, sizeof(cap))) 4295 goto out; 4296 r = kvm_vm_ioctl_enable_cap(kvm, &cap); 4297 break; 4298 } 4299 default: 4300 r = -ENOTTY; 4301 } 4302 out: 4303 return r; 4304 } 4305 4306 static void kvm_init_msr_list(void) 4307 { 4308 u32 dummy[2]; 4309 unsigned i, j; 4310 4311 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { 4312 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4313 continue; 4314 4315 /* 4316 * Even MSRs that are valid in the host may not be exposed 4317 * to the guests in some cases. 4318 */ 4319 switch (msrs_to_save[i]) { 4320 case MSR_IA32_BNDCFGS: 4321 if (!kvm_x86_ops->mpx_supported()) 4322 continue; 4323 break; 4324 case MSR_TSC_AUX: 4325 if (!kvm_x86_ops->rdtscp_supported()) 4326 continue; 4327 break; 4328 default: 4329 break; 4330 } 4331 4332 if (j < i) 4333 msrs_to_save[j] = msrs_to_save[i]; 4334 j++; 4335 } 4336 num_msrs_to_save = j; 4337 4338 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { 4339 switch (emulated_msrs[i]) { 4340 case MSR_IA32_SMBASE: 4341 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase()) 4342 continue; 4343 break; 4344 default: 4345 break; 4346 } 4347 4348 if (j < i) 4349 emulated_msrs[j] = emulated_msrs[i]; 4350 j++; 4351 } 4352 num_emulated_msrs = j; 4353 } 4354 4355 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 4356 const void *v) 4357 { 4358 int handled = 0; 4359 int n; 4360 4361 do { 4362 n = min(len, 8); 4363 if (!(lapic_in_kernel(vcpu) && 4364 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 4365 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 4366 break; 4367 handled += n; 4368 addr += n; 4369 len -= n; 4370 v += n; 4371 } while (len); 4372 4373 return handled; 4374 } 4375 4376 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4377 { 4378 int handled = 0; 4379 int n; 4380 4381 do { 4382 n = min(len, 8); 4383 if (!(lapic_in_kernel(vcpu) && 4384 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 4385 addr, n, v)) 4386 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 4387 break; 4388 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); 4389 handled += n; 4390 addr += n; 4391 len -= n; 4392 v += n; 4393 } while (len); 4394 4395 return handled; 4396 } 4397 4398 static void kvm_set_segment(struct kvm_vcpu *vcpu, 4399 struct kvm_segment *var, int seg) 4400 { 4401 kvm_x86_ops->set_segment(vcpu, var, seg); 4402 } 4403 4404 void kvm_get_segment(struct kvm_vcpu *vcpu, 4405 struct kvm_segment *var, int seg) 4406 { 4407 kvm_x86_ops->get_segment(vcpu, var, seg); 4408 } 4409 4410 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 4411 struct x86_exception *exception) 4412 { 4413 gpa_t t_gpa; 4414 4415 BUG_ON(!mmu_is_nested(vcpu)); 4416 4417 /* NPT walks are always user-walks */ 4418 access |= PFERR_USER_MASK; 4419 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); 4420 4421 return t_gpa; 4422 } 4423 4424 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 4425 struct x86_exception *exception) 4426 { 4427 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4428 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4429 } 4430 4431 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 4432 struct x86_exception *exception) 4433 { 4434 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4435 access |= PFERR_FETCH_MASK; 4436 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4437 } 4438 4439 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 4440 struct x86_exception *exception) 4441 { 4442 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4443 access |= PFERR_WRITE_MASK; 4444 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4445 } 4446 4447 /* uses this to access any guest's mapped memory without checking CPL */ 4448 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 4449 struct x86_exception *exception) 4450 { 4451 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 4452 } 4453 4454 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 4455 struct kvm_vcpu *vcpu, u32 access, 4456 struct x86_exception *exception) 4457 { 4458 void *data = val; 4459 int r = X86EMUL_CONTINUE; 4460 4461 while (bytes) { 4462 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 4463 exception); 4464 unsigned offset = addr & (PAGE_SIZE-1); 4465 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 4466 int ret; 4467 4468 if (gpa == UNMAPPED_GVA) 4469 return X86EMUL_PROPAGATE_FAULT; 4470 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 4471 offset, toread); 4472 if (ret < 0) { 4473 r = X86EMUL_IO_NEEDED; 4474 goto out; 4475 } 4476 4477 bytes -= toread; 4478 data += toread; 4479 addr += toread; 4480 } 4481 out: 4482 return r; 4483 } 4484 4485 /* used for instruction fetching */ 4486 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4487 gva_t addr, void *val, unsigned int bytes, 4488 struct x86_exception *exception) 4489 { 4490 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4491 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4492 unsigned offset; 4493 int ret; 4494 4495 /* Inline kvm_read_guest_virt_helper for speed. */ 4496 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 4497 exception); 4498 if (unlikely(gpa == UNMAPPED_GVA)) 4499 return X86EMUL_PROPAGATE_FAULT; 4500 4501 offset = addr & (PAGE_SIZE-1); 4502 if (WARN_ON(offset + bytes > PAGE_SIZE)) 4503 bytes = (unsigned)PAGE_SIZE - offset; 4504 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 4505 offset, bytes); 4506 if (unlikely(ret < 0)) 4507 return X86EMUL_IO_NEEDED; 4508 4509 return X86EMUL_CONTINUE; 4510 } 4511 4512 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4513 gva_t addr, void *val, unsigned int bytes, 4514 struct x86_exception *exception) 4515 { 4516 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4517 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4518 4519 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4520 exception); 4521 } 4522 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4523 4524 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4525 gva_t addr, void *val, unsigned int bytes, 4526 struct x86_exception *exception) 4527 { 4528 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4529 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4530 } 4531 4532 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 4533 unsigned long addr, void *val, unsigned int bytes) 4534 { 4535 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4536 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 4537 4538 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 4539 } 4540 4541 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4542 gva_t addr, void *val, 4543 unsigned int bytes, 4544 struct x86_exception *exception) 4545 { 4546 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4547 void *data = val; 4548 int r = X86EMUL_CONTINUE; 4549 4550 while (bytes) { 4551 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4552 PFERR_WRITE_MASK, 4553 exception); 4554 unsigned offset = addr & (PAGE_SIZE-1); 4555 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4556 int ret; 4557 4558 if (gpa == UNMAPPED_GVA) 4559 return X86EMUL_PROPAGATE_FAULT; 4560 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 4561 if (ret < 0) { 4562 r = X86EMUL_IO_NEEDED; 4563 goto out; 4564 } 4565 4566 bytes -= towrite; 4567 data += towrite; 4568 addr += towrite; 4569 } 4570 out: 4571 return r; 4572 } 4573 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4574 4575 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4576 gpa_t gpa, bool write) 4577 { 4578 /* For APIC access vmexit */ 4579 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4580 return 1; 4581 4582 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 4583 trace_vcpu_match_mmio(gva, gpa, write, true); 4584 return 1; 4585 } 4586 4587 return 0; 4588 } 4589 4590 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4591 gpa_t *gpa, struct x86_exception *exception, 4592 bool write) 4593 { 4594 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4595 | (write ? PFERR_WRITE_MASK : 0); 4596 4597 /* 4598 * currently PKRU is only applied to ept enabled guest so 4599 * there is no pkey in EPT page table for L1 guest or EPT 4600 * shadow page table for L2 guest. 4601 */ 4602 if (vcpu_match_mmio_gva(vcpu, gva) 4603 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4604 vcpu->arch.access, 0, access)) { 4605 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4606 (gva & (PAGE_SIZE - 1)); 4607 trace_vcpu_match_mmio(gva, *gpa, write, false); 4608 return 1; 4609 } 4610 4611 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4612 4613 if (*gpa == UNMAPPED_GVA) 4614 return -1; 4615 4616 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 4617 } 4618 4619 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4620 const void *val, int bytes) 4621 { 4622 int ret; 4623 4624 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 4625 if (ret < 0) 4626 return 0; 4627 kvm_page_track_write(vcpu, gpa, val, bytes); 4628 return 1; 4629 } 4630 4631 struct read_write_emulator_ops { 4632 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4633 int bytes); 4634 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4635 void *val, int bytes); 4636 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4637 int bytes, void *val); 4638 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4639 void *val, int bytes); 4640 bool write; 4641 }; 4642 4643 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4644 { 4645 if (vcpu->mmio_read_completed) { 4646 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4647 vcpu->mmio_fragments[0].gpa, *(u64 *)val); 4648 vcpu->mmio_read_completed = 0; 4649 return 1; 4650 } 4651 4652 return 0; 4653 } 4654 4655 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4656 void *val, int bytes) 4657 { 4658 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 4659 } 4660 4661 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4662 void *val, int bytes) 4663 { 4664 return emulator_write_phys(vcpu, gpa, val, bytes); 4665 } 4666 4667 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4668 { 4669 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); 4670 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4671 } 4672 4673 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4674 void *val, int bytes) 4675 { 4676 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); 4677 return X86EMUL_IO_NEEDED; 4678 } 4679 4680 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4681 void *val, int bytes) 4682 { 4683 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4684 4685 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4686 return X86EMUL_CONTINUE; 4687 } 4688 4689 static const struct read_write_emulator_ops read_emultor = { 4690 .read_write_prepare = read_prepare, 4691 .read_write_emulate = read_emulate, 4692 .read_write_mmio = vcpu_mmio_read, 4693 .read_write_exit_mmio = read_exit_mmio, 4694 }; 4695 4696 static const struct read_write_emulator_ops write_emultor = { 4697 .read_write_emulate = write_emulate, 4698 .read_write_mmio = write_mmio, 4699 .read_write_exit_mmio = write_exit_mmio, 4700 .write = true, 4701 }; 4702 4703 static int emulator_read_write_onepage(unsigned long addr, void *val, 4704 unsigned int bytes, 4705 struct x86_exception *exception, 4706 struct kvm_vcpu *vcpu, 4707 const struct read_write_emulator_ops *ops) 4708 { 4709 gpa_t gpa; 4710 int handled, ret; 4711 bool write = ops->write; 4712 struct kvm_mmio_fragment *frag; 4713 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 4714 4715 /* 4716 * If the exit was due to a NPF we may already have a GPA. 4717 * If the GPA is present, use it to avoid the GVA to GPA table walk. 4718 * Note, this cannot be used on string operations since string 4719 * operation using rep will only have the initial GPA from the NPF 4720 * occurred. 4721 */ 4722 if (vcpu->arch.gpa_available && 4723 emulator_can_use_gpa(ctxt) && 4724 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) { 4725 gpa = vcpu->arch.gpa_val; 4726 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 4727 } else { 4728 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 4729 if (ret < 0) 4730 return X86EMUL_PROPAGATE_FAULT; 4731 } 4732 4733 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 4734 return X86EMUL_CONTINUE; 4735 4736 /* 4737 * Is this MMIO handled locally? 4738 */ 4739 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 4740 if (handled == bytes) 4741 return X86EMUL_CONTINUE; 4742 4743 gpa += handled; 4744 bytes -= handled; 4745 val += handled; 4746 4747 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 4748 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 4749 frag->gpa = gpa; 4750 frag->data = val; 4751 frag->len = bytes; 4752 return X86EMUL_CONTINUE; 4753 } 4754 4755 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 4756 unsigned long addr, 4757 void *val, unsigned int bytes, 4758 struct x86_exception *exception, 4759 const struct read_write_emulator_ops *ops) 4760 { 4761 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4762 gpa_t gpa; 4763 int rc; 4764 4765 if (ops->read_write_prepare && 4766 ops->read_write_prepare(vcpu, val, bytes)) 4767 return X86EMUL_CONTINUE; 4768 4769 vcpu->mmio_nr_fragments = 0; 4770 4771 /* Crossing a page boundary? */ 4772 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 4773 int now; 4774 4775 now = -addr & ~PAGE_MASK; 4776 rc = emulator_read_write_onepage(addr, val, now, exception, 4777 vcpu, ops); 4778 4779 if (rc != X86EMUL_CONTINUE) 4780 return rc; 4781 addr += now; 4782 if (ctxt->mode != X86EMUL_MODE_PROT64) 4783 addr = (u32)addr; 4784 val += now; 4785 bytes -= now; 4786 } 4787 4788 rc = emulator_read_write_onepage(addr, val, bytes, exception, 4789 vcpu, ops); 4790 if (rc != X86EMUL_CONTINUE) 4791 return rc; 4792 4793 if (!vcpu->mmio_nr_fragments) 4794 return rc; 4795 4796 gpa = vcpu->mmio_fragments[0].gpa; 4797 4798 vcpu->mmio_needed = 1; 4799 vcpu->mmio_cur_fragment = 0; 4800 4801 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 4802 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 4803 vcpu->run->exit_reason = KVM_EXIT_MMIO; 4804 vcpu->run->mmio.phys_addr = gpa; 4805 4806 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 4807 } 4808 4809 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 4810 unsigned long addr, 4811 void *val, 4812 unsigned int bytes, 4813 struct x86_exception *exception) 4814 { 4815 return emulator_read_write(ctxt, addr, val, bytes, 4816 exception, &read_emultor); 4817 } 4818 4819 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 4820 unsigned long addr, 4821 const void *val, 4822 unsigned int bytes, 4823 struct x86_exception *exception) 4824 { 4825 return emulator_read_write(ctxt, addr, (void *)val, bytes, 4826 exception, &write_emultor); 4827 } 4828 4829 #define CMPXCHG_TYPE(t, ptr, old, new) \ 4830 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 4831 4832 #ifdef CONFIG_X86_64 4833 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 4834 #else 4835 # define CMPXCHG64(ptr, old, new) \ 4836 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 4837 #endif 4838 4839 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 4840 unsigned long addr, 4841 const void *old, 4842 const void *new, 4843 unsigned int bytes, 4844 struct x86_exception *exception) 4845 { 4846 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4847 gpa_t gpa; 4848 struct page *page; 4849 char *kaddr; 4850 bool exchanged; 4851 4852 /* guests cmpxchg8b have to be emulated atomically */ 4853 if (bytes > 8 || (bytes & (bytes - 1))) 4854 goto emul_write; 4855 4856 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 4857 4858 if (gpa == UNMAPPED_GVA || 4859 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4860 goto emul_write; 4861 4862 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 4863 goto emul_write; 4864 4865 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); 4866 if (is_error_page(page)) 4867 goto emul_write; 4868 4869 kaddr = kmap_atomic(page); 4870 kaddr += offset_in_page(gpa); 4871 switch (bytes) { 4872 case 1: 4873 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 4874 break; 4875 case 2: 4876 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 4877 break; 4878 case 4: 4879 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 4880 break; 4881 case 8: 4882 exchanged = CMPXCHG64(kaddr, old, new); 4883 break; 4884 default: 4885 BUG(); 4886 } 4887 kunmap_atomic(kaddr); 4888 kvm_release_page_dirty(page); 4889 4890 if (!exchanged) 4891 return X86EMUL_CMPXCHG_FAILED; 4892 4893 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 4894 kvm_page_track_write(vcpu, gpa, new, bytes); 4895 4896 return X86EMUL_CONTINUE; 4897 4898 emul_write: 4899 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 4900 4901 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 4902 } 4903 4904 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 4905 { 4906 int r = 0, i; 4907 4908 for (i = 0; i < vcpu->arch.pio.count; i++) { 4909 if (vcpu->arch.pio.in) 4910 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 4911 vcpu->arch.pio.size, pd); 4912 else 4913 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 4914 vcpu->arch.pio.port, vcpu->arch.pio.size, 4915 pd); 4916 if (r) 4917 break; 4918 pd += vcpu->arch.pio.size; 4919 } 4920 return r; 4921 } 4922 4923 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 4924 unsigned short port, void *val, 4925 unsigned int count, bool in) 4926 { 4927 vcpu->arch.pio.port = port; 4928 vcpu->arch.pio.in = in; 4929 vcpu->arch.pio.count = count; 4930 vcpu->arch.pio.size = size; 4931 4932 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 4933 vcpu->arch.pio.count = 0; 4934 return 1; 4935 } 4936 4937 vcpu->run->exit_reason = KVM_EXIT_IO; 4938 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 4939 vcpu->run->io.size = size; 4940 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 4941 vcpu->run->io.count = count; 4942 vcpu->run->io.port = port; 4943 4944 return 0; 4945 } 4946 4947 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 4948 int size, unsigned short port, void *val, 4949 unsigned int count) 4950 { 4951 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4952 int ret; 4953 4954 if (vcpu->arch.pio.count) 4955 goto data_avail; 4956 4957 memset(vcpu->arch.pio_data, 0, size * count); 4958 4959 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 4960 if (ret) { 4961 data_avail: 4962 memcpy(val, vcpu->arch.pio_data, size * count); 4963 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 4964 vcpu->arch.pio.count = 0; 4965 return 1; 4966 } 4967 4968 return 0; 4969 } 4970 4971 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 4972 int size, unsigned short port, 4973 const void *val, unsigned int count) 4974 { 4975 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4976 4977 memcpy(vcpu->arch.pio_data, val, size * count); 4978 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 4979 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 4980 } 4981 4982 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 4983 { 4984 return kvm_x86_ops->get_segment_base(vcpu, seg); 4985 } 4986 4987 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 4988 { 4989 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 4990 } 4991 4992 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 4993 { 4994 if (!need_emulate_wbinvd(vcpu)) 4995 return X86EMUL_CONTINUE; 4996 4997 if (kvm_x86_ops->has_wbinvd_exit()) { 4998 int cpu = get_cpu(); 4999 5000 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 5001 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 5002 wbinvd_ipi, NULL, 1); 5003 put_cpu(); 5004 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 5005 } else 5006 wbinvd(); 5007 return X86EMUL_CONTINUE; 5008 } 5009 5010 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 5011 { 5012 kvm_emulate_wbinvd_noskip(vcpu); 5013 return kvm_skip_emulated_instruction(vcpu); 5014 } 5015 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 5016 5017 5018 5019 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 5020 { 5021 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 5022 } 5023 5024 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 5025 unsigned long *dest) 5026 { 5027 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 5028 } 5029 5030 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 5031 unsigned long value) 5032 { 5033 5034 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 5035 } 5036 5037 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 5038 { 5039 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 5040 } 5041 5042 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 5043 { 5044 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5045 unsigned long value; 5046 5047 switch (cr) { 5048 case 0: 5049 value = kvm_read_cr0(vcpu); 5050 break; 5051 case 2: 5052 value = vcpu->arch.cr2; 5053 break; 5054 case 3: 5055 value = kvm_read_cr3(vcpu); 5056 break; 5057 case 4: 5058 value = kvm_read_cr4(vcpu); 5059 break; 5060 case 8: 5061 value = kvm_get_cr8(vcpu); 5062 break; 5063 default: 5064 kvm_err("%s: unexpected cr %u\n", __func__, cr); 5065 return 0; 5066 } 5067 5068 return value; 5069 } 5070 5071 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 5072 { 5073 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5074 int res = 0; 5075 5076 switch (cr) { 5077 case 0: 5078 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 5079 break; 5080 case 2: 5081 vcpu->arch.cr2 = val; 5082 break; 5083 case 3: 5084 res = kvm_set_cr3(vcpu, val); 5085 break; 5086 case 4: 5087 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 5088 break; 5089 case 8: 5090 res = kvm_set_cr8(vcpu, val); 5091 break; 5092 default: 5093 kvm_err("%s: unexpected cr %u\n", __func__, cr); 5094 res = -1; 5095 } 5096 5097 return res; 5098 } 5099 5100 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 5101 { 5102 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 5103 } 5104 5105 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5106 { 5107 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 5108 } 5109 5110 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5111 { 5112 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 5113 } 5114 5115 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5116 { 5117 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 5118 } 5119 5120 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5121 { 5122 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 5123 } 5124 5125 static unsigned long emulator_get_cached_segment_base( 5126 struct x86_emulate_ctxt *ctxt, int seg) 5127 { 5128 return get_segment_base(emul_to_vcpu(ctxt), seg); 5129 } 5130 5131 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 5132 struct desc_struct *desc, u32 *base3, 5133 int seg) 5134 { 5135 struct kvm_segment var; 5136 5137 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 5138 *selector = var.selector; 5139 5140 if (var.unusable) { 5141 memset(desc, 0, sizeof(*desc)); 5142 if (base3) 5143 *base3 = 0; 5144 return false; 5145 } 5146 5147 if (var.g) 5148 var.limit >>= 12; 5149 set_desc_limit(desc, var.limit); 5150 set_desc_base(desc, (unsigned long)var.base); 5151 #ifdef CONFIG_X86_64 5152 if (base3) 5153 *base3 = var.base >> 32; 5154 #endif 5155 desc->type = var.type; 5156 desc->s = var.s; 5157 desc->dpl = var.dpl; 5158 desc->p = var.present; 5159 desc->avl = var.avl; 5160 desc->l = var.l; 5161 desc->d = var.db; 5162 desc->g = var.g; 5163 5164 return true; 5165 } 5166 5167 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 5168 struct desc_struct *desc, u32 base3, 5169 int seg) 5170 { 5171 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5172 struct kvm_segment var; 5173 5174 var.selector = selector; 5175 var.base = get_desc_base(desc); 5176 #ifdef CONFIG_X86_64 5177 var.base |= ((u64)base3) << 32; 5178 #endif 5179 var.limit = get_desc_limit(desc); 5180 if (desc->g) 5181 var.limit = (var.limit << 12) | 0xfff; 5182 var.type = desc->type; 5183 var.dpl = desc->dpl; 5184 var.db = desc->d; 5185 var.s = desc->s; 5186 var.l = desc->l; 5187 var.g = desc->g; 5188 var.avl = desc->avl; 5189 var.present = desc->p; 5190 var.unusable = !var.present; 5191 var.padding = 0; 5192 5193 kvm_set_segment(vcpu, &var, seg); 5194 return; 5195 } 5196 5197 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 5198 u32 msr_index, u64 *pdata) 5199 { 5200 struct msr_data msr; 5201 int r; 5202 5203 msr.index = msr_index; 5204 msr.host_initiated = false; 5205 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); 5206 if (r) 5207 return r; 5208 5209 *pdata = msr.data; 5210 return 0; 5211 } 5212 5213 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 5214 u32 msr_index, u64 data) 5215 { 5216 struct msr_data msr; 5217 5218 msr.data = data; 5219 msr.index = msr_index; 5220 msr.host_initiated = false; 5221 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 5222 } 5223 5224 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 5225 { 5226 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5227 5228 return vcpu->arch.smbase; 5229 } 5230 5231 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 5232 { 5233 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5234 5235 vcpu->arch.smbase = smbase; 5236 } 5237 5238 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 5239 u32 pmc) 5240 { 5241 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); 5242 } 5243 5244 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 5245 u32 pmc, u64 *pdata) 5246 { 5247 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 5248 } 5249 5250 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 5251 { 5252 emul_to_vcpu(ctxt)->arch.halt_request = 1; 5253 } 5254 5255 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) 5256 { 5257 preempt_disable(); 5258 kvm_load_guest_fpu(emul_to_vcpu(ctxt)); 5259 } 5260 5261 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) 5262 { 5263 preempt_enable(); 5264 } 5265 5266 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 5267 struct x86_instruction_info *info, 5268 enum x86_intercept_stage stage) 5269 { 5270 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 5271 } 5272 5273 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 5274 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit) 5275 { 5276 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit); 5277 } 5278 5279 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 5280 { 5281 return kvm_register_read(emul_to_vcpu(ctxt), reg); 5282 } 5283 5284 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 5285 { 5286 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 5287 } 5288 5289 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 5290 { 5291 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 5292 } 5293 5294 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 5295 { 5296 return emul_to_vcpu(ctxt)->arch.hflags; 5297 } 5298 5299 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) 5300 { 5301 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags); 5302 } 5303 5304 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase) 5305 { 5306 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase); 5307 } 5308 5309 static const struct x86_emulate_ops emulate_ops = { 5310 .read_gpr = emulator_read_gpr, 5311 .write_gpr = emulator_write_gpr, 5312 .read_std = kvm_read_guest_virt_system, 5313 .write_std = kvm_write_guest_virt_system, 5314 .read_phys = kvm_read_guest_phys_system, 5315 .fetch = kvm_fetch_guest_virt, 5316 .read_emulated = emulator_read_emulated, 5317 .write_emulated = emulator_write_emulated, 5318 .cmpxchg_emulated = emulator_cmpxchg_emulated, 5319 .invlpg = emulator_invlpg, 5320 .pio_in_emulated = emulator_pio_in_emulated, 5321 .pio_out_emulated = emulator_pio_out_emulated, 5322 .get_segment = emulator_get_segment, 5323 .set_segment = emulator_set_segment, 5324 .get_cached_segment_base = emulator_get_cached_segment_base, 5325 .get_gdt = emulator_get_gdt, 5326 .get_idt = emulator_get_idt, 5327 .set_gdt = emulator_set_gdt, 5328 .set_idt = emulator_set_idt, 5329 .get_cr = emulator_get_cr, 5330 .set_cr = emulator_set_cr, 5331 .cpl = emulator_get_cpl, 5332 .get_dr = emulator_get_dr, 5333 .set_dr = emulator_set_dr, 5334 .get_smbase = emulator_get_smbase, 5335 .set_smbase = emulator_set_smbase, 5336 .set_msr = emulator_set_msr, 5337 .get_msr = emulator_get_msr, 5338 .check_pmc = emulator_check_pmc, 5339 .read_pmc = emulator_read_pmc, 5340 .halt = emulator_halt, 5341 .wbinvd = emulator_wbinvd, 5342 .fix_hypercall = emulator_fix_hypercall, 5343 .get_fpu = emulator_get_fpu, 5344 .put_fpu = emulator_put_fpu, 5345 .intercept = emulator_intercept, 5346 .get_cpuid = emulator_get_cpuid, 5347 .set_nmi_mask = emulator_set_nmi_mask, 5348 .get_hflags = emulator_get_hflags, 5349 .set_hflags = emulator_set_hflags, 5350 .pre_leave_smm = emulator_pre_leave_smm, 5351 }; 5352 5353 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 5354 { 5355 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 5356 /* 5357 * an sti; sti; sequence only disable interrupts for the first 5358 * instruction. So, if the last instruction, be it emulated or 5359 * not, left the system with the INT_STI flag enabled, it 5360 * means that the last instruction is an sti. We should not 5361 * leave the flag on in this case. The same goes for mov ss 5362 */ 5363 if (int_shadow & mask) 5364 mask = 0; 5365 if (unlikely(int_shadow || mask)) { 5366 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 5367 if (!mask) 5368 kvm_make_request(KVM_REQ_EVENT, vcpu); 5369 } 5370 } 5371 5372 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 5373 { 5374 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5375 if (ctxt->exception.vector == PF_VECTOR) 5376 return kvm_propagate_fault(vcpu, &ctxt->exception); 5377 5378 if (ctxt->exception.error_code_valid) 5379 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 5380 ctxt->exception.error_code); 5381 else 5382 kvm_queue_exception(vcpu, ctxt->exception.vector); 5383 return false; 5384 } 5385 5386 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 5387 { 5388 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5389 int cs_db, cs_l; 5390 5391 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 5392 5393 ctxt->eflags = kvm_get_rflags(vcpu); 5394 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 5395 5396 ctxt->eip = kvm_rip_read(vcpu); 5397 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 5398 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 5399 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 5400 cs_db ? X86EMUL_MODE_PROT32 : 5401 X86EMUL_MODE_PROT16; 5402 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 5403 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 5404 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 5405 5406 init_decode_cache(ctxt); 5407 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5408 } 5409 5410 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 5411 { 5412 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5413 int ret; 5414 5415 init_emulate_ctxt(vcpu); 5416 5417 ctxt->op_bytes = 2; 5418 ctxt->ad_bytes = 2; 5419 ctxt->_eip = ctxt->eip + inc_eip; 5420 ret = emulate_int_real(ctxt, irq); 5421 5422 if (ret != X86EMUL_CONTINUE) 5423 return EMULATE_FAIL; 5424 5425 ctxt->eip = ctxt->_eip; 5426 kvm_rip_write(vcpu, ctxt->eip); 5427 kvm_set_rflags(vcpu, ctxt->eflags); 5428 5429 if (irq == NMI_VECTOR) 5430 vcpu->arch.nmi_pending = 0; 5431 else 5432 vcpu->arch.interrupt.pending = false; 5433 5434 return EMULATE_DONE; 5435 } 5436 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 5437 5438 static int handle_emulation_failure(struct kvm_vcpu *vcpu) 5439 { 5440 int r = EMULATE_DONE; 5441 5442 ++vcpu->stat.insn_emulation_fail; 5443 trace_kvm_emulate_insn_failed(vcpu); 5444 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 5445 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5446 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 5447 vcpu->run->internal.ndata = 0; 5448 r = EMULATE_USER_EXIT; 5449 } 5450 kvm_queue_exception(vcpu, UD_VECTOR); 5451 5452 return r; 5453 } 5454 5455 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 5456 bool write_fault_to_shadow_pgtable, 5457 int emulation_type) 5458 { 5459 gpa_t gpa = cr2; 5460 kvm_pfn_t pfn; 5461 5462 if (emulation_type & EMULTYPE_NO_REEXECUTE) 5463 return false; 5464 5465 if (!vcpu->arch.mmu.direct_map) { 5466 /* 5467 * Write permission should be allowed since only 5468 * write access need to be emulated. 5469 */ 5470 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5471 5472 /* 5473 * If the mapping is invalid in guest, let cpu retry 5474 * it to generate fault. 5475 */ 5476 if (gpa == UNMAPPED_GVA) 5477 return true; 5478 } 5479 5480 /* 5481 * Do not retry the unhandleable instruction if it faults on the 5482 * readonly host memory, otherwise it will goto a infinite loop: 5483 * retry instruction -> write #PF -> emulation fail -> retry 5484 * instruction -> ... 5485 */ 5486 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 5487 5488 /* 5489 * If the instruction failed on the error pfn, it can not be fixed, 5490 * report the error to userspace. 5491 */ 5492 if (is_error_noslot_pfn(pfn)) 5493 return false; 5494 5495 kvm_release_pfn_clean(pfn); 5496 5497 /* The instructions are well-emulated on direct mmu. */ 5498 if (vcpu->arch.mmu.direct_map) { 5499 unsigned int indirect_shadow_pages; 5500 5501 spin_lock(&vcpu->kvm->mmu_lock); 5502 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 5503 spin_unlock(&vcpu->kvm->mmu_lock); 5504 5505 if (indirect_shadow_pages) 5506 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5507 5508 return true; 5509 } 5510 5511 /* 5512 * if emulation was due to access to shadowed page table 5513 * and it failed try to unshadow page and re-enter the 5514 * guest to let CPU execute the instruction. 5515 */ 5516 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5517 5518 /* 5519 * If the access faults on its page table, it can not 5520 * be fixed by unprotecting shadow page and it should 5521 * be reported to userspace. 5522 */ 5523 return !write_fault_to_shadow_pgtable; 5524 } 5525 5526 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5527 unsigned long cr2, int emulation_type) 5528 { 5529 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5530 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5531 5532 last_retry_eip = vcpu->arch.last_retry_eip; 5533 last_retry_addr = vcpu->arch.last_retry_addr; 5534 5535 /* 5536 * If the emulation is caused by #PF and it is non-page_table 5537 * writing instruction, it means the VM-EXIT is caused by shadow 5538 * page protected, we can zap the shadow page and retry this 5539 * instruction directly. 5540 * 5541 * Note: if the guest uses a non-page-table modifying instruction 5542 * on the PDE that points to the instruction, then we will unmap 5543 * the instruction and go to an infinite loop. So, we cache the 5544 * last retried eip and the last fault address, if we meet the eip 5545 * and the address again, we can break out of the potential infinite 5546 * loop. 5547 */ 5548 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5549 5550 if (!(emulation_type & EMULTYPE_RETRY)) 5551 return false; 5552 5553 if (x86_page_table_writing_insn(ctxt)) 5554 return false; 5555 5556 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5557 return false; 5558 5559 vcpu->arch.last_retry_eip = ctxt->eip; 5560 vcpu->arch.last_retry_addr = cr2; 5561 5562 if (!vcpu->arch.mmu.direct_map) 5563 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5564 5565 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5566 5567 return true; 5568 } 5569 5570 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5571 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5572 5573 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 5574 { 5575 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 5576 /* This is a good place to trace that we are exiting SMM. */ 5577 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 5578 5579 /* Process a latched INIT or SMI, if any. */ 5580 kvm_make_request(KVM_REQ_EVENT, vcpu); 5581 } 5582 5583 kvm_mmu_reset_context(vcpu); 5584 } 5585 5586 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) 5587 { 5588 unsigned changed = vcpu->arch.hflags ^ emul_flags; 5589 5590 vcpu->arch.hflags = emul_flags; 5591 5592 if (changed & HF_SMM_MASK) 5593 kvm_smm_changed(vcpu); 5594 } 5595 5596 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5597 unsigned long *db) 5598 { 5599 u32 dr6 = 0; 5600 int i; 5601 u32 enable, rwlen; 5602 5603 enable = dr7; 5604 rwlen = dr7 >> 16; 5605 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5606 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5607 dr6 |= (1 << i); 5608 return dr6; 5609 } 5610 5611 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r) 5612 { 5613 struct kvm_run *kvm_run = vcpu->run; 5614 5615 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5616 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; 5617 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5618 kvm_run->debug.arch.exception = DB_VECTOR; 5619 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5620 *r = EMULATE_USER_EXIT; 5621 } else { 5622 /* 5623 * "Certain debug exceptions may clear bit 0-3. The 5624 * remaining contents of the DR6 register are never 5625 * cleared by the processor". 5626 */ 5627 vcpu->arch.dr6 &= ~15; 5628 vcpu->arch.dr6 |= DR6_BS | DR6_RTM; 5629 kvm_queue_exception(vcpu, DB_VECTOR); 5630 } 5631 } 5632 5633 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 5634 { 5635 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5636 int r = EMULATE_DONE; 5637 5638 kvm_x86_ops->skip_emulated_instruction(vcpu); 5639 5640 /* 5641 * rflags is the old, "raw" value of the flags. The new value has 5642 * not been saved yet. 5643 * 5644 * This is correct even for TF set by the guest, because "the 5645 * processor will not generate this exception after the instruction 5646 * that sets the TF flag". 5647 */ 5648 if (unlikely(rflags & X86_EFLAGS_TF)) 5649 kvm_vcpu_do_singlestep(vcpu, &r); 5650 return r == EMULATE_DONE; 5651 } 5652 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 5653 5654 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5655 { 5656 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5657 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5658 struct kvm_run *kvm_run = vcpu->run; 5659 unsigned long eip = kvm_get_linear_rip(vcpu); 5660 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5661 vcpu->arch.guest_debug_dr7, 5662 vcpu->arch.eff_db); 5663 5664 if (dr6 != 0) { 5665 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 5666 kvm_run->debug.arch.pc = eip; 5667 kvm_run->debug.arch.exception = DB_VECTOR; 5668 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5669 *r = EMULATE_USER_EXIT; 5670 return true; 5671 } 5672 } 5673 5674 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 5675 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 5676 unsigned long eip = kvm_get_linear_rip(vcpu); 5677 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5678 vcpu->arch.dr7, 5679 vcpu->arch.db); 5680 5681 if (dr6 != 0) { 5682 vcpu->arch.dr6 &= ~15; 5683 vcpu->arch.dr6 |= dr6 | DR6_RTM; 5684 kvm_queue_exception(vcpu, DB_VECTOR); 5685 *r = EMULATE_DONE; 5686 return true; 5687 } 5688 } 5689 5690 return false; 5691 } 5692 5693 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 5694 unsigned long cr2, 5695 int emulation_type, 5696 void *insn, 5697 int insn_len) 5698 { 5699 int r; 5700 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5701 bool writeback = true; 5702 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 5703 5704 /* 5705 * Clear write_fault_to_shadow_pgtable here to ensure it is 5706 * never reused. 5707 */ 5708 vcpu->arch.write_fault_to_shadow_pgtable = false; 5709 kvm_clear_exception_queue(vcpu); 5710 5711 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 5712 init_emulate_ctxt(vcpu); 5713 5714 /* 5715 * We will reenter on the same instruction since 5716 * we do not set complete_userspace_io. This does not 5717 * handle watchpoints yet, those would be handled in 5718 * the emulate_ops. 5719 */ 5720 if (kvm_vcpu_check_breakpoint(vcpu, &r)) 5721 return r; 5722 5723 ctxt->interruptibility = 0; 5724 ctxt->have_exception = false; 5725 ctxt->exception.vector = -1; 5726 ctxt->perm_ok = false; 5727 5728 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 5729 5730 r = x86_decode_insn(ctxt, insn, insn_len); 5731 5732 trace_kvm_emulate_insn_start(vcpu); 5733 ++vcpu->stat.insn_emulation; 5734 if (r != EMULATION_OK) { 5735 if (emulation_type & EMULTYPE_TRAP_UD) 5736 return EMULATE_FAIL; 5737 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5738 emulation_type)) 5739 return EMULATE_DONE; 5740 if (ctxt->have_exception && inject_emulated_exception(vcpu)) 5741 return EMULATE_DONE; 5742 if (emulation_type & EMULTYPE_SKIP) 5743 return EMULATE_FAIL; 5744 return handle_emulation_failure(vcpu); 5745 } 5746 } 5747 5748 if (emulation_type & EMULTYPE_SKIP) { 5749 kvm_rip_write(vcpu, ctxt->_eip); 5750 if (ctxt->eflags & X86_EFLAGS_RF) 5751 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 5752 return EMULATE_DONE; 5753 } 5754 5755 if (retry_instruction(ctxt, cr2, emulation_type)) 5756 return EMULATE_DONE; 5757 5758 /* this is needed for vmware backdoor interface to work since it 5759 changes registers values during IO operation */ 5760 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 5761 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5762 emulator_invalidate_register_cache(ctxt); 5763 } 5764 5765 restart: 5766 /* Save the faulting GPA (cr2) in the address field */ 5767 ctxt->exception.address = cr2; 5768 5769 r = x86_emulate_insn(ctxt); 5770 5771 if (r == EMULATION_INTERCEPTED) 5772 return EMULATE_DONE; 5773 5774 if (r == EMULATION_FAILED) { 5775 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5776 emulation_type)) 5777 return EMULATE_DONE; 5778 5779 return handle_emulation_failure(vcpu); 5780 } 5781 5782 if (ctxt->have_exception) { 5783 r = EMULATE_DONE; 5784 if (inject_emulated_exception(vcpu)) 5785 return r; 5786 } else if (vcpu->arch.pio.count) { 5787 if (!vcpu->arch.pio.in) { 5788 /* FIXME: return into emulator if single-stepping. */ 5789 vcpu->arch.pio.count = 0; 5790 } else { 5791 writeback = false; 5792 vcpu->arch.complete_userspace_io = complete_emulated_pio; 5793 } 5794 r = EMULATE_USER_EXIT; 5795 } else if (vcpu->mmio_needed) { 5796 if (!vcpu->mmio_is_write) 5797 writeback = false; 5798 r = EMULATE_USER_EXIT; 5799 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 5800 } else if (r == EMULATION_RESTART) 5801 goto restart; 5802 else 5803 r = EMULATE_DONE; 5804 5805 if (writeback) { 5806 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5807 toggle_interruptibility(vcpu, ctxt->interruptibility); 5808 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 5809 kvm_rip_write(vcpu, ctxt->eip); 5810 if (r == EMULATE_DONE && 5811 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 5812 kvm_vcpu_do_singlestep(vcpu, &r); 5813 if (!ctxt->have_exception || 5814 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 5815 __kvm_set_rflags(vcpu, ctxt->eflags); 5816 5817 /* 5818 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 5819 * do nothing, and it will be requested again as soon as 5820 * the shadow expires. But we still need to check here, 5821 * because POPF has no interrupt shadow. 5822 */ 5823 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 5824 kvm_make_request(KVM_REQ_EVENT, vcpu); 5825 } else 5826 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 5827 5828 return r; 5829 } 5830 EXPORT_SYMBOL_GPL(x86_emulate_instruction); 5831 5832 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) 5833 { 5834 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 5835 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 5836 size, port, &val, 1); 5837 /* do not return to emulator after return from userspace */ 5838 vcpu->arch.pio.count = 0; 5839 return ret; 5840 } 5841 EXPORT_SYMBOL_GPL(kvm_fast_pio_out); 5842 5843 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 5844 { 5845 unsigned long val; 5846 5847 /* We should only ever be called with arch.pio.count equal to 1 */ 5848 BUG_ON(vcpu->arch.pio.count != 1); 5849 5850 /* For size less than 4 we merge, else we zero extend */ 5851 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) 5852 : 0; 5853 5854 /* 5855 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform 5856 * the copy and tracing 5857 */ 5858 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size, 5859 vcpu->arch.pio.port, &val, 1); 5860 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 5861 5862 return 1; 5863 } 5864 5865 int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port) 5866 { 5867 unsigned long val; 5868 int ret; 5869 5870 /* For size less than 4 we merge, else we zero extend */ 5871 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0; 5872 5873 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port, 5874 &val, 1); 5875 if (ret) { 5876 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 5877 return ret; 5878 } 5879 5880 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 5881 5882 return 0; 5883 } 5884 EXPORT_SYMBOL_GPL(kvm_fast_pio_in); 5885 5886 static int kvmclock_cpu_down_prep(unsigned int cpu) 5887 { 5888 __this_cpu_write(cpu_tsc_khz, 0); 5889 return 0; 5890 } 5891 5892 static void tsc_khz_changed(void *data) 5893 { 5894 struct cpufreq_freqs *freq = data; 5895 unsigned long khz = 0; 5896 5897 if (data) 5898 khz = freq->new; 5899 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5900 khz = cpufreq_quick_get(raw_smp_processor_id()); 5901 if (!khz) 5902 khz = tsc_khz; 5903 __this_cpu_write(cpu_tsc_khz, khz); 5904 } 5905 5906 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 5907 void *data) 5908 { 5909 struct cpufreq_freqs *freq = data; 5910 struct kvm *kvm; 5911 struct kvm_vcpu *vcpu; 5912 int i, send_ipi = 0; 5913 5914 /* 5915 * We allow guests to temporarily run on slowing clocks, 5916 * provided we notify them after, or to run on accelerating 5917 * clocks, provided we notify them before. Thus time never 5918 * goes backwards. 5919 * 5920 * However, we have a problem. We can't atomically update 5921 * the frequency of a given CPU from this function; it is 5922 * merely a notifier, which can be called from any CPU. 5923 * Changing the TSC frequency at arbitrary points in time 5924 * requires a recomputation of local variables related to 5925 * the TSC for each VCPU. We must flag these local variables 5926 * to be updated and be sure the update takes place with the 5927 * new frequency before any guests proceed. 5928 * 5929 * Unfortunately, the combination of hotplug CPU and frequency 5930 * change creates an intractable locking scenario; the order 5931 * of when these callouts happen is undefined with respect to 5932 * CPU hotplug, and they can race with each other. As such, 5933 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 5934 * undefined; you can actually have a CPU frequency change take 5935 * place in between the computation of X and the setting of the 5936 * variable. To protect against this problem, all updates of 5937 * the per_cpu tsc_khz variable are done in an interrupt 5938 * protected IPI, and all callers wishing to update the value 5939 * must wait for a synchronous IPI to complete (which is trivial 5940 * if the caller is on the CPU already). This establishes the 5941 * necessary total order on variable updates. 5942 * 5943 * Note that because a guest time update may take place 5944 * anytime after the setting of the VCPU's request bit, the 5945 * correct TSC value must be set before the request. However, 5946 * to ensure the update actually makes it to any guest which 5947 * starts running in hardware virtualization between the set 5948 * and the acquisition of the spinlock, we must also ping the 5949 * CPU after setting the request bit. 5950 * 5951 */ 5952 5953 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 5954 return 0; 5955 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 5956 return 0; 5957 5958 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5959 5960 spin_lock(&kvm_lock); 5961 list_for_each_entry(kvm, &vm_list, vm_list) { 5962 kvm_for_each_vcpu(i, vcpu, kvm) { 5963 if (vcpu->cpu != freq->cpu) 5964 continue; 5965 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5966 if (vcpu->cpu != smp_processor_id()) 5967 send_ipi = 1; 5968 } 5969 } 5970 spin_unlock(&kvm_lock); 5971 5972 if (freq->old < freq->new && send_ipi) { 5973 /* 5974 * We upscale the frequency. Must make the guest 5975 * doesn't see old kvmclock values while running with 5976 * the new frequency, otherwise we risk the guest sees 5977 * time go backwards. 5978 * 5979 * In case we update the frequency for another cpu 5980 * (which might be in guest context) send an interrupt 5981 * to kick the cpu out of guest context. Next time 5982 * guest context is entered kvmclock will be updated, 5983 * so the guest will not see stale values. 5984 */ 5985 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5986 } 5987 return 0; 5988 } 5989 5990 static struct notifier_block kvmclock_cpufreq_notifier_block = { 5991 .notifier_call = kvmclock_cpufreq_notifier 5992 }; 5993 5994 static int kvmclock_cpu_online(unsigned int cpu) 5995 { 5996 tsc_khz_changed(NULL); 5997 return 0; 5998 } 5999 6000 static void kvm_timer_init(void) 6001 { 6002 max_tsc_khz = tsc_khz; 6003 6004 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 6005 #ifdef CONFIG_CPU_FREQ 6006 struct cpufreq_policy policy; 6007 int cpu; 6008 6009 memset(&policy, 0, sizeof(policy)); 6010 cpu = get_cpu(); 6011 cpufreq_get_policy(&policy, cpu); 6012 if (policy.cpuinfo.max_freq) 6013 max_tsc_khz = policy.cpuinfo.max_freq; 6014 put_cpu(); 6015 #endif 6016 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 6017 CPUFREQ_TRANSITION_NOTIFIER); 6018 } 6019 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 6020 6021 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 6022 kvmclock_cpu_online, kvmclock_cpu_down_prep); 6023 } 6024 6025 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 6026 6027 int kvm_is_in_guest(void) 6028 { 6029 return __this_cpu_read(current_vcpu) != NULL; 6030 } 6031 6032 static int kvm_is_user_mode(void) 6033 { 6034 int user_mode = 3; 6035 6036 if (__this_cpu_read(current_vcpu)) 6037 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 6038 6039 return user_mode != 0; 6040 } 6041 6042 static unsigned long kvm_get_guest_ip(void) 6043 { 6044 unsigned long ip = 0; 6045 6046 if (__this_cpu_read(current_vcpu)) 6047 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 6048 6049 return ip; 6050 } 6051 6052 static struct perf_guest_info_callbacks kvm_guest_cbs = { 6053 .is_in_guest = kvm_is_in_guest, 6054 .is_user_mode = kvm_is_user_mode, 6055 .get_guest_ip = kvm_get_guest_ip, 6056 }; 6057 6058 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) 6059 { 6060 __this_cpu_write(current_vcpu, vcpu); 6061 } 6062 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); 6063 6064 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) 6065 { 6066 __this_cpu_write(current_vcpu, NULL); 6067 } 6068 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); 6069 6070 static void kvm_set_mmio_spte_mask(void) 6071 { 6072 u64 mask; 6073 int maxphyaddr = boot_cpu_data.x86_phys_bits; 6074 6075 /* 6076 * Set the reserved bits and the present bit of an paging-structure 6077 * entry to generate page fault with PFER.RSV = 1. 6078 */ 6079 /* Mask the reserved physical address bits. */ 6080 mask = rsvd_bits(maxphyaddr, 51); 6081 6082 /* Set the present bit. */ 6083 mask |= 1ull; 6084 6085 #ifdef CONFIG_X86_64 6086 /* 6087 * If reserved bit is not supported, clear the present bit to disable 6088 * mmio page fault. 6089 */ 6090 if (maxphyaddr == 52) 6091 mask &= ~1ull; 6092 #endif 6093 6094 kvm_mmu_set_mmio_spte_mask(mask, mask); 6095 } 6096 6097 #ifdef CONFIG_X86_64 6098 static void pvclock_gtod_update_fn(struct work_struct *work) 6099 { 6100 struct kvm *kvm; 6101 6102 struct kvm_vcpu *vcpu; 6103 int i; 6104 6105 spin_lock(&kvm_lock); 6106 list_for_each_entry(kvm, &vm_list, vm_list) 6107 kvm_for_each_vcpu(i, vcpu, kvm) 6108 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 6109 atomic_set(&kvm_guest_has_master_clock, 0); 6110 spin_unlock(&kvm_lock); 6111 } 6112 6113 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 6114 6115 /* 6116 * Notification about pvclock gtod data update. 6117 */ 6118 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 6119 void *priv) 6120 { 6121 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 6122 struct timekeeper *tk = priv; 6123 6124 update_pvclock_gtod(tk); 6125 6126 /* disable master clock if host does not trust, or does not 6127 * use, TSC clocksource 6128 */ 6129 if (gtod->clock.vclock_mode != VCLOCK_TSC && 6130 atomic_read(&kvm_guest_has_master_clock) != 0) 6131 queue_work(system_long_wq, &pvclock_gtod_work); 6132 6133 return 0; 6134 } 6135 6136 static struct notifier_block pvclock_gtod_notifier = { 6137 .notifier_call = pvclock_gtod_notify, 6138 }; 6139 #endif 6140 6141 int kvm_arch_init(void *opaque) 6142 { 6143 int r; 6144 struct kvm_x86_ops *ops = opaque; 6145 6146 if (kvm_x86_ops) { 6147 printk(KERN_ERR "kvm: already loaded the other module\n"); 6148 r = -EEXIST; 6149 goto out; 6150 } 6151 6152 if (!ops->cpu_has_kvm_support()) { 6153 printk(KERN_ERR "kvm: no hardware support\n"); 6154 r = -EOPNOTSUPP; 6155 goto out; 6156 } 6157 if (ops->disabled_by_bios()) { 6158 printk(KERN_ERR "kvm: disabled by bios\n"); 6159 r = -EOPNOTSUPP; 6160 goto out; 6161 } 6162 6163 r = -ENOMEM; 6164 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 6165 if (!shared_msrs) { 6166 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 6167 goto out; 6168 } 6169 6170 r = kvm_mmu_module_init(); 6171 if (r) 6172 goto out_free_percpu; 6173 6174 kvm_set_mmio_spte_mask(); 6175 6176 kvm_x86_ops = ops; 6177 6178 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 6179 PT_DIRTY_MASK, PT64_NX_MASK, 0, 6180 PT_PRESENT_MASK, 0, sme_me_mask); 6181 kvm_timer_init(); 6182 6183 perf_register_guest_info_callbacks(&kvm_guest_cbs); 6184 6185 if (boot_cpu_has(X86_FEATURE_XSAVE)) 6186 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 6187 6188 kvm_lapic_init(); 6189 #ifdef CONFIG_X86_64 6190 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 6191 #endif 6192 6193 return 0; 6194 6195 out_free_percpu: 6196 free_percpu(shared_msrs); 6197 out: 6198 return r; 6199 } 6200 6201 void kvm_arch_exit(void) 6202 { 6203 kvm_lapic_exit(); 6204 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 6205 6206 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 6207 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 6208 CPUFREQ_TRANSITION_NOTIFIER); 6209 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 6210 #ifdef CONFIG_X86_64 6211 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 6212 #endif 6213 kvm_x86_ops = NULL; 6214 kvm_mmu_module_exit(); 6215 free_percpu(shared_msrs); 6216 } 6217 6218 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 6219 { 6220 ++vcpu->stat.halt_exits; 6221 if (lapic_in_kernel(vcpu)) { 6222 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 6223 return 1; 6224 } else { 6225 vcpu->run->exit_reason = KVM_EXIT_HLT; 6226 return 0; 6227 } 6228 } 6229 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 6230 6231 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 6232 { 6233 int ret = kvm_skip_emulated_instruction(vcpu); 6234 /* 6235 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 6236 * KVM_EXIT_DEBUG here. 6237 */ 6238 return kvm_vcpu_halt(vcpu) && ret; 6239 } 6240 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 6241 6242 #ifdef CONFIG_X86_64 6243 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 6244 unsigned long clock_type) 6245 { 6246 struct kvm_clock_pairing clock_pairing; 6247 struct timespec ts; 6248 u64 cycle; 6249 int ret; 6250 6251 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 6252 return -KVM_EOPNOTSUPP; 6253 6254 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) 6255 return -KVM_EOPNOTSUPP; 6256 6257 clock_pairing.sec = ts.tv_sec; 6258 clock_pairing.nsec = ts.tv_nsec; 6259 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 6260 clock_pairing.flags = 0; 6261 6262 ret = 0; 6263 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 6264 sizeof(struct kvm_clock_pairing))) 6265 ret = -KVM_EFAULT; 6266 6267 return ret; 6268 } 6269 #endif 6270 6271 /* 6272 * kvm_pv_kick_cpu_op: Kick a vcpu. 6273 * 6274 * @apicid - apicid of vcpu to be kicked. 6275 */ 6276 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 6277 { 6278 struct kvm_lapic_irq lapic_irq; 6279 6280 lapic_irq.shorthand = 0; 6281 lapic_irq.dest_mode = 0; 6282 lapic_irq.level = 0; 6283 lapic_irq.dest_id = apicid; 6284 lapic_irq.msi_redir_hint = false; 6285 6286 lapic_irq.delivery_mode = APIC_DM_REMRD; 6287 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 6288 } 6289 6290 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) 6291 { 6292 vcpu->arch.apicv_active = false; 6293 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); 6294 } 6295 6296 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 6297 { 6298 unsigned long nr, a0, a1, a2, a3, ret; 6299 int op_64_bit, r; 6300 6301 r = kvm_skip_emulated_instruction(vcpu); 6302 6303 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 6304 return kvm_hv_hypercall(vcpu); 6305 6306 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 6307 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 6308 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 6309 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 6310 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 6311 6312 trace_kvm_hypercall(nr, a0, a1, a2, a3); 6313 6314 op_64_bit = is_64_bit_mode(vcpu); 6315 if (!op_64_bit) { 6316 nr &= 0xFFFFFFFF; 6317 a0 &= 0xFFFFFFFF; 6318 a1 &= 0xFFFFFFFF; 6319 a2 &= 0xFFFFFFFF; 6320 a3 &= 0xFFFFFFFF; 6321 } 6322 6323 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 6324 ret = -KVM_EPERM; 6325 goto out; 6326 } 6327 6328 switch (nr) { 6329 case KVM_HC_VAPIC_POLL_IRQ: 6330 ret = 0; 6331 break; 6332 case KVM_HC_KICK_CPU: 6333 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 6334 ret = 0; 6335 break; 6336 #ifdef CONFIG_X86_64 6337 case KVM_HC_CLOCK_PAIRING: 6338 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 6339 break; 6340 #endif 6341 default: 6342 ret = -KVM_ENOSYS; 6343 break; 6344 } 6345 out: 6346 if (!op_64_bit) 6347 ret = (u32)ret; 6348 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 6349 ++vcpu->stat.hypercalls; 6350 return r; 6351 } 6352 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 6353 6354 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 6355 { 6356 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6357 char instruction[3]; 6358 unsigned long rip = kvm_rip_read(vcpu); 6359 6360 kvm_x86_ops->patch_hypercall(vcpu, instruction); 6361 6362 return emulator_write_emulated(ctxt, rip, instruction, 3, 6363 &ctxt->exception); 6364 } 6365 6366 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 6367 { 6368 return vcpu->run->request_interrupt_window && 6369 likely(!pic_in_kernel(vcpu->kvm)); 6370 } 6371 6372 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 6373 { 6374 struct kvm_run *kvm_run = vcpu->run; 6375 6376 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 6377 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 6378 kvm_run->cr8 = kvm_get_cr8(vcpu); 6379 kvm_run->apic_base = kvm_get_apic_base(vcpu); 6380 kvm_run->ready_for_interrupt_injection = 6381 pic_in_kernel(vcpu->kvm) || 6382 kvm_vcpu_ready_for_interrupt_injection(vcpu); 6383 } 6384 6385 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 6386 { 6387 int max_irr, tpr; 6388 6389 if (!kvm_x86_ops->update_cr8_intercept) 6390 return; 6391 6392 if (!lapic_in_kernel(vcpu)) 6393 return; 6394 6395 if (vcpu->arch.apicv_active) 6396 return; 6397 6398 if (!vcpu->arch.apic->vapic_addr) 6399 max_irr = kvm_lapic_find_highest_irr(vcpu); 6400 else 6401 max_irr = -1; 6402 6403 if (max_irr != -1) 6404 max_irr >>= 4; 6405 6406 tpr = kvm_lapic_get_cr8(vcpu); 6407 6408 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 6409 } 6410 6411 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 6412 { 6413 int r; 6414 6415 /* try to reinject previous events if any */ 6416 if (vcpu->arch.exception.injected) { 6417 kvm_x86_ops->queue_exception(vcpu); 6418 return 0; 6419 } 6420 6421 /* 6422 * Exceptions must be injected immediately, or the exception 6423 * frame will have the address of the NMI or interrupt handler. 6424 */ 6425 if (!vcpu->arch.exception.pending) { 6426 if (vcpu->arch.nmi_injected) { 6427 kvm_x86_ops->set_nmi(vcpu); 6428 return 0; 6429 } 6430 6431 if (vcpu->arch.interrupt.pending) { 6432 kvm_x86_ops->set_irq(vcpu); 6433 return 0; 6434 } 6435 } 6436 6437 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6438 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6439 if (r != 0) 6440 return r; 6441 } 6442 6443 /* try to inject new event if pending */ 6444 if (vcpu->arch.exception.pending) { 6445 trace_kvm_inj_exception(vcpu->arch.exception.nr, 6446 vcpu->arch.exception.has_error_code, 6447 vcpu->arch.exception.error_code); 6448 6449 vcpu->arch.exception.pending = false; 6450 vcpu->arch.exception.injected = true; 6451 6452 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 6453 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 6454 X86_EFLAGS_RF); 6455 6456 if (vcpu->arch.exception.nr == DB_VECTOR && 6457 (vcpu->arch.dr7 & DR7_GD)) { 6458 vcpu->arch.dr7 &= ~DR7_GD; 6459 kvm_update_dr7(vcpu); 6460 } 6461 6462 kvm_x86_ops->queue_exception(vcpu); 6463 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) { 6464 vcpu->arch.smi_pending = false; 6465 enter_smm(vcpu); 6466 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { 6467 --vcpu->arch.nmi_pending; 6468 vcpu->arch.nmi_injected = true; 6469 kvm_x86_ops->set_nmi(vcpu); 6470 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 6471 /* 6472 * Because interrupts can be injected asynchronously, we are 6473 * calling check_nested_events again here to avoid a race condition. 6474 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 6475 * proposal and current concerns. Perhaps we should be setting 6476 * KVM_REQ_EVENT only on certain events and not unconditionally? 6477 */ 6478 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6479 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6480 if (r != 0) 6481 return r; 6482 } 6483 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 6484 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 6485 false); 6486 kvm_x86_ops->set_irq(vcpu); 6487 } 6488 } 6489 6490 return 0; 6491 } 6492 6493 static void process_nmi(struct kvm_vcpu *vcpu) 6494 { 6495 unsigned limit = 2; 6496 6497 /* 6498 * x86 is limited to one NMI running, and one NMI pending after it. 6499 * If an NMI is already in progress, limit further NMIs to just one. 6500 * Otherwise, allow two (and we'll inject the first one immediately). 6501 */ 6502 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 6503 limit = 1; 6504 6505 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 6506 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 6507 kvm_make_request(KVM_REQ_EVENT, vcpu); 6508 } 6509 6510 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 6511 { 6512 u32 flags = 0; 6513 flags |= seg->g << 23; 6514 flags |= seg->db << 22; 6515 flags |= seg->l << 21; 6516 flags |= seg->avl << 20; 6517 flags |= seg->present << 15; 6518 flags |= seg->dpl << 13; 6519 flags |= seg->s << 12; 6520 flags |= seg->type << 8; 6521 return flags; 6522 } 6523 6524 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 6525 { 6526 struct kvm_segment seg; 6527 int offset; 6528 6529 kvm_get_segment(vcpu, &seg, n); 6530 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 6531 6532 if (n < 3) 6533 offset = 0x7f84 + n * 12; 6534 else 6535 offset = 0x7f2c + (n - 3) * 12; 6536 6537 put_smstate(u32, buf, offset + 8, seg.base); 6538 put_smstate(u32, buf, offset + 4, seg.limit); 6539 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 6540 } 6541 6542 #ifdef CONFIG_X86_64 6543 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 6544 { 6545 struct kvm_segment seg; 6546 int offset; 6547 u16 flags; 6548 6549 kvm_get_segment(vcpu, &seg, n); 6550 offset = 0x7e00 + n * 16; 6551 6552 flags = enter_smm_get_segment_flags(&seg) >> 8; 6553 put_smstate(u16, buf, offset, seg.selector); 6554 put_smstate(u16, buf, offset + 2, flags); 6555 put_smstate(u32, buf, offset + 4, seg.limit); 6556 put_smstate(u64, buf, offset + 8, seg.base); 6557 } 6558 #endif 6559 6560 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 6561 { 6562 struct desc_ptr dt; 6563 struct kvm_segment seg; 6564 unsigned long val; 6565 int i; 6566 6567 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 6568 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 6569 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 6570 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 6571 6572 for (i = 0; i < 8; i++) 6573 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 6574 6575 kvm_get_dr(vcpu, 6, &val); 6576 put_smstate(u32, buf, 0x7fcc, (u32)val); 6577 kvm_get_dr(vcpu, 7, &val); 6578 put_smstate(u32, buf, 0x7fc8, (u32)val); 6579 6580 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6581 put_smstate(u32, buf, 0x7fc4, seg.selector); 6582 put_smstate(u32, buf, 0x7f64, seg.base); 6583 put_smstate(u32, buf, 0x7f60, seg.limit); 6584 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 6585 6586 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6587 put_smstate(u32, buf, 0x7fc0, seg.selector); 6588 put_smstate(u32, buf, 0x7f80, seg.base); 6589 put_smstate(u32, buf, 0x7f7c, seg.limit); 6590 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 6591 6592 kvm_x86_ops->get_gdt(vcpu, &dt); 6593 put_smstate(u32, buf, 0x7f74, dt.address); 6594 put_smstate(u32, buf, 0x7f70, dt.size); 6595 6596 kvm_x86_ops->get_idt(vcpu, &dt); 6597 put_smstate(u32, buf, 0x7f58, dt.address); 6598 put_smstate(u32, buf, 0x7f54, dt.size); 6599 6600 for (i = 0; i < 6; i++) 6601 enter_smm_save_seg_32(vcpu, buf, i); 6602 6603 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 6604 6605 /* revision id */ 6606 put_smstate(u32, buf, 0x7efc, 0x00020000); 6607 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 6608 } 6609 6610 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 6611 { 6612 #ifdef CONFIG_X86_64 6613 struct desc_ptr dt; 6614 struct kvm_segment seg; 6615 unsigned long val; 6616 int i; 6617 6618 for (i = 0; i < 16; i++) 6619 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 6620 6621 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 6622 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 6623 6624 kvm_get_dr(vcpu, 6, &val); 6625 put_smstate(u64, buf, 0x7f68, val); 6626 kvm_get_dr(vcpu, 7, &val); 6627 put_smstate(u64, buf, 0x7f60, val); 6628 6629 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 6630 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 6631 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 6632 6633 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 6634 6635 /* revision id */ 6636 put_smstate(u32, buf, 0x7efc, 0x00020064); 6637 6638 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 6639 6640 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6641 put_smstate(u16, buf, 0x7e90, seg.selector); 6642 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 6643 put_smstate(u32, buf, 0x7e94, seg.limit); 6644 put_smstate(u64, buf, 0x7e98, seg.base); 6645 6646 kvm_x86_ops->get_idt(vcpu, &dt); 6647 put_smstate(u32, buf, 0x7e84, dt.size); 6648 put_smstate(u64, buf, 0x7e88, dt.address); 6649 6650 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6651 put_smstate(u16, buf, 0x7e70, seg.selector); 6652 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 6653 put_smstate(u32, buf, 0x7e74, seg.limit); 6654 put_smstate(u64, buf, 0x7e78, seg.base); 6655 6656 kvm_x86_ops->get_gdt(vcpu, &dt); 6657 put_smstate(u32, buf, 0x7e64, dt.size); 6658 put_smstate(u64, buf, 0x7e68, dt.address); 6659 6660 for (i = 0; i < 6; i++) 6661 enter_smm_save_seg_64(vcpu, buf, i); 6662 #else 6663 WARN_ON_ONCE(1); 6664 #endif 6665 } 6666 6667 static void enter_smm(struct kvm_vcpu *vcpu) 6668 { 6669 struct kvm_segment cs, ds; 6670 struct desc_ptr dt; 6671 char buf[512]; 6672 u32 cr0; 6673 6674 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 6675 memset(buf, 0, 512); 6676 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 6677 enter_smm_save_state_64(vcpu, buf); 6678 else 6679 enter_smm_save_state_32(vcpu, buf); 6680 6681 /* 6682 * Give pre_enter_smm() a chance to make ISA-specific changes to the 6683 * vCPU state (e.g. leave guest mode) after we've saved the state into 6684 * the SMM state-save area. 6685 */ 6686 kvm_x86_ops->pre_enter_smm(vcpu, buf); 6687 6688 vcpu->arch.hflags |= HF_SMM_MASK; 6689 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 6690 6691 if (kvm_x86_ops->get_nmi_mask(vcpu)) 6692 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 6693 else 6694 kvm_x86_ops->set_nmi_mask(vcpu, true); 6695 6696 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 6697 kvm_rip_write(vcpu, 0x8000); 6698 6699 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 6700 kvm_x86_ops->set_cr0(vcpu, cr0); 6701 vcpu->arch.cr0 = cr0; 6702 6703 kvm_x86_ops->set_cr4(vcpu, 0); 6704 6705 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 6706 dt.address = dt.size = 0; 6707 kvm_x86_ops->set_idt(vcpu, &dt); 6708 6709 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 6710 6711 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 6712 cs.base = vcpu->arch.smbase; 6713 6714 ds.selector = 0; 6715 ds.base = 0; 6716 6717 cs.limit = ds.limit = 0xffffffff; 6718 cs.type = ds.type = 0x3; 6719 cs.dpl = ds.dpl = 0; 6720 cs.db = ds.db = 0; 6721 cs.s = ds.s = 1; 6722 cs.l = ds.l = 0; 6723 cs.g = ds.g = 1; 6724 cs.avl = ds.avl = 0; 6725 cs.present = ds.present = 1; 6726 cs.unusable = ds.unusable = 0; 6727 cs.padding = ds.padding = 0; 6728 6729 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 6730 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 6731 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 6732 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 6733 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 6734 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 6735 6736 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 6737 kvm_x86_ops->set_efer(vcpu, 0); 6738 6739 kvm_update_cpuid(vcpu); 6740 kvm_mmu_reset_context(vcpu); 6741 } 6742 6743 static void process_smi(struct kvm_vcpu *vcpu) 6744 { 6745 vcpu->arch.smi_pending = true; 6746 kvm_make_request(KVM_REQ_EVENT, vcpu); 6747 } 6748 6749 void kvm_make_scan_ioapic_request(struct kvm *kvm) 6750 { 6751 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 6752 } 6753 6754 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 6755 { 6756 u64 eoi_exit_bitmap[4]; 6757 6758 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 6759 return; 6760 6761 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 6762 6763 if (irqchip_split(vcpu->kvm)) 6764 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 6765 else { 6766 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active) 6767 kvm_x86_ops->sync_pir_to_irr(vcpu); 6768 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 6769 } 6770 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, 6771 vcpu_to_synic(vcpu)->vec_bitmap, 256); 6772 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 6773 } 6774 6775 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) 6776 { 6777 ++vcpu->stat.tlb_flush; 6778 kvm_x86_ops->tlb_flush(vcpu); 6779 } 6780 6781 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 6782 { 6783 struct page *page = NULL; 6784 6785 if (!lapic_in_kernel(vcpu)) 6786 return; 6787 6788 if (!kvm_x86_ops->set_apic_access_page_addr) 6789 return; 6790 6791 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 6792 if (is_error_page(page)) 6793 return; 6794 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 6795 6796 /* 6797 * Do not pin apic access page in memory, the MMU notifier 6798 * will call us again if it is migrated or swapped out. 6799 */ 6800 put_page(page); 6801 } 6802 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 6803 6804 /* 6805 * Returns 1 to let vcpu_run() continue the guest execution loop without 6806 * exiting to the userspace. Otherwise, the value will be returned to the 6807 * userspace. 6808 */ 6809 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 6810 { 6811 int r; 6812 bool req_int_win = 6813 dm_request_for_irq_injection(vcpu) && 6814 kvm_cpu_accept_dm_intr(vcpu); 6815 6816 bool req_immediate_exit = false; 6817 6818 if (kvm_request_pending(vcpu)) { 6819 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 6820 kvm_mmu_unload(vcpu); 6821 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 6822 __kvm_migrate_timers(vcpu); 6823 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 6824 kvm_gen_update_masterclock(vcpu->kvm); 6825 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 6826 kvm_gen_kvmclock_update(vcpu); 6827 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 6828 r = kvm_guest_time_update(vcpu); 6829 if (unlikely(r)) 6830 goto out; 6831 } 6832 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 6833 kvm_mmu_sync_roots(vcpu); 6834 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 6835 kvm_vcpu_flush_tlb(vcpu); 6836 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 6837 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 6838 r = 0; 6839 goto out; 6840 } 6841 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 6842 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 6843 vcpu->mmio_needed = 0; 6844 r = 0; 6845 goto out; 6846 } 6847 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 6848 /* Page is swapped out. Do synthetic halt */ 6849 vcpu->arch.apf.halted = true; 6850 r = 1; 6851 goto out; 6852 } 6853 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 6854 record_steal_time(vcpu); 6855 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 6856 process_smi(vcpu); 6857 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 6858 process_nmi(vcpu); 6859 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 6860 kvm_pmu_handle_event(vcpu); 6861 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 6862 kvm_pmu_deliver_pmi(vcpu); 6863 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 6864 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 6865 if (test_bit(vcpu->arch.pending_ioapic_eoi, 6866 vcpu->arch.ioapic_handled_vectors)) { 6867 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 6868 vcpu->run->eoi.vector = 6869 vcpu->arch.pending_ioapic_eoi; 6870 r = 0; 6871 goto out; 6872 } 6873 } 6874 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 6875 vcpu_scan_ioapic(vcpu); 6876 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 6877 kvm_vcpu_reload_apic_access_page(vcpu); 6878 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 6879 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 6880 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 6881 r = 0; 6882 goto out; 6883 } 6884 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 6885 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 6886 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 6887 r = 0; 6888 goto out; 6889 } 6890 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 6891 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 6892 vcpu->run->hyperv = vcpu->arch.hyperv.exit; 6893 r = 0; 6894 goto out; 6895 } 6896 6897 /* 6898 * KVM_REQ_HV_STIMER has to be processed after 6899 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 6900 * depend on the guest clock being up-to-date 6901 */ 6902 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 6903 kvm_hv_process_stimers(vcpu); 6904 } 6905 6906 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 6907 ++vcpu->stat.req_event; 6908 kvm_apic_accept_events(vcpu); 6909 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 6910 r = 1; 6911 goto out; 6912 } 6913 6914 if (inject_pending_event(vcpu, req_int_win) != 0) 6915 req_immediate_exit = true; 6916 else { 6917 /* Enable SMI/NMI/IRQ window open exits if needed. 6918 * 6919 * SMIs have three cases: 6920 * 1) They can be nested, and then there is nothing to 6921 * do here because RSM will cause a vmexit anyway. 6922 * 2) There is an ISA-specific reason why SMI cannot be 6923 * injected, and the moment when this changes can be 6924 * intercepted. 6925 * 3) Or the SMI can be pending because 6926 * inject_pending_event has completed the injection 6927 * of an IRQ or NMI from the previous vmexit, and 6928 * then we request an immediate exit to inject the 6929 * SMI. 6930 */ 6931 if (vcpu->arch.smi_pending && !is_smm(vcpu)) 6932 if (!kvm_x86_ops->enable_smi_window(vcpu)) 6933 req_immediate_exit = true; 6934 if (vcpu->arch.nmi_pending) 6935 kvm_x86_ops->enable_nmi_window(vcpu); 6936 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 6937 kvm_x86_ops->enable_irq_window(vcpu); 6938 WARN_ON(vcpu->arch.exception.pending); 6939 } 6940 6941 if (kvm_lapic_enabled(vcpu)) { 6942 update_cr8_intercept(vcpu); 6943 kvm_lapic_sync_to_vapic(vcpu); 6944 } 6945 } 6946 6947 r = kvm_mmu_reload(vcpu); 6948 if (unlikely(r)) { 6949 goto cancel_injection; 6950 } 6951 6952 preempt_disable(); 6953 6954 kvm_x86_ops->prepare_guest_switch(vcpu); 6955 kvm_load_guest_fpu(vcpu); 6956 6957 /* 6958 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 6959 * IPI are then delayed after guest entry, which ensures that they 6960 * result in virtual interrupt delivery. 6961 */ 6962 local_irq_disable(); 6963 vcpu->mode = IN_GUEST_MODE; 6964 6965 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6966 6967 /* 6968 * 1) We should set ->mode before checking ->requests. Please see 6969 * the comment in kvm_vcpu_exiting_guest_mode(). 6970 * 6971 * 2) For APICv, we should set ->mode before checking PIR.ON. This 6972 * pairs with the memory barrier implicit in pi_test_and_set_on 6973 * (see vmx_deliver_posted_interrupt). 6974 * 6975 * 3) This also orders the write to mode from any reads to the page 6976 * tables done while the VCPU is running. Please see the comment 6977 * in kvm_flush_remote_tlbs. 6978 */ 6979 smp_mb__after_srcu_read_unlock(); 6980 6981 /* 6982 * This handles the case where a posted interrupt was 6983 * notified with kvm_vcpu_kick. 6984 */ 6985 if (kvm_lapic_enabled(vcpu)) { 6986 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active) 6987 kvm_x86_ops->sync_pir_to_irr(vcpu); 6988 } 6989 6990 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) 6991 || need_resched() || signal_pending(current)) { 6992 vcpu->mode = OUTSIDE_GUEST_MODE; 6993 smp_wmb(); 6994 local_irq_enable(); 6995 preempt_enable(); 6996 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6997 r = 1; 6998 goto cancel_injection; 6999 } 7000 7001 kvm_load_guest_xcr0(vcpu); 7002 7003 if (req_immediate_exit) { 7004 kvm_make_request(KVM_REQ_EVENT, vcpu); 7005 smp_send_reschedule(vcpu->cpu); 7006 } 7007 7008 trace_kvm_entry(vcpu->vcpu_id); 7009 wait_lapic_expire(vcpu); 7010 guest_enter_irqoff(); 7011 7012 if (unlikely(vcpu->arch.switch_db_regs)) { 7013 set_debugreg(0, 7); 7014 set_debugreg(vcpu->arch.eff_db[0], 0); 7015 set_debugreg(vcpu->arch.eff_db[1], 1); 7016 set_debugreg(vcpu->arch.eff_db[2], 2); 7017 set_debugreg(vcpu->arch.eff_db[3], 3); 7018 set_debugreg(vcpu->arch.dr6, 6); 7019 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 7020 } 7021 7022 kvm_x86_ops->run(vcpu); 7023 7024 /* 7025 * Do this here before restoring debug registers on the host. And 7026 * since we do this before handling the vmexit, a DR access vmexit 7027 * can (a) read the correct value of the debug registers, (b) set 7028 * KVM_DEBUGREG_WONT_EXIT again. 7029 */ 7030 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 7031 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 7032 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 7033 kvm_update_dr0123(vcpu); 7034 kvm_update_dr6(vcpu); 7035 kvm_update_dr7(vcpu); 7036 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 7037 } 7038 7039 /* 7040 * If the guest has used debug registers, at least dr7 7041 * will be disabled while returning to the host. 7042 * If we don't have active breakpoints in the host, we don't 7043 * care about the messed up debug address registers. But if 7044 * we have some of them active, restore the old state. 7045 */ 7046 if (hw_breakpoint_active()) 7047 hw_breakpoint_restore(); 7048 7049 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 7050 7051 vcpu->mode = OUTSIDE_GUEST_MODE; 7052 smp_wmb(); 7053 7054 kvm_put_guest_xcr0(vcpu); 7055 7056 kvm_x86_ops->handle_external_intr(vcpu); 7057 7058 ++vcpu->stat.exits; 7059 7060 guest_exit_irqoff(); 7061 7062 local_irq_enable(); 7063 preempt_enable(); 7064 7065 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7066 7067 /* 7068 * Profile KVM exit RIPs: 7069 */ 7070 if (unlikely(prof_on == KVM_PROFILING)) { 7071 unsigned long rip = kvm_rip_read(vcpu); 7072 profile_hit(KVM_PROFILING, (void *)rip); 7073 } 7074 7075 if (unlikely(vcpu->arch.tsc_always_catchup)) 7076 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7077 7078 if (vcpu->arch.apic_attention) 7079 kvm_lapic_sync_from_vapic(vcpu); 7080 7081 vcpu->arch.gpa_available = false; 7082 r = kvm_x86_ops->handle_exit(vcpu); 7083 return r; 7084 7085 cancel_injection: 7086 kvm_x86_ops->cancel_injection(vcpu); 7087 if (unlikely(vcpu->arch.apic_attention)) 7088 kvm_lapic_sync_from_vapic(vcpu); 7089 out: 7090 return r; 7091 } 7092 7093 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 7094 { 7095 if (!kvm_arch_vcpu_runnable(vcpu) && 7096 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { 7097 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7098 kvm_vcpu_block(vcpu); 7099 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7100 7101 if (kvm_x86_ops->post_block) 7102 kvm_x86_ops->post_block(vcpu); 7103 7104 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 7105 return 1; 7106 } 7107 7108 kvm_apic_accept_events(vcpu); 7109 switch(vcpu->arch.mp_state) { 7110 case KVM_MP_STATE_HALTED: 7111 vcpu->arch.pv.pv_unhalted = false; 7112 vcpu->arch.mp_state = 7113 KVM_MP_STATE_RUNNABLE; 7114 case KVM_MP_STATE_RUNNABLE: 7115 vcpu->arch.apf.halted = false; 7116 break; 7117 case KVM_MP_STATE_INIT_RECEIVED: 7118 break; 7119 default: 7120 return -EINTR; 7121 break; 7122 } 7123 return 1; 7124 } 7125 7126 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 7127 { 7128 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 7129 kvm_x86_ops->check_nested_events(vcpu, false); 7130 7131 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 7132 !vcpu->arch.apf.halted); 7133 } 7134 7135 static int vcpu_run(struct kvm_vcpu *vcpu) 7136 { 7137 int r; 7138 struct kvm *kvm = vcpu->kvm; 7139 7140 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7141 7142 for (;;) { 7143 if (kvm_vcpu_running(vcpu)) { 7144 r = vcpu_enter_guest(vcpu); 7145 } else { 7146 r = vcpu_block(kvm, vcpu); 7147 } 7148 7149 if (r <= 0) 7150 break; 7151 7152 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); 7153 if (kvm_cpu_has_pending_timer(vcpu)) 7154 kvm_inject_pending_timer_irqs(vcpu); 7155 7156 if (dm_request_for_irq_injection(vcpu) && 7157 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 7158 r = 0; 7159 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 7160 ++vcpu->stat.request_irq_exits; 7161 break; 7162 } 7163 7164 kvm_check_async_pf_completion(vcpu); 7165 7166 if (signal_pending(current)) { 7167 r = -EINTR; 7168 vcpu->run->exit_reason = KVM_EXIT_INTR; 7169 ++vcpu->stat.signal_exits; 7170 break; 7171 } 7172 if (need_resched()) { 7173 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7174 cond_resched(); 7175 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7176 } 7177 } 7178 7179 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7180 7181 return r; 7182 } 7183 7184 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 7185 { 7186 int r; 7187 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7188 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 7189 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 7190 if (r != EMULATE_DONE) 7191 return 0; 7192 return 1; 7193 } 7194 7195 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 7196 { 7197 BUG_ON(!vcpu->arch.pio.count); 7198 7199 return complete_emulated_io(vcpu); 7200 } 7201 7202 /* 7203 * Implements the following, as a state machine: 7204 * 7205 * read: 7206 * for each fragment 7207 * for each mmio piece in the fragment 7208 * write gpa, len 7209 * exit 7210 * copy data 7211 * execute insn 7212 * 7213 * write: 7214 * for each fragment 7215 * for each mmio piece in the fragment 7216 * write gpa, len 7217 * copy data 7218 * exit 7219 */ 7220 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 7221 { 7222 struct kvm_run *run = vcpu->run; 7223 struct kvm_mmio_fragment *frag; 7224 unsigned len; 7225 7226 BUG_ON(!vcpu->mmio_needed); 7227 7228 /* Complete previous fragment */ 7229 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 7230 len = min(8u, frag->len); 7231 if (!vcpu->mmio_is_write) 7232 memcpy(frag->data, run->mmio.data, len); 7233 7234 if (frag->len <= 8) { 7235 /* Switch to the next fragment. */ 7236 frag++; 7237 vcpu->mmio_cur_fragment++; 7238 } else { 7239 /* Go forward to the next mmio piece. */ 7240 frag->data += len; 7241 frag->gpa += len; 7242 frag->len -= len; 7243 } 7244 7245 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 7246 vcpu->mmio_needed = 0; 7247 7248 /* FIXME: return into emulator if single-stepping. */ 7249 if (vcpu->mmio_is_write) 7250 return 1; 7251 vcpu->mmio_read_completed = 1; 7252 return complete_emulated_io(vcpu); 7253 } 7254 7255 run->exit_reason = KVM_EXIT_MMIO; 7256 run->mmio.phys_addr = frag->gpa; 7257 if (vcpu->mmio_is_write) 7258 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 7259 run->mmio.len = min(8u, frag->len); 7260 run->mmio.is_write = vcpu->mmio_is_write; 7261 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 7262 return 0; 7263 } 7264 7265 7266 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 7267 { 7268 struct fpu *fpu = ¤t->thread.fpu; 7269 int r; 7270 7271 fpu__initialize(fpu); 7272 7273 kvm_sigset_activate(vcpu); 7274 7275 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 7276 if (kvm_run->immediate_exit) { 7277 r = -EINTR; 7278 goto out; 7279 } 7280 kvm_vcpu_block(vcpu); 7281 kvm_apic_accept_events(vcpu); 7282 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 7283 r = -EAGAIN; 7284 if (signal_pending(current)) { 7285 r = -EINTR; 7286 vcpu->run->exit_reason = KVM_EXIT_INTR; 7287 ++vcpu->stat.signal_exits; 7288 } 7289 goto out; 7290 } 7291 7292 /* re-sync apic's tpr */ 7293 if (!lapic_in_kernel(vcpu)) { 7294 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 7295 r = -EINVAL; 7296 goto out; 7297 } 7298 } 7299 7300 if (unlikely(vcpu->arch.complete_userspace_io)) { 7301 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 7302 vcpu->arch.complete_userspace_io = NULL; 7303 r = cui(vcpu); 7304 if (r <= 0) 7305 goto out; 7306 } else 7307 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 7308 7309 if (kvm_run->immediate_exit) 7310 r = -EINTR; 7311 else 7312 r = vcpu_run(vcpu); 7313 7314 out: 7315 post_kvm_run_save(vcpu); 7316 kvm_sigset_deactivate(vcpu); 7317 7318 return r; 7319 } 7320 7321 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7322 { 7323 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 7324 /* 7325 * We are here if userspace calls get_regs() in the middle of 7326 * instruction emulation. Registers state needs to be copied 7327 * back from emulation context to vcpu. Userspace shouldn't do 7328 * that usually, but some bad designed PV devices (vmware 7329 * backdoor interface) need this to work 7330 */ 7331 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 7332 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7333 } 7334 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 7335 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 7336 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 7337 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 7338 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 7339 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 7340 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 7341 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 7342 #ifdef CONFIG_X86_64 7343 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 7344 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 7345 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 7346 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 7347 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 7348 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 7349 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 7350 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 7351 #endif 7352 7353 regs->rip = kvm_rip_read(vcpu); 7354 regs->rflags = kvm_get_rflags(vcpu); 7355 7356 return 0; 7357 } 7358 7359 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7360 { 7361 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 7362 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7363 7364 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 7365 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 7366 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 7367 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 7368 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 7369 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 7370 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 7371 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 7372 #ifdef CONFIG_X86_64 7373 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 7374 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 7375 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 7376 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 7377 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 7378 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 7379 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 7380 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 7381 #endif 7382 7383 kvm_rip_write(vcpu, regs->rip); 7384 kvm_set_rflags(vcpu, regs->rflags); 7385 7386 vcpu->arch.exception.pending = false; 7387 7388 kvm_make_request(KVM_REQ_EVENT, vcpu); 7389 7390 return 0; 7391 } 7392 7393 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 7394 { 7395 struct kvm_segment cs; 7396 7397 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7398 *db = cs.db; 7399 *l = cs.l; 7400 } 7401 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 7402 7403 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 7404 struct kvm_sregs *sregs) 7405 { 7406 struct desc_ptr dt; 7407 7408 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7409 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7410 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7411 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7412 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7413 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7414 7415 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7416 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7417 7418 kvm_x86_ops->get_idt(vcpu, &dt); 7419 sregs->idt.limit = dt.size; 7420 sregs->idt.base = dt.address; 7421 kvm_x86_ops->get_gdt(vcpu, &dt); 7422 sregs->gdt.limit = dt.size; 7423 sregs->gdt.base = dt.address; 7424 7425 sregs->cr0 = kvm_read_cr0(vcpu); 7426 sregs->cr2 = vcpu->arch.cr2; 7427 sregs->cr3 = kvm_read_cr3(vcpu); 7428 sregs->cr4 = kvm_read_cr4(vcpu); 7429 sregs->cr8 = kvm_get_cr8(vcpu); 7430 sregs->efer = vcpu->arch.efer; 7431 sregs->apic_base = kvm_get_apic_base(vcpu); 7432 7433 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 7434 7435 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) 7436 set_bit(vcpu->arch.interrupt.nr, 7437 (unsigned long *)sregs->interrupt_bitmap); 7438 7439 return 0; 7440 } 7441 7442 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 7443 struct kvm_mp_state *mp_state) 7444 { 7445 kvm_apic_accept_events(vcpu); 7446 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 7447 vcpu->arch.pv.pv_unhalted) 7448 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 7449 else 7450 mp_state->mp_state = vcpu->arch.mp_state; 7451 7452 return 0; 7453 } 7454 7455 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 7456 struct kvm_mp_state *mp_state) 7457 { 7458 if (!lapic_in_kernel(vcpu) && 7459 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 7460 return -EINVAL; 7461 7462 /* INITs are latched while in SMM */ 7463 if ((is_smm(vcpu) || vcpu->arch.smi_pending) && 7464 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 7465 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 7466 return -EINVAL; 7467 7468 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 7469 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 7470 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 7471 } else 7472 vcpu->arch.mp_state = mp_state->mp_state; 7473 kvm_make_request(KVM_REQ_EVENT, vcpu); 7474 return 0; 7475 } 7476 7477 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 7478 int reason, bool has_error_code, u32 error_code) 7479 { 7480 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 7481 int ret; 7482 7483 init_emulate_ctxt(vcpu); 7484 7485 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 7486 has_error_code, error_code); 7487 7488 if (ret) 7489 return EMULATE_FAIL; 7490 7491 kvm_rip_write(vcpu, ctxt->eip); 7492 kvm_set_rflags(vcpu, ctxt->eflags); 7493 kvm_make_request(KVM_REQ_EVENT, vcpu); 7494 return EMULATE_DONE; 7495 } 7496 EXPORT_SYMBOL_GPL(kvm_task_switch); 7497 7498 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 7499 struct kvm_sregs *sregs) 7500 { 7501 struct msr_data apic_base_msr; 7502 int mmu_reset_needed = 0; 7503 int pending_vec, max_bits, idx; 7504 struct desc_ptr dt; 7505 7506 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 7507 (sregs->cr4 & X86_CR4_OSXSAVE)) 7508 return -EINVAL; 7509 7510 apic_base_msr.data = sregs->apic_base; 7511 apic_base_msr.host_initiated = true; 7512 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 7513 return -EINVAL; 7514 7515 dt.size = sregs->idt.limit; 7516 dt.address = sregs->idt.base; 7517 kvm_x86_ops->set_idt(vcpu, &dt); 7518 dt.size = sregs->gdt.limit; 7519 dt.address = sregs->gdt.base; 7520 kvm_x86_ops->set_gdt(vcpu, &dt); 7521 7522 vcpu->arch.cr2 = sregs->cr2; 7523 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 7524 vcpu->arch.cr3 = sregs->cr3; 7525 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 7526 7527 kvm_set_cr8(vcpu, sregs->cr8); 7528 7529 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 7530 kvm_x86_ops->set_efer(vcpu, sregs->efer); 7531 7532 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 7533 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 7534 vcpu->arch.cr0 = sregs->cr0; 7535 7536 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 7537 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 7538 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 7539 kvm_update_cpuid(vcpu); 7540 7541 idx = srcu_read_lock(&vcpu->kvm->srcu); 7542 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 7543 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 7544 mmu_reset_needed = 1; 7545 } 7546 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7547 7548 if (mmu_reset_needed) 7549 kvm_mmu_reset_context(vcpu); 7550 7551 max_bits = KVM_NR_INTERRUPTS; 7552 pending_vec = find_first_bit( 7553 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 7554 if (pending_vec < max_bits) { 7555 kvm_queue_interrupt(vcpu, pending_vec, false); 7556 pr_debug("Set back pending irq %d\n", pending_vec); 7557 } 7558 7559 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7560 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7561 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7562 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7563 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7564 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7565 7566 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7567 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7568 7569 update_cr8_intercept(vcpu); 7570 7571 /* Older userspace won't unhalt the vcpu on reset. */ 7572 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 7573 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 7574 !is_protmode(vcpu)) 7575 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7576 7577 kvm_make_request(KVM_REQ_EVENT, vcpu); 7578 7579 return 0; 7580 } 7581 7582 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 7583 struct kvm_guest_debug *dbg) 7584 { 7585 unsigned long rflags; 7586 int i, r; 7587 7588 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 7589 r = -EBUSY; 7590 if (vcpu->arch.exception.pending) 7591 goto out; 7592 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 7593 kvm_queue_exception(vcpu, DB_VECTOR); 7594 else 7595 kvm_queue_exception(vcpu, BP_VECTOR); 7596 } 7597 7598 /* 7599 * Read rflags as long as potentially injected trace flags are still 7600 * filtered out. 7601 */ 7602 rflags = kvm_get_rflags(vcpu); 7603 7604 vcpu->guest_debug = dbg->control; 7605 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 7606 vcpu->guest_debug = 0; 7607 7608 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 7609 for (i = 0; i < KVM_NR_DB_REGS; ++i) 7610 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 7611 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 7612 } else { 7613 for (i = 0; i < KVM_NR_DB_REGS; i++) 7614 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 7615 } 7616 kvm_update_dr7(vcpu); 7617 7618 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 7619 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 7620 get_segment_base(vcpu, VCPU_SREG_CS); 7621 7622 /* 7623 * Trigger an rflags update that will inject or remove the trace 7624 * flags. 7625 */ 7626 kvm_set_rflags(vcpu, rflags); 7627 7628 kvm_x86_ops->update_bp_intercept(vcpu); 7629 7630 r = 0; 7631 7632 out: 7633 7634 return r; 7635 } 7636 7637 /* 7638 * Translate a guest virtual address to a guest physical address. 7639 */ 7640 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 7641 struct kvm_translation *tr) 7642 { 7643 unsigned long vaddr = tr->linear_address; 7644 gpa_t gpa; 7645 int idx; 7646 7647 idx = srcu_read_lock(&vcpu->kvm->srcu); 7648 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 7649 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7650 tr->physical_address = gpa; 7651 tr->valid = gpa != UNMAPPED_GVA; 7652 tr->writeable = 1; 7653 tr->usermode = 0; 7654 7655 return 0; 7656 } 7657 7658 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7659 { 7660 struct fxregs_state *fxsave = 7661 &vcpu->arch.guest_fpu.state.fxsave; 7662 7663 memcpy(fpu->fpr, fxsave->st_space, 128); 7664 fpu->fcw = fxsave->cwd; 7665 fpu->fsw = fxsave->swd; 7666 fpu->ftwx = fxsave->twd; 7667 fpu->last_opcode = fxsave->fop; 7668 fpu->last_ip = fxsave->rip; 7669 fpu->last_dp = fxsave->rdp; 7670 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 7671 7672 return 0; 7673 } 7674 7675 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7676 { 7677 struct fxregs_state *fxsave = 7678 &vcpu->arch.guest_fpu.state.fxsave; 7679 7680 memcpy(fxsave->st_space, fpu->fpr, 128); 7681 fxsave->cwd = fpu->fcw; 7682 fxsave->swd = fpu->fsw; 7683 fxsave->twd = fpu->ftwx; 7684 fxsave->fop = fpu->last_opcode; 7685 fxsave->rip = fpu->last_ip; 7686 fxsave->rdp = fpu->last_dp; 7687 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 7688 7689 return 0; 7690 } 7691 7692 static void fx_init(struct kvm_vcpu *vcpu) 7693 { 7694 fpstate_init(&vcpu->arch.guest_fpu.state); 7695 if (boot_cpu_has(X86_FEATURE_XSAVES)) 7696 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv = 7697 host_xcr0 | XSTATE_COMPACTION_ENABLED; 7698 7699 /* 7700 * Ensure guest xcr0 is valid for loading 7701 */ 7702 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 7703 7704 vcpu->arch.cr0 |= X86_CR0_ET; 7705 } 7706 7707 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 7708 { 7709 if (vcpu->guest_fpu_loaded) 7710 return; 7711 7712 /* 7713 * Restore all possible states in the guest, 7714 * and assume host would use all available bits. 7715 * Guest xcr0 would be loaded later. 7716 */ 7717 vcpu->guest_fpu_loaded = 1; 7718 __kernel_fpu_begin(); 7719 /* PKRU is separately restored in kvm_x86_ops->run. */ 7720 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state, 7721 ~XFEATURE_MASK_PKRU); 7722 trace_kvm_fpu(1); 7723 } 7724 7725 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 7726 { 7727 if (!vcpu->guest_fpu_loaded) 7728 return; 7729 7730 vcpu->guest_fpu_loaded = 0; 7731 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu); 7732 __kernel_fpu_end(); 7733 ++vcpu->stat.fpu_reload; 7734 trace_kvm_fpu(0); 7735 } 7736 7737 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 7738 { 7739 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask; 7740 7741 kvmclock_reset(vcpu); 7742 7743 kvm_x86_ops->vcpu_free(vcpu); 7744 free_cpumask_var(wbinvd_dirty_mask); 7745 } 7746 7747 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 7748 unsigned int id) 7749 { 7750 struct kvm_vcpu *vcpu; 7751 7752 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 7753 printk_once(KERN_WARNING 7754 "kvm: SMP vm created on host with unstable TSC; " 7755 "guest TSC will not be reliable\n"); 7756 7757 vcpu = kvm_x86_ops->vcpu_create(kvm, id); 7758 7759 return vcpu; 7760 } 7761 7762 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 7763 { 7764 int r; 7765 7766 kvm_vcpu_mtrr_init(vcpu); 7767 r = vcpu_load(vcpu); 7768 if (r) 7769 return r; 7770 kvm_vcpu_reset(vcpu, false); 7771 kvm_mmu_setup(vcpu); 7772 vcpu_put(vcpu); 7773 return r; 7774 } 7775 7776 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 7777 { 7778 struct msr_data msr; 7779 struct kvm *kvm = vcpu->kvm; 7780 7781 kvm_hv_vcpu_postcreate(vcpu); 7782 7783 if (vcpu_load(vcpu)) 7784 return; 7785 msr.data = 0x0; 7786 msr.index = MSR_IA32_TSC; 7787 msr.host_initiated = true; 7788 kvm_write_tsc(vcpu, &msr); 7789 vcpu_put(vcpu); 7790 7791 if (!kvmclock_periodic_sync) 7792 return; 7793 7794 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 7795 KVMCLOCK_SYNC_PERIOD); 7796 } 7797 7798 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 7799 { 7800 int r; 7801 vcpu->arch.apf.msr_val = 0; 7802 7803 r = vcpu_load(vcpu); 7804 BUG_ON(r); 7805 kvm_mmu_unload(vcpu); 7806 vcpu_put(vcpu); 7807 7808 kvm_x86_ops->vcpu_free(vcpu); 7809 } 7810 7811 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 7812 { 7813 vcpu->arch.hflags = 0; 7814 7815 vcpu->arch.smi_pending = 0; 7816 atomic_set(&vcpu->arch.nmi_queued, 0); 7817 vcpu->arch.nmi_pending = 0; 7818 vcpu->arch.nmi_injected = false; 7819 kvm_clear_interrupt_queue(vcpu); 7820 kvm_clear_exception_queue(vcpu); 7821 vcpu->arch.exception.pending = false; 7822 7823 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 7824 kvm_update_dr0123(vcpu); 7825 vcpu->arch.dr6 = DR6_INIT; 7826 kvm_update_dr6(vcpu); 7827 vcpu->arch.dr7 = DR7_FIXED_1; 7828 kvm_update_dr7(vcpu); 7829 7830 vcpu->arch.cr2 = 0; 7831 7832 kvm_make_request(KVM_REQ_EVENT, vcpu); 7833 vcpu->arch.apf.msr_val = 0; 7834 vcpu->arch.st.msr_val = 0; 7835 7836 kvmclock_reset(vcpu); 7837 7838 kvm_clear_async_pf_completion_queue(vcpu); 7839 kvm_async_pf_hash_reset(vcpu); 7840 vcpu->arch.apf.halted = false; 7841 7842 if (kvm_mpx_supported()) { 7843 void *mpx_state_buffer; 7844 7845 /* 7846 * To avoid have the INIT path from kvm_apic_has_events() that be 7847 * called with loaded FPU and does not let userspace fix the state. 7848 */ 7849 kvm_put_guest_fpu(vcpu); 7850 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave, 7851 XFEATURE_MASK_BNDREGS); 7852 if (mpx_state_buffer) 7853 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); 7854 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave, 7855 XFEATURE_MASK_BNDCSR); 7856 if (mpx_state_buffer) 7857 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); 7858 } 7859 7860 if (!init_event) { 7861 kvm_pmu_reset(vcpu); 7862 vcpu->arch.smbase = 0x30000; 7863 7864 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 7865 vcpu->arch.msr_misc_features_enables = 0; 7866 7867 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 7868 } 7869 7870 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 7871 vcpu->arch.regs_avail = ~0; 7872 vcpu->arch.regs_dirty = ~0; 7873 7874 vcpu->arch.ia32_xss = 0; 7875 7876 kvm_x86_ops->vcpu_reset(vcpu, init_event); 7877 } 7878 7879 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 7880 { 7881 struct kvm_segment cs; 7882 7883 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7884 cs.selector = vector << 8; 7885 cs.base = vector << 12; 7886 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7887 kvm_rip_write(vcpu, 0); 7888 } 7889 7890 int kvm_arch_hardware_enable(void) 7891 { 7892 struct kvm *kvm; 7893 struct kvm_vcpu *vcpu; 7894 int i; 7895 int ret; 7896 u64 local_tsc; 7897 u64 max_tsc = 0; 7898 bool stable, backwards_tsc = false; 7899 7900 kvm_shared_msr_cpu_online(); 7901 ret = kvm_x86_ops->hardware_enable(); 7902 if (ret != 0) 7903 return ret; 7904 7905 local_tsc = rdtsc(); 7906 stable = !check_tsc_unstable(); 7907 list_for_each_entry(kvm, &vm_list, vm_list) { 7908 kvm_for_each_vcpu(i, vcpu, kvm) { 7909 if (!stable && vcpu->cpu == smp_processor_id()) 7910 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7911 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 7912 backwards_tsc = true; 7913 if (vcpu->arch.last_host_tsc > max_tsc) 7914 max_tsc = vcpu->arch.last_host_tsc; 7915 } 7916 } 7917 } 7918 7919 /* 7920 * Sometimes, even reliable TSCs go backwards. This happens on 7921 * platforms that reset TSC during suspend or hibernate actions, but 7922 * maintain synchronization. We must compensate. Fortunately, we can 7923 * detect that condition here, which happens early in CPU bringup, 7924 * before any KVM threads can be running. Unfortunately, we can't 7925 * bring the TSCs fully up to date with real time, as we aren't yet far 7926 * enough into CPU bringup that we know how much real time has actually 7927 * elapsed; our helper function, ktime_get_boot_ns() will be using boot 7928 * variables that haven't been updated yet. 7929 * 7930 * So we simply find the maximum observed TSC above, then record the 7931 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 7932 * the adjustment will be applied. Note that we accumulate 7933 * adjustments, in case multiple suspend cycles happen before some VCPU 7934 * gets a chance to run again. In the event that no KVM threads get a 7935 * chance to run, we will miss the entire elapsed period, as we'll have 7936 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 7937 * loose cycle time. This isn't too big a deal, since the loss will be 7938 * uniform across all VCPUs (not to mention the scenario is extremely 7939 * unlikely). It is possible that a second hibernate recovery happens 7940 * much faster than a first, causing the observed TSC here to be 7941 * smaller; this would require additional padding adjustment, which is 7942 * why we set last_host_tsc to the local tsc observed here. 7943 * 7944 * N.B. - this code below runs only on platforms with reliable TSC, 7945 * as that is the only way backwards_tsc is set above. Also note 7946 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 7947 * have the same delta_cyc adjustment applied if backwards_tsc 7948 * is detected. Note further, this adjustment is only done once, 7949 * as we reset last_host_tsc on all VCPUs to stop this from being 7950 * called multiple times (one for each physical CPU bringup). 7951 * 7952 * Platforms with unreliable TSCs don't have to deal with this, they 7953 * will be compensated by the logic in vcpu_load, which sets the TSC to 7954 * catchup mode. This will catchup all VCPUs to real time, but cannot 7955 * guarantee that they stay in perfect synchronization. 7956 */ 7957 if (backwards_tsc) { 7958 u64 delta_cyc = max_tsc - local_tsc; 7959 list_for_each_entry(kvm, &vm_list, vm_list) { 7960 kvm->arch.backwards_tsc_observed = true; 7961 kvm_for_each_vcpu(i, vcpu, kvm) { 7962 vcpu->arch.tsc_offset_adjustment += delta_cyc; 7963 vcpu->arch.last_host_tsc = local_tsc; 7964 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7965 } 7966 7967 /* 7968 * We have to disable TSC offset matching.. if you were 7969 * booting a VM while issuing an S4 host suspend.... 7970 * you may have some problem. Solving this issue is 7971 * left as an exercise to the reader. 7972 */ 7973 kvm->arch.last_tsc_nsec = 0; 7974 kvm->arch.last_tsc_write = 0; 7975 } 7976 7977 } 7978 return 0; 7979 } 7980 7981 void kvm_arch_hardware_disable(void) 7982 { 7983 kvm_x86_ops->hardware_disable(); 7984 drop_user_return_notifiers(); 7985 } 7986 7987 int kvm_arch_hardware_setup(void) 7988 { 7989 int r; 7990 7991 r = kvm_x86_ops->hardware_setup(); 7992 if (r != 0) 7993 return r; 7994 7995 if (kvm_has_tsc_control) { 7996 /* 7997 * Make sure the user can only configure tsc_khz values that 7998 * fit into a signed integer. 7999 * A min value is not calculated needed because it will always 8000 * be 1 on all machines. 8001 */ 8002 u64 max = min(0x7fffffffULL, 8003 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 8004 kvm_max_guest_tsc_khz = max; 8005 8006 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 8007 } 8008 8009 kvm_init_msr_list(); 8010 return 0; 8011 } 8012 8013 void kvm_arch_hardware_unsetup(void) 8014 { 8015 kvm_x86_ops->hardware_unsetup(); 8016 } 8017 8018 void kvm_arch_check_processor_compat(void *rtn) 8019 { 8020 kvm_x86_ops->check_processor_compatibility(rtn); 8021 } 8022 8023 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 8024 { 8025 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 8026 } 8027 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 8028 8029 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 8030 { 8031 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 8032 } 8033 8034 struct static_key kvm_no_apic_vcpu __read_mostly; 8035 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); 8036 8037 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 8038 { 8039 struct page *page; 8040 int r; 8041 8042 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu); 8043 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 8044 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 8045 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8046 else 8047 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 8048 8049 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 8050 if (!page) { 8051 r = -ENOMEM; 8052 goto fail; 8053 } 8054 vcpu->arch.pio_data = page_address(page); 8055 8056 kvm_set_tsc_khz(vcpu, max_tsc_khz); 8057 8058 r = kvm_mmu_create(vcpu); 8059 if (r < 0) 8060 goto fail_free_pio_data; 8061 8062 if (irqchip_in_kernel(vcpu->kvm)) { 8063 r = kvm_create_lapic(vcpu); 8064 if (r < 0) 8065 goto fail_mmu_destroy; 8066 } else 8067 static_key_slow_inc(&kvm_no_apic_vcpu); 8068 8069 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 8070 GFP_KERNEL); 8071 if (!vcpu->arch.mce_banks) { 8072 r = -ENOMEM; 8073 goto fail_free_lapic; 8074 } 8075 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 8076 8077 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 8078 r = -ENOMEM; 8079 goto fail_free_mce_banks; 8080 } 8081 8082 fx_init(vcpu); 8083 8084 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 8085 8086 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 8087 8088 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 8089 8090 kvm_async_pf_hash_reset(vcpu); 8091 kvm_pmu_init(vcpu); 8092 8093 vcpu->arch.pending_external_vector = -1; 8094 vcpu->arch.preempted_in_kernel = false; 8095 8096 kvm_hv_vcpu_init(vcpu); 8097 8098 return 0; 8099 8100 fail_free_mce_banks: 8101 kfree(vcpu->arch.mce_banks); 8102 fail_free_lapic: 8103 kvm_free_lapic(vcpu); 8104 fail_mmu_destroy: 8105 kvm_mmu_destroy(vcpu); 8106 fail_free_pio_data: 8107 free_page((unsigned long)vcpu->arch.pio_data); 8108 fail: 8109 return r; 8110 } 8111 8112 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 8113 { 8114 int idx; 8115 8116 kvm_hv_vcpu_uninit(vcpu); 8117 kvm_pmu_destroy(vcpu); 8118 kfree(vcpu->arch.mce_banks); 8119 kvm_free_lapic(vcpu); 8120 idx = srcu_read_lock(&vcpu->kvm->srcu); 8121 kvm_mmu_destroy(vcpu); 8122 srcu_read_unlock(&vcpu->kvm->srcu, idx); 8123 free_page((unsigned long)vcpu->arch.pio_data); 8124 if (!lapic_in_kernel(vcpu)) 8125 static_key_slow_dec(&kvm_no_apic_vcpu); 8126 } 8127 8128 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 8129 { 8130 kvm_x86_ops->sched_in(vcpu, cpu); 8131 } 8132 8133 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 8134 { 8135 if (type) 8136 return -EINVAL; 8137 8138 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 8139 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 8140 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 8141 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 8142 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 8143 8144 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 8145 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 8146 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 8147 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 8148 &kvm->arch.irq_sources_bitmap); 8149 8150 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 8151 mutex_init(&kvm->arch.apic_map_lock); 8152 mutex_init(&kvm->arch.hyperv.hv_lock); 8153 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 8154 8155 kvm->arch.kvmclock_offset = -ktime_get_boot_ns(); 8156 pvclock_update_vm_gtod_copy(kvm); 8157 8158 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 8159 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 8160 8161 kvm_page_track_init(kvm); 8162 kvm_mmu_init_vm(kvm); 8163 8164 if (kvm_x86_ops->vm_init) 8165 return kvm_x86_ops->vm_init(kvm); 8166 8167 return 0; 8168 } 8169 8170 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 8171 { 8172 int r; 8173 r = vcpu_load(vcpu); 8174 BUG_ON(r); 8175 kvm_mmu_unload(vcpu); 8176 vcpu_put(vcpu); 8177 } 8178 8179 static void kvm_free_vcpus(struct kvm *kvm) 8180 { 8181 unsigned int i; 8182 struct kvm_vcpu *vcpu; 8183 8184 /* 8185 * Unpin any mmu pages first. 8186 */ 8187 kvm_for_each_vcpu(i, vcpu, kvm) { 8188 kvm_clear_async_pf_completion_queue(vcpu); 8189 kvm_unload_vcpu_mmu(vcpu); 8190 } 8191 kvm_for_each_vcpu(i, vcpu, kvm) 8192 kvm_arch_vcpu_free(vcpu); 8193 8194 mutex_lock(&kvm->lock); 8195 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 8196 kvm->vcpus[i] = NULL; 8197 8198 atomic_set(&kvm->online_vcpus, 0); 8199 mutex_unlock(&kvm->lock); 8200 } 8201 8202 void kvm_arch_sync_events(struct kvm *kvm) 8203 { 8204 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 8205 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 8206 kvm_free_pit(kvm); 8207 } 8208 8209 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 8210 { 8211 int i, r; 8212 unsigned long hva; 8213 struct kvm_memslots *slots = kvm_memslots(kvm); 8214 struct kvm_memory_slot *slot, old; 8215 8216 /* Called with kvm->slots_lock held. */ 8217 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 8218 return -EINVAL; 8219 8220 slot = id_to_memslot(slots, id); 8221 if (size) { 8222 if (slot->npages) 8223 return -EEXIST; 8224 8225 /* 8226 * MAP_SHARED to prevent internal slot pages from being moved 8227 * by fork()/COW. 8228 */ 8229 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 8230 MAP_SHARED | MAP_ANONYMOUS, 0); 8231 if (IS_ERR((void *)hva)) 8232 return PTR_ERR((void *)hva); 8233 } else { 8234 if (!slot->npages) 8235 return 0; 8236 8237 hva = 0; 8238 } 8239 8240 old = *slot; 8241 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 8242 struct kvm_userspace_memory_region m; 8243 8244 m.slot = id | (i << 16); 8245 m.flags = 0; 8246 m.guest_phys_addr = gpa; 8247 m.userspace_addr = hva; 8248 m.memory_size = size; 8249 r = __kvm_set_memory_region(kvm, &m); 8250 if (r < 0) 8251 return r; 8252 } 8253 8254 if (!size) { 8255 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); 8256 WARN_ON(r < 0); 8257 } 8258 8259 return 0; 8260 } 8261 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 8262 8263 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 8264 { 8265 int r; 8266 8267 mutex_lock(&kvm->slots_lock); 8268 r = __x86_set_memory_region(kvm, id, gpa, size); 8269 mutex_unlock(&kvm->slots_lock); 8270 8271 return r; 8272 } 8273 EXPORT_SYMBOL_GPL(x86_set_memory_region); 8274 8275 void kvm_arch_destroy_vm(struct kvm *kvm) 8276 { 8277 if (current->mm == kvm->mm) { 8278 /* 8279 * Free memory regions allocated on behalf of userspace, 8280 * unless the the memory map has changed due to process exit 8281 * or fd copying. 8282 */ 8283 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); 8284 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); 8285 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 8286 } 8287 if (kvm_x86_ops->vm_destroy) 8288 kvm_x86_ops->vm_destroy(kvm); 8289 kvm_pic_destroy(kvm); 8290 kvm_ioapic_destroy(kvm); 8291 kvm_free_vcpus(kvm); 8292 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 8293 kvm_mmu_uninit_vm(kvm); 8294 kvm_page_track_cleanup(kvm); 8295 } 8296 8297 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 8298 struct kvm_memory_slot *dont) 8299 { 8300 int i; 8301 8302 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8303 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 8304 kvfree(free->arch.rmap[i]); 8305 free->arch.rmap[i] = NULL; 8306 } 8307 if (i == 0) 8308 continue; 8309 8310 if (!dont || free->arch.lpage_info[i - 1] != 8311 dont->arch.lpage_info[i - 1]) { 8312 kvfree(free->arch.lpage_info[i - 1]); 8313 free->arch.lpage_info[i - 1] = NULL; 8314 } 8315 } 8316 8317 kvm_page_track_free_memslot(free, dont); 8318 } 8319 8320 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 8321 unsigned long npages) 8322 { 8323 int i; 8324 8325 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8326 struct kvm_lpage_info *linfo; 8327 unsigned long ugfn; 8328 int lpages; 8329 int level = i + 1; 8330 8331 lpages = gfn_to_index(slot->base_gfn + npages - 1, 8332 slot->base_gfn, level) + 1; 8333 8334 slot->arch.rmap[i] = 8335 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL); 8336 if (!slot->arch.rmap[i]) 8337 goto out_free; 8338 if (i == 0) 8339 continue; 8340 8341 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL); 8342 if (!linfo) 8343 goto out_free; 8344 8345 slot->arch.lpage_info[i - 1] = linfo; 8346 8347 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 8348 linfo[0].disallow_lpage = 1; 8349 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 8350 linfo[lpages - 1].disallow_lpage = 1; 8351 ugfn = slot->userspace_addr >> PAGE_SHIFT; 8352 /* 8353 * If the gfn and userspace address are not aligned wrt each 8354 * other, or if explicitly asked to, disable large page 8355 * support for this slot 8356 */ 8357 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 8358 !kvm_largepages_enabled()) { 8359 unsigned long j; 8360 8361 for (j = 0; j < lpages; ++j) 8362 linfo[j].disallow_lpage = 1; 8363 } 8364 } 8365 8366 if (kvm_page_track_create_memslot(slot, npages)) 8367 goto out_free; 8368 8369 return 0; 8370 8371 out_free: 8372 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8373 kvfree(slot->arch.rmap[i]); 8374 slot->arch.rmap[i] = NULL; 8375 if (i == 0) 8376 continue; 8377 8378 kvfree(slot->arch.lpage_info[i - 1]); 8379 slot->arch.lpage_info[i - 1] = NULL; 8380 } 8381 return -ENOMEM; 8382 } 8383 8384 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) 8385 { 8386 /* 8387 * memslots->generation has been incremented. 8388 * mmio generation may have reached its maximum value. 8389 */ 8390 kvm_mmu_invalidate_mmio_sptes(kvm, slots); 8391 } 8392 8393 int kvm_arch_prepare_memory_region(struct kvm *kvm, 8394 struct kvm_memory_slot *memslot, 8395 const struct kvm_userspace_memory_region *mem, 8396 enum kvm_mr_change change) 8397 { 8398 return 0; 8399 } 8400 8401 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 8402 struct kvm_memory_slot *new) 8403 { 8404 /* Still write protect RO slot */ 8405 if (new->flags & KVM_MEM_READONLY) { 8406 kvm_mmu_slot_remove_write_access(kvm, new); 8407 return; 8408 } 8409 8410 /* 8411 * Call kvm_x86_ops dirty logging hooks when they are valid. 8412 * 8413 * kvm_x86_ops->slot_disable_log_dirty is called when: 8414 * 8415 * - KVM_MR_CREATE with dirty logging is disabled 8416 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 8417 * 8418 * The reason is, in case of PML, we need to set D-bit for any slots 8419 * with dirty logging disabled in order to eliminate unnecessary GPA 8420 * logging in PML buffer (and potential PML buffer full VMEXT). This 8421 * guarantees leaving PML enabled during guest's lifetime won't have 8422 * any additonal overhead from PML when guest is running with dirty 8423 * logging disabled for memory slots. 8424 * 8425 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 8426 * to dirty logging mode. 8427 * 8428 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 8429 * 8430 * In case of write protect: 8431 * 8432 * Write protect all pages for dirty logging. 8433 * 8434 * All the sptes including the large sptes which point to this 8435 * slot are set to readonly. We can not create any new large 8436 * spte on this slot until the end of the logging. 8437 * 8438 * See the comments in fast_page_fault(). 8439 */ 8440 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 8441 if (kvm_x86_ops->slot_enable_log_dirty) 8442 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 8443 else 8444 kvm_mmu_slot_remove_write_access(kvm, new); 8445 } else { 8446 if (kvm_x86_ops->slot_disable_log_dirty) 8447 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 8448 } 8449 } 8450 8451 void kvm_arch_commit_memory_region(struct kvm *kvm, 8452 const struct kvm_userspace_memory_region *mem, 8453 const struct kvm_memory_slot *old, 8454 const struct kvm_memory_slot *new, 8455 enum kvm_mr_change change) 8456 { 8457 int nr_mmu_pages = 0; 8458 8459 if (!kvm->arch.n_requested_mmu_pages) 8460 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 8461 8462 if (nr_mmu_pages) 8463 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 8464 8465 /* 8466 * Dirty logging tracks sptes in 4k granularity, meaning that large 8467 * sptes have to be split. If live migration is successful, the guest 8468 * in the source machine will be destroyed and large sptes will be 8469 * created in the destination. However, if the guest continues to run 8470 * in the source machine (for example if live migration fails), small 8471 * sptes will remain around and cause bad performance. 8472 * 8473 * Scan sptes if dirty logging has been stopped, dropping those 8474 * which can be collapsed into a single large-page spte. Later 8475 * page faults will create the large-page sptes. 8476 */ 8477 if ((change != KVM_MR_DELETE) && 8478 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 8479 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 8480 kvm_mmu_zap_collapsible_sptes(kvm, new); 8481 8482 /* 8483 * Set up write protection and/or dirty logging for the new slot. 8484 * 8485 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 8486 * been zapped so no dirty logging staff is needed for old slot. For 8487 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 8488 * new and it's also covered when dealing with the new slot. 8489 * 8490 * FIXME: const-ify all uses of struct kvm_memory_slot. 8491 */ 8492 if (change != KVM_MR_DELETE) 8493 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 8494 } 8495 8496 void kvm_arch_flush_shadow_all(struct kvm *kvm) 8497 { 8498 kvm_mmu_invalidate_zap_all_pages(kvm); 8499 } 8500 8501 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 8502 struct kvm_memory_slot *slot) 8503 { 8504 kvm_page_track_flush_slot(kvm, slot); 8505 } 8506 8507 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 8508 { 8509 if (!list_empty_careful(&vcpu->async_pf.done)) 8510 return true; 8511 8512 if (kvm_apic_has_events(vcpu)) 8513 return true; 8514 8515 if (vcpu->arch.pv.pv_unhalted) 8516 return true; 8517 8518 if (vcpu->arch.exception.pending) 8519 return true; 8520 8521 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 8522 (vcpu->arch.nmi_pending && 8523 kvm_x86_ops->nmi_allowed(vcpu))) 8524 return true; 8525 8526 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 8527 (vcpu->arch.smi_pending && !is_smm(vcpu))) 8528 return true; 8529 8530 if (kvm_arch_interrupt_allowed(vcpu) && 8531 kvm_cpu_has_interrupt(vcpu)) 8532 return true; 8533 8534 if (kvm_hv_has_stimer_pending(vcpu)) 8535 return true; 8536 8537 return false; 8538 } 8539 8540 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 8541 { 8542 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 8543 } 8544 8545 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 8546 { 8547 return vcpu->arch.preempted_in_kernel; 8548 } 8549 8550 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 8551 { 8552 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 8553 } 8554 8555 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 8556 { 8557 return kvm_x86_ops->interrupt_allowed(vcpu); 8558 } 8559 8560 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 8561 { 8562 if (is_64_bit_mode(vcpu)) 8563 return kvm_rip_read(vcpu); 8564 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 8565 kvm_rip_read(vcpu)); 8566 } 8567 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 8568 8569 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 8570 { 8571 return kvm_get_linear_rip(vcpu) == linear_rip; 8572 } 8573 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 8574 8575 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 8576 { 8577 unsigned long rflags; 8578 8579 rflags = kvm_x86_ops->get_rflags(vcpu); 8580 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 8581 rflags &= ~X86_EFLAGS_TF; 8582 return rflags; 8583 } 8584 EXPORT_SYMBOL_GPL(kvm_get_rflags); 8585 8586 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8587 { 8588 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 8589 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 8590 rflags |= X86_EFLAGS_TF; 8591 kvm_x86_ops->set_rflags(vcpu, rflags); 8592 } 8593 8594 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8595 { 8596 __kvm_set_rflags(vcpu, rflags); 8597 kvm_make_request(KVM_REQ_EVENT, vcpu); 8598 } 8599 EXPORT_SYMBOL_GPL(kvm_set_rflags); 8600 8601 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 8602 { 8603 int r; 8604 8605 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 8606 work->wakeup_all) 8607 return; 8608 8609 r = kvm_mmu_reload(vcpu); 8610 if (unlikely(r)) 8611 return; 8612 8613 if (!vcpu->arch.mmu.direct_map && 8614 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 8615 return; 8616 8617 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 8618 } 8619 8620 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 8621 { 8622 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 8623 } 8624 8625 static inline u32 kvm_async_pf_next_probe(u32 key) 8626 { 8627 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 8628 } 8629 8630 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8631 { 8632 u32 key = kvm_async_pf_hash_fn(gfn); 8633 8634 while (vcpu->arch.apf.gfns[key] != ~0) 8635 key = kvm_async_pf_next_probe(key); 8636 8637 vcpu->arch.apf.gfns[key] = gfn; 8638 } 8639 8640 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 8641 { 8642 int i; 8643 u32 key = kvm_async_pf_hash_fn(gfn); 8644 8645 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 8646 (vcpu->arch.apf.gfns[key] != gfn && 8647 vcpu->arch.apf.gfns[key] != ~0); i++) 8648 key = kvm_async_pf_next_probe(key); 8649 8650 return key; 8651 } 8652 8653 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8654 { 8655 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 8656 } 8657 8658 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8659 { 8660 u32 i, j, k; 8661 8662 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 8663 while (true) { 8664 vcpu->arch.apf.gfns[i] = ~0; 8665 do { 8666 j = kvm_async_pf_next_probe(j); 8667 if (vcpu->arch.apf.gfns[j] == ~0) 8668 return; 8669 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 8670 /* 8671 * k lies cyclically in ]i,j] 8672 * | i.k.j | 8673 * |....j i.k.| or |.k..j i...| 8674 */ 8675 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 8676 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 8677 i = j; 8678 } 8679 } 8680 8681 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 8682 { 8683 8684 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 8685 sizeof(val)); 8686 } 8687 8688 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val) 8689 { 8690 8691 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val, 8692 sizeof(u32)); 8693 } 8694 8695 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 8696 struct kvm_async_pf *work) 8697 { 8698 struct x86_exception fault; 8699 8700 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 8701 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 8702 8703 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 8704 (vcpu->arch.apf.send_user_only && 8705 kvm_x86_ops->get_cpl(vcpu) == 0)) 8706 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 8707 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 8708 fault.vector = PF_VECTOR; 8709 fault.error_code_valid = true; 8710 fault.error_code = 0; 8711 fault.nested_page_fault = false; 8712 fault.address = work->arch.token; 8713 fault.async_page_fault = true; 8714 kvm_inject_page_fault(vcpu, &fault); 8715 } 8716 } 8717 8718 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 8719 struct kvm_async_pf *work) 8720 { 8721 struct x86_exception fault; 8722 u32 val; 8723 8724 if (work->wakeup_all) 8725 work->arch.token = ~0; /* broadcast wakeup */ 8726 else 8727 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 8728 trace_kvm_async_pf_ready(work->arch.token, work->gva); 8729 8730 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED && 8731 !apf_get_user(vcpu, &val)) { 8732 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT && 8733 vcpu->arch.exception.pending && 8734 vcpu->arch.exception.nr == PF_VECTOR && 8735 !apf_put_user(vcpu, 0)) { 8736 vcpu->arch.exception.injected = false; 8737 vcpu->arch.exception.pending = false; 8738 vcpu->arch.exception.nr = 0; 8739 vcpu->arch.exception.has_error_code = false; 8740 vcpu->arch.exception.error_code = 0; 8741 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 8742 fault.vector = PF_VECTOR; 8743 fault.error_code_valid = true; 8744 fault.error_code = 0; 8745 fault.nested_page_fault = false; 8746 fault.address = work->arch.token; 8747 fault.async_page_fault = true; 8748 kvm_inject_page_fault(vcpu, &fault); 8749 } 8750 } 8751 vcpu->arch.apf.halted = false; 8752 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8753 } 8754 8755 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 8756 { 8757 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 8758 return true; 8759 else 8760 return kvm_can_do_async_pf(vcpu); 8761 } 8762 8763 void kvm_arch_start_assignment(struct kvm *kvm) 8764 { 8765 atomic_inc(&kvm->arch.assigned_device_count); 8766 } 8767 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 8768 8769 void kvm_arch_end_assignment(struct kvm *kvm) 8770 { 8771 atomic_dec(&kvm->arch.assigned_device_count); 8772 } 8773 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 8774 8775 bool kvm_arch_has_assigned_device(struct kvm *kvm) 8776 { 8777 return atomic_read(&kvm->arch.assigned_device_count); 8778 } 8779 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 8780 8781 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 8782 { 8783 atomic_inc(&kvm->arch.noncoherent_dma_count); 8784 } 8785 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 8786 8787 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 8788 { 8789 atomic_dec(&kvm->arch.noncoherent_dma_count); 8790 } 8791 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 8792 8793 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 8794 { 8795 return atomic_read(&kvm->arch.noncoherent_dma_count); 8796 } 8797 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 8798 8799 bool kvm_arch_has_irq_bypass(void) 8800 { 8801 return kvm_x86_ops->update_pi_irte != NULL; 8802 } 8803 8804 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 8805 struct irq_bypass_producer *prod) 8806 { 8807 struct kvm_kernel_irqfd *irqfd = 8808 container_of(cons, struct kvm_kernel_irqfd, consumer); 8809 8810 irqfd->producer = prod; 8811 8812 return kvm_x86_ops->update_pi_irte(irqfd->kvm, 8813 prod->irq, irqfd->gsi, 1); 8814 } 8815 8816 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 8817 struct irq_bypass_producer *prod) 8818 { 8819 int ret; 8820 struct kvm_kernel_irqfd *irqfd = 8821 container_of(cons, struct kvm_kernel_irqfd, consumer); 8822 8823 WARN_ON(irqfd->producer != prod); 8824 irqfd->producer = NULL; 8825 8826 /* 8827 * When producer of consumer is unregistered, we change back to 8828 * remapped mode, so we can re-use the current implementation 8829 * when the irq is masked/disabled or the consumer side (KVM 8830 * int this case doesn't want to receive the interrupts. 8831 */ 8832 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 8833 if (ret) 8834 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 8835 " fails: %d\n", irqfd->consumer.token, ret); 8836 } 8837 8838 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 8839 uint32_t guest_irq, bool set) 8840 { 8841 if (!kvm_x86_ops->update_pi_irte) 8842 return -EINVAL; 8843 8844 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); 8845 } 8846 8847 bool kvm_vector_hashing_enabled(void) 8848 { 8849 return vector_hashing; 8850 } 8851 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled); 8852 8853 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 8854 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 8855 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 8856 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 8857 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 8858 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 8859 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 8860 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 8861 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 8862 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 8863 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 8864 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 8865 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 8866 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 8867 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 8868 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 8869 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 8870 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 8871 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 8872