1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "pmu.h" 31 #include "hyperv.h" 32 33 #include <linux/clocksource.h> 34 #include <linux/interrupt.h> 35 #include <linux/kvm.h> 36 #include <linux/fs.h> 37 #include <linux/vmalloc.h> 38 #include <linux/export.h> 39 #include <linux/moduleparam.h> 40 #include <linux/mman.h> 41 #include <linux/highmem.h> 42 #include <linux/iommu.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/cpufreq.h> 45 #include <linux/user-return-notifier.h> 46 #include <linux/srcu.h> 47 #include <linux/slab.h> 48 #include <linux/perf_event.h> 49 #include <linux/uaccess.h> 50 #include <linux/hash.h> 51 #include <linux/pci.h> 52 #include <linux/timekeeper_internal.h> 53 #include <linux/pvclock_gtod.h> 54 #include <linux/kvm_irqfd.h> 55 #include <linux/irqbypass.h> 56 #include <linux/sched/stat.h> 57 #include <linux/mem_encrypt.h> 58 59 #include <trace/events/kvm.h> 60 61 #include <asm/debugreg.h> 62 #include <asm/msr.h> 63 #include <asm/desc.h> 64 #include <asm/mce.h> 65 #include <linux/kernel_stat.h> 66 #include <asm/fpu/internal.h> /* Ugh! */ 67 #include <asm/pvclock.h> 68 #include <asm/div64.h> 69 #include <asm/irq_remapping.h> 70 #include <asm/mshyperv.h> 71 #include <asm/hypervisor.h> 72 73 #define CREATE_TRACE_POINTS 74 #include "trace.h" 75 76 #define MAX_IO_MSRS 256 77 #define KVM_MAX_MCE_BANKS 32 78 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 79 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 80 81 #define emul_to_vcpu(ctxt) \ 82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 83 84 /* EFER defaults: 85 * - enable syscall per default because its emulated by KVM 86 * - enable LME and LMA per default on 64 bit KVM 87 */ 88 #ifdef CONFIG_X86_64 89 static 90 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 91 #else 92 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 93 #endif 94 95 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 96 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 97 98 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 100 101 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 102 static void process_nmi(struct kvm_vcpu *vcpu); 103 static void enter_smm(struct kvm_vcpu *vcpu); 104 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 105 static void store_regs(struct kvm_vcpu *vcpu); 106 static int sync_regs(struct kvm_vcpu *vcpu); 107 108 struct kvm_x86_ops *kvm_x86_ops __read_mostly; 109 EXPORT_SYMBOL_GPL(kvm_x86_ops); 110 111 static bool __read_mostly ignore_msrs = 0; 112 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 113 114 static bool __read_mostly report_ignored_msrs = true; 115 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 116 117 unsigned int min_timer_period_us = 200; 118 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 119 120 static bool __read_mostly kvmclock_periodic_sync = true; 121 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 122 123 bool __read_mostly kvm_has_tsc_control; 124 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 125 u32 __read_mostly kvm_max_guest_tsc_khz; 126 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 127 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 128 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 129 u64 __read_mostly kvm_max_tsc_scaling_ratio; 130 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 131 u64 __read_mostly kvm_default_tsc_scaling_ratio; 132 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 133 134 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 135 static u32 __read_mostly tsc_tolerance_ppm = 250; 136 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 137 138 /* lapic timer advance (tscdeadline mode only) in nanoseconds */ 139 unsigned int __read_mostly lapic_timer_advance_ns = 0; 140 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 141 142 static bool __read_mostly vector_hashing = true; 143 module_param(vector_hashing, bool, S_IRUGO); 144 145 bool __read_mostly enable_vmware_backdoor = false; 146 module_param(enable_vmware_backdoor, bool, S_IRUGO); 147 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 148 149 static bool __read_mostly force_emulation_prefix = false; 150 module_param(force_emulation_prefix, bool, S_IRUGO); 151 152 #define KVM_NR_SHARED_MSRS 16 153 154 struct kvm_shared_msrs_global { 155 int nr; 156 u32 msrs[KVM_NR_SHARED_MSRS]; 157 }; 158 159 struct kvm_shared_msrs { 160 struct user_return_notifier urn; 161 bool registered; 162 struct kvm_shared_msr_values { 163 u64 host; 164 u64 curr; 165 } values[KVM_NR_SHARED_MSRS]; 166 }; 167 168 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 169 static struct kvm_shared_msrs __percpu *shared_msrs; 170 171 struct kvm_stats_debugfs_item debugfs_entries[] = { 172 { "pf_fixed", VCPU_STAT(pf_fixed) }, 173 { "pf_guest", VCPU_STAT(pf_guest) }, 174 { "tlb_flush", VCPU_STAT(tlb_flush) }, 175 { "invlpg", VCPU_STAT(invlpg) }, 176 { "exits", VCPU_STAT(exits) }, 177 { "io_exits", VCPU_STAT(io_exits) }, 178 { "mmio_exits", VCPU_STAT(mmio_exits) }, 179 { "signal_exits", VCPU_STAT(signal_exits) }, 180 { "irq_window", VCPU_STAT(irq_window_exits) }, 181 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 182 { "halt_exits", VCPU_STAT(halt_exits) }, 183 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 184 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 185 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, 186 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 187 { "hypercalls", VCPU_STAT(hypercalls) }, 188 { "request_irq", VCPU_STAT(request_irq_exits) }, 189 { "irq_exits", VCPU_STAT(irq_exits) }, 190 { "host_state_reload", VCPU_STAT(host_state_reload) }, 191 { "fpu_reload", VCPU_STAT(fpu_reload) }, 192 { "insn_emulation", VCPU_STAT(insn_emulation) }, 193 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 194 { "irq_injections", VCPU_STAT(irq_injections) }, 195 { "nmi_injections", VCPU_STAT(nmi_injections) }, 196 { "req_event", VCPU_STAT(req_event) }, 197 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 198 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 199 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 200 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 201 { "mmu_flooded", VM_STAT(mmu_flooded) }, 202 { "mmu_recycled", VM_STAT(mmu_recycled) }, 203 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 204 { "mmu_unsync", VM_STAT(mmu_unsync) }, 205 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 206 { "largepages", VM_STAT(lpages) }, 207 { "max_mmu_page_hash_collisions", 208 VM_STAT(max_mmu_page_hash_collisions) }, 209 { NULL } 210 }; 211 212 u64 __read_mostly host_xcr0; 213 214 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 215 216 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 217 { 218 int i; 219 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 220 vcpu->arch.apf.gfns[i] = ~0; 221 } 222 223 static void kvm_on_user_return(struct user_return_notifier *urn) 224 { 225 unsigned slot; 226 struct kvm_shared_msrs *locals 227 = container_of(urn, struct kvm_shared_msrs, urn); 228 struct kvm_shared_msr_values *values; 229 unsigned long flags; 230 231 /* 232 * Disabling irqs at this point since the following code could be 233 * interrupted and executed through kvm_arch_hardware_disable() 234 */ 235 local_irq_save(flags); 236 if (locals->registered) { 237 locals->registered = false; 238 user_return_notifier_unregister(urn); 239 } 240 local_irq_restore(flags); 241 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 242 values = &locals->values[slot]; 243 if (values->host != values->curr) { 244 wrmsrl(shared_msrs_global.msrs[slot], values->host); 245 values->curr = values->host; 246 } 247 } 248 } 249 250 static void shared_msr_update(unsigned slot, u32 msr) 251 { 252 u64 value; 253 unsigned int cpu = smp_processor_id(); 254 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 255 256 /* only read, and nobody should modify it at this time, 257 * so don't need lock */ 258 if (slot >= shared_msrs_global.nr) { 259 printk(KERN_ERR "kvm: invalid MSR slot!"); 260 return; 261 } 262 rdmsrl_safe(msr, &value); 263 smsr->values[slot].host = value; 264 smsr->values[slot].curr = value; 265 } 266 267 void kvm_define_shared_msr(unsigned slot, u32 msr) 268 { 269 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 270 shared_msrs_global.msrs[slot] = msr; 271 if (slot >= shared_msrs_global.nr) 272 shared_msrs_global.nr = slot + 1; 273 } 274 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 275 276 static void kvm_shared_msr_cpu_online(void) 277 { 278 unsigned i; 279 280 for (i = 0; i < shared_msrs_global.nr; ++i) 281 shared_msr_update(i, shared_msrs_global.msrs[i]); 282 } 283 284 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 285 { 286 unsigned int cpu = smp_processor_id(); 287 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 288 int err; 289 290 if (((value ^ smsr->values[slot].curr) & mask) == 0) 291 return 0; 292 smsr->values[slot].curr = value; 293 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 294 if (err) 295 return 1; 296 297 if (!smsr->registered) { 298 smsr->urn.on_user_return = kvm_on_user_return; 299 user_return_notifier_register(&smsr->urn); 300 smsr->registered = true; 301 } 302 return 0; 303 } 304 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 305 306 static void drop_user_return_notifiers(void) 307 { 308 unsigned int cpu = smp_processor_id(); 309 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 310 311 if (smsr->registered) 312 kvm_on_user_return(&smsr->urn); 313 } 314 315 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 316 { 317 return vcpu->arch.apic_base; 318 } 319 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 320 321 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 322 { 323 u64 old_state = vcpu->arch.apic_base & 324 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 325 u64 new_state = msr_info->data & 326 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 327 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | 328 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 329 330 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE) 331 return 1; 332 if (!msr_info->host_initiated && 333 ((new_state == MSR_IA32_APICBASE_ENABLE && 334 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 335 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 336 old_state == 0))) 337 return 1; 338 339 kvm_lapic_set_base(vcpu, msr_info->data); 340 return 0; 341 } 342 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 343 344 asmlinkage __visible void kvm_spurious_fault(void) 345 { 346 /* Fault while not rebooting. We want the trace. */ 347 BUG(); 348 } 349 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 350 351 #define EXCPT_BENIGN 0 352 #define EXCPT_CONTRIBUTORY 1 353 #define EXCPT_PF 2 354 355 static int exception_class(int vector) 356 { 357 switch (vector) { 358 case PF_VECTOR: 359 return EXCPT_PF; 360 case DE_VECTOR: 361 case TS_VECTOR: 362 case NP_VECTOR: 363 case SS_VECTOR: 364 case GP_VECTOR: 365 return EXCPT_CONTRIBUTORY; 366 default: 367 break; 368 } 369 return EXCPT_BENIGN; 370 } 371 372 #define EXCPT_FAULT 0 373 #define EXCPT_TRAP 1 374 #define EXCPT_ABORT 2 375 #define EXCPT_INTERRUPT 3 376 377 static int exception_type(int vector) 378 { 379 unsigned int mask; 380 381 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 382 return EXCPT_INTERRUPT; 383 384 mask = 1 << vector; 385 386 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 387 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 388 return EXCPT_TRAP; 389 390 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 391 return EXCPT_ABORT; 392 393 /* Reserved exceptions will result in fault */ 394 return EXCPT_FAULT; 395 } 396 397 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 398 unsigned nr, bool has_error, u32 error_code, 399 bool reinject) 400 { 401 u32 prev_nr; 402 int class1, class2; 403 404 kvm_make_request(KVM_REQ_EVENT, vcpu); 405 406 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 407 queue: 408 if (has_error && !is_protmode(vcpu)) 409 has_error = false; 410 if (reinject) { 411 /* 412 * On vmentry, vcpu->arch.exception.pending is only 413 * true if an event injection was blocked by 414 * nested_run_pending. In that case, however, 415 * vcpu_enter_guest requests an immediate exit, 416 * and the guest shouldn't proceed far enough to 417 * need reinjection. 418 */ 419 WARN_ON_ONCE(vcpu->arch.exception.pending); 420 vcpu->arch.exception.injected = true; 421 } else { 422 vcpu->arch.exception.pending = true; 423 vcpu->arch.exception.injected = false; 424 } 425 vcpu->arch.exception.has_error_code = has_error; 426 vcpu->arch.exception.nr = nr; 427 vcpu->arch.exception.error_code = error_code; 428 return; 429 } 430 431 /* to check exception */ 432 prev_nr = vcpu->arch.exception.nr; 433 if (prev_nr == DF_VECTOR) { 434 /* triple fault -> shutdown */ 435 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 436 return; 437 } 438 class1 = exception_class(prev_nr); 439 class2 = exception_class(nr); 440 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 441 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 442 /* 443 * Generate double fault per SDM Table 5-5. Set 444 * exception.pending = true so that the double fault 445 * can trigger a nested vmexit. 446 */ 447 vcpu->arch.exception.pending = true; 448 vcpu->arch.exception.injected = false; 449 vcpu->arch.exception.has_error_code = true; 450 vcpu->arch.exception.nr = DF_VECTOR; 451 vcpu->arch.exception.error_code = 0; 452 } else 453 /* replace previous exception with a new one in a hope 454 that instruction re-execution will regenerate lost 455 exception */ 456 goto queue; 457 } 458 459 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 460 { 461 kvm_multiple_exception(vcpu, nr, false, 0, false); 462 } 463 EXPORT_SYMBOL_GPL(kvm_queue_exception); 464 465 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 466 { 467 kvm_multiple_exception(vcpu, nr, false, 0, true); 468 } 469 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 470 471 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 472 { 473 if (err) 474 kvm_inject_gp(vcpu, 0); 475 else 476 return kvm_skip_emulated_instruction(vcpu); 477 478 return 1; 479 } 480 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 481 482 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 483 { 484 ++vcpu->stat.pf_guest; 485 vcpu->arch.exception.nested_apf = 486 is_guest_mode(vcpu) && fault->async_page_fault; 487 if (vcpu->arch.exception.nested_apf) 488 vcpu->arch.apf.nested_apf_token = fault->address; 489 else 490 vcpu->arch.cr2 = fault->address; 491 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 492 } 493 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 494 495 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 496 { 497 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 498 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 499 else 500 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 501 502 return fault->nested_page_fault; 503 } 504 505 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 506 { 507 atomic_inc(&vcpu->arch.nmi_queued); 508 kvm_make_request(KVM_REQ_NMI, vcpu); 509 } 510 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 511 512 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 513 { 514 kvm_multiple_exception(vcpu, nr, true, error_code, false); 515 } 516 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 517 518 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 519 { 520 kvm_multiple_exception(vcpu, nr, true, error_code, true); 521 } 522 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 523 524 /* 525 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 526 * a #GP and return false. 527 */ 528 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 529 { 530 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 531 return true; 532 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 533 return false; 534 } 535 EXPORT_SYMBOL_GPL(kvm_require_cpl); 536 537 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 538 { 539 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 540 return true; 541 542 kvm_queue_exception(vcpu, UD_VECTOR); 543 return false; 544 } 545 EXPORT_SYMBOL_GPL(kvm_require_dr); 546 547 /* 548 * This function will be used to read from the physical memory of the currently 549 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 550 * can read from guest physical or from the guest's guest physical memory. 551 */ 552 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 553 gfn_t ngfn, void *data, int offset, int len, 554 u32 access) 555 { 556 struct x86_exception exception; 557 gfn_t real_gfn; 558 gpa_t ngpa; 559 560 ngpa = gfn_to_gpa(ngfn); 561 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 562 if (real_gfn == UNMAPPED_GVA) 563 return -EFAULT; 564 565 real_gfn = gpa_to_gfn(real_gfn); 566 567 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 568 } 569 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 570 571 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 572 void *data, int offset, int len, u32 access) 573 { 574 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 575 data, offset, len, access); 576 } 577 578 /* 579 * Load the pae pdptrs. Return true is they are all valid. 580 */ 581 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 582 { 583 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 584 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 585 int i; 586 int ret; 587 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 588 589 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 590 offset * sizeof(u64), sizeof(pdpte), 591 PFERR_USER_MASK|PFERR_WRITE_MASK); 592 if (ret < 0) { 593 ret = 0; 594 goto out; 595 } 596 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 597 if ((pdpte[i] & PT_PRESENT_MASK) && 598 (pdpte[i] & 599 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) { 600 ret = 0; 601 goto out; 602 } 603 } 604 ret = 1; 605 606 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 607 __set_bit(VCPU_EXREG_PDPTR, 608 (unsigned long *)&vcpu->arch.regs_avail); 609 __set_bit(VCPU_EXREG_PDPTR, 610 (unsigned long *)&vcpu->arch.regs_dirty); 611 out: 612 613 return ret; 614 } 615 EXPORT_SYMBOL_GPL(load_pdptrs); 616 617 bool pdptrs_changed(struct kvm_vcpu *vcpu) 618 { 619 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 620 bool changed = true; 621 int offset; 622 gfn_t gfn; 623 int r; 624 625 if (is_long_mode(vcpu) || !is_pae(vcpu)) 626 return false; 627 628 if (!test_bit(VCPU_EXREG_PDPTR, 629 (unsigned long *)&vcpu->arch.regs_avail)) 630 return true; 631 632 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; 633 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); 634 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 635 PFERR_USER_MASK | PFERR_WRITE_MASK); 636 if (r < 0) 637 goto out; 638 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 639 out: 640 641 return changed; 642 } 643 EXPORT_SYMBOL_GPL(pdptrs_changed); 644 645 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 646 { 647 unsigned long old_cr0 = kvm_read_cr0(vcpu); 648 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 649 650 cr0 |= X86_CR0_ET; 651 652 #ifdef CONFIG_X86_64 653 if (cr0 & 0xffffffff00000000UL) 654 return 1; 655 #endif 656 657 cr0 &= ~CR0_RESERVED_BITS; 658 659 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 660 return 1; 661 662 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 663 return 1; 664 665 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 666 #ifdef CONFIG_X86_64 667 if ((vcpu->arch.efer & EFER_LME)) { 668 int cs_db, cs_l; 669 670 if (!is_pae(vcpu)) 671 return 1; 672 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 673 if (cs_l) 674 return 1; 675 } else 676 #endif 677 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 678 kvm_read_cr3(vcpu))) 679 return 1; 680 } 681 682 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 683 return 1; 684 685 kvm_x86_ops->set_cr0(vcpu, cr0); 686 687 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 688 kvm_clear_async_pf_completion_queue(vcpu); 689 kvm_async_pf_hash_reset(vcpu); 690 } 691 692 if ((cr0 ^ old_cr0) & update_bits) 693 kvm_mmu_reset_context(vcpu); 694 695 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 696 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 697 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 698 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 699 700 return 0; 701 } 702 EXPORT_SYMBOL_GPL(kvm_set_cr0); 703 704 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 705 { 706 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 707 } 708 EXPORT_SYMBOL_GPL(kvm_lmsw); 709 710 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 711 { 712 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 713 !vcpu->guest_xcr0_loaded) { 714 /* kvm_set_xcr() also depends on this */ 715 if (vcpu->arch.xcr0 != host_xcr0) 716 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 717 vcpu->guest_xcr0_loaded = 1; 718 } 719 } 720 721 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 722 { 723 if (vcpu->guest_xcr0_loaded) { 724 if (vcpu->arch.xcr0 != host_xcr0) 725 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 726 vcpu->guest_xcr0_loaded = 0; 727 } 728 } 729 730 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 731 { 732 u64 xcr0 = xcr; 733 u64 old_xcr0 = vcpu->arch.xcr0; 734 u64 valid_bits; 735 736 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 737 if (index != XCR_XFEATURE_ENABLED_MASK) 738 return 1; 739 if (!(xcr0 & XFEATURE_MASK_FP)) 740 return 1; 741 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 742 return 1; 743 744 /* 745 * Do not allow the guest to set bits that we do not support 746 * saving. However, xcr0 bit 0 is always set, even if the 747 * emulated CPU does not support XSAVE (see fx_init). 748 */ 749 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 750 if (xcr0 & ~valid_bits) 751 return 1; 752 753 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 754 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 755 return 1; 756 757 if (xcr0 & XFEATURE_MASK_AVX512) { 758 if (!(xcr0 & XFEATURE_MASK_YMM)) 759 return 1; 760 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 761 return 1; 762 } 763 vcpu->arch.xcr0 = xcr0; 764 765 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 766 kvm_update_cpuid(vcpu); 767 return 0; 768 } 769 770 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 771 { 772 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 773 __kvm_set_xcr(vcpu, index, xcr)) { 774 kvm_inject_gp(vcpu, 0); 775 return 1; 776 } 777 return 0; 778 } 779 EXPORT_SYMBOL_GPL(kvm_set_xcr); 780 781 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 782 { 783 unsigned long old_cr4 = kvm_read_cr4(vcpu); 784 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 785 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 786 787 if (cr4 & CR4_RESERVED_BITS) 788 return 1; 789 790 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE)) 791 return 1; 792 793 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP)) 794 return 1; 795 796 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP)) 797 return 1; 798 799 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE)) 800 return 1; 801 802 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE)) 803 return 1; 804 805 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57)) 806 return 1; 807 808 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP)) 809 return 1; 810 811 if (is_long_mode(vcpu)) { 812 if (!(cr4 & X86_CR4_PAE)) 813 return 1; 814 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 815 && ((cr4 ^ old_cr4) & pdptr_bits) 816 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 817 kvm_read_cr3(vcpu))) 818 return 1; 819 820 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 821 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 822 return 1; 823 824 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 825 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 826 return 1; 827 } 828 829 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 830 return 1; 831 832 if (((cr4 ^ old_cr4) & pdptr_bits) || 833 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 834 kvm_mmu_reset_context(vcpu); 835 836 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 837 kvm_update_cpuid(vcpu); 838 839 return 0; 840 } 841 EXPORT_SYMBOL_GPL(kvm_set_cr4); 842 843 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 844 { 845 #ifdef CONFIG_X86_64 846 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 847 848 if (pcid_enabled) 849 cr3 &= ~CR3_PCID_INVD; 850 #endif 851 852 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 853 kvm_mmu_sync_roots(vcpu); 854 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 855 return 0; 856 } 857 858 if (is_long_mode(vcpu) && 859 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62))) 860 return 1; 861 else if (is_pae(vcpu) && is_paging(vcpu) && 862 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 863 return 1; 864 865 vcpu->arch.cr3 = cr3; 866 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 867 kvm_mmu_new_cr3(vcpu); 868 return 0; 869 } 870 EXPORT_SYMBOL_GPL(kvm_set_cr3); 871 872 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 873 { 874 if (cr8 & CR8_RESERVED_BITS) 875 return 1; 876 if (lapic_in_kernel(vcpu)) 877 kvm_lapic_set_tpr(vcpu, cr8); 878 else 879 vcpu->arch.cr8 = cr8; 880 return 0; 881 } 882 EXPORT_SYMBOL_GPL(kvm_set_cr8); 883 884 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 885 { 886 if (lapic_in_kernel(vcpu)) 887 return kvm_lapic_get_cr8(vcpu); 888 else 889 return vcpu->arch.cr8; 890 } 891 EXPORT_SYMBOL_GPL(kvm_get_cr8); 892 893 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 894 { 895 int i; 896 897 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 898 for (i = 0; i < KVM_NR_DB_REGS; i++) 899 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 900 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 901 } 902 } 903 904 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 905 { 906 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 907 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 908 } 909 910 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 911 { 912 unsigned long dr7; 913 914 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 915 dr7 = vcpu->arch.guest_debug_dr7; 916 else 917 dr7 = vcpu->arch.dr7; 918 kvm_x86_ops->set_dr7(vcpu, dr7); 919 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 920 if (dr7 & DR7_BP_EN_MASK) 921 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 922 } 923 924 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 925 { 926 u64 fixed = DR6_FIXED_1; 927 928 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 929 fixed |= DR6_RTM; 930 return fixed; 931 } 932 933 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 934 { 935 switch (dr) { 936 case 0 ... 3: 937 vcpu->arch.db[dr] = val; 938 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 939 vcpu->arch.eff_db[dr] = val; 940 break; 941 case 4: 942 /* fall through */ 943 case 6: 944 if (val & 0xffffffff00000000ULL) 945 return -1; /* #GP */ 946 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 947 kvm_update_dr6(vcpu); 948 break; 949 case 5: 950 /* fall through */ 951 default: /* 7 */ 952 if (val & 0xffffffff00000000ULL) 953 return -1; /* #GP */ 954 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 955 kvm_update_dr7(vcpu); 956 break; 957 } 958 959 return 0; 960 } 961 962 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 963 { 964 if (__kvm_set_dr(vcpu, dr, val)) { 965 kvm_inject_gp(vcpu, 0); 966 return 1; 967 } 968 return 0; 969 } 970 EXPORT_SYMBOL_GPL(kvm_set_dr); 971 972 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 973 { 974 switch (dr) { 975 case 0 ... 3: 976 *val = vcpu->arch.db[dr]; 977 break; 978 case 4: 979 /* fall through */ 980 case 6: 981 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 982 *val = vcpu->arch.dr6; 983 else 984 *val = kvm_x86_ops->get_dr6(vcpu); 985 break; 986 case 5: 987 /* fall through */ 988 default: /* 7 */ 989 *val = vcpu->arch.dr7; 990 break; 991 } 992 return 0; 993 } 994 EXPORT_SYMBOL_GPL(kvm_get_dr); 995 996 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 997 { 998 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 999 u64 data; 1000 int err; 1001 1002 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 1003 if (err) 1004 return err; 1005 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 1006 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 1007 return err; 1008 } 1009 EXPORT_SYMBOL_GPL(kvm_rdpmc); 1010 1011 /* 1012 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1013 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1014 * 1015 * This list is modified at module load time to reflect the 1016 * capabilities of the host cpu. This capabilities test skips MSRs that are 1017 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs 1018 * may depend on host virtualization features rather than host cpu features. 1019 */ 1020 1021 static u32 msrs_to_save[] = { 1022 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1023 MSR_STAR, 1024 #ifdef CONFIG_X86_64 1025 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1026 #endif 1027 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1028 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1029 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES 1030 }; 1031 1032 static unsigned num_msrs_to_save; 1033 1034 static u32 emulated_msrs[] = { 1035 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1036 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1037 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1038 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1039 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1040 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1041 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1042 HV_X64_MSR_RESET, 1043 HV_X64_MSR_VP_INDEX, 1044 HV_X64_MSR_VP_RUNTIME, 1045 HV_X64_MSR_SCONTROL, 1046 HV_X64_MSR_STIMER0_CONFIG, 1047 HV_X64_MSR_VP_ASSIST_PAGE, 1048 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1049 HV_X64_MSR_TSC_EMULATION_STATUS, 1050 1051 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1052 MSR_KVM_PV_EOI_EN, 1053 1054 MSR_IA32_TSC_ADJUST, 1055 MSR_IA32_TSCDEADLINE, 1056 MSR_IA32_MISC_ENABLE, 1057 MSR_IA32_MCG_STATUS, 1058 MSR_IA32_MCG_CTL, 1059 MSR_IA32_MCG_EXT_CTL, 1060 MSR_IA32_SMBASE, 1061 MSR_SMI_COUNT, 1062 MSR_PLATFORM_INFO, 1063 MSR_MISC_FEATURES_ENABLES, 1064 }; 1065 1066 static unsigned num_emulated_msrs; 1067 1068 /* 1069 * List of msr numbers which are used to expose MSR-based features that 1070 * can be used by a hypervisor to validate requested CPU features. 1071 */ 1072 static u32 msr_based_features[] = { 1073 MSR_IA32_VMX_BASIC, 1074 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1075 MSR_IA32_VMX_PINBASED_CTLS, 1076 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1077 MSR_IA32_VMX_PROCBASED_CTLS, 1078 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1079 MSR_IA32_VMX_EXIT_CTLS, 1080 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1081 MSR_IA32_VMX_ENTRY_CTLS, 1082 MSR_IA32_VMX_MISC, 1083 MSR_IA32_VMX_CR0_FIXED0, 1084 MSR_IA32_VMX_CR0_FIXED1, 1085 MSR_IA32_VMX_CR4_FIXED0, 1086 MSR_IA32_VMX_CR4_FIXED1, 1087 MSR_IA32_VMX_VMCS_ENUM, 1088 MSR_IA32_VMX_PROCBASED_CTLS2, 1089 MSR_IA32_VMX_EPT_VPID_CAP, 1090 MSR_IA32_VMX_VMFUNC, 1091 1092 MSR_F10H_DECFG, 1093 MSR_IA32_UCODE_REV, 1094 }; 1095 1096 static unsigned int num_msr_based_features; 1097 1098 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1099 { 1100 switch (msr->index) { 1101 case MSR_IA32_UCODE_REV: 1102 rdmsrl(msr->index, msr->data); 1103 break; 1104 default: 1105 if (kvm_x86_ops->get_msr_feature(msr)) 1106 return 1; 1107 } 1108 return 0; 1109 } 1110 1111 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1112 { 1113 struct kvm_msr_entry msr; 1114 int r; 1115 1116 msr.index = index; 1117 r = kvm_get_msr_feature(&msr); 1118 if (r) 1119 return r; 1120 1121 *data = msr.data; 1122 1123 return 0; 1124 } 1125 1126 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1127 { 1128 if (efer & efer_reserved_bits) 1129 return false; 1130 1131 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1132 return false; 1133 1134 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1135 return false; 1136 1137 return true; 1138 } 1139 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1140 1141 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 1142 { 1143 u64 old_efer = vcpu->arch.efer; 1144 1145 if (!kvm_valid_efer(vcpu, efer)) 1146 return 1; 1147 1148 if (is_paging(vcpu) 1149 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1150 return 1; 1151 1152 efer &= ~EFER_LMA; 1153 efer |= vcpu->arch.efer & EFER_LMA; 1154 1155 kvm_x86_ops->set_efer(vcpu, efer); 1156 1157 /* Update reserved bits */ 1158 if ((efer ^ old_efer) & EFER_NX) 1159 kvm_mmu_reset_context(vcpu); 1160 1161 return 0; 1162 } 1163 1164 void kvm_enable_efer_bits(u64 mask) 1165 { 1166 efer_reserved_bits &= ~mask; 1167 } 1168 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1169 1170 /* 1171 * Writes msr value into into the appropriate "register". 1172 * Returns 0 on success, non-0 otherwise. 1173 * Assumes vcpu_load() was already called. 1174 */ 1175 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1176 { 1177 switch (msr->index) { 1178 case MSR_FS_BASE: 1179 case MSR_GS_BASE: 1180 case MSR_KERNEL_GS_BASE: 1181 case MSR_CSTAR: 1182 case MSR_LSTAR: 1183 if (is_noncanonical_address(msr->data, vcpu)) 1184 return 1; 1185 break; 1186 case MSR_IA32_SYSENTER_EIP: 1187 case MSR_IA32_SYSENTER_ESP: 1188 /* 1189 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1190 * non-canonical address is written on Intel but not on 1191 * AMD (which ignores the top 32-bits, because it does 1192 * not implement 64-bit SYSENTER). 1193 * 1194 * 64-bit code should hence be able to write a non-canonical 1195 * value on AMD. Making the address canonical ensures that 1196 * vmentry does not fail on Intel after writing a non-canonical 1197 * value, and that something deterministic happens if the guest 1198 * invokes 64-bit SYSENTER. 1199 */ 1200 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu)); 1201 } 1202 return kvm_x86_ops->set_msr(vcpu, msr); 1203 } 1204 EXPORT_SYMBOL_GPL(kvm_set_msr); 1205 1206 /* 1207 * Adapt set_msr() to msr_io()'s calling convention 1208 */ 1209 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1210 { 1211 struct msr_data msr; 1212 int r; 1213 1214 msr.index = index; 1215 msr.host_initiated = true; 1216 r = kvm_get_msr(vcpu, &msr); 1217 if (r) 1218 return r; 1219 1220 *data = msr.data; 1221 return 0; 1222 } 1223 1224 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1225 { 1226 struct msr_data msr; 1227 1228 msr.data = *data; 1229 msr.index = index; 1230 msr.host_initiated = true; 1231 return kvm_set_msr(vcpu, &msr); 1232 } 1233 1234 #ifdef CONFIG_X86_64 1235 struct pvclock_gtod_data { 1236 seqcount_t seq; 1237 1238 struct { /* extract of a clocksource struct */ 1239 int vclock_mode; 1240 u64 cycle_last; 1241 u64 mask; 1242 u32 mult; 1243 u32 shift; 1244 } clock; 1245 1246 u64 boot_ns; 1247 u64 nsec_base; 1248 u64 wall_time_sec; 1249 }; 1250 1251 static struct pvclock_gtod_data pvclock_gtod_data; 1252 1253 static void update_pvclock_gtod(struct timekeeper *tk) 1254 { 1255 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1256 u64 boot_ns; 1257 1258 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1259 1260 write_seqcount_begin(&vdata->seq); 1261 1262 /* copy pvclock gtod data */ 1263 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1264 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1265 vdata->clock.mask = tk->tkr_mono.mask; 1266 vdata->clock.mult = tk->tkr_mono.mult; 1267 vdata->clock.shift = tk->tkr_mono.shift; 1268 1269 vdata->boot_ns = boot_ns; 1270 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1271 1272 vdata->wall_time_sec = tk->xtime_sec; 1273 1274 write_seqcount_end(&vdata->seq); 1275 } 1276 #endif 1277 1278 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1279 { 1280 /* 1281 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1282 * vcpu_enter_guest. This function is only called from 1283 * the physical CPU that is running vcpu. 1284 */ 1285 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1286 } 1287 1288 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1289 { 1290 int version; 1291 int r; 1292 struct pvclock_wall_clock wc; 1293 struct timespec64 boot; 1294 1295 if (!wall_clock) 1296 return; 1297 1298 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1299 if (r) 1300 return; 1301 1302 if (version & 1) 1303 ++version; /* first time write, random junk */ 1304 1305 ++version; 1306 1307 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1308 return; 1309 1310 /* 1311 * The guest calculates current wall clock time by adding 1312 * system time (updated by kvm_guest_time_update below) to the 1313 * wall clock specified here. guest system time equals host 1314 * system time for us, thus we must fill in host boot time here. 1315 */ 1316 getboottime64(&boot); 1317 1318 if (kvm->arch.kvmclock_offset) { 1319 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset); 1320 boot = timespec64_sub(boot, ts); 1321 } 1322 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */ 1323 wc.nsec = boot.tv_nsec; 1324 wc.version = version; 1325 1326 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1327 1328 version++; 1329 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1330 } 1331 1332 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1333 { 1334 do_shl32_div32(dividend, divisor); 1335 return dividend; 1336 } 1337 1338 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 1339 s8 *pshift, u32 *pmultiplier) 1340 { 1341 uint64_t scaled64; 1342 int32_t shift = 0; 1343 uint64_t tps64; 1344 uint32_t tps32; 1345 1346 tps64 = base_hz; 1347 scaled64 = scaled_hz; 1348 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1349 tps64 >>= 1; 1350 shift--; 1351 } 1352 1353 tps32 = (uint32_t)tps64; 1354 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1355 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1356 scaled64 >>= 1; 1357 else 1358 tps32 <<= 1; 1359 shift++; 1360 } 1361 1362 *pshift = shift; 1363 *pmultiplier = div_frac(scaled64, tps32); 1364 1365 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n", 1366 __func__, base_hz, scaled_hz, shift, *pmultiplier); 1367 } 1368 1369 #ifdef CONFIG_X86_64 1370 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1371 #endif 1372 1373 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1374 static unsigned long max_tsc_khz; 1375 1376 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1377 { 1378 u64 v = (u64)khz * (1000000 + ppm); 1379 do_div(v, 1000000); 1380 return v; 1381 } 1382 1383 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 1384 { 1385 u64 ratio; 1386 1387 /* Guest TSC same frequency as host TSC? */ 1388 if (!scale) { 1389 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1390 return 0; 1391 } 1392 1393 /* TSC scaling supported? */ 1394 if (!kvm_has_tsc_control) { 1395 if (user_tsc_khz > tsc_khz) { 1396 vcpu->arch.tsc_catchup = 1; 1397 vcpu->arch.tsc_always_catchup = 1; 1398 return 0; 1399 } else { 1400 WARN(1, "user requested TSC rate below hardware speed\n"); 1401 return -1; 1402 } 1403 } 1404 1405 /* TSC scaling required - calculate ratio */ 1406 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 1407 user_tsc_khz, tsc_khz); 1408 1409 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 1410 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 1411 user_tsc_khz); 1412 return -1; 1413 } 1414 1415 vcpu->arch.tsc_scaling_ratio = ratio; 1416 return 0; 1417 } 1418 1419 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 1420 { 1421 u32 thresh_lo, thresh_hi; 1422 int use_scaling = 0; 1423 1424 /* tsc_khz can be zero if TSC calibration fails */ 1425 if (user_tsc_khz == 0) { 1426 /* set tsc_scaling_ratio to a safe value */ 1427 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1428 return -1; 1429 } 1430 1431 /* Compute a scale to convert nanoseconds in TSC cycles */ 1432 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 1433 &vcpu->arch.virtual_tsc_shift, 1434 &vcpu->arch.virtual_tsc_mult); 1435 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 1436 1437 /* 1438 * Compute the variation in TSC rate which is acceptable 1439 * within the range of tolerance and decide if the 1440 * rate being applied is within that bounds of the hardware 1441 * rate. If so, no scaling or compensation need be done. 1442 */ 1443 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1444 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1445 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 1446 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 1447 use_scaling = 1; 1448 } 1449 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 1450 } 1451 1452 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1453 { 1454 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1455 vcpu->arch.virtual_tsc_mult, 1456 vcpu->arch.virtual_tsc_shift); 1457 tsc += vcpu->arch.this_tsc_write; 1458 return tsc; 1459 } 1460 1461 static inline int gtod_is_based_on_tsc(int mode) 1462 { 1463 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK; 1464 } 1465 1466 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1467 { 1468 #ifdef CONFIG_X86_64 1469 bool vcpus_matched; 1470 struct kvm_arch *ka = &vcpu->kvm->arch; 1471 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1472 1473 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1474 atomic_read(&vcpu->kvm->online_vcpus)); 1475 1476 /* 1477 * Once the masterclock is enabled, always perform request in 1478 * order to update it. 1479 * 1480 * In order to enable masterclock, the host clocksource must be TSC 1481 * and the vcpus need to have matched TSCs. When that happens, 1482 * perform request to enable masterclock. 1483 */ 1484 if (ka->use_master_clock || 1485 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 1486 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1487 1488 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1489 atomic_read(&vcpu->kvm->online_vcpus), 1490 ka->use_master_clock, gtod->clock.vclock_mode); 1491 #endif 1492 } 1493 1494 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1495 { 1496 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); 1497 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1498 } 1499 1500 /* 1501 * Multiply tsc by a fixed point number represented by ratio. 1502 * 1503 * The most significant 64-N bits (mult) of ratio represent the 1504 * integral part of the fixed point number; the remaining N bits 1505 * (frac) represent the fractional part, ie. ratio represents a fixed 1506 * point number (mult + frac * 2^(-N)). 1507 * 1508 * N equals to kvm_tsc_scaling_ratio_frac_bits. 1509 */ 1510 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 1511 { 1512 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 1513 } 1514 1515 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 1516 { 1517 u64 _tsc = tsc; 1518 u64 ratio = vcpu->arch.tsc_scaling_ratio; 1519 1520 if (ratio != kvm_default_tsc_scaling_ratio) 1521 _tsc = __scale_tsc(ratio, tsc); 1522 1523 return _tsc; 1524 } 1525 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 1526 1527 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 1528 { 1529 u64 tsc; 1530 1531 tsc = kvm_scale_tsc(vcpu, rdtsc()); 1532 1533 return target_tsc - tsc; 1534 } 1535 1536 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 1537 { 1538 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); 1539 1540 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc); 1541 } 1542 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 1543 1544 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1545 { 1546 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1547 vcpu->arch.tsc_offset = offset; 1548 } 1549 1550 static inline bool kvm_check_tsc_unstable(void) 1551 { 1552 #ifdef CONFIG_X86_64 1553 /* 1554 * TSC is marked unstable when we're running on Hyper-V, 1555 * 'TSC page' clocksource is good. 1556 */ 1557 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK) 1558 return false; 1559 #endif 1560 return check_tsc_unstable(); 1561 } 1562 1563 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1564 { 1565 struct kvm *kvm = vcpu->kvm; 1566 u64 offset, ns, elapsed; 1567 unsigned long flags; 1568 bool matched; 1569 bool already_matched; 1570 u64 data = msr->data; 1571 bool synchronizing = false; 1572 1573 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1574 offset = kvm_compute_tsc_offset(vcpu, data); 1575 ns = ktime_get_boot_ns(); 1576 elapsed = ns - kvm->arch.last_tsc_nsec; 1577 1578 if (vcpu->arch.virtual_tsc_khz) { 1579 if (data == 0 && msr->host_initiated) { 1580 /* 1581 * detection of vcpu initialization -- need to sync 1582 * with other vCPUs. This particularly helps to keep 1583 * kvm_clock stable after CPU hotplug 1584 */ 1585 synchronizing = true; 1586 } else { 1587 u64 tsc_exp = kvm->arch.last_tsc_write + 1588 nsec_to_cycles(vcpu, elapsed); 1589 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 1590 /* 1591 * Special case: TSC write with a small delta (1 second) 1592 * of virtual cycle time against real time is 1593 * interpreted as an attempt to synchronize the CPU. 1594 */ 1595 synchronizing = data < tsc_exp + tsc_hz && 1596 data + tsc_hz > tsc_exp; 1597 } 1598 } 1599 1600 /* 1601 * For a reliable TSC, we can match TSC offsets, and for an unstable 1602 * TSC, we add elapsed time in this computation. We could let the 1603 * compensation code attempt to catch up if we fall behind, but 1604 * it's better to try to match offsets from the beginning. 1605 */ 1606 if (synchronizing && 1607 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1608 if (!kvm_check_tsc_unstable()) { 1609 offset = kvm->arch.cur_tsc_offset; 1610 pr_debug("kvm: matched tsc offset for %llu\n", data); 1611 } else { 1612 u64 delta = nsec_to_cycles(vcpu, elapsed); 1613 data += delta; 1614 offset = kvm_compute_tsc_offset(vcpu, data); 1615 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1616 } 1617 matched = true; 1618 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1619 } else { 1620 /* 1621 * We split periods of matched TSC writes into generations. 1622 * For each generation, we track the original measured 1623 * nanosecond time, offset, and write, so if TSCs are in 1624 * sync, we can match exact offset, and if not, we can match 1625 * exact software computation in compute_guest_tsc() 1626 * 1627 * These values are tracked in kvm->arch.cur_xxx variables. 1628 */ 1629 kvm->arch.cur_tsc_generation++; 1630 kvm->arch.cur_tsc_nsec = ns; 1631 kvm->arch.cur_tsc_write = data; 1632 kvm->arch.cur_tsc_offset = offset; 1633 matched = false; 1634 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1635 kvm->arch.cur_tsc_generation, data); 1636 } 1637 1638 /* 1639 * We also track th most recent recorded KHZ, write and time to 1640 * allow the matching interval to be extended at each write. 1641 */ 1642 kvm->arch.last_tsc_nsec = ns; 1643 kvm->arch.last_tsc_write = data; 1644 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1645 1646 vcpu->arch.last_guest_tsc = data; 1647 1648 /* Keep track of which generation this VCPU has synchronized to */ 1649 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1650 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1651 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1652 1653 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) 1654 update_ia32_tsc_adjust_msr(vcpu, offset); 1655 1656 kvm_vcpu_write_tsc_offset(vcpu, offset); 1657 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1658 1659 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1660 if (!matched) { 1661 kvm->arch.nr_vcpus_matched_tsc = 0; 1662 } else if (!already_matched) { 1663 kvm->arch.nr_vcpus_matched_tsc++; 1664 } 1665 1666 kvm_track_tsc_matching(vcpu); 1667 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1668 } 1669 1670 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1671 1672 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 1673 s64 adjustment) 1674 { 1675 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment); 1676 } 1677 1678 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 1679 { 1680 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 1681 WARN_ON(adjustment < 0); 1682 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 1683 adjust_tsc_offset_guest(vcpu, adjustment); 1684 } 1685 1686 #ifdef CONFIG_X86_64 1687 1688 static u64 read_tsc(void) 1689 { 1690 u64 ret = (u64)rdtsc_ordered(); 1691 u64 last = pvclock_gtod_data.clock.cycle_last; 1692 1693 if (likely(ret >= last)) 1694 return ret; 1695 1696 /* 1697 * GCC likes to generate cmov here, but this branch is extremely 1698 * predictable (it's just a function of time and the likely is 1699 * very likely) and there's a data dependence, so force GCC 1700 * to generate a branch instead. I don't barrier() because 1701 * we don't actually need a barrier, and if this function 1702 * ever gets inlined it will generate worse code. 1703 */ 1704 asm volatile (""); 1705 return last; 1706 } 1707 1708 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode) 1709 { 1710 long v; 1711 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1712 u64 tsc_pg_val; 1713 1714 switch (gtod->clock.vclock_mode) { 1715 case VCLOCK_HVCLOCK: 1716 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 1717 tsc_timestamp); 1718 if (tsc_pg_val != U64_MAX) { 1719 /* TSC page valid */ 1720 *mode = VCLOCK_HVCLOCK; 1721 v = (tsc_pg_val - gtod->clock.cycle_last) & 1722 gtod->clock.mask; 1723 } else { 1724 /* TSC page invalid */ 1725 *mode = VCLOCK_NONE; 1726 } 1727 break; 1728 case VCLOCK_TSC: 1729 *mode = VCLOCK_TSC; 1730 *tsc_timestamp = read_tsc(); 1731 v = (*tsc_timestamp - gtod->clock.cycle_last) & 1732 gtod->clock.mask; 1733 break; 1734 default: 1735 *mode = VCLOCK_NONE; 1736 } 1737 1738 if (*mode == VCLOCK_NONE) 1739 *tsc_timestamp = v = 0; 1740 1741 return v * gtod->clock.mult; 1742 } 1743 1744 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp) 1745 { 1746 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1747 unsigned long seq; 1748 int mode; 1749 u64 ns; 1750 1751 do { 1752 seq = read_seqcount_begin(>od->seq); 1753 ns = gtod->nsec_base; 1754 ns += vgettsc(tsc_timestamp, &mode); 1755 ns >>= gtod->clock.shift; 1756 ns += gtod->boot_ns; 1757 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1758 *t = ns; 1759 1760 return mode; 1761 } 1762 1763 static int do_realtime(struct timespec *ts, u64 *tsc_timestamp) 1764 { 1765 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1766 unsigned long seq; 1767 int mode; 1768 u64 ns; 1769 1770 do { 1771 seq = read_seqcount_begin(>od->seq); 1772 ts->tv_sec = gtod->wall_time_sec; 1773 ns = gtod->nsec_base; 1774 ns += vgettsc(tsc_timestamp, &mode); 1775 ns >>= gtod->clock.shift; 1776 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1777 1778 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 1779 ts->tv_nsec = ns; 1780 1781 return mode; 1782 } 1783 1784 /* returns true if host is using TSC based clocksource */ 1785 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 1786 { 1787 /* checked again under seqlock below */ 1788 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 1789 return false; 1790 1791 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns, 1792 tsc_timestamp)); 1793 } 1794 1795 /* returns true if host is using TSC based clocksource */ 1796 static bool kvm_get_walltime_and_clockread(struct timespec *ts, 1797 u64 *tsc_timestamp) 1798 { 1799 /* checked again under seqlock below */ 1800 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 1801 return false; 1802 1803 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 1804 } 1805 #endif 1806 1807 /* 1808 * 1809 * Assuming a stable TSC across physical CPUS, and a stable TSC 1810 * across virtual CPUs, the following condition is possible. 1811 * Each numbered line represents an event visible to both 1812 * CPUs at the next numbered event. 1813 * 1814 * "timespecX" represents host monotonic time. "tscX" represents 1815 * RDTSC value. 1816 * 1817 * VCPU0 on CPU0 | VCPU1 on CPU1 1818 * 1819 * 1. read timespec0,tsc0 1820 * 2. | timespec1 = timespec0 + N 1821 * | tsc1 = tsc0 + M 1822 * 3. transition to guest | transition to guest 1823 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1824 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1825 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1826 * 1827 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1828 * 1829 * - ret0 < ret1 1830 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1831 * ... 1832 * - 0 < N - M => M < N 1833 * 1834 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1835 * always the case (the difference between two distinct xtime instances 1836 * might be smaller then the difference between corresponding TSC reads, 1837 * when updating guest vcpus pvclock areas). 1838 * 1839 * To avoid that problem, do not allow visibility of distinct 1840 * system_timestamp/tsc_timestamp values simultaneously: use a master 1841 * copy of host monotonic time values. Update that master copy 1842 * in lockstep. 1843 * 1844 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1845 * 1846 */ 1847 1848 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1849 { 1850 #ifdef CONFIG_X86_64 1851 struct kvm_arch *ka = &kvm->arch; 1852 int vclock_mode; 1853 bool host_tsc_clocksource, vcpus_matched; 1854 1855 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1856 atomic_read(&kvm->online_vcpus)); 1857 1858 /* 1859 * If the host uses TSC clock, then passthrough TSC as stable 1860 * to the guest. 1861 */ 1862 host_tsc_clocksource = kvm_get_time_and_clockread( 1863 &ka->master_kernel_ns, 1864 &ka->master_cycle_now); 1865 1866 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 1867 && !ka->backwards_tsc_observed 1868 && !ka->boot_vcpu_runs_old_kvmclock; 1869 1870 if (ka->use_master_clock) 1871 atomic_set(&kvm_guest_has_master_clock, 1); 1872 1873 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1874 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1875 vcpus_matched); 1876 #endif 1877 } 1878 1879 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 1880 { 1881 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 1882 } 1883 1884 static void kvm_gen_update_masterclock(struct kvm *kvm) 1885 { 1886 #ifdef CONFIG_X86_64 1887 int i; 1888 struct kvm_vcpu *vcpu; 1889 struct kvm_arch *ka = &kvm->arch; 1890 1891 spin_lock(&ka->pvclock_gtod_sync_lock); 1892 kvm_make_mclock_inprogress_request(kvm); 1893 /* no guest entries from this point */ 1894 pvclock_update_vm_gtod_copy(kvm); 1895 1896 kvm_for_each_vcpu(i, vcpu, kvm) 1897 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1898 1899 /* guest entries allowed */ 1900 kvm_for_each_vcpu(i, vcpu, kvm) 1901 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 1902 1903 spin_unlock(&ka->pvclock_gtod_sync_lock); 1904 #endif 1905 } 1906 1907 u64 get_kvmclock_ns(struct kvm *kvm) 1908 { 1909 struct kvm_arch *ka = &kvm->arch; 1910 struct pvclock_vcpu_time_info hv_clock; 1911 u64 ret; 1912 1913 spin_lock(&ka->pvclock_gtod_sync_lock); 1914 if (!ka->use_master_clock) { 1915 spin_unlock(&ka->pvclock_gtod_sync_lock); 1916 return ktime_get_boot_ns() + ka->kvmclock_offset; 1917 } 1918 1919 hv_clock.tsc_timestamp = ka->master_cycle_now; 1920 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 1921 spin_unlock(&ka->pvclock_gtod_sync_lock); 1922 1923 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 1924 get_cpu(); 1925 1926 if (__this_cpu_read(cpu_tsc_khz)) { 1927 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 1928 &hv_clock.tsc_shift, 1929 &hv_clock.tsc_to_system_mul); 1930 ret = __pvclock_read_cycles(&hv_clock, rdtsc()); 1931 } else 1932 ret = ktime_get_boot_ns() + ka->kvmclock_offset; 1933 1934 put_cpu(); 1935 1936 return ret; 1937 } 1938 1939 static void kvm_setup_pvclock_page(struct kvm_vcpu *v) 1940 { 1941 struct kvm_vcpu_arch *vcpu = &v->arch; 1942 struct pvclock_vcpu_time_info guest_hv_clock; 1943 1944 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1945 &guest_hv_clock, sizeof(guest_hv_clock)))) 1946 return; 1947 1948 /* This VCPU is paused, but it's legal for a guest to read another 1949 * VCPU's kvmclock, so we really have to follow the specification where 1950 * it says that version is odd if data is being modified, and even after 1951 * it is consistent. 1952 * 1953 * Version field updates must be kept separate. This is because 1954 * kvm_write_guest_cached might use a "rep movs" instruction, and 1955 * writes within a string instruction are weakly ordered. So there 1956 * are three writes overall. 1957 * 1958 * As a small optimization, only write the version field in the first 1959 * and third write. The vcpu->pv_time cache is still valid, because the 1960 * version field is the first in the struct. 1961 */ 1962 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 1963 1964 if (guest_hv_clock.version & 1) 1965 ++guest_hv_clock.version; /* first time write, random junk */ 1966 1967 vcpu->hv_clock.version = guest_hv_clock.version + 1; 1968 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1969 &vcpu->hv_clock, 1970 sizeof(vcpu->hv_clock.version)); 1971 1972 smp_wmb(); 1973 1974 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1975 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1976 1977 if (vcpu->pvclock_set_guest_stopped_request) { 1978 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 1979 vcpu->pvclock_set_guest_stopped_request = false; 1980 } 1981 1982 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 1983 1984 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1985 &vcpu->hv_clock, 1986 sizeof(vcpu->hv_clock)); 1987 1988 smp_wmb(); 1989 1990 vcpu->hv_clock.version++; 1991 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1992 &vcpu->hv_clock, 1993 sizeof(vcpu->hv_clock.version)); 1994 } 1995 1996 static int kvm_guest_time_update(struct kvm_vcpu *v) 1997 { 1998 unsigned long flags, tgt_tsc_khz; 1999 struct kvm_vcpu_arch *vcpu = &v->arch; 2000 struct kvm_arch *ka = &v->kvm->arch; 2001 s64 kernel_ns; 2002 u64 tsc_timestamp, host_tsc; 2003 u8 pvclock_flags; 2004 bool use_master_clock; 2005 2006 kernel_ns = 0; 2007 host_tsc = 0; 2008 2009 /* 2010 * If the host uses TSC clock, then passthrough TSC as stable 2011 * to the guest. 2012 */ 2013 spin_lock(&ka->pvclock_gtod_sync_lock); 2014 use_master_clock = ka->use_master_clock; 2015 if (use_master_clock) { 2016 host_tsc = ka->master_cycle_now; 2017 kernel_ns = ka->master_kernel_ns; 2018 } 2019 spin_unlock(&ka->pvclock_gtod_sync_lock); 2020 2021 /* Keep irq disabled to prevent changes to the clock */ 2022 local_irq_save(flags); 2023 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 2024 if (unlikely(tgt_tsc_khz == 0)) { 2025 local_irq_restore(flags); 2026 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2027 return 1; 2028 } 2029 if (!use_master_clock) { 2030 host_tsc = rdtsc(); 2031 kernel_ns = ktime_get_boot_ns(); 2032 } 2033 2034 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 2035 2036 /* 2037 * We may have to catch up the TSC to match elapsed wall clock 2038 * time for two reasons, even if kvmclock is used. 2039 * 1) CPU could have been running below the maximum TSC rate 2040 * 2) Broken TSC compensation resets the base at each VCPU 2041 * entry to avoid unknown leaps of TSC even when running 2042 * again on the same CPU. This may cause apparent elapsed 2043 * time to disappear, and the guest to stand still or run 2044 * very slowly. 2045 */ 2046 if (vcpu->tsc_catchup) { 2047 u64 tsc = compute_guest_tsc(v, kernel_ns); 2048 if (tsc > tsc_timestamp) { 2049 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 2050 tsc_timestamp = tsc; 2051 } 2052 } 2053 2054 local_irq_restore(flags); 2055 2056 /* With all the info we got, fill in the values */ 2057 2058 if (kvm_has_tsc_control) 2059 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 2060 2061 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 2062 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 2063 &vcpu->hv_clock.tsc_shift, 2064 &vcpu->hv_clock.tsc_to_system_mul); 2065 vcpu->hw_tsc_khz = tgt_tsc_khz; 2066 } 2067 2068 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 2069 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 2070 vcpu->last_guest_tsc = tsc_timestamp; 2071 2072 /* If the host uses TSC clocksource, then it is stable */ 2073 pvclock_flags = 0; 2074 if (use_master_clock) 2075 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 2076 2077 vcpu->hv_clock.flags = pvclock_flags; 2078 2079 if (vcpu->pv_time_enabled) 2080 kvm_setup_pvclock_page(v); 2081 if (v == kvm_get_vcpu(v->kvm, 0)) 2082 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 2083 return 0; 2084 } 2085 2086 /* 2087 * kvmclock updates which are isolated to a given vcpu, such as 2088 * vcpu->cpu migration, should not allow system_timestamp from 2089 * the rest of the vcpus to remain static. Otherwise ntp frequency 2090 * correction applies to one vcpu's system_timestamp but not 2091 * the others. 2092 * 2093 * So in those cases, request a kvmclock update for all vcpus. 2094 * We need to rate-limit these requests though, as they can 2095 * considerably slow guests that have a large number of vcpus. 2096 * The time for a remote vcpu to update its kvmclock is bound 2097 * by the delay we use to rate-limit the updates. 2098 */ 2099 2100 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 2101 2102 static void kvmclock_update_fn(struct work_struct *work) 2103 { 2104 int i; 2105 struct delayed_work *dwork = to_delayed_work(work); 2106 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2107 kvmclock_update_work); 2108 struct kvm *kvm = container_of(ka, struct kvm, arch); 2109 struct kvm_vcpu *vcpu; 2110 2111 kvm_for_each_vcpu(i, vcpu, kvm) { 2112 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2113 kvm_vcpu_kick(vcpu); 2114 } 2115 } 2116 2117 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 2118 { 2119 struct kvm *kvm = v->kvm; 2120 2121 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2122 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 2123 KVMCLOCK_UPDATE_DELAY); 2124 } 2125 2126 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 2127 2128 static void kvmclock_sync_fn(struct work_struct *work) 2129 { 2130 struct delayed_work *dwork = to_delayed_work(work); 2131 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2132 kvmclock_sync_work); 2133 struct kvm *kvm = container_of(ka, struct kvm, arch); 2134 2135 if (!kvmclock_periodic_sync) 2136 return; 2137 2138 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 2139 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 2140 KVMCLOCK_SYNC_PERIOD); 2141 } 2142 2143 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2144 { 2145 u64 mcg_cap = vcpu->arch.mcg_cap; 2146 unsigned bank_num = mcg_cap & 0xff; 2147 u32 msr = msr_info->index; 2148 u64 data = msr_info->data; 2149 2150 switch (msr) { 2151 case MSR_IA32_MCG_STATUS: 2152 vcpu->arch.mcg_status = data; 2153 break; 2154 case MSR_IA32_MCG_CTL: 2155 if (!(mcg_cap & MCG_CTL_P)) 2156 return 1; 2157 if (data != 0 && data != ~(u64)0) 2158 return -1; 2159 vcpu->arch.mcg_ctl = data; 2160 break; 2161 default: 2162 if (msr >= MSR_IA32_MC0_CTL && 2163 msr < MSR_IA32_MCx_CTL(bank_num)) { 2164 u32 offset = msr - MSR_IA32_MC0_CTL; 2165 /* only 0 or all 1s can be written to IA32_MCi_CTL 2166 * some Linux kernels though clear bit 10 in bank 4 to 2167 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 2168 * this to avoid an uncatched #GP in the guest 2169 */ 2170 if ((offset & 0x3) == 0 && 2171 data != 0 && (data | (1 << 10)) != ~(u64)0) 2172 return -1; 2173 if (!msr_info->host_initiated && 2174 (offset & 0x3) == 1 && data != 0) 2175 return -1; 2176 vcpu->arch.mce_banks[offset] = data; 2177 break; 2178 } 2179 return 1; 2180 } 2181 return 0; 2182 } 2183 2184 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 2185 { 2186 struct kvm *kvm = vcpu->kvm; 2187 int lm = is_long_mode(vcpu); 2188 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 2189 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 2190 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 2191 : kvm->arch.xen_hvm_config.blob_size_32; 2192 u32 page_num = data & ~PAGE_MASK; 2193 u64 page_addr = data & PAGE_MASK; 2194 u8 *page; 2195 int r; 2196 2197 r = -E2BIG; 2198 if (page_num >= blob_size) 2199 goto out; 2200 r = -ENOMEM; 2201 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 2202 if (IS_ERR(page)) { 2203 r = PTR_ERR(page); 2204 goto out; 2205 } 2206 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 2207 goto out_free; 2208 r = 0; 2209 out_free: 2210 kfree(page); 2211 out: 2212 return r; 2213 } 2214 2215 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2216 { 2217 gpa_t gpa = data & ~0x3f; 2218 2219 /* Bits 3:5 are reserved, Should be zero */ 2220 if (data & 0x38) 2221 return 1; 2222 2223 vcpu->arch.apf.msr_val = data; 2224 2225 if (!(data & KVM_ASYNC_PF_ENABLED)) { 2226 kvm_clear_async_pf_completion_queue(vcpu); 2227 kvm_async_pf_hash_reset(vcpu); 2228 return 0; 2229 } 2230 2231 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2232 sizeof(u32))) 2233 return 1; 2234 2235 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2236 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 2237 kvm_async_pf_wakeup_all(vcpu); 2238 return 0; 2239 } 2240 2241 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2242 { 2243 vcpu->arch.pv_time_enabled = false; 2244 } 2245 2246 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) 2247 { 2248 ++vcpu->stat.tlb_flush; 2249 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa); 2250 } 2251 2252 static void record_steal_time(struct kvm_vcpu *vcpu) 2253 { 2254 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2255 return; 2256 2257 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2258 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2259 return; 2260 2261 /* 2262 * Doing a TLB flush here, on the guest's behalf, can avoid 2263 * expensive IPIs. 2264 */ 2265 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB) 2266 kvm_vcpu_flush_tlb(vcpu, false); 2267 2268 if (vcpu->arch.st.steal.version & 1) 2269 vcpu->arch.st.steal.version += 1; /* first time write, random junk */ 2270 2271 vcpu->arch.st.steal.version += 1; 2272 2273 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2274 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2275 2276 smp_wmb(); 2277 2278 vcpu->arch.st.steal.steal += current->sched_info.run_delay - 2279 vcpu->arch.st.last_steal; 2280 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2281 2282 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2283 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2284 2285 smp_wmb(); 2286 2287 vcpu->arch.st.steal.version += 1; 2288 2289 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2290 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2291 } 2292 2293 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2294 { 2295 bool pr = false; 2296 u32 msr = msr_info->index; 2297 u64 data = msr_info->data; 2298 2299 switch (msr) { 2300 case MSR_AMD64_NB_CFG: 2301 case MSR_IA32_UCODE_WRITE: 2302 case MSR_VM_HSAVE_PA: 2303 case MSR_AMD64_PATCH_LOADER: 2304 case MSR_AMD64_BU_CFG2: 2305 case MSR_AMD64_DC_CFG: 2306 break; 2307 2308 case MSR_IA32_UCODE_REV: 2309 if (msr_info->host_initiated) 2310 vcpu->arch.microcode_version = data; 2311 break; 2312 case MSR_EFER: 2313 return set_efer(vcpu, data); 2314 case MSR_K7_HWCR: 2315 data &= ~(u64)0x40; /* ignore flush filter disable */ 2316 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2317 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2318 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2319 if (data != 0) { 2320 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2321 data); 2322 return 1; 2323 } 2324 break; 2325 case MSR_FAM10H_MMIO_CONF_BASE: 2326 if (data != 0) { 2327 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2328 "0x%llx\n", data); 2329 return 1; 2330 } 2331 break; 2332 case MSR_IA32_DEBUGCTLMSR: 2333 if (!data) { 2334 /* We support the non-activated case already */ 2335 break; 2336 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2337 /* Values other than LBR and BTF are vendor-specific, 2338 thus reserved and should throw a #GP */ 2339 return 1; 2340 } 2341 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2342 __func__, data); 2343 break; 2344 case 0x200 ... 0x2ff: 2345 return kvm_mtrr_set_msr(vcpu, msr, data); 2346 case MSR_IA32_APICBASE: 2347 return kvm_set_apic_base(vcpu, msr_info); 2348 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2349 return kvm_x2apic_msr_write(vcpu, msr, data); 2350 case MSR_IA32_TSCDEADLINE: 2351 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2352 break; 2353 case MSR_IA32_TSC_ADJUST: 2354 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 2355 if (!msr_info->host_initiated) { 2356 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2357 adjust_tsc_offset_guest(vcpu, adj); 2358 } 2359 vcpu->arch.ia32_tsc_adjust_msr = data; 2360 } 2361 break; 2362 case MSR_IA32_MISC_ENABLE: 2363 vcpu->arch.ia32_misc_enable_msr = data; 2364 break; 2365 case MSR_IA32_SMBASE: 2366 if (!msr_info->host_initiated) 2367 return 1; 2368 vcpu->arch.smbase = data; 2369 break; 2370 case MSR_IA32_TSC: 2371 kvm_write_tsc(vcpu, msr_info); 2372 break; 2373 case MSR_SMI_COUNT: 2374 if (!msr_info->host_initiated) 2375 return 1; 2376 vcpu->arch.smi_count = data; 2377 break; 2378 case MSR_KVM_WALL_CLOCK_NEW: 2379 case MSR_KVM_WALL_CLOCK: 2380 vcpu->kvm->arch.wall_clock = data; 2381 kvm_write_wall_clock(vcpu->kvm, data); 2382 break; 2383 case MSR_KVM_SYSTEM_TIME_NEW: 2384 case MSR_KVM_SYSTEM_TIME: { 2385 struct kvm_arch *ka = &vcpu->kvm->arch; 2386 2387 kvmclock_reset(vcpu); 2388 2389 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2390 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2391 2392 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2393 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2394 2395 ka->boot_vcpu_runs_old_kvmclock = tmp; 2396 } 2397 2398 vcpu->arch.time = data; 2399 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2400 2401 /* we verify if the enable bit is set... */ 2402 if (!(data & 1)) 2403 break; 2404 2405 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2406 &vcpu->arch.pv_time, data & ~1ULL, 2407 sizeof(struct pvclock_vcpu_time_info))) 2408 vcpu->arch.pv_time_enabled = false; 2409 else 2410 vcpu->arch.pv_time_enabled = true; 2411 2412 break; 2413 } 2414 case MSR_KVM_ASYNC_PF_EN: 2415 if (kvm_pv_enable_async_pf(vcpu, data)) 2416 return 1; 2417 break; 2418 case MSR_KVM_STEAL_TIME: 2419 2420 if (unlikely(!sched_info_on())) 2421 return 1; 2422 2423 if (data & KVM_STEAL_RESERVED_MASK) 2424 return 1; 2425 2426 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2427 data & KVM_STEAL_VALID_BITS, 2428 sizeof(struct kvm_steal_time))) 2429 return 1; 2430 2431 vcpu->arch.st.msr_val = data; 2432 2433 if (!(data & KVM_MSR_ENABLED)) 2434 break; 2435 2436 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2437 2438 break; 2439 case MSR_KVM_PV_EOI_EN: 2440 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2441 return 1; 2442 break; 2443 2444 case MSR_IA32_MCG_CTL: 2445 case MSR_IA32_MCG_STATUS: 2446 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2447 return set_msr_mce(vcpu, msr_info); 2448 2449 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2450 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2451 pr = true; /* fall through */ 2452 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2453 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2454 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2455 return kvm_pmu_set_msr(vcpu, msr_info); 2456 2457 if (pr || data != 0) 2458 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2459 "0x%x data 0x%llx\n", msr, data); 2460 break; 2461 case MSR_K7_CLK_CTL: 2462 /* 2463 * Ignore all writes to this no longer documented MSR. 2464 * Writes are only relevant for old K7 processors, 2465 * all pre-dating SVM, but a recommended workaround from 2466 * AMD for these chips. It is possible to specify the 2467 * affected processor models on the command line, hence 2468 * the need to ignore the workaround. 2469 */ 2470 break; 2471 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2472 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2473 case HV_X64_MSR_CRASH_CTL: 2474 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2475 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 2476 case HV_X64_MSR_TSC_EMULATION_CONTROL: 2477 case HV_X64_MSR_TSC_EMULATION_STATUS: 2478 return kvm_hv_set_msr_common(vcpu, msr, data, 2479 msr_info->host_initiated); 2480 case MSR_IA32_BBL_CR_CTL3: 2481 /* Drop writes to this legacy MSR -- see rdmsr 2482 * counterpart for further detail. 2483 */ 2484 if (report_ignored_msrs) 2485 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 2486 msr, data); 2487 break; 2488 case MSR_AMD64_OSVW_ID_LENGTH: 2489 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2490 return 1; 2491 vcpu->arch.osvw.length = data; 2492 break; 2493 case MSR_AMD64_OSVW_STATUS: 2494 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2495 return 1; 2496 vcpu->arch.osvw.status = data; 2497 break; 2498 case MSR_PLATFORM_INFO: 2499 if (!msr_info->host_initiated || 2500 data & ~MSR_PLATFORM_INFO_CPUID_FAULT || 2501 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 2502 cpuid_fault_enabled(vcpu))) 2503 return 1; 2504 vcpu->arch.msr_platform_info = data; 2505 break; 2506 case MSR_MISC_FEATURES_ENABLES: 2507 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 2508 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 2509 !supports_cpuid_fault(vcpu))) 2510 return 1; 2511 vcpu->arch.msr_misc_features_enables = data; 2512 break; 2513 default: 2514 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2515 return xen_hvm_config(vcpu, data); 2516 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2517 return kvm_pmu_set_msr(vcpu, msr_info); 2518 if (!ignore_msrs) { 2519 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n", 2520 msr, data); 2521 return 1; 2522 } else { 2523 if (report_ignored_msrs) 2524 vcpu_unimpl(vcpu, 2525 "ignored wrmsr: 0x%x data 0x%llx\n", 2526 msr, data); 2527 break; 2528 } 2529 } 2530 return 0; 2531 } 2532 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2533 2534 2535 /* 2536 * Reads an msr value (of 'msr_index') into 'pdata'. 2537 * Returns 0 on success, non-0 otherwise. 2538 * Assumes vcpu_load() was already called. 2539 */ 2540 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 2541 { 2542 return kvm_x86_ops->get_msr(vcpu, msr); 2543 } 2544 EXPORT_SYMBOL_GPL(kvm_get_msr); 2545 2546 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2547 { 2548 u64 data; 2549 u64 mcg_cap = vcpu->arch.mcg_cap; 2550 unsigned bank_num = mcg_cap & 0xff; 2551 2552 switch (msr) { 2553 case MSR_IA32_P5_MC_ADDR: 2554 case MSR_IA32_P5_MC_TYPE: 2555 data = 0; 2556 break; 2557 case MSR_IA32_MCG_CAP: 2558 data = vcpu->arch.mcg_cap; 2559 break; 2560 case MSR_IA32_MCG_CTL: 2561 if (!(mcg_cap & MCG_CTL_P)) 2562 return 1; 2563 data = vcpu->arch.mcg_ctl; 2564 break; 2565 case MSR_IA32_MCG_STATUS: 2566 data = vcpu->arch.mcg_status; 2567 break; 2568 default: 2569 if (msr >= MSR_IA32_MC0_CTL && 2570 msr < MSR_IA32_MCx_CTL(bank_num)) { 2571 u32 offset = msr - MSR_IA32_MC0_CTL; 2572 data = vcpu->arch.mce_banks[offset]; 2573 break; 2574 } 2575 return 1; 2576 } 2577 *pdata = data; 2578 return 0; 2579 } 2580 2581 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2582 { 2583 switch (msr_info->index) { 2584 case MSR_IA32_PLATFORM_ID: 2585 case MSR_IA32_EBL_CR_POWERON: 2586 case MSR_IA32_DEBUGCTLMSR: 2587 case MSR_IA32_LASTBRANCHFROMIP: 2588 case MSR_IA32_LASTBRANCHTOIP: 2589 case MSR_IA32_LASTINTFROMIP: 2590 case MSR_IA32_LASTINTTOIP: 2591 case MSR_K8_SYSCFG: 2592 case MSR_K8_TSEG_ADDR: 2593 case MSR_K8_TSEG_MASK: 2594 case MSR_K7_HWCR: 2595 case MSR_VM_HSAVE_PA: 2596 case MSR_K8_INT_PENDING_MSG: 2597 case MSR_AMD64_NB_CFG: 2598 case MSR_FAM10H_MMIO_CONF_BASE: 2599 case MSR_AMD64_BU_CFG2: 2600 case MSR_IA32_PERF_CTL: 2601 case MSR_AMD64_DC_CFG: 2602 msr_info->data = 0; 2603 break; 2604 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 2605 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2606 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2607 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2608 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2609 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2610 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2611 msr_info->data = 0; 2612 break; 2613 case MSR_IA32_UCODE_REV: 2614 msr_info->data = vcpu->arch.microcode_version; 2615 break; 2616 case MSR_IA32_TSC: 2617 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset; 2618 break; 2619 case MSR_MTRRcap: 2620 case 0x200 ... 0x2ff: 2621 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 2622 case 0xcd: /* fsb frequency */ 2623 msr_info->data = 3; 2624 break; 2625 /* 2626 * MSR_EBC_FREQUENCY_ID 2627 * Conservative value valid for even the basic CPU models. 2628 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2629 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2630 * and 266MHz for model 3, or 4. Set Core Clock 2631 * Frequency to System Bus Frequency Ratio to 1 (bits 2632 * 31:24) even though these are only valid for CPU 2633 * models > 2, however guests may end up dividing or 2634 * multiplying by zero otherwise. 2635 */ 2636 case MSR_EBC_FREQUENCY_ID: 2637 msr_info->data = 1 << 24; 2638 break; 2639 case MSR_IA32_APICBASE: 2640 msr_info->data = kvm_get_apic_base(vcpu); 2641 break; 2642 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2643 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 2644 break; 2645 case MSR_IA32_TSCDEADLINE: 2646 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 2647 break; 2648 case MSR_IA32_TSC_ADJUST: 2649 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2650 break; 2651 case MSR_IA32_MISC_ENABLE: 2652 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 2653 break; 2654 case MSR_IA32_SMBASE: 2655 if (!msr_info->host_initiated) 2656 return 1; 2657 msr_info->data = vcpu->arch.smbase; 2658 break; 2659 case MSR_SMI_COUNT: 2660 msr_info->data = vcpu->arch.smi_count; 2661 break; 2662 case MSR_IA32_PERF_STATUS: 2663 /* TSC increment by tick */ 2664 msr_info->data = 1000ULL; 2665 /* CPU multiplier */ 2666 msr_info->data |= (((uint64_t)4ULL) << 40); 2667 break; 2668 case MSR_EFER: 2669 msr_info->data = vcpu->arch.efer; 2670 break; 2671 case MSR_KVM_WALL_CLOCK: 2672 case MSR_KVM_WALL_CLOCK_NEW: 2673 msr_info->data = vcpu->kvm->arch.wall_clock; 2674 break; 2675 case MSR_KVM_SYSTEM_TIME: 2676 case MSR_KVM_SYSTEM_TIME_NEW: 2677 msr_info->data = vcpu->arch.time; 2678 break; 2679 case MSR_KVM_ASYNC_PF_EN: 2680 msr_info->data = vcpu->arch.apf.msr_val; 2681 break; 2682 case MSR_KVM_STEAL_TIME: 2683 msr_info->data = vcpu->arch.st.msr_val; 2684 break; 2685 case MSR_KVM_PV_EOI_EN: 2686 msr_info->data = vcpu->arch.pv_eoi.msr_val; 2687 break; 2688 case MSR_IA32_P5_MC_ADDR: 2689 case MSR_IA32_P5_MC_TYPE: 2690 case MSR_IA32_MCG_CAP: 2691 case MSR_IA32_MCG_CTL: 2692 case MSR_IA32_MCG_STATUS: 2693 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2694 return get_msr_mce(vcpu, msr_info->index, &msr_info->data); 2695 case MSR_K7_CLK_CTL: 2696 /* 2697 * Provide expected ramp-up count for K7. All other 2698 * are set to zero, indicating minimum divisors for 2699 * every field. 2700 * 2701 * This prevents guest kernels on AMD host with CPU 2702 * type 6, model 8 and higher from exploding due to 2703 * the rdmsr failing. 2704 */ 2705 msr_info->data = 0x20000000; 2706 break; 2707 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2708 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2709 case HV_X64_MSR_CRASH_CTL: 2710 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2711 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 2712 case HV_X64_MSR_TSC_EMULATION_CONTROL: 2713 case HV_X64_MSR_TSC_EMULATION_STATUS: 2714 return kvm_hv_get_msr_common(vcpu, 2715 msr_info->index, &msr_info->data); 2716 break; 2717 case MSR_IA32_BBL_CR_CTL3: 2718 /* This legacy MSR exists but isn't fully documented in current 2719 * silicon. It is however accessed by winxp in very narrow 2720 * scenarios where it sets bit #19, itself documented as 2721 * a "reserved" bit. Best effort attempt to source coherent 2722 * read data here should the balance of the register be 2723 * interpreted by the guest: 2724 * 2725 * L2 cache control register 3: 64GB range, 256KB size, 2726 * enabled, latency 0x1, configured 2727 */ 2728 msr_info->data = 0xbe702111; 2729 break; 2730 case MSR_AMD64_OSVW_ID_LENGTH: 2731 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2732 return 1; 2733 msr_info->data = vcpu->arch.osvw.length; 2734 break; 2735 case MSR_AMD64_OSVW_STATUS: 2736 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2737 return 1; 2738 msr_info->data = vcpu->arch.osvw.status; 2739 break; 2740 case MSR_PLATFORM_INFO: 2741 msr_info->data = vcpu->arch.msr_platform_info; 2742 break; 2743 case MSR_MISC_FEATURES_ENABLES: 2744 msr_info->data = vcpu->arch.msr_misc_features_enables; 2745 break; 2746 default: 2747 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2748 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2749 if (!ignore_msrs) { 2750 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n", 2751 msr_info->index); 2752 return 1; 2753 } else { 2754 if (report_ignored_msrs) 2755 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", 2756 msr_info->index); 2757 msr_info->data = 0; 2758 } 2759 break; 2760 } 2761 return 0; 2762 } 2763 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2764 2765 /* 2766 * Read or write a bunch of msrs. All parameters are kernel addresses. 2767 * 2768 * @return number of msrs set successfully. 2769 */ 2770 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2771 struct kvm_msr_entry *entries, 2772 int (*do_msr)(struct kvm_vcpu *vcpu, 2773 unsigned index, u64 *data)) 2774 { 2775 int i; 2776 2777 for (i = 0; i < msrs->nmsrs; ++i) 2778 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2779 break; 2780 2781 return i; 2782 } 2783 2784 /* 2785 * Read or write a bunch of msrs. Parameters are user addresses. 2786 * 2787 * @return number of msrs set successfully. 2788 */ 2789 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2790 int (*do_msr)(struct kvm_vcpu *vcpu, 2791 unsigned index, u64 *data), 2792 int writeback) 2793 { 2794 struct kvm_msrs msrs; 2795 struct kvm_msr_entry *entries; 2796 int r, n; 2797 unsigned size; 2798 2799 r = -EFAULT; 2800 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2801 goto out; 2802 2803 r = -E2BIG; 2804 if (msrs.nmsrs >= MAX_IO_MSRS) 2805 goto out; 2806 2807 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2808 entries = memdup_user(user_msrs->entries, size); 2809 if (IS_ERR(entries)) { 2810 r = PTR_ERR(entries); 2811 goto out; 2812 } 2813 2814 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2815 if (r < 0) 2816 goto out_free; 2817 2818 r = -EFAULT; 2819 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2820 goto out_free; 2821 2822 r = n; 2823 2824 out_free: 2825 kfree(entries); 2826 out: 2827 return r; 2828 } 2829 2830 static inline bool kvm_can_mwait_in_guest(void) 2831 { 2832 return boot_cpu_has(X86_FEATURE_MWAIT) && 2833 !boot_cpu_has_bug(X86_BUG_MONITOR) && 2834 boot_cpu_has(X86_FEATURE_ARAT); 2835 } 2836 2837 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2838 { 2839 int r = 0; 2840 2841 switch (ext) { 2842 case KVM_CAP_IRQCHIP: 2843 case KVM_CAP_HLT: 2844 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2845 case KVM_CAP_SET_TSS_ADDR: 2846 case KVM_CAP_EXT_CPUID: 2847 case KVM_CAP_EXT_EMUL_CPUID: 2848 case KVM_CAP_CLOCKSOURCE: 2849 case KVM_CAP_PIT: 2850 case KVM_CAP_NOP_IO_DELAY: 2851 case KVM_CAP_MP_STATE: 2852 case KVM_CAP_SYNC_MMU: 2853 case KVM_CAP_USER_NMI: 2854 case KVM_CAP_REINJECT_CONTROL: 2855 case KVM_CAP_IRQ_INJECT_STATUS: 2856 case KVM_CAP_IOEVENTFD: 2857 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2858 case KVM_CAP_PIT2: 2859 case KVM_CAP_PIT_STATE2: 2860 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2861 case KVM_CAP_XEN_HVM: 2862 case KVM_CAP_VCPU_EVENTS: 2863 case KVM_CAP_HYPERV: 2864 case KVM_CAP_HYPERV_VAPIC: 2865 case KVM_CAP_HYPERV_SPIN: 2866 case KVM_CAP_HYPERV_SYNIC: 2867 case KVM_CAP_HYPERV_SYNIC2: 2868 case KVM_CAP_HYPERV_VP_INDEX: 2869 case KVM_CAP_HYPERV_EVENTFD: 2870 case KVM_CAP_PCI_SEGMENT: 2871 case KVM_CAP_DEBUGREGS: 2872 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2873 case KVM_CAP_XSAVE: 2874 case KVM_CAP_ASYNC_PF: 2875 case KVM_CAP_GET_TSC_KHZ: 2876 case KVM_CAP_KVMCLOCK_CTRL: 2877 case KVM_CAP_READONLY_MEM: 2878 case KVM_CAP_HYPERV_TIME: 2879 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2880 case KVM_CAP_TSC_DEADLINE_TIMER: 2881 case KVM_CAP_ENABLE_CAP_VM: 2882 case KVM_CAP_DISABLE_QUIRKS: 2883 case KVM_CAP_SET_BOOT_CPU_ID: 2884 case KVM_CAP_SPLIT_IRQCHIP: 2885 case KVM_CAP_IMMEDIATE_EXIT: 2886 case KVM_CAP_GET_MSR_FEATURES: 2887 r = 1; 2888 break; 2889 case KVM_CAP_SYNC_REGS: 2890 r = KVM_SYNC_X86_VALID_FIELDS; 2891 break; 2892 case KVM_CAP_ADJUST_CLOCK: 2893 r = KVM_CLOCK_TSC_STABLE; 2894 break; 2895 case KVM_CAP_X86_DISABLE_EXITS: 2896 r |= KVM_X86_DISABLE_EXITS_HTL | KVM_X86_DISABLE_EXITS_PAUSE; 2897 if(kvm_can_mwait_in_guest()) 2898 r |= KVM_X86_DISABLE_EXITS_MWAIT; 2899 break; 2900 case KVM_CAP_X86_SMM: 2901 /* SMBASE is usually relocated above 1M on modern chipsets, 2902 * and SMM handlers might indeed rely on 4G segment limits, 2903 * so do not report SMM to be available if real mode is 2904 * emulated via vm86 mode. Still, do not go to great lengths 2905 * to avoid userspace's usage of the feature, because it is a 2906 * fringe case that is not enabled except via specific settings 2907 * of the module parameters. 2908 */ 2909 r = kvm_x86_ops->cpu_has_high_real_mode_segbase(); 2910 break; 2911 case KVM_CAP_VAPIC: 2912 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2913 break; 2914 case KVM_CAP_NR_VCPUS: 2915 r = KVM_SOFT_MAX_VCPUS; 2916 break; 2917 case KVM_CAP_MAX_VCPUS: 2918 r = KVM_MAX_VCPUS; 2919 break; 2920 case KVM_CAP_NR_MEMSLOTS: 2921 r = KVM_USER_MEM_SLOTS; 2922 break; 2923 case KVM_CAP_PV_MMU: /* obsolete */ 2924 r = 0; 2925 break; 2926 case KVM_CAP_MCE: 2927 r = KVM_MAX_MCE_BANKS; 2928 break; 2929 case KVM_CAP_XCRS: 2930 r = boot_cpu_has(X86_FEATURE_XSAVE); 2931 break; 2932 case KVM_CAP_TSC_CONTROL: 2933 r = kvm_has_tsc_control; 2934 break; 2935 case KVM_CAP_X2APIC_API: 2936 r = KVM_X2APIC_API_VALID_FLAGS; 2937 break; 2938 default: 2939 break; 2940 } 2941 return r; 2942 2943 } 2944 2945 long kvm_arch_dev_ioctl(struct file *filp, 2946 unsigned int ioctl, unsigned long arg) 2947 { 2948 void __user *argp = (void __user *)arg; 2949 long r; 2950 2951 switch (ioctl) { 2952 case KVM_GET_MSR_INDEX_LIST: { 2953 struct kvm_msr_list __user *user_msr_list = argp; 2954 struct kvm_msr_list msr_list; 2955 unsigned n; 2956 2957 r = -EFAULT; 2958 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2959 goto out; 2960 n = msr_list.nmsrs; 2961 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 2962 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2963 goto out; 2964 r = -E2BIG; 2965 if (n < msr_list.nmsrs) 2966 goto out; 2967 r = -EFAULT; 2968 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2969 num_msrs_to_save * sizeof(u32))) 2970 goto out; 2971 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2972 &emulated_msrs, 2973 num_emulated_msrs * sizeof(u32))) 2974 goto out; 2975 r = 0; 2976 break; 2977 } 2978 case KVM_GET_SUPPORTED_CPUID: 2979 case KVM_GET_EMULATED_CPUID: { 2980 struct kvm_cpuid2 __user *cpuid_arg = argp; 2981 struct kvm_cpuid2 cpuid; 2982 2983 r = -EFAULT; 2984 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2985 goto out; 2986 2987 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2988 ioctl); 2989 if (r) 2990 goto out; 2991 2992 r = -EFAULT; 2993 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2994 goto out; 2995 r = 0; 2996 break; 2997 } 2998 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2999 r = -EFAULT; 3000 if (copy_to_user(argp, &kvm_mce_cap_supported, 3001 sizeof(kvm_mce_cap_supported))) 3002 goto out; 3003 r = 0; 3004 break; 3005 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 3006 struct kvm_msr_list __user *user_msr_list = argp; 3007 struct kvm_msr_list msr_list; 3008 unsigned int n; 3009 3010 r = -EFAULT; 3011 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3012 goto out; 3013 n = msr_list.nmsrs; 3014 msr_list.nmsrs = num_msr_based_features; 3015 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3016 goto out; 3017 r = -E2BIG; 3018 if (n < msr_list.nmsrs) 3019 goto out; 3020 r = -EFAULT; 3021 if (copy_to_user(user_msr_list->indices, &msr_based_features, 3022 num_msr_based_features * sizeof(u32))) 3023 goto out; 3024 r = 0; 3025 break; 3026 } 3027 case KVM_GET_MSRS: 3028 r = msr_io(NULL, argp, do_get_msr_feature, 1); 3029 break; 3030 } 3031 default: 3032 r = -EINVAL; 3033 } 3034 out: 3035 return r; 3036 } 3037 3038 static void wbinvd_ipi(void *garbage) 3039 { 3040 wbinvd(); 3041 } 3042 3043 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 3044 { 3045 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 3046 } 3047 3048 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 3049 { 3050 /* Address WBINVD may be executed by guest */ 3051 if (need_emulate_wbinvd(vcpu)) { 3052 if (kvm_x86_ops->has_wbinvd_exit()) 3053 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 3054 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 3055 smp_call_function_single(vcpu->cpu, 3056 wbinvd_ipi, NULL, 1); 3057 } 3058 3059 kvm_x86_ops->vcpu_load(vcpu, cpu); 3060 3061 /* Apply any externally detected TSC adjustments (due to suspend) */ 3062 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 3063 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 3064 vcpu->arch.tsc_offset_adjustment = 0; 3065 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3066 } 3067 3068 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 3069 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 3070 rdtsc() - vcpu->arch.last_host_tsc; 3071 if (tsc_delta < 0) 3072 mark_tsc_unstable("KVM discovered backwards TSC"); 3073 3074 if (kvm_check_tsc_unstable()) { 3075 u64 offset = kvm_compute_tsc_offset(vcpu, 3076 vcpu->arch.last_guest_tsc); 3077 kvm_vcpu_write_tsc_offset(vcpu, offset); 3078 vcpu->arch.tsc_catchup = 1; 3079 } 3080 3081 if (kvm_lapic_hv_timer_in_use(vcpu)) 3082 kvm_lapic_restart_hv_timer(vcpu); 3083 3084 /* 3085 * On a host with synchronized TSC, there is no need to update 3086 * kvmclock on vcpu->cpu migration 3087 */ 3088 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 3089 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 3090 if (vcpu->cpu != cpu) 3091 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 3092 vcpu->cpu = cpu; 3093 } 3094 3095 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3096 } 3097 3098 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 3099 { 3100 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3101 return; 3102 3103 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED; 3104 3105 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime, 3106 &vcpu->arch.st.steal.preempted, 3107 offsetof(struct kvm_steal_time, preempted), 3108 sizeof(vcpu->arch.st.steal.preempted)); 3109 } 3110 3111 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 3112 { 3113 int idx; 3114 3115 if (vcpu->preempted) 3116 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu); 3117 3118 /* 3119 * Disable page faults because we're in atomic context here. 3120 * kvm_write_guest_offset_cached() would call might_fault() 3121 * that relies on pagefault_disable() to tell if there's a 3122 * bug. NOTE: the write to guest memory may not go through if 3123 * during postcopy live migration or if there's heavy guest 3124 * paging. 3125 */ 3126 pagefault_disable(); 3127 /* 3128 * kvm_memslots() will be called by 3129 * kvm_write_guest_offset_cached() so take the srcu lock. 3130 */ 3131 idx = srcu_read_lock(&vcpu->kvm->srcu); 3132 kvm_steal_time_set_preempted(vcpu); 3133 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3134 pagefault_enable(); 3135 kvm_x86_ops->vcpu_put(vcpu); 3136 vcpu->arch.last_host_tsc = rdtsc(); 3137 /* 3138 * If userspace has set any breakpoints or watchpoints, dr6 is restored 3139 * on every vmexit, but if not, we might have a stale dr6 from the 3140 * guest. do_debug expects dr6 to be cleared after it runs, do the same. 3141 */ 3142 set_debugreg(0, 6); 3143 } 3144 3145 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 3146 struct kvm_lapic_state *s) 3147 { 3148 if (vcpu->arch.apicv_active) 3149 kvm_x86_ops->sync_pir_to_irr(vcpu); 3150 3151 return kvm_apic_get_state(vcpu, s); 3152 } 3153 3154 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 3155 struct kvm_lapic_state *s) 3156 { 3157 int r; 3158 3159 r = kvm_apic_set_state(vcpu, s); 3160 if (r) 3161 return r; 3162 update_cr8_intercept(vcpu); 3163 3164 return 0; 3165 } 3166 3167 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 3168 { 3169 return (!lapic_in_kernel(vcpu) || 3170 kvm_apic_accept_pic_intr(vcpu)); 3171 } 3172 3173 /* 3174 * if userspace requested an interrupt window, check that the 3175 * interrupt window is open. 3176 * 3177 * No need to exit to userspace if we already have an interrupt queued. 3178 */ 3179 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 3180 { 3181 return kvm_arch_interrupt_allowed(vcpu) && 3182 !kvm_cpu_has_interrupt(vcpu) && 3183 !kvm_event_needs_reinjection(vcpu) && 3184 kvm_cpu_accept_dm_intr(vcpu); 3185 } 3186 3187 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 3188 struct kvm_interrupt *irq) 3189 { 3190 if (irq->irq >= KVM_NR_INTERRUPTS) 3191 return -EINVAL; 3192 3193 if (!irqchip_in_kernel(vcpu->kvm)) { 3194 kvm_queue_interrupt(vcpu, irq->irq, false); 3195 kvm_make_request(KVM_REQ_EVENT, vcpu); 3196 return 0; 3197 } 3198 3199 /* 3200 * With in-kernel LAPIC, we only use this to inject EXTINT, so 3201 * fail for in-kernel 8259. 3202 */ 3203 if (pic_in_kernel(vcpu->kvm)) 3204 return -ENXIO; 3205 3206 if (vcpu->arch.pending_external_vector != -1) 3207 return -EEXIST; 3208 3209 vcpu->arch.pending_external_vector = irq->irq; 3210 kvm_make_request(KVM_REQ_EVENT, vcpu); 3211 return 0; 3212 } 3213 3214 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 3215 { 3216 kvm_inject_nmi(vcpu); 3217 3218 return 0; 3219 } 3220 3221 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 3222 { 3223 kvm_make_request(KVM_REQ_SMI, vcpu); 3224 3225 return 0; 3226 } 3227 3228 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 3229 struct kvm_tpr_access_ctl *tac) 3230 { 3231 if (tac->flags) 3232 return -EINVAL; 3233 vcpu->arch.tpr_access_reporting = !!tac->enabled; 3234 return 0; 3235 } 3236 3237 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 3238 u64 mcg_cap) 3239 { 3240 int r; 3241 unsigned bank_num = mcg_cap & 0xff, bank; 3242 3243 r = -EINVAL; 3244 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 3245 goto out; 3246 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 3247 goto out; 3248 r = 0; 3249 vcpu->arch.mcg_cap = mcg_cap; 3250 /* Init IA32_MCG_CTL to all 1s */ 3251 if (mcg_cap & MCG_CTL_P) 3252 vcpu->arch.mcg_ctl = ~(u64)0; 3253 /* Init IA32_MCi_CTL to all 1s */ 3254 for (bank = 0; bank < bank_num; bank++) 3255 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 3256 3257 if (kvm_x86_ops->setup_mce) 3258 kvm_x86_ops->setup_mce(vcpu); 3259 out: 3260 return r; 3261 } 3262 3263 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 3264 struct kvm_x86_mce *mce) 3265 { 3266 u64 mcg_cap = vcpu->arch.mcg_cap; 3267 unsigned bank_num = mcg_cap & 0xff; 3268 u64 *banks = vcpu->arch.mce_banks; 3269 3270 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 3271 return -EINVAL; 3272 /* 3273 * if IA32_MCG_CTL is not all 1s, the uncorrected error 3274 * reporting is disabled 3275 */ 3276 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 3277 vcpu->arch.mcg_ctl != ~(u64)0) 3278 return 0; 3279 banks += 4 * mce->bank; 3280 /* 3281 * if IA32_MCi_CTL is not all 1s, the uncorrected error 3282 * reporting is disabled for the bank 3283 */ 3284 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 3285 return 0; 3286 if (mce->status & MCI_STATUS_UC) { 3287 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 3288 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 3289 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 3290 return 0; 3291 } 3292 if (banks[1] & MCI_STATUS_VAL) 3293 mce->status |= MCI_STATUS_OVER; 3294 banks[2] = mce->addr; 3295 banks[3] = mce->misc; 3296 vcpu->arch.mcg_status = mce->mcg_status; 3297 banks[1] = mce->status; 3298 kvm_queue_exception(vcpu, MC_VECTOR); 3299 } else if (!(banks[1] & MCI_STATUS_VAL) 3300 || !(banks[1] & MCI_STATUS_UC)) { 3301 if (banks[1] & MCI_STATUS_VAL) 3302 mce->status |= MCI_STATUS_OVER; 3303 banks[2] = mce->addr; 3304 banks[3] = mce->misc; 3305 banks[1] = mce->status; 3306 } else 3307 banks[1] |= MCI_STATUS_OVER; 3308 return 0; 3309 } 3310 3311 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 3312 struct kvm_vcpu_events *events) 3313 { 3314 process_nmi(vcpu); 3315 /* 3316 * FIXME: pass injected and pending separately. This is only 3317 * needed for nested virtualization, whose state cannot be 3318 * migrated yet. For now we can combine them. 3319 */ 3320 events->exception.injected = 3321 (vcpu->arch.exception.pending || 3322 vcpu->arch.exception.injected) && 3323 !kvm_exception_is_soft(vcpu->arch.exception.nr); 3324 events->exception.nr = vcpu->arch.exception.nr; 3325 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 3326 events->exception.pad = 0; 3327 events->exception.error_code = vcpu->arch.exception.error_code; 3328 3329 events->interrupt.injected = 3330 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 3331 events->interrupt.nr = vcpu->arch.interrupt.nr; 3332 events->interrupt.soft = 0; 3333 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 3334 3335 events->nmi.injected = vcpu->arch.nmi_injected; 3336 events->nmi.pending = vcpu->arch.nmi_pending != 0; 3337 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 3338 events->nmi.pad = 0; 3339 3340 events->sipi_vector = 0; /* never valid when reporting to user space */ 3341 3342 events->smi.smm = is_smm(vcpu); 3343 events->smi.pending = vcpu->arch.smi_pending; 3344 events->smi.smm_inside_nmi = 3345 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 3346 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 3347 3348 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 3349 | KVM_VCPUEVENT_VALID_SHADOW 3350 | KVM_VCPUEVENT_VALID_SMM); 3351 memset(&events->reserved, 0, sizeof(events->reserved)); 3352 } 3353 3354 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags); 3355 3356 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 3357 struct kvm_vcpu_events *events) 3358 { 3359 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 3360 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 3361 | KVM_VCPUEVENT_VALID_SHADOW 3362 | KVM_VCPUEVENT_VALID_SMM)) 3363 return -EINVAL; 3364 3365 if (events->exception.injected && 3366 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR || 3367 is_guest_mode(vcpu))) 3368 return -EINVAL; 3369 3370 /* INITs are latched while in SMM */ 3371 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 3372 (events->smi.smm || events->smi.pending) && 3373 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 3374 return -EINVAL; 3375 3376 process_nmi(vcpu); 3377 vcpu->arch.exception.injected = false; 3378 vcpu->arch.exception.pending = events->exception.injected; 3379 vcpu->arch.exception.nr = events->exception.nr; 3380 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 3381 vcpu->arch.exception.error_code = events->exception.error_code; 3382 3383 vcpu->arch.interrupt.injected = events->interrupt.injected; 3384 vcpu->arch.interrupt.nr = events->interrupt.nr; 3385 vcpu->arch.interrupt.soft = events->interrupt.soft; 3386 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3387 kvm_x86_ops->set_interrupt_shadow(vcpu, 3388 events->interrupt.shadow); 3389 3390 vcpu->arch.nmi_injected = events->nmi.injected; 3391 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3392 vcpu->arch.nmi_pending = events->nmi.pending; 3393 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 3394 3395 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3396 lapic_in_kernel(vcpu)) 3397 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3398 3399 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 3400 u32 hflags = vcpu->arch.hflags; 3401 if (events->smi.smm) 3402 hflags |= HF_SMM_MASK; 3403 else 3404 hflags &= ~HF_SMM_MASK; 3405 kvm_set_hflags(vcpu, hflags); 3406 3407 vcpu->arch.smi_pending = events->smi.pending; 3408 3409 if (events->smi.smm) { 3410 if (events->smi.smm_inside_nmi) 3411 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 3412 else 3413 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 3414 if (lapic_in_kernel(vcpu)) { 3415 if (events->smi.latched_init) 3416 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3417 else 3418 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3419 } 3420 } 3421 } 3422 3423 kvm_make_request(KVM_REQ_EVENT, vcpu); 3424 3425 return 0; 3426 } 3427 3428 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3429 struct kvm_debugregs *dbgregs) 3430 { 3431 unsigned long val; 3432 3433 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3434 kvm_get_dr(vcpu, 6, &val); 3435 dbgregs->dr6 = val; 3436 dbgregs->dr7 = vcpu->arch.dr7; 3437 dbgregs->flags = 0; 3438 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3439 } 3440 3441 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3442 struct kvm_debugregs *dbgregs) 3443 { 3444 if (dbgregs->flags) 3445 return -EINVAL; 3446 3447 if (dbgregs->dr6 & ~0xffffffffull) 3448 return -EINVAL; 3449 if (dbgregs->dr7 & ~0xffffffffull) 3450 return -EINVAL; 3451 3452 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3453 kvm_update_dr0123(vcpu); 3454 vcpu->arch.dr6 = dbgregs->dr6; 3455 kvm_update_dr6(vcpu); 3456 vcpu->arch.dr7 = dbgregs->dr7; 3457 kvm_update_dr7(vcpu); 3458 3459 return 0; 3460 } 3461 3462 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3463 3464 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3465 { 3466 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3467 u64 xstate_bv = xsave->header.xfeatures; 3468 u64 valid; 3469 3470 /* 3471 * Copy legacy XSAVE area, to avoid complications with CPUID 3472 * leaves 0 and 1 in the loop below. 3473 */ 3474 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3475 3476 /* Set XSTATE_BV */ 3477 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; 3478 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3479 3480 /* 3481 * Copy each region from the possibly compacted offset to the 3482 * non-compacted offset. 3483 */ 3484 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3485 while (valid) { 3486 u64 feature = valid & -valid; 3487 int index = fls64(feature) - 1; 3488 void *src = get_xsave_addr(xsave, feature); 3489 3490 if (src) { 3491 u32 size, offset, ecx, edx; 3492 cpuid_count(XSTATE_CPUID, index, 3493 &size, &offset, &ecx, &edx); 3494 if (feature == XFEATURE_MASK_PKRU) 3495 memcpy(dest + offset, &vcpu->arch.pkru, 3496 sizeof(vcpu->arch.pkru)); 3497 else 3498 memcpy(dest + offset, src, size); 3499 3500 } 3501 3502 valid -= feature; 3503 } 3504 } 3505 3506 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3507 { 3508 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3509 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3510 u64 valid; 3511 3512 /* 3513 * Copy legacy XSAVE area, to avoid complications with CPUID 3514 * leaves 0 and 1 in the loop below. 3515 */ 3516 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3517 3518 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3519 xsave->header.xfeatures = xstate_bv; 3520 if (boot_cpu_has(X86_FEATURE_XSAVES)) 3521 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3522 3523 /* 3524 * Copy each region from the non-compacted offset to the 3525 * possibly compacted offset. 3526 */ 3527 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3528 while (valid) { 3529 u64 feature = valid & -valid; 3530 int index = fls64(feature) - 1; 3531 void *dest = get_xsave_addr(xsave, feature); 3532 3533 if (dest) { 3534 u32 size, offset, ecx, edx; 3535 cpuid_count(XSTATE_CPUID, index, 3536 &size, &offset, &ecx, &edx); 3537 if (feature == XFEATURE_MASK_PKRU) 3538 memcpy(&vcpu->arch.pkru, src + offset, 3539 sizeof(vcpu->arch.pkru)); 3540 else 3541 memcpy(dest, src + offset, size); 3542 } 3543 3544 valid -= feature; 3545 } 3546 } 3547 3548 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3549 struct kvm_xsave *guest_xsave) 3550 { 3551 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3552 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3553 fill_xsave((u8 *) guest_xsave->region, vcpu); 3554 } else { 3555 memcpy(guest_xsave->region, 3556 &vcpu->arch.guest_fpu.state.fxsave, 3557 sizeof(struct fxregs_state)); 3558 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3559 XFEATURE_MASK_FPSSE; 3560 } 3561 } 3562 3563 #define XSAVE_MXCSR_OFFSET 24 3564 3565 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3566 struct kvm_xsave *guest_xsave) 3567 { 3568 u64 xstate_bv = 3569 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3570 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; 3571 3572 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3573 /* 3574 * Here we allow setting states that are not present in 3575 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3576 * with old userspace. 3577 */ 3578 if (xstate_bv & ~kvm_supported_xcr0() || 3579 mxcsr & ~mxcsr_feature_mask) 3580 return -EINVAL; 3581 load_xsave(vcpu, (u8 *)guest_xsave->region); 3582 } else { 3583 if (xstate_bv & ~XFEATURE_MASK_FPSSE || 3584 mxcsr & ~mxcsr_feature_mask) 3585 return -EINVAL; 3586 memcpy(&vcpu->arch.guest_fpu.state.fxsave, 3587 guest_xsave->region, sizeof(struct fxregs_state)); 3588 } 3589 return 0; 3590 } 3591 3592 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3593 struct kvm_xcrs *guest_xcrs) 3594 { 3595 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 3596 guest_xcrs->nr_xcrs = 0; 3597 return; 3598 } 3599 3600 guest_xcrs->nr_xcrs = 1; 3601 guest_xcrs->flags = 0; 3602 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3603 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3604 } 3605 3606 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3607 struct kvm_xcrs *guest_xcrs) 3608 { 3609 int i, r = 0; 3610 3611 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 3612 return -EINVAL; 3613 3614 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3615 return -EINVAL; 3616 3617 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3618 /* Only support XCR0 currently */ 3619 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3620 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3621 guest_xcrs->xcrs[i].value); 3622 break; 3623 } 3624 if (r) 3625 r = -EINVAL; 3626 return r; 3627 } 3628 3629 /* 3630 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3631 * stopped by the hypervisor. This function will be called from the host only. 3632 * EINVAL is returned when the host attempts to set the flag for a guest that 3633 * does not support pv clocks. 3634 */ 3635 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3636 { 3637 if (!vcpu->arch.pv_time_enabled) 3638 return -EINVAL; 3639 vcpu->arch.pvclock_set_guest_stopped_request = true; 3640 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3641 return 0; 3642 } 3643 3644 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 3645 struct kvm_enable_cap *cap) 3646 { 3647 if (cap->flags) 3648 return -EINVAL; 3649 3650 switch (cap->cap) { 3651 case KVM_CAP_HYPERV_SYNIC2: 3652 if (cap->args[0]) 3653 return -EINVAL; 3654 case KVM_CAP_HYPERV_SYNIC: 3655 if (!irqchip_in_kernel(vcpu->kvm)) 3656 return -EINVAL; 3657 return kvm_hv_activate_synic(vcpu, cap->cap == 3658 KVM_CAP_HYPERV_SYNIC2); 3659 default: 3660 return -EINVAL; 3661 } 3662 } 3663 3664 long kvm_arch_vcpu_ioctl(struct file *filp, 3665 unsigned int ioctl, unsigned long arg) 3666 { 3667 struct kvm_vcpu *vcpu = filp->private_data; 3668 void __user *argp = (void __user *)arg; 3669 int r; 3670 union { 3671 struct kvm_lapic_state *lapic; 3672 struct kvm_xsave *xsave; 3673 struct kvm_xcrs *xcrs; 3674 void *buffer; 3675 } u; 3676 3677 vcpu_load(vcpu); 3678 3679 u.buffer = NULL; 3680 switch (ioctl) { 3681 case KVM_GET_LAPIC: { 3682 r = -EINVAL; 3683 if (!lapic_in_kernel(vcpu)) 3684 goto out; 3685 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3686 3687 r = -ENOMEM; 3688 if (!u.lapic) 3689 goto out; 3690 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3691 if (r) 3692 goto out; 3693 r = -EFAULT; 3694 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3695 goto out; 3696 r = 0; 3697 break; 3698 } 3699 case KVM_SET_LAPIC: { 3700 r = -EINVAL; 3701 if (!lapic_in_kernel(vcpu)) 3702 goto out; 3703 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3704 if (IS_ERR(u.lapic)) { 3705 r = PTR_ERR(u.lapic); 3706 goto out_nofree; 3707 } 3708 3709 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3710 break; 3711 } 3712 case KVM_INTERRUPT: { 3713 struct kvm_interrupt irq; 3714 3715 r = -EFAULT; 3716 if (copy_from_user(&irq, argp, sizeof irq)) 3717 goto out; 3718 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3719 break; 3720 } 3721 case KVM_NMI: { 3722 r = kvm_vcpu_ioctl_nmi(vcpu); 3723 break; 3724 } 3725 case KVM_SMI: { 3726 r = kvm_vcpu_ioctl_smi(vcpu); 3727 break; 3728 } 3729 case KVM_SET_CPUID: { 3730 struct kvm_cpuid __user *cpuid_arg = argp; 3731 struct kvm_cpuid cpuid; 3732 3733 r = -EFAULT; 3734 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3735 goto out; 3736 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3737 break; 3738 } 3739 case KVM_SET_CPUID2: { 3740 struct kvm_cpuid2 __user *cpuid_arg = argp; 3741 struct kvm_cpuid2 cpuid; 3742 3743 r = -EFAULT; 3744 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3745 goto out; 3746 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3747 cpuid_arg->entries); 3748 break; 3749 } 3750 case KVM_GET_CPUID2: { 3751 struct kvm_cpuid2 __user *cpuid_arg = argp; 3752 struct kvm_cpuid2 cpuid; 3753 3754 r = -EFAULT; 3755 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3756 goto out; 3757 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3758 cpuid_arg->entries); 3759 if (r) 3760 goto out; 3761 r = -EFAULT; 3762 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3763 goto out; 3764 r = 0; 3765 break; 3766 } 3767 case KVM_GET_MSRS: { 3768 int idx = srcu_read_lock(&vcpu->kvm->srcu); 3769 r = msr_io(vcpu, argp, do_get_msr, 1); 3770 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3771 break; 3772 } 3773 case KVM_SET_MSRS: { 3774 int idx = srcu_read_lock(&vcpu->kvm->srcu); 3775 r = msr_io(vcpu, argp, do_set_msr, 0); 3776 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3777 break; 3778 } 3779 case KVM_TPR_ACCESS_REPORTING: { 3780 struct kvm_tpr_access_ctl tac; 3781 3782 r = -EFAULT; 3783 if (copy_from_user(&tac, argp, sizeof tac)) 3784 goto out; 3785 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3786 if (r) 3787 goto out; 3788 r = -EFAULT; 3789 if (copy_to_user(argp, &tac, sizeof tac)) 3790 goto out; 3791 r = 0; 3792 break; 3793 }; 3794 case KVM_SET_VAPIC_ADDR: { 3795 struct kvm_vapic_addr va; 3796 int idx; 3797 3798 r = -EINVAL; 3799 if (!lapic_in_kernel(vcpu)) 3800 goto out; 3801 r = -EFAULT; 3802 if (copy_from_user(&va, argp, sizeof va)) 3803 goto out; 3804 idx = srcu_read_lock(&vcpu->kvm->srcu); 3805 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3806 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3807 break; 3808 } 3809 case KVM_X86_SETUP_MCE: { 3810 u64 mcg_cap; 3811 3812 r = -EFAULT; 3813 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3814 goto out; 3815 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3816 break; 3817 } 3818 case KVM_X86_SET_MCE: { 3819 struct kvm_x86_mce mce; 3820 3821 r = -EFAULT; 3822 if (copy_from_user(&mce, argp, sizeof mce)) 3823 goto out; 3824 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3825 break; 3826 } 3827 case KVM_GET_VCPU_EVENTS: { 3828 struct kvm_vcpu_events events; 3829 3830 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3831 3832 r = -EFAULT; 3833 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3834 break; 3835 r = 0; 3836 break; 3837 } 3838 case KVM_SET_VCPU_EVENTS: { 3839 struct kvm_vcpu_events events; 3840 3841 r = -EFAULT; 3842 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3843 break; 3844 3845 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3846 break; 3847 } 3848 case KVM_GET_DEBUGREGS: { 3849 struct kvm_debugregs dbgregs; 3850 3851 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3852 3853 r = -EFAULT; 3854 if (copy_to_user(argp, &dbgregs, 3855 sizeof(struct kvm_debugregs))) 3856 break; 3857 r = 0; 3858 break; 3859 } 3860 case KVM_SET_DEBUGREGS: { 3861 struct kvm_debugregs dbgregs; 3862 3863 r = -EFAULT; 3864 if (copy_from_user(&dbgregs, argp, 3865 sizeof(struct kvm_debugregs))) 3866 break; 3867 3868 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3869 break; 3870 } 3871 case KVM_GET_XSAVE: { 3872 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3873 r = -ENOMEM; 3874 if (!u.xsave) 3875 break; 3876 3877 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3878 3879 r = -EFAULT; 3880 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3881 break; 3882 r = 0; 3883 break; 3884 } 3885 case KVM_SET_XSAVE: { 3886 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3887 if (IS_ERR(u.xsave)) { 3888 r = PTR_ERR(u.xsave); 3889 goto out_nofree; 3890 } 3891 3892 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3893 break; 3894 } 3895 case KVM_GET_XCRS: { 3896 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3897 r = -ENOMEM; 3898 if (!u.xcrs) 3899 break; 3900 3901 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3902 3903 r = -EFAULT; 3904 if (copy_to_user(argp, u.xcrs, 3905 sizeof(struct kvm_xcrs))) 3906 break; 3907 r = 0; 3908 break; 3909 } 3910 case KVM_SET_XCRS: { 3911 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3912 if (IS_ERR(u.xcrs)) { 3913 r = PTR_ERR(u.xcrs); 3914 goto out_nofree; 3915 } 3916 3917 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3918 break; 3919 } 3920 case KVM_SET_TSC_KHZ: { 3921 u32 user_tsc_khz; 3922 3923 r = -EINVAL; 3924 user_tsc_khz = (u32)arg; 3925 3926 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3927 goto out; 3928 3929 if (user_tsc_khz == 0) 3930 user_tsc_khz = tsc_khz; 3931 3932 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 3933 r = 0; 3934 3935 goto out; 3936 } 3937 case KVM_GET_TSC_KHZ: { 3938 r = vcpu->arch.virtual_tsc_khz; 3939 goto out; 3940 } 3941 case KVM_KVMCLOCK_CTRL: { 3942 r = kvm_set_guest_paused(vcpu); 3943 goto out; 3944 } 3945 case KVM_ENABLE_CAP: { 3946 struct kvm_enable_cap cap; 3947 3948 r = -EFAULT; 3949 if (copy_from_user(&cap, argp, sizeof(cap))) 3950 goto out; 3951 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 3952 break; 3953 } 3954 default: 3955 r = -EINVAL; 3956 } 3957 out: 3958 kfree(u.buffer); 3959 out_nofree: 3960 vcpu_put(vcpu); 3961 return r; 3962 } 3963 3964 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3965 { 3966 return VM_FAULT_SIGBUS; 3967 } 3968 3969 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3970 { 3971 int ret; 3972 3973 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3974 return -EINVAL; 3975 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3976 return ret; 3977 } 3978 3979 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3980 u64 ident_addr) 3981 { 3982 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr); 3983 } 3984 3985 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3986 u32 kvm_nr_mmu_pages) 3987 { 3988 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3989 return -EINVAL; 3990 3991 mutex_lock(&kvm->slots_lock); 3992 3993 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3994 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3995 3996 mutex_unlock(&kvm->slots_lock); 3997 return 0; 3998 } 3999 4000 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 4001 { 4002 return kvm->arch.n_max_mmu_pages; 4003 } 4004 4005 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 4006 { 4007 struct kvm_pic *pic = kvm->arch.vpic; 4008 int r; 4009 4010 r = 0; 4011 switch (chip->chip_id) { 4012 case KVM_IRQCHIP_PIC_MASTER: 4013 memcpy(&chip->chip.pic, &pic->pics[0], 4014 sizeof(struct kvm_pic_state)); 4015 break; 4016 case KVM_IRQCHIP_PIC_SLAVE: 4017 memcpy(&chip->chip.pic, &pic->pics[1], 4018 sizeof(struct kvm_pic_state)); 4019 break; 4020 case KVM_IRQCHIP_IOAPIC: 4021 kvm_get_ioapic(kvm, &chip->chip.ioapic); 4022 break; 4023 default: 4024 r = -EINVAL; 4025 break; 4026 } 4027 return r; 4028 } 4029 4030 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 4031 { 4032 struct kvm_pic *pic = kvm->arch.vpic; 4033 int r; 4034 4035 r = 0; 4036 switch (chip->chip_id) { 4037 case KVM_IRQCHIP_PIC_MASTER: 4038 spin_lock(&pic->lock); 4039 memcpy(&pic->pics[0], &chip->chip.pic, 4040 sizeof(struct kvm_pic_state)); 4041 spin_unlock(&pic->lock); 4042 break; 4043 case KVM_IRQCHIP_PIC_SLAVE: 4044 spin_lock(&pic->lock); 4045 memcpy(&pic->pics[1], &chip->chip.pic, 4046 sizeof(struct kvm_pic_state)); 4047 spin_unlock(&pic->lock); 4048 break; 4049 case KVM_IRQCHIP_IOAPIC: 4050 kvm_set_ioapic(kvm, &chip->chip.ioapic); 4051 break; 4052 default: 4053 r = -EINVAL; 4054 break; 4055 } 4056 kvm_pic_update_irq(pic); 4057 return r; 4058 } 4059 4060 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 4061 { 4062 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 4063 4064 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 4065 4066 mutex_lock(&kps->lock); 4067 memcpy(ps, &kps->channels, sizeof(*ps)); 4068 mutex_unlock(&kps->lock); 4069 return 0; 4070 } 4071 4072 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 4073 { 4074 int i; 4075 struct kvm_pit *pit = kvm->arch.vpit; 4076 4077 mutex_lock(&pit->pit_state.lock); 4078 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 4079 for (i = 0; i < 3; i++) 4080 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 4081 mutex_unlock(&pit->pit_state.lock); 4082 return 0; 4083 } 4084 4085 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 4086 { 4087 mutex_lock(&kvm->arch.vpit->pit_state.lock); 4088 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 4089 sizeof(ps->channels)); 4090 ps->flags = kvm->arch.vpit->pit_state.flags; 4091 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 4092 memset(&ps->reserved, 0, sizeof(ps->reserved)); 4093 return 0; 4094 } 4095 4096 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 4097 { 4098 int start = 0; 4099 int i; 4100 u32 prev_legacy, cur_legacy; 4101 struct kvm_pit *pit = kvm->arch.vpit; 4102 4103 mutex_lock(&pit->pit_state.lock); 4104 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 4105 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 4106 if (!prev_legacy && cur_legacy) 4107 start = 1; 4108 memcpy(&pit->pit_state.channels, &ps->channels, 4109 sizeof(pit->pit_state.channels)); 4110 pit->pit_state.flags = ps->flags; 4111 for (i = 0; i < 3; i++) 4112 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 4113 start && i == 0); 4114 mutex_unlock(&pit->pit_state.lock); 4115 return 0; 4116 } 4117 4118 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 4119 struct kvm_reinject_control *control) 4120 { 4121 struct kvm_pit *pit = kvm->arch.vpit; 4122 4123 if (!pit) 4124 return -ENXIO; 4125 4126 /* pit->pit_state.lock was overloaded to prevent userspace from getting 4127 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 4128 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 4129 */ 4130 mutex_lock(&pit->pit_state.lock); 4131 kvm_pit_set_reinject(pit, control->pit_reinject); 4132 mutex_unlock(&pit->pit_state.lock); 4133 4134 return 0; 4135 } 4136 4137 /** 4138 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 4139 * @kvm: kvm instance 4140 * @log: slot id and address to which we copy the log 4141 * 4142 * Steps 1-4 below provide general overview of dirty page logging. See 4143 * kvm_get_dirty_log_protect() function description for additional details. 4144 * 4145 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 4146 * always flush the TLB (step 4) even if previous step failed and the dirty 4147 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 4148 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 4149 * writes will be marked dirty for next log read. 4150 * 4151 * 1. Take a snapshot of the bit and clear it if needed. 4152 * 2. Write protect the corresponding page. 4153 * 3. Copy the snapshot to the userspace. 4154 * 4. Flush TLB's if needed. 4155 */ 4156 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 4157 { 4158 bool is_dirty = false; 4159 int r; 4160 4161 mutex_lock(&kvm->slots_lock); 4162 4163 /* 4164 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 4165 */ 4166 if (kvm_x86_ops->flush_log_dirty) 4167 kvm_x86_ops->flush_log_dirty(kvm); 4168 4169 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 4170 4171 /* 4172 * All the TLBs can be flushed out of mmu lock, see the comments in 4173 * kvm_mmu_slot_remove_write_access(). 4174 */ 4175 lockdep_assert_held(&kvm->slots_lock); 4176 if (is_dirty) 4177 kvm_flush_remote_tlbs(kvm); 4178 4179 mutex_unlock(&kvm->slots_lock); 4180 return r; 4181 } 4182 4183 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 4184 bool line_status) 4185 { 4186 if (!irqchip_in_kernel(kvm)) 4187 return -ENXIO; 4188 4189 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 4190 irq_event->irq, irq_event->level, 4191 line_status); 4192 return 0; 4193 } 4194 4195 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 4196 struct kvm_enable_cap *cap) 4197 { 4198 int r; 4199 4200 if (cap->flags) 4201 return -EINVAL; 4202 4203 switch (cap->cap) { 4204 case KVM_CAP_DISABLE_QUIRKS: 4205 kvm->arch.disabled_quirks = cap->args[0]; 4206 r = 0; 4207 break; 4208 case KVM_CAP_SPLIT_IRQCHIP: { 4209 mutex_lock(&kvm->lock); 4210 r = -EINVAL; 4211 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 4212 goto split_irqchip_unlock; 4213 r = -EEXIST; 4214 if (irqchip_in_kernel(kvm)) 4215 goto split_irqchip_unlock; 4216 if (kvm->created_vcpus) 4217 goto split_irqchip_unlock; 4218 r = kvm_setup_empty_irq_routing(kvm); 4219 if (r) 4220 goto split_irqchip_unlock; 4221 /* Pairs with irqchip_in_kernel. */ 4222 smp_wmb(); 4223 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 4224 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 4225 r = 0; 4226 split_irqchip_unlock: 4227 mutex_unlock(&kvm->lock); 4228 break; 4229 } 4230 case KVM_CAP_X2APIC_API: 4231 r = -EINVAL; 4232 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 4233 break; 4234 4235 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 4236 kvm->arch.x2apic_format = true; 4237 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 4238 kvm->arch.x2apic_broadcast_quirk_disabled = true; 4239 4240 r = 0; 4241 break; 4242 case KVM_CAP_X86_DISABLE_EXITS: 4243 r = -EINVAL; 4244 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 4245 break; 4246 4247 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 4248 kvm_can_mwait_in_guest()) 4249 kvm->arch.mwait_in_guest = true; 4250 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HTL) 4251 kvm->arch.hlt_in_guest = true; 4252 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 4253 kvm->arch.pause_in_guest = true; 4254 r = 0; 4255 break; 4256 default: 4257 r = -EINVAL; 4258 break; 4259 } 4260 return r; 4261 } 4262 4263 long kvm_arch_vm_ioctl(struct file *filp, 4264 unsigned int ioctl, unsigned long arg) 4265 { 4266 struct kvm *kvm = filp->private_data; 4267 void __user *argp = (void __user *)arg; 4268 int r = -ENOTTY; 4269 /* 4270 * This union makes it completely explicit to gcc-3.x 4271 * that these two variables' stack usage should be 4272 * combined, not added together. 4273 */ 4274 union { 4275 struct kvm_pit_state ps; 4276 struct kvm_pit_state2 ps2; 4277 struct kvm_pit_config pit_config; 4278 } u; 4279 4280 switch (ioctl) { 4281 case KVM_SET_TSS_ADDR: 4282 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 4283 break; 4284 case KVM_SET_IDENTITY_MAP_ADDR: { 4285 u64 ident_addr; 4286 4287 mutex_lock(&kvm->lock); 4288 r = -EINVAL; 4289 if (kvm->created_vcpus) 4290 goto set_identity_unlock; 4291 r = -EFAULT; 4292 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 4293 goto set_identity_unlock; 4294 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 4295 set_identity_unlock: 4296 mutex_unlock(&kvm->lock); 4297 break; 4298 } 4299 case KVM_SET_NR_MMU_PAGES: 4300 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 4301 break; 4302 case KVM_GET_NR_MMU_PAGES: 4303 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 4304 break; 4305 case KVM_CREATE_IRQCHIP: { 4306 mutex_lock(&kvm->lock); 4307 4308 r = -EEXIST; 4309 if (irqchip_in_kernel(kvm)) 4310 goto create_irqchip_unlock; 4311 4312 r = -EINVAL; 4313 if (kvm->created_vcpus) 4314 goto create_irqchip_unlock; 4315 4316 r = kvm_pic_init(kvm); 4317 if (r) 4318 goto create_irqchip_unlock; 4319 4320 r = kvm_ioapic_init(kvm); 4321 if (r) { 4322 kvm_pic_destroy(kvm); 4323 goto create_irqchip_unlock; 4324 } 4325 4326 r = kvm_setup_default_irq_routing(kvm); 4327 if (r) { 4328 kvm_ioapic_destroy(kvm); 4329 kvm_pic_destroy(kvm); 4330 goto create_irqchip_unlock; 4331 } 4332 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 4333 smp_wmb(); 4334 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 4335 create_irqchip_unlock: 4336 mutex_unlock(&kvm->lock); 4337 break; 4338 } 4339 case KVM_CREATE_PIT: 4340 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 4341 goto create_pit; 4342 case KVM_CREATE_PIT2: 4343 r = -EFAULT; 4344 if (copy_from_user(&u.pit_config, argp, 4345 sizeof(struct kvm_pit_config))) 4346 goto out; 4347 create_pit: 4348 mutex_lock(&kvm->lock); 4349 r = -EEXIST; 4350 if (kvm->arch.vpit) 4351 goto create_pit_unlock; 4352 r = -ENOMEM; 4353 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 4354 if (kvm->arch.vpit) 4355 r = 0; 4356 create_pit_unlock: 4357 mutex_unlock(&kvm->lock); 4358 break; 4359 case KVM_GET_IRQCHIP: { 4360 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4361 struct kvm_irqchip *chip; 4362 4363 chip = memdup_user(argp, sizeof(*chip)); 4364 if (IS_ERR(chip)) { 4365 r = PTR_ERR(chip); 4366 goto out; 4367 } 4368 4369 r = -ENXIO; 4370 if (!irqchip_kernel(kvm)) 4371 goto get_irqchip_out; 4372 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 4373 if (r) 4374 goto get_irqchip_out; 4375 r = -EFAULT; 4376 if (copy_to_user(argp, chip, sizeof *chip)) 4377 goto get_irqchip_out; 4378 r = 0; 4379 get_irqchip_out: 4380 kfree(chip); 4381 break; 4382 } 4383 case KVM_SET_IRQCHIP: { 4384 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4385 struct kvm_irqchip *chip; 4386 4387 chip = memdup_user(argp, sizeof(*chip)); 4388 if (IS_ERR(chip)) { 4389 r = PTR_ERR(chip); 4390 goto out; 4391 } 4392 4393 r = -ENXIO; 4394 if (!irqchip_kernel(kvm)) 4395 goto set_irqchip_out; 4396 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 4397 if (r) 4398 goto set_irqchip_out; 4399 r = 0; 4400 set_irqchip_out: 4401 kfree(chip); 4402 break; 4403 } 4404 case KVM_GET_PIT: { 4405 r = -EFAULT; 4406 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 4407 goto out; 4408 r = -ENXIO; 4409 if (!kvm->arch.vpit) 4410 goto out; 4411 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 4412 if (r) 4413 goto out; 4414 r = -EFAULT; 4415 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 4416 goto out; 4417 r = 0; 4418 break; 4419 } 4420 case KVM_SET_PIT: { 4421 r = -EFAULT; 4422 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 4423 goto out; 4424 r = -ENXIO; 4425 if (!kvm->arch.vpit) 4426 goto out; 4427 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 4428 break; 4429 } 4430 case KVM_GET_PIT2: { 4431 r = -ENXIO; 4432 if (!kvm->arch.vpit) 4433 goto out; 4434 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 4435 if (r) 4436 goto out; 4437 r = -EFAULT; 4438 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 4439 goto out; 4440 r = 0; 4441 break; 4442 } 4443 case KVM_SET_PIT2: { 4444 r = -EFAULT; 4445 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 4446 goto out; 4447 r = -ENXIO; 4448 if (!kvm->arch.vpit) 4449 goto out; 4450 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 4451 break; 4452 } 4453 case KVM_REINJECT_CONTROL: { 4454 struct kvm_reinject_control control; 4455 r = -EFAULT; 4456 if (copy_from_user(&control, argp, sizeof(control))) 4457 goto out; 4458 r = kvm_vm_ioctl_reinject(kvm, &control); 4459 break; 4460 } 4461 case KVM_SET_BOOT_CPU_ID: 4462 r = 0; 4463 mutex_lock(&kvm->lock); 4464 if (kvm->created_vcpus) 4465 r = -EBUSY; 4466 else 4467 kvm->arch.bsp_vcpu_id = arg; 4468 mutex_unlock(&kvm->lock); 4469 break; 4470 case KVM_XEN_HVM_CONFIG: { 4471 struct kvm_xen_hvm_config xhc; 4472 r = -EFAULT; 4473 if (copy_from_user(&xhc, argp, sizeof(xhc))) 4474 goto out; 4475 r = -EINVAL; 4476 if (xhc.flags) 4477 goto out; 4478 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); 4479 r = 0; 4480 break; 4481 } 4482 case KVM_SET_CLOCK: { 4483 struct kvm_clock_data user_ns; 4484 u64 now_ns; 4485 4486 r = -EFAULT; 4487 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 4488 goto out; 4489 4490 r = -EINVAL; 4491 if (user_ns.flags) 4492 goto out; 4493 4494 r = 0; 4495 /* 4496 * TODO: userspace has to take care of races with VCPU_RUN, so 4497 * kvm_gen_update_masterclock() can be cut down to locked 4498 * pvclock_update_vm_gtod_copy(). 4499 */ 4500 kvm_gen_update_masterclock(kvm); 4501 now_ns = get_kvmclock_ns(kvm); 4502 kvm->arch.kvmclock_offset += user_ns.clock - now_ns; 4503 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); 4504 break; 4505 } 4506 case KVM_GET_CLOCK: { 4507 struct kvm_clock_data user_ns; 4508 u64 now_ns; 4509 4510 now_ns = get_kvmclock_ns(kvm); 4511 user_ns.clock = now_ns; 4512 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 4513 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 4514 4515 r = -EFAULT; 4516 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 4517 goto out; 4518 r = 0; 4519 break; 4520 } 4521 case KVM_ENABLE_CAP: { 4522 struct kvm_enable_cap cap; 4523 4524 r = -EFAULT; 4525 if (copy_from_user(&cap, argp, sizeof(cap))) 4526 goto out; 4527 r = kvm_vm_ioctl_enable_cap(kvm, &cap); 4528 break; 4529 } 4530 case KVM_MEMORY_ENCRYPT_OP: { 4531 r = -ENOTTY; 4532 if (kvm_x86_ops->mem_enc_op) 4533 r = kvm_x86_ops->mem_enc_op(kvm, argp); 4534 break; 4535 } 4536 case KVM_MEMORY_ENCRYPT_REG_REGION: { 4537 struct kvm_enc_region region; 4538 4539 r = -EFAULT; 4540 if (copy_from_user(®ion, argp, sizeof(region))) 4541 goto out; 4542 4543 r = -ENOTTY; 4544 if (kvm_x86_ops->mem_enc_reg_region) 4545 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion); 4546 break; 4547 } 4548 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 4549 struct kvm_enc_region region; 4550 4551 r = -EFAULT; 4552 if (copy_from_user(®ion, argp, sizeof(region))) 4553 goto out; 4554 4555 r = -ENOTTY; 4556 if (kvm_x86_ops->mem_enc_unreg_region) 4557 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion); 4558 break; 4559 } 4560 case KVM_HYPERV_EVENTFD: { 4561 struct kvm_hyperv_eventfd hvevfd; 4562 4563 r = -EFAULT; 4564 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 4565 goto out; 4566 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 4567 break; 4568 } 4569 default: 4570 r = -ENOTTY; 4571 } 4572 out: 4573 return r; 4574 } 4575 4576 static void kvm_init_msr_list(void) 4577 { 4578 u32 dummy[2]; 4579 unsigned i, j; 4580 4581 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { 4582 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4583 continue; 4584 4585 /* 4586 * Even MSRs that are valid in the host may not be exposed 4587 * to the guests in some cases. 4588 */ 4589 switch (msrs_to_save[i]) { 4590 case MSR_IA32_BNDCFGS: 4591 if (!kvm_x86_ops->mpx_supported()) 4592 continue; 4593 break; 4594 case MSR_TSC_AUX: 4595 if (!kvm_x86_ops->rdtscp_supported()) 4596 continue; 4597 break; 4598 default: 4599 break; 4600 } 4601 4602 if (j < i) 4603 msrs_to_save[j] = msrs_to_save[i]; 4604 j++; 4605 } 4606 num_msrs_to_save = j; 4607 4608 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { 4609 switch (emulated_msrs[i]) { 4610 case MSR_IA32_SMBASE: 4611 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase()) 4612 continue; 4613 break; 4614 default: 4615 break; 4616 } 4617 4618 if (j < i) 4619 emulated_msrs[j] = emulated_msrs[i]; 4620 j++; 4621 } 4622 num_emulated_msrs = j; 4623 4624 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) { 4625 struct kvm_msr_entry msr; 4626 4627 msr.index = msr_based_features[i]; 4628 if (kvm_get_msr_feature(&msr)) 4629 continue; 4630 4631 if (j < i) 4632 msr_based_features[j] = msr_based_features[i]; 4633 j++; 4634 } 4635 num_msr_based_features = j; 4636 } 4637 4638 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 4639 const void *v) 4640 { 4641 int handled = 0; 4642 int n; 4643 4644 do { 4645 n = min(len, 8); 4646 if (!(lapic_in_kernel(vcpu) && 4647 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 4648 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 4649 break; 4650 handled += n; 4651 addr += n; 4652 len -= n; 4653 v += n; 4654 } while (len); 4655 4656 return handled; 4657 } 4658 4659 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4660 { 4661 int handled = 0; 4662 int n; 4663 4664 do { 4665 n = min(len, 8); 4666 if (!(lapic_in_kernel(vcpu) && 4667 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 4668 addr, n, v)) 4669 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 4670 break; 4671 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 4672 handled += n; 4673 addr += n; 4674 len -= n; 4675 v += n; 4676 } while (len); 4677 4678 return handled; 4679 } 4680 4681 static void kvm_set_segment(struct kvm_vcpu *vcpu, 4682 struct kvm_segment *var, int seg) 4683 { 4684 kvm_x86_ops->set_segment(vcpu, var, seg); 4685 } 4686 4687 void kvm_get_segment(struct kvm_vcpu *vcpu, 4688 struct kvm_segment *var, int seg) 4689 { 4690 kvm_x86_ops->get_segment(vcpu, var, seg); 4691 } 4692 4693 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 4694 struct x86_exception *exception) 4695 { 4696 gpa_t t_gpa; 4697 4698 BUG_ON(!mmu_is_nested(vcpu)); 4699 4700 /* NPT walks are always user-walks */ 4701 access |= PFERR_USER_MASK; 4702 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); 4703 4704 return t_gpa; 4705 } 4706 4707 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 4708 struct x86_exception *exception) 4709 { 4710 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4711 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4712 } 4713 4714 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 4715 struct x86_exception *exception) 4716 { 4717 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4718 access |= PFERR_FETCH_MASK; 4719 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4720 } 4721 4722 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 4723 struct x86_exception *exception) 4724 { 4725 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4726 access |= PFERR_WRITE_MASK; 4727 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4728 } 4729 4730 /* uses this to access any guest's mapped memory without checking CPL */ 4731 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 4732 struct x86_exception *exception) 4733 { 4734 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 4735 } 4736 4737 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 4738 struct kvm_vcpu *vcpu, u32 access, 4739 struct x86_exception *exception) 4740 { 4741 void *data = val; 4742 int r = X86EMUL_CONTINUE; 4743 4744 while (bytes) { 4745 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 4746 exception); 4747 unsigned offset = addr & (PAGE_SIZE-1); 4748 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 4749 int ret; 4750 4751 if (gpa == UNMAPPED_GVA) 4752 return X86EMUL_PROPAGATE_FAULT; 4753 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 4754 offset, toread); 4755 if (ret < 0) { 4756 r = X86EMUL_IO_NEEDED; 4757 goto out; 4758 } 4759 4760 bytes -= toread; 4761 data += toread; 4762 addr += toread; 4763 } 4764 out: 4765 return r; 4766 } 4767 4768 /* used for instruction fetching */ 4769 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4770 gva_t addr, void *val, unsigned int bytes, 4771 struct x86_exception *exception) 4772 { 4773 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4774 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4775 unsigned offset; 4776 int ret; 4777 4778 /* Inline kvm_read_guest_virt_helper for speed. */ 4779 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 4780 exception); 4781 if (unlikely(gpa == UNMAPPED_GVA)) 4782 return X86EMUL_PROPAGATE_FAULT; 4783 4784 offset = addr & (PAGE_SIZE-1); 4785 if (WARN_ON(offset + bytes > PAGE_SIZE)) 4786 bytes = (unsigned)PAGE_SIZE - offset; 4787 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 4788 offset, bytes); 4789 if (unlikely(ret < 0)) 4790 return X86EMUL_IO_NEEDED; 4791 4792 return X86EMUL_CONTINUE; 4793 } 4794 4795 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4796 gva_t addr, void *val, unsigned int bytes, 4797 struct x86_exception *exception) 4798 { 4799 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4800 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4801 4802 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4803 exception); 4804 } 4805 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4806 4807 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4808 gva_t addr, void *val, unsigned int bytes, 4809 struct x86_exception *exception) 4810 { 4811 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4812 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4813 } 4814 4815 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 4816 unsigned long addr, void *val, unsigned int bytes) 4817 { 4818 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4819 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 4820 4821 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 4822 } 4823 4824 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4825 gva_t addr, void *val, 4826 unsigned int bytes, 4827 struct x86_exception *exception) 4828 { 4829 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4830 void *data = val; 4831 int r = X86EMUL_CONTINUE; 4832 4833 while (bytes) { 4834 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4835 PFERR_WRITE_MASK, 4836 exception); 4837 unsigned offset = addr & (PAGE_SIZE-1); 4838 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4839 int ret; 4840 4841 if (gpa == UNMAPPED_GVA) 4842 return X86EMUL_PROPAGATE_FAULT; 4843 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 4844 if (ret < 0) { 4845 r = X86EMUL_IO_NEEDED; 4846 goto out; 4847 } 4848 4849 bytes -= towrite; 4850 data += towrite; 4851 addr += towrite; 4852 } 4853 out: 4854 return r; 4855 } 4856 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4857 4858 int handle_ud(struct kvm_vcpu *vcpu) 4859 { 4860 int emul_type = EMULTYPE_TRAP_UD; 4861 enum emulation_result er; 4862 char sig[5]; /* ud2; .ascii "kvm" */ 4863 struct x86_exception e; 4864 4865 if (force_emulation_prefix && 4866 kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, 4867 kvm_get_linear_rip(vcpu), sig, sizeof(sig), &e) == 0 && 4868 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) { 4869 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 4870 emul_type = 0; 4871 } 4872 4873 er = emulate_instruction(vcpu, emul_type); 4874 if (er == EMULATE_USER_EXIT) 4875 return 0; 4876 if (er != EMULATE_DONE) 4877 kvm_queue_exception(vcpu, UD_VECTOR); 4878 return 1; 4879 } 4880 EXPORT_SYMBOL_GPL(handle_ud); 4881 4882 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4883 gpa_t gpa, bool write) 4884 { 4885 /* For APIC access vmexit */ 4886 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4887 return 1; 4888 4889 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 4890 trace_vcpu_match_mmio(gva, gpa, write, true); 4891 return 1; 4892 } 4893 4894 return 0; 4895 } 4896 4897 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4898 gpa_t *gpa, struct x86_exception *exception, 4899 bool write) 4900 { 4901 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4902 | (write ? PFERR_WRITE_MASK : 0); 4903 4904 /* 4905 * currently PKRU is only applied to ept enabled guest so 4906 * there is no pkey in EPT page table for L1 guest or EPT 4907 * shadow page table for L2 guest. 4908 */ 4909 if (vcpu_match_mmio_gva(vcpu, gva) 4910 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4911 vcpu->arch.access, 0, access)) { 4912 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4913 (gva & (PAGE_SIZE - 1)); 4914 trace_vcpu_match_mmio(gva, *gpa, write, false); 4915 return 1; 4916 } 4917 4918 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4919 4920 if (*gpa == UNMAPPED_GVA) 4921 return -1; 4922 4923 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 4924 } 4925 4926 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4927 const void *val, int bytes) 4928 { 4929 int ret; 4930 4931 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 4932 if (ret < 0) 4933 return 0; 4934 kvm_page_track_write(vcpu, gpa, val, bytes); 4935 return 1; 4936 } 4937 4938 struct read_write_emulator_ops { 4939 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4940 int bytes); 4941 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4942 void *val, int bytes); 4943 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4944 int bytes, void *val); 4945 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4946 void *val, int bytes); 4947 bool write; 4948 }; 4949 4950 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4951 { 4952 if (vcpu->mmio_read_completed) { 4953 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4954 vcpu->mmio_fragments[0].gpa, val); 4955 vcpu->mmio_read_completed = 0; 4956 return 1; 4957 } 4958 4959 return 0; 4960 } 4961 4962 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4963 void *val, int bytes) 4964 { 4965 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 4966 } 4967 4968 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4969 void *val, int bytes) 4970 { 4971 return emulator_write_phys(vcpu, gpa, val, bytes); 4972 } 4973 4974 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4975 { 4976 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 4977 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4978 } 4979 4980 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4981 void *val, int bytes) 4982 { 4983 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 4984 return X86EMUL_IO_NEEDED; 4985 } 4986 4987 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4988 void *val, int bytes) 4989 { 4990 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4991 4992 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4993 return X86EMUL_CONTINUE; 4994 } 4995 4996 static const struct read_write_emulator_ops read_emultor = { 4997 .read_write_prepare = read_prepare, 4998 .read_write_emulate = read_emulate, 4999 .read_write_mmio = vcpu_mmio_read, 5000 .read_write_exit_mmio = read_exit_mmio, 5001 }; 5002 5003 static const struct read_write_emulator_ops write_emultor = { 5004 .read_write_emulate = write_emulate, 5005 .read_write_mmio = write_mmio, 5006 .read_write_exit_mmio = write_exit_mmio, 5007 .write = true, 5008 }; 5009 5010 static int emulator_read_write_onepage(unsigned long addr, void *val, 5011 unsigned int bytes, 5012 struct x86_exception *exception, 5013 struct kvm_vcpu *vcpu, 5014 const struct read_write_emulator_ops *ops) 5015 { 5016 gpa_t gpa; 5017 int handled, ret; 5018 bool write = ops->write; 5019 struct kvm_mmio_fragment *frag; 5020 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5021 5022 /* 5023 * If the exit was due to a NPF we may already have a GPA. 5024 * If the GPA is present, use it to avoid the GVA to GPA table walk. 5025 * Note, this cannot be used on string operations since string 5026 * operation using rep will only have the initial GPA from the NPF 5027 * occurred. 5028 */ 5029 if (vcpu->arch.gpa_available && 5030 emulator_can_use_gpa(ctxt) && 5031 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) { 5032 gpa = vcpu->arch.gpa_val; 5033 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 5034 } else { 5035 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 5036 if (ret < 0) 5037 return X86EMUL_PROPAGATE_FAULT; 5038 } 5039 5040 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 5041 return X86EMUL_CONTINUE; 5042 5043 /* 5044 * Is this MMIO handled locally? 5045 */ 5046 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 5047 if (handled == bytes) 5048 return X86EMUL_CONTINUE; 5049 5050 gpa += handled; 5051 bytes -= handled; 5052 val += handled; 5053 5054 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 5055 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 5056 frag->gpa = gpa; 5057 frag->data = val; 5058 frag->len = bytes; 5059 return X86EMUL_CONTINUE; 5060 } 5061 5062 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 5063 unsigned long addr, 5064 void *val, unsigned int bytes, 5065 struct x86_exception *exception, 5066 const struct read_write_emulator_ops *ops) 5067 { 5068 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5069 gpa_t gpa; 5070 int rc; 5071 5072 if (ops->read_write_prepare && 5073 ops->read_write_prepare(vcpu, val, bytes)) 5074 return X86EMUL_CONTINUE; 5075 5076 vcpu->mmio_nr_fragments = 0; 5077 5078 /* Crossing a page boundary? */ 5079 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 5080 int now; 5081 5082 now = -addr & ~PAGE_MASK; 5083 rc = emulator_read_write_onepage(addr, val, now, exception, 5084 vcpu, ops); 5085 5086 if (rc != X86EMUL_CONTINUE) 5087 return rc; 5088 addr += now; 5089 if (ctxt->mode != X86EMUL_MODE_PROT64) 5090 addr = (u32)addr; 5091 val += now; 5092 bytes -= now; 5093 } 5094 5095 rc = emulator_read_write_onepage(addr, val, bytes, exception, 5096 vcpu, ops); 5097 if (rc != X86EMUL_CONTINUE) 5098 return rc; 5099 5100 if (!vcpu->mmio_nr_fragments) 5101 return rc; 5102 5103 gpa = vcpu->mmio_fragments[0].gpa; 5104 5105 vcpu->mmio_needed = 1; 5106 vcpu->mmio_cur_fragment = 0; 5107 5108 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 5109 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 5110 vcpu->run->exit_reason = KVM_EXIT_MMIO; 5111 vcpu->run->mmio.phys_addr = gpa; 5112 5113 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 5114 } 5115 5116 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 5117 unsigned long addr, 5118 void *val, 5119 unsigned int bytes, 5120 struct x86_exception *exception) 5121 { 5122 return emulator_read_write(ctxt, addr, val, bytes, 5123 exception, &read_emultor); 5124 } 5125 5126 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 5127 unsigned long addr, 5128 const void *val, 5129 unsigned int bytes, 5130 struct x86_exception *exception) 5131 { 5132 return emulator_read_write(ctxt, addr, (void *)val, bytes, 5133 exception, &write_emultor); 5134 } 5135 5136 #define CMPXCHG_TYPE(t, ptr, old, new) \ 5137 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 5138 5139 #ifdef CONFIG_X86_64 5140 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 5141 #else 5142 # define CMPXCHG64(ptr, old, new) \ 5143 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 5144 #endif 5145 5146 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 5147 unsigned long addr, 5148 const void *old, 5149 const void *new, 5150 unsigned int bytes, 5151 struct x86_exception *exception) 5152 { 5153 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5154 gpa_t gpa; 5155 struct page *page; 5156 char *kaddr; 5157 bool exchanged; 5158 5159 /* guests cmpxchg8b have to be emulated atomically */ 5160 if (bytes > 8 || (bytes & (bytes - 1))) 5161 goto emul_write; 5162 5163 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 5164 5165 if (gpa == UNMAPPED_GVA || 5166 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 5167 goto emul_write; 5168 5169 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 5170 goto emul_write; 5171 5172 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); 5173 if (is_error_page(page)) 5174 goto emul_write; 5175 5176 kaddr = kmap_atomic(page); 5177 kaddr += offset_in_page(gpa); 5178 switch (bytes) { 5179 case 1: 5180 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 5181 break; 5182 case 2: 5183 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 5184 break; 5185 case 4: 5186 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 5187 break; 5188 case 8: 5189 exchanged = CMPXCHG64(kaddr, old, new); 5190 break; 5191 default: 5192 BUG(); 5193 } 5194 kunmap_atomic(kaddr); 5195 kvm_release_page_dirty(page); 5196 5197 if (!exchanged) 5198 return X86EMUL_CMPXCHG_FAILED; 5199 5200 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5201 kvm_page_track_write(vcpu, gpa, new, bytes); 5202 5203 return X86EMUL_CONTINUE; 5204 5205 emul_write: 5206 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 5207 5208 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 5209 } 5210 5211 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 5212 { 5213 int r = 0, i; 5214 5215 for (i = 0; i < vcpu->arch.pio.count; i++) { 5216 if (vcpu->arch.pio.in) 5217 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 5218 vcpu->arch.pio.size, pd); 5219 else 5220 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 5221 vcpu->arch.pio.port, vcpu->arch.pio.size, 5222 pd); 5223 if (r) 5224 break; 5225 pd += vcpu->arch.pio.size; 5226 } 5227 return r; 5228 } 5229 5230 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 5231 unsigned short port, void *val, 5232 unsigned int count, bool in) 5233 { 5234 vcpu->arch.pio.port = port; 5235 vcpu->arch.pio.in = in; 5236 vcpu->arch.pio.count = count; 5237 vcpu->arch.pio.size = size; 5238 5239 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 5240 vcpu->arch.pio.count = 0; 5241 return 1; 5242 } 5243 5244 vcpu->run->exit_reason = KVM_EXIT_IO; 5245 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 5246 vcpu->run->io.size = size; 5247 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 5248 vcpu->run->io.count = count; 5249 vcpu->run->io.port = port; 5250 5251 return 0; 5252 } 5253 5254 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 5255 int size, unsigned short port, void *val, 5256 unsigned int count) 5257 { 5258 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5259 int ret; 5260 5261 if (vcpu->arch.pio.count) 5262 goto data_avail; 5263 5264 memset(vcpu->arch.pio_data, 0, size * count); 5265 5266 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 5267 if (ret) { 5268 data_avail: 5269 memcpy(val, vcpu->arch.pio_data, size * count); 5270 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 5271 vcpu->arch.pio.count = 0; 5272 return 1; 5273 } 5274 5275 return 0; 5276 } 5277 5278 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 5279 int size, unsigned short port, 5280 const void *val, unsigned int count) 5281 { 5282 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5283 5284 memcpy(vcpu->arch.pio_data, val, size * count); 5285 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 5286 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 5287 } 5288 5289 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 5290 { 5291 return kvm_x86_ops->get_segment_base(vcpu, seg); 5292 } 5293 5294 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 5295 { 5296 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 5297 } 5298 5299 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 5300 { 5301 if (!need_emulate_wbinvd(vcpu)) 5302 return X86EMUL_CONTINUE; 5303 5304 if (kvm_x86_ops->has_wbinvd_exit()) { 5305 int cpu = get_cpu(); 5306 5307 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 5308 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 5309 wbinvd_ipi, NULL, 1); 5310 put_cpu(); 5311 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 5312 } else 5313 wbinvd(); 5314 return X86EMUL_CONTINUE; 5315 } 5316 5317 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 5318 { 5319 kvm_emulate_wbinvd_noskip(vcpu); 5320 return kvm_skip_emulated_instruction(vcpu); 5321 } 5322 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 5323 5324 5325 5326 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 5327 { 5328 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 5329 } 5330 5331 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 5332 unsigned long *dest) 5333 { 5334 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 5335 } 5336 5337 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 5338 unsigned long value) 5339 { 5340 5341 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 5342 } 5343 5344 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 5345 { 5346 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 5347 } 5348 5349 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 5350 { 5351 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5352 unsigned long value; 5353 5354 switch (cr) { 5355 case 0: 5356 value = kvm_read_cr0(vcpu); 5357 break; 5358 case 2: 5359 value = vcpu->arch.cr2; 5360 break; 5361 case 3: 5362 value = kvm_read_cr3(vcpu); 5363 break; 5364 case 4: 5365 value = kvm_read_cr4(vcpu); 5366 break; 5367 case 8: 5368 value = kvm_get_cr8(vcpu); 5369 break; 5370 default: 5371 kvm_err("%s: unexpected cr %u\n", __func__, cr); 5372 return 0; 5373 } 5374 5375 return value; 5376 } 5377 5378 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 5379 { 5380 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5381 int res = 0; 5382 5383 switch (cr) { 5384 case 0: 5385 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 5386 break; 5387 case 2: 5388 vcpu->arch.cr2 = val; 5389 break; 5390 case 3: 5391 res = kvm_set_cr3(vcpu, val); 5392 break; 5393 case 4: 5394 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 5395 break; 5396 case 8: 5397 res = kvm_set_cr8(vcpu, val); 5398 break; 5399 default: 5400 kvm_err("%s: unexpected cr %u\n", __func__, cr); 5401 res = -1; 5402 } 5403 5404 return res; 5405 } 5406 5407 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 5408 { 5409 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 5410 } 5411 5412 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5413 { 5414 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 5415 } 5416 5417 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5418 { 5419 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 5420 } 5421 5422 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5423 { 5424 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 5425 } 5426 5427 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5428 { 5429 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 5430 } 5431 5432 static unsigned long emulator_get_cached_segment_base( 5433 struct x86_emulate_ctxt *ctxt, int seg) 5434 { 5435 return get_segment_base(emul_to_vcpu(ctxt), seg); 5436 } 5437 5438 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 5439 struct desc_struct *desc, u32 *base3, 5440 int seg) 5441 { 5442 struct kvm_segment var; 5443 5444 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 5445 *selector = var.selector; 5446 5447 if (var.unusable) { 5448 memset(desc, 0, sizeof(*desc)); 5449 if (base3) 5450 *base3 = 0; 5451 return false; 5452 } 5453 5454 if (var.g) 5455 var.limit >>= 12; 5456 set_desc_limit(desc, var.limit); 5457 set_desc_base(desc, (unsigned long)var.base); 5458 #ifdef CONFIG_X86_64 5459 if (base3) 5460 *base3 = var.base >> 32; 5461 #endif 5462 desc->type = var.type; 5463 desc->s = var.s; 5464 desc->dpl = var.dpl; 5465 desc->p = var.present; 5466 desc->avl = var.avl; 5467 desc->l = var.l; 5468 desc->d = var.db; 5469 desc->g = var.g; 5470 5471 return true; 5472 } 5473 5474 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 5475 struct desc_struct *desc, u32 base3, 5476 int seg) 5477 { 5478 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5479 struct kvm_segment var; 5480 5481 var.selector = selector; 5482 var.base = get_desc_base(desc); 5483 #ifdef CONFIG_X86_64 5484 var.base |= ((u64)base3) << 32; 5485 #endif 5486 var.limit = get_desc_limit(desc); 5487 if (desc->g) 5488 var.limit = (var.limit << 12) | 0xfff; 5489 var.type = desc->type; 5490 var.dpl = desc->dpl; 5491 var.db = desc->d; 5492 var.s = desc->s; 5493 var.l = desc->l; 5494 var.g = desc->g; 5495 var.avl = desc->avl; 5496 var.present = desc->p; 5497 var.unusable = !var.present; 5498 var.padding = 0; 5499 5500 kvm_set_segment(vcpu, &var, seg); 5501 return; 5502 } 5503 5504 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 5505 u32 msr_index, u64 *pdata) 5506 { 5507 struct msr_data msr; 5508 int r; 5509 5510 msr.index = msr_index; 5511 msr.host_initiated = false; 5512 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); 5513 if (r) 5514 return r; 5515 5516 *pdata = msr.data; 5517 return 0; 5518 } 5519 5520 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 5521 u32 msr_index, u64 data) 5522 { 5523 struct msr_data msr; 5524 5525 msr.data = data; 5526 msr.index = msr_index; 5527 msr.host_initiated = false; 5528 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 5529 } 5530 5531 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 5532 { 5533 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5534 5535 return vcpu->arch.smbase; 5536 } 5537 5538 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 5539 { 5540 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5541 5542 vcpu->arch.smbase = smbase; 5543 } 5544 5545 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 5546 u32 pmc) 5547 { 5548 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); 5549 } 5550 5551 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 5552 u32 pmc, u64 *pdata) 5553 { 5554 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 5555 } 5556 5557 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 5558 { 5559 emul_to_vcpu(ctxt)->arch.halt_request = 1; 5560 } 5561 5562 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 5563 struct x86_instruction_info *info, 5564 enum x86_intercept_stage stage) 5565 { 5566 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 5567 } 5568 5569 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 5570 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit) 5571 { 5572 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit); 5573 } 5574 5575 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 5576 { 5577 return kvm_register_read(emul_to_vcpu(ctxt), reg); 5578 } 5579 5580 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 5581 { 5582 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 5583 } 5584 5585 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 5586 { 5587 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 5588 } 5589 5590 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 5591 { 5592 return emul_to_vcpu(ctxt)->arch.hflags; 5593 } 5594 5595 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) 5596 { 5597 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags); 5598 } 5599 5600 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase) 5601 { 5602 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase); 5603 } 5604 5605 static const struct x86_emulate_ops emulate_ops = { 5606 .read_gpr = emulator_read_gpr, 5607 .write_gpr = emulator_write_gpr, 5608 .read_std = kvm_read_guest_virt_system, 5609 .write_std = kvm_write_guest_virt_system, 5610 .read_phys = kvm_read_guest_phys_system, 5611 .fetch = kvm_fetch_guest_virt, 5612 .read_emulated = emulator_read_emulated, 5613 .write_emulated = emulator_write_emulated, 5614 .cmpxchg_emulated = emulator_cmpxchg_emulated, 5615 .invlpg = emulator_invlpg, 5616 .pio_in_emulated = emulator_pio_in_emulated, 5617 .pio_out_emulated = emulator_pio_out_emulated, 5618 .get_segment = emulator_get_segment, 5619 .set_segment = emulator_set_segment, 5620 .get_cached_segment_base = emulator_get_cached_segment_base, 5621 .get_gdt = emulator_get_gdt, 5622 .get_idt = emulator_get_idt, 5623 .set_gdt = emulator_set_gdt, 5624 .set_idt = emulator_set_idt, 5625 .get_cr = emulator_get_cr, 5626 .set_cr = emulator_set_cr, 5627 .cpl = emulator_get_cpl, 5628 .get_dr = emulator_get_dr, 5629 .set_dr = emulator_set_dr, 5630 .get_smbase = emulator_get_smbase, 5631 .set_smbase = emulator_set_smbase, 5632 .set_msr = emulator_set_msr, 5633 .get_msr = emulator_get_msr, 5634 .check_pmc = emulator_check_pmc, 5635 .read_pmc = emulator_read_pmc, 5636 .halt = emulator_halt, 5637 .wbinvd = emulator_wbinvd, 5638 .fix_hypercall = emulator_fix_hypercall, 5639 .intercept = emulator_intercept, 5640 .get_cpuid = emulator_get_cpuid, 5641 .set_nmi_mask = emulator_set_nmi_mask, 5642 .get_hflags = emulator_get_hflags, 5643 .set_hflags = emulator_set_hflags, 5644 .pre_leave_smm = emulator_pre_leave_smm, 5645 }; 5646 5647 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 5648 { 5649 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 5650 /* 5651 * an sti; sti; sequence only disable interrupts for the first 5652 * instruction. So, if the last instruction, be it emulated or 5653 * not, left the system with the INT_STI flag enabled, it 5654 * means that the last instruction is an sti. We should not 5655 * leave the flag on in this case. The same goes for mov ss 5656 */ 5657 if (int_shadow & mask) 5658 mask = 0; 5659 if (unlikely(int_shadow || mask)) { 5660 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 5661 if (!mask) 5662 kvm_make_request(KVM_REQ_EVENT, vcpu); 5663 } 5664 } 5665 5666 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 5667 { 5668 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5669 if (ctxt->exception.vector == PF_VECTOR) 5670 return kvm_propagate_fault(vcpu, &ctxt->exception); 5671 5672 if (ctxt->exception.error_code_valid) 5673 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 5674 ctxt->exception.error_code); 5675 else 5676 kvm_queue_exception(vcpu, ctxt->exception.vector); 5677 return false; 5678 } 5679 5680 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 5681 { 5682 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5683 int cs_db, cs_l; 5684 5685 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 5686 5687 ctxt->eflags = kvm_get_rflags(vcpu); 5688 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 5689 5690 ctxt->eip = kvm_rip_read(vcpu); 5691 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 5692 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 5693 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 5694 cs_db ? X86EMUL_MODE_PROT32 : 5695 X86EMUL_MODE_PROT16; 5696 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 5697 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 5698 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 5699 5700 init_decode_cache(ctxt); 5701 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5702 } 5703 5704 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 5705 { 5706 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5707 int ret; 5708 5709 init_emulate_ctxt(vcpu); 5710 5711 ctxt->op_bytes = 2; 5712 ctxt->ad_bytes = 2; 5713 ctxt->_eip = ctxt->eip + inc_eip; 5714 ret = emulate_int_real(ctxt, irq); 5715 5716 if (ret != X86EMUL_CONTINUE) 5717 return EMULATE_FAIL; 5718 5719 ctxt->eip = ctxt->_eip; 5720 kvm_rip_write(vcpu, ctxt->eip); 5721 kvm_set_rflags(vcpu, ctxt->eflags); 5722 5723 return EMULATE_DONE; 5724 } 5725 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 5726 5727 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 5728 { 5729 int r = EMULATE_DONE; 5730 5731 ++vcpu->stat.insn_emulation_fail; 5732 trace_kvm_emulate_insn_failed(vcpu); 5733 5734 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL) 5735 return EMULATE_FAIL; 5736 5737 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 5738 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5739 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 5740 vcpu->run->internal.ndata = 0; 5741 r = EMULATE_USER_EXIT; 5742 } 5743 5744 kvm_queue_exception(vcpu, UD_VECTOR); 5745 5746 return r; 5747 } 5748 5749 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 5750 bool write_fault_to_shadow_pgtable, 5751 int emulation_type) 5752 { 5753 gpa_t gpa = cr2; 5754 kvm_pfn_t pfn; 5755 5756 if (emulation_type & EMULTYPE_NO_REEXECUTE) 5757 return false; 5758 5759 if (!vcpu->arch.mmu.direct_map) { 5760 /* 5761 * Write permission should be allowed since only 5762 * write access need to be emulated. 5763 */ 5764 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5765 5766 /* 5767 * If the mapping is invalid in guest, let cpu retry 5768 * it to generate fault. 5769 */ 5770 if (gpa == UNMAPPED_GVA) 5771 return true; 5772 } 5773 5774 /* 5775 * Do not retry the unhandleable instruction if it faults on the 5776 * readonly host memory, otherwise it will goto a infinite loop: 5777 * retry instruction -> write #PF -> emulation fail -> retry 5778 * instruction -> ... 5779 */ 5780 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 5781 5782 /* 5783 * If the instruction failed on the error pfn, it can not be fixed, 5784 * report the error to userspace. 5785 */ 5786 if (is_error_noslot_pfn(pfn)) 5787 return false; 5788 5789 kvm_release_pfn_clean(pfn); 5790 5791 /* The instructions are well-emulated on direct mmu. */ 5792 if (vcpu->arch.mmu.direct_map) { 5793 unsigned int indirect_shadow_pages; 5794 5795 spin_lock(&vcpu->kvm->mmu_lock); 5796 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 5797 spin_unlock(&vcpu->kvm->mmu_lock); 5798 5799 if (indirect_shadow_pages) 5800 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5801 5802 return true; 5803 } 5804 5805 /* 5806 * if emulation was due to access to shadowed page table 5807 * and it failed try to unshadow page and re-enter the 5808 * guest to let CPU execute the instruction. 5809 */ 5810 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5811 5812 /* 5813 * If the access faults on its page table, it can not 5814 * be fixed by unprotecting shadow page and it should 5815 * be reported to userspace. 5816 */ 5817 return !write_fault_to_shadow_pgtable; 5818 } 5819 5820 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5821 unsigned long cr2, int emulation_type) 5822 { 5823 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5824 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5825 5826 last_retry_eip = vcpu->arch.last_retry_eip; 5827 last_retry_addr = vcpu->arch.last_retry_addr; 5828 5829 /* 5830 * If the emulation is caused by #PF and it is non-page_table 5831 * writing instruction, it means the VM-EXIT is caused by shadow 5832 * page protected, we can zap the shadow page and retry this 5833 * instruction directly. 5834 * 5835 * Note: if the guest uses a non-page-table modifying instruction 5836 * on the PDE that points to the instruction, then we will unmap 5837 * the instruction and go to an infinite loop. So, we cache the 5838 * last retried eip and the last fault address, if we meet the eip 5839 * and the address again, we can break out of the potential infinite 5840 * loop. 5841 */ 5842 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5843 5844 if (!(emulation_type & EMULTYPE_RETRY)) 5845 return false; 5846 5847 if (x86_page_table_writing_insn(ctxt)) 5848 return false; 5849 5850 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5851 return false; 5852 5853 vcpu->arch.last_retry_eip = ctxt->eip; 5854 vcpu->arch.last_retry_addr = cr2; 5855 5856 if (!vcpu->arch.mmu.direct_map) 5857 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5858 5859 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5860 5861 return true; 5862 } 5863 5864 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5865 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5866 5867 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 5868 { 5869 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 5870 /* This is a good place to trace that we are exiting SMM. */ 5871 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 5872 5873 /* Process a latched INIT or SMI, if any. */ 5874 kvm_make_request(KVM_REQ_EVENT, vcpu); 5875 } 5876 5877 kvm_mmu_reset_context(vcpu); 5878 } 5879 5880 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) 5881 { 5882 unsigned changed = vcpu->arch.hflags ^ emul_flags; 5883 5884 vcpu->arch.hflags = emul_flags; 5885 5886 if (changed & HF_SMM_MASK) 5887 kvm_smm_changed(vcpu); 5888 } 5889 5890 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5891 unsigned long *db) 5892 { 5893 u32 dr6 = 0; 5894 int i; 5895 u32 enable, rwlen; 5896 5897 enable = dr7; 5898 rwlen = dr7 >> 16; 5899 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5900 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5901 dr6 |= (1 << i); 5902 return dr6; 5903 } 5904 5905 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r) 5906 { 5907 struct kvm_run *kvm_run = vcpu->run; 5908 5909 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5910 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; 5911 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5912 kvm_run->debug.arch.exception = DB_VECTOR; 5913 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5914 *r = EMULATE_USER_EXIT; 5915 } else { 5916 /* 5917 * "Certain debug exceptions may clear bit 0-3. The 5918 * remaining contents of the DR6 register are never 5919 * cleared by the processor". 5920 */ 5921 vcpu->arch.dr6 &= ~15; 5922 vcpu->arch.dr6 |= DR6_BS | DR6_RTM; 5923 kvm_queue_exception(vcpu, DB_VECTOR); 5924 } 5925 } 5926 5927 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 5928 { 5929 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5930 int r = EMULATE_DONE; 5931 5932 kvm_x86_ops->skip_emulated_instruction(vcpu); 5933 5934 /* 5935 * rflags is the old, "raw" value of the flags. The new value has 5936 * not been saved yet. 5937 * 5938 * This is correct even for TF set by the guest, because "the 5939 * processor will not generate this exception after the instruction 5940 * that sets the TF flag". 5941 */ 5942 if (unlikely(rflags & X86_EFLAGS_TF)) 5943 kvm_vcpu_do_singlestep(vcpu, &r); 5944 return r == EMULATE_DONE; 5945 } 5946 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 5947 5948 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5949 { 5950 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5951 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5952 struct kvm_run *kvm_run = vcpu->run; 5953 unsigned long eip = kvm_get_linear_rip(vcpu); 5954 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5955 vcpu->arch.guest_debug_dr7, 5956 vcpu->arch.eff_db); 5957 5958 if (dr6 != 0) { 5959 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 5960 kvm_run->debug.arch.pc = eip; 5961 kvm_run->debug.arch.exception = DB_VECTOR; 5962 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5963 *r = EMULATE_USER_EXIT; 5964 return true; 5965 } 5966 } 5967 5968 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 5969 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 5970 unsigned long eip = kvm_get_linear_rip(vcpu); 5971 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5972 vcpu->arch.dr7, 5973 vcpu->arch.db); 5974 5975 if (dr6 != 0) { 5976 vcpu->arch.dr6 &= ~15; 5977 vcpu->arch.dr6 |= dr6 | DR6_RTM; 5978 kvm_queue_exception(vcpu, DB_VECTOR); 5979 *r = EMULATE_DONE; 5980 return true; 5981 } 5982 } 5983 5984 return false; 5985 } 5986 5987 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 5988 { 5989 switch (ctxt->opcode_len) { 5990 case 1: 5991 switch (ctxt->b) { 5992 case 0xe4: /* IN */ 5993 case 0xe5: 5994 case 0xec: 5995 case 0xed: 5996 case 0xe6: /* OUT */ 5997 case 0xe7: 5998 case 0xee: 5999 case 0xef: 6000 case 0x6c: /* INS */ 6001 case 0x6d: 6002 case 0x6e: /* OUTS */ 6003 case 0x6f: 6004 return true; 6005 } 6006 break; 6007 case 2: 6008 switch (ctxt->b) { 6009 case 0x33: /* RDPMC */ 6010 return true; 6011 } 6012 break; 6013 } 6014 6015 return false; 6016 } 6017 6018 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 6019 unsigned long cr2, 6020 int emulation_type, 6021 void *insn, 6022 int insn_len) 6023 { 6024 int r; 6025 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6026 bool writeback = true; 6027 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 6028 6029 /* 6030 * Clear write_fault_to_shadow_pgtable here to ensure it is 6031 * never reused. 6032 */ 6033 vcpu->arch.write_fault_to_shadow_pgtable = false; 6034 kvm_clear_exception_queue(vcpu); 6035 6036 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 6037 init_emulate_ctxt(vcpu); 6038 6039 /* 6040 * We will reenter on the same instruction since 6041 * we do not set complete_userspace_io. This does not 6042 * handle watchpoints yet, those would be handled in 6043 * the emulate_ops. 6044 */ 6045 if (!(emulation_type & EMULTYPE_SKIP) && 6046 kvm_vcpu_check_breakpoint(vcpu, &r)) 6047 return r; 6048 6049 ctxt->interruptibility = 0; 6050 ctxt->have_exception = false; 6051 ctxt->exception.vector = -1; 6052 ctxt->perm_ok = false; 6053 6054 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 6055 6056 r = x86_decode_insn(ctxt, insn, insn_len); 6057 6058 trace_kvm_emulate_insn_start(vcpu); 6059 ++vcpu->stat.insn_emulation; 6060 if (r != EMULATION_OK) { 6061 if (emulation_type & EMULTYPE_TRAP_UD) 6062 return EMULATE_FAIL; 6063 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 6064 emulation_type)) 6065 return EMULATE_DONE; 6066 if (ctxt->have_exception && inject_emulated_exception(vcpu)) 6067 return EMULATE_DONE; 6068 if (emulation_type & EMULTYPE_SKIP) 6069 return EMULATE_FAIL; 6070 return handle_emulation_failure(vcpu, emulation_type); 6071 } 6072 } 6073 6074 if ((emulation_type & EMULTYPE_VMWARE) && 6075 !is_vmware_backdoor_opcode(ctxt)) 6076 return EMULATE_FAIL; 6077 6078 if (emulation_type & EMULTYPE_SKIP) { 6079 kvm_rip_write(vcpu, ctxt->_eip); 6080 if (ctxt->eflags & X86_EFLAGS_RF) 6081 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 6082 return EMULATE_DONE; 6083 } 6084 6085 if (retry_instruction(ctxt, cr2, emulation_type)) 6086 return EMULATE_DONE; 6087 6088 /* this is needed for vmware backdoor interface to work since it 6089 changes registers values during IO operation */ 6090 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 6091 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 6092 emulator_invalidate_register_cache(ctxt); 6093 } 6094 6095 restart: 6096 /* Save the faulting GPA (cr2) in the address field */ 6097 ctxt->exception.address = cr2; 6098 6099 r = x86_emulate_insn(ctxt); 6100 6101 if (r == EMULATION_INTERCEPTED) 6102 return EMULATE_DONE; 6103 6104 if (r == EMULATION_FAILED) { 6105 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 6106 emulation_type)) 6107 return EMULATE_DONE; 6108 6109 return handle_emulation_failure(vcpu, emulation_type); 6110 } 6111 6112 if (ctxt->have_exception) { 6113 r = EMULATE_DONE; 6114 if (inject_emulated_exception(vcpu)) 6115 return r; 6116 } else if (vcpu->arch.pio.count) { 6117 if (!vcpu->arch.pio.in) { 6118 /* FIXME: return into emulator if single-stepping. */ 6119 vcpu->arch.pio.count = 0; 6120 } else { 6121 writeback = false; 6122 vcpu->arch.complete_userspace_io = complete_emulated_pio; 6123 } 6124 r = EMULATE_USER_EXIT; 6125 } else if (vcpu->mmio_needed) { 6126 if (!vcpu->mmio_is_write) 6127 writeback = false; 6128 r = EMULATE_USER_EXIT; 6129 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6130 } else if (r == EMULATION_RESTART) 6131 goto restart; 6132 else 6133 r = EMULATE_DONE; 6134 6135 if (writeback) { 6136 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 6137 toggle_interruptibility(vcpu, ctxt->interruptibility); 6138 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6139 kvm_rip_write(vcpu, ctxt->eip); 6140 if (r == EMULATE_DONE && 6141 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 6142 kvm_vcpu_do_singlestep(vcpu, &r); 6143 if (!ctxt->have_exception || 6144 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 6145 __kvm_set_rflags(vcpu, ctxt->eflags); 6146 6147 /* 6148 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 6149 * do nothing, and it will be requested again as soon as 6150 * the shadow expires. But we still need to check here, 6151 * because POPF has no interrupt shadow. 6152 */ 6153 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 6154 kvm_make_request(KVM_REQ_EVENT, vcpu); 6155 } else 6156 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 6157 6158 return r; 6159 } 6160 EXPORT_SYMBOL_GPL(x86_emulate_instruction); 6161 6162 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 6163 unsigned short port) 6164 { 6165 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 6166 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 6167 size, port, &val, 1); 6168 /* do not return to emulator after return from userspace */ 6169 vcpu->arch.pio.count = 0; 6170 return ret; 6171 } 6172 6173 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 6174 { 6175 unsigned long val; 6176 6177 /* We should only ever be called with arch.pio.count equal to 1 */ 6178 BUG_ON(vcpu->arch.pio.count != 1); 6179 6180 /* For size less than 4 we merge, else we zero extend */ 6181 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) 6182 : 0; 6183 6184 /* 6185 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform 6186 * the copy and tracing 6187 */ 6188 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size, 6189 vcpu->arch.pio.port, &val, 1); 6190 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 6191 6192 return 1; 6193 } 6194 6195 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 6196 unsigned short port) 6197 { 6198 unsigned long val; 6199 int ret; 6200 6201 /* For size less than 4 we merge, else we zero extend */ 6202 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0; 6203 6204 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port, 6205 &val, 1); 6206 if (ret) { 6207 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 6208 return ret; 6209 } 6210 6211 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 6212 6213 return 0; 6214 } 6215 6216 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 6217 { 6218 int ret = kvm_skip_emulated_instruction(vcpu); 6219 6220 /* 6221 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered 6222 * KVM_EXIT_DEBUG here. 6223 */ 6224 if (in) 6225 return kvm_fast_pio_in(vcpu, size, port) && ret; 6226 else 6227 return kvm_fast_pio_out(vcpu, size, port) && ret; 6228 } 6229 EXPORT_SYMBOL_GPL(kvm_fast_pio); 6230 6231 static int kvmclock_cpu_down_prep(unsigned int cpu) 6232 { 6233 __this_cpu_write(cpu_tsc_khz, 0); 6234 return 0; 6235 } 6236 6237 static void tsc_khz_changed(void *data) 6238 { 6239 struct cpufreq_freqs *freq = data; 6240 unsigned long khz = 0; 6241 6242 if (data) 6243 khz = freq->new; 6244 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 6245 khz = cpufreq_quick_get(raw_smp_processor_id()); 6246 if (!khz) 6247 khz = tsc_khz; 6248 __this_cpu_write(cpu_tsc_khz, khz); 6249 } 6250 6251 #ifdef CONFIG_X86_64 6252 static void kvm_hyperv_tsc_notifier(void) 6253 { 6254 struct kvm *kvm; 6255 struct kvm_vcpu *vcpu; 6256 int cpu; 6257 6258 spin_lock(&kvm_lock); 6259 list_for_each_entry(kvm, &vm_list, vm_list) 6260 kvm_make_mclock_inprogress_request(kvm); 6261 6262 hyperv_stop_tsc_emulation(); 6263 6264 /* TSC frequency always matches when on Hyper-V */ 6265 for_each_present_cpu(cpu) 6266 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 6267 kvm_max_guest_tsc_khz = tsc_khz; 6268 6269 list_for_each_entry(kvm, &vm_list, vm_list) { 6270 struct kvm_arch *ka = &kvm->arch; 6271 6272 spin_lock(&ka->pvclock_gtod_sync_lock); 6273 6274 pvclock_update_vm_gtod_copy(kvm); 6275 6276 kvm_for_each_vcpu(cpu, vcpu, kvm) 6277 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6278 6279 kvm_for_each_vcpu(cpu, vcpu, kvm) 6280 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 6281 6282 spin_unlock(&ka->pvclock_gtod_sync_lock); 6283 } 6284 spin_unlock(&kvm_lock); 6285 } 6286 #endif 6287 6288 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 6289 void *data) 6290 { 6291 struct cpufreq_freqs *freq = data; 6292 struct kvm *kvm; 6293 struct kvm_vcpu *vcpu; 6294 int i, send_ipi = 0; 6295 6296 /* 6297 * We allow guests to temporarily run on slowing clocks, 6298 * provided we notify them after, or to run on accelerating 6299 * clocks, provided we notify them before. Thus time never 6300 * goes backwards. 6301 * 6302 * However, we have a problem. We can't atomically update 6303 * the frequency of a given CPU from this function; it is 6304 * merely a notifier, which can be called from any CPU. 6305 * Changing the TSC frequency at arbitrary points in time 6306 * requires a recomputation of local variables related to 6307 * the TSC for each VCPU. We must flag these local variables 6308 * to be updated and be sure the update takes place with the 6309 * new frequency before any guests proceed. 6310 * 6311 * Unfortunately, the combination of hotplug CPU and frequency 6312 * change creates an intractable locking scenario; the order 6313 * of when these callouts happen is undefined with respect to 6314 * CPU hotplug, and they can race with each other. As such, 6315 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 6316 * undefined; you can actually have a CPU frequency change take 6317 * place in between the computation of X and the setting of the 6318 * variable. To protect against this problem, all updates of 6319 * the per_cpu tsc_khz variable are done in an interrupt 6320 * protected IPI, and all callers wishing to update the value 6321 * must wait for a synchronous IPI to complete (which is trivial 6322 * if the caller is on the CPU already). This establishes the 6323 * necessary total order on variable updates. 6324 * 6325 * Note that because a guest time update may take place 6326 * anytime after the setting of the VCPU's request bit, the 6327 * correct TSC value must be set before the request. However, 6328 * to ensure the update actually makes it to any guest which 6329 * starts running in hardware virtualization between the set 6330 * and the acquisition of the spinlock, we must also ping the 6331 * CPU after setting the request bit. 6332 * 6333 */ 6334 6335 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 6336 return 0; 6337 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 6338 return 0; 6339 6340 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 6341 6342 spin_lock(&kvm_lock); 6343 list_for_each_entry(kvm, &vm_list, vm_list) { 6344 kvm_for_each_vcpu(i, vcpu, kvm) { 6345 if (vcpu->cpu != freq->cpu) 6346 continue; 6347 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6348 if (vcpu->cpu != smp_processor_id()) 6349 send_ipi = 1; 6350 } 6351 } 6352 spin_unlock(&kvm_lock); 6353 6354 if (freq->old < freq->new && send_ipi) { 6355 /* 6356 * We upscale the frequency. Must make the guest 6357 * doesn't see old kvmclock values while running with 6358 * the new frequency, otherwise we risk the guest sees 6359 * time go backwards. 6360 * 6361 * In case we update the frequency for another cpu 6362 * (which might be in guest context) send an interrupt 6363 * to kick the cpu out of guest context. Next time 6364 * guest context is entered kvmclock will be updated, 6365 * so the guest will not see stale values. 6366 */ 6367 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 6368 } 6369 return 0; 6370 } 6371 6372 static struct notifier_block kvmclock_cpufreq_notifier_block = { 6373 .notifier_call = kvmclock_cpufreq_notifier 6374 }; 6375 6376 static int kvmclock_cpu_online(unsigned int cpu) 6377 { 6378 tsc_khz_changed(NULL); 6379 return 0; 6380 } 6381 6382 static void kvm_timer_init(void) 6383 { 6384 max_tsc_khz = tsc_khz; 6385 6386 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 6387 #ifdef CONFIG_CPU_FREQ 6388 struct cpufreq_policy policy; 6389 int cpu; 6390 6391 memset(&policy, 0, sizeof(policy)); 6392 cpu = get_cpu(); 6393 cpufreq_get_policy(&policy, cpu); 6394 if (policy.cpuinfo.max_freq) 6395 max_tsc_khz = policy.cpuinfo.max_freq; 6396 put_cpu(); 6397 #endif 6398 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 6399 CPUFREQ_TRANSITION_NOTIFIER); 6400 } 6401 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 6402 6403 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 6404 kvmclock_cpu_online, kvmclock_cpu_down_prep); 6405 } 6406 6407 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 6408 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); 6409 6410 int kvm_is_in_guest(void) 6411 { 6412 return __this_cpu_read(current_vcpu) != NULL; 6413 } 6414 6415 static int kvm_is_user_mode(void) 6416 { 6417 int user_mode = 3; 6418 6419 if (__this_cpu_read(current_vcpu)) 6420 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 6421 6422 return user_mode != 0; 6423 } 6424 6425 static unsigned long kvm_get_guest_ip(void) 6426 { 6427 unsigned long ip = 0; 6428 6429 if (__this_cpu_read(current_vcpu)) 6430 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 6431 6432 return ip; 6433 } 6434 6435 static struct perf_guest_info_callbacks kvm_guest_cbs = { 6436 .is_in_guest = kvm_is_in_guest, 6437 .is_user_mode = kvm_is_user_mode, 6438 .get_guest_ip = kvm_get_guest_ip, 6439 }; 6440 6441 static void kvm_set_mmio_spte_mask(void) 6442 { 6443 u64 mask; 6444 int maxphyaddr = boot_cpu_data.x86_phys_bits; 6445 6446 /* 6447 * Set the reserved bits and the present bit of an paging-structure 6448 * entry to generate page fault with PFER.RSV = 1. 6449 */ 6450 /* Mask the reserved physical address bits. */ 6451 mask = rsvd_bits(maxphyaddr, 51); 6452 6453 /* Set the present bit. */ 6454 mask |= 1ull; 6455 6456 #ifdef CONFIG_X86_64 6457 /* 6458 * If reserved bit is not supported, clear the present bit to disable 6459 * mmio page fault. 6460 */ 6461 if (maxphyaddr == 52) 6462 mask &= ~1ull; 6463 #endif 6464 6465 kvm_mmu_set_mmio_spte_mask(mask, mask); 6466 } 6467 6468 #ifdef CONFIG_X86_64 6469 static void pvclock_gtod_update_fn(struct work_struct *work) 6470 { 6471 struct kvm *kvm; 6472 6473 struct kvm_vcpu *vcpu; 6474 int i; 6475 6476 spin_lock(&kvm_lock); 6477 list_for_each_entry(kvm, &vm_list, vm_list) 6478 kvm_for_each_vcpu(i, vcpu, kvm) 6479 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 6480 atomic_set(&kvm_guest_has_master_clock, 0); 6481 spin_unlock(&kvm_lock); 6482 } 6483 6484 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 6485 6486 /* 6487 * Notification about pvclock gtod data update. 6488 */ 6489 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 6490 void *priv) 6491 { 6492 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 6493 struct timekeeper *tk = priv; 6494 6495 update_pvclock_gtod(tk); 6496 6497 /* disable master clock if host does not trust, or does not 6498 * use, TSC based clocksource. 6499 */ 6500 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 6501 atomic_read(&kvm_guest_has_master_clock) != 0) 6502 queue_work(system_long_wq, &pvclock_gtod_work); 6503 6504 return 0; 6505 } 6506 6507 static struct notifier_block pvclock_gtod_notifier = { 6508 .notifier_call = pvclock_gtod_notify, 6509 }; 6510 #endif 6511 6512 int kvm_arch_init(void *opaque) 6513 { 6514 int r; 6515 struct kvm_x86_ops *ops = opaque; 6516 6517 if (kvm_x86_ops) { 6518 printk(KERN_ERR "kvm: already loaded the other module\n"); 6519 r = -EEXIST; 6520 goto out; 6521 } 6522 6523 if (!ops->cpu_has_kvm_support()) { 6524 printk(KERN_ERR "kvm: no hardware support\n"); 6525 r = -EOPNOTSUPP; 6526 goto out; 6527 } 6528 if (ops->disabled_by_bios()) { 6529 printk(KERN_ERR "kvm: disabled by bios\n"); 6530 r = -EOPNOTSUPP; 6531 goto out; 6532 } 6533 6534 r = -ENOMEM; 6535 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 6536 if (!shared_msrs) { 6537 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 6538 goto out; 6539 } 6540 6541 r = kvm_mmu_module_init(); 6542 if (r) 6543 goto out_free_percpu; 6544 6545 kvm_set_mmio_spte_mask(); 6546 6547 kvm_x86_ops = ops; 6548 6549 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 6550 PT_DIRTY_MASK, PT64_NX_MASK, 0, 6551 PT_PRESENT_MASK, 0, sme_me_mask); 6552 kvm_timer_init(); 6553 6554 perf_register_guest_info_callbacks(&kvm_guest_cbs); 6555 6556 if (boot_cpu_has(X86_FEATURE_XSAVE)) 6557 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 6558 6559 kvm_lapic_init(); 6560 #ifdef CONFIG_X86_64 6561 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 6562 6563 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 6564 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 6565 #endif 6566 6567 return 0; 6568 6569 out_free_percpu: 6570 free_percpu(shared_msrs); 6571 out: 6572 return r; 6573 } 6574 6575 void kvm_arch_exit(void) 6576 { 6577 #ifdef CONFIG_X86_64 6578 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 6579 clear_hv_tscchange_cb(); 6580 #endif 6581 kvm_lapic_exit(); 6582 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 6583 6584 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 6585 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 6586 CPUFREQ_TRANSITION_NOTIFIER); 6587 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 6588 #ifdef CONFIG_X86_64 6589 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 6590 #endif 6591 kvm_x86_ops = NULL; 6592 kvm_mmu_module_exit(); 6593 free_percpu(shared_msrs); 6594 } 6595 6596 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 6597 { 6598 ++vcpu->stat.halt_exits; 6599 if (lapic_in_kernel(vcpu)) { 6600 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 6601 return 1; 6602 } else { 6603 vcpu->run->exit_reason = KVM_EXIT_HLT; 6604 return 0; 6605 } 6606 } 6607 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 6608 6609 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 6610 { 6611 int ret = kvm_skip_emulated_instruction(vcpu); 6612 /* 6613 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 6614 * KVM_EXIT_DEBUG here. 6615 */ 6616 return kvm_vcpu_halt(vcpu) && ret; 6617 } 6618 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 6619 6620 #ifdef CONFIG_X86_64 6621 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 6622 unsigned long clock_type) 6623 { 6624 struct kvm_clock_pairing clock_pairing; 6625 struct timespec ts; 6626 u64 cycle; 6627 int ret; 6628 6629 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 6630 return -KVM_EOPNOTSUPP; 6631 6632 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) 6633 return -KVM_EOPNOTSUPP; 6634 6635 clock_pairing.sec = ts.tv_sec; 6636 clock_pairing.nsec = ts.tv_nsec; 6637 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 6638 clock_pairing.flags = 0; 6639 6640 ret = 0; 6641 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 6642 sizeof(struct kvm_clock_pairing))) 6643 ret = -KVM_EFAULT; 6644 6645 return ret; 6646 } 6647 #endif 6648 6649 /* 6650 * kvm_pv_kick_cpu_op: Kick a vcpu. 6651 * 6652 * @apicid - apicid of vcpu to be kicked. 6653 */ 6654 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 6655 { 6656 struct kvm_lapic_irq lapic_irq; 6657 6658 lapic_irq.shorthand = 0; 6659 lapic_irq.dest_mode = 0; 6660 lapic_irq.level = 0; 6661 lapic_irq.dest_id = apicid; 6662 lapic_irq.msi_redir_hint = false; 6663 6664 lapic_irq.delivery_mode = APIC_DM_REMRD; 6665 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 6666 } 6667 6668 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) 6669 { 6670 vcpu->arch.apicv_active = false; 6671 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); 6672 } 6673 6674 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 6675 { 6676 unsigned long nr, a0, a1, a2, a3, ret; 6677 int op_64_bit; 6678 6679 if (kvm_hv_hypercall_enabled(vcpu->kvm)) { 6680 if (!kvm_hv_hypercall(vcpu)) 6681 return 0; 6682 goto out; 6683 } 6684 6685 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 6686 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 6687 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 6688 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 6689 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 6690 6691 trace_kvm_hypercall(nr, a0, a1, a2, a3); 6692 6693 op_64_bit = is_64_bit_mode(vcpu); 6694 if (!op_64_bit) { 6695 nr &= 0xFFFFFFFF; 6696 a0 &= 0xFFFFFFFF; 6697 a1 &= 0xFFFFFFFF; 6698 a2 &= 0xFFFFFFFF; 6699 a3 &= 0xFFFFFFFF; 6700 } 6701 6702 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 6703 ret = -KVM_EPERM; 6704 goto out_error; 6705 } 6706 6707 switch (nr) { 6708 case KVM_HC_VAPIC_POLL_IRQ: 6709 ret = 0; 6710 break; 6711 case KVM_HC_KICK_CPU: 6712 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 6713 ret = 0; 6714 break; 6715 #ifdef CONFIG_X86_64 6716 case KVM_HC_CLOCK_PAIRING: 6717 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 6718 break; 6719 #endif 6720 default: 6721 ret = -KVM_ENOSYS; 6722 break; 6723 } 6724 out_error: 6725 if (!op_64_bit) 6726 ret = (u32)ret; 6727 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 6728 6729 out: 6730 ++vcpu->stat.hypercalls; 6731 return kvm_skip_emulated_instruction(vcpu); 6732 } 6733 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 6734 6735 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 6736 { 6737 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6738 char instruction[3]; 6739 unsigned long rip = kvm_rip_read(vcpu); 6740 6741 kvm_x86_ops->patch_hypercall(vcpu, instruction); 6742 6743 return emulator_write_emulated(ctxt, rip, instruction, 3, 6744 &ctxt->exception); 6745 } 6746 6747 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 6748 { 6749 return vcpu->run->request_interrupt_window && 6750 likely(!pic_in_kernel(vcpu->kvm)); 6751 } 6752 6753 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 6754 { 6755 struct kvm_run *kvm_run = vcpu->run; 6756 6757 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 6758 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 6759 kvm_run->cr8 = kvm_get_cr8(vcpu); 6760 kvm_run->apic_base = kvm_get_apic_base(vcpu); 6761 kvm_run->ready_for_interrupt_injection = 6762 pic_in_kernel(vcpu->kvm) || 6763 kvm_vcpu_ready_for_interrupt_injection(vcpu); 6764 } 6765 6766 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 6767 { 6768 int max_irr, tpr; 6769 6770 if (!kvm_x86_ops->update_cr8_intercept) 6771 return; 6772 6773 if (!lapic_in_kernel(vcpu)) 6774 return; 6775 6776 if (vcpu->arch.apicv_active) 6777 return; 6778 6779 if (!vcpu->arch.apic->vapic_addr) 6780 max_irr = kvm_lapic_find_highest_irr(vcpu); 6781 else 6782 max_irr = -1; 6783 6784 if (max_irr != -1) 6785 max_irr >>= 4; 6786 6787 tpr = kvm_lapic_get_cr8(vcpu); 6788 6789 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 6790 } 6791 6792 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 6793 { 6794 int r; 6795 6796 /* try to reinject previous events if any */ 6797 6798 if (vcpu->arch.exception.injected) 6799 kvm_x86_ops->queue_exception(vcpu); 6800 /* 6801 * Do not inject an NMI or interrupt if there is a pending 6802 * exception. Exceptions and interrupts are recognized at 6803 * instruction boundaries, i.e. the start of an instruction. 6804 * Trap-like exceptions, e.g. #DB, have higher priority than 6805 * NMIs and interrupts, i.e. traps are recognized before an 6806 * NMI/interrupt that's pending on the same instruction. 6807 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 6808 * priority, but are only generated (pended) during instruction 6809 * execution, i.e. a pending fault-like exception means the 6810 * fault occurred on the *previous* instruction and must be 6811 * serviced prior to recognizing any new events in order to 6812 * fully complete the previous instruction. 6813 */ 6814 else if (!vcpu->arch.exception.pending) { 6815 if (vcpu->arch.nmi_injected) 6816 kvm_x86_ops->set_nmi(vcpu); 6817 else if (vcpu->arch.interrupt.injected) 6818 kvm_x86_ops->set_irq(vcpu); 6819 } 6820 6821 /* 6822 * Call check_nested_events() even if we reinjected a previous event 6823 * in order for caller to determine if it should require immediate-exit 6824 * from L2 to L1 due to pending L1 events which require exit 6825 * from L2 to L1. 6826 */ 6827 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6828 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6829 if (r != 0) 6830 return r; 6831 } 6832 6833 /* try to inject new event if pending */ 6834 if (vcpu->arch.exception.pending) { 6835 trace_kvm_inj_exception(vcpu->arch.exception.nr, 6836 vcpu->arch.exception.has_error_code, 6837 vcpu->arch.exception.error_code); 6838 6839 WARN_ON_ONCE(vcpu->arch.exception.injected); 6840 vcpu->arch.exception.pending = false; 6841 vcpu->arch.exception.injected = true; 6842 6843 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 6844 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 6845 X86_EFLAGS_RF); 6846 6847 if (vcpu->arch.exception.nr == DB_VECTOR && 6848 (vcpu->arch.dr7 & DR7_GD)) { 6849 vcpu->arch.dr7 &= ~DR7_GD; 6850 kvm_update_dr7(vcpu); 6851 } 6852 6853 kvm_x86_ops->queue_exception(vcpu); 6854 } 6855 6856 /* Don't consider new event if we re-injected an event */ 6857 if (kvm_event_needs_reinjection(vcpu)) 6858 return 0; 6859 6860 if (vcpu->arch.smi_pending && !is_smm(vcpu) && 6861 kvm_x86_ops->smi_allowed(vcpu)) { 6862 vcpu->arch.smi_pending = false; 6863 ++vcpu->arch.smi_count; 6864 enter_smm(vcpu); 6865 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { 6866 --vcpu->arch.nmi_pending; 6867 vcpu->arch.nmi_injected = true; 6868 kvm_x86_ops->set_nmi(vcpu); 6869 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 6870 /* 6871 * Because interrupts can be injected asynchronously, we are 6872 * calling check_nested_events again here to avoid a race condition. 6873 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 6874 * proposal and current concerns. Perhaps we should be setting 6875 * KVM_REQ_EVENT only on certain events and not unconditionally? 6876 */ 6877 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6878 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6879 if (r != 0) 6880 return r; 6881 } 6882 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 6883 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 6884 false); 6885 kvm_x86_ops->set_irq(vcpu); 6886 } 6887 } 6888 6889 return 0; 6890 } 6891 6892 static void process_nmi(struct kvm_vcpu *vcpu) 6893 { 6894 unsigned limit = 2; 6895 6896 /* 6897 * x86 is limited to one NMI running, and one NMI pending after it. 6898 * If an NMI is already in progress, limit further NMIs to just one. 6899 * Otherwise, allow two (and we'll inject the first one immediately). 6900 */ 6901 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 6902 limit = 1; 6903 6904 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 6905 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 6906 kvm_make_request(KVM_REQ_EVENT, vcpu); 6907 } 6908 6909 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 6910 { 6911 u32 flags = 0; 6912 flags |= seg->g << 23; 6913 flags |= seg->db << 22; 6914 flags |= seg->l << 21; 6915 flags |= seg->avl << 20; 6916 flags |= seg->present << 15; 6917 flags |= seg->dpl << 13; 6918 flags |= seg->s << 12; 6919 flags |= seg->type << 8; 6920 return flags; 6921 } 6922 6923 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 6924 { 6925 struct kvm_segment seg; 6926 int offset; 6927 6928 kvm_get_segment(vcpu, &seg, n); 6929 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 6930 6931 if (n < 3) 6932 offset = 0x7f84 + n * 12; 6933 else 6934 offset = 0x7f2c + (n - 3) * 12; 6935 6936 put_smstate(u32, buf, offset + 8, seg.base); 6937 put_smstate(u32, buf, offset + 4, seg.limit); 6938 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 6939 } 6940 6941 #ifdef CONFIG_X86_64 6942 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 6943 { 6944 struct kvm_segment seg; 6945 int offset; 6946 u16 flags; 6947 6948 kvm_get_segment(vcpu, &seg, n); 6949 offset = 0x7e00 + n * 16; 6950 6951 flags = enter_smm_get_segment_flags(&seg) >> 8; 6952 put_smstate(u16, buf, offset, seg.selector); 6953 put_smstate(u16, buf, offset + 2, flags); 6954 put_smstate(u32, buf, offset + 4, seg.limit); 6955 put_smstate(u64, buf, offset + 8, seg.base); 6956 } 6957 #endif 6958 6959 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 6960 { 6961 struct desc_ptr dt; 6962 struct kvm_segment seg; 6963 unsigned long val; 6964 int i; 6965 6966 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 6967 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 6968 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 6969 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 6970 6971 for (i = 0; i < 8; i++) 6972 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 6973 6974 kvm_get_dr(vcpu, 6, &val); 6975 put_smstate(u32, buf, 0x7fcc, (u32)val); 6976 kvm_get_dr(vcpu, 7, &val); 6977 put_smstate(u32, buf, 0x7fc8, (u32)val); 6978 6979 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6980 put_smstate(u32, buf, 0x7fc4, seg.selector); 6981 put_smstate(u32, buf, 0x7f64, seg.base); 6982 put_smstate(u32, buf, 0x7f60, seg.limit); 6983 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 6984 6985 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6986 put_smstate(u32, buf, 0x7fc0, seg.selector); 6987 put_smstate(u32, buf, 0x7f80, seg.base); 6988 put_smstate(u32, buf, 0x7f7c, seg.limit); 6989 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 6990 6991 kvm_x86_ops->get_gdt(vcpu, &dt); 6992 put_smstate(u32, buf, 0x7f74, dt.address); 6993 put_smstate(u32, buf, 0x7f70, dt.size); 6994 6995 kvm_x86_ops->get_idt(vcpu, &dt); 6996 put_smstate(u32, buf, 0x7f58, dt.address); 6997 put_smstate(u32, buf, 0x7f54, dt.size); 6998 6999 for (i = 0; i < 6; i++) 7000 enter_smm_save_seg_32(vcpu, buf, i); 7001 7002 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 7003 7004 /* revision id */ 7005 put_smstate(u32, buf, 0x7efc, 0x00020000); 7006 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 7007 } 7008 7009 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 7010 { 7011 #ifdef CONFIG_X86_64 7012 struct desc_ptr dt; 7013 struct kvm_segment seg; 7014 unsigned long val; 7015 int i; 7016 7017 for (i = 0; i < 16; i++) 7018 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 7019 7020 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 7021 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 7022 7023 kvm_get_dr(vcpu, 6, &val); 7024 put_smstate(u64, buf, 0x7f68, val); 7025 kvm_get_dr(vcpu, 7, &val); 7026 put_smstate(u64, buf, 0x7f60, val); 7027 7028 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 7029 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 7030 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 7031 7032 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 7033 7034 /* revision id */ 7035 put_smstate(u32, buf, 0x7efc, 0x00020064); 7036 7037 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 7038 7039 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 7040 put_smstate(u16, buf, 0x7e90, seg.selector); 7041 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 7042 put_smstate(u32, buf, 0x7e94, seg.limit); 7043 put_smstate(u64, buf, 0x7e98, seg.base); 7044 7045 kvm_x86_ops->get_idt(vcpu, &dt); 7046 put_smstate(u32, buf, 0x7e84, dt.size); 7047 put_smstate(u64, buf, 0x7e88, dt.address); 7048 7049 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 7050 put_smstate(u16, buf, 0x7e70, seg.selector); 7051 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 7052 put_smstate(u32, buf, 0x7e74, seg.limit); 7053 put_smstate(u64, buf, 0x7e78, seg.base); 7054 7055 kvm_x86_ops->get_gdt(vcpu, &dt); 7056 put_smstate(u32, buf, 0x7e64, dt.size); 7057 put_smstate(u64, buf, 0x7e68, dt.address); 7058 7059 for (i = 0; i < 6; i++) 7060 enter_smm_save_seg_64(vcpu, buf, i); 7061 #else 7062 WARN_ON_ONCE(1); 7063 #endif 7064 } 7065 7066 static void enter_smm(struct kvm_vcpu *vcpu) 7067 { 7068 struct kvm_segment cs, ds; 7069 struct desc_ptr dt; 7070 char buf[512]; 7071 u32 cr0; 7072 7073 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 7074 memset(buf, 0, 512); 7075 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 7076 enter_smm_save_state_64(vcpu, buf); 7077 else 7078 enter_smm_save_state_32(vcpu, buf); 7079 7080 /* 7081 * Give pre_enter_smm() a chance to make ISA-specific changes to the 7082 * vCPU state (e.g. leave guest mode) after we've saved the state into 7083 * the SMM state-save area. 7084 */ 7085 kvm_x86_ops->pre_enter_smm(vcpu, buf); 7086 7087 vcpu->arch.hflags |= HF_SMM_MASK; 7088 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 7089 7090 if (kvm_x86_ops->get_nmi_mask(vcpu)) 7091 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 7092 else 7093 kvm_x86_ops->set_nmi_mask(vcpu, true); 7094 7095 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 7096 kvm_rip_write(vcpu, 0x8000); 7097 7098 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 7099 kvm_x86_ops->set_cr0(vcpu, cr0); 7100 vcpu->arch.cr0 = cr0; 7101 7102 kvm_x86_ops->set_cr4(vcpu, 0); 7103 7104 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 7105 dt.address = dt.size = 0; 7106 kvm_x86_ops->set_idt(vcpu, &dt); 7107 7108 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 7109 7110 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 7111 cs.base = vcpu->arch.smbase; 7112 7113 ds.selector = 0; 7114 ds.base = 0; 7115 7116 cs.limit = ds.limit = 0xffffffff; 7117 cs.type = ds.type = 0x3; 7118 cs.dpl = ds.dpl = 0; 7119 cs.db = ds.db = 0; 7120 cs.s = ds.s = 1; 7121 cs.l = ds.l = 0; 7122 cs.g = ds.g = 1; 7123 cs.avl = ds.avl = 0; 7124 cs.present = ds.present = 1; 7125 cs.unusable = ds.unusable = 0; 7126 cs.padding = ds.padding = 0; 7127 7128 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7129 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 7130 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 7131 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 7132 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 7133 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 7134 7135 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 7136 kvm_x86_ops->set_efer(vcpu, 0); 7137 7138 kvm_update_cpuid(vcpu); 7139 kvm_mmu_reset_context(vcpu); 7140 } 7141 7142 static void process_smi(struct kvm_vcpu *vcpu) 7143 { 7144 vcpu->arch.smi_pending = true; 7145 kvm_make_request(KVM_REQ_EVENT, vcpu); 7146 } 7147 7148 void kvm_make_scan_ioapic_request(struct kvm *kvm) 7149 { 7150 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 7151 } 7152 7153 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 7154 { 7155 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 7156 return; 7157 7158 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 7159 7160 if (irqchip_split(vcpu->kvm)) 7161 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 7162 else { 7163 if (vcpu->arch.apicv_active) 7164 kvm_x86_ops->sync_pir_to_irr(vcpu); 7165 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 7166 } 7167 7168 if (is_guest_mode(vcpu)) 7169 vcpu->arch.load_eoi_exitmap_pending = true; 7170 else 7171 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 7172 } 7173 7174 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 7175 { 7176 u64 eoi_exit_bitmap[4]; 7177 7178 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 7179 return; 7180 7181 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, 7182 vcpu_to_synic(vcpu)->vec_bitmap, 256); 7183 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 7184 } 7185 7186 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 7187 unsigned long start, unsigned long end) 7188 { 7189 unsigned long apic_address; 7190 7191 /* 7192 * The physical address of apic access page is stored in the VMCS. 7193 * Update it when it becomes invalid. 7194 */ 7195 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 7196 if (start <= apic_address && apic_address < end) 7197 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 7198 } 7199 7200 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 7201 { 7202 struct page *page = NULL; 7203 7204 if (!lapic_in_kernel(vcpu)) 7205 return; 7206 7207 if (!kvm_x86_ops->set_apic_access_page_addr) 7208 return; 7209 7210 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 7211 if (is_error_page(page)) 7212 return; 7213 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 7214 7215 /* 7216 * Do not pin apic access page in memory, the MMU notifier 7217 * will call us again if it is migrated or swapped out. 7218 */ 7219 put_page(page); 7220 } 7221 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 7222 7223 /* 7224 * Returns 1 to let vcpu_run() continue the guest execution loop without 7225 * exiting to the userspace. Otherwise, the value will be returned to the 7226 * userspace. 7227 */ 7228 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 7229 { 7230 int r; 7231 bool req_int_win = 7232 dm_request_for_irq_injection(vcpu) && 7233 kvm_cpu_accept_dm_intr(vcpu); 7234 7235 bool req_immediate_exit = false; 7236 7237 if (kvm_request_pending(vcpu)) { 7238 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 7239 kvm_mmu_unload(vcpu); 7240 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 7241 __kvm_migrate_timers(vcpu); 7242 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 7243 kvm_gen_update_masterclock(vcpu->kvm); 7244 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 7245 kvm_gen_kvmclock_update(vcpu); 7246 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 7247 r = kvm_guest_time_update(vcpu); 7248 if (unlikely(r)) 7249 goto out; 7250 } 7251 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 7252 kvm_mmu_sync_roots(vcpu); 7253 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 7254 kvm_vcpu_flush_tlb(vcpu, true); 7255 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 7256 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 7257 r = 0; 7258 goto out; 7259 } 7260 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 7261 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 7262 vcpu->mmio_needed = 0; 7263 r = 0; 7264 goto out; 7265 } 7266 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 7267 /* Page is swapped out. Do synthetic halt */ 7268 vcpu->arch.apf.halted = true; 7269 r = 1; 7270 goto out; 7271 } 7272 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 7273 record_steal_time(vcpu); 7274 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 7275 process_smi(vcpu); 7276 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 7277 process_nmi(vcpu); 7278 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 7279 kvm_pmu_handle_event(vcpu); 7280 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 7281 kvm_pmu_deliver_pmi(vcpu); 7282 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 7283 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 7284 if (test_bit(vcpu->arch.pending_ioapic_eoi, 7285 vcpu->arch.ioapic_handled_vectors)) { 7286 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 7287 vcpu->run->eoi.vector = 7288 vcpu->arch.pending_ioapic_eoi; 7289 r = 0; 7290 goto out; 7291 } 7292 } 7293 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 7294 vcpu_scan_ioapic(vcpu); 7295 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 7296 vcpu_load_eoi_exitmap(vcpu); 7297 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 7298 kvm_vcpu_reload_apic_access_page(vcpu); 7299 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 7300 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 7301 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 7302 r = 0; 7303 goto out; 7304 } 7305 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 7306 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 7307 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 7308 r = 0; 7309 goto out; 7310 } 7311 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 7312 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 7313 vcpu->run->hyperv = vcpu->arch.hyperv.exit; 7314 r = 0; 7315 goto out; 7316 } 7317 7318 /* 7319 * KVM_REQ_HV_STIMER has to be processed after 7320 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 7321 * depend on the guest clock being up-to-date 7322 */ 7323 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 7324 kvm_hv_process_stimers(vcpu); 7325 } 7326 7327 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 7328 ++vcpu->stat.req_event; 7329 kvm_apic_accept_events(vcpu); 7330 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 7331 r = 1; 7332 goto out; 7333 } 7334 7335 if (inject_pending_event(vcpu, req_int_win) != 0) 7336 req_immediate_exit = true; 7337 else { 7338 /* Enable SMI/NMI/IRQ window open exits if needed. 7339 * 7340 * SMIs have three cases: 7341 * 1) They can be nested, and then there is nothing to 7342 * do here because RSM will cause a vmexit anyway. 7343 * 2) There is an ISA-specific reason why SMI cannot be 7344 * injected, and the moment when this changes can be 7345 * intercepted. 7346 * 3) Or the SMI can be pending because 7347 * inject_pending_event has completed the injection 7348 * of an IRQ or NMI from the previous vmexit, and 7349 * then we request an immediate exit to inject the 7350 * SMI. 7351 */ 7352 if (vcpu->arch.smi_pending && !is_smm(vcpu)) 7353 if (!kvm_x86_ops->enable_smi_window(vcpu)) 7354 req_immediate_exit = true; 7355 if (vcpu->arch.nmi_pending) 7356 kvm_x86_ops->enable_nmi_window(vcpu); 7357 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 7358 kvm_x86_ops->enable_irq_window(vcpu); 7359 WARN_ON(vcpu->arch.exception.pending); 7360 } 7361 7362 if (kvm_lapic_enabled(vcpu)) { 7363 update_cr8_intercept(vcpu); 7364 kvm_lapic_sync_to_vapic(vcpu); 7365 } 7366 } 7367 7368 r = kvm_mmu_reload(vcpu); 7369 if (unlikely(r)) { 7370 goto cancel_injection; 7371 } 7372 7373 preempt_disable(); 7374 7375 kvm_x86_ops->prepare_guest_switch(vcpu); 7376 7377 /* 7378 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 7379 * IPI are then delayed after guest entry, which ensures that they 7380 * result in virtual interrupt delivery. 7381 */ 7382 local_irq_disable(); 7383 vcpu->mode = IN_GUEST_MODE; 7384 7385 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 7386 7387 /* 7388 * 1) We should set ->mode before checking ->requests. Please see 7389 * the comment in kvm_vcpu_exiting_guest_mode(). 7390 * 7391 * 2) For APICv, we should set ->mode before checking PIR.ON. This 7392 * pairs with the memory barrier implicit in pi_test_and_set_on 7393 * (see vmx_deliver_posted_interrupt). 7394 * 7395 * 3) This also orders the write to mode from any reads to the page 7396 * tables done while the VCPU is running. Please see the comment 7397 * in kvm_flush_remote_tlbs. 7398 */ 7399 smp_mb__after_srcu_read_unlock(); 7400 7401 /* 7402 * This handles the case where a posted interrupt was 7403 * notified with kvm_vcpu_kick. 7404 */ 7405 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) 7406 kvm_x86_ops->sync_pir_to_irr(vcpu); 7407 7408 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) 7409 || need_resched() || signal_pending(current)) { 7410 vcpu->mode = OUTSIDE_GUEST_MODE; 7411 smp_wmb(); 7412 local_irq_enable(); 7413 preempt_enable(); 7414 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7415 r = 1; 7416 goto cancel_injection; 7417 } 7418 7419 kvm_load_guest_xcr0(vcpu); 7420 7421 if (req_immediate_exit) { 7422 kvm_make_request(KVM_REQ_EVENT, vcpu); 7423 smp_send_reschedule(vcpu->cpu); 7424 } 7425 7426 trace_kvm_entry(vcpu->vcpu_id); 7427 if (lapic_timer_advance_ns) 7428 wait_lapic_expire(vcpu); 7429 guest_enter_irqoff(); 7430 7431 if (unlikely(vcpu->arch.switch_db_regs)) { 7432 set_debugreg(0, 7); 7433 set_debugreg(vcpu->arch.eff_db[0], 0); 7434 set_debugreg(vcpu->arch.eff_db[1], 1); 7435 set_debugreg(vcpu->arch.eff_db[2], 2); 7436 set_debugreg(vcpu->arch.eff_db[3], 3); 7437 set_debugreg(vcpu->arch.dr6, 6); 7438 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 7439 } 7440 7441 kvm_x86_ops->run(vcpu); 7442 7443 /* 7444 * Do this here before restoring debug registers on the host. And 7445 * since we do this before handling the vmexit, a DR access vmexit 7446 * can (a) read the correct value of the debug registers, (b) set 7447 * KVM_DEBUGREG_WONT_EXIT again. 7448 */ 7449 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 7450 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 7451 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 7452 kvm_update_dr0123(vcpu); 7453 kvm_update_dr6(vcpu); 7454 kvm_update_dr7(vcpu); 7455 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 7456 } 7457 7458 /* 7459 * If the guest has used debug registers, at least dr7 7460 * will be disabled while returning to the host. 7461 * If we don't have active breakpoints in the host, we don't 7462 * care about the messed up debug address registers. But if 7463 * we have some of them active, restore the old state. 7464 */ 7465 if (hw_breakpoint_active()) 7466 hw_breakpoint_restore(); 7467 7468 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 7469 7470 vcpu->mode = OUTSIDE_GUEST_MODE; 7471 smp_wmb(); 7472 7473 kvm_put_guest_xcr0(vcpu); 7474 7475 kvm_before_interrupt(vcpu); 7476 kvm_x86_ops->handle_external_intr(vcpu); 7477 kvm_after_interrupt(vcpu); 7478 7479 ++vcpu->stat.exits; 7480 7481 guest_exit_irqoff(); 7482 7483 local_irq_enable(); 7484 preempt_enable(); 7485 7486 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7487 7488 /* 7489 * Profile KVM exit RIPs: 7490 */ 7491 if (unlikely(prof_on == KVM_PROFILING)) { 7492 unsigned long rip = kvm_rip_read(vcpu); 7493 profile_hit(KVM_PROFILING, (void *)rip); 7494 } 7495 7496 if (unlikely(vcpu->arch.tsc_always_catchup)) 7497 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7498 7499 if (vcpu->arch.apic_attention) 7500 kvm_lapic_sync_from_vapic(vcpu); 7501 7502 vcpu->arch.gpa_available = false; 7503 r = kvm_x86_ops->handle_exit(vcpu); 7504 return r; 7505 7506 cancel_injection: 7507 kvm_x86_ops->cancel_injection(vcpu); 7508 if (unlikely(vcpu->arch.apic_attention)) 7509 kvm_lapic_sync_from_vapic(vcpu); 7510 out: 7511 return r; 7512 } 7513 7514 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 7515 { 7516 if (!kvm_arch_vcpu_runnable(vcpu) && 7517 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { 7518 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7519 kvm_vcpu_block(vcpu); 7520 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7521 7522 if (kvm_x86_ops->post_block) 7523 kvm_x86_ops->post_block(vcpu); 7524 7525 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 7526 return 1; 7527 } 7528 7529 kvm_apic_accept_events(vcpu); 7530 switch(vcpu->arch.mp_state) { 7531 case KVM_MP_STATE_HALTED: 7532 vcpu->arch.pv.pv_unhalted = false; 7533 vcpu->arch.mp_state = 7534 KVM_MP_STATE_RUNNABLE; 7535 case KVM_MP_STATE_RUNNABLE: 7536 vcpu->arch.apf.halted = false; 7537 break; 7538 case KVM_MP_STATE_INIT_RECEIVED: 7539 break; 7540 default: 7541 return -EINTR; 7542 break; 7543 } 7544 return 1; 7545 } 7546 7547 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 7548 { 7549 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 7550 kvm_x86_ops->check_nested_events(vcpu, false); 7551 7552 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 7553 !vcpu->arch.apf.halted); 7554 } 7555 7556 static int vcpu_run(struct kvm_vcpu *vcpu) 7557 { 7558 int r; 7559 struct kvm *kvm = vcpu->kvm; 7560 7561 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7562 7563 for (;;) { 7564 if (kvm_vcpu_running(vcpu)) { 7565 r = vcpu_enter_guest(vcpu); 7566 } else { 7567 r = vcpu_block(kvm, vcpu); 7568 } 7569 7570 if (r <= 0) 7571 break; 7572 7573 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); 7574 if (kvm_cpu_has_pending_timer(vcpu)) 7575 kvm_inject_pending_timer_irqs(vcpu); 7576 7577 if (dm_request_for_irq_injection(vcpu) && 7578 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 7579 r = 0; 7580 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 7581 ++vcpu->stat.request_irq_exits; 7582 break; 7583 } 7584 7585 kvm_check_async_pf_completion(vcpu); 7586 7587 if (signal_pending(current)) { 7588 r = -EINTR; 7589 vcpu->run->exit_reason = KVM_EXIT_INTR; 7590 ++vcpu->stat.signal_exits; 7591 break; 7592 } 7593 if (need_resched()) { 7594 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7595 cond_resched(); 7596 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7597 } 7598 } 7599 7600 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7601 7602 return r; 7603 } 7604 7605 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 7606 { 7607 int r; 7608 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7609 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 7610 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 7611 if (r != EMULATE_DONE) 7612 return 0; 7613 return 1; 7614 } 7615 7616 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 7617 { 7618 BUG_ON(!vcpu->arch.pio.count); 7619 7620 return complete_emulated_io(vcpu); 7621 } 7622 7623 /* 7624 * Implements the following, as a state machine: 7625 * 7626 * read: 7627 * for each fragment 7628 * for each mmio piece in the fragment 7629 * write gpa, len 7630 * exit 7631 * copy data 7632 * execute insn 7633 * 7634 * write: 7635 * for each fragment 7636 * for each mmio piece in the fragment 7637 * write gpa, len 7638 * copy data 7639 * exit 7640 */ 7641 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 7642 { 7643 struct kvm_run *run = vcpu->run; 7644 struct kvm_mmio_fragment *frag; 7645 unsigned len; 7646 7647 BUG_ON(!vcpu->mmio_needed); 7648 7649 /* Complete previous fragment */ 7650 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 7651 len = min(8u, frag->len); 7652 if (!vcpu->mmio_is_write) 7653 memcpy(frag->data, run->mmio.data, len); 7654 7655 if (frag->len <= 8) { 7656 /* Switch to the next fragment. */ 7657 frag++; 7658 vcpu->mmio_cur_fragment++; 7659 } else { 7660 /* Go forward to the next mmio piece. */ 7661 frag->data += len; 7662 frag->gpa += len; 7663 frag->len -= len; 7664 } 7665 7666 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 7667 vcpu->mmio_needed = 0; 7668 7669 /* FIXME: return into emulator if single-stepping. */ 7670 if (vcpu->mmio_is_write) 7671 return 1; 7672 vcpu->mmio_read_completed = 1; 7673 return complete_emulated_io(vcpu); 7674 } 7675 7676 run->exit_reason = KVM_EXIT_MMIO; 7677 run->mmio.phys_addr = frag->gpa; 7678 if (vcpu->mmio_is_write) 7679 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 7680 run->mmio.len = min(8u, frag->len); 7681 run->mmio.is_write = vcpu->mmio_is_write; 7682 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 7683 return 0; 7684 } 7685 7686 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 7687 { 7688 int r; 7689 7690 vcpu_load(vcpu); 7691 kvm_sigset_activate(vcpu); 7692 kvm_load_guest_fpu(vcpu); 7693 7694 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 7695 if (kvm_run->immediate_exit) { 7696 r = -EINTR; 7697 goto out; 7698 } 7699 kvm_vcpu_block(vcpu); 7700 kvm_apic_accept_events(vcpu); 7701 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 7702 r = -EAGAIN; 7703 if (signal_pending(current)) { 7704 r = -EINTR; 7705 vcpu->run->exit_reason = KVM_EXIT_INTR; 7706 ++vcpu->stat.signal_exits; 7707 } 7708 goto out; 7709 } 7710 7711 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { 7712 r = -EINVAL; 7713 goto out; 7714 } 7715 7716 if (vcpu->run->kvm_dirty_regs) { 7717 r = sync_regs(vcpu); 7718 if (r != 0) 7719 goto out; 7720 } 7721 7722 /* re-sync apic's tpr */ 7723 if (!lapic_in_kernel(vcpu)) { 7724 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 7725 r = -EINVAL; 7726 goto out; 7727 } 7728 } 7729 7730 if (unlikely(vcpu->arch.complete_userspace_io)) { 7731 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 7732 vcpu->arch.complete_userspace_io = NULL; 7733 r = cui(vcpu); 7734 if (r <= 0) 7735 goto out; 7736 } else 7737 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 7738 7739 if (kvm_run->immediate_exit) 7740 r = -EINTR; 7741 else 7742 r = vcpu_run(vcpu); 7743 7744 out: 7745 kvm_put_guest_fpu(vcpu); 7746 if (vcpu->run->kvm_valid_regs) 7747 store_regs(vcpu); 7748 post_kvm_run_save(vcpu); 7749 kvm_sigset_deactivate(vcpu); 7750 7751 vcpu_put(vcpu); 7752 return r; 7753 } 7754 7755 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7756 { 7757 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 7758 /* 7759 * We are here if userspace calls get_regs() in the middle of 7760 * instruction emulation. Registers state needs to be copied 7761 * back from emulation context to vcpu. Userspace shouldn't do 7762 * that usually, but some bad designed PV devices (vmware 7763 * backdoor interface) need this to work 7764 */ 7765 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 7766 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7767 } 7768 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 7769 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 7770 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 7771 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 7772 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 7773 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 7774 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 7775 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 7776 #ifdef CONFIG_X86_64 7777 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 7778 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 7779 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 7780 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 7781 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 7782 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 7783 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 7784 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 7785 #endif 7786 7787 regs->rip = kvm_rip_read(vcpu); 7788 regs->rflags = kvm_get_rflags(vcpu); 7789 } 7790 7791 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7792 { 7793 vcpu_load(vcpu); 7794 __get_regs(vcpu, regs); 7795 vcpu_put(vcpu); 7796 return 0; 7797 } 7798 7799 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7800 { 7801 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 7802 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7803 7804 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 7805 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 7806 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 7807 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 7808 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 7809 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 7810 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 7811 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 7812 #ifdef CONFIG_X86_64 7813 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 7814 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 7815 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 7816 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 7817 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 7818 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 7819 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 7820 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 7821 #endif 7822 7823 kvm_rip_write(vcpu, regs->rip); 7824 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 7825 7826 vcpu->arch.exception.pending = false; 7827 7828 kvm_make_request(KVM_REQ_EVENT, vcpu); 7829 } 7830 7831 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7832 { 7833 vcpu_load(vcpu); 7834 __set_regs(vcpu, regs); 7835 vcpu_put(vcpu); 7836 return 0; 7837 } 7838 7839 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 7840 { 7841 struct kvm_segment cs; 7842 7843 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7844 *db = cs.db; 7845 *l = cs.l; 7846 } 7847 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 7848 7849 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 7850 { 7851 struct desc_ptr dt; 7852 7853 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7854 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7855 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7856 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7857 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7858 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7859 7860 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7861 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7862 7863 kvm_x86_ops->get_idt(vcpu, &dt); 7864 sregs->idt.limit = dt.size; 7865 sregs->idt.base = dt.address; 7866 kvm_x86_ops->get_gdt(vcpu, &dt); 7867 sregs->gdt.limit = dt.size; 7868 sregs->gdt.base = dt.address; 7869 7870 sregs->cr0 = kvm_read_cr0(vcpu); 7871 sregs->cr2 = vcpu->arch.cr2; 7872 sregs->cr3 = kvm_read_cr3(vcpu); 7873 sregs->cr4 = kvm_read_cr4(vcpu); 7874 sregs->cr8 = kvm_get_cr8(vcpu); 7875 sregs->efer = vcpu->arch.efer; 7876 sregs->apic_base = kvm_get_apic_base(vcpu); 7877 7878 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 7879 7880 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 7881 set_bit(vcpu->arch.interrupt.nr, 7882 (unsigned long *)sregs->interrupt_bitmap); 7883 } 7884 7885 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 7886 struct kvm_sregs *sregs) 7887 { 7888 vcpu_load(vcpu); 7889 __get_sregs(vcpu, sregs); 7890 vcpu_put(vcpu); 7891 return 0; 7892 } 7893 7894 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 7895 struct kvm_mp_state *mp_state) 7896 { 7897 vcpu_load(vcpu); 7898 7899 kvm_apic_accept_events(vcpu); 7900 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 7901 vcpu->arch.pv.pv_unhalted) 7902 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 7903 else 7904 mp_state->mp_state = vcpu->arch.mp_state; 7905 7906 vcpu_put(vcpu); 7907 return 0; 7908 } 7909 7910 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 7911 struct kvm_mp_state *mp_state) 7912 { 7913 int ret = -EINVAL; 7914 7915 vcpu_load(vcpu); 7916 7917 if (!lapic_in_kernel(vcpu) && 7918 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 7919 goto out; 7920 7921 /* INITs are latched while in SMM */ 7922 if ((is_smm(vcpu) || vcpu->arch.smi_pending) && 7923 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 7924 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 7925 goto out; 7926 7927 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 7928 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 7929 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 7930 } else 7931 vcpu->arch.mp_state = mp_state->mp_state; 7932 kvm_make_request(KVM_REQ_EVENT, vcpu); 7933 7934 ret = 0; 7935 out: 7936 vcpu_put(vcpu); 7937 return ret; 7938 } 7939 7940 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 7941 int reason, bool has_error_code, u32 error_code) 7942 { 7943 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 7944 int ret; 7945 7946 init_emulate_ctxt(vcpu); 7947 7948 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 7949 has_error_code, error_code); 7950 7951 if (ret) 7952 return EMULATE_FAIL; 7953 7954 kvm_rip_write(vcpu, ctxt->eip); 7955 kvm_set_rflags(vcpu, ctxt->eflags); 7956 kvm_make_request(KVM_REQ_EVENT, vcpu); 7957 return EMULATE_DONE; 7958 } 7959 EXPORT_SYMBOL_GPL(kvm_task_switch); 7960 7961 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 7962 { 7963 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 7964 /* 7965 * When EFER.LME and CR0.PG are set, the processor is in 7966 * 64-bit mode (though maybe in a 32-bit code segment). 7967 * CR4.PAE and EFER.LMA must be set. 7968 */ 7969 if (!(sregs->cr4 & X86_CR4_PAE) 7970 || !(sregs->efer & EFER_LMA)) 7971 return -EINVAL; 7972 } else { 7973 /* 7974 * Not in 64-bit mode: EFER.LMA is clear and the code 7975 * segment cannot be 64-bit. 7976 */ 7977 if (sregs->efer & EFER_LMA || sregs->cs.l) 7978 return -EINVAL; 7979 } 7980 7981 return 0; 7982 } 7983 7984 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 7985 { 7986 struct msr_data apic_base_msr; 7987 int mmu_reset_needed = 0; 7988 int pending_vec, max_bits, idx; 7989 struct desc_ptr dt; 7990 int ret = -EINVAL; 7991 7992 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 7993 (sregs->cr4 & X86_CR4_OSXSAVE)) 7994 goto out; 7995 7996 if (kvm_valid_sregs(vcpu, sregs)) 7997 goto out; 7998 7999 apic_base_msr.data = sregs->apic_base; 8000 apic_base_msr.host_initiated = true; 8001 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 8002 goto out; 8003 8004 dt.size = sregs->idt.limit; 8005 dt.address = sregs->idt.base; 8006 kvm_x86_ops->set_idt(vcpu, &dt); 8007 dt.size = sregs->gdt.limit; 8008 dt.address = sregs->gdt.base; 8009 kvm_x86_ops->set_gdt(vcpu, &dt); 8010 8011 vcpu->arch.cr2 = sregs->cr2; 8012 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 8013 vcpu->arch.cr3 = sregs->cr3; 8014 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 8015 8016 kvm_set_cr8(vcpu, sregs->cr8); 8017 8018 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 8019 kvm_x86_ops->set_efer(vcpu, sregs->efer); 8020 8021 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 8022 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 8023 vcpu->arch.cr0 = sregs->cr0; 8024 8025 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 8026 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 8027 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 8028 kvm_update_cpuid(vcpu); 8029 8030 idx = srcu_read_lock(&vcpu->kvm->srcu); 8031 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 8032 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 8033 mmu_reset_needed = 1; 8034 } 8035 srcu_read_unlock(&vcpu->kvm->srcu, idx); 8036 8037 if (mmu_reset_needed) 8038 kvm_mmu_reset_context(vcpu); 8039 8040 max_bits = KVM_NR_INTERRUPTS; 8041 pending_vec = find_first_bit( 8042 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 8043 if (pending_vec < max_bits) { 8044 kvm_queue_interrupt(vcpu, pending_vec, false); 8045 pr_debug("Set back pending irq %d\n", pending_vec); 8046 } 8047 8048 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 8049 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 8050 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 8051 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 8052 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 8053 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 8054 8055 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 8056 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 8057 8058 update_cr8_intercept(vcpu); 8059 8060 /* Older userspace won't unhalt the vcpu on reset. */ 8061 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 8062 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 8063 !is_protmode(vcpu)) 8064 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8065 8066 kvm_make_request(KVM_REQ_EVENT, vcpu); 8067 8068 ret = 0; 8069 out: 8070 return ret; 8071 } 8072 8073 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 8074 struct kvm_sregs *sregs) 8075 { 8076 int ret; 8077 8078 vcpu_load(vcpu); 8079 ret = __set_sregs(vcpu, sregs); 8080 vcpu_put(vcpu); 8081 return ret; 8082 } 8083 8084 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 8085 struct kvm_guest_debug *dbg) 8086 { 8087 unsigned long rflags; 8088 int i, r; 8089 8090 vcpu_load(vcpu); 8091 8092 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 8093 r = -EBUSY; 8094 if (vcpu->arch.exception.pending) 8095 goto out; 8096 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 8097 kvm_queue_exception(vcpu, DB_VECTOR); 8098 else 8099 kvm_queue_exception(vcpu, BP_VECTOR); 8100 } 8101 8102 /* 8103 * Read rflags as long as potentially injected trace flags are still 8104 * filtered out. 8105 */ 8106 rflags = kvm_get_rflags(vcpu); 8107 8108 vcpu->guest_debug = dbg->control; 8109 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 8110 vcpu->guest_debug = 0; 8111 8112 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 8113 for (i = 0; i < KVM_NR_DB_REGS; ++i) 8114 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 8115 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 8116 } else { 8117 for (i = 0; i < KVM_NR_DB_REGS; i++) 8118 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 8119 } 8120 kvm_update_dr7(vcpu); 8121 8122 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 8123 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 8124 get_segment_base(vcpu, VCPU_SREG_CS); 8125 8126 /* 8127 * Trigger an rflags update that will inject or remove the trace 8128 * flags. 8129 */ 8130 kvm_set_rflags(vcpu, rflags); 8131 8132 kvm_x86_ops->update_bp_intercept(vcpu); 8133 8134 r = 0; 8135 8136 out: 8137 vcpu_put(vcpu); 8138 return r; 8139 } 8140 8141 /* 8142 * Translate a guest virtual address to a guest physical address. 8143 */ 8144 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 8145 struct kvm_translation *tr) 8146 { 8147 unsigned long vaddr = tr->linear_address; 8148 gpa_t gpa; 8149 int idx; 8150 8151 vcpu_load(vcpu); 8152 8153 idx = srcu_read_lock(&vcpu->kvm->srcu); 8154 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 8155 srcu_read_unlock(&vcpu->kvm->srcu, idx); 8156 tr->physical_address = gpa; 8157 tr->valid = gpa != UNMAPPED_GVA; 8158 tr->writeable = 1; 8159 tr->usermode = 0; 8160 8161 vcpu_put(vcpu); 8162 return 0; 8163 } 8164 8165 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 8166 { 8167 struct fxregs_state *fxsave; 8168 8169 vcpu_load(vcpu); 8170 8171 fxsave = &vcpu->arch.guest_fpu.state.fxsave; 8172 memcpy(fpu->fpr, fxsave->st_space, 128); 8173 fpu->fcw = fxsave->cwd; 8174 fpu->fsw = fxsave->swd; 8175 fpu->ftwx = fxsave->twd; 8176 fpu->last_opcode = fxsave->fop; 8177 fpu->last_ip = fxsave->rip; 8178 fpu->last_dp = fxsave->rdp; 8179 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 8180 8181 vcpu_put(vcpu); 8182 return 0; 8183 } 8184 8185 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 8186 { 8187 struct fxregs_state *fxsave; 8188 8189 vcpu_load(vcpu); 8190 8191 fxsave = &vcpu->arch.guest_fpu.state.fxsave; 8192 8193 memcpy(fxsave->st_space, fpu->fpr, 128); 8194 fxsave->cwd = fpu->fcw; 8195 fxsave->swd = fpu->fsw; 8196 fxsave->twd = fpu->ftwx; 8197 fxsave->fop = fpu->last_opcode; 8198 fxsave->rip = fpu->last_ip; 8199 fxsave->rdp = fpu->last_dp; 8200 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 8201 8202 vcpu_put(vcpu); 8203 return 0; 8204 } 8205 8206 static void store_regs(struct kvm_vcpu *vcpu) 8207 { 8208 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 8209 8210 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 8211 __get_regs(vcpu, &vcpu->run->s.regs.regs); 8212 8213 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 8214 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 8215 8216 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 8217 kvm_vcpu_ioctl_x86_get_vcpu_events( 8218 vcpu, &vcpu->run->s.regs.events); 8219 } 8220 8221 static int sync_regs(struct kvm_vcpu *vcpu) 8222 { 8223 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) 8224 return -EINVAL; 8225 8226 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 8227 __set_regs(vcpu, &vcpu->run->s.regs.regs); 8228 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 8229 } 8230 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 8231 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 8232 return -EINVAL; 8233 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 8234 } 8235 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 8236 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 8237 vcpu, &vcpu->run->s.regs.events)) 8238 return -EINVAL; 8239 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 8240 } 8241 8242 return 0; 8243 } 8244 8245 static void fx_init(struct kvm_vcpu *vcpu) 8246 { 8247 fpstate_init(&vcpu->arch.guest_fpu.state); 8248 if (boot_cpu_has(X86_FEATURE_XSAVES)) 8249 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv = 8250 host_xcr0 | XSTATE_COMPACTION_ENABLED; 8251 8252 /* 8253 * Ensure guest xcr0 is valid for loading 8254 */ 8255 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 8256 8257 vcpu->arch.cr0 |= X86_CR0_ET; 8258 } 8259 8260 /* Swap (qemu) user FPU context for the guest FPU context. */ 8261 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 8262 { 8263 preempt_disable(); 8264 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu); 8265 /* PKRU is separately restored in kvm_x86_ops->run. */ 8266 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state, 8267 ~XFEATURE_MASK_PKRU); 8268 preempt_enable(); 8269 trace_kvm_fpu(1); 8270 } 8271 8272 /* When vcpu_run ends, restore user space FPU context. */ 8273 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 8274 { 8275 preempt_disable(); 8276 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu); 8277 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state); 8278 preempt_enable(); 8279 ++vcpu->stat.fpu_reload; 8280 trace_kvm_fpu(0); 8281 } 8282 8283 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 8284 { 8285 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask; 8286 8287 kvmclock_reset(vcpu); 8288 8289 kvm_x86_ops->vcpu_free(vcpu); 8290 free_cpumask_var(wbinvd_dirty_mask); 8291 } 8292 8293 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 8294 unsigned int id) 8295 { 8296 struct kvm_vcpu *vcpu; 8297 8298 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 8299 printk_once(KERN_WARNING 8300 "kvm: SMP vm created on host with unstable TSC; " 8301 "guest TSC will not be reliable\n"); 8302 8303 vcpu = kvm_x86_ops->vcpu_create(kvm, id); 8304 8305 return vcpu; 8306 } 8307 8308 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 8309 { 8310 kvm_vcpu_mtrr_init(vcpu); 8311 vcpu_load(vcpu); 8312 kvm_vcpu_reset(vcpu, false); 8313 kvm_mmu_setup(vcpu); 8314 vcpu_put(vcpu); 8315 return 0; 8316 } 8317 8318 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 8319 { 8320 struct msr_data msr; 8321 struct kvm *kvm = vcpu->kvm; 8322 8323 kvm_hv_vcpu_postcreate(vcpu); 8324 8325 if (mutex_lock_killable(&vcpu->mutex)) 8326 return; 8327 vcpu_load(vcpu); 8328 msr.data = 0x0; 8329 msr.index = MSR_IA32_TSC; 8330 msr.host_initiated = true; 8331 kvm_write_tsc(vcpu, &msr); 8332 vcpu_put(vcpu); 8333 mutex_unlock(&vcpu->mutex); 8334 8335 if (!kvmclock_periodic_sync) 8336 return; 8337 8338 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 8339 KVMCLOCK_SYNC_PERIOD); 8340 } 8341 8342 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 8343 { 8344 vcpu->arch.apf.msr_val = 0; 8345 8346 vcpu_load(vcpu); 8347 kvm_mmu_unload(vcpu); 8348 vcpu_put(vcpu); 8349 8350 kvm_x86_ops->vcpu_free(vcpu); 8351 } 8352 8353 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 8354 { 8355 kvm_lapic_reset(vcpu, init_event); 8356 8357 vcpu->arch.hflags = 0; 8358 8359 vcpu->arch.smi_pending = 0; 8360 vcpu->arch.smi_count = 0; 8361 atomic_set(&vcpu->arch.nmi_queued, 0); 8362 vcpu->arch.nmi_pending = 0; 8363 vcpu->arch.nmi_injected = false; 8364 kvm_clear_interrupt_queue(vcpu); 8365 kvm_clear_exception_queue(vcpu); 8366 vcpu->arch.exception.pending = false; 8367 8368 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 8369 kvm_update_dr0123(vcpu); 8370 vcpu->arch.dr6 = DR6_INIT; 8371 kvm_update_dr6(vcpu); 8372 vcpu->arch.dr7 = DR7_FIXED_1; 8373 kvm_update_dr7(vcpu); 8374 8375 vcpu->arch.cr2 = 0; 8376 8377 kvm_make_request(KVM_REQ_EVENT, vcpu); 8378 vcpu->arch.apf.msr_val = 0; 8379 vcpu->arch.st.msr_val = 0; 8380 8381 kvmclock_reset(vcpu); 8382 8383 kvm_clear_async_pf_completion_queue(vcpu); 8384 kvm_async_pf_hash_reset(vcpu); 8385 vcpu->arch.apf.halted = false; 8386 8387 if (kvm_mpx_supported()) { 8388 void *mpx_state_buffer; 8389 8390 /* 8391 * To avoid have the INIT path from kvm_apic_has_events() that be 8392 * called with loaded FPU and does not let userspace fix the state. 8393 */ 8394 if (init_event) 8395 kvm_put_guest_fpu(vcpu); 8396 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave, 8397 XFEATURE_MASK_BNDREGS); 8398 if (mpx_state_buffer) 8399 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); 8400 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave, 8401 XFEATURE_MASK_BNDCSR); 8402 if (mpx_state_buffer) 8403 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); 8404 if (init_event) 8405 kvm_load_guest_fpu(vcpu); 8406 } 8407 8408 if (!init_event) { 8409 kvm_pmu_reset(vcpu); 8410 vcpu->arch.smbase = 0x30000; 8411 8412 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 8413 vcpu->arch.msr_misc_features_enables = 0; 8414 8415 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 8416 } 8417 8418 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 8419 vcpu->arch.regs_avail = ~0; 8420 vcpu->arch.regs_dirty = ~0; 8421 8422 vcpu->arch.ia32_xss = 0; 8423 8424 kvm_x86_ops->vcpu_reset(vcpu, init_event); 8425 } 8426 8427 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 8428 { 8429 struct kvm_segment cs; 8430 8431 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 8432 cs.selector = vector << 8; 8433 cs.base = vector << 12; 8434 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 8435 kvm_rip_write(vcpu, 0); 8436 } 8437 8438 int kvm_arch_hardware_enable(void) 8439 { 8440 struct kvm *kvm; 8441 struct kvm_vcpu *vcpu; 8442 int i; 8443 int ret; 8444 u64 local_tsc; 8445 u64 max_tsc = 0; 8446 bool stable, backwards_tsc = false; 8447 8448 kvm_shared_msr_cpu_online(); 8449 ret = kvm_x86_ops->hardware_enable(); 8450 if (ret != 0) 8451 return ret; 8452 8453 local_tsc = rdtsc(); 8454 stable = !kvm_check_tsc_unstable(); 8455 list_for_each_entry(kvm, &vm_list, vm_list) { 8456 kvm_for_each_vcpu(i, vcpu, kvm) { 8457 if (!stable && vcpu->cpu == smp_processor_id()) 8458 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 8459 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 8460 backwards_tsc = true; 8461 if (vcpu->arch.last_host_tsc > max_tsc) 8462 max_tsc = vcpu->arch.last_host_tsc; 8463 } 8464 } 8465 } 8466 8467 /* 8468 * Sometimes, even reliable TSCs go backwards. This happens on 8469 * platforms that reset TSC during suspend or hibernate actions, but 8470 * maintain synchronization. We must compensate. Fortunately, we can 8471 * detect that condition here, which happens early in CPU bringup, 8472 * before any KVM threads can be running. Unfortunately, we can't 8473 * bring the TSCs fully up to date with real time, as we aren't yet far 8474 * enough into CPU bringup that we know how much real time has actually 8475 * elapsed; our helper function, ktime_get_boot_ns() will be using boot 8476 * variables that haven't been updated yet. 8477 * 8478 * So we simply find the maximum observed TSC above, then record the 8479 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 8480 * the adjustment will be applied. Note that we accumulate 8481 * adjustments, in case multiple suspend cycles happen before some VCPU 8482 * gets a chance to run again. In the event that no KVM threads get a 8483 * chance to run, we will miss the entire elapsed period, as we'll have 8484 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 8485 * loose cycle time. This isn't too big a deal, since the loss will be 8486 * uniform across all VCPUs (not to mention the scenario is extremely 8487 * unlikely). It is possible that a second hibernate recovery happens 8488 * much faster than a first, causing the observed TSC here to be 8489 * smaller; this would require additional padding adjustment, which is 8490 * why we set last_host_tsc to the local tsc observed here. 8491 * 8492 * N.B. - this code below runs only on platforms with reliable TSC, 8493 * as that is the only way backwards_tsc is set above. Also note 8494 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 8495 * have the same delta_cyc adjustment applied if backwards_tsc 8496 * is detected. Note further, this adjustment is only done once, 8497 * as we reset last_host_tsc on all VCPUs to stop this from being 8498 * called multiple times (one for each physical CPU bringup). 8499 * 8500 * Platforms with unreliable TSCs don't have to deal with this, they 8501 * will be compensated by the logic in vcpu_load, which sets the TSC to 8502 * catchup mode. This will catchup all VCPUs to real time, but cannot 8503 * guarantee that they stay in perfect synchronization. 8504 */ 8505 if (backwards_tsc) { 8506 u64 delta_cyc = max_tsc - local_tsc; 8507 list_for_each_entry(kvm, &vm_list, vm_list) { 8508 kvm->arch.backwards_tsc_observed = true; 8509 kvm_for_each_vcpu(i, vcpu, kvm) { 8510 vcpu->arch.tsc_offset_adjustment += delta_cyc; 8511 vcpu->arch.last_host_tsc = local_tsc; 8512 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 8513 } 8514 8515 /* 8516 * We have to disable TSC offset matching.. if you were 8517 * booting a VM while issuing an S4 host suspend.... 8518 * you may have some problem. Solving this issue is 8519 * left as an exercise to the reader. 8520 */ 8521 kvm->arch.last_tsc_nsec = 0; 8522 kvm->arch.last_tsc_write = 0; 8523 } 8524 8525 } 8526 return 0; 8527 } 8528 8529 void kvm_arch_hardware_disable(void) 8530 { 8531 kvm_x86_ops->hardware_disable(); 8532 drop_user_return_notifiers(); 8533 } 8534 8535 int kvm_arch_hardware_setup(void) 8536 { 8537 int r; 8538 8539 r = kvm_x86_ops->hardware_setup(); 8540 if (r != 0) 8541 return r; 8542 8543 if (kvm_has_tsc_control) { 8544 /* 8545 * Make sure the user can only configure tsc_khz values that 8546 * fit into a signed integer. 8547 * A min value is not calculated needed because it will always 8548 * be 1 on all machines. 8549 */ 8550 u64 max = min(0x7fffffffULL, 8551 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 8552 kvm_max_guest_tsc_khz = max; 8553 8554 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 8555 } 8556 8557 kvm_init_msr_list(); 8558 return 0; 8559 } 8560 8561 void kvm_arch_hardware_unsetup(void) 8562 { 8563 kvm_x86_ops->hardware_unsetup(); 8564 } 8565 8566 void kvm_arch_check_processor_compat(void *rtn) 8567 { 8568 kvm_x86_ops->check_processor_compatibility(rtn); 8569 } 8570 8571 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 8572 { 8573 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 8574 } 8575 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 8576 8577 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 8578 { 8579 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 8580 } 8581 8582 struct static_key kvm_no_apic_vcpu __read_mostly; 8583 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); 8584 8585 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 8586 { 8587 struct page *page; 8588 int r; 8589 8590 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu); 8591 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 8592 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 8593 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8594 else 8595 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 8596 8597 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 8598 if (!page) { 8599 r = -ENOMEM; 8600 goto fail; 8601 } 8602 vcpu->arch.pio_data = page_address(page); 8603 8604 kvm_set_tsc_khz(vcpu, max_tsc_khz); 8605 8606 r = kvm_mmu_create(vcpu); 8607 if (r < 0) 8608 goto fail_free_pio_data; 8609 8610 if (irqchip_in_kernel(vcpu->kvm)) { 8611 r = kvm_create_lapic(vcpu); 8612 if (r < 0) 8613 goto fail_mmu_destroy; 8614 } else 8615 static_key_slow_inc(&kvm_no_apic_vcpu); 8616 8617 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 8618 GFP_KERNEL); 8619 if (!vcpu->arch.mce_banks) { 8620 r = -ENOMEM; 8621 goto fail_free_lapic; 8622 } 8623 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 8624 8625 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 8626 r = -ENOMEM; 8627 goto fail_free_mce_banks; 8628 } 8629 8630 fx_init(vcpu); 8631 8632 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 8633 8634 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 8635 8636 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 8637 8638 kvm_async_pf_hash_reset(vcpu); 8639 kvm_pmu_init(vcpu); 8640 8641 vcpu->arch.pending_external_vector = -1; 8642 vcpu->arch.preempted_in_kernel = false; 8643 8644 kvm_hv_vcpu_init(vcpu); 8645 8646 return 0; 8647 8648 fail_free_mce_banks: 8649 kfree(vcpu->arch.mce_banks); 8650 fail_free_lapic: 8651 kvm_free_lapic(vcpu); 8652 fail_mmu_destroy: 8653 kvm_mmu_destroy(vcpu); 8654 fail_free_pio_data: 8655 free_page((unsigned long)vcpu->arch.pio_data); 8656 fail: 8657 return r; 8658 } 8659 8660 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 8661 { 8662 int idx; 8663 8664 kvm_hv_vcpu_uninit(vcpu); 8665 kvm_pmu_destroy(vcpu); 8666 kfree(vcpu->arch.mce_banks); 8667 kvm_free_lapic(vcpu); 8668 idx = srcu_read_lock(&vcpu->kvm->srcu); 8669 kvm_mmu_destroy(vcpu); 8670 srcu_read_unlock(&vcpu->kvm->srcu, idx); 8671 free_page((unsigned long)vcpu->arch.pio_data); 8672 if (!lapic_in_kernel(vcpu)) 8673 static_key_slow_dec(&kvm_no_apic_vcpu); 8674 } 8675 8676 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 8677 { 8678 kvm_x86_ops->sched_in(vcpu, cpu); 8679 } 8680 8681 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 8682 { 8683 if (type) 8684 return -EINVAL; 8685 8686 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 8687 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 8688 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 8689 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 8690 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 8691 8692 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 8693 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 8694 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 8695 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 8696 &kvm->arch.irq_sources_bitmap); 8697 8698 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 8699 mutex_init(&kvm->arch.apic_map_lock); 8700 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 8701 8702 kvm->arch.kvmclock_offset = -ktime_get_boot_ns(); 8703 pvclock_update_vm_gtod_copy(kvm); 8704 8705 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 8706 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 8707 8708 kvm_hv_init_vm(kvm); 8709 kvm_page_track_init(kvm); 8710 kvm_mmu_init_vm(kvm); 8711 8712 if (kvm_x86_ops->vm_init) 8713 return kvm_x86_ops->vm_init(kvm); 8714 8715 return 0; 8716 } 8717 8718 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 8719 { 8720 vcpu_load(vcpu); 8721 kvm_mmu_unload(vcpu); 8722 vcpu_put(vcpu); 8723 } 8724 8725 static void kvm_free_vcpus(struct kvm *kvm) 8726 { 8727 unsigned int i; 8728 struct kvm_vcpu *vcpu; 8729 8730 /* 8731 * Unpin any mmu pages first. 8732 */ 8733 kvm_for_each_vcpu(i, vcpu, kvm) { 8734 kvm_clear_async_pf_completion_queue(vcpu); 8735 kvm_unload_vcpu_mmu(vcpu); 8736 } 8737 kvm_for_each_vcpu(i, vcpu, kvm) 8738 kvm_arch_vcpu_free(vcpu); 8739 8740 mutex_lock(&kvm->lock); 8741 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 8742 kvm->vcpus[i] = NULL; 8743 8744 atomic_set(&kvm->online_vcpus, 0); 8745 mutex_unlock(&kvm->lock); 8746 } 8747 8748 void kvm_arch_sync_events(struct kvm *kvm) 8749 { 8750 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 8751 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 8752 kvm_free_pit(kvm); 8753 } 8754 8755 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 8756 { 8757 int i, r; 8758 unsigned long hva; 8759 struct kvm_memslots *slots = kvm_memslots(kvm); 8760 struct kvm_memory_slot *slot, old; 8761 8762 /* Called with kvm->slots_lock held. */ 8763 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 8764 return -EINVAL; 8765 8766 slot = id_to_memslot(slots, id); 8767 if (size) { 8768 if (slot->npages) 8769 return -EEXIST; 8770 8771 /* 8772 * MAP_SHARED to prevent internal slot pages from being moved 8773 * by fork()/COW. 8774 */ 8775 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 8776 MAP_SHARED | MAP_ANONYMOUS, 0); 8777 if (IS_ERR((void *)hva)) 8778 return PTR_ERR((void *)hva); 8779 } else { 8780 if (!slot->npages) 8781 return 0; 8782 8783 hva = 0; 8784 } 8785 8786 old = *slot; 8787 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 8788 struct kvm_userspace_memory_region m; 8789 8790 m.slot = id | (i << 16); 8791 m.flags = 0; 8792 m.guest_phys_addr = gpa; 8793 m.userspace_addr = hva; 8794 m.memory_size = size; 8795 r = __kvm_set_memory_region(kvm, &m); 8796 if (r < 0) 8797 return r; 8798 } 8799 8800 if (!size) 8801 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); 8802 8803 return 0; 8804 } 8805 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 8806 8807 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 8808 { 8809 int r; 8810 8811 mutex_lock(&kvm->slots_lock); 8812 r = __x86_set_memory_region(kvm, id, gpa, size); 8813 mutex_unlock(&kvm->slots_lock); 8814 8815 return r; 8816 } 8817 EXPORT_SYMBOL_GPL(x86_set_memory_region); 8818 8819 void kvm_arch_destroy_vm(struct kvm *kvm) 8820 { 8821 if (current->mm == kvm->mm) { 8822 /* 8823 * Free memory regions allocated on behalf of userspace, 8824 * unless the the memory map has changed due to process exit 8825 * or fd copying. 8826 */ 8827 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); 8828 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); 8829 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 8830 } 8831 if (kvm_x86_ops->vm_destroy) 8832 kvm_x86_ops->vm_destroy(kvm); 8833 kvm_pic_destroy(kvm); 8834 kvm_ioapic_destroy(kvm); 8835 kvm_free_vcpus(kvm); 8836 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 8837 kvm_mmu_uninit_vm(kvm); 8838 kvm_page_track_cleanup(kvm); 8839 kvm_hv_destroy_vm(kvm); 8840 } 8841 8842 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 8843 struct kvm_memory_slot *dont) 8844 { 8845 int i; 8846 8847 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8848 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 8849 kvfree(free->arch.rmap[i]); 8850 free->arch.rmap[i] = NULL; 8851 } 8852 if (i == 0) 8853 continue; 8854 8855 if (!dont || free->arch.lpage_info[i - 1] != 8856 dont->arch.lpage_info[i - 1]) { 8857 kvfree(free->arch.lpage_info[i - 1]); 8858 free->arch.lpage_info[i - 1] = NULL; 8859 } 8860 } 8861 8862 kvm_page_track_free_memslot(free, dont); 8863 } 8864 8865 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 8866 unsigned long npages) 8867 { 8868 int i; 8869 8870 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8871 struct kvm_lpage_info *linfo; 8872 unsigned long ugfn; 8873 int lpages; 8874 int level = i + 1; 8875 8876 lpages = gfn_to_index(slot->base_gfn + npages - 1, 8877 slot->base_gfn, level) + 1; 8878 8879 slot->arch.rmap[i] = 8880 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL); 8881 if (!slot->arch.rmap[i]) 8882 goto out_free; 8883 if (i == 0) 8884 continue; 8885 8886 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL); 8887 if (!linfo) 8888 goto out_free; 8889 8890 slot->arch.lpage_info[i - 1] = linfo; 8891 8892 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 8893 linfo[0].disallow_lpage = 1; 8894 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 8895 linfo[lpages - 1].disallow_lpage = 1; 8896 ugfn = slot->userspace_addr >> PAGE_SHIFT; 8897 /* 8898 * If the gfn and userspace address are not aligned wrt each 8899 * other, or if explicitly asked to, disable large page 8900 * support for this slot 8901 */ 8902 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 8903 !kvm_largepages_enabled()) { 8904 unsigned long j; 8905 8906 for (j = 0; j < lpages; ++j) 8907 linfo[j].disallow_lpage = 1; 8908 } 8909 } 8910 8911 if (kvm_page_track_create_memslot(slot, npages)) 8912 goto out_free; 8913 8914 return 0; 8915 8916 out_free: 8917 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8918 kvfree(slot->arch.rmap[i]); 8919 slot->arch.rmap[i] = NULL; 8920 if (i == 0) 8921 continue; 8922 8923 kvfree(slot->arch.lpage_info[i - 1]); 8924 slot->arch.lpage_info[i - 1] = NULL; 8925 } 8926 return -ENOMEM; 8927 } 8928 8929 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) 8930 { 8931 /* 8932 * memslots->generation has been incremented. 8933 * mmio generation may have reached its maximum value. 8934 */ 8935 kvm_mmu_invalidate_mmio_sptes(kvm, slots); 8936 } 8937 8938 int kvm_arch_prepare_memory_region(struct kvm *kvm, 8939 struct kvm_memory_slot *memslot, 8940 const struct kvm_userspace_memory_region *mem, 8941 enum kvm_mr_change change) 8942 { 8943 return 0; 8944 } 8945 8946 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 8947 struct kvm_memory_slot *new) 8948 { 8949 /* Still write protect RO slot */ 8950 if (new->flags & KVM_MEM_READONLY) { 8951 kvm_mmu_slot_remove_write_access(kvm, new); 8952 return; 8953 } 8954 8955 /* 8956 * Call kvm_x86_ops dirty logging hooks when they are valid. 8957 * 8958 * kvm_x86_ops->slot_disable_log_dirty is called when: 8959 * 8960 * - KVM_MR_CREATE with dirty logging is disabled 8961 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 8962 * 8963 * The reason is, in case of PML, we need to set D-bit for any slots 8964 * with dirty logging disabled in order to eliminate unnecessary GPA 8965 * logging in PML buffer (and potential PML buffer full VMEXT). This 8966 * guarantees leaving PML enabled during guest's lifetime won't have 8967 * any additonal overhead from PML when guest is running with dirty 8968 * logging disabled for memory slots. 8969 * 8970 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 8971 * to dirty logging mode. 8972 * 8973 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 8974 * 8975 * In case of write protect: 8976 * 8977 * Write protect all pages for dirty logging. 8978 * 8979 * All the sptes including the large sptes which point to this 8980 * slot are set to readonly. We can not create any new large 8981 * spte on this slot until the end of the logging. 8982 * 8983 * See the comments in fast_page_fault(). 8984 */ 8985 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 8986 if (kvm_x86_ops->slot_enable_log_dirty) 8987 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 8988 else 8989 kvm_mmu_slot_remove_write_access(kvm, new); 8990 } else { 8991 if (kvm_x86_ops->slot_disable_log_dirty) 8992 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 8993 } 8994 } 8995 8996 void kvm_arch_commit_memory_region(struct kvm *kvm, 8997 const struct kvm_userspace_memory_region *mem, 8998 const struct kvm_memory_slot *old, 8999 const struct kvm_memory_slot *new, 9000 enum kvm_mr_change change) 9001 { 9002 int nr_mmu_pages = 0; 9003 9004 if (!kvm->arch.n_requested_mmu_pages) 9005 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 9006 9007 if (nr_mmu_pages) 9008 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 9009 9010 /* 9011 * Dirty logging tracks sptes in 4k granularity, meaning that large 9012 * sptes have to be split. If live migration is successful, the guest 9013 * in the source machine will be destroyed and large sptes will be 9014 * created in the destination. However, if the guest continues to run 9015 * in the source machine (for example if live migration fails), small 9016 * sptes will remain around and cause bad performance. 9017 * 9018 * Scan sptes if dirty logging has been stopped, dropping those 9019 * which can be collapsed into a single large-page spte. Later 9020 * page faults will create the large-page sptes. 9021 */ 9022 if ((change != KVM_MR_DELETE) && 9023 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 9024 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 9025 kvm_mmu_zap_collapsible_sptes(kvm, new); 9026 9027 /* 9028 * Set up write protection and/or dirty logging for the new slot. 9029 * 9030 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 9031 * been zapped so no dirty logging staff is needed for old slot. For 9032 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 9033 * new and it's also covered when dealing with the new slot. 9034 * 9035 * FIXME: const-ify all uses of struct kvm_memory_slot. 9036 */ 9037 if (change != KVM_MR_DELETE) 9038 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 9039 } 9040 9041 void kvm_arch_flush_shadow_all(struct kvm *kvm) 9042 { 9043 kvm_mmu_invalidate_zap_all_pages(kvm); 9044 } 9045 9046 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 9047 struct kvm_memory_slot *slot) 9048 { 9049 kvm_page_track_flush_slot(kvm, slot); 9050 } 9051 9052 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 9053 { 9054 if (!list_empty_careful(&vcpu->async_pf.done)) 9055 return true; 9056 9057 if (kvm_apic_has_events(vcpu)) 9058 return true; 9059 9060 if (vcpu->arch.pv.pv_unhalted) 9061 return true; 9062 9063 if (vcpu->arch.exception.pending) 9064 return true; 9065 9066 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 9067 (vcpu->arch.nmi_pending && 9068 kvm_x86_ops->nmi_allowed(vcpu))) 9069 return true; 9070 9071 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 9072 (vcpu->arch.smi_pending && !is_smm(vcpu))) 9073 return true; 9074 9075 if (kvm_arch_interrupt_allowed(vcpu) && 9076 kvm_cpu_has_interrupt(vcpu)) 9077 return true; 9078 9079 if (kvm_hv_has_stimer_pending(vcpu)) 9080 return true; 9081 9082 return false; 9083 } 9084 9085 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 9086 { 9087 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 9088 } 9089 9090 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 9091 { 9092 return vcpu->arch.preempted_in_kernel; 9093 } 9094 9095 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 9096 { 9097 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 9098 } 9099 9100 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 9101 { 9102 return kvm_x86_ops->interrupt_allowed(vcpu); 9103 } 9104 9105 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 9106 { 9107 if (is_64_bit_mode(vcpu)) 9108 return kvm_rip_read(vcpu); 9109 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 9110 kvm_rip_read(vcpu)); 9111 } 9112 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 9113 9114 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 9115 { 9116 return kvm_get_linear_rip(vcpu) == linear_rip; 9117 } 9118 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 9119 9120 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 9121 { 9122 unsigned long rflags; 9123 9124 rflags = kvm_x86_ops->get_rflags(vcpu); 9125 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 9126 rflags &= ~X86_EFLAGS_TF; 9127 return rflags; 9128 } 9129 EXPORT_SYMBOL_GPL(kvm_get_rflags); 9130 9131 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 9132 { 9133 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 9134 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 9135 rflags |= X86_EFLAGS_TF; 9136 kvm_x86_ops->set_rflags(vcpu, rflags); 9137 } 9138 9139 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 9140 { 9141 __kvm_set_rflags(vcpu, rflags); 9142 kvm_make_request(KVM_REQ_EVENT, vcpu); 9143 } 9144 EXPORT_SYMBOL_GPL(kvm_set_rflags); 9145 9146 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 9147 { 9148 int r; 9149 9150 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 9151 work->wakeup_all) 9152 return; 9153 9154 r = kvm_mmu_reload(vcpu); 9155 if (unlikely(r)) 9156 return; 9157 9158 if (!vcpu->arch.mmu.direct_map && 9159 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 9160 return; 9161 9162 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 9163 } 9164 9165 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 9166 { 9167 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 9168 } 9169 9170 static inline u32 kvm_async_pf_next_probe(u32 key) 9171 { 9172 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 9173 } 9174 9175 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 9176 { 9177 u32 key = kvm_async_pf_hash_fn(gfn); 9178 9179 while (vcpu->arch.apf.gfns[key] != ~0) 9180 key = kvm_async_pf_next_probe(key); 9181 9182 vcpu->arch.apf.gfns[key] = gfn; 9183 } 9184 9185 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 9186 { 9187 int i; 9188 u32 key = kvm_async_pf_hash_fn(gfn); 9189 9190 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 9191 (vcpu->arch.apf.gfns[key] != gfn && 9192 vcpu->arch.apf.gfns[key] != ~0); i++) 9193 key = kvm_async_pf_next_probe(key); 9194 9195 return key; 9196 } 9197 9198 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 9199 { 9200 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 9201 } 9202 9203 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 9204 { 9205 u32 i, j, k; 9206 9207 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 9208 while (true) { 9209 vcpu->arch.apf.gfns[i] = ~0; 9210 do { 9211 j = kvm_async_pf_next_probe(j); 9212 if (vcpu->arch.apf.gfns[j] == ~0) 9213 return; 9214 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 9215 /* 9216 * k lies cyclically in ]i,j] 9217 * | i.k.j | 9218 * |....j i.k.| or |.k..j i...| 9219 */ 9220 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 9221 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 9222 i = j; 9223 } 9224 } 9225 9226 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 9227 { 9228 9229 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 9230 sizeof(val)); 9231 } 9232 9233 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val) 9234 { 9235 9236 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val, 9237 sizeof(u32)); 9238 } 9239 9240 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 9241 struct kvm_async_pf *work) 9242 { 9243 struct x86_exception fault; 9244 9245 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 9246 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 9247 9248 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 9249 (vcpu->arch.apf.send_user_only && 9250 kvm_x86_ops->get_cpl(vcpu) == 0)) 9251 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 9252 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 9253 fault.vector = PF_VECTOR; 9254 fault.error_code_valid = true; 9255 fault.error_code = 0; 9256 fault.nested_page_fault = false; 9257 fault.address = work->arch.token; 9258 fault.async_page_fault = true; 9259 kvm_inject_page_fault(vcpu, &fault); 9260 } 9261 } 9262 9263 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 9264 struct kvm_async_pf *work) 9265 { 9266 struct x86_exception fault; 9267 u32 val; 9268 9269 if (work->wakeup_all) 9270 work->arch.token = ~0; /* broadcast wakeup */ 9271 else 9272 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 9273 trace_kvm_async_pf_ready(work->arch.token, work->gva); 9274 9275 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED && 9276 !apf_get_user(vcpu, &val)) { 9277 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT && 9278 vcpu->arch.exception.pending && 9279 vcpu->arch.exception.nr == PF_VECTOR && 9280 !apf_put_user(vcpu, 0)) { 9281 vcpu->arch.exception.injected = false; 9282 vcpu->arch.exception.pending = false; 9283 vcpu->arch.exception.nr = 0; 9284 vcpu->arch.exception.has_error_code = false; 9285 vcpu->arch.exception.error_code = 0; 9286 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 9287 fault.vector = PF_VECTOR; 9288 fault.error_code_valid = true; 9289 fault.error_code = 0; 9290 fault.nested_page_fault = false; 9291 fault.address = work->arch.token; 9292 fault.async_page_fault = true; 9293 kvm_inject_page_fault(vcpu, &fault); 9294 } 9295 } 9296 vcpu->arch.apf.halted = false; 9297 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 9298 } 9299 9300 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 9301 { 9302 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 9303 return true; 9304 else 9305 return kvm_can_do_async_pf(vcpu); 9306 } 9307 9308 void kvm_arch_start_assignment(struct kvm *kvm) 9309 { 9310 atomic_inc(&kvm->arch.assigned_device_count); 9311 } 9312 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 9313 9314 void kvm_arch_end_assignment(struct kvm *kvm) 9315 { 9316 atomic_dec(&kvm->arch.assigned_device_count); 9317 } 9318 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 9319 9320 bool kvm_arch_has_assigned_device(struct kvm *kvm) 9321 { 9322 return atomic_read(&kvm->arch.assigned_device_count); 9323 } 9324 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 9325 9326 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 9327 { 9328 atomic_inc(&kvm->arch.noncoherent_dma_count); 9329 } 9330 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 9331 9332 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 9333 { 9334 atomic_dec(&kvm->arch.noncoherent_dma_count); 9335 } 9336 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 9337 9338 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 9339 { 9340 return atomic_read(&kvm->arch.noncoherent_dma_count); 9341 } 9342 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 9343 9344 bool kvm_arch_has_irq_bypass(void) 9345 { 9346 return kvm_x86_ops->update_pi_irte != NULL; 9347 } 9348 9349 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 9350 struct irq_bypass_producer *prod) 9351 { 9352 struct kvm_kernel_irqfd *irqfd = 9353 container_of(cons, struct kvm_kernel_irqfd, consumer); 9354 9355 irqfd->producer = prod; 9356 9357 return kvm_x86_ops->update_pi_irte(irqfd->kvm, 9358 prod->irq, irqfd->gsi, 1); 9359 } 9360 9361 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 9362 struct irq_bypass_producer *prod) 9363 { 9364 int ret; 9365 struct kvm_kernel_irqfd *irqfd = 9366 container_of(cons, struct kvm_kernel_irqfd, consumer); 9367 9368 WARN_ON(irqfd->producer != prod); 9369 irqfd->producer = NULL; 9370 9371 /* 9372 * When producer of consumer is unregistered, we change back to 9373 * remapped mode, so we can re-use the current implementation 9374 * when the irq is masked/disabled or the consumer side (KVM 9375 * int this case doesn't want to receive the interrupts. 9376 */ 9377 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 9378 if (ret) 9379 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 9380 " fails: %d\n", irqfd->consumer.token, ret); 9381 } 9382 9383 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 9384 uint32_t guest_irq, bool set) 9385 { 9386 if (!kvm_x86_ops->update_pi_irte) 9387 return -EINVAL; 9388 9389 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); 9390 } 9391 9392 bool kvm_vector_hashing_enabled(void) 9393 { 9394 return vector_hashing; 9395 } 9396 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled); 9397 9398 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 9399 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 9400 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 9401 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 9402 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 9403 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 9404 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 9405 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 9406 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 9407 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 9408 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 9409 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 9410 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 9411 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 9412 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 9413 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 9414 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 9415 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 9416 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 9417