1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * derived from drivers/kvm/kvm_main.c 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright (C) 2008 Qumranet, Inc. 9 * Copyright IBM Corporation, 2008 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 11 * 12 * Authors: 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * Amit Shah <amit.shah@qumranet.com> 16 * Ben-Ami Yassour <benami@il.ibm.com> 17 */ 18 19 #include <linux/kvm_host.h> 20 #include "irq.h" 21 #include "mmu.h" 22 #include "i8254.h" 23 #include "tss.h" 24 #include "kvm_cache_regs.h" 25 #include "kvm_emulate.h" 26 #include "x86.h" 27 #include "cpuid.h" 28 #include "pmu.h" 29 #include "hyperv.h" 30 #include "lapic.h" 31 32 #include <linux/clocksource.h> 33 #include <linux/interrupt.h> 34 #include <linux/kvm.h> 35 #include <linux/fs.h> 36 #include <linux/vmalloc.h> 37 #include <linux/export.h> 38 #include <linux/moduleparam.h> 39 #include <linux/mman.h> 40 #include <linux/highmem.h> 41 #include <linux/iommu.h> 42 #include <linux/intel-iommu.h> 43 #include <linux/cpufreq.h> 44 #include <linux/user-return-notifier.h> 45 #include <linux/srcu.h> 46 #include <linux/slab.h> 47 #include <linux/perf_event.h> 48 #include <linux/uaccess.h> 49 #include <linux/hash.h> 50 #include <linux/pci.h> 51 #include <linux/timekeeper_internal.h> 52 #include <linux/pvclock_gtod.h> 53 #include <linux/kvm_irqfd.h> 54 #include <linux/irqbypass.h> 55 #include <linux/sched/stat.h> 56 #include <linux/sched/isolation.h> 57 #include <linux/mem_encrypt.h> 58 59 #include <trace/events/kvm.h> 60 61 #include <asm/debugreg.h> 62 #include <asm/msr.h> 63 #include <asm/desc.h> 64 #include <asm/mce.h> 65 #include <linux/kernel_stat.h> 66 #include <asm/fpu/internal.h> /* Ugh! */ 67 #include <asm/pvclock.h> 68 #include <asm/div64.h> 69 #include <asm/irq_remapping.h> 70 #include <asm/mshyperv.h> 71 #include <asm/hypervisor.h> 72 #include <asm/intel_pt.h> 73 #include <asm/emulate_prefix.h> 74 #include <clocksource/hyperv_timer.h> 75 76 #define CREATE_TRACE_POINTS 77 #include "trace.h" 78 79 #define MAX_IO_MSRS 256 80 #define KVM_MAX_MCE_BANKS 32 81 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 82 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 83 84 #define emul_to_vcpu(ctxt) \ 85 ((struct kvm_vcpu *)(ctxt)->vcpu) 86 87 /* EFER defaults: 88 * - enable syscall per default because its emulated by KVM 89 * - enable LME and LMA per default on 64 bit KVM 90 */ 91 #ifdef CONFIG_X86_64 92 static 93 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 94 #else 95 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 96 #endif 97 98 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; 99 100 #define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__ 101 #define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__ 102 103 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 104 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 105 106 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 107 static void process_nmi(struct kvm_vcpu *vcpu); 108 static void enter_smm(struct kvm_vcpu *vcpu); 109 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 110 static void store_regs(struct kvm_vcpu *vcpu); 111 static int sync_regs(struct kvm_vcpu *vcpu); 112 113 struct kvm_x86_ops kvm_x86_ops __read_mostly; 114 EXPORT_SYMBOL_GPL(kvm_x86_ops); 115 116 static bool __read_mostly ignore_msrs = 0; 117 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 118 119 static bool __read_mostly report_ignored_msrs = true; 120 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 121 122 unsigned int min_timer_period_us = 200; 123 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 124 125 static bool __read_mostly kvmclock_periodic_sync = true; 126 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 127 128 bool __read_mostly kvm_has_tsc_control; 129 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 130 u32 __read_mostly kvm_max_guest_tsc_khz; 131 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 132 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 133 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 134 u64 __read_mostly kvm_max_tsc_scaling_ratio; 135 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 136 u64 __read_mostly kvm_default_tsc_scaling_ratio; 137 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 138 139 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 140 static u32 __read_mostly tsc_tolerance_ppm = 250; 141 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 142 143 /* 144 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 145 * adaptive tuning starting from default advancment of 1000ns. '0' disables 146 * advancement entirely. Any other value is used as-is and disables adaptive 147 * tuning, i.e. allows priveleged userspace to set an exact advancement time. 148 */ 149 static int __read_mostly lapic_timer_advance_ns = -1; 150 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); 151 152 static bool __read_mostly vector_hashing = true; 153 module_param(vector_hashing, bool, S_IRUGO); 154 155 bool __read_mostly enable_vmware_backdoor = false; 156 module_param(enable_vmware_backdoor, bool, S_IRUGO); 157 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 158 159 static bool __read_mostly force_emulation_prefix = false; 160 module_param(force_emulation_prefix, bool, S_IRUGO); 161 162 int __read_mostly pi_inject_timer = -1; 163 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); 164 165 #define KVM_NR_SHARED_MSRS 16 166 167 struct kvm_shared_msrs_global { 168 int nr; 169 u32 msrs[KVM_NR_SHARED_MSRS]; 170 }; 171 172 struct kvm_shared_msrs { 173 struct user_return_notifier urn; 174 bool registered; 175 struct kvm_shared_msr_values { 176 u64 host; 177 u64 curr; 178 } values[KVM_NR_SHARED_MSRS]; 179 }; 180 181 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 182 static struct kvm_shared_msrs __percpu *shared_msrs; 183 184 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 185 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 186 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 187 | XFEATURE_MASK_PKRU) 188 189 u64 __read_mostly host_efer; 190 EXPORT_SYMBOL_GPL(host_efer); 191 192 static u64 __read_mostly host_xss; 193 u64 __read_mostly supported_xss; 194 EXPORT_SYMBOL_GPL(supported_xss); 195 196 struct kvm_stats_debugfs_item debugfs_entries[] = { 197 { "pf_fixed", VCPU_STAT(pf_fixed) }, 198 { "pf_guest", VCPU_STAT(pf_guest) }, 199 { "tlb_flush", VCPU_STAT(tlb_flush) }, 200 { "invlpg", VCPU_STAT(invlpg) }, 201 { "exits", VCPU_STAT(exits) }, 202 { "io_exits", VCPU_STAT(io_exits) }, 203 { "mmio_exits", VCPU_STAT(mmio_exits) }, 204 { "signal_exits", VCPU_STAT(signal_exits) }, 205 { "irq_window", VCPU_STAT(irq_window_exits) }, 206 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 207 { "halt_exits", VCPU_STAT(halt_exits) }, 208 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 209 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 210 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, 211 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 212 { "hypercalls", VCPU_STAT(hypercalls) }, 213 { "request_irq", VCPU_STAT(request_irq_exits) }, 214 { "irq_exits", VCPU_STAT(irq_exits) }, 215 { "host_state_reload", VCPU_STAT(host_state_reload) }, 216 { "fpu_reload", VCPU_STAT(fpu_reload) }, 217 { "insn_emulation", VCPU_STAT(insn_emulation) }, 218 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 219 { "irq_injections", VCPU_STAT(irq_injections) }, 220 { "nmi_injections", VCPU_STAT(nmi_injections) }, 221 { "req_event", VCPU_STAT(req_event) }, 222 { "l1d_flush", VCPU_STAT(l1d_flush) }, 223 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 224 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 225 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 226 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 227 { "mmu_flooded", VM_STAT(mmu_flooded) }, 228 { "mmu_recycled", VM_STAT(mmu_recycled) }, 229 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 230 { "mmu_unsync", VM_STAT(mmu_unsync) }, 231 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 232 { "largepages", VM_STAT(lpages, .mode = 0444) }, 233 { "nx_largepages_splitted", VM_STAT(nx_lpage_splits, .mode = 0444) }, 234 { "max_mmu_page_hash_collisions", 235 VM_STAT(max_mmu_page_hash_collisions) }, 236 { NULL } 237 }; 238 239 u64 __read_mostly host_xcr0; 240 u64 __read_mostly supported_xcr0; 241 EXPORT_SYMBOL_GPL(supported_xcr0); 242 243 struct kmem_cache *x86_fpu_cache; 244 EXPORT_SYMBOL_GPL(x86_fpu_cache); 245 246 static struct kmem_cache *x86_emulator_cache; 247 248 static struct kmem_cache *kvm_alloc_emulator_cache(void) 249 { 250 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); 251 unsigned int size = sizeof(struct x86_emulate_ctxt); 252 253 return kmem_cache_create_usercopy("x86_emulator", size, 254 __alignof__(struct x86_emulate_ctxt), 255 SLAB_ACCOUNT, useroffset, 256 size - useroffset, NULL); 257 } 258 259 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 260 261 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 262 { 263 int i; 264 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 265 vcpu->arch.apf.gfns[i] = ~0; 266 } 267 268 static void kvm_on_user_return(struct user_return_notifier *urn) 269 { 270 unsigned slot; 271 struct kvm_shared_msrs *locals 272 = container_of(urn, struct kvm_shared_msrs, urn); 273 struct kvm_shared_msr_values *values; 274 unsigned long flags; 275 276 /* 277 * Disabling irqs at this point since the following code could be 278 * interrupted and executed through kvm_arch_hardware_disable() 279 */ 280 local_irq_save(flags); 281 if (locals->registered) { 282 locals->registered = false; 283 user_return_notifier_unregister(urn); 284 } 285 local_irq_restore(flags); 286 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 287 values = &locals->values[slot]; 288 if (values->host != values->curr) { 289 wrmsrl(shared_msrs_global.msrs[slot], values->host); 290 values->curr = values->host; 291 } 292 } 293 } 294 295 void kvm_define_shared_msr(unsigned slot, u32 msr) 296 { 297 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 298 shared_msrs_global.msrs[slot] = msr; 299 if (slot >= shared_msrs_global.nr) 300 shared_msrs_global.nr = slot + 1; 301 } 302 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 303 304 static void kvm_shared_msr_cpu_online(void) 305 { 306 unsigned int cpu = smp_processor_id(); 307 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 308 u64 value; 309 int i; 310 311 for (i = 0; i < shared_msrs_global.nr; ++i) { 312 rdmsrl_safe(shared_msrs_global.msrs[i], &value); 313 smsr->values[i].host = value; 314 smsr->values[i].curr = value; 315 } 316 } 317 318 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 319 { 320 unsigned int cpu = smp_processor_id(); 321 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 322 int err; 323 324 value = (value & mask) | (smsr->values[slot].host & ~mask); 325 if (value == smsr->values[slot].curr) 326 return 0; 327 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 328 if (err) 329 return 1; 330 331 smsr->values[slot].curr = value; 332 if (!smsr->registered) { 333 smsr->urn.on_user_return = kvm_on_user_return; 334 user_return_notifier_register(&smsr->urn); 335 smsr->registered = true; 336 } 337 return 0; 338 } 339 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 340 341 static void drop_user_return_notifiers(void) 342 { 343 unsigned int cpu = smp_processor_id(); 344 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 345 346 if (smsr->registered) 347 kvm_on_user_return(&smsr->urn); 348 } 349 350 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 351 { 352 return vcpu->arch.apic_base; 353 } 354 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 355 356 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 357 { 358 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 359 } 360 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 361 362 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 363 { 364 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 365 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 366 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | 367 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 368 369 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 370 return 1; 371 if (!msr_info->host_initiated) { 372 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 373 return 1; 374 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 375 return 1; 376 } 377 378 kvm_lapic_set_base(vcpu, msr_info->data); 379 kvm_recalculate_apic_map(vcpu->kvm); 380 return 0; 381 } 382 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 383 384 asmlinkage __visible void kvm_spurious_fault(void) 385 { 386 /* Fault while not rebooting. We want the trace. */ 387 BUG_ON(!kvm_rebooting); 388 } 389 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 390 391 #define EXCPT_BENIGN 0 392 #define EXCPT_CONTRIBUTORY 1 393 #define EXCPT_PF 2 394 395 static int exception_class(int vector) 396 { 397 switch (vector) { 398 case PF_VECTOR: 399 return EXCPT_PF; 400 case DE_VECTOR: 401 case TS_VECTOR: 402 case NP_VECTOR: 403 case SS_VECTOR: 404 case GP_VECTOR: 405 return EXCPT_CONTRIBUTORY; 406 default: 407 break; 408 } 409 return EXCPT_BENIGN; 410 } 411 412 #define EXCPT_FAULT 0 413 #define EXCPT_TRAP 1 414 #define EXCPT_ABORT 2 415 #define EXCPT_INTERRUPT 3 416 417 static int exception_type(int vector) 418 { 419 unsigned int mask; 420 421 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 422 return EXCPT_INTERRUPT; 423 424 mask = 1 << vector; 425 426 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 427 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 428 return EXCPT_TRAP; 429 430 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 431 return EXCPT_ABORT; 432 433 /* Reserved exceptions will result in fault */ 434 return EXCPT_FAULT; 435 } 436 437 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 438 { 439 unsigned nr = vcpu->arch.exception.nr; 440 bool has_payload = vcpu->arch.exception.has_payload; 441 unsigned long payload = vcpu->arch.exception.payload; 442 443 if (!has_payload) 444 return; 445 446 switch (nr) { 447 case DB_VECTOR: 448 /* 449 * "Certain debug exceptions may clear bit 0-3. The 450 * remaining contents of the DR6 register are never 451 * cleared by the processor". 452 */ 453 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 454 /* 455 * DR6.RTM is set by all #DB exceptions that don't clear it. 456 */ 457 vcpu->arch.dr6 |= DR6_RTM; 458 vcpu->arch.dr6 |= payload; 459 /* 460 * Bit 16 should be set in the payload whenever the #DB 461 * exception should clear DR6.RTM. This makes the payload 462 * compatible with the pending debug exceptions under VMX. 463 * Though not currently documented in the SDM, this also 464 * makes the payload compatible with the exit qualification 465 * for #DB exceptions under VMX. 466 */ 467 vcpu->arch.dr6 ^= payload & DR6_RTM; 468 469 /* 470 * The #DB payload is defined as compatible with the 'pending 471 * debug exceptions' field under VMX, not DR6. While bit 12 is 472 * defined in the 'pending debug exceptions' field (enabled 473 * breakpoint), it is reserved and must be zero in DR6. 474 */ 475 vcpu->arch.dr6 &= ~BIT(12); 476 break; 477 case PF_VECTOR: 478 vcpu->arch.cr2 = payload; 479 break; 480 } 481 482 vcpu->arch.exception.has_payload = false; 483 vcpu->arch.exception.payload = 0; 484 } 485 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 486 487 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 488 unsigned nr, bool has_error, u32 error_code, 489 bool has_payload, unsigned long payload, bool reinject) 490 { 491 u32 prev_nr; 492 int class1, class2; 493 494 kvm_make_request(KVM_REQ_EVENT, vcpu); 495 496 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 497 queue: 498 if (has_error && !is_protmode(vcpu)) 499 has_error = false; 500 if (reinject) { 501 /* 502 * On vmentry, vcpu->arch.exception.pending is only 503 * true if an event injection was blocked by 504 * nested_run_pending. In that case, however, 505 * vcpu_enter_guest requests an immediate exit, 506 * and the guest shouldn't proceed far enough to 507 * need reinjection. 508 */ 509 WARN_ON_ONCE(vcpu->arch.exception.pending); 510 vcpu->arch.exception.injected = true; 511 if (WARN_ON_ONCE(has_payload)) { 512 /* 513 * A reinjected event has already 514 * delivered its payload. 515 */ 516 has_payload = false; 517 payload = 0; 518 } 519 } else { 520 vcpu->arch.exception.pending = true; 521 vcpu->arch.exception.injected = false; 522 } 523 vcpu->arch.exception.has_error_code = has_error; 524 vcpu->arch.exception.nr = nr; 525 vcpu->arch.exception.error_code = error_code; 526 vcpu->arch.exception.has_payload = has_payload; 527 vcpu->arch.exception.payload = payload; 528 if (!is_guest_mode(vcpu)) 529 kvm_deliver_exception_payload(vcpu); 530 return; 531 } 532 533 /* to check exception */ 534 prev_nr = vcpu->arch.exception.nr; 535 if (prev_nr == DF_VECTOR) { 536 /* triple fault -> shutdown */ 537 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 538 return; 539 } 540 class1 = exception_class(prev_nr); 541 class2 = exception_class(nr); 542 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 543 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 544 /* 545 * Generate double fault per SDM Table 5-5. Set 546 * exception.pending = true so that the double fault 547 * can trigger a nested vmexit. 548 */ 549 vcpu->arch.exception.pending = true; 550 vcpu->arch.exception.injected = false; 551 vcpu->arch.exception.has_error_code = true; 552 vcpu->arch.exception.nr = DF_VECTOR; 553 vcpu->arch.exception.error_code = 0; 554 vcpu->arch.exception.has_payload = false; 555 vcpu->arch.exception.payload = 0; 556 } else 557 /* replace previous exception with a new one in a hope 558 that instruction re-execution will regenerate lost 559 exception */ 560 goto queue; 561 } 562 563 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 564 { 565 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 566 } 567 EXPORT_SYMBOL_GPL(kvm_queue_exception); 568 569 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 570 { 571 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 572 } 573 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 574 575 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 576 unsigned long payload) 577 { 578 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 579 } 580 581 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 582 u32 error_code, unsigned long payload) 583 { 584 kvm_multiple_exception(vcpu, nr, true, error_code, 585 true, payload, false); 586 } 587 588 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 589 { 590 if (err) 591 kvm_inject_gp(vcpu, 0); 592 else 593 return kvm_skip_emulated_instruction(vcpu); 594 595 return 1; 596 } 597 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 598 599 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 600 { 601 ++vcpu->stat.pf_guest; 602 vcpu->arch.exception.nested_apf = 603 is_guest_mode(vcpu) && fault->async_page_fault; 604 if (vcpu->arch.exception.nested_apf) { 605 vcpu->arch.apf.nested_apf_token = fault->address; 606 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 607 } else { 608 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 609 fault->address); 610 } 611 } 612 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 613 614 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 615 { 616 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 617 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 618 else 619 vcpu->arch.mmu->inject_page_fault(vcpu, fault); 620 621 return fault->nested_page_fault; 622 } 623 624 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 625 { 626 atomic_inc(&vcpu->arch.nmi_queued); 627 kvm_make_request(KVM_REQ_NMI, vcpu); 628 } 629 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 630 631 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 632 { 633 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 634 } 635 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 636 637 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 638 { 639 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 640 } 641 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 642 643 /* 644 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 645 * a #GP and return false. 646 */ 647 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 648 { 649 if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl) 650 return true; 651 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 652 return false; 653 } 654 EXPORT_SYMBOL_GPL(kvm_require_cpl); 655 656 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 657 { 658 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 659 return true; 660 661 kvm_queue_exception(vcpu, UD_VECTOR); 662 return false; 663 } 664 EXPORT_SYMBOL_GPL(kvm_require_dr); 665 666 /* 667 * This function will be used to read from the physical memory of the currently 668 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 669 * can read from guest physical or from the guest's guest physical memory. 670 */ 671 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 672 gfn_t ngfn, void *data, int offset, int len, 673 u32 access) 674 { 675 struct x86_exception exception; 676 gfn_t real_gfn; 677 gpa_t ngpa; 678 679 ngpa = gfn_to_gpa(ngfn); 680 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 681 if (real_gfn == UNMAPPED_GVA) 682 return -EFAULT; 683 684 real_gfn = gpa_to_gfn(real_gfn); 685 686 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 687 } 688 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 689 690 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 691 void *data, int offset, int len, u32 access) 692 { 693 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 694 data, offset, len, access); 695 } 696 697 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) 698 { 699 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) | 700 rsvd_bits(1, 2); 701 } 702 703 /* 704 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. 705 */ 706 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 707 { 708 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 709 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 710 int i; 711 int ret; 712 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 713 714 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 715 offset * sizeof(u64), sizeof(pdpte), 716 PFERR_USER_MASK|PFERR_WRITE_MASK); 717 if (ret < 0) { 718 ret = 0; 719 goto out; 720 } 721 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 722 if ((pdpte[i] & PT_PRESENT_MASK) && 723 (pdpte[i] & pdptr_rsvd_bits(vcpu))) { 724 ret = 0; 725 goto out; 726 } 727 } 728 ret = 1; 729 730 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 731 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 732 733 out: 734 735 return ret; 736 } 737 EXPORT_SYMBOL_GPL(load_pdptrs); 738 739 bool pdptrs_changed(struct kvm_vcpu *vcpu) 740 { 741 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 742 int offset; 743 gfn_t gfn; 744 int r; 745 746 if (!is_pae_paging(vcpu)) 747 return false; 748 749 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR)) 750 return true; 751 752 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; 753 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); 754 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 755 PFERR_USER_MASK | PFERR_WRITE_MASK); 756 if (r < 0) 757 return true; 758 759 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 760 } 761 EXPORT_SYMBOL_GPL(pdptrs_changed); 762 763 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 764 { 765 unsigned long old_cr0 = kvm_read_cr0(vcpu); 766 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 767 768 cr0 |= X86_CR0_ET; 769 770 #ifdef CONFIG_X86_64 771 if (cr0 & 0xffffffff00000000UL) 772 return 1; 773 #endif 774 775 cr0 &= ~CR0_RESERVED_BITS; 776 777 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 778 return 1; 779 780 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 781 return 1; 782 783 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 784 #ifdef CONFIG_X86_64 785 if ((vcpu->arch.efer & EFER_LME)) { 786 int cs_db, cs_l; 787 788 if (!is_pae(vcpu)) 789 return 1; 790 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 791 if (cs_l) 792 return 1; 793 } else 794 #endif 795 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 796 kvm_read_cr3(vcpu))) 797 return 1; 798 } 799 800 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 801 return 1; 802 803 kvm_x86_ops.set_cr0(vcpu, cr0); 804 805 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 806 kvm_clear_async_pf_completion_queue(vcpu); 807 kvm_async_pf_hash_reset(vcpu); 808 } 809 810 if ((cr0 ^ old_cr0) & update_bits) 811 kvm_mmu_reset_context(vcpu); 812 813 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 814 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 815 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 816 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 817 818 return 0; 819 } 820 EXPORT_SYMBOL_GPL(kvm_set_cr0); 821 822 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 823 { 824 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 825 } 826 EXPORT_SYMBOL_GPL(kvm_lmsw); 827 828 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) 829 { 830 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 831 832 if (vcpu->arch.xcr0 != host_xcr0) 833 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 834 835 if (vcpu->arch.xsaves_enabled && 836 vcpu->arch.ia32_xss != host_xss) 837 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 838 } 839 } 840 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); 841 842 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) 843 { 844 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 845 846 if (vcpu->arch.xcr0 != host_xcr0) 847 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 848 849 if (vcpu->arch.xsaves_enabled && 850 vcpu->arch.ia32_xss != host_xss) 851 wrmsrl(MSR_IA32_XSS, host_xss); 852 } 853 854 } 855 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); 856 857 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 858 { 859 u64 xcr0 = xcr; 860 u64 old_xcr0 = vcpu->arch.xcr0; 861 u64 valid_bits; 862 863 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 864 if (index != XCR_XFEATURE_ENABLED_MASK) 865 return 1; 866 if (!(xcr0 & XFEATURE_MASK_FP)) 867 return 1; 868 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 869 return 1; 870 871 /* 872 * Do not allow the guest to set bits that we do not support 873 * saving. However, xcr0 bit 0 is always set, even if the 874 * emulated CPU does not support XSAVE (see fx_init). 875 */ 876 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 877 if (xcr0 & ~valid_bits) 878 return 1; 879 880 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 881 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 882 return 1; 883 884 if (xcr0 & XFEATURE_MASK_AVX512) { 885 if (!(xcr0 & XFEATURE_MASK_YMM)) 886 return 1; 887 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 888 return 1; 889 } 890 vcpu->arch.xcr0 = xcr0; 891 892 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 893 kvm_update_cpuid(vcpu); 894 return 0; 895 } 896 897 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 898 { 899 if (kvm_x86_ops.get_cpl(vcpu) != 0 || 900 __kvm_set_xcr(vcpu, index, xcr)) { 901 kvm_inject_gp(vcpu, 0); 902 return 1; 903 } 904 return 0; 905 } 906 EXPORT_SYMBOL_GPL(kvm_set_xcr); 907 908 #define __cr4_reserved_bits(__cpu_has, __c) \ 909 ({ \ 910 u64 __reserved_bits = CR4_RESERVED_BITS; \ 911 \ 912 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \ 913 __reserved_bits |= X86_CR4_OSXSAVE; \ 914 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \ 915 __reserved_bits |= X86_CR4_SMEP; \ 916 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \ 917 __reserved_bits |= X86_CR4_SMAP; \ 918 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \ 919 __reserved_bits |= X86_CR4_FSGSBASE; \ 920 if (!__cpu_has(__c, X86_FEATURE_PKU)) \ 921 __reserved_bits |= X86_CR4_PKE; \ 922 if (!__cpu_has(__c, X86_FEATURE_LA57)) \ 923 __reserved_bits |= X86_CR4_LA57; \ 924 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \ 925 __reserved_bits |= X86_CR4_UMIP; \ 926 __reserved_bits; \ 927 }) 928 929 static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 930 { 931 if (cr4 & cr4_reserved_bits) 932 return -EINVAL; 933 934 if (cr4 & __cr4_reserved_bits(guest_cpuid_has, vcpu)) 935 return -EINVAL; 936 937 return 0; 938 } 939 940 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 941 { 942 unsigned long old_cr4 = kvm_read_cr4(vcpu); 943 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 944 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 945 946 if (kvm_valid_cr4(vcpu, cr4)) 947 return 1; 948 949 if (is_long_mode(vcpu)) { 950 if (!(cr4 & X86_CR4_PAE)) 951 return 1; 952 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 953 && ((cr4 ^ old_cr4) & pdptr_bits) 954 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 955 kvm_read_cr3(vcpu))) 956 return 1; 957 958 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 959 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 960 return 1; 961 962 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 963 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 964 return 1; 965 } 966 967 if (kvm_x86_ops.set_cr4(vcpu, cr4)) 968 return 1; 969 970 if (((cr4 ^ old_cr4) & pdptr_bits) || 971 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 972 kvm_mmu_reset_context(vcpu); 973 974 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 975 kvm_update_cpuid(vcpu); 976 977 return 0; 978 } 979 EXPORT_SYMBOL_GPL(kvm_set_cr4); 980 981 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 982 { 983 bool skip_tlb_flush = false; 984 #ifdef CONFIG_X86_64 985 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 986 987 if (pcid_enabled) { 988 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 989 cr3 &= ~X86_CR3_PCID_NOFLUSH; 990 } 991 #endif 992 993 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 994 if (!skip_tlb_flush) { 995 kvm_mmu_sync_roots(vcpu); 996 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 997 } 998 return 0; 999 } 1000 1001 if (is_long_mode(vcpu) && 1002 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63))) 1003 return 1; 1004 else if (is_pae_paging(vcpu) && 1005 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 1006 return 1; 1007 1008 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush); 1009 vcpu->arch.cr3 = cr3; 1010 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 1011 1012 return 0; 1013 } 1014 EXPORT_SYMBOL_GPL(kvm_set_cr3); 1015 1016 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 1017 { 1018 if (cr8 & CR8_RESERVED_BITS) 1019 return 1; 1020 if (lapic_in_kernel(vcpu)) 1021 kvm_lapic_set_tpr(vcpu, cr8); 1022 else 1023 vcpu->arch.cr8 = cr8; 1024 return 0; 1025 } 1026 EXPORT_SYMBOL_GPL(kvm_set_cr8); 1027 1028 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 1029 { 1030 if (lapic_in_kernel(vcpu)) 1031 return kvm_lapic_get_cr8(vcpu); 1032 else 1033 return vcpu->arch.cr8; 1034 } 1035 EXPORT_SYMBOL_GPL(kvm_get_cr8); 1036 1037 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 1038 { 1039 int i; 1040 1041 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1042 for (i = 0; i < KVM_NR_DB_REGS; i++) 1043 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1044 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 1045 } 1046 } 1047 1048 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 1049 { 1050 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1051 kvm_x86_ops.set_dr6(vcpu, vcpu->arch.dr6); 1052 } 1053 1054 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 1055 { 1056 unsigned long dr7; 1057 1058 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1059 dr7 = vcpu->arch.guest_debug_dr7; 1060 else 1061 dr7 = vcpu->arch.dr7; 1062 kvm_x86_ops.set_dr7(vcpu, dr7); 1063 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1064 if (dr7 & DR7_BP_EN_MASK) 1065 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1066 } 1067 1068 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1069 { 1070 u64 fixed = DR6_FIXED_1; 1071 1072 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1073 fixed |= DR6_RTM; 1074 return fixed; 1075 } 1076 1077 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1078 { 1079 size_t size = ARRAY_SIZE(vcpu->arch.db); 1080 1081 switch (dr) { 1082 case 0 ... 3: 1083 vcpu->arch.db[array_index_nospec(dr, size)] = val; 1084 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1085 vcpu->arch.eff_db[dr] = val; 1086 break; 1087 case 4: 1088 /* fall through */ 1089 case 6: 1090 if (val & 0xffffffff00000000ULL) 1091 return -1; /* #GP */ 1092 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1093 kvm_update_dr6(vcpu); 1094 break; 1095 case 5: 1096 /* fall through */ 1097 default: /* 7 */ 1098 if (!kvm_dr7_valid(val)) 1099 return -1; /* #GP */ 1100 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1101 kvm_update_dr7(vcpu); 1102 break; 1103 } 1104 1105 return 0; 1106 } 1107 1108 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1109 { 1110 if (__kvm_set_dr(vcpu, dr, val)) { 1111 kvm_inject_gp(vcpu, 0); 1112 return 1; 1113 } 1114 return 0; 1115 } 1116 EXPORT_SYMBOL_GPL(kvm_set_dr); 1117 1118 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1119 { 1120 size_t size = ARRAY_SIZE(vcpu->arch.db); 1121 1122 switch (dr) { 1123 case 0 ... 3: 1124 *val = vcpu->arch.db[array_index_nospec(dr, size)]; 1125 break; 1126 case 4: 1127 /* fall through */ 1128 case 6: 1129 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1130 *val = vcpu->arch.dr6; 1131 else 1132 *val = kvm_x86_ops.get_dr6(vcpu); 1133 break; 1134 case 5: 1135 /* fall through */ 1136 default: /* 7 */ 1137 *val = vcpu->arch.dr7; 1138 break; 1139 } 1140 return 0; 1141 } 1142 EXPORT_SYMBOL_GPL(kvm_get_dr); 1143 1144 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 1145 { 1146 u32 ecx = kvm_rcx_read(vcpu); 1147 u64 data; 1148 int err; 1149 1150 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 1151 if (err) 1152 return err; 1153 kvm_rax_write(vcpu, (u32)data); 1154 kvm_rdx_write(vcpu, data >> 32); 1155 return err; 1156 } 1157 EXPORT_SYMBOL_GPL(kvm_rdpmc); 1158 1159 /* 1160 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1161 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1162 * 1163 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) 1164 * extract the supported MSRs from the related const lists. 1165 * msrs_to_save is selected from the msrs_to_save_all to reflect the 1166 * capabilities of the host cpu. This capabilities test skips MSRs that are 1167 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs 1168 * may depend on host virtualization features rather than host cpu features. 1169 */ 1170 1171 static const u32 msrs_to_save_all[] = { 1172 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1173 MSR_STAR, 1174 #ifdef CONFIG_X86_64 1175 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1176 #endif 1177 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1178 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1179 MSR_IA32_SPEC_CTRL, 1180 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1181 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1182 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1183 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1184 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1185 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1186 MSR_IA32_UMWAIT_CONTROL, 1187 1188 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, 1189 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, 1190 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, 1191 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 1192 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, 1193 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, 1194 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, 1195 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, 1196 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, 1197 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, 1198 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, 1199 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, 1200 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, 1201 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, 1202 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, 1203 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, 1204 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, 1205 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, 1206 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, 1207 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, 1208 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, 1209 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, 1210 }; 1211 1212 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; 1213 static unsigned num_msrs_to_save; 1214 1215 static const u32 emulated_msrs_all[] = { 1216 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1217 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1218 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1219 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1220 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1221 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1222 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1223 HV_X64_MSR_RESET, 1224 HV_X64_MSR_VP_INDEX, 1225 HV_X64_MSR_VP_RUNTIME, 1226 HV_X64_MSR_SCONTROL, 1227 HV_X64_MSR_STIMER0_CONFIG, 1228 HV_X64_MSR_VP_ASSIST_PAGE, 1229 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1230 HV_X64_MSR_TSC_EMULATION_STATUS, 1231 1232 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1233 MSR_KVM_PV_EOI_EN, 1234 1235 MSR_IA32_TSC_ADJUST, 1236 MSR_IA32_TSCDEADLINE, 1237 MSR_IA32_ARCH_CAPABILITIES, 1238 MSR_IA32_MISC_ENABLE, 1239 MSR_IA32_MCG_STATUS, 1240 MSR_IA32_MCG_CTL, 1241 MSR_IA32_MCG_EXT_CTL, 1242 MSR_IA32_SMBASE, 1243 MSR_SMI_COUNT, 1244 MSR_PLATFORM_INFO, 1245 MSR_MISC_FEATURES_ENABLES, 1246 MSR_AMD64_VIRT_SPEC_CTRL, 1247 MSR_IA32_POWER_CTL, 1248 MSR_IA32_UCODE_REV, 1249 1250 /* 1251 * The following list leaves out MSRs whose values are determined 1252 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. 1253 * We always support the "true" VMX control MSRs, even if the host 1254 * processor does not, so I am putting these registers here rather 1255 * than in msrs_to_save_all. 1256 */ 1257 MSR_IA32_VMX_BASIC, 1258 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1259 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1260 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1261 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1262 MSR_IA32_VMX_MISC, 1263 MSR_IA32_VMX_CR0_FIXED0, 1264 MSR_IA32_VMX_CR4_FIXED0, 1265 MSR_IA32_VMX_VMCS_ENUM, 1266 MSR_IA32_VMX_PROCBASED_CTLS2, 1267 MSR_IA32_VMX_EPT_VPID_CAP, 1268 MSR_IA32_VMX_VMFUNC, 1269 1270 MSR_K7_HWCR, 1271 MSR_KVM_POLL_CONTROL, 1272 }; 1273 1274 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; 1275 static unsigned num_emulated_msrs; 1276 1277 /* 1278 * List of msr numbers which are used to expose MSR-based features that 1279 * can be used by a hypervisor to validate requested CPU features. 1280 */ 1281 static const u32 msr_based_features_all[] = { 1282 MSR_IA32_VMX_BASIC, 1283 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1284 MSR_IA32_VMX_PINBASED_CTLS, 1285 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1286 MSR_IA32_VMX_PROCBASED_CTLS, 1287 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1288 MSR_IA32_VMX_EXIT_CTLS, 1289 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1290 MSR_IA32_VMX_ENTRY_CTLS, 1291 MSR_IA32_VMX_MISC, 1292 MSR_IA32_VMX_CR0_FIXED0, 1293 MSR_IA32_VMX_CR0_FIXED1, 1294 MSR_IA32_VMX_CR4_FIXED0, 1295 MSR_IA32_VMX_CR4_FIXED1, 1296 MSR_IA32_VMX_VMCS_ENUM, 1297 MSR_IA32_VMX_PROCBASED_CTLS2, 1298 MSR_IA32_VMX_EPT_VPID_CAP, 1299 MSR_IA32_VMX_VMFUNC, 1300 1301 MSR_F10H_DECFG, 1302 MSR_IA32_UCODE_REV, 1303 MSR_IA32_ARCH_CAPABILITIES, 1304 }; 1305 1306 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; 1307 static unsigned int num_msr_based_features; 1308 1309 static u64 kvm_get_arch_capabilities(void) 1310 { 1311 u64 data = 0; 1312 1313 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1314 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); 1315 1316 /* 1317 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that 1318 * the nested hypervisor runs with NX huge pages. If it is not, 1319 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other 1320 * L1 guests, so it need not worry about its own (L2) guests. 1321 */ 1322 data |= ARCH_CAP_PSCHANGE_MC_NO; 1323 1324 /* 1325 * If we're doing cache flushes (either "always" or "cond") 1326 * we will do one whenever the guest does a vmlaunch/vmresume. 1327 * If an outer hypervisor is doing the cache flush for us 1328 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1329 * capability to the guest too, and if EPT is disabled we're not 1330 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1331 * require a nested hypervisor to do a flush of its own. 1332 */ 1333 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1334 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1335 1336 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) 1337 data |= ARCH_CAP_RDCL_NO; 1338 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1339 data |= ARCH_CAP_SSB_NO; 1340 if (!boot_cpu_has_bug(X86_BUG_MDS)) 1341 data |= ARCH_CAP_MDS_NO; 1342 1343 /* 1344 * On TAA affected systems: 1345 * - nothing to do if TSX is disabled on the host. 1346 * - we emulate TSX_CTRL if present on the host. 1347 * This lets the guest use VERW to clear CPU buffers. 1348 */ 1349 if (!boot_cpu_has(X86_FEATURE_RTM)) 1350 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR); 1351 else if (!boot_cpu_has_bug(X86_BUG_TAA)) 1352 data |= ARCH_CAP_TAA_NO; 1353 1354 return data; 1355 } 1356 1357 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1358 { 1359 switch (msr->index) { 1360 case MSR_IA32_ARCH_CAPABILITIES: 1361 msr->data = kvm_get_arch_capabilities(); 1362 break; 1363 case MSR_IA32_UCODE_REV: 1364 rdmsrl_safe(msr->index, &msr->data); 1365 break; 1366 default: 1367 if (kvm_x86_ops.get_msr_feature(msr)) 1368 return 1; 1369 } 1370 return 0; 1371 } 1372 1373 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1374 { 1375 struct kvm_msr_entry msr; 1376 int r; 1377 1378 msr.index = index; 1379 r = kvm_get_msr_feature(&msr); 1380 if (r) 1381 return r; 1382 1383 *data = msr.data; 1384 1385 return 0; 1386 } 1387 1388 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1389 { 1390 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1391 return false; 1392 1393 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1394 return false; 1395 1396 if (efer & (EFER_LME | EFER_LMA) && 1397 !guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1398 return false; 1399 1400 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) 1401 return false; 1402 1403 return true; 1404 1405 } 1406 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1407 { 1408 if (efer & efer_reserved_bits) 1409 return false; 1410 1411 return __kvm_valid_efer(vcpu, efer); 1412 } 1413 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1414 1415 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1416 { 1417 u64 old_efer = vcpu->arch.efer; 1418 u64 efer = msr_info->data; 1419 1420 if (efer & efer_reserved_bits) 1421 return 1; 1422 1423 if (!msr_info->host_initiated) { 1424 if (!__kvm_valid_efer(vcpu, efer)) 1425 return 1; 1426 1427 if (is_paging(vcpu) && 1428 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1429 return 1; 1430 } 1431 1432 efer &= ~EFER_LMA; 1433 efer |= vcpu->arch.efer & EFER_LMA; 1434 1435 kvm_x86_ops.set_efer(vcpu, efer); 1436 1437 /* Update reserved bits */ 1438 if ((efer ^ old_efer) & EFER_NX) 1439 kvm_mmu_reset_context(vcpu); 1440 1441 return 0; 1442 } 1443 1444 void kvm_enable_efer_bits(u64 mask) 1445 { 1446 efer_reserved_bits &= ~mask; 1447 } 1448 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1449 1450 /* 1451 * Write @data into the MSR specified by @index. Select MSR specific fault 1452 * checks are bypassed if @host_initiated is %true. 1453 * Returns 0 on success, non-0 otherwise. 1454 * Assumes vcpu_load() was already called. 1455 */ 1456 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, 1457 bool host_initiated) 1458 { 1459 struct msr_data msr; 1460 1461 switch (index) { 1462 case MSR_FS_BASE: 1463 case MSR_GS_BASE: 1464 case MSR_KERNEL_GS_BASE: 1465 case MSR_CSTAR: 1466 case MSR_LSTAR: 1467 if (is_noncanonical_address(data, vcpu)) 1468 return 1; 1469 break; 1470 case MSR_IA32_SYSENTER_EIP: 1471 case MSR_IA32_SYSENTER_ESP: 1472 /* 1473 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1474 * non-canonical address is written on Intel but not on 1475 * AMD (which ignores the top 32-bits, because it does 1476 * not implement 64-bit SYSENTER). 1477 * 1478 * 64-bit code should hence be able to write a non-canonical 1479 * value on AMD. Making the address canonical ensures that 1480 * vmentry does not fail on Intel after writing a non-canonical 1481 * value, and that something deterministic happens if the guest 1482 * invokes 64-bit SYSENTER. 1483 */ 1484 data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); 1485 } 1486 1487 msr.data = data; 1488 msr.index = index; 1489 msr.host_initiated = host_initiated; 1490 1491 return kvm_x86_ops.set_msr(vcpu, &msr); 1492 } 1493 1494 /* 1495 * Read the MSR specified by @index into @data. Select MSR specific fault 1496 * checks are bypassed if @host_initiated is %true. 1497 * Returns 0 on success, non-0 otherwise. 1498 * Assumes vcpu_load() was already called. 1499 */ 1500 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1501 bool host_initiated) 1502 { 1503 struct msr_data msr; 1504 int ret; 1505 1506 msr.index = index; 1507 msr.host_initiated = host_initiated; 1508 1509 ret = kvm_x86_ops.get_msr(vcpu, &msr); 1510 if (!ret) 1511 *data = msr.data; 1512 return ret; 1513 } 1514 1515 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1516 { 1517 return __kvm_get_msr(vcpu, index, data, false); 1518 } 1519 EXPORT_SYMBOL_GPL(kvm_get_msr); 1520 1521 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) 1522 { 1523 return __kvm_set_msr(vcpu, index, data, false); 1524 } 1525 EXPORT_SYMBOL_GPL(kvm_set_msr); 1526 1527 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) 1528 { 1529 u32 ecx = kvm_rcx_read(vcpu); 1530 u64 data; 1531 1532 if (kvm_get_msr(vcpu, ecx, &data)) { 1533 trace_kvm_msr_read_ex(ecx); 1534 kvm_inject_gp(vcpu, 0); 1535 return 1; 1536 } 1537 1538 trace_kvm_msr_read(ecx, data); 1539 1540 kvm_rax_write(vcpu, data & -1u); 1541 kvm_rdx_write(vcpu, (data >> 32) & -1u); 1542 return kvm_skip_emulated_instruction(vcpu); 1543 } 1544 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); 1545 1546 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) 1547 { 1548 u32 ecx = kvm_rcx_read(vcpu); 1549 u64 data = kvm_read_edx_eax(vcpu); 1550 1551 if (kvm_set_msr(vcpu, ecx, data)) { 1552 trace_kvm_msr_write_ex(ecx, data); 1553 kvm_inject_gp(vcpu, 0); 1554 return 1; 1555 } 1556 1557 trace_kvm_msr_write(ecx, data); 1558 return kvm_skip_emulated_instruction(vcpu); 1559 } 1560 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); 1561 1562 /* 1563 * The fast path for frequent and performance sensitive wrmsr emulation, 1564 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces 1565 * the latency of virtual IPI by avoiding the expensive bits of transitioning 1566 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the 1567 * other cases which must be called after interrupts are enabled on the host. 1568 */ 1569 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) 1570 { 1571 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) 1572 return 1; 1573 1574 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && 1575 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && 1576 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && 1577 ((u32)(data >> 32) != X2APIC_BROADCAST)) { 1578 1579 data &= ~(1 << 12); 1580 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); 1581 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); 1582 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); 1583 trace_kvm_apic_write(APIC_ICR, (u32)data); 1584 return 0; 1585 } 1586 1587 return 1; 1588 } 1589 1590 enum exit_fastpath_completion handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) 1591 { 1592 u32 msr = kvm_rcx_read(vcpu); 1593 u64 data; 1594 int ret = 0; 1595 1596 switch (msr) { 1597 case APIC_BASE_MSR + (APIC_ICR >> 4): 1598 data = kvm_read_edx_eax(vcpu); 1599 ret = handle_fastpath_set_x2apic_icr_irqoff(vcpu, data); 1600 break; 1601 default: 1602 return EXIT_FASTPATH_NONE; 1603 } 1604 1605 if (!ret) { 1606 trace_kvm_msr_write(msr, data); 1607 return EXIT_FASTPATH_SKIP_EMUL_INS; 1608 } 1609 1610 return EXIT_FASTPATH_NONE; 1611 } 1612 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); 1613 1614 /* 1615 * Adapt set_msr() to msr_io()'s calling convention 1616 */ 1617 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1618 { 1619 return __kvm_get_msr(vcpu, index, data, true); 1620 } 1621 1622 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1623 { 1624 return __kvm_set_msr(vcpu, index, *data, true); 1625 } 1626 1627 #ifdef CONFIG_X86_64 1628 struct pvclock_clock { 1629 int vclock_mode; 1630 u64 cycle_last; 1631 u64 mask; 1632 u32 mult; 1633 u32 shift; 1634 u64 base_cycles; 1635 u64 offset; 1636 }; 1637 1638 struct pvclock_gtod_data { 1639 seqcount_t seq; 1640 1641 struct pvclock_clock clock; /* extract of a clocksource struct */ 1642 struct pvclock_clock raw_clock; /* extract of a clocksource struct */ 1643 1644 ktime_t offs_boot; 1645 u64 wall_time_sec; 1646 }; 1647 1648 static struct pvclock_gtod_data pvclock_gtod_data; 1649 1650 static void update_pvclock_gtod(struct timekeeper *tk) 1651 { 1652 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1653 1654 write_seqcount_begin(&vdata->seq); 1655 1656 /* copy pvclock gtod data */ 1657 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; 1658 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1659 vdata->clock.mask = tk->tkr_mono.mask; 1660 vdata->clock.mult = tk->tkr_mono.mult; 1661 vdata->clock.shift = tk->tkr_mono.shift; 1662 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 1663 vdata->clock.offset = tk->tkr_mono.base; 1664 1665 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; 1666 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; 1667 vdata->raw_clock.mask = tk->tkr_raw.mask; 1668 vdata->raw_clock.mult = tk->tkr_raw.mult; 1669 vdata->raw_clock.shift = tk->tkr_raw.shift; 1670 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; 1671 vdata->raw_clock.offset = tk->tkr_raw.base; 1672 1673 vdata->wall_time_sec = tk->xtime_sec; 1674 1675 vdata->offs_boot = tk->offs_boot; 1676 1677 write_seqcount_end(&vdata->seq); 1678 } 1679 1680 static s64 get_kvmclock_base_ns(void) 1681 { 1682 /* Count up from boot time, but with the frequency of the raw clock. */ 1683 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); 1684 } 1685 #else 1686 static s64 get_kvmclock_base_ns(void) 1687 { 1688 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ 1689 return ktime_get_boottime_ns(); 1690 } 1691 #endif 1692 1693 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1694 { 1695 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1696 kvm_vcpu_kick(vcpu); 1697 } 1698 1699 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1700 { 1701 int version; 1702 int r; 1703 struct pvclock_wall_clock wc; 1704 u64 wall_nsec; 1705 1706 if (!wall_clock) 1707 return; 1708 1709 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1710 if (r) 1711 return; 1712 1713 if (version & 1) 1714 ++version; /* first time write, random junk */ 1715 1716 ++version; 1717 1718 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1719 return; 1720 1721 /* 1722 * The guest calculates current wall clock time by adding 1723 * system time (updated by kvm_guest_time_update below) to the 1724 * wall clock specified here. We do the reverse here. 1725 */ 1726 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); 1727 1728 wc.nsec = do_div(wall_nsec, 1000000000); 1729 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ 1730 wc.version = version; 1731 1732 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1733 1734 version++; 1735 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1736 } 1737 1738 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1739 { 1740 do_shl32_div32(dividend, divisor); 1741 return dividend; 1742 } 1743 1744 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 1745 s8 *pshift, u32 *pmultiplier) 1746 { 1747 uint64_t scaled64; 1748 int32_t shift = 0; 1749 uint64_t tps64; 1750 uint32_t tps32; 1751 1752 tps64 = base_hz; 1753 scaled64 = scaled_hz; 1754 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1755 tps64 >>= 1; 1756 shift--; 1757 } 1758 1759 tps32 = (uint32_t)tps64; 1760 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1761 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1762 scaled64 >>= 1; 1763 else 1764 tps32 <<= 1; 1765 shift++; 1766 } 1767 1768 *pshift = shift; 1769 *pmultiplier = div_frac(scaled64, tps32); 1770 } 1771 1772 #ifdef CONFIG_X86_64 1773 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1774 #endif 1775 1776 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1777 static unsigned long max_tsc_khz; 1778 1779 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1780 { 1781 u64 v = (u64)khz * (1000000 + ppm); 1782 do_div(v, 1000000); 1783 return v; 1784 } 1785 1786 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 1787 { 1788 u64 ratio; 1789 1790 /* Guest TSC same frequency as host TSC? */ 1791 if (!scale) { 1792 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1793 return 0; 1794 } 1795 1796 /* TSC scaling supported? */ 1797 if (!kvm_has_tsc_control) { 1798 if (user_tsc_khz > tsc_khz) { 1799 vcpu->arch.tsc_catchup = 1; 1800 vcpu->arch.tsc_always_catchup = 1; 1801 return 0; 1802 } else { 1803 pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); 1804 return -1; 1805 } 1806 } 1807 1808 /* TSC scaling required - calculate ratio */ 1809 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 1810 user_tsc_khz, tsc_khz); 1811 1812 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 1813 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 1814 user_tsc_khz); 1815 return -1; 1816 } 1817 1818 vcpu->arch.tsc_scaling_ratio = ratio; 1819 return 0; 1820 } 1821 1822 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 1823 { 1824 u32 thresh_lo, thresh_hi; 1825 int use_scaling = 0; 1826 1827 /* tsc_khz can be zero if TSC calibration fails */ 1828 if (user_tsc_khz == 0) { 1829 /* set tsc_scaling_ratio to a safe value */ 1830 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1831 return -1; 1832 } 1833 1834 /* Compute a scale to convert nanoseconds in TSC cycles */ 1835 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 1836 &vcpu->arch.virtual_tsc_shift, 1837 &vcpu->arch.virtual_tsc_mult); 1838 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 1839 1840 /* 1841 * Compute the variation in TSC rate which is acceptable 1842 * within the range of tolerance and decide if the 1843 * rate being applied is within that bounds of the hardware 1844 * rate. If so, no scaling or compensation need be done. 1845 */ 1846 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1847 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1848 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 1849 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 1850 use_scaling = 1; 1851 } 1852 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 1853 } 1854 1855 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1856 { 1857 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1858 vcpu->arch.virtual_tsc_mult, 1859 vcpu->arch.virtual_tsc_shift); 1860 tsc += vcpu->arch.this_tsc_write; 1861 return tsc; 1862 } 1863 1864 static inline int gtod_is_based_on_tsc(int mode) 1865 { 1866 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; 1867 } 1868 1869 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1870 { 1871 #ifdef CONFIG_X86_64 1872 bool vcpus_matched; 1873 struct kvm_arch *ka = &vcpu->kvm->arch; 1874 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1875 1876 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1877 atomic_read(&vcpu->kvm->online_vcpus)); 1878 1879 /* 1880 * Once the masterclock is enabled, always perform request in 1881 * order to update it. 1882 * 1883 * In order to enable masterclock, the host clocksource must be TSC 1884 * and the vcpus need to have matched TSCs. When that happens, 1885 * perform request to enable masterclock. 1886 */ 1887 if (ka->use_master_clock || 1888 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 1889 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1890 1891 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1892 atomic_read(&vcpu->kvm->online_vcpus), 1893 ka->use_master_clock, gtod->clock.vclock_mode); 1894 #endif 1895 } 1896 1897 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1898 { 1899 u64 curr_offset = kvm_x86_ops.read_l1_tsc_offset(vcpu); 1900 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1901 } 1902 1903 /* 1904 * Multiply tsc by a fixed point number represented by ratio. 1905 * 1906 * The most significant 64-N bits (mult) of ratio represent the 1907 * integral part of the fixed point number; the remaining N bits 1908 * (frac) represent the fractional part, ie. ratio represents a fixed 1909 * point number (mult + frac * 2^(-N)). 1910 * 1911 * N equals to kvm_tsc_scaling_ratio_frac_bits. 1912 */ 1913 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 1914 { 1915 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 1916 } 1917 1918 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 1919 { 1920 u64 _tsc = tsc; 1921 u64 ratio = vcpu->arch.tsc_scaling_ratio; 1922 1923 if (ratio != kvm_default_tsc_scaling_ratio) 1924 _tsc = __scale_tsc(ratio, tsc); 1925 1926 return _tsc; 1927 } 1928 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 1929 1930 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 1931 { 1932 u64 tsc; 1933 1934 tsc = kvm_scale_tsc(vcpu, rdtsc()); 1935 1936 return target_tsc - tsc; 1937 } 1938 1939 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 1940 { 1941 u64 tsc_offset = kvm_x86_ops.read_l1_tsc_offset(vcpu); 1942 1943 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc); 1944 } 1945 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 1946 1947 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1948 { 1949 vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset); 1950 } 1951 1952 static inline bool kvm_check_tsc_unstable(void) 1953 { 1954 #ifdef CONFIG_X86_64 1955 /* 1956 * TSC is marked unstable when we're running on Hyper-V, 1957 * 'TSC page' clocksource is good. 1958 */ 1959 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) 1960 return false; 1961 #endif 1962 return check_tsc_unstable(); 1963 } 1964 1965 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1966 { 1967 struct kvm *kvm = vcpu->kvm; 1968 u64 offset, ns, elapsed; 1969 unsigned long flags; 1970 bool matched; 1971 bool already_matched; 1972 u64 data = msr->data; 1973 bool synchronizing = false; 1974 1975 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1976 offset = kvm_compute_tsc_offset(vcpu, data); 1977 ns = get_kvmclock_base_ns(); 1978 elapsed = ns - kvm->arch.last_tsc_nsec; 1979 1980 if (vcpu->arch.virtual_tsc_khz) { 1981 if (data == 0 && msr->host_initiated) { 1982 /* 1983 * detection of vcpu initialization -- need to sync 1984 * with other vCPUs. This particularly helps to keep 1985 * kvm_clock stable after CPU hotplug 1986 */ 1987 synchronizing = true; 1988 } else { 1989 u64 tsc_exp = kvm->arch.last_tsc_write + 1990 nsec_to_cycles(vcpu, elapsed); 1991 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 1992 /* 1993 * Special case: TSC write with a small delta (1 second) 1994 * of virtual cycle time against real time is 1995 * interpreted as an attempt to synchronize the CPU. 1996 */ 1997 synchronizing = data < tsc_exp + tsc_hz && 1998 data + tsc_hz > tsc_exp; 1999 } 2000 } 2001 2002 /* 2003 * For a reliable TSC, we can match TSC offsets, and for an unstable 2004 * TSC, we add elapsed time in this computation. We could let the 2005 * compensation code attempt to catch up if we fall behind, but 2006 * it's better to try to match offsets from the beginning. 2007 */ 2008 if (synchronizing && 2009 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 2010 if (!kvm_check_tsc_unstable()) { 2011 offset = kvm->arch.cur_tsc_offset; 2012 } else { 2013 u64 delta = nsec_to_cycles(vcpu, elapsed); 2014 data += delta; 2015 offset = kvm_compute_tsc_offset(vcpu, data); 2016 } 2017 matched = true; 2018 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 2019 } else { 2020 /* 2021 * We split periods of matched TSC writes into generations. 2022 * For each generation, we track the original measured 2023 * nanosecond time, offset, and write, so if TSCs are in 2024 * sync, we can match exact offset, and if not, we can match 2025 * exact software computation in compute_guest_tsc() 2026 * 2027 * These values are tracked in kvm->arch.cur_xxx variables. 2028 */ 2029 kvm->arch.cur_tsc_generation++; 2030 kvm->arch.cur_tsc_nsec = ns; 2031 kvm->arch.cur_tsc_write = data; 2032 kvm->arch.cur_tsc_offset = offset; 2033 matched = false; 2034 } 2035 2036 /* 2037 * We also track th most recent recorded KHZ, write and time to 2038 * allow the matching interval to be extended at each write. 2039 */ 2040 kvm->arch.last_tsc_nsec = ns; 2041 kvm->arch.last_tsc_write = data; 2042 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 2043 2044 vcpu->arch.last_guest_tsc = data; 2045 2046 /* Keep track of which generation this VCPU has synchronized to */ 2047 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 2048 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 2049 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 2050 2051 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) 2052 update_ia32_tsc_adjust_msr(vcpu, offset); 2053 2054 kvm_vcpu_write_tsc_offset(vcpu, offset); 2055 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 2056 2057 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 2058 if (!matched) { 2059 kvm->arch.nr_vcpus_matched_tsc = 0; 2060 } else if (!already_matched) { 2061 kvm->arch.nr_vcpus_matched_tsc++; 2062 } 2063 2064 kvm_track_tsc_matching(vcpu); 2065 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 2066 } 2067 2068 EXPORT_SYMBOL_GPL(kvm_write_tsc); 2069 2070 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 2071 s64 adjustment) 2072 { 2073 u64 tsc_offset = kvm_x86_ops.read_l1_tsc_offset(vcpu); 2074 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 2075 } 2076 2077 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 2078 { 2079 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 2080 WARN_ON(adjustment < 0); 2081 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 2082 adjust_tsc_offset_guest(vcpu, adjustment); 2083 } 2084 2085 #ifdef CONFIG_X86_64 2086 2087 static u64 read_tsc(void) 2088 { 2089 u64 ret = (u64)rdtsc_ordered(); 2090 u64 last = pvclock_gtod_data.clock.cycle_last; 2091 2092 if (likely(ret >= last)) 2093 return ret; 2094 2095 /* 2096 * GCC likes to generate cmov here, but this branch is extremely 2097 * predictable (it's just a function of time and the likely is 2098 * very likely) and there's a data dependence, so force GCC 2099 * to generate a branch instead. I don't barrier() because 2100 * we don't actually need a barrier, and if this function 2101 * ever gets inlined it will generate worse code. 2102 */ 2103 asm volatile (""); 2104 return last; 2105 } 2106 2107 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, 2108 int *mode) 2109 { 2110 long v; 2111 u64 tsc_pg_val; 2112 2113 switch (clock->vclock_mode) { 2114 case VDSO_CLOCKMODE_HVCLOCK: 2115 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 2116 tsc_timestamp); 2117 if (tsc_pg_val != U64_MAX) { 2118 /* TSC page valid */ 2119 *mode = VDSO_CLOCKMODE_HVCLOCK; 2120 v = (tsc_pg_val - clock->cycle_last) & 2121 clock->mask; 2122 } else { 2123 /* TSC page invalid */ 2124 *mode = VDSO_CLOCKMODE_NONE; 2125 } 2126 break; 2127 case VDSO_CLOCKMODE_TSC: 2128 *mode = VDSO_CLOCKMODE_TSC; 2129 *tsc_timestamp = read_tsc(); 2130 v = (*tsc_timestamp - clock->cycle_last) & 2131 clock->mask; 2132 break; 2133 default: 2134 *mode = VDSO_CLOCKMODE_NONE; 2135 } 2136 2137 if (*mode == VDSO_CLOCKMODE_NONE) 2138 *tsc_timestamp = v = 0; 2139 2140 return v * clock->mult; 2141 } 2142 2143 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) 2144 { 2145 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2146 unsigned long seq; 2147 int mode; 2148 u64 ns; 2149 2150 do { 2151 seq = read_seqcount_begin(>od->seq); 2152 ns = gtod->raw_clock.base_cycles; 2153 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); 2154 ns >>= gtod->raw_clock.shift; 2155 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); 2156 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2157 *t = ns; 2158 2159 return mode; 2160 } 2161 2162 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 2163 { 2164 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2165 unsigned long seq; 2166 int mode; 2167 u64 ns; 2168 2169 do { 2170 seq = read_seqcount_begin(>od->seq); 2171 ts->tv_sec = gtod->wall_time_sec; 2172 ns = gtod->clock.base_cycles; 2173 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2174 ns >>= gtod->clock.shift; 2175 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2176 2177 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 2178 ts->tv_nsec = ns; 2179 2180 return mode; 2181 } 2182 2183 /* returns true if host is using TSC based clocksource */ 2184 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2185 { 2186 /* checked again under seqlock below */ 2187 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2188 return false; 2189 2190 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, 2191 tsc_timestamp)); 2192 } 2193 2194 /* returns true if host is using TSC based clocksource */ 2195 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 2196 u64 *tsc_timestamp) 2197 { 2198 /* checked again under seqlock below */ 2199 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2200 return false; 2201 2202 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 2203 } 2204 #endif 2205 2206 /* 2207 * 2208 * Assuming a stable TSC across physical CPUS, and a stable TSC 2209 * across virtual CPUs, the following condition is possible. 2210 * Each numbered line represents an event visible to both 2211 * CPUs at the next numbered event. 2212 * 2213 * "timespecX" represents host monotonic time. "tscX" represents 2214 * RDTSC value. 2215 * 2216 * VCPU0 on CPU0 | VCPU1 on CPU1 2217 * 2218 * 1. read timespec0,tsc0 2219 * 2. | timespec1 = timespec0 + N 2220 * | tsc1 = tsc0 + M 2221 * 3. transition to guest | transition to guest 2222 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 2223 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 2224 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 2225 * 2226 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 2227 * 2228 * - ret0 < ret1 2229 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 2230 * ... 2231 * - 0 < N - M => M < N 2232 * 2233 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 2234 * always the case (the difference between two distinct xtime instances 2235 * might be smaller then the difference between corresponding TSC reads, 2236 * when updating guest vcpus pvclock areas). 2237 * 2238 * To avoid that problem, do not allow visibility of distinct 2239 * system_timestamp/tsc_timestamp values simultaneously: use a master 2240 * copy of host monotonic time values. Update that master copy 2241 * in lockstep. 2242 * 2243 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2244 * 2245 */ 2246 2247 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2248 { 2249 #ifdef CONFIG_X86_64 2250 struct kvm_arch *ka = &kvm->arch; 2251 int vclock_mode; 2252 bool host_tsc_clocksource, vcpus_matched; 2253 2254 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2255 atomic_read(&kvm->online_vcpus)); 2256 2257 /* 2258 * If the host uses TSC clock, then passthrough TSC as stable 2259 * to the guest. 2260 */ 2261 host_tsc_clocksource = kvm_get_time_and_clockread( 2262 &ka->master_kernel_ns, 2263 &ka->master_cycle_now); 2264 2265 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2266 && !ka->backwards_tsc_observed 2267 && !ka->boot_vcpu_runs_old_kvmclock; 2268 2269 if (ka->use_master_clock) 2270 atomic_set(&kvm_guest_has_master_clock, 1); 2271 2272 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2273 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2274 vcpus_matched); 2275 #endif 2276 } 2277 2278 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2279 { 2280 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2281 } 2282 2283 static void kvm_gen_update_masterclock(struct kvm *kvm) 2284 { 2285 #ifdef CONFIG_X86_64 2286 int i; 2287 struct kvm_vcpu *vcpu; 2288 struct kvm_arch *ka = &kvm->arch; 2289 2290 spin_lock(&ka->pvclock_gtod_sync_lock); 2291 kvm_make_mclock_inprogress_request(kvm); 2292 /* no guest entries from this point */ 2293 pvclock_update_vm_gtod_copy(kvm); 2294 2295 kvm_for_each_vcpu(i, vcpu, kvm) 2296 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2297 2298 /* guest entries allowed */ 2299 kvm_for_each_vcpu(i, vcpu, kvm) 2300 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2301 2302 spin_unlock(&ka->pvclock_gtod_sync_lock); 2303 #endif 2304 } 2305 2306 u64 get_kvmclock_ns(struct kvm *kvm) 2307 { 2308 struct kvm_arch *ka = &kvm->arch; 2309 struct pvclock_vcpu_time_info hv_clock; 2310 u64 ret; 2311 2312 spin_lock(&ka->pvclock_gtod_sync_lock); 2313 if (!ka->use_master_clock) { 2314 spin_unlock(&ka->pvclock_gtod_sync_lock); 2315 return get_kvmclock_base_ns() + ka->kvmclock_offset; 2316 } 2317 2318 hv_clock.tsc_timestamp = ka->master_cycle_now; 2319 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2320 spin_unlock(&ka->pvclock_gtod_sync_lock); 2321 2322 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2323 get_cpu(); 2324 2325 if (__this_cpu_read(cpu_tsc_khz)) { 2326 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2327 &hv_clock.tsc_shift, 2328 &hv_clock.tsc_to_system_mul); 2329 ret = __pvclock_read_cycles(&hv_clock, rdtsc()); 2330 } else 2331 ret = get_kvmclock_base_ns() + ka->kvmclock_offset; 2332 2333 put_cpu(); 2334 2335 return ret; 2336 } 2337 2338 static void kvm_setup_pvclock_page(struct kvm_vcpu *v) 2339 { 2340 struct kvm_vcpu_arch *vcpu = &v->arch; 2341 struct pvclock_vcpu_time_info guest_hv_clock; 2342 2343 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 2344 &guest_hv_clock, sizeof(guest_hv_clock)))) 2345 return; 2346 2347 /* This VCPU is paused, but it's legal for a guest to read another 2348 * VCPU's kvmclock, so we really have to follow the specification where 2349 * it says that version is odd if data is being modified, and even after 2350 * it is consistent. 2351 * 2352 * Version field updates must be kept separate. This is because 2353 * kvm_write_guest_cached might use a "rep movs" instruction, and 2354 * writes within a string instruction are weakly ordered. So there 2355 * are three writes overall. 2356 * 2357 * As a small optimization, only write the version field in the first 2358 * and third write. The vcpu->pv_time cache is still valid, because the 2359 * version field is the first in the struct. 2360 */ 2361 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 2362 2363 if (guest_hv_clock.version & 1) 2364 ++guest_hv_clock.version; /* first time write, random junk */ 2365 2366 vcpu->hv_clock.version = guest_hv_clock.version + 1; 2367 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2368 &vcpu->hv_clock, 2369 sizeof(vcpu->hv_clock.version)); 2370 2371 smp_wmb(); 2372 2373 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 2374 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 2375 2376 if (vcpu->pvclock_set_guest_stopped_request) { 2377 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 2378 vcpu->pvclock_set_guest_stopped_request = false; 2379 } 2380 2381 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 2382 2383 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2384 &vcpu->hv_clock, 2385 sizeof(vcpu->hv_clock)); 2386 2387 smp_wmb(); 2388 2389 vcpu->hv_clock.version++; 2390 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2391 &vcpu->hv_clock, 2392 sizeof(vcpu->hv_clock.version)); 2393 } 2394 2395 static int kvm_guest_time_update(struct kvm_vcpu *v) 2396 { 2397 unsigned long flags, tgt_tsc_khz; 2398 struct kvm_vcpu_arch *vcpu = &v->arch; 2399 struct kvm_arch *ka = &v->kvm->arch; 2400 s64 kernel_ns; 2401 u64 tsc_timestamp, host_tsc; 2402 u8 pvclock_flags; 2403 bool use_master_clock; 2404 2405 kernel_ns = 0; 2406 host_tsc = 0; 2407 2408 /* 2409 * If the host uses TSC clock, then passthrough TSC as stable 2410 * to the guest. 2411 */ 2412 spin_lock(&ka->pvclock_gtod_sync_lock); 2413 use_master_clock = ka->use_master_clock; 2414 if (use_master_clock) { 2415 host_tsc = ka->master_cycle_now; 2416 kernel_ns = ka->master_kernel_ns; 2417 } 2418 spin_unlock(&ka->pvclock_gtod_sync_lock); 2419 2420 /* Keep irq disabled to prevent changes to the clock */ 2421 local_irq_save(flags); 2422 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 2423 if (unlikely(tgt_tsc_khz == 0)) { 2424 local_irq_restore(flags); 2425 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2426 return 1; 2427 } 2428 if (!use_master_clock) { 2429 host_tsc = rdtsc(); 2430 kernel_ns = get_kvmclock_base_ns(); 2431 } 2432 2433 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 2434 2435 /* 2436 * We may have to catch up the TSC to match elapsed wall clock 2437 * time for two reasons, even if kvmclock is used. 2438 * 1) CPU could have been running below the maximum TSC rate 2439 * 2) Broken TSC compensation resets the base at each VCPU 2440 * entry to avoid unknown leaps of TSC even when running 2441 * again on the same CPU. This may cause apparent elapsed 2442 * time to disappear, and the guest to stand still or run 2443 * very slowly. 2444 */ 2445 if (vcpu->tsc_catchup) { 2446 u64 tsc = compute_guest_tsc(v, kernel_ns); 2447 if (tsc > tsc_timestamp) { 2448 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 2449 tsc_timestamp = tsc; 2450 } 2451 } 2452 2453 local_irq_restore(flags); 2454 2455 /* With all the info we got, fill in the values */ 2456 2457 if (kvm_has_tsc_control) 2458 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 2459 2460 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 2461 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 2462 &vcpu->hv_clock.tsc_shift, 2463 &vcpu->hv_clock.tsc_to_system_mul); 2464 vcpu->hw_tsc_khz = tgt_tsc_khz; 2465 } 2466 2467 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 2468 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 2469 vcpu->last_guest_tsc = tsc_timestamp; 2470 2471 /* If the host uses TSC clocksource, then it is stable */ 2472 pvclock_flags = 0; 2473 if (use_master_clock) 2474 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 2475 2476 vcpu->hv_clock.flags = pvclock_flags; 2477 2478 if (vcpu->pv_time_enabled) 2479 kvm_setup_pvclock_page(v); 2480 if (v == kvm_get_vcpu(v->kvm, 0)) 2481 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 2482 return 0; 2483 } 2484 2485 /* 2486 * kvmclock updates which are isolated to a given vcpu, such as 2487 * vcpu->cpu migration, should not allow system_timestamp from 2488 * the rest of the vcpus to remain static. Otherwise ntp frequency 2489 * correction applies to one vcpu's system_timestamp but not 2490 * the others. 2491 * 2492 * So in those cases, request a kvmclock update for all vcpus. 2493 * We need to rate-limit these requests though, as they can 2494 * considerably slow guests that have a large number of vcpus. 2495 * The time for a remote vcpu to update its kvmclock is bound 2496 * by the delay we use to rate-limit the updates. 2497 */ 2498 2499 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 2500 2501 static void kvmclock_update_fn(struct work_struct *work) 2502 { 2503 int i; 2504 struct delayed_work *dwork = to_delayed_work(work); 2505 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2506 kvmclock_update_work); 2507 struct kvm *kvm = container_of(ka, struct kvm, arch); 2508 struct kvm_vcpu *vcpu; 2509 2510 kvm_for_each_vcpu(i, vcpu, kvm) { 2511 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2512 kvm_vcpu_kick(vcpu); 2513 } 2514 } 2515 2516 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 2517 { 2518 struct kvm *kvm = v->kvm; 2519 2520 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2521 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 2522 KVMCLOCK_UPDATE_DELAY); 2523 } 2524 2525 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 2526 2527 static void kvmclock_sync_fn(struct work_struct *work) 2528 { 2529 struct delayed_work *dwork = to_delayed_work(work); 2530 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2531 kvmclock_sync_work); 2532 struct kvm *kvm = container_of(ka, struct kvm, arch); 2533 2534 if (!kvmclock_periodic_sync) 2535 return; 2536 2537 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 2538 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 2539 KVMCLOCK_SYNC_PERIOD); 2540 } 2541 2542 /* 2543 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 2544 */ 2545 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 2546 { 2547 /* McStatusWrEn enabled? */ 2548 if (guest_cpuid_is_amd_or_hygon(vcpu)) 2549 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 2550 2551 return false; 2552 } 2553 2554 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2555 { 2556 u64 mcg_cap = vcpu->arch.mcg_cap; 2557 unsigned bank_num = mcg_cap & 0xff; 2558 u32 msr = msr_info->index; 2559 u64 data = msr_info->data; 2560 2561 switch (msr) { 2562 case MSR_IA32_MCG_STATUS: 2563 vcpu->arch.mcg_status = data; 2564 break; 2565 case MSR_IA32_MCG_CTL: 2566 if (!(mcg_cap & MCG_CTL_P) && 2567 (data || !msr_info->host_initiated)) 2568 return 1; 2569 if (data != 0 && data != ~(u64)0) 2570 return 1; 2571 vcpu->arch.mcg_ctl = data; 2572 break; 2573 default: 2574 if (msr >= MSR_IA32_MC0_CTL && 2575 msr < MSR_IA32_MCx_CTL(bank_num)) { 2576 u32 offset = array_index_nospec( 2577 msr - MSR_IA32_MC0_CTL, 2578 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 2579 2580 /* only 0 or all 1s can be written to IA32_MCi_CTL 2581 * some Linux kernels though clear bit 10 in bank 4 to 2582 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 2583 * this to avoid an uncatched #GP in the guest 2584 */ 2585 if ((offset & 0x3) == 0 && 2586 data != 0 && (data | (1 << 10)) != ~(u64)0) 2587 return -1; 2588 2589 /* MCi_STATUS */ 2590 if (!msr_info->host_initiated && 2591 (offset & 0x3) == 1 && data != 0) { 2592 if (!can_set_mci_status(vcpu)) 2593 return -1; 2594 } 2595 2596 vcpu->arch.mce_banks[offset] = data; 2597 break; 2598 } 2599 return 1; 2600 } 2601 return 0; 2602 } 2603 2604 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 2605 { 2606 struct kvm *kvm = vcpu->kvm; 2607 int lm = is_long_mode(vcpu); 2608 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 2609 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 2610 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 2611 : kvm->arch.xen_hvm_config.blob_size_32; 2612 u32 page_num = data & ~PAGE_MASK; 2613 u64 page_addr = data & PAGE_MASK; 2614 u8 *page; 2615 int r; 2616 2617 r = -E2BIG; 2618 if (page_num >= blob_size) 2619 goto out; 2620 r = -ENOMEM; 2621 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 2622 if (IS_ERR(page)) { 2623 r = PTR_ERR(page); 2624 goto out; 2625 } 2626 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 2627 goto out_free; 2628 r = 0; 2629 out_free: 2630 kfree(page); 2631 out: 2632 return r; 2633 } 2634 2635 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2636 { 2637 gpa_t gpa = data & ~0x3f; 2638 2639 /* Bits 3:5 are reserved, Should be zero */ 2640 if (data & 0x38) 2641 return 1; 2642 2643 vcpu->arch.apf.msr_val = data; 2644 2645 if (!(data & KVM_ASYNC_PF_ENABLED)) { 2646 kvm_clear_async_pf_completion_queue(vcpu); 2647 kvm_async_pf_hash_reset(vcpu); 2648 return 0; 2649 } 2650 2651 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2652 sizeof(u32))) 2653 return 1; 2654 2655 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2656 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 2657 kvm_async_pf_wakeup_all(vcpu); 2658 return 0; 2659 } 2660 2661 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2662 { 2663 vcpu->arch.pv_time_enabled = false; 2664 vcpu->arch.time = 0; 2665 } 2666 2667 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) 2668 { 2669 ++vcpu->stat.tlb_flush; 2670 kvm_x86_ops.tlb_flush(vcpu, invalidate_gpa); 2671 } 2672 2673 static void record_steal_time(struct kvm_vcpu *vcpu) 2674 { 2675 struct kvm_host_map map; 2676 struct kvm_steal_time *st; 2677 2678 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2679 return; 2680 2681 /* -EAGAIN is returned in atomic context so we can just return. */ 2682 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, 2683 &map, &vcpu->arch.st.cache, false)) 2684 return; 2685 2686 st = map.hva + 2687 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 2688 2689 /* 2690 * Doing a TLB flush here, on the guest's behalf, can avoid 2691 * expensive IPIs. 2692 */ 2693 trace_kvm_pv_tlb_flush(vcpu->vcpu_id, 2694 st->preempted & KVM_VCPU_FLUSH_TLB); 2695 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB) 2696 kvm_vcpu_flush_tlb(vcpu, false); 2697 2698 vcpu->arch.st.preempted = 0; 2699 2700 if (st->version & 1) 2701 st->version += 1; /* first time write, random junk */ 2702 2703 st->version += 1; 2704 2705 smp_wmb(); 2706 2707 st->steal += current->sched_info.run_delay - 2708 vcpu->arch.st.last_steal; 2709 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2710 2711 smp_wmb(); 2712 2713 st->version += 1; 2714 2715 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); 2716 } 2717 2718 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2719 { 2720 bool pr = false; 2721 u32 msr = msr_info->index; 2722 u64 data = msr_info->data; 2723 2724 switch (msr) { 2725 case MSR_AMD64_NB_CFG: 2726 case MSR_IA32_UCODE_WRITE: 2727 case MSR_VM_HSAVE_PA: 2728 case MSR_AMD64_PATCH_LOADER: 2729 case MSR_AMD64_BU_CFG2: 2730 case MSR_AMD64_DC_CFG: 2731 case MSR_F15H_EX_CFG: 2732 break; 2733 2734 case MSR_IA32_UCODE_REV: 2735 if (msr_info->host_initiated) 2736 vcpu->arch.microcode_version = data; 2737 break; 2738 case MSR_IA32_ARCH_CAPABILITIES: 2739 if (!msr_info->host_initiated) 2740 return 1; 2741 vcpu->arch.arch_capabilities = data; 2742 break; 2743 case MSR_EFER: 2744 return set_efer(vcpu, msr_info); 2745 case MSR_K7_HWCR: 2746 data &= ~(u64)0x40; /* ignore flush filter disable */ 2747 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2748 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2749 2750 /* Handle McStatusWrEn */ 2751 if (data == BIT_ULL(18)) { 2752 vcpu->arch.msr_hwcr = data; 2753 } else if (data != 0) { 2754 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2755 data); 2756 return 1; 2757 } 2758 break; 2759 case MSR_FAM10H_MMIO_CONF_BASE: 2760 if (data != 0) { 2761 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2762 "0x%llx\n", data); 2763 return 1; 2764 } 2765 break; 2766 case MSR_IA32_DEBUGCTLMSR: 2767 if (!data) { 2768 /* We support the non-activated case already */ 2769 break; 2770 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2771 /* Values other than LBR and BTF are vendor-specific, 2772 thus reserved and should throw a #GP */ 2773 return 1; 2774 } 2775 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2776 __func__, data); 2777 break; 2778 case 0x200 ... 0x2ff: 2779 return kvm_mtrr_set_msr(vcpu, msr, data); 2780 case MSR_IA32_APICBASE: 2781 return kvm_set_apic_base(vcpu, msr_info); 2782 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2783 return kvm_x2apic_msr_write(vcpu, msr, data); 2784 case MSR_IA32_TSCDEADLINE: 2785 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2786 break; 2787 case MSR_IA32_TSC_ADJUST: 2788 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 2789 if (!msr_info->host_initiated) { 2790 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2791 adjust_tsc_offset_guest(vcpu, adj); 2792 } 2793 vcpu->arch.ia32_tsc_adjust_msr = data; 2794 } 2795 break; 2796 case MSR_IA32_MISC_ENABLE: 2797 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && 2798 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { 2799 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) 2800 return 1; 2801 vcpu->arch.ia32_misc_enable_msr = data; 2802 kvm_update_cpuid(vcpu); 2803 } else { 2804 vcpu->arch.ia32_misc_enable_msr = data; 2805 } 2806 break; 2807 case MSR_IA32_SMBASE: 2808 if (!msr_info->host_initiated) 2809 return 1; 2810 vcpu->arch.smbase = data; 2811 break; 2812 case MSR_IA32_POWER_CTL: 2813 vcpu->arch.msr_ia32_power_ctl = data; 2814 break; 2815 case MSR_IA32_TSC: 2816 kvm_write_tsc(vcpu, msr_info); 2817 break; 2818 case MSR_IA32_XSS: 2819 if (!msr_info->host_initiated && 2820 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 2821 return 1; 2822 /* 2823 * KVM supports exposing PT to the guest, but does not support 2824 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than 2825 * XSAVES/XRSTORS to save/restore PT MSRs. 2826 */ 2827 if (data & ~supported_xss) 2828 return 1; 2829 vcpu->arch.ia32_xss = data; 2830 break; 2831 case MSR_SMI_COUNT: 2832 if (!msr_info->host_initiated) 2833 return 1; 2834 vcpu->arch.smi_count = data; 2835 break; 2836 case MSR_KVM_WALL_CLOCK_NEW: 2837 case MSR_KVM_WALL_CLOCK: 2838 vcpu->kvm->arch.wall_clock = data; 2839 kvm_write_wall_clock(vcpu->kvm, data); 2840 break; 2841 case MSR_KVM_SYSTEM_TIME_NEW: 2842 case MSR_KVM_SYSTEM_TIME: { 2843 struct kvm_arch *ka = &vcpu->kvm->arch; 2844 2845 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2846 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2847 2848 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2849 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2850 2851 ka->boot_vcpu_runs_old_kvmclock = tmp; 2852 } 2853 2854 vcpu->arch.time = data; 2855 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2856 2857 /* we verify if the enable bit is set... */ 2858 vcpu->arch.pv_time_enabled = false; 2859 if (!(data & 1)) 2860 break; 2861 2862 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, 2863 &vcpu->arch.pv_time, data & ~1ULL, 2864 sizeof(struct pvclock_vcpu_time_info))) 2865 vcpu->arch.pv_time_enabled = true; 2866 2867 break; 2868 } 2869 case MSR_KVM_ASYNC_PF_EN: 2870 if (kvm_pv_enable_async_pf(vcpu, data)) 2871 return 1; 2872 break; 2873 case MSR_KVM_STEAL_TIME: 2874 2875 if (unlikely(!sched_info_on())) 2876 return 1; 2877 2878 if (data & KVM_STEAL_RESERVED_MASK) 2879 return 1; 2880 2881 vcpu->arch.st.msr_val = data; 2882 2883 if (!(data & KVM_MSR_ENABLED)) 2884 break; 2885 2886 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2887 2888 break; 2889 case MSR_KVM_PV_EOI_EN: 2890 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) 2891 return 1; 2892 break; 2893 2894 case MSR_KVM_POLL_CONTROL: 2895 /* only enable bit supported */ 2896 if (data & (-1ULL << 1)) 2897 return 1; 2898 2899 vcpu->arch.msr_kvm_poll_control = data; 2900 break; 2901 2902 case MSR_IA32_MCG_CTL: 2903 case MSR_IA32_MCG_STATUS: 2904 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2905 return set_msr_mce(vcpu, msr_info); 2906 2907 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2908 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2909 pr = true; /* fall through */ 2910 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2911 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2912 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2913 return kvm_pmu_set_msr(vcpu, msr_info); 2914 2915 if (pr || data != 0) 2916 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2917 "0x%x data 0x%llx\n", msr, data); 2918 break; 2919 case MSR_K7_CLK_CTL: 2920 /* 2921 * Ignore all writes to this no longer documented MSR. 2922 * Writes are only relevant for old K7 processors, 2923 * all pre-dating SVM, but a recommended workaround from 2924 * AMD for these chips. It is possible to specify the 2925 * affected processor models on the command line, hence 2926 * the need to ignore the workaround. 2927 */ 2928 break; 2929 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2930 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2931 case HV_X64_MSR_CRASH_CTL: 2932 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2933 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 2934 case HV_X64_MSR_TSC_EMULATION_CONTROL: 2935 case HV_X64_MSR_TSC_EMULATION_STATUS: 2936 return kvm_hv_set_msr_common(vcpu, msr, data, 2937 msr_info->host_initiated); 2938 case MSR_IA32_BBL_CR_CTL3: 2939 /* Drop writes to this legacy MSR -- see rdmsr 2940 * counterpart for further detail. 2941 */ 2942 if (report_ignored_msrs) 2943 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 2944 msr, data); 2945 break; 2946 case MSR_AMD64_OSVW_ID_LENGTH: 2947 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2948 return 1; 2949 vcpu->arch.osvw.length = data; 2950 break; 2951 case MSR_AMD64_OSVW_STATUS: 2952 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2953 return 1; 2954 vcpu->arch.osvw.status = data; 2955 break; 2956 case MSR_PLATFORM_INFO: 2957 if (!msr_info->host_initiated || 2958 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 2959 cpuid_fault_enabled(vcpu))) 2960 return 1; 2961 vcpu->arch.msr_platform_info = data; 2962 break; 2963 case MSR_MISC_FEATURES_ENABLES: 2964 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 2965 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 2966 !supports_cpuid_fault(vcpu))) 2967 return 1; 2968 vcpu->arch.msr_misc_features_enables = data; 2969 break; 2970 default: 2971 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2972 return xen_hvm_config(vcpu, data); 2973 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2974 return kvm_pmu_set_msr(vcpu, msr_info); 2975 if (!ignore_msrs) { 2976 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n", 2977 msr, data); 2978 return 1; 2979 } else { 2980 if (report_ignored_msrs) 2981 vcpu_unimpl(vcpu, 2982 "ignored wrmsr: 0x%x data 0x%llx\n", 2983 msr, data); 2984 break; 2985 } 2986 } 2987 return 0; 2988 } 2989 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2990 2991 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 2992 { 2993 u64 data; 2994 u64 mcg_cap = vcpu->arch.mcg_cap; 2995 unsigned bank_num = mcg_cap & 0xff; 2996 2997 switch (msr) { 2998 case MSR_IA32_P5_MC_ADDR: 2999 case MSR_IA32_P5_MC_TYPE: 3000 data = 0; 3001 break; 3002 case MSR_IA32_MCG_CAP: 3003 data = vcpu->arch.mcg_cap; 3004 break; 3005 case MSR_IA32_MCG_CTL: 3006 if (!(mcg_cap & MCG_CTL_P) && !host) 3007 return 1; 3008 data = vcpu->arch.mcg_ctl; 3009 break; 3010 case MSR_IA32_MCG_STATUS: 3011 data = vcpu->arch.mcg_status; 3012 break; 3013 default: 3014 if (msr >= MSR_IA32_MC0_CTL && 3015 msr < MSR_IA32_MCx_CTL(bank_num)) { 3016 u32 offset = array_index_nospec( 3017 msr - MSR_IA32_MC0_CTL, 3018 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3019 3020 data = vcpu->arch.mce_banks[offset]; 3021 break; 3022 } 3023 return 1; 3024 } 3025 *pdata = data; 3026 return 0; 3027 } 3028 3029 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3030 { 3031 switch (msr_info->index) { 3032 case MSR_IA32_PLATFORM_ID: 3033 case MSR_IA32_EBL_CR_POWERON: 3034 case MSR_IA32_DEBUGCTLMSR: 3035 case MSR_IA32_LASTBRANCHFROMIP: 3036 case MSR_IA32_LASTBRANCHTOIP: 3037 case MSR_IA32_LASTINTFROMIP: 3038 case MSR_IA32_LASTINTTOIP: 3039 case MSR_K8_SYSCFG: 3040 case MSR_K8_TSEG_ADDR: 3041 case MSR_K8_TSEG_MASK: 3042 case MSR_VM_HSAVE_PA: 3043 case MSR_K8_INT_PENDING_MSG: 3044 case MSR_AMD64_NB_CFG: 3045 case MSR_FAM10H_MMIO_CONF_BASE: 3046 case MSR_AMD64_BU_CFG2: 3047 case MSR_IA32_PERF_CTL: 3048 case MSR_AMD64_DC_CFG: 3049 case MSR_F15H_EX_CFG: 3050 /* 3051 * Intel Sandy Bridge CPUs must support the RAPL (running average power 3052 * limit) MSRs. Just return 0, as we do not want to expose the host 3053 * data here. Do not conditionalize this on CPUID, as KVM does not do 3054 * so for existing CPU-specific MSRs. 3055 */ 3056 case MSR_RAPL_POWER_UNIT: 3057 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ 3058 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ 3059 case MSR_PKG_ENERGY_STATUS: /* Total package */ 3060 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ 3061 msr_info->data = 0; 3062 break; 3063 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3064 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3065 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3066 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3067 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3068 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3069 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 3070 msr_info->data = 0; 3071 break; 3072 case MSR_IA32_UCODE_REV: 3073 msr_info->data = vcpu->arch.microcode_version; 3074 break; 3075 case MSR_IA32_ARCH_CAPABILITIES: 3076 if (!msr_info->host_initiated && 3077 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 3078 return 1; 3079 msr_info->data = vcpu->arch.arch_capabilities; 3080 break; 3081 case MSR_IA32_POWER_CTL: 3082 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 3083 break; 3084 case MSR_IA32_TSC: 3085 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset; 3086 break; 3087 case MSR_MTRRcap: 3088 case 0x200 ... 0x2ff: 3089 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 3090 case 0xcd: /* fsb frequency */ 3091 msr_info->data = 3; 3092 break; 3093 /* 3094 * MSR_EBC_FREQUENCY_ID 3095 * Conservative value valid for even the basic CPU models. 3096 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 3097 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 3098 * and 266MHz for model 3, or 4. Set Core Clock 3099 * Frequency to System Bus Frequency Ratio to 1 (bits 3100 * 31:24) even though these are only valid for CPU 3101 * models > 2, however guests may end up dividing or 3102 * multiplying by zero otherwise. 3103 */ 3104 case MSR_EBC_FREQUENCY_ID: 3105 msr_info->data = 1 << 24; 3106 break; 3107 case MSR_IA32_APICBASE: 3108 msr_info->data = kvm_get_apic_base(vcpu); 3109 break; 3110 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 3111 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 3112 case MSR_IA32_TSCDEADLINE: 3113 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 3114 break; 3115 case MSR_IA32_TSC_ADJUST: 3116 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 3117 break; 3118 case MSR_IA32_MISC_ENABLE: 3119 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 3120 break; 3121 case MSR_IA32_SMBASE: 3122 if (!msr_info->host_initiated) 3123 return 1; 3124 msr_info->data = vcpu->arch.smbase; 3125 break; 3126 case MSR_SMI_COUNT: 3127 msr_info->data = vcpu->arch.smi_count; 3128 break; 3129 case MSR_IA32_PERF_STATUS: 3130 /* TSC increment by tick */ 3131 msr_info->data = 1000ULL; 3132 /* CPU multiplier */ 3133 msr_info->data |= (((uint64_t)4ULL) << 40); 3134 break; 3135 case MSR_EFER: 3136 msr_info->data = vcpu->arch.efer; 3137 break; 3138 case MSR_KVM_WALL_CLOCK: 3139 case MSR_KVM_WALL_CLOCK_NEW: 3140 msr_info->data = vcpu->kvm->arch.wall_clock; 3141 break; 3142 case MSR_KVM_SYSTEM_TIME: 3143 case MSR_KVM_SYSTEM_TIME_NEW: 3144 msr_info->data = vcpu->arch.time; 3145 break; 3146 case MSR_KVM_ASYNC_PF_EN: 3147 msr_info->data = vcpu->arch.apf.msr_val; 3148 break; 3149 case MSR_KVM_STEAL_TIME: 3150 msr_info->data = vcpu->arch.st.msr_val; 3151 break; 3152 case MSR_KVM_PV_EOI_EN: 3153 msr_info->data = vcpu->arch.pv_eoi.msr_val; 3154 break; 3155 case MSR_KVM_POLL_CONTROL: 3156 msr_info->data = vcpu->arch.msr_kvm_poll_control; 3157 break; 3158 case MSR_IA32_P5_MC_ADDR: 3159 case MSR_IA32_P5_MC_TYPE: 3160 case MSR_IA32_MCG_CAP: 3161 case MSR_IA32_MCG_CTL: 3162 case MSR_IA32_MCG_STATUS: 3163 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3164 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 3165 msr_info->host_initiated); 3166 case MSR_IA32_XSS: 3167 if (!msr_info->host_initiated && 3168 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3169 return 1; 3170 msr_info->data = vcpu->arch.ia32_xss; 3171 break; 3172 case MSR_K7_CLK_CTL: 3173 /* 3174 * Provide expected ramp-up count for K7. All other 3175 * are set to zero, indicating minimum divisors for 3176 * every field. 3177 * 3178 * This prevents guest kernels on AMD host with CPU 3179 * type 6, model 8 and higher from exploding due to 3180 * the rdmsr failing. 3181 */ 3182 msr_info->data = 0x20000000; 3183 break; 3184 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3185 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3186 case HV_X64_MSR_CRASH_CTL: 3187 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3188 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3189 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3190 case HV_X64_MSR_TSC_EMULATION_STATUS: 3191 return kvm_hv_get_msr_common(vcpu, 3192 msr_info->index, &msr_info->data, 3193 msr_info->host_initiated); 3194 case MSR_IA32_BBL_CR_CTL3: 3195 /* This legacy MSR exists but isn't fully documented in current 3196 * silicon. It is however accessed by winxp in very narrow 3197 * scenarios where it sets bit #19, itself documented as 3198 * a "reserved" bit. Best effort attempt to source coherent 3199 * read data here should the balance of the register be 3200 * interpreted by the guest: 3201 * 3202 * L2 cache control register 3: 64GB range, 256KB size, 3203 * enabled, latency 0x1, configured 3204 */ 3205 msr_info->data = 0xbe702111; 3206 break; 3207 case MSR_AMD64_OSVW_ID_LENGTH: 3208 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3209 return 1; 3210 msr_info->data = vcpu->arch.osvw.length; 3211 break; 3212 case MSR_AMD64_OSVW_STATUS: 3213 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3214 return 1; 3215 msr_info->data = vcpu->arch.osvw.status; 3216 break; 3217 case MSR_PLATFORM_INFO: 3218 if (!msr_info->host_initiated && 3219 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 3220 return 1; 3221 msr_info->data = vcpu->arch.msr_platform_info; 3222 break; 3223 case MSR_MISC_FEATURES_ENABLES: 3224 msr_info->data = vcpu->arch.msr_misc_features_enables; 3225 break; 3226 case MSR_K7_HWCR: 3227 msr_info->data = vcpu->arch.msr_hwcr; 3228 break; 3229 default: 3230 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3231 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 3232 if (!ignore_msrs) { 3233 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n", 3234 msr_info->index); 3235 return 1; 3236 } else { 3237 if (report_ignored_msrs) 3238 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", 3239 msr_info->index); 3240 msr_info->data = 0; 3241 } 3242 break; 3243 } 3244 return 0; 3245 } 3246 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 3247 3248 /* 3249 * Read or write a bunch of msrs. All parameters are kernel addresses. 3250 * 3251 * @return number of msrs set successfully. 3252 */ 3253 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 3254 struct kvm_msr_entry *entries, 3255 int (*do_msr)(struct kvm_vcpu *vcpu, 3256 unsigned index, u64 *data)) 3257 { 3258 int i; 3259 3260 for (i = 0; i < msrs->nmsrs; ++i) 3261 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 3262 break; 3263 3264 return i; 3265 } 3266 3267 /* 3268 * Read or write a bunch of msrs. Parameters are user addresses. 3269 * 3270 * @return number of msrs set successfully. 3271 */ 3272 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 3273 int (*do_msr)(struct kvm_vcpu *vcpu, 3274 unsigned index, u64 *data), 3275 int writeback) 3276 { 3277 struct kvm_msrs msrs; 3278 struct kvm_msr_entry *entries; 3279 int r, n; 3280 unsigned size; 3281 3282 r = -EFAULT; 3283 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 3284 goto out; 3285 3286 r = -E2BIG; 3287 if (msrs.nmsrs >= MAX_IO_MSRS) 3288 goto out; 3289 3290 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 3291 entries = memdup_user(user_msrs->entries, size); 3292 if (IS_ERR(entries)) { 3293 r = PTR_ERR(entries); 3294 goto out; 3295 } 3296 3297 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 3298 if (r < 0) 3299 goto out_free; 3300 3301 r = -EFAULT; 3302 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 3303 goto out_free; 3304 3305 r = n; 3306 3307 out_free: 3308 kfree(entries); 3309 out: 3310 return r; 3311 } 3312 3313 static inline bool kvm_can_mwait_in_guest(void) 3314 { 3315 return boot_cpu_has(X86_FEATURE_MWAIT) && 3316 !boot_cpu_has_bug(X86_BUG_MONITOR) && 3317 boot_cpu_has(X86_FEATURE_ARAT); 3318 } 3319 3320 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 3321 { 3322 int r = 0; 3323 3324 switch (ext) { 3325 case KVM_CAP_IRQCHIP: 3326 case KVM_CAP_HLT: 3327 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 3328 case KVM_CAP_SET_TSS_ADDR: 3329 case KVM_CAP_EXT_CPUID: 3330 case KVM_CAP_EXT_EMUL_CPUID: 3331 case KVM_CAP_CLOCKSOURCE: 3332 case KVM_CAP_PIT: 3333 case KVM_CAP_NOP_IO_DELAY: 3334 case KVM_CAP_MP_STATE: 3335 case KVM_CAP_SYNC_MMU: 3336 case KVM_CAP_USER_NMI: 3337 case KVM_CAP_REINJECT_CONTROL: 3338 case KVM_CAP_IRQ_INJECT_STATUS: 3339 case KVM_CAP_IOEVENTFD: 3340 case KVM_CAP_IOEVENTFD_NO_LENGTH: 3341 case KVM_CAP_PIT2: 3342 case KVM_CAP_PIT_STATE2: 3343 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 3344 case KVM_CAP_XEN_HVM: 3345 case KVM_CAP_VCPU_EVENTS: 3346 case KVM_CAP_HYPERV: 3347 case KVM_CAP_HYPERV_VAPIC: 3348 case KVM_CAP_HYPERV_SPIN: 3349 case KVM_CAP_HYPERV_SYNIC: 3350 case KVM_CAP_HYPERV_SYNIC2: 3351 case KVM_CAP_HYPERV_VP_INDEX: 3352 case KVM_CAP_HYPERV_EVENTFD: 3353 case KVM_CAP_HYPERV_TLBFLUSH: 3354 case KVM_CAP_HYPERV_SEND_IPI: 3355 case KVM_CAP_HYPERV_CPUID: 3356 case KVM_CAP_PCI_SEGMENT: 3357 case KVM_CAP_DEBUGREGS: 3358 case KVM_CAP_X86_ROBUST_SINGLESTEP: 3359 case KVM_CAP_XSAVE: 3360 case KVM_CAP_ASYNC_PF: 3361 case KVM_CAP_GET_TSC_KHZ: 3362 case KVM_CAP_KVMCLOCK_CTRL: 3363 case KVM_CAP_READONLY_MEM: 3364 case KVM_CAP_HYPERV_TIME: 3365 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 3366 case KVM_CAP_TSC_DEADLINE_TIMER: 3367 case KVM_CAP_DISABLE_QUIRKS: 3368 case KVM_CAP_SET_BOOT_CPU_ID: 3369 case KVM_CAP_SPLIT_IRQCHIP: 3370 case KVM_CAP_IMMEDIATE_EXIT: 3371 case KVM_CAP_PMU_EVENT_FILTER: 3372 case KVM_CAP_GET_MSR_FEATURES: 3373 case KVM_CAP_MSR_PLATFORM_INFO: 3374 case KVM_CAP_EXCEPTION_PAYLOAD: 3375 case KVM_CAP_SET_GUEST_DEBUG: 3376 r = 1; 3377 break; 3378 case KVM_CAP_SYNC_REGS: 3379 r = KVM_SYNC_X86_VALID_FIELDS; 3380 break; 3381 case KVM_CAP_ADJUST_CLOCK: 3382 r = KVM_CLOCK_TSC_STABLE; 3383 break; 3384 case KVM_CAP_X86_DISABLE_EXITS: 3385 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | 3386 KVM_X86_DISABLE_EXITS_CSTATE; 3387 if(kvm_can_mwait_in_guest()) 3388 r |= KVM_X86_DISABLE_EXITS_MWAIT; 3389 break; 3390 case KVM_CAP_X86_SMM: 3391 /* SMBASE is usually relocated above 1M on modern chipsets, 3392 * and SMM handlers might indeed rely on 4G segment limits, 3393 * so do not report SMM to be available if real mode is 3394 * emulated via vm86 mode. Still, do not go to great lengths 3395 * to avoid userspace's usage of the feature, because it is a 3396 * fringe case that is not enabled except via specific settings 3397 * of the module parameters. 3398 */ 3399 r = kvm_x86_ops.has_emulated_msr(MSR_IA32_SMBASE); 3400 break; 3401 case KVM_CAP_VAPIC: 3402 r = !kvm_x86_ops.cpu_has_accelerated_tpr(); 3403 break; 3404 case KVM_CAP_NR_VCPUS: 3405 r = KVM_SOFT_MAX_VCPUS; 3406 break; 3407 case KVM_CAP_MAX_VCPUS: 3408 r = KVM_MAX_VCPUS; 3409 break; 3410 case KVM_CAP_MAX_VCPU_ID: 3411 r = KVM_MAX_VCPU_ID; 3412 break; 3413 case KVM_CAP_PV_MMU: /* obsolete */ 3414 r = 0; 3415 break; 3416 case KVM_CAP_MCE: 3417 r = KVM_MAX_MCE_BANKS; 3418 break; 3419 case KVM_CAP_XCRS: 3420 r = boot_cpu_has(X86_FEATURE_XSAVE); 3421 break; 3422 case KVM_CAP_TSC_CONTROL: 3423 r = kvm_has_tsc_control; 3424 break; 3425 case KVM_CAP_X2APIC_API: 3426 r = KVM_X2APIC_API_VALID_FLAGS; 3427 break; 3428 case KVM_CAP_NESTED_STATE: 3429 r = kvm_x86_ops.get_nested_state ? 3430 kvm_x86_ops.get_nested_state(NULL, NULL, 0) : 0; 3431 break; 3432 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 3433 r = kvm_x86_ops.enable_direct_tlbflush != NULL; 3434 break; 3435 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 3436 r = kvm_x86_ops.nested_enable_evmcs != NULL; 3437 break; 3438 default: 3439 break; 3440 } 3441 return r; 3442 3443 } 3444 3445 long kvm_arch_dev_ioctl(struct file *filp, 3446 unsigned int ioctl, unsigned long arg) 3447 { 3448 void __user *argp = (void __user *)arg; 3449 long r; 3450 3451 switch (ioctl) { 3452 case KVM_GET_MSR_INDEX_LIST: { 3453 struct kvm_msr_list __user *user_msr_list = argp; 3454 struct kvm_msr_list msr_list; 3455 unsigned n; 3456 3457 r = -EFAULT; 3458 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3459 goto out; 3460 n = msr_list.nmsrs; 3461 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 3462 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3463 goto out; 3464 r = -E2BIG; 3465 if (n < msr_list.nmsrs) 3466 goto out; 3467 r = -EFAULT; 3468 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 3469 num_msrs_to_save * sizeof(u32))) 3470 goto out; 3471 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 3472 &emulated_msrs, 3473 num_emulated_msrs * sizeof(u32))) 3474 goto out; 3475 r = 0; 3476 break; 3477 } 3478 case KVM_GET_SUPPORTED_CPUID: 3479 case KVM_GET_EMULATED_CPUID: { 3480 struct kvm_cpuid2 __user *cpuid_arg = argp; 3481 struct kvm_cpuid2 cpuid; 3482 3483 r = -EFAULT; 3484 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3485 goto out; 3486 3487 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 3488 ioctl); 3489 if (r) 3490 goto out; 3491 3492 r = -EFAULT; 3493 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 3494 goto out; 3495 r = 0; 3496 break; 3497 } 3498 case KVM_X86_GET_MCE_CAP_SUPPORTED: 3499 r = -EFAULT; 3500 if (copy_to_user(argp, &kvm_mce_cap_supported, 3501 sizeof(kvm_mce_cap_supported))) 3502 goto out; 3503 r = 0; 3504 break; 3505 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 3506 struct kvm_msr_list __user *user_msr_list = argp; 3507 struct kvm_msr_list msr_list; 3508 unsigned int n; 3509 3510 r = -EFAULT; 3511 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3512 goto out; 3513 n = msr_list.nmsrs; 3514 msr_list.nmsrs = num_msr_based_features; 3515 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3516 goto out; 3517 r = -E2BIG; 3518 if (n < msr_list.nmsrs) 3519 goto out; 3520 r = -EFAULT; 3521 if (copy_to_user(user_msr_list->indices, &msr_based_features, 3522 num_msr_based_features * sizeof(u32))) 3523 goto out; 3524 r = 0; 3525 break; 3526 } 3527 case KVM_GET_MSRS: 3528 r = msr_io(NULL, argp, do_get_msr_feature, 1); 3529 break; 3530 default: 3531 r = -EINVAL; 3532 break; 3533 } 3534 out: 3535 return r; 3536 } 3537 3538 static void wbinvd_ipi(void *garbage) 3539 { 3540 wbinvd(); 3541 } 3542 3543 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 3544 { 3545 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 3546 } 3547 3548 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 3549 { 3550 /* Address WBINVD may be executed by guest */ 3551 if (need_emulate_wbinvd(vcpu)) { 3552 if (kvm_x86_ops.has_wbinvd_exit()) 3553 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 3554 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 3555 smp_call_function_single(vcpu->cpu, 3556 wbinvd_ipi, NULL, 1); 3557 } 3558 3559 kvm_x86_ops.vcpu_load(vcpu, cpu); 3560 3561 /* Apply any externally detected TSC adjustments (due to suspend) */ 3562 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 3563 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 3564 vcpu->arch.tsc_offset_adjustment = 0; 3565 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3566 } 3567 3568 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 3569 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 3570 rdtsc() - vcpu->arch.last_host_tsc; 3571 if (tsc_delta < 0) 3572 mark_tsc_unstable("KVM discovered backwards TSC"); 3573 3574 if (kvm_check_tsc_unstable()) { 3575 u64 offset = kvm_compute_tsc_offset(vcpu, 3576 vcpu->arch.last_guest_tsc); 3577 kvm_vcpu_write_tsc_offset(vcpu, offset); 3578 vcpu->arch.tsc_catchup = 1; 3579 } 3580 3581 if (kvm_lapic_hv_timer_in_use(vcpu)) 3582 kvm_lapic_restart_hv_timer(vcpu); 3583 3584 /* 3585 * On a host with synchronized TSC, there is no need to update 3586 * kvmclock on vcpu->cpu migration 3587 */ 3588 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 3589 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 3590 if (vcpu->cpu != cpu) 3591 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 3592 vcpu->cpu = cpu; 3593 } 3594 3595 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3596 } 3597 3598 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 3599 { 3600 struct kvm_host_map map; 3601 struct kvm_steal_time *st; 3602 3603 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3604 return; 3605 3606 if (vcpu->arch.st.preempted) 3607 return; 3608 3609 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, 3610 &vcpu->arch.st.cache, true)) 3611 return; 3612 3613 st = map.hva + 3614 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 3615 3616 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 3617 3618 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); 3619 } 3620 3621 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 3622 { 3623 int idx; 3624 3625 if (vcpu->preempted) 3626 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu); 3627 3628 /* 3629 * Disable page faults because we're in atomic context here. 3630 * kvm_write_guest_offset_cached() would call might_fault() 3631 * that relies on pagefault_disable() to tell if there's a 3632 * bug. NOTE: the write to guest memory may not go through if 3633 * during postcopy live migration or if there's heavy guest 3634 * paging. 3635 */ 3636 pagefault_disable(); 3637 /* 3638 * kvm_memslots() will be called by 3639 * kvm_write_guest_offset_cached() so take the srcu lock. 3640 */ 3641 idx = srcu_read_lock(&vcpu->kvm->srcu); 3642 kvm_steal_time_set_preempted(vcpu); 3643 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3644 pagefault_enable(); 3645 kvm_x86_ops.vcpu_put(vcpu); 3646 vcpu->arch.last_host_tsc = rdtsc(); 3647 /* 3648 * If userspace has set any breakpoints or watchpoints, dr6 is restored 3649 * on every vmexit, but if not, we might have a stale dr6 from the 3650 * guest. do_debug expects dr6 to be cleared after it runs, do the same. 3651 */ 3652 set_debugreg(0, 6); 3653 } 3654 3655 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 3656 struct kvm_lapic_state *s) 3657 { 3658 if (vcpu->arch.apicv_active) 3659 kvm_x86_ops.sync_pir_to_irr(vcpu); 3660 3661 return kvm_apic_get_state(vcpu, s); 3662 } 3663 3664 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 3665 struct kvm_lapic_state *s) 3666 { 3667 int r; 3668 3669 r = kvm_apic_set_state(vcpu, s); 3670 if (r) 3671 return r; 3672 update_cr8_intercept(vcpu); 3673 3674 return 0; 3675 } 3676 3677 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 3678 { 3679 return (!lapic_in_kernel(vcpu) || 3680 kvm_apic_accept_pic_intr(vcpu)); 3681 } 3682 3683 /* 3684 * if userspace requested an interrupt window, check that the 3685 * interrupt window is open. 3686 * 3687 * No need to exit to userspace if we already have an interrupt queued. 3688 */ 3689 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 3690 { 3691 return kvm_arch_interrupt_allowed(vcpu) && 3692 !kvm_cpu_has_interrupt(vcpu) && 3693 !kvm_event_needs_reinjection(vcpu) && 3694 kvm_cpu_accept_dm_intr(vcpu); 3695 } 3696 3697 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 3698 struct kvm_interrupt *irq) 3699 { 3700 if (irq->irq >= KVM_NR_INTERRUPTS) 3701 return -EINVAL; 3702 3703 if (!irqchip_in_kernel(vcpu->kvm)) { 3704 kvm_queue_interrupt(vcpu, irq->irq, false); 3705 kvm_make_request(KVM_REQ_EVENT, vcpu); 3706 return 0; 3707 } 3708 3709 /* 3710 * With in-kernel LAPIC, we only use this to inject EXTINT, so 3711 * fail for in-kernel 8259. 3712 */ 3713 if (pic_in_kernel(vcpu->kvm)) 3714 return -ENXIO; 3715 3716 if (vcpu->arch.pending_external_vector != -1) 3717 return -EEXIST; 3718 3719 vcpu->arch.pending_external_vector = irq->irq; 3720 kvm_make_request(KVM_REQ_EVENT, vcpu); 3721 return 0; 3722 } 3723 3724 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 3725 { 3726 kvm_inject_nmi(vcpu); 3727 3728 return 0; 3729 } 3730 3731 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 3732 { 3733 kvm_make_request(KVM_REQ_SMI, vcpu); 3734 3735 return 0; 3736 } 3737 3738 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 3739 struct kvm_tpr_access_ctl *tac) 3740 { 3741 if (tac->flags) 3742 return -EINVAL; 3743 vcpu->arch.tpr_access_reporting = !!tac->enabled; 3744 return 0; 3745 } 3746 3747 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 3748 u64 mcg_cap) 3749 { 3750 int r; 3751 unsigned bank_num = mcg_cap & 0xff, bank; 3752 3753 r = -EINVAL; 3754 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 3755 goto out; 3756 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 3757 goto out; 3758 r = 0; 3759 vcpu->arch.mcg_cap = mcg_cap; 3760 /* Init IA32_MCG_CTL to all 1s */ 3761 if (mcg_cap & MCG_CTL_P) 3762 vcpu->arch.mcg_ctl = ~(u64)0; 3763 /* Init IA32_MCi_CTL to all 1s */ 3764 for (bank = 0; bank < bank_num; bank++) 3765 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 3766 3767 kvm_x86_ops.setup_mce(vcpu); 3768 out: 3769 return r; 3770 } 3771 3772 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 3773 struct kvm_x86_mce *mce) 3774 { 3775 u64 mcg_cap = vcpu->arch.mcg_cap; 3776 unsigned bank_num = mcg_cap & 0xff; 3777 u64 *banks = vcpu->arch.mce_banks; 3778 3779 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 3780 return -EINVAL; 3781 /* 3782 * if IA32_MCG_CTL is not all 1s, the uncorrected error 3783 * reporting is disabled 3784 */ 3785 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 3786 vcpu->arch.mcg_ctl != ~(u64)0) 3787 return 0; 3788 banks += 4 * mce->bank; 3789 /* 3790 * if IA32_MCi_CTL is not all 1s, the uncorrected error 3791 * reporting is disabled for the bank 3792 */ 3793 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 3794 return 0; 3795 if (mce->status & MCI_STATUS_UC) { 3796 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 3797 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 3798 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 3799 return 0; 3800 } 3801 if (banks[1] & MCI_STATUS_VAL) 3802 mce->status |= MCI_STATUS_OVER; 3803 banks[2] = mce->addr; 3804 banks[3] = mce->misc; 3805 vcpu->arch.mcg_status = mce->mcg_status; 3806 banks[1] = mce->status; 3807 kvm_queue_exception(vcpu, MC_VECTOR); 3808 } else if (!(banks[1] & MCI_STATUS_VAL) 3809 || !(banks[1] & MCI_STATUS_UC)) { 3810 if (banks[1] & MCI_STATUS_VAL) 3811 mce->status |= MCI_STATUS_OVER; 3812 banks[2] = mce->addr; 3813 banks[3] = mce->misc; 3814 banks[1] = mce->status; 3815 } else 3816 banks[1] |= MCI_STATUS_OVER; 3817 return 0; 3818 } 3819 3820 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 3821 struct kvm_vcpu_events *events) 3822 { 3823 process_nmi(vcpu); 3824 3825 /* 3826 * In guest mode, payload delivery should be deferred, 3827 * so that the L1 hypervisor can intercept #PF before 3828 * CR2 is modified (or intercept #DB before DR6 is 3829 * modified under nVMX). Unless the per-VM capability, 3830 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of 3831 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we 3832 * opportunistically defer the exception payload, deliver it if the 3833 * capability hasn't been requested before processing a 3834 * KVM_GET_VCPU_EVENTS. 3835 */ 3836 if (!vcpu->kvm->arch.exception_payload_enabled && 3837 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) 3838 kvm_deliver_exception_payload(vcpu); 3839 3840 /* 3841 * The API doesn't provide the instruction length for software 3842 * exceptions, so don't report them. As long as the guest RIP 3843 * isn't advanced, we should expect to encounter the exception 3844 * again. 3845 */ 3846 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 3847 events->exception.injected = 0; 3848 events->exception.pending = 0; 3849 } else { 3850 events->exception.injected = vcpu->arch.exception.injected; 3851 events->exception.pending = vcpu->arch.exception.pending; 3852 /* 3853 * For ABI compatibility, deliberately conflate 3854 * pending and injected exceptions when 3855 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 3856 */ 3857 if (!vcpu->kvm->arch.exception_payload_enabled) 3858 events->exception.injected |= 3859 vcpu->arch.exception.pending; 3860 } 3861 events->exception.nr = vcpu->arch.exception.nr; 3862 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 3863 events->exception.error_code = vcpu->arch.exception.error_code; 3864 events->exception_has_payload = vcpu->arch.exception.has_payload; 3865 events->exception_payload = vcpu->arch.exception.payload; 3866 3867 events->interrupt.injected = 3868 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 3869 events->interrupt.nr = vcpu->arch.interrupt.nr; 3870 events->interrupt.soft = 0; 3871 events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu); 3872 3873 events->nmi.injected = vcpu->arch.nmi_injected; 3874 events->nmi.pending = vcpu->arch.nmi_pending != 0; 3875 events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu); 3876 events->nmi.pad = 0; 3877 3878 events->sipi_vector = 0; /* never valid when reporting to user space */ 3879 3880 events->smi.smm = is_smm(vcpu); 3881 events->smi.pending = vcpu->arch.smi_pending; 3882 events->smi.smm_inside_nmi = 3883 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 3884 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 3885 3886 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 3887 | KVM_VCPUEVENT_VALID_SHADOW 3888 | KVM_VCPUEVENT_VALID_SMM); 3889 if (vcpu->kvm->arch.exception_payload_enabled) 3890 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 3891 3892 memset(&events->reserved, 0, sizeof(events->reserved)); 3893 } 3894 3895 static void kvm_smm_changed(struct kvm_vcpu *vcpu); 3896 3897 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 3898 struct kvm_vcpu_events *events) 3899 { 3900 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 3901 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 3902 | KVM_VCPUEVENT_VALID_SHADOW 3903 | KVM_VCPUEVENT_VALID_SMM 3904 | KVM_VCPUEVENT_VALID_PAYLOAD)) 3905 return -EINVAL; 3906 3907 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 3908 if (!vcpu->kvm->arch.exception_payload_enabled) 3909 return -EINVAL; 3910 if (events->exception.pending) 3911 events->exception.injected = 0; 3912 else 3913 events->exception_has_payload = 0; 3914 } else { 3915 events->exception.pending = 0; 3916 events->exception_has_payload = 0; 3917 } 3918 3919 if ((events->exception.injected || events->exception.pending) && 3920 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 3921 return -EINVAL; 3922 3923 /* INITs are latched while in SMM */ 3924 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 3925 (events->smi.smm || events->smi.pending) && 3926 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 3927 return -EINVAL; 3928 3929 process_nmi(vcpu); 3930 vcpu->arch.exception.injected = events->exception.injected; 3931 vcpu->arch.exception.pending = events->exception.pending; 3932 vcpu->arch.exception.nr = events->exception.nr; 3933 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 3934 vcpu->arch.exception.error_code = events->exception.error_code; 3935 vcpu->arch.exception.has_payload = events->exception_has_payload; 3936 vcpu->arch.exception.payload = events->exception_payload; 3937 3938 vcpu->arch.interrupt.injected = events->interrupt.injected; 3939 vcpu->arch.interrupt.nr = events->interrupt.nr; 3940 vcpu->arch.interrupt.soft = events->interrupt.soft; 3941 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3942 kvm_x86_ops.set_interrupt_shadow(vcpu, 3943 events->interrupt.shadow); 3944 3945 vcpu->arch.nmi_injected = events->nmi.injected; 3946 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3947 vcpu->arch.nmi_pending = events->nmi.pending; 3948 kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked); 3949 3950 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3951 lapic_in_kernel(vcpu)) 3952 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3953 3954 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 3955 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { 3956 if (events->smi.smm) 3957 vcpu->arch.hflags |= HF_SMM_MASK; 3958 else 3959 vcpu->arch.hflags &= ~HF_SMM_MASK; 3960 kvm_smm_changed(vcpu); 3961 } 3962 3963 vcpu->arch.smi_pending = events->smi.pending; 3964 3965 if (events->smi.smm) { 3966 if (events->smi.smm_inside_nmi) 3967 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 3968 else 3969 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 3970 } 3971 3972 if (lapic_in_kernel(vcpu)) { 3973 if (events->smi.latched_init) 3974 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3975 else 3976 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3977 } 3978 } 3979 3980 kvm_make_request(KVM_REQ_EVENT, vcpu); 3981 3982 return 0; 3983 } 3984 3985 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3986 struct kvm_debugregs *dbgregs) 3987 { 3988 unsigned long val; 3989 3990 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3991 kvm_get_dr(vcpu, 6, &val); 3992 dbgregs->dr6 = val; 3993 dbgregs->dr7 = vcpu->arch.dr7; 3994 dbgregs->flags = 0; 3995 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3996 } 3997 3998 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3999 struct kvm_debugregs *dbgregs) 4000 { 4001 if (dbgregs->flags) 4002 return -EINVAL; 4003 4004 if (dbgregs->dr6 & ~0xffffffffull) 4005 return -EINVAL; 4006 if (dbgregs->dr7 & ~0xffffffffull) 4007 return -EINVAL; 4008 4009 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 4010 kvm_update_dr0123(vcpu); 4011 vcpu->arch.dr6 = dbgregs->dr6; 4012 kvm_update_dr6(vcpu); 4013 vcpu->arch.dr7 = dbgregs->dr7; 4014 kvm_update_dr7(vcpu); 4015 4016 return 0; 4017 } 4018 4019 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 4020 4021 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 4022 { 4023 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 4024 u64 xstate_bv = xsave->header.xfeatures; 4025 u64 valid; 4026 4027 /* 4028 * Copy legacy XSAVE area, to avoid complications with CPUID 4029 * leaves 0 and 1 in the loop below. 4030 */ 4031 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 4032 4033 /* Set XSTATE_BV */ 4034 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; 4035 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 4036 4037 /* 4038 * Copy each region from the possibly compacted offset to the 4039 * non-compacted offset. 4040 */ 4041 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 4042 while (valid) { 4043 u64 xfeature_mask = valid & -valid; 4044 int xfeature_nr = fls64(xfeature_mask) - 1; 4045 void *src = get_xsave_addr(xsave, xfeature_nr); 4046 4047 if (src) { 4048 u32 size, offset, ecx, edx; 4049 cpuid_count(XSTATE_CPUID, xfeature_nr, 4050 &size, &offset, &ecx, &edx); 4051 if (xfeature_nr == XFEATURE_PKRU) 4052 memcpy(dest + offset, &vcpu->arch.pkru, 4053 sizeof(vcpu->arch.pkru)); 4054 else 4055 memcpy(dest + offset, src, size); 4056 4057 } 4058 4059 valid -= xfeature_mask; 4060 } 4061 } 4062 4063 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 4064 { 4065 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 4066 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 4067 u64 valid; 4068 4069 /* 4070 * Copy legacy XSAVE area, to avoid complications with CPUID 4071 * leaves 0 and 1 in the loop below. 4072 */ 4073 memcpy(xsave, src, XSAVE_HDR_OFFSET); 4074 4075 /* Set XSTATE_BV and possibly XCOMP_BV. */ 4076 xsave->header.xfeatures = xstate_bv; 4077 if (boot_cpu_has(X86_FEATURE_XSAVES)) 4078 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 4079 4080 /* 4081 * Copy each region from the non-compacted offset to the 4082 * possibly compacted offset. 4083 */ 4084 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 4085 while (valid) { 4086 u64 xfeature_mask = valid & -valid; 4087 int xfeature_nr = fls64(xfeature_mask) - 1; 4088 void *dest = get_xsave_addr(xsave, xfeature_nr); 4089 4090 if (dest) { 4091 u32 size, offset, ecx, edx; 4092 cpuid_count(XSTATE_CPUID, xfeature_nr, 4093 &size, &offset, &ecx, &edx); 4094 if (xfeature_nr == XFEATURE_PKRU) 4095 memcpy(&vcpu->arch.pkru, src + offset, 4096 sizeof(vcpu->arch.pkru)); 4097 else 4098 memcpy(dest, src + offset, size); 4099 } 4100 4101 valid -= xfeature_mask; 4102 } 4103 } 4104 4105 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 4106 struct kvm_xsave *guest_xsave) 4107 { 4108 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 4109 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 4110 fill_xsave((u8 *) guest_xsave->region, vcpu); 4111 } else { 4112 memcpy(guest_xsave->region, 4113 &vcpu->arch.guest_fpu->state.fxsave, 4114 sizeof(struct fxregs_state)); 4115 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 4116 XFEATURE_MASK_FPSSE; 4117 } 4118 } 4119 4120 #define XSAVE_MXCSR_OFFSET 24 4121 4122 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 4123 struct kvm_xsave *guest_xsave) 4124 { 4125 u64 xstate_bv = 4126 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 4127 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; 4128 4129 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 4130 /* 4131 * Here we allow setting states that are not present in 4132 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 4133 * with old userspace. 4134 */ 4135 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask) 4136 return -EINVAL; 4137 load_xsave(vcpu, (u8 *)guest_xsave->region); 4138 } else { 4139 if (xstate_bv & ~XFEATURE_MASK_FPSSE || 4140 mxcsr & ~mxcsr_feature_mask) 4141 return -EINVAL; 4142 memcpy(&vcpu->arch.guest_fpu->state.fxsave, 4143 guest_xsave->region, sizeof(struct fxregs_state)); 4144 } 4145 return 0; 4146 } 4147 4148 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 4149 struct kvm_xcrs *guest_xcrs) 4150 { 4151 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 4152 guest_xcrs->nr_xcrs = 0; 4153 return; 4154 } 4155 4156 guest_xcrs->nr_xcrs = 1; 4157 guest_xcrs->flags = 0; 4158 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 4159 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 4160 } 4161 4162 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 4163 struct kvm_xcrs *guest_xcrs) 4164 { 4165 int i, r = 0; 4166 4167 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 4168 return -EINVAL; 4169 4170 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 4171 return -EINVAL; 4172 4173 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 4174 /* Only support XCR0 currently */ 4175 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 4176 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 4177 guest_xcrs->xcrs[i].value); 4178 break; 4179 } 4180 if (r) 4181 r = -EINVAL; 4182 return r; 4183 } 4184 4185 /* 4186 * kvm_set_guest_paused() indicates to the guest kernel that it has been 4187 * stopped by the hypervisor. This function will be called from the host only. 4188 * EINVAL is returned when the host attempts to set the flag for a guest that 4189 * does not support pv clocks. 4190 */ 4191 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 4192 { 4193 if (!vcpu->arch.pv_time_enabled) 4194 return -EINVAL; 4195 vcpu->arch.pvclock_set_guest_stopped_request = true; 4196 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4197 return 0; 4198 } 4199 4200 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 4201 struct kvm_enable_cap *cap) 4202 { 4203 int r; 4204 uint16_t vmcs_version; 4205 void __user *user_ptr; 4206 4207 if (cap->flags) 4208 return -EINVAL; 4209 4210 switch (cap->cap) { 4211 case KVM_CAP_HYPERV_SYNIC2: 4212 if (cap->args[0]) 4213 return -EINVAL; 4214 /* fall through */ 4215 4216 case KVM_CAP_HYPERV_SYNIC: 4217 if (!irqchip_in_kernel(vcpu->kvm)) 4218 return -EINVAL; 4219 return kvm_hv_activate_synic(vcpu, cap->cap == 4220 KVM_CAP_HYPERV_SYNIC2); 4221 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4222 if (!kvm_x86_ops.nested_enable_evmcs) 4223 return -ENOTTY; 4224 r = kvm_x86_ops.nested_enable_evmcs(vcpu, &vmcs_version); 4225 if (!r) { 4226 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 4227 if (copy_to_user(user_ptr, &vmcs_version, 4228 sizeof(vmcs_version))) 4229 r = -EFAULT; 4230 } 4231 return r; 4232 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4233 if (!kvm_x86_ops.enable_direct_tlbflush) 4234 return -ENOTTY; 4235 4236 return kvm_x86_ops.enable_direct_tlbflush(vcpu); 4237 4238 default: 4239 return -EINVAL; 4240 } 4241 } 4242 4243 long kvm_arch_vcpu_ioctl(struct file *filp, 4244 unsigned int ioctl, unsigned long arg) 4245 { 4246 struct kvm_vcpu *vcpu = filp->private_data; 4247 void __user *argp = (void __user *)arg; 4248 int r; 4249 union { 4250 struct kvm_lapic_state *lapic; 4251 struct kvm_xsave *xsave; 4252 struct kvm_xcrs *xcrs; 4253 void *buffer; 4254 } u; 4255 4256 vcpu_load(vcpu); 4257 4258 u.buffer = NULL; 4259 switch (ioctl) { 4260 case KVM_GET_LAPIC: { 4261 r = -EINVAL; 4262 if (!lapic_in_kernel(vcpu)) 4263 goto out; 4264 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 4265 GFP_KERNEL_ACCOUNT); 4266 4267 r = -ENOMEM; 4268 if (!u.lapic) 4269 goto out; 4270 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 4271 if (r) 4272 goto out; 4273 r = -EFAULT; 4274 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 4275 goto out; 4276 r = 0; 4277 break; 4278 } 4279 case KVM_SET_LAPIC: { 4280 r = -EINVAL; 4281 if (!lapic_in_kernel(vcpu)) 4282 goto out; 4283 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 4284 if (IS_ERR(u.lapic)) { 4285 r = PTR_ERR(u.lapic); 4286 goto out_nofree; 4287 } 4288 4289 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 4290 break; 4291 } 4292 case KVM_INTERRUPT: { 4293 struct kvm_interrupt irq; 4294 4295 r = -EFAULT; 4296 if (copy_from_user(&irq, argp, sizeof(irq))) 4297 goto out; 4298 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 4299 break; 4300 } 4301 case KVM_NMI: { 4302 r = kvm_vcpu_ioctl_nmi(vcpu); 4303 break; 4304 } 4305 case KVM_SMI: { 4306 r = kvm_vcpu_ioctl_smi(vcpu); 4307 break; 4308 } 4309 case KVM_SET_CPUID: { 4310 struct kvm_cpuid __user *cpuid_arg = argp; 4311 struct kvm_cpuid cpuid; 4312 4313 r = -EFAULT; 4314 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4315 goto out; 4316 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 4317 break; 4318 } 4319 case KVM_SET_CPUID2: { 4320 struct kvm_cpuid2 __user *cpuid_arg = argp; 4321 struct kvm_cpuid2 cpuid; 4322 4323 r = -EFAULT; 4324 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4325 goto out; 4326 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 4327 cpuid_arg->entries); 4328 break; 4329 } 4330 case KVM_GET_CPUID2: { 4331 struct kvm_cpuid2 __user *cpuid_arg = argp; 4332 struct kvm_cpuid2 cpuid; 4333 4334 r = -EFAULT; 4335 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4336 goto out; 4337 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 4338 cpuid_arg->entries); 4339 if (r) 4340 goto out; 4341 r = -EFAULT; 4342 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4343 goto out; 4344 r = 0; 4345 break; 4346 } 4347 case KVM_GET_MSRS: { 4348 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4349 r = msr_io(vcpu, argp, do_get_msr, 1); 4350 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4351 break; 4352 } 4353 case KVM_SET_MSRS: { 4354 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4355 r = msr_io(vcpu, argp, do_set_msr, 0); 4356 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4357 break; 4358 } 4359 case KVM_TPR_ACCESS_REPORTING: { 4360 struct kvm_tpr_access_ctl tac; 4361 4362 r = -EFAULT; 4363 if (copy_from_user(&tac, argp, sizeof(tac))) 4364 goto out; 4365 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 4366 if (r) 4367 goto out; 4368 r = -EFAULT; 4369 if (copy_to_user(argp, &tac, sizeof(tac))) 4370 goto out; 4371 r = 0; 4372 break; 4373 }; 4374 case KVM_SET_VAPIC_ADDR: { 4375 struct kvm_vapic_addr va; 4376 int idx; 4377 4378 r = -EINVAL; 4379 if (!lapic_in_kernel(vcpu)) 4380 goto out; 4381 r = -EFAULT; 4382 if (copy_from_user(&va, argp, sizeof(va))) 4383 goto out; 4384 idx = srcu_read_lock(&vcpu->kvm->srcu); 4385 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 4386 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4387 break; 4388 } 4389 case KVM_X86_SETUP_MCE: { 4390 u64 mcg_cap; 4391 4392 r = -EFAULT; 4393 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 4394 goto out; 4395 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 4396 break; 4397 } 4398 case KVM_X86_SET_MCE: { 4399 struct kvm_x86_mce mce; 4400 4401 r = -EFAULT; 4402 if (copy_from_user(&mce, argp, sizeof(mce))) 4403 goto out; 4404 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 4405 break; 4406 } 4407 case KVM_GET_VCPU_EVENTS: { 4408 struct kvm_vcpu_events events; 4409 4410 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 4411 4412 r = -EFAULT; 4413 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 4414 break; 4415 r = 0; 4416 break; 4417 } 4418 case KVM_SET_VCPU_EVENTS: { 4419 struct kvm_vcpu_events events; 4420 4421 r = -EFAULT; 4422 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 4423 break; 4424 4425 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 4426 break; 4427 } 4428 case KVM_GET_DEBUGREGS: { 4429 struct kvm_debugregs dbgregs; 4430 4431 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 4432 4433 r = -EFAULT; 4434 if (copy_to_user(argp, &dbgregs, 4435 sizeof(struct kvm_debugregs))) 4436 break; 4437 r = 0; 4438 break; 4439 } 4440 case KVM_SET_DEBUGREGS: { 4441 struct kvm_debugregs dbgregs; 4442 4443 r = -EFAULT; 4444 if (copy_from_user(&dbgregs, argp, 4445 sizeof(struct kvm_debugregs))) 4446 break; 4447 4448 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 4449 break; 4450 } 4451 case KVM_GET_XSAVE: { 4452 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 4453 r = -ENOMEM; 4454 if (!u.xsave) 4455 break; 4456 4457 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 4458 4459 r = -EFAULT; 4460 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 4461 break; 4462 r = 0; 4463 break; 4464 } 4465 case KVM_SET_XSAVE: { 4466 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 4467 if (IS_ERR(u.xsave)) { 4468 r = PTR_ERR(u.xsave); 4469 goto out_nofree; 4470 } 4471 4472 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 4473 break; 4474 } 4475 case KVM_GET_XCRS: { 4476 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 4477 r = -ENOMEM; 4478 if (!u.xcrs) 4479 break; 4480 4481 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 4482 4483 r = -EFAULT; 4484 if (copy_to_user(argp, u.xcrs, 4485 sizeof(struct kvm_xcrs))) 4486 break; 4487 r = 0; 4488 break; 4489 } 4490 case KVM_SET_XCRS: { 4491 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 4492 if (IS_ERR(u.xcrs)) { 4493 r = PTR_ERR(u.xcrs); 4494 goto out_nofree; 4495 } 4496 4497 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 4498 break; 4499 } 4500 case KVM_SET_TSC_KHZ: { 4501 u32 user_tsc_khz; 4502 4503 r = -EINVAL; 4504 user_tsc_khz = (u32)arg; 4505 4506 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 4507 goto out; 4508 4509 if (user_tsc_khz == 0) 4510 user_tsc_khz = tsc_khz; 4511 4512 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 4513 r = 0; 4514 4515 goto out; 4516 } 4517 case KVM_GET_TSC_KHZ: { 4518 r = vcpu->arch.virtual_tsc_khz; 4519 goto out; 4520 } 4521 case KVM_KVMCLOCK_CTRL: { 4522 r = kvm_set_guest_paused(vcpu); 4523 goto out; 4524 } 4525 case KVM_ENABLE_CAP: { 4526 struct kvm_enable_cap cap; 4527 4528 r = -EFAULT; 4529 if (copy_from_user(&cap, argp, sizeof(cap))) 4530 goto out; 4531 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 4532 break; 4533 } 4534 case KVM_GET_NESTED_STATE: { 4535 struct kvm_nested_state __user *user_kvm_nested_state = argp; 4536 u32 user_data_size; 4537 4538 r = -EINVAL; 4539 if (!kvm_x86_ops.get_nested_state) 4540 break; 4541 4542 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 4543 r = -EFAULT; 4544 if (get_user(user_data_size, &user_kvm_nested_state->size)) 4545 break; 4546 4547 r = kvm_x86_ops.get_nested_state(vcpu, user_kvm_nested_state, 4548 user_data_size); 4549 if (r < 0) 4550 break; 4551 4552 if (r > user_data_size) { 4553 if (put_user(r, &user_kvm_nested_state->size)) 4554 r = -EFAULT; 4555 else 4556 r = -E2BIG; 4557 break; 4558 } 4559 4560 r = 0; 4561 break; 4562 } 4563 case KVM_SET_NESTED_STATE: { 4564 struct kvm_nested_state __user *user_kvm_nested_state = argp; 4565 struct kvm_nested_state kvm_state; 4566 int idx; 4567 4568 r = -EINVAL; 4569 if (!kvm_x86_ops.set_nested_state) 4570 break; 4571 4572 r = -EFAULT; 4573 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 4574 break; 4575 4576 r = -EINVAL; 4577 if (kvm_state.size < sizeof(kvm_state)) 4578 break; 4579 4580 if (kvm_state.flags & 4581 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 4582 | KVM_STATE_NESTED_EVMCS)) 4583 break; 4584 4585 /* nested_run_pending implies guest_mode. */ 4586 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 4587 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 4588 break; 4589 4590 idx = srcu_read_lock(&vcpu->kvm->srcu); 4591 r = kvm_x86_ops.set_nested_state(vcpu, user_kvm_nested_state, &kvm_state); 4592 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4593 break; 4594 } 4595 case KVM_GET_SUPPORTED_HV_CPUID: { 4596 struct kvm_cpuid2 __user *cpuid_arg = argp; 4597 struct kvm_cpuid2 cpuid; 4598 4599 r = -EFAULT; 4600 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4601 goto out; 4602 4603 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid, 4604 cpuid_arg->entries); 4605 if (r) 4606 goto out; 4607 4608 r = -EFAULT; 4609 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4610 goto out; 4611 r = 0; 4612 break; 4613 } 4614 default: 4615 r = -EINVAL; 4616 } 4617 out: 4618 kfree(u.buffer); 4619 out_nofree: 4620 vcpu_put(vcpu); 4621 return r; 4622 } 4623 4624 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 4625 { 4626 return VM_FAULT_SIGBUS; 4627 } 4628 4629 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 4630 { 4631 int ret; 4632 4633 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 4634 return -EINVAL; 4635 ret = kvm_x86_ops.set_tss_addr(kvm, addr); 4636 return ret; 4637 } 4638 4639 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 4640 u64 ident_addr) 4641 { 4642 return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr); 4643 } 4644 4645 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 4646 unsigned long kvm_nr_mmu_pages) 4647 { 4648 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 4649 return -EINVAL; 4650 4651 mutex_lock(&kvm->slots_lock); 4652 4653 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 4654 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 4655 4656 mutex_unlock(&kvm->slots_lock); 4657 return 0; 4658 } 4659 4660 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 4661 { 4662 return kvm->arch.n_max_mmu_pages; 4663 } 4664 4665 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 4666 { 4667 struct kvm_pic *pic = kvm->arch.vpic; 4668 int r; 4669 4670 r = 0; 4671 switch (chip->chip_id) { 4672 case KVM_IRQCHIP_PIC_MASTER: 4673 memcpy(&chip->chip.pic, &pic->pics[0], 4674 sizeof(struct kvm_pic_state)); 4675 break; 4676 case KVM_IRQCHIP_PIC_SLAVE: 4677 memcpy(&chip->chip.pic, &pic->pics[1], 4678 sizeof(struct kvm_pic_state)); 4679 break; 4680 case KVM_IRQCHIP_IOAPIC: 4681 kvm_get_ioapic(kvm, &chip->chip.ioapic); 4682 break; 4683 default: 4684 r = -EINVAL; 4685 break; 4686 } 4687 return r; 4688 } 4689 4690 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 4691 { 4692 struct kvm_pic *pic = kvm->arch.vpic; 4693 int r; 4694 4695 r = 0; 4696 switch (chip->chip_id) { 4697 case KVM_IRQCHIP_PIC_MASTER: 4698 spin_lock(&pic->lock); 4699 memcpy(&pic->pics[0], &chip->chip.pic, 4700 sizeof(struct kvm_pic_state)); 4701 spin_unlock(&pic->lock); 4702 break; 4703 case KVM_IRQCHIP_PIC_SLAVE: 4704 spin_lock(&pic->lock); 4705 memcpy(&pic->pics[1], &chip->chip.pic, 4706 sizeof(struct kvm_pic_state)); 4707 spin_unlock(&pic->lock); 4708 break; 4709 case KVM_IRQCHIP_IOAPIC: 4710 kvm_set_ioapic(kvm, &chip->chip.ioapic); 4711 break; 4712 default: 4713 r = -EINVAL; 4714 break; 4715 } 4716 kvm_pic_update_irq(pic); 4717 return r; 4718 } 4719 4720 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 4721 { 4722 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 4723 4724 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 4725 4726 mutex_lock(&kps->lock); 4727 memcpy(ps, &kps->channels, sizeof(*ps)); 4728 mutex_unlock(&kps->lock); 4729 return 0; 4730 } 4731 4732 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 4733 { 4734 int i; 4735 struct kvm_pit *pit = kvm->arch.vpit; 4736 4737 mutex_lock(&pit->pit_state.lock); 4738 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 4739 for (i = 0; i < 3; i++) 4740 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 4741 mutex_unlock(&pit->pit_state.lock); 4742 return 0; 4743 } 4744 4745 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 4746 { 4747 mutex_lock(&kvm->arch.vpit->pit_state.lock); 4748 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 4749 sizeof(ps->channels)); 4750 ps->flags = kvm->arch.vpit->pit_state.flags; 4751 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 4752 memset(&ps->reserved, 0, sizeof(ps->reserved)); 4753 return 0; 4754 } 4755 4756 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 4757 { 4758 int start = 0; 4759 int i; 4760 u32 prev_legacy, cur_legacy; 4761 struct kvm_pit *pit = kvm->arch.vpit; 4762 4763 mutex_lock(&pit->pit_state.lock); 4764 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 4765 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 4766 if (!prev_legacy && cur_legacy) 4767 start = 1; 4768 memcpy(&pit->pit_state.channels, &ps->channels, 4769 sizeof(pit->pit_state.channels)); 4770 pit->pit_state.flags = ps->flags; 4771 for (i = 0; i < 3; i++) 4772 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 4773 start && i == 0); 4774 mutex_unlock(&pit->pit_state.lock); 4775 return 0; 4776 } 4777 4778 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 4779 struct kvm_reinject_control *control) 4780 { 4781 struct kvm_pit *pit = kvm->arch.vpit; 4782 4783 /* pit->pit_state.lock was overloaded to prevent userspace from getting 4784 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 4785 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 4786 */ 4787 mutex_lock(&pit->pit_state.lock); 4788 kvm_pit_set_reinject(pit, control->pit_reinject); 4789 mutex_unlock(&pit->pit_state.lock); 4790 4791 return 0; 4792 } 4793 4794 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 4795 { 4796 /* 4797 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 4798 */ 4799 if (kvm_x86_ops.flush_log_dirty) 4800 kvm_x86_ops.flush_log_dirty(kvm); 4801 } 4802 4803 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 4804 bool line_status) 4805 { 4806 if (!irqchip_in_kernel(kvm)) 4807 return -ENXIO; 4808 4809 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 4810 irq_event->irq, irq_event->level, 4811 line_status); 4812 return 0; 4813 } 4814 4815 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 4816 struct kvm_enable_cap *cap) 4817 { 4818 int r; 4819 4820 if (cap->flags) 4821 return -EINVAL; 4822 4823 switch (cap->cap) { 4824 case KVM_CAP_DISABLE_QUIRKS: 4825 kvm->arch.disabled_quirks = cap->args[0]; 4826 r = 0; 4827 break; 4828 case KVM_CAP_SPLIT_IRQCHIP: { 4829 mutex_lock(&kvm->lock); 4830 r = -EINVAL; 4831 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 4832 goto split_irqchip_unlock; 4833 r = -EEXIST; 4834 if (irqchip_in_kernel(kvm)) 4835 goto split_irqchip_unlock; 4836 if (kvm->created_vcpus) 4837 goto split_irqchip_unlock; 4838 r = kvm_setup_empty_irq_routing(kvm); 4839 if (r) 4840 goto split_irqchip_unlock; 4841 /* Pairs with irqchip_in_kernel. */ 4842 smp_wmb(); 4843 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 4844 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 4845 r = 0; 4846 split_irqchip_unlock: 4847 mutex_unlock(&kvm->lock); 4848 break; 4849 } 4850 case KVM_CAP_X2APIC_API: 4851 r = -EINVAL; 4852 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 4853 break; 4854 4855 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 4856 kvm->arch.x2apic_format = true; 4857 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 4858 kvm->arch.x2apic_broadcast_quirk_disabled = true; 4859 4860 r = 0; 4861 break; 4862 case KVM_CAP_X86_DISABLE_EXITS: 4863 r = -EINVAL; 4864 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 4865 break; 4866 4867 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 4868 kvm_can_mwait_in_guest()) 4869 kvm->arch.mwait_in_guest = true; 4870 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 4871 kvm->arch.hlt_in_guest = true; 4872 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 4873 kvm->arch.pause_in_guest = true; 4874 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) 4875 kvm->arch.cstate_in_guest = true; 4876 r = 0; 4877 break; 4878 case KVM_CAP_MSR_PLATFORM_INFO: 4879 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 4880 r = 0; 4881 break; 4882 case KVM_CAP_EXCEPTION_PAYLOAD: 4883 kvm->arch.exception_payload_enabled = cap->args[0]; 4884 r = 0; 4885 break; 4886 default: 4887 r = -EINVAL; 4888 break; 4889 } 4890 return r; 4891 } 4892 4893 long kvm_arch_vm_ioctl(struct file *filp, 4894 unsigned int ioctl, unsigned long arg) 4895 { 4896 struct kvm *kvm = filp->private_data; 4897 void __user *argp = (void __user *)arg; 4898 int r = -ENOTTY; 4899 /* 4900 * This union makes it completely explicit to gcc-3.x 4901 * that these two variables' stack usage should be 4902 * combined, not added together. 4903 */ 4904 union { 4905 struct kvm_pit_state ps; 4906 struct kvm_pit_state2 ps2; 4907 struct kvm_pit_config pit_config; 4908 } u; 4909 4910 switch (ioctl) { 4911 case KVM_SET_TSS_ADDR: 4912 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 4913 break; 4914 case KVM_SET_IDENTITY_MAP_ADDR: { 4915 u64 ident_addr; 4916 4917 mutex_lock(&kvm->lock); 4918 r = -EINVAL; 4919 if (kvm->created_vcpus) 4920 goto set_identity_unlock; 4921 r = -EFAULT; 4922 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 4923 goto set_identity_unlock; 4924 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 4925 set_identity_unlock: 4926 mutex_unlock(&kvm->lock); 4927 break; 4928 } 4929 case KVM_SET_NR_MMU_PAGES: 4930 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 4931 break; 4932 case KVM_GET_NR_MMU_PAGES: 4933 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 4934 break; 4935 case KVM_CREATE_IRQCHIP: { 4936 mutex_lock(&kvm->lock); 4937 4938 r = -EEXIST; 4939 if (irqchip_in_kernel(kvm)) 4940 goto create_irqchip_unlock; 4941 4942 r = -EINVAL; 4943 if (kvm->created_vcpus) 4944 goto create_irqchip_unlock; 4945 4946 r = kvm_pic_init(kvm); 4947 if (r) 4948 goto create_irqchip_unlock; 4949 4950 r = kvm_ioapic_init(kvm); 4951 if (r) { 4952 kvm_pic_destroy(kvm); 4953 goto create_irqchip_unlock; 4954 } 4955 4956 r = kvm_setup_default_irq_routing(kvm); 4957 if (r) { 4958 kvm_ioapic_destroy(kvm); 4959 kvm_pic_destroy(kvm); 4960 goto create_irqchip_unlock; 4961 } 4962 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 4963 smp_wmb(); 4964 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 4965 create_irqchip_unlock: 4966 mutex_unlock(&kvm->lock); 4967 break; 4968 } 4969 case KVM_CREATE_PIT: 4970 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 4971 goto create_pit; 4972 case KVM_CREATE_PIT2: 4973 r = -EFAULT; 4974 if (copy_from_user(&u.pit_config, argp, 4975 sizeof(struct kvm_pit_config))) 4976 goto out; 4977 create_pit: 4978 mutex_lock(&kvm->lock); 4979 r = -EEXIST; 4980 if (kvm->arch.vpit) 4981 goto create_pit_unlock; 4982 r = -ENOMEM; 4983 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 4984 if (kvm->arch.vpit) 4985 r = 0; 4986 create_pit_unlock: 4987 mutex_unlock(&kvm->lock); 4988 break; 4989 case KVM_GET_IRQCHIP: { 4990 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4991 struct kvm_irqchip *chip; 4992 4993 chip = memdup_user(argp, sizeof(*chip)); 4994 if (IS_ERR(chip)) { 4995 r = PTR_ERR(chip); 4996 goto out; 4997 } 4998 4999 r = -ENXIO; 5000 if (!irqchip_kernel(kvm)) 5001 goto get_irqchip_out; 5002 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 5003 if (r) 5004 goto get_irqchip_out; 5005 r = -EFAULT; 5006 if (copy_to_user(argp, chip, sizeof(*chip))) 5007 goto get_irqchip_out; 5008 r = 0; 5009 get_irqchip_out: 5010 kfree(chip); 5011 break; 5012 } 5013 case KVM_SET_IRQCHIP: { 5014 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 5015 struct kvm_irqchip *chip; 5016 5017 chip = memdup_user(argp, sizeof(*chip)); 5018 if (IS_ERR(chip)) { 5019 r = PTR_ERR(chip); 5020 goto out; 5021 } 5022 5023 r = -ENXIO; 5024 if (!irqchip_kernel(kvm)) 5025 goto set_irqchip_out; 5026 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 5027 set_irqchip_out: 5028 kfree(chip); 5029 break; 5030 } 5031 case KVM_GET_PIT: { 5032 r = -EFAULT; 5033 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 5034 goto out; 5035 r = -ENXIO; 5036 if (!kvm->arch.vpit) 5037 goto out; 5038 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 5039 if (r) 5040 goto out; 5041 r = -EFAULT; 5042 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 5043 goto out; 5044 r = 0; 5045 break; 5046 } 5047 case KVM_SET_PIT: { 5048 r = -EFAULT; 5049 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 5050 goto out; 5051 mutex_lock(&kvm->lock); 5052 r = -ENXIO; 5053 if (!kvm->arch.vpit) 5054 goto set_pit_out; 5055 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 5056 set_pit_out: 5057 mutex_unlock(&kvm->lock); 5058 break; 5059 } 5060 case KVM_GET_PIT2: { 5061 r = -ENXIO; 5062 if (!kvm->arch.vpit) 5063 goto out; 5064 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 5065 if (r) 5066 goto out; 5067 r = -EFAULT; 5068 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 5069 goto out; 5070 r = 0; 5071 break; 5072 } 5073 case KVM_SET_PIT2: { 5074 r = -EFAULT; 5075 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 5076 goto out; 5077 mutex_lock(&kvm->lock); 5078 r = -ENXIO; 5079 if (!kvm->arch.vpit) 5080 goto set_pit2_out; 5081 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 5082 set_pit2_out: 5083 mutex_unlock(&kvm->lock); 5084 break; 5085 } 5086 case KVM_REINJECT_CONTROL: { 5087 struct kvm_reinject_control control; 5088 r = -EFAULT; 5089 if (copy_from_user(&control, argp, sizeof(control))) 5090 goto out; 5091 r = -ENXIO; 5092 if (!kvm->arch.vpit) 5093 goto out; 5094 r = kvm_vm_ioctl_reinject(kvm, &control); 5095 break; 5096 } 5097 case KVM_SET_BOOT_CPU_ID: 5098 r = 0; 5099 mutex_lock(&kvm->lock); 5100 if (kvm->created_vcpus) 5101 r = -EBUSY; 5102 else 5103 kvm->arch.bsp_vcpu_id = arg; 5104 mutex_unlock(&kvm->lock); 5105 break; 5106 case KVM_XEN_HVM_CONFIG: { 5107 struct kvm_xen_hvm_config xhc; 5108 r = -EFAULT; 5109 if (copy_from_user(&xhc, argp, sizeof(xhc))) 5110 goto out; 5111 r = -EINVAL; 5112 if (xhc.flags) 5113 goto out; 5114 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); 5115 r = 0; 5116 break; 5117 } 5118 case KVM_SET_CLOCK: { 5119 struct kvm_clock_data user_ns; 5120 u64 now_ns; 5121 5122 r = -EFAULT; 5123 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 5124 goto out; 5125 5126 r = -EINVAL; 5127 if (user_ns.flags) 5128 goto out; 5129 5130 r = 0; 5131 /* 5132 * TODO: userspace has to take care of races with VCPU_RUN, so 5133 * kvm_gen_update_masterclock() can be cut down to locked 5134 * pvclock_update_vm_gtod_copy(). 5135 */ 5136 kvm_gen_update_masterclock(kvm); 5137 now_ns = get_kvmclock_ns(kvm); 5138 kvm->arch.kvmclock_offset += user_ns.clock - now_ns; 5139 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); 5140 break; 5141 } 5142 case KVM_GET_CLOCK: { 5143 struct kvm_clock_data user_ns; 5144 u64 now_ns; 5145 5146 now_ns = get_kvmclock_ns(kvm); 5147 user_ns.clock = now_ns; 5148 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 5149 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 5150 5151 r = -EFAULT; 5152 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 5153 goto out; 5154 r = 0; 5155 break; 5156 } 5157 case KVM_MEMORY_ENCRYPT_OP: { 5158 r = -ENOTTY; 5159 if (kvm_x86_ops.mem_enc_op) 5160 r = kvm_x86_ops.mem_enc_op(kvm, argp); 5161 break; 5162 } 5163 case KVM_MEMORY_ENCRYPT_REG_REGION: { 5164 struct kvm_enc_region region; 5165 5166 r = -EFAULT; 5167 if (copy_from_user(®ion, argp, sizeof(region))) 5168 goto out; 5169 5170 r = -ENOTTY; 5171 if (kvm_x86_ops.mem_enc_reg_region) 5172 r = kvm_x86_ops.mem_enc_reg_region(kvm, ®ion); 5173 break; 5174 } 5175 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 5176 struct kvm_enc_region region; 5177 5178 r = -EFAULT; 5179 if (copy_from_user(®ion, argp, sizeof(region))) 5180 goto out; 5181 5182 r = -ENOTTY; 5183 if (kvm_x86_ops.mem_enc_unreg_region) 5184 r = kvm_x86_ops.mem_enc_unreg_region(kvm, ®ion); 5185 break; 5186 } 5187 case KVM_HYPERV_EVENTFD: { 5188 struct kvm_hyperv_eventfd hvevfd; 5189 5190 r = -EFAULT; 5191 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 5192 goto out; 5193 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 5194 break; 5195 } 5196 case KVM_SET_PMU_EVENT_FILTER: 5197 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); 5198 break; 5199 default: 5200 r = -ENOTTY; 5201 } 5202 out: 5203 return r; 5204 } 5205 5206 static void kvm_init_msr_list(void) 5207 { 5208 struct x86_pmu_capability x86_pmu; 5209 u32 dummy[2]; 5210 unsigned i; 5211 5212 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, 5213 "Please update the fixed PMCs in msrs_to_saved_all[]"); 5214 5215 perf_get_x86_pmu_capability(&x86_pmu); 5216 5217 num_msrs_to_save = 0; 5218 num_emulated_msrs = 0; 5219 num_msr_based_features = 0; 5220 5221 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { 5222 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) 5223 continue; 5224 5225 /* 5226 * Even MSRs that are valid in the host may not be exposed 5227 * to the guests in some cases. 5228 */ 5229 switch (msrs_to_save_all[i]) { 5230 case MSR_IA32_BNDCFGS: 5231 if (!kvm_mpx_supported()) 5232 continue; 5233 break; 5234 case MSR_TSC_AUX: 5235 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) 5236 continue; 5237 break; 5238 case MSR_IA32_RTIT_CTL: 5239 case MSR_IA32_RTIT_STATUS: 5240 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) 5241 continue; 5242 break; 5243 case MSR_IA32_RTIT_CR3_MATCH: 5244 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 5245 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 5246 continue; 5247 break; 5248 case MSR_IA32_RTIT_OUTPUT_BASE: 5249 case MSR_IA32_RTIT_OUTPUT_MASK: 5250 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 5251 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 5252 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 5253 continue; 5254 break; 5255 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: { 5256 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 5257 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= 5258 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 5259 continue; 5260 break; 5261 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: 5262 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= 5263 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 5264 continue; 5265 break; 5266 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: 5267 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= 5268 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 5269 continue; 5270 } 5271 default: 5272 break; 5273 } 5274 5275 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; 5276 } 5277 5278 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { 5279 if (!kvm_x86_ops.has_emulated_msr(emulated_msrs_all[i])) 5280 continue; 5281 5282 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; 5283 } 5284 5285 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { 5286 struct kvm_msr_entry msr; 5287 5288 msr.index = msr_based_features_all[i]; 5289 if (kvm_get_msr_feature(&msr)) 5290 continue; 5291 5292 msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; 5293 } 5294 } 5295 5296 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 5297 const void *v) 5298 { 5299 int handled = 0; 5300 int n; 5301 5302 do { 5303 n = min(len, 8); 5304 if (!(lapic_in_kernel(vcpu) && 5305 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 5306 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 5307 break; 5308 handled += n; 5309 addr += n; 5310 len -= n; 5311 v += n; 5312 } while (len); 5313 5314 return handled; 5315 } 5316 5317 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 5318 { 5319 int handled = 0; 5320 int n; 5321 5322 do { 5323 n = min(len, 8); 5324 if (!(lapic_in_kernel(vcpu) && 5325 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 5326 addr, n, v)) 5327 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 5328 break; 5329 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 5330 handled += n; 5331 addr += n; 5332 len -= n; 5333 v += n; 5334 } while (len); 5335 5336 return handled; 5337 } 5338 5339 static void kvm_set_segment(struct kvm_vcpu *vcpu, 5340 struct kvm_segment *var, int seg) 5341 { 5342 kvm_x86_ops.set_segment(vcpu, var, seg); 5343 } 5344 5345 void kvm_get_segment(struct kvm_vcpu *vcpu, 5346 struct kvm_segment *var, int seg) 5347 { 5348 kvm_x86_ops.get_segment(vcpu, var, seg); 5349 } 5350 5351 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 5352 struct x86_exception *exception) 5353 { 5354 gpa_t t_gpa; 5355 5356 BUG_ON(!mmu_is_nested(vcpu)); 5357 5358 /* NPT walks are always user-walks */ 5359 access |= PFERR_USER_MASK; 5360 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); 5361 5362 return t_gpa; 5363 } 5364 5365 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 5366 struct x86_exception *exception) 5367 { 5368 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5369 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5370 } 5371 5372 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 5373 struct x86_exception *exception) 5374 { 5375 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5376 access |= PFERR_FETCH_MASK; 5377 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5378 } 5379 5380 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 5381 struct x86_exception *exception) 5382 { 5383 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5384 access |= PFERR_WRITE_MASK; 5385 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5386 } 5387 5388 /* uses this to access any guest's mapped memory without checking CPL */ 5389 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 5390 struct x86_exception *exception) 5391 { 5392 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 5393 } 5394 5395 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 5396 struct kvm_vcpu *vcpu, u32 access, 5397 struct x86_exception *exception) 5398 { 5399 void *data = val; 5400 int r = X86EMUL_CONTINUE; 5401 5402 while (bytes) { 5403 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 5404 exception); 5405 unsigned offset = addr & (PAGE_SIZE-1); 5406 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 5407 int ret; 5408 5409 if (gpa == UNMAPPED_GVA) 5410 return X86EMUL_PROPAGATE_FAULT; 5411 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 5412 offset, toread); 5413 if (ret < 0) { 5414 r = X86EMUL_IO_NEEDED; 5415 goto out; 5416 } 5417 5418 bytes -= toread; 5419 data += toread; 5420 addr += toread; 5421 } 5422 out: 5423 return r; 5424 } 5425 5426 /* used for instruction fetching */ 5427 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 5428 gva_t addr, void *val, unsigned int bytes, 5429 struct x86_exception *exception) 5430 { 5431 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5432 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5433 unsigned offset; 5434 int ret; 5435 5436 /* Inline kvm_read_guest_virt_helper for speed. */ 5437 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 5438 exception); 5439 if (unlikely(gpa == UNMAPPED_GVA)) 5440 return X86EMUL_PROPAGATE_FAULT; 5441 5442 offset = addr & (PAGE_SIZE-1); 5443 if (WARN_ON(offset + bytes > PAGE_SIZE)) 5444 bytes = (unsigned)PAGE_SIZE - offset; 5445 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 5446 offset, bytes); 5447 if (unlikely(ret < 0)) 5448 return X86EMUL_IO_NEEDED; 5449 5450 return X86EMUL_CONTINUE; 5451 } 5452 5453 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 5454 gva_t addr, void *val, unsigned int bytes, 5455 struct x86_exception *exception) 5456 { 5457 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5458 5459 /* 5460 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 5461 * is returned, but our callers are not ready for that and they blindly 5462 * call kvm_inject_page_fault. Ensure that they at least do not leak 5463 * uninitialized kernel stack memory into cr2 and error code. 5464 */ 5465 memset(exception, 0, sizeof(*exception)); 5466 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 5467 exception); 5468 } 5469 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 5470 5471 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 5472 gva_t addr, void *val, unsigned int bytes, 5473 struct x86_exception *exception, bool system) 5474 { 5475 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5476 u32 access = 0; 5477 5478 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3) 5479 access |= PFERR_USER_MASK; 5480 5481 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 5482 } 5483 5484 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 5485 unsigned long addr, void *val, unsigned int bytes) 5486 { 5487 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5488 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 5489 5490 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 5491 } 5492 5493 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 5494 struct kvm_vcpu *vcpu, u32 access, 5495 struct x86_exception *exception) 5496 { 5497 void *data = val; 5498 int r = X86EMUL_CONTINUE; 5499 5500 while (bytes) { 5501 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 5502 access, 5503 exception); 5504 unsigned offset = addr & (PAGE_SIZE-1); 5505 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 5506 int ret; 5507 5508 if (gpa == UNMAPPED_GVA) 5509 return X86EMUL_PROPAGATE_FAULT; 5510 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 5511 if (ret < 0) { 5512 r = X86EMUL_IO_NEEDED; 5513 goto out; 5514 } 5515 5516 bytes -= towrite; 5517 data += towrite; 5518 addr += towrite; 5519 } 5520 out: 5521 return r; 5522 } 5523 5524 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 5525 unsigned int bytes, struct x86_exception *exception, 5526 bool system) 5527 { 5528 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5529 u32 access = PFERR_WRITE_MASK; 5530 5531 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3) 5532 access |= PFERR_USER_MASK; 5533 5534 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 5535 access, exception); 5536 } 5537 5538 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 5539 unsigned int bytes, struct x86_exception *exception) 5540 { 5541 /* kvm_write_guest_virt_system can pull in tons of pages. */ 5542 vcpu->arch.l1tf_flush_l1d = true; 5543 5544 /* 5545 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 5546 * is returned, but our callers are not ready for that and they blindly 5547 * call kvm_inject_page_fault. Ensure that they at least do not leak 5548 * uninitialized kernel stack memory into cr2 and error code. 5549 */ 5550 memset(exception, 0, sizeof(*exception)); 5551 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 5552 PFERR_WRITE_MASK, exception); 5553 } 5554 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 5555 5556 int handle_ud(struct kvm_vcpu *vcpu) 5557 { 5558 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; 5559 int emul_type = EMULTYPE_TRAP_UD; 5560 char sig[5]; /* ud2; .ascii "kvm" */ 5561 struct x86_exception e; 5562 5563 if (force_emulation_prefix && 5564 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 5565 sig, sizeof(sig), &e) == 0 && 5566 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { 5567 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 5568 emul_type = EMULTYPE_TRAP_UD_FORCED; 5569 } 5570 5571 return kvm_emulate_instruction(vcpu, emul_type); 5572 } 5573 EXPORT_SYMBOL_GPL(handle_ud); 5574 5575 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 5576 gpa_t gpa, bool write) 5577 { 5578 /* For APIC access vmexit */ 5579 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 5580 return 1; 5581 5582 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 5583 trace_vcpu_match_mmio(gva, gpa, write, true); 5584 return 1; 5585 } 5586 5587 return 0; 5588 } 5589 5590 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 5591 gpa_t *gpa, struct x86_exception *exception, 5592 bool write) 5593 { 5594 u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 5595 | (write ? PFERR_WRITE_MASK : 0); 5596 5597 /* 5598 * currently PKRU is only applied to ept enabled guest so 5599 * there is no pkey in EPT page table for L1 guest or EPT 5600 * shadow page table for L2 guest. 5601 */ 5602 if (vcpu_match_mmio_gva(vcpu, gva) 5603 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 5604 vcpu->arch.mmio_access, 0, access)) { 5605 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 5606 (gva & (PAGE_SIZE - 1)); 5607 trace_vcpu_match_mmio(gva, *gpa, write, false); 5608 return 1; 5609 } 5610 5611 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5612 5613 if (*gpa == UNMAPPED_GVA) 5614 return -1; 5615 5616 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 5617 } 5618 5619 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 5620 const void *val, int bytes) 5621 { 5622 int ret; 5623 5624 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 5625 if (ret < 0) 5626 return 0; 5627 kvm_page_track_write(vcpu, gpa, val, bytes); 5628 return 1; 5629 } 5630 5631 struct read_write_emulator_ops { 5632 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 5633 int bytes); 5634 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 5635 void *val, int bytes); 5636 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 5637 int bytes, void *val); 5638 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 5639 void *val, int bytes); 5640 bool write; 5641 }; 5642 5643 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 5644 { 5645 if (vcpu->mmio_read_completed) { 5646 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 5647 vcpu->mmio_fragments[0].gpa, val); 5648 vcpu->mmio_read_completed = 0; 5649 return 1; 5650 } 5651 5652 return 0; 5653 } 5654 5655 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 5656 void *val, int bytes) 5657 { 5658 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 5659 } 5660 5661 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 5662 void *val, int bytes) 5663 { 5664 return emulator_write_phys(vcpu, gpa, val, bytes); 5665 } 5666 5667 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 5668 { 5669 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 5670 return vcpu_mmio_write(vcpu, gpa, bytes, val); 5671 } 5672 5673 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 5674 void *val, int bytes) 5675 { 5676 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 5677 return X86EMUL_IO_NEEDED; 5678 } 5679 5680 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 5681 void *val, int bytes) 5682 { 5683 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 5684 5685 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 5686 return X86EMUL_CONTINUE; 5687 } 5688 5689 static const struct read_write_emulator_ops read_emultor = { 5690 .read_write_prepare = read_prepare, 5691 .read_write_emulate = read_emulate, 5692 .read_write_mmio = vcpu_mmio_read, 5693 .read_write_exit_mmio = read_exit_mmio, 5694 }; 5695 5696 static const struct read_write_emulator_ops write_emultor = { 5697 .read_write_emulate = write_emulate, 5698 .read_write_mmio = write_mmio, 5699 .read_write_exit_mmio = write_exit_mmio, 5700 .write = true, 5701 }; 5702 5703 static int emulator_read_write_onepage(unsigned long addr, void *val, 5704 unsigned int bytes, 5705 struct x86_exception *exception, 5706 struct kvm_vcpu *vcpu, 5707 const struct read_write_emulator_ops *ops) 5708 { 5709 gpa_t gpa; 5710 int handled, ret; 5711 bool write = ops->write; 5712 struct kvm_mmio_fragment *frag; 5713 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 5714 5715 /* 5716 * If the exit was due to a NPF we may already have a GPA. 5717 * If the GPA is present, use it to avoid the GVA to GPA table walk. 5718 * Note, this cannot be used on string operations since string 5719 * operation using rep will only have the initial GPA from the NPF 5720 * occurred. 5721 */ 5722 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && 5723 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { 5724 gpa = ctxt->gpa_val; 5725 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 5726 } else { 5727 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 5728 if (ret < 0) 5729 return X86EMUL_PROPAGATE_FAULT; 5730 } 5731 5732 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 5733 return X86EMUL_CONTINUE; 5734 5735 /* 5736 * Is this MMIO handled locally? 5737 */ 5738 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 5739 if (handled == bytes) 5740 return X86EMUL_CONTINUE; 5741 5742 gpa += handled; 5743 bytes -= handled; 5744 val += handled; 5745 5746 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 5747 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 5748 frag->gpa = gpa; 5749 frag->data = val; 5750 frag->len = bytes; 5751 return X86EMUL_CONTINUE; 5752 } 5753 5754 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 5755 unsigned long addr, 5756 void *val, unsigned int bytes, 5757 struct x86_exception *exception, 5758 const struct read_write_emulator_ops *ops) 5759 { 5760 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5761 gpa_t gpa; 5762 int rc; 5763 5764 if (ops->read_write_prepare && 5765 ops->read_write_prepare(vcpu, val, bytes)) 5766 return X86EMUL_CONTINUE; 5767 5768 vcpu->mmio_nr_fragments = 0; 5769 5770 /* Crossing a page boundary? */ 5771 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 5772 int now; 5773 5774 now = -addr & ~PAGE_MASK; 5775 rc = emulator_read_write_onepage(addr, val, now, exception, 5776 vcpu, ops); 5777 5778 if (rc != X86EMUL_CONTINUE) 5779 return rc; 5780 addr += now; 5781 if (ctxt->mode != X86EMUL_MODE_PROT64) 5782 addr = (u32)addr; 5783 val += now; 5784 bytes -= now; 5785 } 5786 5787 rc = emulator_read_write_onepage(addr, val, bytes, exception, 5788 vcpu, ops); 5789 if (rc != X86EMUL_CONTINUE) 5790 return rc; 5791 5792 if (!vcpu->mmio_nr_fragments) 5793 return rc; 5794 5795 gpa = vcpu->mmio_fragments[0].gpa; 5796 5797 vcpu->mmio_needed = 1; 5798 vcpu->mmio_cur_fragment = 0; 5799 5800 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 5801 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 5802 vcpu->run->exit_reason = KVM_EXIT_MMIO; 5803 vcpu->run->mmio.phys_addr = gpa; 5804 5805 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 5806 } 5807 5808 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 5809 unsigned long addr, 5810 void *val, 5811 unsigned int bytes, 5812 struct x86_exception *exception) 5813 { 5814 return emulator_read_write(ctxt, addr, val, bytes, 5815 exception, &read_emultor); 5816 } 5817 5818 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 5819 unsigned long addr, 5820 const void *val, 5821 unsigned int bytes, 5822 struct x86_exception *exception) 5823 { 5824 return emulator_read_write(ctxt, addr, (void *)val, bytes, 5825 exception, &write_emultor); 5826 } 5827 5828 #define CMPXCHG_TYPE(t, ptr, old, new) \ 5829 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 5830 5831 #ifdef CONFIG_X86_64 5832 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 5833 #else 5834 # define CMPXCHG64(ptr, old, new) \ 5835 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 5836 #endif 5837 5838 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 5839 unsigned long addr, 5840 const void *old, 5841 const void *new, 5842 unsigned int bytes, 5843 struct x86_exception *exception) 5844 { 5845 struct kvm_host_map map; 5846 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5847 u64 page_line_mask; 5848 gpa_t gpa; 5849 char *kaddr; 5850 bool exchanged; 5851 5852 /* guests cmpxchg8b have to be emulated atomically */ 5853 if (bytes > 8 || (bytes & (bytes - 1))) 5854 goto emul_write; 5855 5856 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 5857 5858 if (gpa == UNMAPPED_GVA || 5859 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 5860 goto emul_write; 5861 5862 /* 5863 * Emulate the atomic as a straight write to avoid #AC if SLD is 5864 * enabled in the host and the access splits a cache line. 5865 */ 5866 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 5867 page_line_mask = ~(cache_line_size() - 1); 5868 else 5869 page_line_mask = PAGE_MASK; 5870 5871 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) 5872 goto emul_write; 5873 5874 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) 5875 goto emul_write; 5876 5877 kaddr = map.hva + offset_in_page(gpa); 5878 5879 switch (bytes) { 5880 case 1: 5881 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 5882 break; 5883 case 2: 5884 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 5885 break; 5886 case 4: 5887 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 5888 break; 5889 case 8: 5890 exchanged = CMPXCHG64(kaddr, old, new); 5891 break; 5892 default: 5893 BUG(); 5894 } 5895 5896 kvm_vcpu_unmap(vcpu, &map, true); 5897 5898 if (!exchanged) 5899 return X86EMUL_CMPXCHG_FAILED; 5900 5901 kvm_page_track_write(vcpu, gpa, new, bytes); 5902 5903 return X86EMUL_CONTINUE; 5904 5905 emul_write: 5906 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 5907 5908 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 5909 } 5910 5911 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 5912 { 5913 int r = 0, i; 5914 5915 for (i = 0; i < vcpu->arch.pio.count; i++) { 5916 if (vcpu->arch.pio.in) 5917 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 5918 vcpu->arch.pio.size, pd); 5919 else 5920 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 5921 vcpu->arch.pio.port, vcpu->arch.pio.size, 5922 pd); 5923 if (r) 5924 break; 5925 pd += vcpu->arch.pio.size; 5926 } 5927 return r; 5928 } 5929 5930 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 5931 unsigned short port, void *val, 5932 unsigned int count, bool in) 5933 { 5934 vcpu->arch.pio.port = port; 5935 vcpu->arch.pio.in = in; 5936 vcpu->arch.pio.count = count; 5937 vcpu->arch.pio.size = size; 5938 5939 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 5940 vcpu->arch.pio.count = 0; 5941 return 1; 5942 } 5943 5944 vcpu->run->exit_reason = KVM_EXIT_IO; 5945 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 5946 vcpu->run->io.size = size; 5947 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 5948 vcpu->run->io.count = count; 5949 vcpu->run->io.port = port; 5950 5951 return 0; 5952 } 5953 5954 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, 5955 unsigned short port, void *val, unsigned int count) 5956 { 5957 int ret; 5958 5959 if (vcpu->arch.pio.count) 5960 goto data_avail; 5961 5962 memset(vcpu->arch.pio_data, 0, size * count); 5963 5964 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 5965 if (ret) { 5966 data_avail: 5967 memcpy(val, vcpu->arch.pio_data, size * count); 5968 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 5969 vcpu->arch.pio.count = 0; 5970 return 1; 5971 } 5972 5973 return 0; 5974 } 5975 5976 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 5977 int size, unsigned short port, void *val, 5978 unsigned int count) 5979 { 5980 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); 5981 5982 } 5983 5984 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, 5985 unsigned short port, const void *val, 5986 unsigned int count) 5987 { 5988 memcpy(vcpu->arch.pio_data, val, size * count); 5989 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 5990 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 5991 } 5992 5993 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 5994 int size, unsigned short port, 5995 const void *val, unsigned int count) 5996 { 5997 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); 5998 } 5999 6000 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 6001 { 6002 return kvm_x86_ops.get_segment_base(vcpu, seg); 6003 } 6004 6005 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 6006 { 6007 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 6008 } 6009 6010 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 6011 { 6012 if (!need_emulate_wbinvd(vcpu)) 6013 return X86EMUL_CONTINUE; 6014 6015 if (kvm_x86_ops.has_wbinvd_exit()) { 6016 int cpu = get_cpu(); 6017 6018 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 6019 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 6020 wbinvd_ipi, NULL, 1); 6021 put_cpu(); 6022 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 6023 } else 6024 wbinvd(); 6025 return X86EMUL_CONTINUE; 6026 } 6027 6028 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 6029 { 6030 kvm_emulate_wbinvd_noskip(vcpu); 6031 return kvm_skip_emulated_instruction(vcpu); 6032 } 6033 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 6034 6035 6036 6037 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 6038 { 6039 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 6040 } 6041 6042 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 6043 unsigned long *dest) 6044 { 6045 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 6046 } 6047 6048 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 6049 unsigned long value) 6050 { 6051 6052 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 6053 } 6054 6055 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 6056 { 6057 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 6058 } 6059 6060 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 6061 { 6062 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6063 unsigned long value; 6064 6065 switch (cr) { 6066 case 0: 6067 value = kvm_read_cr0(vcpu); 6068 break; 6069 case 2: 6070 value = vcpu->arch.cr2; 6071 break; 6072 case 3: 6073 value = kvm_read_cr3(vcpu); 6074 break; 6075 case 4: 6076 value = kvm_read_cr4(vcpu); 6077 break; 6078 case 8: 6079 value = kvm_get_cr8(vcpu); 6080 break; 6081 default: 6082 kvm_err("%s: unexpected cr %u\n", __func__, cr); 6083 return 0; 6084 } 6085 6086 return value; 6087 } 6088 6089 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 6090 { 6091 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6092 int res = 0; 6093 6094 switch (cr) { 6095 case 0: 6096 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 6097 break; 6098 case 2: 6099 vcpu->arch.cr2 = val; 6100 break; 6101 case 3: 6102 res = kvm_set_cr3(vcpu, val); 6103 break; 6104 case 4: 6105 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 6106 break; 6107 case 8: 6108 res = kvm_set_cr8(vcpu, val); 6109 break; 6110 default: 6111 kvm_err("%s: unexpected cr %u\n", __func__, cr); 6112 res = -1; 6113 } 6114 6115 return res; 6116 } 6117 6118 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 6119 { 6120 return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt)); 6121 } 6122 6123 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6124 { 6125 kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt); 6126 } 6127 6128 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6129 { 6130 kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt); 6131 } 6132 6133 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6134 { 6135 kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt); 6136 } 6137 6138 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6139 { 6140 kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt); 6141 } 6142 6143 static unsigned long emulator_get_cached_segment_base( 6144 struct x86_emulate_ctxt *ctxt, int seg) 6145 { 6146 return get_segment_base(emul_to_vcpu(ctxt), seg); 6147 } 6148 6149 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 6150 struct desc_struct *desc, u32 *base3, 6151 int seg) 6152 { 6153 struct kvm_segment var; 6154 6155 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 6156 *selector = var.selector; 6157 6158 if (var.unusable) { 6159 memset(desc, 0, sizeof(*desc)); 6160 if (base3) 6161 *base3 = 0; 6162 return false; 6163 } 6164 6165 if (var.g) 6166 var.limit >>= 12; 6167 set_desc_limit(desc, var.limit); 6168 set_desc_base(desc, (unsigned long)var.base); 6169 #ifdef CONFIG_X86_64 6170 if (base3) 6171 *base3 = var.base >> 32; 6172 #endif 6173 desc->type = var.type; 6174 desc->s = var.s; 6175 desc->dpl = var.dpl; 6176 desc->p = var.present; 6177 desc->avl = var.avl; 6178 desc->l = var.l; 6179 desc->d = var.db; 6180 desc->g = var.g; 6181 6182 return true; 6183 } 6184 6185 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 6186 struct desc_struct *desc, u32 base3, 6187 int seg) 6188 { 6189 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6190 struct kvm_segment var; 6191 6192 var.selector = selector; 6193 var.base = get_desc_base(desc); 6194 #ifdef CONFIG_X86_64 6195 var.base |= ((u64)base3) << 32; 6196 #endif 6197 var.limit = get_desc_limit(desc); 6198 if (desc->g) 6199 var.limit = (var.limit << 12) | 0xfff; 6200 var.type = desc->type; 6201 var.dpl = desc->dpl; 6202 var.db = desc->d; 6203 var.s = desc->s; 6204 var.l = desc->l; 6205 var.g = desc->g; 6206 var.avl = desc->avl; 6207 var.present = desc->p; 6208 var.unusable = !var.present; 6209 var.padding = 0; 6210 6211 kvm_set_segment(vcpu, &var, seg); 6212 return; 6213 } 6214 6215 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 6216 u32 msr_index, u64 *pdata) 6217 { 6218 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); 6219 } 6220 6221 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 6222 u32 msr_index, u64 data) 6223 { 6224 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data); 6225 } 6226 6227 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 6228 { 6229 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6230 6231 return vcpu->arch.smbase; 6232 } 6233 6234 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 6235 { 6236 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6237 6238 vcpu->arch.smbase = smbase; 6239 } 6240 6241 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 6242 u32 pmc) 6243 { 6244 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); 6245 } 6246 6247 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 6248 u32 pmc, u64 *pdata) 6249 { 6250 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 6251 } 6252 6253 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 6254 { 6255 emul_to_vcpu(ctxt)->arch.halt_request = 1; 6256 } 6257 6258 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 6259 struct x86_instruction_info *info, 6260 enum x86_intercept_stage stage) 6261 { 6262 return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage, 6263 &ctxt->exception); 6264 } 6265 6266 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 6267 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, 6268 bool exact_only) 6269 { 6270 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); 6271 } 6272 6273 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) 6274 { 6275 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); 6276 } 6277 6278 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) 6279 { 6280 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); 6281 } 6282 6283 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) 6284 { 6285 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); 6286 } 6287 6288 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 6289 { 6290 return kvm_register_read(emul_to_vcpu(ctxt), reg); 6291 } 6292 6293 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 6294 { 6295 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 6296 } 6297 6298 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 6299 { 6300 kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked); 6301 } 6302 6303 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 6304 { 6305 return emul_to_vcpu(ctxt)->arch.hflags; 6306 } 6307 6308 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) 6309 { 6310 emul_to_vcpu(ctxt)->arch.hflags = emul_flags; 6311 } 6312 6313 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, 6314 const char *smstate) 6315 { 6316 return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate); 6317 } 6318 6319 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) 6320 { 6321 kvm_smm_changed(emul_to_vcpu(ctxt)); 6322 } 6323 6324 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) 6325 { 6326 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); 6327 } 6328 6329 static const struct x86_emulate_ops emulate_ops = { 6330 .read_gpr = emulator_read_gpr, 6331 .write_gpr = emulator_write_gpr, 6332 .read_std = emulator_read_std, 6333 .write_std = emulator_write_std, 6334 .read_phys = kvm_read_guest_phys_system, 6335 .fetch = kvm_fetch_guest_virt, 6336 .read_emulated = emulator_read_emulated, 6337 .write_emulated = emulator_write_emulated, 6338 .cmpxchg_emulated = emulator_cmpxchg_emulated, 6339 .invlpg = emulator_invlpg, 6340 .pio_in_emulated = emulator_pio_in_emulated, 6341 .pio_out_emulated = emulator_pio_out_emulated, 6342 .get_segment = emulator_get_segment, 6343 .set_segment = emulator_set_segment, 6344 .get_cached_segment_base = emulator_get_cached_segment_base, 6345 .get_gdt = emulator_get_gdt, 6346 .get_idt = emulator_get_idt, 6347 .set_gdt = emulator_set_gdt, 6348 .set_idt = emulator_set_idt, 6349 .get_cr = emulator_get_cr, 6350 .set_cr = emulator_set_cr, 6351 .cpl = emulator_get_cpl, 6352 .get_dr = emulator_get_dr, 6353 .set_dr = emulator_set_dr, 6354 .get_smbase = emulator_get_smbase, 6355 .set_smbase = emulator_set_smbase, 6356 .set_msr = emulator_set_msr, 6357 .get_msr = emulator_get_msr, 6358 .check_pmc = emulator_check_pmc, 6359 .read_pmc = emulator_read_pmc, 6360 .halt = emulator_halt, 6361 .wbinvd = emulator_wbinvd, 6362 .fix_hypercall = emulator_fix_hypercall, 6363 .intercept = emulator_intercept, 6364 .get_cpuid = emulator_get_cpuid, 6365 .guest_has_long_mode = emulator_guest_has_long_mode, 6366 .guest_has_movbe = emulator_guest_has_movbe, 6367 .guest_has_fxsr = emulator_guest_has_fxsr, 6368 .set_nmi_mask = emulator_set_nmi_mask, 6369 .get_hflags = emulator_get_hflags, 6370 .set_hflags = emulator_set_hflags, 6371 .pre_leave_smm = emulator_pre_leave_smm, 6372 .post_leave_smm = emulator_post_leave_smm, 6373 .set_xcr = emulator_set_xcr, 6374 }; 6375 6376 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 6377 { 6378 u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu); 6379 /* 6380 * an sti; sti; sequence only disable interrupts for the first 6381 * instruction. So, if the last instruction, be it emulated or 6382 * not, left the system with the INT_STI flag enabled, it 6383 * means that the last instruction is an sti. We should not 6384 * leave the flag on in this case. The same goes for mov ss 6385 */ 6386 if (int_shadow & mask) 6387 mask = 0; 6388 if (unlikely(int_shadow || mask)) { 6389 kvm_x86_ops.set_interrupt_shadow(vcpu, mask); 6390 if (!mask) 6391 kvm_make_request(KVM_REQ_EVENT, vcpu); 6392 } 6393 } 6394 6395 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 6396 { 6397 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6398 if (ctxt->exception.vector == PF_VECTOR) 6399 return kvm_propagate_fault(vcpu, &ctxt->exception); 6400 6401 if (ctxt->exception.error_code_valid) 6402 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 6403 ctxt->exception.error_code); 6404 else 6405 kvm_queue_exception(vcpu, ctxt->exception.vector); 6406 return false; 6407 } 6408 6409 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) 6410 { 6411 struct x86_emulate_ctxt *ctxt; 6412 6413 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); 6414 if (!ctxt) { 6415 pr_err("kvm: failed to allocate vcpu's emulator\n"); 6416 return NULL; 6417 } 6418 6419 ctxt->vcpu = vcpu; 6420 ctxt->ops = &emulate_ops; 6421 vcpu->arch.emulate_ctxt = ctxt; 6422 6423 return ctxt; 6424 } 6425 6426 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 6427 { 6428 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6429 int cs_db, cs_l; 6430 6431 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 6432 6433 ctxt->gpa_available = false; 6434 ctxt->eflags = kvm_get_rflags(vcpu); 6435 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 6436 6437 ctxt->eip = kvm_rip_read(vcpu); 6438 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 6439 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 6440 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 6441 cs_db ? X86EMUL_MODE_PROT32 : 6442 X86EMUL_MODE_PROT16; 6443 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 6444 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 6445 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 6446 6447 init_decode_cache(ctxt); 6448 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 6449 } 6450 6451 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 6452 { 6453 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6454 int ret; 6455 6456 init_emulate_ctxt(vcpu); 6457 6458 ctxt->op_bytes = 2; 6459 ctxt->ad_bytes = 2; 6460 ctxt->_eip = ctxt->eip + inc_eip; 6461 ret = emulate_int_real(ctxt, irq); 6462 6463 if (ret != X86EMUL_CONTINUE) { 6464 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 6465 } else { 6466 ctxt->eip = ctxt->_eip; 6467 kvm_rip_write(vcpu, ctxt->eip); 6468 kvm_set_rflags(vcpu, ctxt->eflags); 6469 } 6470 } 6471 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 6472 6473 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 6474 { 6475 ++vcpu->stat.insn_emulation_fail; 6476 trace_kvm_emulate_insn_failed(vcpu); 6477 6478 if (emulation_type & EMULTYPE_VMWARE_GP) { 6479 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 6480 return 1; 6481 } 6482 6483 if (emulation_type & EMULTYPE_SKIP) { 6484 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 6485 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 6486 vcpu->run->internal.ndata = 0; 6487 return 0; 6488 } 6489 6490 kvm_queue_exception(vcpu, UD_VECTOR); 6491 6492 if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) { 6493 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 6494 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 6495 vcpu->run->internal.ndata = 0; 6496 return 0; 6497 } 6498 6499 return 1; 6500 } 6501 6502 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 6503 bool write_fault_to_shadow_pgtable, 6504 int emulation_type) 6505 { 6506 gpa_t gpa = cr2_or_gpa; 6507 kvm_pfn_t pfn; 6508 6509 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 6510 return false; 6511 6512 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 6513 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 6514 return false; 6515 6516 if (!vcpu->arch.mmu->direct_map) { 6517 /* 6518 * Write permission should be allowed since only 6519 * write access need to be emulated. 6520 */ 6521 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 6522 6523 /* 6524 * If the mapping is invalid in guest, let cpu retry 6525 * it to generate fault. 6526 */ 6527 if (gpa == UNMAPPED_GVA) 6528 return true; 6529 } 6530 6531 /* 6532 * Do not retry the unhandleable instruction if it faults on the 6533 * readonly host memory, otherwise it will goto a infinite loop: 6534 * retry instruction -> write #PF -> emulation fail -> retry 6535 * instruction -> ... 6536 */ 6537 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 6538 6539 /* 6540 * If the instruction failed on the error pfn, it can not be fixed, 6541 * report the error to userspace. 6542 */ 6543 if (is_error_noslot_pfn(pfn)) 6544 return false; 6545 6546 kvm_release_pfn_clean(pfn); 6547 6548 /* The instructions are well-emulated on direct mmu. */ 6549 if (vcpu->arch.mmu->direct_map) { 6550 unsigned int indirect_shadow_pages; 6551 6552 spin_lock(&vcpu->kvm->mmu_lock); 6553 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 6554 spin_unlock(&vcpu->kvm->mmu_lock); 6555 6556 if (indirect_shadow_pages) 6557 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 6558 6559 return true; 6560 } 6561 6562 /* 6563 * if emulation was due to access to shadowed page table 6564 * and it failed try to unshadow page and re-enter the 6565 * guest to let CPU execute the instruction. 6566 */ 6567 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 6568 6569 /* 6570 * If the access faults on its page table, it can not 6571 * be fixed by unprotecting shadow page and it should 6572 * be reported to userspace. 6573 */ 6574 return !write_fault_to_shadow_pgtable; 6575 } 6576 6577 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 6578 gpa_t cr2_or_gpa, int emulation_type) 6579 { 6580 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6581 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; 6582 6583 last_retry_eip = vcpu->arch.last_retry_eip; 6584 last_retry_addr = vcpu->arch.last_retry_addr; 6585 6586 /* 6587 * If the emulation is caused by #PF and it is non-page_table 6588 * writing instruction, it means the VM-EXIT is caused by shadow 6589 * page protected, we can zap the shadow page and retry this 6590 * instruction directly. 6591 * 6592 * Note: if the guest uses a non-page-table modifying instruction 6593 * on the PDE that points to the instruction, then we will unmap 6594 * the instruction and go to an infinite loop. So, we cache the 6595 * last retried eip and the last fault address, if we meet the eip 6596 * and the address again, we can break out of the potential infinite 6597 * loop. 6598 */ 6599 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 6600 6601 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 6602 return false; 6603 6604 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 6605 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 6606 return false; 6607 6608 if (x86_page_table_writing_insn(ctxt)) 6609 return false; 6610 6611 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) 6612 return false; 6613 6614 vcpu->arch.last_retry_eip = ctxt->eip; 6615 vcpu->arch.last_retry_addr = cr2_or_gpa; 6616 6617 if (!vcpu->arch.mmu->direct_map) 6618 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 6619 6620 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 6621 6622 return true; 6623 } 6624 6625 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 6626 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 6627 6628 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 6629 { 6630 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 6631 /* This is a good place to trace that we are exiting SMM. */ 6632 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 6633 6634 /* Process a latched INIT or SMI, if any. */ 6635 kvm_make_request(KVM_REQ_EVENT, vcpu); 6636 } 6637 6638 kvm_mmu_reset_context(vcpu); 6639 } 6640 6641 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 6642 unsigned long *db) 6643 { 6644 u32 dr6 = 0; 6645 int i; 6646 u32 enable, rwlen; 6647 6648 enable = dr7; 6649 rwlen = dr7 >> 16; 6650 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 6651 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 6652 dr6 |= (1 << i); 6653 return dr6; 6654 } 6655 6656 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) 6657 { 6658 struct kvm_run *kvm_run = vcpu->run; 6659 6660 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 6661 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; 6662 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 6663 kvm_run->debug.arch.exception = DB_VECTOR; 6664 kvm_run->exit_reason = KVM_EXIT_DEBUG; 6665 return 0; 6666 } 6667 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 6668 return 1; 6669 } 6670 6671 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 6672 { 6673 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu); 6674 int r; 6675 6676 r = kvm_x86_ops.skip_emulated_instruction(vcpu); 6677 if (unlikely(!r)) 6678 return 0; 6679 6680 /* 6681 * rflags is the old, "raw" value of the flags. The new value has 6682 * not been saved yet. 6683 * 6684 * This is correct even for TF set by the guest, because "the 6685 * processor will not generate this exception after the instruction 6686 * that sets the TF flag". 6687 */ 6688 if (unlikely(rflags & X86_EFLAGS_TF)) 6689 r = kvm_vcpu_do_singlestep(vcpu); 6690 return r; 6691 } 6692 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 6693 6694 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 6695 { 6696 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 6697 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 6698 struct kvm_run *kvm_run = vcpu->run; 6699 unsigned long eip = kvm_get_linear_rip(vcpu); 6700 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 6701 vcpu->arch.guest_debug_dr7, 6702 vcpu->arch.eff_db); 6703 6704 if (dr6 != 0) { 6705 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 6706 kvm_run->debug.arch.pc = eip; 6707 kvm_run->debug.arch.exception = DB_VECTOR; 6708 kvm_run->exit_reason = KVM_EXIT_DEBUG; 6709 *r = 0; 6710 return true; 6711 } 6712 } 6713 6714 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 6715 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 6716 unsigned long eip = kvm_get_linear_rip(vcpu); 6717 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 6718 vcpu->arch.dr7, 6719 vcpu->arch.db); 6720 6721 if (dr6 != 0) { 6722 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 6723 vcpu->arch.dr6 |= dr6 | DR6_RTM; 6724 kvm_queue_exception(vcpu, DB_VECTOR); 6725 *r = 1; 6726 return true; 6727 } 6728 } 6729 6730 return false; 6731 } 6732 6733 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 6734 { 6735 switch (ctxt->opcode_len) { 6736 case 1: 6737 switch (ctxt->b) { 6738 case 0xe4: /* IN */ 6739 case 0xe5: 6740 case 0xec: 6741 case 0xed: 6742 case 0xe6: /* OUT */ 6743 case 0xe7: 6744 case 0xee: 6745 case 0xef: 6746 case 0x6c: /* INS */ 6747 case 0x6d: 6748 case 0x6e: /* OUTS */ 6749 case 0x6f: 6750 return true; 6751 } 6752 break; 6753 case 2: 6754 switch (ctxt->b) { 6755 case 0x33: /* RDPMC */ 6756 return true; 6757 } 6758 break; 6759 } 6760 6761 return false; 6762 } 6763 6764 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 6765 int emulation_type, void *insn, int insn_len) 6766 { 6767 int r; 6768 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6769 bool writeback = true; 6770 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 6771 6772 vcpu->arch.l1tf_flush_l1d = true; 6773 6774 /* 6775 * Clear write_fault_to_shadow_pgtable here to ensure it is 6776 * never reused. 6777 */ 6778 vcpu->arch.write_fault_to_shadow_pgtable = false; 6779 kvm_clear_exception_queue(vcpu); 6780 6781 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 6782 init_emulate_ctxt(vcpu); 6783 6784 /* 6785 * We will reenter on the same instruction since 6786 * we do not set complete_userspace_io. This does not 6787 * handle watchpoints yet, those would be handled in 6788 * the emulate_ops. 6789 */ 6790 if (!(emulation_type & EMULTYPE_SKIP) && 6791 kvm_vcpu_check_breakpoint(vcpu, &r)) 6792 return r; 6793 6794 ctxt->interruptibility = 0; 6795 ctxt->have_exception = false; 6796 ctxt->exception.vector = -1; 6797 ctxt->perm_ok = false; 6798 6799 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 6800 6801 r = x86_decode_insn(ctxt, insn, insn_len); 6802 6803 trace_kvm_emulate_insn_start(vcpu); 6804 ++vcpu->stat.insn_emulation; 6805 if (r != EMULATION_OK) { 6806 if ((emulation_type & EMULTYPE_TRAP_UD) || 6807 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { 6808 kvm_queue_exception(vcpu, UD_VECTOR); 6809 return 1; 6810 } 6811 if (reexecute_instruction(vcpu, cr2_or_gpa, 6812 write_fault_to_spt, 6813 emulation_type)) 6814 return 1; 6815 if (ctxt->have_exception) { 6816 /* 6817 * #UD should result in just EMULATION_FAILED, and trap-like 6818 * exception should not be encountered during decode. 6819 */ 6820 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || 6821 exception_type(ctxt->exception.vector) == EXCPT_TRAP); 6822 inject_emulated_exception(vcpu); 6823 return 1; 6824 } 6825 return handle_emulation_failure(vcpu, emulation_type); 6826 } 6827 } 6828 6829 if ((emulation_type & EMULTYPE_VMWARE_GP) && 6830 !is_vmware_backdoor_opcode(ctxt)) { 6831 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 6832 return 1; 6833 } 6834 6835 /* 6836 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks 6837 * for kvm_skip_emulated_instruction(). The caller is responsible for 6838 * updating interruptibility state and injecting single-step #DBs. 6839 */ 6840 if (emulation_type & EMULTYPE_SKIP) { 6841 kvm_rip_write(vcpu, ctxt->_eip); 6842 if (ctxt->eflags & X86_EFLAGS_RF) 6843 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 6844 return 1; 6845 } 6846 6847 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) 6848 return 1; 6849 6850 /* this is needed for vmware backdoor interface to work since it 6851 changes registers values during IO operation */ 6852 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 6853 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 6854 emulator_invalidate_register_cache(ctxt); 6855 } 6856 6857 restart: 6858 if (emulation_type & EMULTYPE_PF) { 6859 /* Save the faulting GPA (cr2) in the address field */ 6860 ctxt->exception.address = cr2_or_gpa; 6861 6862 /* With shadow page tables, cr2 contains a GVA or nGPA. */ 6863 if (vcpu->arch.mmu->direct_map) { 6864 ctxt->gpa_available = true; 6865 ctxt->gpa_val = cr2_or_gpa; 6866 } 6867 } else { 6868 /* Sanitize the address out of an abundance of paranoia. */ 6869 ctxt->exception.address = 0; 6870 } 6871 6872 r = x86_emulate_insn(ctxt); 6873 6874 if (r == EMULATION_INTERCEPTED) 6875 return 1; 6876 6877 if (r == EMULATION_FAILED) { 6878 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, 6879 emulation_type)) 6880 return 1; 6881 6882 return handle_emulation_failure(vcpu, emulation_type); 6883 } 6884 6885 if (ctxt->have_exception) { 6886 r = 1; 6887 if (inject_emulated_exception(vcpu)) 6888 return r; 6889 } else if (vcpu->arch.pio.count) { 6890 if (!vcpu->arch.pio.in) { 6891 /* FIXME: return into emulator if single-stepping. */ 6892 vcpu->arch.pio.count = 0; 6893 } else { 6894 writeback = false; 6895 vcpu->arch.complete_userspace_io = complete_emulated_pio; 6896 } 6897 r = 0; 6898 } else if (vcpu->mmio_needed) { 6899 ++vcpu->stat.mmio_exits; 6900 6901 if (!vcpu->mmio_is_write) 6902 writeback = false; 6903 r = 0; 6904 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6905 } else if (r == EMULATION_RESTART) 6906 goto restart; 6907 else 6908 r = 1; 6909 6910 if (writeback) { 6911 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu); 6912 toggle_interruptibility(vcpu, ctxt->interruptibility); 6913 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6914 if (!ctxt->have_exception || 6915 exception_type(ctxt->exception.vector) == EXCPT_TRAP) { 6916 kvm_rip_write(vcpu, ctxt->eip); 6917 if (r && ctxt->tf) 6918 r = kvm_vcpu_do_singlestep(vcpu); 6919 if (kvm_x86_ops.update_emulated_instruction) 6920 kvm_x86_ops.update_emulated_instruction(vcpu); 6921 __kvm_set_rflags(vcpu, ctxt->eflags); 6922 } 6923 6924 /* 6925 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 6926 * do nothing, and it will be requested again as soon as 6927 * the shadow expires. But we still need to check here, 6928 * because POPF has no interrupt shadow. 6929 */ 6930 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 6931 kvm_make_request(KVM_REQ_EVENT, vcpu); 6932 } else 6933 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 6934 6935 return r; 6936 } 6937 6938 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 6939 { 6940 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 6941 } 6942 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 6943 6944 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 6945 void *insn, int insn_len) 6946 { 6947 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 6948 } 6949 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 6950 6951 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 6952 { 6953 vcpu->arch.pio.count = 0; 6954 return 1; 6955 } 6956 6957 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 6958 { 6959 vcpu->arch.pio.count = 0; 6960 6961 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 6962 return 1; 6963 6964 return kvm_skip_emulated_instruction(vcpu); 6965 } 6966 6967 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 6968 unsigned short port) 6969 { 6970 unsigned long val = kvm_rax_read(vcpu); 6971 int ret = emulator_pio_out(vcpu, size, port, &val, 1); 6972 6973 if (ret) 6974 return ret; 6975 6976 /* 6977 * Workaround userspace that relies on old KVM behavior of %rip being 6978 * incremented prior to exiting to userspace to handle "OUT 0x7e". 6979 */ 6980 if (port == 0x7e && 6981 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 6982 vcpu->arch.complete_userspace_io = 6983 complete_fast_pio_out_port_0x7e; 6984 kvm_skip_emulated_instruction(vcpu); 6985 } else { 6986 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 6987 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 6988 } 6989 return 0; 6990 } 6991 6992 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 6993 { 6994 unsigned long val; 6995 6996 /* We should only ever be called with arch.pio.count equal to 1 */ 6997 BUG_ON(vcpu->arch.pio.count != 1); 6998 6999 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 7000 vcpu->arch.pio.count = 0; 7001 return 1; 7002 } 7003 7004 /* For size less than 4 we merge, else we zero extend */ 7005 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 7006 7007 /* 7008 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform 7009 * the copy and tracing 7010 */ 7011 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); 7012 kvm_rax_write(vcpu, val); 7013 7014 return kvm_skip_emulated_instruction(vcpu); 7015 } 7016 7017 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 7018 unsigned short port) 7019 { 7020 unsigned long val; 7021 int ret; 7022 7023 /* For size less than 4 we merge, else we zero extend */ 7024 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 7025 7026 ret = emulator_pio_in(vcpu, size, port, &val, 1); 7027 if (ret) { 7028 kvm_rax_write(vcpu, val); 7029 return ret; 7030 } 7031 7032 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 7033 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 7034 7035 return 0; 7036 } 7037 7038 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 7039 { 7040 int ret; 7041 7042 if (in) 7043 ret = kvm_fast_pio_in(vcpu, size, port); 7044 else 7045 ret = kvm_fast_pio_out(vcpu, size, port); 7046 return ret && kvm_skip_emulated_instruction(vcpu); 7047 } 7048 EXPORT_SYMBOL_GPL(kvm_fast_pio); 7049 7050 static int kvmclock_cpu_down_prep(unsigned int cpu) 7051 { 7052 __this_cpu_write(cpu_tsc_khz, 0); 7053 return 0; 7054 } 7055 7056 static void tsc_khz_changed(void *data) 7057 { 7058 struct cpufreq_freqs *freq = data; 7059 unsigned long khz = 0; 7060 7061 if (data) 7062 khz = freq->new; 7063 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 7064 khz = cpufreq_quick_get(raw_smp_processor_id()); 7065 if (!khz) 7066 khz = tsc_khz; 7067 __this_cpu_write(cpu_tsc_khz, khz); 7068 } 7069 7070 #ifdef CONFIG_X86_64 7071 static void kvm_hyperv_tsc_notifier(void) 7072 { 7073 struct kvm *kvm; 7074 struct kvm_vcpu *vcpu; 7075 int cpu; 7076 7077 mutex_lock(&kvm_lock); 7078 list_for_each_entry(kvm, &vm_list, vm_list) 7079 kvm_make_mclock_inprogress_request(kvm); 7080 7081 hyperv_stop_tsc_emulation(); 7082 7083 /* TSC frequency always matches when on Hyper-V */ 7084 for_each_present_cpu(cpu) 7085 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 7086 kvm_max_guest_tsc_khz = tsc_khz; 7087 7088 list_for_each_entry(kvm, &vm_list, vm_list) { 7089 struct kvm_arch *ka = &kvm->arch; 7090 7091 spin_lock(&ka->pvclock_gtod_sync_lock); 7092 7093 pvclock_update_vm_gtod_copy(kvm); 7094 7095 kvm_for_each_vcpu(cpu, vcpu, kvm) 7096 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7097 7098 kvm_for_each_vcpu(cpu, vcpu, kvm) 7099 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 7100 7101 spin_unlock(&ka->pvclock_gtod_sync_lock); 7102 } 7103 mutex_unlock(&kvm_lock); 7104 } 7105 #endif 7106 7107 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 7108 { 7109 struct kvm *kvm; 7110 struct kvm_vcpu *vcpu; 7111 int i, send_ipi = 0; 7112 7113 /* 7114 * We allow guests to temporarily run on slowing clocks, 7115 * provided we notify them after, or to run on accelerating 7116 * clocks, provided we notify them before. Thus time never 7117 * goes backwards. 7118 * 7119 * However, we have a problem. We can't atomically update 7120 * the frequency of a given CPU from this function; it is 7121 * merely a notifier, which can be called from any CPU. 7122 * Changing the TSC frequency at arbitrary points in time 7123 * requires a recomputation of local variables related to 7124 * the TSC for each VCPU. We must flag these local variables 7125 * to be updated and be sure the update takes place with the 7126 * new frequency before any guests proceed. 7127 * 7128 * Unfortunately, the combination of hotplug CPU and frequency 7129 * change creates an intractable locking scenario; the order 7130 * of when these callouts happen is undefined with respect to 7131 * CPU hotplug, and they can race with each other. As such, 7132 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 7133 * undefined; you can actually have a CPU frequency change take 7134 * place in between the computation of X and the setting of the 7135 * variable. To protect against this problem, all updates of 7136 * the per_cpu tsc_khz variable are done in an interrupt 7137 * protected IPI, and all callers wishing to update the value 7138 * must wait for a synchronous IPI to complete (which is trivial 7139 * if the caller is on the CPU already). This establishes the 7140 * necessary total order on variable updates. 7141 * 7142 * Note that because a guest time update may take place 7143 * anytime after the setting of the VCPU's request bit, the 7144 * correct TSC value must be set before the request. However, 7145 * to ensure the update actually makes it to any guest which 7146 * starts running in hardware virtualization between the set 7147 * and the acquisition of the spinlock, we must also ping the 7148 * CPU after setting the request bit. 7149 * 7150 */ 7151 7152 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 7153 7154 mutex_lock(&kvm_lock); 7155 list_for_each_entry(kvm, &vm_list, vm_list) { 7156 kvm_for_each_vcpu(i, vcpu, kvm) { 7157 if (vcpu->cpu != cpu) 7158 continue; 7159 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7160 if (vcpu->cpu != raw_smp_processor_id()) 7161 send_ipi = 1; 7162 } 7163 } 7164 mutex_unlock(&kvm_lock); 7165 7166 if (freq->old < freq->new && send_ipi) { 7167 /* 7168 * We upscale the frequency. Must make the guest 7169 * doesn't see old kvmclock values while running with 7170 * the new frequency, otherwise we risk the guest sees 7171 * time go backwards. 7172 * 7173 * In case we update the frequency for another cpu 7174 * (which might be in guest context) send an interrupt 7175 * to kick the cpu out of guest context. Next time 7176 * guest context is entered kvmclock will be updated, 7177 * so the guest will not see stale values. 7178 */ 7179 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 7180 } 7181 } 7182 7183 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 7184 void *data) 7185 { 7186 struct cpufreq_freqs *freq = data; 7187 int cpu; 7188 7189 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 7190 return 0; 7191 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 7192 return 0; 7193 7194 for_each_cpu(cpu, freq->policy->cpus) 7195 __kvmclock_cpufreq_notifier(freq, cpu); 7196 7197 return 0; 7198 } 7199 7200 static struct notifier_block kvmclock_cpufreq_notifier_block = { 7201 .notifier_call = kvmclock_cpufreq_notifier 7202 }; 7203 7204 static int kvmclock_cpu_online(unsigned int cpu) 7205 { 7206 tsc_khz_changed(NULL); 7207 return 0; 7208 } 7209 7210 static void kvm_timer_init(void) 7211 { 7212 max_tsc_khz = tsc_khz; 7213 7214 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 7215 #ifdef CONFIG_CPU_FREQ 7216 struct cpufreq_policy *policy; 7217 int cpu; 7218 7219 cpu = get_cpu(); 7220 policy = cpufreq_cpu_get(cpu); 7221 if (policy) { 7222 if (policy->cpuinfo.max_freq) 7223 max_tsc_khz = policy->cpuinfo.max_freq; 7224 cpufreq_cpu_put(policy); 7225 } 7226 put_cpu(); 7227 #endif 7228 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 7229 CPUFREQ_TRANSITION_NOTIFIER); 7230 } 7231 7232 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 7233 kvmclock_cpu_online, kvmclock_cpu_down_prep); 7234 } 7235 7236 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 7237 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); 7238 7239 int kvm_is_in_guest(void) 7240 { 7241 return __this_cpu_read(current_vcpu) != NULL; 7242 } 7243 7244 static int kvm_is_user_mode(void) 7245 { 7246 int user_mode = 3; 7247 7248 if (__this_cpu_read(current_vcpu)) 7249 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu)); 7250 7251 return user_mode != 0; 7252 } 7253 7254 static unsigned long kvm_get_guest_ip(void) 7255 { 7256 unsigned long ip = 0; 7257 7258 if (__this_cpu_read(current_vcpu)) 7259 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 7260 7261 return ip; 7262 } 7263 7264 static void kvm_handle_intel_pt_intr(void) 7265 { 7266 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); 7267 7268 kvm_make_request(KVM_REQ_PMI, vcpu); 7269 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, 7270 (unsigned long *)&vcpu->arch.pmu.global_status); 7271 } 7272 7273 static struct perf_guest_info_callbacks kvm_guest_cbs = { 7274 .is_in_guest = kvm_is_in_guest, 7275 .is_user_mode = kvm_is_user_mode, 7276 .get_guest_ip = kvm_get_guest_ip, 7277 .handle_intel_pt_intr = kvm_handle_intel_pt_intr, 7278 }; 7279 7280 #ifdef CONFIG_X86_64 7281 static void pvclock_gtod_update_fn(struct work_struct *work) 7282 { 7283 struct kvm *kvm; 7284 7285 struct kvm_vcpu *vcpu; 7286 int i; 7287 7288 mutex_lock(&kvm_lock); 7289 list_for_each_entry(kvm, &vm_list, vm_list) 7290 kvm_for_each_vcpu(i, vcpu, kvm) 7291 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7292 atomic_set(&kvm_guest_has_master_clock, 0); 7293 mutex_unlock(&kvm_lock); 7294 } 7295 7296 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 7297 7298 /* 7299 * Notification about pvclock gtod data update. 7300 */ 7301 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 7302 void *priv) 7303 { 7304 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 7305 struct timekeeper *tk = priv; 7306 7307 update_pvclock_gtod(tk); 7308 7309 /* disable master clock if host does not trust, or does not 7310 * use, TSC based clocksource. 7311 */ 7312 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 7313 atomic_read(&kvm_guest_has_master_clock) != 0) 7314 queue_work(system_long_wq, &pvclock_gtod_work); 7315 7316 return 0; 7317 } 7318 7319 static struct notifier_block pvclock_gtod_notifier = { 7320 .notifier_call = pvclock_gtod_notify, 7321 }; 7322 #endif 7323 7324 int kvm_arch_init(void *opaque) 7325 { 7326 struct kvm_x86_init_ops *ops = opaque; 7327 int r; 7328 7329 if (kvm_x86_ops.hardware_enable) { 7330 printk(KERN_ERR "kvm: already loaded the other module\n"); 7331 r = -EEXIST; 7332 goto out; 7333 } 7334 7335 if (!ops->cpu_has_kvm_support()) { 7336 pr_err_ratelimited("kvm: no hardware support\n"); 7337 r = -EOPNOTSUPP; 7338 goto out; 7339 } 7340 if (ops->disabled_by_bios()) { 7341 pr_err_ratelimited("kvm: disabled by bios\n"); 7342 r = -EOPNOTSUPP; 7343 goto out; 7344 } 7345 7346 /* 7347 * KVM explicitly assumes that the guest has an FPU and 7348 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 7349 * vCPU's FPU state as a fxregs_state struct. 7350 */ 7351 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 7352 printk(KERN_ERR "kvm: inadequate fpu\n"); 7353 r = -EOPNOTSUPP; 7354 goto out; 7355 } 7356 7357 r = -ENOMEM; 7358 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), 7359 __alignof__(struct fpu), SLAB_ACCOUNT, 7360 NULL); 7361 if (!x86_fpu_cache) { 7362 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); 7363 goto out; 7364 } 7365 7366 x86_emulator_cache = kvm_alloc_emulator_cache(); 7367 if (!x86_emulator_cache) { 7368 pr_err("kvm: failed to allocate cache for x86 emulator\n"); 7369 goto out_free_x86_fpu_cache; 7370 } 7371 7372 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 7373 if (!shared_msrs) { 7374 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 7375 goto out_free_x86_emulator_cache; 7376 } 7377 7378 r = kvm_mmu_module_init(); 7379 if (r) 7380 goto out_free_percpu; 7381 7382 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 7383 PT_DIRTY_MASK, PT64_NX_MASK, 0, 7384 PT_PRESENT_MASK, 0, sme_me_mask); 7385 kvm_timer_init(); 7386 7387 perf_register_guest_info_callbacks(&kvm_guest_cbs); 7388 7389 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 7390 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 7391 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; 7392 } 7393 7394 kvm_lapic_init(); 7395 if (pi_inject_timer == -1) 7396 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); 7397 #ifdef CONFIG_X86_64 7398 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 7399 7400 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 7401 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 7402 #endif 7403 7404 return 0; 7405 7406 out_free_percpu: 7407 free_percpu(shared_msrs); 7408 out_free_x86_emulator_cache: 7409 kmem_cache_destroy(x86_emulator_cache); 7410 out_free_x86_fpu_cache: 7411 kmem_cache_destroy(x86_fpu_cache); 7412 out: 7413 return r; 7414 } 7415 7416 void kvm_arch_exit(void) 7417 { 7418 #ifdef CONFIG_X86_64 7419 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 7420 clear_hv_tscchange_cb(); 7421 #endif 7422 kvm_lapic_exit(); 7423 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 7424 7425 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 7426 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 7427 CPUFREQ_TRANSITION_NOTIFIER); 7428 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 7429 #ifdef CONFIG_X86_64 7430 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 7431 #endif 7432 kvm_x86_ops.hardware_enable = NULL; 7433 kvm_mmu_module_exit(); 7434 free_percpu(shared_msrs); 7435 kmem_cache_destroy(x86_fpu_cache); 7436 } 7437 7438 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 7439 { 7440 ++vcpu->stat.halt_exits; 7441 if (lapic_in_kernel(vcpu)) { 7442 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 7443 return 1; 7444 } else { 7445 vcpu->run->exit_reason = KVM_EXIT_HLT; 7446 return 0; 7447 } 7448 } 7449 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 7450 7451 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 7452 { 7453 int ret = kvm_skip_emulated_instruction(vcpu); 7454 /* 7455 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 7456 * KVM_EXIT_DEBUG here. 7457 */ 7458 return kvm_vcpu_halt(vcpu) && ret; 7459 } 7460 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 7461 7462 #ifdef CONFIG_X86_64 7463 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 7464 unsigned long clock_type) 7465 { 7466 struct kvm_clock_pairing clock_pairing; 7467 struct timespec64 ts; 7468 u64 cycle; 7469 int ret; 7470 7471 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 7472 return -KVM_EOPNOTSUPP; 7473 7474 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) 7475 return -KVM_EOPNOTSUPP; 7476 7477 clock_pairing.sec = ts.tv_sec; 7478 clock_pairing.nsec = ts.tv_nsec; 7479 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 7480 clock_pairing.flags = 0; 7481 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 7482 7483 ret = 0; 7484 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 7485 sizeof(struct kvm_clock_pairing))) 7486 ret = -KVM_EFAULT; 7487 7488 return ret; 7489 } 7490 #endif 7491 7492 /* 7493 * kvm_pv_kick_cpu_op: Kick a vcpu. 7494 * 7495 * @apicid - apicid of vcpu to be kicked. 7496 */ 7497 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 7498 { 7499 struct kvm_lapic_irq lapic_irq; 7500 7501 lapic_irq.shorthand = APIC_DEST_NOSHORT; 7502 lapic_irq.dest_mode = APIC_DEST_PHYSICAL; 7503 lapic_irq.level = 0; 7504 lapic_irq.dest_id = apicid; 7505 lapic_irq.msi_redir_hint = false; 7506 7507 lapic_irq.delivery_mode = APIC_DM_REMRD; 7508 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 7509 } 7510 7511 bool kvm_apicv_activated(struct kvm *kvm) 7512 { 7513 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); 7514 } 7515 EXPORT_SYMBOL_GPL(kvm_apicv_activated); 7516 7517 void kvm_apicv_init(struct kvm *kvm, bool enable) 7518 { 7519 if (enable) 7520 clear_bit(APICV_INHIBIT_REASON_DISABLE, 7521 &kvm->arch.apicv_inhibit_reasons); 7522 else 7523 set_bit(APICV_INHIBIT_REASON_DISABLE, 7524 &kvm->arch.apicv_inhibit_reasons); 7525 } 7526 EXPORT_SYMBOL_GPL(kvm_apicv_init); 7527 7528 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id) 7529 { 7530 struct kvm_vcpu *target = NULL; 7531 struct kvm_apic_map *map; 7532 7533 rcu_read_lock(); 7534 map = rcu_dereference(kvm->arch.apic_map); 7535 7536 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 7537 target = map->phys_map[dest_id]->vcpu; 7538 7539 rcu_read_unlock(); 7540 7541 if (target && READ_ONCE(target->ready)) 7542 kvm_vcpu_yield_to(target); 7543 } 7544 7545 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 7546 { 7547 unsigned long nr, a0, a1, a2, a3, ret; 7548 int op_64_bit; 7549 7550 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 7551 return kvm_hv_hypercall(vcpu); 7552 7553 nr = kvm_rax_read(vcpu); 7554 a0 = kvm_rbx_read(vcpu); 7555 a1 = kvm_rcx_read(vcpu); 7556 a2 = kvm_rdx_read(vcpu); 7557 a3 = kvm_rsi_read(vcpu); 7558 7559 trace_kvm_hypercall(nr, a0, a1, a2, a3); 7560 7561 op_64_bit = is_64_bit_mode(vcpu); 7562 if (!op_64_bit) { 7563 nr &= 0xFFFFFFFF; 7564 a0 &= 0xFFFFFFFF; 7565 a1 &= 0xFFFFFFFF; 7566 a2 &= 0xFFFFFFFF; 7567 a3 &= 0xFFFFFFFF; 7568 } 7569 7570 if (kvm_x86_ops.get_cpl(vcpu) != 0) { 7571 ret = -KVM_EPERM; 7572 goto out; 7573 } 7574 7575 switch (nr) { 7576 case KVM_HC_VAPIC_POLL_IRQ: 7577 ret = 0; 7578 break; 7579 case KVM_HC_KICK_CPU: 7580 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 7581 kvm_sched_yield(vcpu->kvm, a1); 7582 ret = 0; 7583 break; 7584 #ifdef CONFIG_X86_64 7585 case KVM_HC_CLOCK_PAIRING: 7586 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 7587 break; 7588 #endif 7589 case KVM_HC_SEND_IPI: 7590 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 7591 break; 7592 case KVM_HC_SCHED_YIELD: 7593 kvm_sched_yield(vcpu->kvm, a0); 7594 ret = 0; 7595 break; 7596 default: 7597 ret = -KVM_ENOSYS; 7598 break; 7599 } 7600 out: 7601 if (!op_64_bit) 7602 ret = (u32)ret; 7603 kvm_rax_write(vcpu, ret); 7604 7605 ++vcpu->stat.hypercalls; 7606 return kvm_skip_emulated_instruction(vcpu); 7607 } 7608 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 7609 7610 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 7611 { 7612 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7613 char instruction[3]; 7614 unsigned long rip = kvm_rip_read(vcpu); 7615 7616 kvm_x86_ops.patch_hypercall(vcpu, instruction); 7617 7618 return emulator_write_emulated(ctxt, rip, instruction, 3, 7619 &ctxt->exception); 7620 } 7621 7622 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 7623 { 7624 return vcpu->run->request_interrupt_window && 7625 likely(!pic_in_kernel(vcpu->kvm)); 7626 } 7627 7628 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 7629 { 7630 struct kvm_run *kvm_run = vcpu->run; 7631 7632 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 7633 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 7634 kvm_run->cr8 = kvm_get_cr8(vcpu); 7635 kvm_run->apic_base = kvm_get_apic_base(vcpu); 7636 kvm_run->ready_for_interrupt_injection = 7637 pic_in_kernel(vcpu->kvm) || 7638 kvm_vcpu_ready_for_interrupt_injection(vcpu); 7639 } 7640 7641 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 7642 { 7643 int max_irr, tpr; 7644 7645 if (!kvm_x86_ops.update_cr8_intercept) 7646 return; 7647 7648 if (!lapic_in_kernel(vcpu)) 7649 return; 7650 7651 if (vcpu->arch.apicv_active) 7652 return; 7653 7654 if (!vcpu->arch.apic->vapic_addr) 7655 max_irr = kvm_lapic_find_highest_irr(vcpu); 7656 else 7657 max_irr = -1; 7658 7659 if (max_irr != -1) 7660 max_irr >>= 4; 7661 7662 tpr = kvm_lapic_get_cr8(vcpu); 7663 7664 kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr); 7665 } 7666 7667 static int inject_pending_event(struct kvm_vcpu *vcpu) 7668 { 7669 int r; 7670 7671 /* try to reinject previous events if any */ 7672 7673 if (vcpu->arch.exception.injected) 7674 kvm_x86_ops.queue_exception(vcpu); 7675 /* 7676 * Do not inject an NMI or interrupt if there is a pending 7677 * exception. Exceptions and interrupts are recognized at 7678 * instruction boundaries, i.e. the start of an instruction. 7679 * Trap-like exceptions, e.g. #DB, have higher priority than 7680 * NMIs and interrupts, i.e. traps are recognized before an 7681 * NMI/interrupt that's pending on the same instruction. 7682 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 7683 * priority, but are only generated (pended) during instruction 7684 * execution, i.e. a pending fault-like exception means the 7685 * fault occurred on the *previous* instruction and must be 7686 * serviced prior to recognizing any new events in order to 7687 * fully complete the previous instruction. 7688 */ 7689 else if (!vcpu->arch.exception.pending) { 7690 if (vcpu->arch.nmi_injected) 7691 kvm_x86_ops.set_nmi(vcpu); 7692 else if (vcpu->arch.interrupt.injected) 7693 kvm_x86_ops.set_irq(vcpu); 7694 } 7695 7696 /* 7697 * Call check_nested_events() even if we reinjected a previous event 7698 * in order for caller to determine if it should require immediate-exit 7699 * from L2 to L1 due to pending L1 events which require exit 7700 * from L2 to L1. 7701 */ 7702 if (is_guest_mode(vcpu) && kvm_x86_ops.check_nested_events) { 7703 r = kvm_x86_ops.check_nested_events(vcpu); 7704 if (r != 0) 7705 return r; 7706 } 7707 7708 /* try to inject new event if pending */ 7709 if (vcpu->arch.exception.pending) { 7710 trace_kvm_inj_exception(vcpu->arch.exception.nr, 7711 vcpu->arch.exception.has_error_code, 7712 vcpu->arch.exception.error_code); 7713 7714 WARN_ON_ONCE(vcpu->arch.exception.injected); 7715 vcpu->arch.exception.pending = false; 7716 vcpu->arch.exception.injected = true; 7717 7718 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 7719 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 7720 X86_EFLAGS_RF); 7721 7722 if (vcpu->arch.exception.nr == DB_VECTOR) { 7723 /* 7724 * This code assumes that nSVM doesn't use 7725 * check_nested_events(). If it does, the 7726 * DR6/DR7 changes should happen before L1 7727 * gets a #VMEXIT for an intercepted #DB in 7728 * L2. (Under VMX, on the other hand, the 7729 * DR6/DR7 changes should not happen in the 7730 * event of a VM-exit to L1 for an intercepted 7731 * #DB in L2.) 7732 */ 7733 kvm_deliver_exception_payload(vcpu); 7734 if (vcpu->arch.dr7 & DR7_GD) { 7735 vcpu->arch.dr7 &= ~DR7_GD; 7736 kvm_update_dr7(vcpu); 7737 } 7738 } 7739 7740 kvm_x86_ops.queue_exception(vcpu); 7741 } 7742 7743 /* Don't consider new event if we re-injected an event */ 7744 if (kvm_event_needs_reinjection(vcpu)) 7745 return 0; 7746 7747 if (vcpu->arch.smi_pending && !is_smm(vcpu) && 7748 kvm_x86_ops.smi_allowed(vcpu)) { 7749 vcpu->arch.smi_pending = false; 7750 ++vcpu->arch.smi_count; 7751 enter_smm(vcpu); 7752 } else if (vcpu->arch.nmi_pending && kvm_x86_ops.nmi_allowed(vcpu)) { 7753 --vcpu->arch.nmi_pending; 7754 vcpu->arch.nmi_injected = true; 7755 kvm_x86_ops.set_nmi(vcpu); 7756 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 7757 /* 7758 * Because interrupts can be injected asynchronously, we are 7759 * calling check_nested_events again here to avoid a race condition. 7760 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 7761 * proposal and current concerns. Perhaps we should be setting 7762 * KVM_REQ_EVENT only on certain events and not unconditionally? 7763 */ 7764 if (is_guest_mode(vcpu) && kvm_x86_ops.check_nested_events) { 7765 r = kvm_x86_ops.check_nested_events(vcpu); 7766 if (r != 0) 7767 return r; 7768 } 7769 if (kvm_x86_ops.interrupt_allowed(vcpu)) { 7770 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 7771 false); 7772 kvm_x86_ops.set_irq(vcpu); 7773 } 7774 } 7775 7776 return 0; 7777 } 7778 7779 static void process_nmi(struct kvm_vcpu *vcpu) 7780 { 7781 unsigned limit = 2; 7782 7783 /* 7784 * x86 is limited to one NMI running, and one NMI pending after it. 7785 * If an NMI is already in progress, limit further NMIs to just one. 7786 * Otherwise, allow two (and we'll inject the first one immediately). 7787 */ 7788 if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 7789 limit = 1; 7790 7791 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 7792 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 7793 kvm_make_request(KVM_REQ_EVENT, vcpu); 7794 } 7795 7796 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 7797 { 7798 u32 flags = 0; 7799 flags |= seg->g << 23; 7800 flags |= seg->db << 22; 7801 flags |= seg->l << 21; 7802 flags |= seg->avl << 20; 7803 flags |= seg->present << 15; 7804 flags |= seg->dpl << 13; 7805 flags |= seg->s << 12; 7806 flags |= seg->type << 8; 7807 return flags; 7808 } 7809 7810 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 7811 { 7812 struct kvm_segment seg; 7813 int offset; 7814 7815 kvm_get_segment(vcpu, &seg, n); 7816 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 7817 7818 if (n < 3) 7819 offset = 0x7f84 + n * 12; 7820 else 7821 offset = 0x7f2c + (n - 3) * 12; 7822 7823 put_smstate(u32, buf, offset + 8, seg.base); 7824 put_smstate(u32, buf, offset + 4, seg.limit); 7825 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 7826 } 7827 7828 #ifdef CONFIG_X86_64 7829 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 7830 { 7831 struct kvm_segment seg; 7832 int offset; 7833 u16 flags; 7834 7835 kvm_get_segment(vcpu, &seg, n); 7836 offset = 0x7e00 + n * 16; 7837 7838 flags = enter_smm_get_segment_flags(&seg) >> 8; 7839 put_smstate(u16, buf, offset, seg.selector); 7840 put_smstate(u16, buf, offset + 2, flags); 7841 put_smstate(u32, buf, offset + 4, seg.limit); 7842 put_smstate(u64, buf, offset + 8, seg.base); 7843 } 7844 #endif 7845 7846 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 7847 { 7848 struct desc_ptr dt; 7849 struct kvm_segment seg; 7850 unsigned long val; 7851 int i; 7852 7853 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 7854 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 7855 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 7856 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 7857 7858 for (i = 0; i < 8; i++) 7859 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 7860 7861 kvm_get_dr(vcpu, 6, &val); 7862 put_smstate(u32, buf, 0x7fcc, (u32)val); 7863 kvm_get_dr(vcpu, 7, &val); 7864 put_smstate(u32, buf, 0x7fc8, (u32)val); 7865 7866 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 7867 put_smstate(u32, buf, 0x7fc4, seg.selector); 7868 put_smstate(u32, buf, 0x7f64, seg.base); 7869 put_smstate(u32, buf, 0x7f60, seg.limit); 7870 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 7871 7872 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 7873 put_smstate(u32, buf, 0x7fc0, seg.selector); 7874 put_smstate(u32, buf, 0x7f80, seg.base); 7875 put_smstate(u32, buf, 0x7f7c, seg.limit); 7876 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 7877 7878 kvm_x86_ops.get_gdt(vcpu, &dt); 7879 put_smstate(u32, buf, 0x7f74, dt.address); 7880 put_smstate(u32, buf, 0x7f70, dt.size); 7881 7882 kvm_x86_ops.get_idt(vcpu, &dt); 7883 put_smstate(u32, buf, 0x7f58, dt.address); 7884 put_smstate(u32, buf, 0x7f54, dt.size); 7885 7886 for (i = 0; i < 6; i++) 7887 enter_smm_save_seg_32(vcpu, buf, i); 7888 7889 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 7890 7891 /* revision id */ 7892 put_smstate(u32, buf, 0x7efc, 0x00020000); 7893 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 7894 } 7895 7896 #ifdef CONFIG_X86_64 7897 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 7898 { 7899 struct desc_ptr dt; 7900 struct kvm_segment seg; 7901 unsigned long val; 7902 int i; 7903 7904 for (i = 0; i < 16; i++) 7905 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 7906 7907 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 7908 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 7909 7910 kvm_get_dr(vcpu, 6, &val); 7911 put_smstate(u64, buf, 0x7f68, val); 7912 kvm_get_dr(vcpu, 7, &val); 7913 put_smstate(u64, buf, 0x7f60, val); 7914 7915 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 7916 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 7917 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 7918 7919 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 7920 7921 /* revision id */ 7922 put_smstate(u32, buf, 0x7efc, 0x00020064); 7923 7924 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 7925 7926 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 7927 put_smstate(u16, buf, 0x7e90, seg.selector); 7928 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 7929 put_smstate(u32, buf, 0x7e94, seg.limit); 7930 put_smstate(u64, buf, 0x7e98, seg.base); 7931 7932 kvm_x86_ops.get_idt(vcpu, &dt); 7933 put_smstate(u32, buf, 0x7e84, dt.size); 7934 put_smstate(u64, buf, 0x7e88, dt.address); 7935 7936 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 7937 put_smstate(u16, buf, 0x7e70, seg.selector); 7938 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 7939 put_smstate(u32, buf, 0x7e74, seg.limit); 7940 put_smstate(u64, buf, 0x7e78, seg.base); 7941 7942 kvm_x86_ops.get_gdt(vcpu, &dt); 7943 put_smstate(u32, buf, 0x7e64, dt.size); 7944 put_smstate(u64, buf, 0x7e68, dt.address); 7945 7946 for (i = 0; i < 6; i++) 7947 enter_smm_save_seg_64(vcpu, buf, i); 7948 } 7949 #endif 7950 7951 static void enter_smm(struct kvm_vcpu *vcpu) 7952 { 7953 struct kvm_segment cs, ds; 7954 struct desc_ptr dt; 7955 char buf[512]; 7956 u32 cr0; 7957 7958 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 7959 memset(buf, 0, 512); 7960 #ifdef CONFIG_X86_64 7961 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 7962 enter_smm_save_state_64(vcpu, buf); 7963 else 7964 #endif 7965 enter_smm_save_state_32(vcpu, buf); 7966 7967 /* 7968 * Give pre_enter_smm() a chance to make ISA-specific changes to the 7969 * vCPU state (e.g. leave guest mode) after we've saved the state into 7970 * the SMM state-save area. 7971 */ 7972 kvm_x86_ops.pre_enter_smm(vcpu, buf); 7973 7974 vcpu->arch.hflags |= HF_SMM_MASK; 7975 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 7976 7977 if (kvm_x86_ops.get_nmi_mask(vcpu)) 7978 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 7979 else 7980 kvm_x86_ops.set_nmi_mask(vcpu, true); 7981 7982 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 7983 kvm_rip_write(vcpu, 0x8000); 7984 7985 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 7986 kvm_x86_ops.set_cr0(vcpu, cr0); 7987 vcpu->arch.cr0 = cr0; 7988 7989 kvm_x86_ops.set_cr4(vcpu, 0); 7990 7991 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 7992 dt.address = dt.size = 0; 7993 kvm_x86_ops.set_idt(vcpu, &dt); 7994 7995 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 7996 7997 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 7998 cs.base = vcpu->arch.smbase; 7999 8000 ds.selector = 0; 8001 ds.base = 0; 8002 8003 cs.limit = ds.limit = 0xffffffff; 8004 cs.type = ds.type = 0x3; 8005 cs.dpl = ds.dpl = 0; 8006 cs.db = ds.db = 0; 8007 cs.s = ds.s = 1; 8008 cs.l = ds.l = 0; 8009 cs.g = ds.g = 1; 8010 cs.avl = ds.avl = 0; 8011 cs.present = ds.present = 1; 8012 cs.unusable = ds.unusable = 0; 8013 cs.padding = ds.padding = 0; 8014 8015 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 8016 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 8017 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 8018 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 8019 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 8020 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 8021 8022 #ifdef CONFIG_X86_64 8023 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 8024 kvm_x86_ops.set_efer(vcpu, 0); 8025 #endif 8026 8027 kvm_update_cpuid(vcpu); 8028 kvm_mmu_reset_context(vcpu); 8029 } 8030 8031 static void process_smi(struct kvm_vcpu *vcpu) 8032 { 8033 vcpu->arch.smi_pending = true; 8034 kvm_make_request(KVM_REQ_EVENT, vcpu); 8035 } 8036 8037 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 8038 unsigned long *vcpu_bitmap) 8039 { 8040 cpumask_var_t cpus; 8041 8042 zalloc_cpumask_var(&cpus, GFP_ATOMIC); 8043 8044 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, 8045 vcpu_bitmap, cpus); 8046 8047 free_cpumask_var(cpus); 8048 } 8049 8050 void kvm_make_scan_ioapic_request(struct kvm *kvm) 8051 { 8052 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 8053 } 8054 8055 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 8056 { 8057 if (!lapic_in_kernel(vcpu)) 8058 return; 8059 8060 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm); 8061 kvm_apic_update_apicv(vcpu); 8062 kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu); 8063 } 8064 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); 8065 8066 /* 8067 * NOTE: Do not hold any lock prior to calling this. 8068 * 8069 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be 8070 * locked, because it calls __x86_set_memory_region() which does 8071 * synchronize_srcu(&kvm->srcu). 8072 */ 8073 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) 8074 { 8075 unsigned long old, new, expected; 8076 8077 if (!kvm_x86_ops.check_apicv_inhibit_reasons || 8078 !kvm_x86_ops.check_apicv_inhibit_reasons(bit)) 8079 return; 8080 8081 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons); 8082 do { 8083 expected = new = old; 8084 if (activate) 8085 __clear_bit(bit, &new); 8086 else 8087 __set_bit(bit, &new); 8088 if (new == old) 8089 break; 8090 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new); 8091 } while (old != expected); 8092 8093 if (!!old == !!new) 8094 return; 8095 8096 trace_kvm_apicv_update_request(activate, bit); 8097 if (kvm_x86_ops.pre_update_apicv_exec_ctrl) 8098 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate); 8099 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); 8100 } 8101 EXPORT_SYMBOL_GPL(kvm_request_apicv_update); 8102 8103 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 8104 { 8105 if (!kvm_apic_present(vcpu)) 8106 return; 8107 8108 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 8109 8110 if (irqchip_split(vcpu->kvm)) 8111 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 8112 else { 8113 if (vcpu->arch.apicv_active) 8114 kvm_x86_ops.sync_pir_to_irr(vcpu); 8115 if (ioapic_in_kernel(vcpu->kvm)) 8116 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 8117 } 8118 8119 if (is_guest_mode(vcpu)) 8120 vcpu->arch.load_eoi_exitmap_pending = true; 8121 else 8122 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 8123 } 8124 8125 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 8126 { 8127 u64 eoi_exit_bitmap[4]; 8128 8129 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 8130 return; 8131 8132 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, 8133 vcpu_to_synic(vcpu)->vec_bitmap, 256); 8134 kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap); 8135 } 8136 8137 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 8138 unsigned long start, unsigned long end, 8139 bool blockable) 8140 { 8141 unsigned long apic_address; 8142 8143 /* 8144 * The physical address of apic access page is stored in the VMCS. 8145 * Update it when it becomes invalid. 8146 */ 8147 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 8148 if (start <= apic_address && apic_address < end) 8149 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 8150 8151 return 0; 8152 } 8153 8154 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 8155 { 8156 struct page *page = NULL; 8157 8158 if (!lapic_in_kernel(vcpu)) 8159 return; 8160 8161 if (!kvm_x86_ops.set_apic_access_page_addr) 8162 return; 8163 8164 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 8165 if (is_error_page(page)) 8166 return; 8167 kvm_x86_ops.set_apic_access_page_addr(vcpu, page_to_phys(page)); 8168 8169 /* 8170 * Do not pin apic access page in memory, the MMU notifier 8171 * will call us again if it is migrated or swapped out. 8172 */ 8173 put_page(page); 8174 } 8175 8176 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 8177 { 8178 smp_send_reschedule(vcpu->cpu); 8179 } 8180 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 8181 8182 /* 8183 * Returns 1 to let vcpu_run() continue the guest execution loop without 8184 * exiting to the userspace. Otherwise, the value will be returned to the 8185 * userspace. 8186 */ 8187 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 8188 { 8189 int r; 8190 bool req_int_win = 8191 dm_request_for_irq_injection(vcpu) && 8192 kvm_cpu_accept_dm_intr(vcpu); 8193 enum exit_fastpath_completion exit_fastpath = EXIT_FASTPATH_NONE; 8194 8195 bool req_immediate_exit = false; 8196 8197 if (kvm_request_pending(vcpu)) { 8198 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) { 8199 if (unlikely(!kvm_x86_ops.get_vmcs12_pages(vcpu))) { 8200 r = 0; 8201 goto out; 8202 } 8203 } 8204 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 8205 kvm_mmu_unload(vcpu); 8206 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 8207 __kvm_migrate_timers(vcpu); 8208 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 8209 kvm_gen_update_masterclock(vcpu->kvm); 8210 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 8211 kvm_gen_kvmclock_update(vcpu); 8212 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 8213 r = kvm_guest_time_update(vcpu); 8214 if (unlikely(r)) 8215 goto out; 8216 } 8217 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 8218 kvm_mmu_sync_roots(vcpu); 8219 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) 8220 kvm_mmu_load_pgd(vcpu); 8221 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 8222 kvm_vcpu_flush_tlb(vcpu, true); 8223 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 8224 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 8225 r = 0; 8226 goto out; 8227 } 8228 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 8229 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 8230 vcpu->mmio_needed = 0; 8231 r = 0; 8232 goto out; 8233 } 8234 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 8235 /* Page is swapped out. Do synthetic halt */ 8236 vcpu->arch.apf.halted = true; 8237 r = 1; 8238 goto out; 8239 } 8240 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 8241 record_steal_time(vcpu); 8242 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 8243 process_smi(vcpu); 8244 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 8245 process_nmi(vcpu); 8246 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 8247 kvm_pmu_handle_event(vcpu); 8248 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 8249 kvm_pmu_deliver_pmi(vcpu); 8250 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 8251 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 8252 if (test_bit(vcpu->arch.pending_ioapic_eoi, 8253 vcpu->arch.ioapic_handled_vectors)) { 8254 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 8255 vcpu->run->eoi.vector = 8256 vcpu->arch.pending_ioapic_eoi; 8257 r = 0; 8258 goto out; 8259 } 8260 } 8261 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 8262 vcpu_scan_ioapic(vcpu); 8263 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 8264 vcpu_load_eoi_exitmap(vcpu); 8265 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 8266 kvm_vcpu_reload_apic_access_page(vcpu); 8267 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 8268 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 8269 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 8270 r = 0; 8271 goto out; 8272 } 8273 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 8274 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 8275 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 8276 r = 0; 8277 goto out; 8278 } 8279 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 8280 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 8281 vcpu->run->hyperv = vcpu->arch.hyperv.exit; 8282 r = 0; 8283 goto out; 8284 } 8285 8286 /* 8287 * KVM_REQ_HV_STIMER has to be processed after 8288 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 8289 * depend on the guest clock being up-to-date 8290 */ 8291 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 8292 kvm_hv_process_stimers(vcpu); 8293 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 8294 kvm_vcpu_update_apicv(vcpu); 8295 } 8296 8297 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 8298 ++vcpu->stat.req_event; 8299 kvm_apic_accept_events(vcpu); 8300 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 8301 r = 1; 8302 goto out; 8303 } 8304 8305 if (inject_pending_event(vcpu) != 0) 8306 req_immediate_exit = true; 8307 else { 8308 /* Enable SMI/NMI/IRQ window open exits if needed. 8309 * 8310 * SMIs have three cases: 8311 * 1) They can be nested, and then there is nothing to 8312 * do here because RSM will cause a vmexit anyway. 8313 * 2) There is an ISA-specific reason why SMI cannot be 8314 * injected, and the moment when this changes can be 8315 * intercepted. 8316 * 3) Or the SMI can be pending because 8317 * inject_pending_event has completed the injection 8318 * of an IRQ or NMI from the previous vmexit, and 8319 * then we request an immediate exit to inject the 8320 * SMI. 8321 */ 8322 if (vcpu->arch.smi_pending && !is_smm(vcpu)) 8323 if (!kvm_x86_ops.enable_smi_window(vcpu)) 8324 req_immediate_exit = true; 8325 if (vcpu->arch.nmi_pending) 8326 kvm_x86_ops.enable_nmi_window(vcpu); 8327 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 8328 kvm_x86_ops.enable_irq_window(vcpu); 8329 WARN_ON(vcpu->arch.exception.pending); 8330 } 8331 8332 if (kvm_lapic_enabled(vcpu)) { 8333 update_cr8_intercept(vcpu); 8334 kvm_lapic_sync_to_vapic(vcpu); 8335 } 8336 } 8337 8338 r = kvm_mmu_reload(vcpu); 8339 if (unlikely(r)) { 8340 goto cancel_injection; 8341 } 8342 8343 preempt_disable(); 8344 8345 kvm_x86_ops.prepare_guest_switch(vcpu); 8346 8347 /* 8348 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 8349 * IPI are then delayed after guest entry, which ensures that they 8350 * result in virtual interrupt delivery. 8351 */ 8352 local_irq_disable(); 8353 vcpu->mode = IN_GUEST_MODE; 8354 8355 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 8356 8357 /* 8358 * 1) We should set ->mode before checking ->requests. Please see 8359 * the comment in kvm_vcpu_exiting_guest_mode(). 8360 * 8361 * 2) For APICv, we should set ->mode before checking PID.ON. This 8362 * pairs with the memory barrier implicit in pi_test_and_set_on 8363 * (see vmx_deliver_posted_interrupt). 8364 * 8365 * 3) This also orders the write to mode from any reads to the page 8366 * tables done while the VCPU is running. Please see the comment 8367 * in kvm_flush_remote_tlbs. 8368 */ 8369 smp_mb__after_srcu_read_unlock(); 8370 8371 /* 8372 * This handles the case where a posted interrupt was 8373 * notified with kvm_vcpu_kick. 8374 */ 8375 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) 8376 kvm_x86_ops.sync_pir_to_irr(vcpu); 8377 8378 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) 8379 || need_resched() || signal_pending(current)) { 8380 vcpu->mode = OUTSIDE_GUEST_MODE; 8381 smp_wmb(); 8382 local_irq_enable(); 8383 preempt_enable(); 8384 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 8385 r = 1; 8386 goto cancel_injection; 8387 } 8388 8389 if (req_immediate_exit) { 8390 kvm_make_request(KVM_REQ_EVENT, vcpu); 8391 kvm_x86_ops.request_immediate_exit(vcpu); 8392 } 8393 8394 trace_kvm_entry(vcpu->vcpu_id); 8395 guest_enter_irqoff(); 8396 8397 fpregs_assert_state_consistent(); 8398 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 8399 switch_fpu_return(); 8400 8401 if (unlikely(vcpu->arch.switch_db_regs)) { 8402 set_debugreg(0, 7); 8403 set_debugreg(vcpu->arch.eff_db[0], 0); 8404 set_debugreg(vcpu->arch.eff_db[1], 1); 8405 set_debugreg(vcpu->arch.eff_db[2], 2); 8406 set_debugreg(vcpu->arch.eff_db[3], 3); 8407 set_debugreg(vcpu->arch.dr6, 6); 8408 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 8409 } 8410 8411 kvm_x86_ops.run(vcpu); 8412 8413 /* 8414 * Do this here before restoring debug registers on the host. And 8415 * since we do this before handling the vmexit, a DR access vmexit 8416 * can (a) read the correct value of the debug registers, (b) set 8417 * KVM_DEBUGREG_WONT_EXIT again. 8418 */ 8419 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 8420 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 8421 kvm_x86_ops.sync_dirty_debug_regs(vcpu); 8422 kvm_update_dr0123(vcpu); 8423 kvm_update_dr6(vcpu); 8424 kvm_update_dr7(vcpu); 8425 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 8426 } 8427 8428 /* 8429 * If the guest has used debug registers, at least dr7 8430 * will be disabled while returning to the host. 8431 * If we don't have active breakpoints in the host, we don't 8432 * care about the messed up debug address registers. But if 8433 * we have some of them active, restore the old state. 8434 */ 8435 if (hw_breakpoint_active()) 8436 hw_breakpoint_restore(); 8437 8438 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 8439 8440 vcpu->mode = OUTSIDE_GUEST_MODE; 8441 smp_wmb(); 8442 8443 kvm_x86_ops.handle_exit_irqoff(vcpu, &exit_fastpath); 8444 8445 /* 8446 * Consume any pending interrupts, including the possible source of 8447 * VM-Exit on SVM and any ticks that occur between VM-Exit and now. 8448 * An instruction is required after local_irq_enable() to fully unblock 8449 * interrupts on processors that implement an interrupt shadow, the 8450 * stat.exits increment will do nicely. 8451 */ 8452 kvm_before_interrupt(vcpu); 8453 local_irq_enable(); 8454 ++vcpu->stat.exits; 8455 local_irq_disable(); 8456 kvm_after_interrupt(vcpu); 8457 8458 guest_exit_irqoff(); 8459 if (lapic_in_kernel(vcpu)) { 8460 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; 8461 if (delta != S64_MIN) { 8462 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); 8463 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; 8464 } 8465 } 8466 8467 local_irq_enable(); 8468 preempt_enable(); 8469 8470 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 8471 8472 /* 8473 * Profile KVM exit RIPs: 8474 */ 8475 if (unlikely(prof_on == KVM_PROFILING)) { 8476 unsigned long rip = kvm_rip_read(vcpu); 8477 profile_hit(KVM_PROFILING, (void *)rip); 8478 } 8479 8480 if (unlikely(vcpu->arch.tsc_always_catchup)) 8481 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 8482 8483 if (vcpu->arch.apic_attention) 8484 kvm_lapic_sync_from_vapic(vcpu); 8485 8486 r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath); 8487 return r; 8488 8489 cancel_injection: 8490 kvm_x86_ops.cancel_injection(vcpu); 8491 if (unlikely(vcpu->arch.apic_attention)) 8492 kvm_lapic_sync_from_vapic(vcpu); 8493 out: 8494 return r; 8495 } 8496 8497 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 8498 { 8499 if (!kvm_arch_vcpu_runnable(vcpu) && 8500 (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) { 8501 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 8502 kvm_vcpu_block(vcpu); 8503 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 8504 8505 if (kvm_x86_ops.post_block) 8506 kvm_x86_ops.post_block(vcpu); 8507 8508 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 8509 return 1; 8510 } 8511 8512 kvm_apic_accept_events(vcpu); 8513 switch(vcpu->arch.mp_state) { 8514 case KVM_MP_STATE_HALTED: 8515 vcpu->arch.pv.pv_unhalted = false; 8516 vcpu->arch.mp_state = 8517 KVM_MP_STATE_RUNNABLE; 8518 /* fall through */ 8519 case KVM_MP_STATE_RUNNABLE: 8520 vcpu->arch.apf.halted = false; 8521 break; 8522 case KVM_MP_STATE_INIT_RECEIVED: 8523 break; 8524 default: 8525 return -EINTR; 8526 } 8527 return 1; 8528 } 8529 8530 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 8531 { 8532 if (is_guest_mode(vcpu) && kvm_x86_ops.check_nested_events) 8533 kvm_x86_ops.check_nested_events(vcpu); 8534 8535 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 8536 !vcpu->arch.apf.halted); 8537 } 8538 8539 static int vcpu_run(struct kvm_vcpu *vcpu) 8540 { 8541 int r; 8542 struct kvm *kvm = vcpu->kvm; 8543 8544 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 8545 vcpu->arch.l1tf_flush_l1d = true; 8546 8547 for (;;) { 8548 if (kvm_vcpu_running(vcpu)) { 8549 r = vcpu_enter_guest(vcpu); 8550 } else { 8551 r = vcpu_block(kvm, vcpu); 8552 } 8553 8554 if (r <= 0) 8555 break; 8556 8557 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); 8558 if (kvm_cpu_has_pending_timer(vcpu)) 8559 kvm_inject_pending_timer_irqs(vcpu); 8560 8561 if (dm_request_for_irq_injection(vcpu) && 8562 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 8563 r = 0; 8564 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 8565 ++vcpu->stat.request_irq_exits; 8566 break; 8567 } 8568 8569 kvm_check_async_pf_completion(vcpu); 8570 8571 if (signal_pending(current)) { 8572 r = -EINTR; 8573 vcpu->run->exit_reason = KVM_EXIT_INTR; 8574 ++vcpu->stat.signal_exits; 8575 break; 8576 } 8577 if (need_resched()) { 8578 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 8579 cond_resched(); 8580 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 8581 } 8582 } 8583 8584 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 8585 8586 return r; 8587 } 8588 8589 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 8590 { 8591 int r; 8592 8593 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 8594 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 8595 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 8596 return r; 8597 } 8598 8599 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 8600 { 8601 BUG_ON(!vcpu->arch.pio.count); 8602 8603 return complete_emulated_io(vcpu); 8604 } 8605 8606 /* 8607 * Implements the following, as a state machine: 8608 * 8609 * read: 8610 * for each fragment 8611 * for each mmio piece in the fragment 8612 * write gpa, len 8613 * exit 8614 * copy data 8615 * execute insn 8616 * 8617 * write: 8618 * for each fragment 8619 * for each mmio piece in the fragment 8620 * write gpa, len 8621 * copy data 8622 * exit 8623 */ 8624 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 8625 { 8626 struct kvm_run *run = vcpu->run; 8627 struct kvm_mmio_fragment *frag; 8628 unsigned len; 8629 8630 BUG_ON(!vcpu->mmio_needed); 8631 8632 /* Complete previous fragment */ 8633 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 8634 len = min(8u, frag->len); 8635 if (!vcpu->mmio_is_write) 8636 memcpy(frag->data, run->mmio.data, len); 8637 8638 if (frag->len <= 8) { 8639 /* Switch to the next fragment. */ 8640 frag++; 8641 vcpu->mmio_cur_fragment++; 8642 } else { 8643 /* Go forward to the next mmio piece. */ 8644 frag->data += len; 8645 frag->gpa += len; 8646 frag->len -= len; 8647 } 8648 8649 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 8650 vcpu->mmio_needed = 0; 8651 8652 /* FIXME: return into emulator if single-stepping. */ 8653 if (vcpu->mmio_is_write) 8654 return 1; 8655 vcpu->mmio_read_completed = 1; 8656 return complete_emulated_io(vcpu); 8657 } 8658 8659 run->exit_reason = KVM_EXIT_MMIO; 8660 run->mmio.phys_addr = frag->gpa; 8661 if (vcpu->mmio_is_write) 8662 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 8663 run->mmio.len = min(8u, frag->len); 8664 run->mmio.is_write = vcpu->mmio_is_write; 8665 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 8666 return 0; 8667 } 8668 8669 static void kvm_save_current_fpu(struct fpu *fpu) 8670 { 8671 /* 8672 * If the target FPU state is not resident in the CPU registers, just 8673 * memcpy() from current, else save CPU state directly to the target. 8674 */ 8675 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 8676 memcpy(&fpu->state, ¤t->thread.fpu.state, 8677 fpu_kernel_xstate_size); 8678 else 8679 copy_fpregs_to_fpstate(fpu); 8680 } 8681 8682 /* Swap (qemu) user FPU context for the guest FPU context. */ 8683 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 8684 { 8685 fpregs_lock(); 8686 8687 kvm_save_current_fpu(vcpu->arch.user_fpu); 8688 8689 /* PKRU is separately restored in kvm_x86_ops.run. */ 8690 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, 8691 ~XFEATURE_MASK_PKRU); 8692 8693 fpregs_mark_activate(); 8694 fpregs_unlock(); 8695 8696 trace_kvm_fpu(1); 8697 } 8698 8699 /* When vcpu_run ends, restore user space FPU context. */ 8700 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 8701 { 8702 fpregs_lock(); 8703 8704 kvm_save_current_fpu(vcpu->arch.guest_fpu); 8705 8706 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); 8707 8708 fpregs_mark_activate(); 8709 fpregs_unlock(); 8710 8711 ++vcpu->stat.fpu_reload; 8712 trace_kvm_fpu(0); 8713 } 8714 8715 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 8716 { 8717 int r; 8718 8719 vcpu_load(vcpu); 8720 kvm_sigset_activate(vcpu); 8721 kvm_load_guest_fpu(vcpu); 8722 8723 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 8724 if (kvm_run->immediate_exit) { 8725 r = -EINTR; 8726 goto out; 8727 } 8728 kvm_vcpu_block(vcpu); 8729 kvm_apic_accept_events(vcpu); 8730 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 8731 r = -EAGAIN; 8732 if (signal_pending(current)) { 8733 r = -EINTR; 8734 vcpu->run->exit_reason = KVM_EXIT_INTR; 8735 ++vcpu->stat.signal_exits; 8736 } 8737 goto out; 8738 } 8739 8740 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { 8741 r = -EINVAL; 8742 goto out; 8743 } 8744 8745 if (vcpu->run->kvm_dirty_regs) { 8746 r = sync_regs(vcpu); 8747 if (r != 0) 8748 goto out; 8749 } 8750 8751 /* re-sync apic's tpr */ 8752 if (!lapic_in_kernel(vcpu)) { 8753 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 8754 r = -EINVAL; 8755 goto out; 8756 } 8757 } 8758 8759 if (unlikely(vcpu->arch.complete_userspace_io)) { 8760 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 8761 vcpu->arch.complete_userspace_io = NULL; 8762 r = cui(vcpu); 8763 if (r <= 0) 8764 goto out; 8765 } else 8766 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 8767 8768 if (kvm_run->immediate_exit) 8769 r = -EINTR; 8770 else 8771 r = vcpu_run(vcpu); 8772 8773 out: 8774 kvm_put_guest_fpu(vcpu); 8775 if (vcpu->run->kvm_valid_regs) 8776 store_regs(vcpu); 8777 post_kvm_run_save(vcpu); 8778 kvm_sigset_deactivate(vcpu); 8779 8780 vcpu_put(vcpu); 8781 return r; 8782 } 8783 8784 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8785 { 8786 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 8787 /* 8788 * We are here if userspace calls get_regs() in the middle of 8789 * instruction emulation. Registers state needs to be copied 8790 * back from emulation context to vcpu. Userspace shouldn't do 8791 * that usually, but some bad designed PV devices (vmware 8792 * backdoor interface) need this to work 8793 */ 8794 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); 8795 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 8796 } 8797 regs->rax = kvm_rax_read(vcpu); 8798 regs->rbx = kvm_rbx_read(vcpu); 8799 regs->rcx = kvm_rcx_read(vcpu); 8800 regs->rdx = kvm_rdx_read(vcpu); 8801 regs->rsi = kvm_rsi_read(vcpu); 8802 regs->rdi = kvm_rdi_read(vcpu); 8803 regs->rsp = kvm_rsp_read(vcpu); 8804 regs->rbp = kvm_rbp_read(vcpu); 8805 #ifdef CONFIG_X86_64 8806 regs->r8 = kvm_r8_read(vcpu); 8807 regs->r9 = kvm_r9_read(vcpu); 8808 regs->r10 = kvm_r10_read(vcpu); 8809 regs->r11 = kvm_r11_read(vcpu); 8810 regs->r12 = kvm_r12_read(vcpu); 8811 regs->r13 = kvm_r13_read(vcpu); 8812 regs->r14 = kvm_r14_read(vcpu); 8813 regs->r15 = kvm_r15_read(vcpu); 8814 #endif 8815 8816 regs->rip = kvm_rip_read(vcpu); 8817 regs->rflags = kvm_get_rflags(vcpu); 8818 } 8819 8820 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8821 { 8822 vcpu_load(vcpu); 8823 __get_regs(vcpu, regs); 8824 vcpu_put(vcpu); 8825 return 0; 8826 } 8827 8828 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8829 { 8830 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 8831 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 8832 8833 kvm_rax_write(vcpu, regs->rax); 8834 kvm_rbx_write(vcpu, regs->rbx); 8835 kvm_rcx_write(vcpu, regs->rcx); 8836 kvm_rdx_write(vcpu, regs->rdx); 8837 kvm_rsi_write(vcpu, regs->rsi); 8838 kvm_rdi_write(vcpu, regs->rdi); 8839 kvm_rsp_write(vcpu, regs->rsp); 8840 kvm_rbp_write(vcpu, regs->rbp); 8841 #ifdef CONFIG_X86_64 8842 kvm_r8_write(vcpu, regs->r8); 8843 kvm_r9_write(vcpu, regs->r9); 8844 kvm_r10_write(vcpu, regs->r10); 8845 kvm_r11_write(vcpu, regs->r11); 8846 kvm_r12_write(vcpu, regs->r12); 8847 kvm_r13_write(vcpu, regs->r13); 8848 kvm_r14_write(vcpu, regs->r14); 8849 kvm_r15_write(vcpu, regs->r15); 8850 #endif 8851 8852 kvm_rip_write(vcpu, regs->rip); 8853 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 8854 8855 vcpu->arch.exception.pending = false; 8856 8857 kvm_make_request(KVM_REQ_EVENT, vcpu); 8858 } 8859 8860 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8861 { 8862 vcpu_load(vcpu); 8863 __set_regs(vcpu, regs); 8864 vcpu_put(vcpu); 8865 return 0; 8866 } 8867 8868 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 8869 { 8870 struct kvm_segment cs; 8871 8872 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 8873 *db = cs.db; 8874 *l = cs.l; 8875 } 8876 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 8877 8878 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 8879 { 8880 struct desc_ptr dt; 8881 8882 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 8883 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 8884 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 8885 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 8886 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 8887 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 8888 8889 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 8890 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 8891 8892 kvm_x86_ops.get_idt(vcpu, &dt); 8893 sregs->idt.limit = dt.size; 8894 sregs->idt.base = dt.address; 8895 kvm_x86_ops.get_gdt(vcpu, &dt); 8896 sregs->gdt.limit = dt.size; 8897 sregs->gdt.base = dt.address; 8898 8899 sregs->cr0 = kvm_read_cr0(vcpu); 8900 sregs->cr2 = vcpu->arch.cr2; 8901 sregs->cr3 = kvm_read_cr3(vcpu); 8902 sregs->cr4 = kvm_read_cr4(vcpu); 8903 sregs->cr8 = kvm_get_cr8(vcpu); 8904 sregs->efer = vcpu->arch.efer; 8905 sregs->apic_base = kvm_get_apic_base(vcpu); 8906 8907 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); 8908 8909 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 8910 set_bit(vcpu->arch.interrupt.nr, 8911 (unsigned long *)sregs->interrupt_bitmap); 8912 } 8913 8914 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 8915 struct kvm_sregs *sregs) 8916 { 8917 vcpu_load(vcpu); 8918 __get_sregs(vcpu, sregs); 8919 vcpu_put(vcpu); 8920 return 0; 8921 } 8922 8923 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 8924 struct kvm_mp_state *mp_state) 8925 { 8926 vcpu_load(vcpu); 8927 if (kvm_mpx_supported()) 8928 kvm_load_guest_fpu(vcpu); 8929 8930 kvm_apic_accept_events(vcpu); 8931 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 8932 vcpu->arch.pv.pv_unhalted) 8933 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 8934 else 8935 mp_state->mp_state = vcpu->arch.mp_state; 8936 8937 if (kvm_mpx_supported()) 8938 kvm_put_guest_fpu(vcpu); 8939 vcpu_put(vcpu); 8940 return 0; 8941 } 8942 8943 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 8944 struct kvm_mp_state *mp_state) 8945 { 8946 int ret = -EINVAL; 8947 8948 vcpu_load(vcpu); 8949 8950 if (!lapic_in_kernel(vcpu) && 8951 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 8952 goto out; 8953 8954 /* 8955 * KVM_MP_STATE_INIT_RECEIVED means the processor is in 8956 * INIT state; latched init should be reported using 8957 * KVM_SET_VCPU_EVENTS, so reject it here. 8958 */ 8959 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && 8960 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 8961 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 8962 goto out; 8963 8964 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 8965 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 8966 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 8967 } else 8968 vcpu->arch.mp_state = mp_state->mp_state; 8969 kvm_make_request(KVM_REQ_EVENT, vcpu); 8970 8971 ret = 0; 8972 out: 8973 vcpu_put(vcpu); 8974 return ret; 8975 } 8976 8977 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 8978 int reason, bool has_error_code, u32 error_code) 8979 { 8980 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8981 int ret; 8982 8983 init_emulate_ctxt(vcpu); 8984 8985 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 8986 has_error_code, error_code); 8987 if (ret) { 8988 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 8989 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 8990 vcpu->run->internal.ndata = 0; 8991 return 0; 8992 } 8993 8994 kvm_rip_write(vcpu, ctxt->eip); 8995 kvm_set_rflags(vcpu, ctxt->eflags); 8996 return 1; 8997 } 8998 EXPORT_SYMBOL_GPL(kvm_task_switch); 8999 9000 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 9001 { 9002 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 9003 /* 9004 * When EFER.LME and CR0.PG are set, the processor is in 9005 * 64-bit mode (though maybe in a 32-bit code segment). 9006 * CR4.PAE and EFER.LMA must be set. 9007 */ 9008 if (!(sregs->cr4 & X86_CR4_PAE) 9009 || !(sregs->efer & EFER_LMA)) 9010 return -EINVAL; 9011 } else { 9012 /* 9013 * Not in 64-bit mode: EFER.LMA is clear and the code 9014 * segment cannot be 64-bit. 9015 */ 9016 if (sregs->efer & EFER_LMA || sregs->cs.l) 9017 return -EINVAL; 9018 } 9019 9020 return kvm_valid_cr4(vcpu, sregs->cr4); 9021 } 9022 9023 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 9024 { 9025 struct msr_data apic_base_msr; 9026 int mmu_reset_needed = 0; 9027 int cpuid_update_needed = 0; 9028 int pending_vec, max_bits, idx; 9029 struct desc_ptr dt; 9030 int ret = -EINVAL; 9031 9032 if (kvm_valid_sregs(vcpu, sregs)) 9033 goto out; 9034 9035 apic_base_msr.data = sregs->apic_base; 9036 apic_base_msr.host_initiated = true; 9037 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 9038 goto out; 9039 9040 dt.size = sregs->idt.limit; 9041 dt.address = sregs->idt.base; 9042 kvm_x86_ops.set_idt(vcpu, &dt); 9043 dt.size = sregs->gdt.limit; 9044 dt.address = sregs->gdt.base; 9045 kvm_x86_ops.set_gdt(vcpu, &dt); 9046 9047 vcpu->arch.cr2 = sregs->cr2; 9048 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 9049 vcpu->arch.cr3 = sregs->cr3; 9050 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 9051 9052 kvm_set_cr8(vcpu, sregs->cr8); 9053 9054 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 9055 kvm_x86_ops.set_efer(vcpu, sregs->efer); 9056 9057 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 9058 kvm_x86_ops.set_cr0(vcpu, sregs->cr0); 9059 vcpu->arch.cr0 = sregs->cr0; 9060 9061 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 9062 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) & 9063 (X86_CR4_OSXSAVE | X86_CR4_PKE)); 9064 kvm_x86_ops.set_cr4(vcpu, sregs->cr4); 9065 if (cpuid_update_needed) 9066 kvm_update_cpuid(vcpu); 9067 9068 idx = srcu_read_lock(&vcpu->kvm->srcu); 9069 if (is_pae_paging(vcpu)) { 9070 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 9071 mmu_reset_needed = 1; 9072 } 9073 srcu_read_unlock(&vcpu->kvm->srcu, idx); 9074 9075 if (mmu_reset_needed) 9076 kvm_mmu_reset_context(vcpu); 9077 9078 max_bits = KVM_NR_INTERRUPTS; 9079 pending_vec = find_first_bit( 9080 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 9081 if (pending_vec < max_bits) { 9082 kvm_queue_interrupt(vcpu, pending_vec, false); 9083 pr_debug("Set back pending irq %d\n", pending_vec); 9084 } 9085 9086 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 9087 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 9088 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 9089 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 9090 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 9091 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 9092 9093 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 9094 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 9095 9096 update_cr8_intercept(vcpu); 9097 9098 /* Older userspace won't unhalt the vcpu on reset. */ 9099 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 9100 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 9101 !is_protmode(vcpu)) 9102 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 9103 9104 kvm_make_request(KVM_REQ_EVENT, vcpu); 9105 9106 ret = 0; 9107 out: 9108 return ret; 9109 } 9110 9111 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 9112 struct kvm_sregs *sregs) 9113 { 9114 int ret; 9115 9116 vcpu_load(vcpu); 9117 ret = __set_sregs(vcpu, sregs); 9118 vcpu_put(vcpu); 9119 return ret; 9120 } 9121 9122 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 9123 struct kvm_guest_debug *dbg) 9124 { 9125 unsigned long rflags; 9126 int i, r; 9127 9128 vcpu_load(vcpu); 9129 9130 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 9131 r = -EBUSY; 9132 if (vcpu->arch.exception.pending) 9133 goto out; 9134 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 9135 kvm_queue_exception(vcpu, DB_VECTOR); 9136 else 9137 kvm_queue_exception(vcpu, BP_VECTOR); 9138 } 9139 9140 /* 9141 * Read rflags as long as potentially injected trace flags are still 9142 * filtered out. 9143 */ 9144 rflags = kvm_get_rflags(vcpu); 9145 9146 vcpu->guest_debug = dbg->control; 9147 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 9148 vcpu->guest_debug = 0; 9149 9150 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 9151 for (i = 0; i < KVM_NR_DB_REGS; ++i) 9152 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 9153 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 9154 } else { 9155 for (i = 0; i < KVM_NR_DB_REGS; i++) 9156 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 9157 } 9158 kvm_update_dr7(vcpu); 9159 9160 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 9161 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 9162 get_segment_base(vcpu, VCPU_SREG_CS); 9163 9164 /* 9165 * Trigger an rflags update that will inject or remove the trace 9166 * flags. 9167 */ 9168 kvm_set_rflags(vcpu, rflags); 9169 9170 kvm_x86_ops.update_bp_intercept(vcpu); 9171 9172 r = 0; 9173 9174 out: 9175 vcpu_put(vcpu); 9176 return r; 9177 } 9178 9179 /* 9180 * Translate a guest virtual address to a guest physical address. 9181 */ 9182 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 9183 struct kvm_translation *tr) 9184 { 9185 unsigned long vaddr = tr->linear_address; 9186 gpa_t gpa; 9187 int idx; 9188 9189 vcpu_load(vcpu); 9190 9191 idx = srcu_read_lock(&vcpu->kvm->srcu); 9192 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 9193 srcu_read_unlock(&vcpu->kvm->srcu, idx); 9194 tr->physical_address = gpa; 9195 tr->valid = gpa != UNMAPPED_GVA; 9196 tr->writeable = 1; 9197 tr->usermode = 0; 9198 9199 vcpu_put(vcpu); 9200 return 0; 9201 } 9202 9203 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 9204 { 9205 struct fxregs_state *fxsave; 9206 9207 vcpu_load(vcpu); 9208 9209 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 9210 memcpy(fpu->fpr, fxsave->st_space, 128); 9211 fpu->fcw = fxsave->cwd; 9212 fpu->fsw = fxsave->swd; 9213 fpu->ftwx = fxsave->twd; 9214 fpu->last_opcode = fxsave->fop; 9215 fpu->last_ip = fxsave->rip; 9216 fpu->last_dp = fxsave->rdp; 9217 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 9218 9219 vcpu_put(vcpu); 9220 return 0; 9221 } 9222 9223 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 9224 { 9225 struct fxregs_state *fxsave; 9226 9227 vcpu_load(vcpu); 9228 9229 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 9230 9231 memcpy(fxsave->st_space, fpu->fpr, 128); 9232 fxsave->cwd = fpu->fcw; 9233 fxsave->swd = fpu->fsw; 9234 fxsave->twd = fpu->ftwx; 9235 fxsave->fop = fpu->last_opcode; 9236 fxsave->rip = fpu->last_ip; 9237 fxsave->rdp = fpu->last_dp; 9238 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 9239 9240 vcpu_put(vcpu); 9241 return 0; 9242 } 9243 9244 static void store_regs(struct kvm_vcpu *vcpu) 9245 { 9246 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 9247 9248 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 9249 __get_regs(vcpu, &vcpu->run->s.regs.regs); 9250 9251 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 9252 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 9253 9254 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 9255 kvm_vcpu_ioctl_x86_get_vcpu_events( 9256 vcpu, &vcpu->run->s.regs.events); 9257 } 9258 9259 static int sync_regs(struct kvm_vcpu *vcpu) 9260 { 9261 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) 9262 return -EINVAL; 9263 9264 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 9265 __set_regs(vcpu, &vcpu->run->s.regs.regs); 9266 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 9267 } 9268 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 9269 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 9270 return -EINVAL; 9271 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 9272 } 9273 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 9274 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 9275 vcpu, &vcpu->run->s.regs.events)) 9276 return -EINVAL; 9277 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 9278 } 9279 9280 return 0; 9281 } 9282 9283 static void fx_init(struct kvm_vcpu *vcpu) 9284 { 9285 fpstate_init(&vcpu->arch.guest_fpu->state); 9286 if (boot_cpu_has(X86_FEATURE_XSAVES)) 9287 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = 9288 host_xcr0 | XSTATE_COMPACTION_ENABLED; 9289 9290 /* 9291 * Ensure guest xcr0 is valid for loading 9292 */ 9293 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 9294 9295 vcpu->arch.cr0 |= X86_CR0_ET; 9296 } 9297 9298 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 9299 { 9300 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 9301 pr_warn_once("kvm: SMP vm created on host with unstable TSC; " 9302 "guest TSC will not be reliable\n"); 9303 9304 return 0; 9305 } 9306 9307 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 9308 { 9309 struct page *page; 9310 int r; 9311 9312 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 9313 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 9314 else 9315 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 9316 9317 kvm_set_tsc_khz(vcpu, max_tsc_khz); 9318 9319 r = kvm_mmu_create(vcpu); 9320 if (r < 0) 9321 return r; 9322 9323 if (irqchip_in_kernel(vcpu->kvm)) { 9324 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 9325 if (r < 0) 9326 goto fail_mmu_destroy; 9327 if (kvm_apicv_activated(vcpu->kvm)) 9328 vcpu->arch.apicv_active = true; 9329 } else 9330 static_key_slow_inc(&kvm_no_apic_vcpu); 9331 9332 r = -ENOMEM; 9333 9334 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 9335 if (!page) 9336 goto fail_free_lapic; 9337 vcpu->arch.pio_data = page_address(page); 9338 9339 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 9340 GFP_KERNEL_ACCOUNT); 9341 if (!vcpu->arch.mce_banks) 9342 goto fail_free_pio_data; 9343 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 9344 9345 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 9346 GFP_KERNEL_ACCOUNT)) 9347 goto fail_free_mce_banks; 9348 9349 if (!alloc_emulate_ctxt(vcpu)) 9350 goto free_wbinvd_dirty_mask; 9351 9352 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, 9353 GFP_KERNEL_ACCOUNT); 9354 if (!vcpu->arch.user_fpu) { 9355 pr_err("kvm: failed to allocate userspace's fpu\n"); 9356 goto free_emulate_ctxt; 9357 } 9358 9359 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, 9360 GFP_KERNEL_ACCOUNT); 9361 if (!vcpu->arch.guest_fpu) { 9362 pr_err("kvm: failed to allocate vcpu's fpu\n"); 9363 goto free_user_fpu; 9364 } 9365 fx_init(vcpu); 9366 9367 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 9368 9369 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 9370 9371 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 9372 9373 kvm_async_pf_hash_reset(vcpu); 9374 kvm_pmu_init(vcpu); 9375 9376 vcpu->arch.pending_external_vector = -1; 9377 vcpu->arch.preempted_in_kernel = false; 9378 9379 kvm_hv_vcpu_init(vcpu); 9380 9381 r = kvm_x86_ops.vcpu_create(vcpu); 9382 if (r) 9383 goto free_guest_fpu; 9384 9385 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 9386 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 9387 kvm_vcpu_mtrr_init(vcpu); 9388 vcpu_load(vcpu); 9389 kvm_vcpu_reset(vcpu, false); 9390 kvm_init_mmu(vcpu, false); 9391 vcpu_put(vcpu); 9392 return 0; 9393 9394 free_guest_fpu: 9395 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); 9396 free_user_fpu: 9397 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); 9398 free_emulate_ctxt: 9399 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 9400 free_wbinvd_dirty_mask: 9401 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 9402 fail_free_mce_banks: 9403 kfree(vcpu->arch.mce_banks); 9404 fail_free_pio_data: 9405 free_page((unsigned long)vcpu->arch.pio_data); 9406 fail_free_lapic: 9407 kvm_free_lapic(vcpu); 9408 fail_mmu_destroy: 9409 kvm_mmu_destroy(vcpu); 9410 return r; 9411 } 9412 9413 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 9414 { 9415 struct msr_data msr; 9416 struct kvm *kvm = vcpu->kvm; 9417 9418 kvm_hv_vcpu_postcreate(vcpu); 9419 9420 if (mutex_lock_killable(&vcpu->mutex)) 9421 return; 9422 vcpu_load(vcpu); 9423 msr.data = 0x0; 9424 msr.index = MSR_IA32_TSC; 9425 msr.host_initiated = true; 9426 kvm_write_tsc(vcpu, &msr); 9427 vcpu_put(vcpu); 9428 9429 /* poll control enabled by default */ 9430 vcpu->arch.msr_kvm_poll_control = 1; 9431 9432 mutex_unlock(&vcpu->mutex); 9433 9434 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) 9435 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 9436 KVMCLOCK_SYNC_PERIOD); 9437 } 9438 9439 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 9440 { 9441 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; 9442 int idx; 9443 9444 kvm_release_pfn(cache->pfn, cache->dirty, cache); 9445 9446 kvmclock_reset(vcpu); 9447 9448 kvm_x86_ops.vcpu_free(vcpu); 9449 9450 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 9451 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 9452 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); 9453 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); 9454 9455 kvm_hv_vcpu_uninit(vcpu); 9456 kvm_pmu_destroy(vcpu); 9457 kfree(vcpu->arch.mce_banks); 9458 kvm_free_lapic(vcpu); 9459 idx = srcu_read_lock(&vcpu->kvm->srcu); 9460 kvm_mmu_destroy(vcpu); 9461 srcu_read_unlock(&vcpu->kvm->srcu, idx); 9462 free_page((unsigned long)vcpu->arch.pio_data); 9463 if (!lapic_in_kernel(vcpu)) 9464 static_key_slow_dec(&kvm_no_apic_vcpu); 9465 } 9466 9467 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 9468 { 9469 kvm_lapic_reset(vcpu, init_event); 9470 9471 vcpu->arch.hflags = 0; 9472 9473 vcpu->arch.smi_pending = 0; 9474 vcpu->arch.smi_count = 0; 9475 atomic_set(&vcpu->arch.nmi_queued, 0); 9476 vcpu->arch.nmi_pending = 0; 9477 vcpu->arch.nmi_injected = false; 9478 kvm_clear_interrupt_queue(vcpu); 9479 kvm_clear_exception_queue(vcpu); 9480 9481 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 9482 kvm_update_dr0123(vcpu); 9483 vcpu->arch.dr6 = DR6_INIT; 9484 kvm_update_dr6(vcpu); 9485 vcpu->arch.dr7 = DR7_FIXED_1; 9486 kvm_update_dr7(vcpu); 9487 9488 vcpu->arch.cr2 = 0; 9489 9490 kvm_make_request(KVM_REQ_EVENT, vcpu); 9491 vcpu->arch.apf.msr_val = 0; 9492 vcpu->arch.st.msr_val = 0; 9493 9494 kvmclock_reset(vcpu); 9495 9496 kvm_clear_async_pf_completion_queue(vcpu); 9497 kvm_async_pf_hash_reset(vcpu); 9498 vcpu->arch.apf.halted = false; 9499 9500 if (kvm_mpx_supported()) { 9501 void *mpx_state_buffer; 9502 9503 /* 9504 * To avoid have the INIT path from kvm_apic_has_events() that be 9505 * called with loaded FPU and does not let userspace fix the state. 9506 */ 9507 if (init_event) 9508 kvm_put_guest_fpu(vcpu); 9509 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 9510 XFEATURE_BNDREGS); 9511 if (mpx_state_buffer) 9512 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); 9513 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 9514 XFEATURE_BNDCSR); 9515 if (mpx_state_buffer) 9516 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); 9517 if (init_event) 9518 kvm_load_guest_fpu(vcpu); 9519 } 9520 9521 if (!init_event) { 9522 kvm_pmu_reset(vcpu); 9523 vcpu->arch.smbase = 0x30000; 9524 9525 vcpu->arch.msr_misc_features_enables = 0; 9526 9527 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 9528 } 9529 9530 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 9531 vcpu->arch.regs_avail = ~0; 9532 vcpu->arch.regs_dirty = ~0; 9533 9534 vcpu->arch.ia32_xss = 0; 9535 9536 kvm_x86_ops.vcpu_reset(vcpu, init_event); 9537 } 9538 9539 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 9540 { 9541 struct kvm_segment cs; 9542 9543 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 9544 cs.selector = vector << 8; 9545 cs.base = vector << 12; 9546 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 9547 kvm_rip_write(vcpu, 0); 9548 } 9549 9550 int kvm_arch_hardware_enable(void) 9551 { 9552 struct kvm *kvm; 9553 struct kvm_vcpu *vcpu; 9554 int i; 9555 int ret; 9556 u64 local_tsc; 9557 u64 max_tsc = 0; 9558 bool stable, backwards_tsc = false; 9559 9560 kvm_shared_msr_cpu_online(); 9561 ret = kvm_x86_ops.hardware_enable(); 9562 if (ret != 0) 9563 return ret; 9564 9565 local_tsc = rdtsc(); 9566 stable = !kvm_check_tsc_unstable(); 9567 list_for_each_entry(kvm, &vm_list, vm_list) { 9568 kvm_for_each_vcpu(i, vcpu, kvm) { 9569 if (!stable && vcpu->cpu == smp_processor_id()) 9570 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 9571 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 9572 backwards_tsc = true; 9573 if (vcpu->arch.last_host_tsc > max_tsc) 9574 max_tsc = vcpu->arch.last_host_tsc; 9575 } 9576 } 9577 } 9578 9579 /* 9580 * Sometimes, even reliable TSCs go backwards. This happens on 9581 * platforms that reset TSC during suspend or hibernate actions, but 9582 * maintain synchronization. We must compensate. Fortunately, we can 9583 * detect that condition here, which happens early in CPU bringup, 9584 * before any KVM threads can be running. Unfortunately, we can't 9585 * bring the TSCs fully up to date with real time, as we aren't yet far 9586 * enough into CPU bringup that we know how much real time has actually 9587 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot 9588 * variables that haven't been updated yet. 9589 * 9590 * So we simply find the maximum observed TSC above, then record the 9591 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 9592 * the adjustment will be applied. Note that we accumulate 9593 * adjustments, in case multiple suspend cycles happen before some VCPU 9594 * gets a chance to run again. In the event that no KVM threads get a 9595 * chance to run, we will miss the entire elapsed period, as we'll have 9596 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 9597 * loose cycle time. This isn't too big a deal, since the loss will be 9598 * uniform across all VCPUs (not to mention the scenario is extremely 9599 * unlikely). It is possible that a second hibernate recovery happens 9600 * much faster than a first, causing the observed TSC here to be 9601 * smaller; this would require additional padding adjustment, which is 9602 * why we set last_host_tsc to the local tsc observed here. 9603 * 9604 * N.B. - this code below runs only on platforms with reliable TSC, 9605 * as that is the only way backwards_tsc is set above. Also note 9606 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 9607 * have the same delta_cyc adjustment applied if backwards_tsc 9608 * is detected. Note further, this adjustment is only done once, 9609 * as we reset last_host_tsc on all VCPUs to stop this from being 9610 * called multiple times (one for each physical CPU bringup). 9611 * 9612 * Platforms with unreliable TSCs don't have to deal with this, they 9613 * will be compensated by the logic in vcpu_load, which sets the TSC to 9614 * catchup mode. This will catchup all VCPUs to real time, but cannot 9615 * guarantee that they stay in perfect synchronization. 9616 */ 9617 if (backwards_tsc) { 9618 u64 delta_cyc = max_tsc - local_tsc; 9619 list_for_each_entry(kvm, &vm_list, vm_list) { 9620 kvm->arch.backwards_tsc_observed = true; 9621 kvm_for_each_vcpu(i, vcpu, kvm) { 9622 vcpu->arch.tsc_offset_adjustment += delta_cyc; 9623 vcpu->arch.last_host_tsc = local_tsc; 9624 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 9625 } 9626 9627 /* 9628 * We have to disable TSC offset matching.. if you were 9629 * booting a VM while issuing an S4 host suspend.... 9630 * you may have some problem. Solving this issue is 9631 * left as an exercise to the reader. 9632 */ 9633 kvm->arch.last_tsc_nsec = 0; 9634 kvm->arch.last_tsc_write = 0; 9635 } 9636 9637 } 9638 return 0; 9639 } 9640 9641 void kvm_arch_hardware_disable(void) 9642 { 9643 kvm_x86_ops.hardware_disable(); 9644 drop_user_return_notifiers(); 9645 } 9646 9647 int kvm_arch_hardware_setup(void *opaque) 9648 { 9649 struct kvm_x86_init_ops *ops = opaque; 9650 int r; 9651 9652 rdmsrl_safe(MSR_EFER, &host_efer); 9653 9654 if (boot_cpu_has(X86_FEATURE_XSAVES)) 9655 rdmsrl(MSR_IA32_XSS, host_xss); 9656 9657 r = ops->hardware_setup(); 9658 if (r != 0) 9659 return r; 9660 9661 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); 9662 9663 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) 9664 supported_xss = 0; 9665 9666 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) 9667 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); 9668 #undef __kvm_cpu_cap_has 9669 9670 if (kvm_has_tsc_control) { 9671 /* 9672 * Make sure the user can only configure tsc_khz values that 9673 * fit into a signed integer. 9674 * A min value is not calculated because it will always 9675 * be 1 on all machines. 9676 */ 9677 u64 max = min(0x7fffffffULL, 9678 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 9679 kvm_max_guest_tsc_khz = max; 9680 9681 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 9682 } 9683 9684 kvm_init_msr_list(); 9685 return 0; 9686 } 9687 9688 void kvm_arch_hardware_unsetup(void) 9689 { 9690 kvm_x86_ops.hardware_unsetup(); 9691 } 9692 9693 int kvm_arch_check_processor_compat(void *opaque) 9694 { 9695 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 9696 struct kvm_x86_init_ops *ops = opaque; 9697 9698 WARN_ON(!irqs_disabled()); 9699 9700 if (__cr4_reserved_bits(cpu_has, c) != 9701 __cr4_reserved_bits(cpu_has, &boot_cpu_data)) 9702 return -EIO; 9703 9704 return ops->check_processor_compatibility(); 9705 } 9706 9707 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 9708 { 9709 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 9710 } 9711 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 9712 9713 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 9714 { 9715 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 9716 } 9717 9718 struct static_key kvm_no_apic_vcpu __read_mostly; 9719 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); 9720 9721 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 9722 { 9723 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 9724 9725 vcpu->arch.l1tf_flush_l1d = true; 9726 if (pmu->version && unlikely(pmu->event_count)) { 9727 pmu->need_cleanup = true; 9728 kvm_make_request(KVM_REQ_PMU, vcpu); 9729 } 9730 kvm_x86_ops.sched_in(vcpu, cpu); 9731 } 9732 9733 void kvm_arch_free_vm(struct kvm *kvm) 9734 { 9735 kfree(kvm->arch.hyperv.hv_pa_pg); 9736 vfree(kvm); 9737 } 9738 9739 9740 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 9741 { 9742 if (type) 9743 return -EINVAL; 9744 9745 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 9746 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 9747 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 9748 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); 9749 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 9750 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 9751 9752 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 9753 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 9754 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 9755 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 9756 &kvm->arch.irq_sources_bitmap); 9757 9758 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 9759 mutex_init(&kvm->arch.apic_map_lock); 9760 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 9761 9762 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); 9763 pvclock_update_vm_gtod_copy(kvm); 9764 9765 kvm->arch.guest_can_read_msr_platform_info = true; 9766 9767 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 9768 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 9769 9770 kvm_hv_init_vm(kvm); 9771 kvm_page_track_init(kvm); 9772 kvm_mmu_init_vm(kvm); 9773 9774 return kvm_x86_ops.vm_init(kvm); 9775 } 9776 9777 int kvm_arch_post_init_vm(struct kvm *kvm) 9778 { 9779 return kvm_mmu_post_init_vm(kvm); 9780 } 9781 9782 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 9783 { 9784 vcpu_load(vcpu); 9785 kvm_mmu_unload(vcpu); 9786 vcpu_put(vcpu); 9787 } 9788 9789 static void kvm_free_vcpus(struct kvm *kvm) 9790 { 9791 unsigned int i; 9792 struct kvm_vcpu *vcpu; 9793 9794 /* 9795 * Unpin any mmu pages first. 9796 */ 9797 kvm_for_each_vcpu(i, vcpu, kvm) { 9798 kvm_clear_async_pf_completion_queue(vcpu); 9799 kvm_unload_vcpu_mmu(vcpu); 9800 } 9801 kvm_for_each_vcpu(i, vcpu, kvm) 9802 kvm_vcpu_destroy(vcpu); 9803 9804 mutex_lock(&kvm->lock); 9805 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 9806 kvm->vcpus[i] = NULL; 9807 9808 atomic_set(&kvm->online_vcpus, 0); 9809 mutex_unlock(&kvm->lock); 9810 } 9811 9812 void kvm_arch_sync_events(struct kvm *kvm) 9813 { 9814 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 9815 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 9816 kvm_free_pit(kvm); 9817 } 9818 9819 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 9820 { 9821 int i, r; 9822 unsigned long hva, uninitialized_var(old_npages); 9823 struct kvm_memslots *slots = kvm_memslots(kvm); 9824 struct kvm_memory_slot *slot; 9825 9826 /* Called with kvm->slots_lock held. */ 9827 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 9828 return -EINVAL; 9829 9830 slot = id_to_memslot(slots, id); 9831 if (size) { 9832 if (slot && slot->npages) 9833 return -EEXIST; 9834 9835 /* 9836 * MAP_SHARED to prevent internal slot pages from being moved 9837 * by fork()/COW. 9838 */ 9839 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 9840 MAP_SHARED | MAP_ANONYMOUS, 0); 9841 if (IS_ERR((void *)hva)) 9842 return PTR_ERR((void *)hva); 9843 } else { 9844 if (!slot || !slot->npages) 9845 return 0; 9846 9847 /* 9848 * Stuff a non-canonical value to catch use-after-delete. This 9849 * ends up being 0 on 32-bit KVM, but there's no better 9850 * alternative. 9851 */ 9852 hva = (unsigned long)(0xdeadull << 48); 9853 old_npages = slot->npages; 9854 } 9855 9856 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 9857 struct kvm_userspace_memory_region m; 9858 9859 m.slot = id | (i << 16); 9860 m.flags = 0; 9861 m.guest_phys_addr = gpa; 9862 m.userspace_addr = hva; 9863 m.memory_size = size; 9864 r = __kvm_set_memory_region(kvm, &m); 9865 if (r < 0) 9866 return r; 9867 } 9868 9869 if (!size) 9870 vm_munmap(hva, old_npages * PAGE_SIZE); 9871 9872 return 0; 9873 } 9874 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 9875 9876 void kvm_arch_pre_destroy_vm(struct kvm *kvm) 9877 { 9878 kvm_mmu_pre_destroy_vm(kvm); 9879 } 9880 9881 void kvm_arch_destroy_vm(struct kvm *kvm) 9882 { 9883 if (current->mm == kvm->mm) { 9884 /* 9885 * Free memory regions allocated on behalf of userspace, 9886 * unless the the memory map has changed due to process exit 9887 * or fd copying. 9888 */ 9889 mutex_lock(&kvm->slots_lock); 9890 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 9891 0, 0); 9892 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 9893 0, 0); 9894 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 9895 mutex_unlock(&kvm->slots_lock); 9896 } 9897 if (kvm_x86_ops.vm_destroy) 9898 kvm_x86_ops.vm_destroy(kvm); 9899 kvm_pic_destroy(kvm); 9900 kvm_ioapic_destroy(kvm); 9901 kvm_free_vcpus(kvm); 9902 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 9903 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); 9904 kvm_mmu_uninit_vm(kvm); 9905 kvm_page_track_cleanup(kvm); 9906 kvm_hv_destroy_vm(kvm); 9907 } 9908 9909 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) 9910 { 9911 int i; 9912 9913 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 9914 kvfree(slot->arch.rmap[i]); 9915 slot->arch.rmap[i] = NULL; 9916 9917 if (i == 0) 9918 continue; 9919 9920 kvfree(slot->arch.lpage_info[i - 1]); 9921 slot->arch.lpage_info[i - 1] = NULL; 9922 } 9923 9924 kvm_page_track_free_memslot(slot); 9925 } 9926 9927 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot, 9928 unsigned long npages) 9929 { 9930 int i; 9931 9932 /* 9933 * Clear out the previous array pointers for the KVM_MR_MOVE case. The 9934 * old arrays will be freed by __kvm_set_memory_region() if installing 9935 * the new memslot is successful. 9936 */ 9937 memset(&slot->arch, 0, sizeof(slot->arch)); 9938 9939 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 9940 struct kvm_lpage_info *linfo; 9941 unsigned long ugfn; 9942 int lpages; 9943 int level = i + 1; 9944 9945 lpages = gfn_to_index(slot->base_gfn + npages - 1, 9946 slot->base_gfn, level) + 1; 9947 9948 slot->arch.rmap[i] = 9949 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), 9950 GFP_KERNEL_ACCOUNT); 9951 if (!slot->arch.rmap[i]) 9952 goto out_free; 9953 if (i == 0) 9954 continue; 9955 9956 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 9957 if (!linfo) 9958 goto out_free; 9959 9960 slot->arch.lpage_info[i - 1] = linfo; 9961 9962 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 9963 linfo[0].disallow_lpage = 1; 9964 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 9965 linfo[lpages - 1].disallow_lpage = 1; 9966 ugfn = slot->userspace_addr >> PAGE_SHIFT; 9967 /* 9968 * If the gfn and userspace address are not aligned wrt each 9969 * other, disable large page support for this slot. 9970 */ 9971 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { 9972 unsigned long j; 9973 9974 for (j = 0; j < lpages; ++j) 9975 linfo[j].disallow_lpage = 1; 9976 } 9977 } 9978 9979 if (kvm_page_track_create_memslot(slot, npages)) 9980 goto out_free; 9981 9982 return 0; 9983 9984 out_free: 9985 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 9986 kvfree(slot->arch.rmap[i]); 9987 slot->arch.rmap[i] = NULL; 9988 if (i == 0) 9989 continue; 9990 9991 kvfree(slot->arch.lpage_info[i - 1]); 9992 slot->arch.lpage_info[i - 1] = NULL; 9993 } 9994 return -ENOMEM; 9995 } 9996 9997 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 9998 { 9999 struct kvm_vcpu *vcpu; 10000 int i; 10001 10002 /* 10003 * memslots->generation has been incremented. 10004 * mmio generation may have reached its maximum value. 10005 */ 10006 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 10007 10008 /* Force re-initialization of steal_time cache */ 10009 kvm_for_each_vcpu(i, vcpu, kvm) 10010 kvm_vcpu_kick(vcpu); 10011 } 10012 10013 int kvm_arch_prepare_memory_region(struct kvm *kvm, 10014 struct kvm_memory_slot *memslot, 10015 const struct kvm_userspace_memory_region *mem, 10016 enum kvm_mr_change change) 10017 { 10018 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) 10019 return kvm_alloc_memslot_metadata(memslot, 10020 mem->memory_size >> PAGE_SHIFT); 10021 return 0; 10022 } 10023 10024 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 10025 struct kvm_memory_slot *new) 10026 { 10027 /* Still write protect RO slot */ 10028 if (new->flags & KVM_MEM_READONLY) { 10029 kvm_mmu_slot_remove_write_access(kvm, new, PT_PAGE_TABLE_LEVEL); 10030 return; 10031 } 10032 10033 /* 10034 * Call kvm_x86_ops dirty logging hooks when they are valid. 10035 * 10036 * kvm_x86_ops.slot_disable_log_dirty is called when: 10037 * 10038 * - KVM_MR_CREATE with dirty logging is disabled 10039 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 10040 * 10041 * The reason is, in case of PML, we need to set D-bit for any slots 10042 * with dirty logging disabled in order to eliminate unnecessary GPA 10043 * logging in PML buffer (and potential PML buffer full VMEXIT). This 10044 * guarantees leaving PML enabled during guest's lifetime won't have 10045 * any additional overhead from PML when guest is running with dirty 10046 * logging disabled for memory slots. 10047 * 10048 * kvm_x86_ops.slot_enable_log_dirty is called when switching new slot 10049 * to dirty logging mode. 10050 * 10051 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 10052 * 10053 * In case of write protect: 10054 * 10055 * Write protect all pages for dirty logging. 10056 * 10057 * All the sptes including the large sptes which point to this 10058 * slot are set to readonly. We can not create any new large 10059 * spte on this slot until the end of the logging. 10060 * 10061 * See the comments in fast_page_fault(). 10062 */ 10063 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 10064 if (kvm_x86_ops.slot_enable_log_dirty) { 10065 kvm_x86_ops.slot_enable_log_dirty(kvm, new); 10066 } else { 10067 int level = 10068 kvm_dirty_log_manual_protect_and_init_set(kvm) ? 10069 PT_DIRECTORY_LEVEL : PT_PAGE_TABLE_LEVEL; 10070 10071 /* 10072 * If we're with initial-all-set, we don't need 10073 * to write protect any small page because 10074 * they're reported as dirty already. However 10075 * we still need to write-protect huge pages 10076 * so that the page split can happen lazily on 10077 * the first write to the huge page. 10078 */ 10079 kvm_mmu_slot_remove_write_access(kvm, new, level); 10080 } 10081 } else { 10082 if (kvm_x86_ops.slot_disable_log_dirty) 10083 kvm_x86_ops.slot_disable_log_dirty(kvm, new); 10084 } 10085 } 10086 10087 void kvm_arch_commit_memory_region(struct kvm *kvm, 10088 const struct kvm_userspace_memory_region *mem, 10089 struct kvm_memory_slot *old, 10090 const struct kvm_memory_slot *new, 10091 enum kvm_mr_change change) 10092 { 10093 if (!kvm->arch.n_requested_mmu_pages) 10094 kvm_mmu_change_mmu_pages(kvm, 10095 kvm_mmu_calculate_default_mmu_pages(kvm)); 10096 10097 /* 10098 * Dirty logging tracks sptes in 4k granularity, meaning that large 10099 * sptes have to be split. If live migration is successful, the guest 10100 * in the source machine will be destroyed and large sptes will be 10101 * created in the destination. However, if the guest continues to run 10102 * in the source machine (for example if live migration fails), small 10103 * sptes will remain around and cause bad performance. 10104 * 10105 * Scan sptes if dirty logging has been stopped, dropping those 10106 * which can be collapsed into a single large-page spte. Later 10107 * page faults will create the large-page sptes. 10108 * 10109 * There is no need to do this in any of the following cases: 10110 * CREATE: No dirty mappings will already exist. 10111 * MOVE/DELETE: The old mappings will already have been cleaned up by 10112 * kvm_arch_flush_shadow_memslot() 10113 */ 10114 if (change == KVM_MR_FLAGS_ONLY && 10115 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 10116 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 10117 kvm_mmu_zap_collapsible_sptes(kvm, new); 10118 10119 /* 10120 * Set up write protection and/or dirty logging for the new slot. 10121 * 10122 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 10123 * been zapped so no dirty logging staff is needed for old slot. For 10124 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 10125 * new and it's also covered when dealing with the new slot. 10126 * 10127 * FIXME: const-ify all uses of struct kvm_memory_slot. 10128 */ 10129 if (change != KVM_MR_DELETE) 10130 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 10131 10132 /* Free the arrays associated with the old memslot. */ 10133 if (change == KVM_MR_MOVE) 10134 kvm_arch_free_memslot(kvm, old); 10135 } 10136 10137 void kvm_arch_flush_shadow_all(struct kvm *kvm) 10138 { 10139 kvm_mmu_zap_all(kvm); 10140 } 10141 10142 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 10143 struct kvm_memory_slot *slot) 10144 { 10145 kvm_page_track_flush_slot(kvm, slot); 10146 } 10147 10148 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 10149 { 10150 return (is_guest_mode(vcpu) && 10151 kvm_x86_ops.guest_apic_has_interrupt && 10152 kvm_x86_ops.guest_apic_has_interrupt(vcpu)); 10153 } 10154 10155 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 10156 { 10157 if (!list_empty_careful(&vcpu->async_pf.done)) 10158 return true; 10159 10160 if (kvm_apic_has_events(vcpu)) 10161 return true; 10162 10163 if (vcpu->arch.pv.pv_unhalted) 10164 return true; 10165 10166 if (vcpu->arch.exception.pending) 10167 return true; 10168 10169 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 10170 (vcpu->arch.nmi_pending && 10171 kvm_x86_ops.nmi_allowed(vcpu))) 10172 return true; 10173 10174 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 10175 (vcpu->arch.smi_pending && !is_smm(vcpu))) 10176 return true; 10177 10178 if (kvm_arch_interrupt_allowed(vcpu) && 10179 (kvm_cpu_has_interrupt(vcpu) || 10180 kvm_guest_apic_has_interrupt(vcpu))) 10181 return true; 10182 10183 if (kvm_hv_has_stimer_pending(vcpu)) 10184 return true; 10185 10186 return false; 10187 } 10188 10189 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 10190 { 10191 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 10192 } 10193 10194 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) 10195 { 10196 if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) 10197 return true; 10198 10199 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 10200 kvm_test_request(KVM_REQ_SMI, vcpu) || 10201 kvm_test_request(KVM_REQ_EVENT, vcpu)) 10202 return true; 10203 10204 if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu)) 10205 return true; 10206 10207 return false; 10208 } 10209 10210 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 10211 { 10212 return vcpu->arch.preempted_in_kernel; 10213 } 10214 10215 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 10216 { 10217 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 10218 } 10219 10220 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 10221 { 10222 return kvm_x86_ops.interrupt_allowed(vcpu); 10223 } 10224 10225 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 10226 { 10227 if (is_64_bit_mode(vcpu)) 10228 return kvm_rip_read(vcpu); 10229 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 10230 kvm_rip_read(vcpu)); 10231 } 10232 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 10233 10234 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 10235 { 10236 return kvm_get_linear_rip(vcpu) == linear_rip; 10237 } 10238 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 10239 10240 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 10241 { 10242 unsigned long rflags; 10243 10244 rflags = kvm_x86_ops.get_rflags(vcpu); 10245 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 10246 rflags &= ~X86_EFLAGS_TF; 10247 return rflags; 10248 } 10249 EXPORT_SYMBOL_GPL(kvm_get_rflags); 10250 10251 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 10252 { 10253 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 10254 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 10255 rflags |= X86_EFLAGS_TF; 10256 kvm_x86_ops.set_rflags(vcpu, rflags); 10257 } 10258 10259 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 10260 { 10261 __kvm_set_rflags(vcpu, rflags); 10262 kvm_make_request(KVM_REQ_EVENT, vcpu); 10263 } 10264 EXPORT_SYMBOL_GPL(kvm_set_rflags); 10265 10266 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 10267 { 10268 int r; 10269 10270 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || 10271 work->wakeup_all) 10272 return; 10273 10274 r = kvm_mmu_reload(vcpu); 10275 if (unlikely(r)) 10276 return; 10277 10278 if (!vcpu->arch.mmu->direct_map && 10279 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) 10280 return; 10281 10282 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); 10283 } 10284 10285 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 10286 { 10287 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 10288 } 10289 10290 static inline u32 kvm_async_pf_next_probe(u32 key) 10291 { 10292 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 10293 } 10294 10295 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 10296 { 10297 u32 key = kvm_async_pf_hash_fn(gfn); 10298 10299 while (vcpu->arch.apf.gfns[key] != ~0) 10300 key = kvm_async_pf_next_probe(key); 10301 10302 vcpu->arch.apf.gfns[key] = gfn; 10303 } 10304 10305 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 10306 { 10307 int i; 10308 u32 key = kvm_async_pf_hash_fn(gfn); 10309 10310 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 10311 (vcpu->arch.apf.gfns[key] != gfn && 10312 vcpu->arch.apf.gfns[key] != ~0); i++) 10313 key = kvm_async_pf_next_probe(key); 10314 10315 return key; 10316 } 10317 10318 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 10319 { 10320 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 10321 } 10322 10323 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 10324 { 10325 u32 i, j, k; 10326 10327 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 10328 while (true) { 10329 vcpu->arch.apf.gfns[i] = ~0; 10330 do { 10331 j = kvm_async_pf_next_probe(j); 10332 if (vcpu->arch.apf.gfns[j] == ~0) 10333 return; 10334 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 10335 /* 10336 * k lies cyclically in ]i,j] 10337 * | i.k.j | 10338 * |....j i.k.| or |.k..j i...| 10339 */ 10340 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 10341 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 10342 i = j; 10343 } 10344 } 10345 10346 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 10347 { 10348 10349 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 10350 sizeof(val)); 10351 } 10352 10353 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val) 10354 { 10355 10356 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val, 10357 sizeof(u32)); 10358 } 10359 10360 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) 10361 { 10362 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) 10363 return false; 10364 10365 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 10366 (vcpu->arch.apf.send_user_only && 10367 kvm_x86_ops.get_cpl(vcpu) == 0)) 10368 return false; 10369 10370 return true; 10371 } 10372 10373 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) 10374 { 10375 if (unlikely(!lapic_in_kernel(vcpu) || 10376 kvm_event_needs_reinjection(vcpu) || 10377 vcpu->arch.exception.pending)) 10378 return false; 10379 10380 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) 10381 return false; 10382 10383 /* 10384 * If interrupts are off we cannot even use an artificial 10385 * halt state. 10386 */ 10387 return kvm_x86_ops.interrupt_allowed(vcpu); 10388 } 10389 10390 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 10391 struct kvm_async_pf *work) 10392 { 10393 struct x86_exception fault; 10394 10395 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); 10396 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 10397 10398 if (kvm_can_deliver_async_pf(vcpu) && 10399 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 10400 fault.vector = PF_VECTOR; 10401 fault.error_code_valid = true; 10402 fault.error_code = 0; 10403 fault.nested_page_fault = false; 10404 fault.address = work->arch.token; 10405 fault.async_page_fault = true; 10406 kvm_inject_page_fault(vcpu, &fault); 10407 } else { 10408 /* 10409 * It is not possible to deliver a paravirtualized asynchronous 10410 * page fault, but putting the guest in an artificial halt state 10411 * can be beneficial nevertheless: if an interrupt arrives, we 10412 * can deliver it timely and perhaps the guest will schedule 10413 * another process. When the instruction that triggered a page 10414 * fault is retried, hopefully the page will be ready in the host. 10415 */ 10416 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 10417 } 10418 } 10419 10420 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 10421 struct kvm_async_pf *work) 10422 { 10423 struct x86_exception fault; 10424 u32 val; 10425 10426 if (work->wakeup_all) 10427 work->arch.token = ~0; /* broadcast wakeup */ 10428 else 10429 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 10430 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); 10431 10432 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED && 10433 !apf_get_user(vcpu, &val)) { 10434 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT && 10435 vcpu->arch.exception.pending && 10436 vcpu->arch.exception.nr == PF_VECTOR && 10437 !apf_put_user(vcpu, 0)) { 10438 vcpu->arch.exception.injected = false; 10439 vcpu->arch.exception.pending = false; 10440 vcpu->arch.exception.nr = 0; 10441 vcpu->arch.exception.has_error_code = false; 10442 vcpu->arch.exception.error_code = 0; 10443 vcpu->arch.exception.has_payload = false; 10444 vcpu->arch.exception.payload = 0; 10445 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 10446 fault.vector = PF_VECTOR; 10447 fault.error_code_valid = true; 10448 fault.error_code = 0; 10449 fault.nested_page_fault = false; 10450 fault.address = work->arch.token; 10451 fault.async_page_fault = true; 10452 kvm_inject_page_fault(vcpu, &fault); 10453 } 10454 } 10455 vcpu->arch.apf.halted = false; 10456 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 10457 } 10458 10459 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 10460 { 10461 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 10462 return true; 10463 else 10464 return kvm_can_do_async_pf(vcpu); 10465 } 10466 10467 void kvm_arch_start_assignment(struct kvm *kvm) 10468 { 10469 atomic_inc(&kvm->arch.assigned_device_count); 10470 } 10471 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 10472 10473 void kvm_arch_end_assignment(struct kvm *kvm) 10474 { 10475 atomic_dec(&kvm->arch.assigned_device_count); 10476 } 10477 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 10478 10479 bool kvm_arch_has_assigned_device(struct kvm *kvm) 10480 { 10481 return atomic_read(&kvm->arch.assigned_device_count); 10482 } 10483 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 10484 10485 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 10486 { 10487 atomic_inc(&kvm->arch.noncoherent_dma_count); 10488 } 10489 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 10490 10491 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 10492 { 10493 atomic_dec(&kvm->arch.noncoherent_dma_count); 10494 } 10495 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 10496 10497 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 10498 { 10499 return atomic_read(&kvm->arch.noncoherent_dma_count); 10500 } 10501 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 10502 10503 bool kvm_arch_has_irq_bypass(void) 10504 { 10505 return true; 10506 } 10507 10508 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 10509 struct irq_bypass_producer *prod) 10510 { 10511 struct kvm_kernel_irqfd *irqfd = 10512 container_of(cons, struct kvm_kernel_irqfd, consumer); 10513 10514 irqfd->producer = prod; 10515 10516 return kvm_x86_ops.update_pi_irte(irqfd->kvm, 10517 prod->irq, irqfd->gsi, 1); 10518 } 10519 10520 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 10521 struct irq_bypass_producer *prod) 10522 { 10523 int ret; 10524 struct kvm_kernel_irqfd *irqfd = 10525 container_of(cons, struct kvm_kernel_irqfd, consumer); 10526 10527 WARN_ON(irqfd->producer != prod); 10528 irqfd->producer = NULL; 10529 10530 /* 10531 * When producer of consumer is unregistered, we change back to 10532 * remapped mode, so we can re-use the current implementation 10533 * when the irq is masked/disabled or the consumer side (KVM 10534 * int this case doesn't want to receive the interrupts. 10535 */ 10536 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 10537 if (ret) 10538 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 10539 " fails: %d\n", irqfd->consumer.token, ret); 10540 } 10541 10542 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 10543 uint32_t guest_irq, bool set) 10544 { 10545 return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set); 10546 } 10547 10548 bool kvm_vector_hashing_enabled(void) 10549 { 10550 return vector_hashing; 10551 } 10552 10553 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) 10554 { 10555 return (vcpu->arch.msr_kvm_poll_control & 1) == 0; 10556 } 10557 EXPORT_SYMBOL_GPL(kvm_arch_no_poll); 10558 10559 u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu) 10560 { 10561 uint64_t bits = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD; 10562 10563 /* The STIBP bit doesn't fault even if it's not advertised */ 10564 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) && 10565 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS)) 10566 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP); 10567 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL) && 10568 !boot_cpu_has(X86_FEATURE_AMD_IBRS)) 10569 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP); 10570 10571 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL_SSBD) && 10572 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD)) 10573 bits &= ~SPEC_CTRL_SSBD; 10574 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && 10575 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 10576 bits &= ~SPEC_CTRL_SSBD; 10577 10578 return bits; 10579 } 10580 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits); 10581 10582 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 10583 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 10584 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 10585 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 10586 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 10587 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 10588 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 10589 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 10590 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 10591 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 10592 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); 10593 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 10594 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 10595 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 10596 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 10597 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); 10598 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 10599 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 10600 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 10601 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 10602 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); 10603 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); 10604