1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "pmu.h" 31 #include "hyperv.h" 32 33 #include <linux/clocksource.h> 34 #include <linux/interrupt.h> 35 #include <linux/kvm.h> 36 #include <linux/fs.h> 37 #include <linux/vmalloc.h> 38 #include <linux/export.h> 39 #include <linux/moduleparam.h> 40 #include <linux/mman.h> 41 #include <linux/highmem.h> 42 #include <linux/iommu.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/cpufreq.h> 45 #include <linux/user-return-notifier.h> 46 #include <linux/srcu.h> 47 #include <linux/slab.h> 48 #include <linux/perf_event.h> 49 #include <linux/uaccess.h> 50 #include <linux/hash.h> 51 #include <linux/pci.h> 52 #include <linux/timekeeper_internal.h> 53 #include <linux/pvclock_gtod.h> 54 #include <linux/kvm_irqfd.h> 55 #include <linux/irqbypass.h> 56 #include <linux/sched/stat.h> 57 #include <linux/mem_encrypt.h> 58 59 #include <trace/events/kvm.h> 60 61 #include <asm/debugreg.h> 62 #include <asm/msr.h> 63 #include <asm/desc.h> 64 #include <asm/mce.h> 65 #include <linux/kernel_stat.h> 66 #include <asm/fpu/internal.h> /* Ugh! */ 67 #include <asm/pvclock.h> 68 #include <asm/div64.h> 69 #include <asm/irq_remapping.h> 70 #include <asm/mshyperv.h> 71 #include <asm/hypervisor.h> 72 #include <asm/intel_pt.h> 73 74 #define CREATE_TRACE_POINTS 75 #include "trace.h" 76 77 #define MAX_IO_MSRS 256 78 #define KVM_MAX_MCE_BANKS 32 79 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 80 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 81 82 #define emul_to_vcpu(ctxt) \ 83 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 84 85 /* EFER defaults: 86 * - enable syscall per default because its emulated by KVM 87 * - enable LME and LMA per default on 64 bit KVM 88 */ 89 #ifdef CONFIG_X86_64 90 static 91 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 92 #else 93 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 94 #endif 95 96 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 97 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 98 99 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 100 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 101 102 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 103 static void process_nmi(struct kvm_vcpu *vcpu); 104 static void enter_smm(struct kvm_vcpu *vcpu); 105 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 106 static void store_regs(struct kvm_vcpu *vcpu); 107 static int sync_regs(struct kvm_vcpu *vcpu); 108 109 struct kvm_x86_ops *kvm_x86_ops __read_mostly; 110 EXPORT_SYMBOL_GPL(kvm_x86_ops); 111 112 static bool __read_mostly ignore_msrs = 0; 113 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 114 115 static bool __read_mostly report_ignored_msrs = true; 116 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 117 118 unsigned int min_timer_period_us = 200; 119 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 120 121 static bool __read_mostly kvmclock_periodic_sync = true; 122 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 123 124 bool __read_mostly kvm_has_tsc_control; 125 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 126 u32 __read_mostly kvm_max_guest_tsc_khz; 127 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 128 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 129 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 130 u64 __read_mostly kvm_max_tsc_scaling_ratio; 131 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 132 u64 __read_mostly kvm_default_tsc_scaling_ratio; 133 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 134 135 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 136 static u32 __read_mostly tsc_tolerance_ppm = 250; 137 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 138 139 /* lapic timer advance (tscdeadline mode only) in nanoseconds */ 140 unsigned int __read_mostly lapic_timer_advance_ns = 1000; 141 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 142 EXPORT_SYMBOL_GPL(lapic_timer_advance_ns); 143 144 static bool __read_mostly vector_hashing = true; 145 module_param(vector_hashing, bool, S_IRUGO); 146 147 bool __read_mostly enable_vmware_backdoor = false; 148 module_param(enable_vmware_backdoor, bool, S_IRUGO); 149 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 150 151 static bool __read_mostly force_emulation_prefix = false; 152 module_param(force_emulation_prefix, bool, S_IRUGO); 153 154 #define KVM_NR_SHARED_MSRS 16 155 156 struct kvm_shared_msrs_global { 157 int nr; 158 u32 msrs[KVM_NR_SHARED_MSRS]; 159 }; 160 161 struct kvm_shared_msrs { 162 struct user_return_notifier urn; 163 bool registered; 164 struct kvm_shared_msr_values { 165 u64 host; 166 u64 curr; 167 } values[KVM_NR_SHARED_MSRS]; 168 }; 169 170 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 171 static struct kvm_shared_msrs __percpu *shared_msrs; 172 173 struct kvm_stats_debugfs_item debugfs_entries[] = { 174 { "pf_fixed", VCPU_STAT(pf_fixed) }, 175 { "pf_guest", VCPU_STAT(pf_guest) }, 176 { "tlb_flush", VCPU_STAT(tlb_flush) }, 177 { "invlpg", VCPU_STAT(invlpg) }, 178 { "exits", VCPU_STAT(exits) }, 179 { "io_exits", VCPU_STAT(io_exits) }, 180 { "mmio_exits", VCPU_STAT(mmio_exits) }, 181 { "signal_exits", VCPU_STAT(signal_exits) }, 182 { "irq_window", VCPU_STAT(irq_window_exits) }, 183 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 184 { "halt_exits", VCPU_STAT(halt_exits) }, 185 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 186 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 187 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, 188 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 189 { "hypercalls", VCPU_STAT(hypercalls) }, 190 { "request_irq", VCPU_STAT(request_irq_exits) }, 191 { "irq_exits", VCPU_STAT(irq_exits) }, 192 { "host_state_reload", VCPU_STAT(host_state_reload) }, 193 { "fpu_reload", VCPU_STAT(fpu_reload) }, 194 { "insn_emulation", VCPU_STAT(insn_emulation) }, 195 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 196 { "irq_injections", VCPU_STAT(irq_injections) }, 197 { "nmi_injections", VCPU_STAT(nmi_injections) }, 198 { "req_event", VCPU_STAT(req_event) }, 199 { "l1d_flush", VCPU_STAT(l1d_flush) }, 200 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 201 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 202 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 203 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 204 { "mmu_flooded", VM_STAT(mmu_flooded) }, 205 { "mmu_recycled", VM_STAT(mmu_recycled) }, 206 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 207 { "mmu_unsync", VM_STAT(mmu_unsync) }, 208 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 209 { "largepages", VM_STAT(lpages) }, 210 { "max_mmu_page_hash_collisions", 211 VM_STAT(max_mmu_page_hash_collisions) }, 212 { NULL } 213 }; 214 215 u64 __read_mostly host_xcr0; 216 217 struct kmem_cache *x86_fpu_cache; 218 EXPORT_SYMBOL_GPL(x86_fpu_cache); 219 220 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 221 222 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 223 { 224 int i; 225 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 226 vcpu->arch.apf.gfns[i] = ~0; 227 } 228 229 static void kvm_on_user_return(struct user_return_notifier *urn) 230 { 231 unsigned slot; 232 struct kvm_shared_msrs *locals 233 = container_of(urn, struct kvm_shared_msrs, urn); 234 struct kvm_shared_msr_values *values; 235 unsigned long flags; 236 237 /* 238 * Disabling irqs at this point since the following code could be 239 * interrupted and executed through kvm_arch_hardware_disable() 240 */ 241 local_irq_save(flags); 242 if (locals->registered) { 243 locals->registered = false; 244 user_return_notifier_unregister(urn); 245 } 246 local_irq_restore(flags); 247 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 248 values = &locals->values[slot]; 249 if (values->host != values->curr) { 250 wrmsrl(shared_msrs_global.msrs[slot], values->host); 251 values->curr = values->host; 252 } 253 } 254 } 255 256 static void shared_msr_update(unsigned slot, u32 msr) 257 { 258 u64 value; 259 unsigned int cpu = smp_processor_id(); 260 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 261 262 /* only read, and nobody should modify it at this time, 263 * so don't need lock */ 264 if (slot >= shared_msrs_global.nr) { 265 printk(KERN_ERR "kvm: invalid MSR slot!"); 266 return; 267 } 268 rdmsrl_safe(msr, &value); 269 smsr->values[slot].host = value; 270 smsr->values[slot].curr = value; 271 } 272 273 void kvm_define_shared_msr(unsigned slot, u32 msr) 274 { 275 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 276 shared_msrs_global.msrs[slot] = msr; 277 if (slot >= shared_msrs_global.nr) 278 shared_msrs_global.nr = slot + 1; 279 } 280 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 281 282 static void kvm_shared_msr_cpu_online(void) 283 { 284 unsigned i; 285 286 for (i = 0; i < shared_msrs_global.nr; ++i) 287 shared_msr_update(i, shared_msrs_global.msrs[i]); 288 } 289 290 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 291 { 292 unsigned int cpu = smp_processor_id(); 293 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 294 int err; 295 296 if (((value ^ smsr->values[slot].curr) & mask) == 0) 297 return 0; 298 smsr->values[slot].curr = value; 299 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 300 if (err) 301 return 1; 302 303 if (!smsr->registered) { 304 smsr->urn.on_user_return = kvm_on_user_return; 305 user_return_notifier_register(&smsr->urn); 306 smsr->registered = true; 307 } 308 return 0; 309 } 310 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 311 312 static void drop_user_return_notifiers(void) 313 { 314 unsigned int cpu = smp_processor_id(); 315 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 316 317 if (smsr->registered) 318 kvm_on_user_return(&smsr->urn); 319 } 320 321 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 322 { 323 return vcpu->arch.apic_base; 324 } 325 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 326 327 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 328 { 329 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 330 } 331 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 332 333 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 334 { 335 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 336 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 337 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | 338 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 339 340 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 341 return 1; 342 if (!msr_info->host_initiated) { 343 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 344 return 1; 345 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 346 return 1; 347 } 348 349 kvm_lapic_set_base(vcpu, msr_info->data); 350 return 0; 351 } 352 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 353 354 asmlinkage __visible void kvm_spurious_fault(void) 355 { 356 /* Fault while not rebooting. We want the trace. */ 357 BUG(); 358 } 359 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 360 361 #define EXCPT_BENIGN 0 362 #define EXCPT_CONTRIBUTORY 1 363 #define EXCPT_PF 2 364 365 static int exception_class(int vector) 366 { 367 switch (vector) { 368 case PF_VECTOR: 369 return EXCPT_PF; 370 case DE_VECTOR: 371 case TS_VECTOR: 372 case NP_VECTOR: 373 case SS_VECTOR: 374 case GP_VECTOR: 375 return EXCPT_CONTRIBUTORY; 376 default: 377 break; 378 } 379 return EXCPT_BENIGN; 380 } 381 382 #define EXCPT_FAULT 0 383 #define EXCPT_TRAP 1 384 #define EXCPT_ABORT 2 385 #define EXCPT_INTERRUPT 3 386 387 static int exception_type(int vector) 388 { 389 unsigned int mask; 390 391 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 392 return EXCPT_INTERRUPT; 393 394 mask = 1 << vector; 395 396 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 397 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 398 return EXCPT_TRAP; 399 400 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 401 return EXCPT_ABORT; 402 403 /* Reserved exceptions will result in fault */ 404 return EXCPT_FAULT; 405 } 406 407 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 408 { 409 unsigned nr = vcpu->arch.exception.nr; 410 bool has_payload = vcpu->arch.exception.has_payload; 411 unsigned long payload = vcpu->arch.exception.payload; 412 413 if (!has_payload) 414 return; 415 416 switch (nr) { 417 case DB_VECTOR: 418 /* 419 * "Certain debug exceptions may clear bit 0-3. The 420 * remaining contents of the DR6 register are never 421 * cleared by the processor". 422 */ 423 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 424 /* 425 * DR6.RTM is set by all #DB exceptions that don't clear it. 426 */ 427 vcpu->arch.dr6 |= DR6_RTM; 428 vcpu->arch.dr6 |= payload; 429 /* 430 * Bit 16 should be set in the payload whenever the #DB 431 * exception should clear DR6.RTM. This makes the payload 432 * compatible with the pending debug exceptions under VMX. 433 * Though not currently documented in the SDM, this also 434 * makes the payload compatible with the exit qualification 435 * for #DB exceptions under VMX. 436 */ 437 vcpu->arch.dr6 ^= payload & DR6_RTM; 438 break; 439 case PF_VECTOR: 440 vcpu->arch.cr2 = payload; 441 break; 442 } 443 444 vcpu->arch.exception.has_payload = false; 445 vcpu->arch.exception.payload = 0; 446 } 447 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 448 449 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 450 unsigned nr, bool has_error, u32 error_code, 451 bool has_payload, unsigned long payload, bool reinject) 452 { 453 u32 prev_nr; 454 int class1, class2; 455 456 kvm_make_request(KVM_REQ_EVENT, vcpu); 457 458 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 459 queue: 460 if (has_error && !is_protmode(vcpu)) 461 has_error = false; 462 if (reinject) { 463 /* 464 * On vmentry, vcpu->arch.exception.pending is only 465 * true if an event injection was blocked by 466 * nested_run_pending. In that case, however, 467 * vcpu_enter_guest requests an immediate exit, 468 * and the guest shouldn't proceed far enough to 469 * need reinjection. 470 */ 471 WARN_ON_ONCE(vcpu->arch.exception.pending); 472 vcpu->arch.exception.injected = true; 473 if (WARN_ON_ONCE(has_payload)) { 474 /* 475 * A reinjected event has already 476 * delivered its payload. 477 */ 478 has_payload = false; 479 payload = 0; 480 } 481 } else { 482 vcpu->arch.exception.pending = true; 483 vcpu->arch.exception.injected = false; 484 } 485 vcpu->arch.exception.has_error_code = has_error; 486 vcpu->arch.exception.nr = nr; 487 vcpu->arch.exception.error_code = error_code; 488 vcpu->arch.exception.has_payload = has_payload; 489 vcpu->arch.exception.payload = payload; 490 /* 491 * In guest mode, payload delivery should be deferred, 492 * so that the L1 hypervisor can intercept #PF before 493 * CR2 is modified (or intercept #DB before DR6 is 494 * modified under nVMX). However, for ABI 495 * compatibility with KVM_GET_VCPU_EVENTS and 496 * KVM_SET_VCPU_EVENTS, we can't delay payload 497 * delivery unless userspace has enabled this 498 * functionality via the per-VM capability, 499 * KVM_CAP_EXCEPTION_PAYLOAD. 500 */ 501 if (!vcpu->kvm->arch.exception_payload_enabled || 502 !is_guest_mode(vcpu)) 503 kvm_deliver_exception_payload(vcpu); 504 return; 505 } 506 507 /* to check exception */ 508 prev_nr = vcpu->arch.exception.nr; 509 if (prev_nr == DF_VECTOR) { 510 /* triple fault -> shutdown */ 511 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 512 return; 513 } 514 class1 = exception_class(prev_nr); 515 class2 = exception_class(nr); 516 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 517 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 518 /* 519 * Generate double fault per SDM Table 5-5. Set 520 * exception.pending = true so that the double fault 521 * can trigger a nested vmexit. 522 */ 523 vcpu->arch.exception.pending = true; 524 vcpu->arch.exception.injected = false; 525 vcpu->arch.exception.has_error_code = true; 526 vcpu->arch.exception.nr = DF_VECTOR; 527 vcpu->arch.exception.error_code = 0; 528 vcpu->arch.exception.has_payload = false; 529 vcpu->arch.exception.payload = 0; 530 } else 531 /* replace previous exception with a new one in a hope 532 that instruction re-execution will regenerate lost 533 exception */ 534 goto queue; 535 } 536 537 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 538 { 539 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 540 } 541 EXPORT_SYMBOL_GPL(kvm_queue_exception); 542 543 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 544 { 545 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 546 } 547 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 548 549 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 550 unsigned long payload) 551 { 552 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 553 } 554 555 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 556 u32 error_code, unsigned long payload) 557 { 558 kvm_multiple_exception(vcpu, nr, true, error_code, 559 true, payload, false); 560 } 561 562 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 563 { 564 if (err) 565 kvm_inject_gp(vcpu, 0); 566 else 567 return kvm_skip_emulated_instruction(vcpu); 568 569 return 1; 570 } 571 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 572 573 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 574 { 575 ++vcpu->stat.pf_guest; 576 vcpu->arch.exception.nested_apf = 577 is_guest_mode(vcpu) && fault->async_page_fault; 578 if (vcpu->arch.exception.nested_apf) { 579 vcpu->arch.apf.nested_apf_token = fault->address; 580 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 581 } else { 582 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 583 fault->address); 584 } 585 } 586 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 587 588 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 589 { 590 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 591 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 592 else 593 vcpu->arch.mmu->inject_page_fault(vcpu, fault); 594 595 return fault->nested_page_fault; 596 } 597 598 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 599 { 600 atomic_inc(&vcpu->arch.nmi_queued); 601 kvm_make_request(KVM_REQ_NMI, vcpu); 602 } 603 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 604 605 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 606 { 607 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 608 } 609 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 610 611 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 612 { 613 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 614 } 615 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 616 617 /* 618 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 619 * a #GP and return false. 620 */ 621 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 622 { 623 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 624 return true; 625 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 626 return false; 627 } 628 EXPORT_SYMBOL_GPL(kvm_require_cpl); 629 630 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 631 { 632 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 633 return true; 634 635 kvm_queue_exception(vcpu, UD_VECTOR); 636 return false; 637 } 638 EXPORT_SYMBOL_GPL(kvm_require_dr); 639 640 /* 641 * This function will be used to read from the physical memory of the currently 642 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 643 * can read from guest physical or from the guest's guest physical memory. 644 */ 645 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 646 gfn_t ngfn, void *data, int offset, int len, 647 u32 access) 648 { 649 struct x86_exception exception; 650 gfn_t real_gfn; 651 gpa_t ngpa; 652 653 ngpa = gfn_to_gpa(ngfn); 654 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 655 if (real_gfn == UNMAPPED_GVA) 656 return -EFAULT; 657 658 real_gfn = gpa_to_gfn(real_gfn); 659 660 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 661 } 662 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 663 664 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 665 void *data, int offset, int len, u32 access) 666 { 667 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 668 data, offset, len, access); 669 } 670 671 /* 672 * Load the pae pdptrs. Return true is they are all valid. 673 */ 674 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 675 { 676 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 677 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 678 int i; 679 int ret; 680 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 681 682 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 683 offset * sizeof(u64), sizeof(pdpte), 684 PFERR_USER_MASK|PFERR_WRITE_MASK); 685 if (ret < 0) { 686 ret = 0; 687 goto out; 688 } 689 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 690 if ((pdpte[i] & PT_PRESENT_MASK) && 691 (pdpte[i] & 692 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) { 693 ret = 0; 694 goto out; 695 } 696 } 697 ret = 1; 698 699 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 700 __set_bit(VCPU_EXREG_PDPTR, 701 (unsigned long *)&vcpu->arch.regs_avail); 702 __set_bit(VCPU_EXREG_PDPTR, 703 (unsigned long *)&vcpu->arch.regs_dirty); 704 out: 705 706 return ret; 707 } 708 EXPORT_SYMBOL_GPL(load_pdptrs); 709 710 bool pdptrs_changed(struct kvm_vcpu *vcpu) 711 { 712 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 713 bool changed = true; 714 int offset; 715 gfn_t gfn; 716 int r; 717 718 if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu)) 719 return false; 720 721 if (!test_bit(VCPU_EXREG_PDPTR, 722 (unsigned long *)&vcpu->arch.regs_avail)) 723 return true; 724 725 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; 726 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); 727 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 728 PFERR_USER_MASK | PFERR_WRITE_MASK); 729 if (r < 0) 730 goto out; 731 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 732 out: 733 734 return changed; 735 } 736 EXPORT_SYMBOL_GPL(pdptrs_changed); 737 738 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 739 { 740 unsigned long old_cr0 = kvm_read_cr0(vcpu); 741 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 742 743 cr0 |= X86_CR0_ET; 744 745 #ifdef CONFIG_X86_64 746 if (cr0 & 0xffffffff00000000UL) 747 return 1; 748 #endif 749 750 cr0 &= ~CR0_RESERVED_BITS; 751 752 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 753 return 1; 754 755 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 756 return 1; 757 758 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 759 #ifdef CONFIG_X86_64 760 if ((vcpu->arch.efer & EFER_LME)) { 761 int cs_db, cs_l; 762 763 if (!is_pae(vcpu)) 764 return 1; 765 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 766 if (cs_l) 767 return 1; 768 } else 769 #endif 770 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 771 kvm_read_cr3(vcpu))) 772 return 1; 773 } 774 775 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 776 return 1; 777 778 kvm_x86_ops->set_cr0(vcpu, cr0); 779 780 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 781 kvm_clear_async_pf_completion_queue(vcpu); 782 kvm_async_pf_hash_reset(vcpu); 783 } 784 785 if ((cr0 ^ old_cr0) & update_bits) 786 kvm_mmu_reset_context(vcpu); 787 788 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 789 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 790 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 791 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 792 793 return 0; 794 } 795 EXPORT_SYMBOL_GPL(kvm_set_cr0); 796 797 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 798 { 799 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 800 } 801 EXPORT_SYMBOL_GPL(kvm_lmsw); 802 803 void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 804 { 805 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 806 !vcpu->guest_xcr0_loaded) { 807 /* kvm_set_xcr() also depends on this */ 808 if (vcpu->arch.xcr0 != host_xcr0) 809 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 810 vcpu->guest_xcr0_loaded = 1; 811 } 812 } 813 EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0); 814 815 void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 816 { 817 if (vcpu->guest_xcr0_loaded) { 818 if (vcpu->arch.xcr0 != host_xcr0) 819 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 820 vcpu->guest_xcr0_loaded = 0; 821 } 822 } 823 EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0); 824 825 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 826 { 827 u64 xcr0 = xcr; 828 u64 old_xcr0 = vcpu->arch.xcr0; 829 u64 valid_bits; 830 831 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 832 if (index != XCR_XFEATURE_ENABLED_MASK) 833 return 1; 834 if (!(xcr0 & XFEATURE_MASK_FP)) 835 return 1; 836 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 837 return 1; 838 839 /* 840 * Do not allow the guest to set bits that we do not support 841 * saving. However, xcr0 bit 0 is always set, even if the 842 * emulated CPU does not support XSAVE (see fx_init). 843 */ 844 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 845 if (xcr0 & ~valid_bits) 846 return 1; 847 848 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 849 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 850 return 1; 851 852 if (xcr0 & XFEATURE_MASK_AVX512) { 853 if (!(xcr0 & XFEATURE_MASK_YMM)) 854 return 1; 855 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 856 return 1; 857 } 858 vcpu->arch.xcr0 = xcr0; 859 860 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 861 kvm_update_cpuid(vcpu); 862 return 0; 863 } 864 865 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 866 { 867 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 868 __kvm_set_xcr(vcpu, index, xcr)) { 869 kvm_inject_gp(vcpu, 0); 870 return 1; 871 } 872 return 0; 873 } 874 EXPORT_SYMBOL_GPL(kvm_set_xcr); 875 876 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 877 { 878 unsigned long old_cr4 = kvm_read_cr4(vcpu); 879 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 880 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 881 882 if (cr4 & CR4_RESERVED_BITS) 883 return 1; 884 885 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE)) 886 return 1; 887 888 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP)) 889 return 1; 890 891 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP)) 892 return 1; 893 894 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE)) 895 return 1; 896 897 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE)) 898 return 1; 899 900 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57)) 901 return 1; 902 903 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP)) 904 return 1; 905 906 if (is_long_mode(vcpu)) { 907 if (!(cr4 & X86_CR4_PAE)) 908 return 1; 909 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 910 && ((cr4 ^ old_cr4) & pdptr_bits) 911 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 912 kvm_read_cr3(vcpu))) 913 return 1; 914 915 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 916 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 917 return 1; 918 919 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 920 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 921 return 1; 922 } 923 924 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 925 return 1; 926 927 if (((cr4 ^ old_cr4) & pdptr_bits) || 928 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 929 kvm_mmu_reset_context(vcpu); 930 931 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 932 kvm_update_cpuid(vcpu); 933 934 return 0; 935 } 936 EXPORT_SYMBOL_GPL(kvm_set_cr4); 937 938 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 939 { 940 bool skip_tlb_flush = false; 941 #ifdef CONFIG_X86_64 942 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 943 944 if (pcid_enabled) { 945 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 946 cr3 &= ~X86_CR3_PCID_NOFLUSH; 947 } 948 #endif 949 950 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 951 if (!skip_tlb_flush) { 952 kvm_mmu_sync_roots(vcpu); 953 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 954 } 955 return 0; 956 } 957 958 if (is_long_mode(vcpu) && 959 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63))) 960 return 1; 961 else if (is_pae(vcpu) && is_paging(vcpu) && 962 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 963 return 1; 964 965 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush); 966 vcpu->arch.cr3 = cr3; 967 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 968 969 return 0; 970 } 971 EXPORT_SYMBOL_GPL(kvm_set_cr3); 972 973 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 974 { 975 if (cr8 & CR8_RESERVED_BITS) 976 return 1; 977 if (lapic_in_kernel(vcpu)) 978 kvm_lapic_set_tpr(vcpu, cr8); 979 else 980 vcpu->arch.cr8 = cr8; 981 return 0; 982 } 983 EXPORT_SYMBOL_GPL(kvm_set_cr8); 984 985 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 986 { 987 if (lapic_in_kernel(vcpu)) 988 return kvm_lapic_get_cr8(vcpu); 989 else 990 return vcpu->arch.cr8; 991 } 992 EXPORT_SYMBOL_GPL(kvm_get_cr8); 993 994 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 995 { 996 int i; 997 998 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 999 for (i = 0; i < KVM_NR_DB_REGS; i++) 1000 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1001 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 1002 } 1003 } 1004 1005 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 1006 { 1007 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1008 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 1009 } 1010 1011 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 1012 { 1013 unsigned long dr7; 1014 1015 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1016 dr7 = vcpu->arch.guest_debug_dr7; 1017 else 1018 dr7 = vcpu->arch.dr7; 1019 kvm_x86_ops->set_dr7(vcpu, dr7); 1020 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1021 if (dr7 & DR7_BP_EN_MASK) 1022 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1023 } 1024 1025 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1026 { 1027 u64 fixed = DR6_FIXED_1; 1028 1029 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1030 fixed |= DR6_RTM; 1031 return fixed; 1032 } 1033 1034 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1035 { 1036 switch (dr) { 1037 case 0 ... 3: 1038 vcpu->arch.db[dr] = val; 1039 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1040 vcpu->arch.eff_db[dr] = val; 1041 break; 1042 case 4: 1043 /* fall through */ 1044 case 6: 1045 if (val & 0xffffffff00000000ULL) 1046 return -1; /* #GP */ 1047 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1048 kvm_update_dr6(vcpu); 1049 break; 1050 case 5: 1051 /* fall through */ 1052 default: /* 7 */ 1053 if (val & 0xffffffff00000000ULL) 1054 return -1; /* #GP */ 1055 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1056 kvm_update_dr7(vcpu); 1057 break; 1058 } 1059 1060 return 0; 1061 } 1062 1063 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1064 { 1065 if (__kvm_set_dr(vcpu, dr, val)) { 1066 kvm_inject_gp(vcpu, 0); 1067 return 1; 1068 } 1069 return 0; 1070 } 1071 EXPORT_SYMBOL_GPL(kvm_set_dr); 1072 1073 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1074 { 1075 switch (dr) { 1076 case 0 ... 3: 1077 *val = vcpu->arch.db[dr]; 1078 break; 1079 case 4: 1080 /* fall through */ 1081 case 6: 1082 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1083 *val = vcpu->arch.dr6; 1084 else 1085 *val = kvm_x86_ops->get_dr6(vcpu); 1086 break; 1087 case 5: 1088 /* fall through */ 1089 default: /* 7 */ 1090 *val = vcpu->arch.dr7; 1091 break; 1092 } 1093 return 0; 1094 } 1095 EXPORT_SYMBOL_GPL(kvm_get_dr); 1096 1097 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 1098 { 1099 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 1100 u64 data; 1101 int err; 1102 1103 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 1104 if (err) 1105 return err; 1106 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 1107 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 1108 return err; 1109 } 1110 EXPORT_SYMBOL_GPL(kvm_rdpmc); 1111 1112 /* 1113 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1114 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1115 * 1116 * This list is modified at module load time to reflect the 1117 * capabilities of the host cpu. This capabilities test skips MSRs that are 1118 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs 1119 * may depend on host virtualization features rather than host cpu features. 1120 */ 1121 1122 static u32 msrs_to_save[] = { 1123 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1124 MSR_STAR, 1125 #ifdef CONFIG_X86_64 1126 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1127 #endif 1128 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1129 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1130 MSR_IA32_SPEC_CTRL, 1131 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1132 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1133 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1134 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1135 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1136 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1137 }; 1138 1139 static unsigned num_msrs_to_save; 1140 1141 static u32 emulated_msrs[] = { 1142 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1143 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1144 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1145 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1146 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1147 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1148 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1149 HV_X64_MSR_RESET, 1150 HV_X64_MSR_VP_INDEX, 1151 HV_X64_MSR_VP_RUNTIME, 1152 HV_X64_MSR_SCONTROL, 1153 HV_X64_MSR_STIMER0_CONFIG, 1154 HV_X64_MSR_VP_ASSIST_PAGE, 1155 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1156 HV_X64_MSR_TSC_EMULATION_STATUS, 1157 1158 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1159 MSR_KVM_PV_EOI_EN, 1160 1161 MSR_IA32_TSC_ADJUST, 1162 MSR_IA32_TSCDEADLINE, 1163 MSR_IA32_ARCH_CAPABILITIES, 1164 MSR_IA32_MISC_ENABLE, 1165 MSR_IA32_MCG_STATUS, 1166 MSR_IA32_MCG_CTL, 1167 MSR_IA32_MCG_EXT_CTL, 1168 MSR_IA32_SMBASE, 1169 MSR_SMI_COUNT, 1170 MSR_PLATFORM_INFO, 1171 MSR_MISC_FEATURES_ENABLES, 1172 MSR_AMD64_VIRT_SPEC_CTRL, 1173 }; 1174 1175 static unsigned num_emulated_msrs; 1176 1177 /* 1178 * List of msr numbers which are used to expose MSR-based features that 1179 * can be used by a hypervisor to validate requested CPU features. 1180 */ 1181 static u32 msr_based_features[] = { 1182 MSR_IA32_VMX_BASIC, 1183 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1184 MSR_IA32_VMX_PINBASED_CTLS, 1185 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1186 MSR_IA32_VMX_PROCBASED_CTLS, 1187 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1188 MSR_IA32_VMX_EXIT_CTLS, 1189 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1190 MSR_IA32_VMX_ENTRY_CTLS, 1191 MSR_IA32_VMX_MISC, 1192 MSR_IA32_VMX_CR0_FIXED0, 1193 MSR_IA32_VMX_CR0_FIXED1, 1194 MSR_IA32_VMX_CR4_FIXED0, 1195 MSR_IA32_VMX_CR4_FIXED1, 1196 MSR_IA32_VMX_VMCS_ENUM, 1197 MSR_IA32_VMX_PROCBASED_CTLS2, 1198 MSR_IA32_VMX_EPT_VPID_CAP, 1199 MSR_IA32_VMX_VMFUNC, 1200 1201 MSR_F10H_DECFG, 1202 MSR_IA32_UCODE_REV, 1203 MSR_IA32_ARCH_CAPABILITIES, 1204 }; 1205 1206 static unsigned int num_msr_based_features; 1207 1208 u64 kvm_get_arch_capabilities(void) 1209 { 1210 u64 data; 1211 1212 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data); 1213 1214 /* 1215 * If we're doing cache flushes (either "always" or "cond") 1216 * we will do one whenever the guest does a vmlaunch/vmresume. 1217 * If an outer hypervisor is doing the cache flush for us 1218 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1219 * capability to the guest too, and if EPT is disabled we're not 1220 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1221 * require a nested hypervisor to do a flush of its own. 1222 */ 1223 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1224 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1225 1226 return data; 1227 } 1228 EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities); 1229 1230 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1231 { 1232 switch (msr->index) { 1233 case MSR_IA32_ARCH_CAPABILITIES: 1234 msr->data = kvm_get_arch_capabilities(); 1235 break; 1236 case MSR_IA32_UCODE_REV: 1237 rdmsrl_safe(msr->index, &msr->data); 1238 break; 1239 default: 1240 if (kvm_x86_ops->get_msr_feature(msr)) 1241 return 1; 1242 } 1243 return 0; 1244 } 1245 1246 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1247 { 1248 struct kvm_msr_entry msr; 1249 int r; 1250 1251 msr.index = index; 1252 r = kvm_get_msr_feature(&msr); 1253 if (r) 1254 return r; 1255 1256 *data = msr.data; 1257 1258 return 0; 1259 } 1260 1261 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1262 { 1263 if (efer & efer_reserved_bits) 1264 return false; 1265 1266 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1267 return false; 1268 1269 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1270 return false; 1271 1272 return true; 1273 } 1274 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1275 1276 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 1277 { 1278 u64 old_efer = vcpu->arch.efer; 1279 1280 if (!kvm_valid_efer(vcpu, efer)) 1281 return 1; 1282 1283 if (is_paging(vcpu) 1284 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1285 return 1; 1286 1287 efer &= ~EFER_LMA; 1288 efer |= vcpu->arch.efer & EFER_LMA; 1289 1290 kvm_x86_ops->set_efer(vcpu, efer); 1291 1292 /* Update reserved bits */ 1293 if ((efer ^ old_efer) & EFER_NX) 1294 kvm_mmu_reset_context(vcpu); 1295 1296 return 0; 1297 } 1298 1299 void kvm_enable_efer_bits(u64 mask) 1300 { 1301 efer_reserved_bits &= ~mask; 1302 } 1303 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1304 1305 /* 1306 * Writes msr value into into the appropriate "register". 1307 * Returns 0 on success, non-0 otherwise. 1308 * Assumes vcpu_load() was already called. 1309 */ 1310 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1311 { 1312 switch (msr->index) { 1313 case MSR_FS_BASE: 1314 case MSR_GS_BASE: 1315 case MSR_KERNEL_GS_BASE: 1316 case MSR_CSTAR: 1317 case MSR_LSTAR: 1318 if (is_noncanonical_address(msr->data, vcpu)) 1319 return 1; 1320 break; 1321 case MSR_IA32_SYSENTER_EIP: 1322 case MSR_IA32_SYSENTER_ESP: 1323 /* 1324 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1325 * non-canonical address is written on Intel but not on 1326 * AMD (which ignores the top 32-bits, because it does 1327 * not implement 64-bit SYSENTER). 1328 * 1329 * 64-bit code should hence be able to write a non-canonical 1330 * value on AMD. Making the address canonical ensures that 1331 * vmentry does not fail on Intel after writing a non-canonical 1332 * value, and that something deterministic happens if the guest 1333 * invokes 64-bit SYSENTER. 1334 */ 1335 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu)); 1336 } 1337 return kvm_x86_ops->set_msr(vcpu, msr); 1338 } 1339 EXPORT_SYMBOL_GPL(kvm_set_msr); 1340 1341 /* 1342 * Adapt set_msr() to msr_io()'s calling convention 1343 */ 1344 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1345 { 1346 struct msr_data msr; 1347 int r; 1348 1349 msr.index = index; 1350 msr.host_initiated = true; 1351 r = kvm_get_msr(vcpu, &msr); 1352 if (r) 1353 return r; 1354 1355 *data = msr.data; 1356 return 0; 1357 } 1358 1359 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1360 { 1361 struct msr_data msr; 1362 1363 msr.data = *data; 1364 msr.index = index; 1365 msr.host_initiated = true; 1366 return kvm_set_msr(vcpu, &msr); 1367 } 1368 1369 #ifdef CONFIG_X86_64 1370 struct pvclock_gtod_data { 1371 seqcount_t seq; 1372 1373 struct { /* extract of a clocksource struct */ 1374 int vclock_mode; 1375 u64 cycle_last; 1376 u64 mask; 1377 u32 mult; 1378 u32 shift; 1379 } clock; 1380 1381 u64 boot_ns; 1382 u64 nsec_base; 1383 u64 wall_time_sec; 1384 }; 1385 1386 static struct pvclock_gtod_data pvclock_gtod_data; 1387 1388 static void update_pvclock_gtod(struct timekeeper *tk) 1389 { 1390 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1391 u64 boot_ns; 1392 1393 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1394 1395 write_seqcount_begin(&vdata->seq); 1396 1397 /* copy pvclock gtod data */ 1398 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1399 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1400 vdata->clock.mask = tk->tkr_mono.mask; 1401 vdata->clock.mult = tk->tkr_mono.mult; 1402 vdata->clock.shift = tk->tkr_mono.shift; 1403 1404 vdata->boot_ns = boot_ns; 1405 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1406 1407 vdata->wall_time_sec = tk->xtime_sec; 1408 1409 write_seqcount_end(&vdata->seq); 1410 } 1411 #endif 1412 1413 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1414 { 1415 /* 1416 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1417 * vcpu_enter_guest. This function is only called from 1418 * the physical CPU that is running vcpu. 1419 */ 1420 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1421 } 1422 1423 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1424 { 1425 int version; 1426 int r; 1427 struct pvclock_wall_clock wc; 1428 struct timespec64 boot; 1429 1430 if (!wall_clock) 1431 return; 1432 1433 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1434 if (r) 1435 return; 1436 1437 if (version & 1) 1438 ++version; /* first time write, random junk */ 1439 1440 ++version; 1441 1442 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1443 return; 1444 1445 /* 1446 * The guest calculates current wall clock time by adding 1447 * system time (updated by kvm_guest_time_update below) to the 1448 * wall clock specified here. guest system time equals host 1449 * system time for us, thus we must fill in host boot time here. 1450 */ 1451 getboottime64(&boot); 1452 1453 if (kvm->arch.kvmclock_offset) { 1454 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset); 1455 boot = timespec64_sub(boot, ts); 1456 } 1457 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */ 1458 wc.nsec = boot.tv_nsec; 1459 wc.version = version; 1460 1461 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1462 1463 version++; 1464 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1465 } 1466 1467 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1468 { 1469 do_shl32_div32(dividend, divisor); 1470 return dividend; 1471 } 1472 1473 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 1474 s8 *pshift, u32 *pmultiplier) 1475 { 1476 uint64_t scaled64; 1477 int32_t shift = 0; 1478 uint64_t tps64; 1479 uint32_t tps32; 1480 1481 tps64 = base_hz; 1482 scaled64 = scaled_hz; 1483 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1484 tps64 >>= 1; 1485 shift--; 1486 } 1487 1488 tps32 = (uint32_t)tps64; 1489 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1490 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1491 scaled64 >>= 1; 1492 else 1493 tps32 <<= 1; 1494 shift++; 1495 } 1496 1497 *pshift = shift; 1498 *pmultiplier = div_frac(scaled64, tps32); 1499 1500 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n", 1501 __func__, base_hz, scaled_hz, shift, *pmultiplier); 1502 } 1503 1504 #ifdef CONFIG_X86_64 1505 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1506 #endif 1507 1508 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1509 static unsigned long max_tsc_khz; 1510 1511 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1512 { 1513 u64 v = (u64)khz * (1000000 + ppm); 1514 do_div(v, 1000000); 1515 return v; 1516 } 1517 1518 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 1519 { 1520 u64 ratio; 1521 1522 /* Guest TSC same frequency as host TSC? */ 1523 if (!scale) { 1524 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1525 return 0; 1526 } 1527 1528 /* TSC scaling supported? */ 1529 if (!kvm_has_tsc_control) { 1530 if (user_tsc_khz > tsc_khz) { 1531 vcpu->arch.tsc_catchup = 1; 1532 vcpu->arch.tsc_always_catchup = 1; 1533 return 0; 1534 } else { 1535 WARN(1, "user requested TSC rate below hardware speed\n"); 1536 return -1; 1537 } 1538 } 1539 1540 /* TSC scaling required - calculate ratio */ 1541 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 1542 user_tsc_khz, tsc_khz); 1543 1544 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 1545 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 1546 user_tsc_khz); 1547 return -1; 1548 } 1549 1550 vcpu->arch.tsc_scaling_ratio = ratio; 1551 return 0; 1552 } 1553 1554 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 1555 { 1556 u32 thresh_lo, thresh_hi; 1557 int use_scaling = 0; 1558 1559 /* tsc_khz can be zero if TSC calibration fails */ 1560 if (user_tsc_khz == 0) { 1561 /* set tsc_scaling_ratio to a safe value */ 1562 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1563 return -1; 1564 } 1565 1566 /* Compute a scale to convert nanoseconds in TSC cycles */ 1567 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 1568 &vcpu->arch.virtual_tsc_shift, 1569 &vcpu->arch.virtual_tsc_mult); 1570 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 1571 1572 /* 1573 * Compute the variation in TSC rate which is acceptable 1574 * within the range of tolerance and decide if the 1575 * rate being applied is within that bounds of the hardware 1576 * rate. If so, no scaling or compensation need be done. 1577 */ 1578 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1579 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1580 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 1581 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 1582 use_scaling = 1; 1583 } 1584 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 1585 } 1586 1587 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1588 { 1589 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1590 vcpu->arch.virtual_tsc_mult, 1591 vcpu->arch.virtual_tsc_shift); 1592 tsc += vcpu->arch.this_tsc_write; 1593 return tsc; 1594 } 1595 1596 static inline int gtod_is_based_on_tsc(int mode) 1597 { 1598 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK; 1599 } 1600 1601 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1602 { 1603 #ifdef CONFIG_X86_64 1604 bool vcpus_matched; 1605 struct kvm_arch *ka = &vcpu->kvm->arch; 1606 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1607 1608 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1609 atomic_read(&vcpu->kvm->online_vcpus)); 1610 1611 /* 1612 * Once the masterclock is enabled, always perform request in 1613 * order to update it. 1614 * 1615 * In order to enable masterclock, the host clocksource must be TSC 1616 * and the vcpus need to have matched TSCs. When that happens, 1617 * perform request to enable masterclock. 1618 */ 1619 if (ka->use_master_clock || 1620 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 1621 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1622 1623 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1624 atomic_read(&vcpu->kvm->online_vcpus), 1625 ka->use_master_clock, gtod->clock.vclock_mode); 1626 #endif 1627 } 1628 1629 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1630 { 1631 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); 1632 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1633 } 1634 1635 /* 1636 * Multiply tsc by a fixed point number represented by ratio. 1637 * 1638 * The most significant 64-N bits (mult) of ratio represent the 1639 * integral part of the fixed point number; the remaining N bits 1640 * (frac) represent the fractional part, ie. ratio represents a fixed 1641 * point number (mult + frac * 2^(-N)). 1642 * 1643 * N equals to kvm_tsc_scaling_ratio_frac_bits. 1644 */ 1645 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 1646 { 1647 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 1648 } 1649 1650 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 1651 { 1652 u64 _tsc = tsc; 1653 u64 ratio = vcpu->arch.tsc_scaling_ratio; 1654 1655 if (ratio != kvm_default_tsc_scaling_ratio) 1656 _tsc = __scale_tsc(ratio, tsc); 1657 1658 return _tsc; 1659 } 1660 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 1661 1662 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 1663 { 1664 u64 tsc; 1665 1666 tsc = kvm_scale_tsc(vcpu, rdtsc()); 1667 1668 return target_tsc - tsc; 1669 } 1670 1671 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 1672 { 1673 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); 1674 1675 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc); 1676 } 1677 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 1678 1679 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1680 { 1681 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset); 1682 } 1683 1684 static inline bool kvm_check_tsc_unstable(void) 1685 { 1686 #ifdef CONFIG_X86_64 1687 /* 1688 * TSC is marked unstable when we're running on Hyper-V, 1689 * 'TSC page' clocksource is good. 1690 */ 1691 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK) 1692 return false; 1693 #endif 1694 return check_tsc_unstable(); 1695 } 1696 1697 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1698 { 1699 struct kvm *kvm = vcpu->kvm; 1700 u64 offset, ns, elapsed; 1701 unsigned long flags; 1702 bool matched; 1703 bool already_matched; 1704 u64 data = msr->data; 1705 bool synchronizing = false; 1706 1707 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1708 offset = kvm_compute_tsc_offset(vcpu, data); 1709 ns = ktime_get_boot_ns(); 1710 elapsed = ns - kvm->arch.last_tsc_nsec; 1711 1712 if (vcpu->arch.virtual_tsc_khz) { 1713 if (data == 0 && msr->host_initiated) { 1714 /* 1715 * detection of vcpu initialization -- need to sync 1716 * with other vCPUs. This particularly helps to keep 1717 * kvm_clock stable after CPU hotplug 1718 */ 1719 synchronizing = true; 1720 } else { 1721 u64 tsc_exp = kvm->arch.last_tsc_write + 1722 nsec_to_cycles(vcpu, elapsed); 1723 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 1724 /* 1725 * Special case: TSC write with a small delta (1 second) 1726 * of virtual cycle time against real time is 1727 * interpreted as an attempt to synchronize the CPU. 1728 */ 1729 synchronizing = data < tsc_exp + tsc_hz && 1730 data + tsc_hz > tsc_exp; 1731 } 1732 } 1733 1734 /* 1735 * For a reliable TSC, we can match TSC offsets, and for an unstable 1736 * TSC, we add elapsed time in this computation. We could let the 1737 * compensation code attempt to catch up if we fall behind, but 1738 * it's better to try to match offsets from the beginning. 1739 */ 1740 if (synchronizing && 1741 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1742 if (!kvm_check_tsc_unstable()) { 1743 offset = kvm->arch.cur_tsc_offset; 1744 pr_debug("kvm: matched tsc offset for %llu\n", data); 1745 } else { 1746 u64 delta = nsec_to_cycles(vcpu, elapsed); 1747 data += delta; 1748 offset = kvm_compute_tsc_offset(vcpu, data); 1749 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1750 } 1751 matched = true; 1752 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1753 } else { 1754 /* 1755 * We split periods of matched TSC writes into generations. 1756 * For each generation, we track the original measured 1757 * nanosecond time, offset, and write, so if TSCs are in 1758 * sync, we can match exact offset, and if not, we can match 1759 * exact software computation in compute_guest_tsc() 1760 * 1761 * These values are tracked in kvm->arch.cur_xxx variables. 1762 */ 1763 kvm->arch.cur_tsc_generation++; 1764 kvm->arch.cur_tsc_nsec = ns; 1765 kvm->arch.cur_tsc_write = data; 1766 kvm->arch.cur_tsc_offset = offset; 1767 matched = false; 1768 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1769 kvm->arch.cur_tsc_generation, data); 1770 } 1771 1772 /* 1773 * We also track th most recent recorded KHZ, write and time to 1774 * allow the matching interval to be extended at each write. 1775 */ 1776 kvm->arch.last_tsc_nsec = ns; 1777 kvm->arch.last_tsc_write = data; 1778 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1779 1780 vcpu->arch.last_guest_tsc = data; 1781 1782 /* Keep track of which generation this VCPU has synchronized to */ 1783 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1784 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1785 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1786 1787 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) 1788 update_ia32_tsc_adjust_msr(vcpu, offset); 1789 1790 kvm_vcpu_write_tsc_offset(vcpu, offset); 1791 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1792 1793 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1794 if (!matched) { 1795 kvm->arch.nr_vcpus_matched_tsc = 0; 1796 } else if (!already_matched) { 1797 kvm->arch.nr_vcpus_matched_tsc++; 1798 } 1799 1800 kvm_track_tsc_matching(vcpu); 1801 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1802 } 1803 1804 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1805 1806 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 1807 s64 adjustment) 1808 { 1809 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); 1810 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 1811 } 1812 1813 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 1814 { 1815 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 1816 WARN_ON(adjustment < 0); 1817 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 1818 adjust_tsc_offset_guest(vcpu, adjustment); 1819 } 1820 1821 #ifdef CONFIG_X86_64 1822 1823 static u64 read_tsc(void) 1824 { 1825 u64 ret = (u64)rdtsc_ordered(); 1826 u64 last = pvclock_gtod_data.clock.cycle_last; 1827 1828 if (likely(ret >= last)) 1829 return ret; 1830 1831 /* 1832 * GCC likes to generate cmov here, but this branch is extremely 1833 * predictable (it's just a function of time and the likely is 1834 * very likely) and there's a data dependence, so force GCC 1835 * to generate a branch instead. I don't barrier() because 1836 * we don't actually need a barrier, and if this function 1837 * ever gets inlined it will generate worse code. 1838 */ 1839 asm volatile (""); 1840 return last; 1841 } 1842 1843 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode) 1844 { 1845 long v; 1846 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1847 u64 tsc_pg_val; 1848 1849 switch (gtod->clock.vclock_mode) { 1850 case VCLOCK_HVCLOCK: 1851 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 1852 tsc_timestamp); 1853 if (tsc_pg_val != U64_MAX) { 1854 /* TSC page valid */ 1855 *mode = VCLOCK_HVCLOCK; 1856 v = (tsc_pg_val - gtod->clock.cycle_last) & 1857 gtod->clock.mask; 1858 } else { 1859 /* TSC page invalid */ 1860 *mode = VCLOCK_NONE; 1861 } 1862 break; 1863 case VCLOCK_TSC: 1864 *mode = VCLOCK_TSC; 1865 *tsc_timestamp = read_tsc(); 1866 v = (*tsc_timestamp - gtod->clock.cycle_last) & 1867 gtod->clock.mask; 1868 break; 1869 default: 1870 *mode = VCLOCK_NONE; 1871 } 1872 1873 if (*mode == VCLOCK_NONE) 1874 *tsc_timestamp = v = 0; 1875 1876 return v * gtod->clock.mult; 1877 } 1878 1879 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp) 1880 { 1881 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1882 unsigned long seq; 1883 int mode; 1884 u64 ns; 1885 1886 do { 1887 seq = read_seqcount_begin(>od->seq); 1888 ns = gtod->nsec_base; 1889 ns += vgettsc(tsc_timestamp, &mode); 1890 ns >>= gtod->clock.shift; 1891 ns += gtod->boot_ns; 1892 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1893 *t = ns; 1894 1895 return mode; 1896 } 1897 1898 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 1899 { 1900 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1901 unsigned long seq; 1902 int mode; 1903 u64 ns; 1904 1905 do { 1906 seq = read_seqcount_begin(>od->seq); 1907 ts->tv_sec = gtod->wall_time_sec; 1908 ns = gtod->nsec_base; 1909 ns += vgettsc(tsc_timestamp, &mode); 1910 ns >>= gtod->clock.shift; 1911 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1912 1913 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 1914 ts->tv_nsec = ns; 1915 1916 return mode; 1917 } 1918 1919 /* returns true if host is using TSC based clocksource */ 1920 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 1921 { 1922 /* checked again under seqlock below */ 1923 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 1924 return false; 1925 1926 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns, 1927 tsc_timestamp)); 1928 } 1929 1930 /* returns true if host is using TSC based clocksource */ 1931 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 1932 u64 *tsc_timestamp) 1933 { 1934 /* checked again under seqlock below */ 1935 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 1936 return false; 1937 1938 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 1939 } 1940 #endif 1941 1942 /* 1943 * 1944 * Assuming a stable TSC across physical CPUS, and a stable TSC 1945 * across virtual CPUs, the following condition is possible. 1946 * Each numbered line represents an event visible to both 1947 * CPUs at the next numbered event. 1948 * 1949 * "timespecX" represents host monotonic time. "tscX" represents 1950 * RDTSC value. 1951 * 1952 * VCPU0 on CPU0 | VCPU1 on CPU1 1953 * 1954 * 1. read timespec0,tsc0 1955 * 2. | timespec1 = timespec0 + N 1956 * | tsc1 = tsc0 + M 1957 * 3. transition to guest | transition to guest 1958 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1959 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1960 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1961 * 1962 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1963 * 1964 * - ret0 < ret1 1965 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1966 * ... 1967 * - 0 < N - M => M < N 1968 * 1969 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1970 * always the case (the difference between two distinct xtime instances 1971 * might be smaller then the difference between corresponding TSC reads, 1972 * when updating guest vcpus pvclock areas). 1973 * 1974 * To avoid that problem, do not allow visibility of distinct 1975 * system_timestamp/tsc_timestamp values simultaneously: use a master 1976 * copy of host monotonic time values. Update that master copy 1977 * in lockstep. 1978 * 1979 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1980 * 1981 */ 1982 1983 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1984 { 1985 #ifdef CONFIG_X86_64 1986 struct kvm_arch *ka = &kvm->arch; 1987 int vclock_mode; 1988 bool host_tsc_clocksource, vcpus_matched; 1989 1990 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1991 atomic_read(&kvm->online_vcpus)); 1992 1993 /* 1994 * If the host uses TSC clock, then passthrough TSC as stable 1995 * to the guest. 1996 */ 1997 host_tsc_clocksource = kvm_get_time_and_clockread( 1998 &ka->master_kernel_ns, 1999 &ka->master_cycle_now); 2000 2001 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2002 && !ka->backwards_tsc_observed 2003 && !ka->boot_vcpu_runs_old_kvmclock; 2004 2005 if (ka->use_master_clock) 2006 atomic_set(&kvm_guest_has_master_clock, 1); 2007 2008 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2009 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2010 vcpus_matched); 2011 #endif 2012 } 2013 2014 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2015 { 2016 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2017 } 2018 2019 static void kvm_gen_update_masterclock(struct kvm *kvm) 2020 { 2021 #ifdef CONFIG_X86_64 2022 int i; 2023 struct kvm_vcpu *vcpu; 2024 struct kvm_arch *ka = &kvm->arch; 2025 2026 spin_lock(&ka->pvclock_gtod_sync_lock); 2027 kvm_make_mclock_inprogress_request(kvm); 2028 /* no guest entries from this point */ 2029 pvclock_update_vm_gtod_copy(kvm); 2030 2031 kvm_for_each_vcpu(i, vcpu, kvm) 2032 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2033 2034 /* guest entries allowed */ 2035 kvm_for_each_vcpu(i, vcpu, kvm) 2036 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2037 2038 spin_unlock(&ka->pvclock_gtod_sync_lock); 2039 #endif 2040 } 2041 2042 u64 get_kvmclock_ns(struct kvm *kvm) 2043 { 2044 struct kvm_arch *ka = &kvm->arch; 2045 struct pvclock_vcpu_time_info hv_clock; 2046 u64 ret; 2047 2048 spin_lock(&ka->pvclock_gtod_sync_lock); 2049 if (!ka->use_master_clock) { 2050 spin_unlock(&ka->pvclock_gtod_sync_lock); 2051 return ktime_get_boot_ns() + ka->kvmclock_offset; 2052 } 2053 2054 hv_clock.tsc_timestamp = ka->master_cycle_now; 2055 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2056 spin_unlock(&ka->pvclock_gtod_sync_lock); 2057 2058 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2059 get_cpu(); 2060 2061 if (__this_cpu_read(cpu_tsc_khz)) { 2062 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2063 &hv_clock.tsc_shift, 2064 &hv_clock.tsc_to_system_mul); 2065 ret = __pvclock_read_cycles(&hv_clock, rdtsc()); 2066 } else 2067 ret = ktime_get_boot_ns() + ka->kvmclock_offset; 2068 2069 put_cpu(); 2070 2071 return ret; 2072 } 2073 2074 static void kvm_setup_pvclock_page(struct kvm_vcpu *v) 2075 { 2076 struct kvm_vcpu_arch *vcpu = &v->arch; 2077 struct pvclock_vcpu_time_info guest_hv_clock; 2078 2079 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 2080 &guest_hv_clock, sizeof(guest_hv_clock)))) 2081 return; 2082 2083 /* This VCPU is paused, but it's legal for a guest to read another 2084 * VCPU's kvmclock, so we really have to follow the specification where 2085 * it says that version is odd if data is being modified, and even after 2086 * it is consistent. 2087 * 2088 * Version field updates must be kept separate. This is because 2089 * kvm_write_guest_cached might use a "rep movs" instruction, and 2090 * writes within a string instruction are weakly ordered. So there 2091 * are three writes overall. 2092 * 2093 * As a small optimization, only write the version field in the first 2094 * and third write. The vcpu->pv_time cache is still valid, because the 2095 * version field is the first in the struct. 2096 */ 2097 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 2098 2099 if (guest_hv_clock.version & 1) 2100 ++guest_hv_clock.version; /* first time write, random junk */ 2101 2102 vcpu->hv_clock.version = guest_hv_clock.version + 1; 2103 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2104 &vcpu->hv_clock, 2105 sizeof(vcpu->hv_clock.version)); 2106 2107 smp_wmb(); 2108 2109 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 2110 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 2111 2112 if (vcpu->pvclock_set_guest_stopped_request) { 2113 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 2114 vcpu->pvclock_set_guest_stopped_request = false; 2115 } 2116 2117 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 2118 2119 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2120 &vcpu->hv_clock, 2121 sizeof(vcpu->hv_clock)); 2122 2123 smp_wmb(); 2124 2125 vcpu->hv_clock.version++; 2126 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2127 &vcpu->hv_clock, 2128 sizeof(vcpu->hv_clock.version)); 2129 } 2130 2131 static int kvm_guest_time_update(struct kvm_vcpu *v) 2132 { 2133 unsigned long flags, tgt_tsc_khz; 2134 struct kvm_vcpu_arch *vcpu = &v->arch; 2135 struct kvm_arch *ka = &v->kvm->arch; 2136 s64 kernel_ns; 2137 u64 tsc_timestamp, host_tsc; 2138 u8 pvclock_flags; 2139 bool use_master_clock; 2140 2141 kernel_ns = 0; 2142 host_tsc = 0; 2143 2144 /* 2145 * If the host uses TSC clock, then passthrough TSC as stable 2146 * to the guest. 2147 */ 2148 spin_lock(&ka->pvclock_gtod_sync_lock); 2149 use_master_clock = ka->use_master_clock; 2150 if (use_master_clock) { 2151 host_tsc = ka->master_cycle_now; 2152 kernel_ns = ka->master_kernel_ns; 2153 } 2154 spin_unlock(&ka->pvclock_gtod_sync_lock); 2155 2156 /* Keep irq disabled to prevent changes to the clock */ 2157 local_irq_save(flags); 2158 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 2159 if (unlikely(tgt_tsc_khz == 0)) { 2160 local_irq_restore(flags); 2161 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2162 return 1; 2163 } 2164 if (!use_master_clock) { 2165 host_tsc = rdtsc(); 2166 kernel_ns = ktime_get_boot_ns(); 2167 } 2168 2169 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 2170 2171 /* 2172 * We may have to catch up the TSC to match elapsed wall clock 2173 * time for two reasons, even if kvmclock is used. 2174 * 1) CPU could have been running below the maximum TSC rate 2175 * 2) Broken TSC compensation resets the base at each VCPU 2176 * entry to avoid unknown leaps of TSC even when running 2177 * again on the same CPU. This may cause apparent elapsed 2178 * time to disappear, and the guest to stand still or run 2179 * very slowly. 2180 */ 2181 if (vcpu->tsc_catchup) { 2182 u64 tsc = compute_guest_tsc(v, kernel_ns); 2183 if (tsc > tsc_timestamp) { 2184 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 2185 tsc_timestamp = tsc; 2186 } 2187 } 2188 2189 local_irq_restore(flags); 2190 2191 /* With all the info we got, fill in the values */ 2192 2193 if (kvm_has_tsc_control) 2194 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 2195 2196 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 2197 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 2198 &vcpu->hv_clock.tsc_shift, 2199 &vcpu->hv_clock.tsc_to_system_mul); 2200 vcpu->hw_tsc_khz = tgt_tsc_khz; 2201 } 2202 2203 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 2204 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 2205 vcpu->last_guest_tsc = tsc_timestamp; 2206 2207 /* If the host uses TSC clocksource, then it is stable */ 2208 pvclock_flags = 0; 2209 if (use_master_clock) 2210 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 2211 2212 vcpu->hv_clock.flags = pvclock_flags; 2213 2214 if (vcpu->pv_time_enabled) 2215 kvm_setup_pvclock_page(v); 2216 if (v == kvm_get_vcpu(v->kvm, 0)) 2217 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 2218 return 0; 2219 } 2220 2221 /* 2222 * kvmclock updates which are isolated to a given vcpu, such as 2223 * vcpu->cpu migration, should not allow system_timestamp from 2224 * the rest of the vcpus to remain static. Otherwise ntp frequency 2225 * correction applies to one vcpu's system_timestamp but not 2226 * the others. 2227 * 2228 * So in those cases, request a kvmclock update for all vcpus. 2229 * We need to rate-limit these requests though, as they can 2230 * considerably slow guests that have a large number of vcpus. 2231 * The time for a remote vcpu to update its kvmclock is bound 2232 * by the delay we use to rate-limit the updates. 2233 */ 2234 2235 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 2236 2237 static void kvmclock_update_fn(struct work_struct *work) 2238 { 2239 int i; 2240 struct delayed_work *dwork = to_delayed_work(work); 2241 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2242 kvmclock_update_work); 2243 struct kvm *kvm = container_of(ka, struct kvm, arch); 2244 struct kvm_vcpu *vcpu; 2245 2246 kvm_for_each_vcpu(i, vcpu, kvm) { 2247 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2248 kvm_vcpu_kick(vcpu); 2249 } 2250 } 2251 2252 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 2253 { 2254 struct kvm *kvm = v->kvm; 2255 2256 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2257 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 2258 KVMCLOCK_UPDATE_DELAY); 2259 } 2260 2261 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 2262 2263 static void kvmclock_sync_fn(struct work_struct *work) 2264 { 2265 struct delayed_work *dwork = to_delayed_work(work); 2266 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2267 kvmclock_sync_work); 2268 struct kvm *kvm = container_of(ka, struct kvm, arch); 2269 2270 if (!kvmclock_periodic_sync) 2271 return; 2272 2273 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 2274 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 2275 KVMCLOCK_SYNC_PERIOD); 2276 } 2277 2278 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2279 { 2280 u64 mcg_cap = vcpu->arch.mcg_cap; 2281 unsigned bank_num = mcg_cap & 0xff; 2282 u32 msr = msr_info->index; 2283 u64 data = msr_info->data; 2284 2285 switch (msr) { 2286 case MSR_IA32_MCG_STATUS: 2287 vcpu->arch.mcg_status = data; 2288 break; 2289 case MSR_IA32_MCG_CTL: 2290 if (!(mcg_cap & MCG_CTL_P) && 2291 (data || !msr_info->host_initiated)) 2292 return 1; 2293 if (data != 0 && data != ~(u64)0) 2294 return 1; 2295 vcpu->arch.mcg_ctl = data; 2296 break; 2297 default: 2298 if (msr >= MSR_IA32_MC0_CTL && 2299 msr < MSR_IA32_MCx_CTL(bank_num)) { 2300 u32 offset = msr - MSR_IA32_MC0_CTL; 2301 /* only 0 or all 1s can be written to IA32_MCi_CTL 2302 * some Linux kernels though clear bit 10 in bank 4 to 2303 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 2304 * this to avoid an uncatched #GP in the guest 2305 */ 2306 if ((offset & 0x3) == 0 && 2307 data != 0 && (data | (1 << 10)) != ~(u64)0) 2308 return -1; 2309 if (!msr_info->host_initiated && 2310 (offset & 0x3) == 1 && data != 0) 2311 return -1; 2312 vcpu->arch.mce_banks[offset] = data; 2313 break; 2314 } 2315 return 1; 2316 } 2317 return 0; 2318 } 2319 2320 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 2321 { 2322 struct kvm *kvm = vcpu->kvm; 2323 int lm = is_long_mode(vcpu); 2324 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 2325 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 2326 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 2327 : kvm->arch.xen_hvm_config.blob_size_32; 2328 u32 page_num = data & ~PAGE_MASK; 2329 u64 page_addr = data & PAGE_MASK; 2330 u8 *page; 2331 int r; 2332 2333 r = -E2BIG; 2334 if (page_num >= blob_size) 2335 goto out; 2336 r = -ENOMEM; 2337 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 2338 if (IS_ERR(page)) { 2339 r = PTR_ERR(page); 2340 goto out; 2341 } 2342 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 2343 goto out_free; 2344 r = 0; 2345 out_free: 2346 kfree(page); 2347 out: 2348 return r; 2349 } 2350 2351 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2352 { 2353 gpa_t gpa = data & ~0x3f; 2354 2355 /* Bits 3:5 are reserved, Should be zero */ 2356 if (data & 0x38) 2357 return 1; 2358 2359 vcpu->arch.apf.msr_val = data; 2360 2361 if (!(data & KVM_ASYNC_PF_ENABLED)) { 2362 kvm_clear_async_pf_completion_queue(vcpu); 2363 kvm_async_pf_hash_reset(vcpu); 2364 return 0; 2365 } 2366 2367 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2368 sizeof(u32))) 2369 return 1; 2370 2371 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2372 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 2373 kvm_async_pf_wakeup_all(vcpu); 2374 return 0; 2375 } 2376 2377 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2378 { 2379 vcpu->arch.pv_time_enabled = false; 2380 } 2381 2382 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) 2383 { 2384 ++vcpu->stat.tlb_flush; 2385 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa); 2386 } 2387 2388 static void record_steal_time(struct kvm_vcpu *vcpu) 2389 { 2390 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2391 return; 2392 2393 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2394 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2395 return; 2396 2397 /* 2398 * Doing a TLB flush here, on the guest's behalf, can avoid 2399 * expensive IPIs. 2400 */ 2401 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB) 2402 kvm_vcpu_flush_tlb(vcpu, false); 2403 2404 if (vcpu->arch.st.steal.version & 1) 2405 vcpu->arch.st.steal.version += 1; /* first time write, random junk */ 2406 2407 vcpu->arch.st.steal.version += 1; 2408 2409 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2410 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2411 2412 smp_wmb(); 2413 2414 vcpu->arch.st.steal.steal += current->sched_info.run_delay - 2415 vcpu->arch.st.last_steal; 2416 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2417 2418 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2419 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2420 2421 smp_wmb(); 2422 2423 vcpu->arch.st.steal.version += 1; 2424 2425 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2426 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2427 } 2428 2429 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2430 { 2431 bool pr = false; 2432 u32 msr = msr_info->index; 2433 u64 data = msr_info->data; 2434 2435 switch (msr) { 2436 case MSR_AMD64_NB_CFG: 2437 case MSR_IA32_UCODE_WRITE: 2438 case MSR_VM_HSAVE_PA: 2439 case MSR_AMD64_PATCH_LOADER: 2440 case MSR_AMD64_BU_CFG2: 2441 case MSR_AMD64_DC_CFG: 2442 case MSR_F15H_EX_CFG: 2443 break; 2444 2445 case MSR_IA32_UCODE_REV: 2446 if (msr_info->host_initiated) 2447 vcpu->arch.microcode_version = data; 2448 break; 2449 case MSR_IA32_ARCH_CAPABILITIES: 2450 if (!msr_info->host_initiated) 2451 return 1; 2452 vcpu->arch.arch_capabilities = data; 2453 break; 2454 case MSR_EFER: 2455 return set_efer(vcpu, data); 2456 case MSR_K7_HWCR: 2457 data &= ~(u64)0x40; /* ignore flush filter disable */ 2458 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2459 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2460 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2461 if (data != 0) { 2462 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2463 data); 2464 return 1; 2465 } 2466 break; 2467 case MSR_FAM10H_MMIO_CONF_BASE: 2468 if (data != 0) { 2469 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2470 "0x%llx\n", data); 2471 return 1; 2472 } 2473 break; 2474 case MSR_IA32_DEBUGCTLMSR: 2475 if (!data) { 2476 /* We support the non-activated case already */ 2477 break; 2478 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2479 /* Values other than LBR and BTF are vendor-specific, 2480 thus reserved and should throw a #GP */ 2481 return 1; 2482 } 2483 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2484 __func__, data); 2485 break; 2486 case 0x200 ... 0x2ff: 2487 return kvm_mtrr_set_msr(vcpu, msr, data); 2488 case MSR_IA32_APICBASE: 2489 return kvm_set_apic_base(vcpu, msr_info); 2490 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2491 return kvm_x2apic_msr_write(vcpu, msr, data); 2492 case MSR_IA32_TSCDEADLINE: 2493 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2494 break; 2495 case MSR_IA32_TSC_ADJUST: 2496 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 2497 if (!msr_info->host_initiated) { 2498 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2499 adjust_tsc_offset_guest(vcpu, adj); 2500 } 2501 vcpu->arch.ia32_tsc_adjust_msr = data; 2502 } 2503 break; 2504 case MSR_IA32_MISC_ENABLE: 2505 vcpu->arch.ia32_misc_enable_msr = data; 2506 break; 2507 case MSR_IA32_SMBASE: 2508 if (!msr_info->host_initiated) 2509 return 1; 2510 vcpu->arch.smbase = data; 2511 break; 2512 case MSR_IA32_TSC: 2513 kvm_write_tsc(vcpu, msr_info); 2514 break; 2515 case MSR_SMI_COUNT: 2516 if (!msr_info->host_initiated) 2517 return 1; 2518 vcpu->arch.smi_count = data; 2519 break; 2520 case MSR_KVM_WALL_CLOCK_NEW: 2521 case MSR_KVM_WALL_CLOCK: 2522 vcpu->kvm->arch.wall_clock = data; 2523 kvm_write_wall_clock(vcpu->kvm, data); 2524 break; 2525 case MSR_KVM_SYSTEM_TIME_NEW: 2526 case MSR_KVM_SYSTEM_TIME: { 2527 struct kvm_arch *ka = &vcpu->kvm->arch; 2528 2529 kvmclock_reset(vcpu); 2530 2531 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2532 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2533 2534 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2535 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2536 2537 ka->boot_vcpu_runs_old_kvmclock = tmp; 2538 } 2539 2540 vcpu->arch.time = data; 2541 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2542 2543 /* we verify if the enable bit is set... */ 2544 if (!(data & 1)) 2545 break; 2546 2547 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2548 &vcpu->arch.pv_time, data & ~1ULL, 2549 sizeof(struct pvclock_vcpu_time_info))) 2550 vcpu->arch.pv_time_enabled = false; 2551 else 2552 vcpu->arch.pv_time_enabled = true; 2553 2554 break; 2555 } 2556 case MSR_KVM_ASYNC_PF_EN: 2557 if (kvm_pv_enable_async_pf(vcpu, data)) 2558 return 1; 2559 break; 2560 case MSR_KVM_STEAL_TIME: 2561 2562 if (unlikely(!sched_info_on())) 2563 return 1; 2564 2565 if (data & KVM_STEAL_RESERVED_MASK) 2566 return 1; 2567 2568 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2569 data & KVM_STEAL_VALID_BITS, 2570 sizeof(struct kvm_steal_time))) 2571 return 1; 2572 2573 vcpu->arch.st.msr_val = data; 2574 2575 if (!(data & KVM_MSR_ENABLED)) 2576 break; 2577 2578 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2579 2580 break; 2581 case MSR_KVM_PV_EOI_EN: 2582 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) 2583 return 1; 2584 break; 2585 2586 case MSR_IA32_MCG_CTL: 2587 case MSR_IA32_MCG_STATUS: 2588 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2589 return set_msr_mce(vcpu, msr_info); 2590 2591 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2592 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2593 pr = true; /* fall through */ 2594 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2595 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2596 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2597 return kvm_pmu_set_msr(vcpu, msr_info); 2598 2599 if (pr || data != 0) 2600 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2601 "0x%x data 0x%llx\n", msr, data); 2602 break; 2603 case MSR_K7_CLK_CTL: 2604 /* 2605 * Ignore all writes to this no longer documented MSR. 2606 * Writes are only relevant for old K7 processors, 2607 * all pre-dating SVM, but a recommended workaround from 2608 * AMD for these chips. It is possible to specify the 2609 * affected processor models on the command line, hence 2610 * the need to ignore the workaround. 2611 */ 2612 break; 2613 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2614 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2615 case HV_X64_MSR_CRASH_CTL: 2616 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2617 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 2618 case HV_X64_MSR_TSC_EMULATION_CONTROL: 2619 case HV_X64_MSR_TSC_EMULATION_STATUS: 2620 return kvm_hv_set_msr_common(vcpu, msr, data, 2621 msr_info->host_initiated); 2622 case MSR_IA32_BBL_CR_CTL3: 2623 /* Drop writes to this legacy MSR -- see rdmsr 2624 * counterpart for further detail. 2625 */ 2626 if (report_ignored_msrs) 2627 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 2628 msr, data); 2629 break; 2630 case MSR_AMD64_OSVW_ID_LENGTH: 2631 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2632 return 1; 2633 vcpu->arch.osvw.length = data; 2634 break; 2635 case MSR_AMD64_OSVW_STATUS: 2636 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2637 return 1; 2638 vcpu->arch.osvw.status = data; 2639 break; 2640 case MSR_PLATFORM_INFO: 2641 if (!msr_info->host_initiated || 2642 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 2643 cpuid_fault_enabled(vcpu))) 2644 return 1; 2645 vcpu->arch.msr_platform_info = data; 2646 break; 2647 case MSR_MISC_FEATURES_ENABLES: 2648 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 2649 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 2650 !supports_cpuid_fault(vcpu))) 2651 return 1; 2652 vcpu->arch.msr_misc_features_enables = data; 2653 break; 2654 default: 2655 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2656 return xen_hvm_config(vcpu, data); 2657 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2658 return kvm_pmu_set_msr(vcpu, msr_info); 2659 if (!ignore_msrs) { 2660 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n", 2661 msr, data); 2662 return 1; 2663 } else { 2664 if (report_ignored_msrs) 2665 vcpu_unimpl(vcpu, 2666 "ignored wrmsr: 0x%x data 0x%llx\n", 2667 msr, data); 2668 break; 2669 } 2670 } 2671 return 0; 2672 } 2673 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2674 2675 2676 /* 2677 * Reads an msr value (of 'msr_index') into 'pdata'. 2678 * Returns 0 on success, non-0 otherwise. 2679 * Assumes vcpu_load() was already called. 2680 */ 2681 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 2682 { 2683 return kvm_x86_ops->get_msr(vcpu, msr); 2684 } 2685 EXPORT_SYMBOL_GPL(kvm_get_msr); 2686 2687 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 2688 { 2689 u64 data; 2690 u64 mcg_cap = vcpu->arch.mcg_cap; 2691 unsigned bank_num = mcg_cap & 0xff; 2692 2693 switch (msr) { 2694 case MSR_IA32_P5_MC_ADDR: 2695 case MSR_IA32_P5_MC_TYPE: 2696 data = 0; 2697 break; 2698 case MSR_IA32_MCG_CAP: 2699 data = vcpu->arch.mcg_cap; 2700 break; 2701 case MSR_IA32_MCG_CTL: 2702 if (!(mcg_cap & MCG_CTL_P) && !host) 2703 return 1; 2704 data = vcpu->arch.mcg_ctl; 2705 break; 2706 case MSR_IA32_MCG_STATUS: 2707 data = vcpu->arch.mcg_status; 2708 break; 2709 default: 2710 if (msr >= MSR_IA32_MC0_CTL && 2711 msr < MSR_IA32_MCx_CTL(bank_num)) { 2712 u32 offset = msr - MSR_IA32_MC0_CTL; 2713 data = vcpu->arch.mce_banks[offset]; 2714 break; 2715 } 2716 return 1; 2717 } 2718 *pdata = data; 2719 return 0; 2720 } 2721 2722 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2723 { 2724 switch (msr_info->index) { 2725 case MSR_IA32_PLATFORM_ID: 2726 case MSR_IA32_EBL_CR_POWERON: 2727 case MSR_IA32_DEBUGCTLMSR: 2728 case MSR_IA32_LASTBRANCHFROMIP: 2729 case MSR_IA32_LASTBRANCHTOIP: 2730 case MSR_IA32_LASTINTFROMIP: 2731 case MSR_IA32_LASTINTTOIP: 2732 case MSR_K8_SYSCFG: 2733 case MSR_K8_TSEG_ADDR: 2734 case MSR_K8_TSEG_MASK: 2735 case MSR_K7_HWCR: 2736 case MSR_VM_HSAVE_PA: 2737 case MSR_K8_INT_PENDING_MSG: 2738 case MSR_AMD64_NB_CFG: 2739 case MSR_FAM10H_MMIO_CONF_BASE: 2740 case MSR_AMD64_BU_CFG2: 2741 case MSR_IA32_PERF_CTL: 2742 case MSR_AMD64_DC_CFG: 2743 case MSR_F15H_EX_CFG: 2744 msr_info->data = 0; 2745 break; 2746 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 2747 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2748 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2749 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2750 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2751 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2752 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2753 msr_info->data = 0; 2754 break; 2755 case MSR_IA32_UCODE_REV: 2756 msr_info->data = vcpu->arch.microcode_version; 2757 break; 2758 case MSR_IA32_ARCH_CAPABILITIES: 2759 if (!msr_info->host_initiated && 2760 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 2761 return 1; 2762 msr_info->data = vcpu->arch.arch_capabilities; 2763 break; 2764 case MSR_IA32_TSC: 2765 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset; 2766 break; 2767 case MSR_MTRRcap: 2768 case 0x200 ... 0x2ff: 2769 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 2770 case 0xcd: /* fsb frequency */ 2771 msr_info->data = 3; 2772 break; 2773 /* 2774 * MSR_EBC_FREQUENCY_ID 2775 * Conservative value valid for even the basic CPU models. 2776 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2777 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2778 * and 266MHz for model 3, or 4. Set Core Clock 2779 * Frequency to System Bus Frequency Ratio to 1 (bits 2780 * 31:24) even though these are only valid for CPU 2781 * models > 2, however guests may end up dividing or 2782 * multiplying by zero otherwise. 2783 */ 2784 case MSR_EBC_FREQUENCY_ID: 2785 msr_info->data = 1 << 24; 2786 break; 2787 case MSR_IA32_APICBASE: 2788 msr_info->data = kvm_get_apic_base(vcpu); 2789 break; 2790 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2791 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 2792 break; 2793 case MSR_IA32_TSCDEADLINE: 2794 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 2795 break; 2796 case MSR_IA32_TSC_ADJUST: 2797 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2798 break; 2799 case MSR_IA32_MISC_ENABLE: 2800 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 2801 break; 2802 case MSR_IA32_SMBASE: 2803 if (!msr_info->host_initiated) 2804 return 1; 2805 msr_info->data = vcpu->arch.smbase; 2806 break; 2807 case MSR_SMI_COUNT: 2808 msr_info->data = vcpu->arch.smi_count; 2809 break; 2810 case MSR_IA32_PERF_STATUS: 2811 /* TSC increment by tick */ 2812 msr_info->data = 1000ULL; 2813 /* CPU multiplier */ 2814 msr_info->data |= (((uint64_t)4ULL) << 40); 2815 break; 2816 case MSR_EFER: 2817 msr_info->data = vcpu->arch.efer; 2818 break; 2819 case MSR_KVM_WALL_CLOCK: 2820 case MSR_KVM_WALL_CLOCK_NEW: 2821 msr_info->data = vcpu->kvm->arch.wall_clock; 2822 break; 2823 case MSR_KVM_SYSTEM_TIME: 2824 case MSR_KVM_SYSTEM_TIME_NEW: 2825 msr_info->data = vcpu->arch.time; 2826 break; 2827 case MSR_KVM_ASYNC_PF_EN: 2828 msr_info->data = vcpu->arch.apf.msr_val; 2829 break; 2830 case MSR_KVM_STEAL_TIME: 2831 msr_info->data = vcpu->arch.st.msr_val; 2832 break; 2833 case MSR_KVM_PV_EOI_EN: 2834 msr_info->data = vcpu->arch.pv_eoi.msr_val; 2835 break; 2836 case MSR_IA32_P5_MC_ADDR: 2837 case MSR_IA32_P5_MC_TYPE: 2838 case MSR_IA32_MCG_CAP: 2839 case MSR_IA32_MCG_CTL: 2840 case MSR_IA32_MCG_STATUS: 2841 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2842 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 2843 msr_info->host_initiated); 2844 case MSR_K7_CLK_CTL: 2845 /* 2846 * Provide expected ramp-up count for K7. All other 2847 * are set to zero, indicating minimum divisors for 2848 * every field. 2849 * 2850 * This prevents guest kernels on AMD host with CPU 2851 * type 6, model 8 and higher from exploding due to 2852 * the rdmsr failing. 2853 */ 2854 msr_info->data = 0x20000000; 2855 break; 2856 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2857 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2858 case HV_X64_MSR_CRASH_CTL: 2859 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2860 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 2861 case HV_X64_MSR_TSC_EMULATION_CONTROL: 2862 case HV_X64_MSR_TSC_EMULATION_STATUS: 2863 return kvm_hv_get_msr_common(vcpu, 2864 msr_info->index, &msr_info->data, 2865 msr_info->host_initiated); 2866 break; 2867 case MSR_IA32_BBL_CR_CTL3: 2868 /* This legacy MSR exists but isn't fully documented in current 2869 * silicon. It is however accessed by winxp in very narrow 2870 * scenarios where it sets bit #19, itself documented as 2871 * a "reserved" bit. Best effort attempt to source coherent 2872 * read data here should the balance of the register be 2873 * interpreted by the guest: 2874 * 2875 * L2 cache control register 3: 64GB range, 256KB size, 2876 * enabled, latency 0x1, configured 2877 */ 2878 msr_info->data = 0xbe702111; 2879 break; 2880 case MSR_AMD64_OSVW_ID_LENGTH: 2881 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2882 return 1; 2883 msr_info->data = vcpu->arch.osvw.length; 2884 break; 2885 case MSR_AMD64_OSVW_STATUS: 2886 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2887 return 1; 2888 msr_info->data = vcpu->arch.osvw.status; 2889 break; 2890 case MSR_PLATFORM_INFO: 2891 if (!msr_info->host_initiated && 2892 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 2893 return 1; 2894 msr_info->data = vcpu->arch.msr_platform_info; 2895 break; 2896 case MSR_MISC_FEATURES_ENABLES: 2897 msr_info->data = vcpu->arch.msr_misc_features_enables; 2898 break; 2899 default: 2900 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2901 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2902 if (!ignore_msrs) { 2903 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n", 2904 msr_info->index); 2905 return 1; 2906 } else { 2907 if (report_ignored_msrs) 2908 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", 2909 msr_info->index); 2910 msr_info->data = 0; 2911 } 2912 break; 2913 } 2914 return 0; 2915 } 2916 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2917 2918 /* 2919 * Read or write a bunch of msrs. All parameters are kernel addresses. 2920 * 2921 * @return number of msrs set successfully. 2922 */ 2923 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2924 struct kvm_msr_entry *entries, 2925 int (*do_msr)(struct kvm_vcpu *vcpu, 2926 unsigned index, u64 *data)) 2927 { 2928 int i; 2929 2930 for (i = 0; i < msrs->nmsrs; ++i) 2931 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2932 break; 2933 2934 return i; 2935 } 2936 2937 /* 2938 * Read or write a bunch of msrs. Parameters are user addresses. 2939 * 2940 * @return number of msrs set successfully. 2941 */ 2942 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2943 int (*do_msr)(struct kvm_vcpu *vcpu, 2944 unsigned index, u64 *data), 2945 int writeback) 2946 { 2947 struct kvm_msrs msrs; 2948 struct kvm_msr_entry *entries; 2949 int r, n; 2950 unsigned size; 2951 2952 r = -EFAULT; 2953 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 2954 goto out; 2955 2956 r = -E2BIG; 2957 if (msrs.nmsrs >= MAX_IO_MSRS) 2958 goto out; 2959 2960 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2961 entries = memdup_user(user_msrs->entries, size); 2962 if (IS_ERR(entries)) { 2963 r = PTR_ERR(entries); 2964 goto out; 2965 } 2966 2967 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2968 if (r < 0) 2969 goto out_free; 2970 2971 r = -EFAULT; 2972 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2973 goto out_free; 2974 2975 r = n; 2976 2977 out_free: 2978 kfree(entries); 2979 out: 2980 return r; 2981 } 2982 2983 static inline bool kvm_can_mwait_in_guest(void) 2984 { 2985 return boot_cpu_has(X86_FEATURE_MWAIT) && 2986 !boot_cpu_has_bug(X86_BUG_MONITOR) && 2987 boot_cpu_has(X86_FEATURE_ARAT); 2988 } 2989 2990 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2991 { 2992 int r = 0; 2993 2994 switch (ext) { 2995 case KVM_CAP_IRQCHIP: 2996 case KVM_CAP_HLT: 2997 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2998 case KVM_CAP_SET_TSS_ADDR: 2999 case KVM_CAP_EXT_CPUID: 3000 case KVM_CAP_EXT_EMUL_CPUID: 3001 case KVM_CAP_CLOCKSOURCE: 3002 case KVM_CAP_PIT: 3003 case KVM_CAP_NOP_IO_DELAY: 3004 case KVM_CAP_MP_STATE: 3005 case KVM_CAP_SYNC_MMU: 3006 case KVM_CAP_USER_NMI: 3007 case KVM_CAP_REINJECT_CONTROL: 3008 case KVM_CAP_IRQ_INJECT_STATUS: 3009 case KVM_CAP_IOEVENTFD: 3010 case KVM_CAP_IOEVENTFD_NO_LENGTH: 3011 case KVM_CAP_PIT2: 3012 case KVM_CAP_PIT_STATE2: 3013 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 3014 case KVM_CAP_XEN_HVM: 3015 case KVM_CAP_VCPU_EVENTS: 3016 case KVM_CAP_HYPERV: 3017 case KVM_CAP_HYPERV_VAPIC: 3018 case KVM_CAP_HYPERV_SPIN: 3019 case KVM_CAP_HYPERV_SYNIC: 3020 case KVM_CAP_HYPERV_SYNIC2: 3021 case KVM_CAP_HYPERV_VP_INDEX: 3022 case KVM_CAP_HYPERV_EVENTFD: 3023 case KVM_CAP_HYPERV_TLBFLUSH: 3024 case KVM_CAP_HYPERV_SEND_IPI: 3025 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 3026 case KVM_CAP_HYPERV_CPUID: 3027 case KVM_CAP_PCI_SEGMENT: 3028 case KVM_CAP_DEBUGREGS: 3029 case KVM_CAP_X86_ROBUST_SINGLESTEP: 3030 case KVM_CAP_XSAVE: 3031 case KVM_CAP_ASYNC_PF: 3032 case KVM_CAP_GET_TSC_KHZ: 3033 case KVM_CAP_KVMCLOCK_CTRL: 3034 case KVM_CAP_READONLY_MEM: 3035 case KVM_CAP_HYPERV_TIME: 3036 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 3037 case KVM_CAP_TSC_DEADLINE_TIMER: 3038 case KVM_CAP_DISABLE_QUIRKS: 3039 case KVM_CAP_SET_BOOT_CPU_ID: 3040 case KVM_CAP_SPLIT_IRQCHIP: 3041 case KVM_CAP_IMMEDIATE_EXIT: 3042 case KVM_CAP_GET_MSR_FEATURES: 3043 case KVM_CAP_MSR_PLATFORM_INFO: 3044 case KVM_CAP_EXCEPTION_PAYLOAD: 3045 r = 1; 3046 break; 3047 case KVM_CAP_SYNC_REGS: 3048 r = KVM_SYNC_X86_VALID_FIELDS; 3049 break; 3050 case KVM_CAP_ADJUST_CLOCK: 3051 r = KVM_CLOCK_TSC_STABLE; 3052 break; 3053 case KVM_CAP_X86_DISABLE_EXITS: 3054 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE; 3055 if(kvm_can_mwait_in_guest()) 3056 r |= KVM_X86_DISABLE_EXITS_MWAIT; 3057 break; 3058 case KVM_CAP_X86_SMM: 3059 /* SMBASE is usually relocated above 1M on modern chipsets, 3060 * and SMM handlers might indeed rely on 4G segment limits, 3061 * so do not report SMM to be available if real mode is 3062 * emulated via vm86 mode. Still, do not go to great lengths 3063 * to avoid userspace's usage of the feature, because it is a 3064 * fringe case that is not enabled except via specific settings 3065 * of the module parameters. 3066 */ 3067 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE); 3068 break; 3069 case KVM_CAP_VAPIC: 3070 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 3071 break; 3072 case KVM_CAP_NR_VCPUS: 3073 r = KVM_SOFT_MAX_VCPUS; 3074 break; 3075 case KVM_CAP_MAX_VCPUS: 3076 r = KVM_MAX_VCPUS; 3077 break; 3078 case KVM_CAP_NR_MEMSLOTS: 3079 r = KVM_USER_MEM_SLOTS; 3080 break; 3081 case KVM_CAP_PV_MMU: /* obsolete */ 3082 r = 0; 3083 break; 3084 case KVM_CAP_MCE: 3085 r = KVM_MAX_MCE_BANKS; 3086 break; 3087 case KVM_CAP_XCRS: 3088 r = boot_cpu_has(X86_FEATURE_XSAVE); 3089 break; 3090 case KVM_CAP_TSC_CONTROL: 3091 r = kvm_has_tsc_control; 3092 break; 3093 case KVM_CAP_X2APIC_API: 3094 r = KVM_X2APIC_API_VALID_FLAGS; 3095 break; 3096 case KVM_CAP_NESTED_STATE: 3097 r = kvm_x86_ops->get_nested_state ? 3098 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0; 3099 break; 3100 default: 3101 break; 3102 } 3103 return r; 3104 3105 } 3106 3107 long kvm_arch_dev_ioctl(struct file *filp, 3108 unsigned int ioctl, unsigned long arg) 3109 { 3110 void __user *argp = (void __user *)arg; 3111 long r; 3112 3113 switch (ioctl) { 3114 case KVM_GET_MSR_INDEX_LIST: { 3115 struct kvm_msr_list __user *user_msr_list = argp; 3116 struct kvm_msr_list msr_list; 3117 unsigned n; 3118 3119 r = -EFAULT; 3120 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3121 goto out; 3122 n = msr_list.nmsrs; 3123 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 3124 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3125 goto out; 3126 r = -E2BIG; 3127 if (n < msr_list.nmsrs) 3128 goto out; 3129 r = -EFAULT; 3130 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 3131 num_msrs_to_save * sizeof(u32))) 3132 goto out; 3133 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 3134 &emulated_msrs, 3135 num_emulated_msrs * sizeof(u32))) 3136 goto out; 3137 r = 0; 3138 break; 3139 } 3140 case KVM_GET_SUPPORTED_CPUID: 3141 case KVM_GET_EMULATED_CPUID: { 3142 struct kvm_cpuid2 __user *cpuid_arg = argp; 3143 struct kvm_cpuid2 cpuid; 3144 3145 r = -EFAULT; 3146 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3147 goto out; 3148 3149 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 3150 ioctl); 3151 if (r) 3152 goto out; 3153 3154 r = -EFAULT; 3155 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 3156 goto out; 3157 r = 0; 3158 break; 3159 } 3160 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 3161 r = -EFAULT; 3162 if (copy_to_user(argp, &kvm_mce_cap_supported, 3163 sizeof(kvm_mce_cap_supported))) 3164 goto out; 3165 r = 0; 3166 break; 3167 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 3168 struct kvm_msr_list __user *user_msr_list = argp; 3169 struct kvm_msr_list msr_list; 3170 unsigned int n; 3171 3172 r = -EFAULT; 3173 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3174 goto out; 3175 n = msr_list.nmsrs; 3176 msr_list.nmsrs = num_msr_based_features; 3177 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3178 goto out; 3179 r = -E2BIG; 3180 if (n < msr_list.nmsrs) 3181 goto out; 3182 r = -EFAULT; 3183 if (copy_to_user(user_msr_list->indices, &msr_based_features, 3184 num_msr_based_features * sizeof(u32))) 3185 goto out; 3186 r = 0; 3187 break; 3188 } 3189 case KVM_GET_MSRS: 3190 r = msr_io(NULL, argp, do_get_msr_feature, 1); 3191 break; 3192 } 3193 default: 3194 r = -EINVAL; 3195 } 3196 out: 3197 return r; 3198 } 3199 3200 static void wbinvd_ipi(void *garbage) 3201 { 3202 wbinvd(); 3203 } 3204 3205 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 3206 { 3207 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 3208 } 3209 3210 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 3211 { 3212 /* Address WBINVD may be executed by guest */ 3213 if (need_emulate_wbinvd(vcpu)) { 3214 if (kvm_x86_ops->has_wbinvd_exit()) 3215 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 3216 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 3217 smp_call_function_single(vcpu->cpu, 3218 wbinvd_ipi, NULL, 1); 3219 } 3220 3221 kvm_x86_ops->vcpu_load(vcpu, cpu); 3222 3223 /* Apply any externally detected TSC adjustments (due to suspend) */ 3224 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 3225 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 3226 vcpu->arch.tsc_offset_adjustment = 0; 3227 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3228 } 3229 3230 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 3231 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 3232 rdtsc() - vcpu->arch.last_host_tsc; 3233 if (tsc_delta < 0) 3234 mark_tsc_unstable("KVM discovered backwards TSC"); 3235 3236 if (kvm_check_tsc_unstable()) { 3237 u64 offset = kvm_compute_tsc_offset(vcpu, 3238 vcpu->arch.last_guest_tsc); 3239 kvm_vcpu_write_tsc_offset(vcpu, offset); 3240 vcpu->arch.tsc_catchup = 1; 3241 } 3242 3243 if (kvm_lapic_hv_timer_in_use(vcpu)) 3244 kvm_lapic_restart_hv_timer(vcpu); 3245 3246 /* 3247 * On a host with synchronized TSC, there is no need to update 3248 * kvmclock on vcpu->cpu migration 3249 */ 3250 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 3251 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 3252 if (vcpu->cpu != cpu) 3253 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 3254 vcpu->cpu = cpu; 3255 } 3256 3257 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3258 } 3259 3260 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 3261 { 3262 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3263 return; 3264 3265 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED; 3266 3267 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime, 3268 &vcpu->arch.st.steal.preempted, 3269 offsetof(struct kvm_steal_time, preempted), 3270 sizeof(vcpu->arch.st.steal.preempted)); 3271 } 3272 3273 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 3274 { 3275 int idx; 3276 3277 if (vcpu->preempted) 3278 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu); 3279 3280 /* 3281 * Disable page faults because we're in atomic context here. 3282 * kvm_write_guest_offset_cached() would call might_fault() 3283 * that relies on pagefault_disable() to tell if there's a 3284 * bug. NOTE: the write to guest memory may not go through if 3285 * during postcopy live migration or if there's heavy guest 3286 * paging. 3287 */ 3288 pagefault_disable(); 3289 /* 3290 * kvm_memslots() will be called by 3291 * kvm_write_guest_offset_cached() so take the srcu lock. 3292 */ 3293 idx = srcu_read_lock(&vcpu->kvm->srcu); 3294 kvm_steal_time_set_preempted(vcpu); 3295 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3296 pagefault_enable(); 3297 kvm_x86_ops->vcpu_put(vcpu); 3298 vcpu->arch.last_host_tsc = rdtsc(); 3299 /* 3300 * If userspace has set any breakpoints or watchpoints, dr6 is restored 3301 * on every vmexit, but if not, we might have a stale dr6 from the 3302 * guest. do_debug expects dr6 to be cleared after it runs, do the same. 3303 */ 3304 set_debugreg(0, 6); 3305 } 3306 3307 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 3308 struct kvm_lapic_state *s) 3309 { 3310 if (vcpu->arch.apicv_active) 3311 kvm_x86_ops->sync_pir_to_irr(vcpu); 3312 3313 return kvm_apic_get_state(vcpu, s); 3314 } 3315 3316 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 3317 struct kvm_lapic_state *s) 3318 { 3319 int r; 3320 3321 r = kvm_apic_set_state(vcpu, s); 3322 if (r) 3323 return r; 3324 update_cr8_intercept(vcpu); 3325 3326 return 0; 3327 } 3328 3329 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 3330 { 3331 return (!lapic_in_kernel(vcpu) || 3332 kvm_apic_accept_pic_intr(vcpu)); 3333 } 3334 3335 /* 3336 * if userspace requested an interrupt window, check that the 3337 * interrupt window is open. 3338 * 3339 * No need to exit to userspace if we already have an interrupt queued. 3340 */ 3341 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 3342 { 3343 return kvm_arch_interrupt_allowed(vcpu) && 3344 !kvm_cpu_has_interrupt(vcpu) && 3345 !kvm_event_needs_reinjection(vcpu) && 3346 kvm_cpu_accept_dm_intr(vcpu); 3347 } 3348 3349 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 3350 struct kvm_interrupt *irq) 3351 { 3352 if (irq->irq >= KVM_NR_INTERRUPTS) 3353 return -EINVAL; 3354 3355 if (!irqchip_in_kernel(vcpu->kvm)) { 3356 kvm_queue_interrupt(vcpu, irq->irq, false); 3357 kvm_make_request(KVM_REQ_EVENT, vcpu); 3358 return 0; 3359 } 3360 3361 /* 3362 * With in-kernel LAPIC, we only use this to inject EXTINT, so 3363 * fail for in-kernel 8259. 3364 */ 3365 if (pic_in_kernel(vcpu->kvm)) 3366 return -ENXIO; 3367 3368 if (vcpu->arch.pending_external_vector != -1) 3369 return -EEXIST; 3370 3371 vcpu->arch.pending_external_vector = irq->irq; 3372 kvm_make_request(KVM_REQ_EVENT, vcpu); 3373 return 0; 3374 } 3375 3376 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 3377 { 3378 kvm_inject_nmi(vcpu); 3379 3380 return 0; 3381 } 3382 3383 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 3384 { 3385 kvm_make_request(KVM_REQ_SMI, vcpu); 3386 3387 return 0; 3388 } 3389 3390 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 3391 struct kvm_tpr_access_ctl *tac) 3392 { 3393 if (tac->flags) 3394 return -EINVAL; 3395 vcpu->arch.tpr_access_reporting = !!tac->enabled; 3396 return 0; 3397 } 3398 3399 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 3400 u64 mcg_cap) 3401 { 3402 int r; 3403 unsigned bank_num = mcg_cap & 0xff, bank; 3404 3405 r = -EINVAL; 3406 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 3407 goto out; 3408 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 3409 goto out; 3410 r = 0; 3411 vcpu->arch.mcg_cap = mcg_cap; 3412 /* Init IA32_MCG_CTL to all 1s */ 3413 if (mcg_cap & MCG_CTL_P) 3414 vcpu->arch.mcg_ctl = ~(u64)0; 3415 /* Init IA32_MCi_CTL to all 1s */ 3416 for (bank = 0; bank < bank_num; bank++) 3417 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 3418 3419 if (kvm_x86_ops->setup_mce) 3420 kvm_x86_ops->setup_mce(vcpu); 3421 out: 3422 return r; 3423 } 3424 3425 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 3426 struct kvm_x86_mce *mce) 3427 { 3428 u64 mcg_cap = vcpu->arch.mcg_cap; 3429 unsigned bank_num = mcg_cap & 0xff; 3430 u64 *banks = vcpu->arch.mce_banks; 3431 3432 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 3433 return -EINVAL; 3434 /* 3435 * if IA32_MCG_CTL is not all 1s, the uncorrected error 3436 * reporting is disabled 3437 */ 3438 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 3439 vcpu->arch.mcg_ctl != ~(u64)0) 3440 return 0; 3441 banks += 4 * mce->bank; 3442 /* 3443 * if IA32_MCi_CTL is not all 1s, the uncorrected error 3444 * reporting is disabled for the bank 3445 */ 3446 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 3447 return 0; 3448 if (mce->status & MCI_STATUS_UC) { 3449 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 3450 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 3451 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 3452 return 0; 3453 } 3454 if (banks[1] & MCI_STATUS_VAL) 3455 mce->status |= MCI_STATUS_OVER; 3456 banks[2] = mce->addr; 3457 banks[3] = mce->misc; 3458 vcpu->arch.mcg_status = mce->mcg_status; 3459 banks[1] = mce->status; 3460 kvm_queue_exception(vcpu, MC_VECTOR); 3461 } else if (!(banks[1] & MCI_STATUS_VAL) 3462 || !(banks[1] & MCI_STATUS_UC)) { 3463 if (banks[1] & MCI_STATUS_VAL) 3464 mce->status |= MCI_STATUS_OVER; 3465 banks[2] = mce->addr; 3466 banks[3] = mce->misc; 3467 banks[1] = mce->status; 3468 } else 3469 banks[1] |= MCI_STATUS_OVER; 3470 return 0; 3471 } 3472 3473 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 3474 struct kvm_vcpu_events *events) 3475 { 3476 process_nmi(vcpu); 3477 3478 /* 3479 * The API doesn't provide the instruction length for software 3480 * exceptions, so don't report them. As long as the guest RIP 3481 * isn't advanced, we should expect to encounter the exception 3482 * again. 3483 */ 3484 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 3485 events->exception.injected = 0; 3486 events->exception.pending = 0; 3487 } else { 3488 events->exception.injected = vcpu->arch.exception.injected; 3489 events->exception.pending = vcpu->arch.exception.pending; 3490 /* 3491 * For ABI compatibility, deliberately conflate 3492 * pending and injected exceptions when 3493 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 3494 */ 3495 if (!vcpu->kvm->arch.exception_payload_enabled) 3496 events->exception.injected |= 3497 vcpu->arch.exception.pending; 3498 } 3499 events->exception.nr = vcpu->arch.exception.nr; 3500 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 3501 events->exception.error_code = vcpu->arch.exception.error_code; 3502 events->exception_has_payload = vcpu->arch.exception.has_payload; 3503 events->exception_payload = vcpu->arch.exception.payload; 3504 3505 events->interrupt.injected = 3506 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 3507 events->interrupt.nr = vcpu->arch.interrupt.nr; 3508 events->interrupt.soft = 0; 3509 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 3510 3511 events->nmi.injected = vcpu->arch.nmi_injected; 3512 events->nmi.pending = vcpu->arch.nmi_pending != 0; 3513 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 3514 events->nmi.pad = 0; 3515 3516 events->sipi_vector = 0; /* never valid when reporting to user space */ 3517 3518 events->smi.smm = is_smm(vcpu); 3519 events->smi.pending = vcpu->arch.smi_pending; 3520 events->smi.smm_inside_nmi = 3521 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 3522 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 3523 3524 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 3525 | KVM_VCPUEVENT_VALID_SHADOW 3526 | KVM_VCPUEVENT_VALID_SMM); 3527 if (vcpu->kvm->arch.exception_payload_enabled) 3528 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 3529 3530 memset(&events->reserved, 0, sizeof(events->reserved)); 3531 } 3532 3533 static void kvm_smm_changed(struct kvm_vcpu *vcpu); 3534 3535 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 3536 struct kvm_vcpu_events *events) 3537 { 3538 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 3539 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 3540 | KVM_VCPUEVENT_VALID_SHADOW 3541 | KVM_VCPUEVENT_VALID_SMM 3542 | KVM_VCPUEVENT_VALID_PAYLOAD)) 3543 return -EINVAL; 3544 3545 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 3546 if (!vcpu->kvm->arch.exception_payload_enabled) 3547 return -EINVAL; 3548 if (events->exception.pending) 3549 events->exception.injected = 0; 3550 else 3551 events->exception_has_payload = 0; 3552 } else { 3553 events->exception.pending = 0; 3554 events->exception_has_payload = 0; 3555 } 3556 3557 if ((events->exception.injected || events->exception.pending) && 3558 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 3559 return -EINVAL; 3560 3561 /* INITs are latched while in SMM */ 3562 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 3563 (events->smi.smm || events->smi.pending) && 3564 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 3565 return -EINVAL; 3566 3567 process_nmi(vcpu); 3568 vcpu->arch.exception.injected = events->exception.injected; 3569 vcpu->arch.exception.pending = events->exception.pending; 3570 vcpu->arch.exception.nr = events->exception.nr; 3571 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 3572 vcpu->arch.exception.error_code = events->exception.error_code; 3573 vcpu->arch.exception.has_payload = events->exception_has_payload; 3574 vcpu->arch.exception.payload = events->exception_payload; 3575 3576 vcpu->arch.interrupt.injected = events->interrupt.injected; 3577 vcpu->arch.interrupt.nr = events->interrupt.nr; 3578 vcpu->arch.interrupt.soft = events->interrupt.soft; 3579 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3580 kvm_x86_ops->set_interrupt_shadow(vcpu, 3581 events->interrupt.shadow); 3582 3583 vcpu->arch.nmi_injected = events->nmi.injected; 3584 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3585 vcpu->arch.nmi_pending = events->nmi.pending; 3586 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 3587 3588 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3589 lapic_in_kernel(vcpu)) 3590 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3591 3592 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 3593 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { 3594 if (events->smi.smm) 3595 vcpu->arch.hflags |= HF_SMM_MASK; 3596 else 3597 vcpu->arch.hflags &= ~HF_SMM_MASK; 3598 kvm_smm_changed(vcpu); 3599 } 3600 3601 vcpu->arch.smi_pending = events->smi.pending; 3602 3603 if (events->smi.smm) { 3604 if (events->smi.smm_inside_nmi) 3605 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 3606 else 3607 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 3608 if (lapic_in_kernel(vcpu)) { 3609 if (events->smi.latched_init) 3610 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3611 else 3612 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3613 } 3614 } 3615 } 3616 3617 kvm_make_request(KVM_REQ_EVENT, vcpu); 3618 3619 return 0; 3620 } 3621 3622 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3623 struct kvm_debugregs *dbgregs) 3624 { 3625 unsigned long val; 3626 3627 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3628 kvm_get_dr(vcpu, 6, &val); 3629 dbgregs->dr6 = val; 3630 dbgregs->dr7 = vcpu->arch.dr7; 3631 dbgregs->flags = 0; 3632 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3633 } 3634 3635 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3636 struct kvm_debugregs *dbgregs) 3637 { 3638 if (dbgregs->flags) 3639 return -EINVAL; 3640 3641 if (dbgregs->dr6 & ~0xffffffffull) 3642 return -EINVAL; 3643 if (dbgregs->dr7 & ~0xffffffffull) 3644 return -EINVAL; 3645 3646 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3647 kvm_update_dr0123(vcpu); 3648 vcpu->arch.dr6 = dbgregs->dr6; 3649 kvm_update_dr6(vcpu); 3650 vcpu->arch.dr7 = dbgregs->dr7; 3651 kvm_update_dr7(vcpu); 3652 3653 return 0; 3654 } 3655 3656 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3657 3658 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3659 { 3660 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 3661 u64 xstate_bv = xsave->header.xfeatures; 3662 u64 valid; 3663 3664 /* 3665 * Copy legacy XSAVE area, to avoid complications with CPUID 3666 * leaves 0 and 1 in the loop below. 3667 */ 3668 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3669 3670 /* Set XSTATE_BV */ 3671 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; 3672 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3673 3674 /* 3675 * Copy each region from the possibly compacted offset to the 3676 * non-compacted offset. 3677 */ 3678 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3679 while (valid) { 3680 u64 feature = valid & -valid; 3681 int index = fls64(feature) - 1; 3682 void *src = get_xsave_addr(xsave, feature); 3683 3684 if (src) { 3685 u32 size, offset, ecx, edx; 3686 cpuid_count(XSTATE_CPUID, index, 3687 &size, &offset, &ecx, &edx); 3688 if (feature == XFEATURE_MASK_PKRU) 3689 memcpy(dest + offset, &vcpu->arch.pkru, 3690 sizeof(vcpu->arch.pkru)); 3691 else 3692 memcpy(dest + offset, src, size); 3693 3694 } 3695 3696 valid -= feature; 3697 } 3698 } 3699 3700 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3701 { 3702 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 3703 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3704 u64 valid; 3705 3706 /* 3707 * Copy legacy XSAVE area, to avoid complications with CPUID 3708 * leaves 0 and 1 in the loop below. 3709 */ 3710 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3711 3712 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3713 xsave->header.xfeatures = xstate_bv; 3714 if (boot_cpu_has(X86_FEATURE_XSAVES)) 3715 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3716 3717 /* 3718 * Copy each region from the non-compacted offset to the 3719 * possibly compacted offset. 3720 */ 3721 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3722 while (valid) { 3723 u64 feature = valid & -valid; 3724 int index = fls64(feature) - 1; 3725 void *dest = get_xsave_addr(xsave, feature); 3726 3727 if (dest) { 3728 u32 size, offset, ecx, edx; 3729 cpuid_count(XSTATE_CPUID, index, 3730 &size, &offset, &ecx, &edx); 3731 if (feature == XFEATURE_MASK_PKRU) 3732 memcpy(&vcpu->arch.pkru, src + offset, 3733 sizeof(vcpu->arch.pkru)); 3734 else 3735 memcpy(dest, src + offset, size); 3736 } 3737 3738 valid -= feature; 3739 } 3740 } 3741 3742 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3743 struct kvm_xsave *guest_xsave) 3744 { 3745 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3746 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3747 fill_xsave((u8 *) guest_xsave->region, vcpu); 3748 } else { 3749 memcpy(guest_xsave->region, 3750 &vcpu->arch.guest_fpu->state.fxsave, 3751 sizeof(struct fxregs_state)); 3752 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3753 XFEATURE_MASK_FPSSE; 3754 } 3755 } 3756 3757 #define XSAVE_MXCSR_OFFSET 24 3758 3759 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3760 struct kvm_xsave *guest_xsave) 3761 { 3762 u64 xstate_bv = 3763 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3764 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; 3765 3766 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3767 /* 3768 * Here we allow setting states that are not present in 3769 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3770 * with old userspace. 3771 */ 3772 if (xstate_bv & ~kvm_supported_xcr0() || 3773 mxcsr & ~mxcsr_feature_mask) 3774 return -EINVAL; 3775 load_xsave(vcpu, (u8 *)guest_xsave->region); 3776 } else { 3777 if (xstate_bv & ~XFEATURE_MASK_FPSSE || 3778 mxcsr & ~mxcsr_feature_mask) 3779 return -EINVAL; 3780 memcpy(&vcpu->arch.guest_fpu->state.fxsave, 3781 guest_xsave->region, sizeof(struct fxregs_state)); 3782 } 3783 return 0; 3784 } 3785 3786 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3787 struct kvm_xcrs *guest_xcrs) 3788 { 3789 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 3790 guest_xcrs->nr_xcrs = 0; 3791 return; 3792 } 3793 3794 guest_xcrs->nr_xcrs = 1; 3795 guest_xcrs->flags = 0; 3796 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3797 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3798 } 3799 3800 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3801 struct kvm_xcrs *guest_xcrs) 3802 { 3803 int i, r = 0; 3804 3805 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 3806 return -EINVAL; 3807 3808 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3809 return -EINVAL; 3810 3811 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3812 /* Only support XCR0 currently */ 3813 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3814 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3815 guest_xcrs->xcrs[i].value); 3816 break; 3817 } 3818 if (r) 3819 r = -EINVAL; 3820 return r; 3821 } 3822 3823 /* 3824 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3825 * stopped by the hypervisor. This function will be called from the host only. 3826 * EINVAL is returned when the host attempts to set the flag for a guest that 3827 * does not support pv clocks. 3828 */ 3829 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3830 { 3831 if (!vcpu->arch.pv_time_enabled) 3832 return -EINVAL; 3833 vcpu->arch.pvclock_set_guest_stopped_request = true; 3834 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3835 return 0; 3836 } 3837 3838 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 3839 struct kvm_enable_cap *cap) 3840 { 3841 int r; 3842 uint16_t vmcs_version; 3843 void __user *user_ptr; 3844 3845 if (cap->flags) 3846 return -EINVAL; 3847 3848 switch (cap->cap) { 3849 case KVM_CAP_HYPERV_SYNIC2: 3850 if (cap->args[0]) 3851 return -EINVAL; 3852 /* fall through */ 3853 3854 case KVM_CAP_HYPERV_SYNIC: 3855 if (!irqchip_in_kernel(vcpu->kvm)) 3856 return -EINVAL; 3857 return kvm_hv_activate_synic(vcpu, cap->cap == 3858 KVM_CAP_HYPERV_SYNIC2); 3859 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 3860 if (!kvm_x86_ops->nested_enable_evmcs) 3861 return -ENOTTY; 3862 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version); 3863 if (!r) { 3864 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 3865 if (copy_to_user(user_ptr, &vmcs_version, 3866 sizeof(vmcs_version))) 3867 r = -EFAULT; 3868 } 3869 return r; 3870 3871 default: 3872 return -EINVAL; 3873 } 3874 } 3875 3876 long kvm_arch_vcpu_ioctl(struct file *filp, 3877 unsigned int ioctl, unsigned long arg) 3878 { 3879 struct kvm_vcpu *vcpu = filp->private_data; 3880 void __user *argp = (void __user *)arg; 3881 int r; 3882 union { 3883 struct kvm_lapic_state *lapic; 3884 struct kvm_xsave *xsave; 3885 struct kvm_xcrs *xcrs; 3886 void *buffer; 3887 } u; 3888 3889 vcpu_load(vcpu); 3890 3891 u.buffer = NULL; 3892 switch (ioctl) { 3893 case KVM_GET_LAPIC: { 3894 r = -EINVAL; 3895 if (!lapic_in_kernel(vcpu)) 3896 goto out; 3897 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 3898 GFP_KERNEL_ACCOUNT); 3899 3900 r = -ENOMEM; 3901 if (!u.lapic) 3902 goto out; 3903 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3904 if (r) 3905 goto out; 3906 r = -EFAULT; 3907 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3908 goto out; 3909 r = 0; 3910 break; 3911 } 3912 case KVM_SET_LAPIC: { 3913 r = -EINVAL; 3914 if (!lapic_in_kernel(vcpu)) 3915 goto out; 3916 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3917 if (IS_ERR(u.lapic)) { 3918 r = PTR_ERR(u.lapic); 3919 goto out_nofree; 3920 } 3921 3922 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3923 break; 3924 } 3925 case KVM_INTERRUPT: { 3926 struct kvm_interrupt irq; 3927 3928 r = -EFAULT; 3929 if (copy_from_user(&irq, argp, sizeof(irq))) 3930 goto out; 3931 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3932 break; 3933 } 3934 case KVM_NMI: { 3935 r = kvm_vcpu_ioctl_nmi(vcpu); 3936 break; 3937 } 3938 case KVM_SMI: { 3939 r = kvm_vcpu_ioctl_smi(vcpu); 3940 break; 3941 } 3942 case KVM_SET_CPUID: { 3943 struct kvm_cpuid __user *cpuid_arg = argp; 3944 struct kvm_cpuid cpuid; 3945 3946 r = -EFAULT; 3947 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3948 goto out; 3949 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3950 break; 3951 } 3952 case KVM_SET_CPUID2: { 3953 struct kvm_cpuid2 __user *cpuid_arg = argp; 3954 struct kvm_cpuid2 cpuid; 3955 3956 r = -EFAULT; 3957 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3958 goto out; 3959 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3960 cpuid_arg->entries); 3961 break; 3962 } 3963 case KVM_GET_CPUID2: { 3964 struct kvm_cpuid2 __user *cpuid_arg = argp; 3965 struct kvm_cpuid2 cpuid; 3966 3967 r = -EFAULT; 3968 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3969 goto out; 3970 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3971 cpuid_arg->entries); 3972 if (r) 3973 goto out; 3974 r = -EFAULT; 3975 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 3976 goto out; 3977 r = 0; 3978 break; 3979 } 3980 case KVM_GET_MSRS: { 3981 int idx = srcu_read_lock(&vcpu->kvm->srcu); 3982 r = msr_io(vcpu, argp, do_get_msr, 1); 3983 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3984 break; 3985 } 3986 case KVM_SET_MSRS: { 3987 int idx = srcu_read_lock(&vcpu->kvm->srcu); 3988 r = msr_io(vcpu, argp, do_set_msr, 0); 3989 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3990 break; 3991 } 3992 case KVM_TPR_ACCESS_REPORTING: { 3993 struct kvm_tpr_access_ctl tac; 3994 3995 r = -EFAULT; 3996 if (copy_from_user(&tac, argp, sizeof(tac))) 3997 goto out; 3998 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3999 if (r) 4000 goto out; 4001 r = -EFAULT; 4002 if (copy_to_user(argp, &tac, sizeof(tac))) 4003 goto out; 4004 r = 0; 4005 break; 4006 }; 4007 case KVM_SET_VAPIC_ADDR: { 4008 struct kvm_vapic_addr va; 4009 int idx; 4010 4011 r = -EINVAL; 4012 if (!lapic_in_kernel(vcpu)) 4013 goto out; 4014 r = -EFAULT; 4015 if (copy_from_user(&va, argp, sizeof(va))) 4016 goto out; 4017 idx = srcu_read_lock(&vcpu->kvm->srcu); 4018 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 4019 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4020 break; 4021 } 4022 case KVM_X86_SETUP_MCE: { 4023 u64 mcg_cap; 4024 4025 r = -EFAULT; 4026 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 4027 goto out; 4028 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 4029 break; 4030 } 4031 case KVM_X86_SET_MCE: { 4032 struct kvm_x86_mce mce; 4033 4034 r = -EFAULT; 4035 if (copy_from_user(&mce, argp, sizeof(mce))) 4036 goto out; 4037 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 4038 break; 4039 } 4040 case KVM_GET_VCPU_EVENTS: { 4041 struct kvm_vcpu_events events; 4042 4043 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 4044 4045 r = -EFAULT; 4046 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 4047 break; 4048 r = 0; 4049 break; 4050 } 4051 case KVM_SET_VCPU_EVENTS: { 4052 struct kvm_vcpu_events events; 4053 4054 r = -EFAULT; 4055 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 4056 break; 4057 4058 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 4059 break; 4060 } 4061 case KVM_GET_DEBUGREGS: { 4062 struct kvm_debugregs dbgregs; 4063 4064 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 4065 4066 r = -EFAULT; 4067 if (copy_to_user(argp, &dbgregs, 4068 sizeof(struct kvm_debugregs))) 4069 break; 4070 r = 0; 4071 break; 4072 } 4073 case KVM_SET_DEBUGREGS: { 4074 struct kvm_debugregs dbgregs; 4075 4076 r = -EFAULT; 4077 if (copy_from_user(&dbgregs, argp, 4078 sizeof(struct kvm_debugregs))) 4079 break; 4080 4081 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 4082 break; 4083 } 4084 case KVM_GET_XSAVE: { 4085 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 4086 r = -ENOMEM; 4087 if (!u.xsave) 4088 break; 4089 4090 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 4091 4092 r = -EFAULT; 4093 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 4094 break; 4095 r = 0; 4096 break; 4097 } 4098 case KVM_SET_XSAVE: { 4099 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 4100 if (IS_ERR(u.xsave)) { 4101 r = PTR_ERR(u.xsave); 4102 goto out_nofree; 4103 } 4104 4105 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 4106 break; 4107 } 4108 case KVM_GET_XCRS: { 4109 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 4110 r = -ENOMEM; 4111 if (!u.xcrs) 4112 break; 4113 4114 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 4115 4116 r = -EFAULT; 4117 if (copy_to_user(argp, u.xcrs, 4118 sizeof(struct kvm_xcrs))) 4119 break; 4120 r = 0; 4121 break; 4122 } 4123 case KVM_SET_XCRS: { 4124 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 4125 if (IS_ERR(u.xcrs)) { 4126 r = PTR_ERR(u.xcrs); 4127 goto out_nofree; 4128 } 4129 4130 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 4131 break; 4132 } 4133 case KVM_SET_TSC_KHZ: { 4134 u32 user_tsc_khz; 4135 4136 r = -EINVAL; 4137 user_tsc_khz = (u32)arg; 4138 4139 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 4140 goto out; 4141 4142 if (user_tsc_khz == 0) 4143 user_tsc_khz = tsc_khz; 4144 4145 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 4146 r = 0; 4147 4148 goto out; 4149 } 4150 case KVM_GET_TSC_KHZ: { 4151 r = vcpu->arch.virtual_tsc_khz; 4152 goto out; 4153 } 4154 case KVM_KVMCLOCK_CTRL: { 4155 r = kvm_set_guest_paused(vcpu); 4156 goto out; 4157 } 4158 case KVM_ENABLE_CAP: { 4159 struct kvm_enable_cap cap; 4160 4161 r = -EFAULT; 4162 if (copy_from_user(&cap, argp, sizeof(cap))) 4163 goto out; 4164 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 4165 break; 4166 } 4167 case KVM_GET_NESTED_STATE: { 4168 struct kvm_nested_state __user *user_kvm_nested_state = argp; 4169 u32 user_data_size; 4170 4171 r = -EINVAL; 4172 if (!kvm_x86_ops->get_nested_state) 4173 break; 4174 4175 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 4176 r = -EFAULT; 4177 if (get_user(user_data_size, &user_kvm_nested_state->size)) 4178 break; 4179 4180 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state, 4181 user_data_size); 4182 if (r < 0) 4183 break; 4184 4185 if (r > user_data_size) { 4186 if (put_user(r, &user_kvm_nested_state->size)) 4187 r = -EFAULT; 4188 else 4189 r = -E2BIG; 4190 break; 4191 } 4192 4193 r = 0; 4194 break; 4195 } 4196 case KVM_SET_NESTED_STATE: { 4197 struct kvm_nested_state __user *user_kvm_nested_state = argp; 4198 struct kvm_nested_state kvm_state; 4199 4200 r = -EINVAL; 4201 if (!kvm_x86_ops->set_nested_state) 4202 break; 4203 4204 r = -EFAULT; 4205 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 4206 break; 4207 4208 r = -EINVAL; 4209 if (kvm_state.size < sizeof(kvm_state)) 4210 break; 4211 4212 if (kvm_state.flags & 4213 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 4214 | KVM_STATE_NESTED_EVMCS)) 4215 break; 4216 4217 /* nested_run_pending implies guest_mode. */ 4218 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 4219 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 4220 break; 4221 4222 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state); 4223 break; 4224 } 4225 case KVM_GET_SUPPORTED_HV_CPUID: { 4226 struct kvm_cpuid2 __user *cpuid_arg = argp; 4227 struct kvm_cpuid2 cpuid; 4228 4229 r = -EFAULT; 4230 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4231 goto out; 4232 4233 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid, 4234 cpuid_arg->entries); 4235 if (r) 4236 goto out; 4237 4238 r = -EFAULT; 4239 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4240 goto out; 4241 r = 0; 4242 break; 4243 } 4244 default: 4245 r = -EINVAL; 4246 } 4247 out: 4248 kfree(u.buffer); 4249 out_nofree: 4250 vcpu_put(vcpu); 4251 return r; 4252 } 4253 4254 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 4255 { 4256 return VM_FAULT_SIGBUS; 4257 } 4258 4259 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 4260 { 4261 int ret; 4262 4263 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 4264 return -EINVAL; 4265 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 4266 return ret; 4267 } 4268 4269 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 4270 u64 ident_addr) 4271 { 4272 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr); 4273 } 4274 4275 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 4276 unsigned long kvm_nr_mmu_pages) 4277 { 4278 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 4279 return -EINVAL; 4280 4281 mutex_lock(&kvm->slots_lock); 4282 4283 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 4284 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 4285 4286 mutex_unlock(&kvm->slots_lock); 4287 return 0; 4288 } 4289 4290 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 4291 { 4292 return kvm->arch.n_max_mmu_pages; 4293 } 4294 4295 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 4296 { 4297 struct kvm_pic *pic = kvm->arch.vpic; 4298 int r; 4299 4300 r = 0; 4301 switch (chip->chip_id) { 4302 case KVM_IRQCHIP_PIC_MASTER: 4303 memcpy(&chip->chip.pic, &pic->pics[0], 4304 sizeof(struct kvm_pic_state)); 4305 break; 4306 case KVM_IRQCHIP_PIC_SLAVE: 4307 memcpy(&chip->chip.pic, &pic->pics[1], 4308 sizeof(struct kvm_pic_state)); 4309 break; 4310 case KVM_IRQCHIP_IOAPIC: 4311 kvm_get_ioapic(kvm, &chip->chip.ioapic); 4312 break; 4313 default: 4314 r = -EINVAL; 4315 break; 4316 } 4317 return r; 4318 } 4319 4320 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 4321 { 4322 struct kvm_pic *pic = kvm->arch.vpic; 4323 int r; 4324 4325 r = 0; 4326 switch (chip->chip_id) { 4327 case KVM_IRQCHIP_PIC_MASTER: 4328 spin_lock(&pic->lock); 4329 memcpy(&pic->pics[0], &chip->chip.pic, 4330 sizeof(struct kvm_pic_state)); 4331 spin_unlock(&pic->lock); 4332 break; 4333 case KVM_IRQCHIP_PIC_SLAVE: 4334 spin_lock(&pic->lock); 4335 memcpy(&pic->pics[1], &chip->chip.pic, 4336 sizeof(struct kvm_pic_state)); 4337 spin_unlock(&pic->lock); 4338 break; 4339 case KVM_IRQCHIP_IOAPIC: 4340 kvm_set_ioapic(kvm, &chip->chip.ioapic); 4341 break; 4342 default: 4343 r = -EINVAL; 4344 break; 4345 } 4346 kvm_pic_update_irq(pic); 4347 return r; 4348 } 4349 4350 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 4351 { 4352 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 4353 4354 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 4355 4356 mutex_lock(&kps->lock); 4357 memcpy(ps, &kps->channels, sizeof(*ps)); 4358 mutex_unlock(&kps->lock); 4359 return 0; 4360 } 4361 4362 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 4363 { 4364 int i; 4365 struct kvm_pit *pit = kvm->arch.vpit; 4366 4367 mutex_lock(&pit->pit_state.lock); 4368 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 4369 for (i = 0; i < 3; i++) 4370 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 4371 mutex_unlock(&pit->pit_state.lock); 4372 return 0; 4373 } 4374 4375 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 4376 { 4377 mutex_lock(&kvm->arch.vpit->pit_state.lock); 4378 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 4379 sizeof(ps->channels)); 4380 ps->flags = kvm->arch.vpit->pit_state.flags; 4381 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 4382 memset(&ps->reserved, 0, sizeof(ps->reserved)); 4383 return 0; 4384 } 4385 4386 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 4387 { 4388 int start = 0; 4389 int i; 4390 u32 prev_legacy, cur_legacy; 4391 struct kvm_pit *pit = kvm->arch.vpit; 4392 4393 mutex_lock(&pit->pit_state.lock); 4394 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 4395 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 4396 if (!prev_legacy && cur_legacy) 4397 start = 1; 4398 memcpy(&pit->pit_state.channels, &ps->channels, 4399 sizeof(pit->pit_state.channels)); 4400 pit->pit_state.flags = ps->flags; 4401 for (i = 0; i < 3; i++) 4402 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 4403 start && i == 0); 4404 mutex_unlock(&pit->pit_state.lock); 4405 return 0; 4406 } 4407 4408 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 4409 struct kvm_reinject_control *control) 4410 { 4411 struct kvm_pit *pit = kvm->arch.vpit; 4412 4413 if (!pit) 4414 return -ENXIO; 4415 4416 /* pit->pit_state.lock was overloaded to prevent userspace from getting 4417 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 4418 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 4419 */ 4420 mutex_lock(&pit->pit_state.lock); 4421 kvm_pit_set_reinject(pit, control->pit_reinject); 4422 mutex_unlock(&pit->pit_state.lock); 4423 4424 return 0; 4425 } 4426 4427 /** 4428 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 4429 * @kvm: kvm instance 4430 * @log: slot id and address to which we copy the log 4431 * 4432 * Steps 1-4 below provide general overview of dirty page logging. See 4433 * kvm_get_dirty_log_protect() function description for additional details. 4434 * 4435 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 4436 * always flush the TLB (step 4) even if previous step failed and the dirty 4437 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 4438 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 4439 * writes will be marked dirty for next log read. 4440 * 4441 * 1. Take a snapshot of the bit and clear it if needed. 4442 * 2. Write protect the corresponding page. 4443 * 3. Copy the snapshot to the userspace. 4444 * 4. Flush TLB's if needed. 4445 */ 4446 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 4447 { 4448 bool flush = false; 4449 int r; 4450 4451 mutex_lock(&kvm->slots_lock); 4452 4453 /* 4454 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 4455 */ 4456 if (kvm_x86_ops->flush_log_dirty) 4457 kvm_x86_ops->flush_log_dirty(kvm); 4458 4459 r = kvm_get_dirty_log_protect(kvm, log, &flush); 4460 4461 /* 4462 * All the TLBs can be flushed out of mmu lock, see the comments in 4463 * kvm_mmu_slot_remove_write_access(). 4464 */ 4465 lockdep_assert_held(&kvm->slots_lock); 4466 if (flush) 4467 kvm_flush_remote_tlbs(kvm); 4468 4469 mutex_unlock(&kvm->slots_lock); 4470 return r; 4471 } 4472 4473 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log) 4474 { 4475 bool flush = false; 4476 int r; 4477 4478 mutex_lock(&kvm->slots_lock); 4479 4480 /* 4481 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 4482 */ 4483 if (kvm_x86_ops->flush_log_dirty) 4484 kvm_x86_ops->flush_log_dirty(kvm); 4485 4486 r = kvm_clear_dirty_log_protect(kvm, log, &flush); 4487 4488 /* 4489 * All the TLBs can be flushed out of mmu lock, see the comments in 4490 * kvm_mmu_slot_remove_write_access(). 4491 */ 4492 lockdep_assert_held(&kvm->slots_lock); 4493 if (flush) 4494 kvm_flush_remote_tlbs(kvm); 4495 4496 mutex_unlock(&kvm->slots_lock); 4497 return r; 4498 } 4499 4500 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 4501 bool line_status) 4502 { 4503 if (!irqchip_in_kernel(kvm)) 4504 return -ENXIO; 4505 4506 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 4507 irq_event->irq, irq_event->level, 4508 line_status); 4509 return 0; 4510 } 4511 4512 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 4513 struct kvm_enable_cap *cap) 4514 { 4515 int r; 4516 4517 if (cap->flags) 4518 return -EINVAL; 4519 4520 switch (cap->cap) { 4521 case KVM_CAP_DISABLE_QUIRKS: 4522 kvm->arch.disabled_quirks = cap->args[0]; 4523 r = 0; 4524 break; 4525 case KVM_CAP_SPLIT_IRQCHIP: { 4526 mutex_lock(&kvm->lock); 4527 r = -EINVAL; 4528 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 4529 goto split_irqchip_unlock; 4530 r = -EEXIST; 4531 if (irqchip_in_kernel(kvm)) 4532 goto split_irqchip_unlock; 4533 if (kvm->created_vcpus) 4534 goto split_irqchip_unlock; 4535 r = kvm_setup_empty_irq_routing(kvm); 4536 if (r) 4537 goto split_irqchip_unlock; 4538 /* Pairs with irqchip_in_kernel. */ 4539 smp_wmb(); 4540 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 4541 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 4542 r = 0; 4543 split_irqchip_unlock: 4544 mutex_unlock(&kvm->lock); 4545 break; 4546 } 4547 case KVM_CAP_X2APIC_API: 4548 r = -EINVAL; 4549 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 4550 break; 4551 4552 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 4553 kvm->arch.x2apic_format = true; 4554 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 4555 kvm->arch.x2apic_broadcast_quirk_disabled = true; 4556 4557 r = 0; 4558 break; 4559 case KVM_CAP_X86_DISABLE_EXITS: 4560 r = -EINVAL; 4561 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 4562 break; 4563 4564 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 4565 kvm_can_mwait_in_guest()) 4566 kvm->arch.mwait_in_guest = true; 4567 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 4568 kvm->arch.hlt_in_guest = true; 4569 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 4570 kvm->arch.pause_in_guest = true; 4571 r = 0; 4572 break; 4573 case KVM_CAP_MSR_PLATFORM_INFO: 4574 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 4575 r = 0; 4576 break; 4577 case KVM_CAP_EXCEPTION_PAYLOAD: 4578 kvm->arch.exception_payload_enabled = cap->args[0]; 4579 r = 0; 4580 break; 4581 default: 4582 r = -EINVAL; 4583 break; 4584 } 4585 return r; 4586 } 4587 4588 long kvm_arch_vm_ioctl(struct file *filp, 4589 unsigned int ioctl, unsigned long arg) 4590 { 4591 struct kvm *kvm = filp->private_data; 4592 void __user *argp = (void __user *)arg; 4593 int r = -ENOTTY; 4594 /* 4595 * This union makes it completely explicit to gcc-3.x 4596 * that these two variables' stack usage should be 4597 * combined, not added together. 4598 */ 4599 union { 4600 struct kvm_pit_state ps; 4601 struct kvm_pit_state2 ps2; 4602 struct kvm_pit_config pit_config; 4603 } u; 4604 4605 switch (ioctl) { 4606 case KVM_SET_TSS_ADDR: 4607 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 4608 break; 4609 case KVM_SET_IDENTITY_MAP_ADDR: { 4610 u64 ident_addr; 4611 4612 mutex_lock(&kvm->lock); 4613 r = -EINVAL; 4614 if (kvm->created_vcpus) 4615 goto set_identity_unlock; 4616 r = -EFAULT; 4617 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 4618 goto set_identity_unlock; 4619 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 4620 set_identity_unlock: 4621 mutex_unlock(&kvm->lock); 4622 break; 4623 } 4624 case KVM_SET_NR_MMU_PAGES: 4625 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 4626 break; 4627 case KVM_GET_NR_MMU_PAGES: 4628 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 4629 break; 4630 case KVM_CREATE_IRQCHIP: { 4631 mutex_lock(&kvm->lock); 4632 4633 r = -EEXIST; 4634 if (irqchip_in_kernel(kvm)) 4635 goto create_irqchip_unlock; 4636 4637 r = -EINVAL; 4638 if (kvm->created_vcpus) 4639 goto create_irqchip_unlock; 4640 4641 r = kvm_pic_init(kvm); 4642 if (r) 4643 goto create_irqchip_unlock; 4644 4645 r = kvm_ioapic_init(kvm); 4646 if (r) { 4647 kvm_pic_destroy(kvm); 4648 goto create_irqchip_unlock; 4649 } 4650 4651 r = kvm_setup_default_irq_routing(kvm); 4652 if (r) { 4653 kvm_ioapic_destroy(kvm); 4654 kvm_pic_destroy(kvm); 4655 goto create_irqchip_unlock; 4656 } 4657 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 4658 smp_wmb(); 4659 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 4660 create_irqchip_unlock: 4661 mutex_unlock(&kvm->lock); 4662 break; 4663 } 4664 case KVM_CREATE_PIT: 4665 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 4666 goto create_pit; 4667 case KVM_CREATE_PIT2: 4668 r = -EFAULT; 4669 if (copy_from_user(&u.pit_config, argp, 4670 sizeof(struct kvm_pit_config))) 4671 goto out; 4672 create_pit: 4673 mutex_lock(&kvm->lock); 4674 r = -EEXIST; 4675 if (kvm->arch.vpit) 4676 goto create_pit_unlock; 4677 r = -ENOMEM; 4678 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 4679 if (kvm->arch.vpit) 4680 r = 0; 4681 create_pit_unlock: 4682 mutex_unlock(&kvm->lock); 4683 break; 4684 case KVM_GET_IRQCHIP: { 4685 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4686 struct kvm_irqchip *chip; 4687 4688 chip = memdup_user(argp, sizeof(*chip)); 4689 if (IS_ERR(chip)) { 4690 r = PTR_ERR(chip); 4691 goto out; 4692 } 4693 4694 r = -ENXIO; 4695 if (!irqchip_kernel(kvm)) 4696 goto get_irqchip_out; 4697 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 4698 if (r) 4699 goto get_irqchip_out; 4700 r = -EFAULT; 4701 if (copy_to_user(argp, chip, sizeof(*chip))) 4702 goto get_irqchip_out; 4703 r = 0; 4704 get_irqchip_out: 4705 kfree(chip); 4706 break; 4707 } 4708 case KVM_SET_IRQCHIP: { 4709 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4710 struct kvm_irqchip *chip; 4711 4712 chip = memdup_user(argp, sizeof(*chip)); 4713 if (IS_ERR(chip)) { 4714 r = PTR_ERR(chip); 4715 goto out; 4716 } 4717 4718 r = -ENXIO; 4719 if (!irqchip_kernel(kvm)) 4720 goto set_irqchip_out; 4721 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 4722 if (r) 4723 goto set_irqchip_out; 4724 r = 0; 4725 set_irqchip_out: 4726 kfree(chip); 4727 break; 4728 } 4729 case KVM_GET_PIT: { 4730 r = -EFAULT; 4731 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 4732 goto out; 4733 r = -ENXIO; 4734 if (!kvm->arch.vpit) 4735 goto out; 4736 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 4737 if (r) 4738 goto out; 4739 r = -EFAULT; 4740 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 4741 goto out; 4742 r = 0; 4743 break; 4744 } 4745 case KVM_SET_PIT: { 4746 r = -EFAULT; 4747 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 4748 goto out; 4749 r = -ENXIO; 4750 if (!kvm->arch.vpit) 4751 goto out; 4752 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 4753 break; 4754 } 4755 case KVM_GET_PIT2: { 4756 r = -ENXIO; 4757 if (!kvm->arch.vpit) 4758 goto out; 4759 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 4760 if (r) 4761 goto out; 4762 r = -EFAULT; 4763 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 4764 goto out; 4765 r = 0; 4766 break; 4767 } 4768 case KVM_SET_PIT2: { 4769 r = -EFAULT; 4770 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 4771 goto out; 4772 r = -ENXIO; 4773 if (!kvm->arch.vpit) 4774 goto out; 4775 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 4776 break; 4777 } 4778 case KVM_REINJECT_CONTROL: { 4779 struct kvm_reinject_control control; 4780 r = -EFAULT; 4781 if (copy_from_user(&control, argp, sizeof(control))) 4782 goto out; 4783 r = kvm_vm_ioctl_reinject(kvm, &control); 4784 break; 4785 } 4786 case KVM_SET_BOOT_CPU_ID: 4787 r = 0; 4788 mutex_lock(&kvm->lock); 4789 if (kvm->created_vcpus) 4790 r = -EBUSY; 4791 else 4792 kvm->arch.bsp_vcpu_id = arg; 4793 mutex_unlock(&kvm->lock); 4794 break; 4795 case KVM_XEN_HVM_CONFIG: { 4796 struct kvm_xen_hvm_config xhc; 4797 r = -EFAULT; 4798 if (copy_from_user(&xhc, argp, sizeof(xhc))) 4799 goto out; 4800 r = -EINVAL; 4801 if (xhc.flags) 4802 goto out; 4803 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); 4804 r = 0; 4805 break; 4806 } 4807 case KVM_SET_CLOCK: { 4808 struct kvm_clock_data user_ns; 4809 u64 now_ns; 4810 4811 r = -EFAULT; 4812 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 4813 goto out; 4814 4815 r = -EINVAL; 4816 if (user_ns.flags) 4817 goto out; 4818 4819 r = 0; 4820 /* 4821 * TODO: userspace has to take care of races with VCPU_RUN, so 4822 * kvm_gen_update_masterclock() can be cut down to locked 4823 * pvclock_update_vm_gtod_copy(). 4824 */ 4825 kvm_gen_update_masterclock(kvm); 4826 now_ns = get_kvmclock_ns(kvm); 4827 kvm->arch.kvmclock_offset += user_ns.clock - now_ns; 4828 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); 4829 break; 4830 } 4831 case KVM_GET_CLOCK: { 4832 struct kvm_clock_data user_ns; 4833 u64 now_ns; 4834 4835 now_ns = get_kvmclock_ns(kvm); 4836 user_ns.clock = now_ns; 4837 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 4838 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 4839 4840 r = -EFAULT; 4841 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 4842 goto out; 4843 r = 0; 4844 break; 4845 } 4846 case KVM_MEMORY_ENCRYPT_OP: { 4847 r = -ENOTTY; 4848 if (kvm_x86_ops->mem_enc_op) 4849 r = kvm_x86_ops->mem_enc_op(kvm, argp); 4850 break; 4851 } 4852 case KVM_MEMORY_ENCRYPT_REG_REGION: { 4853 struct kvm_enc_region region; 4854 4855 r = -EFAULT; 4856 if (copy_from_user(®ion, argp, sizeof(region))) 4857 goto out; 4858 4859 r = -ENOTTY; 4860 if (kvm_x86_ops->mem_enc_reg_region) 4861 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion); 4862 break; 4863 } 4864 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 4865 struct kvm_enc_region region; 4866 4867 r = -EFAULT; 4868 if (copy_from_user(®ion, argp, sizeof(region))) 4869 goto out; 4870 4871 r = -ENOTTY; 4872 if (kvm_x86_ops->mem_enc_unreg_region) 4873 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion); 4874 break; 4875 } 4876 case KVM_HYPERV_EVENTFD: { 4877 struct kvm_hyperv_eventfd hvevfd; 4878 4879 r = -EFAULT; 4880 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 4881 goto out; 4882 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 4883 break; 4884 } 4885 default: 4886 r = -ENOTTY; 4887 } 4888 out: 4889 return r; 4890 } 4891 4892 static void kvm_init_msr_list(void) 4893 { 4894 u32 dummy[2]; 4895 unsigned i, j; 4896 4897 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { 4898 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4899 continue; 4900 4901 /* 4902 * Even MSRs that are valid in the host may not be exposed 4903 * to the guests in some cases. 4904 */ 4905 switch (msrs_to_save[i]) { 4906 case MSR_IA32_BNDCFGS: 4907 if (!kvm_mpx_supported()) 4908 continue; 4909 break; 4910 case MSR_TSC_AUX: 4911 if (!kvm_x86_ops->rdtscp_supported()) 4912 continue; 4913 break; 4914 case MSR_IA32_RTIT_CTL: 4915 case MSR_IA32_RTIT_STATUS: 4916 if (!kvm_x86_ops->pt_supported()) 4917 continue; 4918 break; 4919 case MSR_IA32_RTIT_CR3_MATCH: 4920 if (!kvm_x86_ops->pt_supported() || 4921 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 4922 continue; 4923 break; 4924 case MSR_IA32_RTIT_OUTPUT_BASE: 4925 case MSR_IA32_RTIT_OUTPUT_MASK: 4926 if (!kvm_x86_ops->pt_supported() || 4927 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 4928 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 4929 continue; 4930 break; 4931 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: { 4932 if (!kvm_x86_ops->pt_supported() || 4933 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >= 4934 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 4935 continue; 4936 break; 4937 } 4938 default: 4939 break; 4940 } 4941 4942 if (j < i) 4943 msrs_to_save[j] = msrs_to_save[i]; 4944 j++; 4945 } 4946 num_msrs_to_save = j; 4947 4948 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { 4949 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i])) 4950 continue; 4951 4952 if (j < i) 4953 emulated_msrs[j] = emulated_msrs[i]; 4954 j++; 4955 } 4956 num_emulated_msrs = j; 4957 4958 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) { 4959 struct kvm_msr_entry msr; 4960 4961 msr.index = msr_based_features[i]; 4962 if (kvm_get_msr_feature(&msr)) 4963 continue; 4964 4965 if (j < i) 4966 msr_based_features[j] = msr_based_features[i]; 4967 j++; 4968 } 4969 num_msr_based_features = j; 4970 } 4971 4972 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 4973 const void *v) 4974 { 4975 int handled = 0; 4976 int n; 4977 4978 do { 4979 n = min(len, 8); 4980 if (!(lapic_in_kernel(vcpu) && 4981 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 4982 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 4983 break; 4984 handled += n; 4985 addr += n; 4986 len -= n; 4987 v += n; 4988 } while (len); 4989 4990 return handled; 4991 } 4992 4993 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4994 { 4995 int handled = 0; 4996 int n; 4997 4998 do { 4999 n = min(len, 8); 5000 if (!(lapic_in_kernel(vcpu) && 5001 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 5002 addr, n, v)) 5003 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 5004 break; 5005 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 5006 handled += n; 5007 addr += n; 5008 len -= n; 5009 v += n; 5010 } while (len); 5011 5012 return handled; 5013 } 5014 5015 static void kvm_set_segment(struct kvm_vcpu *vcpu, 5016 struct kvm_segment *var, int seg) 5017 { 5018 kvm_x86_ops->set_segment(vcpu, var, seg); 5019 } 5020 5021 void kvm_get_segment(struct kvm_vcpu *vcpu, 5022 struct kvm_segment *var, int seg) 5023 { 5024 kvm_x86_ops->get_segment(vcpu, var, seg); 5025 } 5026 5027 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 5028 struct x86_exception *exception) 5029 { 5030 gpa_t t_gpa; 5031 5032 BUG_ON(!mmu_is_nested(vcpu)); 5033 5034 /* NPT walks are always user-walks */ 5035 access |= PFERR_USER_MASK; 5036 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); 5037 5038 return t_gpa; 5039 } 5040 5041 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 5042 struct x86_exception *exception) 5043 { 5044 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5045 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5046 } 5047 5048 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 5049 struct x86_exception *exception) 5050 { 5051 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5052 access |= PFERR_FETCH_MASK; 5053 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5054 } 5055 5056 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 5057 struct x86_exception *exception) 5058 { 5059 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5060 access |= PFERR_WRITE_MASK; 5061 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5062 } 5063 5064 /* uses this to access any guest's mapped memory without checking CPL */ 5065 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 5066 struct x86_exception *exception) 5067 { 5068 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 5069 } 5070 5071 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 5072 struct kvm_vcpu *vcpu, u32 access, 5073 struct x86_exception *exception) 5074 { 5075 void *data = val; 5076 int r = X86EMUL_CONTINUE; 5077 5078 while (bytes) { 5079 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 5080 exception); 5081 unsigned offset = addr & (PAGE_SIZE-1); 5082 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 5083 int ret; 5084 5085 if (gpa == UNMAPPED_GVA) 5086 return X86EMUL_PROPAGATE_FAULT; 5087 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 5088 offset, toread); 5089 if (ret < 0) { 5090 r = X86EMUL_IO_NEEDED; 5091 goto out; 5092 } 5093 5094 bytes -= toread; 5095 data += toread; 5096 addr += toread; 5097 } 5098 out: 5099 return r; 5100 } 5101 5102 /* used for instruction fetching */ 5103 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 5104 gva_t addr, void *val, unsigned int bytes, 5105 struct x86_exception *exception) 5106 { 5107 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5108 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5109 unsigned offset; 5110 int ret; 5111 5112 /* Inline kvm_read_guest_virt_helper for speed. */ 5113 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 5114 exception); 5115 if (unlikely(gpa == UNMAPPED_GVA)) 5116 return X86EMUL_PROPAGATE_FAULT; 5117 5118 offset = addr & (PAGE_SIZE-1); 5119 if (WARN_ON(offset + bytes > PAGE_SIZE)) 5120 bytes = (unsigned)PAGE_SIZE - offset; 5121 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 5122 offset, bytes); 5123 if (unlikely(ret < 0)) 5124 return X86EMUL_IO_NEEDED; 5125 5126 return X86EMUL_CONTINUE; 5127 } 5128 5129 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 5130 gva_t addr, void *val, unsigned int bytes, 5131 struct x86_exception *exception) 5132 { 5133 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5134 5135 /* 5136 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 5137 * is returned, but our callers are not ready for that and they blindly 5138 * call kvm_inject_page_fault. Ensure that they at least do not leak 5139 * uninitialized kernel stack memory into cr2 and error code. 5140 */ 5141 memset(exception, 0, sizeof(*exception)); 5142 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 5143 exception); 5144 } 5145 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 5146 5147 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 5148 gva_t addr, void *val, unsigned int bytes, 5149 struct x86_exception *exception, bool system) 5150 { 5151 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5152 u32 access = 0; 5153 5154 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3) 5155 access |= PFERR_USER_MASK; 5156 5157 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 5158 } 5159 5160 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 5161 unsigned long addr, void *val, unsigned int bytes) 5162 { 5163 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5164 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 5165 5166 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 5167 } 5168 5169 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 5170 struct kvm_vcpu *vcpu, u32 access, 5171 struct x86_exception *exception) 5172 { 5173 void *data = val; 5174 int r = X86EMUL_CONTINUE; 5175 5176 while (bytes) { 5177 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 5178 access, 5179 exception); 5180 unsigned offset = addr & (PAGE_SIZE-1); 5181 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 5182 int ret; 5183 5184 if (gpa == UNMAPPED_GVA) 5185 return X86EMUL_PROPAGATE_FAULT; 5186 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 5187 if (ret < 0) { 5188 r = X86EMUL_IO_NEEDED; 5189 goto out; 5190 } 5191 5192 bytes -= towrite; 5193 data += towrite; 5194 addr += towrite; 5195 } 5196 out: 5197 return r; 5198 } 5199 5200 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 5201 unsigned int bytes, struct x86_exception *exception, 5202 bool system) 5203 { 5204 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5205 u32 access = PFERR_WRITE_MASK; 5206 5207 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3) 5208 access |= PFERR_USER_MASK; 5209 5210 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 5211 access, exception); 5212 } 5213 5214 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 5215 unsigned int bytes, struct x86_exception *exception) 5216 { 5217 /* kvm_write_guest_virt_system can pull in tons of pages. */ 5218 vcpu->arch.l1tf_flush_l1d = true; 5219 5220 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 5221 PFERR_WRITE_MASK, exception); 5222 } 5223 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 5224 5225 int handle_ud(struct kvm_vcpu *vcpu) 5226 { 5227 int emul_type = EMULTYPE_TRAP_UD; 5228 enum emulation_result er; 5229 char sig[5]; /* ud2; .ascii "kvm" */ 5230 struct x86_exception e; 5231 5232 if (force_emulation_prefix && 5233 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 5234 sig, sizeof(sig), &e) == 0 && 5235 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) { 5236 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 5237 emul_type = 0; 5238 } 5239 5240 er = kvm_emulate_instruction(vcpu, emul_type); 5241 if (er == EMULATE_USER_EXIT) 5242 return 0; 5243 if (er != EMULATE_DONE) 5244 kvm_queue_exception(vcpu, UD_VECTOR); 5245 return 1; 5246 } 5247 EXPORT_SYMBOL_GPL(handle_ud); 5248 5249 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 5250 gpa_t gpa, bool write) 5251 { 5252 /* For APIC access vmexit */ 5253 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 5254 return 1; 5255 5256 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 5257 trace_vcpu_match_mmio(gva, gpa, write, true); 5258 return 1; 5259 } 5260 5261 return 0; 5262 } 5263 5264 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 5265 gpa_t *gpa, struct x86_exception *exception, 5266 bool write) 5267 { 5268 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 5269 | (write ? PFERR_WRITE_MASK : 0); 5270 5271 /* 5272 * currently PKRU is only applied to ept enabled guest so 5273 * there is no pkey in EPT page table for L1 guest or EPT 5274 * shadow page table for L2 guest. 5275 */ 5276 if (vcpu_match_mmio_gva(vcpu, gva) 5277 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 5278 vcpu->arch.access, 0, access)) { 5279 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 5280 (gva & (PAGE_SIZE - 1)); 5281 trace_vcpu_match_mmio(gva, *gpa, write, false); 5282 return 1; 5283 } 5284 5285 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5286 5287 if (*gpa == UNMAPPED_GVA) 5288 return -1; 5289 5290 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 5291 } 5292 5293 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 5294 const void *val, int bytes) 5295 { 5296 int ret; 5297 5298 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 5299 if (ret < 0) 5300 return 0; 5301 kvm_page_track_write(vcpu, gpa, val, bytes); 5302 return 1; 5303 } 5304 5305 struct read_write_emulator_ops { 5306 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 5307 int bytes); 5308 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 5309 void *val, int bytes); 5310 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 5311 int bytes, void *val); 5312 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 5313 void *val, int bytes); 5314 bool write; 5315 }; 5316 5317 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 5318 { 5319 if (vcpu->mmio_read_completed) { 5320 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 5321 vcpu->mmio_fragments[0].gpa, val); 5322 vcpu->mmio_read_completed = 0; 5323 return 1; 5324 } 5325 5326 return 0; 5327 } 5328 5329 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 5330 void *val, int bytes) 5331 { 5332 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 5333 } 5334 5335 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 5336 void *val, int bytes) 5337 { 5338 return emulator_write_phys(vcpu, gpa, val, bytes); 5339 } 5340 5341 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 5342 { 5343 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 5344 return vcpu_mmio_write(vcpu, gpa, bytes, val); 5345 } 5346 5347 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 5348 void *val, int bytes) 5349 { 5350 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 5351 return X86EMUL_IO_NEEDED; 5352 } 5353 5354 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 5355 void *val, int bytes) 5356 { 5357 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 5358 5359 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 5360 return X86EMUL_CONTINUE; 5361 } 5362 5363 static const struct read_write_emulator_ops read_emultor = { 5364 .read_write_prepare = read_prepare, 5365 .read_write_emulate = read_emulate, 5366 .read_write_mmio = vcpu_mmio_read, 5367 .read_write_exit_mmio = read_exit_mmio, 5368 }; 5369 5370 static const struct read_write_emulator_ops write_emultor = { 5371 .read_write_emulate = write_emulate, 5372 .read_write_mmio = write_mmio, 5373 .read_write_exit_mmio = write_exit_mmio, 5374 .write = true, 5375 }; 5376 5377 static int emulator_read_write_onepage(unsigned long addr, void *val, 5378 unsigned int bytes, 5379 struct x86_exception *exception, 5380 struct kvm_vcpu *vcpu, 5381 const struct read_write_emulator_ops *ops) 5382 { 5383 gpa_t gpa; 5384 int handled, ret; 5385 bool write = ops->write; 5386 struct kvm_mmio_fragment *frag; 5387 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5388 5389 /* 5390 * If the exit was due to a NPF we may already have a GPA. 5391 * If the GPA is present, use it to avoid the GVA to GPA table walk. 5392 * Note, this cannot be used on string operations since string 5393 * operation using rep will only have the initial GPA from the NPF 5394 * occurred. 5395 */ 5396 if (vcpu->arch.gpa_available && 5397 emulator_can_use_gpa(ctxt) && 5398 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) { 5399 gpa = vcpu->arch.gpa_val; 5400 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 5401 } else { 5402 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 5403 if (ret < 0) 5404 return X86EMUL_PROPAGATE_FAULT; 5405 } 5406 5407 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 5408 return X86EMUL_CONTINUE; 5409 5410 /* 5411 * Is this MMIO handled locally? 5412 */ 5413 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 5414 if (handled == bytes) 5415 return X86EMUL_CONTINUE; 5416 5417 gpa += handled; 5418 bytes -= handled; 5419 val += handled; 5420 5421 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 5422 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 5423 frag->gpa = gpa; 5424 frag->data = val; 5425 frag->len = bytes; 5426 return X86EMUL_CONTINUE; 5427 } 5428 5429 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 5430 unsigned long addr, 5431 void *val, unsigned int bytes, 5432 struct x86_exception *exception, 5433 const struct read_write_emulator_ops *ops) 5434 { 5435 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5436 gpa_t gpa; 5437 int rc; 5438 5439 if (ops->read_write_prepare && 5440 ops->read_write_prepare(vcpu, val, bytes)) 5441 return X86EMUL_CONTINUE; 5442 5443 vcpu->mmio_nr_fragments = 0; 5444 5445 /* Crossing a page boundary? */ 5446 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 5447 int now; 5448 5449 now = -addr & ~PAGE_MASK; 5450 rc = emulator_read_write_onepage(addr, val, now, exception, 5451 vcpu, ops); 5452 5453 if (rc != X86EMUL_CONTINUE) 5454 return rc; 5455 addr += now; 5456 if (ctxt->mode != X86EMUL_MODE_PROT64) 5457 addr = (u32)addr; 5458 val += now; 5459 bytes -= now; 5460 } 5461 5462 rc = emulator_read_write_onepage(addr, val, bytes, exception, 5463 vcpu, ops); 5464 if (rc != X86EMUL_CONTINUE) 5465 return rc; 5466 5467 if (!vcpu->mmio_nr_fragments) 5468 return rc; 5469 5470 gpa = vcpu->mmio_fragments[0].gpa; 5471 5472 vcpu->mmio_needed = 1; 5473 vcpu->mmio_cur_fragment = 0; 5474 5475 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 5476 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 5477 vcpu->run->exit_reason = KVM_EXIT_MMIO; 5478 vcpu->run->mmio.phys_addr = gpa; 5479 5480 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 5481 } 5482 5483 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 5484 unsigned long addr, 5485 void *val, 5486 unsigned int bytes, 5487 struct x86_exception *exception) 5488 { 5489 return emulator_read_write(ctxt, addr, val, bytes, 5490 exception, &read_emultor); 5491 } 5492 5493 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 5494 unsigned long addr, 5495 const void *val, 5496 unsigned int bytes, 5497 struct x86_exception *exception) 5498 { 5499 return emulator_read_write(ctxt, addr, (void *)val, bytes, 5500 exception, &write_emultor); 5501 } 5502 5503 #define CMPXCHG_TYPE(t, ptr, old, new) \ 5504 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 5505 5506 #ifdef CONFIG_X86_64 5507 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 5508 #else 5509 # define CMPXCHG64(ptr, old, new) \ 5510 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 5511 #endif 5512 5513 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 5514 unsigned long addr, 5515 const void *old, 5516 const void *new, 5517 unsigned int bytes, 5518 struct x86_exception *exception) 5519 { 5520 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5521 gpa_t gpa; 5522 struct page *page; 5523 char *kaddr; 5524 bool exchanged; 5525 5526 /* guests cmpxchg8b have to be emulated atomically */ 5527 if (bytes > 8 || (bytes & (bytes - 1))) 5528 goto emul_write; 5529 5530 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 5531 5532 if (gpa == UNMAPPED_GVA || 5533 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 5534 goto emul_write; 5535 5536 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 5537 goto emul_write; 5538 5539 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); 5540 if (is_error_page(page)) 5541 goto emul_write; 5542 5543 kaddr = kmap_atomic(page); 5544 kaddr += offset_in_page(gpa); 5545 switch (bytes) { 5546 case 1: 5547 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 5548 break; 5549 case 2: 5550 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 5551 break; 5552 case 4: 5553 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 5554 break; 5555 case 8: 5556 exchanged = CMPXCHG64(kaddr, old, new); 5557 break; 5558 default: 5559 BUG(); 5560 } 5561 kunmap_atomic(kaddr); 5562 kvm_release_page_dirty(page); 5563 5564 if (!exchanged) 5565 return X86EMUL_CMPXCHG_FAILED; 5566 5567 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5568 kvm_page_track_write(vcpu, gpa, new, bytes); 5569 5570 return X86EMUL_CONTINUE; 5571 5572 emul_write: 5573 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 5574 5575 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 5576 } 5577 5578 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 5579 { 5580 int r = 0, i; 5581 5582 for (i = 0; i < vcpu->arch.pio.count; i++) { 5583 if (vcpu->arch.pio.in) 5584 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 5585 vcpu->arch.pio.size, pd); 5586 else 5587 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 5588 vcpu->arch.pio.port, vcpu->arch.pio.size, 5589 pd); 5590 if (r) 5591 break; 5592 pd += vcpu->arch.pio.size; 5593 } 5594 return r; 5595 } 5596 5597 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 5598 unsigned short port, void *val, 5599 unsigned int count, bool in) 5600 { 5601 vcpu->arch.pio.port = port; 5602 vcpu->arch.pio.in = in; 5603 vcpu->arch.pio.count = count; 5604 vcpu->arch.pio.size = size; 5605 5606 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 5607 vcpu->arch.pio.count = 0; 5608 return 1; 5609 } 5610 5611 vcpu->run->exit_reason = KVM_EXIT_IO; 5612 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 5613 vcpu->run->io.size = size; 5614 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 5615 vcpu->run->io.count = count; 5616 vcpu->run->io.port = port; 5617 5618 return 0; 5619 } 5620 5621 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 5622 int size, unsigned short port, void *val, 5623 unsigned int count) 5624 { 5625 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5626 int ret; 5627 5628 if (vcpu->arch.pio.count) 5629 goto data_avail; 5630 5631 memset(vcpu->arch.pio_data, 0, size * count); 5632 5633 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 5634 if (ret) { 5635 data_avail: 5636 memcpy(val, vcpu->arch.pio_data, size * count); 5637 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 5638 vcpu->arch.pio.count = 0; 5639 return 1; 5640 } 5641 5642 return 0; 5643 } 5644 5645 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 5646 int size, unsigned short port, 5647 const void *val, unsigned int count) 5648 { 5649 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5650 5651 memcpy(vcpu->arch.pio_data, val, size * count); 5652 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 5653 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 5654 } 5655 5656 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 5657 { 5658 return kvm_x86_ops->get_segment_base(vcpu, seg); 5659 } 5660 5661 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 5662 { 5663 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 5664 } 5665 5666 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 5667 { 5668 if (!need_emulate_wbinvd(vcpu)) 5669 return X86EMUL_CONTINUE; 5670 5671 if (kvm_x86_ops->has_wbinvd_exit()) { 5672 int cpu = get_cpu(); 5673 5674 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 5675 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 5676 wbinvd_ipi, NULL, 1); 5677 put_cpu(); 5678 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 5679 } else 5680 wbinvd(); 5681 return X86EMUL_CONTINUE; 5682 } 5683 5684 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 5685 { 5686 kvm_emulate_wbinvd_noskip(vcpu); 5687 return kvm_skip_emulated_instruction(vcpu); 5688 } 5689 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 5690 5691 5692 5693 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 5694 { 5695 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 5696 } 5697 5698 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 5699 unsigned long *dest) 5700 { 5701 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 5702 } 5703 5704 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 5705 unsigned long value) 5706 { 5707 5708 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 5709 } 5710 5711 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 5712 { 5713 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 5714 } 5715 5716 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 5717 { 5718 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5719 unsigned long value; 5720 5721 switch (cr) { 5722 case 0: 5723 value = kvm_read_cr0(vcpu); 5724 break; 5725 case 2: 5726 value = vcpu->arch.cr2; 5727 break; 5728 case 3: 5729 value = kvm_read_cr3(vcpu); 5730 break; 5731 case 4: 5732 value = kvm_read_cr4(vcpu); 5733 break; 5734 case 8: 5735 value = kvm_get_cr8(vcpu); 5736 break; 5737 default: 5738 kvm_err("%s: unexpected cr %u\n", __func__, cr); 5739 return 0; 5740 } 5741 5742 return value; 5743 } 5744 5745 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 5746 { 5747 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5748 int res = 0; 5749 5750 switch (cr) { 5751 case 0: 5752 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 5753 break; 5754 case 2: 5755 vcpu->arch.cr2 = val; 5756 break; 5757 case 3: 5758 res = kvm_set_cr3(vcpu, val); 5759 break; 5760 case 4: 5761 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 5762 break; 5763 case 8: 5764 res = kvm_set_cr8(vcpu, val); 5765 break; 5766 default: 5767 kvm_err("%s: unexpected cr %u\n", __func__, cr); 5768 res = -1; 5769 } 5770 5771 return res; 5772 } 5773 5774 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 5775 { 5776 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 5777 } 5778 5779 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5780 { 5781 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 5782 } 5783 5784 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5785 { 5786 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 5787 } 5788 5789 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5790 { 5791 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 5792 } 5793 5794 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5795 { 5796 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 5797 } 5798 5799 static unsigned long emulator_get_cached_segment_base( 5800 struct x86_emulate_ctxt *ctxt, int seg) 5801 { 5802 return get_segment_base(emul_to_vcpu(ctxt), seg); 5803 } 5804 5805 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 5806 struct desc_struct *desc, u32 *base3, 5807 int seg) 5808 { 5809 struct kvm_segment var; 5810 5811 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 5812 *selector = var.selector; 5813 5814 if (var.unusable) { 5815 memset(desc, 0, sizeof(*desc)); 5816 if (base3) 5817 *base3 = 0; 5818 return false; 5819 } 5820 5821 if (var.g) 5822 var.limit >>= 12; 5823 set_desc_limit(desc, var.limit); 5824 set_desc_base(desc, (unsigned long)var.base); 5825 #ifdef CONFIG_X86_64 5826 if (base3) 5827 *base3 = var.base >> 32; 5828 #endif 5829 desc->type = var.type; 5830 desc->s = var.s; 5831 desc->dpl = var.dpl; 5832 desc->p = var.present; 5833 desc->avl = var.avl; 5834 desc->l = var.l; 5835 desc->d = var.db; 5836 desc->g = var.g; 5837 5838 return true; 5839 } 5840 5841 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 5842 struct desc_struct *desc, u32 base3, 5843 int seg) 5844 { 5845 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5846 struct kvm_segment var; 5847 5848 var.selector = selector; 5849 var.base = get_desc_base(desc); 5850 #ifdef CONFIG_X86_64 5851 var.base |= ((u64)base3) << 32; 5852 #endif 5853 var.limit = get_desc_limit(desc); 5854 if (desc->g) 5855 var.limit = (var.limit << 12) | 0xfff; 5856 var.type = desc->type; 5857 var.dpl = desc->dpl; 5858 var.db = desc->d; 5859 var.s = desc->s; 5860 var.l = desc->l; 5861 var.g = desc->g; 5862 var.avl = desc->avl; 5863 var.present = desc->p; 5864 var.unusable = !var.present; 5865 var.padding = 0; 5866 5867 kvm_set_segment(vcpu, &var, seg); 5868 return; 5869 } 5870 5871 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 5872 u32 msr_index, u64 *pdata) 5873 { 5874 struct msr_data msr; 5875 int r; 5876 5877 msr.index = msr_index; 5878 msr.host_initiated = false; 5879 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); 5880 if (r) 5881 return r; 5882 5883 *pdata = msr.data; 5884 return 0; 5885 } 5886 5887 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 5888 u32 msr_index, u64 data) 5889 { 5890 struct msr_data msr; 5891 5892 msr.data = data; 5893 msr.index = msr_index; 5894 msr.host_initiated = false; 5895 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 5896 } 5897 5898 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 5899 { 5900 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5901 5902 return vcpu->arch.smbase; 5903 } 5904 5905 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 5906 { 5907 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5908 5909 vcpu->arch.smbase = smbase; 5910 } 5911 5912 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 5913 u32 pmc) 5914 { 5915 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); 5916 } 5917 5918 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 5919 u32 pmc, u64 *pdata) 5920 { 5921 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 5922 } 5923 5924 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 5925 { 5926 emul_to_vcpu(ctxt)->arch.halt_request = 1; 5927 } 5928 5929 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 5930 struct x86_instruction_info *info, 5931 enum x86_intercept_stage stage) 5932 { 5933 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 5934 } 5935 5936 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 5937 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit) 5938 { 5939 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit); 5940 } 5941 5942 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 5943 { 5944 return kvm_register_read(emul_to_vcpu(ctxt), reg); 5945 } 5946 5947 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 5948 { 5949 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 5950 } 5951 5952 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 5953 { 5954 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 5955 } 5956 5957 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 5958 { 5959 return emul_to_vcpu(ctxt)->arch.hflags; 5960 } 5961 5962 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) 5963 { 5964 emul_to_vcpu(ctxt)->arch.hflags = emul_flags; 5965 } 5966 5967 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, 5968 const char *smstate) 5969 { 5970 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate); 5971 } 5972 5973 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) 5974 { 5975 kvm_smm_changed(emul_to_vcpu(ctxt)); 5976 } 5977 5978 static const struct x86_emulate_ops emulate_ops = { 5979 .read_gpr = emulator_read_gpr, 5980 .write_gpr = emulator_write_gpr, 5981 .read_std = emulator_read_std, 5982 .write_std = emulator_write_std, 5983 .read_phys = kvm_read_guest_phys_system, 5984 .fetch = kvm_fetch_guest_virt, 5985 .read_emulated = emulator_read_emulated, 5986 .write_emulated = emulator_write_emulated, 5987 .cmpxchg_emulated = emulator_cmpxchg_emulated, 5988 .invlpg = emulator_invlpg, 5989 .pio_in_emulated = emulator_pio_in_emulated, 5990 .pio_out_emulated = emulator_pio_out_emulated, 5991 .get_segment = emulator_get_segment, 5992 .set_segment = emulator_set_segment, 5993 .get_cached_segment_base = emulator_get_cached_segment_base, 5994 .get_gdt = emulator_get_gdt, 5995 .get_idt = emulator_get_idt, 5996 .set_gdt = emulator_set_gdt, 5997 .set_idt = emulator_set_idt, 5998 .get_cr = emulator_get_cr, 5999 .set_cr = emulator_set_cr, 6000 .cpl = emulator_get_cpl, 6001 .get_dr = emulator_get_dr, 6002 .set_dr = emulator_set_dr, 6003 .get_smbase = emulator_get_smbase, 6004 .set_smbase = emulator_set_smbase, 6005 .set_msr = emulator_set_msr, 6006 .get_msr = emulator_get_msr, 6007 .check_pmc = emulator_check_pmc, 6008 .read_pmc = emulator_read_pmc, 6009 .halt = emulator_halt, 6010 .wbinvd = emulator_wbinvd, 6011 .fix_hypercall = emulator_fix_hypercall, 6012 .intercept = emulator_intercept, 6013 .get_cpuid = emulator_get_cpuid, 6014 .set_nmi_mask = emulator_set_nmi_mask, 6015 .get_hflags = emulator_get_hflags, 6016 .set_hflags = emulator_set_hflags, 6017 .pre_leave_smm = emulator_pre_leave_smm, 6018 .post_leave_smm = emulator_post_leave_smm, 6019 }; 6020 6021 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 6022 { 6023 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 6024 /* 6025 * an sti; sti; sequence only disable interrupts for the first 6026 * instruction. So, if the last instruction, be it emulated or 6027 * not, left the system with the INT_STI flag enabled, it 6028 * means that the last instruction is an sti. We should not 6029 * leave the flag on in this case. The same goes for mov ss 6030 */ 6031 if (int_shadow & mask) 6032 mask = 0; 6033 if (unlikely(int_shadow || mask)) { 6034 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 6035 if (!mask) 6036 kvm_make_request(KVM_REQ_EVENT, vcpu); 6037 } 6038 } 6039 6040 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 6041 { 6042 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6043 if (ctxt->exception.vector == PF_VECTOR) 6044 return kvm_propagate_fault(vcpu, &ctxt->exception); 6045 6046 if (ctxt->exception.error_code_valid) 6047 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 6048 ctxt->exception.error_code); 6049 else 6050 kvm_queue_exception(vcpu, ctxt->exception.vector); 6051 return false; 6052 } 6053 6054 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 6055 { 6056 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6057 int cs_db, cs_l; 6058 6059 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 6060 6061 ctxt->eflags = kvm_get_rflags(vcpu); 6062 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 6063 6064 ctxt->eip = kvm_rip_read(vcpu); 6065 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 6066 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 6067 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 6068 cs_db ? X86EMUL_MODE_PROT32 : 6069 X86EMUL_MODE_PROT16; 6070 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 6071 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 6072 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 6073 6074 init_decode_cache(ctxt); 6075 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 6076 } 6077 6078 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 6079 { 6080 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6081 int ret; 6082 6083 init_emulate_ctxt(vcpu); 6084 6085 ctxt->op_bytes = 2; 6086 ctxt->ad_bytes = 2; 6087 ctxt->_eip = ctxt->eip + inc_eip; 6088 ret = emulate_int_real(ctxt, irq); 6089 6090 if (ret != X86EMUL_CONTINUE) 6091 return EMULATE_FAIL; 6092 6093 ctxt->eip = ctxt->_eip; 6094 kvm_rip_write(vcpu, ctxt->eip); 6095 kvm_set_rflags(vcpu, ctxt->eflags); 6096 6097 return EMULATE_DONE; 6098 } 6099 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 6100 6101 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 6102 { 6103 int r = EMULATE_DONE; 6104 6105 ++vcpu->stat.insn_emulation_fail; 6106 trace_kvm_emulate_insn_failed(vcpu); 6107 6108 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL) 6109 return EMULATE_FAIL; 6110 6111 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 6112 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 6113 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 6114 vcpu->run->internal.ndata = 0; 6115 r = EMULATE_USER_EXIT; 6116 } 6117 6118 kvm_queue_exception(vcpu, UD_VECTOR); 6119 6120 return r; 6121 } 6122 6123 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 6124 bool write_fault_to_shadow_pgtable, 6125 int emulation_type) 6126 { 6127 gpa_t gpa = cr2; 6128 kvm_pfn_t pfn; 6129 6130 if (!(emulation_type & EMULTYPE_ALLOW_RETRY)) 6131 return false; 6132 6133 if (WARN_ON_ONCE(is_guest_mode(vcpu))) 6134 return false; 6135 6136 if (!vcpu->arch.mmu->direct_map) { 6137 /* 6138 * Write permission should be allowed since only 6139 * write access need to be emulated. 6140 */ 6141 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 6142 6143 /* 6144 * If the mapping is invalid in guest, let cpu retry 6145 * it to generate fault. 6146 */ 6147 if (gpa == UNMAPPED_GVA) 6148 return true; 6149 } 6150 6151 /* 6152 * Do not retry the unhandleable instruction if it faults on the 6153 * readonly host memory, otherwise it will goto a infinite loop: 6154 * retry instruction -> write #PF -> emulation fail -> retry 6155 * instruction -> ... 6156 */ 6157 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 6158 6159 /* 6160 * If the instruction failed on the error pfn, it can not be fixed, 6161 * report the error to userspace. 6162 */ 6163 if (is_error_noslot_pfn(pfn)) 6164 return false; 6165 6166 kvm_release_pfn_clean(pfn); 6167 6168 /* The instructions are well-emulated on direct mmu. */ 6169 if (vcpu->arch.mmu->direct_map) { 6170 unsigned int indirect_shadow_pages; 6171 6172 spin_lock(&vcpu->kvm->mmu_lock); 6173 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 6174 spin_unlock(&vcpu->kvm->mmu_lock); 6175 6176 if (indirect_shadow_pages) 6177 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 6178 6179 return true; 6180 } 6181 6182 /* 6183 * if emulation was due to access to shadowed page table 6184 * and it failed try to unshadow page and re-enter the 6185 * guest to let CPU execute the instruction. 6186 */ 6187 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 6188 6189 /* 6190 * If the access faults on its page table, it can not 6191 * be fixed by unprotecting shadow page and it should 6192 * be reported to userspace. 6193 */ 6194 return !write_fault_to_shadow_pgtable; 6195 } 6196 6197 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 6198 unsigned long cr2, int emulation_type) 6199 { 6200 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6201 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 6202 6203 last_retry_eip = vcpu->arch.last_retry_eip; 6204 last_retry_addr = vcpu->arch.last_retry_addr; 6205 6206 /* 6207 * If the emulation is caused by #PF and it is non-page_table 6208 * writing instruction, it means the VM-EXIT is caused by shadow 6209 * page protected, we can zap the shadow page and retry this 6210 * instruction directly. 6211 * 6212 * Note: if the guest uses a non-page-table modifying instruction 6213 * on the PDE that points to the instruction, then we will unmap 6214 * the instruction and go to an infinite loop. So, we cache the 6215 * last retried eip and the last fault address, if we meet the eip 6216 * and the address again, we can break out of the potential infinite 6217 * loop. 6218 */ 6219 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 6220 6221 if (!(emulation_type & EMULTYPE_ALLOW_RETRY)) 6222 return false; 6223 6224 if (WARN_ON_ONCE(is_guest_mode(vcpu))) 6225 return false; 6226 6227 if (x86_page_table_writing_insn(ctxt)) 6228 return false; 6229 6230 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 6231 return false; 6232 6233 vcpu->arch.last_retry_eip = ctxt->eip; 6234 vcpu->arch.last_retry_addr = cr2; 6235 6236 if (!vcpu->arch.mmu->direct_map) 6237 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 6238 6239 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 6240 6241 return true; 6242 } 6243 6244 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 6245 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 6246 6247 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 6248 { 6249 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 6250 /* This is a good place to trace that we are exiting SMM. */ 6251 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 6252 6253 /* Process a latched INIT or SMI, if any. */ 6254 kvm_make_request(KVM_REQ_EVENT, vcpu); 6255 } 6256 6257 kvm_mmu_reset_context(vcpu); 6258 } 6259 6260 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 6261 unsigned long *db) 6262 { 6263 u32 dr6 = 0; 6264 int i; 6265 u32 enable, rwlen; 6266 6267 enable = dr7; 6268 rwlen = dr7 >> 16; 6269 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 6270 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 6271 dr6 |= (1 << i); 6272 return dr6; 6273 } 6274 6275 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r) 6276 { 6277 struct kvm_run *kvm_run = vcpu->run; 6278 6279 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 6280 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; 6281 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 6282 kvm_run->debug.arch.exception = DB_VECTOR; 6283 kvm_run->exit_reason = KVM_EXIT_DEBUG; 6284 *r = EMULATE_USER_EXIT; 6285 } else { 6286 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 6287 } 6288 } 6289 6290 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 6291 { 6292 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 6293 int r = EMULATE_DONE; 6294 6295 kvm_x86_ops->skip_emulated_instruction(vcpu); 6296 6297 /* 6298 * rflags is the old, "raw" value of the flags. The new value has 6299 * not been saved yet. 6300 * 6301 * This is correct even for TF set by the guest, because "the 6302 * processor will not generate this exception after the instruction 6303 * that sets the TF flag". 6304 */ 6305 if (unlikely(rflags & X86_EFLAGS_TF)) 6306 kvm_vcpu_do_singlestep(vcpu, &r); 6307 return r == EMULATE_DONE; 6308 } 6309 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 6310 6311 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 6312 { 6313 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 6314 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 6315 struct kvm_run *kvm_run = vcpu->run; 6316 unsigned long eip = kvm_get_linear_rip(vcpu); 6317 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 6318 vcpu->arch.guest_debug_dr7, 6319 vcpu->arch.eff_db); 6320 6321 if (dr6 != 0) { 6322 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 6323 kvm_run->debug.arch.pc = eip; 6324 kvm_run->debug.arch.exception = DB_VECTOR; 6325 kvm_run->exit_reason = KVM_EXIT_DEBUG; 6326 *r = EMULATE_USER_EXIT; 6327 return true; 6328 } 6329 } 6330 6331 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 6332 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 6333 unsigned long eip = kvm_get_linear_rip(vcpu); 6334 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 6335 vcpu->arch.dr7, 6336 vcpu->arch.db); 6337 6338 if (dr6 != 0) { 6339 vcpu->arch.dr6 &= ~15; 6340 vcpu->arch.dr6 |= dr6 | DR6_RTM; 6341 kvm_queue_exception(vcpu, DB_VECTOR); 6342 *r = EMULATE_DONE; 6343 return true; 6344 } 6345 } 6346 6347 return false; 6348 } 6349 6350 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 6351 { 6352 switch (ctxt->opcode_len) { 6353 case 1: 6354 switch (ctxt->b) { 6355 case 0xe4: /* IN */ 6356 case 0xe5: 6357 case 0xec: 6358 case 0xed: 6359 case 0xe6: /* OUT */ 6360 case 0xe7: 6361 case 0xee: 6362 case 0xef: 6363 case 0x6c: /* INS */ 6364 case 0x6d: 6365 case 0x6e: /* OUTS */ 6366 case 0x6f: 6367 return true; 6368 } 6369 break; 6370 case 2: 6371 switch (ctxt->b) { 6372 case 0x33: /* RDPMC */ 6373 return true; 6374 } 6375 break; 6376 } 6377 6378 return false; 6379 } 6380 6381 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 6382 unsigned long cr2, 6383 int emulation_type, 6384 void *insn, 6385 int insn_len) 6386 { 6387 int r; 6388 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6389 bool writeback = true; 6390 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 6391 6392 vcpu->arch.l1tf_flush_l1d = true; 6393 6394 /* 6395 * Clear write_fault_to_shadow_pgtable here to ensure it is 6396 * never reused. 6397 */ 6398 vcpu->arch.write_fault_to_shadow_pgtable = false; 6399 kvm_clear_exception_queue(vcpu); 6400 6401 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 6402 init_emulate_ctxt(vcpu); 6403 6404 /* 6405 * We will reenter on the same instruction since 6406 * we do not set complete_userspace_io. This does not 6407 * handle watchpoints yet, those would be handled in 6408 * the emulate_ops. 6409 */ 6410 if (!(emulation_type & EMULTYPE_SKIP) && 6411 kvm_vcpu_check_breakpoint(vcpu, &r)) 6412 return r; 6413 6414 ctxt->interruptibility = 0; 6415 ctxt->have_exception = false; 6416 ctxt->exception.vector = -1; 6417 ctxt->perm_ok = false; 6418 6419 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 6420 6421 r = x86_decode_insn(ctxt, insn, insn_len); 6422 6423 trace_kvm_emulate_insn_start(vcpu); 6424 ++vcpu->stat.insn_emulation; 6425 if (r != EMULATION_OK) { 6426 if (emulation_type & EMULTYPE_TRAP_UD) 6427 return EMULATE_FAIL; 6428 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 6429 emulation_type)) 6430 return EMULATE_DONE; 6431 if (ctxt->have_exception && inject_emulated_exception(vcpu)) 6432 return EMULATE_DONE; 6433 if (emulation_type & EMULTYPE_SKIP) 6434 return EMULATE_FAIL; 6435 return handle_emulation_failure(vcpu, emulation_type); 6436 } 6437 } 6438 6439 if ((emulation_type & EMULTYPE_VMWARE) && 6440 !is_vmware_backdoor_opcode(ctxt)) 6441 return EMULATE_FAIL; 6442 6443 if (emulation_type & EMULTYPE_SKIP) { 6444 kvm_rip_write(vcpu, ctxt->_eip); 6445 if (ctxt->eflags & X86_EFLAGS_RF) 6446 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 6447 return EMULATE_DONE; 6448 } 6449 6450 if (retry_instruction(ctxt, cr2, emulation_type)) 6451 return EMULATE_DONE; 6452 6453 /* this is needed for vmware backdoor interface to work since it 6454 changes registers values during IO operation */ 6455 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 6456 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 6457 emulator_invalidate_register_cache(ctxt); 6458 } 6459 6460 restart: 6461 /* Save the faulting GPA (cr2) in the address field */ 6462 ctxt->exception.address = cr2; 6463 6464 r = x86_emulate_insn(ctxt); 6465 6466 if (r == EMULATION_INTERCEPTED) 6467 return EMULATE_DONE; 6468 6469 if (r == EMULATION_FAILED) { 6470 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 6471 emulation_type)) 6472 return EMULATE_DONE; 6473 6474 return handle_emulation_failure(vcpu, emulation_type); 6475 } 6476 6477 if (ctxt->have_exception) { 6478 r = EMULATE_DONE; 6479 if (inject_emulated_exception(vcpu)) 6480 return r; 6481 } else if (vcpu->arch.pio.count) { 6482 if (!vcpu->arch.pio.in) { 6483 /* FIXME: return into emulator if single-stepping. */ 6484 vcpu->arch.pio.count = 0; 6485 } else { 6486 writeback = false; 6487 vcpu->arch.complete_userspace_io = complete_emulated_pio; 6488 } 6489 r = EMULATE_USER_EXIT; 6490 } else if (vcpu->mmio_needed) { 6491 if (!vcpu->mmio_is_write) 6492 writeback = false; 6493 r = EMULATE_USER_EXIT; 6494 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6495 } else if (r == EMULATION_RESTART) 6496 goto restart; 6497 else 6498 r = EMULATE_DONE; 6499 6500 if (writeback) { 6501 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 6502 toggle_interruptibility(vcpu, ctxt->interruptibility); 6503 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6504 kvm_rip_write(vcpu, ctxt->eip); 6505 if (r == EMULATE_DONE && ctxt->tf) 6506 kvm_vcpu_do_singlestep(vcpu, &r); 6507 if (!ctxt->have_exception || 6508 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 6509 __kvm_set_rflags(vcpu, ctxt->eflags); 6510 6511 /* 6512 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 6513 * do nothing, and it will be requested again as soon as 6514 * the shadow expires. But we still need to check here, 6515 * because POPF has no interrupt shadow. 6516 */ 6517 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 6518 kvm_make_request(KVM_REQ_EVENT, vcpu); 6519 } else 6520 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 6521 6522 return r; 6523 } 6524 6525 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 6526 { 6527 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 6528 } 6529 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 6530 6531 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 6532 void *insn, int insn_len) 6533 { 6534 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 6535 } 6536 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 6537 6538 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 6539 { 6540 vcpu->arch.pio.count = 0; 6541 6542 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 6543 return 1; 6544 6545 return kvm_skip_emulated_instruction(vcpu); 6546 } 6547 6548 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 6549 unsigned short port) 6550 { 6551 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 6552 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 6553 size, port, &val, 1); 6554 6555 if (!ret) { 6556 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 6557 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 6558 } 6559 return ret; 6560 } 6561 6562 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 6563 { 6564 unsigned long val; 6565 6566 /* We should only ever be called with arch.pio.count equal to 1 */ 6567 BUG_ON(vcpu->arch.pio.count != 1); 6568 6569 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 6570 vcpu->arch.pio.count = 0; 6571 return 1; 6572 } 6573 6574 /* For size less than 4 we merge, else we zero extend */ 6575 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) 6576 : 0; 6577 6578 /* 6579 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform 6580 * the copy and tracing 6581 */ 6582 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size, 6583 vcpu->arch.pio.port, &val, 1); 6584 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 6585 6586 return kvm_skip_emulated_instruction(vcpu); 6587 } 6588 6589 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 6590 unsigned short port) 6591 { 6592 unsigned long val; 6593 int ret; 6594 6595 /* For size less than 4 we merge, else we zero extend */ 6596 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0; 6597 6598 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port, 6599 &val, 1); 6600 if (ret) { 6601 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 6602 return ret; 6603 } 6604 6605 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 6606 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 6607 6608 return 0; 6609 } 6610 6611 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 6612 { 6613 int ret; 6614 6615 if (in) 6616 ret = kvm_fast_pio_in(vcpu, size, port); 6617 else 6618 ret = kvm_fast_pio_out(vcpu, size, port); 6619 return ret && kvm_skip_emulated_instruction(vcpu); 6620 } 6621 EXPORT_SYMBOL_GPL(kvm_fast_pio); 6622 6623 static int kvmclock_cpu_down_prep(unsigned int cpu) 6624 { 6625 __this_cpu_write(cpu_tsc_khz, 0); 6626 return 0; 6627 } 6628 6629 static void tsc_khz_changed(void *data) 6630 { 6631 struct cpufreq_freqs *freq = data; 6632 unsigned long khz = 0; 6633 6634 if (data) 6635 khz = freq->new; 6636 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 6637 khz = cpufreq_quick_get(raw_smp_processor_id()); 6638 if (!khz) 6639 khz = tsc_khz; 6640 __this_cpu_write(cpu_tsc_khz, khz); 6641 } 6642 6643 #ifdef CONFIG_X86_64 6644 static void kvm_hyperv_tsc_notifier(void) 6645 { 6646 struct kvm *kvm; 6647 struct kvm_vcpu *vcpu; 6648 int cpu; 6649 6650 spin_lock(&kvm_lock); 6651 list_for_each_entry(kvm, &vm_list, vm_list) 6652 kvm_make_mclock_inprogress_request(kvm); 6653 6654 hyperv_stop_tsc_emulation(); 6655 6656 /* TSC frequency always matches when on Hyper-V */ 6657 for_each_present_cpu(cpu) 6658 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 6659 kvm_max_guest_tsc_khz = tsc_khz; 6660 6661 list_for_each_entry(kvm, &vm_list, vm_list) { 6662 struct kvm_arch *ka = &kvm->arch; 6663 6664 spin_lock(&ka->pvclock_gtod_sync_lock); 6665 6666 pvclock_update_vm_gtod_copy(kvm); 6667 6668 kvm_for_each_vcpu(cpu, vcpu, kvm) 6669 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6670 6671 kvm_for_each_vcpu(cpu, vcpu, kvm) 6672 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 6673 6674 spin_unlock(&ka->pvclock_gtod_sync_lock); 6675 } 6676 spin_unlock(&kvm_lock); 6677 } 6678 #endif 6679 6680 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 6681 void *data) 6682 { 6683 struct cpufreq_freqs *freq = data; 6684 struct kvm *kvm; 6685 struct kvm_vcpu *vcpu; 6686 int i, send_ipi = 0; 6687 6688 /* 6689 * We allow guests to temporarily run on slowing clocks, 6690 * provided we notify them after, or to run on accelerating 6691 * clocks, provided we notify them before. Thus time never 6692 * goes backwards. 6693 * 6694 * However, we have a problem. We can't atomically update 6695 * the frequency of a given CPU from this function; it is 6696 * merely a notifier, which can be called from any CPU. 6697 * Changing the TSC frequency at arbitrary points in time 6698 * requires a recomputation of local variables related to 6699 * the TSC for each VCPU. We must flag these local variables 6700 * to be updated and be sure the update takes place with the 6701 * new frequency before any guests proceed. 6702 * 6703 * Unfortunately, the combination of hotplug CPU and frequency 6704 * change creates an intractable locking scenario; the order 6705 * of when these callouts happen is undefined with respect to 6706 * CPU hotplug, and they can race with each other. As such, 6707 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 6708 * undefined; you can actually have a CPU frequency change take 6709 * place in between the computation of X and the setting of the 6710 * variable. To protect against this problem, all updates of 6711 * the per_cpu tsc_khz variable are done in an interrupt 6712 * protected IPI, and all callers wishing to update the value 6713 * must wait for a synchronous IPI to complete (which is trivial 6714 * if the caller is on the CPU already). This establishes the 6715 * necessary total order on variable updates. 6716 * 6717 * Note that because a guest time update may take place 6718 * anytime after the setting of the VCPU's request bit, the 6719 * correct TSC value must be set before the request. However, 6720 * to ensure the update actually makes it to any guest which 6721 * starts running in hardware virtualization between the set 6722 * and the acquisition of the spinlock, we must also ping the 6723 * CPU after setting the request bit. 6724 * 6725 */ 6726 6727 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 6728 return 0; 6729 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 6730 return 0; 6731 6732 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 6733 6734 spin_lock(&kvm_lock); 6735 list_for_each_entry(kvm, &vm_list, vm_list) { 6736 kvm_for_each_vcpu(i, vcpu, kvm) { 6737 if (vcpu->cpu != freq->cpu) 6738 continue; 6739 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6740 if (vcpu->cpu != smp_processor_id()) 6741 send_ipi = 1; 6742 } 6743 } 6744 spin_unlock(&kvm_lock); 6745 6746 if (freq->old < freq->new && send_ipi) { 6747 /* 6748 * We upscale the frequency. Must make the guest 6749 * doesn't see old kvmclock values while running with 6750 * the new frequency, otherwise we risk the guest sees 6751 * time go backwards. 6752 * 6753 * In case we update the frequency for another cpu 6754 * (which might be in guest context) send an interrupt 6755 * to kick the cpu out of guest context. Next time 6756 * guest context is entered kvmclock will be updated, 6757 * so the guest will not see stale values. 6758 */ 6759 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 6760 } 6761 return 0; 6762 } 6763 6764 static struct notifier_block kvmclock_cpufreq_notifier_block = { 6765 .notifier_call = kvmclock_cpufreq_notifier 6766 }; 6767 6768 static int kvmclock_cpu_online(unsigned int cpu) 6769 { 6770 tsc_khz_changed(NULL); 6771 return 0; 6772 } 6773 6774 static void kvm_timer_init(void) 6775 { 6776 max_tsc_khz = tsc_khz; 6777 6778 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 6779 #ifdef CONFIG_CPU_FREQ 6780 struct cpufreq_policy policy; 6781 int cpu; 6782 6783 memset(&policy, 0, sizeof(policy)); 6784 cpu = get_cpu(); 6785 cpufreq_get_policy(&policy, cpu); 6786 if (policy.cpuinfo.max_freq) 6787 max_tsc_khz = policy.cpuinfo.max_freq; 6788 put_cpu(); 6789 #endif 6790 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 6791 CPUFREQ_TRANSITION_NOTIFIER); 6792 } 6793 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 6794 6795 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 6796 kvmclock_cpu_online, kvmclock_cpu_down_prep); 6797 } 6798 6799 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 6800 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); 6801 6802 int kvm_is_in_guest(void) 6803 { 6804 return __this_cpu_read(current_vcpu) != NULL; 6805 } 6806 6807 static int kvm_is_user_mode(void) 6808 { 6809 int user_mode = 3; 6810 6811 if (__this_cpu_read(current_vcpu)) 6812 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 6813 6814 return user_mode != 0; 6815 } 6816 6817 static unsigned long kvm_get_guest_ip(void) 6818 { 6819 unsigned long ip = 0; 6820 6821 if (__this_cpu_read(current_vcpu)) 6822 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 6823 6824 return ip; 6825 } 6826 6827 static struct perf_guest_info_callbacks kvm_guest_cbs = { 6828 .is_in_guest = kvm_is_in_guest, 6829 .is_user_mode = kvm_is_user_mode, 6830 .get_guest_ip = kvm_get_guest_ip, 6831 }; 6832 6833 static void kvm_set_mmio_spte_mask(void) 6834 { 6835 u64 mask; 6836 int maxphyaddr = boot_cpu_data.x86_phys_bits; 6837 6838 /* 6839 * Set the reserved bits and the present bit of an paging-structure 6840 * entry to generate page fault with PFER.RSV = 1. 6841 */ 6842 6843 /* 6844 * Mask the uppermost physical address bit, which would be reserved as 6845 * long as the supported physical address width is less than 52. 6846 */ 6847 mask = 1ull << 51; 6848 6849 /* Set the present bit. */ 6850 mask |= 1ull; 6851 6852 /* 6853 * If reserved bit is not supported, clear the present bit to disable 6854 * mmio page fault. 6855 */ 6856 if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52) 6857 mask &= ~1ull; 6858 6859 kvm_mmu_set_mmio_spte_mask(mask, mask); 6860 } 6861 6862 #ifdef CONFIG_X86_64 6863 static void pvclock_gtod_update_fn(struct work_struct *work) 6864 { 6865 struct kvm *kvm; 6866 6867 struct kvm_vcpu *vcpu; 6868 int i; 6869 6870 spin_lock(&kvm_lock); 6871 list_for_each_entry(kvm, &vm_list, vm_list) 6872 kvm_for_each_vcpu(i, vcpu, kvm) 6873 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 6874 atomic_set(&kvm_guest_has_master_clock, 0); 6875 spin_unlock(&kvm_lock); 6876 } 6877 6878 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 6879 6880 /* 6881 * Notification about pvclock gtod data update. 6882 */ 6883 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 6884 void *priv) 6885 { 6886 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 6887 struct timekeeper *tk = priv; 6888 6889 update_pvclock_gtod(tk); 6890 6891 /* disable master clock if host does not trust, or does not 6892 * use, TSC based clocksource. 6893 */ 6894 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 6895 atomic_read(&kvm_guest_has_master_clock) != 0) 6896 queue_work(system_long_wq, &pvclock_gtod_work); 6897 6898 return 0; 6899 } 6900 6901 static struct notifier_block pvclock_gtod_notifier = { 6902 .notifier_call = pvclock_gtod_notify, 6903 }; 6904 #endif 6905 6906 int kvm_arch_init(void *opaque) 6907 { 6908 int r; 6909 struct kvm_x86_ops *ops = opaque; 6910 6911 if (kvm_x86_ops) { 6912 printk(KERN_ERR "kvm: already loaded the other module\n"); 6913 r = -EEXIST; 6914 goto out; 6915 } 6916 6917 if (!ops->cpu_has_kvm_support()) { 6918 printk(KERN_ERR "kvm: no hardware support\n"); 6919 r = -EOPNOTSUPP; 6920 goto out; 6921 } 6922 if (ops->disabled_by_bios()) { 6923 printk(KERN_ERR "kvm: disabled by bios\n"); 6924 r = -EOPNOTSUPP; 6925 goto out; 6926 } 6927 6928 /* 6929 * KVM explicitly assumes that the guest has an FPU and 6930 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 6931 * vCPU's FPU state as a fxregs_state struct. 6932 */ 6933 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 6934 printk(KERN_ERR "kvm: inadequate fpu\n"); 6935 r = -EOPNOTSUPP; 6936 goto out; 6937 } 6938 6939 r = -ENOMEM; 6940 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), 6941 __alignof__(struct fpu), SLAB_ACCOUNT, 6942 NULL); 6943 if (!x86_fpu_cache) { 6944 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); 6945 goto out; 6946 } 6947 6948 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 6949 if (!shared_msrs) { 6950 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 6951 goto out_free_x86_fpu_cache; 6952 } 6953 6954 r = kvm_mmu_module_init(); 6955 if (r) 6956 goto out_free_percpu; 6957 6958 kvm_set_mmio_spte_mask(); 6959 6960 kvm_x86_ops = ops; 6961 6962 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 6963 PT_DIRTY_MASK, PT64_NX_MASK, 0, 6964 PT_PRESENT_MASK, 0, sme_me_mask); 6965 kvm_timer_init(); 6966 6967 perf_register_guest_info_callbacks(&kvm_guest_cbs); 6968 6969 if (boot_cpu_has(X86_FEATURE_XSAVE)) 6970 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 6971 6972 kvm_lapic_init(); 6973 #ifdef CONFIG_X86_64 6974 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 6975 6976 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 6977 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 6978 #endif 6979 6980 return 0; 6981 6982 out_free_percpu: 6983 free_percpu(shared_msrs); 6984 out_free_x86_fpu_cache: 6985 kmem_cache_destroy(x86_fpu_cache); 6986 out: 6987 return r; 6988 } 6989 6990 void kvm_arch_exit(void) 6991 { 6992 #ifdef CONFIG_X86_64 6993 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 6994 clear_hv_tscchange_cb(); 6995 #endif 6996 kvm_lapic_exit(); 6997 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 6998 6999 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 7000 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 7001 CPUFREQ_TRANSITION_NOTIFIER); 7002 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 7003 #ifdef CONFIG_X86_64 7004 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 7005 #endif 7006 kvm_x86_ops = NULL; 7007 kvm_mmu_module_exit(); 7008 free_percpu(shared_msrs); 7009 kmem_cache_destroy(x86_fpu_cache); 7010 } 7011 7012 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 7013 { 7014 ++vcpu->stat.halt_exits; 7015 if (lapic_in_kernel(vcpu)) { 7016 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 7017 return 1; 7018 } else { 7019 vcpu->run->exit_reason = KVM_EXIT_HLT; 7020 return 0; 7021 } 7022 } 7023 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 7024 7025 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 7026 { 7027 int ret = kvm_skip_emulated_instruction(vcpu); 7028 /* 7029 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 7030 * KVM_EXIT_DEBUG here. 7031 */ 7032 return kvm_vcpu_halt(vcpu) && ret; 7033 } 7034 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 7035 7036 #ifdef CONFIG_X86_64 7037 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 7038 unsigned long clock_type) 7039 { 7040 struct kvm_clock_pairing clock_pairing; 7041 struct timespec64 ts; 7042 u64 cycle; 7043 int ret; 7044 7045 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 7046 return -KVM_EOPNOTSUPP; 7047 7048 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) 7049 return -KVM_EOPNOTSUPP; 7050 7051 clock_pairing.sec = ts.tv_sec; 7052 clock_pairing.nsec = ts.tv_nsec; 7053 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 7054 clock_pairing.flags = 0; 7055 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 7056 7057 ret = 0; 7058 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 7059 sizeof(struct kvm_clock_pairing))) 7060 ret = -KVM_EFAULT; 7061 7062 return ret; 7063 } 7064 #endif 7065 7066 /* 7067 * kvm_pv_kick_cpu_op: Kick a vcpu. 7068 * 7069 * @apicid - apicid of vcpu to be kicked. 7070 */ 7071 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 7072 { 7073 struct kvm_lapic_irq lapic_irq; 7074 7075 lapic_irq.shorthand = 0; 7076 lapic_irq.dest_mode = 0; 7077 lapic_irq.level = 0; 7078 lapic_irq.dest_id = apicid; 7079 lapic_irq.msi_redir_hint = false; 7080 7081 lapic_irq.delivery_mode = APIC_DM_REMRD; 7082 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 7083 } 7084 7085 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) 7086 { 7087 if (!lapic_in_kernel(vcpu)) { 7088 WARN_ON_ONCE(vcpu->arch.apicv_active); 7089 return; 7090 } 7091 if (!vcpu->arch.apicv_active) 7092 return; 7093 7094 vcpu->arch.apicv_active = false; 7095 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); 7096 } 7097 7098 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 7099 { 7100 unsigned long nr, a0, a1, a2, a3, ret; 7101 int op_64_bit; 7102 7103 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 7104 return kvm_hv_hypercall(vcpu); 7105 7106 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 7107 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 7108 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 7109 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 7110 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 7111 7112 trace_kvm_hypercall(nr, a0, a1, a2, a3); 7113 7114 op_64_bit = is_64_bit_mode(vcpu); 7115 if (!op_64_bit) { 7116 nr &= 0xFFFFFFFF; 7117 a0 &= 0xFFFFFFFF; 7118 a1 &= 0xFFFFFFFF; 7119 a2 &= 0xFFFFFFFF; 7120 a3 &= 0xFFFFFFFF; 7121 } 7122 7123 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 7124 ret = -KVM_EPERM; 7125 goto out; 7126 } 7127 7128 switch (nr) { 7129 case KVM_HC_VAPIC_POLL_IRQ: 7130 ret = 0; 7131 break; 7132 case KVM_HC_KICK_CPU: 7133 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 7134 ret = 0; 7135 break; 7136 #ifdef CONFIG_X86_64 7137 case KVM_HC_CLOCK_PAIRING: 7138 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 7139 break; 7140 #endif 7141 case KVM_HC_SEND_IPI: 7142 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 7143 break; 7144 default: 7145 ret = -KVM_ENOSYS; 7146 break; 7147 } 7148 out: 7149 if (!op_64_bit) 7150 ret = (u32)ret; 7151 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 7152 7153 ++vcpu->stat.hypercalls; 7154 return kvm_skip_emulated_instruction(vcpu); 7155 } 7156 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 7157 7158 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 7159 { 7160 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7161 char instruction[3]; 7162 unsigned long rip = kvm_rip_read(vcpu); 7163 7164 kvm_x86_ops->patch_hypercall(vcpu, instruction); 7165 7166 return emulator_write_emulated(ctxt, rip, instruction, 3, 7167 &ctxt->exception); 7168 } 7169 7170 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 7171 { 7172 return vcpu->run->request_interrupt_window && 7173 likely(!pic_in_kernel(vcpu->kvm)); 7174 } 7175 7176 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 7177 { 7178 struct kvm_run *kvm_run = vcpu->run; 7179 7180 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 7181 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 7182 kvm_run->cr8 = kvm_get_cr8(vcpu); 7183 kvm_run->apic_base = kvm_get_apic_base(vcpu); 7184 kvm_run->ready_for_interrupt_injection = 7185 pic_in_kernel(vcpu->kvm) || 7186 kvm_vcpu_ready_for_interrupt_injection(vcpu); 7187 } 7188 7189 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 7190 { 7191 int max_irr, tpr; 7192 7193 if (!kvm_x86_ops->update_cr8_intercept) 7194 return; 7195 7196 if (!lapic_in_kernel(vcpu)) 7197 return; 7198 7199 if (vcpu->arch.apicv_active) 7200 return; 7201 7202 if (!vcpu->arch.apic->vapic_addr) 7203 max_irr = kvm_lapic_find_highest_irr(vcpu); 7204 else 7205 max_irr = -1; 7206 7207 if (max_irr != -1) 7208 max_irr >>= 4; 7209 7210 tpr = kvm_lapic_get_cr8(vcpu); 7211 7212 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 7213 } 7214 7215 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 7216 { 7217 int r; 7218 7219 /* try to reinject previous events if any */ 7220 7221 if (vcpu->arch.exception.injected) 7222 kvm_x86_ops->queue_exception(vcpu); 7223 /* 7224 * Do not inject an NMI or interrupt if there is a pending 7225 * exception. Exceptions and interrupts are recognized at 7226 * instruction boundaries, i.e. the start of an instruction. 7227 * Trap-like exceptions, e.g. #DB, have higher priority than 7228 * NMIs and interrupts, i.e. traps are recognized before an 7229 * NMI/interrupt that's pending on the same instruction. 7230 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 7231 * priority, but are only generated (pended) during instruction 7232 * execution, i.e. a pending fault-like exception means the 7233 * fault occurred on the *previous* instruction and must be 7234 * serviced prior to recognizing any new events in order to 7235 * fully complete the previous instruction. 7236 */ 7237 else if (!vcpu->arch.exception.pending) { 7238 if (vcpu->arch.nmi_injected) 7239 kvm_x86_ops->set_nmi(vcpu); 7240 else if (vcpu->arch.interrupt.injected) 7241 kvm_x86_ops->set_irq(vcpu); 7242 } 7243 7244 /* 7245 * Call check_nested_events() even if we reinjected a previous event 7246 * in order for caller to determine if it should require immediate-exit 7247 * from L2 to L1 due to pending L1 events which require exit 7248 * from L2 to L1. 7249 */ 7250 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 7251 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 7252 if (r != 0) 7253 return r; 7254 } 7255 7256 /* try to inject new event if pending */ 7257 if (vcpu->arch.exception.pending) { 7258 trace_kvm_inj_exception(vcpu->arch.exception.nr, 7259 vcpu->arch.exception.has_error_code, 7260 vcpu->arch.exception.error_code); 7261 7262 WARN_ON_ONCE(vcpu->arch.exception.injected); 7263 vcpu->arch.exception.pending = false; 7264 vcpu->arch.exception.injected = true; 7265 7266 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 7267 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 7268 X86_EFLAGS_RF); 7269 7270 if (vcpu->arch.exception.nr == DB_VECTOR) { 7271 /* 7272 * This code assumes that nSVM doesn't use 7273 * check_nested_events(). If it does, the 7274 * DR6/DR7 changes should happen before L1 7275 * gets a #VMEXIT for an intercepted #DB in 7276 * L2. (Under VMX, on the other hand, the 7277 * DR6/DR7 changes should not happen in the 7278 * event of a VM-exit to L1 for an intercepted 7279 * #DB in L2.) 7280 */ 7281 kvm_deliver_exception_payload(vcpu); 7282 if (vcpu->arch.dr7 & DR7_GD) { 7283 vcpu->arch.dr7 &= ~DR7_GD; 7284 kvm_update_dr7(vcpu); 7285 } 7286 } 7287 7288 kvm_x86_ops->queue_exception(vcpu); 7289 } 7290 7291 /* Don't consider new event if we re-injected an event */ 7292 if (kvm_event_needs_reinjection(vcpu)) 7293 return 0; 7294 7295 if (vcpu->arch.smi_pending && !is_smm(vcpu) && 7296 kvm_x86_ops->smi_allowed(vcpu)) { 7297 vcpu->arch.smi_pending = false; 7298 ++vcpu->arch.smi_count; 7299 enter_smm(vcpu); 7300 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { 7301 --vcpu->arch.nmi_pending; 7302 vcpu->arch.nmi_injected = true; 7303 kvm_x86_ops->set_nmi(vcpu); 7304 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 7305 /* 7306 * Because interrupts can be injected asynchronously, we are 7307 * calling check_nested_events again here to avoid a race condition. 7308 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 7309 * proposal and current concerns. Perhaps we should be setting 7310 * KVM_REQ_EVENT only on certain events and not unconditionally? 7311 */ 7312 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 7313 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 7314 if (r != 0) 7315 return r; 7316 } 7317 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 7318 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 7319 false); 7320 kvm_x86_ops->set_irq(vcpu); 7321 } 7322 } 7323 7324 return 0; 7325 } 7326 7327 static void process_nmi(struct kvm_vcpu *vcpu) 7328 { 7329 unsigned limit = 2; 7330 7331 /* 7332 * x86 is limited to one NMI running, and one NMI pending after it. 7333 * If an NMI is already in progress, limit further NMIs to just one. 7334 * Otherwise, allow two (and we'll inject the first one immediately). 7335 */ 7336 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 7337 limit = 1; 7338 7339 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 7340 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 7341 kvm_make_request(KVM_REQ_EVENT, vcpu); 7342 } 7343 7344 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 7345 { 7346 u32 flags = 0; 7347 flags |= seg->g << 23; 7348 flags |= seg->db << 22; 7349 flags |= seg->l << 21; 7350 flags |= seg->avl << 20; 7351 flags |= seg->present << 15; 7352 flags |= seg->dpl << 13; 7353 flags |= seg->s << 12; 7354 flags |= seg->type << 8; 7355 return flags; 7356 } 7357 7358 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 7359 { 7360 struct kvm_segment seg; 7361 int offset; 7362 7363 kvm_get_segment(vcpu, &seg, n); 7364 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 7365 7366 if (n < 3) 7367 offset = 0x7f84 + n * 12; 7368 else 7369 offset = 0x7f2c + (n - 3) * 12; 7370 7371 put_smstate(u32, buf, offset + 8, seg.base); 7372 put_smstate(u32, buf, offset + 4, seg.limit); 7373 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 7374 } 7375 7376 #ifdef CONFIG_X86_64 7377 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 7378 { 7379 struct kvm_segment seg; 7380 int offset; 7381 u16 flags; 7382 7383 kvm_get_segment(vcpu, &seg, n); 7384 offset = 0x7e00 + n * 16; 7385 7386 flags = enter_smm_get_segment_flags(&seg) >> 8; 7387 put_smstate(u16, buf, offset, seg.selector); 7388 put_smstate(u16, buf, offset + 2, flags); 7389 put_smstate(u32, buf, offset + 4, seg.limit); 7390 put_smstate(u64, buf, offset + 8, seg.base); 7391 } 7392 #endif 7393 7394 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 7395 { 7396 struct desc_ptr dt; 7397 struct kvm_segment seg; 7398 unsigned long val; 7399 int i; 7400 7401 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 7402 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 7403 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 7404 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 7405 7406 for (i = 0; i < 8; i++) 7407 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 7408 7409 kvm_get_dr(vcpu, 6, &val); 7410 put_smstate(u32, buf, 0x7fcc, (u32)val); 7411 kvm_get_dr(vcpu, 7, &val); 7412 put_smstate(u32, buf, 0x7fc8, (u32)val); 7413 7414 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 7415 put_smstate(u32, buf, 0x7fc4, seg.selector); 7416 put_smstate(u32, buf, 0x7f64, seg.base); 7417 put_smstate(u32, buf, 0x7f60, seg.limit); 7418 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 7419 7420 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 7421 put_smstate(u32, buf, 0x7fc0, seg.selector); 7422 put_smstate(u32, buf, 0x7f80, seg.base); 7423 put_smstate(u32, buf, 0x7f7c, seg.limit); 7424 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 7425 7426 kvm_x86_ops->get_gdt(vcpu, &dt); 7427 put_smstate(u32, buf, 0x7f74, dt.address); 7428 put_smstate(u32, buf, 0x7f70, dt.size); 7429 7430 kvm_x86_ops->get_idt(vcpu, &dt); 7431 put_smstate(u32, buf, 0x7f58, dt.address); 7432 put_smstate(u32, buf, 0x7f54, dt.size); 7433 7434 for (i = 0; i < 6; i++) 7435 enter_smm_save_seg_32(vcpu, buf, i); 7436 7437 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 7438 7439 /* revision id */ 7440 put_smstate(u32, buf, 0x7efc, 0x00020000); 7441 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 7442 } 7443 7444 #ifdef CONFIG_X86_64 7445 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 7446 { 7447 struct desc_ptr dt; 7448 struct kvm_segment seg; 7449 unsigned long val; 7450 int i; 7451 7452 for (i = 0; i < 16; i++) 7453 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 7454 7455 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 7456 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 7457 7458 kvm_get_dr(vcpu, 6, &val); 7459 put_smstate(u64, buf, 0x7f68, val); 7460 kvm_get_dr(vcpu, 7, &val); 7461 put_smstate(u64, buf, 0x7f60, val); 7462 7463 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 7464 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 7465 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 7466 7467 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 7468 7469 /* revision id */ 7470 put_smstate(u32, buf, 0x7efc, 0x00020064); 7471 7472 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 7473 7474 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 7475 put_smstate(u16, buf, 0x7e90, seg.selector); 7476 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 7477 put_smstate(u32, buf, 0x7e94, seg.limit); 7478 put_smstate(u64, buf, 0x7e98, seg.base); 7479 7480 kvm_x86_ops->get_idt(vcpu, &dt); 7481 put_smstate(u32, buf, 0x7e84, dt.size); 7482 put_smstate(u64, buf, 0x7e88, dt.address); 7483 7484 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 7485 put_smstate(u16, buf, 0x7e70, seg.selector); 7486 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 7487 put_smstate(u32, buf, 0x7e74, seg.limit); 7488 put_smstate(u64, buf, 0x7e78, seg.base); 7489 7490 kvm_x86_ops->get_gdt(vcpu, &dt); 7491 put_smstate(u32, buf, 0x7e64, dt.size); 7492 put_smstate(u64, buf, 0x7e68, dt.address); 7493 7494 for (i = 0; i < 6; i++) 7495 enter_smm_save_seg_64(vcpu, buf, i); 7496 } 7497 #endif 7498 7499 static void enter_smm(struct kvm_vcpu *vcpu) 7500 { 7501 struct kvm_segment cs, ds; 7502 struct desc_ptr dt; 7503 char buf[512]; 7504 u32 cr0; 7505 7506 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 7507 memset(buf, 0, 512); 7508 #ifdef CONFIG_X86_64 7509 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 7510 enter_smm_save_state_64(vcpu, buf); 7511 else 7512 #endif 7513 enter_smm_save_state_32(vcpu, buf); 7514 7515 /* 7516 * Give pre_enter_smm() a chance to make ISA-specific changes to the 7517 * vCPU state (e.g. leave guest mode) after we've saved the state into 7518 * the SMM state-save area. 7519 */ 7520 kvm_x86_ops->pre_enter_smm(vcpu, buf); 7521 7522 vcpu->arch.hflags |= HF_SMM_MASK; 7523 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 7524 7525 if (kvm_x86_ops->get_nmi_mask(vcpu)) 7526 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 7527 else 7528 kvm_x86_ops->set_nmi_mask(vcpu, true); 7529 7530 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 7531 kvm_rip_write(vcpu, 0x8000); 7532 7533 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 7534 kvm_x86_ops->set_cr0(vcpu, cr0); 7535 vcpu->arch.cr0 = cr0; 7536 7537 kvm_x86_ops->set_cr4(vcpu, 0); 7538 7539 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 7540 dt.address = dt.size = 0; 7541 kvm_x86_ops->set_idt(vcpu, &dt); 7542 7543 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 7544 7545 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 7546 cs.base = vcpu->arch.smbase; 7547 7548 ds.selector = 0; 7549 ds.base = 0; 7550 7551 cs.limit = ds.limit = 0xffffffff; 7552 cs.type = ds.type = 0x3; 7553 cs.dpl = ds.dpl = 0; 7554 cs.db = ds.db = 0; 7555 cs.s = ds.s = 1; 7556 cs.l = ds.l = 0; 7557 cs.g = ds.g = 1; 7558 cs.avl = ds.avl = 0; 7559 cs.present = ds.present = 1; 7560 cs.unusable = ds.unusable = 0; 7561 cs.padding = ds.padding = 0; 7562 7563 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7564 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 7565 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 7566 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 7567 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 7568 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 7569 7570 #ifdef CONFIG_X86_64 7571 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 7572 kvm_x86_ops->set_efer(vcpu, 0); 7573 #endif 7574 7575 kvm_update_cpuid(vcpu); 7576 kvm_mmu_reset_context(vcpu); 7577 } 7578 7579 static void process_smi(struct kvm_vcpu *vcpu) 7580 { 7581 vcpu->arch.smi_pending = true; 7582 kvm_make_request(KVM_REQ_EVENT, vcpu); 7583 } 7584 7585 void kvm_make_scan_ioapic_request(struct kvm *kvm) 7586 { 7587 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 7588 } 7589 7590 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 7591 { 7592 if (!kvm_apic_present(vcpu)) 7593 return; 7594 7595 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 7596 7597 if (irqchip_split(vcpu->kvm)) 7598 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 7599 else { 7600 if (vcpu->arch.apicv_active) 7601 kvm_x86_ops->sync_pir_to_irr(vcpu); 7602 if (ioapic_in_kernel(vcpu->kvm)) 7603 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 7604 } 7605 7606 if (is_guest_mode(vcpu)) 7607 vcpu->arch.load_eoi_exitmap_pending = true; 7608 else 7609 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 7610 } 7611 7612 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 7613 { 7614 u64 eoi_exit_bitmap[4]; 7615 7616 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 7617 return; 7618 7619 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, 7620 vcpu_to_synic(vcpu)->vec_bitmap, 256); 7621 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 7622 } 7623 7624 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 7625 unsigned long start, unsigned long end, 7626 bool blockable) 7627 { 7628 unsigned long apic_address; 7629 7630 /* 7631 * The physical address of apic access page is stored in the VMCS. 7632 * Update it when it becomes invalid. 7633 */ 7634 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 7635 if (start <= apic_address && apic_address < end) 7636 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 7637 7638 return 0; 7639 } 7640 7641 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 7642 { 7643 struct page *page = NULL; 7644 7645 if (!lapic_in_kernel(vcpu)) 7646 return; 7647 7648 if (!kvm_x86_ops->set_apic_access_page_addr) 7649 return; 7650 7651 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 7652 if (is_error_page(page)) 7653 return; 7654 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 7655 7656 /* 7657 * Do not pin apic access page in memory, the MMU notifier 7658 * will call us again if it is migrated or swapped out. 7659 */ 7660 put_page(page); 7661 } 7662 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 7663 7664 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 7665 { 7666 smp_send_reschedule(vcpu->cpu); 7667 } 7668 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 7669 7670 /* 7671 * Returns 1 to let vcpu_run() continue the guest execution loop without 7672 * exiting to the userspace. Otherwise, the value will be returned to the 7673 * userspace. 7674 */ 7675 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 7676 { 7677 int r; 7678 bool req_int_win = 7679 dm_request_for_irq_injection(vcpu) && 7680 kvm_cpu_accept_dm_intr(vcpu); 7681 7682 bool req_immediate_exit = false; 7683 7684 if (kvm_request_pending(vcpu)) { 7685 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) 7686 kvm_x86_ops->get_vmcs12_pages(vcpu); 7687 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 7688 kvm_mmu_unload(vcpu); 7689 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 7690 __kvm_migrate_timers(vcpu); 7691 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 7692 kvm_gen_update_masterclock(vcpu->kvm); 7693 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 7694 kvm_gen_kvmclock_update(vcpu); 7695 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 7696 r = kvm_guest_time_update(vcpu); 7697 if (unlikely(r)) 7698 goto out; 7699 } 7700 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 7701 kvm_mmu_sync_roots(vcpu); 7702 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu)) 7703 kvm_mmu_load_cr3(vcpu); 7704 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 7705 kvm_vcpu_flush_tlb(vcpu, true); 7706 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 7707 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 7708 r = 0; 7709 goto out; 7710 } 7711 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 7712 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 7713 vcpu->mmio_needed = 0; 7714 r = 0; 7715 goto out; 7716 } 7717 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 7718 /* Page is swapped out. Do synthetic halt */ 7719 vcpu->arch.apf.halted = true; 7720 r = 1; 7721 goto out; 7722 } 7723 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 7724 record_steal_time(vcpu); 7725 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 7726 process_smi(vcpu); 7727 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 7728 process_nmi(vcpu); 7729 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 7730 kvm_pmu_handle_event(vcpu); 7731 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 7732 kvm_pmu_deliver_pmi(vcpu); 7733 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 7734 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 7735 if (test_bit(vcpu->arch.pending_ioapic_eoi, 7736 vcpu->arch.ioapic_handled_vectors)) { 7737 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 7738 vcpu->run->eoi.vector = 7739 vcpu->arch.pending_ioapic_eoi; 7740 r = 0; 7741 goto out; 7742 } 7743 } 7744 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 7745 vcpu_scan_ioapic(vcpu); 7746 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 7747 vcpu_load_eoi_exitmap(vcpu); 7748 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 7749 kvm_vcpu_reload_apic_access_page(vcpu); 7750 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 7751 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 7752 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 7753 r = 0; 7754 goto out; 7755 } 7756 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 7757 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 7758 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 7759 r = 0; 7760 goto out; 7761 } 7762 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 7763 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 7764 vcpu->run->hyperv = vcpu->arch.hyperv.exit; 7765 r = 0; 7766 goto out; 7767 } 7768 7769 /* 7770 * KVM_REQ_HV_STIMER has to be processed after 7771 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 7772 * depend on the guest clock being up-to-date 7773 */ 7774 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 7775 kvm_hv_process_stimers(vcpu); 7776 } 7777 7778 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 7779 ++vcpu->stat.req_event; 7780 kvm_apic_accept_events(vcpu); 7781 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 7782 r = 1; 7783 goto out; 7784 } 7785 7786 if (inject_pending_event(vcpu, req_int_win) != 0) 7787 req_immediate_exit = true; 7788 else { 7789 /* Enable SMI/NMI/IRQ window open exits if needed. 7790 * 7791 * SMIs have three cases: 7792 * 1) They can be nested, and then there is nothing to 7793 * do here because RSM will cause a vmexit anyway. 7794 * 2) There is an ISA-specific reason why SMI cannot be 7795 * injected, and the moment when this changes can be 7796 * intercepted. 7797 * 3) Or the SMI can be pending because 7798 * inject_pending_event has completed the injection 7799 * of an IRQ or NMI from the previous vmexit, and 7800 * then we request an immediate exit to inject the 7801 * SMI. 7802 */ 7803 if (vcpu->arch.smi_pending && !is_smm(vcpu)) 7804 if (!kvm_x86_ops->enable_smi_window(vcpu)) 7805 req_immediate_exit = true; 7806 if (vcpu->arch.nmi_pending) 7807 kvm_x86_ops->enable_nmi_window(vcpu); 7808 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 7809 kvm_x86_ops->enable_irq_window(vcpu); 7810 WARN_ON(vcpu->arch.exception.pending); 7811 } 7812 7813 if (kvm_lapic_enabled(vcpu)) { 7814 update_cr8_intercept(vcpu); 7815 kvm_lapic_sync_to_vapic(vcpu); 7816 } 7817 } 7818 7819 r = kvm_mmu_reload(vcpu); 7820 if (unlikely(r)) { 7821 goto cancel_injection; 7822 } 7823 7824 preempt_disable(); 7825 7826 kvm_x86_ops->prepare_guest_switch(vcpu); 7827 7828 /* 7829 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 7830 * IPI are then delayed after guest entry, which ensures that they 7831 * result in virtual interrupt delivery. 7832 */ 7833 local_irq_disable(); 7834 vcpu->mode = IN_GUEST_MODE; 7835 7836 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 7837 7838 /* 7839 * 1) We should set ->mode before checking ->requests. Please see 7840 * the comment in kvm_vcpu_exiting_guest_mode(). 7841 * 7842 * 2) For APICv, we should set ->mode before checking PID.ON. This 7843 * pairs with the memory barrier implicit in pi_test_and_set_on 7844 * (see vmx_deliver_posted_interrupt). 7845 * 7846 * 3) This also orders the write to mode from any reads to the page 7847 * tables done while the VCPU is running. Please see the comment 7848 * in kvm_flush_remote_tlbs. 7849 */ 7850 smp_mb__after_srcu_read_unlock(); 7851 7852 /* 7853 * This handles the case where a posted interrupt was 7854 * notified with kvm_vcpu_kick. 7855 */ 7856 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) 7857 kvm_x86_ops->sync_pir_to_irr(vcpu); 7858 7859 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) 7860 || need_resched() || signal_pending(current)) { 7861 vcpu->mode = OUTSIDE_GUEST_MODE; 7862 smp_wmb(); 7863 local_irq_enable(); 7864 preempt_enable(); 7865 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7866 r = 1; 7867 goto cancel_injection; 7868 } 7869 7870 if (req_immediate_exit) { 7871 kvm_make_request(KVM_REQ_EVENT, vcpu); 7872 kvm_x86_ops->request_immediate_exit(vcpu); 7873 } 7874 7875 trace_kvm_entry(vcpu->vcpu_id); 7876 if (lapic_timer_advance_ns) 7877 wait_lapic_expire(vcpu); 7878 guest_enter_irqoff(); 7879 7880 if (unlikely(vcpu->arch.switch_db_regs)) { 7881 set_debugreg(0, 7); 7882 set_debugreg(vcpu->arch.eff_db[0], 0); 7883 set_debugreg(vcpu->arch.eff_db[1], 1); 7884 set_debugreg(vcpu->arch.eff_db[2], 2); 7885 set_debugreg(vcpu->arch.eff_db[3], 3); 7886 set_debugreg(vcpu->arch.dr6, 6); 7887 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 7888 } 7889 7890 kvm_x86_ops->run(vcpu); 7891 7892 /* 7893 * Do this here before restoring debug registers on the host. And 7894 * since we do this before handling the vmexit, a DR access vmexit 7895 * can (a) read the correct value of the debug registers, (b) set 7896 * KVM_DEBUGREG_WONT_EXIT again. 7897 */ 7898 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 7899 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 7900 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 7901 kvm_update_dr0123(vcpu); 7902 kvm_update_dr6(vcpu); 7903 kvm_update_dr7(vcpu); 7904 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 7905 } 7906 7907 /* 7908 * If the guest has used debug registers, at least dr7 7909 * will be disabled while returning to the host. 7910 * If we don't have active breakpoints in the host, we don't 7911 * care about the messed up debug address registers. But if 7912 * we have some of them active, restore the old state. 7913 */ 7914 if (hw_breakpoint_active()) 7915 hw_breakpoint_restore(); 7916 7917 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 7918 7919 vcpu->mode = OUTSIDE_GUEST_MODE; 7920 smp_wmb(); 7921 7922 kvm_before_interrupt(vcpu); 7923 kvm_x86_ops->handle_external_intr(vcpu); 7924 kvm_after_interrupt(vcpu); 7925 7926 ++vcpu->stat.exits; 7927 7928 guest_exit_irqoff(); 7929 7930 local_irq_enable(); 7931 preempt_enable(); 7932 7933 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7934 7935 /* 7936 * Profile KVM exit RIPs: 7937 */ 7938 if (unlikely(prof_on == KVM_PROFILING)) { 7939 unsigned long rip = kvm_rip_read(vcpu); 7940 profile_hit(KVM_PROFILING, (void *)rip); 7941 } 7942 7943 if (unlikely(vcpu->arch.tsc_always_catchup)) 7944 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7945 7946 if (vcpu->arch.apic_attention) 7947 kvm_lapic_sync_from_vapic(vcpu); 7948 7949 vcpu->arch.gpa_available = false; 7950 r = kvm_x86_ops->handle_exit(vcpu); 7951 return r; 7952 7953 cancel_injection: 7954 kvm_x86_ops->cancel_injection(vcpu); 7955 if (unlikely(vcpu->arch.apic_attention)) 7956 kvm_lapic_sync_from_vapic(vcpu); 7957 out: 7958 return r; 7959 } 7960 7961 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 7962 { 7963 if (!kvm_arch_vcpu_runnable(vcpu) && 7964 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { 7965 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7966 kvm_vcpu_block(vcpu); 7967 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7968 7969 if (kvm_x86_ops->post_block) 7970 kvm_x86_ops->post_block(vcpu); 7971 7972 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 7973 return 1; 7974 } 7975 7976 kvm_apic_accept_events(vcpu); 7977 switch(vcpu->arch.mp_state) { 7978 case KVM_MP_STATE_HALTED: 7979 vcpu->arch.pv.pv_unhalted = false; 7980 vcpu->arch.mp_state = 7981 KVM_MP_STATE_RUNNABLE; 7982 /* fall through */ 7983 case KVM_MP_STATE_RUNNABLE: 7984 vcpu->arch.apf.halted = false; 7985 break; 7986 case KVM_MP_STATE_INIT_RECEIVED: 7987 break; 7988 default: 7989 return -EINTR; 7990 break; 7991 } 7992 return 1; 7993 } 7994 7995 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 7996 { 7997 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 7998 kvm_x86_ops->check_nested_events(vcpu, false); 7999 8000 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 8001 !vcpu->arch.apf.halted); 8002 } 8003 8004 static int vcpu_run(struct kvm_vcpu *vcpu) 8005 { 8006 int r; 8007 struct kvm *kvm = vcpu->kvm; 8008 8009 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 8010 vcpu->arch.l1tf_flush_l1d = true; 8011 8012 for (;;) { 8013 if (kvm_vcpu_running(vcpu)) { 8014 r = vcpu_enter_guest(vcpu); 8015 } else { 8016 r = vcpu_block(kvm, vcpu); 8017 } 8018 8019 if (r <= 0) 8020 break; 8021 8022 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); 8023 if (kvm_cpu_has_pending_timer(vcpu)) 8024 kvm_inject_pending_timer_irqs(vcpu); 8025 8026 if (dm_request_for_irq_injection(vcpu) && 8027 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 8028 r = 0; 8029 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 8030 ++vcpu->stat.request_irq_exits; 8031 break; 8032 } 8033 8034 kvm_check_async_pf_completion(vcpu); 8035 8036 if (signal_pending(current)) { 8037 r = -EINTR; 8038 vcpu->run->exit_reason = KVM_EXIT_INTR; 8039 ++vcpu->stat.signal_exits; 8040 break; 8041 } 8042 if (need_resched()) { 8043 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 8044 cond_resched(); 8045 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 8046 } 8047 } 8048 8049 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 8050 8051 return r; 8052 } 8053 8054 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 8055 { 8056 int r; 8057 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 8058 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 8059 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 8060 if (r != EMULATE_DONE) 8061 return 0; 8062 return 1; 8063 } 8064 8065 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 8066 { 8067 BUG_ON(!vcpu->arch.pio.count); 8068 8069 return complete_emulated_io(vcpu); 8070 } 8071 8072 /* 8073 * Implements the following, as a state machine: 8074 * 8075 * read: 8076 * for each fragment 8077 * for each mmio piece in the fragment 8078 * write gpa, len 8079 * exit 8080 * copy data 8081 * execute insn 8082 * 8083 * write: 8084 * for each fragment 8085 * for each mmio piece in the fragment 8086 * write gpa, len 8087 * copy data 8088 * exit 8089 */ 8090 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 8091 { 8092 struct kvm_run *run = vcpu->run; 8093 struct kvm_mmio_fragment *frag; 8094 unsigned len; 8095 8096 BUG_ON(!vcpu->mmio_needed); 8097 8098 /* Complete previous fragment */ 8099 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 8100 len = min(8u, frag->len); 8101 if (!vcpu->mmio_is_write) 8102 memcpy(frag->data, run->mmio.data, len); 8103 8104 if (frag->len <= 8) { 8105 /* Switch to the next fragment. */ 8106 frag++; 8107 vcpu->mmio_cur_fragment++; 8108 } else { 8109 /* Go forward to the next mmio piece. */ 8110 frag->data += len; 8111 frag->gpa += len; 8112 frag->len -= len; 8113 } 8114 8115 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 8116 vcpu->mmio_needed = 0; 8117 8118 /* FIXME: return into emulator if single-stepping. */ 8119 if (vcpu->mmio_is_write) 8120 return 1; 8121 vcpu->mmio_read_completed = 1; 8122 return complete_emulated_io(vcpu); 8123 } 8124 8125 run->exit_reason = KVM_EXIT_MMIO; 8126 run->mmio.phys_addr = frag->gpa; 8127 if (vcpu->mmio_is_write) 8128 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 8129 run->mmio.len = min(8u, frag->len); 8130 run->mmio.is_write = vcpu->mmio_is_write; 8131 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 8132 return 0; 8133 } 8134 8135 /* Swap (qemu) user FPU context for the guest FPU context. */ 8136 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 8137 { 8138 preempt_disable(); 8139 copy_fpregs_to_fpstate(¤t->thread.fpu); 8140 /* PKRU is separately restored in kvm_x86_ops->run. */ 8141 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, 8142 ~XFEATURE_MASK_PKRU); 8143 preempt_enable(); 8144 trace_kvm_fpu(1); 8145 } 8146 8147 /* When vcpu_run ends, restore user space FPU context. */ 8148 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 8149 { 8150 preempt_disable(); 8151 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu); 8152 copy_kernel_to_fpregs(¤t->thread.fpu.state); 8153 preempt_enable(); 8154 ++vcpu->stat.fpu_reload; 8155 trace_kvm_fpu(0); 8156 } 8157 8158 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 8159 { 8160 int r; 8161 8162 vcpu_load(vcpu); 8163 kvm_sigset_activate(vcpu); 8164 kvm_load_guest_fpu(vcpu); 8165 8166 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 8167 if (kvm_run->immediate_exit) { 8168 r = -EINTR; 8169 goto out; 8170 } 8171 kvm_vcpu_block(vcpu); 8172 kvm_apic_accept_events(vcpu); 8173 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 8174 r = -EAGAIN; 8175 if (signal_pending(current)) { 8176 r = -EINTR; 8177 vcpu->run->exit_reason = KVM_EXIT_INTR; 8178 ++vcpu->stat.signal_exits; 8179 } 8180 goto out; 8181 } 8182 8183 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { 8184 r = -EINVAL; 8185 goto out; 8186 } 8187 8188 if (vcpu->run->kvm_dirty_regs) { 8189 r = sync_regs(vcpu); 8190 if (r != 0) 8191 goto out; 8192 } 8193 8194 /* re-sync apic's tpr */ 8195 if (!lapic_in_kernel(vcpu)) { 8196 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 8197 r = -EINVAL; 8198 goto out; 8199 } 8200 } 8201 8202 if (unlikely(vcpu->arch.complete_userspace_io)) { 8203 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 8204 vcpu->arch.complete_userspace_io = NULL; 8205 r = cui(vcpu); 8206 if (r <= 0) 8207 goto out; 8208 } else 8209 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 8210 8211 if (kvm_run->immediate_exit) 8212 r = -EINTR; 8213 else 8214 r = vcpu_run(vcpu); 8215 8216 out: 8217 kvm_put_guest_fpu(vcpu); 8218 if (vcpu->run->kvm_valid_regs) 8219 store_regs(vcpu); 8220 post_kvm_run_save(vcpu); 8221 kvm_sigset_deactivate(vcpu); 8222 8223 vcpu_put(vcpu); 8224 return r; 8225 } 8226 8227 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8228 { 8229 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 8230 /* 8231 * We are here if userspace calls get_regs() in the middle of 8232 * instruction emulation. Registers state needs to be copied 8233 * back from emulation context to vcpu. Userspace shouldn't do 8234 * that usually, but some bad designed PV devices (vmware 8235 * backdoor interface) need this to work 8236 */ 8237 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 8238 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 8239 } 8240 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 8241 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 8242 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 8243 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 8244 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 8245 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 8246 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 8247 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 8248 #ifdef CONFIG_X86_64 8249 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 8250 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 8251 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 8252 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 8253 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 8254 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 8255 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 8256 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 8257 #endif 8258 8259 regs->rip = kvm_rip_read(vcpu); 8260 regs->rflags = kvm_get_rflags(vcpu); 8261 } 8262 8263 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8264 { 8265 vcpu_load(vcpu); 8266 __get_regs(vcpu, regs); 8267 vcpu_put(vcpu); 8268 return 0; 8269 } 8270 8271 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8272 { 8273 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 8274 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 8275 8276 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 8277 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 8278 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 8279 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 8280 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 8281 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 8282 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 8283 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 8284 #ifdef CONFIG_X86_64 8285 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 8286 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 8287 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 8288 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 8289 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 8290 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 8291 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 8292 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 8293 #endif 8294 8295 kvm_rip_write(vcpu, regs->rip); 8296 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 8297 8298 vcpu->arch.exception.pending = false; 8299 8300 kvm_make_request(KVM_REQ_EVENT, vcpu); 8301 } 8302 8303 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8304 { 8305 vcpu_load(vcpu); 8306 __set_regs(vcpu, regs); 8307 vcpu_put(vcpu); 8308 return 0; 8309 } 8310 8311 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 8312 { 8313 struct kvm_segment cs; 8314 8315 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 8316 *db = cs.db; 8317 *l = cs.l; 8318 } 8319 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 8320 8321 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 8322 { 8323 struct desc_ptr dt; 8324 8325 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 8326 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 8327 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 8328 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 8329 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 8330 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 8331 8332 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 8333 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 8334 8335 kvm_x86_ops->get_idt(vcpu, &dt); 8336 sregs->idt.limit = dt.size; 8337 sregs->idt.base = dt.address; 8338 kvm_x86_ops->get_gdt(vcpu, &dt); 8339 sregs->gdt.limit = dt.size; 8340 sregs->gdt.base = dt.address; 8341 8342 sregs->cr0 = kvm_read_cr0(vcpu); 8343 sregs->cr2 = vcpu->arch.cr2; 8344 sregs->cr3 = kvm_read_cr3(vcpu); 8345 sregs->cr4 = kvm_read_cr4(vcpu); 8346 sregs->cr8 = kvm_get_cr8(vcpu); 8347 sregs->efer = vcpu->arch.efer; 8348 sregs->apic_base = kvm_get_apic_base(vcpu); 8349 8350 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); 8351 8352 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 8353 set_bit(vcpu->arch.interrupt.nr, 8354 (unsigned long *)sregs->interrupt_bitmap); 8355 } 8356 8357 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 8358 struct kvm_sregs *sregs) 8359 { 8360 vcpu_load(vcpu); 8361 __get_sregs(vcpu, sregs); 8362 vcpu_put(vcpu); 8363 return 0; 8364 } 8365 8366 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 8367 struct kvm_mp_state *mp_state) 8368 { 8369 vcpu_load(vcpu); 8370 8371 kvm_apic_accept_events(vcpu); 8372 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 8373 vcpu->arch.pv.pv_unhalted) 8374 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 8375 else 8376 mp_state->mp_state = vcpu->arch.mp_state; 8377 8378 vcpu_put(vcpu); 8379 return 0; 8380 } 8381 8382 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 8383 struct kvm_mp_state *mp_state) 8384 { 8385 int ret = -EINVAL; 8386 8387 vcpu_load(vcpu); 8388 8389 if (!lapic_in_kernel(vcpu) && 8390 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 8391 goto out; 8392 8393 /* INITs are latched while in SMM */ 8394 if ((is_smm(vcpu) || vcpu->arch.smi_pending) && 8395 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 8396 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 8397 goto out; 8398 8399 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 8400 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 8401 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 8402 } else 8403 vcpu->arch.mp_state = mp_state->mp_state; 8404 kvm_make_request(KVM_REQ_EVENT, vcpu); 8405 8406 ret = 0; 8407 out: 8408 vcpu_put(vcpu); 8409 return ret; 8410 } 8411 8412 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 8413 int reason, bool has_error_code, u32 error_code) 8414 { 8415 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 8416 int ret; 8417 8418 init_emulate_ctxt(vcpu); 8419 8420 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 8421 has_error_code, error_code); 8422 8423 if (ret) 8424 return EMULATE_FAIL; 8425 8426 kvm_rip_write(vcpu, ctxt->eip); 8427 kvm_set_rflags(vcpu, ctxt->eflags); 8428 kvm_make_request(KVM_REQ_EVENT, vcpu); 8429 return EMULATE_DONE; 8430 } 8431 EXPORT_SYMBOL_GPL(kvm_task_switch); 8432 8433 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 8434 { 8435 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 8436 (sregs->cr4 & X86_CR4_OSXSAVE)) 8437 return -EINVAL; 8438 8439 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 8440 /* 8441 * When EFER.LME and CR0.PG are set, the processor is in 8442 * 64-bit mode (though maybe in a 32-bit code segment). 8443 * CR4.PAE and EFER.LMA must be set. 8444 */ 8445 if (!(sregs->cr4 & X86_CR4_PAE) 8446 || !(sregs->efer & EFER_LMA)) 8447 return -EINVAL; 8448 } else { 8449 /* 8450 * Not in 64-bit mode: EFER.LMA is clear and the code 8451 * segment cannot be 64-bit. 8452 */ 8453 if (sregs->efer & EFER_LMA || sregs->cs.l) 8454 return -EINVAL; 8455 } 8456 8457 return 0; 8458 } 8459 8460 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 8461 { 8462 struct msr_data apic_base_msr; 8463 int mmu_reset_needed = 0; 8464 int cpuid_update_needed = 0; 8465 int pending_vec, max_bits, idx; 8466 struct desc_ptr dt; 8467 int ret = -EINVAL; 8468 8469 if (kvm_valid_sregs(vcpu, sregs)) 8470 goto out; 8471 8472 apic_base_msr.data = sregs->apic_base; 8473 apic_base_msr.host_initiated = true; 8474 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 8475 goto out; 8476 8477 dt.size = sregs->idt.limit; 8478 dt.address = sregs->idt.base; 8479 kvm_x86_ops->set_idt(vcpu, &dt); 8480 dt.size = sregs->gdt.limit; 8481 dt.address = sregs->gdt.base; 8482 kvm_x86_ops->set_gdt(vcpu, &dt); 8483 8484 vcpu->arch.cr2 = sregs->cr2; 8485 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 8486 vcpu->arch.cr3 = sregs->cr3; 8487 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 8488 8489 kvm_set_cr8(vcpu, sregs->cr8); 8490 8491 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 8492 kvm_x86_ops->set_efer(vcpu, sregs->efer); 8493 8494 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 8495 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 8496 vcpu->arch.cr0 = sregs->cr0; 8497 8498 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 8499 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) & 8500 (X86_CR4_OSXSAVE | X86_CR4_PKE)); 8501 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 8502 if (cpuid_update_needed) 8503 kvm_update_cpuid(vcpu); 8504 8505 idx = srcu_read_lock(&vcpu->kvm->srcu); 8506 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) { 8507 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 8508 mmu_reset_needed = 1; 8509 } 8510 srcu_read_unlock(&vcpu->kvm->srcu, idx); 8511 8512 if (mmu_reset_needed) 8513 kvm_mmu_reset_context(vcpu); 8514 8515 max_bits = KVM_NR_INTERRUPTS; 8516 pending_vec = find_first_bit( 8517 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 8518 if (pending_vec < max_bits) { 8519 kvm_queue_interrupt(vcpu, pending_vec, false); 8520 pr_debug("Set back pending irq %d\n", pending_vec); 8521 } 8522 8523 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 8524 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 8525 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 8526 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 8527 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 8528 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 8529 8530 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 8531 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 8532 8533 update_cr8_intercept(vcpu); 8534 8535 /* Older userspace won't unhalt the vcpu on reset. */ 8536 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 8537 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 8538 !is_protmode(vcpu)) 8539 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8540 8541 kvm_make_request(KVM_REQ_EVENT, vcpu); 8542 8543 ret = 0; 8544 out: 8545 return ret; 8546 } 8547 8548 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 8549 struct kvm_sregs *sregs) 8550 { 8551 int ret; 8552 8553 vcpu_load(vcpu); 8554 ret = __set_sregs(vcpu, sregs); 8555 vcpu_put(vcpu); 8556 return ret; 8557 } 8558 8559 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 8560 struct kvm_guest_debug *dbg) 8561 { 8562 unsigned long rflags; 8563 int i, r; 8564 8565 vcpu_load(vcpu); 8566 8567 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 8568 r = -EBUSY; 8569 if (vcpu->arch.exception.pending) 8570 goto out; 8571 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 8572 kvm_queue_exception(vcpu, DB_VECTOR); 8573 else 8574 kvm_queue_exception(vcpu, BP_VECTOR); 8575 } 8576 8577 /* 8578 * Read rflags as long as potentially injected trace flags are still 8579 * filtered out. 8580 */ 8581 rflags = kvm_get_rflags(vcpu); 8582 8583 vcpu->guest_debug = dbg->control; 8584 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 8585 vcpu->guest_debug = 0; 8586 8587 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 8588 for (i = 0; i < KVM_NR_DB_REGS; ++i) 8589 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 8590 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 8591 } else { 8592 for (i = 0; i < KVM_NR_DB_REGS; i++) 8593 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 8594 } 8595 kvm_update_dr7(vcpu); 8596 8597 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 8598 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 8599 get_segment_base(vcpu, VCPU_SREG_CS); 8600 8601 /* 8602 * Trigger an rflags update that will inject or remove the trace 8603 * flags. 8604 */ 8605 kvm_set_rflags(vcpu, rflags); 8606 8607 kvm_x86_ops->update_bp_intercept(vcpu); 8608 8609 r = 0; 8610 8611 out: 8612 vcpu_put(vcpu); 8613 return r; 8614 } 8615 8616 /* 8617 * Translate a guest virtual address to a guest physical address. 8618 */ 8619 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 8620 struct kvm_translation *tr) 8621 { 8622 unsigned long vaddr = tr->linear_address; 8623 gpa_t gpa; 8624 int idx; 8625 8626 vcpu_load(vcpu); 8627 8628 idx = srcu_read_lock(&vcpu->kvm->srcu); 8629 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 8630 srcu_read_unlock(&vcpu->kvm->srcu, idx); 8631 tr->physical_address = gpa; 8632 tr->valid = gpa != UNMAPPED_GVA; 8633 tr->writeable = 1; 8634 tr->usermode = 0; 8635 8636 vcpu_put(vcpu); 8637 return 0; 8638 } 8639 8640 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 8641 { 8642 struct fxregs_state *fxsave; 8643 8644 vcpu_load(vcpu); 8645 8646 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 8647 memcpy(fpu->fpr, fxsave->st_space, 128); 8648 fpu->fcw = fxsave->cwd; 8649 fpu->fsw = fxsave->swd; 8650 fpu->ftwx = fxsave->twd; 8651 fpu->last_opcode = fxsave->fop; 8652 fpu->last_ip = fxsave->rip; 8653 fpu->last_dp = fxsave->rdp; 8654 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 8655 8656 vcpu_put(vcpu); 8657 return 0; 8658 } 8659 8660 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 8661 { 8662 struct fxregs_state *fxsave; 8663 8664 vcpu_load(vcpu); 8665 8666 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 8667 8668 memcpy(fxsave->st_space, fpu->fpr, 128); 8669 fxsave->cwd = fpu->fcw; 8670 fxsave->swd = fpu->fsw; 8671 fxsave->twd = fpu->ftwx; 8672 fxsave->fop = fpu->last_opcode; 8673 fxsave->rip = fpu->last_ip; 8674 fxsave->rdp = fpu->last_dp; 8675 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 8676 8677 vcpu_put(vcpu); 8678 return 0; 8679 } 8680 8681 static void store_regs(struct kvm_vcpu *vcpu) 8682 { 8683 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 8684 8685 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 8686 __get_regs(vcpu, &vcpu->run->s.regs.regs); 8687 8688 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 8689 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 8690 8691 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 8692 kvm_vcpu_ioctl_x86_get_vcpu_events( 8693 vcpu, &vcpu->run->s.regs.events); 8694 } 8695 8696 static int sync_regs(struct kvm_vcpu *vcpu) 8697 { 8698 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) 8699 return -EINVAL; 8700 8701 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 8702 __set_regs(vcpu, &vcpu->run->s.regs.regs); 8703 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 8704 } 8705 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 8706 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 8707 return -EINVAL; 8708 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 8709 } 8710 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 8711 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 8712 vcpu, &vcpu->run->s.regs.events)) 8713 return -EINVAL; 8714 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 8715 } 8716 8717 return 0; 8718 } 8719 8720 static void fx_init(struct kvm_vcpu *vcpu) 8721 { 8722 fpstate_init(&vcpu->arch.guest_fpu->state); 8723 if (boot_cpu_has(X86_FEATURE_XSAVES)) 8724 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = 8725 host_xcr0 | XSTATE_COMPACTION_ENABLED; 8726 8727 /* 8728 * Ensure guest xcr0 is valid for loading 8729 */ 8730 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 8731 8732 vcpu->arch.cr0 |= X86_CR0_ET; 8733 } 8734 8735 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 8736 { 8737 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask; 8738 8739 kvmclock_reset(vcpu); 8740 8741 kvm_x86_ops->vcpu_free(vcpu); 8742 free_cpumask_var(wbinvd_dirty_mask); 8743 } 8744 8745 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 8746 unsigned int id) 8747 { 8748 struct kvm_vcpu *vcpu; 8749 8750 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 8751 printk_once(KERN_WARNING 8752 "kvm: SMP vm created on host with unstable TSC; " 8753 "guest TSC will not be reliable\n"); 8754 8755 vcpu = kvm_x86_ops->vcpu_create(kvm, id); 8756 8757 return vcpu; 8758 } 8759 8760 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 8761 { 8762 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 8763 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 8764 kvm_vcpu_mtrr_init(vcpu); 8765 vcpu_load(vcpu); 8766 kvm_vcpu_reset(vcpu, false); 8767 kvm_init_mmu(vcpu, false); 8768 vcpu_put(vcpu); 8769 return 0; 8770 } 8771 8772 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 8773 { 8774 struct msr_data msr; 8775 struct kvm *kvm = vcpu->kvm; 8776 8777 kvm_hv_vcpu_postcreate(vcpu); 8778 8779 if (mutex_lock_killable(&vcpu->mutex)) 8780 return; 8781 vcpu_load(vcpu); 8782 msr.data = 0x0; 8783 msr.index = MSR_IA32_TSC; 8784 msr.host_initiated = true; 8785 kvm_write_tsc(vcpu, &msr); 8786 vcpu_put(vcpu); 8787 mutex_unlock(&vcpu->mutex); 8788 8789 if (!kvmclock_periodic_sync) 8790 return; 8791 8792 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 8793 KVMCLOCK_SYNC_PERIOD); 8794 } 8795 8796 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 8797 { 8798 vcpu->arch.apf.msr_val = 0; 8799 8800 vcpu_load(vcpu); 8801 kvm_mmu_unload(vcpu); 8802 vcpu_put(vcpu); 8803 8804 kvm_x86_ops->vcpu_free(vcpu); 8805 } 8806 8807 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 8808 { 8809 kvm_lapic_reset(vcpu, init_event); 8810 8811 vcpu->arch.hflags = 0; 8812 8813 vcpu->arch.smi_pending = 0; 8814 vcpu->arch.smi_count = 0; 8815 atomic_set(&vcpu->arch.nmi_queued, 0); 8816 vcpu->arch.nmi_pending = 0; 8817 vcpu->arch.nmi_injected = false; 8818 kvm_clear_interrupt_queue(vcpu); 8819 kvm_clear_exception_queue(vcpu); 8820 vcpu->arch.exception.pending = false; 8821 8822 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 8823 kvm_update_dr0123(vcpu); 8824 vcpu->arch.dr6 = DR6_INIT; 8825 kvm_update_dr6(vcpu); 8826 vcpu->arch.dr7 = DR7_FIXED_1; 8827 kvm_update_dr7(vcpu); 8828 8829 vcpu->arch.cr2 = 0; 8830 8831 kvm_make_request(KVM_REQ_EVENT, vcpu); 8832 vcpu->arch.apf.msr_val = 0; 8833 vcpu->arch.st.msr_val = 0; 8834 8835 kvmclock_reset(vcpu); 8836 8837 kvm_clear_async_pf_completion_queue(vcpu); 8838 kvm_async_pf_hash_reset(vcpu); 8839 vcpu->arch.apf.halted = false; 8840 8841 if (kvm_mpx_supported()) { 8842 void *mpx_state_buffer; 8843 8844 /* 8845 * To avoid have the INIT path from kvm_apic_has_events() that be 8846 * called with loaded FPU and does not let userspace fix the state. 8847 */ 8848 if (init_event) 8849 kvm_put_guest_fpu(vcpu); 8850 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 8851 XFEATURE_MASK_BNDREGS); 8852 if (mpx_state_buffer) 8853 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); 8854 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 8855 XFEATURE_MASK_BNDCSR); 8856 if (mpx_state_buffer) 8857 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); 8858 if (init_event) 8859 kvm_load_guest_fpu(vcpu); 8860 } 8861 8862 if (!init_event) { 8863 kvm_pmu_reset(vcpu); 8864 vcpu->arch.smbase = 0x30000; 8865 8866 vcpu->arch.msr_misc_features_enables = 0; 8867 8868 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 8869 } 8870 8871 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 8872 vcpu->arch.regs_avail = ~0; 8873 vcpu->arch.regs_dirty = ~0; 8874 8875 vcpu->arch.ia32_xss = 0; 8876 8877 kvm_x86_ops->vcpu_reset(vcpu, init_event); 8878 } 8879 8880 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 8881 { 8882 struct kvm_segment cs; 8883 8884 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 8885 cs.selector = vector << 8; 8886 cs.base = vector << 12; 8887 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 8888 kvm_rip_write(vcpu, 0); 8889 } 8890 8891 int kvm_arch_hardware_enable(void) 8892 { 8893 struct kvm *kvm; 8894 struct kvm_vcpu *vcpu; 8895 int i; 8896 int ret; 8897 u64 local_tsc; 8898 u64 max_tsc = 0; 8899 bool stable, backwards_tsc = false; 8900 8901 kvm_shared_msr_cpu_online(); 8902 ret = kvm_x86_ops->hardware_enable(); 8903 if (ret != 0) 8904 return ret; 8905 8906 local_tsc = rdtsc(); 8907 stable = !kvm_check_tsc_unstable(); 8908 list_for_each_entry(kvm, &vm_list, vm_list) { 8909 kvm_for_each_vcpu(i, vcpu, kvm) { 8910 if (!stable && vcpu->cpu == smp_processor_id()) 8911 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 8912 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 8913 backwards_tsc = true; 8914 if (vcpu->arch.last_host_tsc > max_tsc) 8915 max_tsc = vcpu->arch.last_host_tsc; 8916 } 8917 } 8918 } 8919 8920 /* 8921 * Sometimes, even reliable TSCs go backwards. This happens on 8922 * platforms that reset TSC during suspend or hibernate actions, but 8923 * maintain synchronization. We must compensate. Fortunately, we can 8924 * detect that condition here, which happens early in CPU bringup, 8925 * before any KVM threads can be running. Unfortunately, we can't 8926 * bring the TSCs fully up to date with real time, as we aren't yet far 8927 * enough into CPU bringup that we know how much real time has actually 8928 * elapsed; our helper function, ktime_get_boot_ns() will be using boot 8929 * variables that haven't been updated yet. 8930 * 8931 * So we simply find the maximum observed TSC above, then record the 8932 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 8933 * the adjustment will be applied. Note that we accumulate 8934 * adjustments, in case multiple suspend cycles happen before some VCPU 8935 * gets a chance to run again. In the event that no KVM threads get a 8936 * chance to run, we will miss the entire elapsed period, as we'll have 8937 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 8938 * loose cycle time. This isn't too big a deal, since the loss will be 8939 * uniform across all VCPUs (not to mention the scenario is extremely 8940 * unlikely). It is possible that a second hibernate recovery happens 8941 * much faster than a first, causing the observed TSC here to be 8942 * smaller; this would require additional padding adjustment, which is 8943 * why we set last_host_tsc to the local tsc observed here. 8944 * 8945 * N.B. - this code below runs only on platforms with reliable TSC, 8946 * as that is the only way backwards_tsc is set above. Also note 8947 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 8948 * have the same delta_cyc adjustment applied if backwards_tsc 8949 * is detected. Note further, this adjustment is only done once, 8950 * as we reset last_host_tsc on all VCPUs to stop this from being 8951 * called multiple times (one for each physical CPU bringup). 8952 * 8953 * Platforms with unreliable TSCs don't have to deal with this, they 8954 * will be compensated by the logic in vcpu_load, which sets the TSC to 8955 * catchup mode. This will catchup all VCPUs to real time, but cannot 8956 * guarantee that they stay in perfect synchronization. 8957 */ 8958 if (backwards_tsc) { 8959 u64 delta_cyc = max_tsc - local_tsc; 8960 list_for_each_entry(kvm, &vm_list, vm_list) { 8961 kvm->arch.backwards_tsc_observed = true; 8962 kvm_for_each_vcpu(i, vcpu, kvm) { 8963 vcpu->arch.tsc_offset_adjustment += delta_cyc; 8964 vcpu->arch.last_host_tsc = local_tsc; 8965 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 8966 } 8967 8968 /* 8969 * We have to disable TSC offset matching.. if you were 8970 * booting a VM while issuing an S4 host suspend.... 8971 * you may have some problem. Solving this issue is 8972 * left as an exercise to the reader. 8973 */ 8974 kvm->arch.last_tsc_nsec = 0; 8975 kvm->arch.last_tsc_write = 0; 8976 } 8977 8978 } 8979 return 0; 8980 } 8981 8982 void kvm_arch_hardware_disable(void) 8983 { 8984 kvm_x86_ops->hardware_disable(); 8985 drop_user_return_notifiers(); 8986 } 8987 8988 int kvm_arch_hardware_setup(void) 8989 { 8990 int r; 8991 8992 r = kvm_x86_ops->hardware_setup(); 8993 if (r != 0) 8994 return r; 8995 8996 if (kvm_has_tsc_control) { 8997 /* 8998 * Make sure the user can only configure tsc_khz values that 8999 * fit into a signed integer. 9000 * A min value is not calculated because it will always 9001 * be 1 on all machines. 9002 */ 9003 u64 max = min(0x7fffffffULL, 9004 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 9005 kvm_max_guest_tsc_khz = max; 9006 9007 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 9008 } 9009 9010 kvm_init_msr_list(); 9011 return 0; 9012 } 9013 9014 void kvm_arch_hardware_unsetup(void) 9015 { 9016 kvm_x86_ops->hardware_unsetup(); 9017 } 9018 9019 void kvm_arch_check_processor_compat(void *rtn) 9020 { 9021 kvm_x86_ops->check_processor_compatibility(rtn); 9022 } 9023 9024 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 9025 { 9026 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 9027 } 9028 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 9029 9030 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 9031 { 9032 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 9033 } 9034 9035 struct static_key kvm_no_apic_vcpu __read_mostly; 9036 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); 9037 9038 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 9039 { 9040 struct page *page; 9041 int r; 9042 9043 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 9044 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 9045 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 9046 else 9047 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 9048 9049 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 9050 if (!page) { 9051 r = -ENOMEM; 9052 goto fail; 9053 } 9054 vcpu->arch.pio_data = page_address(page); 9055 9056 kvm_set_tsc_khz(vcpu, max_tsc_khz); 9057 9058 r = kvm_mmu_create(vcpu); 9059 if (r < 0) 9060 goto fail_free_pio_data; 9061 9062 if (irqchip_in_kernel(vcpu->kvm)) { 9063 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu); 9064 r = kvm_create_lapic(vcpu); 9065 if (r < 0) 9066 goto fail_mmu_destroy; 9067 } else 9068 static_key_slow_inc(&kvm_no_apic_vcpu); 9069 9070 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 9071 GFP_KERNEL_ACCOUNT); 9072 if (!vcpu->arch.mce_banks) { 9073 r = -ENOMEM; 9074 goto fail_free_lapic; 9075 } 9076 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 9077 9078 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 9079 GFP_KERNEL_ACCOUNT)) { 9080 r = -ENOMEM; 9081 goto fail_free_mce_banks; 9082 } 9083 9084 fx_init(vcpu); 9085 9086 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 9087 9088 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 9089 9090 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 9091 9092 kvm_async_pf_hash_reset(vcpu); 9093 kvm_pmu_init(vcpu); 9094 9095 vcpu->arch.pending_external_vector = -1; 9096 vcpu->arch.preempted_in_kernel = false; 9097 9098 kvm_hv_vcpu_init(vcpu); 9099 9100 return 0; 9101 9102 fail_free_mce_banks: 9103 kfree(vcpu->arch.mce_banks); 9104 fail_free_lapic: 9105 kvm_free_lapic(vcpu); 9106 fail_mmu_destroy: 9107 kvm_mmu_destroy(vcpu); 9108 fail_free_pio_data: 9109 free_page((unsigned long)vcpu->arch.pio_data); 9110 fail: 9111 return r; 9112 } 9113 9114 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 9115 { 9116 int idx; 9117 9118 kvm_hv_vcpu_uninit(vcpu); 9119 kvm_pmu_destroy(vcpu); 9120 kfree(vcpu->arch.mce_banks); 9121 kvm_free_lapic(vcpu); 9122 idx = srcu_read_lock(&vcpu->kvm->srcu); 9123 kvm_mmu_destroy(vcpu); 9124 srcu_read_unlock(&vcpu->kvm->srcu, idx); 9125 free_page((unsigned long)vcpu->arch.pio_data); 9126 if (!lapic_in_kernel(vcpu)) 9127 static_key_slow_dec(&kvm_no_apic_vcpu); 9128 } 9129 9130 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 9131 { 9132 vcpu->arch.l1tf_flush_l1d = true; 9133 kvm_x86_ops->sched_in(vcpu, cpu); 9134 } 9135 9136 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 9137 { 9138 if (type) 9139 return -EINVAL; 9140 9141 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 9142 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 9143 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 9144 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 9145 9146 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 9147 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 9148 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 9149 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 9150 &kvm->arch.irq_sources_bitmap); 9151 9152 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 9153 mutex_init(&kvm->arch.apic_map_lock); 9154 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 9155 9156 kvm->arch.kvmclock_offset = -ktime_get_boot_ns(); 9157 pvclock_update_vm_gtod_copy(kvm); 9158 9159 kvm->arch.guest_can_read_msr_platform_info = true; 9160 9161 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 9162 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 9163 9164 kvm_hv_init_vm(kvm); 9165 kvm_page_track_init(kvm); 9166 kvm_mmu_init_vm(kvm); 9167 9168 if (kvm_x86_ops->vm_init) 9169 return kvm_x86_ops->vm_init(kvm); 9170 9171 return 0; 9172 } 9173 9174 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 9175 { 9176 vcpu_load(vcpu); 9177 kvm_mmu_unload(vcpu); 9178 vcpu_put(vcpu); 9179 } 9180 9181 static void kvm_free_vcpus(struct kvm *kvm) 9182 { 9183 unsigned int i; 9184 struct kvm_vcpu *vcpu; 9185 9186 /* 9187 * Unpin any mmu pages first. 9188 */ 9189 kvm_for_each_vcpu(i, vcpu, kvm) { 9190 kvm_clear_async_pf_completion_queue(vcpu); 9191 kvm_unload_vcpu_mmu(vcpu); 9192 } 9193 kvm_for_each_vcpu(i, vcpu, kvm) 9194 kvm_arch_vcpu_free(vcpu); 9195 9196 mutex_lock(&kvm->lock); 9197 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 9198 kvm->vcpus[i] = NULL; 9199 9200 atomic_set(&kvm->online_vcpus, 0); 9201 mutex_unlock(&kvm->lock); 9202 } 9203 9204 void kvm_arch_sync_events(struct kvm *kvm) 9205 { 9206 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 9207 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 9208 kvm_free_pit(kvm); 9209 } 9210 9211 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 9212 { 9213 int i, r; 9214 unsigned long hva; 9215 struct kvm_memslots *slots = kvm_memslots(kvm); 9216 struct kvm_memory_slot *slot, old; 9217 9218 /* Called with kvm->slots_lock held. */ 9219 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 9220 return -EINVAL; 9221 9222 slot = id_to_memslot(slots, id); 9223 if (size) { 9224 if (slot->npages) 9225 return -EEXIST; 9226 9227 /* 9228 * MAP_SHARED to prevent internal slot pages from being moved 9229 * by fork()/COW. 9230 */ 9231 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 9232 MAP_SHARED | MAP_ANONYMOUS, 0); 9233 if (IS_ERR((void *)hva)) 9234 return PTR_ERR((void *)hva); 9235 } else { 9236 if (!slot->npages) 9237 return 0; 9238 9239 hva = 0; 9240 } 9241 9242 old = *slot; 9243 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 9244 struct kvm_userspace_memory_region m; 9245 9246 m.slot = id | (i << 16); 9247 m.flags = 0; 9248 m.guest_phys_addr = gpa; 9249 m.userspace_addr = hva; 9250 m.memory_size = size; 9251 r = __kvm_set_memory_region(kvm, &m); 9252 if (r < 0) 9253 return r; 9254 } 9255 9256 if (!size) 9257 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); 9258 9259 return 0; 9260 } 9261 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 9262 9263 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 9264 { 9265 int r; 9266 9267 mutex_lock(&kvm->slots_lock); 9268 r = __x86_set_memory_region(kvm, id, gpa, size); 9269 mutex_unlock(&kvm->slots_lock); 9270 9271 return r; 9272 } 9273 EXPORT_SYMBOL_GPL(x86_set_memory_region); 9274 9275 void kvm_arch_destroy_vm(struct kvm *kvm) 9276 { 9277 if (current->mm == kvm->mm) { 9278 /* 9279 * Free memory regions allocated on behalf of userspace, 9280 * unless the the memory map has changed due to process exit 9281 * or fd copying. 9282 */ 9283 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); 9284 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); 9285 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 9286 } 9287 if (kvm_x86_ops->vm_destroy) 9288 kvm_x86_ops->vm_destroy(kvm); 9289 kvm_pic_destroy(kvm); 9290 kvm_ioapic_destroy(kvm); 9291 kvm_free_vcpus(kvm); 9292 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 9293 kvm_mmu_uninit_vm(kvm); 9294 kvm_page_track_cleanup(kvm); 9295 kvm_hv_destroy_vm(kvm); 9296 } 9297 9298 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 9299 struct kvm_memory_slot *dont) 9300 { 9301 int i; 9302 9303 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 9304 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 9305 kvfree(free->arch.rmap[i]); 9306 free->arch.rmap[i] = NULL; 9307 } 9308 if (i == 0) 9309 continue; 9310 9311 if (!dont || free->arch.lpage_info[i - 1] != 9312 dont->arch.lpage_info[i - 1]) { 9313 kvfree(free->arch.lpage_info[i - 1]); 9314 free->arch.lpage_info[i - 1] = NULL; 9315 } 9316 } 9317 9318 kvm_page_track_free_memslot(free, dont); 9319 } 9320 9321 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 9322 unsigned long npages) 9323 { 9324 int i; 9325 9326 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 9327 struct kvm_lpage_info *linfo; 9328 unsigned long ugfn; 9329 int lpages; 9330 int level = i + 1; 9331 9332 lpages = gfn_to_index(slot->base_gfn + npages - 1, 9333 slot->base_gfn, level) + 1; 9334 9335 slot->arch.rmap[i] = 9336 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), 9337 GFP_KERNEL_ACCOUNT); 9338 if (!slot->arch.rmap[i]) 9339 goto out_free; 9340 if (i == 0) 9341 continue; 9342 9343 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 9344 if (!linfo) 9345 goto out_free; 9346 9347 slot->arch.lpage_info[i - 1] = linfo; 9348 9349 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 9350 linfo[0].disallow_lpage = 1; 9351 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 9352 linfo[lpages - 1].disallow_lpage = 1; 9353 ugfn = slot->userspace_addr >> PAGE_SHIFT; 9354 /* 9355 * If the gfn and userspace address are not aligned wrt each 9356 * other, or if explicitly asked to, disable large page 9357 * support for this slot 9358 */ 9359 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 9360 !kvm_largepages_enabled()) { 9361 unsigned long j; 9362 9363 for (j = 0; j < lpages; ++j) 9364 linfo[j].disallow_lpage = 1; 9365 } 9366 } 9367 9368 if (kvm_page_track_create_memslot(slot, npages)) 9369 goto out_free; 9370 9371 return 0; 9372 9373 out_free: 9374 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 9375 kvfree(slot->arch.rmap[i]); 9376 slot->arch.rmap[i] = NULL; 9377 if (i == 0) 9378 continue; 9379 9380 kvfree(slot->arch.lpage_info[i - 1]); 9381 slot->arch.lpage_info[i - 1] = NULL; 9382 } 9383 return -ENOMEM; 9384 } 9385 9386 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 9387 { 9388 /* 9389 * memslots->generation has been incremented. 9390 * mmio generation may have reached its maximum value. 9391 */ 9392 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 9393 } 9394 9395 int kvm_arch_prepare_memory_region(struct kvm *kvm, 9396 struct kvm_memory_slot *memslot, 9397 const struct kvm_userspace_memory_region *mem, 9398 enum kvm_mr_change change) 9399 { 9400 return 0; 9401 } 9402 9403 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 9404 struct kvm_memory_slot *new) 9405 { 9406 /* Still write protect RO slot */ 9407 if (new->flags & KVM_MEM_READONLY) { 9408 kvm_mmu_slot_remove_write_access(kvm, new); 9409 return; 9410 } 9411 9412 /* 9413 * Call kvm_x86_ops dirty logging hooks when they are valid. 9414 * 9415 * kvm_x86_ops->slot_disable_log_dirty is called when: 9416 * 9417 * - KVM_MR_CREATE with dirty logging is disabled 9418 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 9419 * 9420 * The reason is, in case of PML, we need to set D-bit for any slots 9421 * with dirty logging disabled in order to eliminate unnecessary GPA 9422 * logging in PML buffer (and potential PML buffer full VMEXT). This 9423 * guarantees leaving PML enabled during guest's lifetime won't have 9424 * any additional overhead from PML when guest is running with dirty 9425 * logging disabled for memory slots. 9426 * 9427 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 9428 * to dirty logging mode. 9429 * 9430 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 9431 * 9432 * In case of write protect: 9433 * 9434 * Write protect all pages for dirty logging. 9435 * 9436 * All the sptes including the large sptes which point to this 9437 * slot are set to readonly. We can not create any new large 9438 * spte on this slot until the end of the logging. 9439 * 9440 * See the comments in fast_page_fault(). 9441 */ 9442 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 9443 if (kvm_x86_ops->slot_enable_log_dirty) 9444 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 9445 else 9446 kvm_mmu_slot_remove_write_access(kvm, new); 9447 } else { 9448 if (kvm_x86_ops->slot_disable_log_dirty) 9449 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 9450 } 9451 } 9452 9453 void kvm_arch_commit_memory_region(struct kvm *kvm, 9454 const struct kvm_userspace_memory_region *mem, 9455 const struct kvm_memory_slot *old, 9456 const struct kvm_memory_slot *new, 9457 enum kvm_mr_change change) 9458 { 9459 if (!kvm->arch.n_requested_mmu_pages) 9460 kvm_mmu_change_mmu_pages(kvm, 9461 kvm_mmu_calculate_default_mmu_pages(kvm)); 9462 9463 /* 9464 * Dirty logging tracks sptes in 4k granularity, meaning that large 9465 * sptes have to be split. If live migration is successful, the guest 9466 * in the source machine will be destroyed and large sptes will be 9467 * created in the destination. However, if the guest continues to run 9468 * in the source machine (for example if live migration fails), small 9469 * sptes will remain around and cause bad performance. 9470 * 9471 * Scan sptes if dirty logging has been stopped, dropping those 9472 * which can be collapsed into a single large-page spte. Later 9473 * page faults will create the large-page sptes. 9474 */ 9475 if ((change != KVM_MR_DELETE) && 9476 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 9477 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 9478 kvm_mmu_zap_collapsible_sptes(kvm, new); 9479 9480 /* 9481 * Set up write protection and/or dirty logging for the new slot. 9482 * 9483 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 9484 * been zapped so no dirty logging staff is needed for old slot. For 9485 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 9486 * new and it's also covered when dealing with the new slot. 9487 * 9488 * FIXME: const-ify all uses of struct kvm_memory_slot. 9489 */ 9490 if (change != KVM_MR_DELETE) 9491 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 9492 } 9493 9494 void kvm_arch_flush_shadow_all(struct kvm *kvm) 9495 { 9496 kvm_mmu_zap_all(kvm); 9497 } 9498 9499 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 9500 struct kvm_memory_slot *slot) 9501 { 9502 kvm_page_track_flush_slot(kvm, slot); 9503 } 9504 9505 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 9506 { 9507 return (is_guest_mode(vcpu) && 9508 kvm_x86_ops->guest_apic_has_interrupt && 9509 kvm_x86_ops->guest_apic_has_interrupt(vcpu)); 9510 } 9511 9512 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 9513 { 9514 if (!list_empty_careful(&vcpu->async_pf.done)) 9515 return true; 9516 9517 if (kvm_apic_has_events(vcpu)) 9518 return true; 9519 9520 if (vcpu->arch.pv.pv_unhalted) 9521 return true; 9522 9523 if (vcpu->arch.exception.pending) 9524 return true; 9525 9526 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 9527 (vcpu->arch.nmi_pending && 9528 kvm_x86_ops->nmi_allowed(vcpu))) 9529 return true; 9530 9531 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 9532 (vcpu->arch.smi_pending && !is_smm(vcpu))) 9533 return true; 9534 9535 if (kvm_arch_interrupt_allowed(vcpu) && 9536 (kvm_cpu_has_interrupt(vcpu) || 9537 kvm_guest_apic_has_interrupt(vcpu))) 9538 return true; 9539 9540 if (kvm_hv_has_stimer_pending(vcpu)) 9541 return true; 9542 9543 return false; 9544 } 9545 9546 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 9547 { 9548 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 9549 } 9550 9551 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 9552 { 9553 return vcpu->arch.preempted_in_kernel; 9554 } 9555 9556 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 9557 { 9558 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 9559 } 9560 9561 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 9562 { 9563 return kvm_x86_ops->interrupt_allowed(vcpu); 9564 } 9565 9566 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 9567 { 9568 if (is_64_bit_mode(vcpu)) 9569 return kvm_rip_read(vcpu); 9570 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 9571 kvm_rip_read(vcpu)); 9572 } 9573 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 9574 9575 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 9576 { 9577 return kvm_get_linear_rip(vcpu) == linear_rip; 9578 } 9579 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 9580 9581 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 9582 { 9583 unsigned long rflags; 9584 9585 rflags = kvm_x86_ops->get_rflags(vcpu); 9586 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 9587 rflags &= ~X86_EFLAGS_TF; 9588 return rflags; 9589 } 9590 EXPORT_SYMBOL_GPL(kvm_get_rflags); 9591 9592 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 9593 { 9594 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 9595 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 9596 rflags |= X86_EFLAGS_TF; 9597 kvm_x86_ops->set_rflags(vcpu, rflags); 9598 } 9599 9600 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 9601 { 9602 __kvm_set_rflags(vcpu, rflags); 9603 kvm_make_request(KVM_REQ_EVENT, vcpu); 9604 } 9605 EXPORT_SYMBOL_GPL(kvm_set_rflags); 9606 9607 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 9608 { 9609 int r; 9610 9611 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || 9612 work->wakeup_all) 9613 return; 9614 9615 r = kvm_mmu_reload(vcpu); 9616 if (unlikely(r)) 9617 return; 9618 9619 if (!vcpu->arch.mmu->direct_map && 9620 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu)) 9621 return; 9622 9623 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true); 9624 } 9625 9626 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 9627 { 9628 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 9629 } 9630 9631 static inline u32 kvm_async_pf_next_probe(u32 key) 9632 { 9633 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 9634 } 9635 9636 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 9637 { 9638 u32 key = kvm_async_pf_hash_fn(gfn); 9639 9640 while (vcpu->arch.apf.gfns[key] != ~0) 9641 key = kvm_async_pf_next_probe(key); 9642 9643 vcpu->arch.apf.gfns[key] = gfn; 9644 } 9645 9646 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 9647 { 9648 int i; 9649 u32 key = kvm_async_pf_hash_fn(gfn); 9650 9651 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 9652 (vcpu->arch.apf.gfns[key] != gfn && 9653 vcpu->arch.apf.gfns[key] != ~0); i++) 9654 key = kvm_async_pf_next_probe(key); 9655 9656 return key; 9657 } 9658 9659 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 9660 { 9661 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 9662 } 9663 9664 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 9665 { 9666 u32 i, j, k; 9667 9668 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 9669 while (true) { 9670 vcpu->arch.apf.gfns[i] = ~0; 9671 do { 9672 j = kvm_async_pf_next_probe(j); 9673 if (vcpu->arch.apf.gfns[j] == ~0) 9674 return; 9675 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 9676 /* 9677 * k lies cyclically in ]i,j] 9678 * | i.k.j | 9679 * |....j i.k.| or |.k..j i...| 9680 */ 9681 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 9682 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 9683 i = j; 9684 } 9685 } 9686 9687 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 9688 { 9689 9690 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 9691 sizeof(val)); 9692 } 9693 9694 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val) 9695 { 9696 9697 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val, 9698 sizeof(u32)); 9699 } 9700 9701 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 9702 struct kvm_async_pf *work) 9703 { 9704 struct x86_exception fault; 9705 9706 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 9707 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 9708 9709 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 9710 (vcpu->arch.apf.send_user_only && 9711 kvm_x86_ops->get_cpl(vcpu) == 0)) 9712 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 9713 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 9714 fault.vector = PF_VECTOR; 9715 fault.error_code_valid = true; 9716 fault.error_code = 0; 9717 fault.nested_page_fault = false; 9718 fault.address = work->arch.token; 9719 fault.async_page_fault = true; 9720 kvm_inject_page_fault(vcpu, &fault); 9721 } 9722 } 9723 9724 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 9725 struct kvm_async_pf *work) 9726 { 9727 struct x86_exception fault; 9728 u32 val; 9729 9730 if (work->wakeup_all) 9731 work->arch.token = ~0; /* broadcast wakeup */ 9732 else 9733 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 9734 trace_kvm_async_pf_ready(work->arch.token, work->gva); 9735 9736 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED && 9737 !apf_get_user(vcpu, &val)) { 9738 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT && 9739 vcpu->arch.exception.pending && 9740 vcpu->arch.exception.nr == PF_VECTOR && 9741 !apf_put_user(vcpu, 0)) { 9742 vcpu->arch.exception.injected = false; 9743 vcpu->arch.exception.pending = false; 9744 vcpu->arch.exception.nr = 0; 9745 vcpu->arch.exception.has_error_code = false; 9746 vcpu->arch.exception.error_code = 0; 9747 vcpu->arch.exception.has_payload = false; 9748 vcpu->arch.exception.payload = 0; 9749 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 9750 fault.vector = PF_VECTOR; 9751 fault.error_code_valid = true; 9752 fault.error_code = 0; 9753 fault.nested_page_fault = false; 9754 fault.address = work->arch.token; 9755 fault.async_page_fault = true; 9756 kvm_inject_page_fault(vcpu, &fault); 9757 } 9758 } 9759 vcpu->arch.apf.halted = false; 9760 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 9761 } 9762 9763 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 9764 { 9765 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 9766 return true; 9767 else 9768 return kvm_can_do_async_pf(vcpu); 9769 } 9770 9771 void kvm_arch_start_assignment(struct kvm *kvm) 9772 { 9773 atomic_inc(&kvm->arch.assigned_device_count); 9774 } 9775 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 9776 9777 void kvm_arch_end_assignment(struct kvm *kvm) 9778 { 9779 atomic_dec(&kvm->arch.assigned_device_count); 9780 } 9781 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 9782 9783 bool kvm_arch_has_assigned_device(struct kvm *kvm) 9784 { 9785 return atomic_read(&kvm->arch.assigned_device_count); 9786 } 9787 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 9788 9789 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 9790 { 9791 atomic_inc(&kvm->arch.noncoherent_dma_count); 9792 } 9793 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 9794 9795 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 9796 { 9797 atomic_dec(&kvm->arch.noncoherent_dma_count); 9798 } 9799 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 9800 9801 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 9802 { 9803 return atomic_read(&kvm->arch.noncoherent_dma_count); 9804 } 9805 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 9806 9807 bool kvm_arch_has_irq_bypass(void) 9808 { 9809 return kvm_x86_ops->update_pi_irte != NULL; 9810 } 9811 9812 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 9813 struct irq_bypass_producer *prod) 9814 { 9815 struct kvm_kernel_irqfd *irqfd = 9816 container_of(cons, struct kvm_kernel_irqfd, consumer); 9817 9818 irqfd->producer = prod; 9819 9820 return kvm_x86_ops->update_pi_irte(irqfd->kvm, 9821 prod->irq, irqfd->gsi, 1); 9822 } 9823 9824 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 9825 struct irq_bypass_producer *prod) 9826 { 9827 int ret; 9828 struct kvm_kernel_irqfd *irqfd = 9829 container_of(cons, struct kvm_kernel_irqfd, consumer); 9830 9831 WARN_ON(irqfd->producer != prod); 9832 irqfd->producer = NULL; 9833 9834 /* 9835 * When producer of consumer is unregistered, we change back to 9836 * remapped mode, so we can re-use the current implementation 9837 * when the irq is masked/disabled or the consumer side (KVM 9838 * int this case doesn't want to receive the interrupts. 9839 */ 9840 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 9841 if (ret) 9842 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 9843 " fails: %d\n", irqfd->consumer.token, ret); 9844 } 9845 9846 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 9847 uint32_t guest_irq, bool set) 9848 { 9849 if (!kvm_x86_ops->update_pi_irte) 9850 return -EINVAL; 9851 9852 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); 9853 } 9854 9855 bool kvm_vector_hashing_enabled(void) 9856 { 9857 return vector_hashing; 9858 } 9859 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled); 9860 9861 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 9862 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 9863 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 9864 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 9865 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 9866 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 9867 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 9868 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 9869 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 9870 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 9871 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 9872 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 9873 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 9874 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 9875 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 9876 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 9877 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 9878 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 9879 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 9880