1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * derived from drivers/kvm/kvm_main.c 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright (C) 2008 Qumranet, Inc. 9 * Copyright IBM Corporation, 2008 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 11 * 12 * Authors: 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * Amit Shah <amit.shah@qumranet.com> 16 * Ben-Ami Yassour <benami@il.ibm.com> 17 */ 18 19 #include <linux/kvm_host.h> 20 #include "irq.h" 21 #include "ioapic.h" 22 #include "mmu.h" 23 #include "i8254.h" 24 #include "tss.h" 25 #include "kvm_cache_regs.h" 26 #include "kvm_emulate.h" 27 #include "x86.h" 28 #include "cpuid.h" 29 #include "pmu.h" 30 #include "hyperv.h" 31 #include "lapic.h" 32 33 #include <linux/clocksource.h> 34 #include <linux/interrupt.h> 35 #include <linux/kvm.h> 36 #include <linux/fs.h> 37 #include <linux/vmalloc.h> 38 #include <linux/export.h> 39 #include <linux/moduleparam.h> 40 #include <linux/mman.h> 41 #include <linux/highmem.h> 42 #include <linux/iommu.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/cpufreq.h> 45 #include <linux/user-return-notifier.h> 46 #include <linux/srcu.h> 47 #include <linux/slab.h> 48 #include <linux/perf_event.h> 49 #include <linux/uaccess.h> 50 #include <linux/hash.h> 51 #include <linux/pci.h> 52 #include <linux/timekeeper_internal.h> 53 #include <linux/pvclock_gtod.h> 54 #include <linux/kvm_irqfd.h> 55 #include <linux/irqbypass.h> 56 #include <linux/sched/stat.h> 57 #include <linux/sched/isolation.h> 58 #include <linux/mem_encrypt.h> 59 #include <linux/entry-kvm.h> 60 61 #include <trace/events/kvm.h> 62 63 #include <asm/debugreg.h> 64 #include <asm/msr.h> 65 #include <asm/desc.h> 66 #include <asm/mce.h> 67 #include <linux/kernel_stat.h> 68 #include <asm/fpu/internal.h> /* Ugh! */ 69 #include <asm/pvclock.h> 70 #include <asm/div64.h> 71 #include <asm/irq_remapping.h> 72 #include <asm/mshyperv.h> 73 #include <asm/hypervisor.h> 74 #include <asm/tlbflush.h> 75 #include <asm/intel_pt.h> 76 #include <asm/emulate_prefix.h> 77 #include <clocksource/hyperv_timer.h> 78 79 #define CREATE_TRACE_POINTS 80 #include "trace.h" 81 82 #define MAX_IO_MSRS 256 83 #define KVM_MAX_MCE_BANKS 32 84 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 85 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 86 87 #define emul_to_vcpu(ctxt) \ 88 ((struct kvm_vcpu *)(ctxt)->vcpu) 89 90 /* EFER defaults: 91 * - enable syscall per default because its emulated by KVM 92 * - enable LME and LMA per default on 64 bit KVM 93 */ 94 #ifdef CONFIG_X86_64 95 static 96 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 97 #else 98 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 99 #endif 100 101 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; 102 103 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 104 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 105 106 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 107 static void process_nmi(struct kvm_vcpu *vcpu); 108 static void process_smi(struct kvm_vcpu *vcpu); 109 static void enter_smm(struct kvm_vcpu *vcpu); 110 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 111 static void store_regs(struct kvm_vcpu *vcpu); 112 static int sync_regs(struct kvm_vcpu *vcpu); 113 114 struct kvm_x86_ops kvm_x86_ops __read_mostly; 115 EXPORT_SYMBOL_GPL(kvm_x86_ops); 116 117 static bool __read_mostly ignore_msrs = 0; 118 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 119 120 static bool __read_mostly report_ignored_msrs = true; 121 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 122 123 unsigned int min_timer_period_us = 200; 124 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 125 126 static bool __read_mostly kvmclock_periodic_sync = true; 127 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 128 129 bool __read_mostly kvm_has_tsc_control; 130 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 131 u32 __read_mostly kvm_max_guest_tsc_khz; 132 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 133 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 134 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 135 u64 __read_mostly kvm_max_tsc_scaling_ratio; 136 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 137 u64 __read_mostly kvm_default_tsc_scaling_ratio; 138 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 139 140 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 141 static u32 __read_mostly tsc_tolerance_ppm = 250; 142 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 143 144 /* 145 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 146 * adaptive tuning starting from default advancment of 1000ns. '0' disables 147 * advancement entirely. Any other value is used as-is and disables adaptive 148 * tuning, i.e. allows priveleged userspace to set an exact advancement time. 149 */ 150 static int __read_mostly lapic_timer_advance_ns = -1; 151 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); 152 153 static bool __read_mostly vector_hashing = true; 154 module_param(vector_hashing, bool, S_IRUGO); 155 156 bool __read_mostly enable_vmware_backdoor = false; 157 module_param(enable_vmware_backdoor, bool, S_IRUGO); 158 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 159 160 static bool __read_mostly force_emulation_prefix = false; 161 module_param(force_emulation_prefix, bool, S_IRUGO); 162 163 int __read_mostly pi_inject_timer = -1; 164 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); 165 166 /* 167 * Restoring the host value for MSRs that are only consumed when running in 168 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU 169 * returns to userspace, i.e. the kernel can run with the guest's value. 170 */ 171 #define KVM_MAX_NR_USER_RETURN_MSRS 16 172 173 struct kvm_user_return_msrs_global { 174 int nr; 175 u32 msrs[KVM_MAX_NR_USER_RETURN_MSRS]; 176 }; 177 178 struct kvm_user_return_msrs { 179 struct user_return_notifier urn; 180 bool registered; 181 struct kvm_user_return_msr_values { 182 u64 host; 183 u64 curr; 184 } values[KVM_MAX_NR_USER_RETURN_MSRS]; 185 }; 186 187 static struct kvm_user_return_msrs_global __read_mostly user_return_msrs_global; 188 static struct kvm_user_return_msrs __percpu *user_return_msrs; 189 190 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 191 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 192 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 193 | XFEATURE_MASK_PKRU) 194 195 u64 __read_mostly host_efer; 196 EXPORT_SYMBOL_GPL(host_efer); 197 198 bool __read_mostly allow_smaller_maxphyaddr = 0; 199 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); 200 201 u64 __read_mostly host_xss; 202 EXPORT_SYMBOL_GPL(host_xss); 203 u64 __read_mostly supported_xss; 204 EXPORT_SYMBOL_GPL(supported_xss); 205 206 struct kvm_stats_debugfs_item debugfs_entries[] = { 207 VCPU_STAT("pf_fixed", pf_fixed), 208 VCPU_STAT("pf_guest", pf_guest), 209 VCPU_STAT("tlb_flush", tlb_flush), 210 VCPU_STAT("invlpg", invlpg), 211 VCPU_STAT("exits", exits), 212 VCPU_STAT("io_exits", io_exits), 213 VCPU_STAT("mmio_exits", mmio_exits), 214 VCPU_STAT("signal_exits", signal_exits), 215 VCPU_STAT("irq_window", irq_window_exits), 216 VCPU_STAT("nmi_window", nmi_window_exits), 217 VCPU_STAT("halt_exits", halt_exits), 218 VCPU_STAT("halt_successful_poll", halt_successful_poll), 219 VCPU_STAT("halt_attempted_poll", halt_attempted_poll), 220 VCPU_STAT("halt_poll_invalid", halt_poll_invalid), 221 VCPU_STAT("halt_wakeup", halt_wakeup), 222 VCPU_STAT("hypercalls", hypercalls), 223 VCPU_STAT("request_irq", request_irq_exits), 224 VCPU_STAT("irq_exits", irq_exits), 225 VCPU_STAT("host_state_reload", host_state_reload), 226 VCPU_STAT("fpu_reload", fpu_reload), 227 VCPU_STAT("insn_emulation", insn_emulation), 228 VCPU_STAT("insn_emulation_fail", insn_emulation_fail), 229 VCPU_STAT("irq_injections", irq_injections), 230 VCPU_STAT("nmi_injections", nmi_injections), 231 VCPU_STAT("req_event", req_event), 232 VCPU_STAT("l1d_flush", l1d_flush), 233 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns), 234 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns), 235 VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped), 236 VM_STAT("mmu_pte_write", mmu_pte_write), 237 VM_STAT("mmu_pte_updated", mmu_pte_updated), 238 VM_STAT("mmu_pde_zapped", mmu_pde_zapped), 239 VM_STAT("mmu_flooded", mmu_flooded), 240 VM_STAT("mmu_recycled", mmu_recycled), 241 VM_STAT("mmu_cache_miss", mmu_cache_miss), 242 VM_STAT("mmu_unsync", mmu_unsync), 243 VM_STAT("remote_tlb_flush", remote_tlb_flush), 244 VM_STAT("largepages", lpages, .mode = 0444), 245 VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444), 246 VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions), 247 { NULL } 248 }; 249 250 u64 __read_mostly host_xcr0; 251 u64 __read_mostly supported_xcr0; 252 EXPORT_SYMBOL_GPL(supported_xcr0); 253 254 static struct kmem_cache *x86_fpu_cache; 255 256 static struct kmem_cache *x86_emulator_cache; 257 258 /* 259 * When called, it means the previous get/set msr reached an invalid msr. 260 * Return true if we want to ignore/silent this failed msr access. 261 */ 262 static bool kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr, 263 u64 data, bool write) 264 { 265 const char *op = write ? "wrmsr" : "rdmsr"; 266 267 if (ignore_msrs) { 268 if (report_ignored_msrs) 269 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", 270 op, msr, data); 271 /* Mask the error */ 272 return true; 273 } else { 274 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", 275 op, msr, data); 276 return false; 277 } 278 } 279 280 static struct kmem_cache *kvm_alloc_emulator_cache(void) 281 { 282 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); 283 unsigned int size = sizeof(struct x86_emulate_ctxt); 284 285 return kmem_cache_create_usercopy("x86_emulator", size, 286 __alignof__(struct x86_emulate_ctxt), 287 SLAB_ACCOUNT, useroffset, 288 size - useroffset, NULL); 289 } 290 291 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 292 293 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 294 { 295 int i; 296 for (i = 0; i < ASYNC_PF_PER_VCPU; i++) 297 vcpu->arch.apf.gfns[i] = ~0; 298 } 299 300 static void kvm_on_user_return(struct user_return_notifier *urn) 301 { 302 unsigned slot; 303 struct kvm_user_return_msrs *msrs 304 = container_of(urn, struct kvm_user_return_msrs, urn); 305 struct kvm_user_return_msr_values *values; 306 unsigned long flags; 307 308 /* 309 * Disabling irqs at this point since the following code could be 310 * interrupted and executed through kvm_arch_hardware_disable() 311 */ 312 local_irq_save(flags); 313 if (msrs->registered) { 314 msrs->registered = false; 315 user_return_notifier_unregister(urn); 316 } 317 local_irq_restore(flags); 318 for (slot = 0; slot < user_return_msrs_global.nr; ++slot) { 319 values = &msrs->values[slot]; 320 if (values->host != values->curr) { 321 wrmsrl(user_return_msrs_global.msrs[slot], values->host); 322 values->curr = values->host; 323 } 324 } 325 } 326 327 void kvm_define_user_return_msr(unsigned slot, u32 msr) 328 { 329 BUG_ON(slot >= KVM_MAX_NR_USER_RETURN_MSRS); 330 user_return_msrs_global.msrs[slot] = msr; 331 if (slot >= user_return_msrs_global.nr) 332 user_return_msrs_global.nr = slot + 1; 333 } 334 EXPORT_SYMBOL_GPL(kvm_define_user_return_msr); 335 336 static void kvm_user_return_msr_cpu_online(void) 337 { 338 unsigned int cpu = smp_processor_id(); 339 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 340 u64 value; 341 int i; 342 343 for (i = 0; i < user_return_msrs_global.nr; ++i) { 344 rdmsrl_safe(user_return_msrs_global.msrs[i], &value); 345 msrs->values[i].host = value; 346 msrs->values[i].curr = value; 347 } 348 } 349 350 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) 351 { 352 unsigned int cpu = smp_processor_id(); 353 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 354 int err; 355 356 value = (value & mask) | (msrs->values[slot].host & ~mask); 357 if (value == msrs->values[slot].curr) 358 return 0; 359 err = wrmsrl_safe(user_return_msrs_global.msrs[slot], value); 360 if (err) 361 return 1; 362 363 msrs->values[slot].curr = value; 364 if (!msrs->registered) { 365 msrs->urn.on_user_return = kvm_on_user_return; 366 user_return_notifier_register(&msrs->urn); 367 msrs->registered = true; 368 } 369 return 0; 370 } 371 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); 372 373 static void drop_user_return_notifiers(void) 374 { 375 unsigned int cpu = smp_processor_id(); 376 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 377 378 if (msrs->registered) 379 kvm_on_user_return(&msrs->urn); 380 } 381 382 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 383 { 384 return vcpu->arch.apic_base; 385 } 386 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 387 388 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 389 { 390 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 391 } 392 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 393 394 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 395 { 396 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 397 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 398 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | 399 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 400 401 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 402 return 1; 403 if (!msr_info->host_initiated) { 404 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 405 return 1; 406 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 407 return 1; 408 } 409 410 kvm_lapic_set_base(vcpu, msr_info->data); 411 kvm_recalculate_apic_map(vcpu->kvm); 412 return 0; 413 } 414 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 415 416 asmlinkage __visible noinstr void kvm_spurious_fault(void) 417 { 418 /* Fault while not rebooting. We want the trace. */ 419 BUG_ON(!kvm_rebooting); 420 } 421 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 422 423 #define EXCPT_BENIGN 0 424 #define EXCPT_CONTRIBUTORY 1 425 #define EXCPT_PF 2 426 427 static int exception_class(int vector) 428 { 429 switch (vector) { 430 case PF_VECTOR: 431 return EXCPT_PF; 432 case DE_VECTOR: 433 case TS_VECTOR: 434 case NP_VECTOR: 435 case SS_VECTOR: 436 case GP_VECTOR: 437 return EXCPT_CONTRIBUTORY; 438 default: 439 break; 440 } 441 return EXCPT_BENIGN; 442 } 443 444 #define EXCPT_FAULT 0 445 #define EXCPT_TRAP 1 446 #define EXCPT_ABORT 2 447 #define EXCPT_INTERRUPT 3 448 449 static int exception_type(int vector) 450 { 451 unsigned int mask; 452 453 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 454 return EXCPT_INTERRUPT; 455 456 mask = 1 << vector; 457 458 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 459 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 460 return EXCPT_TRAP; 461 462 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 463 return EXCPT_ABORT; 464 465 /* Reserved exceptions will result in fault */ 466 return EXCPT_FAULT; 467 } 468 469 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 470 { 471 unsigned nr = vcpu->arch.exception.nr; 472 bool has_payload = vcpu->arch.exception.has_payload; 473 unsigned long payload = vcpu->arch.exception.payload; 474 475 if (!has_payload) 476 return; 477 478 switch (nr) { 479 case DB_VECTOR: 480 /* 481 * "Certain debug exceptions may clear bit 0-3. The 482 * remaining contents of the DR6 register are never 483 * cleared by the processor". 484 */ 485 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 486 /* 487 * DR6.RTM is set by all #DB exceptions that don't clear it. 488 */ 489 vcpu->arch.dr6 |= DR6_RTM; 490 vcpu->arch.dr6 |= payload; 491 /* 492 * Bit 16 should be set in the payload whenever the #DB 493 * exception should clear DR6.RTM. This makes the payload 494 * compatible with the pending debug exceptions under VMX. 495 * Though not currently documented in the SDM, this also 496 * makes the payload compatible with the exit qualification 497 * for #DB exceptions under VMX. 498 */ 499 vcpu->arch.dr6 ^= payload & DR6_RTM; 500 501 /* 502 * The #DB payload is defined as compatible with the 'pending 503 * debug exceptions' field under VMX, not DR6. While bit 12 is 504 * defined in the 'pending debug exceptions' field (enabled 505 * breakpoint), it is reserved and must be zero in DR6. 506 */ 507 vcpu->arch.dr6 &= ~BIT(12); 508 break; 509 case PF_VECTOR: 510 vcpu->arch.cr2 = payload; 511 break; 512 } 513 514 vcpu->arch.exception.has_payload = false; 515 vcpu->arch.exception.payload = 0; 516 } 517 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 518 519 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 520 unsigned nr, bool has_error, u32 error_code, 521 bool has_payload, unsigned long payload, bool reinject) 522 { 523 u32 prev_nr; 524 int class1, class2; 525 526 kvm_make_request(KVM_REQ_EVENT, vcpu); 527 528 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 529 queue: 530 if (has_error && !is_protmode(vcpu)) 531 has_error = false; 532 if (reinject) { 533 /* 534 * On vmentry, vcpu->arch.exception.pending is only 535 * true if an event injection was blocked by 536 * nested_run_pending. In that case, however, 537 * vcpu_enter_guest requests an immediate exit, 538 * and the guest shouldn't proceed far enough to 539 * need reinjection. 540 */ 541 WARN_ON_ONCE(vcpu->arch.exception.pending); 542 vcpu->arch.exception.injected = true; 543 if (WARN_ON_ONCE(has_payload)) { 544 /* 545 * A reinjected event has already 546 * delivered its payload. 547 */ 548 has_payload = false; 549 payload = 0; 550 } 551 } else { 552 vcpu->arch.exception.pending = true; 553 vcpu->arch.exception.injected = false; 554 } 555 vcpu->arch.exception.has_error_code = has_error; 556 vcpu->arch.exception.nr = nr; 557 vcpu->arch.exception.error_code = error_code; 558 vcpu->arch.exception.has_payload = has_payload; 559 vcpu->arch.exception.payload = payload; 560 if (!is_guest_mode(vcpu)) 561 kvm_deliver_exception_payload(vcpu); 562 return; 563 } 564 565 /* to check exception */ 566 prev_nr = vcpu->arch.exception.nr; 567 if (prev_nr == DF_VECTOR) { 568 /* triple fault -> shutdown */ 569 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 570 return; 571 } 572 class1 = exception_class(prev_nr); 573 class2 = exception_class(nr); 574 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 575 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 576 /* 577 * Generate double fault per SDM Table 5-5. Set 578 * exception.pending = true so that the double fault 579 * can trigger a nested vmexit. 580 */ 581 vcpu->arch.exception.pending = true; 582 vcpu->arch.exception.injected = false; 583 vcpu->arch.exception.has_error_code = true; 584 vcpu->arch.exception.nr = DF_VECTOR; 585 vcpu->arch.exception.error_code = 0; 586 vcpu->arch.exception.has_payload = false; 587 vcpu->arch.exception.payload = 0; 588 } else 589 /* replace previous exception with a new one in a hope 590 that instruction re-execution will regenerate lost 591 exception */ 592 goto queue; 593 } 594 595 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 596 { 597 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 598 } 599 EXPORT_SYMBOL_GPL(kvm_queue_exception); 600 601 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 602 { 603 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 604 } 605 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 606 607 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 608 unsigned long payload) 609 { 610 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 611 } 612 EXPORT_SYMBOL_GPL(kvm_queue_exception_p); 613 614 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 615 u32 error_code, unsigned long payload) 616 { 617 kvm_multiple_exception(vcpu, nr, true, error_code, 618 true, payload, false); 619 } 620 621 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 622 { 623 if (err) 624 kvm_inject_gp(vcpu, 0); 625 else 626 return kvm_skip_emulated_instruction(vcpu); 627 628 return 1; 629 } 630 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 631 632 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 633 { 634 ++vcpu->stat.pf_guest; 635 vcpu->arch.exception.nested_apf = 636 is_guest_mode(vcpu) && fault->async_page_fault; 637 if (vcpu->arch.exception.nested_apf) { 638 vcpu->arch.apf.nested_apf_token = fault->address; 639 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 640 } else { 641 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 642 fault->address); 643 } 644 } 645 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 646 647 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 648 struct x86_exception *fault) 649 { 650 struct kvm_mmu *fault_mmu; 651 WARN_ON_ONCE(fault->vector != PF_VECTOR); 652 653 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : 654 vcpu->arch.walk_mmu; 655 656 /* 657 * Invalidate the TLB entry for the faulting address, if it exists, 658 * else the access will fault indefinitely (and to emulate hardware). 659 */ 660 if ((fault->error_code & PFERR_PRESENT_MASK) && 661 !(fault->error_code & PFERR_RSVD_MASK)) 662 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, 663 fault_mmu->root_hpa); 664 665 fault_mmu->inject_page_fault(vcpu, fault); 666 return fault->nested_page_fault; 667 } 668 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); 669 670 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 671 { 672 atomic_inc(&vcpu->arch.nmi_queued); 673 kvm_make_request(KVM_REQ_NMI, vcpu); 674 } 675 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 676 677 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 678 { 679 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 680 } 681 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 682 683 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 684 { 685 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 686 } 687 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 688 689 /* 690 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 691 * a #GP and return false. 692 */ 693 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 694 { 695 if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl) 696 return true; 697 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 698 return false; 699 } 700 EXPORT_SYMBOL_GPL(kvm_require_cpl); 701 702 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 703 { 704 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 705 return true; 706 707 kvm_queue_exception(vcpu, UD_VECTOR); 708 return false; 709 } 710 EXPORT_SYMBOL_GPL(kvm_require_dr); 711 712 /* 713 * This function will be used to read from the physical memory of the currently 714 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 715 * can read from guest physical or from the guest's guest physical memory. 716 */ 717 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 718 gfn_t ngfn, void *data, int offset, int len, 719 u32 access) 720 { 721 struct x86_exception exception; 722 gfn_t real_gfn; 723 gpa_t ngpa; 724 725 ngpa = gfn_to_gpa(ngfn); 726 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 727 if (real_gfn == UNMAPPED_GVA) 728 return -EFAULT; 729 730 real_gfn = gpa_to_gfn(real_gfn); 731 732 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 733 } 734 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 735 736 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 737 void *data, int offset, int len, u32 access) 738 { 739 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 740 data, offset, len, access); 741 } 742 743 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) 744 { 745 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) | 746 rsvd_bits(1, 2); 747 } 748 749 /* 750 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. 751 */ 752 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 753 { 754 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 755 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 756 int i; 757 int ret; 758 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 759 760 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 761 offset * sizeof(u64), sizeof(pdpte), 762 PFERR_USER_MASK|PFERR_WRITE_MASK); 763 if (ret < 0) { 764 ret = 0; 765 goto out; 766 } 767 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 768 if ((pdpte[i] & PT_PRESENT_MASK) && 769 (pdpte[i] & pdptr_rsvd_bits(vcpu))) { 770 ret = 0; 771 goto out; 772 } 773 } 774 ret = 1; 775 776 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 777 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 778 779 out: 780 781 return ret; 782 } 783 EXPORT_SYMBOL_GPL(load_pdptrs); 784 785 bool pdptrs_changed(struct kvm_vcpu *vcpu) 786 { 787 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 788 int offset; 789 gfn_t gfn; 790 int r; 791 792 if (!is_pae_paging(vcpu)) 793 return false; 794 795 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR)) 796 return true; 797 798 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; 799 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); 800 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 801 PFERR_USER_MASK | PFERR_WRITE_MASK); 802 if (r < 0) 803 return true; 804 805 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 806 } 807 EXPORT_SYMBOL_GPL(pdptrs_changed); 808 809 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) 810 { 811 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 812 813 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 814 kvm_clear_async_pf_completion_queue(vcpu); 815 kvm_async_pf_hash_reset(vcpu); 816 } 817 818 if ((cr0 ^ old_cr0) & update_bits) 819 kvm_mmu_reset_context(vcpu); 820 821 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 822 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 823 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 824 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 825 } 826 EXPORT_SYMBOL_GPL(kvm_post_set_cr0); 827 828 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 829 { 830 unsigned long old_cr0 = kvm_read_cr0(vcpu); 831 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; 832 833 cr0 |= X86_CR0_ET; 834 835 #ifdef CONFIG_X86_64 836 if (cr0 & 0xffffffff00000000UL) 837 return 1; 838 #endif 839 840 cr0 &= ~CR0_RESERVED_BITS; 841 842 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 843 return 1; 844 845 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 846 return 1; 847 848 #ifdef CONFIG_X86_64 849 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && 850 (cr0 & X86_CR0_PG)) { 851 int cs_db, cs_l; 852 853 if (!is_pae(vcpu)) 854 return 1; 855 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 856 if (cs_l) 857 return 1; 858 } 859 #endif 860 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && 861 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && 862 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) 863 return 1; 864 865 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 866 return 1; 867 868 kvm_x86_ops.set_cr0(vcpu, cr0); 869 870 kvm_post_set_cr0(vcpu, old_cr0, cr0); 871 872 return 0; 873 } 874 EXPORT_SYMBOL_GPL(kvm_set_cr0); 875 876 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 877 { 878 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 879 } 880 EXPORT_SYMBOL_GPL(kvm_lmsw); 881 882 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) 883 { 884 if (vcpu->arch.guest_state_protected) 885 return; 886 887 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 888 889 if (vcpu->arch.xcr0 != host_xcr0) 890 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 891 892 if (vcpu->arch.xsaves_enabled && 893 vcpu->arch.ia32_xss != host_xss) 894 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 895 } 896 897 if (static_cpu_has(X86_FEATURE_PKU) && 898 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 899 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && 900 vcpu->arch.pkru != vcpu->arch.host_pkru) 901 __write_pkru(vcpu->arch.pkru); 902 } 903 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); 904 905 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) 906 { 907 if (vcpu->arch.guest_state_protected) 908 return; 909 910 if (static_cpu_has(X86_FEATURE_PKU) && 911 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 912 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { 913 vcpu->arch.pkru = rdpkru(); 914 if (vcpu->arch.pkru != vcpu->arch.host_pkru) 915 __write_pkru(vcpu->arch.host_pkru); 916 } 917 918 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 919 920 if (vcpu->arch.xcr0 != host_xcr0) 921 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 922 923 if (vcpu->arch.xsaves_enabled && 924 vcpu->arch.ia32_xss != host_xss) 925 wrmsrl(MSR_IA32_XSS, host_xss); 926 } 927 928 } 929 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); 930 931 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 932 { 933 u64 xcr0 = xcr; 934 u64 old_xcr0 = vcpu->arch.xcr0; 935 u64 valid_bits; 936 937 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 938 if (index != XCR_XFEATURE_ENABLED_MASK) 939 return 1; 940 if (!(xcr0 & XFEATURE_MASK_FP)) 941 return 1; 942 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 943 return 1; 944 945 /* 946 * Do not allow the guest to set bits that we do not support 947 * saving. However, xcr0 bit 0 is always set, even if the 948 * emulated CPU does not support XSAVE (see fx_init). 949 */ 950 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 951 if (xcr0 & ~valid_bits) 952 return 1; 953 954 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 955 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 956 return 1; 957 958 if (xcr0 & XFEATURE_MASK_AVX512) { 959 if (!(xcr0 & XFEATURE_MASK_YMM)) 960 return 1; 961 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 962 return 1; 963 } 964 vcpu->arch.xcr0 = xcr0; 965 966 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 967 kvm_update_cpuid_runtime(vcpu); 968 return 0; 969 } 970 971 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 972 { 973 if (kvm_x86_ops.get_cpl(vcpu) != 0 || 974 __kvm_set_xcr(vcpu, index, xcr)) { 975 kvm_inject_gp(vcpu, 0); 976 return 1; 977 } 978 return 0; 979 } 980 EXPORT_SYMBOL_GPL(kvm_set_xcr); 981 982 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 983 { 984 if (cr4 & cr4_reserved_bits) 985 return false; 986 987 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) 988 return false; 989 990 return kvm_x86_ops.is_valid_cr4(vcpu, cr4); 991 } 992 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); 993 994 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) 995 { 996 unsigned long mmu_role_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 997 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 998 999 if (((cr4 ^ old_cr4) & mmu_role_bits) || 1000 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 1001 kvm_mmu_reset_context(vcpu); 1002 } 1003 EXPORT_SYMBOL_GPL(kvm_post_set_cr4); 1004 1005 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1006 { 1007 unsigned long old_cr4 = kvm_read_cr4(vcpu); 1008 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 1009 X86_CR4_SMEP; 1010 1011 if (!kvm_is_valid_cr4(vcpu, cr4)) 1012 return 1; 1013 1014 if (is_long_mode(vcpu)) { 1015 if (!(cr4 & X86_CR4_PAE)) 1016 return 1; 1017 if ((cr4 ^ old_cr4) & X86_CR4_LA57) 1018 return 1; 1019 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 1020 && ((cr4 ^ old_cr4) & pdptr_bits) 1021 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 1022 kvm_read_cr3(vcpu))) 1023 return 1; 1024 1025 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 1026 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 1027 return 1; 1028 1029 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 1030 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 1031 return 1; 1032 } 1033 1034 kvm_x86_ops.set_cr4(vcpu, cr4); 1035 1036 kvm_post_set_cr4(vcpu, old_cr4, cr4); 1037 1038 return 0; 1039 } 1040 EXPORT_SYMBOL_GPL(kvm_set_cr4); 1041 1042 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 1043 { 1044 bool skip_tlb_flush = false; 1045 #ifdef CONFIG_X86_64 1046 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 1047 1048 if (pcid_enabled) { 1049 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 1050 cr3 &= ~X86_CR3_PCID_NOFLUSH; 1051 } 1052 #endif 1053 1054 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 1055 if (!skip_tlb_flush) { 1056 kvm_mmu_sync_roots(vcpu); 1057 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1058 } 1059 return 0; 1060 } 1061 1062 if (is_long_mode(vcpu) && 1063 (cr3 & vcpu->arch.cr3_lm_rsvd_bits)) 1064 return 1; 1065 else if (is_pae_paging(vcpu) && 1066 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 1067 return 1; 1068 1069 kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush); 1070 vcpu->arch.cr3 = cr3; 1071 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 1072 1073 return 0; 1074 } 1075 EXPORT_SYMBOL_GPL(kvm_set_cr3); 1076 1077 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 1078 { 1079 if (cr8 & CR8_RESERVED_BITS) 1080 return 1; 1081 if (lapic_in_kernel(vcpu)) 1082 kvm_lapic_set_tpr(vcpu, cr8); 1083 else 1084 vcpu->arch.cr8 = cr8; 1085 return 0; 1086 } 1087 EXPORT_SYMBOL_GPL(kvm_set_cr8); 1088 1089 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 1090 { 1091 if (lapic_in_kernel(vcpu)) 1092 return kvm_lapic_get_cr8(vcpu); 1093 else 1094 return vcpu->arch.cr8; 1095 } 1096 EXPORT_SYMBOL_GPL(kvm_get_cr8); 1097 1098 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 1099 { 1100 int i; 1101 1102 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1103 for (i = 0; i < KVM_NR_DB_REGS; i++) 1104 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1105 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 1106 } 1107 } 1108 1109 void kvm_update_dr7(struct kvm_vcpu *vcpu) 1110 { 1111 unsigned long dr7; 1112 1113 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1114 dr7 = vcpu->arch.guest_debug_dr7; 1115 else 1116 dr7 = vcpu->arch.dr7; 1117 kvm_x86_ops.set_dr7(vcpu, dr7); 1118 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1119 if (dr7 & DR7_BP_EN_MASK) 1120 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1121 } 1122 EXPORT_SYMBOL_GPL(kvm_update_dr7); 1123 1124 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1125 { 1126 u64 fixed = DR6_FIXED_1; 1127 1128 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1129 fixed |= DR6_RTM; 1130 return fixed; 1131 } 1132 1133 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1134 { 1135 size_t size = ARRAY_SIZE(vcpu->arch.db); 1136 1137 switch (dr) { 1138 case 0 ... 3: 1139 vcpu->arch.db[array_index_nospec(dr, size)] = val; 1140 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1141 vcpu->arch.eff_db[dr] = val; 1142 break; 1143 case 4: 1144 case 6: 1145 if (!kvm_dr6_valid(val)) 1146 return -1; /* #GP */ 1147 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1148 break; 1149 case 5: 1150 default: /* 7 */ 1151 if (!kvm_dr7_valid(val)) 1152 return -1; /* #GP */ 1153 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1154 kvm_update_dr7(vcpu); 1155 break; 1156 } 1157 1158 return 0; 1159 } 1160 1161 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1162 { 1163 if (__kvm_set_dr(vcpu, dr, val)) { 1164 kvm_inject_gp(vcpu, 0); 1165 return 1; 1166 } 1167 return 0; 1168 } 1169 EXPORT_SYMBOL_GPL(kvm_set_dr); 1170 1171 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1172 { 1173 size_t size = ARRAY_SIZE(vcpu->arch.db); 1174 1175 switch (dr) { 1176 case 0 ... 3: 1177 *val = vcpu->arch.db[array_index_nospec(dr, size)]; 1178 break; 1179 case 4: 1180 case 6: 1181 *val = vcpu->arch.dr6; 1182 break; 1183 case 5: 1184 default: /* 7 */ 1185 *val = vcpu->arch.dr7; 1186 break; 1187 } 1188 return 0; 1189 } 1190 EXPORT_SYMBOL_GPL(kvm_get_dr); 1191 1192 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 1193 { 1194 u32 ecx = kvm_rcx_read(vcpu); 1195 u64 data; 1196 int err; 1197 1198 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 1199 if (err) 1200 return err; 1201 kvm_rax_write(vcpu, (u32)data); 1202 kvm_rdx_write(vcpu, data >> 32); 1203 return err; 1204 } 1205 EXPORT_SYMBOL_GPL(kvm_rdpmc); 1206 1207 /* 1208 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1209 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1210 * 1211 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) 1212 * extract the supported MSRs from the related const lists. 1213 * msrs_to_save is selected from the msrs_to_save_all to reflect the 1214 * capabilities of the host cpu. This capabilities test skips MSRs that are 1215 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs 1216 * may depend on host virtualization features rather than host cpu features. 1217 */ 1218 1219 static const u32 msrs_to_save_all[] = { 1220 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1221 MSR_STAR, 1222 #ifdef CONFIG_X86_64 1223 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1224 #endif 1225 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1226 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1227 MSR_IA32_SPEC_CTRL, 1228 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1229 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1230 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1231 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1232 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1233 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1234 MSR_IA32_UMWAIT_CONTROL, 1235 1236 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, 1237 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, 1238 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, 1239 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 1240 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, 1241 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, 1242 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, 1243 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, 1244 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, 1245 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, 1246 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, 1247 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, 1248 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, 1249 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, 1250 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, 1251 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, 1252 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, 1253 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, 1254 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, 1255 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, 1256 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, 1257 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, 1258 }; 1259 1260 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; 1261 static unsigned num_msrs_to_save; 1262 1263 static const u32 emulated_msrs_all[] = { 1264 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1265 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1266 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1267 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1268 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1269 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1270 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1271 HV_X64_MSR_RESET, 1272 HV_X64_MSR_VP_INDEX, 1273 HV_X64_MSR_VP_RUNTIME, 1274 HV_X64_MSR_SCONTROL, 1275 HV_X64_MSR_STIMER0_CONFIG, 1276 HV_X64_MSR_VP_ASSIST_PAGE, 1277 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1278 HV_X64_MSR_TSC_EMULATION_STATUS, 1279 HV_X64_MSR_SYNDBG_OPTIONS, 1280 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, 1281 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, 1282 HV_X64_MSR_SYNDBG_PENDING_BUFFER, 1283 1284 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1285 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, 1286 1287 MSR_IA32_TSC_ADJUST, 1288 MSR_IA32_TSCDEADLINE, 1289 MSR_IA32_ARCH_CAPABILITIES, 1290 MSR_IA32_PERF_CAPABILITIES, 1291 MSR_IA32_MISC_ENABLE, 1292 MSR_IA32_MCG_STATUS, 1293 MSR_IA32_MCG_CTL, 1294 MSR_IA32_MCG_EXT_CTL, 1295 MSR_IA32_SMBASE, 1296 MSR_SMI_COUNT, 1297 MSR_PLATFORM_INFO, 1298 MSR_MISC_FEATURES_ENABLES, 1299 MSR_AMD64_VIRT_SPEC_CTRL, 1300 MSR_IA32_POWER_CTL, 1301 MSR_IA32_UCODE_REV, 1302 1303 /* 1304 * The following list leaves out MSRs whose values are determined 1305 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. 1306 * We always support the "true" VMX control MSRs, even if the host 1307 * processor does not, so I am putting these registers here rather 1308 * than in msrs_to_save_all. 1309 */ 1310 MSR_IA32_VMX_BASIC, 1311 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1312 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1313 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1314 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1315 MSR_IA32_VMX_MISC, 1316 MSR_IA32_VMX_CR0_FIXED0, 1317 MSR_IA32_VMX_CR4_FIXED0, 1318 MSR_IA32_VMX_VMCS_ENUM, 1319 MSR_IA32_VMX_PROCBASED_CTLS2, 1320 MSR_IA32_VMX_EPT_VPID_CAP, 1321 MSR_IA32_VMX_VMFUNC, 1322 1323 MSR_K7_HWCR, 1324 MSR_KVM_POLL_CONTROL, 1325 }; 1326 1327 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; 1328 static unsigned num_emulated_msrs; 1329 1330 /* 1331 * List of msr numbers which are used to expose MSR-based features that 1332 * can be used by a hypervisor to validate requested CPU features. 1333 */ 1334 static const u32 msr_based_features_all[] = { 1335 MSR_IA32_VMX_BASIC, 1336 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1337 MSR_IA32_VMX_PINBASED_CTLS, 1338 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1339 MSR_IA32_VMX_PROCBASED_CTLS, 1340 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1341 MSR_IA32_VMX_EXIT_CTLS, 1342 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1343 MSR_IA32_VMX_ENTRY_CTLS, 1344 MSR_IA32_VMX_MISC, 1345 MSR_IA32_VMX_CR0_FIXED0, 1346 MSR_IA32_VMX_CR0_FIXED1, 1347 MSR_IA32_VMX_CR4_FIXED0, 1348 MSR_IA32_VMX_CR4_FIXED1, 1349 MSR_IA32_VMX_VMCS_ENUM, 1350 MSR_IA32_VMX_PROCBASED_CTLS2, 1351 MSR_IA32_VMX_EPT_VPID_CAP, 1352 MSR_IA32_VMX_VMFUNC, 1353 1354 MSR_F10H_DECFG, 1355 MSR_IA32_UCODE_REV, 1356 MSR_IA32_ARCH_CAPABILITIES, 1357 MSR_IA32_PERF_CAPABILITIES, 1358 }; 1359 1360 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; 1361 static unsigned int num_msr_based_features; 1362 1363 static u64 kvm_get_arch_capabilities(void) 1364 { 1365 u64 data = 0; 1366 1367 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1368 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); 1369 1370 /* 1371 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that 1372 * the nested hypervisor runs with NX huge pages. If it is not, 1373 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other 1374 * L1 guests, so it need not worry about its own (L2) guests. 1375 */ 1376 data |= ARCH_CAP_PSCHANGE_MC_NO; 1377 1378 /* 1379 * If we're doing cache flushes (either "always" or "cond") 1380 * we will do one whenever the guest does a vmlaunch/vmresume. 1381 * If an outer hypervisor is doing the cache flush for us 1382 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1383 * capability to the guest too, and if EPT is disabled we're not 1384 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1385 * require a nested hypervisor to do a flush of its own. 1386 */ 1387 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1388 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1389 1390 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) 1391 data |= ARCH_CAP_RDCL_NO; 1392 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1393 data |= ARCH_CAP_SSB_NO; 1394 if (!boot_cpu_has_bug(X86_BUG_MDS)) 1395 data |= ARCH_CAP_MDS_NO; 1396 1397 /* 1398 * On TAA affected systems: 1399 * - nothing to do if TSX is disabled on the host. 1400 * - we emulate TSX_CTRL if present on the host. 1401 * This lets the guest use VERW to clear CPU buffers. 1402 */ 1403 if (!boot_cpu_has(X86_FEATURE_RTM)) 1404 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR); 1405 else if (!boot_cpu_has_bug(X86_BUG_TAA)) 1406 data |= ARCH_CAP_TAA_NO; 1407 1408 return data; 1409 } 1410 1411 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1412 { 1413 switch (msr->index) { 1414 case MSR_IA32_ARCH_CAPABILITIES: 1415 msr->data = kvm_get_arch_capabilities(); 1416 break; 1417 case MSR_IA32_UCODE_REV: 1418 rdmsrl_safe(msr->index, &msr->data); 1419 break; 1420 default: 1421 return kvm_x86_ops.get_msr_feature(msr); 1422 } 1423 return 0; 1424 } 1425 1426 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1427 { 1428 struct kvm_msr_entry msr; 1429 int r; 1430 1431 msr.index = index; 1432 r = kvm_get_msr_feature(&msr); 1433 1434 if (r == KVM_MSR_RET_INVALID) { 1435 /* Unconditionally clear the output for simplicity */ 1436 *data = 0; 1437 if (kvm_msr_ignored_check(vcpu, index, 0, false)) 1438 r = 0; 1439 } 1440 1441 if (r) 1442 return r; 1443 1444 *data = msr.data; 1445 1446 return 0; 1447 } 1448 1449 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1450 { 1451 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1452 return false; 1453 1454 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1455 return false; 1456 1457 if (efer & (EFER_LME | EFER_LMA) && 1458 !guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1459 return false; 1460 1461 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) 1462 return false; 1463 1464 return true; 1465 1466 } 1467 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1468 { 1469 if (efer & efer_reserved_bits) 1470 return false; 1471 1472 return __kvm_valid_efer(vcpu, efer); 1473 } 1474 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1475 1476 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1477 { 1478 u64 old_efer = vcpu->arch.efer; 1479 u64 efer = msr_info->data; 1480 int r; 1481 1482 if (efer & efer_reserved_bits) 1483 return 1; 1484 1485 if (!msr_info->host_initiated) { 1486 if (!__kvm_valid_efer(vcpu, efer)) 1487 return 1; 1488 1489 if (is_paging(vcpu) && 1490 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1491 return 1; 1492 } 1493 1494 efer &= ~EFER_LMA; 1495 efer |= vcpu->arch.efer & EFER_LMA; 1496 1497 r = kvm_x86_ops.set_efer(vcpu, efer); 1498 if (r) { 1499 WARN_ON(r > 0); 1500 return r; 1501 } 1502 1503 /* Update reserved bits */ 1504 if ((efer ^ old_efer) & EFER_NX) 1505 kvm_mmu_reset_context(vcpu); 1506 1507 return 0; 1508 } 1509 1510 void kvm_enable_efer_bits(u64 mask) 1511 { 1512 efer_reserved_bits &= ~mask; 1513 } 1514 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1515 1516 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) 1517 { 1518 struct kvm *kvm = vcpu->kvm; 1519 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges; 1520 u32 count = kvm->arch.msr_filter.count; 1521 u32 i; 1522 bool r = kvm->arch.msr_filter.default_allow; 1523 int idx; 1524 1525 /* MSR filtering not set up or x2APIC enabled, allow everything */ 1526 if (!count || (index >= 0x800 && index <= 0x8ff)) 1527 return true; 1528 1529 /* Prevent collision with set_msr_filter */ 1530 idx = srcu_read_lock(&kvm->srcu); 1531 1532 for (i = 0; i < count; i++) { 1533 u32 start = ranges[i].base; 1534 u32 end = start + ranges[i].nmsrs; 1535 u32 flags = ranges[i].flags; 1536 unsigned long *bitmap = ranges[i].bitmap; 1537 1538 if ((index >= start) && (index < end) && (flags & type)) { 1539 r = !!test_bit(index - start, bitmap); 1540 break; 1541 } 1542 } 1543 1544 srcu_read_unlock(&kvm->srcu, idx); 1545 1546 return r; 1547 } 1548 EXPORT_SYMBOL_GPL(kvm_msr_allowed); 1549 1550 /* 1551 * Write @data into the MSR specified by @index. Select MSR specific fault 1552 * checks are bypassed if @host_initiated is %true. 1553 * Returns 0 on success, non-0 otherwise. 1554 * Assumes vcpu_load() was already called. 1555 */ 1556 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, 1557 bool host_initiated) 1558 { 1559 struct msr_data msr; 1560 1561 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) 1562 return KVM_MSR_RET_FILTERED; 1563 1564 switch (index) { 1565 case MSR_FS_BASE: 1566 case MSR_GS_BASE: 1567 case MSR_KERNEL_GS_BASE: 1568 case MSR_CSTAR: 1569 case MSR_LSTAR: 1570 if (is_noncanonical_address(data, vcpu)) 1571 return 1; 1572 break; 1573 case MSR_IA32_SYSENTER_EIP: 1574 case MSR_IA32_SYSENTER_ESP: 1575 /* 1576 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1577 * non-canonical address is written on Intel but not on 1578 * AMD (which ignores the top 32-bits, because it does 1579 * not implement 64-bit SYSENTER). 1580 * 1581 * 64-bit code should hence be able to write a non-canonical 1582 * value on AMD. Making the address canonical ensures that 1583 * vmentry does not fail on Intel after writing a non-canonical 1584 * value, and that something deterministic happens if the guest 1585 * invokes 64-bit SYSENTER. 1586 */ 1587 data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); 1588 } 1589 1590 msr.data = data; 1591 msr.index = index; 1592 msr.host_initiated = host_initiated; 1593 1594 return kvm_x86_ops.set_msr(vcpu, &msr); 1595 } 1596 1597 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, 1598 u32 index, u64 data, bool host_initiated) 1599 { 1600 int ret = __kvm_set_msr(vcpu, index, data, host_initiated); 1601 1602 if (ret == KVM_MSR_RET_INVALID) 1603 if (kvm_msr_ignored_check(vcpu, index, data, true)) 1604 ret = 0; 1605 1606 return ret; 1607 } 1608 1609 /* 1610 * Read the MSR specified by @index into @data. Select MSR specific fault 1611 * checks are bypassed if @host_initiated is %true. 1612 * Returns 0 on success, non-0 otherwise. 1613 * Assumes vcpu_load() was already called. 1614 */ 1615 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1616 bool host_initiated) 1617 { 1618 struct msr_data msr; 1619 int ret; 1620 1621 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) 1622 return KVM_MSR_RET_FILTERED; 1623 1624 msr.index = index; 1625 msr.host_initiated = host_initiated; 1626 1627 ret = kvm_x86_ops.get_msr(vcpu, &msr); 1628 if (!ret) 1629 *data = msr.data; 1630 return ret; 1631 } 1632 1633 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, 1634 u32 index, u64 *data, bool host_initiated) 1635 { 1636 int ret = __kvm_get_msr(vcpu, index, data, host_initiated); 1637 1638 if (ret == KVM_MSR_RET_INVALID) { 1639 /* Unconditionally clear *data for simplicity */ 1640 *data = 0; 1641 if (kvm_msr_ignored_check(vcpu, index, 0, false)) 1642 ret = 0; 1643 } 1644 1645 return ret; 1646 } 1647 1648 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1649 { 1650 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1651 } 1652 EXPORT_SYMBOL_GPL(kvm_get_msr); 1653 1654 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) 1655 { 1656 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1657 } 1658 EXPORT_SYMBOL_GPL(kvm_set_msr); 1659 1660 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) 1661 { 1662 int err = vcpu->run->msr.error; 1663 if (!err) { 1664 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); 1665 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); 1666 } 1667 1668 return kvm_x86_ops.complete_emulated_msr(vcpu, err); 1669 } 1670 1671 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu) 1672 { 1673 return kvm_x86_ops.complete_emulated_msr(vcpu, vcpu->run->msr.error); 1674 } 1675 1676 static u64 kvm_msr_reason(int r) 1677 { 1678 switch (r) { 1679 case KVM_MSR_RET_INVALID: 1680 return KVM_MSR_EXIT_REASON_UNKNOWN; 1681 case KVM_MSR_RET_FILTERED: 1682 return KVM_MSR_EXIT_REASON_FILTER; 1683 default: 1684 return KVM_MSR_EXIT_REASON_INVAL; 1685 } 1686 } 1687 1688 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, 1689 u32 exit_reason, u64 data, 1690 int (*completion)(struct kvm_vcpu *vcpu), 1691 int r) 1692 { 1693 u64 msr_reason = kvm_msr_reason(r); 1694 1695 /* Check if the user wanted to know about this MSR fault */ 1696 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) 1697 return 0; 1698 1699 vcpu->run->exit_reason = exit_reason; 1700 vcpu->run->msr.error = 0; 1701 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); 1702 vcpu->run->msr.reason = msr_reason; 1703 vcpu->run->msr.index = index; 1704 vcpu->run->msr.data = data; 1705 vcpu->arch.complete_userspace_io = completion; 1706 1707 return 1; 1708 } 1709 1710 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r) 1711 { 1712 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0, 1713 complete_emulated_rdmsr, r); 1714 } 1715 1716 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r) 1717 { 1718 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data, 1719 complete_emulated_wrmsr, r); 1720 } 1721 1722 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) 1723 { 1724 u32 ecx = kvm_rcx_read(vcpu); 1725 u64 data; 1726 int r; 1727 1728 r = kvm_get_msr(vcpu, ecx, &data); 1729 1730 /* MSR read failed? See if we should ask user space */ 1731 if (r && kvm_get_msr_user_space(vcpu, ecx, r)) { 1732 /* Bounce to user space */ 1733 return 0; 1734 } 1735 1736 if (!r) { 1737 trace_kvm_msr_read(ecx, data); 1738 1739 kvm_rax_write(vcpu, data & -1u); 1740 kvm_rdx_write(vcpu, (data >> 32) & -1u); 1741 } else { 1742 trace_kvm_msr_read_ex(ecx); 1743 } 1744 1745 return kvm_x86_ops.complete_emulated_msr(vcpu, r); 1746 } 1747 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); 1748 1749 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) 1750 { 1751 u32 ecx = kvm_rcx_read(vcpu); 1752 u64 data = kvm_read_edx_eax(vcpu); 1753 int r; 1754 1755 r = kvm_set_msr(vcpu, ecx, data); 1756 1757 /* MSR write failed? See if we should ask user space */ 1758 if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) 1759 /* Bounce to user space */ 1760 return 0; 1761 1762 /* Signal all other negative errors to userspace */ 1763 if (r < 0) 1764 return r; 1765 1766 if (!r) 1767 trace_kvm_msr_write(ecx, data); 1768 else 1769 trace_kvm_msr_write_ex(ecx, data); 1770 1771 return kvm_x86_ops.complete_emulated_msr(vcpu, r); 1772 } 1773 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); 1774 1775 bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) 1776 { 1777 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || 1778 xfer_to_guest_mode_work_pending(); 1779 } 1780 EXPORT_SYMBOL_GPL(kvm_vcpu_exit_request); 1781 1782 /* 1783 * The fast path for frequent and performance sensitive wrmsr emulation, 1784 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces 1785 * the latency of virtual IPI by avoiding the expensive bits of transitioning 1786 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the 1787 * other cases which must be called after interrupts are enabled on the host. 1788 */ 1789 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) 1790 { 1791 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) 1792 return 1; 1793 1794 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && 1795 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && 1796 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && 1797 ((u32)(data >> 32) != X2APIC_BROADCAST)) { 1798 1799 data &= ~(1 << 12); 1800 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); 1801 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); 1802 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); 1803 trace_kvm_apic_write(APIC_ICR, (u32)data); 1804 return 0; 1805 } 1806 1807 return 1; 1808 } 1809 1810 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) 1811 { 1812 if (!kvm_can_use_hv_timer(vcpu)) 1813 return 1; 1814 1815 kvm_set_lapic_tscdeadline_msr(vcpu, data); 1816 return 0; 1817 } 1818 1819 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) 1820 { 1821 u32 msr = kvm_rcx_read(vcpu); 1822 u64 data; 1823 fastpath_t ret = EXIT_FASTPATH_NONE; 1824 1825 switch (msr) { 1826 case APIC_BASE_MSR + (APIC_ICR >> 4): 1827 data = kvm_read_edx_eax(vcpu); 1828 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { 1829 kvm_skip_emulated_instruction(vcpu); 1830 ret = EXIT_FASTPATH_EXIT_HANDLED; 1831 } 1832 break; 1833 case MSR_IA32_TSCDEADLINE: 1834 data = kvm_read_edx_eax(vcpu); 1835 if (!handle_fastpath_set_tscdeadline(vcpu, data)) { 1836 kvm_skip_emulated_instruction(vcpu); 1837 ret = EXIT_FASTPATH_REENTER_GUEST; 1838 } 1839 break; 1840 default: 1841 break; 1842 } 1843 1844 if (ret != EXIT_FASTPATH_NONE) 1845 trace_kvm_msr_write(msr, data); 1846 1847 return ret; 1848 } 1849 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); 1850 1851 /* 1852 * Adapt set_msr() to msr_io()'s calling convention 1853 */ 1854 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1855 { 1856 return kvm_get_msr_ignored_check(vcpu, index, data, true); 1857 } 1858 1859 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1860 { 1861 return kvm_set_msr_ignored_check(vcpu, index, *data, true); 1862 } 1863 1864 #ifdef CONFIG_X86_64 1865 struct pvclock_clock { 1866 int vclock_mode; 1867 u64 cycle_last; 1868 u64 mask; 1869 u32 mult; 1870 u32 shift; 1871 u64 base_cycles; 1872 u64 offset; 1873 }; 1874 1875 struct pvclock_gtod_data { 1876 seqcount_t seq; 1877 1878 struct pvclock_clock clock; /* extract of a clocksource struct */ 1879 struct pvclock_clock raw_clock; /* extract of a clocksource struct */ 1880 1881 ktime_t offs_boot; 1882 u64 wall_time_sec; 1883 }; 1884 1885 static struct pvclock_gtod_data pvclock_gtod_data; 1886 1887 static void update_pvclock_gtod(struct timekeeper *tk) 1888 { 1889 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1890 1891 write_seqcount_begin(&vdata->seq); 1892 1893 /* copy pvclock gtod data */ 1894 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; 1895 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1896 vdata->clock.mask = tk->tkr_mono.mask; 1897 vdata->clock.mult = tk->tkr_mono.mult; 1898 vdata->clock.shift = tk->tkr_mono.shift; 1899 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 1900 vdata->clock.offset = tk->tkr_mono.base; 1901 1902 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; 1903 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; 1904 vdata->raw_clock.mask = tk->tkr_raw.mask; 1905 vdata->raw_clock.mult = tk->tkr_raw.mult; 1906 vdata->raw_clock.shift = tk->tkr_raw.shift; 1907 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; 1908 vdata->raw_clock.offset = tk->tkr_raw.base; 1909 1910 vdata->wall_time_sec = tk->xtime_sec; 1911 1912 vdata->offs_boot = tk->offs_boot; 1913 1914 write_seqcount_end(&vdata->seq); 1915 } 1916 1917 static s64 get_kvmclock_base_ns(void) 1918 { 1919 /* Count up from boot time, but with the frequency of the raw clock. */ 1920 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); 1921 } 1922 #else 1923 static s64 get_kvmclock_base_ns(void) 1924 { 1925 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ 1926 return ktime_get_boottime_ns(); 1927 } 1928 #endif 1929 1930 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1931 { 1932 int version; 1933 int r; 1934 struct pvclock_wall_clock wc; 1935 u64 wall_nsec; 1936 1937 kvm->arch.wall_clock = wall_clock; 1938 1939 if (!wall_clock) 1940 return; 1941 1942 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1943 if (r) 1944 return; 1945 1946 if (version & 1) 1947 ++version; /* first time write, random junk */ 1948 1949 ++version; 1950 1951 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1952 return; 1953 1954 /* 1955 * The guest calculates current wall clock time by adding 1956 * system time (updated by kvm_guest_time_update below) to the 1957 * wall clock specified here. We do the reverse here. 1958 */ 1959 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); 1960 1961 wc.nsec = do_div(wall_nsec, 1000000000); 1962 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ 1963 wc.version = version; 1964 1965 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1966 1967 version++; 1968 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1969 } 1970 1971 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, 1972 bool old_msr, bool host_initiated) 1973 { 1974 struct kvm_arch *ka = &vcpu->kvm->arch; 1975 1976 if (vcpu->vcpu_id == 0 && !host_initiated) { 1977 if (ka->boot_vcpu_runs_old_kvmclock != old_msr) 1978 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1979 1980 ka->boot_vcpu_runs_old_kvmclock = old_msr; 1981 } 1982 1983 vcpu->arch.time = system_time; 1984 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 1985 1986 /* we verify if the enable bit is set... */ 1987 vcpu->arch.pv_time_enabled = false; 1988 if (!(system_time & 1)) 1989 return; 1990 1991 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, 1992 &vcpu->arch.pv_time, system_time & ~1ULL, 1993 sizeof(struct pvclock_vcpu_time_info))) 1994 vcpu->arch.pv_time_enabled = true; 1995 1996 return; 1997 } 1998 1999 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 2000 { 2001 do_shl32_div32(dividend, divisor); 2002 return dividend; 2003 } 2004 2005 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 2006 s8 *pshift, u32 *pmultiplier) 2007 { 2008 uint64_t scaled64; 2009 int32_t shift = 0; 2010 uint64_t tps64; 2011 uint32_t tps32; 2012 2013 tps64 = base_hz; 2014 scaled64 = scaled_hz; 2015 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 2016 tps64 >>= 1; 2017 shift--; 2018 } 2019 2020 tps32 = (uint32_t)tps64; 2021 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 2022 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 2023 scaled64 >>= 1; 2024 else 2025 tps32 <<= 1; 2026 shift++; 2027 } 2028 2029 *pshift = shift; 2030 *pmultiplier = div_frac(scaled64, tps32); 2031 } 2032 2033 #ifdef CONFIG_X86_64 2034 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 2035 #endif 2036 2037 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 2038 static unsigned long max_tsc_khz; 2039 2040 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 2041 { 2042 u64 v = (u64)khz * (1000000 + ppm); 2043 do_div(v, 1000000); 2044 return v; 2045 } 2046 2047 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 2048 { 2049 u64 ratio; 2050 2051 /* Guest TSC same frequency as host TSC? */ 2052 if (!scale) { 2053 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 2054 return 0; 2055 } 2056 2057 /* TSC scaling supported? */ 2058 if (!kvm_has_tsc_control) { 2059 if (user_tsc_khz > tsc_khz) { 2060 vcpu->arch.tsc_catchup = 1; 2061 vcpu->arch.tsc_always_catchup = 1; 2062 return 0; 2063 } else { 2064 pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); 2065 return -1; 2066 } 2067 } 2068 2069 /* TSC scaling required - calculate ratio */ 2070 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 2071 user_tsc_khz, tsc_khz); 2072 2073 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 2074 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 2075 user_tsc_khz); 2076 return -1; 2077 } 2078 2079 vcpu->arch.tsc_scaling_ratio = ratio; 2080 return 0; 2081 } 2082 2083 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 2084 { 2085 u32 thresh_lo, thresh_hi; 2086 int use_scaling = 0; 2087 2088 /* tsc_khz can be zero if TSC calibration fails */ 2089 if (user_tsc_khz == 0) { 2090 /* set tsc_scaling_ratio to a safe value */ 2091 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 2092 return -1; 2093 } 2094 2095 /* Compute a scale to convert nanoseconds in TSC cycles */ 2096 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 2097 &vcpu->arch.virtual_tsc_shift, 2098 &vcpu->arch.virtual_tsc_mult); 2099 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 2100 2101 /* 2102 * Compute the variation in TSC rate which is acceptable 2103 * within the range of tolerance and decide if the 2104 * rate being applied is within that bounds of the hardware 2105 * rate. If so, no scaling or compensation need be done. 2106 */ 2107 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 2108 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 2109 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 2110 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 2111 use_scaling = 1; 2112 } 2113 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 2114 } 2115 2116 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 2117 { 2118 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 2119 vcpu->arch.virtual_tsc_mult, 2120 vcpu->arch.virtual_tsc_shift); 2121 tsc += vcpu->arch.this_tsc_write; 2122 return tsc; 2123 } 2124 2125 static inline int gtod_is_based_on_tsc(int mode) 2126 { 2127 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; 2128 } 2129 2130 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 2131 { 2132 #ifdef CONFIG_X86_64 2133 bool vcpus_matched; 2134 struct kvm_arch *ka = &vcpu->kvm->arch; 2135 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2136 2137 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2138 atomic_read(&vcpu->kvm->online_vcpus)); 2139 2140 /* 2141 * Once the masterclock is enabled, always perform request in 2142 * order to update it. 2143 * 2144 * In order to enable masterclock, the host clocksource must be TSC 2145 * and the vcpus need to have matched TSCs. When that happens, 2146 * perform request to enable masterclock. 2147 */ 2148 if (ka->use_master_clock || 2149 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 2150 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2151 2152 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 2153 atomic_read(&vcpu->kvm->online_vcpus), 2154 ka->use_master_clock, gtod->clock.vclock_mode); 2155 #endif 2156 } 2157 2158 /* 2159 * Multiply tsc by a fixed point number represented by ratio. 2160 * 2161 * The most significant 64-N bits (mult) of ratio represent the 2162 * integral part of the fixed point number; the remaining N bits 2163 * (frac) represent the fractional part, ie. ratio represents a fixed 2164 * point number (mult + frac * 2^(-N)). 2165 * 2166 * N equals to kvm_tsc_scaling_ratio_frac_bits. 2167 */ 2168 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 2169 { 2170 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 2171 } 2172 2173 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 2174 { 2175 u64 _tsc = tsc; 2176 u64 ratio = vcpu->arch.tsc_scaling_ratio; 2177 2178 if (ratio != kvm_default_tsc_scaling_ratio) 2179 _tsc = __scale_tsc(ratio, tsc); 2180 2181 return _tsc; 2182 } 2183 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 2184 2185 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 2186 { 2187 u64 tsc; 2188 2189 tsc = kvm_scale_tsc(vcpu, rdtsc()); 2190 2191 return target_tsc - tsc; 2192 } 2193 2194 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 2195 { 2196 return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc); 2197 } 2198 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 2199 2200 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 2201 { 2202 vcpu->arch.l1_tsc_offset = offset; 2203 vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset); 2204 } 2205 2206 static inline bool kvm_check_tsc_unstable(void) 2207 { 2208 #ifdef CONFIG_X86_64 2209 /* 2210 * TSC is marked unstable when we're running on Hyper-V, 2211 * 'TSC page' clocksource is good. 2212 */ 2213 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) 2214 return false; 2215 #endif 2216 return check_tsc_unstable(); 2217 } 2218 2219 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) 2220 { 2221 struct kvm *kvm = vcpu->kvm; 2222 u64 offset, ns, elapsed; 2223 unsigned long flags; 2224 bool matched; 2225 bool already_matched; 2226 bool synchronizing = false; 2227 2228 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 2229 offset = kvm_compute_tsc_offset(vcpu, data); 2230 ns = get_kvmclock_base_ns(); 2231 elapsed = ns - kvm->arch.last_tsc_nsec; 2232 2233 if (vcpu->arch.virtual_tsc_khz) { 2234 if (data == 0) { 2235 /* 2236 * detection of vcpu initialization -- need to sync 2237 * with other vCPUs. This particularly helps to keep 2238 * kvm_clock stable after CPU hotplug 2239 */ 2240 synchronizing = true; 2241 } else { 2242 u64 tsc_exp = kvm->arch.last_tsc_write + 2243 nsec_to_cycles(vcpu, elapsed); 2244 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 2245 /* 2246 * Special case: TSC write with a small delta (1 second) 2247 * of virtual cycle time against real time is 2248 * interpreted as an attempt to synchronize the CPU. 2249 */ 2250 synchronizing = data < tsc_exp + tsc_hz && 2251 data + tsc_hz > tsc_exp; 2252 } 2253 } 2254 2255 /* 2256 * For a reliable TSC, we can match TSC offsets, and for an unstable 2257 * TSC, we add elapsed time in this computation. We could let the 2258 * compensation code attempt to catch up if we fall behind, but 2259 * it's better to try to match offsets from the beginning. 2260 */ 2261 if (synchronizing && 2262 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 2263 if (!kvm_check_tsc_unstable()) { 2264 offset = kvm->arch.cur_tsc_offset; 2265 } else { 2266 u64 delta = nsec_to_cycles(vcpu, elapsed); 2267 data += delta; 2268 offset = kvm_compute_tsc_offset(vcpu, data); 2269 } 2270 matched = true; 2271 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 2272 } else { 2273 /* 2274 * We split periods of matched TSC writes into generations. 2275 * For each generation, we track the original measured 2276 * nanosecond time, offset, and write, so if TSCs are in 2277 * sync, we can match exact offset, and if not, we can match 2278 * exact software computation in compute_guest_tsc() 2279 * 2280 * These values are tracked in kvm->arch.cur_xxx variables. 2281 */ 2282 kvm->arch.cur_tsc_generation++; 2283 kvm->arch.cur_tsc_nsec = ns; 2284 kvm->arch.cur_tsc_write = data; 2285 kvm->arch.cur_tsc_offset = offset; 2286 matched = false; 2287 } 2288 2289 /* 2290 * We also track th most recent recorded KHZ, write and time to 2291 * allow the matching interval to be extended at each write. 2292 */ 2293 kvm->arch.last_tsc_nsec = ns; 2294 kvm->arch.last_tsc_write = data; 2295 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 2296 2297 vcpu->arch.last_guest_tsc = data; 2298 2299 /* Keep track of which generation this VCPU has synchronized to */ 2300 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 2301 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 2302 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 2303 2304 kvm_vcpu_write_tsc_offset(vcpu, offset); 2305 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 2306 2307 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 2308 if (!matched) { 2309 kvm->arch.nr_vcpus_matched_tsc = 0; 2310 } else if (!already_matched) { 2311 kvm->arch.nr_vcpus_matched_tsc++; 2312 } 2313 2314 kvm_track_tsc_matching(vcpu); 2315 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 2316 } 2317 2318 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 2319 s64 adjustment) 2320 { 2321 u64 tsc_offset = vcpu->arch.l1_tsc_offset; 2322 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 2323 } 2324 2325 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 2326 { 2327 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 2328 WARN_ON(adjustment < 0); 2329 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 2330 adjust_tsc_offset_guest(vcpu, adjustment); 2331 } 2332 2333 #ifdef CONFIG_X86_64 2334 2335 static u64 read_tsc(void) 2336 { 2337 u64 ret = (u64)rdtsc_ordered(); 2338 u64 last = pvclock_gtod_data.clock.cycle_last; 2339 2340 if (likely(ret >= last)) 2341 return ret; 2342 2343 /* 2344 * GCC likes to generate cmov here, but this branch is extremely 2345 * predictable (it's just a function of time and the likely is 2346 * very likely) and there's a data dependence, so force GCC 2347 * to generate a branch instead. I don't barrier() because 2348 * we don't actually need a barrier, and if this function 2349 * ever gets inlined it will generate worse code. 2350 */ 2351 asm volatile (""); 2352 return last; 2353 } 2354 2355 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, 2356 int *mode) 2357 { 2358 long v; 2359 u64 tsc_pg_val; 2360 2361 switch (clock->vclock_mode) { 2362 case VDSO_CLOCKMODE_HVCLOCK: 2363 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 2364 tsc_timestamp); 2365 if (tsc_pg_val != U64_MAX) { 2366 /* TSC page valid */ 2367 *mode = VDSO_CLOCKMODE_HVCLOCK; 2368 v = (tsc_pg_val - clock->cycle_last) & 2369 clock->mask; 2370 } else { 2371 /* TSC page invalid */ 2372 *mode = VDSO_CLOCKMODE_NONE; 2373 } 2374 break; 2375 case VDSO_CLOCKMODE_TSC: 2376 *mode = VDSO_CLOCKMODE_TSC; 2377 *tsc_timestamp = read_tsc(); 2378 v = (*tsc_timestamp - clock->cycle_last) & 2379 clock->mask; 2380 break; 2381 default: 2382 *mode = VDSO_CLOCKMODE_NONE; 2383 } 2384 2385 if (*mode == VDSO_CLOCKMODE_NONE) 2386 *tsc_timestamp = v = 0; 2387 2388 return v * clock->mult; 2389 } 2390 2391 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) 2392 { 2393 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2394 unsigned long seq; 2395 int mode; 2396 u64 ns; 2397 2398 do { 2399 seq = read_seqcount_begin(>od->seq); 2400 ns = gtod->raw_clock.base_cycles; 2401 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); 2402 ns >>= gtod->raw_clock.shift; 2403 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); 2404 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2405 *t = ns; 2406 2407 return mode; 2408 } 2409 2410 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 2411 { 2412 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2413 unsigned long seq; 2414 int mode; 2415 u64 ns; 2416 2417 do { 2418 seq = read_seqcount_begin(>od->seq); 2419 ts->tv_sec = gtod->wall_time_sec; 2420 ns = gtod->clock.base_cycles; 2421 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2422 ns >>= gtod->clock.shift; 2423 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2424 2425 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 2426 ts->tv_nsec = ns; 2427 2428 return mode; 2429 } 2430 2431 /* returns true if host is using TSC based clocksource */ 2432 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2433 { 2434 /* checked again under seqlock below */ 2435 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2436 return false; 2437 2438 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, 2439 tsc_timestamp)); 2440 } 2441 2442 /* returns true if host is using TSC based clocksource */ 2443 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 2444 u64 *tsc_timestamp) 2445 { 2446 /* checked again under seqlock below */ 2447 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2448 return false; 2449 2450 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 2451 } 2452 #endif 2453 2454 /* 2455 * 2456 * Assuming a stable TSC across physical CPUS, and a stable TSC 2457 * across virtual CPUs, the following condition is possible. 2458 * Each numbered line represents an event visible to both 2459 * CPUs at the next numbered event. 2460 * 2461 * "timespecX" represents host monotonic time. "tscX" represents 2462 * RDTSC value. 2463 * 2464 * VCPU0 on CPU0 | VCPU1 on CPU1 2465 * 2466 * 1. read timespec0,tsc0 2467 * 2. | timespec1 = timespec0 + N 2468 * | tsc1 = tsc0 + M 2469 * 3. transition to guest | transition to guest 2470 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 2471 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 2472 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 2473 * 2474 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 2475 * 2476 * - ret0 < ret1 2477 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 2478 * ... 2479 * - 0 < N - M => M < N 2480 * 2481 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 2482 * always the case (the difference between two distinct xtime instances 2483 * might be smaller then the difference between corresponding TSC reads, 2484 * when updating guest vcpus pvclock areas). 2485 * 2486 * To avoid that problem, do not allow visibility of distinct 2487 * system_timestamp/tsc_timestamp values simultaneously: use a master 2488 * copy of host monotonic time values. Update that master copy 2489 * in lockstep. 2490 * 2491 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2492 * 2493 */ 2494 2495 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2496 { 2497 #ifdef CONFIG_X86_64 2498 struct kvm_arch *ka = &kvm->arch; 2499 int vclock_mode; 2500 bool host_tsc_clocksource, vcpus_matched; 2501 2502 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2503 atomic_read(&kvm->online_vcpus)); 2504 2505 /* 2506 * If the host uses TSC clock, then passthrough TSC as stable 2507 * to the guest. 2508 */ 2509 host_tsc_clocksource = kvm_get_time_and_clockread( 2510 &ka->master_kernel_ns, 2511 &ka->master_cycle_now); 2512 2513 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2514 && !ka->backwards_tsc_observed 2515 && !ka->boot_vcpu_runs_old_kvmclock; 2516 2517 if (ka->use_master_clock) 2518 atomic_set(&kvm_guest_has_master_clock, 1); 2519 2520 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2521 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2522 vcpus_matched); 2523 #endif 2524 } 2525 2526 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2527 { 2528 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2529 } 2530 2531 static void kvm_gen_update_masterclock(struct kvm *kvm) 2532 { 2533 #ifdef CONFIG_X86_64 2534 int i; 2535 struct kvm_vcpu *vcpu; 2536 struct kvm_arch *ka = &kvm->arch; 2537 2538 spin_lock(&ka->pvclock_gtod_sync_lock); 2539 kvm_make_mclock_inprogress_request(kvm); 2540 /* no guest entries from this point */ 2541 pvclock_update_vm_gtod_copy(kvm); 2542 2543 kvm_for_each_vcpu(i, vcpu, kvm) 2544 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2545 2546 /* guest entries allowed */ 2547 kvm_for_each_vcpu(i, vcpu, kvm) 2548 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2549 2550 spin_unlock(&ka->pvclock_gtod_sync_lock); 2551 #endif 2552 } 2553 2554 u64 get_kvmclock_ns(struct kvm *kvm) 2555 { 2556 struct kvm_arch *ka = &kvm->arch; 2557 struct pvclock_vcpu_time_info hv_clock; 2558 u64 ret; 2559 2560 spin_lock(&ka->pvclock_gtod_sync_lock); 2561 if (!ka->use_master_clock) { 2562 spin_unlock(&ka->pvclock_gtod_sync_lock); 2563 return get_kvmclock_base_ns() + ka->kvmclock_offset; 2564 } 2565 2566 hv_clock.tsc_timestamp = ka->master_cycle_now; 2567 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2568 spin_unlock(&ka->pvclock_gtod_sync_lock); 2569 2570 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2571 get_cpu(); 2572 2573 if (__this_cpu_read(cpu_tsc_khz)) { 2574 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2575 &hv_clock.tsc_shift, 2576 &hv_clock.tsc_to_system_mul); 2577 ret = __pvclock_read_cycles(&hv_clock, rdtsc()); 2578 } else 2579 ret = get_kvmclock_base_ns() + ka->kvmclock_offset; 2580 2581 put_cpu(); 2582 2583 return ret; 2584 } 2585 2586 static void kvm_setup_pvclock_page(struct kvm_vcpu *v) 2587 { 2588 struct kvm_vcpu_arch *vcpu = &v->arch; 2589 struct pvclock_vcpu_time_info guest_hv_clock; 2590 2591 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 2592 &guest_hv_clock, sizeof(guest_hv_clock)))) 2593 return; 2594 2595 /* This VCPU is paused, but it's legal for a guest to read another 2596 * VCPU's kvmclock, so we really have to follow the specification where 2597 * it says that version is odd if data is being modified, and even after 2598 * it is consistent. 2599 * 2600 * Version field updates must be kept separate. This is because 2601 * kvm_write_guest_cached might use a "rep movs" instruction, and 2602 * writes within a string instruction are weakly ordered. So there 2603 * are three writes overall. 2604 * 2605 * As a small optimization, only write the version field in the first 2606 * and third write. The vcpu->pv_time cache is still valid, because the 2607 * version field is the first in the struct. 2608 */ 2609 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 2610 2611 if (guest_hv_clock.version & 1) 2612 ++guest_hv_clock.version; /* first time write, random junk */ 2613 2614 vcpu->hv_clock.version = guest_hv_clock.version + 1; 2615 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2616 &vcpu->hv_clock, 2617 sizeof(vcpu->hv_clock.version)); 2618 2619 smp_wmb(); 2620 2621 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 2622 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 2623 2624 if (vcpu->pvclock_set_guest_stopped_request) { 2625 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 2626 vcpu->pvclock_set_guest_stopped_request = false; 2627 } 2628 2629 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 2630 2631 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2632 &vcpu->hv_clock, 2633 sizeof(vcpu->hv_clock)); 2634 2635 smp_wmb(); 2636 2637 vcpu->hv_clock.version++; 2638 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2639 &vcpu->hv_clock, 2640 sizeof(vcpu->hv_clock.version)); 2641 } 2642 2643 static int kvm_guest_time_update(struct kvm_vcpu *v) 2644 { 2645 unsigned long flags, tgt_tsc_khz; 2646 struct kvm_vcpu_arch *vcpu = &v->arch; 2647 struct kvm_arch *ka = &v->kvm->arch; 2648 s64 kernel_ns; 2649 u64 tsc_timestamp, host_tsc; 2650 u8 pvclock_flags; 2651 bool use_master_clock; 2652 2653 kernel_ns = 0; 2654 host_tsc = 0; 2655 2656 /* 2657 * If the host uses TSC clock, then passthrough TSC as stable 2658 * to the guest. 2659 */ 2660 spin_lock(&ka->pvclock_gtod_sync_lock); 2661 use_master_clock = ka->use_master_clock; 2662 if (use_master_clock) { 2663 host_tsc = ka->master_cycle_now; 2664 kernel_ns = ka->master_kernel_ns; 2665 } 2666 spin_unlock(&ka->pvclock_gtod_sync_lock); 2667 2668 /* Keep irq disabled to prevent changes to the clock */ 2669 local_irq_save(flags); 2670 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 2671 if (unlikely(tgt_tsc_khz == 0)) { 2672 local_irq_restore(flags); 2673 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2674 return 1; 2675 } 2676 if (!use_master_clock) { 2677 host_tsc = rdtsc(); 2678 kernel_ns = get_kvmclock_base_ns(); 2679 } 2680 2681 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 2682 2683 /* 2684 * We may have to catch up the TSC to match elapsed wall clock 2685 * time for two reasons, even if kvmclock is used. 2686 * 1) CPU could have been running below the maximum TSC rate 2687 * 2) Broken TSC compensation resets the base at each VCPU 2688 * entry to avoid unknown leaps of TSC even when running 2689 * again on the same CPU. This may cause apparent elapsed 2690 * time to disappear, and the guest to stand still or run 2691 * very slowly. 2692 */ 2693 if (vcpu->tsc_catchup) { 2694 u64 tsc = compute_guest_tsc(v, kernel_ns); 2695 if (tsc > tsc_timestamp) { 2696 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 2697 tsc_timestamp = tsc; 2698 } 2699 } 2700 2701 local_irq_restore(flags); 2702 2703 /* With all the info we got, fill in the values */ 2704 2705 if (kvm_has_tsc_control) 2706 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 2707 2708 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 2709 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 2710 &vcpu->hv_clock.tsc_shift, 2711 &vcpu->hv_clock.tsc_to_system_mul); 2712 vcpu->hw_tsc_khz = tgt_tsc_khz; 2713 } 2714 2715 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 2716 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 2717 vcpu->last_guest_tsc = tsc_timestamp; 2718 2719 /* If the host uses TSC clocksource, then it is stable */ 2720 pvclock_flags = 0; 2721 if (use_master_clock) 2722 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 2723 2724 vcpu->hv_clock.flags = pvclock_flags; 2725 2726 if (vcpu->pv_time_enabled) 2727 kvm_setup_pvclock_page(v); 2728 if (v == kvm_get_vcpu(v->kvm, 0)) 2729 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 2730 return 0; 2731 } 2732 2733 /* 2734 * kvmclock updates which are isolated to a given vcpu, such as 2735 * vcpu->cpu migration, should not allow system_timestamp from 2736 * the rest of the vcpus to remain static. Otherwise ntp frequency 2737 * correction applies to one vcpu's system_timestamp but not 2738 * the others. 2739 * 2740 * So in those cases, request a kvmclock update for all vcpus. 2741 * We need to rate-limit these requests though, as they can 2742 * considerably slow guests that have a large number of vcpus. 2743 * The time for a remote vcpu to update its kvmclock is bound 2744 * by the delay we use to rate-limit the updates. 2745 */ 2746 2747 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 2748 2749 static void kvmclock_update_fn(struct work_struct *work) 2750 { 2751 int i; 2752 struct delayed_work *dwork = to_delayed_work(work); 2753 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2754 kvmclock_update_work); 2755 struct kvm *kvm = container_of(ka, struct kvm, arch); 2756 struct kvm_vcpu *vcpu; 2757 2758 kvm_for_each_vcpu(i, vcpu, kvm) { 2759 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2760 kvm_vcpu_kick(vcpu); 2761 } 2762 } 2763 2764 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 2765 { 2766 struct kvm *kvm = v->kvm; 2767 2768 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2769 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 2770 KVMCLOCK_UPDATE_DELAY); 2771 } 2772 2773 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 2774 2775 static void kvmclock_sync_fn(struct work_struct *work) 2776 { 2777 struct delayed_work *dwork = to_delayed_work(work); 2778 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2779 kvmclock_sync_work); 2780 struct kvm *kvm = container_of(ka, struct kvm, arch); 2781 2782 if (!kvmclock_periodic_sync) 2783 return; 2784 2785 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 2786 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 2787 KVMCLOCK_SYNC_PERIOD); 2788 } 2789 2790 /* 2791 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 2792 */ 2793 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 2794 { 2795 /* McStatusWrEn enabled? */ 2796 if (guest_cpuid_is_amd_or_hygon(vcpu)) 2797 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 2798 2799 return false; 2800 } 2801 2802 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2803 { 2804 u64 mcg_cap = vcpu->arch.mcg_cap; 2805 unsigned bank_num = mcg_cap & 0xff; 2806 u32 msr = msr_info->index; 2807 u64 data = msr_info->data; 2808 2809 switch (msr) { 2810 case MSR_IA32_MCG_STATUS: 2811 vcpu->arch.mcg_status = data; 2812 break; 2813 case MSR_IA32_MCG_CTL: 2814 if (!(mcg_cap & MCG_CTL_P) && 2815 (data || !msr_info->host_initiated)) 2816 return 1; 2817 if (data != 0 && data != ~(u64)0) 2818 return 1; 2819 vcpu->arch.mcg_ctl = data; 2820 break; 2821 default: 2822 if (msr >= MSR_IA32_MC0_CTL && 2823 msr < MSR_IA32_MCx_CTL(bank_num)) { 2824 u32 offset = array_index_nospec( 2825 msr - MSR_IA32_MC0_CTL, 2826 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 2827 2828 /* only 0 or all 1s can be written to IA32_MCi_CTL 2829 * some Linux kernels though clear bit 10 in bank 4 to 2830 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 2831 * this to avoid an uncatched #GP in the guest 2832 */ 2833 if ((offset & 0x3) == 0 && 2834 data != 0 && (data | (1 << 10)) != ~(u64)0) 2835 return -1; 2836 2837 /* MCi_STATUS */ 2838 if (!msr_info->host_initiated && 2839 (offset & 0x3) == 1 && data != 0) { 2840 if (!can_set_mci_status(vcpu)) 2841 return -1; 2842 } 2843 2844 vcpu->arch.mce_banks[offset] = data; 2845 break; 2846 } 2847 return 1; 2848 } 2849 return 0; 2850 } 2851 2852 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 2853 { 2854 struct kvm *kvm = vcpu->kvm; 2855 int lm = is_long_mode(vcpu); 2856 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 2857 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 2858 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 2859 : kvm->arch.xen_hvm_config.blob_size_32; 2860 u32 page_num = data & ~PAGE_MASK; 2861 u64 page_addr = data & PAGE_MASK; 2862 u8 *page; 2863 2864 if (page_num >= blob_size) 2865 return 1; 2866 2867 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 2868 if (IS_ERR(page)) 2869 return PTR_ERR(page); 2870 2871 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) { 2872 kfree(page); 2873 return 1; 2874 } 2875 return 0; 2876 } 2877 2878 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) 2879 { 2880 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; 2881 2882 return (vcpu->arch.apf.msr_en_val & mask) == mask; 2883 } 2884 2885 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2886 { 2887 gpa_t gpa = data & ~0x3f; 2888 2889 /* Bits 4:5 are reserved, Should be zero */ 2890 if (data & 0x30) 2891 return 1; 2892 2893 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && 2894 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) 2895 return 1; 2896 2897 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && 2898 (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) 2899 return 1; 2900 2901 if (!lapic_in_kernel(vcpu)) 2902 return data ? 1 : 0; 2903 2904 vcpu->arch.apf.msr_en_val = data; 2905 2906 if (!kvm_pv_async_pf_enabled(vcpu)) { 2907 kvm_clear_async_pf_completion_queue(vcpu); 2908 kvm_async_pf_hash_reset(vcpu); 2909 return 0; 2910 } 2911 2912 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2913 sizeof(u64))) 2914 return 1; 2915 2916 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2917 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 2918 2919 kvm_async_pf_wakeup_all(vcpu); 2920 2921 return 0; 2922 } 2923 2924 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) 2925 { 2926 /* Bits 8-63 are reserved */ 2927 if (data >> 8) 2928 return 1; 2929 2930 if (!lapic_in_kernel(vcpu)) 2931 return 1; 2932 2933 vcpu->arch.apf.msr_int_val = data; 2934 2935 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; 2936 2937 return 0; 2938 } 2939 2940 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2941 { 2942 vcpu->arch.pv_time_enabled = false; 2943 vcpu->arch.time = 0; 2944 } 2945 2946 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) 2947 { 2948 ++vcpu->stat.tlb_flush; 2949 kvm_x86_ops.tlb_flush_all(vcpu); 2950 } 2951 2952 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) 2953 { 2954 ++vcpu->stat.tlb_flush; 2955 kvm_x86_ops.tlb_flush_guest(vcpu); 2956 } 2957 2958 static void record_steal_time(struct kvm_vcpu *vcpu) 2959 { 2960 struct kvm_host_map map; 2961 struct kvm_steal_time *st; 2962 2963 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2964 return; 2965 2966 /* -EAGAIN is returned in atomic context so we can just return. */ 2967 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, 2968 &map, &vcpu->arch.st.cache, false)) 2969 return; 2970 2971 st = map.hva + 2972 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 2973 2974 /* 2975 * Doing a TLB flush here, on the guest's behalf, can avoid 2976 * expensive IPIs. 2977 */ 2978 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { 2979 trace_kvm_pv_tlb_flush(vcpu->vcpu_id, 2980 st->preempted & KVM_VCPU_FLUSH_TLB); 2981 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB) 2982 kvm_vcpu_flush_tlb_guest(vcpu); 2983 } 2984 2985 vcpu->arch.st.preempted = 0; 2986 2987 if (st->version & 1) 2988 st->version += 1; /* first time write, random junk */ 2989 2990 st->version += 1; 2991 2992 smp_wmb(); 2993 2994 st->steal += current->sched_info.run_delay - 2995 vcpu->arch.st.last_steal; 2996 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2997 2998 smp_wmb(); 2999 3000 st->version += 1; 3001 3002 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); 3003 } 3004 3005 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3006 { 3007 bool pr = false; 3008 u32 msr = msr_info->index; 3009 u64 data = msr_info->data; 3010 3011 switch (msr) { 3012 case MSR_AMD64_NB_CFG: 3013 case MSR_IA32_UCODE_WRITE: 3014 case MSR_VM_HSAVE_PA: 3015 case MSR_AMD64_PATCH_LOADER: 3016 case MSR_AMD64_BU_CFG2: 3017 case MSR_AMD64_DC_CFG: 3018 case MSR_F15H_EX_CFG: 3019 break; 3020 3021 case MSR_IA32_UCODE_REV: 3022 if (msr_info->host_initiated) 3023 vcpu->arch.microcode_version = data; 3024 break; 3025 case MSR_IA32_ARCH_CAPABILITIES: 3026 if (!msr_info->host_initiated) 3027 return 1; 3028 vcpu->arch.arch_capabilities = data; 3029 break; 3030 case MSR_IA32_PERF_CAPABILITIES: { 3031 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; 3032 3033 if (!msr_info->host_initiated) 3034 return 1; 3035 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent)) 3036 return 1; 3037 if (data & ~msr_ent.data) 3038 return 1; 3039 3040 vcpu->arch.perf_capabilities = data; 3041 3042 return 0; 3043 } 3044 case MSR_EFER: 3045 return set_efer(vcpu, msr_info); 3046 case MSR_K7_HWCR: 3047 data &= ~(u64)0x40; /* ignore flush filter disable */ 3048 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 3049 data &= ~(u64)0x8; /* ignore TLB cache disable */ 3050 3051 /* Handle McStatusWrEn */ 3052 if (data == BIT_ULL(18)) { 3053 vcpu->arch.msr_hwcr = data; 3054 } else if (data != 0) { 3055 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 3056 data); 3057 return 1; 3058 } 3059 break; 3060 case MSR_FAM10H_MMIO_CONF_BASE: 3061 if (data != 0) { 3062 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 3063 "0x%llx\n", data); 3064 return 1; 3065 } 3066 break; 3067 case MSR_IA32_DEBUGCTLMSR: 3068 if (!data) { 3069 /* We support the non-activated case already */ 3070 break; 3071 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 3072 /* Values other than LBR and BTF are vendor-specific, 3073 thus reserved and should throw a #GP */ 3074 return 1; 3075 } else if (report_ignored_msrs) 3076 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 3077 __func__, data); 3078 break; 3079 case 0x200 ... 0x2ff: 3080 return kvm_mtrr_set_msr(vcpu, msr, data); 3081 case MSR_IA32_APICBASE: 3082 return kvm_set_apic_base(vcpu, msr_info); 3083 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3084 return kvm_x2apic_msr_write(vcpu, msr, data); 3085 case MSR_IA32_TSCDEADLINE: 3086 kvm_set_lapic_tscdeadline_msr(vcpu, data); 3087 break; 3088 case MSR_IA32_TSC_ADJUST: 3089 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 3090 if (!msr_info->host_initiated) { 3091 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 3092 adjust_tsc_offset_guest(vcpu, adj); 3093 } 3094 vcpu->arch.ia32_tsc_adjust_msr = data; 3095 } 3096 break; 3097 case MSR_IA32_MISC_ENABLE: 3098 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && 3099 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { 3100 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) 3101 return 1; 3102 vcpu->arch.ia32_misc_enable_msr = data; 3103 kvm_update_cpuid_runtime(vcpu); 3104 } else { 3105 vcpu->arch.ia32_misc_enable_msr = data; 3106 } 3107 break; 3108 case MSR_IA32_SMBASE: 3109 if (!msr_info->host_initiated) 3110 return 1; 3111 vcpu->arch.smbase = data; 3112 break; 3113 case MSR_IA32_POWER_CTL: 3114 vcpu->arch.msr_ia32_power_ctl = data; 3115 break; 3116 case MSR_IA32_TSC: 3117 if (msr_info->host_initiated) { 3118 kvm_synchronize_tsc(vcpu, data); 3119 } else { 3120 u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; 3121 adjust_tsc_offset_guest(vcpu, adj); 3122 vcpu->arch.ia32_tsc_adjust_msr += adj; 3123 } 3124 break; 3125 case MSR_IA32_XSS: 3126 if (!msr_info->host_initiated && 3127 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3128 return 1; 3129 /* 3130 * KVM supports exposing PT to the guest, but does not support 3131 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than 3132 * XSAVES/XRSTORS to save/restore PT MSRs. 3133 */ 3134 if (data & ~supported_xss) 3135 return 1; 3136 vcpu->arch.ia32_xss = data; 3137 break; 3138 case MSR_SMI_COUNT: 3139 if (!msr_info->host_initiated) 3140 return 1; 3141 vcpu->arch.smi_count = data; 3142 break; 3143 case MSR_KVM_WALL_CLOCK_NEW: 3144 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3145 return 1; 3146 3147 kvm_write_wall_clock(vcpu->kvm, data); 3148 break; 3149 case MSR_KVM_WALL_CLOCK: 3150 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3151 return 1; 3152 3153 kvm_write_wall_clock(vcpu->kvm, data); 3154 break; 3155 case MSR_KVM_SYSTEM_TIME_NEW: 3156 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3157 return 1; 3158 3159 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); 3160 break; 3161 case MSR_KVM_SYSTEM_TIME: 3162 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3163 return 1; 3164 3165 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); 3166 break; 3167 case MSR_KVM_ASYNC_PF_EN: 3168 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3169 return 1; 3170 3171 if (kvm_pv_enable_async_pf(vcpu, data)) 3172 return 1; 3173 break; 3174 case MSR_KVM_ASYNC_PF_INT: 3175 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3176 return 1; 3177 3178 if (kvm_pv_enable_async_pf_int(vcpu, data)) 3179 return 1; 3180 break; 3181 case MSR_KVM_ASYNC_PF_ACK: 3182 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3183 return 1; 3184 if (data & 0x1) { 3185 vcpu->arch.apf.pageready_pending = false; 3186 kvm_check_async_pf_completion(vcpu); 3187 } 3188 break; 3189 case MSR_KVM_STEAL_TIME: 3190 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3191 return 1; 3192 3193 if (unlikely(!sched_info_on())) 3194 return 1; 3195 3196 if (data & KVM_STEAL_RESERVED_MASK) 3197 return 1; 3198 3199 vcpu->arch.st.msr_val = data; 3200 3201 if (!(data & KVM_MSR_ENABLED)) 3202 break; 3203 3204 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3205 3206 break; 3207 case MSR_KVM_PV_EOI_EN: 3208 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3209 return 1; 3210 3211 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) 3212 return 1; 3213 break; 3214 3215 case MSR_KVM_POLL_CONTROL: 3216 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3217 return 1; 3218 3219 /* only enable bit supported */ 3220 if (data & (-1ULL << 1)) 3221 return 1; 3222 3223 vcpu->arch.msr_kvm_poll_control = data; 3224 break; 3225 3226 case MSR_IA32_MCG_CTL: 3227 case MSR_IA32_MCG_STATUS: 3228 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3229 return set_msr_mce(vcpu, msr_info); 3230 3231 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3232 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3233 pr = true; 3234 fallthrough; 3235 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3236 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3237 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3238 return kvm_pmu_set_msr(vcpu, msr_info); 3239 3240 if (pr || data != 0) 3241 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 3242 "0x%x data 0x%llx\n", msr, data); 3243 break; 3244 case MSR_K7_CLK_CTL: 3245 /* 3246 * Ignore all writes to this no longer documented MSR. 3247 * Writes are only relevant for old K7 processors, 3248 * all pre-dating SVM, but a recommended workaround from 3249 * AMD for these chips. It is possible to specify the 3250 * affected processor models on the command line, hence 3251 * the need to ignore the workaround. 3252 */ 3253 break; 3254 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3255 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3256 case HV_X64_MSR_SYNDBG_OPTIONS: 3257 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3258 case HV_X64_MSR_CRASH_CTL: 3259 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3260 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3261 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3262 case HV_X64_MSR_TSC_EMULATION_STATUS: 3263 return kvm_hv_set_msr_common(vcpu, msr, data, 3264 msr_info->host_initiated); 3265 case MSR_IA32_BBL_CR_CTL3: 3266 /* Drop writes to this legacy MSR -- see rdmsr 3267 * counterpart for further detail. 3268 */ 3269 if (report_ignored_msrs) 3270 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 3271 msr, data); 3272 break; 3273 case MSR_AMD64_OSVW_ID_LENGTH: 3274 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3275 return 1; 3276 vcpu->arch.osvw.length = data; 3277 break; 3278 case MSR_AMD64_OSVW_STATUS: 3279 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3280 return 1; 3281 vcpu->arch.osvw.status = data; 3282 break; 3283 case MSR_PLATFORM_INFO: 3284 if (!msr_info->host_initiated || 3285 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 3286 cpuid_fault_enabled(vcpu))) 3287 return 1; 3288 vcpu->arch.msr_platform_info = data; 3289 break; 3290 case MSR_MISC_FEATURES_ENABLES: 3291 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 3292 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3293 !supports_cpuid_fault(vcpu))) 3294 return 1; 3295 vcpu->arch.msr_misc_features_enables = data; 3296 break; 3297 default: 3298 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 3299 return xen_hvm_config(vcpu, data); 3300 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3301 return kvm_pmu_set_msr(vcpu, msr_info); 3302 return KVM_MSR_RET_INVALID; 3303 } 3304 return 0; 3305 } 3306 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 3307 3308 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 3309 { 3310 u64 data; 3311 u64 mcg_cap = vcpu->arch.mcg_cap; 3312 unsigned bank_num = mcg_cap & 0xff; 3313 3314 switch (msr) { 3315 case MSR_IA32_P5_MC_ADDR: 3316 case MSR_IA32_P5_MC_TYPE: 3317 data = 0; 3318 break; 3319 case MSR_IA32_MCG_CAP: 3320 data = vcpu->arch.mcg_cap; 3321 break; 3322 case MSR_IA32_MCG_CTL: 3323 if (!(mcg_cap & MCG_CTL_P) && !host) 3324 return 1; 3325 data = vcpu->arch.mcg_ctl; 3326 break; 3327 case MSR_IA32_MCG_STATUS: 3328 data = vcpu->arch.mcg_status; 3329 break; 3330 default: 3331 if (msr >= MSR_IA32_MC0_CTL && 3332 msr < MSR_IA32_MCx_CTL(bank_num)) { 3333 u32 offset = array_index_nospec( 3334 msr - MSR_IA32_MC0_CTL, 3335 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3336 3337 data = vcpu->arch.mce_banks[offset]; 3338 break; 3339 } 3340 return 1; 3341 } 3342 *pdata = data; 3343 return 0; 3344 } 3345 3346 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3347 { 3348 switch (msr_info->index) { 3349 case MSR_IA32_PLATFORM_ID: 3350 case MSR_IA32_EBL_CR_POWERON: 3351 case MSR_IA32_DEBUGCTLMSR: 3352 case MSR_IA32_LASTBRANCHFROMIP: 3353 case MSR_IA32_LASTBRANCHTOIP: 3354 case MSR_IA32_LASTINTFROMIP: 3355 case MSR_IA32_LASTINTTOIP: 3356 case MSR_K8_SYSCFG: 3357 case MSR_K8_TSEG_ADDR: 3358 case MSR_K8_TSEG_MASK: 3359 case MSR_VM_HSAVE_PA: 3360 case MSR_K8_INT_PENDING_MSG: 3361 case MSR_AMD64_NB_CFG: 3362 case MSR_FAM10H_MMIO_CONF_BASE: 3363 case MSR_AMD64_BU_CFG2: 3364 case MSR_IA32_PERF_CTL: 3365 case MSR_AMD64_DC_CFG: 3366 case MSR_F15H_EX_CFG: 3367 /* 3368 * Intel Sandy Bridge CPUs must support the RAPL (running average power 3369 * limit) MSRs. Just return 0, as we do not want to expose the host 3370 * data here. Do not conditionalize this on CPUID, as KVM does not do 3371 * so for existing CPU-specific MSRs. 3372 */ 3373 case MSR_RAPL_POWER_UNIT: 3374 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ 3375 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ 3376 case MSR_PKG_ENERGY_STATUS: /* Total package */ 3377 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ 3378 msr_info->data = 0; 3379 break; 3380 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3381 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3382 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3383 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3384 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3385 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3386 return kvm_pmu_get_msr(vcpu, msr_info); 3387 msr_info->data = 0; 3388 break; 3389 case MSR_IA32_UCODE_REV: 3390 msr_info->data = vcpu->arch.microcode_version; 3391 break; 3392 case MSR_IA32_ARCH_CAPABILITIES: 3393 if (!msr_info->host_initiated && 3394 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 3395 return 1; 3396 msr_info->data = vcpu->arch.arch_capabilities; 3397 break; 3398 case MSR_IA32_PERF_CAPABILITIES: 3399 if (!msr_info->host_initiated && 3400 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) 3401 return 1; 3402 msr_info->data = vcpu->arch.perf_capabilities; 3403 break; 3404 case MSR_IA32_POWER_CTL: 3405 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 3406 break; 3407 case MSR_IA32_TSC: { 3408 /* 3409 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset 3410 * even when not intercepted. AMD manual doesn't explicitly 3411 * state this but appears to behave the same. 3412 * 3413 * On userspace reads and writes, however, we unconditionally 3414 * return L1's TSC value to ensure backwards-compatible 3415 * behavior for migration. 3416 */ 3417 u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset : 3418 vcpu->arch.tsc_offset; 3419 3420 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset; 3421 break; 3422 } 3423 case MSR_MTRRcap: 3424 case 0x200 ... 0x2ff: 3425 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 3426 case 0xcd: /* fsb frequency */ 3427 msr_info->data = 3; 3428 break; 3429 /* 3430 * MSR_EBC_FREQUENCY_ID 3431 * Conservative value valid for even the basic CPU models. 3432 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 3433 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 3434 * and 266MHz for model 3, or 4. Set Core Clock 3435 * Frequency to System Bus Frequency Ratio to 1 (bits 3436 * 31:24) even though these are only valid for CPU 3437 * models > 2, however guests may end up dividing or 3438 * multiplying by zero otherwise. 3439 */ 3440 case MSR_EBC_FREQUENCY_ID: 3441 msr_info->data = 1 << 24; 3442 break; 3443 case MSR_IA32_APICBASE: 3444 msr_info->data = kvm_get_apic_base(vcpu); 3445 break; 3446 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3447 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 3448 case MSR_IA32_TSCDEADLINE: 3449 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 3450 break; 3451 case MSR_IA32_TSC_ADJUST: 3452 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 3453 break; 3454 case MSR_IA32_MISC_ENABLE: 3455 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 3456 break; 3457 case MSR_IA32_SMBASE: 3458 if (!msr_info->host_initiated) 3459 return 1; 3460 msr_info->data = vcpu->arch.smbase; 3461 break; 3462 case MSR_SMI_COUNT: 3463 msr_info->data = vcpu->arch.smi_count; 3464 break; 3465 case MSR_IA32_PERF_STATUS: 3466 /* TSC increment by tick */ 3467 msr_info->data = 1000ULL; 3468 /* CPU multiplier */ 3469 msr_info->data |= (((uint64_t)4ULL) << 40); 3470 break; 3471 case MSR_EFER: 3472 msr_info->data = vcpu->arch.efer; 3473 break; 3474 case MSR_KVM_WALL_CLOCK: 3475 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3476 return 1; 3477 3478 msr_info->data = vcpu->kvm->arch.wall_clock; 3479 break; 3480 case MSR_KVM_WALL_CLOCK_NEW: 3481 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3482 return 1; 3483 3484 msr_info->data = vcpu->kvm->arch.wall_clock; 3485 break; 3486 case MSR_KVM_SYSTEM_TIME: 3487 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3488 return 1; 3489 3490 msr_info->data = vcpu->arch.time; 3491 break; 3492 case MSR_KVM_SYSTEM_TIME_NEW: 3493 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3494 return 1; 3495 3496 msr_info->data = vcpu->arch.time; 3497 break; 3498 case MSR_KVM_ASYNC_PF_EN: 3499 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3500 return 1; 3501 3502 msr_info->data = vcpu->arch.apf.msr_en_val; 3503 break; 3504 case MSR_KVM_ASYNC_PF_INT: 3505 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3506 return 1; 3507 3508 msr_info->data = vcpu->arch.apf.msr_int_val; 3509 break; 3510 case MSR_KVM_ASYNC_PF_ACK: 3511 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3512 return 1; 3513 3514 msr_info->data = 0; 3515 break; 3516 case MSR_KVM_STEAL_TIME: 3517 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3518 return 1; 3519 3520 msr_info->data = vcpu->arch.st.msr_val; 3521 break; 3522 case MSR_KVM_PV_EOI_EN: 3523 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3524 return 1; 3525 3526 msr_info->data = vcpu->arch.pv_eoi.msr_val; 3527 break; 3528 case MSR_KVM_POLL_CONTROL: 3529 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3530 return 1; 3531 3532 msr_info->data = vcpu->arch.msr_kvm_poll_control; 3533 break; 3534 case MSR_IA32_P5_MC_ADDR: 3535 case MSR_IA32_P5_MC_TYPE: 3536 case MSR_IA32_MCG_CAP: 3537 case MSR_IA32_MCG_CTL: 3538 case MSR_IA32_MCG_STATUS: 3539 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3540 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 3541 msr_info->host_initiated); 3542 case MSR_IA32_XSS: 3543 if (!msr_info->host_initiated && 3544 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3545 return 1; 3546 msr_info->data = vcpu->arch.ia32_xss; 3547 break; 3548 case MSR_K7_CLK_CTL: 3549 /* 3550 * Provide expected ramp-up count for K7. All other 3551 * are set to zero, indicating minimum divisors for 3552 * every field. 3553 * 3554 * This prevents guest kernels on AMD host with CPU 3555 * type 6, model 8 and higher from exploding due to 3556 * the rdmsr failing. 3557 */ 3558 msr_info->data = 0x20000000; 3559 break; 3560 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3561 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3562 case HV_X64_MSR_SYNDBG_OPTIONS: 3563 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3564 case HV_X64_MSR_CRASH_CTL: 3565 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3566 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3567 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3568 case HV_X64_MSR_TSC_EMULATION_STATUS: 3569 return kvm_hv_get_msr_common(vcpu, 3570 msr_info->index, &msr_info->data, 3571 msr_info->host_initiated); 3572 case MSR_IA32_BBL_CR_CTL3: 3573 /* This legacy MSR exists but isn't fully documented in current 3574 * silicon. It is however accessed by winxp in very narrow 3575 * scenarios where it sets bit #19, itself documented as 3576 * a "reserved" bit. Best effort attempt to source coherent 3577 * read data here should the balance of the register be 3578 * interpreted by the guest: 3579 * 3580 * L2 cache control register 3: 64GB range, 256KB size, 3581 * enabled, latency 0x1, configured 3582 */ 3583 msr_info->data = 0xbe702111; 3584 break; 3585 case MSR_AMD64_OSVW_ID_LENGTH: 3586 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3587 return 1; 3588 msr_info->data = vcpu->arch.osvw.length; 3589 break; 3590 case MSR_AMD64_OSVW_STATUS: 3591 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3592 return 1; 3593 msr_info->data = vcpu->arch.osvw.status; 3594 break; 3595 case MSR_PLATFORM_INFO: 3596 if (!msr_info->host_initiated && 3597 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 3598 return 1; 3599 msr_info->data = vcpu->arch.msr_platform_info; 3600 break; 3601 case MSR_MISC_FEATURES_ENABLES: 3602 msr_info->data = vcpu->arch.msr_misc_features_enables; 3603 break; 3604 case MSR_K7_HWCR: 3605 msr_info->data = vcpu->arch.msr_hwcr; 3606 break; 3607 default: 3608 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3609 return kvm_pmu_get_msr(vcpu, msr_info); 3610 return KVM_MSR_RET_INVALID; 3611 } 3612 return 0; 3613 } 3614 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 3615 3616 /* 3617 * Read or write a bunch of msrs. All parameters are kernel addresses. 3618 * 3619 * @return number of msrs set successfully. 3620 */ 3621 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 3622 struct kvm_msr_entry *entries, 3623 int (*do_msr)(struct kvm_vcpu *vcpu, 3624 unsigned index, u64 *data)) 3625 { 3626 int i; 3627 3628 for (i = 0; i < msrs->nmsrs; ++i) 3629 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 3630 break; 3631 3632 return i; 3633 } 3634 3635 /* 3636 * Read or write a bunch of msrs. Parameters are user addresses. 3637 * 3638 * @return number of msrs set successfully. 3639 */ 3640 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 3641 int (*do_msr)(struct kvm_vcpu *vcpu, 3642 unsigned index, u64 *data), 3643 int writeback) 3644 { 3645 struct kvm_msrs msrs; 3646 struct kvm_msr_entry *entries; 3647 int r, n; 3648 unsigned size; 3649 3650 r = -EFAULT; 3651 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 3652 goto out; 3653 3654 r = -E2BIG; 3655 if (msrs.nmsrs >= MAX_IO_MSRS) 3656 goto out; 3657 3658 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 3659 entries = memdup_user(user_msrs->entries, size); 3660 if (IS_ERR(entries)) { 3661 r = PTR_ERR(entries); 3662 goto out; 3663 } 3664 3665 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 3666 if (r < 0) 3667 goto out_free; 3668 3669 r = -EFAULT; 3670 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 3671 goto out_free; 3672 3673 r = n; 3674 3675 out_free: 3676 kfree(entries); 3677 out: 3678 return r; 3679 } 3680 3681 static inline bool kvm_can_mwait_in_guest(void) 3682 { 3683 return boot_cpu_has(X86_FEATURE_MWAIT) && 3684 !boot_cpu_has_bug(X86_BUG_MONITOR) && 3685 boot_cpu_has(X86_FEATURE_ARAT); 3686 } 3687 3688 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, 3689 struct kvm_cpuid2 __user *cpuid_arg) 3690 { 3691 struct kvm_cpuid2 cpuid; 3692 int r; 3693 3694 r = -EFAULT; 3695 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3696 return r; 3697 3698 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3699 if (r) 3700 return r; 3701 3702 r = -EFAULT; 3703 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 3704 return r; 3705 3706 return 0; 3707 } 3708 3709 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 3710 { 3711 int r = 0; 3712 3713 switch (ext) { 3714 case KVM_CAP_IRQCHIP: 3715 case KVM_CAP_HLT: 3716 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 3717 case KVM_CAP_SET_TSS_ADDR: 3718 case KVM_CAP_EXT_CPUID: 3719 case KVM_CAP_EXT_EMUL_CPUID: 3720 case KVM_CAP_CLOCKSOURCE: 3721 case KVM_CAP_PIT: 3722 case KVM_CAP_NOP_IO_DELAY: 3723 case KVM_CAP_MP_STATE: 3724 case KVM_CAP_SYNC_MMU: 3725 case KVM_CAP_USER_NMI: 3726 case KVM_CAP_REINJECT_CONTROL: 3727 case KVM_CAP_IRQ_INJECT_STATUS: 3728 case KVM_CAP_IOEVENTFD: 3729 case KVM_CAP_IOEVENTFD_NO_LENGTH: 3730 case KVM_CAP_PIT2: 3731 case KVM_CAP_PIT_STATE2: 3732 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 3733 case KVM_CAP_XEN_HVM: 3734 case KVM_CAP_VCPU_EVENTS: 3735 case KVM_CAP_HYPERV: 3736 case KVM_CAP_HYPERV_VAPIC: 3737 case KVM_CAP_HYPERV_SPIN: 3738 case KVM_CAP_HYPERV_SYNIC: 3739 case KVM_CAP_HYPERV_SYNIC2: 3740 case KVM_CAP_HYPERV_VP_INDEX: 3741 case KVM_CAP_HYPERV_EVENTFD: 3742 case KVM_CAP_HYPERV_TLBFLUSH: 3743 case KVM_CAP_HYPERV_SEND_IPI: 3744 case KVM_CAP_HYPERV_CPUID: 3745 case KVM_CAP_SYS_HYPERV_CPUID: 3746 case KVM_CAP_PCI_SEGMENT: 3747 case KVM_CAP_DEBUGREGS: 3748 case KVM_CAP_X86_ROBUST_SINGLESTEP: 3749 case KVM_CAP_XSAVE: 3750 case KVM_CAP_ASYNC_PF: 3751 case KVM_CAP_ASYNC_PF_INT: 3752 case KVM_CAP_GET_TSC_KHZ: 3753 case KVM_CAP_KVMCLOCK_CTRL: 3754 case KVM_CAP_READONLY_MEM: 3755 case KVM_CAP_HYPERV_TIME: 3756 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 3757 case KVM_CAP_TSC_DEADLINE_TIMER: 3758 case KVM_CAP_DISABLE_QUIRKS: 3759 case KVM_CAP_SET_BOOT_CPU_ID: 3760 case KVM_CAP_SPLIT_IRQCHIP: 3761 case KVM_CAP_IMMEDIATE_EXIT: 3762 case KVM_CAP_PMU_EVENT_FILTER: 3763 case KVM_CAP_GET_MSR_FEATURES: 3764 case KVM_CAP_MSR_PLATFORM_INFO: 3765 case KVM_CAP_EXCEPTION_PAYLOAD: 3766 case KVM_CAP_SET_GUEST_DEBUG: 3767 case KVM_CAP_LAST_CPU: 3768 case KVM_CAP_X86_USER_SPACE_MSR: 3769 case KVM_CAP_X86_MSR_FILTER: 3770 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 3771 r = 1; 3772 break; 3773 case KVM_CAP_SYNC_REGS: 3774 r = KVM_SYNC_X86_VALID_FIELDS; 3775 break; 3776 case KVM_CAP_ADJUST_CLOCK: 3777 r = KVM_CLOCK_TSC_STABLE; 3778 break; 3779 case KVM_CAP_X86_DISABLE_EXITS: 3780 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | 3781 KVM_X86_DISABLE_EXITS_CSTATE; 3782 if(kvm_can_mwait_in_guest()) 3783 r |= KVM_X86_DISABLE_EXITS_MWAIT; 3784 break; 3785 case KVM_CAP_X86_SMM: 3786 /* SMBASE is usually relocated above 1M on modern chipsets, 3787 * and SMM handlers might indeed rely on 4G segment limits, 3788 * so do not report SMM to be available if real mode is 3789 * emulated via vm86 mode. Still, do not go to great lengths 3790 * to avoid userspace's usage of the feature, because it is a 3791 * fringe case that is not enabled except via specific settings 3792 * of the module parameters. 3793 */ 3794 r = kvm_x86_ops.has_emulated_msr(kvm, MSR_IA32_SMBASE); 3795 break; 3796 case KVM_CAP_VAPIC: 3797 r = !kvm_x86_ops.cpu_has_accelerated_tpr(); 3798 break; 3799 case KVM_CAP_NR_VCPUS: 3800 r = KVM_SOFT_MAX_VCPUS; 3801 break; 3802 case KVM_CAP_MAX_VCPUS: 3803 r = KVM_MAX_VCPUS; 3804 break; 3805 case KVM_CAP_MAX_VCPU_ID: 3806 r = KVM_MAX_VCPU_ID; 3807 break; 3808 case KVM_CAP_PV_MMU: /* obsolete */ 3809 r = 0; 3810 break; 3811 case KVM_CAP_MCE: 3812 r = KVM_MAX_MCE_BANKS; 3813 break; 3814 case KVM_CAP_XCRS: 3815 r = boot_cpu_has(X86_FEATURE_XSAVE); 3816 break; 3817 case KVM_CAP_TSC_CONTROL: 3818 r = kvm_has_tsc_control; 3819 break; 3820 case KVM_CAP_X2APIC_API: 3821 r = KVM_X2APIC_API_VALID_FLAGS; 3822 break; 3823 case KVM_CAP_NESTED_STATE: 3824 r = kvm_x86_ops.nested_ops->get_state ? 3825 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; 3826 break; 3827 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 3828 r = kvm_x86_ops.enable_direct_tlbflush != NULL; 3829 break; 3830 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 3831 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; 3832 break; 3833 case KVM_CAP_SMALLER_MAXPHYADDR: 3834 r = (int) allow_smaller_maxphyaddr; 3835 break; 3836 case KVM_CAP_STEAL_TIME: 3837 r = sched_info_on(); 3838 break; 3839 default: 3840 break; 3841 } 3842 return r; 3843 3844 } 3845 3846 long kvm_arch_dev_ioctl(struct file *filp, 3847 unsigned int ioctl, unsigned long arg) 3848 { 3849 void __user *argp = (void __user *)arg; 3850 long r; 3851 3852 switch (ioctl) { 3853 case KVM_GET_MSR_INDEX_LIST: { 3854 struct kvm_msr_list __user *user_msr_list = argp; 3855 struct kvm_msr_list msr_list; 3856 unsigned n; 3857 3858 r = -EFAULT; 3859 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3860 goto out; 3861 n = msr_list.nmsrs; 3862 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 3863 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3864 goto out; 3865 r = -E2BIG; 3866 if (n < msr_list.nmsrs) 3867 goto out; 3868 r = -EFAULT; 3869 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 3870 num_msrs_to_save * sizeof(u32))) 3871 goto out; 3872 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 3873 &emulated_msrs, 3874 num_emulated_msrs * sizeof(u32))) 3875 goto out; 3876 r = 0; 3877 break; 3878 } 3879 case KVM_GET_SUPPORTED_CPUID: 3880 case KVM_GET_EMULATED_CPUID: { 3881 struct kvm_cpuid2 __user *cpuid_arg = argp; 3882 struct kvm_cpuid2 cpuid; 3883 3884 r = -EFAULT; 3885 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3886 goto out; 3887 3888 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 3889 ioctl); 3890 if (r) 3891 goto out; 3892 3893 r = -EFAULT; 3894 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 3895 goto out; 3896 r = 0; 3897 break; 3898 } 3899 case KVM_X86_GET_MCE_CAP_SUPPORTED: 3900 r = -EFAULT; 3901 if (copy_to_user(argp, &kvm_mce_cap_supported, 3902 sizeof(kvm_mce_cap_supported))) 3903 goto out; 3904 r = 0; 3905 break; 3906 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 3907 struct kvm_msr_list __user *user_msr_list = argp; 3908 struct kvm_msr_list msr_list; 3909 unsigned int n; 3910 3911 r = -EFAULT; 3912 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3913 goto out; 3914 n = msr_list.nmsrs; 3915 msr_list.nmsrs = num_msr_based_features; 3916 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3917 goto out; 3918 r = -E2BIG; 3919 if (n < msr_list.nmsrs) 3920 goto out; 3921 r = -EFAULT; 3922 if (copy_to_user(user_msr_list->indices, &msr_based_features, 3923 num_msr_based_features * sizeof(u32))) 3924 goto out; 3925 r = 0; 3926 break; 3927 } 3928 case KVM_GET_MSRS: 3929 r = msr_io(NULL, argp, do_get_msr_feature, 1); 3930 break; 3931 case KVM_GET_SUPPORTED_HV_CPUID: 3932 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); 3933 break; 3934 default: 3935 r = -EINVAL; 3936 break; 3937 } 3938 out: 3939 return r; 3940 } 3941 3942 static void wbinvd_ipi(void *garbage) 3943 { 3944 wbinvd(); 3945 } 3946 3947 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 3948 { 3949 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 3950 } 3951 3952 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 3953 { 3954 /* Address WBINVD may be executed by guest */ 3955 if (need_emulate_wbinvd(vcpu)) { 3956 if (kvm_x86_ops.has_wbinvd_exit()) 3957 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 3958 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 3959 smp_call_function_single(vcpu->cpu, 3960 wbinvd_ipi, NULL, 1); 3961 } 3962 3963 kvm_x86_ops.vcpu_load(vcpu, cpu); 3964 3965 /* Save host pkru register if supported */ 3966 vcpu->arch.host_pkru = read_pkru(); 3967 3968 /* Apply any externally detected TSC adjustments (due to suspend) */ 3969 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 3970 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 3971 vcpu->arch.tsc_offset_adjustment = 0; 3972 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3973 } 3974 3975 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 3976 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 3977 rdtsc() - vcpu->arch.last_host_tsc; 3978 if (tsc_delta < 0) 3979 mark_tsc_unstable("KVM discovered backwards TSC"); 3980 3981 if (kvm_check_tsc_unstable()) { 3982 u64 offset = kvm_compute_tsc_offset(vcpu, 3983 vcpu->arch.last_guest_tsc); 3984 kvm_vcpu_write_tsc_offset(vcpu, offset); 3985 vcpu->arch.tsc_catchup = 1; 3986 } 3987 3988 if (kvm_lapic_hv_timer_in_use(vcpu)) 3989 kvm_lapic_restart_hv_timer(vcpu); 3990 3991 /* 3992 * On a host with synchronized TSC, there is no need to update 3993 * kvmclock on vcpu->cpu migration 3994 */ 3995 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 3996 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 3997 if (vcpu->cpu != cpu) 3998 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 3999 vcpu->cpu = cpu; 4000 } 4001 4002 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 4003 } 4004 4005 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 4006 { 4007 struct kvm_host_map map; 4008 struct kvm_steal_time *st; 4009 4010 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 4011 return; 4012 4013 if (vcpu->arch.st.preempted) 4014 return; 4015 4016 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, 4017 &vcpu->arch.st.cache, true)) 4018 return; 4019 4020 st = map.hva + 4021 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 4022 4023 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 4024 4025 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); 4026 } 4027 4028 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 4029 { 4030 int idx; 4031 4032 if (vcpu->preempted && !vcpu->arch.guest_state_protected) 4033 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu); 4034 4035 /* 4036 * Disable page faults because we're in atomic context here. 4037 * kvm_write_guest_offset_cached() would call might_fault() 4038 * that relies on pagefault_disable() to tell if there's a 4039 * bug. NOTE: the write to guest memory may not go through if 4040 * during postcopy live migration or if there's heavy guest 4041 * paging. 4042 */ 4043 pagefault_disable(); 4044 /* 4045 * kvm_memslots() will be called by 4046 * kvm_write_guest_offset_cached() so take the srcu lock. 4047 */ 4048 idx = srcu_read_lock(&vcpu->kvm->srcu); 4049 kvm_steal_time_set_preempted(vcpu); 4050 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4051 pagefault_enable(); 4052 kvm_x86_ops.vcpu_put(vcpu); 4053 vcpu->arch.last_host_tsc = rdtsc(); 4054 /* 4055 * If userspace has set any breakpoints or watchpoints, dr6 is restored 4056 * on every vmexit, but if not, we might have a stale dr6 from the 4057 * guest. do_debug expects dr6 to be cleared after it runs, do the same. 4058 */ 4059 set_debugreg(0, 6); 4060 } 4061 4062 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 4063 struct kvm_lapic_state *s) 4064 { 4065 if (vcpu->arch.apicv_active) 4066 kvm_x86_ops.sync_pir_to_irr(vcpu); 4067 4068 return kvm_apic_get_state(vcpu, s); 4069 } 4070 4071 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 4072 struct kvm_lapic_state *s) 4073 { 4074 int r; 4075 4076 r = kvm_apic_set_state(vcpu, s); 4077 if (r) 4078 return r; 4079 update_cr8_intercept(vcpu); 4080 4081 return 0; 4082 } 4083 4084 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 4085 { 4086 /* 4087 * We can accept userspace's request for interrupt injection 4088 * as long as we have a place to store the interrupt number. 4089 * The actual injection will happen when the CPU is able to 4090 * deliver the interrupt. 4091 */ 4092 if (kvm_cpu_has_extint(vcpu)) 4093 return false; 4094 4095 /* Acknowledging ExtINT does not happen if LINT0 is masked. */ 4096 return (!lapic_in_kernel(vcpu) || 4097 kvm_apic_accept_pic_intr(vcpu)); 4098 } 4099 4100 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 4101 { 4102 return kvm_arch_interrupt_allowed(vcpu) && 4103 kvm_cpu_accept_dm_intr(vcpu); 4104 } 4105 4106 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 4107 struct kvm_interrupt *irq) 4108 { 4109 if (irq->irq >= KVM_NR_INTERRUPTS) 4110 return -EINVAL; 4111 4112 if (!irqchip_in_kernel(vcpu->kvm)) { 4113 kvm_queue_interrupt(vcpu, irq->irq, false); 4114 kvm_make_request(KVM_REQ_EVENT, vcpu); 4115 return 0; 4116 } 4117 4118 /* 4119 * With in-kernel LAPIC, we only use this to inject EXTINT, so 4120 * fail for in-kernel 8259. 4121 */ 4122 if (pic_in_kernel(vcpu->kvm)) 4123 return -ENXIO; 4124 4125 if (vcpu->arch.pending_external_vector != -1) 4126 return -EEXIST; 4127 4128 vcpu->arch.pending_external_vector = irq->irq; 4129 kvm_make_request(KVM_REQ_EVENT, vcpu); 4130 return 0; 4131 } 4132 4133 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 4134 { 4135 kvm_inject_nmi(vcpu); 4136 4137 return 0; 4138 } 4139 4140 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 4141 { 4142 kvm_make_request(KVM_REQ_SMI, vcpu); 4143 4144 return 0; 4145 } 4146 4147 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 4148 struct kvm_tpr_access_ctl *tac) 4149 { 4150 if (tac->flags) 4151 return -EINVAL; 4152 vcpu->arch.tpr_access_reporting = !!tac->enabled; 4153 return 0; 4154 } 4155 4156 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 4157 u64 mcg_cap) 4158 { 4159 int r; 4160 unsigned bank_num = mcg_cap & 0xff, bank; 4161 4162 r = -EINVAL; 4163 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) 4164 goto out; 4165 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 4166 goto out; 4167 r = 0; 4168 vcpu->arch.mcg_cap = mcg_cap; 4169 /* Init IA32_MCG_CTL to all 1s */ 4170 if (mcg_cap & MCG_CTL_P) 4171 vcpu->arch.mcg_ctl = ~(u64)0; 4172 /* Init IA32_MCi_CTL to all 1s */ 4173 for (bank = 0; bank < bank_num; bank++) 4174 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 4175 4176 kvm_x86_ops.setup_mce(vcpu); 4177 out: 4178 return r; 4179 } 4180 4181 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 4182 struct kvm_x86_mce *mce) 4183 { 4184 u64 mcg_cap = vcpu->arch.mcg_cap; 4185 unsigned bank_num = mcg_cap & 0xff; 4186 u64 *banks = vcpu->arch.mce_banks; 4187 4188 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 4189 return -EINVAL; 4190 /* 4191 * if IA32_MCG_CTL is not all 1s, the uncorrected error 4192 * reporting is disabled 4193 */ 4194 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 4195 vcpu->arch.mcg_ctl != ~(u64)0) 4196 return 0; 4197 banks += 4 * mce->bank; 4198 /* 4199 * if IA32_MCi_CTL is not all 1s, the uncorrected error 4200 * reporting is disabled for the bank 4201 */ 4202 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 4203 return 0; 4204 if (mce->status & MCI_STATUS_UC) { 4205 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 4206 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 4207 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 4208 return 0; 4209 } 4210 if (banks[1] & MCI_STATUS_VAL) 4211 mce->status |= MCI_STATUS_OVER; 4212 banks[2] = mce->addr; 4213 banks[3] = mce->misc; 4214 vcpu->arch.mcg_status = mce->mcg_status; 4215 banks[1] = mce->status; 4216 kvm_queue_exception(vcpu, MC_VECTOR); 4217 } else if (!(banks[1] & MCI_STATUS_VAL) 4218 || !(banks[1] & MCI_STATUS_UC)) { 4219 if (banks[1] & MCI_STATUS_VAL) 4220 mce->status |= MCI_STATUS_OVER; 4221 banks[2] = mce->addr; 4222 banks[3] = mce->misc; 4223 banks[1] = mce->status; 4224 } else 4225 banks[1] |= MCI_STATUS_OVER; 4226 return 0; 4227 } 4228 4229 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 4230 struct kvm_vcpu_events *events) 4231 { 4232 process_nmi(vcpu); 4233 4234 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 4235 process_smi(vcpu); 4236 4237 /* 4238 * In guest mode, payload delivery should be deferred, 4239 * so that the L1 hypervisor can intercept #PF before 4240 * CR2 is modified (or intercept #DB before DR6 is 4241 * modified under nVMX). Unless the per-VM capability, 4242 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of 4243 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we 4244 * opportunistically defer the exception payload, deliver it if the 4245 * capability hasn't been requested before processing a 4246 * KVM_GET_VCPU_EVENTS. 4247 */ 4248 if (!vcpu->kvm->arch.exception_payload_enabled && 4249 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) 4250 kvm_deliver_exception_payload(vcpu); 4251 4252 /* 4253 * The API doesn't provide the instruction length for software 4254 * exceptions, so don't report them. As long as the guest RIP 4255 * isn't advanced, we should expect to encounter the exception 4256 * again. 4257 */ 4258 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 4259 events->exception.injected = 0; 4260 events->exception.pending = 0; 4261 } else { 4262 events->exception.injected = vcpu->arch.exception.injected; 4263 events->exception.pending = vcpu->arch.exception.pending; 4264 /* 4265 * For ABI compatibility, deliberately conflate 4266 * pending and injected exceptions when 4267 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 4268 */ 4269 if (!vcpu->kvm->arch.exception_payload_enabled) 4270 events->exception.injected |= 4271 vcpu->arch.exception.pending; 4272 } 4273 events->exception.nr = vcpu->arch.exception.nr; 4274 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 4275 events->exception.error_code = vcpu->arch.exception.error_code; 4276 events->exception_has_payload = vcpu->arch.exception.has_payload; 4277 events->exception_payload = vcpu->arch.exception.payload; 4278 4279 events->interrupt.injected = 4280 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 4281 events->interrupt.nr = vcpu->arch.interrupt.nr; 4282 events->interrupt.soft = 0; 4283 events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu); 4284 4285 events->nmi.injected = vcpu->arch.nmi_injected; 4286 events->nmi.pending = vcpu->arch.nmi_pending != 0; 4287 events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu); 4288 events->nmi.pad = 0; 4289 4290 events->sipi_vector = 0; /* never valid when reporting to user space */ 4291 4292 events->smi.smm = is_smm(vcpu); 4293 events->smi.pending = vcpu->arch.smi_pending; 4294 events->smi.smm_inside_nmi = 4295 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 4296 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 4297 4298 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 4299 | KVM_VCPUEVENT_VALID_SHADOW 4300 | KVM_VCPUEVENT_VALID_SMM); 4301 if (vcpu->kvm->arch.exception_payload_enabled) 4302 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 4303 4304 memset(&events->reserved, 0, sizeof(events->reserved)); 4305 } 4306 4307 static void kvm_smm_changed(struct kvm_vcpu *vcpu); 4308 4309 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 4310 struct kvm_vcpu_events *events) 4311 { 4312 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 4313 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 4314 | KVM_VCPUEVENT_VALID_SHADOW 4315 | KVM_VCPUEVENT_VALID_SMM 4316 | KVM_VCPUEVENT_VALID_PAYLOAD)) 4317 return -EINVAL; 4318 4319 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 4320 if (!vcpu->kvm->arch.exception_payload_enabled) 4321 return -EINVAL; 4322 if (events->exception.pending) 4323 events->exception.injected = 0; 4324 else 4325 events->exception_has_payload = 0; 4326 } else { 4327 events->exception.pending = 0; 4328 events->exception_has_payload = 0; 4329 } 4330 4331 if ((events->exception.injected || events->exception.pending) && 4332 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 4333 return -EINVAL; 4334 4335 /* INITs are latched while in SMM */ 4336 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 4337 (events->smi.smm || events->smi.pending) && 4338 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 4339 return -EINVAL; 4340 4341 process_nmi(vcpu); 4342 vcpu->arch.exception.injected = events->exception.injected; 4343 vcpu->arch.exception.pending = events->exception.pending; 4344 vcpu->arch.exception.nr = events->exception.nr; 4345 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 4346 vcpu->arch.exception.error_code = events->exception.error_code; 4347 vcpu->arch.exception.has_payload = events->exception_has_payload; 4348 vcpu->arch.exception.payload = events->exception_payload; 4349 4350 vcpu->arch.interrupt.injected = events->interrupt.injected; 4351 vcpu->arch.interrupt.nr = events->interrupt.nr; 4352 vcpu->arch.interrupt.soft = events->interrupt.soft; 4353 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 4354 kvm_x86_ops.set_interrupt_shadow(vcpu, 4355 events->interrupt.shadow); 4356 4357 vcpu->arch.nmi_injected = events->nmi.injected; 4358 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 4359 vcpu->arch.nmi_pending = events->nmi.pending; 4360 kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked); 4361 4362 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 4363 lapic_in_kernel(vcpu)) 4364 vcpu->arch.apic->sipi_vector = events->sipi_vector; 4365 4366 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 4367 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { 4368 if (events->smi.smm) 4369 vcpu->arch.hflags |= HF_SMM_MASK; 4370 else 4371 vcpu->arch.hflags &= ~HF_SMM_MASK; 4372 kvm_smm_changed(vcpu); 4373 } 4374 4375 vcpu->arch.smi_pending = events->smi.pending; 4376 4377 if (events->smi.smm) { 4378 if (events->smi.smm_inside_nmi) 4379 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 4380 else 4381 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 4382 } 4383 4384 if (lapic_in_kernel(vcpu)) { 4385 if (events->smi.latched_init) 4386 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4387 else 4388 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4389 } 4390 } 4391 4392 kvm_make_request(KVM_REQ_EVENT, vcpu); 4393 4394 return 0; 4395 } 4396 4397 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 4398 struct kvm_debugregs *dbgregs) 4399 { 4400 unsigned long val; 4401 4402 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 4403 kvm_get_dr(vcpu, 6, &val); 4404 dbgregs->dr6 = val; 4405 dbgregs->dr7 = vcpu->arch.dr7; 4406 dbgregs->flags = 0; 4407 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 4408 } 4409 4410 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 4411 struct kvm_debugregs *dbgregs) 4412 { 4413 if (dbgregs->flags) 4414 return -EINVAL; 4415 4416 if (dbgregs->dr6 & ~0xffffffffull) 4417 return -EINVAL; 4418 if (dbgregs->dr7 & ~0xffffffffull) 4419 return -EINVAL; 4420 4421 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 4422 kvm_update_dr0123(vcpu); 4423 vcpu->arch.dr6 = dbgregs->dr6; 4424 vcpu->arch.dr7 = dbgregs->dr7; 4425 kvm_update_dr7(vcpu); 4426 4427 return 0; 4428 } 4429 4430 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 4431 4432 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 4433 { 4434 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 4435 u64 xstate_bv = xsave->header.xfeatures; 4436 u64 valid; 4437 4438 /* 4439 * Copy legacy XSAVE area, to avoid complications with CPUID 4440 * leaves 0 and 1 in the loop below. 4441 */ 4442 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 4443 4444 /* Set XSTATE_BV */ 4445 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; 4446 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 4447 4448 /* 4449 * Copy each region from the possibly compacted offset to the 4450 * non-compacted offset. 4451 */ 4452 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 4453 while (valid) { 4454 u64 xfeature_mask = valid & -valid; 4455 int xfeature_nr = fls64(xfeature_mask) - 1; 4456 void *src = get_xsave_addr(xsave, xfeature_nr); 4457 4458 if (src) { 4459 u32 size, offset, ecx, edx; 4460 cpuid_count(XSTATE_CPUID, xfeature_nr, 4461 &size, &offset, &ecx, &edx); 4462 if (xfeature_nr == XFEATURE_PKRU) 4463 memcpy(dest + offset, &vcpu->arch.pkru, 4464 sizeof(vcpu->arch.pkru)); 4465 else 4466 memcpy(dest + offset, src, size); 4467 4468 } 4469 4470 valid -= xfeature_mask; 4471 } 4472 } 4473 4474 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 4475 { 4476 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 4477 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 4478 u64 valid; 4479 4480 /* 4481 * Copy legacy XSAVE area, to avoid complications with CPUID 4482 * leaves 0 and 1 in the loop below. 4483 */ 4484 memcpy(xsave, src, XSAVE_HDR_OFFSET); 4485 4486 /* Set XSTATE_BV and possibly XCOMP_BV. */ 4487 xsave->header.xfeatures = xstate_bv; 4488 if (boot_cpu_has(X86_FEATURE_XSAVES)) 4489 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 4490 4491 /* 4492 * Copy each region from the non-compacted offset to the 4493 * possibly compacted offset. 4494 */ 4495 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 4496 while (valid) { 4497 u64 xfeature_mask = valid & -valid; 4498 int xfeature_nr = fls64(xfeature_mask) - 1; 4499 void *dest = get_xsave_addr(xsave, xfeature_nr); 4500 4501 if (dest) { 4502 u32 size, offset, ecx, edx; 4503 cpuid_count(XSTATE_CPUID, xfeature_nr, 4504 &size, &offset, &ecx, &edx); 4505 if (xfeature_nr == XFEATURE_PKRU) 4506 memcpy(&vcpu->arch.pkru, src + offset, 4507 sizeof(vcpu->arch.pkru)); 4508 else 4509 memcpy(dest, src + offset, size); 4510 } 4511 4512 valid -= xfeature_mask; 4513 } 4514 } 4515 4516 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 4517 struct kvm_xsave *guest_xsave) 4518 { 4519 if (!vcpu->arch.guest_fpu) 4520 return; 4521 4522 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 4523 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 4524 fill_xsave((u8 *) guest_xsave->region, vcpu); 4525 } else { 4526 memcpy(guest_xsave->region, 4527 &vcpu->arch.guest_fpu->state.fxsave, 4528 sizeof(struct fxregs_state)); 4529 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 4530 XFEATURE_MASK_FPSSE; 4531 } 4532 } 4533 4534 #define XSAVE_MXCSR_OFFSET 24 4535 4536 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 4537 struct kvm_xsave *guest_xsave) 4538 { 4539 u64 xstate_bv; 4540 u32 mxcsr; 4541 4542 if (!vcpu->arch.guest_fpu) 4543 return 0; 4544 4545 xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 4546 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; 4547 4548 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 4549 /* 4550 * Here we allow setting states that are not present in 4551 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 4552 * with old userspace. 4553 */ 4554 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask) 4555 return -EINVAL; 4556 load_xsave(vcpu, (u8 *)guest_xsave->region); 4557 } else { 4558 if (xstate_bv & ~XFEATURE_MASK_FPSSE || 4559 mxcsr & ~mxcsr_feature_mask) 4560 return -EINVAL; 4561 memcpy(&vcpu->arch.guest_fpu->state.fxsave, 4562 guest_xsave->region, sizeof(struct fxregs_state)); 4563 } 4564 return 0; 4565 } 4566 4567 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 4568 struct kvm_xcrs *guest_xcrs) 4569 { 4570 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 4571 guest_xcrs->nr_xcrs = 0; 4572 return; 4573 } 4574 4575 guest_xcrs->nr_xcrs = 1; 4576 guest_xcrs->flags = 0; 4577 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 4578 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 4579 } 4580 4581 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 4582 struct kvm_xcrs *guest_xcrs) 4583 { 4584 int i, r = 0; 4585 4586 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 4587 return -EINVAL; 4588 4589 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 4590 return -EINVAL; 4591 4592 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 4593 /* Only support XCR0 currently */ 4594 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 4595 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 4596 guest_xcrs->xcrs[i].value); 4597 break; 4598 } 4599 if (r) 4600 r = -EINVAL; 4601 return r; 4602 } 4603 4604 /* 4605 * kvm_set_guest_paused() indicates to the guest kernel that it has been 4606 * stopped by the hypervisor. This function will be called from the host only. 4607 * EINVAL is returned when the host attempts to set the flag for a guest that 4608 * does not support pv clocks. 4609 */ 4610 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 4611 { 4612 if (!vcpu->arch.pv_time_enabled) 4613 return -EINVAL; 4614 vcpu->arch.pvclock_set_guest_stopped_request = true; 4615 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4616 return 0; 4617 } 4618 4619 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 4620 struct kvm_enable_cap *cap) 4621 { 4622 int r; 4623 uint16_t vmcs_version; 4624 void __user *user_ptr; 4625 4626 if (cap->flags) 4627 return -EINVAL; 4628 4629 switch (cap->cap) { 4630 case KVM_CAP_HYPERV_SYNIC2: 4631 if (cap->args[0]) 4632 return -EINVAL; 4633 fallthrough; 4634 4635 case KVM_CAP_HYPERV_SYNIC: 4636 if (!irqchip_in_kernel(vcpu->kvm)) 4637 return -EINVAL; 4638 return kvm_hv_activate_synic(vcpu, cap->cap == 4639 KVM_CAP_HYPERV_SYNIC2); 4640 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4641 if (!kvm_x86_ops.nested_ops->enable_evmcs) 4642 return -ENOTTY; 4643 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); 4644 if (!r) { 4645 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 4646 if (copy_to_user(user_ptr, &vmcs_version, 4647 sizeof(vmcs_version))) 4648 r = -EFAULT; 4649 } 4650 return r; 4651 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4652 if (!kvm_x86_ops.enable_direct_tlbflush) 4653 return -ENOTTY; 4654 4655 return kvm_x86_ops.enable_direct_tlbflush(vcpu); 4656 4657 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 4658 vcpu->arch.pv_cpuid.enforce = cap->args[0]; 4659 if (vcpu->arch.pv_cpuid.enforce) 4660 kvm_update_pv_runtime(vcpu); 4661 4662 return 0; 4663 4664 default: 4665 return -EINVAL; 4666 } 4667 } 4668 4669 long kvm_arch_vcpu_ioctl(struct file *filp, 4670 unsigned int ioctl, unsigned long arg) 4671 { 4672 struct kvm_vcpu *vcpu = filp->private_data; 4673 void __user *argp = (void __user *)arg; 4674 int r; 4675 union { 4676 struct kvm_lapic_state *lapic; 4677 struct kvm_xsave *xsave; 4678 struct kvm_xcrs *xcrs; 4679 void *buffer; 4680 } u; 4681 4682 vcpu_load(vcpu); 4683 4684 u.buffer = NULL; 4685 switch (ioctl) { 4686 case KVM_GET_LAPIC: { 4687 r = -EINVAL; 4688 if (!lapic_in_kernel(vcpu)) 4689 goto out; 4690 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 4691 GFP_KERNEL_ACCOUNT); 4692 4693 r = -ENOMEM; 4694 if (!u.lapic) 4695 goto out; 4696 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 4697 if (r) 4698 goto out; 4699 r = -EFAULT; 4700 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 4701 goto out; 4702 r = 0; 4703 break; 4704 } 4705 case KVM_SET_LAPIC: { 4706 r = -EINVAL; 4707 if (!lapic_in_kernel(vcpu)) 4708 goto out; 4709 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 4710 if (IS_ERR(u.lapic)) { 4711 r = PTR_ERR(u.lapic); 4712 goto out_nofree; 4713 } 4714 4715 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 4716 break; 4717 } 4718 case KVM_INTERRUPT: { 4719 struct kvm_interrupt irq; 4720 4721 r = -EFAULT; 4722 if (copy_from_user(&irq, argp, sizeof(irq))) 4723 goto out; 4724 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 4725 break; 4726 } 4727 case KVM_NMI: { 4728 r = kvm_vcpu_ioctl_nmi(vcpu); 4729 break; 4730 } 4731 case KVM_SMI: { 4732 r = kvm_vcpu_ioctl_smi(vcpu); 4733 break; 4734 } 4735 case KVM_SET_CPUID: { 4736 struct kvm_cpuid __user *cpuid_arg = argp; 4737 struct kvm_cpuid cpuid; 4738 4739 r = -EFAULT; 4740 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4741 goto out; 4742 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 4743 break; 4744 } 4745 case KVM_SET_CPUID2: { 4746 struct kvm_cpuid2 __user *cpuid_arg = argp; 4747 struct kvm_cpuid2 cpuid; 4748 4749 r = -EFAULT; 4750 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4751 goto out; 4752 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 4753 cpuid_arg->entries); 4754 break; 4755 } 4756 case KVM_GET_CPUID2: { 4757 struct kvm_cpuid2 __user *cpuid_arg = argp; 4758 struct kvm_cpuid2 cpuid; 4759 4760 r = -EFAULT; 4761 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4762 goto out; 4763 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 4764 cpuid_arg->entries); 4765 if (r) 4766 goto out; 4767 r = -EFAULT; 4768 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4769 goto out; 4770 r = 0; 4771 break; 4772 } 4773 case KVM_GET_MSRS: { 4774 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4775 r = msr_io(vcpu, argp, do_get_msr, 1); 4776 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4777 break; 4778 } 4779 case KVM_SET_MSRS: { 4780 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4781 r = msr_io(vcpu, argp, do_set_msr, 0); 4782 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4783 break; 4784 } 4785 case KVM_TPR_ACCESS_REPORTING: { 4786 struct kvm_tpr_access_ctl tac; 4787 4788 r = -EFAULT; 4789 if (copy_from_user(&tac, argp, sizeof(tac))) 4790 goto out; 4791 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 4792 if (r) 4793 goto out; 4794 r = -EFAULT; 4795 if (copy_to_user(argp, &tac, sizeof(tac))) 4796 goto out; 4797 r = 0; 4798 break; 4799 }; 4800 case KVM_SET_VAPIC_ADDR: { 4801 struct kvm_vapic_addr va; 4802 int idx; 4803 4804 r = -EINVAL; 4805 if (!lapic_in_kernel(vcpu)) 4806 goto out; 4807 r = -EFAULT; 4808 if (copy_from_user(&va, argp, sizeof(va))) 4809 goto out; 4810 idx = srcu_read_lock(&vcpu->kvm->srcu); 4811 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 4812 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4813 break; 4814 } 4815 case KVM_X86_SETUP_MCE: { 4816 u64 mcg_cap; 4817 4818 r = -EFAULT; 4819 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 4820 goto out; 4821 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 4822 break; 4823 } 4824 case KVM_X86_SET_MCE: { 4825 struct kvm_x86_mce mce; 4826 4827 r = -EFAULT; 4828 if (copy_from_user(&mce, argp, sizeof(mce))) 4829 goto out; 4830 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 4831 break; 4832 } 4833 case KVM_GET_VCPU_EVENTS: { 4834 struct kvm_vcpu_events events; 4835 4836 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 4837 4838 r = -EFAULT; 4839 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 4840 break; 4841 r = 0; 4842 break; 4843 } 4844 case KVM_SET_VCPU_EVENTS: { 4845 struct kvm_vcpu_events events; 4846 4847 r = -EFAULT; 4848 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 4849 break; 4850 4851 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 4852 break; 4853 } 4854 case KVM_GET_DEBUGREGS: { 4855 struct kvm_debugregs dbgregs; 4856 4857 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 4858 4859 r = -EFAULT; 4860 if (copy_to_user(argp, &dbgregs, 4861 sizeof(struct kvm_debugregs))) 4862 break; 4863 r = 0; 4864 break; 4865 } 4866 case KVM_SET_DEBUGREGS: { 4867 struct kvm_debugregs dbgregs; 4868 4869 r = -EFAULT; 4870 if (copy_from_user(&dbgregs, argp, 4871 sizeof(struct kvm_debugregs))) 4872 break; 4873 4874 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 4875 break; 4876 } 4877 case KVM_GET_XSAVE: { 4878 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 4879 r = -ENOMEM; 4880 if (!u.xsave) 4881 break; 4882 4883 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 4884 4885 r = -EFAULT; 4886 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 4887 break; 4888 r = 0; 4889 break; 4890 } 4891 case KVM_SET_XSAVE: { 4892 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 4893 if (IS_ERR(u.xsave)) { 4894 r = PTR_ERR(u.xsave); 4895 goto out_nofree; 4896 } 4897 4898 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 4899 break; 4900 } 4901 case KVM_GET_XCRS: { 4902 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 4903 r = -ENOMEM; 4904 if (!u.xcrs) 4905 break; 4906 4907 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 4908 4909 r = -EFAULT; 4910 if (copy_to_user(argp, u.xcrs, 4911 sizeof(struct kvm_xcrs))) 4912 break; 4913 r = 0; 4914 break; 4915 } 4916 case KVM_SET_XCRS: { 4917 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 4918 if (IS_ERR(u.xcrs)) { 4919 r = PTR_ERR(u.xcrs); 4920 goto out_nofree; 4921 } 4922 4923 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 4924 break; 4925 } 4926 case KVM_SET_TSC_KHZ: { 4927 u32 user_tsc_khz; 4928 4929 r = -EINVAL; 4930 user_tsc_khz = (u32)arg; 4931 4932 if (kvm_has_tsc_control && 4933 user_tsc_khz >= kvm_max_guest_tsc_khz) 4934 goto out; 4935 4936 if (user_tsc_khz == 0) 4937 user_tsc_khz = tsc_khz; 4938 4939 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 4940 r = 0; 4941 4942 goto out; 4943 } 4944 case KVM_GET_TSC_KHZ: { 4945 r = vcpu->arch.virtual_tsc_khz; 4946 goto out; 4947 } 4948 case KVM_KVMCLOCK_CTRL: { 4949 r = kvm_set_guest_paused(vcpu); 4950 goto out; 4951 } 4952 case KVM_ENABLE_CAP: { 4953 struct kvm_enable_cap cap; 4954 4955 r = -EFAULT; 4956 if (copy_from_user(&cap, argp, sizeof(cap))) 4957 goto out; 4958 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 4959 break; 4960 } 4961 case KVM_GET_NESTED_STATE: { 4962 struct kvm_nested_state __user *user_kvm_nested_state = argp; 4963 u32 user_data_size; 4964 4965 r = -EINVAL; 4966 if (!kvm_x86_ops.nested_ops->get_state) 4967 break; 4968 4969 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 4970 r = -EFAULT; 4971 if (get_user(user_data_size, &user_kvm_nested_state->size)) 4972 break; 4973 4974 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, 4975 user_data_size); 4976 if (r < 0) 4977 break; 4978 4979 if (r > user_data_size) { 4980 if (put_user(r, &user_kvm_nested_state->size)) 4981 r = -EFAULT; 4982 else 4983 r = -E2BIG; 4984 break; 4985 } 4986 4987 r = 0; 4988 break; 4989 } 4990 case KVM_SET_NESTED_STATE: { 4991 struct kvm_nested_state __user *user_kvm_nested_state = argp; 4992 struct kvm_nested_state kvm_state; 4993 int idx; 4994 4995 r = -EINVAL; 4996 if (!kvm_x86_ops.nested_ops->set_state) 4997 break; 4998 4999 r = -EFAULT; 5000 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 5001 break; 5002 5003 r = -EINVAL; 5004 if (kvm_state.size < sizeof(kvm_state)) 5005 break; 5006 5007 if (kvm_state.flags & 5008 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 5009 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING 5010 | KVM_STATE_NESTED_GIF_SET)) 5011 break; 5012 5013 /* nested_run_pending implies guest_mode. */ 5014 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 5015 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 5016 break; 5017 5018 idx = srcu_read_lock(&vcpu->kvm->srcu); 5019 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); 5020 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5021 break; 5022 } 5023 case KVM_GET_SUPPORTED_HV_CPUID: 5024 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); 5025 break; 5026 default: 5027 r = -EINVAL; 5028 } 5029 out: 5030 kfree(u.buffer); 5031 out_nofree: 5032 vcpu_put(vcpu); 5033 return r; 5034 } 5035 5036 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 5037 { 5038 return VM_FAULT_SIGBUS; 5039 } 5040 5041 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 5042 { 5043 int ret; 5044 5045 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 5046 return -EINVAL; 5047 ret = kvm_x86_ops.set_tss_addr(kvm, addr); 5048 return ret; 5049 } 5050 5051 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 5052 u64 ident_addr) 5053 { 5054 return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr); 5055 } 5056 5057 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 5058 unsigned long kvm_nr_mmu_pages) 5059 { 5060 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 5061 return -EINVAL; 5062 5063 mutex_lock(&kvm->slots_lock); 5064 5065 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 5066 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 5067 5068 mutex_unlock(&kvm->slots_lock); 5069 return 0; 5070 } 5071 5072 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 5073 { 5074 return kvm->arch.n_max_mmu_pages; 5075 } 5076 5077 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5078 { 5079 struct kvm_pic *pic = kvm->arch.vpic; 5080 int r; 5081 5082 r = 0; 5083 switch (chip->chip_id) { 5084 case KVM_IRQCHIP_PIC_MASTER: 5085 memcpy(&chip->chip.pic, &pic->pics[0], 5086 sizeof(struct kvm_pic_state)); 5087 break; 5088 case KVM_IRQCHIP_PIC_SLAVE: 5089 memcpy(&chip->chip.pic, &pic->pics[1], 5090 sizeof(struct kvm_pic_state)); 5091 break; 5092 case KVM_IRQCHIP_IOAPIC: 5093 kvm_get_ioapic(kvm, &chip->chip.ioapic); 5094 break; 5095 default: 5096 r = -EINVAL; 5097 break; 5098 } 5099 return r; 5100 } 5101 5102 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5103 { 5104 struct kvm_pic *pic = kvm->arch.vpic; 5105 int r; 5106 5107 r = 0; 5108 switch (chip->chip_id) { 5109 case KVM_IRQCHIP_PIC_MASTER: 5110 spin_lock(&pic->lock); 5111 memcpy(&pic->pics[0], &chip->chip.pic, 5112 sizeof(struct kvm_pic_state)); 5113 spin_unlock(&pic->lock); 5114 break; 5115 case KVM_IRQCHIP_PIC_SLAVE: 5116 spin_lock(&pic->lock); 5117 memcpy(&pic->pics[1], &chip->chip.pic, 5118 sizeof(struct kvm_pic_state)); 5119 spin_unlock(&pic->lock); 5120 break; 5121 case KVM_IRQCHIP_IOAPIC: 5122 kvm_set_ioapic(kvm, &chip->chip.ioapic); 5123 break; 5124 default: 5125 r = -EINVAL; 5126 break; 5127 } 5128 kvm_pic_update_irq(pic); 5129 return r; 5130 } 5131 5132 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5133 { 5134 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 5135 5136 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 5137 5138 mutex_lock(&kps->lock); 5139 memcpy(ps, &kps->channels, sizeof(*ps)); 5140 mutex_unlock(&kps->lock); 5141 return 0; 5142 } 5143 5144 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5145 { 5146 int i; 5147 struct kvm_pit *pit = kvm->arch.vpit; 5148 5149 mutex_lock(&pit->pit_state.lock); 5150 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 5151 for (i = 0; i < 3; i++) 5152 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 5153 mutex_unlock(&pit->pit_state.lock); 5154 return 0; 5155 } 5156 5157 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5158 { 5159 mutex_lock(&kvm->arch.vpit->pit_state.lock); 5160 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 5161 sizeof(ps->channels)); 5162 ps->flags = kvm->arch.vpit->pit_state.flags; 5163 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 5164 memset(&ps->reserved, 0, sizeof(ps->reserved)); 5165 return 0; 5166 } 5167 5168 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5169 { 5170 int start = 0; 5171 int i; 5172 u32 prev_legacy, cur_legacy; 5173 struct kvm_pit *pit = kvm->arch.vpit; 5174 5175 mutex_lock(&pit->pit_state.lock); 5176 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 5177 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 5178 if (!prev_legacy && cur_legacy) 5179 start = 1; 5180 memcpy(&pit->pit_state.channels, &ps->channels, 5181 sizeof(pit->pit_state.channels)); 5182 pit->pit_state.flags = ps->flags; 5183 for (i = 0; i < 3; i++) 5184 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 5185 start && i == 0); 5186 mutex_unlock(&pit->pit_state.lock); 5187 return 0; 5188 } 5189 5190 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 5191 struct kvm_reinject_control *control) 5192 { 5193 struct kvm_pit *pit = kvm->arch.vpit; 5194 5195 /* pit->pit_state.lock was overloaded to prevent userspace from getting 5196 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 5197 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 5198 */ 5199 mutex_lock(&pit->pit_state.lock); 5200 kvm_pit_set_reinject(pit, control->pit_reinject); 5201 mutex_unlock(&pit->pit_state.lock); 5202 5203 return 0; 5204 } 5205 5206 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 5207 { 5208 /* 5209 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 5210 */ 5211 if (kvm_x86_ops.flush_log_dirty) 5212 kvm_x86_ops.flush_log_dirty(kvm); 5213 } 5214 5215 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 5216 bool line_status) 5217 { 5218 if (!irqchip_in_kernel(kvm)) 5219 return -ENXIO; 5220 5221 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 5222 irq_event->irq, irq_event->level, 5223 line_status); 5224 return 0; 5225 } 5226 5227 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 5228 struct kvm_enable_cap *cap) 5229 { 5230 int r; 5231 5232 if (cap->flags) 5233 return -EINVAL; 5234 5235 switch (cap->cap) { 5236 case KVM_CAP_DISABLE_QUIRKS: 5237 kvm->arch.disabled_quirks = cap->args[0]; 5238 r = 0; 5239 break; 5240 case KVM_CAP_SPLIT_IRQCHIP: { 5241 mutex_lock(&kvm->lock); 5242 r = -EINVAL; 5243 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 5244 goto split_irqchip_unlock; 5245 r = -EEXIST; 5246 if (irqchip_in_kernel(kvm)) 5247 goto split_irqchip_unlock; 5248 if (kvm->created_vcpus) 5249 goto split_irqchip_unlock; 5250 r = kvm_setup_empty_irq_routing(kvm); 5251 if (r) 5252 goto split_irqchip_unlock; 5253 /* Pairs with irqchip_in_kernel. */ 5254 smp_wmb(); 5255 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 5256 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 5257 r = 0; 5258 split_irqchip_unlock: 5259 mutex_unlock(&kvm->lock); 5260 break; 5261 } 5262 case KVM_CAP_X2APIC_API: 5263 r = -EINVAL; 5264 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 5265 break; 5266 5267 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 5268 kvm->arch.x2apic_format = true; 5269 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 5270 kvm->arch.x2apic_broadcast_quirk_disabled = true; 5271 5272 r = 0; 5273 break; 5274 case KVM_CAP_X86_DISABLE_EXITS: 5275 r = -EINVAL; 5276 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 5277 break; 5278 5279 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 5280 kvm_can_mwait_in_guest()) 5281 kvm->arch.mwait_in_guest = true; 5282 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 5283 kvm->arch.hlt_in_guest = true; 5284 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 5285 kvm->arch.pause_in_guest = true; 5286 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) 5287 kvm->arch.cstate_in_guest = true; 5288 r = 0; 5289 break; 5290 case KVM_CAP_MSR_PLATFORM_INFO: 5291 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 5292 r = 0; 5293 break; 5294 case KVM_CAP_EXCEPTION_PAYLOAD: 5295 kvm->arch.exception_payload_enabled = cap->args[0]; 5296 r = 0; 5297 break; 5298 case KVM_CAP_X86_USER_SPACE_MSR: 5299 kvm->arch.user_space_msr_mask = cap->args[0]; 5300 r = 0; 5301 break; 5302 default: 5303 r = -EINVAL; 5304 break; 5305 } 5306 return r; 5307 } 5308 5309 static void kvm_clear_msr_filter(struct kvm *kvm) 5310 { 5311 u32 i; 5312 u32 count = kvm->arch.msr_filter.count; 5313 struct msr_bitmap_range ranges[16]; 5314 5315 mutex_lock(&kvm->lock); 5316 kvm->arch.msr_filter.count = 0; 5317 memcpy(ranges, kvm->arch.msr_filter.ranges, count * sizeof(ranges[0])); 5318 mutex_unlock(&kvm->lock); 5319 synchronize_srcu(&kvm->srcu); 5320 5321 for (i = 0; i < count; i++) 5322 kfree(ranges[i].bitmap); 5323 } 5324 5325 static int kvm_add_msr_filter(struct kvm *kvm, struct kvm_msr_filter_range *user_range) 5326 { 5327 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges; 5328 struct msr_bitmap_range range; 5329 unsigned long *bitmap = NULL; 5330 size_t bitmap_size; 5331 int r; 5332 5333 if (!user_range->nmsrs) 5334 return 0; 5335 5336 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); 5337 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) 5338 return -EINVAL; 5339 5340 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); 5341 if (IS_ERR(bitmap)) 5342 return PTR_ERR(bitmap); 5343 5344 range = (struct msr_bitmap_range) { 5345 .flags = user_range->flags, 5346 .base = user_range->base, 5347 .nmsrs = user_range->nmsrs, 5348 .bitmap = bitmap, 5349 }; 5350 5351 if (range.flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) { 5352 r = -EINVAL; 5353 goto err; 5354 } 5355 5356 if (!range.flags) { 5357 r = -EINVAL; 5358 goto err; 5359 } 5360 5361 /* Everything ok, add this range identifier to our global pool */ 5362 ranges[kvm->arch.msr_filter.count] = range; 5363 /* Make sure we filled the array before we tell anyone to walk it */ 5364 smp_wmb(); 5365 kvm->arch.msr_filter.count++; 5366 5367 return 0; 5368 err: 5369 kfree(bitmap); 5370 return r; 5371 } 5372 5373 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) 5374 { 5375 struct kvm_msr_filter __user *user_msr_filter = argp; 5376 struct kvm_msr_filter filter; 5377 bool default_allow; 5378 int r = 0; 5379 bool empty = true; 5380 u32 i; 5381 5382 if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) 5383 return -EFAULT; 5384 5385 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) 5386 empty &= !filter.ranges[i].nmsrs; 5387 5388 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); 5389 if (empty && !default_allow) 5390 return -EINVAL; 5391 5392 kvm_clear_msr_filter(kvm); 5393 5394 kvm->arch.msr_filter.default_allow = default_allow; 5395 5396 /* 5397 * Protect from concurrent calls to this function that could trigger 5398 * a TOCTOU violation on kvm->arch.msr_filter.count. 5399 */ 5400 mutex_lock(&kvm->lock); 5401 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { 5402 r = kvm_add_msr_filter(kvm, &filter.ranges[i]); 5403 if (r) 5404 break; 5405 } 5406 5407 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); 5408 mutex_unlock(&kvm->lock); 5409 5410 return r; 5411 } 5412 5413 long kvm_arch_vm_ioctl(struct file *filp, 5414 unsigned int ioctl, unsigned long arg) 5415 { 5416 struct kvm *kvm = filp->private_data; 5417 void __user *argp = (void __user *)arg; 5418 int r = -ENOTTY; 5419 /* 5420 * This union makes it completely explicit to gcc-3.x 5421 * that these two variables' stack usage should be 5422 * combined, not added together. 5423 */ 5424 union { 5425 struct kvm_pit_state ps; 5426 struct kvm_pit_state2 ps2; 5427 struct kvm_pit_config pit_config; 5428 } u; 5429 5430 switch (ioctl) { 5431 case KVM_SET_TSS_ADDR: 5432 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 5433 break; 5434 case KVM_SET_IDENTITY_MAP_ADDR: { 5435 u64 ident_addr; 5436 5437 mutex_lock(&kvm->lock); 5438 r = -EINVAL; 5439 if (kvm->created_vcpus) 5440 goto set_identity_unlock; 5441 r = -EFAULT; 5442 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 5443 goto set_identity_unlock; 5444 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 5445 set_identity_unlock: 5446 mutex_unlock(&kvm->lock); 5447 break; 5448 } 5449 case KVM_SET_NR_MMU_PAGES: 5450 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 5451 break; 5452 case KVM_GET_NR_MMU_PAGES: 5453 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 5454 break; 5455 case KVM_CREATE_IRQCHIP: { 5456 mutex_lock(&kvm->lock); 5457 5458 r = -EEXIST; 5459 if (irqchip_in_kernel(kvm)) 5460 goto create_irqchip_unlock; 5461 5462 r = -EINVAL; 5463 if (kvm->created_vcpus) 5464 goto create_irqchip_unlock; 5465 5466 r = kvm_pic_init(kvm); 5467 if (r) 5468 goto create_irqchip_unlock; 5469 5470 r = kvm_ioapic_init(kvm); 5471 if (r) { 5472 kvm_pic_destroy(kvm); 5473 goto create_irqchip_unlock; 5474 } 5475 5476 r = kvm_setup_default_irq_routing(kvm); 5477 if (r) { 5478 kvm_ioapic_destroy(kvm); 5479 kvm_pic_destroy(kvm); 5480 goto create_irqchip_unlock; 5481 } 5482 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 5483 smp_wmb(); 5484 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 5485 create_irqchip_unlock: 5486 mutex_unlock(&kvm->lock); 5487 break; 5488 } 5489 case KVM_CREATE_PIT: 5490 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 5491 goto create_pit; 5492 case KVM_CREATE_PIT2: 5493 r = -EFAULT; 5494 if (copy_from_user(&u.pit_config, argp, 5495 sizeof(struct kvm_pit_config))) 5496 goto out; 5497 create_pit: 5498 mutex_lock(&kvm->lock); 5499 r = -EEXIST; 5500 if (kvm->arch.vpit) 5501 goto create_pit_unlock; 5502 r = -ENOMEM; 5503 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 5504 if (kvm->arch.vpit) 5505 r = 0; 5506 create_pit_unlock: 5507 mutex_unlock(&kvm->lock); 5508 break; 5509 case KVM_GET_IRQCHIP: { 5510 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 5511 struct kvm_irqchip *chip; 5512 5513 chip = memdup_user(argp, sizeof(*chip)); 5514 if (IS_ERR(chip)) { 5515 r = PTR_ERR(chip); 5516 goto out; 5517 } 5518 5519 r = -ENXIO; 5520 if (!irqchip_kernel(kvm)) 5521 goto get_irqchip_out; 5522 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 5523 if (r) 5524 goto get_irqchip_out; 5525 r = -EFAULT; 5526 if (copy_to_user(argp, chip, sizeof(*chip))) 5527 goto get_irqchip_out; 5528 r = 0; 5529 get_irqchip_out: 5530 kfree(chip); 5531 break; 5532 } 5533 case KVM_SET_IRQCHIP: { 5534 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 5535 struct kvm_irqchip *chip; 5536 5537 chip = memdup_user(argp, sizeof(*chip)); 5538 if (IS_ERR(chip)) { 5539 r = PTR_ERR(chip); 5540 goto out; 5541 } 5542 5543 r = -ENXIO; 5544 if (!irqchip_kernel(kvm)) 5545 goto set_irqchip_out; 5546 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 5547 set_irqchip_out: 5548 kfree(chip); 5549 break; 5550 } 5551 case KVM_GET_PIT: { 5552 r = -EFAULT; 5553 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 5554 goto out; 5555 r = -ENXIO; 5556 if (!kvm->arch.vpit) 5557 goto out; 5558 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 5559 if (r) 5560 goto out; 5561 r = -EFAULT; 5562 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 5563 goto out; 5564 r = 0; 5565 break; 5566 } 5567 case KVM_SET_PIT: { 5568 r = -EFAULT; 5569 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 5570 goto out; 5571 mutex_lock(&kvm->lock); 5572 r = -ENXIO; 5573 if (!kvm->arch.vpit) 5574 goto set_pit_out; 5575 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 5576 set_pit_out: 5577 mutex_unlock(&kvm->lock); 5578 break; 5579 } 5580 case KVM_GET_PIT2: { 5581 r = -ENXIO; 5582 if (!kvm->arch.vpit) 5583 goto out; 5584 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 5585 if (r) 5586 goto out; 5587 r = -EFAULT; 5588 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 5589 goto out; 5590 r = 0; 5591 break; 5592 } 5593 case KVM_SET_PIT2: { 5594 r = -EFAULT; 5595 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 5596 goto out; 5597 mutex_lock(&kvm->lock); 5598 r = -ENXIO; 5599 if (!kvm->arch.vpit) 5600 goto set_pit2_out; 5601 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 5602 set_pit2_out: 5603 mutex_unlock(&kvm->lock); 5604 break; 5605 } 5606 case KVM_REINJECT_CONTROL: { 5607 struct kvm_reinject_control control; 5608 r = -EFAULT; 5609 if (copy_from_user(&control, argp, sizeof(control))) 5610 goto out; 5611 r = -ENXIO; 5612 if (!kvm->arch.vpit) 5613 goto out; 5614 r = kvm_vm_ioctl_reinject(kvm, &control); 5615 break; 5616 } 5617 case KVM_SET_BOOT_CPU_ID: 5618 r = 0; 5619 mutex_lock(&kvm->lock); 5620 if (kvm->created_vcpus) 5621 r = -EBUSY; 5622 else 5623 kvm->arch.bsp_vcpu_id = arg; 5624 mutex_unlock(&kvm->lock); 5625 break; 5626 case KVM_XEN_HVM_CONFIG: { 5627 struct kvm_xen_hvm_config xhc; 5628 r = -EFAULT; 5629 if (copy_from_user(&xhc, argp, sizeof(xhc))) 5630 goto out; 5631 r = -EINVAL; 5632 if (xhc.flags) 5633 goto out; 5634 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); 5635 r = 0; 5636 break; 5637 } 5638 case KVM_SET_CLOCK: { 5639 struct kvm_clock_data user_ns; 5640 u64 now_ns; 5641 5642 r = -EFAULT; 5643 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 5644 goto out; 5645 5646 r = -EINVAL; 5647 if (user_ns.flags) 5648 goto out; 5649 5650 r = 0; 5651 /* 5652 * TODO: userspace has to take care of races with VCPU_RUN, so 5653 * kvm_gen_update_masterclock() can be cut down to locked 5654 * pvclock_update_vm_gtod_copy(). 5655 */ 5656 kvm_gen_update_masterclock(kvm); 5657 now_ns = get_kvmclock_ns(kvm); 5658 kvm->arch.kvmclock_offset += user_ns.clock - now_ns; 5659 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); 5660 break; 5661 } 5662 case KVM_GET_CLOCK: { 5663 struct kvm_clock_data user_ns; 5664 u64 now_ns; 5665 5666 now_ns = get_kvmclock_ns(kvm); 5667 user_ns.clock = now_ns; 5668 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 5669 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 5670 5671 r = -EFAULT; 5672 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 5673 goto out; 5674 r = 0; 5675 break; 5676 } 5677 case KVM_MEMORY_ENCRYPT_OP: { 5678 r = -ENOTTY; 5679 if (kvm_x86_ops.mem_enc_op) 5680 r = kvm_x86_ops.mem_enc_op(kvm, argp); 5681 break; 5682 } 5683 case KVM_MEMORY_ENCRYPT_REG_REGION: { 5684 struct kvm_enc_region region; 5685 5686 r = -EFAULT; 5687 if (copy_from_user(®ion, argp, sizeof(region))) 5688 goto out; 5689 5690 r = -ENOTTY; 5691 if (kvm_x86_ops.mem_enc_reg_region) 5692 r = kvm_x86_ops.mem_enc_reg_region(kvm, ®ion); 5693 break; 5694 } 5695 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 5696 struct kvm_enc_region region; 5697 5698 r = -EFAULT; 5699 if (copy_from_user(®ion, argp, sizeof(region))) 5700 goto out; 5701 5702 r = -ENOTTY; 5703 if (kvm_x86_ops.mem_enc_unreg_region) 5704 r = kvm_x86_ops.mem_enc_unreg_region(kvm, ®ion); 5705 break; 5706 } 5707 case KVM_HYPERV_EVENTFD: { 5708 struct kvm_hyperv_eventfd hvevfd; 5709 5710 r = -EFAULT; 5711 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 5712 goto out; 5713 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 5714 break; 5715 } 5716 case KVM_SET_PMU_EVENT_FILTER: 5717 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); 5718 break; 5719 case KVM_X86_SET_MSR_FILTER: 5720 r = kvm_vm_ioctl_set_msr_filter(kvm, argp); 5721 break; 5722 default: 5723 r = -ENOTTY; 5724 } 5725 out: 5726 return r; 5727 } 5728 5729 static void kvm_init_msr_list(void) 5730 { 5731 struct x86_pmu_capability x86_pmu; 5732 u32 dummy[2]; 5733 unsigned i; 5734 5735 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, 5736 "Please update the fixed PMCs in msrs_to_saved_all[]"); 5737 5738 perf_get_x86_pmu_capability(&x86_pmu); 5739 5740 num_msrs_to_save = 0; 5741 num_emulated_msrs = 0; 5742 num_msr_based_features = 0; 5743 5744 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { 5745 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) 5746 continue; 5747 5748 /* 5749 * Even MSRs that are valid in the host may not be exposed 5750 * to the guests in some cases. 5751 */ 5752 switch (msrs_to_save_all[i]) { 5753 case MSR_IA32_BNDCFGS: 5754 if (!kvm_mpx_supported()) 5755 continue; 5756 break; 5757 case MSR_TSC_AUX: 5758 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) 5759 continue; 5760 break; 5761 case MSR_IA32_UMWAIT_CONTROL: 5762 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) 5763 continue; 5764 break; 5765 case MSR_IA32_RTIT_CTL: 5766 case MSR_IA32_RTIT_STATUS: 5767 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) 5768 continue; 5769 break; 5770 case MSR_IA32_RTIT_CR3_MATCH: 5771 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 5772 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 5773 continue; 5774 break; 5775 case MSR_IA32_RTIT_OUTPUT_BASE: 5776 case MSR_IA32_RTIT_OUTPUT_MASK: 5777 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 5778 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 5779 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 5780 continue; 5781 break; 5782 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 5783 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 5784 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= 5785 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 5786 continue; 5787 break; 5788 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: 5789 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= 5790 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 5791 continue; 5792 break; 5793 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: 5794 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= 5795 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 5796 continue; 5797 break; 5798 default: 5799 break; 5800 } 5801 5802 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; 5803 } 5804 5805 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { 5806 if (!kvm_x86_ops.has_emulated_msr(NULL, emulated_msrs_all[i])) 5807 continue; 5808 5809 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; 5810 } 5811 5812 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { 5813 struct kvm_msr_entry msr; 5814 5815 msr.index = msr_based_features_all[i]; 5816 if (kvm_get_msr_feature(&msr)) 5817 continue; 5818 5819 msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; 5820 } 5821 } 5822 5823 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 5824 const void *v) 5825 { 5826 int handled = 0; 5827 int n; 5828 5829 do { 5830 n = min(len, 8); 5831 if (!(lapic_in_kernel(vcpu) && 5832 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 5833 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 5834 break; 5835 handled += n; 5836 addr += n; 5837 len -= n; 5838 v += n; 5839 } while (len); 5840 5841 return handled; 5842 } 5843 5844 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 5845 { 5846 int handled = 0; 5847 int n; 5848 5849 do { 5850 n = min(len, 8); 5851 if (!(lapic_in_kernel(vcpu) && 5852 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 5853 addr, n, v)) 5854 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 5855 break; 5856 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 5857 handled += n; 5858 addr += n; 5859 len -= n; 5860 v += n; 5861 } while (len); 5862 5863 return handled; 5864 } 5865 5866 static void kvm_set_segment(struct kvm_vcpu *vcpu, 5867 struct kvm_segment *var, int seg) 5868 { 5869 kvm_x86_ops.set_segment(vcpu, var, seg); 5870 } 5871 5872 void kvm_get_segment(struct kvm_vcpu *vcpu, 5873 struct kvm_segment *var, int seg) 5874 { 5875 kvm_x86_ops.get_segment(vcpu, var, seg); 5876 } 5877 5878 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 5879 struct x86_exception *exception) 5880 { 5881 gpa_t t_gpa; 5882 5883 BUG_ON(!mmu_is_nested(vcpu)); 5884 5885 /* NPT walks are always user-walks */ 5886 access |= PFERR_USER_MASK; 5887 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); 5888 5889 return t_gpa; 5890 } 5891 5892 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 5893 struct x86_exception *exception) 5894 { 5895 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5896 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5897 } 5898 5899 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 5900 struct x86_exception *exception) 5901 { 5902 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5903 access |= PFERR_FETCH_MASK; 5904 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5905 } 5906 5907 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 5908 struct x86_exception *exception) 5909 { 5910 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5911 access |= PFERR_WRITE_MASK; 5912 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5913 } 5914 5915 /* uses this to access any guest's mapped memory without checking CPL */ 5916 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 5917 struct x86_exception *exception) 5918 { 5919 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 5920 } 5921 5922 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 5923 struct kvm_vcpu *vcpu, u32 access, 5924 struct x86_exception *exception) 5925 { 5926 void *data = val; 5927 int r = X86EMUL_CONTINUE; 5928 5929 while (bytes) { 5930 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 5931 exception); 5932 unsigned offset = addr & (PAGE_SIZE-1); 5933 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 5934 int ret; 5935 5936 if (gpa == UNMAPPED_GVA) 5937 return X86EMUL_PROPAGATE_FAULT; 5938 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 5939 offset, toread); 5940 if (ret < 0) { 5941 r = X86EMUL_IO_NEEDED; 5942 goto out; 5943 } 5944 5945 bytes -= toread; 5946 data += toread; 5947 addr += toread; 5948 } 5949 out: 5950 return r; 5951 } 5952 5953 /* used for instruction fetching */ 5954 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 5955 gva_t addr, void *val, unsigned int bytes, 5956 struct x86_exception *exception) 5957 { 5958 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5959 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5960 unsigned offset; 5961 int ret; 5962 5963 /* Inline kvm_read_guest_virt_helper for speed. */ 5964 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 5965 exception); 5966 if (unlikely(gpa == UNMAPPED_GVA)) 5967 return X86EMUL_PROPAGATE_FAULT; 5968 5969 offset = addr & (PAGE_SIZE-1); 5970 if (WARN_ON(offset + bytes > PAGE_SIZE)) 5971 bytes = (unsigned)PAGE_SIZE - offset; 5972 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 5973 offset, bytes); 5974 if (unlikely(ret < 0)) 5975 return X86EMUL_IO_NEEDED; 5976 5977 return X86EMUL_CONTINUE; 5978 } 5979 5980 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 5981 gva_t addr, void *val, unsigned int bytes, 5982 struct x86_exception *exception) 5983 { 5984 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5985 5986 /* 5987 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 5988 * is returned, but our callers are not ready for that and they blindly 5989 * call kvm_inject_page_fault. Ensure that they at least do not leak 5990 * uninitialized kernel stack memory into cr2 and error code. 5991 */ 5992 memset(exception, 0, sizeof(*exception)); 5993 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 5994 exception); 5995 } 5996 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 5997 5998 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 5999 gva_t addr, void *val, unsigned int bytes, 6000 struct x86_exception *exception, bool system) 6001 { 6002 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6003 u32 access = 0; 6004 6005 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3) 6006 access |= PFERR_USER_MASK; 6007 6008 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 6009 } 6010 6011 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 6012 unsigned long addr, void *val, unsigned int bytes) 6013 { 6014 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6015 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 6016 6017 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 6018 } 6019 6020 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6021 struct kvm_vcpu *vcpu, u32 access, 6022 struct x86_exception *exception) 6023 { 6024 void *data = val; 6025 int r = X86EMUL_CONTINUE; 6026 6027 while (bytes) { 6028 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 6029 access, 6030 exception); 6031 unsigned offset = addr & (PAGE_SIZE-1); 6032 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 6033 int ret; 6034 6035 if (gpa == UNMAPPED_GVA) 6036 return X86EMUL_PROPAGATE_FAULT; 6037 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 6038 if (ret < 0) { 6039 r = X86EMUL_IO_NEEDED; 6040 goto out; 6041 } 6042 6043 bytes -= towrite; 6044 data += towrite; 6045 addr += towrite; 6046 } 6047 out: 6048 return r; 6049 } 6050 6051 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 6052 unsigned int bytes, struct x86_exception *exception, 6053 bool system) 6054 { 6055 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6056 u32 access = PFERR_WRITE_MASK; 6057 6058 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3) 6059 access |= PFERR_USER_MASK; 6060 6061 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6062 access, exception); 6063 } 6064 6065 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 6066 unsigned int bytes, struct x86_exception *exception) 6067 { 6068 /* kvm_write_guest_virt_system can pull in tons of pages. */ 6069 vcpu->arch.l1tf_flush_l1d = true; 6070 6071 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6072 PFERR_WRITE_MASK, exception); 6073 } 6074 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 6075 6076 int handle_ud(struct kvm_vcpu *vcpu) 6077 { 6078 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; 6079 int emul_type = EMULTYPE_TRAP_UD; 6080 char sig[5]; /* ud2; .ascii "kvm" */ 6081 struct x86_exception e; 6082 6083 if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, NULL, 0))) 6084 return 1; 6085 6086 if (force_emulation_prefix && 6087 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 6088 sig, sizeof(sig), &e) == 0 && 6089 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { 6090 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 6091 emul_type = EMULTYPE_TRAP_UD_FORCED; 6092 } 6093 6094 return kvm_emulate_instruction(vcpu, emul_type); 6095 } 6096 EXPORT_SYMBOL_GPL(handle_ud); 6097 6098 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6099 gpa_t gpa, bool write) 6100 { 6101 /* For APIC access vmexit */ 6102 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 6103 return 1; 6104 6105 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 6106 trace_vcpu_match_mmio(gva, gpa, write, true); 6107 return 1; 6108 } 6109 6110 return 0; 6111 } 6112 6113 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6114 gpa_t *gpa, struct x86_exception *exception, 6115 bool write) 6116 { 6117 u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 6118 | (write ? PFERR_WRITE_MASK : 0); 6119 6120 /* 6121 * currently PKRU is only applied to ept enabled guest so 6122 * there is no pkey in EPT page table for L1 guest or EPT 6123 * shadow page table for L2 guest. 6124 */ 6125 if (vcpu_match_mmio_gva(vcpu, gva) 6126 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 6127 vcpu->arch.mmio_access, 0, access)) { 6128 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 6129 (gva & (PAGE_SIZE - 1)); 6130 trace_vcpu_match_mmio(gva, *gpa, write, false); 6131 return 1; 6132 } 6133 6134 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6135 6136 if (*gpa == UNMAPPED_GVA) 6137 return -1; 6138 6139 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 6140 } 6141 6142 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 6143 const void *val, int bytes) 6144 { 6145 int ret; 6146 6147 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 6148 if (ret < 0) 6149 return 0; 6150 kvm_page_track_write(vcpu, gpa, val, bytes); 6151 return 1; 6152 } 6153 6154 struct read_write_emulator_ops { 6155 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 6156 int bytes); 6157 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 6158 void *val, int bytes); 6159 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6160 int bytes, void *val); 6161 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6162 void *val, int bytes); 6163 bool write; 6164 }; 6165 6166 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 6167 { 6168 if (vcpu->mmio_read_completed) { 6169 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 6170 vcpu->mmio_fragments[0].gpa, val); 6171 vcpu->mmio_read_completed = 0; 6172 return 1; 6173 } 6174 6175 return 0; 6176 } 6177 6178 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6179 void *val, int bytes) 6180 { 6181 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 6182 } 6183 6184 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6185 void *val, int bytes) 6186 { 6187 return emulator_write_phys(vcpu, gpa, val, bytes); 6188 } 6189 6190 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 6191 { 6192 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 6193 return vcpu_mmio_write(vcpu, gpa, bytes, val); 6194 } 6195 6196 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6197 void *val, int bytes) 6198 { 6199 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 6200 return X86EMUL_IO_NEEDED; 6201 } 6202 6203 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6204 void *val, int bytes) 6205 { 6206 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 6207 6208 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 6209 return X86EMUL_CONTINUE; 6210 } 6211 6212 static const struct read_write_emulator_ops read_emultor = { 6213 .read_write_prepare = read_prepare, 6214 .read_write_emulate = read_emulate, 6215 .read_write_mmio = vcpu_mmio_read, 6216 .read_write_exit_mmio = read_exit_mmio, 6217 }; 6218 6219 static const struct read_write_emulator_ops write_emultor = { 6220 .read_write_emulate = write_emulate, 6221 .read_write_mmio = write_mmio, 6222 .read_write_exit_mmio = write_exit_mmio, 6223 .write = true, 6224 }; 6225 6226 static int emulator_read_write_onepage(unsigned long addr, void *val, 6227 unsigned int bytes, 6228 struct x86_exception *exception, 6229 struct kvm_vcpu *vcpu, 6230 const struct read_write_emulator_ops *ops) 6231 { 6232 gpa_t gpa; 6233 int handled, ret; 6234 bool write = ops->write; 6235 struct kvm_mmio_fragment *frag; 6236 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6237 6238 /* 6239 * If the exit was due to a NPF we may already have a GPA. 6240 * If the GPA is present, use it to avoid the GVA to GPA table walk. 6241 * Note, this cannot be used on string operations since string 6242 * operation using rep will only have the initial GPA from the NPF 6243 * occurred. 6244 */ 6245 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && 6246 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { 6247 gpa = ctxt->gpa_val; 6248 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 6249 } else { 6250 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 6251 if (ret < 0) 6252 return X86EMUL_PROPAGATE_FAULT; 6253 } 6254 6255 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 6256 return X86EMUL_CONTINUE; 6257 6258 /* 6259 * Is this MMIO handled locally? 6260 */ 6261 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 6262 if (handled == bytes) 6263 return X86EMUL_CONTINUE; 6264 6265 gpa += handled; 6266 bytes -= handled; 6267 val += handled; 6268 6269 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 6270 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 6271 frag->gpa = gpa; 6272 frag->data = val; 6273 frag->len = bytes; 6274 return X86EMUL_CONTINUE; 6275 } 6276 6277 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 6278 unsigned long addr, 6279 void *val, unsigned int bytes, 6280 struct x86_exception *exception, 6281 const struct read_write_emulator_ops *ops) 6282 { 6283 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6284 gpa_t gpa; 6285 int rc; 6286 6287 if (ops->read_write_prepare && 6288 ops->read_write_prepare(vcpu, val, bytes)) 6289 return X86EMUL_CONTINUE; 6290 6291 vcpu->mmio_nr_fragments = 0; 6292 6293 /* Crossing a page boundary? */ 6294 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 6295 int now; 6296 6297 now = -addr & ~PAGE_MASK; 6298 rc = emulator_read_write_onepage(addr, val, now, exception, 6299 vcpu, ops); 6300 6301 if (rc != X86EMUL_CONTINUE) 6302 return rc; 6303 addr += now; 6304 if (ctxt->mode != X86EMUL_MODE_PROT64) 6305 addr = (u32)addr; 6306 val += now; 6307 bytes -= now; 6308 } 6309 6310 rc = emulator_read_write_onepage(addr, val, bytes, exception, 6311 vcpu, ops); 6312 if (rc != X86EMUL_CONTINUE) 6313 return rc; 6314 6315 if (!vcpu->mmio_nr_fragments) 6316 return rc; 6317 6318 gpa = vcpu->mmio_fragments[0].gpa; 6319 6320 vcpu->mmio_needed = 1; 6321 vcpu->mmio_cur_fragment = 0; 6322 6323 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 6324 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 6325 vcpu->run->exit_reason = KVM_EXIT_MMIO; 6326 vcpu->run->mmio.phys_addr = gpa; 6327 6328 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 6329 } 6330 6331 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 6332 unsigned long addr, 6333 void *val, 6334 unsigned int bytes, 6335 struct x86_exception *exception) 6336 { 6337 return emulator_read_write(ctxt, addr, val, bytes, 6338 exception, &read_emultor); 6339 } 6340 6341 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 6342 unsigned long addr, 6343 const void *val, 6344 unsigned int bytes, 6345 struct x86_exception *exception) 6346 { 6347 return emulator_read_write(ctxt, addr, (void *)val, bytes, 6348 exception, &write_emultor); 6349 } 6350 6351 #define CMPXCHG_TYPE(t, ptr, old, new) \ 6352 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 6353 6354 #ifdef CONFIG_X86_64 6355 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 6356 #else 6357 # define CMPXCHG64(ptr, old, new) \ 6358 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 6359 #endif 6360 6361 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 6362 unsigned long addr, 6363 const void *old, 6364 const void *new, 6365 unsigned int bytes, 6366 struct x86_exception *exception) 6367 { 6368 struct kvm_host_map map; 6369 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6370 u64 page_line_mask; 6371 gpa_t gpa; 6372 char *kaddr; 6373 bool exchanged; 6374 6375 /* guests cmpxchg8b have to be emulated atomically */ 6376 if (bytes > 8 || (bytes & (bytes - 1))) 6377 goto emul_write; 6378 6379 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 6380 6381 if (gpa == UNMAPPED_GVA || 6382 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 6383 goto emul_write; 6384 6385 /* 6386 * Emulate the atomic as a straight write to avoid #AC if SLD is 6387 * enabled in the host and the access splits a cache line. 6388 */ 6389 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 6390 page_line_mask = ~(cache_line_size() - 1); 6391 else 6392 page_line_mask = PAGE_MASK; 6393 6394 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) 6395 goto emul_write; 6396 6397 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) 6398 goto emul_write; 6399 6400 kaddr = map.hva + offset_in_page(gpa); 6401 6402 switch (bytes) { 6403 case 1: 6404 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 6405 break; 6406 case 2: 6407 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 6408 break; 6409 case 4: 6410 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 6411 break; 6412 case 8: 6413 exchanged = CMPXCHG64(kaddr, old, new); 6414 break; 6415 default: 6416 BUG(); 6417 } 6418 6419 kvm_vcpu_unmap(vcpu, &map, true); 6420 6421 if (!exchanged) 6422 return X86EMUL_CMPXCHG_FAILED; 6423 6424 kvm_page_track_write(vcpu, gpa, new, bytes); 6425 6426 return X86EMUL_CONTINUE; 6427 6428 emul_write: 6429 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 6430 6431 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 6432 } 6433 6434 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 6435 { 6436 int r = 0, i; 6437 6438 for (i = 0; i < vcpu->arch.pio.count; i++) { 6439 if (vcpu->arch.pio.in) 6440 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 6441 vcpu->arch.pio.size, pd); 6442 else 6443 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 6444 vcpu->arch.pio.port, vcpu->arch.pio.size, 6445 pd); 6446 if (r) 6447 break; 6448 pd += vcpu->arch.pio.size; 6449 } 6450 return r; 6451 } 6452 6453 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 6454 unsigned short port, void *val, 6455 unsigned int count, bool in) 6456 { 6457 vcpu->arch.pio.port = port; 6458 vcpu->arch.pio.in = in; 6459 vcpu->arch.pio.count = count; 6460 vcpu->arch.pio.size = size; 6461 6462 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 6463 vcpu->arch.pio.count = 0; 6464 return 1; 6465 } 6466 6467 vcpu->run->exit_reason = KVM_EXIT_IO; 6468 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 6469 vcpu->run->io.size = size; 6470 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 6471 vcpu->run->io.count = count; 6472 vcpu->run->io.port = port; 6473 6474 return 0; 6475 } 6476 6477 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, 6478 unsigned short port, void *val, unsigned int count) 6479 { 6480 int ret; 6481 6482 if (vcpu->arch.pio.count) 6483 goto data_avail; 6484 6485 memset(vcpu->arch.pio_data, 0, size * count); 6486 6487 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 6488 if (ret) { 6489 data_avail: 6490 memcpy(val, vcpu->arch.pio_data, size * count); 6491 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 6492 vcpu->arch.pio.count = 0; 6493 return 1; 6494 } 6495 6496 return 0; 6497 } 6498 6499 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 6500 int size, unsigned short port, void *val, 6501 unsigned int count) 6502 { 6503 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); 6504 6505 } 6506 6507 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, 6508 unsigned short port, const void *val, 6509 unsigned int count) 6510 { 6511 memcpy(vcpu->arch.pio_data, val, size * count); 6512 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 6513 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 6514 } 6515 6516 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 6517 int size, unsigned short port, 6518 const void *val, unsigned int count) 6519 { 6520 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); 6521 } 6522 6523 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 6524 { 6525 return kvm_x86_ops.get_segment_base(vcpu, seg); 6526 } 6527 6528 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 6529 { 6530 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 6531 } 6532 6533 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 6534 { 6535 if (!need_emulate_wbinvd(vcpu)) 6536 return X86EMUL_CONTINUE; 6537 6538 if (kvm_x86_ops.has_wbinvd_exit()) { 6539 int cpu = get_cpu(); 6540 6541 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 6542 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 6543 wbinvd_ipi, NULL, 1); 6544 put_cpu(); 6545 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 6546 } else 6547 wbinvd(); 6548 return X86EMUL_CONTINUE; 6549 } 6550 6551 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 6552 { 6553 kvm_emulate_wbinvd_noskip(vcpu); 6554 return kvm_skip_emulated_instruction(vcpu); 6555 } 6556 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 6557 6558 6559 6560 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 6561 { 6562 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 6563 } 6564 6565 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 6566 unsigned long *dest) 6567 { 6568 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 6569 } 6570 6571 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 6572 unsigned long value) 6573 { 6574 6575 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 6576 } 6577 6578 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 6579 { 6580 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 6581 } 6582 6583 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 6584 { 6585 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6586 unsigned long value; 6587 6588 switch (cr) { 6589 case 0: 6590 value = kvm_read_cr0(vcpu); 6591 break; 6592 case 2: 6593 value = vcpu->arch.cr2; 6594 break; 6595 case 3: 6596 value = kvm_read_cr3(vcpu); 6597 break; 6598 case 4: 6599 value = kvm_read_cr4(vcpu); 6600 break; 6601 case 8: 6602 value = kvm_get_cr8(vcpu); 6603 break; 6604 default: 6605 kvm_err("%s: unexpected cr %u\n", __func__, cr); 6606 return 0; 6607 } 6608 6609 return value; 6610 } 6611 6612 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 6613 { 6614 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6615 int res = 0; 6616 6617 switch (cr) { 6618 case 0: 6619 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 6620 break; 6621 case 2: 6622 vcpu->arch.cr2 = val; 6623 break; 6624 case 3: 6625 res = kvm_set_cr3(vcpu, val); 6626 break; 6627 case 4: 6628 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 6629 break; 6630 case 8: 6631 res = kvm_set_cr8(vcpu, val); 6632 break; 6633 default: 6634 kvm_err("%s: unexpected cr %u\n", __func__, cr); 6635 res = -1; 6636 } 6637 6638 return res; 6639 } 6640 6641 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 6642 { 6643 return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt)); 6644 } 6645 6646 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6647 { 6648 kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt); 6649 } 6650 6651 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6652 { 6653 kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt); 6654 } 6655 6656 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6657 { 6658 kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt); 6659 } 6660 6661 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6662 { 6663 kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt); 6664 } 6665 6666 static unsigned long emulator_get_cached_segment_base( 6667 struct x86_emulate_ctxt *ctxt, int seg) 6668 { 6669 return get_segment_base(emul_to_vcpu(ctxt), seg); 6670 } 6671 6672 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 6673 struct desc_struct *desc, u32 *base3, 6674 int seg) 6675 { 6676 struct kvm_segment var; 6677 6678 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 6679 *selector = var.selector; 6680 6681 if (var.unusable) { 6682 memset(desc, 0, sizeof(*desc)); 6683 if (base3) 6684 *base3 = 0; 6685 return false; 6686 } 6687 6688 if (var.g) 6689 var.limit >>= 12; 6690 set_desc_limit(desc, var.limit); 6691 set_desc_base(desc, (unsigned long)var.base); 6692 #ifdef CONFIG_X86_64 6693 if (base3) 6694 *base3 = var.base >> 32; 6695 #endif 6696 desc->type = var.type; 6697 desc->s = var.s; 6698 desc->dpl = var.dpl; 6699 desc->p = var.present; 6700 desc->avl = var.avl; 6701 desc->l = var.l; 6702 desc->d = var.db; 6703 desc->g = var.g; 6704 6705 return true; 6706 } 6707 6708 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 6709 struct desc_struct *desc, u32 base3, 6710 int seg) 6711 { 6712 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6713 struct kvm_segment var; 6714 6715 var.selector = selector; 6716 var.base = get_desc_base(desc); 6717 #ifdef CONFIG_X86_64 6718 var.base |= ((u64)base3) << 32; 6719 #endif 6720 var.limit = get_desc_limit(desc); 6721 if (desc->g) 6722 var.limit = (var.limit << 12) | 0xfff; 6723 var.type = desc->type; 6724 var.dpl = desc->dpl; 6725 var.db = desc->d; 6726 var.s = desc->s; 6727 var.l = desc->l; 6728 var.g = desc->g; 6729 var.avl = desc->avl; 6730 var.present = desc->p; 6731 var.unusable = !var.present; 6732 var.padding = 0; 6733 6734 kvm_set_segment(vcpu, &var, seg); 6735 return; 6736 } 6737 6738 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 6739 u32 msr_index, u64 *pdata) 6740 { 6741 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6742 int r; 6743 6744 r = kvm_get_msr(vcpu, msr_index, pdata); 6745 6746 if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) { 6747 /* Bounce to user space */ 6748 return X86EMUL_IO_NEEDED; 6749 } 6750 6751 return r; 6752 } 6753 6754 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 6755 u32 msr_index, u64 data) 6756 { 6757 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6758 int r; 6759 6760 r = kvm_set_msr(vcpu, msr_index, data); 6761 6762 if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) { 6763 /* Bounce to user space */ 6764 return X86EMUL_IO_NEEDED; 6765 } 6766 6767 return r; 6768 } 6769 6770 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 6771 { 6772 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6773 6774 return vcpu->arch.smbase; 6775 } 6776 6777 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 6778 { 6779 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6780 6781 vcpu->arch.smbase = smbase; 6782 } 6783 6784 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 6785 u32 pmc) 6786 { 6787 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); 6788 } 6789 6790 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 6791 u32 pmc, u64 *pdata) 6792 { 6793 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 6794 } 6795 6796 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 6797 { 6798 emul_to_vcpu(ctxt)->arch.halt_request = 1; 6799 } 6800 6801 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 6802 struct x86_instruction_info *info, 6803 enum x86_intercept_stage stage) 6804 { 6805 return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage, 6806 &ctxt->exception); 6807 } 6808 6809 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 6810 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, 6811 bool exact_only) 6812 { 6813 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); 6814 } 6815 6816 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) 6817 { 6818 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); 6819 } 6820 6821 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) 6822 { 6823 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); 6824 } 6825 6826 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) 6827 { 6828 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); 6829 } 6830 6831 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 6832 { 6833 return kvm_register_read(emul_to_vcpu(ctxt), reg); 6834 } 6835 6836 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 6837 { 6838 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 6839 } 6840 6841 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 6842 { 6843 kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked); 6844 } 6845 6846 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 6847 { 6848 return emul_to_vcpu(ctxt)->arch.hflags; 6849 } 6850 6851 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) 6852 { 6853 emul_to_vcpu(ctxt)->arch.hflags = emul_flags; 6854 } 6855 6856 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, 6857 const char *smstate) 6858 { 6859 return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate); 6860 } 6861 6862 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) 6863 { 6864 kvm_smm_changed(emul_to_vcpu(ctxt)); 6865 } 6866 6867 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) 6868 { 6869 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); 6870 } 6871 6872 static const struct x86_emulate_ops emulate_ops = { 6873 .read_gpr = emulator_read_gpr, 6874 .write_gpr = emulator_write_gpr, 6875 .read_std = emulator_read_std, 6876 .write_std = emulator_write_std, 6877 .read_phys = kvm_read_guest_phys_system, 6878 .fetch = kvm_fetch_guest_virt, 6879 .read_emulated = emulator_read_emulated, 6880 .write_emulated = emulator_write_emulated, 6881 .cmpxchg_emulated = emulator_cmpxchg_emulated, 6882 .invlpg = emulator_invlpg, 6883 .pio_in_emulated = emulator_pio_in_emulated, 6884 .pio_out_emulated = emulator_pio_out_emulated, 6885 .get_segment = emulator_get_segment, 6886 .set_segment = emulator_set_segment, 6887 .get_cached_segment_base = emulator_get_cached_segment_base, 6888 .get_gdt = emulator_get_gdt, 6889 .get_idt = emulator_get_idt, 6890 .set_gdt = emulator_set_gdt, 6891 .set_idt = emulator_set_idt, 6892 .get_cr = emulator_get_cr, 6893 .set_cr = emulator_set_cr, 6894 .cpl = emulator_get_cpl, 6895 .get_dr = emulator_get_dr, 6896 .set_dr = emulator_set_dr, 6897 .get_smbase = emulator_get_smbase, 6898 .set_smbase = emulator_set_smbase, 6899 .set_msr = emulator_set_msr, 6900 .get_msr = emulator_get_msr, 6901 .check_pmc = emulator_check_pmc, 6902 .read_pmc = emulator_read_pmc, 6903 .halt = emulator_halt, 6904 .wbinvd = emulator_wbinvd, 6905 .fix_hypercall = emulator_fix_hypercall, 6906 .intercept = emulator_intercept, 6907 .get_cpuid = emulator_get_cpuid, 6908 .guest_has_long_mode = emulator_guest_has_long_mode, 6909 .guest_has_movbe = emulator_guest_has_movbe, 6910 .guest_has_fxsr = emulator_guest_has_fxsr, 6911 .set_nmi_mask = emulator_set_nmi_mask, 6912 .get_hflags = emulator_get_hflags, 6913 .set_hflags = emulator_set_hflags, 6914 .pre_leave_smm = emulator_pre_leave_smm, 6915 .post_leave_smm = emulator_post_leave_smm, 6916 .set_xcr = emulator_set_xcr, 6917 }; 6918 6919 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 6920 { 6921 u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu); 6922 /* 6923 * an sti; sti; sequence only disable interrupts for the first 6924 * instruction. So, if the last instruction, be it emulated or 6925 * not, left the system with the INT_STI flag enabled, it 6926 * means that the last instruction is an sti. We should not 6927 * leave the flag on in this case. The same goes for mov ss 6928 */ 6929 if (int_shadow & mask) 6930 mask = 0; 6931 if (unlikely(int_shadow || mask)) { 6932 kvm_x86_ops.set_interrupt_shadow(vcpu, mask); 6933 if (!mask) 6934 kvm_make_request(KVM_REQ_EVENT, vcpu); 6935 } 6936 } 6937 6938 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 6939 { 6940 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6941 if (ctxt->exception.vector == PF_VECTOR) 6942 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); 6943 6944 if (ctxt->exception.error_code_valid) 6945 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 6946 ctxt->exception.error_code); 6947 else 6948 kvm_queue_exception(vcpu, ctxt->exception.vector); 6949 return false; 6950 } 6951 6952 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) 6953 { 6954 struct x86_emulate_ctxt *ctxt; 6955 6956 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); 6957 if (!ctxt) { 6958 pr_err("kvm: failed to allocate vcpu's emulator\n"); 6959 return NULL; 6960 } 6961 6962 ctxt->vcpu = vcpu; 6963 ctxt->ops = &emulate_ops; 6964 vcpu->arch.emulate_ctxt = ctxt; 6965 6966 return ctxt; 6967 } 6968 6969 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 6970 { 6971 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6972 int cs_db, cs_l; 6973 6974 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 6975 6976 ctxt->gpa_available = false; 6977 ctxt->eflags = kvm_get_rflags(vcpu); 6978 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 6979 6980 ctxt->eip = kvm_rip_read(vcpu); 6981 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 6982 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 6983 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 6984 cs_db ? X86EMUL_MODE_PROT32 : 6985 X86EMUL_MODE_PROT16; 6986 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 6987 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 6988 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 6989 6990 init_decode_cache(ctxt); 6991 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 6992 } 6993 6994 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 6995 { 6996 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6997 int ret; 6998 6999 init_emulate_ctxt(vcpu); 7000 7001 ctxt->op_bytes = 2; 7002 ctxt->ad_bytes = 2; 7003 ctxt->_eip = ctxt->eip + inc_eip; 7004 ret = emulate_int_real(ctxt, irq); 7005 7006 if (ret != X86EMUL_CONTINUE) { 7007 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 7008 } else { 7009 ctxt->eip = ctxt->_eip; 7010 kvm_rip_write(vcpu, ctxt->eip); 7011 kvm_set_rflags(vcpu, ctxt->eflags); 7012 } 7013 } 7014 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 7015 7016 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 7017 { 7018 ++vcpu->stat.insn_emulation_fail; 7019 trace_kvm_emulate_insn_failed(vcpu); 7020 7021 if (emulation_type & EMULTYPE_VMWARE_GP) { 7022 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 7023 return 1; 7024 } 7025 7026 if (emulation_type & EMULTYPE_SKIP) { 7027 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 7028 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 7029 vcpu->run->internal.ndata = 0; 7030 return 0; 7031 } 7032 7033 kvm_queue_exception(vcpu, UD_VECTOR); 7034 7035 if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) { 7036 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 7037 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 7038 vcpu->run->internal.ndata = 0; 7039 return 0; 7040 } 7041 7042 return 1; 7043 } 7044 7045 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 7046 bool write_fault_to_shadow_pgtable, 7047 int emulation_type) 7048 { 7049 gpa_t gpa = cr2_or_gpa; 7050 kvm_pfn_t pfn; 7051 7052 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7053 return false; 7054 7055 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7056 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7057 return false; 7058 7059 if (!vcpu->arch.mmu->direct_map) { 7060 /* 7061 * Write permission should be allowed since only 7062 * write access need to be emulated. 7063 */ 7064 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 7065 7066 /* 7067 * If the mapping is invalid in guest, let cpu retry 7068 * it to generate fault. 7069 */ 7070 if (gpa == UNMAPPED_GVA) 7071 return true; 7072 } 7073 7074 /* 7075 * Do not retry the unhandleable instruction if it faults on the 7076 * readonly host memory, otherwise it will goto a infinite loop: 7077 * retry instruction -> write #PF -> emulation fail -> retry 7078 * instruction -> ... 7079 */ 7080 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 7081 7082 /* 7083 * If the instruction failed on the error pfn, it can not be fixed, 7084 * report the error to userspace. 7085 */ 7086 if (is_error_noslot_pfn(pfn)) 7087 return false; 7088 7089 kvm_release_pfn_clean(pfn); 7090 7091 /* The instructions are well-emulated on direct mmu. */ 7092 if (vcpu->arch.mmu->direct_map) { 7093 unsigned int indirect_shadow_pages; 7094 7095 spin_lock(&vcpu->kvm->mmu_lock); 7096 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 7097 spin_unlock(&vcpu->kvm->mmu_lock); 7098 7099 if (indirect_shadow_pages) 7100 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7101 7102 return true; 7103 } 7104 7105 /* 7106 * if emulation was due to access to shadowed page table 7107 * and it failed try to unshadow page and re-enter the 7108 * guest to let CPU execute the instruction. 7109 */ 7110 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7111 7112 /* 7113 * If the access faults on its page table, it can not 7114 * be fixed by unprotecting shadow page and it should 7115 * be reported to userspace. 7116 */ 7117 return !write_fault_to_shadow_pgtable; 7118 } 7119 7120 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 7121 gpa_t cr2_or_gpa, int emulation_type) 7122 { 7123 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7124 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; 7125 7126 last_retry_eip = vcpu->arch.last_retry_eip; 7127 last_retry_addr = vcpu->arch.last_retry_addr; 7128 7129 /* 7130 * If the emulation is caused by #PF and it is non-page_table 7131 * writing instruction, it means the VM-EXIT is caused by shadow 7132 * page protected, we can zap the shadow page and retry this 7133 * instruction directly. 7134 * 7135 * Note: if the guest uses a non-page-table modifying instruction 7136 * on the PDE that points to the instruction, then we will unmap 7137 * the instruction and go to an infinite loop. So, we cache the 7138 * last retried eip and the last fault address, if we meet the eip 7139 * and the address again, we can break out of the potential infinite 7140 * loop. 7141 */ 7142 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 7143 7144 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7145 return false; 7146 7147 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7148 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7149 return false; 7150 7151 if (x86_page_table_writing_insn(ctxt)) 7152 return false; 7153 7154 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) 7155 return false; 7156 7157 vcpu->arch.last_retry_eip = ctxt->eip; 7158 vcpu->arch.last_retry_addr = cr2_or_gpa; 7159 7160 if (!vcpu->arch.mmu->direct_map) 7161 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 7162 7163 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7164 7165 return true; 7166 } 7167 7168 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 7169 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 7170 7171 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 7172 { 7173 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 7174 /* This is a good place to trace that we are exiting SMM. */ 7175 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 7176 7177 /* Process a latched INIT or SMI, if any. */ 7178 kvm_make_request(KVM_REQ_EVENT, vcpu); 7179 } 7180 7181 kvm_mmu_reset_context(vcpu); 7182 } 7183 7184 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 7185 unsigned long *db) 7186 { 7187 u32 dr6 = 0; 7188 int i; 7189 u32 enable, rwlen; 7190 7191 enable = dr7; 7192 rwlen = dr7 >> 16; 7193 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 7194 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 7195 dr6 |= (1 << i); 7196 return dr6; 7197 } 7198 7199 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) 7200 { 7201 struct kvm_run *kvm_run = vcpu->run; 7202 7203 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 7204 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; 7205 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); 7206 kvm_run->debug.arch.exception = DB_VECTOR; 7207 kvm_run->exit_reason = KVM_EXIT_DEBUG; 7208 return 0; 7209 } 7210 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 7211 return 1; 7212 } 7213 7214 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 7215 { 7216 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu); 7217 int r; 7218 7219 r = kvm_x86_ops.skip_emulated_instruction(vcpu); 7220 if (unlikely(!r)) 7221 return 0; 7222 7223 /* 7224 * rflags is the old, "raw" value of the flags. The new value has 7225 * not been saved yet. 7226 * 7227 * This is correct even for TF set by the guest, because "the 7228 * processor will not generate this exception after the instruction 7229 * that sets the TF flag". 7230 */ 7231 if (unlikely(rflags & X86_EFLAGS_TF)) 7232 r = kvm_vcpu_do_singlestep(vcpu); 7233 return r; 7234 } 7235 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 7236 7237 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 7238 { 7239 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 7240 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 7241 struct kvm_run *kvm_run = vcpu->run; 7242 unsigned long eip = kvm_get_linear_rip(vcpu); 7243 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 7244 vcpu->arch.guest_debug_dr7, 7245 vcpu->arch.eff_db); 7246 7247 if (dr6 != 0) { 7248 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 7249 kvm_run->debug.arch.pc = eip; 7250 kvm_run->debug.arch.exception = DB_VECTOR; 7251 kvm_run->exit_reason = KVM_EXIT_DEBUG; 7252 *r = 0; 7253 return true; 7254 } 7255 } 7256 7257 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 7258 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 7259 unsigned long eip = kvm_get_linear_rip(vcpu); 7260 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 7261 vcpu->arch.dr7, 7262 vcpu->arch.db); 7263 7264 if (dr6 != 0) { 7265 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); 7266 *r = 1; 7267 return true; 7268 } 7269 } 7270 7271 return false; 7272 } 7273 7274 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 7275 { 7276 switch (ctxt->opcode_len) { 7277 case 1: 7278 switch (ctxt->b) { 7279 case 0xe4: /* IN */ 7280 case 0xe5: 7281 case 0xec: 7282 case 0xed: 7283 case 0xe6: /* OUT */ 7284 case 0xe7: 7285 case 0xee: 7286 case 0xef: 7287 case 0x6c: /* INS */ 7288 case 0x6d: 7289 case 0x6e: /* OUTS */ 7290 case 0x6f: 7291 return true; 7292 } 7293 break; 7294 case 2: 7295 switch (ctxt->b) { 7296 case 0x33: /* RDPMC */ 7297 return true; 7298 } 7299 break; 7300 } 7301 7302 return false; 7303 } 7304 7305 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 7306 int emulation_type, void *insn, int insn_len) 7307 { 7308 int r; 7309 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7310 bool writeback = true; 7311 bool write_fault_to_spt; 7312 7313 if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, insn, insn_len))) 7314 return 1; 7315 7316 vcpu->arch.l1tf_flush_l1d = true; 7317 7318 /* 7319 * Clear write_fault_to_shadow_pgtable here to ensure it is 7320 * never reused. 7321 */ 7322 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 7323 vcpu->arch.write_fault_to_shadow_pgtable = false; 7324 kvm_clear_exception_queue(vcpu); 7325 7326 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 7327 init_emulate_ctxt(vcpu); 7328 7329 /* 7330 * We will reenter on the same instruction since 7331 * we do not set complete_userspace_io. This does not 7332 * handle watchpoints yet, those would be handled in 7333 * the emulate_ops. 7334 */ 7335 if (!(emulation_type & EMULTYPE_SKIP) && 7336 kvm_vcpu_check_breakpoint(vcpu, &r)) 7337 return r; 7338 7339 ctxt->interruptibility = 0; 7340 ctxt->have_exception = false; 7341 ctxt->exception.vector = -1; 7342 ctxt->perm_ok = false; 7343 7344 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 7345 7346 r = x86_decode_insn(ctxt, insn, insn_len); 7347 7348 trace_kvm_emulate_insn_start(vcpu); 7349 ++vcpu->stat.insn_emulation; 7350 if (r != EMULATION_OK) { 7351 if ((emulation_type & EMULTYPE_TRAP_UD) || 7352 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { 7353 kvm_queue_exception(vcpu, UD_VECTOR); 7354 return 1; 7355 } 7356 if (reexecute_instruction(vcpu, cr2_or_gpa, 7357 write_fault_to_spt, 7358 emulation_type)) 7359 return 1; 7360 if (ctxt->have_exception) { 7361 /* 7362 * #UD should result in just EMULATION_FAILED, and trap-like 7363 * exception should not be encountered during decode. 7364 */ 7365 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || 7366 exception_type(ctxt->exception.vector) == EXCPT_TRAP); 7367 inject_emulated_exception(vcpu); 7368 return 1; 7369 } 7370 return handle_emulation_failure(vcpu, emulation_type); 7371 } 7372 } 7373 7374 if ((emulation_type & EMULTYPE_VMWARE_GP) && 7375 !is_vmware_backdoor_opcode(ctxt)) { 7376 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 7377 return 1; 7378 } 7379 7380 /* 7381 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks 7382 * for kvm_skip_emulated_instruction(). The caller is responsible for 7383 * updating interruptibility state and injecting single-step #DBs. 7384 */ 7385 if (emulation_type & EMULTYPE_SKIP) { 7386 kvm_rip_write(vcpu, ctxt->_eip); 7387 if (ctxt->eflags & X86_EFLAGS_RF) 7388 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 7389 return 1; 7390 } 7391 7392 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) 7393 return 1; 7394 7395 /* this is needed for vmware backdoor interface to work since it 7396 changes registers values during IO operation */ 7397 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 7398 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 7399 emulator_invalidate_register_cache(ctxt); 7400 } 7401 7402 restart: 7403 if (emulation_type & EMULTYPE_PF) { 7404 /* Save the faulting GPA (cr2) in the address field */ 7405 ctxt->exception.address = cr2_or_gpa; 7406 7407 /* With shadow page tables, cr2 contains a GVA or nGPA. */ 7408 if (vcpu->arch.mmu->direct_map) { 7409 ctxt->gpa_available = true; 7410 ctxt->gpa_val = cr2_or_gpa; 7411 } 7412 } else { 7413 /* Sanitize the address out of an abundance of paranoia. */ 7414 ctxt->exception.address = 0; 7415 } 7416 7417 r = x86_emulate_insn(ctxt); 7418 7419 if (r == EMULATION_INTERCEPTED) 7420 return 1; 7421 7422 if (r == EMULATION_FAILED) { 7423 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, 7424 emulation_type)) 7425 return 1; 7426 7427 return handle_emulation_failure(vcpu, emulation_type); 7428 } 7429 7430 if (ctxt->have_exception) { 7431 r = 1; 7432 if (inject_emulated_exception(vcpu)) 7433 return r; 7434 } else if (vcpu->arch.pio.count) { 7435 if (!vcpu->arch.pio.in) { 7436 /* FIXME: return into emulator if single-stepping. */ 7437 vcpu->arch.pio.count = 0; 7438 } else { 7439 writeback = false; 7440 vcpu->arch.complete_userspace_io = complete_emulated_pio; 7441 } 7442 r = 0; 7443 } else if (vcpu->mmio_needed) { 7444 ++vcpu->stat.mmio_exits; 7445 7446 if (!vcpu->mmio_is_write) 7447 writeback = false; 7448 r = 0; 7449 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 7450 } else if (r == EMULATION_RESTART) 7451 goto restart; 7452 else 7453 r = 1; 7454 7455 if (writeback) { 7456 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu); 7457 toggle_interruptibility(vcpu, ctxt->interruptibility); 7458 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7459 if (!ctxt->have_exception || 7460 exception_type(ctxt->exception.vector) == EXCPT_TRAP) { 7461 kvm_rip_write(vcpu, ctxt->eip); 7462 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 7463 r = kvm_vcpu_do_singlestep(vcpu); 7464 if (kvm_x86_ops.update_emulated_instruction) 7465 kvm_x86_ops.update_emulated_instruction(vcpu); 7466 __kvm_set_rflags(vcpu, ctxt->eflags); 7467 } 7468 7469 /* 7470 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 7471 * do nothing, and it will be requested again as soon as 7472 * the shadow expires. But we still need to check here, 7473 * because POPF has no interrupt shadow. 7474 */ 7475 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 7476 kvm_make_request(KVM_REQ_EVENT, vcpu); 7477 } else 7478 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 7479 7480 return r; 7481 } 7482 7483 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 7484 { 7485 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 7486 } 7487 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 7488 7489 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 7490 void *insn, int insn_len) 7491 { 7492 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 7493 } 7494 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 7495 7496 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 7497 { 7498 vcpu->arch.pio.count = 0; 7499 return 1; 7500 } 7501 7502 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 7503 { 7504 vcpu->arch.pio.count = 0; 7505 7506 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 7507 return 1; 7508 7509 return kvm_skip_emulated_instruction(vcpu); 7510 } 7511 7512 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 7513 unsigned short port) 7514 { 7515 unsigned long val = kvm_rax_read(vcpu); 7516 int ret = emulator_pio_out(vcpu, size, port, &val, 1); 7517 7518 if (ret) 7519 return ret; 7520 7521 /* 7522 * Workaround userspace that relies on old KVM behavior of %rip being 7523 * incremented prior to exiting to userspace to handle "OUT 0x7e". 7524 */ 7525 if (port == 0x7e && 7526 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 7527 vcpu->arch.complete_userspace_io = 7528 complete_fast_pio_out_port_0x7e; 7529 kvm_skip_emulated_instruction(vcpu); 7530 } else { 7531 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 7532 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 7533 } 7534 return 0; 7535 } 7536 7537 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 7538 { 7539 unsigned long val; 7540 7541 /* We should only ever be called with arch.pio.count equal to 1 */ 7542 BUG_ON(vcpu->arch.pio.count != 1); 7543 7544 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 7545 vcpu->arch.pio.count = 0; 7546 return 1; 7547 } 7548 7549 /* For size less than 4 we merge, else we zero extend */ 7550 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 7551 7552 /* 7553 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform 7554 * the copy and tracing 7555 */ 7556 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); 7557 kvm_rax_write(vcpu, val); 7558 7559 return kvm_skip_emulated_instruction(vcpu); 7560 } 7561 7562 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 7563 unsigned short port) 7564 { 7565 unsigned long val; 7566 int ret; 7567 7568 /* For size less than 4 we merge, else we zero extend */ 7569 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 7570 7571 ret = emulator_pio_in(vcpu, size, port, &val, 1); 7572 if (ret) { 7573 kvm_rax_write(vcpu, val); 7574 return ret; 7575 } 7576 7577 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 7578 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 7579 7580 return 0; 7581 } 7582 7583 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 7584 { 7585 int ret; 7586 7587 if (in) 7588 ret = kvm_fast_pio_in(vcpu, size, port); 7589 else 7590 ret = kvm_fast_pio_out(vcpu, size, port); 7591 return ret && kvm_skip_emulated_instruction(vcpu); 7592 } 7593 EXPORT_SYMBOL_GPL(kvm_fast_pio); 7594 7595 static int kvmclock_cpu_down_prep(unsigned int cpu) 7596 { 7597 __this_cpu_write(cpu_tsc_khz, 0); 7598 return 0; 7599 } 7600 7601 static void tsc_khz_changed(void *data) 7602 { 7603 struct cpufreq_freqs *freq = data; 7604 unsigned long khz = 0; 7605 7606 if (data) 7607 khz = freq->new; 7608 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 7609 khz = cpufreq_quick_get(raw_smp_processor_id()); 7610 if (!khz) 7611 khz = tsc_khz; 7612 __this_cpu_write(cpu_tsc_khz, khz); 7613 } 7614 7615 #ifdef CONFIG_X86_64 7616 static void kvm_hyperv_tsc_notifier(void) 7617 { 7618 struct kvm *kvm; 7619 struct kvm_vcpu *vcpu; 7620 int cpu; 7621 7622 mutex_lock(&kvm_lock); 7623 list_for_each_entry(kvm, &vm_list, vm_list) 7624 kvm_make_mclock_inprogress_request(kvm); 7625 7626 hyperv_stop_tsc_emulation(); 7627 7628 /* TSC frequency always matches when on Hyper-V */ 7629 for_each_present_cpu(cpu) 7630 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 7631 kvm_max_guest_tsc_khz = tsc_khz; 7632 7633 list_for_each_entry(kvm, &vm_list, vm_list) { 7634 struct kvm_arch *ka = &kvm->arch; 7635 7636 spin_lock(&ka->pvclock_gtod_sync_lock); 7637 7638 pvclock_update_vm_gtod_copy(kvm); 7639 7640 kvm_for_each_vcpu(cpu, vcpu, kvm) 7641 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7642 7643 kvm_for_each_vcpu(cpu, vcpu, kvm) 7644 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 7645 7646 spin_unlock(&ka->pvclock_gtod_sync_lock); 7647 } 7648 mutex_unlock(&kvm_lock); 7649 } 7650 #endif 7651 7652 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 7653 { 7654 struct kvm *kvm; 7655 struct kvm_vcpu *vcpu; 7656 int i, send_ipi = 0; 7657 7658 /* 7659 * We allow guests to temporarily run on slowing clocks, 7660 * provided we notify them after, or to run on accelerating 7661 * clocks, provided we notify them before. Thus time never 7662 * goes backwards. 7663 * 7664 * However, we have a problem. We can't atomically update 7665 * the frequency of a given CPU from this function; it is 7666 * merely a notifier, which can be called from any CPU. 7667 * Changing the TSC frequency at arbitrary points in time 7668 * requires a recomputation of local variables related to 7669 * the TSC for each VCPU. We must flag these local variables 7670 * to be updated and be sure the update takes place with the 7671 * new frequency before any guests proceed. 7672 * 7673 * Unfortunately, the combination of hotplug CPU and frequency 7674 * change creates an intractable locking scenario; the order 7675 * of when these callouts happen is undefined with respect to 7676 * CPU hotplug, and they can race with each other. As such, 7677 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 7678 * undefined; you can actually have a CPU frequency change take 7679 * place in between the computation of X and the setting of the 7680 * variable. To protect against this problem, all updates of 7681 * the per_cpu tsc_khz variable are done in an interrupt 7682 * protected IPI, and all callers wishing to update the value 7683 * must wait for a synchronous IPI to complete (which is trivial 7684 * if the caller is on the CPU already). This establishes the 7685 * necessary total order on variable updates. 7686 * 7687 * Note that because a guest time update may take place 7688 * anytime after the setting of the VCPU's request bit, the 7689 * correct TSC value must be set before the request. However, 7690 * to ensure the update actually makes it to any guest which 7691 * starts running in hardware virtualization between the set 7692 * and the acquisition of the spinlock, we must also ping the 7693 * CPU after setting the request bit. 7694 * 7695 */ 7696 7697 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 7698 7699 mutex_lock(&kvm_lock); 7700 list_for_each_entry(kvm, &vm_list, vm_list) { 7701 kvm_for_each_vcpu(i, vcpu, kvm) { 7702 if (vcpu->cpu != cpu) 7703 continue; 7704 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7705 if (vcpu->cpu != raw_smp_processor_id()) 7706 send_ipi = 1; 7707 } 7708 } 7709 mutex_unlock(&kvm_lock); 7710 7711 if (freq->old < freq->new && send_ipi) { 7712 /* 7713 * We upscale the frequency. Must make the guest 7714 * doesn't see old kvmclock values while running with 7715 * the new frequency, otherwise we risk the guest sees 7716 * time go backwards. 7717 * 7718 * In case we update the frequency for another cpu 7719 * (which might be in guest context) send an interrupt 7720 * to kick the cpu out of guest context. Next time 7721 * guest context is entered kvmclock will be updated, 7722 * so the guest will not see stale values. 7723 */ 7724 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 7725 } 7726 } 7727 7728 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 7729 void *data) 7730 { 7731 struct cpufreq_freqs *freq = data; 7732 int cpu; 7733 7734 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 7735 return 0; 7736 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 7737 return 0; 7738 7739 for_each_cpu(cpu, freq->policy->cpus) 7740 __kvmclock_cpufreq_notifier(freq, cpu); 7741 7742 return 0; 7743 } 7744 7745 static struct notifier_block kvmclock_cpufreq_notifier_block = { 7746 .notifier_call = kvmclock_cpufreq_notifier 7747 }; 7748 7749 static int kvmclock_cpu_online(unsigned int cpu) 7750 { 7751 tsc_khz_changed(NULL); 7752 return 0; 7753 } 7754 7755 static void kvm_timer_init(void) 7756 { 7757 max_tsc_khz = tsc_khz; 7758 7759 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 7760 #ifdef CONFIG_CPU_FREQ 7761 struct cpufreq_policy *policy; 7762 int cpu; 7763 7764 cpu = get_cpu(); 7765 policy = cpufreq_cpu_get(cpu); 7766 if (policy) { 7767 if (policy->cpuinfo.max_freq) 7768 max_tsc_khz = policy->cpuinfo.max_freq; 7769 cpufreq_cpu_put(policy); 7770 } 7771 put_cpu(); 7772 #endif 7773 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 7774 CPUFREQ_TRANSITION_NOTIFIER); 7775 } 7776 7777 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 7778 kvmclock_cpu_online, kvmclock_cpu_down_prep); 7779 } 7780 7781 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 7782 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); 7783 7784 int kvm_is_in_guest(void) 7785 { 7786 return __this_cpu_read(current_vcpu) != NULL; 7787 } 7788 7789 static int kvm_is_user_mode(void) 7790 { 7791 int user_mode = 3; 7792 7793 if (__this_cpu_read(current_vcpu)) 7794 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu)); 7795 7796 return user_mode != 0; 7797 } 7798 7799 static unsigned long kvm_get_guest_ip(void) 7800 { 7801 unsigned long ip = 0; 7802 7803 if (__this_cpu_read(current_vcpu)) 7804 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 7805 7806 return ip; 7807 } 7808 7809 static void kvm_handle_intel_pt_intr(void) 7810 { 7811 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); 7812 7813 kvm_make_request(KVM_REQ_PMI, vcpu); 7814 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, 7815 (unsigned long *)&vcpu->arch.pmu.global_status); 7816 } 7817 7818 static struct perf_guest_info_callbacks kvm_guest_cbs = { 7819 .is_in_guest = kvm_is_in_guest, 7820 .is_user_mode = kvm_is_user_mode, 7821 .get_guest_ip = kvm_get_guest_ip, 7822 .handle_intel_pt_intr = kvm_handle_intel_pt_intr, 7823 }; 7824 7825 #ifdef CONFIG_X86_64 7826 static void pvclock_gtod_update_fn(struct work_struct *work) 7827 { 7828 struct kvm *kvm; 7829 7830 struct kvm_vcpu *vcpu; 7831 int i; 7832 7833 mutex_lock(&kvm_lock); 7834 list_for_each_entry(kvm, &vm_list, vm_list) 7835 kvm_for_each_vcpu(i, vcpu, kvm) 7836 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7837 atomic_set(&kvm_guest_has_master_clock, 0); 7838 mutex_unlock(&kvm_lock); 7839 } 7840 7841 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 7842 7843 /* 7844 * Notification about pvclock gtod data update. 7845 */ 7846 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 7847 void *priv) 7848 { 7849 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 7850 struct timekeeper *tk = priv; 7851 7852 update_pvclock_gtod(tk); 7853 7854 /* disable master clock if host does not trust, or does not 7855 * use, TSC based clocksource. 7856 */ 7857 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 7858 atomic_read(&kvm_guest_has_master_clock) != 0) 7859 queue_work(system_long_wq, &pvclock_gtod_work); 7860 7861 return 0; 7862 } 7863 7864 static struct notifier_block pvclock_gtod_notifier = { 7865 .notifier_call = pvclock_gtod_notify, 7866 }; 7867 #endif 7868 7869 int kvm_arch_init(void *opaque) 7870 { 7871 struct kvm_x86_init_ops *ops = opaque; 7872 int r; 7873 7874 if (kvm_x86_ops.hardware_enable) { 7875 printk(KERN_ERR "kvm: already loaded the other module\n"); 7876 r = -EEXIST; 7877 goto out; 7878 } 7879 7880 if (!ops->cpu_has_kvm_support()) { 7881 pr_err_ratelimited("kvm: no hardware support\n"); 7882 r = -EOPNOTSUPP; 7883 goto out; 7884 } 7885 if (ops->disabled_by_bios()) { 7886 pr_err_ratelimited("kvm: disabled by bios\n"); 7887 r = -EOPNOTSUPP; 7888 goto out; 7889 } 7890 7891 /* 7892 * KVM explicitly assumes that the guest has an FPU and 7893 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 7894 * vCPU's FPU state as a fxregs_state struct. 7895 */ 7896 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 7897 printk(KERN_ERR "kvm: inadequate fpu\n"); 7898 r = -EOPNOTSUPP; 7899 goto out; 7900 } 7901 7902 r = -ENOMEM; 7903 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), 7904 __alignof__(struct fpu), SLAB_ACCOUNT, 7905 NULL); 7906 if (!x86_fpu_cache) { 7907 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); 7908 goto out; 7909 } 7910 7911 x86_emulator_cache = kvm_alloc_emulator_cache(); 7912 if (!x86_emulator_cache) { 7913 pr_err("kvm: failed to allocate cache for x86 emulator\n"); 7914 goto out_free_x86_fpu_cache; 7915 } 7916 7917 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); 7918 if (!user_return_msrs) { 7919 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); 7920 goto out_free_x86_emulator_cache; 7921 } 7922 7923 r = kvm_mmu_module_init(); 7924 if (r) 7925 goto out_free_percpu; 7926 7927 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 7928 PT_DIRTY_MASK, PT64_NX_MASK, 0, 7929 PT_PRESENT_MASK, 0, sme_me_mask); 7930 kvm_timer_init(); 7931 7932 perf_register_guest_info_callbacks(&kvm_guest_cbs); 7933 7934 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 7935 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 7936 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; 7937 } 7938 7939 kvm_lapic_init(); 7940 if (pi_inject_timer == -1) 7941 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); 7942 #ifdef CONFIG_X86_64 7943 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 7944 7945 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 7946 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 7947 #endif 7948 7949 return 0; 7950 7951 out_free_percpu: 7952 free_percpu(user_return_msrs); 7953 out_free_x86_emulator_cache: 7954 kmem_cache_destroy(x86_emulator_cache); 7955 out_free_x86_fpu_cache: 7956 kmem_cache_destroy(x86_fpu_cache); 7957 out: 7958 return r; 7959 } 7960 7961 void kvm_arch_exit(void) 7962 { 7963 #ifdef CONFIG_X86_64 7964 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 7965 clear_hv_tscchange_cb(); 7966 #endif 7967 kvm_lapic_exit(); 7968 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 7969 7970 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 7971 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 7972 CPUFREQ_TRANSITION_NOTIFIER); 7973 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 7974 #ifdef CONFIG_X86_64 7975 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 7976 #endif 7977 kvm_x86_ops.hardware_enable = NULL; 7978 kvm_mmu_module_exit(); 7979 free_percpu(user_return_msrs); 7980 kmem_cache_destroy(x86_fpu_cache); 7981 } 7982 7983 static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason) 7984 { 7985 ++vcpu->stat.halt_exits; 7986 if (lapic_in_kernel(vcpu)) { 7987 vcpu->arch.mp_state = state; 7988 return 1; 7989 } else { 7990 vcpu->run->exit_reason = reason; 7991 return 0; 7992 } 7993 } 7994 7995 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 7996 { 7997 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); 7998 } 7999 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 8000 8001 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 8002 { 8003 int ret = kvm_skip_emulated_instruction(vcpu); 8004 /* 8005 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 8006 * KVM_EXIT_DEBUG here. 8007 */ 8008 return kvm_vcpu_halt(vcpu) && ret; 8009 } 8010 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 8011 8012 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) 8013 { 8014 int ret = kvm_skip_emulated_instruction(vcpu); 8015 8016 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret; 8017 } 8018 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); 8019 8020 #ifdef CONFIG_X86_64 8021 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 8022 unsigned long clock_type) 8023 { 8024 struct kvm_clock_pairing clock_pairing; 8025 struct timespec64 ts; 8026 u64 cycle; 8027 int ret; 8028 8029 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 8030 return -KVM_EOPNOTSUPP; 8031 8032 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) 8033 return -KVM_EOPNOTSUPP; 8034 8035 clock_pairing.sec = ts.tv_sec; 8036 clock_pairing.nsec = ts.tv_nsec; 8037 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 8038 clock_pairing.flags = 0; 8039 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 8040 8041 ret = 0; 8042 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 8043 sizeof(struct kvm_clock_pairing))) 8044 ret = -KVM_EFAULT; 8045 8046 return ret; 8047 } 8048 #endif 8049 8050 /* 8051 * kvm_pv_kick_cpu_op: Kick a vcpu. 8052 * 8053 * @apicid - apicid of vcpu to be kicked. 8054 */ 8055 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 8056 { 8057 struct kvm_lapic_irq lapic_irq; 8058 8059 lapic_irq.shorthand = APIC_DEST_NOSHORT; 8060 lapic_irq.dest_mode = APIC_DEST_PHYSICAL; 8061 lapic_irq.level = 0; 8062 lapic_irq.dest_id = apicid; 8063 lapic_irq.msi_redir_hint = false; 8064 8065 lapic_irq.delivery_mode = APIC_DM_REMRD; 8066 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 8067 } 8068 8069 bool kvm_apicv_activated(struct kvm *kvm) 8070 { 8071 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); 8072 } 8073 EXPORT_SYMBOL_GPL(kvm_apicv_activated); 8074 8075 void kvm_apicv_init(struct kvm *kvm, bool enable) 8076 { 8077 if (enable) 8078 clear_bit(APICV_INHIBIT_REASON_DISABLE, 8079 &kvm->arch.apicv_inhibit_reasons); 8080 else 8081 set_bit(APICV_INHIBIT_REASON_DISABLE, 8082 &kvm->arch.apicv_inhibit_reasons); 8083 } 8084 EXPORT_SYMBOL_GPL(kvm_apicv_init); 8085 8086 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id) 8087 { 8088 struct kvm_vcpu *target = NULL; 8089 struct kvm_apic_map *map; 8090 8091 rcu_read_lock(); 8092 map = rcu_dereference(kvm->arch.apic_map); 8093 8094 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 8095 target = map->phys_map[dest_id]->vcpu; 8096 8097 rcu_read_unlock(); 8098 8099 if (target && READ_ONCE(target->ready)) 8100 kvm_vcpu_yield_to(target); 8101 } 8102 8103 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 8104 { 8105 unsigned long nr, a0, a1, a2, a3, ret; 8106 int op_64_bit; 8107 8108 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 8109 return kvm_hv_hypercall(vcpu); 8110 8111 nr = kvm_rax_read(vcpu); 8112 a0 = kvm_rbx_read(vcpu); 8113 a1 = kvm_rcx_read(vcpu); 8114 a2 = kvm_rdx_read(vcpu); 8115 a3 = kvm_rsi_read(vcpu); 8116 8117 trace_kvm_hypercall(nr, a0, a1, a2, a3); 8118 8119 op_64_bit = is_64_bit_mode(vcpu); 8120 if (!op_64_bit) { 8121 nr &= 0xFFFFFFFF; 8122 a0 &= 0xFFFFFFFF; 8123 a1 &= 0xFFFFFFFF; 8124 a2 &= 0xFFFFFFFF; 8125 a3 &= 0xFFFFFFFF; 8126 } 8127 8128 if (kvm_x86_ops.get_cpl(vcpu) != 0) { 8129 ret = -KVM_EPERM; 8130 goto out; 8131 } 8132 8133 ret = -KVM_ENOSYS; 8134 8135 switch (nr) { 8136 case KVM_HC_VAPIC_POLL_IRQ: 8137 ret = 0; 8138 break; 8139 case KVM_HC_KICK_CPU: 8140 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) 8141 break; 8142 8143 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 8144 kvm_sched_yield(vcpu->kvm, a1); 8145 ret = 0; 8146 break; 8147 #ifdef CONFIG_X86_64 8148 case KVM_HC_CLOCK_PAIRING: 8149 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 8150 break; 8151 #endif 8152 case KVM_HC_SEND_IPI: 8153 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) 8154 break; 8155 8156 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 8157 break; 8158 case KVM_HC_SCHED_YIELD: 8159 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) 8160 break; 8161 8162 kvm_sched_yield(vcpu->kvm, a0); 8163 ret = 0; 8164 break; 8165 default: 8166 ret = -KVM_ENOSYS; 8167 break; 8168 } 8169 out: 8170 if (!op_64_bit) 8171 ret = (u32)ret; 8172 kvm_rax_write(vcpu, ret); 8173 8174 ++vcpu->stat.hypercalls; 8175 return kvm_skip_emulated_instruction(vcpu); 8176 } 8177 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 8178 8179 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 8180 { 8181 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8182 char instruction[3]; 8183 unsigned long rip = kvm_rip_read(vcpu); 8184 8185 kvm_x86_ops.patch_hypercall(vcpu, instruction); 8186 8187 return emulator_write_emulated(ctxt, rip, instruction, 3, 8188 &ctxt->exception); 8189 } 8190 8191 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 8192 { 8193 return vcpu->run->request_interrupt_window && 8194 likely(!pic_in_kernel(vcpu->kvm)); 8195 } 8196 8197 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 8198 { 8199 struct kvm_run *kvm_run = vcpu->run; 8200 8201 /* 8202 * if_flag is obsolete and useless, so do not bother 8203 * setting it for SEV-ES guests. Userspace can just 8204 * use kvm_run->ready_for_interrupt_injection. 8205 */ 8206 kvm_run->if_flag = !vcpu->arch.guest_state_protected 8207 && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 8208 8209 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 8210 kvm_run->cr8 = kvm_get_cr8(vcpu); 8211 kvm_run->apic_base = kvm_get_apic_base(vcpu); 8212 kvm_run->ready_for_interrupt_injection = 8213 pic_in_kernel(vcpu->kvm) || 8214 kvm_vcpu_ready_for_interrupt_injection(vcpu); 8215 } 8216 8217 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 8218 { 8219 int max_irr, tpr; 8220 8221 if (!kvm_x86_ops.update_cr8_intercept) 8222 return; 8223 8224 if (!lapic_in_kernel(vcpu)) 8225 return; 8226 8227 if (vcpu->arch.apicv_active) 8228 return; 8229 8230 if (!vcpu->arch.apic->vapic_addr) 8231 max_irr = kvm_lapic_find_highest_irr(vcpu); 8232 else 8233 max_irr = -1; 8234 8235 if (max_irr != -1) 8236 max_irr >>= 4; 8237 8238 tpr = kvm_lapic_get_cr8(vcpu); 8239 8240 kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr); 8241 } 8242 8243 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) 8244 { 8245 int r; 8246 bool can_inject = true; 8247 8248 /* try to reinject previous events if any */ 8249 8250 if (vcpu->arch.exception.injected) { 8251 kvm_x86_ops.queue_exception(vcpu); 8252 can_inject = false; 8253 } 8254 /* 8255 * Do not inject an NMI or interrupt if there is a pending 8256 * exception. Exceptions and interrupts are recognized at 8257 * instruction boundaries, i.e. the start of an instruction. 8258 * Trap-like exceptions, e.g. #DB, have higher priority than 8259 * NMIs and interrupts, i.e. traps are recognized before an 8260 * NMI/interrupt that's pending on the same instruction. 8261 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 8262 * priority, but are only generated (pended) during instruction 8263 * execution, i.e. a pending fault-like exception means the 8264 * fault occurred on the *previous* instruction and must be 8265 * serviced prior to recognizing any new events in order to 8266 * fully complete the previous instruction. 8267 */ 8268 else if (!vcpu->arch.exception.pending) { 8269 if (vcpu->arch.nmi_injected) { 8270 kvm_x86_ops.set_nmi(vcpu); 8271 can_inject = false; 8272 } else if (vcpu->arch.interrupt.injected) { 8273 kvm_x86_ops.set_irq(vcpu); 8274 can_inject = false; 8275 } 8276 } 8277 8278 WARN_ON_ONCE(vcpu->arch.exception.injected && 8279 vcpu->arch.exception.pending); 8280 8281 /* 8282 * Call check_nested_events() even if we reinjected a previous event 8283 * in order for caller to determine if it should require immediate-exit 8284 * from L2 to L1 due to pending L1 events which require exit 8285 * from L2 to L1. 8286 */ 8287 if (is_guest_mode(vcpu)) { 8288 r = kvm_x86_ops.nested_ops->check_events(vcpu); 8289 if (r < 0) 8290 goto busy; 8291 } 8292 8293 /* try to inject new event if pending */ 8294 if (vcpu->arch.exception.pending) { 8295 trace_kvm_inj_exception(vcpu->arch.exception.nr, 8296 vcpu->arch.exception.has_error_code, 8297 vcpu->arch.exception.error_code); 8298 8299 vcpu->arch.exception.pending = false; 8300 vcpu->arch.exception.injected = true; 8301 8302 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 8303 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 8304 X86_EFLAGS_RF); 8305 8306 if (vcpu->arch.exception.nr == DB_VECTOR) { 8307 kvm_deliver_exception_payload(vcpu); 8308 if (vcpu->arch.dr7 & DR7_GD) { 8309 vcpu->arch.dr7 &= ~DR7_GD; 8310 kvm_update_dr7(vcpu); 8311 } 8312 } 8313 8314 kvm_x86_ops.queue_exception(vcpu); 8315 can_inject = false; 8316 } 8317 8318 /* 8319 * Finally, inject interrupt events. If an event cannot be injected 8320 * due to architectural conditions (e.g. IF=0) a window-open exit 8321 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending 8322 * and can architecturally be injected, but we cannot do it right now: 8323 * an interrupt could have arrived just now and we have to inject it 8324 * as a vmexit, or there could already an event in the queue, which is 8325 * indicated by can_inject. In that case we request an immediate exit 8326 * in order to make progress and get back here for another iteration. 8327 * The kvm_x86_ops hooks communicate this by returning -EBUSY. 8328 */ 8329 if (vcpu->arch.smi_pending) { 8330 r = can_inject ? kvm_x86_ops.smi_allowed(vcpu, true) : -EBUSY; 8331 if (r < 0) 8332 goto busy; 8333 if (r) { 8334 vcpu->arch.smi_pending = false; 8335 ++vcpu->arch.smi_count; 8336 enter_smm(vcpu); 8337 can_inject = false; 8338 } else 8339 kvm_x86_ops.enable_smi_window(vcpu); 8340 } 8341 8342 if (vcpu->arch.nmi_pending) { 8343 r = can_inject ? kvm_x86_ops.nmi_allowed(vcpu, true) : -EBUSY; 8344 if (r < 0) 8345 goto busy; 8346 if (r) { 8347 --vcpu->arch.nmi_pending; 8348 vcpu->arch.nmi_injected = true; 8349 kvm_x86_ops.set_nmi(vcpu); 8350 can_inject = false; 8351 WARN_ON(kvm_x86_ops.nmi_allowed(vcpu, true) < 0); 8352 } 8353 if (vcpu->arch.nmi_pending) 8354 kvm_x86_ops.enable_nmi_window(vcpu); 8355 } 8356 8357 if (kvm_cpu_has_injectable_intr(vcpu)) { 8358 r = can_inject ? kvm_x86_ops.interrupt_allowed(vcpu, true) : -EBUSY; 8359 if (r < 0) 8360 goto busy; 8361 if (r) { 8362 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); 8363 kvm_x86_ops.set_irq(vcpu); 8364 WARN_ON(kvm_x86_ops.interrupt_allowed(vcpu, true) < 0); 8365 } 8366 if (kvm_cpu_has_injectable_intr(vcpu)) 8367 kvm_x86_ops.enable_irq_window(vcpu); 8368 } 8369 8370 if (is_guest_mode(vcpu) && 8371 kvm_x86_ops.nested_ops->hv_timer_pending && 8372 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 8373 *req_immediate_exit = true; 8374 8375 WARN_ON(vcpu->arch.exception.pending); 8376 return; 8377 8378 busy: 8379 *req_immediate_exit = true; 8380 return; 8381 } 8382 8383 static void process_nmi(struct kvm_vcpu *vcpu) 8384 { 8385 unsigned limit = 2; 8386 8387 /* 8388 * x86 is limited to one NMI running, and one NMI pending after it. 8389 * If an NMI is already in progress, limit further NMIs to just one. 8390 * Otherwise, allow two (and we'll inject the first one immediately). 8391 */ 8392 if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 8393 limit = 1; 8394 8395 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 8396 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 8397 kvm_make_request(KVM_REQ_EVENT, vcpu); 8398 } 8399 8400 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 8401 { 8402 u32 flags = 0; 8403 flags |= seg->g << 23; 8404 flags |= seg->db << 22; 8405 flags |= seg->l << 21; 8406 flags |= seg->avl << 20; 8407 flags |= seg->present << 15; 8408 flags |= seg->dpl << 13; 8409 flags |= seg->s << 12; 8410 flags |= seg->type << 8; 8411 return flags; 8412 } 8413 8414 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 8415 { 8416 struct kvm_segment seg; 8417 int offset; 8418 8419 kvm_get_segment(vcpu, &seg, n); 8420 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 8421 8422 if (n < 3) 8423 offset = 0x7f84 + n * 12; 8424 else 8425 offset = 0x7f2c + (n - 3) * 12; 8426 8427 put_smstate(u32, buf, offset + 8, seg.base); 8428 put_smstate(u32, buf, offset + 4, seg.limit); 8429 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 8430 } 8431 8432 #ifdef CONFIG_X86_64 8433 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 8434 { 8435 struct kvm_segment seg; 8436 int offset; 8437 u16 flags; 8438 8439 kvm_get_segment(vcpu, &seg, n); 8440 offset = 0x7e00 + n * 16; 8441 8442 flags = enter_smm_get_segment_flags(&seg) >> 8; 8443 put_smstate(u16, buf, offset, seg.selector); 8444 put_smstate(u16, buf, offset + 2, flags); 8445 put_smstate(u32, buf, offset + 4, seg.limit); 8446 put_smstate(u64, buf, offset + 8, seg.base); 8447 } 8448 #endif 8449 8450 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 8451 { 8452 struct desc_ptr dt; 8453 struct kvm_segment seg; 8454 unsigned long val; 8455 int i; 8456 8457 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 8458 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 8459 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 8460 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 8461 8462 for (i = 0; i < 8; i++) 8463 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 8464 8465 kvm_get_dr(vcpu, 6, &val); 8466 put_smstate(u32, buf, 0x7fcc, (u32)val); 8467 kvm_get_dr(vcpu, 7, &val); 8468 put_smstate(u32, buf, 0x7fc8, (u32)val); 8469 8470 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 8471 put_smstate(u32, buf, 0x7fc4, seg.selector); 8472 put_smstate(u32, buf, 0x7f64, seg.base); 8473 put_smstate(u32, buf, 0x7f60, seg.limit); 8474 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 8475 8476 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 8477 put_smstate(u32, buf, 0x7fc0, seg.selector); 8478 put_smstate(u32, buf, 0x7f80, seg.base); 8479 put_smstate(u32, buf, 0x7f7c, seg.limit); 8480 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 8481 8482 kvm_x86_ops.get_gdt(vcpu, &dt); 8483 put_smstate(u32, buf, 0x7f74, dt.address); 8484 put_smstate(u32, buf, 0x7f70, dt.size); 8485 8486 kvm_x86_ops.get_idt(vcpu, &dt); 8487 put_smstate(u32, buf, 0x7f58, dt.address); 8488 put_smstate(u32, buf, 0x7f54, dt.size); 8489 8490 for (i = 0; i < 6; i++) 8491 enter_smm_save_seg_32(vcpu, buf, i); 8492 8493 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 8494 8495 /* revision id */ 8496 put_smstate(u32, buf, 0x7efc, 0x00020000); 8497 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 8498 } 8499 8500 #ifdef CONFIG_X86_64 8501 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 8502 { 8503 struct desc_ptr dt; 8504 struct kvm_segment seg; 8505 unsigned long val; 8506 int i; 8507 8508 for (i = 0; i < 16; i++) 8509 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 8510 8511 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 8512 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 8513 8514 kvm_get_dr(vcpu, 6, &val); 8515 put_smstate(u64, buf, 0x7f68, val); 8516 kvm_get_dr(vcpu, 7, &val); 8517 put_smstate(u64, buf, 0x7f60, val); 8518 8519 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 8520 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 8521 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 8522 8523 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 8524 8525 /* revision id */ 8526 put_smstate(u32, buf, 0x7efc, 0x00020064); 8527 8528 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 8529 8530 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 8531 put_smstate(u16, buf, 0x7e90, seg.selector); 8532 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 8533 put_smstate(u32, buf, 0x7e94, seg.limit); 8534 put_smstate(u64, buf, 0x7e98, seg.base); 8535 8536 kvm_x86_ops.get_idt(vcpu, &dt); 8537 put_smstate(u32, buf, 0x7e84, dt.size); 8538 put_smstate(u64, buf, 0x7e88, dt.address); 8539 8540 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 8541 put_smstate(u16, buf, 0x7e70, seg.selector); 8542 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 8543 put_smstate(u32, buf, 0x7e74, seg.limit); 8544 put_smstate(u64, buf, 0x7e78, seg.base); 8545 8546 kvm_x86_ops.get_gdt(vcpu, &dt); 8547 put_smstate(u32, buf, 0x7e64, dt.size); 8548 put_smstate(u64, buf, 0x7e68, dt.address); 8549 8550 for (i = 0; i < 6; i++) 8551 enter_smm_save_seg_64(vcpu, buf, i); 8552 } 8553 #endif 8554 8555 static void enter_smm(struct kvm_vcpu *vcpu) 8556 { 8557 struct kvm_segment cs, ds; 8558 struct desc_ptr dt; 8559 char buf[512]; 8560 u32 cr0; 8561 8562 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 8563 memset(buf, 0, 512); 8564 #ifdef CONFIG_X86_64 8565 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 8566 enter_smm_save_state_64(vcpu, buf); 8567 else 8568 #endif 8569 enter_smm_save_state_32(vcpu, buf); 8570 8571 /* 8572 * Give pre_enter_smm() a chance to make ISA-specific changes to the 8573 * vCPU state (e.g. leave guest mode) after we've saved the state into 8574 * the SMM state-save area. 8575 */ 8576 kvm_x86_ops.pre_enter_smm(vcpu, buf); 8577 8578 vcpu->arch.hflags |= HF_SMM_MASK; 8579 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 8580 8581 if (kvm_x86_ops.get_nmi_mask(vcpu)) 8582 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 8583 else 8584 kvm_x86_ops.set_nmi_mask(vcpu, true); 8585 8586 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 8587 kvm_rip_write(vcpu, 0x8000); 8588 8589 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 8590 kvm_x86_ops.set_cr0(vcpu, cr0); 8591 vcpu->arch.cr0 = cr0; 8592 8593 kvm_x86_ops.set_cr4(vcpu, 0); 8594 8595 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 8596 dt.address = dt.size = 0; 8597 kvm_x86_ops.set_idt(vcpu, &dt); 8598 8599 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 8600 8601 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 8602 cs.base = vcpu->arch.smbase; 8603 8604 ds.selector = 0; 8605 ds.base = 0; 8606 8607 cs.limit = ds.limit = 0xffffffff; 8608 cs.type = ds.type = 0x3; 8609 cs.dpl = ds.dpl = 0; 8610 cs.db = ds.db = 0; 8611 cs.s = ds.s = 1; 8612 cs.l = ds.l = 0; 8613 cs.g = ds.g = 1; 8614 cs.avl = ds.avl = 0; 8615 cs.present = ds.present = 1; 8616 cs.unusable = ds.unusable = 0; 8617 cs.padding = ds.padding = 0; 8618 8619 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 8620 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 8621 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 8622 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 8623 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 8624 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 8625 8626 #ifdef CONFIG_X86_64 8627 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 8628 kvm_x86_ops.set_efer(vcpu, 0); 8629 #endif 8630 8631 kvm_update_cpuid_runtime(vcpu); 8632 kvm_mmu_reset_context(vcpu); 8633 } 8634 8635 static void process_smi(struct kvm_vcpu *vcpu) 8636 { 8637 vcpu->arch.smi_pending = true; 8638 kvm_make_request(KVM_REQ_EVENT, vcpu); 8639 } 8640 8641 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 8642 unsigned long *vcpu_bitmap) 8643 { 8644 cpumask_var_t cpus; 8645 8646 zalloc_cpumask_var(&cpus, GFP_ATOMIC); 8647 8648 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, 8649 NULL, vcpu_bitmap, cpus); 8650 8651 free_cpumask_var(cpus); 8652 } 8653 8654 void kvm_make_scan_ioapic_request(struct kvm *kvm) 8655 { 8656 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 8657 } 8658 8659 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 8660 { 8661 if (!lapic_in_kernel(vcpu)) 8662 return; 8663 8664 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm); 8665 kvm_apic_update_apicv(vcpu); 8666 kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu); 8667 } 8668 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); 8669 8670 /* 8671 * NOTE: Do not hold any lock prior to calling this. 8672 * 8673 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be 8674 * locked, because it calls __x86_set_memory_region() which does 8675 * synchronize_srcu(&kvm->srcu). 8676 */ 8677 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) 8678 { 8679 struct kvm_vcpu *except; 8680 unsigned long old, new, expected; 8681 8682 if (!kvm_x86_ops.check_apicv_inhibit_reasons || 8683 !kvm_x86_ops.check_apicv_inhibit_reasons(bit)) 8684 return; 8685 8686 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons); 8687 do { 8688 expected = new = old; 8689 if (activate) 8690 __clear_bit(bit, &new); 8691 else 8692 __set_bit(bit, &new); 8693 if (new == old) 8694 break; 8695 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new); 8696 } while (old != expected); 8697 8698 if (!!old == !!new) 8699 return; 8700 8701 trace_kvm_apicv_update_request(activate, bit); 8702 if (kvm_x86_ops.pre_update_apicv_exec_ctrl) 8703 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate); 8704 8705 /* 8706 * Sending request to update APICV for all other vcpus, 8707 * while update the calling vcpu immediately instead of 8708 * waiting for another #VMEXIT to handle the request. 8709 */ 8710 except = kvm_get_running_vcpu(); 8711 kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE, 8712 except); 8713 if (except) 8714 kvm_vcpu_update_apicv(except); 8715 } 8716 EXPORT_SYMBOL_GPL(kvm_request_apicv_update); 8717 8718 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 8719 { 8720 if (!kvm_apic_present(vcpu)) 8721 return; 8722 8723 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 8724 8725 if (irqchip_split(vcpu->kvm)) 8726 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 8727 else { 8728 if (vcpu->arch.apicv_active) 8729 kvm_x86_ops.sync_pir_to_irr(vcpu); 8730 if (ioapic_in_kernel(vcpu->kvm)) 8731 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 8732 } 8733 8734 if (is_guest_mode(vcpu)) 8735 vcpu->arch.load_eoi_exitmap_pending = true; 8736 else 8737 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 8738 } 8739 8740 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 8741 { 8742 u64 eoi_exit_bitmap[4]; 8743 8744 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 8745 return; 8746 8747 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, 8748 vcpu_to_synic(vcpu)->vec_bitmap, 256); 8749 kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap); 8750 } 8751 8752 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 8753 unsigned long start, unsigned long end) 8754 { 8755 unsigned long apic_address; 8756 8757 /* 8758 * The physical address of apic access page is stored in the VMCS. 8759 * Update it when it becomes invalid. 8760 */ 8761 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 8762 if (start <= apic_address && apic_address < end) 8763 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 8764 } 8765 8766 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 8767 { 8768 if (!lapic_in_kernel(vcpu)) 8769 return; 8770 8771 if (!kvm_x86_ops.set_apic_access_page_addr) 8772 return; 8773 8774 kvm_x86_ops.set_apic_access_page_addr(vcpu); 8775 } 8776 8777 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 8778 { 8779 smp_send_reschedule(vcpu->cpu); 8780 } 8781 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 8782 8783 /* 8784 * Returns 1 to let vcpu_run() continue the guest execution loop without 8785 * exiting to the userspace. Otherwise, the value will be returned to the 8786 * userspace. 8787 */ 8788 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 8789 { 8790 int r; 8791 bool req_int_win = 8792 dm_request_for_irq_injection(vcpu) && 8793 kvm_cpu_accept_dm_intr(vcpu); 8794 fastpath_t exit_fastpath; 8795 8796 bool req_immediate_exit = false; 8797 8798 /* Forbid vmenter if vcpu dirty ring is soft-full */ 8799 if (unlikely(vcpu->kvm->dirty_ring_size && 8800 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { 8801 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; 8802 trace_kvm_dirty_ring_exit(vcpu); 8803 r = 0; 8804 goto out; 8805 } 8806 8807 if (kvm_request_pending(vcpu)) { 8808 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { 8809 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { 8810 r = 0; 8811 goto out; 8812 } 8813 } 8814 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 8815 kvm_mmu_unload(vcpu); 8816 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 8817 __kvm_migrate_timers(vcpu); 8818 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 8819 kvm_gen_update_masterclock(vcpu->kvm); 8820 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 8821 kvm_gen_kvmclock_update(vcpu); 8822 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 8823 r = kvm_guest_time_update(vcpu); 8824 if (unlikely(r)) 8825 goto out; 8826 } 8827 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 8828 kvm_mmu_sync_roots(vcpu); 8829 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) 8830 kvm_mmu_load_pgd(vcpu); 8831 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { 8832 kvm_vcpu_flush_tlb_all(vcpu); 8833 8834 /* Flushing all ASIDs flushes the current ASID... */ 8835 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 8836 } 8837 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) 8838 kvm_vcpu_flush_tlb_current(vcpu); 8839 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu)) 8840 kvm_vcpu_flush_tlb_guest(vcpu); 8841 8842 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 8843 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 8844 r = 0; 8845 goto out; 8846 } 8847 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 8848 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 8849 vcpu->mmio_needed = 0; 8850 r = 0; 8851 goto out; 8852 } 8853 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 8854 /* Page is swapped out. Do synthetic halt */ 8855 vcpu->arch.apf.halted = true; 8856 r = 1; 8857 goto out; 8858 } 8859 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 8860 record_steal_time(vcpu); 8861 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 8862 process_smi(vcpu); 8863 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 8864 process_nmi(vcpu); 8865 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 8866 kvm_pmu_handle_event(vcpu); 8867 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 8868 kvm_pmu_deliver_pmi(vcpu); 8869 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 8870 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 8871 if (test_bit(vcpu->arch.pending_ioapic_eoi, 8872 vcpu->arch.ioapic_handled_vectors)) { 8873 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 8874 vcpu->run->eoi.vector = 8875 vcpu->arch.pending_ioapic_eoi; 8876 r = 0; 8877 goto out; 8878 } 8879 } 8880 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 8881 vcpu_scan_ioapic(vcpu); 8882 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 8883 vcpu_load_eoi_exitmap(vcpu); 8884 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 8885 kvm_vcpu_reload_apic_access_page(vcpu); 8886 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 8887 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 8888 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 8889 r = 0; 8890 goto out; 8891 } 8892 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 8893 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 8894 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 8895 r = 0; 8896 goto out; 8897 } 8898 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 8899 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 8900 vcpu->run->hyperv = vcpu->arch.hyperv.exit; 8901 r = 0; 8902 goto out; 8903 } 8904 8905 /* 8906 * KVM_REQ_HV_STIMER has to be processed after 8907 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 8908 * depend on the guest clock being up-to-date 8909 */ 8910 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 8911 kvm_hv_process_stimers(vcpu); 8912 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 8913 kvm_vcpu_update_apicv(vcpu); 8914 if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) 8915 kvm_check_async_pf_completion(vcpu); 8916 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) 8917 kvm_x86_ops.msr_filter_changed(vcpu); 8918 } 8919 8920 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 8921 ++vcpu->stat.req_event; 8922 kvm_apic_accept_events(vcpu); 8923 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 8924 r = 1; 8925 goto out; 8926 } 8927 8928 inject_pending_event(vcpu, &req_immediate_exit); 8929 if (req_int_win) 8930 kvm_x86_ops.enable_irq_window(vcpu); 8931 8932 if (kvm_lapic_enabled(vcpu)) { 8933 update_cr8_intercept(vcpu); 8934 kvm_lapic_sync_to_vapic(vcpu); 8935 } 8936 } 8937 8938 r = kvm_mmu_reload(vcpu); 8939 if (unlikely(r)) { 8940 goto cancel_injection; 8941 } 8942 8943 preempt_disable(); 8944 8945 kvm_x86_ops.prepare_guest_switch(vcpu); 8946 8947 /* 8948 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 8949 * IPI are then delayed after guest entry, which ensures that they 8950 * result in virtual interrupt delivery. 8951 */ 8952 local_irq_disable(); 8953 vcpu->mode = IN_GUEST_MODE; 8954 8955 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 8956 8957 /* 8958 * 1) We should set ->mode before checking ->requests. Please see 8959 * the comment in kvm_vcpu_exiting_guest_mode(). 8960 * 8961 * 2) For APICv, we should set ->mode before checking PID.ON. This 8962 * pairs with the memory barrier implicit in pi_test_and_set_on 8963 * (see vmx_deliver_posted_interrupt). 8964 * 8965 * 3) This also orders the write to mode from any reads to the page 8966 * tables done while the VCPU is running. Please see the comment 8967 * in kvm_flush_remote_tlbs. 8968 */ 8969 smp_mb__after_srcu_read_unlock(); 8970 8971 /* 8972 * This handles the case where a posted interrupt was 8973 * notified with kvm_vcpu_kick. 8974 */ 8975 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) 8976 kvm_x86_ops.sync_pir_to_irr(vcpu); 8977 8978 if (kvm_vcpu_exit_request(vcpu)) { 8979 vcpu->mode = OUTSIDE_GUEST_MODE; 8980 smp_wmb(); 8981 local_irq_enable(); 8982 preempt_enable(); 8983 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 8984 r = 1; 8985 goto cancel_injection; 8986 } 8987 8988 if (req_immediate_exit) { 8989 kvm_make_request(KVM_REQ_EVENT, vcpu); 8990 kvm_x86_ops.request_immediate_exit(vcpu); 8991 } 8992 8993 fpregs_assert_state_consistent(); 8994 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 8995 switch_fpu_return(); 8996 8997 if (unlikely(vcpu->arch.switch_db_regs)) { 8998 set_debugreg(0, 7); 8999 set_debugreg(vcpu->arch.eff_db[0], 0); 9000 set_debugreg(vcpu->arch.eff_db[1], 1); 9001 set_debugreg(vcpu->arch.eff_db[2], 2); 9002 set_debugreg(vcpu->arch.eff_db[3], 3); 9003 set_debugreg(vcpu->arch.dr6, 6); 9004 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 9005 } 9006 9007 exit_fastpath = kvm_x86_ops.run(vcpu); 9008 9009 /* 9010 * Do this here before restoring debug registers on the host. And 9011 * since we do this before handling the vmexit, a DR access vmexit 9012 * can (a) read the correct value of the debug registers, (b) set 9013 * KVM_DEBUGREG_WONT_EXIT again. 9014 */ 9015 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 9016 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 9017 kvm_x86_ops.sync_dirty_debug_regs(vcpu); 9018 kvm_update_dr0123(vcpu); 9019 kvm_update_dr7(vcpu); 9020 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 9021 } 9022 9023 /* 9024 * If the guest has used debug registers, at least dr7 9025 * will be disabled while returning to the host. 9026 * If we don't have active breakpoints in the host, we don't 9027 * care about the messed up debug address registers. But if 9028 * we have some of them active, restore the old state. 9029 */ 9030 if (hw_breakpoint_active()) 9031 hw_breakpoint_restore(); 9032 9033 vcpu->arch.last_vmentry_cpu = vcpu->cpu; 9034 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 9035 9036 vcpu->mode = OUTSIDE_GUEST_MODE; 9037 smp_wmb(); 9038 9039 kvm_x86_ops.handle_exit_irqoff(vcpu); 9040 9041 /* 9042 * Consume any pending interrupts, including the possible source of 9043 * VM-Exit on SVM and any ticks that occur between VM-Exit and now. 9044 * An instruction is required after local_irq_enable() to fully unblock 9045 * interrupts on processors that implement an interrupt shadow, the 9046 * stat.exits increment will do nicely. 9047 */ 9048 kvm_before_interrupt(vcpu); 9049 local_irq_enable(); 9050 ++vcpu->stat.exits; 9051 local_irq_disable(); 9052 kvm_after_interrupt(vcpu); 9053 9054 if (lapic_in_kernel(vcpu)) { 9055 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; 9056 if (delta != S64_MIN) { 9057 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); 9058 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; 9059 } 9060 } 9061 9062 local_irq_enable(); 9063 preempt_enable(); 9064 9065 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9066 9067 /* 9068 * Profile KVM exit RIPs: 9069 */ 9070 if (unlikely(prof_on == KVM_PROFILING)) { 9071 unsigned long rip = kvm_rip_read(vcpu); 9072 profile_hit(KVM_PROFILING, (void *)rip); 9073 } 9074 9075 if (unlikely(vcpu->arch.tsc_always_catchup)) 9076 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 9077 9078 if (vcpu->arch.apic_attention) 9079 kvm_lapic_sync_from_vapic(vcpu); 9080 9081 r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath); 9082 return r; 9083 9084 cancel_injection: 9085 if (req_immediate_exit) 9086 kvm_make_request(KVM_REQ_EVENT, vcpu); 9087 kvm_x86_ops.cancel_injection(vcpu); 9088 if (unlikely(vcpu->arch.apic_attention)) 9089 kvm_lapic_sync_from_vapic(vcpu); 9090 out: 9091 return r; 9092 } 9093 9094 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 9095 { 9096 if (!kvm_arch_vcpu_runnable(vcpu) && 9097 (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) { 9098 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9099 kvm_vcpu_block(vcpu); 9100 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9101 9102 if (kvm_x86_ops.post_block) 9103 kvm_x86_ops.post_block(vcpu); 9104 9105 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 9106 return 1; 9107 } 9108 9109 kvm_apic_accept_events(vcpu); 9110 switch(vcpu->arch.mp_state) { 9111 case KVM_MP_STATE_HALTED: 9112 case KVM_MP_STATE_AP_RESET_HOLD: 9113 vcpu->arch.pv.pv_unhalted = false; 9114 vcpu->arch.mp_state = 9115 KVM_MP_STATE_RUNNABLE; 9116 fallthrough; 9117 case KVM_MP_STATE_RUNNABLE: 9118 vcpu->arch.apf.halted = false; 9119 break; 9120 case KVM_MP_STATE_INIT_RECEIVED: 9121 break; 9122 default: 9123 return -EINTR; 9124 } 9125 return 1; 9126 } 9127 9128 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 9129 { 9130 if (is_guest_mode(vcpu)) 9131 kvm_x86_ops.nested_ops->check_events(vcpu); 9132 9133 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 9134 !vcpu->arch.apf.halted); 9135 } 9136 9137 static int vcpu_run(struct kvm_vcpu *vcpu) 9138 { 9139 int r; 9140 struct kvm *kvm = vcpu->kvm; 9141 9142 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9143 vcpu->arch.l1tf_flush_l1d = true; 9144 9145 for (;;) { 9146 if (kvm_vcpu_running(vcpu)) { 9147 r = vcpu_enter_guest(vcpu); 9148 } else { 9149 r = vcpu_block(kvm, vcpu); 9150 } 9151 9152 if (r <= 0) 9153 break; 9154 9155 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); 9156 if (kvm_cpu_has_pending_timer(vcpu)) 9157 kvm_inject_pending_timer_irqs(vcpu); 9158 9159 if (dm_request_for_irq_injection(vcpu) && 9160 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 9161 r = 0; 9162 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 9163 ++vcpu->stat.request_irq_exits; 9164 break; 9165 } 9166 9167 if (__xfer_to_guest_mode_work_pending()) { 9168 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9169 r = xfer_to_guest_mode_handle_work(vcpu); 9170 if (r) 9171 return r; 9172 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9173 } 9174 } 9175 9176 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9177 9178 return r; 9179 } 9180 9181 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 9182 { 9183 int r; 9184 9185 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9186 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 9187 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 9188 return r; 9189 } 9190 9191 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 9192 { 9193 BUG_ON(!vcpu->arch.pio.count); 9194 9195 return complete_emulated_io(vcpu); 9196 } 9197 9198 /* 9199 * Implements the following, as a state machine: 9200 * 9201 * read: 9202 * for each fragment 9203 * for each mmio piece in the fragment 9204 * write gpa, len 9205 * exit 9206 * copy data 9207 * execute insn 9208 * 9209 * write: 9210 * for each fragment 9211 * for each mmio piece in the fragment 9212 * write gpa, len 9213 * copy data 9214 * exit 9215 */ 9216 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 9217 { 9218 struct kvm_run *run = vcpu->run; 9219 struct kvm_mmio_fragment *frag; 9220 unsigned len; 9221 9222 BUG_ON(!vcpu->mmio_needed); 9223 9224 /* Complete previous fragment */ 9225 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 9226 len = min(8u, frag->len); 9227 if (!vcpu->mmio_is_write) 9228 memcpy(frag->data, run->mmio.data, len); 9229 9230 if (frag->len <= 8) { 9231 /* Switch to the next fragment. */ 9232 frag++; 9233 vcpu->mmio_cur_fragment++; 9234 } else { 9235 /* Go forward to the next mmio piece. */ 9236 frag->data += len; 9237 frag->gpa += len; 9238 frag->len -= len; 9239 } 9240 9241 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 9242 vcpu->mmio_needed = 0; 9243 9244 /* FIXME: return into emulator if single-stepping. */ 9245 if (vcpu->mmio_is_write) 9246 return 1; 9247 vcpu->mmio_read_completed = 1; 9248 return complete_emulated_io(vcpu); 9249 } 9250 9251 run->exit_reason = KVM_EXIT_MMIO; 9252 run->mmio.phys_addr = frag->gpa; 9253 if (vcpu->mmio_is_write) 9254 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 9255 run->mmio.len = min(8u, frag->len); 9256 run->mmio.is_write = vcpu->mmio_is_write; 9257 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 9258 return 0; 9259 } 9260 9261 static void kvm_save_current_fpu(struct fpu *fpu) 9262 { 9263 /* 9264 * If the target FPU state is not resident in the CPU registers, just 9265 * memcpy() from current, else save CPU state directly to the target. 9266 */ 9267 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 9268 memcpy(&fpu->state, ¤t->thread.fpu.state, 9269 fpu_kernel_xstate_size); 9270 else 9271 copy_fpregs_to_fpstate(fpu); 9272 } 9273 9274 /* Swap (qemu) user FPU context for the guest FPU context. */ 9275 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 9276 { 9277 fpregs_lock(); 9278 9279 kvm_save_current_fpu(vcpu->arch.user_fpu); 9280 9281 /* 9282 * Guests with protected state can't have it set by the hypervisor, 9283 * so skip trying to set it. 9284 */ 9285 if (vcpu->arch.guest_fpu) 9286 /* PKRU is separately restored in kvm_x86_ops.run. */ 9287 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, 9288 ~XFEATURE_MASK_PKRU); 9289 9290 fpregs_mark_activate(); 9291 fpregs_unlock(); 9292 9293 trace_kvm_fpu(1); 9294 } 9295 9296 /* When vcpu_run ends, restore user space FPU context. */ 9297 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 9298 { 9299 fpregs_lock(); 9300 9301 /* 9302 * Guests with protected state can't have it read by the hypervisor, 9303 * so skip trying to save it. 9304 */ 9305 if (vcpu->arch.guest_fpu) 9306 kvm_save_current_fpu(vcpu->arch.guest_fpu); 9307 9308 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); 9309 9310 fpregs_mark_activate(); 9311 fpregs_unlock(); 9312 9313 ++vcpu->stat.fpu_reload; 9314 trace_kvm_fpu(0); 9315 } 9316 9317 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 9318 { 9319 struct kvm_run *kvm_run = vcpu->run; 9320 int r; 9321 9322 vcpu_load(vcpu); 9323 kvm_sigset_activate(vcpu); 9324 kvm_load_guest_fpu(vcpu); 9325 9326 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 9327 if (kvm_run->immediate_exit) { 9328 r = -EINTR; 9329 goto out; 9330 } 9331 kvm_vcpu_block(vcpu); 9332 kvm_apic_accept_events(vcpu); 9333 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 9334 r = -EAGAIN; 9335 if (signal_pending(current)) { 9336 r = -EINTR; 9337 kvm_run->exit_reason = KVM_EXIT_INTR; 9338 ++vcpu->stat.signal_exits; 9339 } 9340 goto out; 9341 } 9342 9343 if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { 9344 r = -EINVAL; 9345 goto out; 9346 } 9347 9348 if (kvm_run->kvm_dirty_regs) { 9349 r = sync_regs(vcpu); 9350 if (r != 0) 9351 goto out; 9352 } 9353 9354 /* re-sync apic's tpr */ 9355 if (!lapic_in_kernel(vcpu)) { 9356 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 9357 r = -EINVAL; 9358 goto out; 9359 } 9360 } 9361 9362 if (unlikely(vcpu->arch.complete_userspace_io)) { 9363 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 9364 vcpu->arch.complete_userspace_io = NULL; 9365 r = cui(vcpu); 9366 if (r <= 0) 9367 goto out; 9368 } else 9369 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 9370 9371 if (kvm_run->immediate_exit) 9372 r = -EINTR; 9373 else 9374 r = vcpu_run(vcpu); 9375 9376 out: 9377 kvm_put_guest_fpu(vcpu); 9378 if (kvm_run->kvm_valid_regs) 9379 store_regs(vcpu); 9380 post_kvm_run_save(vcpu); 9381 kvm_sigset_deactivate(vcpu); 9382 9383 vcpu_put(vcpu); 9384 return r; 9385 } 9386 9387 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9388 { 9389 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 9390 /* 9391 * We are here if userspace calls get_regs() in the middle of 9392 * instruction emulation. Registers state needs to be copied 9393 * back from emulation context to vcpu. Userspace shouldn't do 9394 * that usually, but some bad designed PV devices (vmware 9395 * backdoor interface) need this to work 9396 */ 9397 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); 9398 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 9399 } 9400 regs->rax = kvm_rax_read(vcpu); 9401 regs->rbx = kvm_rbx_read(vcpu); 9402 regs->rcx = kvm_rcx_read(vcpu); 9403 regs->rdx = kvm_rdx_read(vcpu); 9404 regs->rsi = kvm_rsi_read(vcpu); 9405 regs->rdi = kvm_rdi_read(vcpu); 9406 regs->rsp = kvm_rsp_read(vcpu); 9407 regs->rbp = kvm_rbp_read(vcpu); 9408 #ifdef CONFIG_X86_64 9409 regs->r8 = kvm_r8_read(vcpu); 9410 regs->r9 = kvm_r9_read(vcpu); 9411 regs->r10 = kvm_r10_read(vcpu); 9412 regs->r11 = kvm_r11_read(vcpu); 9413 regs->r12 = kvm_r12_read(vcpu); 9414 regs->r13 = kvm_r13_read(vcpu); 9415 regs->r14 = kvm_r14_read(vcpu); 9416 regs->r15 = kvm_r15_read(vcpu); 9417 #endif 9418 9419 regs->rip = kvm_rip_read(vcpu); 9420 regs->rflags = kvm_get_rflags(vcpu); 9421 } 9422 9423 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9424 { 9425 vcpu_load(vcpu); 9426 __get_regs(vcpu, regs); 9427 vcpu_put(vcpu); 9428 return 0; 9429 } 9430 9431 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9432 { 9433 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 9434 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 9435 9436 kvm_rax_write(vcpu, regs->rax); 9437 kvm_rbx_write(vcpu, regs->rbx); 9438 kvm_rcx_write(vcpu, regs->rcx); 9439 kvm_rdx_write(vcpu, regs->rdx); 9440 kvm_rsi_write(vcpu, regs->rsi); 9441 kvm_rdi_write(vcpu, regs->rdi); 9442 kvm_rsp_write(vcpu, regs->rsp); 9443 kvm_rbp_write(vcpu, regs->rbp); 9444 #ifdef CONFIG_X86_64 9445 kvm_r8_write(vcpu, regs->r8); 9446 kvm_r9_write(vcpu, regs->r9); 9447 kvm_r10_write(vcpu, regs->r10); 9448 kvm_r11_write(vcpu, regs->r11); 9449 kvm_r12_write(vcpu, regs->r12); 9450 kvm_r13_write(vcpu, regs->r13); 9451 kvm_r14_write(vcpu, regs->r14); 9452 kvm_r15_write(vcpu, regs->r15); 9453 #endif 9454 9455 kvm_rip_write(vcpu, regs->rip); 9456 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 9457 9458 vcpu->arch.exception.pending = false; 9459 9460 kvm_make_request(KVM_REQ_EVENT, vcpu); 9461 } 9462 9463 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9464 { 9465 vcpu_load(vcpu); 9466 __set_regs(vcpu, regs); 9467 vcpu_put(vcpu); 9468 return 0; 9469 } 9470 9471 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 9472 { 9473 struct kvm_segment cs; 9474 9475 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 9476 *db = cs.db; 9477 *l = cs.l; 9478 } 9479 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 9480 9481 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 9482 { 9483 struct desc_ptr dt; 9484 9485 if (vcpu->arch.guest_state_protected) 9486 goto skip_protected_regs; 9487 9488 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 9489 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 9490 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 9491 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 9492 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 9493 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 9494 9495 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 9496 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 9497 9498 kvm_x86_ops.get_idt(vcpu, &dt); 9499 sregs->idt.limit = dt.size; 9500 sregs->idt.base = dt.address; 9501 kvm_x86_ops.get_gdt(vcpu, &dt); 9502 sregs->gdt.limit = dt.size; 9503 sregs->gdt.base = dt.address; 9504 9505 sregs->cr2 = vcpu->arch.cr2; 9506 sregs->cr3 = kvm_read_cr3(vcpu); 9507 9508 skip_protected_regs: 9509 sregs->cr0 = kvm_read_cr0(vcpu); 9510 sregs->cr4 = kvm_read_cr4(vcpu); 9511 sregs->cr8 = kvm_get_cr8(vcpu); 9512 sregs->efer = vcpu->arch.efer; 9513 sregs->apic_base = kvm_get_apic_base(vcpu); 9514 9515 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); 9516 9517 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 9518 set_bit(vcpu->arch.interrupt.nr, 9519 (unsigned long *)sregs->interrupt_bitmap); 9520 } 9521 9522 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 9523 struct kvm_sregs *sregs) 9524 { 9525 vcpu_load(vcpu); 9526 __get_sregs(vcpu, sregs); 9527 vcpu_put(vcpu); 9528 return 0; 9529 } 9530 9531 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 9532 struct kvm_mp_state *mp_state) 9533 { 9534 vcpu_load(vcpu); 9535 if (kvm_mpx_supported()) 9536 kvm_load_guest_fpu(vcpu); 9537 9538 kvm_apic_accept_events(vcpu); 9539 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || 9540 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && 9541 vcpu->arch.pv.pv_unhalted) 9542 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 9543 else 9544 mp_state->mp_state = vcpu->arch.mp_state; 9545 9546 if (kvm_mpx_supported()) 9547 kvm_put_guest_fpu(vcpu); 9548 vcpu_put(vcpu); 9549 return 0; 9550 } 9551 9552 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 9553 struct kvm_mp_state *mp_state) 9554 { 9555 int ret = -EINVAL; 9556 9557 vcpu_load(vcpu); 9558 9559 if (!lapic_in_kernel(vcpu) && 9560 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 9561 goto out; 9562 9563 /* 9564 * KVM_MP_STATE_INIT_RECEIVED means the processor is in 9565 * INIT state; latched init should be reported using 9566 * KVM_SET_VCPU_EVENTS, so reject it here. 9567 */ 9568 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && 9569 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 9570 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 9571 goto out; 9572 9573 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 9574 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 9575 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 9576 } else 9577 vcpu->arch.mp_state = mp_state->mp_state; 9578 kvm_make_request(KVM_REQ_EVENT, vcpu); 9579 9580 ret = 0; 9581 out: 9582 vcpu_put(vcpu); 9583 return ret; 9584 } 9585 9586 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 9587 int reason, bool has_error_code, u32 error_code) 9588 { 9589 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 9590 int ret; 9591 9592 init_emulate_ctxt(vcpu); 9593 9594 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 9595 has_error_code, error_code); 9596 if (ret) { 9597 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 9598 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 9599 vcpu->run->internal.ndata = 0; 9600 return 0; 9601 } 9602 9603 kvm_rip_write(vcpu, ctxt->eip); 9604 kvm_set_rflags(vcpu, ctxt->eflags); 9605 return 1; 9606 } 9607 EXPORT_SYMBOL_GPL(kvm_task_switch); 9608 9609 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 9610 { 9611 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 9612 /* 9613 * When EFER.LME and CR0.PG are set, the processor is in 9614 * 64-bit mode (though maybe in a 32-bit code segment). 9615 * CR4.PAE and EFER.LMA must be set. 9616 */ 9617 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) 9618 return false; 9619 } else { 9620 /* 9621 * Not in 64-bit mode: EFER.LMA is clear and the code 9622 * segment cannot be 64-bit. 9623 */ 9624 if (sregs->efer & EFER_LMA || sregs->cs.l) 9625 return false; 9626 } 9627 9628 return kvm_is_valid_cr4(vcpu, sregs->cr4); 9629 } 9630 9631 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 9632 { 9633 struct msr_data apic_base_msr; 9634 int mmu_reset_needed = 0; 9635 int pending_vec, max_bits, idx; 9636 struct desc_ptr dt; 9637 int ret = -EINVAL; 9638 9639 if (!kvm_is_valid_sregs(vcpu, sregs)) 9640 goto out; 9641 9642 apic_base_msr.data = sregs->apic_base; 9643 apic_base_msr.host_initiated = true; 9644 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 9645 goto out; 9646 9647 if (vcpu->arch.guest_state_protected) 9648 goto skip_protected_regs; 9649 9650 dt.size = sregs->idt.limit; 9651 dt.address = sregs->idt.base; 9652 kvm_x86_ops.set_idt(vcpu, &dt); 9653 dt.size = sregs->gdt.limit; 9654 dt.address = sregs->gdt.base; 9655 kvm_x86_ops.set_gdt(vcpu, &dt); 9656 9657 vcpu->arch.cr2 = sregs->cr2; 9658 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 9659 vcpu->arch.cr3 = sregs->cr3; 9660 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 9661 9662 kvm_set_cr8(vcpu, sregs->cr8); 9663 9664 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 9665 kvm_x86_ops.set_efer(vcpu, sregs->efer); 9666 9667 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 9668 kvm_x86_ops.set_cr0(vcpu, sregs->cr0); 9669 vcpu->arch.cr0 = sregs->cr0; 9670 9671 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 9672 kvm_x86_ops.set_cr4(vcpu, sregs->cr4); 9673 9674 idx = srcu_read_lock(&vcpu->kvm->srcu); 9675 if (is_pae_paging(vcpu)) { 9676 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 9677 mmu_reset_needed = 1; 9678 } 9679 srcu_read_unlock(&vcpu->kvm->srcu, idx); 9680 9681 if (mmu_reset_needed) 9682 kvm_mmu_reset_context(vcpu); 9683 9684 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 9685 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 9686 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 9687 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 9688 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 9689 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 9690 9691 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 9692 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 9693 9694 update_cr8_intercept(vcpu); 9695 9696 /* Older userspace won't unhalt the vcpu on reset. */ 9697 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 9698 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 9699 !is_protmode(vcpu)) 9700 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 9701 9702 skip_protected_regs: 9703 max_bits = KVM_NR_INTERRUPTS; 9704 pending_vec = find_first_bit( 9705 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 9706 if (pending_vec < max_bits) { 9707 kvm_queue_interrupt(vcpu, pending_vec, false); 9708 pr_debug("Set back pending irq %d\n", pending_vec); 9709 } 9710 9711 kvm_make_request(KVM_REQ_EVENT, vcpu); 9712 9713 ret = 0; 9714 out: 9715 return ret; 9716 } 9717 9718 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 9719 struct kvm_sregs *sregs) 9720 { 9721 int ret; 9722 9723 vcpu_load(vcpu); 9724 ret = __set_sregs(vcpu, sregs); 9725 vcpu_put(vcpu); 9726 return ret; 9727 } 9728 9729 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 9730 struct kvm_guest_debug *dbg) 9731 { 9732 unsigned long rflags; 9733 int i, r; 9734 9735 if (vcpu->arch.guest_state_protected) 9736 return -EINVAL; 9737 9738 vcpu_load(vcpu); 9739 9740 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 9741 r = -EBUSY; 9742 if (vcpu->arch.exception.pending) 9743 goto out; 9744 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 9745 kvm_queue_exception(vcpu, DB_VECTOR); 9746 else 9747 kvm_queue_exception(vcpu, BP_VECTOR); 9748 } 9749 9750 /* 9751 * Read rflags as long as potentially injected trace flags are still 9752 * filtered out. 9753 */ 9754 rflags = kvm_get_rflags(vcpu); 9755 9756 vcpu->guest_debug = dbg->control; 9757 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 9758 vcpu->guest_debug = 0; 9759 9760 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 9761 for (i = 0; i < KVM_NR_DB_REGS; ++i) 9762 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 9763 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 9764 } else { 9765 for (i = 0; i < KVM_NR_DB_REGS; i++) 9766 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 9767 } 9768 kvm_update_dr7(vcpu); 9769 9770 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 9771 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 9772 get_segment_base(vcpu, VCPU_SREG_CS); 9773 9774 /* 9775 * Trigger an rflags update that will inject or remove the trace 9776 * flags. 9777 */ 9778 kvm_set_rflags(vcpu, rflags); 9779 9780 kvm_x86_ops.update_exception_bitmap(vcpu); 9781 9782 r = 0; 9783 9784 out: 9785 vcpu_put(vcpu); 9786 return r; 9787 } 9788 9789 /* 9790 * Translate a guest virtual address to a guest physical address. 9791 */ 9792 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 9793 struct kvm_translation *tr) 9794 { 9795 unsigned long vaddr = tr->linear_address; 9796 gpa_t gpa; 9797 int idx; 9798 9799 vcpu_load(vcpu); 9800 9801 idx = srcu_read_lock(&vcpu->kvm->srcu); 9802 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 9803 srcu_read_unlock(&vcpu->kvm->srcu, idx); 9804 tr->physical_address = gpa; 9805 tr->valid = gpa != UNMAPPED_GVA; 9806 tr->writeable = 1; 9807 tr->usermode = 0; 9808 9809 vcpu_put(vcpu); 9810 return 0; 9811 } 9812 9813 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 9814 { 9815 struct fxregs_state *fxsave; 9816 9817 if (!vcpu->arch.guest_fpu) 9818 return 0; 9819 9820 vcpu_load(vcpu); 9821 9822 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 9823 memcpy(fpu->fpr, fxsave->st_space, 128); 9824 fpu->fcw = fxsave->cwd; 9825 fpu->fsw = fxsave->swd; 9826 fpu->ftwx = fxsave->twd; 9827 fpu->last_opcode = fxsave->fop; 9828 fpu->last_ip = fxsave->rip; 9829 fpu->last_dp = fxsave->rdp; 9830 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 9831 9832 vcpu_put(vcpu); 9833 return 0; 9834 } 9835 9836 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 9837 { 9838 struct fxregs_state *fxsave; 9839 9840 if (!vcpu->arch.guest_fpu) 9841 return 0; 9842 9843 vcpu_load(vcpu); 9844 9845 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 9846 9847 memcpy(fxsave->st_space, fpu->fpr, 128); 9848 fxsave->cwd = fpu->fcw; 9849 fxsave->swd = fpu->fsw; 9850 fxsave->twd = fpu->ftwx; 9851 fxsave->fop = fpu->last_opcode; 9852 fxsave->rip = fpu->last_ip; 9853 fxsave->rdp = fpu->last_dp; 9854 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 9855 9856 vcpu_put(vcpu); 9857 return 0; 9858 } 9859 9860 static void store_regs(struct kvm_vcpu *vcpu) 9861 { 9862 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 9863 9864 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 9865 __get_regs(vcpu, &vcpu->run->s.regs.regs); 9866 9867 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 9868 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 9869 9870 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 9871 kvm_vcpu_ioctl_x86_get_vcpu_events( 9872 vcpu, &vcpu->run->s.regs.events); 9873 } 9874 9875 static int sync_regs(struct kvm_vcpu *vcpu) 9876 { 9877 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) 9878 return -EINVAL; 9879 9880 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 9881 __set_regs(vcpu, &vcpu->run->s.regs.regs); 9882 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 9883 } 9884 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 9885 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 9886 return -EINVAL; 9887 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 9888 } 9889 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 9890 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 9891 vcpu, &vcpu->run->s.regs.events)) 9892 return -EINVAL; 9893 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 9894 } 9895 9896 return 0; 9897 } 9898 9899 static void fx_init(struct kvm_vcpu *vcpu) 9900 { 9901 if (!vcpu->arch.guest_fpu) 9902 return; 9903 9904 fpstate_init(&vcpu->arch.guest_fpu->state); 9905 if (boot_cpu_has(X86_FEATURE_XSAVES)) 9906 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = 9907 host_xcr0 | XSTATE_COMPACTION_ENABLED; 9908 9909 /* 9910 * Ensure guest xcr0 is valid for loading 9911 */ 9912 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 9913 9914 vcpu->arch.cr0 |= X86_CR0_ET; 9915 } 9916 9917 void kvm_free_guest_fpu(struct kvm_vcpu *vcpu) 9918 { 9919 if (vcpu->arch.guest_fpu) { 9920 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); 9921 vcpu->arch.guest_fpu = NULL; 9922 } 9923 } 9924 EXPORT_SYMBOL_GPL(kvm_free_guest_fpu); 9925 9926 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 9927 { 9928 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 9929 pr_warn_once("kvm: SMP vm created on host with unstable TSC; " 9930 "guest TSC will not be reliable\n"); 9931 9932 return 0; 9933 } 9934 9935 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 9936 { 9937 struct page *page; 9938 int r; 9939 9940 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 9941 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 9942 else 9943 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 9944 9945 kvm_set_tsc_khz(vcpu, max_tsc_khz); 9946 9947 r = kvm_mmu_create(vcpu); 9948 if (r < 0) 9949 return r; 9950 9951 if (irqchip_in_kernel(vcpu->kvm)) { 9952 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 9953 if (r < 0) 9954 goto fail_mmu_destroy; 9955 if (kvm_apicv_activated(vcpu->kvm)) 9956 vcpu->arch.apicv_active = true; 9957 } else 9958 static_key_slow_inc(&kvm_no_apic_vcpu); 9959 9960 r = -ENOMEM; 9961 9962 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 9963 if (!page) 9964 goto fail_free_lapic; 9965 vcpu->arch.pio_data = page_address(page); 9966 9967 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 9968 GFP_KERNEL_ACCOUNT); 9969 if (!vcpu->arch.mce_banks) 9970 goto fail_free_pio_data; 9971 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 9972 9973 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 9974 GFP_KERNEL_ACCOUNT)) 9975 goto fail_free_mce_banks; 9976 9977 if (!alloc_emulate_ctxt(vcpu)) 9978 goto free_wbinvd_dirty_mask; 9979 9980 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, 9981 GFP_KERNEL_ACCOUNT); 9982 if (!vcpu->arch.user_fpu) { 9983 pr_err("kvm: failed to allocate userspace's fpu\n"); 9984 goto free_emulate_ctxt; 9985 } 9986 9987 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, 9988 GFP_KERNEL_ACCOUNT); 9989 if (!vcpu->arch.guest_fpu) { 9990 pr_err("kvm: failed to allocate vcpu's fpu\n"); 9991 goto free_user_fpu; 9992 } 9993 fx_init(vcpu); 9994 9995 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 9996 9997 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 9998 9999 kvm_async_pf_hash_reset(vcpu); 10000 kvm_pmu_init(vcpu); 10001 10002 vcpu->arch.pending_external_vector = -1; 10003 vcpu->arch.preempted_in_kernel = false; 10004 10005 kvm_hv_vcpu_init(vcpu); 10006 10007 r = kvm_x86_ops.vcpu_create(vcpu); 10008 if (r) 10009 goto free_guest_fpu; 10010 10011 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 10012 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 10013 kvm_vcpu_mtrr_init(vcpu); 10014 vcpu_load(vcpu); 10015 kvm_vcpu_reset(vcpu, false); 10016 kvm_init_mmu(vcpu, false); 10017 vcpu_put(vcpu); 10018 return 0; 10019 10020 free_guest_fpu: 10021 kvm_free_guest_fpu(vcpu); 10022 free_user_fpu: 10023 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); 10024 free_emulate_ctxt: 10025 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 10026 free_wbinvd_dirty_mask: 10027 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 10028 fail_free_mce_banks: 10029 kfree(vcpu->arch.mce_banks); 10030 fail_free_pio_data: 10031 free_page((unsigned long)vcpu->arch.pio_data); 10032 fail_free_lapic: 10033 kvm_free_lapic(vcpu); 10034 fail_mmu_destroy: 10035 kvm_mmu_destroy(vcpu); 10036 return r; 10037 } 10038 10039 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 10040 { 10041 struct kvm *kvm = vcpu->kvm; 10042 10043 kvm_hv_vcpu_postcreate(vcpu); 10044 10045 if (mutex_lock_killable(&vcpu->mutex)) 10046 return; 10047 vcpu_load(vcpu); 10048 kvm_synchronize_tsc(vcpu, 0); 10049 vcpu_put(vcpu); 10050 10051 /* poll control enabled by default */ 10052 vcpu->arch.msr_kvm_poll_control = 1; 10053 10054 mutex_unlock(&vcpu->mutex); 10055 10056 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) 10057 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 10058 KVMCLOCK_SYNC_PERIOD); 10059 } 10060 10061 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 10062 { 10063 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; 10064 int idx; 10065 10066 kvm_release_pfn(cache->pfn, cache->dirty, cache); 10067 10068 kvmclock_reset(vcpu); 10069 10070 kvm_x86_ops.vcpu_free(vcpu); 10071 10072 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 10073 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 10074 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); 10075 kvm_free_guest_fpu(vcpu); 10076 10077 kvm_hv_vcpu_uninit(vcpu); 10078 kvm_pmu_destroy(vcpu); 10079 kfree(vcpu->arch.mce_banks); 10080 kvm_free_lapic(vcpu); 10081 idx = srcu_read_lock(&vcpu->kvm->srcu); 10082 kvm_mmu_destroy(vcpu); 10083 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10084 free_page((unsigned long)vcpu->arch.pio_data); 10085 kvfree(vcpu->arch.cpuid_entries); 10086 if (!lapic_in_kernel(vcpu)) 10087 static_key_slow_dec(&kvm_no_apic_vcpu); 10088 } 10089 10090 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 10091 { 10092 kvm_lapic_reset(vcpu, init_event); 10093 10094 vcpu->arch.hflags = 0; 10095 10096 vcpu->arch.smi_pending = 0; 10097 vcpu->arch.smi_count = 0; 10098 atomic_set(&vcpu->arch.nmi_queued, 0); 10099 vcpu->arch.nmi_pending = 0; 10100 vcpu->arch.nmi_injected = false; 10101 kvm_clear_interrupt_queue(vcpu); 10102 kvm_clear_exception_queue(vcpu); 10103 10104 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 10105 kvm_update_dr0123(vcpu); 10106 vcpu->arch.dr6 = DR6_INIT; 10107 vcpu->arch.dr7 = DR7_FIXED_1; 10108 kvm_update_dr7(vcpu); 10109 10110 vcpu->arch.cr2 = 0; 10111 10112 kvm_make_request(KVM_REQ_EVENT, vcpu); 10113 vcpu->arch.apf.msr_en_val = 0; 10114 vcpu->arch.apf.msr_int_val = 0; 10115 vcpu->arch.st.msr_val = 0; 10116 10117 kvmclock_reset(vcpu); 10118 10119 kvm_clear_async_pf_completion_queue(vcpu); 10120 kvm_async_pf_hash_reset(vcpu); 10121 vcpu->arch.apf.halted = false; 10122 10123 if (vcpu->arch.guest_fpu && kvm_mpx_supported()) { 10124 void *mpx_state_buffer; 10125 10126 /* 10127 * To avoid have the INIT path from kvm_apic_has_events() that be 10128 * called with loaded FPU and does not let userspace fix the state. 10129 */ 10130 if (init_event) 10131 kvm_put_guest_fpu(vcpu); 10132 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 10133 XFEATURE_BNDREGS); 10134 if (mpx_state_buffer) 10135 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); 10136 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 10137 XFEATURE_BNDCSR); 10138 if (mpx_state_buffer) 10139 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); 10140 if (init_event) 10141 kvm_load_guest_fpu(vcpu); 10142 } 10143 10144 if (!init_event) { 10145 kvm_pmu_reset(vcpu); 10146 vcpu->arch.smbase = 0x30000; 10147 10148 vcpu->arch.msr_misc_features_enables = 0; 10149 10150 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 10151 } 10152 10153 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 10154 vcpu->arch.regs_avail = ~0; 10155 vcpu->arch.regs_dirty = ~0; 10156 10157 vcpu->arch.ia32_xss = 0; 10158 10159 kvm_x86_ops.vcpu_reset(vcpu, init_event); 10160 } 10161 10162 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 10163 { 10164 struct kvm_segment cs; 10165 10166 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 10167 cs.selector = vector << 8; 10168 cs.base = vector << 12; 10169 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 10170 kvm_rip_write(vcpu, 0); 10171 } 10172 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); 10173 10174 int kvm_arch_hardware_enable(void) 10175 { 10176 struct kvm *kvm; 10177 struct kvm_vcpu *vcpu; 10178 int i; 10179 int ret; 10180 u64 local_tsc; 10181 u64 max_tsc = 0; 10182 bool stable, backwards_tsc = false; 10183 10184 kvm_user_return_msr_cpu_online(); 10185 ret = kvm_x86_ops.hardware_enable(); 10186 if (ret != 0) 10187 return ret; 10188 10189 local_tsc = rdtsc(); 10190 stable = !kvm_check_tsc_unstable(); 10191 list_for_each_entry(kvm, &vm_list, vm_list) { 10192 kvm_for_each_vcpu(i, vcpu, kvm) { 10193 if (!stable && vcpu->cpu == smp_processor_id()) 10194 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 10195 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 10196 backwards_tsc = true; 10197 if (vcpu->arch.last_host_tsc > max_tsc) 10198 max_tsc = vcpu->arch.last_host_tsc; 10199 } 10200 } 10201 } 10202 10203 /* 10204 * Sometimes, even reliable TSCs go backwards. This happens on 10205 * platforms that reset TSC during suspend or hibernate actions, but 10206 * maintain synchronization. We must compensate. Fortunately, we can 10207 * detect that condition here, which happens early in CPU bringup, 10208 * before any KVM threads can be running. Unfortunately, we can't 10209 * bring the TSCs fully up to date with real time, as we aren't yet far 10210 * enough into CPU bringup that we know how much real time has actually 10211 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot 10212 * variables that haven't been updated yet. 10213 * 10214 * So we simply find the maximum observed TSC above, then record the 10215 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 10216 * the adjustment will be applied. Note that we accumulate 10217 * adjustments, in case multiple suspend cycles happen before some VCPU 10218 * gets a chance to run again. In the event that no KVM threads get a 10219 * chance to run, we will miss the entire elapsed period, as we'll have 10220 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 10221 * loose cycle time. This isn't too big a deal, since the loss will be 10222 * uniform across all VCPUs (not to mention the scenario is extremely 10223 * unlikely). It is possible that a second hibernate recovery happens 10224 * much faster than a first, causing the observed TSC here to be 10225 * smaller; this would require additional padding adjustment, which is 10226 * why we set last_host_tsc to the local tsc observed here. 10227 * 10228 * N.B. - this code below runs only on platforms with reliable TSC, 10229 * as that is the only way backwards_tsc is set above. Also note 10230 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 10231 * have the same delta_cyc adjustment applied if backwards_tsc 10232 * is detected. Note further, this adjustment is only done once, 10233 * as we reset last_host_tsc on all VCPUs to stop this from being 10234 * called multiple times (one for each physical CPU bringup). 10235 * 10236 * Platforms with unreliable TSCs don't have to deal with this, they 10237 * will be compensated by the logic in vcpu_load, which sets the TSC to 10238 * catchup mode. This will catchup all VCPUs to real time, but cannot 10239 * guarantee that they stay in perfect synchronization. 10240 */ 10241 if (backwards_tsc) { 10242 u64 delta_cyc = max_tsc - local_tsc; 10243 list_for_each_entry(kvm, &vm_list, vm_list) { 10244 kvm->arch.backwards_tsc_observed = true; 10245 kvm_for_each_vcpu(i, vcpu, kvm) { 10246 vcpu->arch.tsc_offset_adjustment += delta_cyc; 10247 vcpu->arch.last_host_tsc = local_tsc; 10248 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 10249 } 10250 10251 /* 10252 * We have to disable TSC offset matching.. if you were 10253 * booting a VM while issuing an S4 host suspend.... 10254 * you may have some problem. Solving this issue is 10255 * left as an exercise to the reader. 10256 */ 10257 kvm->arch.last_tsc_nsec = 0; 10258 kvm->arch.last_tsc_write = 0; 10259 } 10260 10261 } 10262 return 0; 10263 } 10264 10265 void kvm_arch_hardware_disable(void) 10266 { 10267 kvm_x86_ops.hardware_disable(); 10268 drop_user_return_notifiers(); 10269 } 10270 10271 int kvm_arch_hardware_setup(void *opaque) 10272 { 10273 struct kvm_x86_init_ops *ops = opaque; 10274 int r; 10275 10276 rdmsrl_safe(MSR_EFER, &host_efer); 10277 10278 if (boot_cpu_has(X86_FEATURE_XSAVES)) 10279 rdmsrl(MSR_IA32_XSS, host_xss); 10280 10281 r = ops->hardware_setup(); 10282 if (r != 0) 10283 return r; 10284 10285 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); 10286 10287 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) 10288 supported_xss = 0; 10289 10290 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) 10291 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); 10292 #undef __kvm_cpu_cap_has 10293 10294 if (kvm_has_tsc_control) { 10295 /* 10296 * Make sure the user can only configure tsc_khz values that 10297 * fit into a signed integer. 10298 * A min value is not calculated because it will always 10299 * be 1 on all machines. 10300 */ 10301 u64 max = min(0x7fffffffULL, 10302 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 10303 kvm_max_guest_tsc_khz = max; 10304 10305 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 10306 } 10307 10308 kvm_init_msr_list(); 10309 return 0; 10310 } 10311 10312 void kvm_arch_hardware_unsetup(void) 10313 { 10314 kvm_x86_ops.hardware_unsetup(); 10315 } 10316 10317 int kvm_arch_check_processor_compat(void *opaque) 10318 { 10319 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 10320 struct kvm_x86_init_ops *ops = opaque; 10321 10322 WARN_ON(!irqs_disabled()); 10323 10324 if (__cr4_reserved_bits(cpu_has, c) != 10325 __cr4_reserved_bits(cpu_has, &boot_cpu_data)) 10326 return -EIO; 10327 10328 return ops->check_processor_compatibility(); 10329 } 10330 10331 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 10332 { 10333 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 10334 } 10335 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 10336 10337 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 10338 { 10339 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 10340 } 10341 10342 struct static_key kvm_no_apic_vcpu __read_mostly; 10343 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); 10344 10345 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 10346 { 10347 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 10348 10349 vcpu->arch.l1tf_flush_l1d = true; 10350 if (pmu->version && unlikely(pmu->event_count)) { 10351 pmu->need_cleanup = true; 10352 kvm_make_request(KVM_REQ_PMU, vcpu); 10353 } 10354 kvm_x86_ops.sched_in(vcpu, cpu); 10355 } 10356 10357 void kvm_arch_free_vm(struct kvm *kvm) 10358 { 10359 kfree(kvm->arch.hyperv.hv_pa_pg); 10360 vfree(kvm); 10361 } 10362 10363 10364 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 10365 { 10366 if (type) 10367 return -EINVAL; 10368 10369 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 10370 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 10371 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 10372 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); 10373 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 10374 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 10375 10376 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 10377 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 10378 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 10379 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 10380 &kvm->arch.irq_sources_bitmap); 10381 10382 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 10383 mutex_init(&kvm->arch.apic_map_lock); 10384 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 10385 10386 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); 10387 pvclock_update_vm_gtod_copy(kvm); 10388 10389 kvm->arch.guest_can_read_msr_platform_info = true; 10390 10391 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 10392 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 10393 10394 kvm_hv_init_vm(kvm); 10395 kvm_page_track_init(kvm); 10396 kvm_mmu_init_vm(kvm); 10397 10398 return kvm_x86_ops.vm_init(kvm); 10399 } 10400 10401 int kvm_arch_post_init_vm(struct kvm *kvm) 10402 { 10403 return kvm_mmu_post_init_vm(kvm); 10404 } 10405 10406 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 10407 { 10408 vcpu_load(vcpu); 10409 kvm_mmu_unload(vcpu); 10410 vcpu_put(vcpu); 10411 } 10412 10413 static void kvm_free_vcpus(struct kvm *kvm) 10414 { 10415 unsigned int i; 10416 struct kvm_vcpu *vcpu; 10417 10418 /* 10419 * Unpin any mmu pages first. 10420 */ 10421 kvm_for_each_vcpu(i, vcpu, kvm) { 10422 kvm_clear_async_pf_completion_queue(vcpu); 10423 kvm_unload_vcpu_mmu(vcpu); 10424 } 10425 kvm_for_each_vcpu(i, vcpu, kvm) 10426 kvm_vcpu_destroy(vcpu); 10427 10428 mutex_lock(&kvm->lock); 10429 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 10430 kvm->vcpus[i] = NULL; 10431 10432 atomic_set(&kvm->online_vcpus, 0); 10433 mutex_unlock(&kvm->lock); 10434 } 10435 10436 void kvm_arch_sync_events(struct kvm *kvm) 10437 { 10438 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 10439 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 10440 kvm_free_pit(kvm); 10441 } 10442 10443 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) 10444 10445 /** 10446 * __x86_set_memory_region: Setup KVM internal memory slot 10447 * 10448 * @kvm: the kvm pointer to the VM. 10449 * @id: the slot ID to setup. 10450 * @gpa: the GPA to install the slot (unused when @size == 0). 10451 * @size: the size of the slot. Set to zero to uninstall a slot. 10452 * 10453 * This function helps to setup a KVM internal memory slot. Specify 10454 * @size > 0 to install a new slot, while @size == 0 to uninstall a 10455 * slot. The return code can be one of the following: 10456 * 10457 * HVA: on success (uninstall will return a bogus HVA) 10458 * -errno: on error 10459 * 10460 * The caller should always use IS_ERR() to check the return value 10461 * before use. Note, the KVM internal memory slots are guaranteed to 10462 * remain valid and unchanged until the VM is destroyed, i.e., the 10463 * GPA->HVA translation will not change. However, the HVA is a user 10464 * address, i.e. its accessibility is not guaranteed, and must be 10465 * accessed via __copy_{to,from}_user(). 10466 */ 10467 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, 10468 u32 size) 10469 { 10470 int i, r; 10471 unsigned long hva, old_npages; 10472 struct kvm_memslots *slots = kvm_memslots(kvm); 10473 struct kvm_memory_slot *slot; 10474 10475 /* Called with kvm->slots_lock held. */ 10476 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 10477 return ERR_PTR_USR(-EINVAL); 10478 10479 slot = id_to_memslot(slots, id); 10480 if (size) { 10481 if (slot && slot->npages) 10482 return ERR_PTR_USR(-EEXIST); 10483 10484 /* 10485 * MAP_SHARED to prevent internal slot pages from being moved 10486 * by fork()/COW. 10487 */ 10488 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 10489 MAP_SHARED | MAP_ANONYMOUS, 0); 10490 if (IS_ERR((void *)hva)) 10491 return (void __user *)hva; 10492 } else { 10493 if (!slot || !slot->npages) 10494 return 0; 10495 10496 old_npages = slot->npages; 10497 hva = 0; 10498 } 10499 10500 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 10501 struct kvm_userspace_memory_region m; 10502 10503 m.slot = id | (i << 16); 10504 m.flags = 0; 10505 m.guest_phys_addr = gpa; 10506 m.userspace_addr = hva; 10507 m.memory_size = size; 10508 r = __kvm_set_memory_region(kvm, &m); 10509 if (r < 0) 10510 return ERR_PTR_USR(r); 10511 } 10512 10513 if (!size) 10514 vm_munmap(hva, old_npages * PAGE_SIZE); 10515 10516 return (void __user *)hva; 10517 } 10518 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 10519 10520 void kvm_arch_pre_destroy_vm(struct kvm *kvm) 10521 { 10522 kvm_mmu_pre_destroy_vm(kvm); 10523 } 10524 10525 void kvm_arch_destroy_vm(struct kvm *kvm) 10526 { 10527 u32 i; 10528 10529 if (current->mm == kvm->mm) { 10530 /* 10531 * Free memory regions allocated on behalf of userspace, 10532 * unless the the memory map has changed due to process exit 10533 * or fd copying. 10534 */ 10535 mutex_lock(&kvm->slots_lock); 10536 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 10537 0, 0); 10538 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 10539 0, 0); 10540 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 10541 mutex_unlock(&kvm->slots_lock); 10542 } 10543 if (kvm_x86_ops.vm_destroy) 10544 kvm_x86_ops.vm_destroy(kvm); 10545 for (i = 0; i < kvm->arch.msr_filter.count; i++) 10546 kfree(kvm->arch.msr_filter.ranges[i].bitmap); 10547 kvm_pic_destroy(kvm); 10548 kvm_ioapic_destroy(kvm); 10549 kvm_free_vcpus(kvm); 10550 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 10551 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); 10552 kvm_mmu_uninit_vm(kvm); 10553 kvm_page_track_cleanup(kvm); 10554 kvm_hv_destroy_vm(kvm); 10555 } 10556 10557 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) 10558 { 10559 int i; 10560 10561 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 10562 kvfree(slot->arch.rmap[i]); 10563 slot->arch.rmap[i] = NULL; 10564 10565 if (i == 0) 10566 continue; 10567 10568 kvfree(slot->arch.lpage_info[i - 1]); 10569 slot->arch.lpage_info[i - 1] = NULL; 10570 } 10571 10572 kvm_page_track_free_memslot(slot); 10573 } 10574 10575 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot, 10576 unsigned long npages) 10577 { 10578 int i; 10579 10580 /* 10581 * Clear out the previous array pointers for the KVM_MR_MOVE case. The 10582 * old arrays will be freed by __kvm_set_memory_region() if installing 10583 * the new memslot is successful. 10584 */ 10585 memset(&slot->arch, 0, sizeof(slot->arch)); 10586 10587 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 10588 struct kvm_lpage_info *linfo; 10589 unsigned long ugfn; 10590 int lpages; 10591 int level = i + 1; 10592 10593 lpages = gfn_to_index(slot->base_gfn + npages - 1, 10594 slot->base_gfn, level) + 1; 10595 10596 slot->arch.rmap[i] = 10597 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), 10598 GFP_KERNEL_ACCOUNT); 10599 if (!slot->arch.rmap[i]) 10600 goto out_free; 10601 if (i == 0) 10602 continue; 10603 10604 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 10605 if (!linfo) 10606 goto out_free; 10607 10608 slot->arch.lpage_info[i - 1] = linfo; 10609 10610 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 10611 linfo[0].disallow_lpage = 1; 10612 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 10613 linfo[lpages - 1].disallow_lpage = 1; 10614 ugfn = slot->userspace_addr >> PAGE_SHIFT; 10615 /* 10616 * If the gfn and userspace address are not aligned wrt each 10617 * other, disable large page support for this slot. 10618 */ 10619 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { 10620 unsigned long j; 10621 10622 for (j = 0; j < lpages; ++j) 10623 linfo[j].disallow_lpage = 1; 10624 } 10625 } 10626 10627 if (kvm_page_track_create_memslot(slot, npages)) 10628 goto out_free; 10629 10630 return 0; 10631 10632 out_free: 10633 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 10634 kvfree(slot->arch.rmap[i]); 10635 slot->arch.rmap[i] = NULL; 10636 if (i == 0) 10637 continue; 10638 10639 kvfree(slot->arch.lpage_info[i - 1]); 10640 slot->arch.lpage_info[i - 1] = NULL; 10641 } 10642 return -ENOMEM; 10643 } 10644 10645 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 10646 { 10647 struct kvm_vcpu *vcpu; 10648 int i; 10649 10650 /* 10651 * memslots->generation has been incremented. 10652 * mmio generation may have reached its maximum value. 10653 */ 10654 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 10655 10656 /* Force re-initialization of steal_time cache */ 10657 kvm_for_each_vcpu(i, vcpu, kvm) 10658 kvm_vcpu_kick(vcpu); 10659 } 10660 10661 int kvm_arch_prepare_memory_region(struct kvm *kvm, 10662 struct kvm_memory_slot *memslot, 10663 const struct kvm_userspace_memory_region *mem, 10664 enum kvm_mr_change change) 10665 { 10666 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) 10667 return kvm_alloc_memslot_metadata(memslot, 10668 mem->memory_size >> PAGE_SHIFT); 10669 return 0; 10670 } 10671 10672 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 10673 struct kvm_memory_slot *old, 10674 struct kvm_memory_slot *new, 10675 enum kvm_mr_change change) 10676 { 10677 /* 10678 * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot. 10679 * See comments below. 10680 */ 10681 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) 10682 return; 10683 10684 /* 10685 * Dirty logging tracks sptes in 4k granularity, meaning that large 10686 * sptes have to be split. If live migration is successful, the guest 10687 * in the source machine will be destroyed and large sptes will be 10688 * created in the destination. However, if the guest continues to run 10689 * in the source machine (for example if live migration fails), small 10690 * sptes will remain around and cause bad performance. 10691 * 10692 * Scan sptes if dirty logging has been stopped, dropping those 10693 * which can be collapsed into a single large-page spte. Later 10694 * page faults will create the large-page sptes. 10695 * 10696 * There is no need to do this in any of the following cases: 10697 * CREATE: No dirty mappings will already exist. 10698 * MOVE/DELETE: The old mappings will already have been cleaned up by 10699 * kvm_arch_flush_shadow_memslot() 10700 */ 10701 if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 10702 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 10703 kvm_mmu_zap_collapsible_sptes(kvm, new); 10704 10705 /* 10706 * Enable or disable dirty logging for the slot. 10707 * 10708 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old 10709 * slot have been zapped so no dirty logging updates are needed for 10710 * the old slot. 10711 * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible 10712 * any mappings that might be created in it will consume the 10713 * properties of the new slot and do not need to be updated here. 10714 * 10715 * When PML is enabled, the kvm_x86_ops dirty logging hooks are 10716 * called to enable/disable dirty logging. 10717 * 10718 * When disabling dirty logging with PML enabled, the D-bit is set 10719 * for sptes in the slot in order to prevent unnecessary GPA 10720 * logging in the PML buffer (and potential PML buffer full VMEXIT). 10721 * This guarantees leaving PML enabled for the guest's lifetime 10722 * won't have any additional overhead from PML when the guest is 10723 * running with dirty logging disabled. 10724 * 10725 * When enabling dirty logging, large sptes are write-protected 10726 * so they can be split on first write. New large sptes cannot 10727 * be created for this slot until the end of the logging. 10728 * See the comments in fast_page_fault(). 10729 * For small sptes, nothing is done if the dirty log is in the 10730 * initial-all-set state. Otherwise, depending on whether pml 10731 * is enabled the D-bit or the W-bit will be cleared. 10732 */ 10733 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 10734 if (kvm_x86_ops.slot_enable_log_dirty) { 10735 kvm_x86_ops.slot_enable_log_dirty(kvm, new); 10736 } else { 10737 int level = 10738 kvm_dirty_log_manual_protect_and_init_set(kvm) ? 10739 PG_LEVEL_2M : PG_LEVEL_4K; 10740 10741 /* 10742 * If we're with initial-all-set, we don't need 10743 * to write protect any small page because 10744 * they're reported as dirty already. However 10745 * we still need to write-protect huge pages 10746 * so that the page split can happen lazily on 10747 * the first write to the huge page. 10748 */ 10749 kvm_mmu_slot_remove_write_access(kvm, new, level); 10750 } 10751 } else { 10752 if (kvm_x86_ops.slot_disable_log_dirty) 10753 kvm_x86_ops.slot_disable_log_dirty(kvm, new); 10754 } 10755 } 10756 10757 void kvm_arch_commit_memory_region(struct kvm *kvm, 10758 const struct kvm_userspace_memory_region *mem, 10759 struct kvm_memory_slot *old, 10760 const struct kvm_memory_slot *new, 10761 enum kvm_mr_change change) 10762 { 10763 if (!kvm->arch.n_requested_mmu_pages) 10764 kvm_mmu_change_mmu_pages(kvm, 10765 kvm_mmu_calculate_default_mmu_pages(kvm)); 10766 10767 /* 10768 * FIXME: const-ify all uses of struct kvm_memory_slot. 10769 */ 10770 kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change); 10771 10772 /* Free the arrays associated with the old memslot. */ 10773 if (change == KVM_MR_MOVE) 10774 kvm_arch_free_memslot(kvm, old); 10775 } 10776 10777 void kvm_arch_flush_shadow_all(struct kvm *kvm) 10778 { 10779 kvm_mmu_zap_all(kvm); 10780 } 10781 10782 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 10783 struct kvm_memory_slot *slot) 10784 { 10785 kvm_page_track_flush_slot(kvm, slot); 10786 } 10787 10788 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 10789 { 10790 return (is_guest_mode(vcpu) && 10791 kvm_x86_ops.guest_apic_has_interrupt && 10792 kvm_x86_ops.guest_apic_has_interrupt(vcpu)); 10793 } 10794 10795 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 10796 { 10797 if (!list_empty_careful(&vcpu->async_pf.done)) 10798 return true; 10799 10800 if (kvm_apic_has_events(vcpu)) 10801 return true; 10802 10803 if (vcpu->arch.pv.pv_unhalted) 10804 return true; 10805 10806 if (vcpu->arch.exception.pending) 10807 return true; 10808 10809 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 10810 (vcpu->arch.nmi_pending && 10811 kvm_x86_ops.nmi_allowed(vcpu, false))) 10812 return true; 10813 10814 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 10815 (vcpu->arch.smi_pending && 10816 kvm_x86_ops.smi_allowed(vcpu, false))) 10817 return true; 10818 10819 if (kvm_arch_interrupt_allowed(vcpu) && 10820 (kvm_cpu_has_interrupt(vcpu) || 10821 kvm_guest_apic_has_interrupt(vcpu))) 10822 return true; 10823 10824 if (kvm_hv_has_stimer_pending(vcpu)) 10825 return true; 10826 10827 if (is_guest_mode(vcpu) && 10828 kvm_x86_ops.nested_ops->hv_timer_pending && 10829 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 10830 return true; 10831 10832 return false; 10833 } 10834 10835 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 10836 { 10837 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 10838 } 10839 10840 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) 10841 { 10842 if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) 10843 return true; 10844 10845 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 10846 kvm_test_request(KVM_REQ_SMI, vcpu) || 10847 kvm_test_request(KVM_REQ_EVENT, vcpu)) 10848 return true; 10849 10850 if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu)) 10851 return true; 10852 10853 return false; 10854 } 10855 10856 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 10857 { 10858 return vcpu->arch.preempted_in_kernel; 10859 } 10860 10861 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 10862 { 10863 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 10864 } 10865 10866 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 10867 { 10868 return kvm_x86_ops.interrupt_allowed(vcpu, false); 10869 } 10870 10871 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 10872 { 10873 /* Can't read the RIP when guest state is protected, just return 0 */ 10874 if (vcpu->arch.guest_state_protected) 10875 return 0; 10876 10877 if (is_64_bit_mode(vcpu)) 10878 return kvm_rip_read(vcpu); 10879 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 10880 kvm_rip_read(vcpu)); 10881 } 10882 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 10883 10884 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 10885 { 10886 return kvm_get_linear_rip(vcpu) == linear_rip; 10887 } 10888 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 10889 10890 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 10891 { 10892 unsigned long rflags; 10893 10894 rflags = kvm_x86_ops.get_rflags(vcpu); 10895 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 10896 rflags &= ~X86_EFLAGS_TF; 10897 return rflags; 10898 } 10899 EXPORT_SYMBOL_GPL(kvm_get_rflags); 10900 10901 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 10902 { 10903 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 10904 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 10905 rflags |= X86_EFLAGS_TF; 10906 kvm_x86_ops.set_rflags(vcpu, rflags); 10907 } 10908 10909 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 10910 { 10911 __kvm_set_rflags(vcpu, rflags); 10912 kvm_make_request(KVM_REQ_EVENT, vcpu); 10913 } 10914 EXPORT_SYMBOL_GPL(kvm_set_rflags); 10915 10916 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 10917 { 10918 int r; 10919 10920 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || 10921 work->wakeup_all) 10922 return; 10923 10924 r = kvm_mmu_reload(vcpu); 10925 if (unlikely(r)) 10926 return; 10927 10928 if (!vcpu->arch.mmu->direct_map && 10929 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) 10930 return; 10931 10932 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); 10933 } 10934 10935 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 10936 { 10937 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); 10938 10939 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 10940 } 10941 10942 static inline u32 kvm_async_pf_next_probe(u32 key) 10943 { 10944 return (key + 1) & (ASYNC_PF_PER_VCPU - 1); 10945 } 10946 10947 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 10948 { 10949 u32 key = kvm_async_pf_hash_fn(gfn); 10950 10951 while (vcpu->arch.apf.gfns[key] != ~0) 10952 key = kvm_async_pf_next_probe(key); 10953 10954 vcpu->arch.apf.gfns[key] = gfn; 10955 } 10956 10957 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 10958 { 10959 int i; 10960 u32 key = kvm_async_pf_hash_fn(gfn); 10961 10962 for (i = 0; i < ASYNC_PF_PER_VCPU && 10963 (vcpu->arch.apf.gfns[key] != gfn && 10964 vcpu->arch.apf.gfns[key] != ~0); i++) 10965 key = kvm_async_pf_next_probe(key); 10966 10967 return key; 10968 } 10969 10970 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 10971 { 10972 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 10973 } 10974 10975 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 10976 { 10977 u32 i, j, k; 10978 10979 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 10980 10981 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) 10982 return; 10983 10984 while (true) { 10985 vcpu->arch.apf.gfns[i] = ~0; 10986 do { 10987 j = kvm_async_pf_next_probe(j); 10988 if (vcpu->arch.apf.gfns[j] == ~0) 10989 return; 10990 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 10991 /* 10992 * k lies cyclically in ]i,j] 10993 * | i.k.j | 10994 * |....j i.k.| or |.k..j i...| 10995 */ 10996 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 10997 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 10998 i = j; 10999 } 11000 } 11001 11002 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) 11003 { 11004 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; 11005 11006 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, 11007 sizeof(reason)); 11008 } 11009 11010 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) 11011 { 11012 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 11013 11014 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 11015 &token, offset, sizeof(token)); 11016 } 11017 11018 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) 11019 { 11020 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 11021 u32 val; 11022 11023 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 11024 &val, offset, sizeof(val))) 11025 return false; 11026 11027 return !val; 11028 } 11029 11030 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) 11031 { 11032 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) 11033 return false; 11034 11035 if (!kvm_pv_async_pf_enabled(vcpu) || 11036 (vcpu->arch.apf.send_user_only && kvm_x86_ops.get_cpl(vcpu) == 0)) 11037 return false; 11038 11039 return true; 11040 } 11041 11042 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) 11043 { 11044 if (unlikely(!lapic_in_kernel(vcpu) || 11045 kvm_event_needs_reinjection(vcpu) || 11046 vcpu->arch.exception.pending)) 11047 return false; 11048 11049 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) 11050 return false; 11051 11052 /* 11053 * If interrupts are off we cannot even use an artificial 11054 * halt state. 11055 */ 11056 return kvm_arch_interrupt_allowed(vcpu); 11057 } 11058 11059 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 11060 struct kvm_async_pf *work) 11061 { 11062 struct x86_exception fault; 11063 11064 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); 11065 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 11066 11067 if (kvm_can_deliver_async_pf(vcpu) && 11068 !apf_put_user_notpresent(vcpu)) { 11069 fault.vector = PF_VECTOR; 11070 fault.error_code_valid = true; 11071 fault.error_code = 0; 11072 fault.nested_page_fault = false; 11073 fault.address = work->arch.token; 11074 fault.async_page_fault = true; 11075 kvm_inject_page_fault(vcpu, &fault); 11076 return true; 11077 } else { 11078 /* 11079 * It is not possible to deliver a paravirtualized asynchronous 11080 * page fault, but putting the guest in an artificial halt state 11081 * can be beneficial nevertheless: if an interrupt arrives, we 11082 * can deliver it timely and perhaps the guest will schedule 11083 * another process. When the instruction that triggered a page 11084 * fault is retried, hopefully the page will be ready in the host. 11085 */ 11086 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 11087 return false; 11088 } 11089 } 11090 11091 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 11092 struct kvm_async_pf *work) 11093 { 11094 struct kvm_lapic_irq irq = { 11095 .delivery_mode = APIC_DM_FIXED, 11096 .vector = vcpu->arch.apf.vec 11097 }; 11098 11099 if (work->wakeup_all) 11100 work->arch.token = ~0; /* broadcast wakeup */ 11101 else 11102 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 11103 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); 11104 11105 if ((work->wakeup_all || work->notpresent_injected) && 11106 kvm_pv_async_pf_enabled(vcpu) && 11107 !apf_put_user_ready(vcpu, work->arch.token)) { 11108 vcpu->arch.apf.pageready_pending = true; 11109 kvm_apic_set_irq(vcpu, &irq, NULL); 11110 } 11111 11112 vcpu->arch.apf.halted = false; 11113 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 11114 } 11115 11116 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) 11117 { 11118 kvm_make_request(KVM_REQ_APF_READY, vcpu); 11119 if (!vcpu->arch.apf.pageready_pending) 11120 kvm_vcpu_kick(vcpu); 11121 } 11122 11123 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) 11124 { 11125 if (!kvm_pv_async_pf_enabled(vcpu)) 11126 return true; 11127 else 11128 return apf_pageready_slot_free(vcpu); 11129 } 11130 11131 void kvm_arch_start_assignment(struct kvm *kvm) 11132 { 11133 atomic_inc(&kvm->arch.assigned_device_count); 11134 } 11135 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 11136 11137 void kvm_arch_end_assignment(struct kvm *kvm) 11138 { 11139 atomic_dec(&kvm->arch.assigned_device_count); 11140 } 11141 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 11142 11143 bool kvm_arch_has_assigned_device(struct kvm *kvm) 11144 { 11145 return atomic_read(&kvm->arch.assigned_device_count); 11146 } 11147 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 11148 11149 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 11150 { 11151 atomic_inc(&kvm->arch.noncoherent_dma_count); 11152 } 11153 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 11154 11155 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 11156 { 11157 atomic_dec(&kvm->arch.noncoherent_dma_count); 11158 } 11159 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 11160 11161 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 11162 { 11163 return atomic_read(&kvm->arch.noncoherent_dma_count); 11164 } 11165 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 11166 11167 bool kvm_arch_has_irq_bypass(void) 11168 { 11169 return true; 11170 } 11171 11172 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 11173 struct irq_bypass_producer *prod) 11174 { 11175 struct kvm_kernel_irqfd *irqfd = 11176 container_of(cons, struct kvm_kernel_irqfd, consumer); 11177 int ret; 11178 11179 irqfd->producer = prod; 11180 kvm_arch_start_assignment(irqfd->kvm); 11181 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, 11182 prod->irq, irqfd->gsi, 1); 11183 11184 if (ret) 11185 kvm_arch_end_assignment(irqfd->kvm); 11186 11187 return ret; 11188 } 11189 11190 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 11191 struct irq_bypass_producer *prod) 11192 { 11193 int ret; 11194 struct kvm_kernel_irqfd *irqfd = 11195 container_of(cons, struct kvm_kernel_irqfd, consumer); 11196 11197 WARN_ON(irqfd->producer != prod); 11198 irqfd->producer = NULL; 11199 11200 /* 11201 * When producer of consumer is unregistered, we change back to 11202 * remapped mode, so we can re-use the current implementation 11203 * when the irq is masked/disabled or the consumer side (KVM 11204 * int this case doesn't want to receive the interrupts. 11205 */ 11206 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 11207 if (ret) 11208 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 11209 " fails: %d\n", irqfd->consumer.token, ret); 11210 11211 kvm_arch_end_assignment(irqfd->kvm); 11212 } 11213 11214 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 11215 uint32_t guest_irq, bool set) 11216 { 11217 return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set); 11218 } 11219 11220 bool kvm_vector_hashing_enabled(void) 11221 { 11222 return vector_hashing; 11223 } 11224 11225 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) 11226 { 11227 return (vcpu->arch.msr_kvm_poll_control & 1) == 0; 11228 } 11229 EXPORT_SYMBOL_GPL(kvm_arch_no_poll); 11230 11231 11232 int kvm_spec_ctrl_test_value(u64 value) 11233 { 11234 /* 11235 * test that setting IA32_SPEC_CTRL to given value 11236 * is allowed by the host processor 11237 */ 11238 11239 u64 saved_value; 11240 unsigned long flags; 11241 int ret = 0; 11242 11243 local_irq_save(flags); 11244 11245 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) 11246 ret = 1; 11247 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) 11248 ret = 1; 11249 else 11250 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); 11251 11252 local_irq_restore(flags); 11253 11254 return ret; 11255 } 11256 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); 11257 11258 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) 11259 { 11260 struct x86_exception fault; 11261 u32 access = error_code & 11262 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); 11263 11264 if (!(error_code & PFERR_PRESENT_MASK) || 11265 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) { 11266 /* 11267 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page 11268 * tables probably do not match the TLB. Just proceed 11269 * with the error code that the processor gave. 11270 */ 11271 fault.vector = PF_VECTOR; 11272 fault.error_code_valid = true; 11273 fault.error_code = error_code; 11274 fault.nested_page_fault = false; 11275 fault.address = gva; 11276 } 11277 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); 11278 } 11279 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); 11280 11281 /* 11282 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns 11283 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value 11284 * indicates whether exit to userspace is needed. 11285 */ 11286 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 11287 struct x86_exception *e) 11288 { 11289 if (r == X86EMUL_PROPAGATE_FAULT) { 11290 kvm_inject_emulated_page_fault(vcpu, e); 11291 return 1; 11292 } 11293 11294 /* 11295 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED 11296 * while handling a VMX instruction KVM could've handled the request 11297 * correctly by exiting to userspace and performing I/O but there 11298 * doesn't seem to be a real use-case behind such requests, just return 11299 * KVM_EXIT_INTERNAL_ERROR for now. 11300 */ 11301 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 11302 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 11303 vcpu->run->internal.ndata = 0; 11304 11305 return 0; 11306 } 11307 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); 11308 11309 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) 11310 { 11311 bool pcid_enabled; 11312 struct x86_exception e; 11313 unsigned i; 11314 unsigned long roots_to_free = 0; 11315 struct { 11316 u64 pcid; 11317 u64 gla; 11318 } operand; 11319 int r; 11320 11321 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 11322 if (r != X86EMUL_CONTINUE) 11323 return kvm_handle_memory_failure(vcpu, r, &e); 11324 11325 if (operand.pcid >> 12 != 0) { 11326 kvm_inject_gp(vcpu, 0); 11327 return 1; 11328 } 11329 11330 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 11331 11332 switch (type) { 11333 case INVPCID_TYPE_INDIV_ADDR: 11334 if ((!pcid_enabled && (operand.pcid != 0)) || 11335 is_noncanonical_address(operand.gla, vcpu)) { 11336 kvm_inject_gp(vcpu, 0); 11337 return 1; 11338 } 11339 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 11340 return kvm_skip_emulated_instruction(vcpu); 11341 11342 case INVPCID_TYPE_SINGLE_CTXT: 11343 if (!pcid_enabled && (operand.pcid != 0)) { 11344 kvm_inject_gp(vcpu, 0); 11345 return 1; 11346 } 11347 11348 if (kvm_get_active_pcid(vcpu) == operand.pcid) { 11349 kvm_mmu_sync_roots(vcpu); 11350 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 11351 } 11352 11353 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 11354 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd) 11355 == operand.pcid) 11356 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 11357 11358 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); 11359 /* 11360 * If neither the current cr3 nor any of the prev_roots use the 11361 * given PCID, then nothing needs to be done here because a 11362 * resync will happen anyway before switching to any other CR3. 11363 */ 11364 11365 return kvm_skip_emulated_instruction(vcpu); 11366 11367 case INVPCID_TYPE_ALL_NON_GLOBAL: 11368 /* 11369 * Currently, KVM doesn't mark global entries in the shadow 11370 * page tables, so a non-global flush just degenerates to a 11371 * global flush. If needed, we could optimize this later by 11372 * keeping track of global entries in shadow page tables. 11373 */ 11374 11375 fallthrough; 11376 case INVPCID_TYPE_ALL_INCL_GLOBAL: 11377 kvm_mmu_unload(vcpu); 11378 return kvm_skip_emulated_instruction(vcpu); 11379 11380 default: 11381 BUG(); /* We have already checked above that type <= 3 */ 11382 } 11383 } 11384 EXPORT_SYMBOL_GPL(kvm_handle_invpcid); 11385 11386 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) 11387 { 11388 struct kvm_run *run = vcpu->run; 11389 struct kvm_mmio_fragment *frag; 11390 unsigned int len; 11391 11392 BUG_ON(!vcpu->mmio_needed); 11393 11394 /* Complete previous fragment */ 11395 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 11396 len = min(8u, frag->len); 11397 if (!vcpu->mmio_is_write) 11398 memcpy(frag->data, run->mmio.data, len); 11399 11400 if (frag->len <= 8) { 11401 /* Switch to the next fragment. */ 11402 frag++; 11403 vcpu->mmio_cur_fragment++; 11404 } else { 11405 /* Go forward to the next mmio piece. */ 11406 frag->data += len; 11407 frag->gpa += len; 11408 frag->len -= len; 11409 } 11410 11411 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 11412 vcpu->mmio_needed = 0; 11413 11414 // VMG change, at this point, we're always done 11415 // RIP has already been advanced 11416 return 1; 11417 } 11418 11419 // More MMIO is needed 11420 run->mmio.phys_addr = frag->gpa; 11421 run->mmio.len = min(8u, frag->len); 11422 run->mmio.is_write = vcpu->mmio_is_write; 11423 if (run->mmio.is_write) 11424 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 11425 run->exit_reason = KVM_EXIT_MMIO; 11426 11427 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 11428 11429 return 0; 11430 } 11431 11432 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 11433 void *data) 11434 { 11435 int handled; 11436 struct kvm_mmio_fragment *frag; 11437 11438 if (!data) 11439 return -EINVAL; 11440 11441 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); 11442 if (handled == bytes) 11443 return 1; 11444 11445 bytes -= handled; 11446 gpa += handled; 11447 data += handled; 11448 11449 /*TODO: Check if need to increment number of frags */ 11450 frag = vcpu->mmio_fragments; 11451 vcpu->mmio_nr_fragments = 1; 11452 frag->len = bytes; 11453 frag->gpa = gpa; 11454 frag->data = data; 11455 11456 vcpu->mmio_needed = 1; 11457 vcpu->mmio_cur_fragment = 0; 11458 11459 vcpu->run->mmio.phys_addr = gpa; 11460 vcpu->run->mmio.len = min(8u, frag->len); 11461 vcpu->run->mmio.is_write = 1; 11462 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 11463 vcpu->run->exit_reason = KVM_EXIT_MMIO; 11464 11465 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 11466 11467 return 0; 11468 } 11469 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); 11470 11471 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 11472 void *data) 11473 { 11474 int handled; 11475 struct kvm_mmio_fragment *frag; 11476 11477 if (!data) 11478 return -EINVAL; 11479 11480 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); 11481 if (handled == bytes) 11482 return 1; 11483 11484 bytes -= handled; 11485 gpa += handled; 11486 data += handled; 11487 11488 /*TODO: Check if need to increment number of frags */ 11489 frag = vcpu->mmio_fragments; 11490 vcpu->mmio_nr_fragments = 1; 11491 frag->len = bytes; 11492 frag->gpa = gpa; 11493 frag->data = data; 11494 11495 vcpu->mmio_needed = 1; 11496 vcpu->mmio_cur_fragment = 0; 11497 11498 vcpu->run->mmio.phys_addr = gpa; 11499 vcpu->run->mmio.len = min(8u, frag->len); 11500 vcpu->run->mmio.is_write = 0; 11501 vcpu->run->exit_reason = KVM_EXIT_MMIO; 11502 11503 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 11504 11505 return 0; 11506 } 11507 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); 11508 11509 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 11510 { 11511 memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data, 11512 vcpu->arch.pio.count * vcpu->arch.pio.size); 11513 vcpu->arch.pio.count = 0; 11514 11515 return 1; 11516 } 11517 11518 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 11519 unsigned int port, void *data, unsigned int count) 11520 { 11521 int ret; 11522 11523 ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port, 11524 data, count); 11525 if (ret) 11526 return ret; 11527 11528 vcpu->arch.pio.count = 0; 11529 11530 return 0; 11531 } 11532 11533 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 11534 unsigned int port, void *data, unsigned int count) 11535 { 11536 int ret; 11537 11538 ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port, 11539 data, count); 11540 if (ret) { 11541 vcpu->arch.pio.count = 0; 11542 } else { 11543 vcpu->arch.guest_ins_data = data; 11544 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; 11545 } 11546 11547 return 0; 11548 } 11549 11550 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 11551 unsigned int port, void *data, unsigned int count, 11552 int in) 11553 { 11554 return in ? kvm_sev_es_ins(vcpu, size, port, data, count) 11555 : kvm_sev_es_outs(vcpu, size, port, data, count); 11556 } 11557 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); 11558 11559 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); 11560 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 11561 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 11562 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 11563 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 11564 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 11565 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 11566 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 11567 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 11568 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 11569 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 11570 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); 11571 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 11572 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 11573 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 11574 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 11575 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); 11576 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 11577 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 11578 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 11579 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 11580 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); 11581 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); 11582 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); 11583 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); 11584 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); 11585 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); 11586