1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "assigned-dev.h" 31 #include "pmu.h" 32 #include "hyperv.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/module.h> 40 #include <linux/mman.h> 41 #include <linux/highmem.h> 42 #include <linux/iommu.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/cpufreq.h> 45 #include <linux/user-return-notifier.h> 46 #include <linux/srcu.h> 47 #include <linux/slab.h> 48 #include <linux/perf_event.h> 49 #include <linux/uaccess.h> 50 #include <linux/hash.h> 51 #include <linux/pci.h> 52 #include <linux/timekeeper_internal.h> 53 #include <linux/pvclock_gtod.h> 54 #include <linux/kvm_irqfd.h> 55 #include <linux/irqbypass.h> 56 #include <trace/events/kvm.h> 57 58 #define CREATE_TRACE_POINTS 59 #include "trace.h" 60 61 #include <asm/debugreg.h> 62 #include <asm/msr.h> 63 #include <asm/desc.h> 64 #include <asm/mce.h> 65 #include <linux/kernel_stat.h> 66 #include <asm/fpu/internal.h> /* Ugh! */ 67 #include <asm/pvclock.h> 68 #include <asm/div64.h> 69 #include <asm/irq_remapping.h> 70 71 #define MAX_IO_MSRS 256 72 #define KVM_MAX_MCE_BANKS 32 73 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) 74 75 #define emul_to_vcpu(ctxt) \ 76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 77 78 /* EFER defaults: 79 * - enable syscall per default because its emulated by KVM 80 * - enable LME and LMA per default on 64 bit KVM 81 */ 82 #ifdef CONFIG_X86_64 83 static 84 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 85 #else 86 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 87 #endif 88 89 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 90 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 91 92 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 93 static void process_nmi(struct kvm_vcpu *vcpu); 94 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 95 96 struct kvm_x86_ops *kvm_x86_ops __read_mostly; 97 EXPORT_SYMBOL_GPL(kvm_x86_ops); 98 99 static bool __read_mostly ignore_msrs = 0; 100 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 101 102 unsigned int min_timer_period_us = 500; 103 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 104 105 static bool __read_mostly kvmclock_periodic_sync = true; 106 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 107 108 bool __read_mostly kvm_has_tsc_control; 109 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 110 u32 __read_mostly kvm_max_guest_tsc_khz; 111 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 112 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 113 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 114 u64 __read_mostly kvm_max_tsc_scaling_ratio; 115 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 116 static u64 __read_mostly kvm_default_tsc_scaling_ratio; 117 118 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 119 static u32 __read_mostly tsc_tolerance_ppm = 250; 120 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 121 122 /* lapic timer advance (tscdeadline mode only) in nanoseconds */ 123 unsigned int __read_mostly lapic_timer_advance_ns = 0; 124 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 125 126 static bool __read_mostly backwards_tsc_observed = false; 127 128 #define KVM_NR_SHARED_MSRS 16 129 130 struct kvm_shared_msrs_global { 131 int nr; 132 u32 msrs[KVM_NR_SHARED_MSRS]; 133 }; 134 135 struct kvm_shared_msrs { 136 struct user_return_notifier urn; 137 bool registered; 138 struct kvm_shared_msr_values { 139 u64 host; 140 u64 curr; 141 } values[KVM_NR_SHARED_MSRS]; 142 }; 143 144 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 145 static struct kvm_shared_msrs __percpu *shared_msrs; 146 147 struct kvm_stats_debugfs_item debugfs_entries[] = { 148 { "pf_fixed", VCPU_STAT(pf_fixed) }, 149 { "pf_guest", VCPU_STAT(pf_guest) }, 150 { "tlb_flush", VCPU_STAT(tlb_flush) }, 151 { "invlpg", VCPU_STAT(invlpg) }, 152 { "exits", VCPU_STAT(exits) }, 153 { "io_exits", VCPU_STAT(io_exits) }, 154 { "mmio_exits", VCPU_STAT(mmio_exits) }, 155 { "signal_exits", VCPU_STAT(signal_exits) }, 156 { "irq_window", VCPU_STAT(irq_window_exits) }, 157 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 158 { "halt_exits", VCPU_STAT(halt_exits) }, 159 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 160 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 161 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 162 { "hypercalls", VCPU_STAT(hypercalls) }, 163 { "request_irq", VCPU_STAT(request_irq_exits) }, 164 { "irq_exits", VCPU_STAT(irq_exits) }, 165 { "host_state_reload", VCPU_STAT(host_state_reload) }, 166 { "efer_reload", VCPU_STAT(efer_reload) }, 167 { "fpu_reload", VCPU_STAT(fpu_reload) }, 168 { "insn_emulation", VCPU_STAT(insn_emulation) }, 169 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 170 { "irq_injections", VCPU_STAT(irq_injections) }, 171 { "nmi_injections", VCPU_STAT(nmi_injections) }, 172 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 173 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 174 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 175 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 176 { "mmu_flooded", VM_STAT(mmu_flooded) }, 177 { "mmu_recycled", VM_STAT(mmu_recycled) }, 178 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 179 { "mmu_unsync", VM_STAT(mmu_unsync) }, 180 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 181 { "largepages", VM_STAT(lpages) }, 182 { NULL } 183 }; 184 185 u64 __read_mostly host_xcr0; 186 187 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 188 189 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 190 { 191 int i; 192 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 193 vcpu->arch.apf.gfns[i] = ~0; 194 } 195 196 static void kvm_on_user_return(struct user_return_notifier *urn) 197 { 198 unsigned slot; 199 struct kvm_shared_msrs *locals 200 = container_of(urn, struct kvm_shared_msrs, urn); 201 struct kvm_shared_msr_values *values; 202 203 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 204 values = &locals->values[slot]; 205 if (values->host != values->curr) { 206 wrmsrl(shared_msrs_global.msrs[slot], values->host); 207 values->curr = values->host; 208 } 209 } 210 locals->registered = false; 211 user_return_notifier_unregister(urn); 212 } 213 214 static void shared_msr_update(unsigned slot, u32 msr) 215 { 216 u64 value; 217 unsigned int cpu = smp_processor_id(); 218 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 219 220 /* only read, and nobody should modify it at this time, 221 * so don't need lock */ 222 if (slot >= shared_msrs_global.nr) { 223 printk(KERN_ERR "kvm: invalid MSR slot!"); 224 return; 225 } 226 rdmsrl_safe(msr, &value); 227 smsr->values[slot].host = value; 228 smsr->values[slot].curr = value; 229 } 230 231 void kvm_define_shared_msr(unsigned slot, u32 msr) 232 { 233 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 234 shared_msrs_global.msrs[slot] = msr; 235 if (slot >= shared_msrs_global.nr) 236 shared_msrs_global.nr = slot + 1; 237 } 238 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 239 240 static void kvm_shared_msr_cpu_online(void) 241 { 242 unsigned i; 243 244 for (i = 0; i < shared_msrs_global.nr; ++i) 245 shared_msr_update(i, shared_msrs_global.msrs[i]); 246 } 247 248 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 249 { 250 unsigned int cpu = smp_processor_id(); 251 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 252 int err; 253 254 if (((value ^ smsr->values[slot].curr) & mask) == 0) 255 return 0; 256 smsr->values[slot].curr = value; 257 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 258 if (err) 259 return 1; 260 261 if (!smsr->registered) { 262 smsr->urn.on_user_return = kvm_on_user_return; 263 user_return_notifier_register(&smsr->urn); 264 smsr->registered = true; 265 } 266 return 0; 267 } 268 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 269 270 static void drop_user_return_notifiers(void) 271 { 272 unsigned int cpu = smp_processor_id(); 273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 274 275 if (smsr->registered) 276 kvm_on_user_return(&smsr->urn); 277 } 278 279 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 280 { 281 return vcpu->arch.apic_base; 282 } 283 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 284 285 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 286 { 287 u64 old_state = vcpu->arch.apic_base & 288 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 289 u64 new_state = msr_info->data & 290 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 291 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 292 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); 293 294 if (!msr_info->host_initiated && 295 ((msr_info->data & reserved_bits) != 0 || 296 new_state == X2APIC_ENABLE || 297 (new_state == MSR_IA32_APICBASE_ENABLE && 298 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 299 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 300 old_state == 0))) 301 return 1; 302 303 kvm_lapic_set_base(vcpu, msr_info->data); 304 return 0; 305 } 306 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 307 308 asmlinkage __visible void kvm_spurious_fault(void) 309 { 310 /* Fault while not rebooting. We want the trace. */ 311 BUG(); 312 } 313 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 314 315 #define EXCPT_BENIGN 0 316 #define EXCPT_CONTRIBUTORY 1 317 #define EXCPT_PF 2 318 319 static int exception_class(int vector) 320 { 321 switch (vector) { 322 case PF_VECTOR: 323 return EXCPT_PF; 324 case DE_VECTOR: 325 case TS_VECTOR: 326 case NP_VECTOR: 327 case SS_VECTOR: 328 case GP_VECTOR: 329 return EXCPT_CONTRIBUTORY; 330 default: 331 break; 332 } 333 return EXCPT_BENIGN; 334 } 335 336 #define EXCPT_FAULT 0 337 #define EXCPT_TRAP 1 338 #define EXCPT_ABORT 2 339 #define EXCPT_INTERRUPT 3 340 341 static int exception_type(int vector) 342 { 343 unsigned int mask; 344 345 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 346 return EXCPT_INTERRUPT; 347 348 mask = 1 << vector; 349 350 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 351 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 352 return EXCPT_TRAP; 353 354 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 355 return EXCPT_ABORT; 356 357 /* Reserved exceptions will result in fault */ 358 return EXCPT_FAULT; 359 } 360 361 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 362 unsigned nr, bool has_error, u32 error_code, 363 bool reinject) 364 { 365 u32 prev_nr; 366 int class1, class2; 367 368 kvm_make_request(KVM_REQ_EVENT, vcpu); 369 370 if (!vcpu->arch.exception.pending) { 371 queue: 372 if (has_error && !is_protmode(vcpu)) 373 has_error = false; 374 vcpu->arch.exception.pending = true; 375 vcpu->arch.exception.has_error_code = has_error; 376 vcpu->arch.exception.nr = nr; 377 vcpu->arch.exception.error_code = error_code; 378 vcpu->arch.exception.reinject = reinject; 379 return; 380 } 381 382 /* to check exception */ 383 prev_nr = vcpu->arch.exception.nr; 384 if (prev_nr == DF_VECTOR) { 385 /* triple fault -> shutdown */ 386 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 387 return; 388 } 389 class1 = exception_class(prev_nr); 390 class2 = exception_class(nr); 391 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 392 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 393 /* generate double fault per SDM Table 5-5 */ 394 vcpu->arch.exception.pending = true; 395 vcpu->arch.exception.has_error_code = true; 396 vcpu->arch.exception.nr = DF_VECTOR; 397 vcpu->arch.exception.error_code = 0; 398 } else 399 /* replace previous exception with a new one in a hope 400 that instruction re-execution will regenerate lost 401 exception */ 402 goto queue; 403 } 404 405 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 406 { 407 kvm_multiple_exception(vcpu, nr, false, 0, false); 408 } 409 EXPORT_SYMBOL_GPL(kvm_queue_exception); 410 411 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 412 { 413 kvm_multiple_exception(vcpu, nr, false, 0, true); 414 } 415 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 416 417 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 418 { 419 if (err) 420 kvm_inject_gp(vcpu, 0); 421 else 422 kvm_x86_ops->skip_emulated_instruction(vcpu); 423 } 424 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 425 426 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 427 { 428 ++vcpu->stat.pf_guest; 429 vcpu->arch.cr2 = fault->address; 430 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 431 } 432 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 433 434 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 435 { 436 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 437 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 438 else 439 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 440 441 return fault->nested_page_fault; 442 } 443 444 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 445 { 446 atomic_inc(&vcpu->arch.nmi_queued); 447 kvm_make_request(KVM_REQ_NMI, vcpu); 448 } 449 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 450 451 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 452 { 453 kvm_multiple_exception(vcpu, nr, true, error_code, false); 454 } 455 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 456 457 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 458 { 459 kvm_multiple_exception(vcpu, nr, true, error_code, true); 460 } 461 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 462 463 /* 464 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 465 * a #GP and return false. 466 */ 467 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 468 { 469 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 470 return true; 471 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 472 return false; 473 } 474 EXPORT_SYMBOL_GPL(kvm_require_cpl); 475 476 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 477 { 478 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 479 return true; 480 481 kvm_queue_exception(vcpu, UD_VECTOR); 482 return false; 483 } 484 EXPORT_SYMBOL_GPL(kvm_require_dr); 485 486 /* 487 * This function will be used to read from the physical memory of the currently 488 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 489 * can read from guest physical or from the guest's guest physical memory. 490 */ 491 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 492 gfn_t ngfn, void *data, int offset, int len, 493 u32 access) 494 { 495 struct x86_exception exception; 496 gfn_t real_gfn; 497 gpa_t ngpa; 498 499 ngpa = gfn_to_gpa(ngfn); 500 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 501 if (real_gfn == UNMAPPED_GVA) 502 return -EFAULT; 503 504 real_gfn = gpa_to_gfn(real_gfn); 505 506 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 507 } 508 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 509 510 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 511 void *data, int offset, int len, u32 access) 512 { 513 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 514 data, offset, len, access); 515 } 516 517 /* 518 * Load the pae pdptrs. Return true is they are all valid. 519 */ 520 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 521 { 522 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 523 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 524 int i; 525 int ret; 526 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 527 528 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 529 offset * sizeof(u64), sizeof(pdpte), 530 PFERR_USER_MASK|PFERR_WRITE_MASK); 531 if (ret < 0) { 532 ret = 0; 533 goto out; 534 } 535 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 536 if (is_present_gpte(pdpte[i]) && 537 (pdpte[i] & 538 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) { 539 ret = 0; 540 goto out; 541 } 542 } 543 ret = 1; 544 545 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 546 __set_bit(VCPU_EXREG_PDPTR, 547 (unsigned long *)&vcpu->arch.regs_avail); 548 __set_bit(VCPU_EXREG_PDPTR, 549 (unsigned long *)&vcpu->arch.regs_dirty); 550 out: 551 552 return ret; 553 } 554 EXPORT_SYMBOL_GPL(load_pdptrs); 555 556 static bool pdptrs_changed(struct kvm_vcpu *vcpu) 557 { 558 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 559 bool changed = true; 560 int offset; 561 gfn_t gfn; 562 int r; 563 564 if (is_long_mode(vcpu) || !is_pae(vcpu)) 565 return false; 566 567 if (!test_bit(VCPU_EXREG_PDPTR, 568 (unsigned long *)&vcpu->arch.regs_avail)) 569 return true; 570 571 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; 572 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); 573 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 574 PFERR_USER_MASK | PFERR_WRITE_MASK); 575 if (r < 0) 576 goto out; 577 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 578 out: 579 580 return changed; 581 } 582 583 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 584 { 585 unsigned long old_cr0 = kvm_read_cr0(vcpu); 586 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 587 588 cr0 |= X86_CR0_ET; 589 590 #ifdef CONFIG_X86_64 591 if (cr0 & 0xffffffff00000000UL) 592 return 1; 593 #endif 594 595 cr0 &= ~CR0_RESERVED_BITS; 596 597 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 598 return 1; 599 600 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 601 return 1; 602 603 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 604 #ifdef CONFIG_X86_64 605 if ((vcpu->arch.efer & EFER_LME)) { 606 int cs_db, cs_l; 607 608 if (!is_pae(vcpu)) 609 return 1; 610 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 611 if (cs_l) 612 return 1; 613 } else 614 #endif 615 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 616 kvm_read_cr3(vcpu))) 617 return 1; 618 } 619 620 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 621 return 1; 622 623 kvm_x86_ops->set_cr0(vcpu, cr0); 624 625 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 626 kvm_clear_async_pf_completion_queue(vcpu); 627 kvm_async_pf_hash_reset(vcpu); 628 } 629 630 if ((cr0 ^ old_cr0) & update_bits) 631 kvm_mmu_reset_context(vcpu); 632 633 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 634 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 635 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 636 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 637 638 return 0; 639 } 640 EXPORT_SYMBOL_GPL(kvm_set_cr0); 641 642 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 643 { 644 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 645 } 646 EXPORT_SYMBOL_GPL(kvm_lmsw); 647 648 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 649 { 650 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 651 !vcpu->guest_xcr0_loaded) { 652 /* kvm_set_xcr() also depends on this */ 653 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 654 vcpu->guest_xcr0_loaded = 1; 655 } 656 } 657 658 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 659 { 660 if (vcpu->guest_xcr0_loaded) { 661 if (vcpu->arch.xcr0 != host_xcr0) 662 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 663 vcpu->guest_xcr0_loaded = 0; 664 } 665 } 666 667 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 668 { 669 u64 xcr0 = xcr; 670 u64 old_xcr0 = vcpu->arch.xcr0; 671 u64 valid_bits; 672 673 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 674 if (index != XCR_XFEATURE_ENABLED_MASK) 675 return 1; 676 if (!(xcr0 & XFEATURE_MASK_FP)) 677 return 1; 678 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 679 return 1; 680 681 /* 682 * Do not allow the guest to set bits that we do not support 683 * saving. However, xcr0 bit 0 is always set, even if the 684 * emulated CPU does not support XSAVE (see fx_init). 685 */ 686 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 687 if (xcr0 & ~valid_bits) 688 return 1; 689 690 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 691 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 692 return 1; 693 694 if (xcr0 & XFEATURE_MASK_AVX512) { 695 if (!(xcr0 & XFEATURE_MASK_YMM)) 696 return 1; 697 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 698 return 1; 699 } 700 kvm_put_guest_xcr0(vcpu); 701 vcpu->arch.xcr0 = xcr0; 702 703 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 704 kvm_update_cpuid(vcpu); 705 return 0; 706 } 707 708 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 709 { 710 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 711 __kvm_set_xcr(vcpu, index, xcr)) { 712 kvm_inject_gp(vcpu, 0); 713 return 1; 714 } 715 return 0; 716 } 717 EXPORT_SYMBOL_GPL(kvm_set_xcr); 718 719 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 720 { 721 unsigned long old_cr4 = kvm_read_cr4(vcpu); 722 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 723 X86_CR4_SMEP | X86_CR4_SMAP; 724 725 if (cr4 & CR4_RESERVED_BITS) 726 return 1; 727 728 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) 729 return 1; 730 731 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) 732 return 1; 733 734 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) 735 return 1; 736 737 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) 738 return 1; 739 740 if (is_long_mode(vcpu)) { 741 if (!(cr4 & X86_CR4_PAE)) 742 return 1; 743 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 744 && ((cr4 ^ old_cr4) & pdptr_bits) 745 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 746 kvm_read_cr3(vcpu))) 747 return 1; 748 749 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 750 if (!guest_cpuid_has_pcid(vcpu)) 751 return 1; 752 753 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 754 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 755 return 1; 756 } 757 758 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 759 return 1; 760 761 if (((cr4 ^ old_cr4) & pdptr_bits) || 762 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 763 kvm_mmu_reset_context(vcpu); 764 765 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) 766 kvm_update_cpuid(vcpu); 767 768 return 0; 769 } 770 EXPORT_SYMBOL_GPL(kvm_set_cr4); 771 772 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 773 { 774 #ifdef CONFIG_X86_64 775 cr3 &= ~CR3_PCID_INVD; 776 #endif 777 778 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 779 kvm_mmu_sync_roots(vcpu); 780 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 781 return 0; 782 } 783 784 if (is_long_mode(vcpu)) { 785 if (cr3 & CR3_L_MODE_RESERVED_BITS) 786 return 1; 787 } else if (is_pae(vcpu) && is_paging(vcpu) && 788 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 789 return 1; 790 791 vcpu->arch.cr3 = cr3; 792 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 793 kvm_mmu_new_cr3(vcpu); 794 return 0; 795 } 796 EXPORT_SYMBOL_GPL(kvm_set_cr3); 797 798 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 799 { 800 if (cr8 & CR8_RESERVED_BITS) 801 return 1; 802 if (lapic_in_kernel(vcpu)) 803 kvm_lapic_set_tpr(vcpu, cr8); 804 else 805 vcpu->arch.cr8 = cr8; 806 return 0; 807 } 808 EXPORT_SYMBOL_GPL(kvm_set_cr8); 809 810 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 811 { 812 if (lapic_in_kernel(vcpu)) 813 return kvm_lapic_get_cr8(vcpu); 814 else 815 return vcpu->arch.cr8; 816 } 817 EXPORT_SYMBOL_GPL(kvm_get_cr8); 818 819 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 820 { 821 int i; 822 823 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 824 for (i = 0; i < KVM_NR_DB_REGS; i++) 825 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 826 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 827 } 828 } 829 830 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 831 { 832 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 833 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 834 } 835 836 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 837 { 838 unsigned long dr7; 839 840 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 841 dr7 = vcpu->arch.guest_debug_dr7; 842 else 843 dr7 = vcpu->arch.dr7; 844 kvm_x86_ops->set_dr7(vcpu, dr7); 845 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 846 if (dr7 & DR7_BP_EN_MASK) 847 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 848 } 849 850 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 851 { 852 u64 fixed = DR6_FIXED_1; 853 854 if (!guest_cpuid_has_rtm(vcpu)) 855 fixed |= DR6_RTM; 856 return fixed; 857 } 858 859 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 860 { 861 switch (dr) { 862 case 0 ... 3: 863 vcpu->arch.db[dr] = val; 864 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 865 vcpu->arch.eff_db[dr] = val; 866 break; 867 case 4: 868 /* fall through */ 869 case 6: 870 if (val & 0xffffffff00000000ULL) 871 return -1; /* #GP */ 872 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 873 kvm_update_dr6(vcpu); 874 break; 875 case 5: 876 /* fall through */ 877 default: /* 7 */ 878 if (val & 0xffffffff00000000ULL) 879 return -1; /* #GP */ 880 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 881 kvm_update_dr7(vcpu); 882 break; 883 } 884 885 return 0; 886 } 887 888 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 889 { 890 if (__kvm_set_dr(vcpu, dr, val)) { 891 kvm_inject_gp(vcpu, 0); 892 return 1; 893 } 894 return 0; 895 } 896 EXPORT_SYMBOL_GPL(kvm_set_dr); 897 898 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 899 { 900 switch (dr) { 901 case 0 ... 3: 902 *val = vcpu->arch.db[dr]; 903 break; 904 case 4: 905 /* fall through */ 906 case 6: 907 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 908 *val = vcpu->arch.dr6; 909 else 910 *val = kvm_x86_ops->get_dr6(vcpu); 911 break; 912 case 5: 913 /* fall through */ 914 default: /* 7 */ 915 *val = vcpu->arch.dr7; 916 break; 917 } 918 return 0; 919 } 920 EXPORT_SYMBOL_GPL(kvm_get_dr); 921 922 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 923 { 924 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 925 u64 data; 926 int err; 927 928 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 929 if (err) 930 return err; 931 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 932 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 933 return err; 934 } 935 EXPORT_SYMBOL_GPL(kvm_rdpmc); 936 937 /* 938 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 939 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 940 * 941 * This list is modified at module load time to reflect the 942 * capabilities of the host cpu. This capabilities test skips MSRs that are 943 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs 944 * may depend on host virtualization features rather than host cpu features. 945 */ 946 947 static u32 msrs_to_save[] = { 948 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 949 MSR_STAR, 950 #ifdef CONFIG_X86_64 951 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 952 #endif 953 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 954 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS 955 }; 956 957 static unsigned num_msrs_to_save; 958 959 static u32 emulated_msrs[] = { 960 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 961 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 962 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 963 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 964 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 965 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 966 HV_X64_MSR_RESET, 967 HV_X64_MSR_VP_INDEX, 968 HV_X64_MSR_VP_RUNTIME, 969 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 970 MSR_KVM_PV_EOI_EN, 971 972 MSR_IA32_TSC_ADJUST, 973 MSR_IA32_TSCDEADLINE, 974 MSR_IA32_MISC_ENABLE, 975 MSR_IA32_MCG_STATUS, 976 MSR_IA32_MCG_CTL, 977 MSR_IA32_SMBASE, 978 }; 979 980 static unsigned num_emulated_msrs; 981 982 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 983 { 984 if (efer & efer_reserved_bits) 985 return false; 986 987 if (efer & EFER_FFXSR) { 988 struct kvm_cpuid_entry2 *feat; 989 990 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 991 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) 992 return false; 993 } 994 995 if (efer & EFER_SVME) { 996 struct kvm_cpuid_entry2 *feat; 997 998 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 999 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) 1000 return false; 1001 } 1002 1003 return true; 1004 } 1005 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1006 1007 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 1008 { 1009 u64 old_efer = vcpu->arch.efer; 1010 1011 if (!kvm_valid_efer(vcpu, efer)) 1012 return 1; 1013 1014 if (is_paging(vcpu) 1015 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1016 return 1; 1017 1018 efer &= ~EFER_LMA; 1019 efer |= vcpu->arch.efer & EFER_LMA; 1020 1021 kvm_x86_ops->set_efer(vcpu, efer); 1022 1023 /* Update reserved bits */ 1024 if ((efer ^ old_efer) & EFER_NX) 1025 kvm_mmu_reset_context(vcpu); 1026 1027 return 0; 1028 } 1029 1030 void kvm_enable_efer_bits(u64 mask) 1031 { 1032 efer_reserved_bits &= ~mask; 1033 } 1034 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1035 1036 /* 1037 * Writes msr value into into the appropriate "register". 1038 * Returns 0 on success, non-0 otherwise. 1039 * Assumes vcpu_load() was already called. 1040 */ 1041 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1042 { 1043 switch (msr->index) { 1044 case MSR_FS_BASE: 1045 case MSR_GS_BASE: 1046 case MSR_KERNEL_GS_BASE: 1047 case MSR_CSTAR: 1048 case MSR_LSTAR: 1049 if (is_noncanonical_address(msr->data)) 1050 return 1; 1051 break; 1052 case MSR_IA32_SYSENTER_EIP: 1053 case MSR_IA32_SYSENTER_ESP: 1054 /* 1055 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1056 * non-canonical address is written on Intel but not on 1057 * AMD (which ignores the top 32-bits, because it does 1058 * not implement 64-bit SYSENTER). 1059 * 1060 * 64-bit code should hence be able to write a non-canonical 1061 * value on AMD. Making the address canonical ensures that 1062 * vmentry does not fail on Intel after writing a non-canonical 1063 * value, and that something deterministic happens if the guest 1064 * invokes 64-bit SYSENTER. 1065 */ 1066 msr->data = get_canonical(msr->data); 1067 } 1068 return kvm_x86_ops->set_msr(vcpu, msr); 1069 } 1070 EXPORT_SYMBOL_GPL(kvm_set_msr); 1071 1072 /* 1073 * Adapt set_msr() to msr_io()'s calling convention 1074 */ 1075 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1076 { 1077 struct msr_data msr; 1078 int r; 1079 1080 msr.index = index; 1081 msr.host_initiated = true; 1082 r = kvm_get_msr(vcpu, &msr); 1083 if (r) 1084 return r; 1085 1086 *data = msr.data; 1087 return 0; 1088 } 1089 1090 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1091 { 1092 struct msr_data msr; 1093 1094 msr.data = *data; 1095 msr.index = index; 1096 msr.host_initiated = true; 1097 return kvm_set_msr(vcpu, &msr); 1098 } 1099 1100 #ifdef CONFIG_X86_64 1101 struct pvclock_gtod_data { 1102 seqcount_t seq; 1103 1104 struct { /* extract of a clocksource struct */ 1105 int vclock_mode; 1106 cycle_t cycle_last; 1107 cycle_t mask; 1108 u32 mult; 1109 u32 shift; 1110 } clock; 1111 1112 u64 boot_ns; 1113 u64 nsec_base; 1114 }; 1115 1116 static struct pvclock_gtod_data pvclock_gtod_data; 1117 1118 static void update_pvclock_gtod(struct timekeeper *tk) 1119 { 1120 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1121 u64 boot_ns; 1122 1123 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1124 1125 write_seqcount_begin(&vdata->seq); 1126 1127 /* copy pvclock gtod data */ 1128 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1129 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1130 vdata->clock.mask = tk->tkr_mono.mask; 1131 vdata->clock.mult = tk->tkr_mono.mult; 1132 vdata->clock.shift = tk->tkr_mono.shift; 1133 1134 vdata->boot_ns = boot_ns; 1135 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1136 1137 write_seqcount_end(&vdata->seq); 1138 } 1139 #endif 1140 1141 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1142 { 1143 /* 1144 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1145 * vcpu_enter_guest. This function is only called from 1146 * the physical CPU that is running vcpu. 1147 */ 1148 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1149 } 1150 1151 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1152 { 1153 int version; 1154 int r; 1155 struct pvclock_wall_clock wc; 1156 struct timespec boot; 1157 1158 if (!wall_clock) 1159 return; 1160 1161 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1162 if (r) 1163 return; 1164 1165 if (version & 1) 1166 ++version; /* first time write, random junk */ 1167 1168 ++version; 1169 1170 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1171 1172 /* 1173 * The guest calculates current wall clock time by adding 1174 * system time (updated by kvm_guest_time_update below) to the 1175 * wall clock specified here. guest system time equals host 1176 * system time for us, thus we must fill in host boot time here. 1177 */ 1178 getboottime(&boot); 1179 1180 if (kvm->arch.kvmclock_offset) { 1181 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); 1182 boot = timespec_sub(boot, ts); 1183 } 1184 wc.sec = boot.tv_sec; 1185 wc.nsec = boot.tv_nsec; 1186 wc.version = version; 1187 1188 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1189 1190 version++; 1191 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1192 } 1193 1194 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1195 { 1196 uint32_t quotient, remainder; 1197 1198 /* Don't try to replace with do_div(), this one calculates 1199 * "(dividend << 32) / divisor" */ 1200 __asm__ ( "divl %4" 1201 : "=a" (quotient), "=d" (remainder) 1202 : "0" (0), "1" (dividend), "r" (divisor) ); 1203 return quotient; 1204 } 1205 1206 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, 1207 s8 *pshift, u32 *pmultiplier) 1208 { 1209 uint64_t scaled64; 1210 int32_t shift = 0; 1211 uint64_t tps64; 1212 uint32_t tps32; 1213 1214 tps64 = base_khz * 1000LL; 1215 scaled64 = scaled_khz * 1000LL; 1216 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1217 tps64 >>= 1; 1218 shift--; 1219 } 1220 1221 tps32 = (uint32_t)tps64; 1222 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1223 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1224 scaled64 >>= 1; 1225 else 1226 tps32 <<= 1; 1227 shift++; 1228 } 1229 1230 *pshift = shift; 1231 *pmultiplier = div_frac(scaled64, tps32); 1232 1233 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", 1234 __func__, base_khz, scaled_khz, shift, *pmultiplier); 1235 } 1236 1237 #ifdef CONFIG_X86_64 1238 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1239 #endif 1240 1241 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1242 static unsigned long max_tsc_khz; 1243 1244 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) 1245 { 1246 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, 1247 vcpu->arch.virtual_tsc_shift); 1248 } 1249 1250 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1251 { 1252 u64 v = (u64)khz * (1000000 + ppm); 1253 do_div(v, 1000000); 1254 return v; 1255 } 1256 1257 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 1258 { 1259 u64 ratio; 1260 1261 /* Guest TSC same frequency as host TSC? */ 1262 if (!scale) { 1263 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1264 return 0; 1265 } 1266 1267 /* TSC scaling supported? */ 1268 if (!kvm_has_tsc_control) { 1269 if (user_tsc_khz > tsc_khz) { 1270 vcpu->arch.tsc_catchup = 1; 1271 vcpu->arch.tsc_always_catchup = 1; 1272 return 0; 1273 } else { 1274 WARN(1, "user requested TSC rate below hardware speed\n"); 1275 return -1; 1276 } 1277 } 1278 1279 /* TSC scaling required - calculate ratio */ 1280 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 1281 user_tsc_khz, tsc_khz); 1282 1283 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 1284 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 1285 user_tsc_khz); 1286 return -1; 1287 } 1288 1289 vcpu->arch.tsc_scaling_ratio = ratio; 1290 return 0; 1291 } 1292 1293 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) 1294 { 1295 u32 thresh_lo, thresh_hi; 1296 int use_scaling = 0; 1297 1298 /* tsc_khz can be zero if TSC calibration fails */ 1299 if (this_tsc_khz == 0) { 1300 /* set tsc_scaling_ratio to a safe value */ 1301 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1302 return -1; 1303 } 1304 1305 /* Compute a scale to convert nanoseconds in TSC cycles */ 1306 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, 1307 &vcpu->arch.virtual_tsc_shift, 1308 &vcpu->arch.virtual_tsc_mult); 1309 vcpu->arch.virtual_tsc_khz = this_tsc_khz; 1310 1311 /* 1312 * Compute the variation in TSC rate which is acceptable 1313 * within the range of tolerance and decide if the 1314 * rate being applied is within that bounds of the hardware 1315 * rate. If so, no scaling or compensation need be done. 1316 */ 1317 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1318 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1319 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { 1320 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); 1321 use_scaling = 1; 1322 } 1323 return set_tsc_khz(vcpu, this_tsc_khz, use_scaling); 1324 } 1325 1326 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1327 { 1328 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1329 vcpu->arch.virtual_tsc_mult, 1330 vcpu->arch.virtual_tsc_shift); 1331 tsc += vcpu->arch.this_tsc_write; 1332 return tsc; 1333 } 1334 1335 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1336 { 1337 #ifdef CONFIG_X86_64 1338 bool vcpus_matched; 1339 struct kvm_arch *ka = &vcpu->kvm->arch; 1340 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1341 1342 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1343 atomic_read(&vcpu->kvm->online_vcpus)); 1344 1345 /* 1346 * Once the masterclock is enabled, always perform request in 1347 * order to update it. 1348 * 1349 * In order to enable masterclock, the host clocksource must be TSC 1350 * and the vcpus need to have matched TSCs. When that happens, 1351 * perform request to enable masterclock. 1352 */ 1353 if (ka->use_master_clock || 1354 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) 1355 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1356 1357 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1358 atomic_read(&vcpu->kvm->online_vcpus), 1359 ka->use_master_clock, gtod->clock.vclock_mode); 1360 #endif 1361 } 1362 1363 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1364 { 1365 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); 1366 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1367 } 1368 1369 /* 1370 * Multiply tsc by a fixed point number represented by ratio. 1371 * 1372 * The most significant 64-N bits (mult) of ratio represent the 1373 * integral part of the fixed point number; the remaining N bits 1374 * (frac) represent the fractional part, ie. ratio represents a fixed 1375 * point number (mult + frac * 2^(-N)). 1376 * 1377 * N equals to kvm_tsc_scaling_ratio_frac_bits. 1378 */ 1379 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 1380 { 1381 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 1382 } 1383 1384 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 1385 { 1386 u64 _tsc = tsc; 1387 u64 ratio = vcpu->arch.tsc_scaling_ratio; 1388 1389 if (ratio != kvm_default_tsc_scaling_ratio) 1390 _tsc = __scale_tsc(ratio, tsc); 1391 1392 return _tsc; 1393 } 1394 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 1395 1396 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 1397 { 1398 u64 tsc; 1399 1400 tsc = kvm_scale_tsc(vcpu, rdtsc()); 1401 1402 return target_tsc - tsc; 1403 } 1404 1405 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 1406 { 1407 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc)); 1408 } 1409 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 1410 1411 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1412 { 1413 struct kvm *kvm = vcpu->kvm; 1414 u64 offset, ns, elapsed; 1415 unsigned long flags; 1416 s64 usdiff; 1417 bool matched; 1418 bool already_matched; 1419 u64 data = msr->data; 1420 1421 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1422 offset = kvm_compute_tsc_offset(vcpu, data); 1423 ns = get_kernel_ns(); 1424 elapsed = ns - kvm->arch.last_tsc_nsec; 1425 1426 if (vcpu->arch.virtual_tsc_khz) { 1427 int faulted = 0; 1428 1429 /* n.b - signed multiplication and division required */ 1430 usdiff = data - kvm->arch.last_tsc_write; 1431 #ifdef CONFIG_X86_64 1432 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; 1433 #else 1434 /* do_div() only does unsigned */ 1435 asm("1: idivl %[divisor]\n" 1436 "2: xor %%edx, %%edx\n" 1437 " movl $0, %[faulted]\n" 1438 "3:\n" 1439 ".section .fixup,\"ax\"\n" 1440 "4: movl $1, %[faulted]\n" 1441 " jmp 3b\n" 1442 ".previous\n" 1443 1444 _ASM_EXTABLE(1b, 4b) 1445 1446 : "=A"(usdiff), [faulted] "=r" (faulted) 1447 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); 1448 1449 #endif 1450 do_div(elapsed, 1000); 1451 usdiff -= elapsed; 1452 if (usdiff < 0) 1453 usdiff = -usdiff; 1454 1455 /* idivl overflow => difference is larger than USEC_PER_SEC */ 1456 if (faulted) 1457 usdiff = USEC_PER_SEC; 1458 } else 1459 usdiff = USEC_PER_SEC; /* disable TSC match window below */ 1460 1461 /* 1462 * Special case: TSC write with a small delta (1 second) of virtual 1463 * cycle time against real time is interpreted as an attempt to 1464 * synchronize the CPU. 1465 * 1466 * For a reliable TSC, we can match TSC offsets, and for an unstable 1467 * TSC, we add elapsed time in this computation. We could let the 1468 * compensation code attempt to catch up if we fall behind, but 1469 * it's better to try to match offsets from the beginning. 1470 */ 1471 if (usdiff < USEC_PER_SEC && 1472 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1473 if (!check_tsc_unstable()) { 1474 offset = kvm->arch.cur_tsc_offset; 1475 pr_debug("kvm: matched tsc offset for %llu\n", data); 1476 } else { 1477 u64 delta = nsec_to_cycles(vcpu, elapsed); 1478 data += delta; 1479 offset = kvm_compute_tsc_offset(vcpu, data); 1480 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1481 } 1482 matched = true; 1483 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1484 } else { 1485 /* 1486 * We split periods of matched TSC writes into generations. 1487 * For each generation, we track the original measured 1488 * nanosecond time, offset, and write, so if TSCs are in 1489 * sync, we can match exact offset, and if not, we can match 1490 * exact software computation in compute_guest_tsc() 1491 * 1492 * These values are tracked in kvm->arch.cur_xxx variables. 1493 */ 1494 kvm->arch.cur_tsc_generation++; 1495 kvm->arch.cur_tsc_nsec = ns; 1496 kvm->arch.cur_tsc_write = data; 1497 kvm->arch.cur_tsc_offset = offset; 1498 matched = false; 1499 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1500 kvm->arch.cur_tsc_generation, data); 1501 } 1502 1503 /* 1504 * We also track th most recent recorded KHZ, write and time to 1505 * allow the matching interval to be extended at each write. 1506 */ 1507 kvm->arch.last_tsc_nsec = ns; 1508 kvm->arch.last_tsc_write = data; 1509 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1510 1511 vcpu->arch.last_guest_tsc = data; 1512 1513 /* Keep track of which generation this VCPU has synchronized to */ 1514 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1515 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1516 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1517 1518 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) 1519 update_ia32_tsc_adjust_msr(vcpu, offset); 1520 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1521 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1522 1523 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1524 if (!matched) { 1525 kvm->arch.nr_vcpus_matched_tsc = 0; 1526 } else if (!already_matched) { 1527 kvm->arch.nr_vcpus_matched_tsc++; 1528 } 1529 1530 kvm_track_tsc_matching(vcpu); 1531 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1532 } 1533 1534 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1535 1536 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 1537 s64 adjustment) 1538 { 1539 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment); 1540 } 1541 1542 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 1543 { 1544 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 1545 WARN_ON(adjustment < 0); 1546 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 1547 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment); 1548 } 1549 1550 #ifdef CONFIG_X86_64 1551 1552 static cycle_t read_tsc(void) 1553 { 1554 cycle_t ret = (cycle_t)rdtsc_ordered(); 1555 u64 last = pvclock_gtod_data.clock.cycle_last; 1556 1557 if (likely(ret >= last)) 1558 return ret; 1559 1560 /* 1561 * GCC likes to generate cmov here, but this branch is extremely 1562 * predictable (it's just a funciton of time and the likely is 1563 * very likely) and there's a data dependence, so force GCC 1564 * to generate a branch instead. I don't barrier() because 1565 * we don't actually need a barrier, and if this function 1566 * ever gets inlined it will generate worse code. 1567 */ 1568 asm volatile (""); 1569 return last; 1570 } 1571 1572 static inline u64 vgettsc(cycle_t *cycle_now) 1573 { 1574 long v; 1575 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1576 1577 *cycle_now = read_tsc(); 1578 1579 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; 1580 return v * gtod->clock.mult; 1581 } 1582 1583 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now) 1584 { 1585 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1586 unsigned long seq; 1587 int mode; 1588 u64 ns; 1589 1590 do { 1591 seq = read_seqcount_begin(>od->seq); 1592 mode = gtod->clock.vclock_mode; 1593 ns = gtod->nsec_base; 1594 ns += vgettsc(cycle_now); 1595 ns >>= gtod->clock.shift; 1596 ns += gtod->boot_ns; 1597 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1598 *t = ns; 1599 1600 return mode; 1601 } 1602 1603 /* returns true if host is using tsc clocksource */ 1604 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) 1605 { 1606 /* checked again under seqlock below */ 1607 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) 1608 return false; 1609 1610 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; 1611 } 1612 #endif 1613 1614 /* 1615 * 1616 * Assuming a stable TSC across physical CPUS, and a stable TSC 1617 * across virtual CPUs, the following condition is possible. 1618 * Each numbered line represents an event visible to both 1619 * CPUs at the next numbered event. 1620 * 1621 * "timespecX" represents host monotonic time. "tscX" represents 1622 * RDTSC value. 1623 * 1624 * VCPU0 on CPU0 | VCPU1 on CPU1 1625 * 1626 * 1. read timespec0,tsc0 1627 * 2. | timespec1 = timespec0 + N 1628 * | tsc1 = tsc0 + M 1629 * 3. transition to guest | transition to guest 1630 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1631 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1632 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1633 * 1634 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1635 * 1636 * - ret0 < ret1 1637 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1638 * ... 1639 * - 0 < N - M => M < N 1640 * 1641 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1642 * always the case (the difference between two distinct xtime instances 1643 * might be smaller then the difference between corresponding TSC reads, 1644 * when updating guest vcpus pvclock areas). 1645 * 1646 * To avoid that problem, do not allow visibility of distinct 1647 * system_timestamp/tsc_timestamp values simultaneously: use a master 1648 * copy of host monotonic time values. Update that master copy 1649 * in lockstep. 1650 * 1651 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1652 * 1653 */ 1654 1655 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1656 { 1657 #ifdef CONFIG_X86_64 1658 struct kvm_arch *ka = &kvm->arch; 1659 int vclock_mode; 1660 bool host_tsc_clocksource, vcpus_matched; 1661 1662 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1663 atomic_read(&kvm->online_vcpus)); 1664 1665 /* 1666 * If the host uses TSC clock, then passthrough TSC as stable 1667 * to the guest. 1668 */ 1669 host_tsc_clocksource = kvm_get_time_and_clockread( 1670 &ka->master_kernel_ns, 1671 &ka->master_cycle_now); 1672 1673 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 1674 && !backwards_tsc_observed 1675 && !ka->boot_vcpu_runs_old_kvmclock; 1676 1677 if (ka->use_master_clock) 1678 atomic_set(&kvm_guest_has_master_clock, 1); 1679 1680 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1681 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1682 vcpus_matched); 1683 #endif 1684 } 1685 1686 static void kvm_gen_update_masterclock(struct kvm *kvm) 1687 { 1688 #ifdef CONFIG_X86_64 1689 int i; 1690 struct kvm_vcpu *vcpu; 1691 struct kvm_arch *ka = &kvm->arch; 1692 1693 spin_lock(&ka->pvclock_gtod_sync_lock); 1694 kvm_make_mclock_inprogress_request(kvm); 1695 /* no guest entries from this point */ 1696 pvclock_update_vm_gtod_copy(kvm); 1697 1698 kvm_for_each_vcpu(i, vcpu, kvm) 1699 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1700 1701 /* guest entries allowed */ 1702 kvm_for_each_vcpu(i, vcpu, kvm) 1703 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); 1704 1705 spin_unlock(&ka->pvclock_gtod_sync_lock); 1706 #endif 1707 } 1708 1709 static int kvm_guest_time_update(struct kvm_vcpu *v) 1710 { 1711 unsigned long flags, this_tsc_khz, tgt_tsc_khz; 1712 struct kvm_vcpu_arch *vcpu = &v->arch; 1713 struct kvm_arch *ka = &v->kvm->arch; 1714 s64 kernel_ns; 1715 u64 tsc_timestamp, host_tsc; 1716 struct pvclock_vcpu_time_info guest_hv_clock; 1717 u8 pvclock_flags; 1718 bool use_master_clock; 1719 1720 kernel_ns = 0; 1721 host_tsc = 0; 1722 1723 /* 1724 * If the host uses TSC clock, then passthrough TSC as stable 1725 * to the guest. 1726 */ 1727 spin_lock(&ka->pvclock_gtod_sync_lock); 1728 use_master_clock = ka->use_master_clock; 1729 if (use_master_clock) { 1730 host_tsc = ka->master_cycle_now; 1731 kernel_ns = ka->master_kernel_ns; 1732 } 1733 spin_unlock(&ka->pvclock_gtod_sync_lock); 1734 1735 /* Keep irq disabled to prevent changes to the clock */ 1736 local_irq_save(flags); 1737 this_tsc_khz = __this_cpu_read(cpu_tsc_khz); 1738 if (unlikely(this_tsc_khz == 0)) { 1739 local_irq_restore(flags); 1740 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1741 return 1; 1742 } 1743 if (!use_master_clock) { 1744 host_tsc = rdtsc(); 1745 kernel_ns = get_kernel_ns(); 1746 } 1747 1748 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 1749 1750 /* 1751 * We may have to catch up the TSC to match elapsed wall clock 1752 * time for two reasons, even if kvmclock is used. 1753 * 1) CPU could have been running below the maximum TSC rate 1754 * 2) Broken TSC compensation resets the base at each VCPU 1755 * entry to avoid unknown leaps of TSC even when running 1756 * again on the same CPU. This may cause apparent elapsed 1757 * time to disappear, and the guest to stand still or run 1758 * very slowly. 1759 */ 1760 if (vcpu->tsc_catchup) { 1761 u64 tsc = compute_guest_tsc(v, kernel_ns); 1762 if (tsc > tsc_timestamp) { 1763 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 1764 tsc_timestamp = tsc; 1765 } 1766 } 1767 1768 local_irq_restore(flags); 1769 1770 if (!vcpu->pv_time_enabled) 1771 return 0; 1772 1773 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { 1774 tgt_tsc_khz = kvm_has_tsc_control ? 1775 vcpu->virtual_tsc_khz : this_tsc_khz; 1776 kvm_get_time_scale(NSEC_PER_SEC / 1000, tgt_tsc_khz, 1777 &vcpu->hv_clock.tsc_shift, 1778 &vcpu->hv_clock.tsc_to_system_mul); 1779 vcpu->hw_tsc_khz = this_tsc_khz; 1780 } 1781 1782 /* With all the info we got, fill in the values */ 1783 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 1784 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 1785 vcpu->last_guest_tsc = tsc_timestamp; 1786 1787 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1788 &guest_hv_clock, sizeof(guest_hv_clock)))) 1789 return 0; 1790 1791 /* This VCPU is paused, but it's legal for a guest to read another 1792 * VCPU's kvmclock, so we really have to follow the specification where 1793 * it says that version is odd if data is being modified, and even after 1794 * it is consistent. 1795 * 1796 * Version field updates must be kept separate. This is because 1797 * kvm_write_guest_cached might use a "rep movs" instruction, and 1798 * writes within a string instruction are weakly ordered. So there 1799 * are three writes overall. 1800 * 1801 * As a small optimization, only write the version field in the first 1802 * and third write. The vcpu->pv_time cache is still valid, because the 1803 * version field is the first in the struct. 1804 */ 1805 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 1806 1807 vcpu->hv_clock.version = guest_hv_clock.version + 1; 1808 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1809 &vcpu->hv_clock, 1810 sizeof(vcpu->hv_clock.version)); 1811 1812 smp_wmb(); 1813 1814 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1815 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1816 1817 if (vcpu->pvclock_set_guest_stopped_request) { 1818 pvclock_flags |= PVCLOCK_GUEST_STOPPED; 1819 vcpu->pvclock_set_guest_stopped_request = false; 1820 } 1821 1822 /* If the host uses TSC clocksource, then it is stable */ 1823 if (use_master_clock) 1824 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 1825 1826 vcpu->hv_clock.flags = pvclock_flags; 1827 1828 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 1829 1830 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1831 &vcpu->hv_clock, 1832 sizeof(vcpu->hv_clock)); 1833 1834 smp_wmb(); 1835 1836 vcpu->hv_clock.version++; 1837 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1838 &vcpu->hv_clock, 1839 sizeof(vcpu->hv_clock.version)); 1840 return 0; 1841 } 1842 1843 /* 1844 * kvmclock updates which are isolated to a given vcpu, such as 1845 * vcpu->cpu migration, should not allow system_timestamp from 1846 * the rest of the vcpus to remain static. Otherwise ntp frequency 1847 * correction applies to one vcpu's system_timestamp but not 1848 * the others. 1849 * 1850 * So in those cases, request a kvmclock update for all vcpus. 1851 * We need to rate-limit these requests though, as they can 1852 * considerably slow guests that have a large number of vcpus. 1853 * The time for a remote vcpu to update its kvmclock is bound 1854 * by the delay we use to rate-limit the updates. 1855 */ 1856 1857 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 1858 1859 static void kvmclock_update_fn(struct work_struct *work) 1860 { 1861 int i; 1862 struct delayed_work *dwork = to_delayed_work(work); 1863 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1864 kvmclock_update_work); 1865 struct kvm *kvm = container_of(ka, struct kvm, arch); 1866 struct kvm_vcpu *vcpu; 1867 1868 kvm_for_each_vcpu(i, vcpu, kvm) { 1869 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1870 kvm_vcpu_kick(vcpu); 1871 } 1872 } 1873 1874 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 1875 { 1876 struct kvm *kvm = v->kvm; 1877 1878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1879 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 1880 KVMCLOCK_UPDATE_DELAY); 1881 } 1882 1883 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 1884 1885 static void kvmclock_sync_fn(struct work_struct *work) 1886 { 1887 struct delayed_work *dwork = to_delayed_work(work); 1888 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1889 kvmclock_sync_work); 1890 struct kvm *kvm = container_of(ka, struct kvm, arch); 1891 1892 if (!kvmclock_periodic_sync) 1893 return; 1894 1895 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 1896 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 1897 KVMCLOCK_SYNC_PERIOD); 1898 } 1899 1900 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1901 { 1902 u64 mcg_cap = vcpu->arch.mcg_cap; 1903 unsigned bank_num = mcg_cap & 0xff; 1904 1905 switch (msr) { 1906 case MSR_IA32_MCG_STATUS: 1907 vcpu->arch.mcg_status = data; 1908 break; 1909 case MSR_IA32_MCG_CTL: 1910 if (!(mcg_cap & MCG_CTL_P)) 1911 return 1; 1912 if (data != 0 && data != ~(u64)0) 1913 return -1; 1914 vcpu->arch.mcg_ctl = data; 1915 break; 1916 default: 1917 if (msr >= MSR_IA32_MC0_CTL && 1918 msr < MSR_IA32_MCx_CTL(bank_num)) { 1919 u32 offset = msr - MSR_IA32_MC0_CTL; 1920 /* only 0 or all 1s can be written to IA32_MCi_CTL 1921 * some Linux kernels though clear bit 10 in bank 4 to 1922 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 1923 * this to avoid an uncatched #GP in the guest 1924 */ 1925 if ((offset & 0x3) == 0 && 1926 data != 0 && (data | (1 << 10)) != ~(u64)0) 1927 return -1; 1928 vcpu->arch.mce_banks[offset] = data; 1929 break; 1930 } 1931 return 1; 1932 } 1933 return 0; 1934 } 1935 1936 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 1937 { 1938 struct kvm *kvm = vcpu->kvm; 1939 int lm = is_long_mode(vcpu); 1940 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 1941 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 1942 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 1943 : kvm->arch.xen_hvm_config.blob_size_32; 1944 u32 page_num = data & ~PAGE_MASK; 1945 u64 page_addr = data & PAGE_MASK; 1946 u8 *page; 1947 int r; 1948 1949 r = -E2BIG; 1950 if (page_num >= blob_size) 1951 goto out; 1952 r = -ENOMEM; 1953 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 1954 if (IS_ERR(page)) { 1955 r = PTR_ERR(page); 1956 goto out; 1957 } 1958 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 1959 goto out_free; 1960 r = 0; 1961 out_free: 1962 kfree(page); 1963 out: 1964 return r; 1965 } 1966 1967 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 1968 { 1969 gpa_t gpa = data & ~0x3f; 1970 1971 /* Bits 2:5 are reserved, Should be zero */ 1972 if (data & 0x3c) 1973 return 1; 1974 1975 vcpu->arch.apf.msr_val = data; 1976 1977 if (!(data & KVM_ASYNC_PF_ENABLED)) { 1978 kvm_clear_async_pf_completion_queue(vcpu); 1979 kvm_async_pf_hash_reset(vcpu); 1980 return 0; 1981 } 1982 1983 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 1984 sizeof(u32))) 1985 return 1; 1986 1987 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 1988 kvm_async_pf_wakeup_all(vcpu); 1989 return 0; 1990 } 1991 1992 static void kvmclock_reset(struct kvm_vcpu *vcpu) 1993 { 1994 vcpu->arch.pv_time_enabled = false; 1995 } 1996 1997 static void accumulate_steal_time(struct kvm_vcpu *vcpu) 1998 { 1999 u64 delta; 2000 2001 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2002 return; 2003 2004 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; 2005 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2006 vcpu->arch.st.accum_steal = delta; 2007 } 2008 2009 static void record_steal_time(struct kvm_vcpu *vcpu) 2010 { 2011 accumulate_steal_time(vcpu); 2012 2013 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2014 return; 2015 2016 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2017 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2018 return; 2019 2020 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; 2021 vcpu->arch.st.steal.version += 2; 2022 vcpu->arch.st.accum_steal = 0; 2023 2024 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2025 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2026 } 2027 2028 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2029 { 2030 bool pr = false; 2031 u32 msr = msr_info->index; 2032 u64 data = msr_info->data; 2033 2034 switch (msr) { 2035 case MSR_AMD64_NB_CFG: 2036 case MSR_IA32_UCODE_REV: 2037 case MSR_IA32_UCODE_WRITE: 2038 case MSR_VM_HSAVE_PA: 2039 case MSR_AMD64_PATCH_LOADER: 2040 case MSR_AMD64_BU_CFG2: 2041 break; 2042 2043 case MSR_EFER: 2044 return set_efer(vcpu, data); 2045 case MSR_K7_HWCR: 2046 data &= ~(u64)0x40; /* ignore flush filter disable */ 2047 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2048 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2049 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2050 if (data != 0) { 2051 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2052 data); 2053 return 1; 2054 } 2055 break; 2056 case MSR_FAM10H_MMIO_CONF_BASE: 2057 if (data != 0) { 2058 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2059 "0x%llx\n", data); 2060 return 1; 2061 } 2062 break; 2063 case MSR_IA32_DEBUGCTLMSR: 2064 if (!data) { 2065 /* We support the non-activated case already */ 2066 break; 2067 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2068 /* Values other than LBR and BTF are vendor-specific, 2069 thus reserved and should throw a #GP */ 2070 return 1; 2071 } 2072 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2073 __func__, data); 2074 break; 2075 case 0x200 ... 0x2ff: 2076 return kvm_mtrr_set_msr(vcpu, msr, data); 2077 case MSR_IA32_APICBASE: 2078 return kvm_set_apic_base(vcpu, msr_info); 2079 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2080 return kvm_x2apic_msr_write(vcpu, msr, data); 2081 case MSR_IA32_TSCDEADLINE: 2082 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2083 break; 2084 case MSR_IA32_TSC_ADJUST: 2085 if (guest_cpuid_has_tsc_adjust(vcpu)) { 2086 if (!msr_info->host_initiated) { 2087 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2088 adjust_tsc_offset_guest(vcpu, adj); 2089 } 2090 vcpu->arch.ia32_tsc_adjust_msr = data; 2091 } 2092 break; 2093 case MSR_IA32_MISC_ENABLE: 2094 vcpu->arch.ia32_misc_enable_msr = data; 2095 break; 2096 case MSR_IA32_SMBASE: 2097 if (!msr_info->host_initiated) 2098 return 1; 2099 vcpu->arch.smbase = data; 2100 break; 2101 case MSR_KVM_WALL_CLOCK_NEW: 2102 case MSR_KVM_WALL_CLOCK: 2103 vcpu->kvm->arch.wall_clock = data; 2104 kvm_write_wall_clock(vcpu->kvm, data); 2105 break; 2106 case MSR_KVM_SYSTEM_TIME_NEW: 2107 case MSR_KVM_SYSTEM_TIME: { 2108 u64 gpa_offset; 2109 struct kvm_arch *ka = &vcpu->kvm->arch; 2110 2111 kvmclock_reset(vcpu); 2112 2113 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2114 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2115 2116 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2117 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, 2118 &vcpu->requests); 2119 2120 ka->boot_vcpu_runs_old_kvmclock = tmp; 2121 } 2122 2123 vcpu->arch.time = data; 2124 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2125 2126 /* we verify if the enable bit is set... */ 2127 if (!(data & 1)) 2128 break; 2129 2130 gpa_offset = data & ~(PAGE_MASK | 1); 2131 2132 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2133 &vcpu->arch.pv_time, data & ~1ULL, 2134 sizeof(struct pvclock_vcpu_time_info))) 2135 vcpu->arch.pv_time_enabled = false; 2136 else 2137 vcpu->arch.pv_time_enabled = true; 2138 2139 break; 2140 } 2141 case MSR_KVM_ASYNC_PF_EN: 2142 if (kvm_pv_enable_async_pf(vcpu, data)) 2143 return 1; 2144 break; 2145 case MSR_KVM_STEAL_TIME: 2146 2147 if (unlikely(!sched_info_on())) 2148 return 1; 2149 2150 if (data & KVM_STEAL_RESERVED_MASK) 2151 return 1; 2152 2153 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2154 data & KVM_STEAL_VALID_BITS, 2155 sizeof(struct kvm_steal_time))) 2156 return 1; 2157 2158 vcpu->arch.st.msr_val = data; 2159 2160 if (!(data & KVM_MSR_ENABLED)) 2161 break; 2162 2163 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2164 2165 break; 2166 case MSR_KVM_PV_EOI_EN: 2167 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2168 return 1; 2169 break; 2170 2171 case MSR_IA32_MCG_CTL: 2172 case MSR_IA32_MCG_STATUS: 2173 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2174 return set_msr_mce(vcpu, msr, data); 2175 2176 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2177 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2178 pr = true; /* fall through */ 2179 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2180 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2181 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2182 return kvm_pmu_set_msr(vcpu, msr_info); 2183 2184 if (pr || data != 0) 2185 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2186 "0x%x data 0x%llx\n", msr, data); 2187 break; 2188 case MSR_K7_CLK_CTL: 2189 /* 2190 * Ignore all writes to this no longer documented MSR. 2191 * Writes are only relevant for old K7 processors, 2192 * all pre-dating SVM, but a recommended workaround from 2193 * AMD for these chips. It is possible to specify the 2194 * affected processor models on the command line, hence 2195 * the need to ignore the workaround. 2196 */ 2197 break; 2198 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2199 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2200 case HV_X64_MSR_CRASH_CTL: 2201 return kvm_hv_set_msr_common(vcpu, msr, data, 2202 msr_info->host_initiated); 2203 case MSR_IA32_BBL_CR_CTL3: 2204 /* Drop writes to this legacy MSR -- see rdmsr 2205 * counterpart for further detail. 2206 */ 2207 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); 2208 break; 2209 case MSR_AMD64_OSVW_ID_LENGTH: 2210 if (!guest_cpuid_has_osvw(vcpu)) 2211 return 1; 2212 vcpu->arch.osvw.length = data; 2213 break; 2214 case MSR_AMD64_OSVW_STATUS: 2215 if (!guest_cpuid_has_osvw(vcpu)) 2216 return 1; 2217 vcpu->arch.osvw.status = data; 2218 break; 2219 default: 2220 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2221 return xen_hvm_config(vcpu, data); 2222 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2223 return kvm_pmu_set_msr(vcpu, msr_info); 2224 if (!ignore_msrs) { 2225 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", 2226 msr, data); 2227 return 1; 2228 } else { 2229 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", 2230 msr, data); 2231 break; 2232 } 2233 } 2234 return 0; 2235 } 2236 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2237 2238 2239 /* 2240 * Reads an msr value (of 'msr_index') into 'pdata'. 2241 * Returns 0 on success, non-0 otherwise. 2242 * Assumes vcpu_load() was already called. 2243 */ 2244 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 2245 { 2246 return kvm_x86_ops->get_msr(vcpu, msr); 2247 } 2248 EXPORT_SYMBOL_GPL(kvm_get_msr); 2249 2250 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2251 { 2252 u64 data; 2253 u64 mcg_cap = vcpu->arch.mcg_cap; 2254 unsigned bank_num = mcg_cap & 0xff; 2255 2256 switch (msr) { 2257 case MSR_IA32_P5_MC_ADDR: 2258 case MSR_IA32_P5_MC_TYPE: 2259 data = 0; 2260 break; 2261 case MSR_IA32_MCG_CAP: 2262 data = vcpu->arch.mcg_cap; 2263 break; 2264 case MSR_IA32_MCG_CTL: 2265 if (!(mcg_cap & MCG_CTL_P)) 2266 return 1; 2267 data = vcpu->arch.mcg_ctl; 2268 break; 2269 case MSR_IA32_MCG_STATUS: 2270 data = vcpu->arch.mcg_status; 2271 break; 2272 default: 2273 if (msr >= MSR_IA32_MC0_CTL && 2274 msr < MSR_IA32_MCx_CTL(bank_num)) { 2275 u32 offset = msr - MSR_IA32_MC0_CTL; 2276 data = vcpu->arch.mce_banks[offset]; 2277 break; 2278 } 2279 return 1; 2280 } 2281 *pdata = data; 2282 return 0; 2283 } 2284 2285 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2286 { 2287 switch (msr_info->index) { 2288 case MSR_IA32_PLATFORM_ID: 2289 case MSR_IA32_EBL_CR_POWERON: 2290 case MSR_IA32_DEBUGCTLMSR: 2291 case MSR_IA32_LASTBRANCHFROMIP: 2292 case MSR_IA32_LASTBRANCHTOIP: 2293 case MSR_IA32_LASTINTFROMIP: 2294 case MSR_IA32_LASTINTTOIP: 2295 case MSR_K8_SYSCFG: 2296 case MSR_K8_TSEG_ADDR: 2297 case MSR_K8_TSEG_MASK: 2298 case MSR_K7_HWCR: 2299 case MSR_VM_HSAVE_PA: 2300 case MSR_K8_INT_PENDING_MSG: 2301 case MSR_AMD64_NB_CFG: 2302 case MSR_FAM10H_MMIO_CONF_BASE: 2303 case MSR_AMD64_BU_CFG2: 2304 msr_info->data = 0; 2305 break; 2306 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2307 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2308 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2309 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2310 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2311 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2312 msr_info->data = 0; 2313 break; 2314 case MSR_IA32_UCODE_REV: 2315 msr_info->data = 0x100000000ULL; 2316 break; 2317 case MSR_MTRRcap: 2318 case 0x200 ... 0x2ff: 2319 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 2320 case 0xcd: /* fsb frequency */ 2321 msr_info->data = 3; 2322 break; 2323 /* 2324 * MSR_EBC_FREQUENCY_ID 2325 * Conservative value valid for even the basic CPU models. 2326 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2327 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2328 * and 266MHz for model 3, or 4. Set Core Clock 2329 * Frequency to System Bus Frequency Ratio to 1 (bits 2330 * 31:24) even though these are only valid for CPU 2331 * models > 2, however guests may end up dividing or 2332 * multiplying by zero otherwise. 2333 */ 2334 case MSR_EBC_FREQUENCY_ID: 2335 msr_info->data = 1 << 24; 2336 break; 2337 case MSR_IA32_APICBASE: 2338 msr_info->data = kvm_get_apic_base(vcpu); 2339 break; 2340 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2341 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 2342 break; 2343 case MSR_IA32_TSCDEADLINE: 2344 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 2345 break; 2346 case MSR_IA32_TSC_ADJUST: 2347 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2348 break; 2349 case MSR_IA32_MISC_ENABLE: 2350 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 2351 break; 2352 case MSR_IA32_SMBASE: 2353 if (!msr_info->host_initiated) 2354 return 1; 2355 msr_info->data = vcpu->arch.smbase; 2356 break; 2357 case MSR_IA32_PERF_STATUS: 2358 /* TSC increment by tick */ 2359 msr_info->data = 1000ULL; 2360 /* CPU multiplier */ 2361 msr_info->data |= (((uint64_t)4ULL) << 40); 2362 break; 2363 case MSR_EFER: 2364 msr_info->data = vcpu->arch.efer; 2365 break; 2366 case MSR_KVM_WALL_CLOCK: 2367 case MSR_KVM_WALL_CLOCK_NEW: 2368 msr_info->data = vcpu->kvm->arch.wall_clock; 2369 break; 2370 case MSR_KVM_SYSTEM_TIME: 2371 case MSR_KVM_SYSTEM_TIME_NEW: 2372 msr_info->data = vcpu->arch.time; 2373 break; 2374 case MSR_KVM_ASYNC_PF_EN: 2375 msr_info->data = vcpu->arch.apf.msr_val; 2376 break; 2377 case MSR_KVM_STEAL_TIME: 2378 msr_info->data = vcpu->arch.st.msr_val; 2379 break; 2380 case MSR_KVM_PV_EOI_EN: 2381 msr_info->data = vcpu->arch.pv_eoi.msr_val; 2382 break; 2383 case MSR_IA32_P5_MC_ADDR: 2384 case MSR_IA32_P5_MC_TYPE: 2385 case MSR_IA32_MCG_CAP: 2386 case MSR_IA32_MCG_CTL: 2387 case MSR_IA32_MCG_STATUS: 2388 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2389 return get_msr_mce(vcpu, msr_info->index, &msr_info->data); 2390 case MSR_K7_CLK_CTL: 2391 /* 2392 * Provide expected ramp-up count for K7. All other 2393 * are set to zero, indicating minimum divisors for 2394 * every field. 2395 * 2396 * This prevents guest kernels on AMD host with CPU 2397 * type 6, model 8 and higher from exploding due to 2398 * the rdmsr failing. 2399 */ 2400 msr_info->data = 0x20000000; 2401 break; 2402 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2403 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2404 case HV_X64_MSR_CRASH_CTL: 2405 return kvm_hv_get_msr_common(vcpu, 2406 msr_info->index, &msr_info->data); 2407 break; 2408 case MSR_IA32_BBL_CR_CTL3: 2409 /* This legacy MSR exists but isn't fully documented in current 2410 * silicon. It is however accessed by winxp in very narrow 2411 * scenarios where it sets bit #19, itself documented as 2412 * a "reserved" bit. Best effort attempt to source coherent 2413 * read data here should the balance of the register be 2414 * interpreted by the guest: 2415 * 2416 * L2 cache control register 3: 64GB range, 256KB size, 2417 * enabled, latency 0x1, configured 2418 */ 2419 msr_info->data = 0xbe702111; 2420 break; 2421 case MSR_AMD64_OSVW_ID_LENGTH: 2422 if (!guest_cpuid_has_osvw(vcpu)) 2423 return 1; 2424 msr_info->data = vcpu->arch.osvw.length; 2425 break; 2426 case MSR_AMD64_OSVW_STATUS: 2427 if (!guest_cpuid_has_osvw(vcpu)) 2428 return 1; 2429 msr_info->data = vcpu->arch.osvw.status; 2430 break; 2431 default: 2432 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2433 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2434 if (!ignore_msrs) { 2435 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index); 2436 return 1; 2437 } else { 2438 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index); 2439 msr_info->data = 0; 2440 } 2441 break; 2442 } 2443 return 0; 2444 } 2445 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2446 2447 /* 2448 * Read or write a bunch of msrs. All parameters are kernel addresses. 2449 * 2450 * @return number of msrs set successfully. 2451 */ 2452 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2453 struct kvm_msr_entry *entries, 2454 int (*do_msr)(struct kvm_vcpu *vcpu, 2455 unsigned index, u64 *data)) 2456 { 2457 int i, idx; 2458 2459 idx = srcu_read_lock(&vcpu->kvm->srcu); 2460 for (i = 0; i < msrs->nmsrs; ++i) 2461 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2462 break; 2463 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2464 2465 return i; 2466 } 2467 2468 /* 2469 * Read or write a bunch of msrs. Parameters are user addresses. 2470 * 2471 * @return number of msrs set successfully. 2472 */ 2473 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2474 int (*do_msr)(struct kvm_vcpu *vcpu, 2475 unsigned index, u64 *data), 2476 int writeback) 2477 { 2478 struct kvm_msrs msrs; 2479 struct kvm_msr_entry *entries; 2480 int r, n; 2481 unsigned size; 2482 2483 r = -EFAULT; 2484 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2485 goto out; 2486 2487 r = -E2BIG; 2488 if (msrs.nmsrs >= MAX_IO_MSRS) 2489 goto out; 2490 2491 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2492 entries = memdup_user(user_msrs->entries, size); 2493 if (IS_ERR(entries)) { 2494 r = PTR_ERR(entries); 2495 goto out; 2496 } 2497 2498 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2499 if (r < 0) 2500 goto out_free; 2501 2502 r = -EFAULT; 2503 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2504 goto out_free; 2505 2506 r = n; 2507 2508 out_free: 2509 kfree(entries); 2510 out: 2511 return r; 2512 } 2513 2514 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2515 { 2516 int r; 2517 2518 switch (ext) { 2519 case KVM_CAP_IRQCHIP: 2520 case KVM_CAP_HLT: 2521 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2522 case KVM_CAP_SET_TSS_ADDR: 2523 case KVM_CAP_EXT_CPUID: 2524 case KVM_CAP_EXT_EMUL_CPUID: 2525 case KVM_CAP_CLOCKSOURCE: 2526 case KVM_CAP_PIT: 2527 case KVM_CAP_NOP_IO_DELAY: 2528 case KVM_CAP_MP_STATE: 2529 case KVM_CAP_SYNC_MMU: 2530 case KVM_CAP_USER_NMI: 2531 case KVM_CAP_REINJECT_CONTROL: 2532 case KVM_CAP_IRQ_INJECT_STATUS: 2533 case KVM_CAP_IOEVENTFD: 2534 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2535 case KVM_CAP_PIT2: 2536 case KVM_CAP_PIT_STATE2: 2537 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2538 case KVM_CAP_XEN_HVM: 2539 case KVM_CAP_ADJUST_CLOCK: 2540 case KVM_CAP_VCPU_EVENTS: 2541 case KVM_CAP_HYPERV: 2542 case KVM_CAP_HYPERV_VAPIC: 2543 case KVM_CAP_HYPERV_SPIN: 2544 case KVM_CAP_PCI_SEGMENT: 2545 case KVM_CAP_DEBUGREGS: 2546 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2547 case KVM_CAP_XSAVE: 2548 case KVM_CAP_ASYNC_PF: 2549 case KVM_CAP_GET_TSC_KHZ: 2550 case KVM_CAP_KVMCLOCK_CTRL: 2551 case KVM_CAP_READONLY_MEM: 2552 case KVM_CAP_HYPERV_TIME: 2553 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2554 case KVM_CAP_TSC_DEADLINE_TIMER: 2555 case KVM_CAP_ENABLE_CAP_VM: 2556 case KVM_CAP_DISABLE_QUIRKS: 2557 case KVM_CAP_SET_BOOT_CPU_ID: 2558 case KVM_CAP_SPLIT_IRQCHIP: 2559 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2560 case KVM_CAP_ASSIGN_DEV_IRQ: 2561 case KVM_CAP_PCI_2_3: 2562 #endif 2563 r = 1; 2564 break; 2565 case KVM_CAP_X86_SMM: 2566 /* SMBASE is usually relocated above 1M on modern chipsets, 2567 * and SMM handlers might indeed rely on 4G segment limits, 2568 * so do not report SMM to be available if real mode is 2569 * emulated via vm86 mode. Still, do not go to great lengths 2570 * to avoid userspace's usage of the feature, because it is a 2571 * fringe case that is not enabled except via specific settings 2572 * of the module parameters. 2573 */ 2574 r = kvm_x86_ops->cpu_has_high_real_mode_segbase(); 2575 break; 2576 case KVM_CAP_COALESCED_MMIO: 2577 r = KVM_COALESCED_MMIO_PAGE_OFFSET; 2578 break; 2579 case KVM_CAP_VAPIC: 2580 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2581 break; 2582 case KVM_CAP_NR_VCPUS: 2583 r = KVM_SOFT_MAX_VCPUS; 2584 break; 2585 case KVM_CAP_MAX_VCPUS: 2586 r = KVM_MAX_VCPUS; 2587 break; 2588 case KVM_CAP_NR_MEMSLOTS: 2589 r = KVM_USER_MEM_SLOTS; 2590 break; 2591 case KVM_CAP_PV_MMU: /* obsolete */ 2592 r = 0; 2593 break; 2594 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2595 case KVM_CAP_IOMMU: 2596 r = iommu_present(&pci_bus_type); 2597 break; 2598 #endif 2599 case KVM_CAP_MCE: 2600 r = KVM_MAX_MCE_BANKS; 2601 break; 2602 case KVM_CAP_XCRS: 2603 r = cpu_has_xsave; 2604 break; 2605 case KVM_CAP_TSC_CONTROL: 2606 r = kvm_has_tsc_control; 2607 break; 2608 default: 2609 r = 0; 2610 break; 2611 } 2612 return r; 2613 2614 } 2615 2616 long kvm_arch_dev_ioctl(struct file *filp, 2617 unsigned int ioctl, unsigned long arg) 2618 { 2619 void __user *argp = (void __user *)arg; 2620 long r; 2621 2622 switch (ioctl) { 2623 case KVM_GET_MSR_INDEX_LIST: { 2624 struct kvm_msr_list __user *user_msr_list = argp; 2625 struct kvm_msr_list msr_list; 2626 unsigned n; 2627 2628 r = -EFAULT; 2629 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2630 goto out; 2631 n = msr_list.nmsrs; 2632 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 2633 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2634 goto out; 2635 r = -E2BIG; 2636 if (n < msr_list.nmsrs) 2637 goto out; 2638 r = -EFAULT; 2639 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2640 num_msrs_to_save * sizeof(u32))) 2641 goto out; 2642 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2643 &emulated_msrs, 2644 num_emulated_msrs * sizeof(u32))) 2645 goto out; 2646 r = 0; 2647 break; 2648 } 2649 case KVM_GET_SUPPORTED_CPUID: 2650 case KVM_GET_EMULATED_CPUID: { 2651 struct kvm_cpuid2 __user *cpuid_arg = argp; 2652 struct kvm_cpuid2 cpuid; 2653 2654 r = -EFAULT; 2655 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2656 goto out; 2657 2658 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2659 ioctl); 2660 if (r) 2661 goto out; 2662 2663 r = -EFAULT; 2664 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2665 goto out; 2666 r = 0; 2667 break; 2668 } 2669 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2670 u64 mce_cap; 2671 2672 mce_cap = KVM_MCE_CAP_SUPPORTED; 2673 r = -EFAULT; 2674 if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) 2675 goto out; 2676 r = 0; 2677 break; 2678 } 2679 default: 2680 r = -EINVAL; 2681 } 2682 out: 2683 return r; 2684 } 2685 2686 static void wbinvd_ipi(void *garbage) 2687 { 2688 wbinvd(); 2689 } 2690 2691 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 2692 { 2693 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 2694 } 2695 2696 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 2697 { 2698 /* Address WBINVD may be executed by guest */ 2699 if (need_emulate_wbinvd(vcpu)) { 2700 if (kvm_x86_ops->has_wbinvd_exit()) 2701 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 2702 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 2703 smp_call_function_single(vcpu->cpu, 2704 wbinvd_ipi, NULL, 1); 2705 } 2706 2707 kvm_x86_ops->vcpu_load(vcpu, cpu); 2708 2709 /* Apply any externally detected TSC adjustments (due to suspend) */ 2710 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 2711 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 2712 vcpu->arch.tsc_offset_adjustment = 0; 2713 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2714 } 2715 2716 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { 2717 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 2718 rdtsc() - vcpu->arch.last_host_tsc; 2719 if (tsc_delta < 0) 2720 mark_tsc_unstable("KVM discovered backwards TSC"); 2721 if (check_tsc_unstable()) { 2722 u64 offset = kvm_compute_tsc_offset(vcpu, 2723 vcpu->arch.last_guest_tsc); 2724 kvm_x86_ops->write_tsc_offset(vcpu, offset); 2725 vcpu->arch.tsc_catchup = 1; 2726 } 2727 /* 2728 * On a host with synchronized TSC, there is no need to update 2729 * kvmclock on vcpu->cpu migration 2730 */ 2731 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 2732 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2733 if (vcpu->cpu != cpu) 2734 kvm_migrate_timers(vcpu); 2735 vcpu->cpu = cpu; 2736 } 2737 2738 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2739 } 2740 2741 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 2742 { 2743 kvm_x86_ops->vcpu_put(vcpu); 2744 kvm_put_guest_fpu(vcpu); 2745 vcpu->arch.last_host_tsc = rdtsc(); 2746 } 2747 2748 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 2749 struct kvm_lapic_state *s) 2750 { 2751 kvm_x86_ops->sync_pir_to_irr(vcpu); 2752 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); 2753 2754 return 0; 2755 } 2756 2757 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 2758 struct kvm_lapic_state *s) 2759 { 2760 kvm_apic_post_state_restore(vcpu, s); 2761 update_cr8_intercept(vcpu); 2762 2763 return 0; 2764 } 2765 2766 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 2767 { 2768 return (!lapic_in_kernel(vcpu) || 2769 kvm_apic_accept_pic_intr(vcpu)); 2770 } 2771 2772 /* 2773 * if userspace requested an interrupt window, check that the 2774 * interrupt window is open. 2775 * 2776 * No need to exit to userspace if we already have an interrupt queued. 2777 */ 2778 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 2779 { 2780 return kvm_arch_interrupt_allowed(vcpu) && 2781 !kvm_cpu_has_interrupt(vcpu) && 2782 !kvm_event_needs_reinjection(vcpu) && 2783 kvm_cpu_accept_dm_intr(vcpu); 2784 } 2785 2786 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 2787 struct kvm_interrupt *irq) 2788 { 2789 if (irq->irq >= KVM_NR_INTERRUPTS) 2790 return -EINVAL; 2791 2792 if (!irqchip_in_kernel(vcpu->kvm)) { 2793 kvm_queue_interrupt(vcpu, irq->irq, false); 2794 kvm_make_request(KVM_REQ_EVENT, vcpu); 2795 return 0; 2796 } 2797 2798 /* 2799 * With in-kernel LAPIC, we only use this to inject EXTINT, so 2800 * fail for in-kernel 8259. 2801 */ 2802 if (pic_in_kernel(vcpu->kvm)) 2803 return -ENXIO; 2804 2805 if (vcpu->arch.pending_external_vector != -1) 2806 return -EEXIST; 2807 2808 vcpu->arch.pending_external_vector = irq->irq; 2809 kvm_make_request(KVM_REQ_EVENT, vcpu); 2810 return 0; 2811 } 2812 2813 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 2814 { 2815 kvm_inject_nmi(vcpu); 2816 2817 return 0; 2818 } 2819 2820 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 2821 { 2822 kvm_make_request(KVM_REQ_SMI, vcpu); 2823 2824 return 0; 2825 } 2826 2827 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 2828 struct kvm_tpr_access_ctl *tac) 2829 { 2830 if (tac->flags) 2831 return -EINVAL; 2832 vcpu->arch.tpr_access_reporting = !!tac->enabled; 2833 return 0; 2834 } 2835 2836 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 2837 u64 mcg_cap) 2838 { 2839 int r; 2840 unsigned bank_num = mcg_cap & 0xff, bank; 2841 2842 r = -EINVAL; 2843 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 2844 goto out; 2845 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) 2846 goto out; 2847 r = 0; 2848 vcpu->arch.mcg_cap = mcg_cap; 2849 /* Init IA32_MCG_CTL to all 1s */ 2850 if (mcg_cap & MCG_CTL_P) 2851 vcpu->arch.mcg_ctl = ~(u64)0; 2852 /* Init IA32_MCi_CTL to all 1s */ 2853 for (bank = 0; bank < bank_num; bank++) 2854 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 2855 out: 2856 return r; 2857 } 2858 2859 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 2860 struct kvm_x86_mce *mce) 2861 { 2862 u64 mcg_cap = vcpu->arch.mcg_cap; 2863 unsigned bank_num = mcg_cap & 0xff; 2864 u64 *banks = vcpu->arch.mce_banks; 2865 2866 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 2867 return -EINVAL; 2868 /* 2869 * if IA32_MCG_CTL is not all 1s, the uncorrected error 2870 * reporting is disabled 2871 */ 2872 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 2873 vcpu->arch.mcg_ctl != ~(u64)0) 2874 return 0; 2875 banks += 4 * mce->bank; 2876 /* 2877 * if IA32_MCi_CTL is not all 1s, the uncorrected error 2878 * reporting is disabled for the bank 2879 */ 2880 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 2881 return 0; 2882 if (mce->status & MCI_STATUS_UC) { 2883 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 2884 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 2885 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 2886 return 0; 2887 } 2888 if (banks[1] & MCI_STATUS_VAL) 2889 mce->status |= MCI_STATUS_OVER; 2890 banks[2] = mce->addr; 2891 banks[3] = mce->misc; 2892 vcpu->arch.mcg_status = mce->mcg_status; 2893 banks[1] = mce->status; 2894 kvm_queue_exception(vcpu, MC_VECTOR); 2895 } else if (!(banks[1] & MCI_STATUS_VAL) 2896 || !(banks[1] & MCI_STATUS_UC)) { 2897 if (banks[1] & MCI_STATUS_VAL) 2898 mce->status |= MCI_STATUS_OVER; 2899 banks[2] = mce->addr; 2900 banks[3] = mce->misc; 2901 banks[1] = mce->status; 2902 } else 2903 banks[1] |= MCI_STATUS_OVER; 2904 return 0; 2905 } 2906 2907 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 2908 struct kvm_vcpu_events *events) 2909 { 2910 process_nmi(vcpu); 2911 events->exception.injected = 2912 vcpu->arch.exception.pending && 2913 !kvm_exception_is_soft(vcpu->arch.exception.nr); 2914 events->exception.nr = vcpu->arch.exception.nr; 2915 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 2916 events->exception.pad = 0; 2917 events->exception.error_code = vcpu->arch.exception.error_code; 2918 2919 events->interrupt.injected = 2920 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; 2921 events->interrupt.nr = vcpu->arch.interrupt.nr; 2922 events->interrupt.soft = 0; 2923 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 2924 2925 events->nmi.injected = vcpu->arch.nmi_injected; 2926 events->nmi.pending = vcpu->arch.nmi_pending != 0; 2927 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 2928 events->nmi.pad = 0; 2929 2930 events->sipi_vector = 0; /* never valid when reporting to user space */ 2931 2932 events->smi.smm = is_smm(vcpu); 2933 events->smi.pending = vcpu->arch.smi_pending; 2934 events->smi.smm_inside_nmi = 2935 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 2936 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 2937 2938 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 2939 | KVM_VCPUEVENT_VALID_SHADOW 2940 | KVM_VCPUEVENT_VALID_SMM); 2941 memset(&events->reserved, 0, sizeof(events->reserved)); 2942 } 2943 2944 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 2945 struct kvm_vcpu_events *events) 2946 { 2947 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 2948 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 2949 | KVM_VCPUEVENT_VALID_SHADOW 2950 | KVM_VCPUEVENT_VALID_SMM)) 2951 return -EINVAL; 2952 2953 process_nmi(vcpu); 2954 vcpu->arch.exception.pending = events->exception.injected; 2955 vcpu->arch.exception.nr = events->exception.nr; 2956 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 2957 vcpu->arch.exception.error_code = events->exception.error_code; 2958 2959 vcpu->arch.interrupt.pending = events->interrupt.injected; 2960 vcpu->arch.interrupt.nr = events->interrupt.nr; 2961 vcpu->arch.interrupt.soft = events->interrupt.soft; 2962 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 2963 kvm_x86_ops->set_interrupt_shadow(vcpu, 2964 events->interrupt.shadow); 2965 2966 vcpu->arch.nmi_injected = events->nmi.injected; 2967 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 2968 vcpu->arch.nmi_pending = events->nmi.pending; 2969 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 2970 2971 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 2972 kvm_vcpu_has_lapic(vcpu)) 2973 vcpu->arch.apic->sipi_vector = events->sipi_vector; 2974 2975 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 2976 if (events->smi.smm) 2977 vcpu->arch.hflags |= HF_SMM_MASK; 2978 else 2979 vcpu->arch.hflags &= ~HF_SMM_MASK; 2980 vcpu->arch.smi_pending = events->smi.pending; 2981 if (events->smi.smm_inside_nmi) 2982 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 2983 else 2984 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 2985 if (kvm_vcpu_has_lapic(vcpu)) { 2986 if (events->smi.latched_init) 2987 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 2988 else 2989 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 2990 } 2991 } 2992 2993 kvm_make_request(KVM_REQ_EVENT, vcpu); 2994 2995 return 0; 2996 } 2997 2998 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 2999 struct kvm_debugregs *dbgregs) 3000 { 3001 unsigned long val; 3002 3003 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3004 kvm_get_dr(vcpu, 6, &val); 3005 dbgregs->dr6 = val; 3006 dbgregs->dr7 = vcpu->arch.dr7; 3007 dbgregs->flags = 0; 3008 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3009 } 3010 3011 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3012 struct kvm_debugregs *dbgregs) 3013 { 3014 if (dbgregs->flags) 3015 return -EINVAL; 3016 3017 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3018 kvm_update_dr0123(vcpu); 3019 vcpu->arch.dr6 = dbgregs->dr6; 3020 kvm_update_dr6(vcpu); 3021 vcpu->arch.dr7 = dbgregs->dr7; 3022 kvm_update_dr7(vcpu); 3023 3024 return 0; 3025 } 3026 3027 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3028 3029 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3030 { 3031 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3032 u64 xstate_bv = xsave->header.xfeatures; 3033 u64 valid; 3034 3035 /* 3036 * Copy legacy XSAVE area, to avoid complications with CPUID 3037 * leaves 0 and 1 in the loop below. 3038 */ 3039 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3040 3041 /* Set XSTATE_BV */ 3042 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3043 3044 /* 3045 * Copy each region from the possibly compacted offset to the 3046 * non-compacted offset. 3047 */ 3048 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3049 while (valid) { 3050 u64 feature = valid & -valid; 3051 int index = fls64(feature) - 1; 3052 void *src = get_xsave_addr(xsave, feature); 3053 3054 if (src) { 3055 u32 size, offset, ecx, edx; 3056 cpuid_count(XSTATE_CPUID, index, 3057 &size, &offset, &ecx, &edx); 3058 memcpy(dest + offset, src, size); 3059 } 3060 3061 valid -= feature; 3062 } 3063 } 3064 3065 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3066 { 3067 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3068 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3069 u64 valid; 3070 3071 /* 3072 * Copy legacy XSAVE area, to avoid complications with CPUID 3073 * leaves 0 and 1 in the loop below. 3074 */ 3075 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3076 3077 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3078 xsave->header.xfeatures = xstate_bv; 3079 if (cpu_has_xsaves) 3080 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3081 3082 /* 3083 * Copy each region from the non-compacted offset to the 3084 * possibly compacted offset. 3085 */ 3086 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3087 while (valid) { 3088 u64 feature = valid & -valid; 3089 int index = fls64(feature) - 1; 3090 void *dest = get_xsave_addr(xsave, feature); 3091 3092 if (dest) { 3093 u32 size, offset, ecx, edx; 3094 cpuid_count(XSTATE_CPUID, index, 3095 &size, &offset, &ecx, &edx); 3096 memcpy(dest, src + offset, size); 3097 } 3098 3099 valid -= feature; 3100 } 3101 } 3102 3103 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3104 struct kvm_xsave *guest_xsave) 3105 { 3106 if (cpu_has_xsave) { 3107 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3108 fill_xsave((u8 *) guest_xsave->region, vcpu); 3109 } else { 3110 memcpy(guest_xsave->region, 3111 &vcpu->arch.guest_fpu.state.fxsave, 3112 sizeof(struct fxregs_state)); 3113 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3114 XFEATURE_MASK_FPSSE; 3115 } 3116 } 3117 3118 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3119 struct kvm_xsave *guest_xsave) 3120 { 3121 u64 xstate_bv = 3122 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3123 3124 if (cpu_has_xsave) { 3125 /* 3126 * Here we allow setting states that are not present in 3127 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3128 * with old userspace. 3129 */ 3130 if (xstate_bv & ~kvm_supported_xcr0()) 3131 return -EINVAL; 3132 load_xsave(vcpu, (u8 *)guest_xsave->region); 3133 } else { 3134 if (xstate_bv & ~XFEATURE_MASK_FPSSE) 3135 return -EINVAL; 3136 memcpy(&vcpu->arch.guest_fpu.state.fxsave, 3137 guest_xsave->region, sizeof(struct fxregs_state)); 3138 } 3139 return 0; 3140 } 3141 3142 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3143 struct kvm_xcrs *guest_xcrs) 3144 { 3145 if (!cpu_has_xsave) { 3146 guest_xcrs->nr_xcrs = 0; 3147 return; 3148 } 3149 3150 guest_xcrs->nr_xcrs = 1; 3151 guest_xcrs->flags = 0; 3152 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3153 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3154 } 3155 3156 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3157 struct kvm_xcrs *guest_xcrs) 3158 { 3159 int i, r = 0; 3160 3161 if (!cpu_has_xsave) 3162 return -EINVAL; 3163 3164 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3165 return -EINVAL; 3166 3167 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3168 /* Only support XCR0 currently */ 3169 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3170 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3171 guest_xcrs->xcrs[i].value); 3172 break; 3173 } 3174 if (r) 3175 r = -EINVAL; 3176 return r; 3177 } 3178 3179 /* 3180 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3181 * stopped by the hypervisor. This function will be called from the host only. 3182 * EINVAL is returned when the host attempts to set the flag for a guest that 3183 * does not support pv clocks. 3184 */ 3185 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3186 { 3187 if (!vcpu->arch.pv_time_enabled) 3188 return -EINVAL; 3189 vcpu->arch.pvclock_set_guest_stopped_request = true; 3190 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3191 return 0; 3192 } 3193 3194 long kvm_arch_vcpu_ioctl(struct file *filp, 3195 unsigned int ioctl, unsigned long arg) 3196 { 3197 struct kvm_vcpu *vcpu = filp->private_data; 3198 void __user *argp = (void __user *)arg; 3199 int r; 3200 union { 3201 struct kvm_lapic_state *lapic; 3202 struct kvm_xsave *xsave; 3203 struct kvm_xcrs *xcrs; 3204 void *buffer; 3205 } u; 3206 3207 u.buffer = NULL; 3208 switch (ioctl) { 3209 case KVM_GET_LAPIC: { 3210 r = -EINVAL; 3211 if (!vcpu->arch.apic) 3212 goto out; 3213 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3214 3215 r = -ENOMEM; 3216 if (!u.lapic) 3217 goto out; 3218 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3219 if (r) 3220 goto out; 3221 r = -EFAULT; 3222 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3223 goto out; 3224 r = 0; 3225 break; 3226 } 3227 case KVM_SET_LAPIC: { 3228 r = -EINVAL; 3229 if (!vcpu->arch.apic) 3230 goto out; 3231 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3232 if (IS_ERR(u.lapic)) 3233 return PTR_ERR(u.lapic); 3234 3235 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3236 break; 3237 } 3238 case KVM_INTERRUPT: { 3239 struct kvm_interrupt irq; 3240 3241 r = -EFAULT; 3242 if (copy_from_user(&irq, argp, sizeof irq)) 3243 goto out; 3244 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3245 break; 3246 } 3247 case KVM_NMI: { 3248 r = kvm_vcpu_ioctl_nmi(vcpu); 3249 break; 3250 } 3251 case KVM_SMI: { 3252 r = kvm_vcpu_ioctl_smi(vcpu); 3253 break; 3254 } 3255 case KVM_SET_CPUID: { 3256 struct kvm_cpuid __user *cpuid_arg = argp; 3257 struct kvm_cpuid cpuid; 3258 3259 r = -EFAULT; 3260 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3261 goto out; 3262 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3263 break; 3264 } 3265 case KVM_SET_CPUID2: { 3266 struct kvm_cpuid2 __user *cpuid_arg = argp; 3267 struct kvm_cpuid2 cpuid; 3268 3269 r = -EFAULT; 3270 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3271 goto out; 3272 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3273 cpuid_arg->entries); 3274 break; 3275 } 3276 case KVM_GET_CPUID2: { 3277 struct kvm_cpuid2 __user *cpuid_arg = argp; 3278 struct kvm_cpuid2 cpuid; 3279 3280 r = -EFAULT; 3281 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3282 goto out; 3283 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3284 cpuid_arg->entries); 3285 if (r) 3286 goto out; 3287 r = -EFAULT; 3288 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3289 goto out; 3290 r = 0; 3291 break; 3292 } 3293 case KVM_GET_MSRS: 3294 r = msr_io(vcpu, argp, do_get_msr, 1); 3295 break; 3296 case KVM_SET_MSRS: 3297 r = msr_io(vcpu, argp, do_set_msr, 0); 3298 break; 3299 case KVM_TPR_ACCESS_REPORTING: { 3300 struct kvm_tpr_access_ctl tac; 3301 3302 r = -EFAULT; 3303 if (copy_from_user(&tac, argp, sizeof tac)) 3304 goto out; 3305 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3306 if (r) 3307 goto out; 3308 r = -EFAULT; 3309 if (copy_to_user(argp, &tac, sizeof tac)) 3310 goto out; 3311 r = 0; 3312 break; 3313 }; 3314 case KVM_SET_VAPIC_ADDR: { 3315 struct kvm_vapic_addr va; 3316 3317 r = -EINVAL; 3318 if (!lapic_in_kernel(vcpu)) 3319 goto out; 3320 r = -EFAULT; 3321 if (copy_from_user(&va, argp, sizeof va)) 3322 goto out; 3323 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3324 break; 3325 } 3326 case KVM_X86_SETUP_MCE: { 3327 u64 mcg_cap; 3328 3329 r = -EFAULT; 3330 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3331 goto out; 3332 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3333 break; 3334 } 3335 case KVM_X86_SET_MCE: { 3336 struct kvm_x86_mce mce; 3337 3338 r = -EFAULT; 3339 if (copy_from_user(&mce, argp, sizeof mce)) 3340 goto out; 3341 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3342 break; 3343 } 3344 case KVM_GET_VCPU_EVENTS: { 3345 struct kvm_vcpu_events events; 3346 3347 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3348 3349 r = -EFAULT; 3350 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3351 break; 3352 r = 0; 3353 break; 3354 } 3355 case KVM_SET_VCPU_EVENTS: { 3356 struct kvm_vcpu_events events; 3357 3358 r = -EFAULT; 3359 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3360 break; 3361 3362 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3363 break; 3364 } 3365 case KVM_GET_DEBUGREGS: { 3366 struct kvm_debugregs dbgregs; 3367 3368 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3369 3370 r = -EFAULT; 3371 if (copy_to_user(argp, &dbgregs, 3372 sizeof(struct kvm_debugregs))) 3373 break; 3374 r = 0; 3375 break; 3376 } 3377 case KVM_SET_DEBUGREGS: { 3378 struct kvm_debugregs dbgregs; 3379 3380 r = -EFAULT; 3381 if (copy_from_user(&dbgregs, argp, 3382 sizeof(struct kvm_debugregs))) 3383 break; 3384 3385 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3386 break; 3387 } 3388 case KVM_GET_XSAVE: { 3389 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3390 r = -ENOMEM; 3391 if (!u.xsave) 3392 break; 3393 3394 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3395 3396 r = -EFAULT; 3397 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3398 break; 3399 r = 0; 3400 break; 3401 } 3402 case KVM_SET_XSAVE: { 3403 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3404 if (IS_ERR(u.xsave)) 3405 return PTR_ERR(u.xsave); 3406 3407 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3408 break; 3409 } 3410 case KVM_GET_XCRS: { 3411 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3412 r = -ENOMEM; 3413 if (!u.xcrs) 3414 break; 3415 3416 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3417 3418 r = -EFAULT; 3419 if (copy_to_user(argp, u.xcrs, 3420 sizeof(struct kvm_xcrs))) 3421 break; 3422 r = 0; 3423 break; 3424 } 3425 case KVM_SET_XCRS: { 3426 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3427 if (IS_ERR(u.xcrs)) 3428 return PTR_ERR(u.xcrs); 3429 3430 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3431 break; 3432 } 3433 case KVM_SET_TSC_KHZ: { 3434 u32 user_tsc_khz; 3435 3436 r = -EINVAL; 3437 user_tsc_khz = (u32)arg; 3438 3439 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3440 goto out; 3441 3442 if (user_tsc_khz == 0) 3443 user_tsc_khz = tsc_khz; 3444 3445 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 3446 r = 0; 3447 3448 goto out; 3449 } 3450 case KVM_GET_TSC_KHZ: { 3451 r = vcpu->arch.virtual_tsc_khz; 3452 goto out; 3453 } 3454 case KVM_KVMCLOCK_CTRL: { 3455 r = kvm_set_guest_paused(vcpu); 3456 goto out; 3457 } 3458 default: 3459 r = -EINVAL; 3460 } 3461 out: 3462 kfree(u.buffer); 3463 return r; 3464 } 3465 3466 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3467 { 3468 return VM_FAULT_SIGBUS; 3469 } 3470 3471 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3472 { 3473 int ret; 3474 3475 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3476 return -EINVAL; 3477 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3478 return ret; 3479 } 3480 3481 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3482 u64 ident_addr) 3483 { 3484 kvm->arch.ept_identity_map_addr = ident_addr; 3485 return 0; 3486 } 3487 3488 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3489 u32 kvm_nr_mmu_pages) 3490 { 3491 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3492 return -EINVAL; 3493 3494 mutex_lock(&kvm->slots_lock); 3495 3496 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3497 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3498 3499 mutex_unlock(&kvm->slots_lock); 3500 return 0; 3501 } 3502 3503 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 3504 { 3505 return kvm->arch.n_max_mmu_pages; 3506 } 3507 3508 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3509 { 3510 int r; 3511 3512 r = 0; 3513 switch (chip->chip_id) { 3514 case KVM_IRQCHIP_PIC_MASTER: 3515 memcpy(&chip->chip.pic, 3516 &pic_irqchip(kvm)->pics[0], 3517 sizeof(struct kvm_pic_state)); 3518 break; 3519 case KVM_IRQCHIP_PIC_SLAVE: 3520 memcpy(&chip->chip.pic, 3521 &pic_irqchip(kvm)->pics[1], 3522 sizeof(struct kvm_pic_state)); 3523 break; 3524 case KVM_IRQCHIP_IOAPIC: 3525 r = kvm_get_ioapic(kvm, &chip->chip.ioapic); 3526 break; 3527 default: 3528 r = -EINVAL; 3529 break; 3530 } 3531 return r; 3532 } 3533 3534 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3535 { 3536 int r; 3537 3538 r = 0; 3539 switch (chip->chip_id) { 3540 case KVM_IRQCHIP_PIC_MASTER: 3541 spin_lock(&pic_irqchip(kvm)->lock); 3542 memcpy(&pic_irqchip(kvm)->pics[0], 3543 &chip->chip.pic, 3544 sizeof(struct kvm_pic_state)); 3545 spin_unlock(&pic_irqchip(kvm)->lock); 3546 break; 3547 case KVM_IRQCHIP_PIC_SLAVE: 3548 spin_lock(&pic_irqchip(kvm)->lock); 3549 memcpy(&pic_irqchip(kvm)->pics[1], 3550 &chip->chip.pic, 3551 sizeof(struct kvm_pic_state)); 3552 spin_unlock(&pic_irqchip(kvm)->lock); 3553 break; 3554 case KVM_IRQCHIP_IOAPIC: 3555 r = kvm_set_ioapic(kvm, &chip->chip.ioapic); 3556 break; 3557 default: 3558 r = -EINVAL; 3559 break; 3560 } 3561 kvm_pic_update_irq(pic_irqchip(kvm)); 3562 return r; 3563 } 3564 3565 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3566 { 3567 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3568 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); 3569 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3570 return 0; 3571 } 3572 3573 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3574 { 3575 int i; 3576 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3577 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); 3578 for (i = 0; i < 3; i++) 3579 kvm_pit_load_count(kvm, i, ps->channels[i].count, 0); 3580 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3581 return 0; 3582 } 3583 3584 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3585 { 3586 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3587 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 3588 sizeof(ps->channels)); 3589 ps->flags = kvm->arch.vpit->pit_state.flags; 3590 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3591 memset(&ps->reserved, 0, sizeof(ps->reserved)); 3592 return 0; 3593 } 3594 3595 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3596 { 3597 int start = 0; 3598 int i; 3599 u32 prev_legacy, cur_legacy; 3600 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3601 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 3602 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 3603 if (!prev_legacy && cur_legacy) 3604 start = 1; 3605 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, 3606 sizeof(kvm->arch.vpit->pit_state.channels)); 3607 kvm->arch.vpit->pit_state.flags = ps->flags; 3608 for (i = 0; i < 3; i++) 3609 kvm_pit_load_count(kvm, i, kvm->arch.vpit->pit_state.channels[i].count, start); 3610 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3611 return 0; 3612 } 3613 3614 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 3615 struct kvm_reinject_control *control) 3616 { 3617 if (!kvm->arch.vpit) 3618 return -ENXIO; 3619 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3620 kvm->arch.vpit->pit_state.reinject = control->pit_reinject; 3621 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3622 return 0; 3623 } 3624 3625 /** 3626 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 3627 * @kvm: kvm instance 3628 * @log: slot id and address to which we copy the log 3629 * 3630 * Steps 1-4 below provide general overview of dirty page logging. See 3631 * kvm_get_dirty_log_protect() function description for additional details. 3632 * 3633 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 3634 * always flush the TLB (step 4) even if previous step failed and the dirty 3635 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 3636 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 3637 * writes will be marked dirty for next log read. 3638 * 3639 * 1. Take a snapshot of the bit and clear it if needed. 3640 * 2. Write protect the corresponding page. 3641 * 3. Copy the snapshot to the userspace. 3642 * 4. Flush TLB's if needed. 3643 */ 3644 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 3645 { 3646 bool is_dirty = false; 3647 int r; 3648 3649 mutex_lock(&kvm->slots_lock); 3650 3651 /* 3652 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 3653 */ 3654 if (kvm_x86_ops->flush_log_dirty) 3655 kvm_x86_ops->flush_log_dirty(kvm); 3656 3657 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 3658 3659 /* 3660 * All the TLBs can be flushed out of mmu lock, see the comments in 3661 * kvm_mmu_slot_remove_write_access(). 3662 */ 3663 lockdep_assert_held(&kvm->slots_lock); 3664 if (is_dirty) 3665 kvm_flush_remote_tlbs(kvm); 3666 3667 mutex_unlock(&kvm->slots_lock); 3668 return r; 3669 } 3670 3671 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 3672 bool line_status) 3673 { 3674 if (!irqchip_in_kernel(kvm)) 3675 return -ENXIO; 3676 3677 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 3678 irq_event->irq, irq_event->level, 3679 line_status); 3680 return 0; 3681 } 3682 3683 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 3684 struct kvm_enable_cap *cap) 3685 { 3686 int r; 3687 3688 if (cap->flags) 3689 return -EINVAL; 3690 3691 switch (cap->cap) { 3692 case KVM_CAP_DISABLE_QUIRKS: 3693 kvm->arch.disabled_quirks = cap->args[0]; 3694 r = 0; 3695 break; 3696 case KVM_CAP_SPLIT_IRQCHIP: { 3697 mutex_lock(&kvm->lock); 3698 r = -EINVAL; 3699 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 3700 goto split_irqchip_unlock; 3701 r = -EEXIST; 3702 if (irqchip_in_kernel(kvm)) 3703 goto split_irqchip_unlock; 3704 if (atomic_read(&kvm->online_vcpus)) 3705 goto split_irqchip_unlock; 3706 r = kvm_setup_empty_irq_routing(kvm); 3707 if (r) 3708 goto split_irqchip_unlock; 3709 /* Pairs with irqchip_in_kernel. */ 3710 smp_wmb(); 3711 kvm->arch.irqchip_split = true; 3712 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 3713 r = 0; 3714 split_irqchip_unlock: 3715 mutex_unlock(&kvm->lock); 3716 break; 3717 } 3718 default: 3719 r = -EINVAL; 3720 break; 3721 } 3722 return r; 3723 } 3724 3725 long kvm_arch_vm_ioctl(struct file *filp, 3726 unsigned int ioctl, unsigned long arg) 3727 { 3728 struct kvm *kvm = filp->private_data; 3729 void __user *argp = (void __user *)arg; 3730 int r = -ENOTTY; 3731 /* 3732 * This union makes it completely explicit to gcc-3.x 3733 * that these two variables' stack usage should be 3734 * combined, not added together. 3735 */ 3736 union { 3737 struct kvm_pit_state ps; 3738 struct kvm_pit_state2 ps2; 3739 struct kvm_pit_config pit_config; 3740 } u; 3741 3742 switch (ioctl) { 3743 case KVM_SET_TSS_ADDR: 3744 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 3745 break; 3746 case KVM_SET_IDENTITY_MAP_ADDR: { 3747 u64 ident_addr; 3748 3749 r = -EFAULT; 3750 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 3751 goto out; 3752 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 3753 break; 3754 } 3755 case KVM_SET_NR_MMU_PAGES: 3756 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 3757 break; 3758 case KVM_GET_NR_MMU_PAGES: 3759 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 3760 break; 3761 case KVM_CREATE_IRQCHIP: { 3762 struct kvm_pic *vpic; 3763 3764 mutex_lock(&kvm->lock); 3765 r = -EEXIST; 3766 if (kvm->arch.vpic) 3767 goto create_irqchip_unlock; 3768 r = -EINVAL; 3769 if (atomic_read(&kvm->online_vcpus)) 3770 goto create_irqchip_unlock; 3771 r = -ENOMEM; 3772 vpic = kvm_create_pic(kvm); 3773 if (vpic) { 3774 r = kvm_ioapic_init(kvm); 3775 if (r) { 3776 mutex_lock(&kvm->slots_lock); 3777 kvm_destroy_pic(vpic); 3778 mutex_unlock(&kvm->slots_lock); 3779 goto create_irqchip_unlock; 3780 } 3781 } else 3782 goto create_irqchip_unlock; 3783 r = kvm_setup_default_irq_routing(kvm); 3784 if (r) { 3785 mutex_lock(&kvm->slots_lock); 3786 mutex_lock(&kvm->irq_lock); 3787 kvm_ioapic_destroy(kvm); 3788 kvm_destroy_pic(vpic); 3789 mutex_unlock(&kvm->irq_lock); 3790 mutex_unlock(&kvm->slots_lock); 3791 goto create_irqchip_unlock; 3792 } 3793 /* Write kvm->irq_routing before kvm->arch.vpic. */ 3794 smp_wmb(); 3795 kvm->arch.vpic = vpic; 3796 create_irqchip_unlock: 3797 mutex_unlock(&kvm->lock); 3798 break; 3799 } 3800 case KVM_CREATE_PIT: 3801 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 3802 goto create_pit; 3803 case KVM_CREATE_PIT2: 3804 r = -EFAULT; 3805 if (copy_from_user(&u.pit_config, argp, 3806 sizeof(struct kvm_pit_config))) 3807 goto out; 3808 create_pit: 3809 mutex_lock(&kvm->slots_lock); 3810 r = -EEXIST; 3811 if (kvm->arch.vpit) 3812 goto create_pit_unlock; 3813 r = -ENOMEM; 3814 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 3815 if (kvm->arch.vpit) 3816 r = 0; 3817 create_pit_unlock: 3818 mutex_unlock(&kvm->slots_lock); 3819 break; 3820 case KVM_GET_IRQCHIP: { 3821 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3822 struct kvm_irqchip *chip; 3823 3824 chip = memdup_user(argp, sizeof(*chip)); 3825 if (IS_ERR(chip)) { 3826 r = PTR_ERR(chip); 3827 goto out; 3828 } 3829 3830 r = -ENXIO; 3831 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm)) 3832 goto get_irqchip_out; 3833 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 3834 if (r) 3835 goto get_irqchip_out; 3836 r = -EFAULT; 3837 if (copy_to_user(argp, chip, sizeof *chip)) 3838 goto get_irqchip_out; 3839 r = 0; 3840 get_irqchip_out: 3841 kfree(chip); 3842 break; 3843 } 3844 case KVM_SET_IRQCHIP: { 3845 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3846 struct kvm_irqchip *chip; 3847 3848 chip = memdup_user(argp, sizeof(*chip)); 3849 if (IS_ERR(chip)) { 3850 r = PTR_ERR(chip); 3851 goto out; 3852 } 3853 3854 r = -ENXIO; 3855 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm)) 3856 goto set_irqchip_out; 3857 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 3858 if (r) 3859 goto set_irqchip_out; 3860 r = 0; 3861 set_irqchip_out: 3862 kfree(chip); 3863 break; 3864 } 3865 case KVM_GET_PIT: { 3866 r = -EFAULT; 3867 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 3868 goto out; 3869 r = -ENXIO; 3870 if (!kvm->arch.vpit) 3871 goto out; 3872 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 3873 if (r) 3874 goto out; 3875 r = -EFAULT; 3876 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 3877 goto out; 3878 r = 0; 3879 break; 3880 } 3881 case KVM_SET_PIT: { 3882 r = -EFAULT; 3883 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 3884 goto out; 3885 r = -ENXIO; 3886 if (!kvm->arch.vpit) 3887 goto out; 3888 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 3889 break; 3890 } 3891 case KVM_GET_PIT2: { 3892 r = -ENXIO; 3893 if (!kvm->arch.vpit) 3894 goto out; 3895 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 3896 if (r) 3897 goto out; 3898 r = -EFAULT; 3899 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 3900 goto out; 3901 r = 0; 3902 break; 3903 } 3904 case KVM_SET_PIT2: { 3905 r = -EFAULT; 3906 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 3907 goto out; 3908 r = -ENXIO; 3909 if (!kvm->arch.vpit) 3910 goto out; 3911 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 3912 break; 3913 } 3914 case KVM_REINJECT_CONTROL: { 3915 struct kvm_reinject_control control; 3916 r = -EFAULT; 3917 if (copy_from_user(&control, argp, sizeof(control))) 3918 goto out; 3919 r = kvm_vm_ioctl_reinject(kvm, &control); 3920 break; 3921 } 3922 case KVM_SET_BOOT_CPU_ID: 3923 r = 0; 3924 mutex_lock(&kvm->lock); 3925 if (atomic_read(&kvm->online_vcpus) != 0) 3926 r = -EBUSY; 3927 else 3928 kvm->arch.bsp_vcpu_id = arg; 3929 mutex_unlock(&kvm->lock); 3930 break; 3931 case KVM_XEN_HVM_CONFIG: { 3932 r = -EFAULT; 3933 if (copy_from_user(&kvm->arch.xen_hvm_config, argp, 3934 sizeof(struct kvm_xen_hvm_config))) 3935 goto out; 3936 r = -EINVAL; 3937 if (kvm->arch.xen_hvm_config.flags) 3938 goto out; 3939 r = 0; 3940 break; 3941 } 3942 case KVM_SET_CLOCK: { 3943 struct kvm_clock_data user_ns; 3944 u64 now_ns; 3945 s64 delta; 3946 3947 r = -EFAULT; 3948 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 3949 goto out; 3950 3951 r = -EINVAL; 3952 if (user_ns.flags) 3953 goto out; 3954 3955 r = 0; 3956 local_irq_disable(); 3957 now_ns = get_kernel_ns(); 3958 delta = user_ns.clock - now_ns; 3959 local_irq_enable(); 3960 kvm->arch.kvmclock_offset = delta; 3961 kvm_gen_update_masterclock(kvm); 3962 break; 3963 } 3964 case KVM_GET_CLOCK: { 3965 struct kvm_clock_data user_ns; 3966 u64 now_ns; 3967 3968 local_irq_disable(); 3969 now_ns = get_kernel_ns(); 3970 user_ns.clock = kvm->arch.kvmclock_offset + now_ns; 3971 local_irq_enable(); 3972 user_ns.flags = 0; 3973 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 3974 3975 r = -EFAULT; 3976 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 3977 goto out; 3978 r = 0; 3979 break; 3980 } 3981 case KVM_ENABLE_CAP: { 3982 struct kvm_enable_cap cap; 3983 3984 r = -EFAULT; 3985 if (copy_from_user(&cap, argp, sizeof(cap))) 3986 goto out; 3987 r = kvm_vm_ioctl_enable_cap(kvm, &cap); 3988 break; 3989 } 3990 default: 3991 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg); 3992 } 3993 out: 3994 return r; 3995 } 3996 3997 static void kvm_init_msr_list(void) 3998 { 3999 u32 dummy[2]; 4000 unsigned i, j; 4001 4002 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { 4003 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4004 continue; 4005 4006 /* 4007 * Even MSRs that are valid in the host may not be exposed 4008 * to the guests in some cases. We could work around this 4009 * in VMX with the generic MSR save/load machinery, but it 4010 * is not really worthwhile since it will really only 4011 * happen with nested virtualization. 4012 */ 4013 switch (msrs_to_save[i]) { 4014 case MSR_IA32_BNDCFGS: 4015 if (!kvm_x86_ops->mpx_supported()) 4016 continue; 4017 break; 4018 default: 4019 break; 4020 } 4021 4022 if (j < i) 4023 msrs_to_save[j] = msrs_to_save[i]; 4024 j++; 4025 } 4026 num_msrs_to_save = j; 4027 4028 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { 4029 switch (emulated_msrs[i]) { 4030 case MSR_IA32_SMBASE: 4031 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase()) 4032 continue; 4033 break; 4034 default: 4035 break; 4036 } 4037 4038 if (j < i) 4039 emulated_msrs[j] = emulated_msrs[i]; 4040 j++; 4041 } 4042 num_emulated_msrs = j; 4043 } 4044 4045 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 4046 const void *v) 4047 { 4048 int handled = 0; 4049 int n; 4050 4051 do { 4052 n = min(len, 8); 4053 if (!(vcpu->arch.apic && 4054 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 4055 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 4056 break; 4057 handled += n; 4058 addr += n; 4059 len -= n; 4060 v += n; 4061 } while (len); 4062 4063 return handled; 4064 } 4065 4066 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4067 { 4068 int handled = 0; 4069 int n; 4070 4071 do { 4072 n = min(len, 8); 4073 if (!(vcpu->arch.apic && 4074 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 4075 addr, n, v)) 4076 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 4077 break; 4078 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); 4079 handled += n; 4080 addr += n; 4081 len -= n; 4082 v += n; 4083 } while (len); 4084 4085 return handled; 4086 } 4087 4088 static void kvm_set_segment(struct kvm_vcpu *vcpu, 4089 struct kvm_segment *var, int seg) 4090 { 4091 kvm_x86_ops->set_segment(vcpu, var, seg); 4092 } 4093 4094 void kvm_get_segment(struct kvm_vcpu *vcpu, 4095 struct kvm_segment *var, int seg) 4096 { 4097 kvm_x86_ops->get_segment(vcpu, var, seg); 4098 } 4099 4100 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 4101 struct x86_exception *exception) 4102 { 4103 gpa_t t_gpa; 4104 4105 BUG_ON(!mmu_is_nested(vcpu)); 4106 4107 /* NPT walks are always user-walks */ 4108 access |= PFERR_USER_MASK; 4109 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); 4110 4111 return t_gpa; 4112 } 4113 4114 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 4115 struct x86_exception *exception) 4116 { 4117 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4118 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4119 } 4120 4121 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 4122 struct x86_exception *exception) 4123 { 4124 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4125 access |= PFERR_FETCH_MASK; 4126 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4127 } 4128 4129 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 4130 struct x86_exception *exception) 4131 { 4132 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4133 access |= PFERR_WRITE_MASK; 4134 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4135 } 4136 4137 /* uses this to access any guest's mapped memory without checking CPL */ 4138 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 4139 struct x86_exception *exception) 4140 { 4141 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 4142 } 4143 4144 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 4145 struct kvm_vcpu *vcpu, u32 access, 4146 struct x86_exception *exception) 4147 { 4148 void *data = val; 4149 int r = X86EMUL_CONTINUE; 4150 4151 while (bytes) { 4152 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 4153 exception); 4154 unsigned offset = addr & (PAGE_SIZE-1); 4155 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 4156 int ret; 4157 4158 if (gpa == UNMAPPED_GVA) 4159 return X86EMUL_PROPAGATE_FAULT; 4160 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 4161 offset, toread); 4162 if (ret < 0) { 4163 r = X86EMUL_IO_NEEDED; 4164 goto out; 4165 } 4166 4167 bytes -= toread; 4168 data += toread; 4169 addr += toread; 4170 } 4171 out: 4172 return r; 4173 } 4174 4175 /* used for instruction fetching */ 4176 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4177 gva_t addr, void *val, unsigned int bytes, 4178 struct x86_exception *exception) 4179 { 4180 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4181 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4182 unsigned offset; 4183 int ret; 4184 4185 /* Inline kvm_read_guest_virt_helper for speed. */ 4186 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 4187 exception); 4188 if (unlikely(gpa == UNMAPPED_GVA)) 4189 return X86EMUL_PROPAGATE_FAULT; 4190 4191 offset = addr & (PAGE_SIZE-1); 4192 if (WARN_ON(offset + bytes > PAGE_SIZE)) 4193 bytes = (unsigned)PAGE_SIZE - offset; 4194 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 4195 offset, bytes); 4196 if (unlikely(ret < 0)) 4197 return X86EMUL_IO_NEEDED; 4198 4199 return X86EMUL_CONTINUE; 4200 } 4201 4202 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4203 gva_t addr, void *val, unsigned int bytes, 4204 struct x86_exception *exception) 4205 { 4206 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4207 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4208 4209 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4210 exception); 4211 } 4212 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4213 4214 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4215 gva_t addr, void *val, unsigned int bytes, 4216 struct x86_exception *exception) 4217 { 4218 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4219 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4220 } 4221 4222 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 4223 unsigned long addr, void *val, unsigned int bytes) 4224 { 4225 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4226 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 4227 4228 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 4229 } 4230 4231 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4232 gva_t addr, void *val, 4233 unsigned int bytes, 4234 struct x86_exception *exception) 4235 { 4236 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4237 void *data = val; 4238 int r = X86EMUL_CONTINUE; 4239 4240 while (bytes) { 4241 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4242 PFERR_WRITE_MASK, 4243 exception); 4244 unsigned offset = addr & (PAGE_SIZE-1); 4245 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4246 int ret; 4247 4248 if (gpa == UNMAPPED_GVA) 4249 return X86EMUL_PROPAGATE_FAULT; 4250 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 4251 if (ret < 0) { 4252 r = X86EMUL_IO_NEEDED; 4253 goto out; 4254 } 4255 4256 bytes -= towrite; 4257 data += towrite; 4258 addr += towrite; 4259 } 4260 out: 4261 return r; 4262 } 4263 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4264 4265 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4266 gpa_t *gpa, struct x86_exception *exception, 4267 bool write) 4268 { 4269 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4270 | (write ? PFERR_WRITE_MASK : 0); 4271 4272 if (vcpu_match_mmio_gva(vcpu, gva) 4273 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4274 vcpu->arch.access, access)) { 4275 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4276 (gva & (PAGE_SIZE - 1)); 4277 trace_vcpu_match_mmio(gva, *gpa, write, false); 4278 return 1; 4279 } 4280 4281 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4282 4283 if (*gpa == UNMAPPED_GVA) 4284 return -1; 4285 4286 /* For APIC access vmexit */ 4287 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4288 return 1; 4289 4290 if (vcpu_match_mmio_gpa(vcpu, *gpa)) { 4291 trace_vcpu_match_mmio(gva, *gpa, write, true); 4292 return 1; 4293 } 4294 4295 return 0; 4296 } 4297 4298 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4299 const void *val, int bytes) 4300 { 4301 int ret; 4302 4303 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 4304 if (ret < 0) 4305 return 0; 4306 kvm_mmu_pte_write(vcpu, gpa, val, bytes); 4307 return 1; 4308 } 4309 4310 struct read_write_emulator_ops { 4311 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4312 int bytes); 4313 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4314 void *val, int bytes); 4315 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4316 int bytes, void *val); 4317 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4318 void *val, int bytes); 4319 bool write; 4320 }; 4321 4322 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4323 { 4324 if (vcpu->mmio_read_completed) { 4325 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4326 vcpu->mmio_fragments[0].gpa, *(u64 *)val); 4327 vcpu->mmio_read_completed = 0; 4328 return 1; 4329 } 4330 4331 return 0; 4332 } 4333 4334 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4335 void *val, int bytes) 4336 { 4337 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 4338 } 4339 4340 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4341 void *val, int bytes) 4342 { 4343 return emulator_write_phys(vcpu, gpa, val, bytes); 4344 } 4345 4346 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4347 { 4348 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); 4349 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4350 } 4351 4352 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4353 void *val, int bytes) 4354 { 4355 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); 4356 return X86EMUL_IO_NEEDED; 4357 } 4358 4359 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4360 void *val, int bytes) 4361 { 4362 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4363 4364 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4365 return X86EMUL_CONTINUE; 4366 } 4367 4368 static const struct read_write_emulator_ops read_emultor = { 4369 .read_write_prepare = read_prepare, 4370 .read_write_emulate = read_emulate, 4371 .read_write_mmio = vcpu_mmio_read, 4372 .read_write_exit_mmio = read_exit_mmio, 4373 }; 4374 4375 static const struct read_write_emulator_ops write_emultor = { 4376 .read_write_emulate = write_emulate, 4377 .read_write_mmio = write_mmio, 4378 .read_write_exit_mmio = write_exit_mmio, 4379 .write = true, 4380 }; 4381 4382 static int emulator_read_write_onepage(unsigned long addr, void *val, 4383 unsigned int bytes, 4384 struct x86_exception *exception, 4385 struct kvm_vcpu *vcpu, 4386 const struct read_write_emulator_ops *ops) 4387 { 4388 gpa_t gpa; 4389 int handled, ret; 4390 bool write = ops->write; 4391 struct kvm_mmio_fragment *frag; 4392 4393 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 4394 4395 if (ret < 0) 4396 return X86EMUL_PROPAGATE_FAULT; 4397 4398 /* For APIC access vmexit */ 4399 if (ret) 4400 goto mmio; 4401 4402 if (ops->read_write_emulate(vcpu, gpa, val, bytes)) 4403 return X86EMUL_CONTINUE; 4404 4405 mmio: 4406 /* 4407 * Is this MMIO handled locally? 4408 */ 4409 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 4410 if (handled == bytes) 4411 return X86EMUL_CONTINUE; 4412 4413 gpa += handled; 4414 bytes -= handled; 4415 val += handled; 4416 4417 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 4418 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 4419 frag->gpa = gpa; 4420 frag->data = val; 4421 frag->len = bytes; 4422 return X86EMUL_CONTINUE; 4423 } 4424 4425 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 4426 unsigned long addr, 4427 void *val, unsigned int bytes, 4428 struct x86_exception *exception, 4429 const struct read_write_emulator_ops *ops) 4430 { 4431 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4432 gpa_t gpa; 4433 int rc; 4434 4435 if (ops->read_write_prepare && 4436 ops->read_write_prepare(vcpu, val, bytes)) 4437 return X86EMUL_CONTINUE; 4438 4439 vcpu->mmio_nr_fragments = 0; 4440 4441 /* Crossing a page boundary? */ 4442 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 4443 int now; 4444 4445 now = -addr & ~PAGE_MASK; 4446 rc = emulator_read_write_onepage(addr, val, now, exception, 4447 vcpu, ops); 4448 4449 if (rc != X86EMUL_CONTINUE) 4450 return rc; 4451 addr += now; 4452 if (ctxt->mode != X86EMUL_MODE_PROT64) 4453 addr = (u32)addr; 4454 val += now; 4455 bytes -= now; 4456 } 4457 4458 rc = emulator_read_write_onepage(addr, val, bytes, exception, 4459 vcpu, ops); 4460 if (rc != X86EMUL_CONTINUE) 4461 return rc; 4462 4463 if (!vcpu->mmio_nr_fragments) 4464 return rc; 4465 4466 gpa = vcpu->mmio_fragments[0].gpa; 4467 4468 vcpu->mmio_needed = 1; 4469 vcpu->mmio_cur_fragment = 0; 4470 4471 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 4472 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 4473 vcpu->run->exit_reason = KVM_EXIT_MMIO; 4474 vcpu->run->mmio.phys_addr = gpa; 4475 4476 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 4477 } 4478 4479 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 4480 unsigned long addr, 4481 void *val, 4482 unsigned int bytes, 4483 struct x86_exception *exception) 4484 { 4485 return emulator_read_write(ctxt, addr, val, bytes, 4486 exception, &read_emultor); 4487 } 4488 4489 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 4490 unsigned long addr, 4491 const void *val, 4492 unsigned int bytes, 4493 struct x86_exception *exception) 4494 { 4495 return emulator_read_write(ctxt, addr, (void *)val, bytes, 4496 exception, &write_emultor); 4497 } 4498 4499 #define CMPXCHG_TYPE(t, ptr, old, new) \ 4500 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 4501 4502 #ifdef CONFIG_X86_64 4503 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 4504 #else 4505 # define CMPXCHG64(ptr, old, new) \ 4506 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 4507 #endif 4508 4509 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 4510 unsigned long addr, 4511 const void *old, 4512 const void *new, 4513 unsigned int bytes, 4514 struct x86_exception *exception) 4515 { 4516 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4517 gpa_t gpa; 4518 struct page *page; 4519 char *kaddr; 4520 bool exchanged; 4521 4522 /* guests cmpxchg8b have to be emulated atomically */ 4523 if (bytes > 8 || (bytes & (bytes - 1))) 4524 goto emul_write; 4525 4526 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 4527 4528 if (gpa == UNMAPPED_GVA || 4529 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4530 goto emul_write; 4531 4532 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 4533 goto emul_write; 4534 4535 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); 4536 if (is_error_page(page)) 4537 goto emul_write; 4538 4539 kaddr = kmap_atomic(page); 4540 kaddr += offset_in_page(gpa); 4541 switch (bytes) { 4542 case 1: 4543 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 4544 break; 4545 case 2: 4546 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 4547 break; 4548 case 4: 4549 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 4550 break; 4551 case 8: 4552 exchanged = CMPXCHG64(kaddr, old, new); 4553 break; 4554 default: 4555 BUG(); 4556 } 4557 kunmap_atomic(kaddr); 4558 kvm_release_page_dirty(page); 4559 4560 if (!exchanged) 4561 return X86EMUL_CMPXCHG_FAILED; 4562 4563 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 4564 kvm_mmu_pte_write(vcpu, gpa, new, bytes); 4565 4566 return X86EMUL_CONTINUE; 4567 4568 emul_write: 4569 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 4570 4571 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 4572 } 4573 4574 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 4575 { 4576 /* TODO: String I/O for in kernel device */ 4577 int r; 4578 4579 if (vcpu->arch.pio.in) 4580 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 4581 vcpu->arch.pio.size, pd); 4582 else 4583 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 4584 vcpu->arch.pio.port, vcpu->arch.pio.size, 4585 pd); 4586 return r; 4587 } 4588 4589 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 4590 unsigned short port, void *val, 4591 unsigned int count, bool in) 4592 { 4593 vcpu->arch.pio.port = port; 4594 vcpu->arch.pio.in = in; 4595 vcpu->arch.pio.count = count; 4596 vcpu->arch.pio.size = size; 4597 4598 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 4599 vcpu->arch.pio.count = 0; 4600 return 1; 4601 } 4602 4603 vcpu->run->exit_reason = KVM_EXIT_IO; 4604 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 4605 vcpu->run->io.size = size; 4606 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 4607 vcpu->run->io.count = count; 4608 vcpu->run->io.port = port; 4609 4610 return 0; 4611 } 4612 4613 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 4614 int size, unsigned short port, void *val, 4615 unsigned int count) 4616 { 4617 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4618 int ret; 4619 4620 if (vcpu->arch.pio.count) 4621 goto data_avail; 4622 4623 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 4624 if (ret) { 4625 data_avail: 4626 memcpy(val, vcpu->arch.pio_data, size * count); 4627 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 4628 vcpu->arch.pio.count = 0; 4629 return 1; 4630 } 4631 4632 return 0; 4633 } 4634 4635 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 4636 int size, unsigned short port, 4637 const void *val, unsigned int count) 4638 { 4639 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4640 4641 memcpy(vcpu->arch.pio_data, val, size * count); 4642 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 4643 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 4644 } 4645 4646 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 4647 { 4648 return kvm_x86_ops->get_segment_base(vcpu, seg); 4649 } 4650 4651 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 4652 { 4653 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 4654 } 4655 4656 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 4657 { 4658 if (!need_emulate_wbinvd(vcpu)) 4659 return X86EMUL_CONTINUE; 4660 4661 if (kvm_x86_ops->has_wbinvd_exit()) { 4662 int cpu = get_cpu(); 4663 4664 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4665 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 4666 wbinvd_ipi, NULL, 1); 4667 put_cpu(); 4668 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 4669 } else 4670 wbinvd(); 4671 return X86EMUL_CONTINUE; 4672 } 4673 4674 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 4675 { 4676 kvm_x86_ops->skip_emulated_instruction(vcpu); 4677 return kvm_emulate_wbinvd_noskip(vcpu); 4678 } 4679 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 4680 4681 4682 4683 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 4684 { 4685 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 4686 } 4687 4688 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 4689 unsigned long *dest) 4690 { 4691 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 4692 } 4693 4694 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 4695 unsigned long value) 4696 { 4697 4698 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 4699 } 4700 4701 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 4702 { 4703 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 4704 } 4705 4706 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 4707 { 4708 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4709 unsigned long value; 4710 4711 switch (cr) { 4712 case 0: 4713 value = kvm_read_cr0(vcpu); 4714 break; 4715 case 2: 4716 value = vcpu->arch.cr2; 4717 break; 4718 case 3: 4719 value = kvm_read_cr3(vcpu); 4720 break; 4721 case 4: 4722 value = kvm_read_cr4(vcpu); 4723 break; 4724 case 8: 4725 value = kvm_get_cr8(vcpu); 4726 break; 4727 default: 4728 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4729 return 0; 4730 } 4731 4732 return value; 4733 } 4734 4735 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 4736 { 4737 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4738 int res = 0; 4739 4740 switch (cr) { 4741 case 0: 4742 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 4743 break; 4744 case 2: 4745 vcpu->arch.cr2 = val; 4746 break; 4747 case 3: 4748 res = kvm_set_cr3(vcpu, val); 4749 break; 4750 case 4: 4751 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 4752 break; 4753 case 8: 4754 res = kvm_set_cr8(vcpu, val); 4755 break; 4756 default: 4757 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4758 res = -1; 4759 } 4760 4761 return res; 4762 } 4763 4764 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 4765 { 4766 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 4767 } 4768 4769 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4770 { 4771 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 4772 } 4773 4774 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4775 { 4776 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 4777 } 4778 4779 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4780 { 4781 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 4782 } 4783 4784 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4785 { 4786 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 4787 } 4788 4789 static unsigned long emulator_get_cached_segment_base( 4790 struct x86_emulate_ctxt *ctxt, int seg) 4791 { 4792 return get_segment_base(emul_to_vcpu(ctxt), seg); 4793 } 4794 4795 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 4796 struct desc_struct *desc, u32 *base3, 4797 int seg) 4798 { 4799 struct kvm_segment var; 4800 4801 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 4802 *selector = var.selector; 4803 4804 if (var.unusable) { 4805 memset(desc, 0, sizeof(*desc)); 4806 return false; 4807 } 4808 4809 if (var.g) 4810 var.limit >>= 12; 4811 set_desc_limit(desc, var.limit); 4812 set_desc_base(desc, (unsigned long)var.base); 4813 #ifdef CONFIG_X86_64 4814 if (base3) 4815 *base3 = var.base >> 32; 4816 #endif 4817 desc->type = var.type; 4818 desc->s = var.s; 4819 desc->dpl = var.dpl; 4820 desc->p = var.present; 4821 desc->avl = var.avl; 4822 desc->l = var.l; 4823 desc->d = var.db; 4824 desc->g = var.g; 4825 4826 return true; 4827 } 4828 4829 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 4830 struct desc_struct *desc, u32 base3, 4831 int seg) 4832 { 4833 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4834 struct kvm_segment var; 4835 4836 var.selector = selector; 4837 var.base = get_desc_base(desc); 4838 #ifdef CONFIG_X86_64 4839 var.base |= ((u64)base3) << 32; 4840 #endif 4841 var.limit = get_desc_limit(desc); 4842 if (desc->g) 4843 var.limit = (var.limit << 12) | 0xfff; 4844 var.type = desc->type; 4845 var.dpl = desc->dpl; 4846 var.db = desc->d; 4847 var.s = desc->s; 4848 var.l = desc->l; 4849 var.g = desc->g; 4850 var.avl = desc->avl; 4851 var.present = desc->p; 4852 var.unusable = !var.present; 4853 var.padding = 0; 4854 4855 kvm_set_segment(vcpu, &var, seg); 4856 return; 4857 } 4858 4859 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 4860 u32 msr_index, u64 *pdata) 4861 { 4862 struct msr_data msr; 4863 int r; 4864 4865 msr.index = msr_index; 4866 msr.host_initiated = false; 4867 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); 4868 if (r) 4869 return r; 4870 4871 *pdata = msr.data; 4872 return 0; 4873 } 4874 4875 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 4876 u32 msr_index, u64 data) 4877 { 4878 struct msr_data msr; 4879 4880 msr.data = data; 4881 msr.index = msr_index; 4882 msr.host_initiated = false; 4883 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 4884 } 4885 4886 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 4887 { 4888 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4889 4890 return vcpu->arch.smbase; 4891 } 4892 4893 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 4894 { 4895 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4896 4897 vcpu->arch.smbase = smbase; 4898 } 4899 4900 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 4901 u32 pmc) 4902 { 4903 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); 4904 } 4905 4906 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 4907 u32 pmc, u64 *pdata) 4908 { 4909 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 4910 } 4911 4912 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 4913 { 4914 emul_to_vcpu(ctxt)->arch.halt_request = 1; 4915 } 4916 4917 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) 4918 { 4919 preempt_disable(); 4920 kvm_load_guest_fpu(emul_to_vcpu(ctxt)); 4921 /* 4922 * CR0.TS may reference the host fpu state, not the guest fpu state, 4923 * so it may be clear at this point. 4924 */ 4925 clts(); 4926 } 4927 4928 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) 4929 { 4930 preempt_enable(); 4931 } 4932 4933 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 4934 struct x86_instruction_info *info, 4935 enum x86_intercept_stage stage) 4936 { 4937 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 4938 } 4939 4940 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 4941 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) 4942 { 4943 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); 4944 } 4945 4946 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 4947 { 4948 return kvm_register_read(emul_to_vcpu(ctxt), reg); 4949 } 4950 4951 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 4952 { 4953 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 4954 } 4955 4956 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 4957 { 4958 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 4959 } 4960 4961 static const struct x86_emulate_ops emulate_ops = { 4962 .read_gpr = emulator_read_gpr, 4963 .write_gpr = emulator_write_gpr, 4964 .read_std = kvm_read_guest_virt_system, 4965 .write_std = kvm_write_guest_virt_system, 4966 .read_phys = kvm_read_guest_phys_system, 4967 .fetch = kvm_fetch_guest_virt, 4968 .read_emulated = emulator_read_emulated, 4969 .write_emulated = emulator_write_emulated, 4970 .cmpxchg_emulated = emulator_cmpxchg_emulated, 4971 .invlpg = emulator_invlpg, 4972 .pio_in_emulated = emulator_pio_in_emulated, 4973 .pio_out_emulated = emulator_pio_out_emulated, 4974 .get_segment = emulator_get_segment, 4975 .set_segment = emulator_set_segment, 4976 .get_cached_segment_base = emulator_get_cached_segment_base, 4977 .get_gdt = emulator_get_gdt, 4978 .get_idt = emulator_get_idt, 4979 .set_gdt = emulator_set_gdt, 4980 .set_idt = emulator_set_idt, 4981 .get_cr = emulator_get_cr, 4982 .set_cr = emulator_set_cr, 4983 .cpl = emulator_get_cpl, 4984 .get_dr = emulator_get_dr, 4985 .set_dr = emulator_set_dr, 4986 .get_smbase = emulator_get_smbase, 4987 .set_smbase = emulator_set_smbase, 4988 .set_msr = emulator_set_msr, 4989 .get_msr = emulator_get_msr, 4990 .check_pmc = emulator_check_pmc, 4991 .read_pmc = emulator_read_pmc, 4992 .halt = emulator_halt, 4993 .wbinvd = emulator_wbinvd, 4994 .fix_hypercall = emulator_fix_hypercall, 4995 .get_fpu = emulator_get_fpu, 4996 .put_fpu = emulator_put_fpu, 4997 .intercept = emulator_intercept, 4998 .get_cpuid = emulator_get_cpuid, 4999 .set_nmi_mask = emulator_set_nmi_mask, 5000 }; 5001 5002 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 5003 { 5004 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 5005 /* 5006 * an sti; sti; sequence only disable interrupts for the first 5007 * instruction. So, if the last instruction, be it emulated or 5008 * not, left the system with the INT_STI flag enabled, it 5009 * means that the last instruction is an sti. We should not 5010 * leave the flag on in this case. The same goes for mov ss 5011 */ 5012 if (int_shadow & mask) 5013 mask = 0; 5014 if (unlikely(int_shadow || mask)) { 5015 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 5016 if (!mask) 5017 kvm_make_request(KVM_REQ_EVENT, vcpu); 5018 } 5019 } 5020 5021 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 5022 { 5023 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5024 if (ctxt->exception.vector == PF_VECTOR) 5025 return kvm_propagate_fault(vcpu, &ctxt->exception); 5026 5027 if (ctxt->exception.error_code_valid) 5028 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 5029 ctxt->exception.error_code); 5030 else 5031 kvm_queue_exception(vcpu, ctxt->exception.vector); 5032 return false; 5033 } 5034 5035 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 5036 { 5037 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5038 int cs_db, cs_l; 5039 5040 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 5041 5042 ctxt->eflags = kvm_get_rflags(vcpu); 5043 ctxt->eip = kvm_rip_read(vcpu); 5044 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 5045 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 5046 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 5047 cs_db ? X86EMUL_MODE_PROT32 : 5048 X86EMUL_MODE_PROT16; 5049 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 5050 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 5051 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 5052 ctxt->emul_flags = vcpu->arch.hflags; 5053 5054 init_decode_cache(ctxt); 5055 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5056 } 5057 5058 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 5059 { 5060 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5061 int ret; 5062 5063 init_emulate_ctxt(vcpu); 5064 5065 ctxt->op_bytes = 2; 5066 ctxt->ad_bytes = 2; 5067 ctxt->_eip = ctxt->eip + inc_eip; 5068 ret = emulate_int_real(ctxt, irq); 5069 5070 if (ret != X86EMUL_CONTINUE) 5071 return EMULATE_FAIL; 5072 5073 ctxt->eip = ctxt->_eip; 5074 kvm_rip_write(vcpu, ctxt->eip); 5075 kvm_set_rflags(vcpu, ctxt->eflags); 5076 5077 if (irq == NMI_VECTOR) 5078 vcpu->arch.nmi_pending = 0; 5079 else 5080 vcpu->arch.interrupt.pending = false; 5081 5082 return EMULATE_DONE; 5083 } 5084 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 5085 5086 static int handle_emulation_failure(struct kvm_vcpu *vcpu) 5087 { 5088 int r = EMULATE_DONE; 5089 5090 ++vcpu->stat.insn_emulation_fail; 5091 trace_kvm_emulate_insn_failed(vcpu); 5092 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 5093 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5094 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 5095 vcpu->run->internal.ndata = 0; 5096 r = EMULATE_FAIL; 5097 } 5098 kvm_queue_exception(vcpu, UD_VECTOR); 5099 5100 return r; 5101 } 5102 5103 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 5104 bool write_fault_to_shadow_pgtable, 5105 int emulation_type) 5106 { 5107 gpa_t gpa = cr2; 5108 pfn_t pfn; 5109 5110 if (emulation_type & EMULTYPE_NO_REEXECUTE) 5111 return false; 5112 5113 if (!vcpu->arch.mmu.direct_map) { 5114 /* 5115 * Write permission should be allowed since only 5116 * write access need to be emulated. 5117 */ 5118 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5119 5120 /* 5121 * If the mapping is invalid in guest, let cpu retry 5122 * it to generate fault. 5123 */ 5124 if (gpa == UNMAPPED_GVA) 5125 return true; 5126 } 5127 5128 /* 5129 * Do not retry the unhandleable instruction if it faults on the 5130 * readonly host memory, otherwise it will goto a infinite loop: 5131 * retry instruction -> write #PF -> emulation fail -> retry 5132 * instruction -> ... 5133 */ 5134 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 5135 5136 /* 5137 * If the instruction failed on the error pfn, it can not be fixed, 5138 * report the error to userspace. 5139 */ 5140 if (is_error_noslot_pfn(pfn)) 5141 return false; 5142 5143 kvm_release_pfn_clean(pfn); 5144 5145 /* The instructions are well-emulated on direct mmu. */ 5146 if (vcpu->arch.mmu.direct_map) { 5147 unsigned int indirect_shadow_pages; 5148 5149 spin_lock(&vcpu->kvm->mmu_lock); 5150 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 5151 spin_unlock(&vcpu->kvm->mmu_lock); 5152 5153 if (indirect_shadow_pages) 5154 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5155 5156 return true; 5157 } 5158 5159 /* 5160 * if emulation was due to access to shadowed page table 5161 * and it failed try to unshadow page and re-enter the 5162 * guest to let CPU execute the instruction. 5163 */ 5164 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5165 5166 /* 5167 * If the access faults on its page table, it can not 5168 * be fixed by unprotecting shadow page and it should 5169 * be reported to userspace. 5170 */ 5171 return !write_fault_to_shadow_pgtable; 5172 } 5173 5174 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5175 unsigned long cr2, int emulation_type) 5176 { 5177 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5178 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5179 5180 last_retry_eip = vcpu->arch.last_retry_eip; 5181 last_retry_addr = vcpu->arch.last_retry_addr; 5182 5183 /* 5184 * If the emulation is caused by #PF and it is non-page_table 5185 * writing instruction, it means the VM-EXIT is caused by shadow 5186 * page protected, we can zap the shadow page and retry this 5187 * instruction directly. 5188 * 5189 * Note: if the guest uses a non-page-table modifying instruction 5190 * on the PDE that points to the instruction, then we will unmap 5191 * the instruction and go to an infinite loop. So, we cache the 5192 * last retried eip and the last fault address, if we meet the eip 5193 * and the address again, we can break out of the potential infinite 5194 * loop. 5195 */ 5196 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5197 5198 if (!(emulation_type & EMULTYPE_RETRY)) 5199 return false; 5200 5201 if (x86_page_table_writing_insn(ctxt)) 5202 return false; 5203 5204 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5205 return false; 5206 5207 vcpu->arch.last_retry_eip = ctxt->eip; 5208 vcpu->arch.last_retry_addr = cr2; 5209 5210 if (!vcpu->arch.mmu.direct_map) 5211 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5212 5213 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5214 5215 return true; 5216 } 5217 5218 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5219 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5220 5221 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 5222 { 5223 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 5224 /* This is a good place to trace that we are exiting SMM. */ 5225 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 5226 5227 if (unlikely(vcpu->arch.smi_pending)) { 5228 kvm_make_request(KVM_REQ_SMI, vcpu); 5229 vcpu->arch.smi_pending = 0; 5230 } else { 5231 /* Process a latched INIT, if any. */ 5232 kvm_make_request(KVM_REQ_EVENT, vcpu); 5233 } 5234 } 5235 5236 kvm_mmu_reset_context(vcpu); 5237 } 5238 5239 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) 5240 { 5241 unsigned changed = vcpu->arch.hflags ^ emul_flags; 5242 5243 vcpu->arch.hflags = emul_flags; 5244 5245 if (changed & HF_SMM_MASK) 5246 kvm_smm_changed(vcpu); 5247 } 5248 5249 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5250 unsigned long *db) 5251 { 5252 u32 dr6 = 0; 5253 int i; 5254 u32 enable, rwlen; 5255 5256 enable = dr7; 5257 rwlen = dr7 >> 16; 5258 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5259 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5260 dr6 |= (1 << i); 5261 return dr6; 5262 } 5263 5264 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) 5265 { 5266 struct kvm_run *kvm_run = vcpu->run; 5267 5268 /* 5269 * rflags is the old, "raw" value of the flags. The new value has 5270 * not been saved yet. 5271 * 5272 * This is correct even for TF set by the guest, because "the 5273 * processor will not generate this exception after the instruction 5274 * that sets the TF flag". 5275 */ 5276 if (unlikely(rflags & X86_EFLAGS_TF)) { 5277 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5278 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | 5279 DR6_RTM; 5280 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5281 kvm_run->debug.arch.exception = DB_VECTOR; 5282 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5283 *r = EMULATE_USER_EXIT; 5284 } else { 5285 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; 5286 /* 5287 * "Certain debug exceptions may clear bit 0-3. The 5288 * remaining contents of the DR6 register are never 5289 * cleared by the processor". 5290 */ 5291 vcpu->arch.dr6 &= ~15; 5292 vcpu->arch.dr6 |= DR6_BS | DR6_RTM; 5293 kvm_queue_exception(vcpu, DB_VECTOR); 5294 } 5295 } 5296 } 5297 5298 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5299 { 5300 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5301 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5302 struct kvm_run *kvm_run = vcpu->run; 5303 unsigned long eip = kvm_get_linear_rip(vcpu); 5304 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5305 vcpu->arch.guest_debug_dr7, 5306 vcpu->arch.eff_db); 5307 5308 if (dr6 != 0) { 5309 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 5310 kvm_run->debug.arch.pc = eip; 5311 kvm_run->debug.arch.exception = DB_VECTOR; 5312 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5313 *r = EMULATE_USER_EXIT; 5314 return true; 5315 } 5316 } 5317 5318 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 5319 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 5320 unsigned long eip = kvm_get_linear_rip(vcpu); 5321 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5322 vcpu->arch.dr7, 5323 vcpu->arch.db); 5324 5325 if (dr6 != 0) { 5326 vcpu->arch.dr6 &= ~15; 5327 vcpu->arch.dr6 |= dr6 | DR6_RTM; 5328 kvm_queue_exception(vcpu, DB_VECTOR); 5329 *r = EMULATE_DONE; 5330 return true; 5331 } 5332 } 5333 5334 return false; 5335 } 5336 5337 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 5338 unsigned long cr2, 5339 int emulation_type, 5340 void *insn, 5341 int insn_len) 5342 { 5343 int r; 5344 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5345 bool writeback = true; 5346 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 5347 5348 /* 5349 * Clear write_fault_to_shadow_pgtable here to ensure it is 5350 * never reused. 5351 */ 5352 vcpu->arch.write_fault_to_shadow_pgtable = false; 5353 kvm_clear_exception_queue(vcpu); 5354 5355 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 5356 init_emulate_ctxt(vcpu); 5357 5358 /* 5359 * We will reenter on the same instruction since 5360 * we do not set complete_userspace_io. This does not 5361 * handle watchpoints yet, those would be handled in 5362 * the emulate_ops. 5363 */ 5364 if (kvm_vcpu_check_breakpoint(vcpu, &r)) 5365 return r; 5366 5367 ctxt->interruptibility = 0; 5368 ctxt->have_exception = false; 5369 ctxt->exception.vector = -1; 5370 ctxt->perm_ok = false; 5371 5372 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 5373 5374 r = x86_decode_insn(ctxt, insn, insn_len); 5375 5376 trace_kvm_emulate_insn_start(vcpu); 5377 ++vcpu->stat.insn_emulation; 5378 if (r != EMULATION_OK) { 5379 if (emulation_type & EMULTYPE_TRAP_UD) 5380 return EMULATE_FAIL; 5381 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5382 emulation_type)) 5383 return EMULATE_DONE; 5384 if (emulation_type & EMULTYPE_SKIP) 5385 return EMULATE_FAIL; 5386 return handle_emulation_failure(vcpu); 5387 } 5388 } 5389 5390 if (emulation_type & EMULTYPE_SKIP) { 5391 kvm_rip_write(vcpu, ctxt->_eip); 5392 if (ctxt->eflags & X86_EFLAGS_RF) 5393 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 5394 return EMULATE_DONE; 5395 } 5396 5397 if (retry_instruction(ctxt, cr2, emulation_type)) 5398 return EMULATE_DONE; 5399 5400 /* this is needed for vmware backdoor interface to work since it 5401 changes registers values during IO operation */ 5402 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 5403 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5404 emulator_invalidate_register_cache(ctxt); 5405 } 5406 5407 restart: 5408 r = x86_emulate_insn(ctxt); 5409 5410 if (r == EMULATION_INTERCEPTED) 5411 return EMULATE_DONE; 5412 5413 if (r == EMULATION_FAILED) { 5414 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5415 emulation_type)) 5416 return EMULATE_DONE; 5417 5418 return handle_emulation_failure(vcpu); 5419 } 5420 5421 if (ctxt->have_exception) { 5422 r = EMULATE_DONE; 5423 if (inject_emulated_exception(vcpu)) 5424 return r; 5425 } else if (vcpu->arch.pio.count) { 5426 if (!vcpu->arch.pio.in) { 5427 /* FIXME: return into emulator if single-stepping. */ 5428 vcpu->arch.pio.count = 0; 5429 } else { 5430 writeback = false; 5431 vcpu->arch.complete_userspace_io = complete_emulated_pio; 5432 } 5433 r = EMULATE_USER_EXIT; 5434 } else if (vcpu->mmio_needed) { 5435 if (!vcpu->mmio_is_write) 5436 writeback = false; 5437 r = EMULATE_USER_EXIT; 5438 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 5439 } else if (r == EMULATION_RESTART) 5440 goto restart; 5441 else 5442 r = EMULATE_DONE; 5443 5444 if (writeback) { 5445 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5446 toggle_interruptibility(vcpu, ctxt->interruptibility); 5447 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 5448 if (vcpu->arch.hflags != ctxt->emul_flags) 5449 kvm_set_hflags(vcpu, ctxt->emul_flags); 5450 kvm_rip_write(vcpu, ctxt->eip); 5451 if (r == EMULATE_DONE) 5452 kvm_vcpu_check_singlestep(vcpu, rflags, &r); 5453 if (!ctxt->have_exception || 5454 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 5455 __kvm_set_rflags(vcpu, ctxt->eflags); 5456 5457 /* 5458 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 5459 * do nothing, and it will be requested again as soon as 5460 * the shadow expires. But we still need to check here, 5461 * because POPF has no interrupt shadow. 5462 */ 5463 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 5464 kvm_make_request(KVM_REQ_EVENT, vcpu); 5465 } else 5466 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 5467 5468 return r; 5469 } 5470 EXPORT_SYMBOL_GPL(x86_emulate_instruction); 5471 5472 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) 5473 { 5474 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 5475 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 5476 size, port, &val, 1); 5477 /* do not return to emulator after return from userspace */ 5478 vcpu->arch.pio.count = 0; 5479 return ret; 5480 } 5481 EXPORT_SYMBOL_GPL(kvm_fast_pio_out); 5482 5483 static void tsc_bad(void *info) 5484 { 5485 __this_cpu_write(cpu_tsc_khz, 0); 5486 } 5487 5488 static void tsc_khz_changed(void *data) 5489 { 5490 struct cpufreq_freqs *freq = data; 5491 unsigned long khz = 0; 5492 5493 if (data) 5494 khz = freq->new; 5495 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5496 khz = cpufreq_quick_get(raw_smp_processor_id()); 5497 if (!khz) 5498 khz = tsc_khz; 5499 __this_cpu_write(cpu_tsc_khz, khz); 5500 } 5501 5502 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 5503 void *data) 5504 { 5505 struct cpufreq_freqs *freq = data; 5506 struct kvm *kvm; 5507 struct kvm_vcpu *vcpu; 5508 int i, send_ipi = 0; 5509 5510 /* 5511 * We allow guests to temporarily run on slowing clocks, 5512 * provided we notify them after, or to run on accelerating 5513 * clocks, provided we notify them before. Thus time never 5514 * goes backwards. 5515 * 5516 * However, we have a problem. We can't atomically update 5517 * the frequency of a given CPU from this function; it is 5518 * merely a notifier, which can be called from any CPU. 5519 * Changing the TSC frequency at arbitrary points in time 5520 * requires a recomputation of local variables related to 5521 * the TSC for each VCPU. We must flag these local variables 5522 * to be updated and be sure the update takes place with the 5523 * new frequency before any guests proceed. 5524 * 5525 * Unfortunately, the combination of hotplug CPU and frequency 5526 * change creates an intractable locking scenario; the order 5527 * of when these callouts happen is undefined with respect to 5528 * CPU hotplug, and they can race with each other. As such, 5529 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 5530 * undefined; you can actually have a CPU frequency change take 5531 * place in between the computation of X and the setting of the 5532 * variable. To protect against this problem, all updates of 5533 * the per_cpu tsc_khz variable are done in an interrupt 5534 * protected IPI, and all callers wishing to update the value 5535 * must wait for a synchronous IPI to complete (which is trivial 5536 * if the caller is on the CPU already). This establishes the 5537 * necessary total order on variable updates. 5538 * 5539 * Note that because a guest time update may take place 5540 * anytime after the setting of the VCPU's request bit, the 5541 * correct TSC value must be set before the request. However, 5542 * to ensure the update actually makes it to any guest which 5543 * starts running in hardware virtualization between the set 5544 * and the acquisition of the spinlock, we must also ping the 5545 * CPU after setting the request bit. 5546 * 5547 */ 5548 5549 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 5550 return 0; 5551 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 5552 return 0; 5553 5554 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5555 5556 spin_lock(&kvm_lock); 5557 list_for_each_entry(kvm, &vm_list, vm_list) { 5558 kvm_for_each_vcpu(i, vcpu, kvm) { 5559 if (vcpu->cpu != freq->cpu) 5560 continue; 5561 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5562 if (vcpu->cpu != smp_processor_id()) 5563 send_ipi = 1; 5564 } 5565 } 5566 spin_unlock(&kvm_lock); 5567 5568 if (freq->old < freq->new && send_ipi) { 5569 /* 5570 * We upscale the frequency. Must make the guest 5571 * doesn't see old kvmclock values while running with 5572 * the new frequency, otherwise we risk the guest sees 5573 * time go backwards. 5574 * 5575 * In case we update the frequency for another cpu 5576 * (which might be in guest context) send an interrupt 5577 * to kick the cpu out of guest context. Next time 5578 * guest context is entered kvmclock will be updated, 5579 * so the guest will not see stale values. 5580 */ 5581 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5582 } 5583 return 0; 5584 } 5585 5586 static struct notifier_block kvmclock_cpufreq_notifier_block = { 5587 .notifier_call = kvmclock_cpufreq_notifier 5588 }; 5589 5590 static int kvmclock_cpu_notifier(struct notifier_block *nfb, 5591 unsigned long action, void *hcpu) 5592 { 5593 unsigned int cpu = (unsigned long)hcpu; 5594 5595 switch (action) { 5596 case CPU_ONLINE: 5597 case CPU_DOWN_FAILED: 5598 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5599 break; 5600 case CPU_DOWN_PREPARE: 5601 smp_call_function_single(cpu, tsc_bad, NULL, 1); 5602 break; 5603 } 5604 return NOTIFY_OK; 5605 } 5606 5607 static struct notifier_block kvmclock_cpu_notifier_block = { 5608 .notifier_call = kvmclock_cpu_notifier, 5609 .priority = -INT_MAX 5610 }; 5611 5612 static void kvm_timer_init(void) 5613 { 5614 int cpu; 5615 5616 max_tsc_khz = tsc_khz; 5617 5618 cpu_notifier_register_begin(); 5619 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 5620 #ifdef CONFIG_CPU_FREQ 5621 struct cpufreq_policy policy; 5622 memset(&policy, 0, sizeof(policy)); 5623 cpu = get_cpu(); 5624 cpufreq_get_policy(&policy, cpu); 5625 if (policy.cpuinfo.max_freq) 5626 max_tsc_khz = policy.cpuinfo.max_freq; 5627 put_cpu(); 5628 #endif 5629 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 5630 CPUFREQ_TRANSITION_NOTIFIER); 5631 } 5632 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 5633 for_each_online_cpu(cpu) 5634 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5635 5636 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5637 cpu_notifier_register_done(); 5638 5639 } 5640 5641 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 5642 5643 int kvm_is_in_guest(void) 5644 { 5645 return __this_cpu_read(current_vcpu) != NULL; 5646 } 5647 5648 static int kvm_is_user_mode(void) 5649 { 5650 int user_mode = 3; 5651 5652 if (__this_cpu_read(current_vcpu)) 5653 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 5654 5655 return user_mode != 0; 5656 } 5657 5658 static unsigned long kvm_get_guest_ip(void) 5659 { 5660 unsigned long ip = 0; 5661 5662 if (__this_cpu_read(current_vcpu)) 5663 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 5664 5665 return ip; 5666 } 5667 5668 static struct perf_guest_info_callbacks kvm_guest_cbs = { 5669 .is_in_guest = kvm_is_in_guest, 5670 .is_user_mode = kvm_is_user_mode, 5671 .get_guest_ip = kvm_get_guest_ip, 5672 }; 5673 5674 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) 5675 { 5676 __this_cpu_write(current_vcpu, vcpu); 5677 } 5678 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); 5679 5680 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) 5681 { 5682 __this_cpu_write(current_vcpu, NULL); 5683 } 5684 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); 5685 5686 static void kvm_set_mmio_spte_mask(void) 5687 { 5688 u64 mask; 5689 int maxphyaddr = boot_cpu_data.x86_phys_bits; 5690 5691 /* 5692 * Set the reserved bits and the present bit of an paging-structure 5693 * entry to generate page fault with PFER.RSV = 1. 5694 */ 5695 /* Mask the reserved physical address bits. */ 5696 mask = rsvd_bits(maxphyaddr, 51); 5697 5698 /* Bit 62 is always reserved for 32bit host. */ 5699 mask |= 0x3ull << 62; 5700 5701 /* Set the present bit. */ 5702 mask |= 1ull; 5703 5704 #ifdef CONFIG_X86_64 5705 /* 5706 * If reserved bit is not supported, clear the present bit to disable 5707 * mmio page fault. 5708 */ 5709 if (maxphyaddr == 52) 5710 mask &= ~1ull; 5711 #endif 5712 5713 kvm_mmu_set_mmio_spte_mask(mask); 5714 } 5715 5716 #ifdef CONFIG_X86_64 5717 static void pvclock_gtod_update_fn(struct work_struct *work) 5718 { 5719 struct kvm *kvm; 5720 5721 struct kvm_vcpu *vcpu; 5722 int i; 5723 5724 spin_lock(&kvm_lock); 5725 list_for_each_entry(kvm, &vm_list, vm_list) 5726 kvm_for_each_vcpu(i, vcpu, kvm) 5727 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 5728 atomic_set(&kvm_guest_has_master_clock, 0); 5729 spin_unlock(&kvm_lock); 5730 } 5731 5732 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 5733 5734 /* 5735 * Notification about pvclock gtod data update. 5736 */ 5737 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 5738 void *priv) 5739 { 5740 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 5741 struct timekeeper *tk = priv; 5742 5743 update_pvclock_gtod(tk); 5744 5745 /* disable master clock if host does not trust, or does not 5746 * use, TSC clocksource 5747 */ 5748 if (gtod->clock.vclock_mode != VCLOCK_TSC && 5749 atomic_read(&kvm_guest_has_master_clock) != 0) 5750 queue_work(system_long_wq, &pvclock_gtod_work); 5751 5752 return 0; 5753 } 5754 5755 static struct notifier_block pvclock_gtod_notifier = { 5756 .notifier_call = pvclock_gtod_notify, 5757 }; 5758 #endif 5759 5760 int kvm_arch_init(void *opaque) 5761 { 5762 int r; 5763 struct kvm_x86_ops *ops = opaque; 5764 5765 if (kvm_x86_ops) { 5766 printk(KERN_ERR "kvm: already loaded the other module\n"); 5767 r = -EEXIST; 5768 goto out; 5769 } 5770 5771 if (!ops->cpu_has_kvm_support()) { 5772 printk(KERN_ERR "kvm: no hardware support\n"); 5773 r = -EOPNOTSUPP; 5774 goto out; 5775 } 5776 if (ops->disabled_by_bios()) { 5777 printk(KERN_ERR "kvm: disabled by bios\n"); 5778 r = -EOPNOTSUPP; 5779 goto out; 5780 } 5781 5782 r = -ENOMEM; 5783 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 5784 if (!shared_msrs) { 5785 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 5786 goto out; 5787 } 5788 5789 r = kvm_mmu_module_init(); 5790 if (r) 5791 goto out_free_percpu; 5792 5793 kvm_set_mmio_spte_mask(); 5794 5795 kvm_x86_ops = ops; 5796 5797 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 5798 PT_DIRTY_MASK, PT64_NX_MASK, 0); 5799 5800 kvm_timer_init(); 5801 5802 perf_register_guest_info_callbacks(&kvm_guest_cbs); 5803 5804 if (cpu_has_xsave) 5805 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 5806 5807 kvm_lapic_init(); 5808 #ifdef CONFIG_X86_64 5809 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 5810 #endif 5811 5812 return 0; 5813 5814 out_free_percpu: 5815 free_percpu(shared_msrs); 5816 out: 5817 return r; 5818 } 5819 5820 void kvm_arch_exit(void) 5821 { 5822 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 5823 5824 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5825 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 5826 CPUFREQ_TRANSITION_NOTIFIER); 5827 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5828 #ifdef CONFIG_X86_64 5829 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 5830 #endif 5831 kvm_x86_ops = NULL; 5832 kvm_mmu_module_exit(); 5833 free_percpu(shared_msrs); 5834 } 5835 5836 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 5837 { 5838 ++vcpu->stat.halt_exits; 5839 if (lapic_in_kernel(vcpu)) { 5840 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 5841 return 1; 5842 } else { 5843 vcpu->run->exit_reason = KVM_EXIT_HLT; 5844 return 0; 5845 } 5846 } 5847 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 5848 5849 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 5850 { 5851 kvm_x86_ops->skip_emulated_instruction(vcpu); 5852 return kvm_vcpu_halt(vcpu); 5853 } 5854 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 5855 5856 /* 5857 * kvm_pv_kick_cpu_op: Kick a vcpu. 5858 * 5859 * @apicid - apicid of vcpu to be kicked. 5860 */ 5861 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 5862 { 5863 struct kvm_lapic_irq lapic_irq; 5864 5865 lapic_irq.shorthand = 0; 5866 lapic_irq.dest_mode = 0; 5867 lapic_irq.dest_id = apicid; 5868 lapic_irq.msi_redir_hint = false; 5869 5870 lapic_irq.delivery_mode = APIC_DM_REMRD; 5871 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 5872 } 5873 5874 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 5875 { 5876 unsigned long nr, a0, a1, a2, a3, ret; 5877 int op_64_bit, r = 1; 5878 5879 kvm_x86_ops->skip_emulated_instruction(vcpu); 5880 5881 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 5882 return kvm_hv_hypercall(vcpu); 5883 5884 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 5885 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 5886 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 5887 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 5888 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 5889 5890 trace_kvm_hypercall(nr, a0, a1, a2, a3); 5891 5892 op_64_bit = is_64_bit_mode(vcpu); 5893 if (!op_64_bit) { 5894 nr &= 0xFFFFFFFF; 5895 a0 &= 0xFFFFFFFF; 5896 a1 &= 0xFFFFFFFF; 5897 a2 &= 0xFFFFFFFF; 5898 a3 &= 0xFFFFFFFF; 5899 } 5900 5901 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 5902 ret = -KVM_EPERM; 5903 goto out; 5904 } 5905 5906 switch (nr) { 5907 case KVM_HC_VAPIC_POLL_IRQ: 5908 ret = 0; 5909 break; 5910 case KVM_HC_KICK_CPU: 5911 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 5912 ret = 0; 5913 break; 5914 default: 5915 ret = -KVM_ENOSYS; 5916 break; 5917 } 5918 out: 5919 if (!op_64_bit) 5920 ret = (u32)ret; 5921 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 5922 ++vcpu->stat.hypercalls; 5923 return r; 5924 } 5925 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 5926 5927 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 5928 { 5929 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5930 char instruction[3]; 5931 unsigned long rip = kvm_rip_read(vcpu); 5932 5933 kvm_x86_ops->patch_hypercall(vcpu, instruction); 5934 5935 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); 5936 } 5937 5938 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 5939 { 5940 return vcpu->run->request_interrupt_window && 5941 likely(!pic_in_kernel(vcpu->kvm)); 5942 } 5943 5944 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 5945 { 5946 struct kvm_run *kvm_run = vcpu->run; 5947 5948 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 5949 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 5950 kvm_run->cr8 = kvm_get_cr8(vcpu); 5951 kvm_run->apic_base = kvm_get_apic_base(vcpu); 5952 kvm_run->ready_for_interrupt_injection = 5953 pic_in_kernel(vcpu->kvm) || 5954 kvm_vcpu_ready_for_interrupt_injection(vcpu); 5955 } 5956 5957 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 5958 { 5959 int max_irr, tpr; 5960 5961 if (!kvm_x86_ops->update_cr8_intercept) 5962 return; 5963 5964 if (!vcpu->arch.apic) 5965 return; 5966 5967 if (!vcpu->arch.apic->vapic_addr) 5968 max_irr = kvm_lapic_find_highest_irr(vcpu); 5969 else 5970 max_irr = -1; 5971 5972 if (max_irr != -1) 5973 max_irr >>= 4; 5974 5975 tpr = kvm_lapic_get_cr8(vcpu); 5976 5977 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 5978 } 5979 5980 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 5981 { 5982 int r; 5983 5984 /* try to reinject previous events if any */ 5985 if (vcpu->arch.exception.pending) { 5986 trace_kvm_inj_exception(vcpu->arch.exception.nr, 5987 vcpu->arch.exception.has_error_code, 5988 vcpu->arch.exception.error_code); 5989 5990 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 5991 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 5992 X86_EFLAGS_RF); 5993 5994 if (vcpu->arch.exception.nr == DB_VECTOR && 5995 (vcpu->arch.dr7 & DR7_GD)) { 5996 vcpu->arch.dr7 &= ~DR7_GD; 5997 kvm_update_dr7(vcpu); 5998 } 5999 6000 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, 6001 vcpu->arch.exception.has_error_code, 6002 vcpu->arch.exception.error_code, 6003 vcpu->arch.exception.reinject); 6004 return 0; 6005 } 6006 6007 if (vcpu->arch.nmi_injected) { 6008 kvm_x86_ops->set_nmi(vcpu); 6009 return 0; 6010 } 6011 6012 if (vcpu->arch.interrupt.pending) { 6013 kvm_x86_ops->set_irq(vcpu); 6014 return 0; 6015 } 6016 6017 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6018 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6019 if (r != 0) 6020 return r; 6021 } 6022 6023 /* try to inject new event if pending */ 6024 if (vcpu->arch.nmi_pending) { 6025 if (kvm_x86_ops->nmi_allowed(vcpu)) { 6026 --vcpu->arch.nmi_pending; 6027 vcpu->arch.nmi_injected = true; 6028 kvm_x86_ops->set_nmi(vcpu); 6029 } 6030 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 6031 /* 6032 * Because interrupts can be injected asynchronously, we are 6033 * calling check_nested_events again here to avoid a race condition. 6034 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 6035 * proposal and current concerns. Perhaps we should be setting 6036 * KVM_REQ_EVENT only on certain events and not unconditionally? 6037 */ 6038 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6039 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6040 if (r != 0) 6041 return r; 6042 } 6043 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 6044 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 6045 false); 6046 kvm_x86_ops->set_irq(vcpu); 6047 } 6048 } 6049 return 0; 6050 } 6051 6052 static void process_nmi(struct kvm_vcpu *vcpu) 6053 { 6054 unsigned limit = 2; 6055 6056 /* 6057 * x86 is limited to one NMI running, and one NMI pending after it. 6058 * If an NMI is already in progress, limit further NMIs to just one. 6059 * Otherwise, allow two (and we'll inject the first one immediately). 6060 */ 6061 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 6062 limit = 1; 6063 6064 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 6065 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 6066 kvm_make_request(KVM_REQ_EVENT, vcpu); 6067 } 6068 6069 #define put_smstate(type, buf, offset, val) \ 6070 *(type *)((buf) + (offset) - 0x7e00) = val 6071 6072 static u32 process_smi_get_segment_flags(struct kvm_segment *seg) 6073 { 6074 u32 flags = 0; 6075 flags |= seg->g << 23; 6076 flags |= seg->db << 22; 6077 flags |= seg->l << 21; 6078 flags |= seg->avl << 20; 6079 flags |= seg->present << 15; 6080 flags |= seg->dpl << 13; 6081 flags |= seg->s << 12; 6082 flags |= seg->type << 8; 6083 return flags; 6084 } 6085 6086 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 6087 { 6088 struct kvm_segment seg; 6089 int offset; 6090 6091 kvm_get_segment(vcpu, &seg, n); 6092 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 6093 6094 if (n < 3) 6095 offset = 0x7f84 + n * 12; 6096 else 6097 offset = 0x7f2c + (n - 3) * 12; 6098 6099 put_smstate(u32, buf, offset + 8, seg.base); 6100 put_smstate(u32, buf, offset + 4, seg.limit); 6101 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg)); 6102 } 6103 6104 #ifdef CONFIG_X86_64 6105 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 6106 { 6107 struct kvm_segment seg; 6108 int offset; 6109 u16 flags; 6110 6111 kvm_get_segment(vcpu, &seg, n); 6112 offset = 0x7e00 + n * 16; 6113 6114 flags = process_smi_get_segment_flags(&seg) >> 8; 6115 put_smstate(u16, buf, offset, seg.selector); 6116 put_smstate(u16, buf, offset + 2, flags); 6117 put_smstate(u32, buf, offset + 4, seg.limit); 6118 put_smstate(u64, buf, offset + 8, seg.base); 6119 } 6120 #endif 6121 6122 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf) 6123 { 6124 struct desc_ptr dt; 6125 struct kvm_segment seg; 6126 unsigned long val; 6127 int i; 6128 6129 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 6130 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 6131 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 6132 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 6133 6134 for (i = 0; i < 8; i++) 6135 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 6136 6137 kvm_get_dr(vcpu, 6, &val); 6138 put_smstate(u32, buf, 0x7fcc, (u32)val); 6139 kvm_get_dr(vcpu, 7, &val); 6140 put_smstate(u32, buf, 0x7fc8, (u32)val); 6141 6142 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6143 put_smstate(u32, buf, 0x7fc4, seg.selector); 6144 put_smstate(u32, buf, 0x7f64, seg.base); 6145 put_smstate(u32, buf, 0x7f60, seg.limit); 6146 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg)); 6147 6148 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6149 put_smstate(u32, buf, 0x7fc0, seg.selector); 6150 put_smstate(u32, buf, 0x7f80, seg.base); 6151 put_smstate(u32, buf, 0x7f7c, seg.limit); 6152 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg)); 6153 6154 kvm_x86_ops->get_gdt(vcpu, &dt); 6155 put_smstate(u32, buf, 0x7f74, dt.address); 6156 put_smstate(u32, buf, 0x7f70, dt.size); 6157 6158 kvm_x86_ops->get_idt(vcpu, &dt); 6159 put_smstate(u32, buf, 0x7f58, dt.address); 6160 put_smstate(u32, buf, 0x7f54, dt.size); 6161 6162 for (i = 0; i < 6; i++) 6163 process_smi_save_seg_32(vcpu, buf, i); 6164 6165 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 6166 6167 /* revision id */ 6168 put_smstate(u32, buf, 0x7efc, 0x00020000); 6169 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 6170 } 6171 6172 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf) 6173 { 6174 #ifdef CONFIG_X86_64 6175 struct desc_ptr dt; 6176 struct kvm_segment seg; 6177 unsigned long val; 6178 int i; 6179 6180 for (i = 0; i < 16; i++) 6181 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 6182 6183 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 6184 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 6185 6186 kvm_get_dr(vcpu, 6, &val); 6187 put_smstate(u64, buf, 0x7f68, val); 6188 kvm_get_dr(vcpu, 7, &val); 6189 put_smstate(u64, buf, 0x7f60, val); 6190 6191 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 6192 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 6193 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 6194 6195 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 6196 6197 /* revision id */ 6198 put_smstate(u32, buf, 0x7efc, 0x00020064); 6199 6200 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 6201 6202 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6203 put_smstate(u16, buf, 0x7e90, seg.selector); 6204 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8); 6205 put_smstate(u32, buf, 0x7e94, seg.limit); 6206 put_smstate(u64, buf, 0x7e98, seg.base); 6207 6208 kvm_x86_ops->get_idt(vcpu, &dt); 6209 put_smstate(u32, buf, 0x7e84, dt.size); 6210 put_smstate(u64, buf, 0x7e88, dt.address); 6211 6212 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6213 put_smstate(u16, buf, 0x7e70, seg.selector); 6214 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8); 6215 put_smstate(u32, buf, 0x7e74, seg.limit); 6216 put_smstate(u64, buf, 0x7e78, seg.base); 6217 6218 kvm_x86_ops->get_gdt(vcpu, &dt); 6219 put_smstate(u32, buf, 0x7e64, dt.size); 6220 put_smstate(u64, buf, 0x7e68, dt.address); 6221 6222 for (i = 0; i < 6; i++) 6223 process_smi_save_seg_64(vcpu, buf, i); 6224 #else 6225 WARN_ON_ONCE(1); 6226 #endif 6227 } 6228 6229 static void process_smi(struct kvm_vcpu *vcpu) 6230 { 6231 struct kvm_segment cs, ds; 6232 struct desc_ptr dt; 6233 char buf[512]; 6234 u32 cr0; 6235 6236 if (is_smm(vcpu)) { 6237 vcpu->arch.smi_pending = true; 6238 return; 6239 } 6240 6241 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 6242 vcpu->arch.hflags |= HF_SMM_MASK; 6243 memset(buf, 0, 512); 6244 if (guest_cpuid_has_longmode(vcpu)) 6245 process_smi_save_state_64(vcpu, buf); 6246 else 6247 process_smi_save_state_32(vcpu, buf); 6248 6249 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 6250 6251 if (kvm_x86_ops->get_nmi_mask(vcpu)) 6252 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 6253 else 6254 kvm_x86_ops->set_nmi_mask(vcpu, true); 6255 6256 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 6257 kvm_rip_write(vcpu, 0x8000); 6258 6259 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 6260 kvm_x86_ops->set_cr0(vcpu, cr0); 6261 vcpu->arch.cr0 = cr0; 6262 6263 kvm_x86_ops->set_cr4(vcpu, 0); 6264 6265 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 6266 dt.address = dt.size = 0; 6267 kvm_x86_ops->set_idt(vcpu, &dt); 6268 6269 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 6270 6271 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 6272 cs.base = vcpu->arch.smbase; 6273 6274 ds.selector = 0; 6275 ds.base = 0; 6276 6277 cs.limit = ds.limit = 0xffffffff; 6278 cs.type = ds.type = 0x3; 6279 cs.dpl = ds.dpl = 0; 6280 cs.db = ds.db = 0; 6281 cs.s = ds.s = 1; 6282 cs.l = ds.l = 0; 6283 cs.g = ds.g = 1; 6284 cs.avl = ds.avl = 0; 6285 cs.present = ds.present = 1; 6286 cs.unusable = ds.unusable = 0; 6287 cs.padding = ds.padding = 0; 6288 6289 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 6290 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 6291 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 6292 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 6293 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 6294 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 6295 6296 if (guest_cpuid_has_longmode(vcpu)) 6297 kvm_x86_ops->set_efer(vcpu, 0); 6298 6299 kvm_update_cpuid(vcpu); 6300 kvm_mmu_reset_context(vcpu); 6301 } 6302 6303 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 6304 { 6305 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 6306 return; 6307 6308 memset(vcpu->arch.eoi_exit_bitmap, 0, 256 / 8); 6309 6310 if (irqchip_split(vcpu->kvm)) 6311 kvm_scan_ioapic_routes(vcpu, vcpu->arch.eoi_exit_bitmap); 6312 else { 6313 kvm_x86_ops->sync_pir_to_irr(vcpu); 6314 kvm_ioapic_scan_entry(vcpu, vcpu->arch.eoi_exit_bitmap); 6315 } 6316 kvm_x86_ops->load_eoi_exitmap(vcpu); 6317 } 6318 6319 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) 6320 { 6321 ++vcpu->stat.tlb_flush; 6322 kvm_x86_ops->tlb_flush(vcpu); 6323 } 6324 6325 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 6326 { 6327 struct page *page = NULL; 6328 6329 if (!lapic_in_kernel(vcpu)) 6330 return; 6331 6332 if (!kvm_x86_ops->set_apic_access_page_addr) 6333 return; 6334 6335 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 6336 if (is_error_page(page)) 6337 return; 6338 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 6339 6340 /* 6341 * Do not pin apic access page in memory, the MMU notifier 6342 * will call us again if it is migrated or swapped out. 6343 */ 6344 put_page(page); 6345 } 6346 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 6347 6348 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, 6349 unsigned long address) 6350 { 6351 /* 6352 * The physical address of apic access page is stored in the VMCS. 6353 * Update it when it becomes invalid. 6354 */ 6355 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT)) 6356 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 6357 } 6358 6359 /* 6360 * Returns 1 to let vcpu_run() continue the guest execution loop without 6361 * exiting to the userspace. Otherwise, the value will be returned to the 6362 * userspace. 6363 */ 6364 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 6365 { 6366 int r; 6367 bool req_int_win = 6368 dm_request_for_irq_injection(vcpu) && 6369 kvm_cpu_accept_dm_intr(vcpu); 6370 6371 bool req_immediate_exit = false; 6372 6373 if (vcpu->requests) { 6374 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 6375 kvm_mmu_unload(vcpu); 6376 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 6377 __kvm_migrate_timers(vcpu); 6378 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 6379 kvm_gen_update_masterclock(vcpu->kvm); 6380 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 6381 kvm_gen_kvmclock_update(vcpu); 6382 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 6383 r = kvm_guest_time_update(vcpu); 6384 if (unlikely(r)) 6385 goto out; 6386 } 6387 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 6388 kvm_mmu_sync_roots(vcpu); 6389 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 6390 kvm_vcpu_flush_tlb(vcpu); 6391 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 6392 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 6393 r = 0; 6394 goto out; 6395 } 6396 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 6397 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 6398 r = 0; 6399 goto out; 6400 } 6401 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { 6402 vcpu->fpu_active = 0; 6403 kvm_x86_ops->fpu_deactivate(vcpu); 6404 } 6405 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 6406 /* Page is swapped out. Do synthetic halt */ 6407 vcpu->arch.apf.halted = true; 6408 r = 1; 6409 goto out; 6410 } 6411 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 6412 record_steal_time(vcpu); 6413 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 6414 process_smi(vcpu); 6415 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 6416 process_nmi(vcpu); 6417 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 6418 kvm_pmu_handle_event(vcpu); 6419 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 6420 kvm_pmu_deliver_pmi(vcpu); 6421 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 6422 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 6423 if (test_bit(vcpu->arch.pending_ioapic_eoi, 6424 (void *) vcpu->arch.eoi_exit_bitmap)) { 6425 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 6426 vcpu->run->eoi.vector = 6427 vcpu->arch.pending_ioapic_eoi; 6428 r = 0; 6429 goto out; 6430 } 6431 } 6432 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 6433 vcpu_scan_ioapic(vcpu); 6434 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 6435 kvm_vcpu_reload_apic_access_page(vcpu); 6436 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 6437 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 6438 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 6439 r = 0; 6440 goto out; 6441 } 6442 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 6443 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 6444 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 6445 r = 0; 6446 goto out; 6447 } 6448 } 6449 6450 /* 6451 * KVM_REQ_EVENT is not set when posted interrupts are set by 6452 * VT-d hardware, so we have to update RVI unconditionally. 6453 */ 6454 if (kvm_lapic_enabled(vcpu)) { 6455 /* 6456 * Update architecture specific hints for APIC 6457 * virtual interrupt delivery. 6458 */ 6459 if (kvm_x86_ops->hwapic_irr_update) 6460 kvm_x86_ops->hwapic_irr_update(vcpu, 6461 kvm_lapic_find_highest_irr(vcpu)); 6462 } 6463 6464 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 6465 kvm_apic_accept_events(vcpu); 6466 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 6467 r = 1; 6468 goto out; 6469 } 6470 6471 if (inject_pending_event(vcpu, req_int_win) != 0) 6472 req_immediate_exit = true; 6473 /* enable NMI/IRQ window open exits if needed */ 6474 else if (vcpu->arch.nmi_pending) 6475 kvm_x86_ops->enable_nmi_window(vcpu); 6476 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 6477 kvm_x86_ops->enable_irq_window(vcpu); 6478 6479 if (kvm_lapic_enabled(vcpu)) { 6480 update_cr8_intercept(vcpu); 6481 kvm_lapic_sync_to_vapic(vcpu); 6482 } 6483 } 6484 6485 r = kvm_mmu_reload(vcpu); 6486 if (unlikely(r)) { 6487 goto cancel_injection; 6488 } 6489 6490 preempt_disable(); 6491 6492 kvm_x86_ops->prepare_guest_switch(vcpu); 6493 if (vcpu->fpu_active) 6494 kvm_load_guest_fpu(vcpu); 6495 kvm_load_guest_xcr0(vcpu); 6496 6497 vcpu->mode = IN_GUEST_MODE; 6498 6499 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6500 6501 /* We should set ->mode before check ->requests, 6502 * see the comment in make_all_cpus_request. 6503 */ 6504 smp_mb__after_srcu_read_unlock(); 6505 6506 local_irq_disable(); 6507 6508 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests 6509 || need_resched() || signal_pending(current)) { 6510 vcpu->mode = OUTSIDE_GUEST_MODE; 6511 smp_wmb(); 6512 local_irq_enable(); 6513 preempt_enable(); 6514 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6515 r = 1; 6516 goto cancel_injection; 6517 } 6518 6519 if (req_immediate_exit) 6520 smp_send_reschedule(vcpu->cpu); 6521 6522 trace_kvm_entry(vcpu->vcpu_id); 6523 wait_lapic_expire(vcpu); 6524 __kvm_guest_enter(); 6525 6526 if (unlikely(vcpu->arch.switch_db_regs)) { 6527 set_debugreg(0, 7); 6528 set_debugreg(vcpu->arch.eff_db[0], 0); 6529 set_debugreg(vcpu->arch.eff_db[1], 1); 6530 set_debugreg(vcpu->arch.eff_db[2], 2); 6531 set_debugreg(vcpu->arch.eff_db[3], 3); 6532 set_debugreg(vcpu->arch.dr6, 6); 6533 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 6534 } 6535 6536 kvm_x86_ops->run(vcpu); 6537 6538 /* 6539 * Do this here before restoring debug registers on the host. And 6540 * since we do this before handling the vmexit, a DR access vmexit 6541 * can (a) read the correct value of the debug registers, (b) set 6542 * KVM_DEBUGREG_WONT_EXIT again. 6543 */ 6544 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 6545 int i; 6546 6547 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 6548 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 6549 for (i = 0; i < KVM_NR_DB_REGS; i++) 6550 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 6551 } 6552 6553 /* 6554 * If the guest has used debug registers, at least dr7 6555 * will be disabled while returning to the host. 6556 * If we don't have active breakpoints in the host, we don't 6557 * care about the messed up debug address registers. But if 6558 * we have some of them active, restore the old state. 6559 */ 6560 if (hw_breakpoint_active()) 6561 hw_breakpoint_restore(); 6562 6563 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 6564 6565 vcpu->mode = OUTSIDE_GUEST_MODE; 6566 smp_wmb(); 6567 6568 /* Interrupt is enabled by handle_external_intr() */ 6569 kvm_x86_ops->handle_external_intr(vcpu); 6570 6571 ++vcpu->stat.exits; 6572 6573 /* 6574 * We must have an instruction between local_irq_enable() and 6575 * kvm_guest_exit(), so the timer interrupt isn't delayed by 6576 * the interrupt shadow. The stat.exits increment will do nicely. 6577 * But we need to prevent reordering, hence this barrier(): 6578 */ 6579 barrier(); 6580 6581 kvm_guest_exit(); 6582 6583 preempt_enable(); 6584 6585 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6586 6587 /* 6588 * Profile KVM exit RIPs: 6589 */ 6590 if (unlikely(prof_on == KVM_PROFILING)) { 6591 unsigned long rip = kvm_rip_read(vcpu); 6592 profile_hit(KVM_PROFILING, (void *)rip); 6593 } 6594 6595 if (unlikely(vcpu->arch.tsc_always_catchup)) 6596 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6597 6598 if (vcpu->arch.apic_attention) 6599 kvm_lapic_sync_from_vapic(vcpu); 6600 6601 r = kvm_x86_ops->handle_exit(vcpu); 6602 return r; 6603 6604 cancel_injection: 6605 kvm_x86_ops->cancel_injection(vcpu); 6606 if (unlikely(vcpu->arch.apic_attention)) 6607 kvm_lapic_sync_from_vapic(vcpu); 6608 out: 6609 return r; 6610 } 6611 6612 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 6613 { 6614 if (!kvm_arch_vcpu_runnable(vcpu) && 6615 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { 6616 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6617 kvm_vcpu_block(vcpu); 6618 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6619 6620 if (kvm_x86_ops->post_block) 6621 kvm_x86_ops->post_block(vcpu); 6622 6623 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 6624 return 1; 6625 } 6626 6627 kvm_apic_accept_events(vcpu); 6628 switch(vcpu->arch.mp_state) { 6629 case KVM_MP_STATE_HALTED: 6630 vcpu->arch.pv.pv_unhalted = false; 6631 vcpu->arch.mp_state = 6632 KVM_MP_STATE_RUNNABLE; 6633 case KVM_MP_STATE_RUNNABLE: 6634 vcpu->arch.apf.halted = false; 6635 break; 6636 case KVM_MP_STATE_INIT_RECEIVED: 6637 break; 6638 default: 6639 return -EINTR; 6640 break; 6641 } 6642 return 1; 6643 } 6644 6645 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 6646 { 6647 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 6648 !vcpu->arch.apf.halted); 6649 } 6650 6651 static int vcpu_run(struct kvm_vcpu *vcpu) 6652 { 6653 int r; 6654 struct kvm *kvm = vcpu->kvm; 6655 6656 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6657 6658 for (;;) { 6659 if (kvm_vcpu_running(vcpu)) { 6660 r = vcpu_enter_guest(vcpu); 6661 } else { 6662 r = vcpu_block(kvm, vcpu); 6663 } 6664 6665 if (r <= 0) 6666 break; 6667 6668 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); 6669 if (kvm_cpu_has_pending_timer(vcpu)) 6670 kvm_inject_pending_timer_irqs(vcpu); 6671 6672 if (dm_request_for_irq_injection(vcpu) && 6673 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 6674 r = 0; 6675 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 6676 ++vcpu->stat.request_irq_exits; 6677 break; 6678 } 6679 6680 kvm_check_async_pf_completion(vcpu); 6681 6682 if (signal_pending(current)) { 6683 r = -EINTR; 6684 vcpu->run->exit_reason = KVM_EXIT_INTR; 6685 ++vcpu->stat.signal_exits; 6686 break; 6687 } 6688 if (need_resched()) { 6689 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6690 cond_resched(); 6691 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6692 } 6693 } 6694 6695 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6696 6697 return r; 6698 } 6699 6700 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 6701 { 6702 int r; 6703 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6704 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 6705 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6706 if (r != EMULATE_DONE) 6707 return 0; 6708 return 1; 6709 } 6710 6711 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 6712 { 6713 BUG_ON(!vcpu->arch.pio.count); 6714 6715 return complete_emulated_io(vcpu); 6716 } 6717 6718 /* 6719 * Implements the following, as a state machine: 6720 * 6721 * read: 6722 * for each fragment 6723 * for each mmio piece in the fragment 6724 * write gpa, len 6725 * exit 6726 * copy data 6727 * execute insn 6728 * 6729 * write: 6730 * for each fragment 6731 * for each mmio piece in the fragment 6732 * write gpa, len 6733 * copy data 6734 * exit 6735 */ 6736 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 6737 { 6738 struct kvm_run *run = vcpu->run; 6739 struct kvm_mmio_fragment *frag; 6740 unsigned len; 6741 6742 BUG_ON(!vcpu->mmio_needed); 6743 6744 /* Complete previous fragment */ 6745 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 6746 len = min(8u, frag->len); 6747 if (!vcpu->mmio_is_write) 6748 memcpy(frag->data, run->mmio.data, len); 6749 6750 if (frag->len <= 8) { 6751 /* Switch to the next fragment. */ 6752 frag++; 6753 vcpu->mmio_cur_fragment++; 6754 } else { 6755 /* Go forward to the next mmio piece. */ 6756 frag->data += len; 6757 frag->gpa += len; 6758 frag->len -= len; 6759 } 6760 6761 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 6762 vcpu->mmio_needed = 0; 6763 6764 /* FIXME: return into emulator if single-stepping. */ 6765 if (vcpu->mmio_is_write) 6766 return 1; 6767 vcpu->mmio_read_completed = 1; 6768 return complete_emulated_io(vcpu); 6769 } 6770 6771 run->exit_reason = KVM_EXIT_MMIO; 6772 run->mmio.phys_addr = frag->gpa; 6773 if (vcpu->mmio_is_write) 6774 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 6775 run->mmio.len = min(8u, frag->len); 6776 run->mmio.is_write = vcpu->mmio_is_write; 6777 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6778 return 0; 6779 } 6780 6781 6782 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 6783 { 6784 struct fpu *fpu = ¤t->thread.fpu; 6785 int r; 6786 sigset_t sigsaved; 6787 6788 fpu__activate_curr(fpu); 6789 6790 if (vcpu->sigset_active) 6791 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); 6792 6793 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 6794 kvm_vcpu_block(vcpu); 6795 kvm_apic_accept_events(vcpu); 6796 clear_bit(KVM_REQ_UNHALT, &vcpu->requests); 6797 r = -EAGAIN; 6798 goto out; 6799 } 6800 6801 /* re-sync apic's tpr */ 6802 if (!lapic_in_kernel(vcpu)) { 6803 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 6804 r = -EINVAL; 6805 goto out; 6806 } 6807 } 6808 6809 if (unlikely(vcpu->arch.complete_userspace_io)) { 6810 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 6811 vcpu->arch.complete_userspace_io = NULL; 6812 r = cui(vcpu); 6813 if (r <= 0) 6814 goto out; 6815 } else 6816 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 6817 6818 r = vcpu_run(vcpu); 6819 6820 out: 6821 post_kvm_run_save(vcpu); 6822 if (vcpu->sigset_active) 6823 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 6824 6825 return r; 6826 } 6827 6828 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6829 { 6830 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 6831 /* 6832 * We are here if userspace calls get_regs() in the middle of 6833 * instruction emulation. Registers state needs to be copied 6834 * back from emulation context to vcpu. Userspace shouldn't do 6835 * that usually, but some bad designed PV devices (vmware 6836 * backdoor interface) need this to work 6837 */ 6838 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 6839 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6840 } 6841 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 6842 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 6843 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 6844 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 6845 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 6846 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 6847 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 6848 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 6849 #ifdef CONFIG_X86_64 6850 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 6851 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 6852 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 6853 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 6854 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 6855 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 6856 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 6857 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 6858 #endif 6859 6860 regs->rip = kvm_rip_read(vcpu); 6861 regs->rflags = kvm_get_rflags(vcpu); 6862 6863 return 0; 6864 } 6865 6866 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6867 { 6868 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 6869 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6870 6871 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 6872 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 6873 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 6874 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 6875 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 6876 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 6877 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 6878 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 6879 #ifdef CONFIG_X86_64 6880 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 6881 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 6882 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 6883 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 6884 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 6885 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 6886 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 6887 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 6888 #endif 6889 6890 kvm_rip_write(vcpu, regs->rip); 6891 kvm_set_rflags(vcpu, regs->rflags); 6892 6893 vcpu->arch.exception.pending = false; 6894 6895 kvm_make_request(KVM_REQ_EVENT, vcpu); 6896 6897 return 0; 6898 } 6899 6900 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 6901 { 6902 struct kvm_segment cs; 6903 6904 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 6905 *db = cs.db; 6906 *l = cs.l; 6907 } 6908 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 6909 6910 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 6911 struct kvm_sregs *sregs) 6912 { 6913 struct desc_ptr dt; 6914 6915 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 6916 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 6917 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 6918 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 6919 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 6920 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 6921 6922 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 6923 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 6924 6925 kvm_x86_ops->get_idt(vcpu, &dt); 6926 sregs->idt.limit = dt.size; 6927 sregs->idt.base = dt.address; 6928 kvm_x86_ops->get_gdt(vcpu, &dt); 6929 sregs->gdt.limit = dt.size; 6930 sregs->gdt.base = dt.address; 6931 6932 sregs->cr0 = kvm_read_cr0(vcpu); 6933 sregs->cr2 = vcpu->arch.cr2; 6934 sregs->cr3 = kvm_read_cr3(vcpu); 6935 sregs->cr4 = kvm_read_cr4(vcpu); 6936 sregs->cr8 = kvm_get_cr8(vcpu); 6937 sregs->efer = vcpu->arch.efer; 6938 sregs->apic_base = kvm_get_apic_base(vcpu); 6939 6940 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 6941 6942 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) 6943 set_bit(vcpu->arch.interrupt.nr, 6944 (unsigned long *)sregs->interrupt_bitmap); 6945 6946 return 0; 6947 } 6948 6949 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 6950 struct kvm_mp_state *mp_state) 6951 { 6952 kvm_apic_accept_events(vcpu); 6953 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 6954 vcpu->arch.pv.pv_unhalted) 6955 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 6956 else 6957 mp_state->mp_state = vcpu->arch.mp_state; 6958 6959 return 0; 6960 } 6961 6962 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 6963 struct kvm_mp_state *mp_state) 6964 { 6965 if (!kvm_vcpu_has_lapic(vcpu) && 6966 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 6967 return -EINVAL; 6968 6969 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 6970 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 6971 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 6972 } else 6973 vcpu->arch.mp_state = mp_state->mp_state; 6974 kvm_make_request(KVM_REQ_EVENT, vcpu); 6975 return 0; 6976 } 6977 6978 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 6979 int reason, bool has_error_code, u32 error_code) 6980 { 6981 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6982 int ret; 6983 6984 init_emulate_ctxt(vcpu); 6985 6986 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 6987 has_error_code, error_code); 6988 6989 if (ret) 6990 return EMULATE_FAIL; 6991 6992 kvm_rip_write(vcpu, ctxt->eip); 6993 kvm_set_rflags(vcpu, ctxt->eflags); 6994 kvm_make_request(KVM_REQ_EVENT, vcpu); 6995 return EMULATE_DONE; 6996 } 6997 EXPORT_SYMBOL_GPL(kvm_task_switch); 6998 6999 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 7000 struct kvm_sregs *sregs) 7001 { 7002 struct msr_data apic_base_msr; 7003 int mmu_reset_needed = 0; 7004 int pending_vec, max_bits, idx; 7005 struct desc_ptr dt; 7006 7007 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) 7008 return -EINVAL; 7009 7010 dt.size = sregs->idt.limit; 7011 dt.address = sregs->idt.base; 7012 kvm_x86_ops->set_idt(vcpu, &dt); 7013 dt.size = sregs->gdt.limit; 7014 dt.address = sregs->gdt.base; 7015 kvm_x86_ops->set_gdt(vcpu, &dt); 7016 7017 vcpu->arch.cr2 = sregs->cr2; 7018 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 7019 vcpu->arch.cr3 = sregs->cr3; 7020 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 7021 7022 kvm_set_cr8(vcpu, sregs->cr8); 7023 7024 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 7025 kvm_x86_ops->set_efer(vcpu, sregs->efer); 7026 apic_base_msr.data = sregs->apic_base; 7027 apic_base_msr.host_initiated = true; 7028 kvm_set_apic_base(vcpu, &apic_base_msr); 7029 7030 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 7031 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 7032 vcpu->arch.cr0 = sregs->cr0; 7033 7034 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 7035 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 7036 if (sregs->cr4 & X86_CR4_OSXSAVE) 7037 kvm_update_cpuid(vcpu); 7038 7039 idx = srcu_read_lock(&vcpu->kvm->srcu); 7040 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 7041 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 7042 mmu_reset_needed = 1; 7043 } 7044 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7045 7046 if (mmu_reset_needed) 7047 kvm_mmu_reset_context(vcpu); 7048 7049 max_bits = KVM_NR_INTERRUPTS; 7050 pending_vec = find_first_bit( 7051 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 7052 if (pending_vec < max_bits) { 7053 kvm_queue_interrupt(vcpu, pending_vec, false); 7054 pr_debug("Set back pending irq %d\n", pending_vec); 7055 } 7056 7057 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7058 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7059 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7060 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7061 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7062 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7063 7064 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7065 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7066 7067 update_cr8_intercept(vcpu); 7068 7069 /* Older userspace won't unhalt the vcpu on reset. */ 7070 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 7071 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 7072 !is_protmode(vcpu)) 7073 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7074 7075 kvm_make_request(KVM_REQ_EVENT, vcpu); 7076 7077 return 0; 7078 } 7079 7080 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 7081 struct kvm_guest_debug *dbg) 7082 { 7083 unsigned long rflags; 7084 int i, r; 7085 7086 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 7087 r = -EBUSY; 7088 if (vcpu->arch.exception.pending) 7089 goto out; 7090 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 7091 kvm_queue_exception(vcpu, DB_VECTOR); 7092 else 7093 kvm_queue_exception(vcpu, BP_VECTOR); 7094 } 7095 7096 /* 7097 * Read rflags as long as potentially injected trace flags are still 7098 * filtered out. 7099 */ 7100 rflags = kvm_get_rflags(vcpu); 7101 7102 vcpu->guest_debug = dbg->control; 7103 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 7104 vcpu->guest_debug = 0; 7105 7106 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 7107 for (i = 0; i < KVM_NR_DB_REGS; ++i) 7108 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 7109 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 7110 } else { 7111 for (i = 0; i < KVM_NR_DB_REGS; i++) 7112 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 7113 } 7114 kvm_update_dr7(vcpu); 7115 7116 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 7117 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 7118 get_segment_base(vcpu, VCPU_SREG_CS); 7119 7120 /* 7121 * Trigger an rflags update that will inject or remove the trace 7122 * flags. 7123 */ 7124 kvm_set_rflags(vcpu, rflags); 7125 7126 kvm_x86_ops->update_bp_intercept(vcpu); 7127 7128 r = 0; 7129 7130 out: 7131 7132 return r; 7133 } 7134 7135 /* 7136 * Translate a guest virtual address to a guest physical address. 7137 */ 7138 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 7139 struct kvm_translation *tr) 7140 { 7141 unsigned long vaddr = tr->linear_address; 7142 gpa_t gpa; 7143 int idx; 7144 7145 idx = srcu_read_lock(&vcpu->kvm->srcu); 7146 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 7147 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7148 tr->physical_address = gpa; 7149 tr->valid = gpa != UNMAPPED_GVA; 7150 tr->writeable = 1; 7151 tr->usermode = 0; 7152 7153 return 0; 7154 } 7155 7156 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7157 { 7158 struct fxregs_state *fxsave = 7159 &vcpu->arch.guest_fpu.state.fxsave; 7160 7161 memcpy(fpu->fpr, fxsave->st_space, 128); 7162 fpu->fcw = fxsave->cwd; 7163 fpu->fsw = fxsave->swd; 7164 fpu->ftwx = fxsave->twd; 7165 fpu->last_opcode = fxsave->fop; 7166 fpu->last_ip = fxsave->rip; 7167 fpu->last_dp = fxsave->rdp; 7168 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 7169 7170 return 0; 7171 } 7172 7173 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7174 { 7175 struct fxregs_state *fxsave = 7176 &vcpu->arch.guest_fpu.state.fxsave; 7177 7178 memcpy(fxsave->st_space, fpu->fpr, 128); 7179 fxsave->cwd = fpu->fcw; 7180 fxsave->swd = fpu->fsw; 7181 fxsave->twd = fpu->ftwx; 7182 fxsave->fop = fpu->last_opcode; 7183 fxsave->rip = fpu->last_ip; 7184 fxsave->rdp = fpu->last_dp; 7185 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 7186 7187 return 0; 7188 } 7189 7190 static void fx_init(struct kvm_vcpu *vcpu) 7191 { 7192 fpstate_init(&vcpu->arch.guest_fpu.state); 7193 if (cpu_has_xsaves) 7194 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv = 7195 host_xcr0 | XSTATE_COMPACTION_ENABLED; 7196 7197 /* 7198 * Ensure guest xcr0 is valid for loading 7199 */ 7200 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 7201 7202 vcpu->arch.cr0 |= X86_CR0_ET; 7203 } 7204 7205 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 7206 { 7207 if (vcpu->guest_fpu_loaded) 7208 return; 7209 7210 /* 7211 * Restore all possible states in the guest, 7212 * and assume host would use all available bits. 7213 * Guest xcr0 would be loaded later. 7214 */ 7215 kvm_put_guest_xcr0(vcpu); 7216 vcpu->guest_fpu_loaded = 1; 7217 __kernel_fpu_begin(); 7218 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state); 7219 trace_kvm_fpu(1); 7220 } 7221 7222 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 7223 { 7224 kvm_put_guest_xcr0(vcpu); 7225 7226 if (!vcpu->guest_fpu_loaded) { 7227 vcpu->fpu_counter = 0; 7228 return; 7229 } 7230 7231 vcpu->guest_fpu_loaded = 0; 7232 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu); 7233 __kernel_fpu_end(); 7234 ++vcpu->stat.fpu_reload; 7235 /* 7236 * If using eager FPU mode, or if the guest is a frequent user 7237 * of the FPU, just leave the FPU active for next time. 7238 * Every 255 times fpu_counter rolls over to 0; a guest that uses 7239 * the FPU in bursts will revert to loading it on demand. 7240 */ 7241 if (!vcpu->arch.eager_fpu) { 7242 if (++vcpu->fpu_counter < 5) 7243 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); 7244 } 7245 trace_kvm_fpu(0); 7246 } 7247 7248 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 7249 { 7250 kvmclock_reset(vcpu); 7251 7252 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 7253 kvm_x86_ops->vcpu_free(vcpu); 7254 } 7255 7256 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 7257 unsigned int id) 7258 { 7259 struct kvm_vcpu *vcpu; 7260 7261 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 7262 printk_once(KERN_WARNING 7263 "kvm: SMP vm created on host with unstable TSC; " 7264 "guest TSC will not be reliable\n"); 7265 7266 vcpu = kvm_x86_ops->vcpu_create(kvm, id); 7267 7268 return vcpu; 7269 } 7270 7271 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 7272 { 7273 int r; 7274 7275 kvm_vcpu_mtrr_init(vcpu); 7276 r = vcpu_load(vcpu); 7277 if (r) 7278 return r; 7279 kvm_vcpu_reset(vcpu, false); 7280 kvm_mmu_setup(vcpu); 7281 vcpu_put(vcpu); 7282 return r; 7283 } 7284 7285 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 7286 { 7287 struct msr_data msr; 7288 struct kvm *kvm = vcpu->kvm; 7289 7290 if (vcpu_load(vcpu)) 7291 return; 7292 msr.data = 0x0; 7293 msr.index = MSR_IA32_TSC; 7294 msr.host_initiated = true; 7295 kvm_write_tsc(vcpu, &msr); 7296 vcpu_put(vcpu); 7297 7298 if (!kvmclock_periodic_sync) 7299 return; 7300 7301 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 7302 KVMCLOCK_SYNC_PERIOD); 7303 } 7304 7305 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 7306 { 7307 int r; 7308 vcpu->arch.apf.msr_val = 0; 7309 7310 r = vcpu_load(vcpu); 7311 BUG_ON(r); 7312 kvm_mmu_unload(vcpu); 7313 vcpu_put(vcpu); 7314 7315 kvm_x86_ops->vcpu_free(vcpu); 7316 } 7317 7318 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 7319 { 7320 vcpu->arch.hflags = 0; 7321 7322 atomic_set(&vcpu->arch.nmi_queued, 0); 7323 vcpu->arch.nmi_pending = 0; 7324 vcpu->arch.nmi_injected = false; 7325 kvm_clear_interrupt_queue(vcpu); 7326 kvm_clear_exception_queue(vcpu); 7327 7328 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 7329 kvm_update_dr0123(vcpu); 7330 vcpu->arch.dr6 = DR6_INIT; 7331 kvm_update_dr6(vcpu); 7332 vcpu->arch.dr7 = DR7_FIXED_1; 7333 kvm_update_dr7(vcpu); 7334 7335 vcpu->arch.cr2 = 0; 7336 7337 kvm_make_request(KVM_REQ_EVENT, vcpu); 7338 vcpu->arch.apf.msr_val = 0; 7339 vcpu->arch.st.msr_val = 0; 7340 7341 kvmclock_reset(vcpu); 7342 7343 kvm_clear_async_pf_completion_queue(vcpu); 7344 kvm_async_pf_hash_reset(vcpu); 7345 vcpu->arch.apf.halted = false; 7346 7347 if (!init_event) { 7348 kvm_pmu_reset(vcpu); 7349 vcpu->arch.smbase = 0x30000; 7350 } 7351 7352 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 7353 vcpu->arch.regs_avail = ~0; 7354 vcpu->arch.regs_dirty = ~0; 7355 7356 kvm_x86_ops->vcpu_reset(vcpu, init_event); 7357 } 7358 7359 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 7360 { 7361 struct kvm_segment cs; 7362 7363 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7364 cs.selector = vector << 8; 7365 cs.base = vector << 12; 7366 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7367 kvm_rip_write(vcpu, 0); 7368 } 7369 7370 int kvm_arch_hardware_enable(void) 7371 { 7372 struct kvm *kvm; 7373 struct kvm_vcpu *vcpu; 7374 int i; 7375 int ret; 7376 u64 local_tsc; 7377 u64 max_tsc = 0; 7378 bool stable, backwards_tsc = false; 7379 7380 kvm_shared_msr_cpu_online(); 7381 ret = kvm_x86_ops->hardware_enable(); 7382 if (ret != 0) 7383 return ret; 7384 7385 local_tsc = rdtsc(); 7386 stable = !check_tsc_unstable(); 7387 list_for_each_entry(kvm, &vm_list, vm_list) { 7388 kvm_for_each_vcpu(i, vcpu, kvm) { 7389 if (!stable && vcpu->cpu == smp_processor_id()) 7390 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7391 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 7392 backwards_tsc = true; 7393 if (vcpu->arch.last_host_tsc > max_tsc) 7394 max_tsc = vcpu->arch.last_host_tsc; 7395 } 7396 } 7397 } 7398 7399 /* 7400 * Sometimes, even reliable TSCs go backwards. This happens on 7401 * platforms that reset TSC during suspend or hibernate actions, but 7402 * maintain synchronization. We must compensate. Fortunately, we can 7403 * detect that condition here, which happens early in CPU bringup, 7404 * before any KVM threads can be running. Unfortunately, we can't 7405 * bring the TSCs fully up to date with real time, as we aren't yet far 7406 * enough into CPU bringup that we know how much real time has actually 7407 * elapsed; our helper function, get_kernel_ns() will be using boot 7408 * variables that haven't been updated yet. 7409 * 7410 * So we simply find the maximum observed TSC above, then record the 7411 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 7412 * the adjustment will be applied. Note that we accumulate 7413 * adjustments, in case multiple suspend cycles happen before some VCPU 7414 * gets a chance to run again. In the event that no KVM threads get a 7415 * chance to run, we will miss the entire elapsed period, as we'll have 7416 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 7417 * loose cycle time. This isn't too big a deal, since the loss will be 7418 * uniform across all VCPUs (not to mention the scenario is extremely 7419 * unlikely). It is possible that a second hibernate recovery happens 7420 * much faster than a first, causing the observed TSC here to be 7421 * smaller; this would require additional padding adjustment, which is 7422 * why we set last_host_tsc to the local tsc observed here. 7423 * 7424 * N.B. - this code below runs only on platforms with reliable TSC, 7425 * as that is the only way backwards_tsc is set above. Also note 7426 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 7427 * have the same delta_cyc adjustment applied if backwards_tsc 7428 * is detected. Note further, this adjustment is only done once, 7429 * as we reset last_host_tsc on all VCPUs to stop this from being 7430 * called multiple times (one for each physical CPU bringup). 7431 * 7432 * Platforms with unreliable TSCs don't have to deal with this, they 7433 * will be compensated by the logic in vcpu_load, which sets the TSC to 7434 * catchup mode. This will catchup all VCPUs to real time, but cannot 7435 * guarantee that they stay in perfect synchronization. 7436 */ 7437 if (backwards_tsc) { 7438 u64 delta_cyc = max_tsc - local_tsc; 7439 backwards_tsc_observed = true; 7440 list_for_each_entry(kvm, &vm_list, vm_list) { 7441 kvm_for_each_vcpu(i, vcpu, kvm) { 7442 vcpu->arch.tsc_offset_adjustment += delta_cyc; 7443 vcpu->arch.last_host_tsc = local_tsc; 7444 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7445 } 7446 7447 /* 7448 * We have to disable TSC offset matching.. if you were 7449 * booting a VM while issuing an S4 host suspend.... 7450 * you may have some problem. Solving this issue is 7451 * left as an exercise to the reader. 7452 */ 7453 kvm->arch.last_tsc_nsec = 0; 7454 kvm->arch.last_tsc_write = 0; 7455 } 7456 7457 } 7458 return 0; 7459 } 7460 7461 void kvm_arch_hardware_disable(void) 7462 { 7463 kvm_x86_ops->hardware_disable(); 7464 drop_user_return_notifiers(); 7465 } 7466 7467 int kvm_arch_hardware_setup(void) 7468 { 7469 int r; 7470 7471 r = kvm_x86_ops->hardware_setup(); 7472 if (r != 0) 7473 return r; 7474 7475 if (kvm_has_tsc_control) { 7476 /* 7477 * Make sure the user can only configure tsc_khz values that 7478 * fit into a signed integer. 7479 * A min value is not calculated needed because it will always 7480 * be 1 on all machines. 7481 */ 7482 u64 max = min(0x7fffffffULL, 7483 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 7484 kvm_max_guest_tsc_khz = max; 7485 7486 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 7487 } 7488 7489 kvm_init_msr_list(); 7490 return 0; 7491 } 7492 7493 void kvm_arch_hardware_unsetup(void) 7494 { 7495 kvm_x86_ops->hardware_unsetup(); 7496 } 7497 7498 void kvm_arch_check_processor_compat(void *rtn) 7499 { 7500 kvm_x86_ops->check_processor_compatibility(rtn); 7501 } 7502 7503 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 7504 { 7505 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 7506 } 7507 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 7508 7509 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 7510 { 7511 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 7512 } 7513 7514 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) 7515 { 7516 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu); 7517 } 7518 7519 struct static_key kvm_no_apic_vcpu __read_mostly; 7520 7521 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 7522 { 7523 struct page *page; 7524 struct kvm *kvm; 7525 int r; 7526 7527 BUG_ON(vcpu->kvm == NULL); 7528 kvm = vcpu->kvm; 7529 7530 vcpu->arch.pv.pv_unhalted = false; 7531 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 7532 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 7533 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7534 else 7535 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 7536 7537 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 7538 if (!page) { 7539 r = -ENOMEM; 7540 goto fail; 7541 } 7542 vcpu->arch.pio_data = page_address(page); 7543 7544 kvm_set_tsc_khz(vcpu, max_tsc_khz); 7545 7546 r = kvm_mmu_create(vcpu); 7547 if (r < 0) 7548 goto fail_free_pio_data; 7549 7550 if (irqchip_in_kernel(kvm)) { 7551 r = kvm_create_lapic(vcpu); 7552 if (r < 0) 7553 goto fail_mmu_destroy; 7554 } else 7555 static_key_slow_inc(&kvm_no_apic_vcpu); 7556 7557 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 7558 GFP_KERNEL); 7559 if (!vcpu->arch.mce_banks) { 7560 r = -ENOMEM; 7561 goto fail_free_lapic; 7562 } 7563 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 7564 7565 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 7566 r = -ENOMEM; 7567 goto fail_free_mce_banks; 7568 } 7569 7570 fx_init(vcpu); 7571 7572 vcpu->arch.ia32_tsc_adjust_msr = 0x0; 7573 vcpu->arch.pv_time_enabled = false; 7574 7575 vcpu->arch.guest_supported_xcr0 = 0; 7576 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 7577 7578 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 7579 7580 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 7581 7582 kvm_async_pf_hash_reset(vcpu); 7583 kvm_pmu_init(vcpu); 7584 7585 vcpu->arch.pending_external_vector = -1; 7586 7587 return 0; 7588 7589 fail_free_mce_banks: 7590 kfree(vcpu->arch.mce_banks); 7591 fail_free_lapic: 7592 kvm_free_lapic(vcpu); 7593 fail_mmu_destroy: 7594 kvm_mmu_destroy(vcpu); 7595 fail_free_pio_data: 7596 free_page((unsigned long)vcpu->arch.pio_data); 7597 fail: 7598 return r; 7599 } 7600 7601 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 7602 { 7603 int idx; 7604 7605 kvm_pmu_destroy(vcpu); 7606 kfree(vcpu->arch.mce_banks); 7607 kvm_free_lapic(vcpu); 7608 idx = srcu_read_lock(&vcpu->kvm->srcu); 7609 kvm_mmu_destroy(vcpu); 7610 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7611 free_page((unsigned long)vcpu->arch.pio_data); 7612 if (!lapic_in_kernel(vcpu)) 7613 static_key_slow_dec(&kvm_no_apic_vcpu); 7614 } 7615 7616 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 7617 { 7618 kvm_x86_ops->sched_in(vcpu, cpu); 7619 } 7620 7621 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 7622 { 7623 if (type) 7624 return -EINVAL; 7625 7626 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 7627 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 7628 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 7629 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 7630 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 7631 7632 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 7633 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 7634 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 7635 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 7636 &kvm->arch.irq_sources_bitmap); 7637 7638 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 7639 mutex_init(&kvm->arch.apic_map_lock); 7640 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 7641 7642 pvclock_update_vm_gtod_copy(kvm); 7643 7644 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 7645 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 7646 7647 return 0; 7648 } 7649 7650 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 7651 { 7652 int r; 7653 r = vcpu_load(vcpu); 7654 BUG_ON(r); 7655 kvm_mmu_unload(vcpu); 7656 vcpu_put(vcpu); 7657 } 7658 7659 static void kvm_free_vcpus(struct kvm *kvm) 7660 { 7661 unsigned int i; 7662 struct kvm_vcpu *vcpu; 7663 7664 /* 7665 * Unpin any mmu pages first. 7666 */ 7667 kvm_for_each_vcpu(i, vcpu, kvm) { 7668 kvm_clear_async_pf_completion_queue(vcpu); 7669 kvm_unload_vcpu_mmu(vcpu); 7670 } 7671 kvm_for_each_vcpu(i, vcpu, kvm) 7672 kvm_arch_vcpu_free(vcpu); 7673 7674 mutex_lock(&kvm->lock); 7675 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 7676 kvm->vcpus[i] = NULL; 7677 7678 atomic_set(&kvm->online_vcpus, 0); 7679 mutex_unlock(&kvm->lock); 7680 } 7681 7682 void kvm_arch_sync_events(struct kvm *kvm) 7683 { 7684 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 7685 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 7686 kvm_free_all_assigned_devices(kvm); 7687 kvm_free_pit(kvm); 7688 } 7689 7690 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 7691 { 7692 int i, r; 7693 unsigned long hva; 7694 struct kvm_memslots *slots = kvm_memslots(kvm); 7695 struct kvm_memory_slot *slot, old; 7696 7697 /* Called with kvm->slots_lock held. */ 7698 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 7699 return -EINVAL; 7700 7701 slot = id_to_memslot(slots, id); 7702 if (size) { 7703 if (WARN_ON(slot->npages)) 7704 return -EEXIST; 7705 7706 /* 7707 * MAP_SHARED to prevent internal slot pages from being moved 7708 * by fork()/COW. 7709 */ 7710 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 7711 MAP_SHARED | MAP_ANONYMOUS, 0); 7712 if (IS_ERR((void *)hva)) 7713 return PTR_ERR((void *)hva); 7714 } else { 7715 if (!slot->npages) 7716 return 0; 7717 7718 hva = 0; 7719 } 7720 7721 old = *slot; 7722 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 7723 struct kvm_userspace_memory_region m; 7724 7725 m.slot = id | (i << 16); 7726 m.flags = 0; 7727 m.guest_phys_addr = gpa; 7728 m.userspace_addr = hva; 7729 m.memory_size = size; 7730 r = __kvm_set_memory_region(kvm, &m); 7731 if (r < 0) 7732 return r; 7733 } 7734 7735 if (!size) { 7736 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); 7737 WARN_ON(r < 0); 7738 } 7739 7740 return 0; 7741 } 7742 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 7743 7744 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 7745 { 7746 int r; 7747 7748 mutex_lock(&kvm->slots_lock); 7749 r = __x86_set_memory_region(kvm, id, gpa, size); 7750 mutex_unlock(&kvm->slots_lock); 7751 7752 return r; 7753 } 7754 EXPORT_SYMBOL_GPL(x86_set_memory_region); 7755 7756 void kvm_arch_destroy_vm(struct kvm *kvm) 7757 { 7758 if (current->mm == kvm->mm) { 7759 /* 7760 * Free memory regions allocated on behalf of userspace, 7761 * unless the the memory map has changed due to process exit 7762 * or fd copying. 7763 */ 7764 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); 7765 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); 7766 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 7767 } 7768 kvm_iommu_unmap_guest(kvm); 7769 kfree(kvm->arch.vpic); 7770 kfree(kvm->arch.vioapic); 7771 kvm_free_vcpus(kvm); 7772 kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 7773 } 7774 7775 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 7776 struct kvm_memory_slot *dont) 7777 { 7778 int i; 7779 7780 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7781 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 7782 kvfree(free->arch.rmap[i]); 7783 free->arch.rmap[i] = NULL; 7784 } 7785 if (i == 0) 7786 continue; 7787 7788 if (!dont || free->arch.lpage_info[i - 1] != 7789 dont->arch.lpage_info[i - 1]) { 7790 kvfree(free->arch.lpage_info[i - 1]); 7791 free->arch.lpage_info[i - 1] = NULL; 7792 } 7793 } 7794 } 7795 7796 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 7797 unsigned long npages) 7798 { 7799 int i; 7800 7801 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7802 unsigned long ugfn; 7803 int lpages; 7804 int level = i + 1; 7805 7806 lpages = gfn_to_index(slot->base_gfn + npages - 1, 7807 slot->base_gfn, level) + 1; 7808 7809 slot->arch.rmap[i] = 7810 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); 7811 if (!slot->arch.rmap[i]) 7812 goto out_free; 7813 if (i == 0) 7814 continue; 7815 7816 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages * 7817 sizeof(*slot->arch.lpage_info[i - 1])); 7818 if (!slot->arch.lpage_info[i - 1]) 7819 goto out_free; 7820 7821 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 7822 slot->arch.lpage_info[i - 1][0].write_count = 1; 7823 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 7824 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1; 7825 ugfn = slot->userspace_addr >> PAGE_SHIFT; 7826 /* 7827 * If the gfn and userspace address are not aligned wrt each 7828 * other, or if explicitly asked to, disable large page 7829 * support for this slot 7830 */ 7831 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 7832 !kvm_largepages_enabled()) { 7833 unsigned long j; 7834 7835 for (j = 0; j < lpages; ++j) 7836 slot->arch.lpage_info[i - 1][j].write_count = 1; 7837 } 7838 } 7839 7840 return 0; 7841 7842 out_free: 7843 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7844 kvfree(slot->arch.rmap[i]); 7845 slot->arch.rmap[i] = NULL; 7846 if (i == 0) 7847 continue; 7848 7849 kvfree(slot->arch.lpage_info[i - 1]); 7850 slot->arch.lpage_info[i - 1] = NULL; 7851 } 7852 return -ENOMEM; 7853 } 7854 7855 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) 7856 { 7857 /* 7858 * memslots->generation has been incremented. 7859 * mmio generation may have reached its maximum value. 7860 */ 7861 kvm_mmu_invalidate_mmio_sptes(kvm, slots); 7862 } 7863 7864 int kvm_arch_prepare_memory_region(struct kvm *kvm, 7865 struct kvm_memory_slot *memslot, 7866 const struct kvm_userspace_memory_region *mem, 7867 enum kvm_mr_change change) 7868 { 7869 return 0; 7870 } 7871 7872 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 7873 struct kvm_memory_slot *new) 7874 { 7875 /* Still write protect RO slot */ 7876 if (new->flags & KVM_MEM_READONLY) { 7877 kvm_mmu_slot_remove_write_access(kvm, new); 7878 return; 7879 } 7880 7881 /* 7882 * Call kvm_x86_ops dirty logging hooks when they are valid. 7883 * 7884 * kvm_x86_ops->slot_disable_log_dirty is called when: 7885 * 7886 * - KVM_MR_CREATE with dirty logging is disabled 7887 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 7888 * 7889 * The reason is, in case of PML, we need to set D-bit for any slots 7890 * with dirty logging disabled in order to eliminate unnecessary GPA 7891 * logging in PML buffer (and potential PML buffer full VMEXT). This 7892 * guarantees leaving PML enabled during guest's lifetime won't have 7893 * any additonal overhead from PML when guest is running with dirty 7894 * logging disabled for memory slots. 7895 * 7896 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 7897 * to dirty logging mode. 7898 * 7899 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 7900 * 7901 * In case of write protect: 7902 * 7903 * Write protect all pages for dirty logging. 7904 * 7905 * All the sptes including the large sptes which point to this 7906 * slot are set to readonly. We can not create any new large 7907 * spte on this slot until the end of the logging. 7908 * 7909 * See the comments in fast_page_fault(). 7910 */ 7911 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 7912 if (kvm_x86_ops->slot_enable_log_dirty) 7913 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 7914 else 7915 kvm_mmu_slot_remove_write_access(kvm, new); 7916 } else { 7917 if (kvm_x86_ops->slot_disable_log_dirty) 7918 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 7919 } 7920 } 7921 7922 void kvm_arch_commit_memory_region(struct kvm *kvm, 7923 const struct kvm_userspace_memory_region *mem, 7924 const struct kvm_memory_slot *old, 7925 const struct kvm_memory_slot *new, 7926 enum kvm_mr_change change) 7927 { 7928 int nr_mmu_pages = 0; 7929 7930 if (!kvm->arch.n_requested_mmu_pages) 7931 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 7932 7933 if (nr_mmu_pages) 7934 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 7935 7936 /* 7937 * Dirty logging tracks sptes in 4k granularity, meaning that large 7938 * sptes have to be split. If live migration is successful, the guest 7939 * in the source machine will be destroyed and large sptes will be 7940 * created in the destination. However, if the guest continues to run 7941 * in the source machine (for example if live migration fails), small 7942 * sptes will remain around and cause bad performance. 7943 * 7944 * Scan sptes if dirty logging has been stopped, dropping those 7945 * which can be collapsed into a single large-page spte. Later 7946 * page faults will create the large-page sptes. 7947 */ 7948 if ((change != KVM_MR_DELETE) && 7949 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 7950 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 7951 kvm_mmu_zap_collapsible_sptes(kvm, new); 7952 7953 /* 7954 * Set up write protection and/or dirty logging for the new slot. 7955 * 7956 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 7957 * been zapped so no dirty logging staff is needed for old slot. For 7958 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 7959 * new and it's also covered when dealing with the new slot. 7960 * 7961 * FIXME: const-ify all uses of struct kvm_memory_slot. 7962 */ 7963 if (change != KVM_MR_DELETE) 7964 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 7965 } 7966 7967 void kvm_arch_flush_shadow_all(struct kvm *kvm) 7968 { 7969 kvm_mmu_invalidate_zap_all_pages(kvm); 7970 } 7971 7972 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 7973 struct kvm_memory_slot *slot) 7974 { 7975 kvm_mmu_invalidate_zap_all_pages(kvm); 7976 } 7977 7978 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 7979 { 7980 if (!list_empty_careful(&vcpu->async_pf.done)) 7981 return true; 7982 7983 if (kvm_apic_has_events(vcpu)) 7984 return true; 7985 7986 if (vcpu->arch.pv.pv_unhalted) 7987 return true; 7988 7989 if (atomic_read(&vcpu->arch.nmi_queued)) 7990 return true; 7991 7992 if (test_bit(KVM_REQ_SMI, &vcpu->requests)) 7993 return true; 7994 7995 if (kvm_arch_interrupt_allowed(vcpu) && 7996 kvm_cpu_has_interrupt(vcpu)) 7997 return true; 7998 7999 return false; 8000 } 8001 8002 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 8003 { 8004 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 8005 kvm_x86_ops->check_nested_events(vcpu, false); 8006 8007 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 8008 } 8009 8010 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 8011 { 8012 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 8013 } 8014 8015 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 8016 { 8017 return kvm_x86_ops->interrupt_allowed(vcpu); 8018 } 8019 8020 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 8021 { 8022 if (is_64_bit_mode(vcpu)) 8023 return kvm_rip_read(vcpu); 8024 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 8025 kvm_rip_read(vcpu)); 8026 } 8027 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 8028 8029 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 8030 { 8031 return kvm_get_linear_rip(vcpu) == linear_rip; 8032 } 8033 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 8034 8035 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 8036 { 8037 unsigned long rflags; 8038 8039 rflags = kvm_x86_ops->get_rflags(vcpu); 8040 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 8041 rflags &= ~X86_EFLAGS_TF; 8042 return rflags; 8043 } 8044 EXPORT_SYMBOL_GPL(kvm_get_rflags); 8045 8046 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8047 { 8048 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 8049 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 8050 rflags |= X86_EFLAGS_TF; 8051 kvm_x86_ops->set_rflags(vcpu, rflags); 8052 } 8053 8054 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8055 { 8056 __kvm_set_rflags(vcpu, rflags); 8057 kvm_make_request(KVM_REQ_EVENT, vcpu); 8058 } 8059 EXPORT_SYMBOL_GPL(kvm_set_rflags); 8060 8061 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 8062 { 8063 int r; 8064 8065 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 8066 work->wakeup_all) 8067 return; 8068 8069 r = kvm_mmu_reload(vcpu); 8070 if (unlikely(r)) 8071 return; 8072 8073 if (!vcpu->arch.mmu.direct_map && 8074 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 8075 return; 8076 8077 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 8078 } 8079 8080 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 8081 { 8082 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 8083 } 8084 8085 static inline u32 kvm_async_pf_next_probe(u32 key) 8086 { 8087 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 8088 } 8089 8090 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8091 { 8092 u32 key = kvm_async_pf_hash_fn(gfn); 8093 8094 while (vcpu->arch.apf.gfns[key] != ~0) 8095 key = kvm_async_pf_next_probe(key); 8096 8097 vcpu->arch.apf.gfns[key] = gfn; 8098 } 8099 8100 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 8101 { 8102 int i; 8103 u32 key = kvm_async_pf_hash_fn(gfn); 8104 8105 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 8106 (vcpu->arch.apf.gfns[key] != gfn && 8107 vcpu->arch.apf.gfns[key] != ~0); i++) 8108 key = kvm_async_pf_next_probe(key); 8109 8110 return key; 8111 } 8112 8113 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8114 { 8115 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 8116 } 8117 8118 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8119 { 8120 u32 i, j, k; 8121 8122 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 8123 while (true) { 8124 vcpu->arch.apf.gfns[i] = ~0; 8125 do { 8126 j = kvm_async_pf_next_probe(j); 8127 if (vcpu->arch.apf.gfns[j] == ~0) 8128 return; 8129 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 8130 /* 8131 * k lies cyclically in ]i,j] 8132 * | i.k.j | 8133 * |....j i.k.| or |.k..j i...| 8134 */ 8135 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 8136 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 8137 i = j; 8138 } 8139 } 8140 8141 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 8142 { 8143 8144 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 8145 sizeof(val)); 8146 } 8147 8148 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 8149 struct kvm_async_pf *work) 8150 { 8151 struct x86_exception fault; 8152 8153 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 8154 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 8155 8156 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 8157 (vcpu->arch.apf.send_user_only && 8158 kvm_x86_ops->get_cpl(vcpu) == 0)) 8159 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 8160 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 8161 fault.vector = PF_VECTOR; 8162 fault.error_code_valid = true; 8163 fault.error_code = 0; 8164 fault.nested_page_fault = false; 8165 fault.address = work->arch.token; 8166 kvm_inject_page_fault(vcpu, &fault); 8167 } 8168 } 8169 8170 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 8171 struct kvm_async_pf *work) 8172 { 8173 struct x86_exception fault; 8174 8175 trace_kvm_async_pf_ready(work->arch.token, work->gva); 8176 if (work->wakeup_all) 8177 work->arch.token = ~0; /* broadcast wakeup */ 8178 else 8179 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 8180 8181 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && 8182 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 8183 fault.vector = PF_VECTOR; 8184 fault.error_code_valid = true; 8185 fault.error_code = 0; 8186 fault.nested_page_fault = false; 8187 fault.address = work->arch.token; 8188 kvm_inject_page_fault(vcpu, &fault); 8189 } 8190 vcpu->arch.apf.halted = false; 8191 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8192 } 8193 8194 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 8195 { 8196 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 8197 return true; 8198 else 8199 return !kvm_event_needs_reinjection(vcpu) && 8200 kvm_x86_ops->interrupt_allowed(vcpu); 8201 } 8202 8203 void kvm_arch_start_assignment(struct kvm *kvm) 8204 { 8205 atomic_inc(&kvm->arch.assigned_device_count); 8206 } 8207 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 8208 8209 void kvm_arch_end_assignment(struct kvm *kvm) 8210 { 8211 atomic_dec(&kvm->arch.assigned_device_count); 8212 } 8213 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 8214 8215 bool kvm_arch_has_assigned_device(struct kvm *kvm) 8216 { 8217 return atomic_read(&kvm->arch.assigned_device_count); 8218 } 8219 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 8220 8221 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 8222 { 8223 atomic_inc(&kvm->arch.noncoherent_dma_count); 8224 } 8225 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 8226 8227 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 8228 { 8229 atomic_dec(&kvm->arch.noncoherent_dma_count); 8230 } 8231 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 8232 8233 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 8234 { 8235 return atomic_read(&kvm->arch.noncoherent_dma_count); 8236 } 8237 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 8238 8239 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 8240 struct irq_bypass_producer *prod) 8241 { 8242 struct kvm_kernel_irqfd *irqfd = 8243 container_of(cons, struct kvm_kernel_irqfd, consumer); 8244 8245 if (kvm_x86_ops->update_pi_irte) { 8246 irqfd->producer = prod; 8247 return kvm_x86_ops->update_pi_irte(irqfd->kvm, 8248 prod->irq, irqfd->gsi, 1); 8249 } 8250 8251 return -EINVAL; 8252 } 8253 8254 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 8255 struct irq_bypass_producer *prod) 8256 { 8257 int ret; 8258 struct kvm_kernel_irqfd *irqfd = 8259 container_of(cons, struct kvm_kernel_irqfd, consumer); 8260 8261 if (!kvm_x86_ops->update_pi_irte) { 8262 WARN_ON(irqfd->producer != NULL); 8263 return; 8264 } 8265 8266 WARN_ON(irqfd->producer != prod); 8267 irqfd->producer = NULL; 8268 8269 /* 8270 * When producer of consumer is unregistered, we change back to 8271 * remapped mode, so we can re-use the current implementation 8272 * when the irq is masked/disabed or the consumer side (KVM 8273 * int this case doesn't want to receive the interrupts. 8274 */ 8275 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 8276 if (ret) 8277 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 8278 " fails: %d\n", irqfd->consumer.token, ret); 8279 } 8280 8281 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 8282 uint32_t guest_irq, bool set) 8283 { 8284 if (!kvm_x86_ops->update_pi_irte) 8285 return -EINVAL; 8286 8287 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); 8288 } 8289 8290 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 8291 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 8292 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 8293 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 8294 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 8295 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 8296 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 8297 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 8298 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 8299 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 8300 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 8301 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 8302 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 8303 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 8304 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 8305 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 8306 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 8307