1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "assigned-dev.h" 31 #include "pmu.h" 32 #include "hyperv.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/module.h> 40 #include <linux/mman.h> 41 #include <linux/highmem.h> 42 #include <linux/iommu.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/cpufreq.h> 45 #include <linux/user-return-notifier.h> 46 #include <linux/srcu.h> 47 #include <linux/slab.h> 48 #include <linux/perf_event.h> 49 #include <linux/uaccess.h> 50 #include <linux/hash.h> 51 #include <linux/pci.h> 52 #include <linux/timekeeper_internal.h> 53 #include <linux/pvclock_gtod.h> 54 #include <linux/kvm_irqfd.h> 55 #include <linux/irqbypass.h> 56 #include <trace/events/kvm.h> 57 58 #define CREATE_TRACE_POINTS 59 #include "trace.h" 60 61 #include <asm/debugreg.h> 62 #include <asm/msr.h> 63 #include <asm/desc.h> 64 #include <asm/mce.h> 65 #include <linux/kernel_stat.h> 66 #include <asm/fpu/internal.h> /* Ugh! */ 67 #include <asm/pvclock.h> 68 #include <asm/div64.h> 69 #include <asm/irq_remapping.h> 70 71 #define MAX_IO_MSRS 256 72 #define KVM_MAX_MCE_BANKS 32 73 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) 74 75 #define emul_to_vcpu(ctxt) \ 76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 77 78 /* EFER defaults: 79 * - enable syscall per default because its emulated by KVM 80 * - enable LME and LMA per default on 64 bit KVM 81 */ 82 #ifdef CONFIG_X86_64 83 static 84 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 85 #else 86 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 87 #endif 88 89 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 90 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 91 92 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 93 static void process_nmi(struct kvm_vcpu *vcpu); 94 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 95 96 struct kvm_x86_ops *kvm_x86_ops __read_mostly; 97 EXPORT_SYMBOL_GPL(kvm_x86_ops); 98 99 static bool __read_mostly ignore_msrs = 0; 100 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 101 102 unsigned int min_timer_period_us = 500; 103 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 104 105 static bool __read_mostly kvmclock_periodic_sync = true; 106 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 107 108 bool __read_mostly kvm_has_tsc_control; 109 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 110 u32 __read_mostly kvm_max_guest_tsc_khz; 111 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 112 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 113 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 114 u64 __read_mostly kvm_max_tsc_scaling_ratio; 115 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 116 static u64 __read_mostly kvm_default_tsc_scaling_ratio; 117 118 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 119 static u32 __read_mostly tsc_tolerance_ppm = 250; 120 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 121 122 /* lapic timer advance (tscdeadline mode only) in nanoseconds */ 123 unsigned int __read_mostly lapic_timer_advance_ns = 0; 124 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 125 126 static bool __read_mostly vector_hashing = true; 127 module_param(vector_hashing, bool, S_IRUGO); 128 129 static bool __read_mostly backwards_tsc_observed = false; 130 131 #define KVM_NR_SHARED_MSRS 16 132 133 struct kvm_shared_msrs_global { 134 int nr; 135 u32 msrs[KVM_NR_SHARED_MSRS]; 136 }; 137 138 struct kvm_shared_msrs { 139 struct user_return_notifier urn; 140 bool registered; 141 struct kvm_shared_msr_values { 142 u64 host; 143 u64 curr; 144 } values[KVM_NR_SHARED_MSRS]; 145 }; 146 147 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 148 static struct kvm_shared_msrs __percpu *shared_msrs; 149 150 struct kvm_stats_debugfs_item debugfs_entries[] = { 151 { "pf_fixed", VCPU_STAT(pf_fixed) }, 152 { "pf_guest", VCPU_STAT(pf_guest) }, 153 { "tlb_flush", VCPU_STAT(tlb_flush) }, 154 { "invlpg", VCPU_STAT(invlpg) }, 155 { "exits", VCPU_STAT(exits) }, 156 { "io_exits", VCPU_STAT(io_exits) }, 157 { "mmio_exits", VCPU_STAT(mmio_exits) }, 158 { "signal_exits", VCPU_STAT(signal_exits) }, 159 { "irq_window", VCPU_STAT(irq_window_exits) }, 160 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 161 { "halt_exits", VCPU_STAT(halt_exits) }, 162 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 163 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 164 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, 165 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 166 { "hypercalls", VCPU_STAT(hypercalls) }, 167 { "request_irq", VCPU_STAT(request_irq_exits) }, 168 { "irq_exits", VCPU_STAT(irq_exits) }, 169 { "host_state_reload", VCPU_STAT(host_state_reload) }, 170 { "efer_reload", VCPU_STAT(efer_reload) }, 171 { "fpu_reload", VCPU_STAT(fpu_reload) }, 172 { "insn_emulation", VCPU_STAT(insn_emulation) }, 173 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 174 { "irq_injections", VCPU_STAT(irq_injections) }, 175 { "nmi_injections", VCPU_STAT(nmi_injections) }, 176 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 177 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 178 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 179 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 180 { "mmu_flooded", VM_STAT(mmu_flooded) }, 181 { "mmu_recycled", VM_STAT(mmu_recycled) }, 182 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 183 { "mmu_unsync", VM_STAT(mmu_unsync) }, 184 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 185 { "largepages", VM_STAT(lpages) }, 186 { NULL } 187 }; 188 189 u64 __read_mostly host_xcr0; 190 191 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 192 193 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 194 { 195 int i; 196 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 197 vcpu->arch.apf.gfns[i] = ~0; 198 } 199 200 static void kvm_on_user_return(struct user_return_notifier *urn) 201 { 202 unsigned slot; 203 struct kvm_shared_msrs *locals 204 = container_of(urn, struct kvm_shared_msrs, urn); 205 struct kvm_shared_msr_values *values; 206 207 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 208 values = &locals->values[slot]; 209 if (values->host != values->curr) { 210 wrmsrl(shared_msrs_global.msrs[slot], values->host); 211 values->curr = values->host; 212 } 213 } 214 locals->registered = false; 215 user_return_notifier_unregister(urn); 216 } 217 218 static void shared_msr_update(unsigned slot, u32 msr) 219 { 220 u64 value; 221 unsigned int cpu = smp_processor_id(); 222 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 223 224 /* only read, and nobody should modify it at this time, 225 * so don't need lock */ 226 if (slot >= shared_msrs_global.nr) { 227 printk(KERN_ERR "kvm: invalid MSR slot!"); 228 return; 229 } 230 rdmsrl_safe(msr, &value); 231 smsr->values[slot].host = value; 232 smsr->values[slot].curr = value; 233 } 234 235 void kvm_define_shared_msr(unsigned slot, u32 msr) 236 { 237 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 238 shared_msrs_global.msrs[slot] = msr; 239 if (slot >= shared_msrs_global.nr) 240 shared_msrs_global.nr = slot + 1; 241 } 242 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 243 244 static void kvm_shared_msr_cpu_online(void) 245 { 246 unsigned i; 247 248 for (i = 0; i < shared_msrs_global.nr; ++i) 249 shared_msr_update(i, shared_msrs_global.msrs[i]); 250 } 251 252 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 253 { 254 unsigned int cpu = smp_processor_id(); 255 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 256 int err; 257 258 if (((value ^ smsr->values[slot].curr) & mask) == 0) 259 return 0; 260 smsr->values[slot].curr = value; 261 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 262 if (err) 263 return 1; 264 265 if (!smsr->registered) { 266 smsr->urn.on_user_return = kvm_on_user_return; 267 user_return_notifier_register(&smsr->urn); 268 smsr->registered = true; 269 } 270 return 0; 271 } 272 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 273 274 static void drop_user_return_notifiers(void) 275 { 276 unsigned int cpu = smp_processor_id(); 277 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 278 279 if (smsr->registered) 280 kvm_on_user_return(&smsr->urn); 281 } 282 283 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 284 { 285 return vcpu->arch.apic_base; 286 } 287 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 288 289 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 290 { 291 u64 old_state = vcpu->arch.apic_base & 292 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 293 u64 new_state = msr_info->data & 294 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 295 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 296 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); 297 298 if (!msr_info->host_initiated && 299 ((msr_info->data & reserved_bits) != 0 || 300 new_state == X2APIC_ENABLE || 301 (new_state == MSR_IA32_APICBASE_ENABLE && 302 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 303 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 304 old_state == 0))) 305 return 1; 306 307 kvm_lapic_set_base(vcpu, msr_info->data); 308 return 0; 309 } 310 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 311 312 asmlinkage __visible void kvm_spurious_fault(void) 313 { 314 /* Fault while not rebooting. We want the trace. */ 315 BUG(); 316 } 317 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 318 319 #define EXCPT_BENIGN 0 320 #define EXCPT_CONTRIBUTORY 1 321 #define EXCPT_PF 2 322 323 static int exception_class(int vector) 324 { 325 switch (vector) { 326 case PF_VECTOR: 327 return EXCPT_PF; 328 case DE_VECTOR: 329 case TS_VECTOR: 330 case NP_VECTOR: 331 case SS_VECTOR: 332 case GP_VECTOR: 333 return EXCPT_CONTRIBUTORY; 334 default: 335 break; 336 } 337 return EXCPT_BENIGN; 338 } 339 340 #define EXCPT_FAULT 0 341 #define EXCPT_TRAP 1 342 #define EXCPT_ABORT 2 343 #define EXCPT_INTERRUPT 3 344 345 static int exception_type(int vector) 346 { 347 unsigned int mask; 348 349 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 350 return EXCPT_INTERRUPT; 351 352 mask = 1 << vector; 353 354 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 355 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 356 return EXCPT_TRAP; 357 358 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 359 return EXCPT_ABORT; 360 361 /* Reserved exceptions will result in fault */ 362 return EXCPT_FAULT; 363 } 364 365 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 366 unsigned nr, bool has_error, u32 error_code, 367 bool reinject) 368 { 369 u32 prev_nr; 370 int class1, class2; 371 372 kvm_make_request(KVM_REQ_EVENT, vcpu); 373 374 if (!vcpu->arch.exception.pending) { 375 queue: 376 if (has_error && !is_protmode(vcpu)) 377 has_error = false; 378 vcpu->arch.exception.pending = true; 379 vcpu->arch.exception.has_error_code = has_error; 380 vcpu->arch.exception.nr = nr; 381 vcpu->arch.exception.error_code = error_code; 382 vcpu->arch.exception.reinject = reinject; 383 return; 384 } 385 386 /* to check exception */ 387 prev_nr = vcpu->arch.exception.nr; 388 if (prev_nr == DF_VECTOR) { 389 /* triple fault -> shutdown */ 390 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 391 return; 392 } 393 class1 = exception_class(prev_nr); 394 class2 = exception_class(nr); 395 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 396 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 397 /* generate double fault per SDM Table 5-5 */ 398 vcpu->arch.exception.pending = true; 399 vcpu->arch.exception.has_error_code = true; 400 vcpu->arch.exception.nr = DF_VECTOR; 401 vcpu->arch.exception.error_code = 0; 402 } else 403 /* replace previous exception with a new one in a hope 404 that instruction re-execution will regenerate lost 405 exception */ 406 goto queue; 407 } 408 409 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 410 { 411 kvm_multiple_exception(vcpu, nr, false, 0, false); 412 } 413 EXPORT_SYMBOL_GPL(kvm_queue_exception); 414 415 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 416 { 417 kvm_multiple_exception(vcpu, nr, false, 0, true); 418 } 419 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 420 421 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 422 { 423 if (err) 424 kvm_inject_gp(vcpu, 0); 425 else 426 kvm_x86_ops->skip_emulated_instruction(vcpu); 427 } 428 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 429 430 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 431 { 432 ++vcpu->stat.pf_guest; 433 vcpu->arch.cr2 = fault->address; 434 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 435 } 436 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 437 438 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 439 { 440 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 441 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 442 else 443 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 444 445 return fault->nested_page_fault; 446 } 447 448 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 449 { 450 atomic_inc(&vcpu->arch.nmi_queued); 451 kvm_make_request(KVM_REQ_NMI, vcpu); 452 } 453 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 454 455 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 456 { 457 kvm_multiple_exception(vcpu, nr, true, error_code, false); 458 } 459 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 460 461 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 462 { 463 kvm_multiple_exception(vcpu, nr, true, error_code, true); 464 } 465 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 466 467 /* 468 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 469 * a #GP and return false. 470 */ 471 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 472 { 473 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 474 return true; 475 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 476 return false; 477 } 478 EXPORT_SYMBOL_GPL(kvm_require_cpl); 479 480 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 481 { 482 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 483 return true; 484 485 kvm_queue_exception(vcpu, UD_VECTOR); 486 return false; 487 } 488 EXPORT_SYMBOL_GPL(kvm_require_dr); 489 490 /* 491 * This function will be used to read from the physical memory of the currently 492 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 493 * can read from guest physical or from the guest's guest physical memory. 494 */ 495 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 496 gfn_t ngfn, void *data, int offset, int len, 497 u32 access) 498 { 499 struct x86_exception exception; 500 gfn_t real_gfn; 501 gpa_t ngpa; 502 503 ngpa = gfn_to_gpa(ngfn); 504 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 505 if (real_gfn == UNMAPPED_GVA) 506 return -EFAULT; 507 508 real_gfn = gpa_to_gfn(real_gfn); 509 510 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 511 } 512 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 513 514 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 515 void *data, int offset, int len, u32 access) 516 { 517 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 518 data, offset, len, access); 519 } 520 521 /* 522 * Load the pae pdptrs. Return true is they are all valid. 523 */ 524 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 525 { 526 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 527 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 528 int i; 529 int ret; 530 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 531 532 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 533 offset * sizeof(u64), sizeof(pdpte), 534 PFERR_USER_MASK|PFERR_WRITE_MASK); 535 if (ret < 0) { 536 ret = 0; 537 goto out; 538 } 539 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 540 if (is_present_gpte(pdpte[i]) && 541 (pdpte[i] & 542 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) { 543 ret = 0; 544 goto out; 545 } 546 } 547 ret = 1; 548 549 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 550 __set_bit(VCPU_EXREG_PDPTR, 551 (unsigned long *)&vcpu->arch.regs_avail); 552 __set_bit(VCPU_EXREG_PDPTR, 553 (unsigned long *)&vcpu->arch.regs_dirty); 554 out: 555 556 return ret; 557 } 558 EXPORT_SYMBOL_GPL(load_pdptrs); 559 560 static bool pdptrs_changed(struct kvm_vcpu *vcpu) 561 { 562 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 563 bool changed = true; 564 int offset; 565 gfn_t gfn; 566 int r; 567 568 if (is_long_mode(vcpu) || !is_pae(vcpu)) 569 return false; 570 571 if (!test_bit(VCPU_EXREG_PDPTR, 572 (unsigned long *)&vcpu->arch.regs_avail)) 573 return true; 574 575 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; 576 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); 577 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 578 PFERR_USER_MASK | PFERR_WRITE_MASK); 579 if (r < 0) 580 goto out; 581 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 582 out: 583 584 return changed; 585 } 586 587 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 588 { 589 unsigned long old_cr0 = kvm_read_cr0(vcpu); 590 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 591 592 cr0 |= X86_CR0_ET; 593 594 #ifdef CONFIG_X86_64 595 if (cr0 & 0xffffffff00000000UL) 596 return 1; 597 #endif 598 599 cr0 &= ~CR0_RESERVED_BITS; 600 601 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 602 return 1; 603 604 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 605 return 1; 606 607 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 608 #ifdef CONFIG_X86_64 609 if ((vcpu->arch.efer & EFER_LME)) { 610 int cs_db, cs_l; 611 612 if (!is_pae(vcpu)) 613 return 1; 614 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 615 if (cs_l) 616 return 1; 617 } else 618 #endif 619 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 620 kvm_read_cr3(vcpu))) 621 return 1; 622 } 623 624 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 625 return 1; 626 627 kvm_x86_ops->set_cr0(vcpu, cr0); 628 629 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 630 kvm_clear_async_pf_completion_queue(vcpu); 631 kvm_async_pf_hash_reset(vcpu); 632 } 633 634 if ((cr0 ^ old_cr0) & update_bits) 635 kvm_mmu_reset_context(vcpu); 636 637 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 638 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 639 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 640 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 641 642 return 0; 643 } 644 EXPORT_SYMBOL_GPL(kvm_set_cr0); 645 646 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 647 { 648 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 649 } 650 EXPORT_SYMBOL_GPL(kvm_lmsw); 651 652 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 653 { 654 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 655 !vcpu->guest_xcr0_loaded) { 656 /* kvm_set_xcr() also depends on this */ 657 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 658 vcpu->guest_xcr0_loaded = 1; 659 } 660 } 661 662 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 663 { 664 if (vcpu->guest_xcr0_loaded) { 665 if (vcpu->arch.xcr0 != host_xcr0) 666 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 667 vcpu->guest_xcr0_loaded = 0; 668 } 669 } 670 671 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 672 { 673 u64 xcr0 = xcr; 674 u64 old_xcr0 = vcpu->arch.xcr0; 675 u64 valid_bits; 676 677 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 678 if (index != XCR_XFEATURE_ENABLED_MASK) 679 return 1; 680 if (!(xcr0 & XFEATURE_MASK_FP)) 681 return 1; 682 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 683 return 1; 684 685 /* 686 * Do not allow the guest to set bits that we do not support 687 * saving. However, xcr0 bit 0 is always set, even if the 688 * emulated CPU does not support XSAVE (see fx_init). 689 */ 690 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 691 if (xcr0 & ~valid_bits) 692 return 1; 693 694 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 695 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 696 return 1; 697 698 if (xcr0 & XFEATURE_MASK_AVX512) { 699 if (!(xcr0 & XFEATURE_MASK_YMM)) 700 return 1; 701 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 702 return 1; 703 } 704 vcpu->arch.xcr0 = xcr0; 705 706 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 707 kvm_update_cpuid(vcpu); 708 return 0; 709 } 710 711 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 712 { 713 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 714 __kvm_set_xcr(vcpu, index, xcr)) { 715 kvm_inject_gp(vcpu, 0); 716 return 1; 717 } 718 return 0; 719 } 720 EXPORT_SYMBOL_GPL(kvm_set_xcr); 721 722 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 723 { 724 unsigned long old_cr4 = kvm_read_cr4(vcpu); 725 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 726 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 727 728 if (cr4 & CR4_RESERVED_BITS) 729 return 1; 730 731 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) 732 return 1; 733 734 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) 735 return 1; 736 737 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) 738 return 1; 739 740 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) 741 return 1; 742 743 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE)) 744 return 1; 745 746 if (is_long_mode(vcpu)) { 747 if (!(cr4 & X86_CR4_PAE)) 748 return 1; 749 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 750 && ((cr4 ^ old_cr4) & pdptr_bits) 751 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 752 kvm_read_cr3(vcpu))) 753 return 1; 754 755 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 756 if (!guest_cpuid_has_pcid(vcpu)) 757 return 1; 758 759 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 760 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 761 return 1; 762 } 763 764 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 765 return 1; 766 767 if (((cr4 ^ old_cr4) & pdptr_bits) || 768 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 769 kvm_mmu_reset_context(vcpu); 770 771 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 772 kvm_update_cpuid(vcpu); 773 774 return 0; 775 } 776 EXPORT_SYMBOL_GPL(kvm_set_cr4); 777 778 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 779 { 780 #ifdef CONFIG_X86_64 781 cr3 &= ~CR3_PCID_INVD; 782 #endif 783 784 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 785 kvm_mmu_sync_roots(vcpu); 786 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 787 return 0; 788 } 789 790 if (is_long_mode(vcpu)) { 791 if (cr3 & CR3_L_MODE_RESERVED_BITS) 792 return 1; 793 } else if (is_pae(vcpu) && is_paging(vcpu) && 794 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 795 return 1; 796 797 vcpu->arch.cr3 = cr3; 798 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 799 kvm_mmu_new_cr3(vcpu); 800 return 0; 801 } 802 EXPORT_SYMBOL_GPL(kvm_set_cr3); 803 804 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 805 { 806 if (cr8 & CR8_RESERVED_BITS) 807 return 1; 808 if (lapic_in_kernel(vcpu)) 809 kvm_lapic_set_tpr(vcpu, cr8); 810 else 811 vcpu->arch.cr8 = cr8; 812 return 0; 813 } 814 EXPORT_SYMBOL_GPL(kvm_set_cr8); 815 816 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 817 { 818 if (lapic_in_kernel(vcpu)) 819 return kvm_lapic_get_cr8(vcpu); 820 else 821 return vcpu->arch.cr8; 822 } 823 EXPORT_SYMBOL_GPL(kvm_get_cr8); 824 825 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 826 { 827 int i; 828 829 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 830 for (i = 0; i < KVM_NR_DB_REGS; i++) 831 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 832 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 833 } 834 } 835 836 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 837 { 838 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 839 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 840 } 841 842 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 843 { 844 unsigned long dr7; 845 846 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 847 dr7 = vcpu->arch.guest_debug_dr7; 848 else 849 dr7 = vcpu->arch.dr7; 850 kvm_x86_ops->set_dr7(vcpu, dr7); 851 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 852 if (dr7 & DR7_BP_EN_MASK) 853 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 854 } 855 856 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 857 { 858 u64 fixed = DR6_FIXED_1; 859 860 if (!guest_cpuid_has_rtm(vcpu)) 861 fixed |= DR6_RTM; 862 return fixed; 863 } 864 865 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 866 { 867 switch (dr) { 868 case 0 ... 3: 869 vcpu->arch.db[dr] = val; 870 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 871 vcpu->arch.eff_db[dr] = val; 872 break; 873 case 4: 874 /* fall through */ 875 case 6: 876 if (val & 0xffffffff00000000ULL) 877 return -1; /* #GP */ 878 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 879 kvm_update_dr6(vcpu); 880 break; 881 case 5: 882 /* fall through */ 883 default: /* 7 */ 884 if (val & 0xffffffff00000000ULL) 885 return -1; /* #GP */ 886 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 887 kvm_update_dr7(vcpu); 888 break; 889 } 890 891 return 0; 892 } 893 894 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 895 { 896 if (__kvm_set_dr(vcpu, dr, val)) { 897 kvm_inject_gp(vcpu, 0); 898 return 1; 899 } 900 return 0; 901 } 902 EXPORT_SYMBOL_GPL(kvm_set_dr); 903 904 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 905 { 906 switch (dr) { 907 case 0 ... 3: 908 *val = vcpu->arch.db[dr]; 909 break; 910 case 4: 911 /* fall through */ 912 case 6: 913 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 914 *val = vcpu->arch.dr6; 915 else 916 *val = kvm_x86_ops->get_dr6(vcpu); 917 break; 918 case 5: 919 /* fall through */ 920 default: /* 7 */ 921 *val = vcpu->arch.dr7; 922 break; 923 } 924 return 0; 925 } 926 EXPORT_SYMBOL_GPL(kvm_get_dr); 927 928 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 929 { 930 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 931 u64 data; 932 int err; 933 934 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 935 if (err) 936 return err; 937 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 938 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 939 return err; 940 } 941 EXPORT_SYMBOL_GPL(kvm_rdpmc); 942 943 /* 944 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 945 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 946 * 947 * This list is modified at module load time to reflect the 948 * capabilities of the host cpu. This capabilities test skips MSRs that are 949 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs 950 * may depend on host virtualization features rather than host cpu features. 951 */ 952 953 static u32 msrs_to_save[] = { 954 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 955 MSR_STAR, 956 #ifdef CONFIG_X86_64 957 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 958 #endif 959 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 960 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 961 }; 962 963 static unsigned num_msrs_to_save; 964 965 static u32 emulated_msrs[] = { 966 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 967 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 968 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 969 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 970 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 971 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 972 HV_X64_MSR_RESET, 973 HV_X64_MSR_VP_INDEX, 974 HV_X64_MSR_VP_RUNTIME, 975 HV_X64_MSR_SCONTROL, 976 HV_X64_MSR_STIMER0_CONFIG, 977 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 978 MSR_KVM_PV_EOI_EN, 979 980 MSR_IA32_TSC_ADJUST, 981 MSR_IA32_TSCDEADLINE, 982 MSR_IA32_MISC_ENABLE, 983 MSR_IA32_MCG_STATUS, 984 MSR_IA32_MCG_CTL, 985 MSR_IA32_SMBASE, 986 }; 987 988 static unsigned num_emulated_msrs; 989 990 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 991 { 992 if (efer & efer_reserved_bits) 993 return false; 994 995 if (efer & EFER_FFXSR) { 996 struct kvm_cpuid_entry2 *feat; 997 998 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 999 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) 1000 return false; 1001 } 1002 1003 if (efer & EFER_SVME) { 1004 struct kvm_cpuid_entry2 *feat; 1005 1006 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 1007 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) 1008 return false; 1009 } 1010 1011 return true; 1012 } 1013 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1014 1015 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 1016 { 1017 u64 old_efer = vcpu->arch.efer; 1018 1019 if (!kvm_valid_efer(vcpu, efer)) 1020 return 1; 1021 1022 if (is_paging(vcpu) 1023 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1024 return 1; 1025 1026 efer &= ~EFER_LMA; 1027 efer |= vcpu->arch.efer & EFER_LMA; 1028 1029 kvm_x86_ops->set_efer(vcpu, efer); 1030 1031 /* Update reserved bits */ 1032 if ((efer ^ old_efer) & EFER_NX) 1033 kvm_mmu_reset_context(vcpu); 1034 1035 return 0; 1036 } 1037 1038 void kvm_enable_efer_bits(u64 mask) 1039 { 1040 efer_reserved_bits &= ~mask; 1041 } 1042 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1043 1044 /* 1045 * Writes msr value into into the appropriate "register". 1046 * Returns 0 on success, non-0 otherwise. 1047 * Assumes vcpu_load() was already called. 1048 */ 1049 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1050 { 1051 switch (msr->index) { 1052 case MSR_FS_BASE: 1053 case MSR_GS_BASE: 1054 case MSR_KERNEL_GS_BASE: 1055 case MSR_CSTAR: 1056 case MSR_LSTAR: 1057 if (is_noncanonical_address(msr->data)) 1058 return 1; 1059 break; 1060 case MSR_IA32_SYSENTER_EIP: 1061 case MSR_IA32_SYSENTER_ESP: 1062 /* 1063 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1064 * non-canonical address is written on Intel but not on 1065 * AMD (which ignores the top 32-bits, because it does 1066 * not implement 64-bit SYSENTER). 1067 * 1068 * 64-bit code should hence be able to write a non-canonical 1069 * value on AMD. Making the address canonical ensures that 1070 * vmentry does not fail on Intel after writing a non-canonical 1071 * value, and that something deterministic happens if the guest 1072 * invokes 64-bit SYSENTER. 1073 */ 1074 msr->data = get_canonical(msr->data); 1075 } 1076 return kvm_x86_ops->set_msr(vcpu, msr); 1077 } 1078 EXPORT_SYMBOL_GPL(kvm_set_msr); 1079 1080 /* 1081 * Adapt set_msr() to msr_io()'s calling convention 1082 */ 1083 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1084 { 1085 struct msr_data msr; 1086 int r; 1087 1088 msr.index = index; 1089 msr.host_initiated = true; 1090 r = kvm_get_msr(vcpu, &msr); 1091 if (r) 1092 return r; 1093 1094 *data = msr.data; 1095 return 0; 1096 } 1097 1098 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1099 { 1100 struct msr_data msr; 1101 1102 msr.data = *data; 1103 msr.index = index; 1104 msr.host_initiated = true; 1105 return kvm_set_msr(vcpu, &msr); 1106 } 1107 1108 #ifdef CONFIG_X86_64 1109 struct pvclock_gtod_data { 1110 seqcount_t seq; 1111 1112 struct { /* extract of a clocksource struct */ 1113 int vclock_mode; 1114 cycle_t cycle_last; 1115 cycle_t mask; 1116 u32 mult; 1117 u32 shift; 1118 } clock; 1119 1120 u64 boot_ns; 1121 u64 nsec_base; 1122 }; 1123 1124 static struct pvclock_gtod_data pvclock_gtod_data; 1125 1126 static void update_pvclock_gtod(struct timekeeper *tk) 1127 { 1128 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1129 u64 boot_ns; 1130 1131 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1132 1133 write_seqcount_begin(&vdata->seq); 1134 1135 /* copy pvclock gtod data */ 1136 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1137 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1138 vdata->clock.mask = tk->tkr_mono.mask; 1139 vdata->clock.mult = tk->tkr_mono.mult; 1140 vdata->clock.shift = tk->tkr_mono.shift; 1141 1142 vdata->boot_ns = boot_ns; 1143 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1144 1145 write_seqcount_end(&vdata->seq); 1146 } 1147 #endif 1148 1149 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1150 { 1151 /* 1152 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1153 * vcpu_enter_guest. This function is only called from 1154 * the physical CPU that is running vcpu. 1155 */ 1156 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1157 } 1158 1159 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1160 { 1161 int version; 1162 int r; 1163 struct pvclock_wall_clock wc; 1164 struct timespec boot; 1165 1166 if (!wall_clock) 1167 return; 1168 1169 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1170 if (r) 1171 return; 1172 1173 if (version & 1) 1174 ++version; /* first time write, random junk */ 1175 1176 ++version; 1177 1178 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1179 return; 1180 1181 /* 1182 * The guest calculates current wall clock time by adding 1183 * system time (updated by kvm_guest_time_update below) to the 1184 * wall clock specified here. guest system time equals host 1185 * system time for us, thus we must fill in host boot time here. 1186 */ 1187 getboottime(&boot); 1188 1189 if (kvm->arch.kvmclock_offset) { 1190 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); 1191 boot = timespec_sub(boot, ts); 1192 } 1193 wc.sec = boot.tv_sec; 1194 wc.nsec = boot.tv_nsec; 1195 wc.version = version; 1196 1197 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1198 1199 version++; 1200 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1201 } 1202 1203 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1204 { 1205 do_shl32_div32(dividend, divisor); 1206 return dividend; 1207 } 1208 1209 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 1210 s8 *pshift, u32 *pmultiplier) 1211 { 1212 uint64_t scaled64; 1213 int32_t shift = 0; 1214 uint64_t tps64; 1215 uint32_t tps32; 1216 1217 tps64 = base_hz; 1218 scaled64 = scaled_hz; 1219 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1220 tps64 >>= 1; 1221 shift--; 1222 } 1223 1224 tps32 = (uint32_t)tps64; 1225 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1226 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1227 scaled64 >>= 1; 1228 else 1229 tps32 <<= 1; 1230 shift++; 1231 } 1232 1233 *pshift = shift; 1234 *pmultiplier = div_frac(scaled64, tps32); 1235 1236 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n", 1237 __func__, base_hz, scaled_hz, shift, *pmultiplier); 1238 } 1239 1240 #ifdef CONFIG_X86_64 1241 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1242 #endif 1243 1244 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1245 static unsigned long max_tsc_khz; 1246 1247 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) 1248 { 1249 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, 1250 vcpu->arch.virtual_tsc_shift); 1251 } 1252 1253 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1254 { 1255 u64 v = (u64)khz * (1000000 + ppm); 1256 do_div(v, 1000000); 1257 return v; 1258 } 1259 1260 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 1261 { 1262 u64 ratio; 1263 1264 /* Guest TSC same frequency as host TSC? */ 1265 if (!scale) { 1266 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1267 return 0; 1268 } 1269 1270 /* TSC scaling supported? */ 1271 if (!kvm_has_tsc_control) { 1272 if (user_tsc_khz > tsc_khz) { 1273 vcpu->arch.tsc_catchup = 1; 1274 vcpu->arch.tsc_always_catchup = 1; 1275 return 0; 1276 } else { 1277 WARN(1, "user requested TSC rate below hardware speed\n"); 1278 return -1; 1279 } 1280 } 1281 1282 /* TSC scaling required - calculate ratio */ 1283 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 1284 user_tsc_khz, tsc_khz); 1285 1286 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 1287 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 1288 user_tsc_khz); 1289 return -1; 1290 } 1291 1292 vcpu->arch.tsc_scaling_ratio = ratio; 1293 return 0; 1294 } 1295 1296 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 1297 { 1298 u32 thresh_lo, thresh_hi; 1299 int use_scaling = 0; 1300 1301 /* tsc_khz can be zero if TSC calibration fails */ 1302 if (user_tsc_khz == 0) { 1303 /* set tsc_scaling_ratio to a safe value */ 1304 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1305 return -1; 1306 } 1307 1308 /* Compute a scale to convert nanoseconds in TSC cycles */ 1309 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 1310 &vcpu->arch.virtual_tsc_shift, 1311 &vcpu->arch.virtual_tsc_mult); 1312 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 1313 1314 /* 1315 * Compute the variation in TSC rate which is acceptable 1316 * within the range of tolerance and decide if the 1317 * rate being applied is within that bounds of the hardware 1318 * rate. If so, no scaling or compensation need be done. 1319 */ 1320 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1321 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1322 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 1323 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 1324 use_scaling = 1; 1325 } 1326 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 1327 } 1328 1329 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1330 { 1331 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1332 vcpu->arch.virtual_tsc_mult, 1333 vcpu->arch.virtual_tsc_shift); 1334 tsc += vcpu->arch.this_tsc_write; 1335 return tsc; 1336 } 1337 1338 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1339 { 1340 #ifdef CONFIG_X86_64 1341 bool vcpus_matched; 1342 struct kvm_arch *ka = &vcpu->kvm->arch; 1343 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1344 1345 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1346 atomic_read(&vcpu->kvm->online_vcpus)); 1347 1348 /* 1349 * Once the masterclock is enabled, always perform request in 1350 * order to update it. 1351 * 1352 * In order to enable masterclock, the host clocksource must be TSC 1353 * and the vcpus need to have matched TSCs. When that happens, 1354 * perform request to enable masterclock. 1355 */ 1356 if (ka->use_master_clock || 1357 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) 1358 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1359 1360 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1361 atomic_read(&vcpu->kvm->online_vcpus), 1362 ka->use_master_clock, gtod->clock.vclock_mode); 1363 #endif 1364 } 1365 1366 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1367 { 1368 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); 1369 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1370 } 1371 1372 /* 1373 * Multiply tsc by a fixed point number represented by ratio. 1374 * 1375 * The most significant 64-N bits (mult) of ratio represent the 1376 * integral part of the fixed point number; the remaining N bits 1377 * (frac) represent the fractional part, ie. ratio represents a fixed 1378 * point number (mult + frac * 2^(-N)). 1379 * 1380 * N equals to kvm_tsc_scaling_ratio_frac_bits. 1381 */ 1382 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 1383 { 1384 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 1385 } 1386 1387 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 1388 { 1389 u64 _tsc = tsc; 1390 u64 ratio = vcpu->arch.tsc_scaling_ratio; 1391 1392 if (ratio != kvm_default_tsc_scaling_ratio) 1393 _tsc = __scale_tsc(ratio, tsc); 1394 1395 return _tsc; 1396 } 1397 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 1398 1399 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 1400 { 1401 u64 tsc; 1402 1403 tsc = kvm_scale_tsc(vcpu, rdtsc()); 1404 1405 return target_tsc - tsc; 1406 } 1407 1408 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 1409 { 1410 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc)); 1411 } 1412 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 1413 1414 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1415 { 1416 struct kvm *kvm = vcpu->kvm; 1417 u64 offset, ns, elapsed; 1418 unsigned long flags; 1419 s64 usdiff; 1420 bool matched; 1421 bool already_matched; 1422 u64 data = msr->data; 1423 1424 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1425 offset = kvm_compute_tsc_offset(vcpu, data); 1426 ns = get_kernel_ns(); 1427 elapsed = ns - kvm->arch.last_tsc_nsec; 1428 1429 if (vcpu->arch.virtual_tsc_khz) { 1430 int faulted = 0; 1431 1432 /* n.b - signed multiplication and division required */ 1433 usdiff = data - kvm->arch.last_tsc_write; 1434 #ifdef CONFIG_X86_64 1435 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; 1436 #else 1437 /* do_div() only does unsigned */ 1438 asm("1: idivl %[divisor]\n" 1439 "2: xor %%edx, %%edx\n" 1440 " movl $0, %[faulted]\n" 1441 "3:\n" 1442 ".section .fixup,\"ax\"\n" 1443 "4: movl $1, %[faulted]\n" 1444 " jmp 3b\n" 1445 ".previous\n" 1446 1447 _ASM_EXTABLE(1b, 4b) 1448 1449 : "=A"(usdiff), [faulted] "=r" (faulted) 1450 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); 1451 1452 #endif 1453 do_div(elapsed, 1000); 1454 usdiff -= elapsed; 1455 if (usdiff < 0) 1456 usdiff = -usdiff; 1457 1458 /* idivl overflow => difference is larger than USEC_PER_SEC */ 1459 if (faulted) 1460 usdiff = USEC_PER_SEC; 1461 } else 1462 usdiff = USEC_PER_SEC; /* disable TSC match window below */ 1463 1464 /* 1465 * Special case: TSC write with a small delta (1 second) of virtual 1466 * cycle time against real time is interpreted as an attempt to 1467 * synchronize the CPU. 1468 * 1469 * For a reliable TSC, we can match TSC offsets, and for an unstable 1470 * TSC, we add elapsed time in this computation. We could let the 1471 * compensation code attempt to catch up if we fall behind, but 1472 * it's better to try to match offsets from the beginning. 1473 */ 1474 if (usdiff < USEC_PER_SEC && 1475 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1476 if (!check_tsc_unstable()) { 1477 offset = kvm->arch.cur_tsc_offset; 1478 pr_debug("kvm: matched tsc offset for %llu\n", data); 1479 } else { 1480 u64 delta = nsec_to_cycles(vcpu, elapsed); 1481 data += delta; 1482 offset = kvm_compute_tsc_offset(vcpu, data); 1483 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1484 } 1485 matched = true; 1486 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1487 } else { 1488 /* 1489 * We split periods of matched TSC writes into generations. 1490 * For each generation, we track the original measured 1491 * nanosecond time, offset, and write, so if TSCs are in 1492 * sync, we can match exact offset, and if not, we can match 1493 * exact software computation in compute_guest_tsc() 1494 * 1495 * These values are tracked in kvm->arch.cur_xxx variables. 1496 */ 1497 kvm->arch.cur_tsc_generation++; 1498 kvm->arch.cur_tsc_nsec = ns; 1499 kvm->arch.cur_tsc_write = data; 1500 kvm->arch.cur_tsc_offset = offset; 1501 matched = false; 1502 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1503 kvm->arch.cur_tsc_generation, data); 1504 } 1505 1506 /* 1507 * We also track th most recent recorded KHZ, write and time to 1508 * allow the matching interval to be extended at each write. 1509 */ 1510 kvm->arch.last_tsc_nsec = ns; 1511 kvm->arch.last_tsc_write = data; 1512 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1513 1514 vcpu->arch.last_guest_tsc = data; 1515 1516 /* Keep track of which generation this VCPU has synchronized to */ 1517 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1518 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1519 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1520 1521 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) 1522 update_ia32_tsc_adjust_msr(vcpu, offset); 1523 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1524 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1525 1526 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1527 if (!matched) { 1528 kvm->arch.nr_vcpus_matched_tsc = 0; 1529 } else if (!already_matched) { 1530 kvm->arch.nr_vcpus_matched_tsc++; 1531 } 1532 1533 kvm_track_tsc_matching(vcpu); 1534 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1535 } 1536 1537 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1538 1539 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 1540 s64 adjustment) 1541 { 1542 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment); 1543 } 1544 1545 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 1546 { 1547 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 1548 WARN_ON(adjustment < 0); 1549 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 1550 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment); 1551 } 1552 1553 #ifdef CONFIG_X86_64 1554 1555 static cycle_t read_tsc(void) 1556 { 1557 cycle_t ret = (cycle_t)rdtsc_ordered(); 1558 u64 last = pvclock_gtod_data.clock.cycle_last; 1559 1560 if (likely(ret >= last)) 1561 return ret; 1562 1563 /* 1564 * GCC likes to generate cmov here, but this branch is extremely 1565 * predictable (it's just a function of time and the likely is 1566 * very likely) and there's a data dependence, so force GCC 1567 * to generate a branch instead. I don't barrier() because 1568 * we don't actually need a barrier, and if this function 1569 * ever gets inlined it will generate worse code. 1570 */ 1571 asm volatile (""); 1572 return last; 1573 } 1574 1575 static inline u64 vgettsc(cycle_t *cycle_now) 1576 { 1577 long v; 1578 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1579 1580 *cycle_now = read_tsc(); 1581 1582 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; 1583 return v * gtod->clock.mult; 1584 } 1585 1586 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now) 1587 { 1588 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1589 unsigned long seq; 1590 int mode; 1591 u64 ns; 1592 1593 do { 1594 seq = read_seqcount_begin(>od->seq); 1595 mode = gtod->clock.vclock_mode; 1596 ns = gtod->nsec_base; 1597 ns += vgettsc(cycle_now); 1598 ns >>= gtod->clock.shift; 1599 ns += gtod->boot_ns; 1600 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1601 *t = ns; 1602 1603 return mode; 1604 } 1605 1606 /* returns true if host is using tsc clocksource */ 1607 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) 1608 { 1609 /* checked again under seqlock below */ 1610 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) 1611 return false; 1612 1613 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; 1614 } 1615 #endif 1616 1617 /* 1618 * 1619 * Assuming a stable TSC across physical CPUS, and a stable TSC 1620 * across virtual CPUs, the following condition is possible. 1621 * Each numbered line represents an event visible to both 1622 * CPUs at the next numbered event. 1623 * 1624 * "timespecX" represents host monotonic time. "tscX" represents 1625 * RDTSC value. 1626 * 1627 * VCPU0 on CPU0 | VCPU1 on CPU1 1628 * 1629 * 1. read timespec0,tsc0 1630 * 2. | timespec1 = timespec0 + N 1631 * | tsc1 = tsc0 + M 1632 * 3. transition to guest | transition to guest 1633 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1634 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1635 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1636 * 1637 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1638 * 1639 * - ret0 < ret1 1640 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1641 * ... 1642 * - 0 < N - M => M < N 1643 * 1644 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1645 * always the case (the difference between two distinct xtime instances 1646 * might be smaller then the difference between corresponding TSC reads, 1647 * when updating guest vcpus pvclock areas). 1648 * 1649 * To avoid that problem, do not allow visibility of distinct 1650 * system_timestamp/tsc_timestamp values simultaneously: use a master 1651 * copy of host monotonic time values. Update that master copy 1652 * in lockstep. 1653 * 1654 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1655 * 1656 */ 1657 1658 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1659 { 1660 #ifdef CONFIG_X86_64 1661 struct kvm_arch *ka = &kvm->arch; 1662 int vclock_mode; 1663 bool host_tsc_clocksource, vcpus_matched; 1664 1665 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1666 atomic_read(&kvm->online_vcpus)); 1667 1668 /* 1669 * If the host uses TSC clock, then passthrough TSC as stable 1670 * to the guest. 1671 */ 1672 host_tsc_clocksource = kvm_get_time_and_clockread( 1673 &ka->master_kernel_ns, 1674 &ka->master_cycle_now); 1675 1676 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 1677 && !backwards_tsc_observed 1678 && !ka->boot_vcpu_runs_old_kvmclock; 1679 1680 if (ka->use_master_clock) 1681 atomic_set(&kvm_guest_has_master_clock, 1); 1682 1683 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1684 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1685 vcpus_matched); 1686 #endif 1687 } 1688 1689 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 1690 { 1691 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 1692 } 1693 1694 static void kvm_gen_update_masterclock(struct kvm *kvm) 1695 { 1696 #ifdef CONFIG_X86_64 1697 int i; 1698 struct kvm_vcpu *vcpu; 1699 struct kvm_arch *ka = &kvm->arch; 1700 1701 spin_lock(&ka->pvclock_gtod_sync_lock); 1702 kvm_make_mclock_inprogress_request(kvm); 1703 /* no guest entries from this point */ 1704 pvclock_update_vm_gtod_copy(kvm); 1705 1706 kvm_for_each_vcpu(i, vcpu, kvm) 1707 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1708 1709 /* guest entries allowed */ 1710 kvm_for_each_vcpu(i, vcpu, kvm) 1711 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); 1712 1713 spin_unlock(&ka->pvclock_gtod_sync_lock); 1714 #endif 1715 } 1716 1717 static int kvm_guest_time_update(struct kvm_vcpu *v) 1718 { 1719 unsigned long flags, tgt_tsc_khz; 1720 struct kvm_vcpu_arch *vcpu = &v->arch; 1721 struct kvm_arch *ka = &v->kvm->arch; 1722 s64 kernel_ns; 1723 u64 tsc_timestamp, host_tsc; 1724 struct pvclock_vcpu_time_info guest_hv_clock; 1725 u8 pvclock_flags; 1726 bool use_master_clock; 1727 1728 kernel_ns = 0; 1729 host_tsc = 0; 1730 1731 /* 1732 * If the host uses TSC clock, then passthrough TSC as stable 1733 * to the guest. 1734 */ 1735 spin_lock(&ka->pvclock_gtod_sync_lock); 1736 use_master_clock = ka->use_master_clock; 1737 if (use_master_clock) { 1738 host_tsc = ka->master_cycle_now; 1739 kernel_ns = ka->master_kernel_ns; 1740 } 1741 spin_unlock(&ka->pvclock_gtod_sync_lock); 1742 1743 /* Keep irq disabled to prevent changes to the clock */ 1744 local_irq_save(flags); 1745 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 1746 if (unlikely(tgt_tsc_khz == 0)) { 1747 local_irq_restore(flags); 1748 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1749 return 1; 1750 } 1751 if (!use_master_clock) { 1752 host_tsc = rdtsc(); 1753 kernel_ns = get_kernel_ns(); 1754 } 1755 1756 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 1757 1758 /* 1759 * We may have to catch up the TSC to match elapsed wall clock 1760 * time for two reasons, even if kvmclock is used. 1761 * 1) CPU could have been running below the maximum TSC rate 1762 * 2) Broken TSC compensation resets the base at each VCPU 1763 * entry to avoid unknown leaps of TSC even when running 1764 * again on the same CPU. This may cause apparent elapsed 1765 * time to disappear, and the guest to stand still or run 1766 * very slowly. 1767 */ 1768 if (vcpu->tsc_catchup) { 1769 u64 tsc = compute_guest_tsc(v, kernel_ns); 1770 if (tsc > tsc_timestamp) { 1771 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 1772 tsc_timestamp = tsc; 1773 } 1774 } 1775 1776 local_irq_restore(flags); 1777 1778 if (!vcpu->pv_time_enabled) 1779 return 0; 1780 1781 if (kvm_has_tsc_control) 1782 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 1783 1784 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 1785 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 1786 &vcpu->hv_clock.tsc_shift, 1787 &vcpu->hv_clock.tsc_to_system_mul); 1788 vcpu->hw_tsc_khz = tgt_tsc_khz; 1789 } 1790 1791 /* With all the info we got, fill in the values */ 1792 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 1793 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 1794 vcpu->last_guest_tsc = tsc_timestamp; 1795 1796 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1797 &guest_hv_clock, sizeof(guest_hv_clock)))) 1798 return 0; 1799 1800 /* This VCPU is paused, but it's legal for a guest to read another 1801 * VCPU's kvmclock, so we really have to follow the specification where 1802 * it says that version is odd if data is being modified, and even after 1803 * it is consistent. 1804 * 1805 * Version field updates must be kept separate. This is because 1806 * kvm_write_guest_cached might use a "rep movs" instruction, and 1807 * writes within a string instruction are weakly ordered. So there 1808 * are three writes overall. 1809 * 1810 * As a small optimization, only write the version field in the first 1811 * and third write. The vcpu->pv_time cache is still valid, because the 1812 * version field is the first in the struct. 1813 */ 1814 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 1815 1816 vcpu->hv_clock.version = guest_hv_clock.version + 1; 1817 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1818 &vcpu->hv_clock, 1819 sizeof(vcpu->hv_clock.version)); 1820 1821 smp_wmb(); 1822 1823 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1824 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1825 1826 if (vcpu->pvclock_set_guest_stopped_request) { 1827 pvclock_flags |= PVCLOCK_GUEST_STOPPED; 1828 vcpu->pvclock_set_guest_stopped_request = false; 1829 } 1830 1831 /* If the host uses TSC clocksource, then it is stable */ 1832 if (use_master_clock) 1833 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 1834 1835 vcpu->hv_clock.flags = pvclock_flags; 1836 1837 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 1838 1839 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1840 &vcpu->hv_clock, 1841 sizeof(vcpu->hv_clock)); 1842 1843 smp_wmb(); 1844 1845 vcpu->hv_clock.version++; 1846 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1847 &vcpu->hv_clock, 1848 sizeof(vcpu->hv_clock.version)); 1849 return 0; 1850 } 1851 1852 /* 1853 * kvmclock updates which are isolated to a given vcpu, such as 1854 * vcpu->cpu migration, should not allow system_timestamp from 1855 * the rest of the vcpus to remain static. Otherwise ntp frequency 1856 * correction applies to one vcpu's system_timestamp but not 1857 * the others. 1858 * 1859 * So in those cases, request a kvmclock update for all vcpus. 1860 * We need to rate-limit these requests though, as they can 1861 * considerably slow guests that have a large number of vcpus. 1862 * The time for a remote vcpu to update its kvmclock is bound 1863 * by the delay we use to rate-limit the updates. 1864 */ 1865 1866 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 1867 1868 static void kvmclock_update_fn(struct work_struct *work) 1869 { 1870 int i; 1871 struct delayed_work *dwork = to_delayed_work(work); 1872 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1873 kvmclock_update_work); 1874 struct kvm *kvm = container_of(ka, struct kvm, arch); 1875 struct kvm_vcpu *vcpu; 1876 1877 kvm_for_each_vcpu(i, vcpu, kvm) { 1878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1879 kvm_vcpu_kick(vcpu); 1880 } 1881 } 1882 1883 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 1884 { 1885 struct kvm *kvm = v->kvm; 1886 1887 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1888 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 1889 KVMCLOCK_UPDATE_DELAY); 1890 } 1891 1892 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 1893 1894 static void kvmclock_sync_fn(struct work_struct *work) 1895 { 1896 struct delayed_work *dwork = to_delayed_work(work); 1897 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1898 kvmclock_sync_work); 1899 struct kvm *kvm = container_of(ka, struct kvm, arch); 1900 1901 if (!kvmclock_periodic_sync) 1902 return; 1903 1904 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 1905 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 1906 KVMCLOCK_SYNC_PERIOD); 1907 } 1908 1909 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1910 { 1911 u64 mcg_cap = vcpu->arch.mcg_cap; 1912 unsigned bank_num = mcg_cap & 0xff; 1913 1914 switch (msr) { 1915 case MSR_IA32_MCG_STATUS: 1916 vcpu->arch.mcg_status = data; 1917 break; 1918 case MSR_IA32_MCG_CTL: 1919 if (!(mcg_cap & MCG_CTL_P)) 1920 return 1; 1921 if (data != 0 && data != ~(u64)0) 1922 return -1; 1923 vcpu->arch.mcg_ctl = data; 1924 break; 1925 default: 1926 if (msr >= MSR_IA32_MC0_CTL && 1927 msr < MSR_IA32_MCx_CTL(bank_num)) { 1928 u32 offset = msr - MSR_IA32_MC0_CTL; 1929 /* only 0 or all 1s can be written to IA32_MCi_CTL 1930 * some Linux kernels though clear bit 10 in bank 4 to 1931 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 1932 * this to avoid an uncatched #GP in the guest 1933 */ 1934 if ((offset & 0x3) == 0 && 1935 data != 0 && (data | (1 << 10)) != ~(u64)0) 1936 return -1; 1937 vcpu->arch.mce_banks[offset] = data; 1938 break; 1939 } 1940 return 1; 1941 } 1942 return 0; 1943 } 1944 1945 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 1946 { 1947 struct kvm *kvm = vcpu->kvm; 1948 int lm = is_long_mode(vcpu); 1949 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 1950 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 1951 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 1952 : kvm->arch.xen_hvm_config.blob_size_32; 1953 u32 page_num = data & ~PAGE_MASK; 1954 u64 page_addr = data & PAGE_MASK; 1955 u8 *page; 1956 int r; 1957 1958 r = -E2BIG; 1959 if (page_num >= blob_size) 1960 goto out; 1961 r = -ENOMEM; 1962 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 1963 if (IS_ERR(page)) { 1964 r = PTR_ERR(page); 1965 goto out; 1966 } 1967 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 1968 goto out_free; 1969 r = 0; 1970 out_free: 1971 kfree(page); 1972 out: 1973 return r; 1974 } 1975 1976 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 1977 { 1978 gpa_t gpa = data & ~0x3f; 1979 1980 /* Bits 2:5 are reserved, Should be zero */ 1981 if (data & 0x3c) 1982 return 1; 1983 1984 vcpu->arch.apf.msr_val = data; 1985 1986 if (!(data & KVM_ASYNC_PF_ENABLED)) { 1987 kvm_clear_async_pf_completion_queue(vcpu); 1988 kvm_async_pf_hash_reset(vcpu); 1989 return 0; 1990 } 1991 1992 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 1993 sizeof(u32))) 1994 return 1; 1995 1996 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 1997 kvm_async_pf_wakeup_all(vcpu); 1998 return 0; 1999 } 2000 2001 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2002 { 2003 vcpu->arch.pv_time_enabled = false; 2004 } 2005 2006 static void record_steal_time(struct kvm_vcpu *vcpu) 2007 { 2008 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2009 return; 2010 2011 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2012 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2013 return; 2014 2015 if (vcpu->arch.st.steal.version & 1) 2016 vcpu->arch.st.steal.version += 1; /* first time write, random junk */ 2017 2018 vcpu->arch.st.steal.version += 1; 2019 2020 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2021 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2022 2023 smp_wmb(); 2024 2025 vcpu->arch.st.steal.steal += current->sched_info.run_delay - 2026 vcpu->arch.st.last_steal; 2027 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2028 2029 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2030 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2031 2032 smp_wmb(); 2033 2034 vcpu->arch.st.steal.version += 1; 2035 2036 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2037 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2038 } 2039 2040 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2041 { 2042 bool pr = false; 2043 u32 msr = msr_info->index; 2044 u64 data = msr_info->data; 2045 2046 switch (msr) { 2047 case MSR_AMD64_NB_CFG: 2048 case MSR_IA32_UCODE_REV: 2049 case MSR_IA32_UCODE_WRITE: 2050 case MSR_VM_HSAVE_PA: 2051 case MSR_AMD64_PATCH_LOADER: 2052 case MSR_AMD64_BU_CFG2: 2053 break; 2054 2055 case MSR_EFER: 2056 return set_efer(vcpu, data); 2057 case MSR_K7_HWCR: 2058 data &= ~(u64)0x40; /* ignore flush filter disable */ 2059 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2060 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2061 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2062 if (data != 0) { 2063 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2064 data); 2065 return 1; 2066 } 2067 break; 2068 case MSR_FAM10H_MMIO_CONF_BASE: 2069 if (data != 0) { 2070 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2071 "0x%llx\n", data); 2072 return 1; 2073 } 2074 break; 2075 case MSR_IA32_DEBUGCTLMSR: 2076 if (!data) { 2077 /* We support the non-activated case already */ 2078 break; 2079 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2080 /* Values other than LBR and BTF are vendor-specific, 2081 thus reserved and should throw a #GP */ 2082 return 1; 2083 } 2084 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2085 __func__, data); 2086 break; 2087 case 0x200 ... 0x2ff: 2088 return kvm_mtrr_set_msr(vcpu, msr, data); 2089 case MSR_IA32_APICBASE: 2090 return kvm_set_apic_base(vcpu, msr_info); 2091 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2092 return kvm_x2apic_msr_write(vcpu, msr, data); 2093 case MSR_IA32_TSCDEADLINE: 2094 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2095 break; 2096 case MSR_IA32_TSC_ADJUST: 2097 if (guest_cpuid_has_tsc_adjust(vcpu)) { 2098 if (!msr_info->host_initiated) { 2099 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2100 adjust_tsc_offset_guest(vcpu, adj); 2101 } 2102 vcpu->arch.ia32_tsc_adjust_msr = data; 2103 } 2104 break; 2105 case MSR_IA32_MISC_ENABLE: 2106 vcpu->arch.ia32_misc_enable_msr = data; 2107 break; 2108 case MSR_IA32_SMBASE: 2109 if (!msr_info->host_initiated) 2110 return 1; 2111 vcpu->arch.smbase = data; 2112 break; 2113 case MSR_KVM_WALL_CLOCK_NEW: 2114 case MSR_KVM_WALL_CLOCK: 2115 vcpu->kvm->arch.wall_clock = data; 2116 kvm_write_wall_clock(vcpu->kvm, data); 2117 break; 2118 case MSR_KVM_SYSTEM_TIME_NEW: 2119 case MSR_KVM_SYSTEM_TIME: { 2120 u64 gpa_offset; 2121 struct kvm_arch *ka = &vcpu->kvm->arch; 2122 2123 kvmclock_reset(vcpu); 2124 2125 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2126 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2127 2128 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2129 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, 2130 &vcpu->requests); 2131 2132 ka->boot_vcpu_runs_old_kvmclock = tmp; 2133 } 2134 2135 vcpu->arch.time = data; 2136 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2137 2138 /* we verify if the enable bit is set... */ 2139 if (!(data & 1)) 2140 break; 2141 2142 gpa_offset = data & ~(PAGE_MASK | 1); 2143 2144 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2145 &vcpu->arch.pv_time, data & ~1ULL, 2146 sizeof(struct pvclock_vcpu_time_info))) 2147 vcpu->arch.pv_time_enabled = false; 2148 else 2149 vcpu->arch.pv_time_enabled = true; 2150 2151 break; 2152 } 2153 case MSR_KVM_ASYNC_PF_EN: 2154 if (kvm_pv_enable_async_pf(vcpu, data)) 2155 return 1; 2156 break; 2157 case MSR_KVM_STEAL_TIME: 2158 2159 if (unlikely(!sched_info_on())) 2160 return 1; 2161 2162 if (data & KVM_STEAL_RESERVED_MASK) 2163 return 1; 2164 2165 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2166 data & KVM_STEAL_VALID_BITS, 2167 sizeof(struct kvm_steal_time))) 2168 return 1; 2169 2170 vcpu->arch.st.msr_val = data; 2171 2172 if (!(data & KVM_MSR_ENABLED)) 2173 break; 2174 2175 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2176 2177 break; 2178 case MSR_KVM_PV_EOI_EN: 2179 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2180 return 1; 2181 break; 2182 2183 case MSR_IA32_MCG_CTL: 2184 case MSR_IA32_MCG_STATUS: 2185 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2186 return set_msr_mce(vcpu, msr, data); 2187 2188 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2189 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2190 pr = true; /* fall through */ 2191 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2192 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2193 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2194 return kvm_pmu_set_msr(vcpu, msr_info); 2195 2196 if (pr || data != 0) 2197 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2198 "0x%x data 0x%llx\n", msr, data); 2199 break; 2200 case MSR_K7_CLK_CTL: 2201 /* 2202 * Ignore all writes to this no longer documented MSR. 2203 * Writes are only relevant for old K7 processors, 2204 * all pre-dating SVM, but a recommended workaround from 2205 * AMD for these chips. It is possible to specify the 2206 * affected processor models on the command line, hence 2207 * the need to ignore the workaround. 2208 */ 2209 break; 2210 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2211 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2212 case HV_X64_MSR_CRASH_CTL: 2213 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2214 return kvm_hv_set_msr_common(vcpu, msr, data, 2215 msr_info->host_initiated); 2216 case MSR_IA32_BBL_CR_CTL3: 2217 /* Drop writes to this legacy MSR -- see rdmsr 2218 * counterpart for further detail. 2219 */ 2220 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); 2221 break; 2222 case MSR_AMD64_OSVW_ID_LENGTH: 2223 if (!guest_cpuid_has_osvw(vcpu)) 2224 return 1; 2225 vcpu->arch.osvw.length = data; 2226 break; 2227 case MSR_AMD64_OSVW_STATUS: 2228 if (!guest_cpuid_has_osvw(vcpu)) 2229 return 1; 2230 vcpu->arch.osvw.status = data; 2231 break; 2232 default: 2233 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2234 return xen_hvm_config(vcpu, data); 2235 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2236 return kvm_pmu_set_msr(vcpu, msr_info); 2237 if (!ignore_msrs) { 2238 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", 2239 msr, data); 2240 return 1; 2241 } else { 2242 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", 2243 msr, data); 2244 break; 2245 } 2246 } 2247 return 0; 2248 } 2249 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2250 2251 2252 /* 2253 * Reads an msr value (of 'msr_index') into 'pdata'. 2254 * Returns 0 on success, non-0 otherwise. 2255 * Assumes vcpu_load() was already called. 2256 */ 2257 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 2258 { 2259 return kvm_x86_ops->get_msr(vcpu, msr); 2260 } 2261 EXPORT_SYMBOL_GPL(kvm_get_msr); 2262 2263 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2264 { 2265 u64 data; 2266 u64 mcg_cap = vcpu->arch.mcg_cap; 2267 unsigned bank_num = mcg_cap & 0xff; 2268 2269 switch (msr) { 2270 case MSR_IA32_P5_MC_ADDR: 2271 case MSR_IA32_P5_MC_TYPE: 2272 data = 0; 2273 break; 2274 case MSR_IA32_MCG_CAP: 2275 data = vcpu->arch.mcg_cap; 2276 break; 2277 case MSR_IA32_MCG_CTL: 2278 if (!(mcg_cap & MCG_CTL_P)) 2279 return 1; 2280 data = vcpu->arch.mcg_ctl; 2281 break; 2282 case MSR_IA32_MCG_STATUS: 2283 data = vcpu->arch.mcg_status; 2284 break; 2285 default: 2286 if (msr >= MSR_IA32_MC0_CTL && 2287 msr < MSR_IA32_MCx_CTL(bank_num)) { 2288 u32 offset = msr - MSR_IA32_MC0_CTL; 2289 data = vcpu->arch.mce_banks[offset]; 2290 break; 2291 } 2292 return 1; 2293 } 2294 *pdata = data; 2295 return 0; 2296 } 2297 2298 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2299 { 2300 switch (msr_info->index) { 2301 case MSR_IA32_PLATFORM_ID: 2302 case MSR_IA32_EBL_CR_POWERON: 2303 case MSR_IA32_DEBUGCTLMSR: 2304 case MSR_IA32_LASTBRANCHFROMIP: 2305 case MSR_IA32_LASTBRANCHTOIP: 2306 case MSR_IA32_LASTINTFROMIP: 2307 case MSR_IA32_LASTINTTOIP: 2308 case MSR_K8_SYSCFG: 2309 case MSR_K8_TSEG_ADDR: 2310 case MSR_K8_TSEG_MASK: 2311 case MSR_K7_HWCR: 2312 case MSR_VM_HSAVE_PA: 2313 case MSR_K8_INT_PENDING_MSG: 2314 case MSR_AMD64_NB_CFG: 2315 case MSR_FAM10H_MMIO_CONF_BASE: 2316 case MSR_AMD64_BU_CFG2: 2317 msr_info->data = 0; 2318 break; 2319 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2320 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2321 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2322 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2323 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2324 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2325 msr_info->data = 0; 2326 break; 2327 case MSR_IA32_UCODE_REV: 2328 msr_info->data = 0x100000000ULL; 2329 break; 2330 case MSR_MTRRcap: 2331 case 0x200 ... 0x2ff: 2332 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 2333 case 0xcd: /* fsb frequency */ 2334 msr_info->data = 3; 2335 break; 2336 /* 2337 * MSR_EBC_FREQUENCY_ID 2338 * Conservative value valid for even the basic CPU models. 2339 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2340 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2341 * and 266MHz for model 3, or 4. Set Core Clock 2342 * Frequency to System Bus Frequency Ratio to 1 (bits 2343 * 31:24) even though these are only valid for CPU 2344 * models > 2, however guests may end up dividing or 2345 * multiplying by zero otherwise. 2346 */ 2347 case MSR_EBC_FREQUENCY_ID: 2348 msr_info->data = 1 << 24; 2349 break; 2350 case MSR_IA32_APICBASE: 2351 msr_info->data = kvm_get_apic_base(vcpu); 2352 break; 2353 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2354 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 2355 break; 2356 case MSR_IA32_TSCDEADLINE: 2357 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 2358 break; 2359 case MSR_IA32_TSC_ADJUST: 2360 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2361 break; 2362 case MSR_IA32_MISC_ENABLE: 2363 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 2364 break; 2365 case MSR_IA32_SMBASE: 2366 if (!msr_info->host_initiated) 2367 return 1; 2368 msr_info->data = vcpu->arch.smbase; 2369 break; 2370 case MSR_IA32_PERF_STATUS: 2371 /* TSC increment by tick */ 2372 msr_info->data = 1000ULL; 2373 /* CPU multiplier */ 2374 msr_info->data |= (((uint64_t)4ULL) << 40); 2375 break; 2376 case MSR_EFER: 2377 msr_info->data = vcpu->arch.efer; 2378 break; 2379 case MSR_KVM_WALL_CLOCK: 2380 case MSR_KVM_WALL_CLOCK_NEW: 2381 msr_info->data = vcpu->kvm->arch.wall_clock; 2382 break; 2383 case MSR_KVM_SYSTEM_TIME: 2384 case MSR_KVM_SYSTEM_TIME_NEW: 2385 msr_info->data = vcpu->arch.time; 2386 break; 2387 case MSR_KVM_ASYNC_PF_EN: 2388 msr_info->data = vcpu->arch.apf.msr_val; 2389 break; 2390 case MSR_KVM_STEAL_TIME: 2391 msr_info->data = vcpu->arch.st.msr_val; 2392 break; 2393 case MSR_KVM_PV_EOI_EN: 2394 msr_info->data = vcpu->arch.pv_eoi.msr_val; 2395 break; 2396 case MSR_IA32_P5_MC_ADDR: 2397 case MSR_IA32_P5_MC_TYPE: 2398 case MSR_IA32_MCG_CAP: 2399 case MSR_IA32_MCG_CTL: 2400 case MSR_IA32_MCG_STATUS: 2401 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2402 return get_msr_mce(vcpu, msr_info->index, &msr_info->data); 2403 case MSR_K7_CLK_CTL: 2404 /* 2405 * Provide expected ramp-up count for K7. All other 2406 * are set to zero, indicating minimum divisors for 2407 * every field. 2408 * 2409 * This prevents guest kernels on AMD host with CPU 2410 * type 6, model 8 and higher from exploding due to 2411 * the rdmsr failing. 2412 */ 2413 msr_info->data = 0x20000000; 2414 break; 2415 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2416 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2417 case HV_X64_MSR_CRASH_CTL: 2418 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2419 return kvm_hv_get_msr_common(vcpu, 2420 msr_info->index, &msr_info->data); 2421 break; 2422 case MSR_IA32_BBL_CR_CTL3: 2423 /* This legacy MSR exists but isn't fully documented in current 2424 * silicon. It is however accessed by winxp in very narrow 2425 * scenarios where it sets bit #19, itself documented as 2426 * a "reserved" bit. Best effort attempt to source coherent 2427 * read data here should the balance of the register be 2428 * interpreted by the guest: 2429 * 2430 * L2 cache control register 3: 64GB range, 256KB size, 2431 * enabled, latency 0x1, configured 2432 */ 2433 msr_info->data = 0xbe702111; 2434 break; 2435 case MSR_AMD64_OSVW_ID_LENGTH: 2436 if (!guest_cpuid_has_osvw(vcpu)) 2437 return 1; 2438 msr_info->data = vcpu->arch.osvw.length; 2439 break; 2440 case MSR_AMD64_OSVW_STATUS: 2441 if (!guest_cpuid_has_osvw(vcpu)) 2442 return 1; 2443 msr_info->data = vcpu->arch.osvw.status; 2444 break; 2445 default: 2446 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2447 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2448 if (!ignore_msrs) { 2449 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index); 2450 return 1; 2451 } else { 2452 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index); 2453 msr_info->data = 0; 2454 } 2455 break; 2456 } 2457 return 0; 2458 } 2459 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2460 2461 /* 2462 * Read or write a bunch of msrs. All parameters are kernel addresses. 2463 * 2464 * @return number of msrs set successfully. 2465 */ 2466 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2467 struct kvm_msr_entry *entries, 2468 int (*do_msr)(struct kvm_vcpu *vcpu, 2469 unsigned index, u64 *data)) 2470 { 2471 int i, idx; 2472 2473 idx = srcu_read_lock(&vcpu->kvm->srcu); 2474 for (i = 0; i < msrs->nmsrs; ++i) 2475 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2476 break; 2477 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2478 2479 return i; 2480 } 2481 2482 /* 2483 * Read or write a bunch of msrs. Parameters are user addresses. 2484 * 2485 * @return number of msrs set successfully. 2486 */ 2487 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2488 int (*do_msr)(struct kvm_vcpu *vcpu, 2489 unsigned index, u64 *data), 2490 int writeback) 2491 { 2492 struct kvm_msrs msrs; 2493 struct kvm_msr_entry *entries; 2494 int r, n; 2495 unsigned size; 2496 2497 r = -EFAULT; 2498 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2499 goto out; 2500 2501 r = -E2BIG; 2502 if (msrs.nmsrs >= MAX_IO_MSRS) 2503 goto out; 2504 2505 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2506 entries = memdup_user(user_msrs->entries, size); 2507 if (IS_ERR(entries)) { 2508 r = PTR_ERR(entries); 2509 goto out; 2510 } 2511 2512 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2513 if (r < 0) 2514 goto out_free; 2515 2516 r = -EFAULT; 2517 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2518 goto out_free; 2519 2520 r = n; 2521 2522 out_free: 2523 kfree(entries); 2524 out: 2525 return r; 2526 } 2527 2528 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2529 { 2530 int r; 2531 2532 switch (ext) { 2533 case KVM_CAP_IRQCHIP: 2534 case KVM_CAP_HLT: 2535 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2536 case KVM_CAP_SET_TSS_ADDR: 2537 case KVM_CAP_EXT_CPUID: 2538 case KVM_CAP_EXT_EMUL_CPUID: 2539 case KVM_CAP_CLOCKSOURCE: 2540 case KVM_CAP_PIT: 2541 case KVM_CAP_NOP_IO_DELAY: 2542 case KVM_CAP_MP_STATE: 2543 case KVM_CAP_SYNC_MMU: 2544 case KVM_CAP_USER_NMI: 2545 case KVM_CAP_REINJECT_CONTROL: 2546 case KVM_CAP_IRQ_INJECT_STATUS: 2547 case KVM_CAP_IOEVENTFD: 2548 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2549 case KVM_CAP_PIT2: 2550 case KVM_CAP_PIT_STATE2: 2551 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2552 case KVM_CAP_XEN_HVM: 2553 case KVM_CAP_ADJUST_CLOCK: 2554 case KVM_CAP_VCPU_EVENTS: 2555 case KVM_CAP_HYPERV: 2556 case KVM_CAP_HYPERV_VAPIC: 2557 case KVM_CAP_HYPERV_SPIN: 2558 case KVM_CAP_HYPERV_SYNIC: 2559 case KVM_CAP_PCI_SEGMENT: 2560 case KVM_CAP_DEBUGREGS: 2561 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2562 case KVM_CAP_XSAVE: 2563 case KVM_CAP_ASYNC_PF: 2564 case KVM_CAP_GET_TSC_KHZ: 2565 case KVM_CAP_KVMCLOCK_CTRL: 2566 case KVM_CAP_READONLY_MEM: 2567 case KVM_CAP_HYPERV_TIME: 2568 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2569 case KVM_CAP_TSC_DEADLINE_TIMER: 2570 case KVM_CAP_ENABLE_CAP_VM: 2571 case KVM_CAP_DISABLE_QUIRKS: 2572 case KVM_CAP_SET_BOOT_CPU_ID: 2573 case KVM_CAP_SPLIT_IRQCHIP: 2574 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2575 case KVM_CAP_ASSIGN_DEV_IRQ: 2576 case KVM_CAP_PCI_2_3: 2577 #endif 2578 r = 1; 2579 break; 2580 case KVM_CAP_X86_SMM: 2581 /* SMBASE is usually relocated above 1M on modern chipsets, 2582 * and SMM handlers might indeed rely on 4G segment limits, 2583 * so do not report SMM to be available if real mode is 2584 * emulated via vm86 mode. Still, do not go to great lengths 2585 * to avoid userspace's usage of the feature, because it is a 2586 * fringe case that is not enabled except via specific settings 2587 * of the module parameters. 2588 */ 2589 r = kvm_x86_ops->cpu_has_high_real_mode_segbase(); 2590 break; 2591 case KVM_CAP_COALESCED_MMIO: 2592 r = KVM_COALESCED_MMIO_PAGE_OFFSET; 2593 break; 2594 case KVM_CAP_VAPIC: 2595 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2596 break; 2597 case KVM_CAP_NR_VCPUS: 2598 r = KVM_SOFT_MAX_VCPUS; 2599 break; 2600 case KVM_CAP_MAX_VCPUS: 2601 r = KVM_MAX_VCPUS; 2602 break; 2603 case KVM_CAP_NR_MEMSLOTS: 2604 r = KVM_USER_MEM_SLOTS; 2605 break; 2606 case KVM_CAP_PV_MMU: /* obsolete */ 2607 r = 0; 2608 break; 2609 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2610 case KVM_CAP_IOMMU: 2611 r = iommu_present(&pci_bus_type); 2612 break; 2613 #endif 2614 case KVM_CAP_MCE: 2615 r = KVM_MAX_MCE_BANKS; 2616 break; 2617 case KVM_CAP_XCRS: 2618 r = boot_cpu_has(X86_FEATURE_XSAVE); 2619 break; 2620 case KVM_CAP_TSC_CONTROL: 2621 r = kvm_has_tsc_control; 2622 break; 2623 default: 2624 r = 0; 2625 break; 2626 } 2627 return r; 2628 2629 } 2630 2631 long kvm_arch_dev_ioctl(struct file *filp, 2632 unsigned int ioctl, unsigned long arg) 2633 { 2634 void __user *argp = (void __user *)arg; 2635 long r; 2636 2637 switch (ioctl) { 2638 case KVM_GET_MSR_INDEX_LIST: { 2639 struct kvm_msr_list __user *user_msr_list = argp; 2640 struct kvm_msr_list msr_list; 2641 unsigned n; 2642 2643 r = -EFAULT; 2644 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2645 goto out; 2646 n = msr_list.nmsrs; 2647 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 2648 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2649 goto out; 2650 r = -E2BIG; 2651 if (n < msr_list.nmsrs) 2652 goto out; 2653 r = -EFAULT; 2654 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2655 num_msrs_to_save * sizeof(u32))) 2656 goto out; 2657 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2658 &emulated_msrs, 2659 num_emulated_msrs * sizeof(u32))) 2660 goto out; 2661 r = 0; 2662 break; 2663 } 2664 case KVM_GET_SUPPORTED_CPUID: 2665 case KVM_GET_EMULATED_CPUID: { 2666 struct kvm_cpuid2 __user *cpuid_arg = argp; 2667 struct kvm_cpuid2 cpuid; 2668 2669 r = -EFAULT; 2670 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2671 goto out; 2672 2673 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2674 ioctl); 2675 if (r) 2676 goto out; 2677 2678 r = -EFAULT; 2679 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2680 goto out; 2681 r = 0; 2682 break; 2683 } 2684 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2685 u64 mce_cap; 2686 2687 mce_cap = KVM_MCE_CAP_SUPPORTED; 2688 r = -EFAULT; 2689 if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) 2690 goto out; 2691 r = 0; 2692 break; 2693 } 2694 default: 2695 r = -EINVAL; 2696 } 2697 out: 2698 return r; 2699 } 2700 2701 static void wbinvd_ipi(void *garbage) 2702 { 2703 wbinvd(); 2704 } 2705 2706 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 2707 { 2708 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 2709 } 2710 2711 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu) 2712 { 2713 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests); 2714 } 2715 2716 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 2717 { 2718 /* Address WBINVD may be executed by guest */ 2719 if (need_emulate_wbinvd(vcpu)) { 2720 if (kvm_x86_ops->has_wbinvd_exit()) 2721 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 2722 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 2723 smp_call_function_single(vcpu->cpu, 2724 wbinvd_ipi, NULL, 1); 2725 } 2726 2727 kvm_x86_ops->vcpu_load(vcpu, cpu); 2728 2729 /* Apply any externally detected TSC adjustments (due to suspend) */ 2730 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 2731 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 2732 vcpu->arch.tsc_offset_adjustment = 0; 2733 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2734 } 2735 2736 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { 2737 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 2738 rdtsc() - vcpu->arch.last_host_tsc; 2739 if (tsc_delta < 0) 2740 mark_tsc_unstable("KVM discovered backwards TSC"); 2741 if (check_tsc_unstable()) { 2742 u64 offset = kvm_compute_tsc_offset(vcpu, 2743 vcpu->arch.last_guest_tsc); 2744 kvm_x86_ops->write_tsc_offset(vcpu, offset); 2745 vcpu->arch.tsc_catchup = 1; 2746 } 2747 /* 2748 * On a host with synchronized TSC, there is no need to update 2749 * kvmclock on vcpu->cpu migration 2750 */ 2751 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 2752 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2753 if (vcpu->cpu != cpu) 2754 kvm_migrate_timers(vcpu); 2755 vcpu->cpu = cpu; 2756 } 2757 2758 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2759 } 2760 2761 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 2762 { 2763 kvm_x86_ops->vcpu_put(vcpu); 2764 kvm_put_guest_fpu(vcpu); 2765 vcpu->arch.last_host_tsc = rdtsc(); 2766 } 2767 2768 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 2769 struct kvm_lapic_state *s) 2770 { 2771 if (vcpu->arch.apicv_active) 2772 kvm_x86_ops->sync_pir_to_irr(vcpu); 2773 2774 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); 2775 2776 return 0; 2777 } 2778 2779 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 2780 struct kvm_lapic_state *s) 2781 { 2782 kvm_apic_post_state_restore(vcpu, s); 2783 update_cr8_intercept(vcpu); 2784 2785 return 0; 2786 } 2787 2788 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 2789 { 2790 return (!lapic_in_kernel(vcpu) || 2791 kvm_apic_accept_pic_intr(vcpu)); 2792 } 2793 2794 /* 2795 * if userspace requested an interrupt window, check that the 2796 * interrupt window is open. 2797 * 2798 * No need to exit to userspace if we already have an interrupt queued. 2799 */ 2800 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 2801 { 2802 return kvm_arch_interrupt_allowed(vcpu) && 2803 !kvm_cpu_has_interrupt(vcpu) && 2804 !kvm_event_needs_reinjection(vcpu) && 2805 kvm_cpu_accept_dm_intr(vcpu); 2806 } 2807 2808 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 2809 struct kvm_interrupt *irq) 2810 { 2811 if (irq->irq >= KVM_NR_INTERRUPTS) 2812 return -EINVAL; 2813 2814 if (!irqchip_in_kernel(vcpu->kvm)) { 2815 kvm_queue_interrupt(vcpu, irq->irq, false); 2816 kvm_make_request(KVM_REQ_EVENT, vcpu); 2817 return 0; 2818 } 2819 2820 /* 2821 * With in-kernel LAPIC, we only use this to inject EXTINT, so 2822 * fail for in-kernel 8259. 2823 */ 2824 if (pic_in_kernel(vcpu->kvm)) 2825 return -ENXIO; 2826 2827 if (vcpu->arch.pending_external_vector != -1) 2828 return -EEXIST; 2829 2830 vcpu->arch.pending_external_vector = irq->irq; 2831 kvm_make_request(KVM_REQ_EVENT, vcpu); 2832 return 0; 2833 } 2834 2835 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 2836 { 2837 kvm_inject_nmi(vcpu); 2838 2839 return 0; 2840 } 2841 2842 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 2843 { 2844 kvm_make_request(KVM_REQ_SMI, vcpu); 2845 2846 return 0; 2847 } 2848 2849 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 2850 struct kvm_tpr_access_ctl *tac) 2851 { 2852 if (tac->flags) 2853 return -EINVAL; 2854 vcpu->arch.tpr_access_reporting = !!tac->enabled; 2855 return 0; 2856 } 2857 2858 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 2859 u64 mcg_cap) 2860 { 2861 int r; 2862 unsigned bank_num = mcg_cap & 0xff, bank; 2863 2864 r = -EINVAL; 2865 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 2866 goto out; 2867 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) 2868 goto out; 2869 r = 0; 2870 vcpu->arch.mcg_cap = mcg_cap; 2871 /* Init IA32_MCG_CTL to all 1s */ 2872 if (mcg_cap & MCG_CTL_P) 2873 vcpu->arch.mcg_ctl = ~(u64)0; 2874 /* Init IA32_MCi_CTL to all 1s */ 2875 for (bank = 0; bank < bank_num; bank++) 2876 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 2877 out: 2878 return r; 2879 } 2880 2881 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 2882 struct kvm_x86_mce *mce) 2883 { 2884 u64 mcg_cap = vcpu->arch.mcg_cap; 2885 unsigned bank_num = mcg_cap & 0xff; 2886 u64 *banks = vcpu->arch.mce_banks; 2887 2888 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 2889 return -EINVAL; 2890 /* 2891 * if IA32_MCG_CTL is not all 1s, the uncorrected error 2892 * reporting is disabled 2893 */ 2894 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 2895 vcpu->arch.mcg_ctl != ~(u64)0) 2896 return 0; 2897 banks += 4 * mce->bank; 2898 /* 2899 * if IA32_MCi_CTL is not all 1s, the uncorrected error 2900 * reporting is disabled for the bank 2901 */ 2902 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 2903 return 0; 2904 if (mce->status & MCI_STATUS_UC) { 2905 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 2906 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 2907 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 2908 return 0; 2909 } 2910 if (banks[1] & MCI_STATUS_VAL) 2911 mce->status |= MCI_STATUS_OVER; 2912 banks[2] = mce->addr; 2913 banks[3] = mce->misc; 2914 vcpu->arch.mcg_status = mce->mcg_status; 2915 banks[1] = mce->status; 2916 kvm_queue_exception(vcpu, MC_VECTOR); 2917 } else if (!(banks[1] & MCI_STATUS_VAL) 2918 || !(banks[1] & MCI_STATUS_UC)) { 2919 if (banks[1] & MCI_STATUS_VAL) 2920 mce->status |= MCI_STATUS_OVER; 2921 banks[2] = mce->addr; 2922 banks[3] = mce->misc; 2923 banks[1] = mce->status; 2924 } else 2925 banks[1] |= MCI_STATUS_OVER; 2926 return 0; 2927 } 2928 2929 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 2930 struct kvm_vcpu_events *events) 2931 { 2932 process_nmi(vcpu); 2933 events->exception.injected = 2934 vcpu->arch.exception.pending && 2935 !kvm_exception_is_soft(vcpu->arch.exception.nr); 2936 events->exception.nr = vcpu->arch.exception.nr; 2937 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 2938 events->exception.pad = 0; 2939 events->exception.error_code = vcpu->arch.exception.error_code; 2940 2941 events->interrupt.injected = 2942 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; 2943 events->interrupt.nr = vcpu->arch.interrupt.nr; 2944 events->interrupt.soft = 0; 2945 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 2946 2947 events->nmi.injected = vcpu->arch.nmi_injected; 2948 events->nmi.pending = vcpu->arch.nmi_pending != 0; 2949 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 2950 events->nmi.pad = 0; 2951 2952 events->sipi_vector = 0; /* never valid when reporting to user space */ 2953 2954 events->smi.smm = is_smm(vcpu); 2955 events->smi.pending = vcpu->arch.smi_pending; 2956 events->smi.smm_inside_nmi = 2957 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 2958 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 2959 2960 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 2961 | KVM_VCPUEVENT_VALID_SHADOW 2962 | KVM_VCPUEVENT_VALID_SMM); 2963 memset(&events->reserved, 0, sizeof(events->reserved)); 2964 } 2965 2966 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 2967 struct kvm_vcpu_events *events) 2968 { 2969 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 2970 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 2971 | KVM_VCPUEVENT_VALID_SHADOW 2972 | KVM_VCPUEVENT_VALID_SMM)) 2973 return -EINVAL; 2974 2975 process_nmi(vcpu); 2976 vcpu->arch.exception.pending = events->exception.injected; 2977 vcpu->arch.exception.nr = events->exception.nr; 2978 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 2979 vcpu->arch.exception.error_code = events->exception.error_code; 2980 2981 vcpu->arch.interrupt.pending = events->interrupt.injected; 2982 vcpu->arch.interrupt.nr = events->interrupt.nr; 2983 vcpu->arch.interrupt.soft = events->interrupt.soft; 2984 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 2985 kvm_x86_ops->set_interrupt_shadow(vcpu, 2986 events->interrupt.shadow); 2987 2988 vcpu->arch.nmi_injected = events->nmi.injected; 2989 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 2990 vcpu->arch.nmi_pending = events->nmi.pending; 2991 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 2992 2993 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 2994 lapic_in_kernel(vcpu)) 2995 vcpu->arch.apic->sipi_vector = events->sipi_vector; 2996 2997 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 2998 if (events->smi.smm) 2999 vcpu->arch.hflags |= HF_SMM_MASK; 3000 else 3001 vcpu->arch.hflags &= ~HF_SMM_MASK; 3002 vcpu->arch.smi_pending = events->smi.pending; 3003 if (events->smi.smm_inside_nmi) 3004 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 3005 else 3006 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 3007 if (lapic_in_kernel(vcpu)) { 3008 if (events->smi.latched_init) 3009 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3010 else 3011 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3012 } 3013 } 3014 3015 kvm_make_request(KVM_REQ_EVENT, vcpu); 3016 3017 return 0; 3018 } 3019 3020 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3021 struct kvm_debugregs *dbgregs) 3022 { 3023 unsigned long val; 3024 3025 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3026 kvm_get_dr(vcpu, 6, &val); 3027 dbgregs->dr6 = val; 3028 dbgregs->dr7 = vcpu->arch.dr7; 3029 dbgregs->flags = 0; 3030 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3031 } 3032 3033 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3034 struct kvm_debugregs *dbgregs) 3035 { 3036 if (dbgregs->flags) 3037 return -EINVAL; 3038 3039 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3040 kvm_update_dr0123(vcpu); 3041 vcpu->arch.dr6 = dbgregs->dr6; 3042 kvm_update_dr6(vcpu); 3043 vcpu->arch.dr7 = dbgregs->dr7; 3044 kvm_update_dr7(vcpu); 3045 3046 return 0; 3047 } 3048 3049 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3050 3051 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3052 { 3053 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3054 u64 xstate_bv = xsave->header.xfeatures; 3055 u64 valid; 3056 3057 /* 3058 * Copy legacy XSAVE area, to avoid complications with CPUID 3059 * leaves 0 and 1 in the loop below. 3060 */ 3061 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3062 3063 /* Set XSTATE_BV */ 3064 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3065 3066 /* 3067 * Copy each region from the possibly compacted offset to the 3068 * non-compacted offset. 3069 */ 3070 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3071 while (valid) { 3072 u64 feature = valid & -valid; 3073 int index = fls64(feature) - 1; 3074 void *src = get_xsave_addr(xsave, feature); 3075 3076 if (src) { 3077 u32 size, offset, ecx, edx; 3078 cpuid_count(XSTATE_CPUID, index, 3079 &size, &offset, &ecx, &edx); 3080 memcpy(dest + offset, src, size); 3081 } 3082 3083 valid -= feature; 3084 } 3085 } 3086 3087 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3088 { 3089 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3090 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3091 u64 valid; 3092 3093 /* 3094 * Copy legacy XSAVE area, to avoid complications with CPUID 3095 * leaves 0 and 1 in the loop below. 3096 */ 3097 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3098 3099 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3100 xsave->header.xfeatures = xstate_bv; 3101 if (boot_cpu_has(X86_FEATURE_XSAVES)) 3102 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3103 3104 /* 3105 * Copy each region from the non-compacted offset to the 3106 * possibly compacted offset. 3107 */ 3108 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3109 while (valid) { 3110 u64 feature = valid & -valid; 3111 int index = fls64(feature) - 1; 3112 void *dest = get_xsave_addr(xsave, feature); 3113 3114 if (dest) { 3115 u32 size, offset, ecx, edx; 3116 cpuid_count(XSTATE_CPUID, index, 3117 &size, &offset, &ecx, &edx); 3118 memcpy(dest, src + offset, size); 3119 } 3120 3121 valid -= feature; 3122 } 3123 } 3124 3125 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3126 struct kvm_xsave *guest_xsave) 3127 { 3128 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3129 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3130 fill_xsave((u8 *) guest_xsave->region, vcpu); 3131 } else { 3132 memcpy(guest_xsave->region, 3133 &vcpu->arch.guest_fpu.state.fxsave, 3134 sizeof(struct fxregs_state)); 3135 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3136 XFEATURE_MASK_FPSSE; 3137 } 3138 } 3139 3140 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3141 struct kvm_xsave *guest_xsave) 3142 { 3143 u64 xstate_bv = 3144 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3145 3146 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3147 /* 3148 * Here we allow setting states that are not present in 3149 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3150 * with old userspace. 3151 */ 3152 if (xstate_bv & ~kvm_supported_xcr0()) 3153 return -EINVAL; 3154 load_xsave(vcpu, (u8 *)guest_xsave->region); 3155 } else { 3156 if (xstate_bv & ~XFEATURE_MASK_FPSSE) 3157 return -EINVAL; 3158 memcpy(&vcpu->arch.guest_fpu.state.fxsave, 3159 guest_xsave->region, sizeof(struct fxregs_state)); 3160 } 3161 return 0; 3162 } 3163 3164 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3165 struct kvm_xcrs *guest_xcrs) 3166 { 3167 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 3168 guest_xcrs->nr_xcrs = 0; 3169 return; 3170 } 3171 3172 guest_xcrs->nr_xcrs = 1; 3173 guest_xcrs->flags = 0; 3174 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3175 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3176 } 3177 3178 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3179 struct kvm_xcrs *guest_xcrs) 3180 { 3181 int i, r = 0; 3182 3183 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 3184 return -EINVAL; 3185 3186 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3187 return -EINVAL; 3188 3189 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3190 /* Only support XCR0 currently */ 3191 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3192 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3193 guest_xcrs->xcrs[i].value); 3194 break; 3195 } 3196 if (r) 3197 r = -EINVAL; 3198 return r; 3199 } 3200 3201 /* 3202 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3203 * stopped by the hypervisor. This function will be called from the host only. 3204 * EINVAL is returned when the host attempts to set the flag for a guest that 3205 * does not support pv clocks. 3206 */ 3207 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3208 { 3209 if (!vcpu->arch.pv_time_enabled) 3210 return -EINVAL; 3211 vcpu->arch.pvclock_set_guest_stopped_request = true; 3212 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3213 return 0; 3214 } 3215 3216 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 3217 struct kvm_enable_cap *cap) 3218 { 3219 if (cap->flags) 3220 return -EINVAL; 3221 3222 switch (cap->cap) { 3223 case KVM_CAP_HYPERV_SYNIC: 3224 return kvm_hv_activate_synic(vcpu); 3225 default: 3226 return -EINVAL; 3227 } 3228 } 3229 3230 long kvm_arch_vcpu_ioctl(struct file *filp, 3231 unsigned int ioctl, unsigned long arg) 3232 { 3233 struct kvm_vcpu *vcpu = filp->private_data; 3234 void __user *argp = (void __user *)arg; 3235 int r; 3236 union { 3237 struct kvm_lapic_state *lapic; 3238 struct kvm_xsave *xsave; 3239 struct kvm_xcrs *xcrs; 3240 void *buffer; 3241 } u; 3242 3243 u.buffer = NULL; 3244 switch (ioctl) { 3245 case KVM_GET_LAPIC: { 3246 r = -EINVAL; 3247 if (!lapic_in_kernel(vcpu)) 3248 goto out; 3249 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3250 3251 r = -ENOMEM; 3252 if (!u.lapic) 3253 goto out; 3254 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3255 if (r) 3256 goto out; 3257 r = -EFAULT; 3258 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3259 goto out; 3260 r = 0; 3261 break; 3262 } 3263 case KVM_SET_LAPIC: { 3264 r = -EINVAL; 3265 if (!lapic_in_kernel(vcpu)) 3266 goto out; 3267 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3268 if (IS_ERR(u.lapic)) 3269 return PTR_ERR(u.lapic); 3270 3271 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3272 break; 3273 } 3274 case KVM_INTERRUPT: { 3275 struct kvm_interrupt irq; 3276 3277 r = -EFAULT; 3278 if (copy_from_user(&irq, argp, sizeof irq)) 3279 goto out; 3280 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3281 break; 3282 } 3283 case KVM_NMI: { 3284 r = kvm_vcpu_ioctl_nmi(vcpu); 3285 break; 3286 } 3287 case KVM_SMI: { 3288 r = kvm_vcpu_ioctl_smi(vcpu); 3289 break; 3290 } 3291 case KVM_SET_CPUID: { 3292 struct kvm_cpuid __user *cpuid_arg = argp; 3293 struct kvm_cpuid cpuid; 3294 3295 r = -EFAULT; 3296 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3297 goto out; 3298 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3299 break; 3300 } 3301 case KVM_SET_CPUID2: { 3302 struct kvm_cpuid2 __user *cpuid_arg = argp; 3303 struct kvm_cpuid2 cpuid; 3304 3305 r = -EFAULT; 3306 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3307 goto out; 3308 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3309 cpuid_arg->entries); 3310 break; 3311 } 3312 case KVM_GET_CPUID2: { 3313 struct kvm_cpuid2 __user *cpuid_arg = argp; 3314 struct kvm_cpuid2 cpuid; 3315 3316 r = -EFAULT; 3317 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3318 goto out; 3319 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3320 cpuid_arg->entries); 3321 if (r) 3322 goto out; 3323 r = -EFAULT; 3324 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3325 goto out; 3326 r = 0; 3327 break; 3328 } 3329 case KVM_GET_MSRS: 3330 r = msr_io(vcpu, argp, do_get_msr, 1); 3331 break; 3332 case KVM_SET_MSRS: 3333 r = msr_io(vcpu, argp, do_set_msr, 0); 3334 break; 3335 case KVM_TPR_ACCESS_REPORTING: { 3336 struct kvm_tpr_access_ctl tac; 3337 3338 r = -EFAULT; 3339 if (copy_from_user(&tac, argp, sizeof tac)) 3340 goto out; 3341 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3342 if (r) 3343 goto out; 3344 r = -EFAULT; 3345 if (copy_to_user(argp, &tac, sizeof tac)) 3346 goto out; 3347 r = 0; 3348 break; 3349 }; 3350 case KVM_SET_VAPIC_ADDR: { 3351 struct kvm_vapic_addr va; 3352 3353 r = -EINVAL; 3354 if (!lapic_in_kernel(vcpu)) 3355 goto out; 3356 r = -EFAULT; 3357 if (copy_from_user(&va, argp, sizeof va)) 3358 goto out; 3359 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3360 break; 3361 } 3362 case KVM_X86_SETUP_MCE: { 3363 u64 mcg_cap; 3364 3365 r = -EFAULT; 3366 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3367 goto out; 3368 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3369 break; 3370 } 3371 case KVM_X86_SET_MCE: { 3372 struct kvm_x86_mce mce; 3373 3374 r = -EFAULT; 3375 if (copy_from_user(&mce, argp, sizeof mce)) 3376 goto out; 3377 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3378 break; 3379 } 3380 case KVM_GET_VCPU_EVENTS: { 3381 struct kvm_vcpu_events events; 3382 3383 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3384 3385 r = -EFAULT; 3386 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3387 break; 3388 r = 0; 3389 break; 3390 } 3391 case KVM_SET_VCPU_EVENTS: { 3392 struct kvm_vcpu_events events; 3393 3394 r = -EFAULT; 3395 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3396 break; 3397 3398 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3399 break; 3400 } 3401 case KVM_GET_DEBUGREGS: { 3402 struct kvm_debugregs dbgregs; 3403 3404 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3405 3406 r = -EFAULT; 3407 if (copy_to_user(argp, &dbgregs, 3408 sizeof(struct kvm_debugregs))) 3409 break; 3410 r = 0; 3411 break; 3412 } 3413 case KVM_SET_DEBUGREGS: { 3414 struct kvm_debugregs dbgregs; 3415 3416 r = -EFAULT; 3417 if (copy_from_user(&dbgregs, argp, 3418 sizeof(struct kvm_debugregs))) 3419 break; 3420 3421 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3422 break; 3423 } 3424 case KVM_GET_XSAVE: { 3425 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3426 r = -ENOMEM; 3427 if (!u.xsave) 3428 break; 3429 3430 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3431 3432 r = -EFAULT; 3433 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3434 break; 3435 r = 0; 3436 break; 3437 } 3438 case KVM_SET_XSAVE: { 3439 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3440 if (IS_ERR(u.xsave)) 3441 return PTR_ERR(u.xsave); 3442 3443 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3444 break; 3445 } 3446 case KVM_GET_XCRS: { 3447 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3448 r = -ENOMEM; 3449 if (!u.xcrs) 3450 break; 3451 3452 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3453 3454 r = -EFAULT; 3455 if (copy_to_user(argp, u.xcrs, 3456 sizeof(struct kvm_xcrs))) 3457 break; 3458 r = 0; 3459 break; 3460 } 3461 case KVM_SET_XCRS: { 3462 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3463 if (IS_ERR(u.xcrs)) 3464 return PTR_ERR(u.xcrs); 3465 3466 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3467 break; 3468 } 3469 case KVM_SET_TSC_KHZ: { 3470 u32 user_tsc_khz; 3471 3472 r = -EINVAL; 3473 user_tsc_khz = (u32)arg; 3474 3475 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3476 goto out; 3477 3478 if (user_tsc_khz == 0) 3479 user_tsc_khz = tsc_khz; 3480 3481 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 3482 r = 0; 3483 3484 goto out; 3485 } 3486 case KVM_GET_TSC_KHZ: { 3487 r = vcpu->arch.virtual_tsc_khz; 3488 goto out; 3489 } 3490 case KVM_KVMCLOCK_CTRL: { 3491 r = kvm_set_guest_paused(vcpu); 3492 goto out; 3493 } 3494 case KVM_ENABLE_CAP: { 3495 struct kvm_enable_cap cap; 3496 3497 r = -EFAULT; 3498 if (copy_from_user(&cap, argp, sizeof(cap))) 3499 goto out; 3500 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 3501 break; 3502 } 3503 default: 3504 r = -EINVAL; 3505 } 3506 out: 3507 kfree(u.buffer); 3508 return r; 3509 } 3510 3511 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3512 { 3513 return VM_FAULT_SIGBUS; 3514 } 3515 3516 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3517 { 3518 int ret; 3519 3520 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3521 return -EINVAL; 3522 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3523 return ret; 3524 } 3525 3526 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3527 u64 ident_addr) 3528 { 3529 kvm->arch.ept_identity_map_addr = ident_addr; 3530 return 0; 3531 } 3532 3533 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3534 u32 kvm_nr_mmu_pages) 3535 { 3536 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3537 return -EINVAL; 3538 3539 mutex_lock(&kvm->slots_lock); 3540 3541 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3542 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3543 3544 mutex_unlock(&kvm->slots_lock); 3545 return 0; 3546 } 3547 3548 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 3549 { 3550 return kvm->arch.n_max_mmu_pages; 3551 } 3552 3553 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3554 { 3555 int r; 3556 3557 r = 0; 3558 switch (chip->chip_id) { 3559 case KVM_IRQCHIP_PIC_MASTER: 3560 memcpy(&chip->chip.pic, 3561 &pic_irqchip(kvm)->pics[0], 3562 sizeof(struct kvm_pic_state)); 3563 break; 3564 case KVM_IRQCHIP_PIC_SLAVE: 3565 memcpy(&chip->chip.pic, 3566 &pic_irqchip(kvm)->pics[1], 3567 sizeof(struct kvm_pic_state)); 3568 break; 3569 case KVM_IRQCHIP_IOAPIC: 3570 r = kvm_get_ioapic(kvm, &chip->chip.ioapic); 3571 break; 3572 default: 3573 r = -EINVAL; 3574 break; 3575 } 3576 return r; 3577 } 3578 3579 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3580 { 3581 int r; 3582 3583 r = 0; 3584 switch (chip->chip_id) { 3585 case KVM_IRQCHIP_PIC_MASTER: 3586 spin_lock(&pic_irqchip(kvm)->lock); 3587 memcpy(&pic_irqchip(kvm)->pics[0], 3588 &chip->chip.pic, 3589 sizeof(struct kvm_pic_state)); 3590 spin_unlock(&pic_irqchip(kvm)->lock); 3591 break; 3592 case KVM_IRQCHIP_PIC_SLAVE: 3593 spin_lock(&pic_irqchip(kvm)->lock); 3594 memcpy(&pic_irqchip(kvm)->pics[1], 3595 &chip->chip.pic, 3596 sizeof(struct kvm_pic_state)); 3597 spin_unlock(&pic_irqchip(kvm)->lock); 3598 break; 3599 case KVM_IRQCHIP_IOAPIC: 3600 r = kvm_set_ioapic(kvm, &chip->chip.ioapic); 3601 break; 3602 default: 3603 r = -EINVAL; 3604 break; 3605 } 3606 kvm_pic_update_irq(pic_irqchip(kvm)); 3607 return r; 3608 } 3609 3610 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3611 { 3612 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 3613 3614 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 3615 3616 mutex_lock(&kps->lock); 3617 memcpy(ps, &kps->channels, sizeof(*ps)); 3618 mutex_unlock(&kps->lock); 3619 return 0; 3620 } 3621 3622 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3623 { 3624 int i; 3625 struct kvm_pit *pit = kvm->arch.vpit; 3626 3627 mutex_lock(&pit->pit_state.lock); 3628 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 3629 for (i = 0; i < 3; i++) 3630 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 3631 mutex_unlock(&pit->pit_state.lock); 3632 return 0; 3633 } 3634 3635 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3636 { 3637 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3638 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 3639 sizeof(ps->channels)); 3640 ps->flags = kvm->arch.vpit->pit_state.flags; 3641 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3642 memset(&ps->reserved, 0, sizeof(ps->reserved)); 3643 return 0; 3644 } 3645 3646 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3647 { 3648 int start = 0; 3649 int i; 3650 u32 prev_legacy, cur_legacy; 3651 struct kvm_pit *pit = kvm->arch.vpit; 3652 3653 mutex_lock(&pit->pit_state.lock); 3654 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 3655 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 3656 if (!prev_legacy && cur_legacy) 3657 start = 1; 3658 memcpy(&pit->pit_state.channels, &ps->channels, 3659 sizeof(pit->pit_state.channels)); 3660 pit->pit_state.flags = ps->flags; 3661 for (i = 0; i < 3; i++) 3662 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 3663 start && i == 0); 3664 mutex_unlock(&pit->pit_state.lock); 3665 return 0; 3666 } 3667 3668 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 3669 struct kvm_reinject_control *control) 3670 { 3671 struct kvm_pit *pit = kvm->arch.vpit; 3672 3673 if (!pit) 3674 return -ENXIO; 3675 3676 /* pit->pit_state.lock was overloaded to prevent userspace from getting 3677 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 3678 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 3679 */ 3680 mutex_lock(&pit->pit_state.lock); 3681 kvm_pit_set_reinject(pit, control->pit_reinject); 3682 mutex_unlock(&pit->pit_state.lock); 3683 3684 return 0; 3685 } 3686 3687 /** 3688 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 3689 * @kvm: kvm instance 3690 * @log: slot id and address to which we copy the log 3691 * 3692 * Steps 1-4 below provide general overview of dirty page logging. See 3693 * kvm_get_dirty_log_protect() function description for additional details. 3694 * 3695 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 3696 * always flush the TLB (step 4) even if previous step failed and the dirty 3697 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 3698 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 3699 * writes will be marked dirty for next log read. 3700 * 3701 * 1. Take a snapshot of the bit and clear it if needed. 3702 * 2. Write protect the corresponding page. 3703 * 3. Copy the snapshot to the userspace. 3704 * 4. Flush TLB's if needed. 3705 */ 3706 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 3707 { 3708 bool is_dirty = false; 3709 int r; 3710 3711 mutex_lock(&kvm->slots_lock); 3712 3713 /* 3714 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 3715 */ 3716 if (kvm_x86_ops->flush_log_dirty) 3717 kvm_x86_ops->flush_log_dirty(kvm); 3718 3719 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 3720 3721 /* 3722 * All the TLBs can be flushed out of mmu lock, see the comments in 3723 * kvm_mmu_slot_remove_write_access(). 3724 */ 3725 lockdep_assert_held(&kvm->slots_lock); 3726 if (is_dirty) 3727 kvm_flush_remote_tlbs(kvm); 3728 3729 mutex_unlock(&kvm->slots_lock); 3730 return r; 3731 } 3732 3733 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 3734 bool line_status) 3735 { 3736 if (!irqchip_in_kernel(kvm)) 3737 return -ENXIO; 3738 3739 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 3740 irq_event->irq, irq_event->level, 3741 line_status); 3742 return 0; 3743 } 3744 3745 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 3746 struct kvm_enable_cap *cap) 3747 { 3748 int r; 3749 3750 if (cap->flags) 3751 return -EINVAL; 3752 3753 switch (cap->cap) { 3754 case KVM_CAP_DISABLE_QUIRKS: 3755 kvm->arch.disabled_quirks = cap->args[0]; 3756 r = 0; 3757 break; 3758 case KVM_CAP_SPLIT_IRQCHIP: { 3759 mutex_lock(&kvm->lock); 3760 r = -EINVAL; 3761 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 3762 goto split_irqchip_unlock; 3763 r = -EEXIST; 3764 if (irqchip_in_kernel(kvm)) 3765 goto split_irqchip_unlock; 3766 if (atomic_read(&kvm->online_vcpus)) 3767 goto split_irqchip_unlock; 3768 r = kvm_setup_empty_irq_routing(kvm); 3769 if (r) 3770 goto split_irqchip_unlock; 3771 /* Pairs with irqchip_in_kernel. */ 3772 smp_wmb(); 3773 kvm->arch.irqchip_split = true; 3774 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 3775 r = 0; 3776 split_irqchip_unlock: 3777 mutex_unlock(&kvm->lock); 3778 break; 3779 } 3780 default: 3781 r = -EINVAL; 3782 break; 3783 } 3784 return r; 3785 } 3786 3787 long kvm_arch_vm_ioctl(struct file *filp, 3788 unsigned int ioctl, unsigned long arg) 3789 { 3790 struct kvm *kvm = filp->private_data; 3791 void __user *argp = (void __user *)arg; 3792 int r = -ENOTTY; 3793 /* 3794 * This union makes it completely explicit to gcc-3.x 3795 * that these two variables' stack usage should be 3796 * combined, not added together. 3797 */ 3798 union { 3799 struct kvm_pit_state ps; 3800 struct kvm_pit_state2 ps2; 3801 struct kvm_pit_config pit_config; 3802 } u; 3803 3804 switch (ioctl) { 3805 case KVM_SET_TSS_ADDR: 3806 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 3807 break; 3808 case KVM_SET_IDENTITY_MAP_ADDR: { 3809 u64 ident_addr; 3810 3811 r = -EFAULT; 3812 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 3813 goto out; 3814 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 3815 break; 3816 } 3817 case KVM_SET_NR_MMU_PAGES: 3818 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 3819 break; 3820 case KVM_GET_NR_MMU_PAGES: 3821 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 3822 break; 3823 case KVM_CREATE_IRQCHIP: { 3824 struct kvm_pic *vpic; 3825 3826 mutex_lock(&kvm->lock); 3827 r = -EEXIST; 3828 if (kvm->arch.vpic) 3829 goto create_irqchip_unlock; 3830 r = -EINVAL; 3831 if (atomic_read(&kvm->online_vcpus)) 3832 goto create_irqchip_unlock; 3833 r = -ENOMEM; 3834 vpic = kvm_create_pic(kvm); 3835 if (vpic) { 3836 r = kvm_ioapic_init(kvm); 3837 if (r) { 3838 mutex_lock(&kvm->slots_lock); 3839 kvm_destroy_pic(vpic); 3840 mutex_unlock(&kvm->slots_lock); 3841 goto create_irqchip_unlock; 3842 } 3843 } else 3844 goto create_irqchip_unlock; 3845 r = kvm_setup_default_irq_routing(kvm); 3846 if (r) { 3847 mutex_lock(&kvm->slots_lock); 3848 mutex_lock(&kvm->irq_lock); 3849 kvm_ioapic_destroy(kvm); 3850 kvm_destroy_pic(vpic); 3851 mutex_unlock(&kvm->irq_lock); 3852 mutex_unlock(&kvm->slots_lock); 3853 goto create_irqchip_unlock; 3854 } 3855 /* Write kvm->irq_routing before kvm->arch.vpic. */ 3856 smp_wmb(); 3857 kvm->arch.vpic = vpic; 3858 create_irqchip_unlock: 3859 mutex_unlock(&kvm->lock); 3860 break; 3861 } 3862 case KVM_CREATE_PIT: 3863 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 3864 goto create_pit; 3865 case KVM_CREATE_PIT2: 3866 r = -EFAULT; 3867 if (copy_from_user(&u.pit_config, argp, 3868 sizeof(struct kvm_pit_config))) 3869 goto out; 3870 create_pit: 3871 mutex_lock(&kvm->slots_lock); 3872 r = -EEXIST; 3873 if (kvm->arch.vpit) 3874 goto create_pit_unlock; 3875 r = -ENOMEM; 3876 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 3877 if (kvm->arch.vpit) 3878 r = 0; 3879 create_pit_unlock: 3880 mutex_unlock(&kvm->slots_lock); 3881 break; 3882 case KVM_GET_IRQCHIP: { 3883 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3884 struct kvm_irqchip *chip; 3885 3886 chip = memdup_user(argp, sizeof(*chip)); 3887 if (IS_ERR(chip)) { 3888 r = PTR_ERR(chip); 3889 goto out; 3890 } 3891 3892 r = -ENXIO; 3893 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm)) 3894 goto get_irqchip_out; 3895 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 3896 if (r) 3897 goto get_irqchip_out; 3898 r = -EFAULT; 3899 if (copy_to_user(argp, chip, sizeof *chip)) 3900 goto get_irqchip_out; 3901 r = 0; 3902 get_irqchip_out: 3903 kfree(chip); 3904 break; 3905 } 3906 case KVM_SET_IRQCHIP: { 3907 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3908 struct kvm_irqchip *chip; 3909 3910 chip = memdup_user(argp, sizeof(*chip)); 3911 if (IS_ERR(chip)) { 3912 r = PTR_ERR(chip); 3913 goto out; 3914 } 3915 3916 r = -ENXIO; 3917 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm)) 3918 goto set_irqchip_out; 3919 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 3920 if (r) 3921 goto set_irqchip_out; 3922 r = 0; 3923 set_irqchip_out: 3924 kfree(chip); 3925 break; 3926 } 3927 case KVM_GET_PIT: { 3928 r = -EFAULT; 3929 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 3930 goto out; 3931 r = -ENXIO; 3932 if (!kvm->arch.vpit) 3933 goto out; 3934 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 3935 if (r) 3936 goto out; 3937 r = -EFAULT; 3938 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 3939 goto out; 3940 r = 0; 3941 break; 3942 } 3943 case KVM_SET_PIT: { 3944 r = -EFAULT; 3945 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 3946 goto out; 3947 r = -ENXIO; 3948 if (!kvm->arch.vpit) 3949 goto out; 3950 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 3951 break; 3952 } 3953 case KVM_GET_PIT2: { 3954 r = -ENXIO; 3955 if (!kvm->arch.vpit) 3956 goto out; 3957 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 3958 if (r) 3959 goto out; 3960 r = -EFAULT; 3961 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 3962 goto out; 3963 r = 0; 3964 break; 3965 } 3966 case KVM_SET_PIT2: { 3967 r = -EFAULT; 3968 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 3969 goto out; 3970 r = -ENXIO; 3971 if (!kvm->arch.vpit) 3972 goto out; 3973 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 3974 break; 3975 } 3976 case KVM_REINJECT_CONTROL: { 3977 struct kvm_reinject_control control; 3978 r = -EFAULT; 3979 if (copy_from_user(&control, argp, sizeof(control))) 3980 goto out; 3981 r = kvm_vm_ioctl_reinject(kvm, &control); 3982 break; 3983 } 3984 case KVM_SET_BOOT_CPU_ID: 3985 r = 0; 3986 mutex_lock(&kvm->lock); 3987 if (atomic_read(&kvm->online_vcpus) != 0) 3988 r = -EBUSY; 3989 else 3990 kvm->arch.bsp_vcpu_id = arg; 3991 mutex_unlock(&kvm->lock); 3992 break; 3993 case KVM_XEN_HVM_CONFIG: { 3994 r = -EFAULT; 3995 if (copy_from_user(&kvm->arch.xen_hvm_config, argp, 3996 sizeof(struct kvm_xen_hvm_config))) 3997 goto out; 3998 r = -EINVAL; 3999 if (kvm->arch.xen_hvm_config.flags) 4000 goto out; 4001 r = 0; 4002 break; 4003 } 4004 case KVM_SET_CLOCK: { 4005 struct kvm_clock_data user_ns; 4006 u64 now_ns; 4007 s64 delta; 4008 4009 r = -EFAULT; 4010 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 4011 goto out; 4012 4013 r = -EINVAL; 4014 if (user_ns.flags) 4015 goto out; 4016 4017 r = 0; 4018 local_irq_disable(); 4019 now_ns = get_kernel_ns(); 4020 delta = user_ns.clock - now_ns; 4021 local_irq_enable(); 4022 kvm->arch.kvmclock_offset = delta; 4023 kvm_gen_update_masterclock(kvm); 4024 break; 4025 } 4026 case KVM_GET_CLOCK: { 4027 struct kvm_clock_data user_ns; 4028 u64 now_ns; 4029 4030 local_irq_disable(); 4031 now_ns = get_kernel_ns(); 4032 user_ns.clock = kvm->arch.kvmclock_offset + now_ns; 4033 local_irq_enable(); 4034 user_ns.flags = 0; 4035 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 4036 4037 r = -EFAULT; 4038 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 4039 goto out; 4040 r = 0; 4041 break; 4042 } 4043 case KVM_ENABLE_CAP: { 4044 struct kvm_enable_cap cap; 4045 4046 r = -EFAULT; 4047 if (copy_from_user(&cap, argp, sizeof(cap))) 4048 goto out; 4049 r = kvm_vm_ioctl_enable_cap(kvm, &cap); 4050 break; 4051 } 4052 default: 4053 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg); 4054 } 4055 out: 4056 return r; 4057 } 4058 4059 static void kvm_init_msr_list(void) 4060 { 4061 u32 dummy[2]; 4062 unsigned i, j; 4063 4064 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { 4065 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4066 continue; 4067 4068 /* 4069 * Even MSRs that are valid in the host may not be exposed 4070 * to the guests in some cases. 4071 */ 4072 switch (msrs_to_save[i]) { 4073 case MSR_IA32_BNDCFGS: 4074 if (!kvm_x86_ops->mpx_supported()) 4075 continue; 4076 break; 4077 case MSR_TSC_AUX: 4078 if (!kvm_x86_ops->rdtscp_supported()) 4079 continue; 4080 break; 4081 default: 4082 break; 4083 } 4084 4085 if (j < i) 4086 msrs_to_save[j] = msrs_to_save[i]; 4087 j++; 4088 } 4089 num_msrs_to_save = j; 4090 4091 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { 4092 switch (emulated_msrs[i]) { 4093 case MSR_IA32_SMBASE: 4094 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase()) 4095 continue; 4096 break; 4097 default: 4098 break; 4099 } 4100 4101 if (j < i) 4102 emulated_msrs[j] = emulated_msrs[i]; 4103 j++; 4104 } 4105 num_emulated_msrs = j; 4106 } 4107 4108 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 4109 const void *v) 4110 { 4111 int handled = 0; 4112 int n; 4113 4114 do { 4115 n = min(len, 8); 4116 if (!(lapic_in_kernel(vcpu) && 4117 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 4118 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 4119 break; 4120 handled += n; 4121 addr += n; 4122 len -= n; 4123 v += n; 4124 } while (len); 4125 4126 return handled; 4127 } 4128 4129 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4130 { 4131 int handled = 0; 4132 int n; 4133 4134 do { 4135 n = min(len, 8); 4136 if (!(lapic_in_kernel(vcpu) && 4137 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 4138 addr, n, v)) 4139 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 4140 break; 4141 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); 4142 handled += n; 4143 addr += n; 4144 len -= n; 4145 v += n; 4146 } while (len); 4147 4148 return handled; 4149 } 4150 4151 static void kvm_set_segment(struct kvm_vcpu *vcpu, 4152 struct kvm_segment *var, int seg) 4153 { 4154 kvm_x86_ops->set_segment(vcpu, var, seg); 4155 } 4156 4157 void kvm_get_segment(struct kvm_vcpu *vcpu, 4158 struct kvm_segment *var, int seg) 4159 { 4160 kvm_x86_ops->get_segment(vcpu, var, seg); 4161 } 4162 4163 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 4164 struct x86_exception *exception) 4165 { 4166 gpa_t t_gpa; 4167 4168 BUG_ON(!mmu_is_nested(vcpu)); 4169 4170 /* NPT walks are always user-walks */ 4171 access |= PFERR_USER_MASK; 4172 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); 4173 4174 return t_gpa; 4175 } 4176 4177 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 4178 struct x86_exception *exception) 4179 { 4180 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4181 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4182 } 4183 4184 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 4185 struct x86_exception *exception) 4186 { 4187 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4188 access |= PFERR_FETCH_MASK; 4189 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4190 } 4191 4192 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 4193 struct x86_exception *exception) 4194 { 4195 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4196 access |= PFERR_WRITE_MASK; 4197 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4198 } 4199 4200 /* uses this to access any guest's mapped memory without checking CPL */ 4201 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 4202 struct x86_exception *exception) 4203 { 4204 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 4205 } 4206 4207 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 4208 struct kvm_vcpu *vcpu, u32 access, 4209 struct x86_exception *exception) 4210 { 4211 void *data = val; 4212 int r = X86EMUL_CONTINUE; 4213 4214 while (bytes) { 4215 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 4216 exception); 4217 unsigned offset = addr & (PAGE_SIZE-1); 4218 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 4219 int ret; 4220 4221 if (gpa == UNMAPPED_GVA) 4222 return X86EMUL_PROPAGATE_FAULT; 4223 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 4224 offset, toread); 4225 if (ret < 0) { 4226 r = X86EMUL_IO_NEEDED; 4227 goto out; 4228 } 4229 4230 bytes -= toread; 4231 data += toread; 4232 addr += toread; 4233 } 4234 out: 4235 return r; 4236 } 4237 4238 /* used for instruction fetching */ 4239 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4240 gva_t addr, void *val, unsigned int bytes, 4241 struct x86_exception *exception) 4242 { 4243 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4244 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4245 unsigned offset; 4246 int ret; 4247 4248 /* Inline kvm_read_guest_virt_helper for speed. */ 4249 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 4250 exception); 4251 if (unlikely(gpa == UNMAPPED_GVA)) 4252 return X86EMUL_PROPAGATE_FAULT; 4253 4254 offset = addr & (PAGE_SIZE-1); 4255 if (WARN_ON(offset + bytes > PAGE_SIZE)) 4256 bytes = (unsigned)PAGE_SIZE - offset; 4257 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 4258 offset, bytes); 4259 if (unlikely(ret < 0)) 4260 return X86EMUL_IO_NEEDED; 4261 4262 return X86EMUL_CONTINUE; 4263 } 4264 4265 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4266 gva_t addr, void *val, unsigned int bytes, 4267 struct x86_exception *exception) 4268 { 4269 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4270 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4271 4272 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4273 exception); 4274 } 4275 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4276 4277 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4278 gva_t addr, void *val, unsigned int bytes, 4279 struct x86_exception *exception) 4280 { 4281 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4282 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4283 } 4284 4285 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 4286 unsigned long addr, void *val, unsigned int bytes) 4287 { 4288 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4289 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 4290 4291 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 4292 } 4293 4294 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4295 gva_t addr, void *val, 4296 unsigned int bytes, 4297 struct x86_exception *exception) 4298 { 4299 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4300 void *data = val; 4301 int r = X86EMUL_CONTINUE; 4302 4303 while (bytes) { 4304 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4305 PFERR_WRITE_MASK, 4306 exception); 4307 unsigned offset = addr & (PAGE_SIZE-1); 4308 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4309 int ret; 4310 4311 if (gpa == UNMAPPED_GVA) 4312 return X86EMUL_PROPAGATE_FAULT; 4313 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 4314 if (ret < 0) { 4315 r = X86EMUL_IO_NEEDED; 4316 goto out; 4317 } 4318 4319 bytes -= towrite; 4320 data += towrite; 4321 addr += towrite; 4322 } 4323 out: 4324 return r; 4325 } 4326 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4327 4328 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4329 gpa_t *gpa, struct x86_exception *exception, 4330 bool write) 4331 { 4332 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4333 | (write ? PFERR_WRITE_MASK : 0); 4334 4335 /* 4336 * currently PKRU is only applied to ept enabled guest so 4337 * there is no pkey in EPT page table for L1 guest or EPT 4338 * shadow page table for L2 guest. 4339 */ 4340 if (vcpu_match_mmio_gva(vcpu, gva) 4341 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4342 vcpu->arch.access, 0, access)) { 4343 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4344 (gva & (PAGE_SIZE - 1)); 4345 trace_vcpu_match_mmio(gva, *gpa, write, false); 4346 return 1; 4347 } 4348 4349 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4350 4351 if (*gpa == UNMAPPED_GVA) 4352 return -1; 4353 4354 /* For APIC access vmexit */ 4355 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4356 return 1; 4357 4358 if (vcpu_match_mmio_gpa(vcpu, *gpa)) { 4359 trace_vcpu_match_mmio(gva, *gpa, write, true); 4360 return 1; 4361 } 4362 4363 return 0; 4364 } 4365 4366 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4367 const void *val, int bytes) 4368 { 4369 int ret; 4370 4371 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 4372 if (ret < 0) 4373 return 0; 4374 kvm_page_track_write(vcpu, gpa, val, bytes); 4375 return 1; 4376 } 4377 4378 struct read_write_emulator_ops { 4379 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4380 int bytes); 4381 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4382 void *val, int bytes); 4383 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4384 int bytes, void *val); 4385 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4386 void *val, int bytes); 4387 bool write; 4388 }; 4389 4390 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4391 { 4392 if (vcpu->mmio_read_completed) { 4393 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4394 vcpu->mmio_fragments[0].gpa, *(u64 *)val); 4395 vcpu->mmio_read_completed = 0; 4396 return 1; 4397 } 4398 4399 return 0; 4400 } 4401 4402 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4403 void *val, int bytes) 4404 { 4405 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 4406 } 4407 4408 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4409 void *val, int bytes) 4410 { 4411 return emulator_write_phys(vcpu, gpa, val, bytes); 4412 } 4413 4414 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4415 { 4416 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); 4417 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4418 } 4419 4420 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4421 void *val, int bytes) 4422 { 4423 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); 4424 return X86EMUL_IO_NEEDED; 4425 } 4426 4427 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4428 void *val, int bytes) 4429 { 4430 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4431 4432 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4433 return X86EMUL_CONTINUE; 4434 } 4435 4436 static const struct read_write_emulator_ops read_emultor = { 4437 .read_write_prepare = read_prepare, 4438 .read_write_emulate = read_emulate, 4439 .read_write_mmio = vcpu_mmio_read, 4440 .read_write_exit_mmio = read_exit_mmio, 4441 }; 4442 4443 static const struct read_write_emulator_ops write_emultor = { 4444 .read_write_emulate = write_emulate, 4445 .read_write_mmio = write_mmio, 4446 .read_write_exit_mmio = write_exit_mmio, 4447 .write = true, 4448 }; 4449 4450 static int emulator_read_write_onepage(unsigned long addr, void *val, 4451 unsigned int bytes, 4452 struct x86_exception *exception, 4453 struct kvm_vcpu *vcpu, 4454 const struct read_write_emulator_ops *ops) 4455 { 4456 gpa_t gpa; 4457 int handled, ret; 4458 bool write = ops->write; 4459 struct kvm_mmio_fragment *frag; 4460 4461 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 4462 4463 if (ret < 0) 4464 return X86EMUL_PROPAGATE_FAULT; 4465 4466 /* For APIC access vmexit */ 4467 if (ret) 4468 goto mmio; 4469 4470 if (ops->read_write_emulate(vcpu, gpa, val, bytes)) 4471 return X86EMUL_CONTINUE; 4472 4473 mmio: 4474 /* 4475 * Is this MMIO handled locally? 4476 */ 4477 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 4478 if (handled == bytes) 4479 return X86EMUL_CONTINUE; 4480 4481 gpa += handled; 4482 bytes -= handled; 4483 val += handled; 4484 4485 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 4486 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 4487 frag->gpa = gpa; 4488 frag->data = val; 4489 frag->len = bytes; 4490 return X86EMUL_CONTINUE; 4491 } 4492 4493 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 4494 unsigned long addr, 4495 void *val, unsigned int bytes, 4496 struct x86_exception *exception, 4497 const struct read_write_emulator_ops *ops) 4498 { 4499 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4500 gpa_t gpa; 4501 int rc; 4502 4503 if (ops->read_write_prepare && 4504 ops->read_write_prepare(vcpu, val, bytes)) 4505 return X86EMUL_CONTINUE; 4506 4507 vcpu->mmio_nr_fragments = 0; 4508 4509 /* Crossing a page boundary? */ 4510 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 4511 int now; 4512 4513 now = -addr & ~PAGE_MASK; 4514 rc = emulator_read_write_onepage(addr, val, now, exception, 4515 vcpu, ops); 4516 4517 if (rc != X86EMUL_CONTINUE) 4518 return rc; 4519 addr += now; 4520 if (ctxt->mode != X86EMUL_MODE_PROT64) 4521 addr = (u32)addr; 4522 val += now; 4523 bytes -= now; 4524 } 4525 4526 rc = emulator_read_write_onepage(addr, val, bytes, exception, 4527 vcpu, ops); 4528 if (rc != X86EMUL_CONTINUE) 4529 return rc; 4530 4531 if (!vcpu->mmio_nr_fragments) 4532 return rc; 4533 4534 gpa = vcpu->mmio_fragments[0].gpa; 4535 4536 vcpu->mmio_needed = 1; 4537 vcpu->mmio_cur_fragment = 0; 4538 4539 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 4540 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 4541 vcpu->run->exit_reason = KVM_EXIT_MMIO; 4542 vcpu->run->mmio.phys_addr = gpa; 4543 4544 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 4545 } 4546 4547 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 4548 unsigned long addr, 4549 void *val, 4550 unsigned int bytes, 4551 struct x86_exception *exception) 4552 { 4553 return emulator_read_write(ctxt, addr, val, bytes, 4554 exception, &read_emultor); 4555 } 4556 4557 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 4558 unsigned long addr, 4559 const void *val, 4560 unsigned int bytes, 4561 struct x86_exception *exception) 4562 { 4563 return emulator_read_write(ctxt, addr, (void *)val, bytes, 4564 exception, &write_emultor); 4565 } 4566 4567 #define CMPXCHG_TYPE(t, ptr, old, new) \ 4568 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 4569 4570 #ifdef CONFIG_X86_64 4571 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 4572 #else 4573 # define CMPXCHG64(ptr, old, new) \ 4574 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 4575 #endif 4576 4577 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 4578 unsigned long addr, 4579 const void *old, 4580 const void *new, 4581 unsigned int bytes, 4582 struct x86_exception *exception) 4583 { 4584 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4585 gpa_t gpa; 4586 struct page *page; 4587 char *kaddr; 4588 bool exchanged; 4589 4590 /* guests cmpxchg8b have to be emulated atomically */ 4591 if (bytes > 8 || (bytes & (bytes - 1))) 4592 goto emul_write; 4593 4594 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 4595 4596 if (gpa == UNMAPPED_GVA || 4597 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4598 goto emul_write; 4599 4600 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 4601 goto emul_write; 4602 4603 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); 4604 if (is_error_page(page)) 4605 goto emul_write; 4606 4607 kaddr = kmap_atomic(page); 4608 kaddr += offset_in_page(gpa); 4609 switch (bytes) { 4610 case 1: 4611 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 4612 break; 4613 case 2: 4614 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 4615 break; 4616 case 4: 4617 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 4618 break; 4619 case 8: 4620 exchanged = CMPXCHG64(kaddr, old, new); 4621 break; 4622 default: 4623 BUG(); 4624 } 4625 kunmap_atomic(kaddr); 4626 kvm_release_page_dirty(page); 4627 4628 if (!exchanged) 4629 return X86EMUL_CMPXCHG_FAILED; 4630 4631 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 4632 kvm_page_track_write(vcpu, gpa, new, bytes); 4633 4634 return X86EMUL_CONTINUE; 4635 4636 emul_write: 4637 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 4638 4639 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 4640 } 4641 4642 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 4643 { 4644 /* TODO: String I/O for in kernel device */ 4645 int r; 4646 4647 if (vcpu->arch.pio.in) 4648 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 4649 vcpu->arch.pio.size, pd); 4650 else 4651 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 4652 vcpu->arch.pio.port, vcpu->arch.pio.size, 4653 pd); 4654 return r; 4655 } 4656 4657 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 4658 unsigned short port, void *val, 4659 unsigned int count, bool in) 4660 { 4661 vcpu->arch.pio.port = port; 4662 vcpu->arch.pio.in = in; 4663 vcpu->arch.pio.count = count; 4664 vcpu->arch.pio.size = size; 4665 4666 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 4667 vcpu->arch.pio.count = 0; 4668 return 1; 4669 } 4670 4671 vcpu->run->exit_reason = KVM_EXIT_IO; 4672 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 4673 vcpu->run->io.size = size; 4674 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 4675 vcpu->run->io.count = count; 4676 vcpu->run->io.port = port; 4677 4678 return 0; 4679 } 4680 4681 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 4682 int size, unsigned short port, void *val, 4683 unsigned int count) 4684 { 4685 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4686 int ret; 4687 4688 if (vcpu->arch.pio.count) 4689 goto data_avail; 4690 4691 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 4692 if (ret) { 4693 data_avail: 4694 memcpy(val, vcpu->arch.pio_data, size * count); 4695 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 4696 vcpu->arch.pio.count = 0; 4697 return 1; 4698 } 4699 4700 return 0; 4701 } 4702 4703 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 4704 int size, unsigned short port, 4705 const void *val, unsigned int count) 4706 { 4707 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4708 4709 memcpy(vcpu->arch.pio_data, val, size * count); 4710 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 4711 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 4712 } 4713 4714 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 4715 { 4716 return kvm_x86_ops->get_segment_base(vcpu, seg); 4717 } 4718 4719 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 4720 { 4721 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 4722 } 4723 4724 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 4725 { 4726 if (!need_emulate_wbinvd(vcpu)) 4727 return X86EMUL_CONTINUE; 4728 4729 if (kvm_x86_ops->has_wbinvd_exit()) { 4730 int cpu = get_cpu(); 4731 4732 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4733 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 4734 wbinvd_ipi, NULL, 1); 4735 put_cpu(); 4736 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 4737 } else 4738 wbinvd(); 4739 return X86EMUL_CONTINUE; 4740 } 4741 4742 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 4743 { 4744 kvm_x86_ops->skip_emulated_instruction(vcpu); 4745 return kvm_emulate_wbinvd_noskip(vcpu); 4746 } 4747 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 4748 4749 4750 4751 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 4752 { 4753 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 4754 } 4755 4756 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 4757 unsigned long *dest) 4758 { 4759 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 4760 } 4761 4762 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 4763 unsigned long value) 4764 { 4765 4766 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 4767 } 4768 4769 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 4770 { 4771 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 4772 } 4773 4774 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 4775 { 4776 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4777 unsigned long value; 4778 4779 switch (cr) { 4780 case 0: 4781 value = kvm_read_cr0(vcpu); 4782 break; 4783 case 2: 4784 value = vcpu->arch.cr2; 4785 break; 4786 case 3: 4787 value = kvm_read_cr3(vcpu); 4788 break; 4789 case 4: 4790 value = kvm_read_cr4(vcpu); 4791 break; 4792 case 8: 4793 value = kvm_get_cr8(vcpu); 4794 break; 4795 default: 4796 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4797 return 0; 4798 } 4799 4800 return value; 4801 } 4802 4803 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 4804 { 4805 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4806 int res = 0; 4807 4808 switch (cr) { 4809 case 0: 4810 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 4811 break; 4812 case 2: 4813 vcpu->arch.cr2 = val; 4814 break; 4815 case 3: 4816 res = kvm_set_cr3(vcpu, val); 4817 break; 4818 case 4: 4819 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 4820 break; 4821 case 8: 4822 res = kvm_set_cr8(vcpu, val); 4823 break; 4824 default: 4825 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4826 res = -1; 4827 } 4828 4829 return res; 4830 } 4831 4832 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 4833 { 4834 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 4835 } 4836 4837 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4838 { 4839 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 4840 } 4841 4842 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4843 { 4844 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 4845 } 4846 4847 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4848 { 4849 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 4850 } 4851 4852 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4853 { 4854 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 4855 } 4856 4857 static unsigned long emulator_get_cached_segment_base( 4858 struct x86_emulate_ctxt *ctxt, int seg) 4859 { 4860 return get_segment_base(emul_to_vcpu(ctxt), seg); 4861 } 4862 4863 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 4864 struct desc_struct *desc, u32 *base3, 4865 int seg) 4866 { 4867 struct kvm_segment var; 4868 4869 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 4870 *selector = var.selector; 4871 4872 if (var.unusable) { 4873 memset(desc, 0, sizeof(*desc)); 4874 return false; 4875 } 4876 4877 if (var.g) 4878 var.limit >>= 12; 4879 set_desc_limit(desc, var.limit); 4880 set_desc_base(desc, (unsigned long)var.base); 4881 #ifdef CONFIG_X86_64 4882 if (base3) 4883 *base3 = var.base >> 32; 4884 #endif 4885 desc->type = var.type; 4886 desc->s = var.s; 4887 desc->dpl = var.dpl; 4888 desc->p = var.present; 4889 desc->avl = var.avl; 4890 desc->l = var.l; 4891 desc->d = var.db; 4892 desc->g = var.g; 4893 4894 return true; 4895 } 4896 4897 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 4898 struct desc_struct *desc, u32 base3, 4899 int seg) 4900 { 4901 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4902 struct kvm_segment var; 4903 4904 var.selector = selector; 4905 var.base = get_desc_base(desc); 4906 #ifdef CONFIG_X86_64 4907 var.base |= ((u64)base3) << 32; 4908 #endif 4909 var.limit = get_desc_limit(desc); 4910 if (desc->g) 4911 var.limit = (var.limit << 12) | 0xfff; 4912 var.type = desc->type; 4913 var.dpl = desc->dpl; 4914 var.db = desc->d; 4915 var.s = desc->s; 4916 var.l = desc->l; 4917 var.g = desc->g; 4918 var.avl = desc->avl; 4919 var.present = desc->p; 4920 var.unusable = !var.present; 4921 var.padding = 0; 4922 4923 kvm_set_segment(vcpu, &var, seg); 4924 return; 4925 } 4926 4927 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 4928 u32 msr_index, u64 *pdata) 4929 { 4930 struct msr_data msr; 4931 int r; 4932 4933 msr.index = msr_index; 4934 msr.host_initiated = false; 4935 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); 4936 if (r) 4937 return r; 4938 4939 *pdata = msr.data; 4940 return 0; 4941 } 4942 4943 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 4944 u32 msr_index, u64 data) 4945 { 4946 struct msr_data msr; 4947 4948 msr.data = data; 4949 msr.index = msr_index; 4950 msr.host_initiated = false; 4951 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 4952 } 4953 4954 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 4955 { 4956 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4957 4958 return vcpu->arch.smbase; 4959 } 4960 4961 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 4962 { 4963 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4964 4965 vcpu->arch.smbase = smbase; 4966 } 4967 4968 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 4969 u32 pmc) 4970 { 4971 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); 4972 } 4973 4974 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 4975 u32 pmc, u64 *pdata) 4976 { 4977 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 4978 } 4979 4980 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 4981 { 4982 emul_to_vcpu(ctxt)->arch.halt_request = 1; 4983 } 4984 4985 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) 4986 { 4987 preempt_disable(); 4988 kvm_load_guest_fpu(emul_to_vcpu(ctxt)); 4989 /* 4990 * CR0.TS may reference the host fpu state, not the guest fpu state, 4991 * so it may be clear at this point. 4992 */ 4993 clts(); 4994 } 4995 4996 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) 4997 { 4998 preempt_enable(); 4999 } 5000 5001 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 5002 struct x86_instruction_info *info, 5003 enum x86_intercept_stage stage) 5004 { 5005 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 5006 } 5007 5008 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 5009 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) 5010 { 5011 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); 5012 } 5013 5014 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 5015 { 5016 return kvm_register_read(emul_to_vcpu(ctxt), reg); 5017 } 5018 5019 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 5020 { 5021 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 5022 } 5023 5024 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 5025 { 5026 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 5027 } 5028 5029 static const struct x86_emulate_ops emulate_ops = { 5030 .read_gpr = emulator_read_gpr, 5031 .write_gpr = emulator_write_gpr, 5032 .read_std = kvm_read_guest_virt_system, 5033 .write_std = kvm_write_guest_virt_system, 5034 .read_phys = kvm_read_guest_phys_system, 5035 .fetch = kvm_fetch_guest_virt, 5036 .read_emulated = emulator_read_emulated, 5037 .write_emulated = emulator_write_emulated, 5038 .cmpxchg_emulated = emulator_cmpxchg_emulated, 5039 .invlpg = emulator_invlpg, 5040 .pio_in_emulated = emulator_pio_in_emulated, 5041 .pio_out_emulated = emulator_pio_out_emulated, 5042 .get_segment = emulator_get_segment, 5043 .set_segment = emulator_set_segment, 5044 .get_cached_segment_base = emulator_get_cached_segment_base, 5045 .get_gdt = emulator_get_gdt, 5046 .get_idt = emulator_get_idt, 5047 .set_gdt = emulator_set_gdt, 5048 .set_idt = emulator_set_idt, 5049 .get_cr = emulator_get_cr, 5050 .set_cr = emulator_set_cr, 5051 .cpl = emulator_get_cpl, 5052 .get_dr = emulator_get_dr, 5053 .set_dr = emulator_set_dr, 5054 .get_smbase = emulator_get_smbase, 5055 .set_smbase = emulator_set_smbase, 5056 .set_msr = emulator_set_msr, 5057 .get_msr = emulator_get_msr, 5058 .check_pmc = emulator_check_pmc, 5059 .read_pmc = emulator_read_pmc, 5060 .halt = emulator_halt, 5061 .wbinvd = emulator_wbinvd, 5062 .fix_hypercall = emulator_fix_hypercall, 5063 .get_fpu = emulator_get_fpu, 5064 .put_fpu = emulator_put_fpu, 5065 .intercept = emulator_intercept, 5066 .get_cpuid = emulator_get_cpuid, 5067 .set_nmi_mask = emulator_set_nmi_mask, 5068 }; 5069 5070 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 5071 { 5072 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 5073 /* 5074 * an sti; sti; sequence only disable interrupts for the first 5075 * instruction. So, if the last instruction, be it emulated or 5076 * not, left the system with the INT_STI flag enabled, it 5077 * means that the last instruction is an sti. We should not 5078 * leave the flag on in this case. The same goes for mov ss 5079 */ 5080 if (int_shadow & mask) 5081 mask = 0; 5082 if (unlikely(int_shadow || mask)) { 5083 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 5084 if (!mask) 5085 kvm_make_request(KVM_REQ_EVENT, vcpu); 5086 } 5087 } 5088 5089 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 5090 { 5091 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5092 if (ctxt->exception.vector == PF_VECTOR) 5093 return kvm_propagate_fault(vcpu, &ctxt->exception); 5094 5095 if (ctxt->exception.error_code_valid) 5096 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 5097 ctxt->exception.error_code); 5098 else 5099 kvm_queue_exception(vcpu, ctxt->exception.vector); 5100 return false; 5101 } 5102 5103 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 5104 { 5105 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5106 int cs_db, cs_l; 5107 5108 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 5109 5110 ctxt->eflags = kvm_get_rflags(vcpu); 5111 ctxt->eip = kvm_rip_read(vcpu); 5112 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 5113 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 5114 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 5115 cs_db ? X86EMUL_MODE_PROT32 : 5116 X86EMUL_MODE_PROT16; 5117 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 5118 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 5119 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 5120 ctxt->emul_flags = vcpu->arch.hflags; 5121 5122 init_decode_cache(ctxt); 5123 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5124 } 5125 5126 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 5127 { 5128 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5129 int ret; 5130 5131 init_emulate_ctxt(vcpu); 5132 5133 ctxt->op_bytes = 2; 5134 ctxt->ad_bytes = 2; 5135 ctxt->_eip = ctxt->eip + inc_eip; 5136 ret = emulate_int_real(ctxt, irq); 5137 5138 if (ret != X86EMUL_CONTINUE) 5139 return EMULATE_FAIL; 5140 5141 ctxt->eip = ctxt->_eip; 5142 kvm_rip_write(vcpu, ctxt->eip); 5143 kvm_set_rflags(vcpu, ctxt->eflags); 5144 5145 if (irq == NMI_VECTOR) 5146 vcpu->arch.nmi_pending = 0; 5147 else 5148 vcpu->arch.interrupt.pending = false; 5149 5150 return EMULATE_DONE; 5151 } 5152 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 5153 5154 static int handle_emulation_failure(struct kvm_vcpu *vcpu) 5155 { 5156 int r = EMULATE_DONE; 5157 5158 ++vcpu->stat.insn_emulation_fail; 5159 trace_kvm_emulate_insn_failed(vcpu); 5160 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 5161 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5162 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 5163 vcpu->run->internal.ndata = 0; 5164 r = EMULATE_FAIL; 5165 } 5166 kvm_queue_exception(vcpu, UD_VECTOR); 5167 5168 return r; 5169 } 5170 5171 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 5172 bool write_fault_to_shadow_pgtable, 5173 int emulation_type) 5174 { 5175 gpa_t gpa = cr2; 5176 kvm_pfn_t pfn; 5177 5178 if (emulation_type & EMULTYPE_NO_REEXECUTE) 5179 return false; 5180 5181 if (!vcpu->arch.mmu.direct_map) { 5182 /* 5183 * Write permission should be allowed since only 5184 * write access need to be emulated. 5185 */ 5186 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5187 5188 /* 5189 * If the mapping is invalid in guest, let cpu retry 5190 * it to generate fault. 5191 */ 5192 if (gpa == UNMAPPED_GVA) 5193 return true; 5194 } 5195 5196 /* 5197 * Do not retry the unhandleable instruction if it faults on the 5198 * readonly host memory, otherwise it will goto a infinite loop: 5199 * retry instruction -> write #PF -> emulation fail -> retry 5200 * instruction -> ... 5201 */ 5202 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 5203 5204 /* 5205 * If the instruction failed on the error pfn, it can not be fixed, 5206 * report the error to userspace. 5207 */ 5208 if (is_error_noslot_pfn(pfn)) 5209 return false; 5210 5211 kvm_release_pfn_clean(pfn); 5212 5213 /* The instructions are well-emulated on direct mmu. */ 5214 if (vcpu->arch.mmu.direct_map) { 5215 unsigned int indirect_shadow_pages; 5216 5217 spin_lock(&vcpu->kvm->mmu_lock); 5218 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 5219 spin_unlock(&vcpu->kvm->mmu_lock); 5220 5221 if (indirect_shadow_pages) 5222 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5223 5224 return true; 5225 } 5226 5227 /* 5228 * if emulation was due to access to shadowed page table 5229 * and it failed try to unshadow page and re-enter the 5230 * guest to let CPU execute the instruction. 5231 */ 5232 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5233 5234 /* 5235 * If the access faults on its page table, it can not 5236 * be fixed by unprotecting shadow page and it should 5237 * be reported to userspace. 5238 */ 5239 return !write_fault_to_shadow_pgtable; 5240 } 5241 5242 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5243 unsigned long cr2, int emulation_type) 5244 { 5245 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5246 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5247 5248 last_retry_eip = vcpu->arch.last_retry_eip; 5249 last_retry_addr = vcpu->arch.last_retry_addr; 5250 5251 /* 5252 * If the emulation is caused by #PF and it is non-page_table 5253 * writing instruction, it means the VM-EXIT is caused by shadow 5254 * page protected, we can zap the shadow page and retry this 5255 * instruction directly. 5256 * 5257 * Note: if the guest uses a non-page-table modifying instruction 5258 * on the PDE that points to the instruction, then we will unmap 5259 * the instruction and go to an infinite loop. So, we cache the 5260 * last retried eip and the last fault address, if we meet the eip 5261 * and the address again, we can break out of the potential infinite 5262 * loop. 5263 */ 5264 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5265 5266 if (!(emulation_type & EMULTYPE_RETRY)) 5267 return false; 5268 5269 if (x86_page_table_writing_insn(ctxt)) 5270 return false; 5271 5272 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5273 return false; 5274 5275 vcpu->arch.last_retry_eip = ctxt->eip; 5276 vcpu->arch.last_retry_addr = cr2; 5277 5278 if (!vcpu->arch.mmu.direct_map) 5279 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5280 5281 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5282 5283 return true; 5284 } 5285 5286 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5287 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5288 5289 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 5290 { 5291 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 5292 /* This is a good place to trace that we are exiting SMM. */ 5293 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 5294 5295 if (unlikely(vcpu->arch.smi_pending)) { 5296 kvm_make_request(KVM_REQ_SMI, vcpu); 5297 vcpu->arch.smi_pending = 0; 5298 } else { 5299 /* Process a latched INIT, if any. */ 5300 kvm_make_request(KVM_REQ_EVENT, vcpu); 5301 } 5302 } 5303 5304 kvm_mmu_reset_context(vcpu); 5305 } 5306 5307 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) 5308 { 5309 unsigned changed = vcpu->arch.hflags ^ emul_flags; 5310 5311 vcpu->arch.hflags = emul_flags; 5312 5313 if (changed & HF_SMM_MASK) 5314 kvm_smm_changed(vcpu); 5315 } 5316 5317 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5318 unsigned long *db) 5319 { 5320 u32 dr6 = 0; 5321 int i; 5322 u32 enable, rwlen; 5323 5324 enable = dr7; 5325 rwlen = dr7 >> 16; 5326 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5327 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5328 dr6 |= (1 << i); 5329 return dr6; 5330 } 5331 5332 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) 5333 { 5334 struct kvm_run *kvm_run = vcpu->run; 5335 5336 /* 5337 * rflags is the old, "raw" value of the flags. The new value has 5338 * not been saved yet. 5339 * 5340 * This is correct even for TF set by the guest, because "the 5341 * processor will not generate this exception after the instruction 5342 * that sets the TF flag". 5343 */ 5344 if (unlikely(rflags & X86_EFLAGS_TF)) { 5345 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5346 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | 5347 DR6_RTM; 5348 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5349 kvm_run->debug.arch.exception = DB_VECTOR; 5350 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5351 *r = EMULATE_USER_EXIT; 5352 } else { 5353 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; 5354 /* 5355 * "Certain debug exceptions may clear bit 0-3. The 5356 * remaining contents of the DR6 register are never 5357 * cleared by the processor". 5358 */ 5359 vcpu->arch.dr6 &= ~15; 5360 vcpu->arch.dr6 |= DR6_BS | DR6_RTM; 5361 kvm_queue_exception(vcpu, DB_VECTOR); 5362 } 5363 } 5364 } 5365 5366 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5367 { 5368 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5369 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5370 struct kvm_run *kvm_run = vcpu->run; 5371 unsigned long eip = kvm_get_linear_rip(vcpu); 5372 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5373 vcpu->arch.guest_debug_dr7, 5374 vcpu->arch.eff_db); 5375 5376 if (dr6 != 0) { 5377 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 5378 kvm_run->debug.arch.pc = eip; 5379 kvm_run->debug.arch.exception = DB_VECTOR; 5380 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5381 *r = EMULATE_USER_EXIT; 5382 return true; 5383 } 5384 } 5385 5386 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 5387 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 5388 unsigned long eip = kvm_get_linear_rip(vcpu); 5389 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5390 vcpu->arch.dr7, 5391 vcpu->arch.db); 5392 5393 if (dr6 != 0) { 5394 vcpu->arch.dr6 &= ~15; 5395 vcpu->arch.dr6 |= dr6 | DR6_RTM; 5396 kvm_queue_exception(vcpu, DB_VECTOR); 5397 *r = EMULATE_DONE; 5398 return true; 5399 } 5400 } 5401 5402 return false; 5403 } 5404 5405 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 5406 unsigned long cr2, 5407 int emulation_type, 5408 void *insn, 5409 int insn_len) 5410 { 5411 int r; 5412 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5413 bool writeback = true; 5414 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 5415 5416 /* 5417 * Clear write_fault_to_shadow_pgtable here to ensure it is 5418 * never reused. 5419 */ 5420 vcpu->arch.write_fault_to_shadow_pgtable = false; 5421 kvm_clear_exception_queue(vcpu); 5422 5423 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 5424 init_emulate_ctxt(vcpu); 5425 5426 /* 5427 * We will reenter on the same instruction since 5428 * we do not set complete_userspace_io. This does not 5429 * handle watchpoints yet, those would be handled in 5430 * the emulate_ops. 5431 */ 5432 if (kvm_vcpu_check_breakpoint(vcpu, &r)) 5433 return r; 5434 5435 ctxt->interruptibility = 0; 5436 ctxt->have_exception = false; 5437 ctxt->exception.vector = -1; 5438 ctxt->perm_ok = false; 5439 5440 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 5441 5442 r = x86_decode_insn(ctxt, insn, insn_len); 5443 5444 trace_kvm_emulate_insn_start(vcpu); 5445 ++vcpu->stat.insn_emulation; 5446 if (r != EMULATION_OK) { 5447 if (emulation_type & EMULTYPE_TRAP_UD) 5448 return EMULATE_FAIL; 5449 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5450 emulation_type)) 5451 return EMULATE_DONE; 5452 if (emulation_type & EMULTYPE_SKIP) 5453 return EMULATE_FAIL; 5454 return handle_emulation_failure(vcpu); 5455 } 5456 } 5457 5458 if (emulation_type & EMULTYPE_SKIP) { 5459 kvm_rip_write(vcpu, ctxt->_eip); 5460 if (ctxt->eflags & X86_EFLAGS_RF) 5461 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 5462 return EMULATE_DONE; 5463 } 5464 5465 if (retry_instruction(ctxt, cr2, emulation_type)) 5466 return EMULATE_DONE; 5467 5468 /* this is needed for vmware backdoor interface to work since it 5469 changes registers values during IO operation */ 5470 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 5471 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5472 emulator_invalidate_register_cache(ctxt); 5473 } 5474 5475 restart: 5476 r = x86_emulate_insn(ctxt); 5477 5478 if (r == EMULATION_INTERCEPTED) 5479 return EMULATE_DONE; 5480 5481 if (r == EMULATION_FAILED) { 5482 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5483 emulation_type)) 5484 return EMULATE_DONE; 5485 5486 return handle_emulation_failure(vcpu); 5487 } 5488 5489 if (ctxt->have_exception) { 5490 r = EMULATE_DONE; 5491 if (inject_emulated_exception(vcpu)) 5492 return r; 5493 } else if (vcpu->arch.pio.count) { 5494 if (!vcpu->arch.pio.in) { 5495 /* FIXME: return into emulator if single-stepping. */ 5496 vcpu->arch.pio.count = 0; 5497 } else { 5498 writeback = false; 5499 vcpu->arch.complete_userspace_io = complete_emulated_pio; 5500 } 5501 r = EMULATE_USER_EXIT; 5502 } else if (vcpu->mmio_needed) { 5503 if (!vcpu->mmio_is_write) 5504 writeback = false; 5505 r = EMULATE_USER_EXIT; 5506 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 5507 } else if (r == EMULATION_RESTART) 5508 goto restart; 5509 else 5510 r = EMULATE_DONE; 5511 5512 if (writeback) { 5513 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5514 toggle_interruptibility(vcpu, ctxt->interruptibility); 5515 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 5516 if (vcpu->arch.hflags != ctxt->emul_flags) 5517 kvm_set_hflags(vcpu, ctxt->emul_flags); 5518 kvm_rip_write(vcpu, ctxt->eip); 5519 if (r == EMULATE_DONE) 5520 kvm_vcpu_check_singlestep(vcpu, rflags, &r); 5521 if (!ctxt->have_exception || 5522 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 5523 __kvm_set_rflags(vcpu, ctxt->eflags); 5524 5525 /* 5526 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 5527 * do nothing, and it will be requested again as soon as 5528 * the shadow expires. But we still need to check here, 5529 * because POPF has no interrupt shadow. 5530 */ 5531 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 5532 kvm_make_request(KVM_REQ_EVENT, vcpu); 5533 } else 5534 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 5535 5536 return r; 5537 } 5538 EXPORT_SYMBOL_GPL(x86_emulate_instruction); 5539 5540 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) 5541 { 5542 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 5543 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 5544 size, port, &val, 1); 5545 /* do not return to emulator after return from userspace */ 5546 vcpu->arch.pio.count = 0; 5547 return ret; 5548 } 5549 EXPORT_SYMBOL_GPL(kvm_fast_pio_out); 5550 5551 static void tsc_bad(void *info) 5552 { 5553 __this_cpu_write(cpu_tsc_khz, 0); 5554 } 5555 5556 static void tsc_khz_changed(void *data) 5557 { 5558 struct cpufreq_freqs *freq = data; 5559 unsigned long khz = 0; 5560 5561 if (data) 5562 khz = freq->new; 5563 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5564 khz = cpufreq_quick_get(raw_smp_processor_id()); 5565 if (!khz) 5566 khz = tsc_khz; 5567 __this_cpu_write(cpu_tsc_khz, khz); 5568 } 5569 5570 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 5571 void *data) 5572 { 5573 struct cpufreq_freqs *freq = data; 5574 struct kvm *kvm; 5575 struct kvm_vcpu *vcpu; 5576 int i, send_ipi = 0; 5577 5578 /* 5579 * We allow guests to temporarily run on slowing clocks, 5580 * provided we notify them after, or to run on accelerating 5581 * clocks, provided we notify them before. Thus time never 5582 * goes backwards. 5583 * 5584 * However, we have a problem. We can't atomically update 5585 * the frequency of a given CPU from this function; it is 5586 * merely a notifier, which can be called from any CPU. 5587 * Changing the TSC frequency at arbitrary points in time 5588 * requires a recomputation of local variables related to 5589 * the TSC for each VCPU. We must flag these local variables 5590 * to be updated and be sure the update takes place with the 5591 * new frequency before any guests proceed. 5592 * 5593 * Unfortunately, the combination of hotplug CPU and frequency 5594 * change creates an intractable locking scenario; the order 5595 * of when these callouts happen is undefined with respect to 5596 * CPU hotplug, and they can race with each other. As such, 5597 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 5598 * undefined; you can actually have a CPU frequency change take 5599 * place in between the computation of X and the setting of the 5600 * variable. To protect against this problem, all updates of 5601 * the per_cpu tsc_khz variable are done in an interrupt 5602 * protected IPI, and all callers wishing to update the value 5603 * must wait for a synchronous IPI to complete (which is trivial 5604 * if the caller is on the CPU already). This establishes the 5605 * necessary total order on variable updates. 5606 * 5607 * Note that because a guest time update may take place 5608 * anytime after the setting of the VCPU's request bit, the 5609 * correct TSC value must be set before the request. However, 5610 * to ensure the update actually makes it to any guest which 5611 * starts running in hardware virtualization between the set 5612 * and the acquisition of the spinlock, we must also ping the 5613 * CPU after setting the request bit. 5614 * 5615 */ 5616 5617 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 5618 return 0; 5619 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 5620 return 0; 5621 5622 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5623 5624 spin_lock(&kvm_lock); 5625 list_for_each_entry(kvm, &vm_list, vm_list) { 5626 kvm_for_each_vcpu(i, vcpu, kvm) { 5627 if (vcpu->cpu != freq->cpu) 5628 continue; 5629 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5630 if (vcpu->cpu != smp_processor_id()) 5631 send_ipi = 1; 5632 } 5633 } 5634 spin_unlock(&kvm_lock); 5635 5636 if (freq->old < freq->new && send_ipi) { 5637 /* 5638 * We upscale the frequency. Must make the guest 5639 * doesn't see old kvmclock values while running with 5640 * the new frequency, otherwise we risk the guest sees 5641 * time go backwards. 5642 * 5643 * In case we update the frequency for another cpu 5644 * (which might be in guest context) send an interrupt 5645 * to kick the cpu out of guest context. Next time 5646 * guest context is entered kvmclock will be updated, 5647 * so the guest will not see stale values. 5648 */ 5649 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5650 } 5651 return 0; 5652 } 5653 5654 static struct notifier_block kvmclock_cpufreq_notifier_block = { 5655 .notifier_call = kvmclock_cpufreq_notifier 5656 }; 5657 5658 static int kvmclock_cpu_notifier(struct notifier_block *nfb, 5659 unsigned long action, void *hcpu) 5660 { 5661 unsigned int cpu = (unsigned long)hcpu; 5662 5663 switch (action) { 5664 case CPU_ONLINE: 5665 case CPU_DOWN_FAILED: 5666 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5667 break; 5668 case CPU_DOWN_PREPARE: 5669 smp_call_function_single(cpu, tsc_bad, NULL, 1); 5670 break; 5671 } 5672 return NOTIFY_OK; 5673 } 5674 5675 static struct notifier_block kvmclock_cpu_notifier_block = { 5676 .notifier_call = kvmclock_cpu_notifier, 5677 .priority = -INT_MAX 5678 }; 5679 5680 static void kvm_timer_init(void) 5681 { 5682 int cpu; 5683 5684 max_tsc_khz = tsc_khz; 5685 5686 cpu_notifier_register_begin(); 5687 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 5688 #ifdef CONFIG_CPU_FREQ 5689 struct cpufreq_policy policy; 5690 memset(&policy, 0, sizeof(policy)); 5691 cpu = get_cpu(); 5692 cpufreq_get_policy(&policy, cpu); 5693 if (policy.cpuinfo.max_freq) 5694 max_tsc_khz = policy.cpuinfo.max_freq; 5695 put_cpu(); 5696 #endif 5697 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 5698 CPUFREQ_TRANSITION_NOTIFIER); 5699 } 5700 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 5701 for_each_online_cpu(cpu) 5702 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5703 5704 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5705 cpu_notifier_register_done(); 5706 5707 } 5708 5709 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 5710 5711 int kvm_is_in_guest(void) 5712 { 5713 return __this_cpu_read(current_vcpu) != NULL; 5714 } 5715 5716 static int kvm_is_user_mode(void) 5717 { 5718 int user_mode = 3; 5719 5720 if (__this_cpu_read(current_vcpu)) 5721 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 5722 5723 return user_mode != 0; 5724 } 5725 5726 static unsigned long kvm_get_guest_ip(void) 5727 { 5728 unsigned long ip = 0; 5729 5730 if (__this_cpu_read(current_vcpu)) 5731 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 5732 5733 return ip; 5734 } 5735 5736 static struct perf_guest_info_callbacks kvm_guest_cbs = { 5737 .is_in_guest = kvm_is_in_guest, 5738 .is_user_mode = kvm_is_user_mode, 5739 .get_guest_ip = kvm_get_guest_ip, 5740 }; 5741 5742 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) 5743 { 5744 __this_cpu_write(current_vcpu, vcpu); 5745 } 5746 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); 5747 5748 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) 5749 { 5750 __this_cpu_write(current_vcpu, NULL); 5751 } 5752 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); 5753 5754 static void kvm_set_mmio_spte_mask(void) 5755 { 5756 u64 mask; 5757 int maxphyaddr = boot_cpu_data.x86_phys_bits; 5758 5759 /* 5760 * Set the reserved bits and the present bit of an paging-structure 5761 * entry to generate page fault with PFER.RSV = 1. 5762 */ 5763 /* Mask the reserved physical address bits. */ 5764 mask = rsvd_bits(maxphyaddr, 51); 5765 5766 /* Bit 62 is always reserved for 32bit host. */ 5767 mask |= 0x3ull << 62; 5768 5769 /* Set the present bit. */ 5770 mask |= 1ull; 5771 5772 #ifdef CONFIG_X86_64 5773 /* 5774 * If reserved bit is not supported, clear the present bit to disable 5775 * mmio page fault. 5776 */ 5777 if (maxphyaddr == 52) 5778 mask &= ~1ull; 5779 #endif 5780 5781 kvm_mmu_set_mmio_spte_mask(mask); 5782 } 5783 5784 #ifdef CONFIG_X86_64 5785 static void pvclock_gtod_update_fn(struct work_struct *work) 5786 { 5787 struct kvm *kvm; 5788 5789 struct kvm_vcpu *vcpu; 5790 int i; 5791 5792 spin_lock(&kvm_lock); 5793 list_for_each_entry(kvm, &vm_list, vm_list) 5794 kvm_for_each_vcpu(i, vcpu, kvm) 5795 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 5796 atomic_set(&kvm_guest_has_master_clock, 0); 5797 spin_unlock(&kvm_lock); 5798 } 5799 5800 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 5801 5802 /* 5803 * Notification about pvclock gtod data update. 5804 */ 5805 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 5806 void *priv) 5807 { 5808 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 5809 struct timekeeper *tk = priv; 5810 5811 update_pvclock_gtod(tk); 5812 5813 /* disable master clock if host does not trust, or does not 5814 * use, TSC clocksource 5815 */ 5816 if (gtod->clock.vclock_mode != VCLOCK_TSC && 5817 atomic_read(&kvm_guest_has_master_clock) != 0) 5818 queue_work(system_long_wq, &pvclock_gtod_work); 5819 5820 return 0; 5821 } 5822 5823 static struct notifier_block pvclock_gtod_notifier = { 5824 .notifier_call = pvclock_gtod_notify, 5825 }; 5826 #endif 5827 5828 int kvm_arch_init(void *opaque) 5829 { 5830 int r; 5831 struct kvm_x86_ops *ops = opaque; 5832 5833 if (kvm_x86_ops) { 5834 printk(KERN_ERR "kvm: already loaded the other module\n"); 5835 r = -EEXIST; 5836 goto out; 5837 } 5838 5839 if (!ops->cpu_has_kvm_support()) { 5840 printk(KERN_ERR "kvm: no hardware support\n"); 5841 r = -EOPNOTSUPP; 5842 goto out; 5843 } 5844 if (ops->disabled_by_bios()) { 5845 printk(KERN_ERR "kvm: disabled by bios\n"); 5846 r = -EOPNOTSUPP; 5847 goto out; 5848 } 5849 5850 r = -ENOMEM; 5851 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 5852 if (!shared_msrs) { 5853 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 5854 goto out; 5855 } 5856 5857 r = kvm_mmu_module_init(); 5858 if (r) 5859 goto out_free_percpu; 5860 5861 kvm_set_mmio_spte_mask(); 5862 5863 kvm_x86_ops = ops; 5864 5865 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 5866 PT_DIRTY_MASK, PT64_NX_MASK, 0); 5867 5868 kvm_timer_init(); 5869 5870 perf_register_guest_info_callbacks(&kvm_guest_cbs); 5871 5872 if (boot_cpu_has(X86_FEATURE_XSAVE)) 5873 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 5874 5875 kvm_lapic_init(); 5876 #ifdef CONFIG_X86_64 5877 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 5878 #endif 5879 5880 return 0; 5881 5882 out_free_percpu: 5883 free_percpu(shared_msrs); 5884 out: 5885 return r; 5886 } 5887 5888 void kvm_arch_exit(void) 5889 { 5890 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 5891 5892 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5893 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 5894 CPUFREQ_TRANSITION_NOTIFIER); 5895 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5896 #ifdef CONFIG_X86_64 5897 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 5898 #endif 5899 kvm_x86_ops = NULL; 5900 kvm_mmu_module_exit(); 5901 free_percpu(shared_msrs); 5902 } 5903 5904 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 5905 { 5906 ++vcpu->stat.halt_exits; 5907 if (lapic_in_kernel(vcpu)) { 5908 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 5909 return 1; 5910 } else { 5911 vcpu->run->exit_reason = KVM_EXIT_HLT; 5912 return 0; 5913 } 5914 } 5915 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 5916 5917 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 5918 { 5919 kvm_x86_ops->skip_emulated_instruction(vcpu); 5920 return kvm_vcpu_halt(vcpu); 5921 } 5922 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 5923 5924 /* 5925 * kvm_pv_kick_cpu_op: Kick a vcpu. 5926 * 5927 * @apicid - apicid of vcpu to be kicked. 5928 */ 5929 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 5930 { 5931 struct kvm_lapic_irq lapic_irq; 5932 5933 lapic_irq.shorthand = 0; 5934 lapic_irq.dest_mode = 0; 5935 lapic_irq.dest_id = apicid; 5936 lapic_irq.msi_redir_hint = false; 5937 5938 lapic_irq.delivery_mode = APIC_DM_REMRD; 5939 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 5940 } 5941 5942 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) 5943 { 5944 vcpu->arch.apicv_active = false; 5945 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); 5946 } 5947 5948 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 5949 { 5950 unsigned long nr, a0, a1, a2, a3, ret; 5951 int op_64_bit, r = 1; 5952 5953 kvm_x86_ops->skip_emulated_instruction(vcpu); 5954 5955 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 5956 return kvm_hv_hypercall(vcpu); 5957 5958 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 5959 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 5960 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 5961 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 5962 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 5963 5964 trace_kvm_hypercall(nr, a0, a1, a2, a3); 5965 5966 op_64_bit = is_64_bit_mode(vcpu); 5967 if (!op_64_bit) { 5968 nr &= 0xFFFFFFFF; 5969 a0 &= 0xFFFFFFFF; 5970 a1 &= 0xFFFFFFFF; 5971 a2 &= 0xFFFFFFFF; 5972 a3 &= 0xFFFFFFFF; 5973 } 5974 5975 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 5976 ret = -KVM_EPERM; 5977 goto out; 5978 } 5979 5980 switch (nr) { 5981 case KVM_HC_VAPIC_POLL_IRQ: 5982 ret = 0; 5983 break; 5984 case KVM_HC_KICK_CPU: 5985 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 5986 ret = 0; 5987 break; 5988 default: 5989 ret = -KVM_ENOSYS; 5990 break; 5991 } 5992 out: 5993 if (!op_64_bit) 5994 ret = (u32)ret; 5995 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 5996 ++vcpu->stat.hypercalls; 5997 return r; 5998 } 5999 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 6000 6001 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 6002 { 6003 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6004 char instruction[3]; 6005 unsigned long rip = kvm_rip_read(vcpu); 6006 6007 kvm_x86_ops->patch_hypercall(vcpu, instruction); 6008 6009 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); 6010 } 6011 6012 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 6013 { 6014 return vcpu->run->request_interrupt_window && 6015 likely(!pic_in_kernel(vcpu->kvm)); 6016 } 6017 6018 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 6019 { 6020 struct kvm_run *kvm_run = vcpu->run; 6021 6022 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 6023 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 6024 kvm_run->cr8 = kvm_get_cr8(vcpu); 6025 kvm_run->apic_base = kvm_get_apic_base(vcpu); 6026 kvm_run->ready_for_interrupt_injection = 6027 pic_in_kernel(vcpu->kvm) || 6028 kvm_vcpu_ready_for_interrupt_injection(vcpu); 6029 } 6030 6031 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 6032 { 6033 int max_irr, tpr; 6034 6035 if (!kvm_x86_ops->update_cr8_intercept) 6036 return; 6037 6038 if (!lapic_in_kernel(vcpu)) 6039 return; 6040 6041 if (vcpu->arch.apicv_active) 6042 return; 6043 6044 if (!vcpu->arch.apic->vapic_addr) 6045 max_irr = kvm_lapic_find_highest_irr(vcpu); 6046 else 6047 max_irr = -1; 6048 6049 if (max_irr != -1) 6050 max_irr >>= 4; 6051 6052 tpr = kvm_lapic_get_cr8(vcpu); 6053 6054 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 6055 } 6056 6057 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 6058 { 6059 int r; 6060 6061 /* try to reinject previous events if any */ 6062 if (vcpu->arch.exception.pending) { 6063 trace_kvm_inj_exception(vcpu->arch.exception.nr, 6064 vcpu->arch.exception.has_error_code, 6065 vcpu->arch.exception.error_code); 6066 6067 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 6068 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 6069 X86_EFLAGS_RF); 6070 6071 if (vcpu->arch.exception.nr == DB_VECTOR && 6072 (vcpu->arch.dr7 & DR7_GD)) { 6073 vcpu->arch.dr7 &= ~DR7_GD; 6074 kvm_update_dr7(vcpu); 6075 } 6076 6077 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, 6078 vcpu->arch.exception.has_error_code, 6079 vcpu->arch.exception.error_code, 6080 vcpu->arch.exception.reinject); 6081 return 0; 6082 } 6083 6084 if (vcpu->arch.nmi_injected) { 6085 kvm_x86_ops->set_nmi(vcpu); 6086 return 0; 6087 } 6088 6089 if (vcpu->arch.interrupt.pending) { 6090 kvm_x86_ops->set_irq(vcpu); 6091 return 0; 6092 } 6093 6094 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6095 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6096 if (r != 0) 6097 return r; 6098 } 6099 6100 /* try to inject new event if pending */ 6101 if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { 6102 --vcpu->arch.nmi_pending; 6103 vcpu->arch.nmi_injected = true; 6104 kvm_x86_ops->set_nmi(vcpu); 6105 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 6106 /* 6107 * Because interrupts can be injected asynchronously, we are 6108 * calling check_nested_events again here to avoid a race condition. 6109 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 6110 * proposal and current concerns. Perhaps we should be setting 6111 * KVM_REQ_EVENT only on certain events and not unconditionally? 6112 */ 6113 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6114 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6115 if (r != 0) 6116 return r; 6117 } 6118 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 6119 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 6120 false); 6121 kvm_x86_ops->set_irq(vcpu); 6122 } 6123 } 6124 return 0; 6125 } 6126 6127 static void process_nmi(struct kvm_vcpu *vcpu) 6128 { 6129 unsigned limit = 2; 6130 6131 /* 6132 * x86 is limited to one NMI running, and one NMI pending after it. 6133 * If an NMI is already in progress, limit further NMIs to just one. 6134 * Otherwise, allow two (and we'll inject the first one immediately). 6135 */ 6136 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 6137 limit = 1; 6138 6139 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 6140 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 6141 kvm_make_request(KVM_REQ_EVENT, vcpu); 6142 } 6143 6144 #define put_smstate(type, buf, offset, val) \ 6145 *(type *)((buf) + (offset) - 0x7e00) = val 6146 6147 static u32 process_smi_get_segment_flags(struct kvm_segment *seg) 6148 { 6149 u32 flags = 0; 6150 flags |= seg->g << 23; 6151 flags |= seg->db << 22; 6152 flags |= seg->l << 21; 6153 flags |= seg->avl << 20; 6154 flags |= seg->present << 15; 6155 flags |= seg->dpl << 13; 6156 flags |= seg->s << 12; 6157 flags |= seg->type << 8; 6158 return flags; 6159 } 6160 6161 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 6162 { 6163 struct kvm_segment seg; 6164 int offset; 6165 6166 kvm_get_segment(vcpu, &seg, n); 6167 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 6168 6169 if (n < 3) 6170 offset = 0x7f84 + n * 12; 6171 else 6172 offset = 0x7f2c + (n - 3) * 12; 6173 6174 put_smstate(u32, buf, offset + 8, seg.base); 6175 put_smstate(u32, buf, offset + 4, seg.limit); 6176 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg)); 6177 } 6178 6179 #ifdef CONFIG_X86_64 6180 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 6181 { 6182 struct kvm_segment seg; 6183 int offset; 6184 u16 flags; 6185 6186 kvm_get_segment(vcpu, &seg, n); 6187 offset = 0x7e00 + n * 16; 6188 6189 flags = process_smi_get_segment_flags(&seg) >> 8; 6190 put_smstate(u16, buf, offset, seg.selector); 6191 put_smstate(u16, buf, offset + 2, flags); 6192 put_smstate(u32, buf, offset + 4, seg.limit); 6193 put_smstate(u64, buf, offset + 8, seg.base); 6194 } 6195 #endif 6196 6197 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf) 6198 { 6199 struct desc_ptr dt; 6200 struct kvm_segment seg; 6201 unsigned long val; 6202 int i; 6203 6204 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 6205 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 6206 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 6207 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 6208 6209 for (i = 0; i < 8; i++) 6210 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 6211 6212 kvm_get_dr(vcpu, 6, &val); 6213 put_smstate(u32, buf, 0x7fcc, (u32)val); 6214 kvm_get_dr(vcpu, 7, &val); 6215 put_smstate(u32, buf, 0x7fc8, (u32)val); 6216 6217 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6218 put_smstate(u32, buf, 0x7fc4, seg.selector); 6219 put_smstate(u32, buf, 0x7f64, seg.base); 6220 put_smstate(u32, buf, 0x7f60, seg.limit); 6221 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg)); 6222 6223 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6224 put_smstate(u32, buf, 0x7fc0, seg.selector); 6225 put_smstate(u32, buf, 0x7f80, seg.base); 6226 put_smstate(u32, buf, 0x7f7c, seg.limit); 6227 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg)); 6228 6229 kvm_x86_ops->get_gdt(vcpu, &dt); 6230 put_smstate(u32, buf, 0x7f74, dt.address); 6231 put_smstate(u32, buf, 0x7f70, dt.size); 6232 6233 kvm_x86_ops->get_idt(vcpu, &dt); 6234 put_smstate(u32, buf, 0x7f58, dt.address); 6235 put_smstate(u32, buf, 0x7f54, dt.size); 6236 6237 for (i = 0; i < 6; i++) 6238 process_smi_save_seg_32(vcpu, buf, i); 6239 6240 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 6241 6242 /* revision id */ 6243 put_smstate(u32, buf, 0x7efc, 0x00020000); 6244 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 6245 } 6246 6247 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf) 6248 { 6249 #ifdef CONFIG_X86_64 6250 struct desc_ptr dt; 6251 struct kvm_segment seg; 6252 unsigned long val; 6253 int i; 6254 6255 for (i = 0; i < 16; i++) 6256 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 6257 6258 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 6259 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 6260 6261 kvm_get_dr(vcpu, 6, &val); 6262 put_smstate(u64, buf, 0x7f68, val); 6263 kvm_get_dr(vcpu, 7, &val); 6264 put_smstate(u64, buf, 0x7f60, val); 6265 6266 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 6267 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 6268 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 6269 6270 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 6271 6272 /* revision id */ 6273 put_smstate(u32, buf, 0x7efc, 0x00020064); 6274 6275 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 6276 6277 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6278 put_smstate(u16, buf, 0x7e90, seg.selector); 6279 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8); 6280 put_smstate(u32, buf, 0x7e94, seg.limit); 6281 put_smstate(u64, buf, 0x7e98, seg.base); 6282 6283 kvm_x86_ops->get_idt(vcpu, &dt); 6284 put_smstate(u32, buf, 0x7e84, dt.size); 6285 put_smstate(u64, buf, 0x7e88, dt.address); 6286 6287 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6288 put_smstate(u16, buf, 0x7e70, seg.selector); 6289 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8); 6290 put_smstate(u32, buf, 0x7e74, seg.limit); 6291 put_smstate(u64, buf, 0x7e78, seg.base); 6292 6293 kvm_x86_ops->get_gdt(vcpu, &dt); 6294 put_smstate(u32, buf, 0x7e64, dt.size); 6295 put_smstate(u64, buf, 0x7e68, dt.address); 6296 6297 for (i = 0; i < 6; i++) 6298 process_smi_save_seg_64(vcpu, buf, i); 6299 #else 6300 WARN_ON_ONCE(1); 6301 #endif 6302 } 6303 6304 static void process_smi(struct kvm_vcpu *vcpu) 6305 { 6306 struct kvm_segment cs, ds; 6307 struct desc_ptr dt; 6308 char buf[512]; 6309 u32 cr0; 6310 6311 if (is_smm(vcpu)) { 6312 vcpu->arch.smi_pending = true; 6313 return; 6314 } 6315 6316 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 6317 vcpu->arch.hflags |= HF_SMM_MASK; 6318 memset(buf, 0, 512); 6319 if (guest_cpuid_has_longmode(vcpu)) 6320 process_smi_save_state_64(vcpu, buf); 6321 else 6322 process_smi_save_state_32(vcpu, buf); 6323 6324 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 6325 6326 if (kvm_x86_ops->get_nmi_mask(vcpu)) 6327 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 6328 else 6329 kvm_x86_ops->set_nmi_mask(vcpu, true); 6330 6331 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 6332 kvm_rip_write(vcpu, 0x8000); 6333 6334 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 6335 kvm_x86_ops->set_cr0(vcpu, cr0); 6336 vcpu->arch.cr0 = cr0; 6337 6338 kvm_x86_ops->set_cr4(vcpu, 0); 6339 6340 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 6341 dt.address = dt.size = 0; 6342 kvm_x86_ops->set_idt(vcpu, &dt); 6343 6344 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 6345 6346 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 6347 cs.base = vcpu->arch.smbase; 6348 6349 ds.selector = 0; 6350 ds.base = 0; 6351 6352 cs.limit = ds.limit = 0xffffffff; 6353 cs.type = ds.type = 0x3; 6354 cs.dpl = ds.dpl = 0; 6355 cs.db = ds.db = 0; 6356 cs.s = ds.s = 1; 6357 cs.l = ds.l = 0; 6358 cs.g = ds.g = 1; 6359 cs.avl = ds.avl = 0; 6360 cs.present = ds.present = 1; 6361 cs.unusable = ds.unusable = 0; 6362 cs.padding = ds.padding = 0; 6363 6364 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 6365 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 6366 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 6367 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 6368 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 6369 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 6370 6371 if (guest_cpuid_has_longmode(vcpu)) 6372 kvm_x86_ops->set_efer(vcpu, 0); 6373 6374 kvm_update_cpuid(vcpu); 6375 kvm_mmu_reset_context(vcpu); 6376 } 6377 6378 void kvm_make_scan_ioapic_request(struct kvm *kvm) 6379 { 6380 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 6381 } 6382 6383 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 6384 { 6385 u64 eoi_exit_bitmap[4]; 6386 6387 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 6388 return; 6389 6390 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 6391 6392 if (irqchip_split(vcpu->kvm)) 6393 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 6394 else { 6395 if (vcpu->arch.apicv_active) 6396 kvm_x86_ops->sync_pir_to_irr(vcpu); 6397 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 6398 } 6399 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, 6400 vcpu_to_synic(vcpu)->vec_bitmap, 256); 6401 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 6402 } 6403 6404 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) 6405 { 6406 ++vcpu->stat.tlb_flush; 6407 kvm_x86_ops->tlb_flush(vcpu); 6408 } 6409 6410 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 6411 { 6412 struct page *page = NULL; 6413 6414 if (!lapic_in_kernel(vcpu)) 6415 return; 6416 6417 if (!kvm_x86_ops->set_apic_access_page_addr) 6418 return; 6419 6420 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 6421 if (is_error_page(page)) 6422 return; 6423 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 6424 6425 /* 6426 * Do not pin apic access page in memory, the MMU notifier 6427 * will call us again if it is migrated or swapped out. 6428 */ 6429 put_page(page); 6430 } 6431 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 6432 6433 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, 6434 unsigned long address) 6435 { 6436 /* 6437 * The physical address of apic access page is stored in the VMCS. 6438 * Update it when it becomes invalid. 6439 */ 6440 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT)) 6441 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 6442 } 6443 6444 /* 6445 * Returns 1 to let vcpu_run() continue the guest execution loop without 6446 * exiting to the userspace. Otherwise, the value will be returned to the 6447 * userspace. 6448 */ 6449 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 6450 { 6451 int r; 6452 bool req_int_win = 6453 dm_request_for_irq_injection(vcpu) && 6454 kvm_cpu_accept_dm_intr(vcpu); 6455 6456 bool req_immediate_exit = false; 6457 6458 if (vcpu->requests) { 6459 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 6460 kvm_mmu_unload(vcpu); 6461 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 6462 __kvm_migrate_timers(vcpu); 6463 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 6464 kvm_gen_update_masterclock(vcpu->kvm); 6465 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 6466 kvm_gen_kvmclock_update(vcpu); 6467 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 6468 r = kvm_guest_time_update(vcpu); 6469 if (unlikely(r)) 6470 goto out; 6471 } 6472 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 6473 kvm_mmu_sync_roots(vcpu); 6474 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 6475 kvm_vcpu_flush_tlb(vcpu); 6476 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 6477 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 6478 r = 0; 6479 goto out; 6480 } 6481 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 6482 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 6483 r = 0; 6484 goto out; 6485 } 6486 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { 6487 vcpu->fpu_active = 0; 6488 kvm_x86_ops->fpu_deactivate(vcpu); 6489 } 6490 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 6491 /* Page is swapped out. Do synthetic halt */ 6492 vcpu->arch.apf.halted = true; 6493 r = 1; 6494 goto out; 6495 } 6496 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 6497 record_steal_time(vcpu); 6498 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 6499 process_smi(vcpu); 6500 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 6501 process_nmi(vcpu); 6502 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 6503 kvm_pmu_handle_event(vcpu); 6504 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 6505 kvm_pmu_deliver_pmi(vcpu); 6506 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 6507 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 6508 if (test_bit(vcpu->arch.pending_ioapic_eoi, 6509 vcpu->arch.ioapic_handled_vectors)) { 6510 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 6511 vcpu->run->eoi.vector = 6512 vcpu->arch.pending_ioapic_eoi; 6513 r = 0; 6514 goto out; 6515 } 6516 } 6517 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 6518 vcpu_scan_ioapic(vcpu); 6519 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 6520 kvm_vcpu_reload_apic_access_page(vcpu); 6521 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 6522 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 6523 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 6524 r = 0; 6525 goto out; 6526 } 6527 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 6528 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 6529 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 6530 r = 0; 6531 goto out; 6532 } 6533 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 6534 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 6535 vcpu->run->hyperv = vcpu->arch.hyperv.exit; 6536 r = 0; 6537 goto out; 6538 } 6539 6540 /* 6541 * KVM_REQ_HV_STIMER has to be processed after 6542 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 6543 * depend on the guest clock being up-to-date 6544 */ 6545 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 6546 kvm_hv_process_stimers(vcpu); 6547 } 6548 6549 /* 6550 * KVM_REQ_EVENT is not set when posted interrupts are set by 6551 * VT-d hardware, so we have to update RVI unconditionally. 6552 */ 6553 if (kvm_lapic_enabled(vcpu)) { 6554 /* 6555 * Update architecture specific hints for APIC 6556 * virtual interrupt delivery. 6557 */ 6558 if (vcpu->arch.apicv_active) 6559 kvm_x86_ops->hwapic_irr_update(vcpu, 6560 kvm_lapic_find_highest_irr(vcpu)); 6561 } 6562 6563 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 6564 kvm_apic_accept_events(vcpu); 6565 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 6566 r = 1; 6567 goto out; 6568 } 6569 6570 if (inject_pending_event(vcpu, req_int_win) != 0) 6571 req_immediate_exit = true; 6572 /* enable NMI/IRQ window open exits if needed */ 6573 else { 6574 if (vcpu->arch.nmi_pending) 6575 kvm_x86_ops->enable_nmi_window(vcpu); 6576 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 6577 kvm_x86_ops->enable_irq_window(vcpu); 6578 } 6579 6580 if (kvm_lapic_enabled(vcpu)) { 6581 update_cr8_intercept(vcpu); 6582 kvm_lapic_sync_to_vapic(vcpu); 6583 } 6584 } 6585 6586 r = kvm_mmu_reload(vcpu); 6587 if (unlikely(r)) { 6588 goto cancel_injection; 6589 } 6590 6591 preempt_disable(); 6592 6593 kvm_x86_ops->prepare_guest_switch(vcpu); 6594 if (vcpu->fpu_active) 6595 kvm_load_guest_fpu(vcpu); 6596 vcpu->mode = IN_GUEST_MODE; 6597 6598 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6599 6600 /* 6601 * We should set ->mode before check ->requests, 6602 * Please see the comment in kvm_make_all_cpus_request. 6603 * This also orders the write to mode from any reads 6604 * to the page tables done while the VCPU is running. 6605 * Please see the comment in kvm_flush_remote_tlbs. 6606 */ 6607 smp_mb__after_srcu_read_unlock(); 6608 6609 local_irq_disable(); 6610 6611 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests 6612 || need_resched() || signal_pending(current)) { 6613 vcpu->mode = OUTSIDE_GUEST_MODE; 6614 smp_wmb(); 6615 local_irq_enable(); 6616 preempt_enable(); 6617 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6618 r = 1; 6619 goto cancel_injection; 6620 } 6621 6622 kvm_load_guest_xcr0(vcpu); 6623 6624 if (req_immediate_exit) 6625 smp_send_reschedule(vcpu->cpu); 6626 6627 trace_kvm_entry(vcpu->vcpu_id); 6628 wait_lapic_expire(vcpu); 6629 __kvm_guest_enter(); 6630 6631 if (unlikely(vcpu->arch.switch_db_regs)) { 6632 set_debugreg(0, 7); 6633 set_debugreg(vcpu->arch.eff_db[0], 0); 6634 set_debugreg(vcpu->arch.eff_db[1], 1); 6635 set_debugreg(vcpu->arch.eff_db[2], 2); 6636 set_debugreg(vcpu->arch.eff_db[3], 3); 6637 set_debugreg(vcpu->arch.dr6, 6); 6638 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 6639 } 6640 6641 kvm_x86_ops->run(vcpu); 6642 6643 /* 6644 * Do this here before restoring debug registers on the host. And 6645 * since we do this before handling the vmexit, a DR access vmexit 6646 * can (a) read the correct value of the debug registers, (b) set 6647 * KVM_DEBUGREG_WONT_EXIT again. 6648 */ 6649 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 6650 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 6651 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 6652 kvm_update_dr0123(vcpu); 6653 kvm_update_dr6(vcpu); 6654 kvm_update_dr7(vcpu); 6655 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 6656 } 6657 6658 /* 6659 * If the guest has used debug registers, at least dr7 6660 * will be disabled while returning to the host. 6661 * If we don't have active breakpoints in the host, we don't 6662 * care about the messed up debug address registers. But if 6663 * we have some of them active, restore the old state. 6664 */ 6665 if (hw_breakpoint_active()) 6666 hw_breakpoint_restore(); 6667 6668 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 6669 6670 vcpu->mode = OUTSIDE_GUEST_MODE; 6671 smp_wmb(); 6672 6673 kvm_put_guest_xcr0(vcpu); 6674 6675 /* Interrupt is enabled by handle_external_intr() */ 6676 kvm_x86_ops->handle_external_intr(vcpu); 6677 6678 ++vcpu->stat.exits; 6679 6680 /* 6681 * We must have an instruction between local_irq_enable() and 6682 * kvm_guest_exit(), so the timer interrupt isn't delayed by 6683 * the interrupt shadow. The stat.exits increment will do nicely. 6684 * But we need to prevent reordering, hence this barrier(): 6685 */ 6686 barrier(); 6687 6688 kvm_guest_exit(); 6689 6690 preempt_enable(); 6691 6692 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6693 6694 /* 6695 * Profile KVM exit RIPs: 6696 */ 6697 if (unlikely(prof_on == KVM_PROFILING)) { 6698 unsigned long rip = kvm_rip_read(vcpu); 6699 profile_hit(KVM_PROFILING, (void *)rip); 6700 } 6701 6702 if (unlikely(vcpu->arch.tsc_always_catchup)) 6703 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6704 6705 if (vcpu->arch.apic_attention) 6706 kvm_lapic_sync_from_vapic(vcpu); 6707 6708 r = kvm_x86_ops->handle_exit(vcpu); 6709 return r; 6710 6711 cancel_injection: 6712 kvm_x86_ops->cancel_injection(vcpu); 6713 if (unlikely(vcpu->arch.apic_attention)) 6714 kvm_lapic_sync_from_vapic(vcpu); 6715 out: 6716 return r; 6717 } 6718 6719 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 6720 { 6721 if (!kvm_arch_vcpu_runnable(vcpu) && 6722 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { 6723 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6724 kvm_vcpu_block(vcpu); 6725 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6726 6727 if (kvm_x86_ops->post_block) 6728 kvm_x86_ops->post_block(vcpu); 6729 6730 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 6731 return 1; 6732 } 6733 6734 kvm_apic_accept_events(vcpu); 6735 switch(vcpu->arch.mp_state) { 6736 case KVM_MP_STATE_HALTED: 6737 vcpu->arch.pv.pv_unhalted = false; 6738 vcpu->arch.mp_state = 6739 KVM_MP_STATE_RUNNABLE; 6740 case KVM_MP_STATE_RUNNABLE: 6741 vcpu->arch.apf.halted = false; 6742 break; 6743 case KVM_MP_STATE_INIT_RECEIVED: 6744 break; 6745 default: 6746 return -EINTR; 6747 break; 6748 } 6749 return 1; 6750 } 6751 6752 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 6753 { 6754 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 6755 !vcpu->arch.apf.halted); 6756 } 6757 6758 static int vcpu_run(struct kvm_vcpu *vcpu) 6759 { 6760 int r; 6761 struct kvm *kvm = vcpu->kvm; 6762 6763 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6764 6765 for (;;) { 6766 if (kvm_vcpu_running(vcpu)) { 6767 r = vcpu_enter_guest(vcpu); 6768 } else { 6769 r = vcpu_block(kvm, vcpu); 6770 } 6771 6772 if (r <= 0) 6773 break; 6774 6775 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); 6776 if (kvm_cpu_has_pending_timer(vcpu)) 6777 kvm_inject_pending_timer_irqs(vcpu); 6778 6779 if (dm_request_for_irq_injection(vcpu) && 6780 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 6781 r = 0; 6782 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 6783 ++vcpu->stat.request_irq_exits; 6784 break; 6785 } 6786 6787 kvm_check_async_pf_completion(vcpu); 6788 6789 if (signal_pending(current)) { 6790 r = -EINTR; 6791 vcpu->run->exit_reason = KVM_EXIT_INTR; 6792 ++vcpu->stat.signal_exits; 6793 break; 6794 } 6795 if (need_resched()) { 6796 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6797 cond_resched(); 6798 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6799 } 6800 } 6801 6802 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6803 6804 return r; 6805 } 6806 6807 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 6808 { 6809 int r; 6810 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6811 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 6812 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6813 if (r != EMULATE_DONE) 6814 return 0; 6815 return 1; 6816 } 6817 6818 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 6819 { 6820 BUG_ON(!vcpu->arch.pio.count); 6821 6822 return complete_emulated_io(vcpu); 6823 } 6824 6825 /* 6826 * Implements the following, as a state machine: 6827 * 6828 * read: 6829 * for each fragment 6830 * for each mmio piece in the fragment 6831 * write gpa, len 6832 * exit 6833 * copy data 6834 * execute insn 6835 * 6836 * write: 6837 * for each fragment 6838 * for each mmio piece in the fragment 6839 * write gpa, len 6840 * copy data 6841 * exit 6842 */ 6843 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 6844 { 6845 struct kvm_run *run = vcpu->run; 6846 struct kvm_mmio_fragment *frag; 6847 unsigned len; 6848 6849 BUG_ON(!vcpu->mmio_needed); 6850 6851 /* Complete previous fragment */ 6852 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 6853 len = min(8u, frag->len); 6854 if (!vcpu->mmio_is_write) 6855 memcpy(frag->data, run->mmio.data, len); 6856 6857 if (frag->len <= 8) { 6858 /* Switch to the next fragment. */ 6859 frag++; 6860 vcpu->mmio_cur_fragment++; 6861 } else { 6862 /* Go forward to the next mmio piece. */ 6863 frag->data += len; 6864 frag->gpa += len; 6865 frag->len -= len; 6866 } 6867 6868 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 6869 vcpu->mmio_needed = 0; 6870 6871 /* FIXME: return into emulator if single-stepping. */ 6872 if (vcpu->mmio_is_write) 6873 return 1; 6874 vcpu->mmio_read_completed = 1; 6875 return complete_emulated_io(vcpu); 6876 } 6877 6878 run->exit_reason = KVM_EXIT_MMIO; 6879 run->mmio.phys_addr = frag->gpa; 6880 if (vcpu->mmio_is_write) 6881 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 6882 run->mmio.len = min(8u, frag->len); 6883 run->mmio.is_write = vcpu->mmio_is_write; 6884 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6885 return 0; 6886 } 6887 6888 6889 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 6890 { 6891 struct fpu *fpu = ¤t->thread.fpu; 6892 int r; 6893 sigset_t sigsaved; 6894 6895 fpu__activate_curr(fpu); 6896 6897 if (vcpu->sigset_active) 6898 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); 6899 6900 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 6901 kvm_vcpu_block(vcpu); 6902 kvm_apic_accept_events(vcpu); 6903 clear_bit(KVM_REQ_UNHALT, &vcpu->requests); 6904 r = -EAGAIN; 6905 goto out; 6906 } 6907 6908 /* re-sync apic's tpr */ 6909 if (!lapic_in_kernel(vcpu)) { 6910 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 6911 r = -EINVAL; 6912 goto out; 6913 } 6914 } 6915 6916 if (unlikely(vcpu->arch.complete_userspace_io)) { 6917 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 6918 vcpu->arch.complete_userspace_io = NULL; 6919 r = cui(vcpu); 6920 if (r <= 0) 6921 goto out; 6922 } else 6923 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 6924 6925 r = vcpu_run(vcpu); 6926 6927 out: 6928 post_kvm_run_save(vcpu); 6929 if (vcpu->sigset_active) 6930 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 6931 6932 return r; 6933 } 6934 6935 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6936 { 6937 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 6938 /* 6939 * We are here if userspace calls get_regs() in the middle of 6940 * instruction emulation. Registers state needs to be copied 6941 * back from emulation context to vcpu. Userspace shouldn't do 6942 * that usually, but some bad designed PV devices (vmware 6943 * backdoor interface) need this to work 6944 */ 6945 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 6946 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6947 } 6948 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 6949 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 6950 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 6951 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 6952 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 6953 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 6954 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 6955 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 6956 #ifdef CONFIG_X86_64 6957 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 6958 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 6959 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 6960 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 6961 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 6962 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 6963 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 6964 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 6965 #endif 6966 6967 regs->rip = kvm_rip_read(vcpu); 6968 regs->rflags = kvm_get_rflags(vcpu); 6969 6970 return 0; 6971 } 6972 6973 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6974 { 6975 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 6976 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6977 6978 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 6979 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 6980 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 6981 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 6982 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 6983 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 6984 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 6985 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 6986 #ifdef CONFIG_X86_64 6987 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 6988 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 6989 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 6990 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 6991 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 6992 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 6993 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 6994 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 6995 #endif 6996 6997 kvm_rip_write(vcpu, regs->rip); 6998 kvm_set_rflags(vcpu, regs->rflags); 6999 7000 vcpu->arch.exception.pending = false; 7001 7002 kvm_make_request(KVM_REQ_EVENT, vcpu); 7003 7004 return 0; 7005 } 7006 7007 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 7008 { 7009 struct kvm_segment cs; 7010 7011 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7012 *db = cs.db; 7013 *l = cs.l; 7014 } 7015 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 7016 7017 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 7018 struct kvm_sregs *sregs) 7019 { 7020 struct desc_ptr dt; 7021 7022 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7023 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7024 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7025 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7026 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7027 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7028 7029 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7030 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7031 7032 kvm_x86_ops->get_idt(vcpu, &dt); 7033 sregs->idt.limit = dt.size; 7034 sregs->idt.base = dt.address; 7035 kvm_x86_ops->get_gdt(vcpu, &dt); 7036 sregs->gdt.limit = dt.size; 7037 sregs->gdt.base = dt.address; 7038 7039 sregs->cr0 = kvm_read_cr0(vcpu); 7040 sregs->cr2 = vcpu->arch.cr2; 7041 sregs->cr3 = kvm_read_cr3(vcpu); 7042 sregs->cr4 = kvm_read_cr4(vcpu); 7043 sregs->cr8 = kvm_get_cr8(vcpu); 7044 sregs->efer = vcpu->arch.efer; 7045 sregs->apic_base = kvm_get_apic_base(vcpu); 7046 7047 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 7048 7049 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) 7050 set_bit(vcpu->arch.interrupt.nr, 7051 (unsigned long *)sregs->interrupt_bitmap); 7052 7053 return 0; 7054 } 7055 7056 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 7057 struct kvm_mp_state *mp_state) 7058 { 7059 kvm_apic_accept_events(vcpu); 7060 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 7061 vcpu->arch.pv.pv_unhalted) 7062 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 7063 else 7064 mp_state->mp_state = vcpu->arch.mp_state; 7065 7066 return 0; 7067 } 7068 7069 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 7070 struct kvm_mp_state *mp_state) 7071 { 7072 if (!lapic_in_kernel(vcpu) && 7073 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 7074 return -EINVAL; 7075 7076 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 7077 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 7078 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 7079 } else 7080 vcpu->arch.mp_state = mp_state->mp_state; 7081 kvm_make_request(KVM_REQ_EVENT, vcpu); 7082 return 0; 7083 } 7084 7085 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 7086 int reason, bool has_error_code, u32 error_code) 7087 { 7088 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 7089 int ret; 7090 7091 init_emulate_ctxt(vcpu); 7092 7093 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 7094 has_error_code, error_code); 7095 7096 if (ret) 7097 return EMULATE_FAIL; 7098 7099 kvm_rip_write(vcpu, ctxt->eip); 7100 kvm_set_rflags(vcpu, ctxt->eflags); 7101 kvm_make_request(KVM_REQ_EVENT, vcpu); 7102 return EMULATE_DONE; 7103 } 7104 EXPORT_SYMBOL_GPL(kvm_task_switch); 7105 7106 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 7107 struct kvm_sregs *sregs) 7108 { 7109 struct msr_data apic_base_msr; 7110 int mmu_reset_needed = 0; 7111 int pending_vec, max_bits, idx; 7112 struct desc_ptr dt; 7113 7114 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) 7115 return -EINVAL; 7116 7117 dt.size = sregs->idt.limit; 7118 dt.address = sregs->idt.base; 7119 kvm_x86_ops->set_idt(vcpu, &dt); 7120 dt.size = sregs->gdt.limit; 7121 dt.address = sregs->gdt.base; 7122 kvm_x86_ops->set_gdt(vcpu, &dt); 7123 7124 vcpu->arch.cr2 = sregs->cr2; 7125 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 7126 vcpu->arch.cr3 = sregs->cr3; 7127 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 7128 7129 kvm_set_cr8(vcpu, sregs->cr8); 7130 7131 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 7132 kvm_x86_ops->set_efer(vcpu, sregs->efer); 7133 apic_base_msr.data = sregs->apic_base; 7134 apic_base_msr.host_initiated = true; 7135 kvm_set_apic_base(vcpu, &apic_base_msr); 7136 7137 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 7138 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 7139 vcpu->arch.cr0 = sregs->cr0; 7140 7141 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 7142 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 7143 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 7144 kvm_update_cpuid(vcpu); 7145 7146 idx = srcu_read_lock(&vcpu->kvm->srcu); 7147 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 7148 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 7149 mmu_reset_needed = 1; 7150 } 7151 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7152 7153 if (mmu_reset_needed) 7154 kvm_mmu_reset_context(vcpu); 7155 7156 max_bits = KVM_NR_INTERRUPTS; 7157 pending_vec = find_first_bit( 7158 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 7159 if (pending_vec < max_bits) { 7160 kvm_queue_interrupt(vcpu, pending_vec, false); 7161 pr_debug("Set back pending irq %d\n", pending_vec); 7162 } 7163 7164 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7165 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7166 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7167 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7168 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7169 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7170 7171 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7172 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7173 7174 update_cr8_intercept(vcpu); 7175 7176 /* Older userspace won't unhalt the vcpu on reset. */ 7177 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 7178 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 7179 !is_protmode(vcpu)) 7180 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7181 7182 kvm_make_request(KVM_REQ_EVENT, vcpu); 7183 7184 return 0; 7185 } 7186 7187 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 7188 struct kvm_guest_debug *dbg) 7189 { 7190 unsigned long rflags; 7191 int i, r; 7192 7193 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 7194 r = -EBUSY; 7195 if (vcpu->arch.exception.pending) 7196 goto out; 7197 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 7198 kvm_queue_exception(vcpu, DB_VECTOR); 7199 else 7200 kvm_queue_exception(vcpu, BP_VECTOR); 7201 } 7202 7203 /* 7204 * Read rflags as long as potentially injected trace flags are still 7205 * filtered out. 7206 */ 7207 rflags = kvm_get_rflags(vcpu); 7208 7209 vcpu->guest_debug = dbg->control; 7210 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 7211 vcpu->guest_debug = 0; 7212 7213 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 7214 for (i = 0; i < KVM_NR_DB_REGS; ++i) 7215 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 7216 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 7217 } else { 7218 for (i = 0; i < KVM_NR_DB_REGS; i++) 7219 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 7220 } 7221 kvm_update_dr7(vcpu); 7222 7223 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 7224 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 7225 get_segment_base(vcpu, VCPU_SREG_CS); 7226 7227 /* 7228 * Trigger an rflags update that will inject or remove the trace 7229 * flags. 7230 */ 7231 kvm_set_rflags(vcpu, rflags); 7232 7233 kvm_x86_ops->update_bp_intercept(vcpu); 7234 7235 r = 0; 7236 7237 out: 7238 7239 return r; 7240 } 7241 7242 /* 7243 * Translate a guest virtual address to a guest physical address. 7244 */ 7245 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 7246 struct kvm_translation *tr) 7247 { 7248 unsigned long vaddr = tr->linear_address; 7249 gpa_t gpa; 7250 int idx; 7251 7252 idx = srcu_read_lock(&vcpu->kvm->srcu); 7253 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 7254 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7255 tr->physical_address = gpa; 7256 tr->valid = gpa != UNMAPPED_GVA; 7257 tr->writeable = 1; 7258 tr->usermode = 0; 7259 7260 return 0; 7261 } 7262 7263 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7264 { 7265 struct fxregs_state *fxsave = 7266 &vcpu->arch.guest_fpu.state.fxsave; 7267 7268 memcpy(fpu->fpr, fxsave->st_space, 128); 7269 fpu->fcw = fxsave->cwd; 7270 fpu->fsw = fxsave->swd; 7271 fpu->ftwx = fxsave->twd; 7272 fpu->last_opcode = fxsave->fop; 7273 fpu->last_ip = fxsave->rip; 7274 fpu->last_dp = fxsave->rdp; 7275 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 7276 7277 return 0; 7278 } 7279 7280 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7281 { 7282 struct fxregs_state *fxsave = 7283 &vcpu->arch.guest_fpu.state.fxsave; 7284 7285 memcpy(fxsave->st_space, fpu->fpr, 128); 7286 fxsave->cwd = fpu->fcw; 7287 fxsave->swd = fpu->fsw; 7288 fxsave->twd = fpu->ftwx; 7289 fxsave->fop = fpu->last_opcode; 7290 fxsave->rip = fpu->last_ip; 7291 fxsave->rdp = fpu->last_dp; 7292 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 7293 7294 return 0; 7295 } 7296 7297 static void fx_init(struct kvm_vcpu *vcpu) 7298 { 7299 fpstate_init(&vcpu->arch.guest_fpu.state); 7300 if (boot_cpu_has(X86_FEATURE_XSAVES)) 7301 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv = 7302 host_xcr0 | XSTATE_COMPACTION_ENABLED; 7303 7304 /* 7305 * Ensure guest xcr0 is valid for loading 7306 */ 7307 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 7308 7309 vcpu->arch.cr0 |= X86_CR0_ET; 7310 } 7311 7312 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 7313 { 7314 if (vcpu->guest_fpu_loaded) 7315 return; 7316 7317 /* 7318 * Restore all possible states in the guest, 7319 * and assume host would use all available bits. 7320 * Guest xcr0 would be loaded later. 7321 */ 7322 vcpu->guest_fpu_loaded = 1; 7323 __kernel_fpu_begin(); 7324 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state); 7325 trace_kvm_fpu(1); 7326 } 7327 7328 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 7329 { 7330 if (!vcpu->guest_fpu_loaded) { 7331 vcpu->fpu_counter = 0; 7332 return; 7333 } 7334 7335 vcpu->guest_fpu_loaded = 0; 7336 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu); 7337 __kernel_fpu_end(); 7338 ++vcpu->stat.fpu_reload; 7339 /* 7340 * If using eager FPU mode, or if the guest is a frequent user 7341 * of the FPU, just leave the FPU active for next time. 7342 * Every 255 times fpu_counter rolls over to 0; a guest that uses 7343 * the FPU in bursts will revert to loading it on demand. 7344 */ 7345 if (!use_eager_fpu()) { 7346 if (++vcpu->fpu_counter < 5) 7347 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); 7348 } 7349 trace_kvm_fpu(0); 7350 } 7351 7352 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 7353 { 7354 kvmclock_reset(vcpu); 7355 7356 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 7357 kvm_x86_ops->vcpu_free(vcpu); 7358 } 7359 7360 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 7361 unsigned int id) 7362 { 7363 struct kvm_vcpu *vcpu; 7364 7365 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 7366 printk_once(KERN_WARNING 7367 "kvm: SMP vm created on host with unstable TSC; " 7368 "guest TSC will not be reliable\n"); 7369 7370 vcpu = kvm_x86_ops->vcpu_create(kvm, id); 7371 7372 return vcpu; 7373 } 7374 7375 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 7376 { 7377 int r; 7378 7379 kvm_vcpu_mtrr_init(vcpu); 7380 r = vcpu_load(vcpu); 7381 if (r) 7382 return r; 7383 kvm_vcpu_reset(vcpu, false); 7384 kvm_mmu_setup(vcpu); 7385 vcpu_put(vcpu); 7386 return r; 7387 } 7388 7389 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 7390 { 7391 struct msr_data msr; 7392 struct kvm *kvm = vcpu->kvm; 7393 7394 if (vcpu_load(vcpu)) 7395 return; 7396 msr.data = 0x0; 7397 msr.index = MSR_IA32_TSC; 7398 msr.host_initiated = true; 7399 kvm_write_tsc(vcpu, &msr); 7400 vcpu_put(vcpu); 7401 7402 if (!kvmclock_periodic_sync) 7403 return; 7404 7405 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 7406 KVMCLOCK_SYNC_PERIOD); 7407 } 7408 7409 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 7410 { 7411 int r; 7412 vcpu->arch.apf.msr_val = 0; 7413 7414 r = vcpu_load(vcpu); 7415 BUG_ON(r); 7416 kvm_mmu_unload(vcpu); 7417 vcpu_put(vcpu); 7418 7419 kvm_x86_ops->vcpu_free(vcpu); 7420 } 7421 7422 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 7423 { 7424 vcpu->arch.hflags = 0; 7425 7426 atomic_set(&vcpu->arch.nmi_queued, 0); 7427 vcpu->arch.nmi_pending = 0; 7428 vcpu->arch.nmi_injected = false; 7429 kvm_clear_interrupt_queue(vcpu); 7430 kvm_clear_exception_queue(vcpu); 7431 7432 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 7433 kvm_update_dr0123(vcpu); 7434 vcpu->arch.dr6 = DR6_INIT; 7435 kvm_update_dr6(vcpu); 7436 vcpu->arch.dr7 = DR7_FIXED_1; 7437 kvm_update_dr7(vcpu); 7438 7439 vcpu->arch.cr2 = 0; 7440 7441 kvm_make_request(KVM_REQ_EVENT, vcpu); 7442 vcpu->arch.apf.msr_val = 0; 7443 vcpu->arch.st.msr_val = 0; 7444 7445 kvmclock_reset(vcpu); 7446 7447 kvm_clear_async_pf_completion_queue(vcpu); 7448 kvm_async_pf_hash_reset(vcpu); 7449 vcpu->arch.apf.halted = false; 7450 7451 if (!init_event) { 7452 kvm_pmu_reset(vcpu); 7453 vcpu->arch.smbase = 0x30000; 7454 } 7455 7456 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 7457 vcpu->arch.regs_avail = ~0; 7458 vcpu->arch.regs_dirty = ~0; 7459 7460 kvm_x86_ops->vcpu_reset(vcpu, init_event); 7461 } 7462 7463 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 7464 { 7465 struct kvm_segment cs; 7466 7467 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7468 cs.selector = vector << 8; 7469 cs.base = vector << 12; 7470 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7471 kvm_rip_write(vcpu, 0); 7472 } 7473 7474 int kvm_arch_hardware_enable(void) 7475 { 7476 struct kvm *kvm; 7477 struct kvm_vcpu *vcpu; 7478 int i; 7479 int ret; 7480 u64 local_tsc; 7481 u64 max_tsc = 0; 7482 bool stable, backwards_tsc = false; 7483 7484 kvm_shared_msr_cpu_online(); 7485 ret = kvm_x86_ops->hardware_enable(); 7486 if (ret != 0) 7487 return ret; 7488 7489 local_tsc = rdtsc(); 7490 stable = !check_tsc_unstable(); 7491 list_for_each_entry(kvm, &vm_list, vm_list) { 7492 kvm_for_each_vcpu(i, vcpu, kvm) { 7493 if (!stable && vcpu->cpu == smp_processor_id()) 7494 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7495 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 7496 backwards_tsc = true; 7497 if (vcpu->arch.last_host_tsc > max_tsc) 7498 max_tsc = vcpu->arch.last_host_tsc; 7499 } 7500 } 7501 } 7502 7503 /* 7504 * Sometimes, even reliable TSCs go backwards. This happens on 7505 * platforms that reset TSC during suspend or hibernate actions, but 7506 * maintain synchronization. We must compensate. Fortunately, we can 7507 * detect that condition here, which happens early in CPU bringup, 7508 * before any KVM threads can be running. Unfortunately, we can't 7509 * bring the TSCs fully up to date with real time, as we aren't yet far 7510 * enough into CPU bringup that we know how much real time has actually 7511 * elapsed; our helper function, get_kernel_ns() will be using boot 7512 * variables that haven't been updated yet. 7513 * 7514 * So we simply find the maximum observed TSC above, then record the 7515 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 7516 * the adjustment will be applied. Note that we accumulate 7517 * adjustments, in case multiple suspend cycles happen before some VCPU 7518 * gets a chance to run again. In the event that no KVM threads get a 7519 * chance to run, we will miss the entire elapsed period, as we'll have 7520 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 7521 * loose cycle time. This isn't too big a deal, since the loss will be 7522 * uniform across all VCPUs (not to mention the scenario is extremely 7523 * unlikely). It is possible that a second hibernate recovery happens 7524 * much faster than a first, causing the observed TSC here to be 7525 * smaller; this would require additional padding adjustment, which is 7526 * why we set last_host_tsc to the local tsc observed here. 7527 * 7528 * N.B. - this code below runs only on platforms with reliable TSC, 7529 * as that is the only way backwards_tsc is set above. Also note 7530 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 7531 * have the same delta_cyc adjustment applied if backwards_tsc 7532 * is detected. Note further, this adjustment is only done once, 7533 * as we reset last_host_tsc on all VCPUs to stop this from being 7534 * called multiple times (one for each physical CPU bringup). 7535 * 7536 * Platforms with unreliable TSCs don't have to deal with this, they 7537 * will be compensated by the logic in vcpu_load, which sets the TSC to 7538 * catchup mode. This will catchup all VCPUs to real time, but cannot 7539 * guarantee that they stay in perfect synchronization. 7540 */ 7541 if (backwards_tsc) { 7542 u64 delta_cyc = max_tsc - local_tsc; 7543 backwards_tsc_observed = true; 7544 list_for_each_entry(kvm, &vm_list, vm_list) { 7545 kvm_for_each_vcpu(i, vcpu, kvm) { 7546 vcpu->arch.tsc_offset_adjustment += delta_cyc; 7547 vcpu->arch.last_host_tsc = local_tsc; 7548 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7549 } 7550 7551 /* 7552 * We have to disable TSC offset matching.. if you were 7553 * booting a VM while issuing an S4 host suspend.... 7554 * you may have some problem. Solving this issue is 7555 * left as an exercise to the reader. 7556 */ 7557 kvm->arch.last_tsc_nsec = 0; 7558 kvm->arch.last_tsc_write = 0; 7559 } 7560 7561 } 7562 return 0; 7563 } 7564 7565 void kvm_arch_hardware_disable(void) 7566 { 7567 kvm_x86_ops->hardware_disable(); 7568 drop_user_return_notifiers(); 7569 } 7570 7571 int kvm_arch_hardware_setup(void) 7572 { 7573 int r; 7574 7575 r = kvm_x86_ops->hardware_setup(); 7576 if (r != 0) 7577 return r; 7578 7579 if (kvm_has_tsc_control) { 7580 /* 7581 * Make sure the user can only configure tsc_khz values that 7582 * fit into a signed integer. 7583 * A min value is not calculated needed because it will always 7584 * be 1 on all machines. 7585 */ 7586 u64 max = min(0x7fffffffULL, 7587 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 7588 kvm_max_guest_tsc_khz = max; 7589 7590 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 7591 } 7592 7593 kvm_init_msr_list(); 7594 return 0; 7595 } 7596 7597 void kvm_arch_hardware_unsetup(void) 7598 { 7599 kvm_x86_ops->hardware_unsetup(); 7600 } 7601 7602 void kvm_arch_check_processor_compat(void *rtn) 7603 { 7604 kvm_x86_ops->check_processor_compatibility(rtn); 7605 } 7606 7607 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 7608 { 7609 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 7610 } 7611 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 7612 7613 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 7614 { 7615 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 7616 } 7617 7618 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) 7619 { 7620 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu); 7621 } 7622 7623 struct static_key kvm_no_apic_vcpu __read_mostly; 7624 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); 7625 7626 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 7627 { 7628 struct page *page; 7629 struct kvm *kvm; 7630 int r; 7631 7632 BUG_ON(vcpu->kvm == NULL); 7633 kvm = vcpu->kvm; 7634 7635 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(); 7636 vcpu->arch.pv.pv_unhalted = false; 7637 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 7638 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 7639 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7640 else 7641 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 7642 7643 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 7644 if (!page) { 7645 r = -ENOMEM; 7646 goto fail; 7647 } 7648 vcpu->arch.pio_data = page_address(page); 7649 7650 kvm_set_tsc_khz(vcpu, max_tsc_khz); 7651 7652 r = kvm_mmu_create(vcpu); 7653 if (r < 0) 7654 goto fail_free_pio_data; 7655 7656 if (irqchip_in_kernel(kvm)) { 7657 r = kvm_create_lapic(vcpu); 7658 if (r < 0) 7659 goto fail_mmu_destroy; 7660 } else 7661 static_key_slow_inc(&kvm_no_apic_vcpu); 7662 7663 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 7664 GFP_KERNEL); 7665 if (!vcpu->arch.mce_banks) { 7666 r = -ENOMEM; 7667 goto fail_free_lapic; 7668 } 7669 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 7670 7671 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 7672 r = -ENOMEM; 7673 goto fail_free_mce_banks; 7674 } 7675 7676 fx_init(vcpu); 7677 7678 vcpu->arch.ia32_tsc_adjust_msr = 0x0; 7679 vcpu->arch.pv_time_enabled = false; 7680 7681 vcpu->arch.guest_supported_xcr0 = 0; 7682 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 7683 7684 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 7685 7686 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 7687 7688 kvm_async_pf_hash_reset(vcpu); 7689 kvm_pmu_init(vcpu); 7690 7691 vcpu->arch.pending_external_vector = -1; 7692 7693 kvm_hv_vcpu_init(vcpu); 7694 7695 return 0; 7696 7697 fail_free_mce_banks: 7698 kfree(vcpu->arch.mce_banks); 7699 fail_free_lapic: 7700 kvm_free_lapic(vcpu); 7701 fail_mmu_destroy: 7702 kvm_mmu_destroy(vcpu); 7703 fail_free_pio_data: 7704 free_page((unsigned long)vcpu->arch.pio_data); 7705 fail: 7706 return r; 7707 } 7708 7709 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 7710 { 7711 int idx; 7712 7713 kvm_hv_vcpu_uninit(vcpu); 7714 kvm_pmu_destroy(vcpu); 7715 kfree(vcpu->arch.mce_banks); 7716 kvm_free_lapic(vcpu); 7717 idx = srcu_read_lock(&vcpu->kvm->srcu); 7718 kvm_mmu_destroy(vcpu); 7719 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7720 free_page((unsigned long)vcpu->arch.pio_data); 7721 if (!lapic_in_kernel(vcpu)) 7722 static_key_slow_dec(&kvm_no_apic_vcpu); 7723 } 7724 7725 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 7726 { 7727 kvm_x86_ops->sched_in(vcpu, cpu); 7728 } 7729 7730 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 7731 { 7732 if (type) 7733 return -EINVAL; 7734 7735 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 7736 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 7737 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 7738 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 7739 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 7740 7741 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 7742 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 7743 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 7744 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 7745 &kvm->arch.irq_sources_bitmap); 7746 7747 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 7748 mutex_init(&kvm->arch.apic_map_lock); 7749 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 7750 7751 pvclock_update_vm_gtod_copy(kvm); 7752 7753 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 7754 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 7755 7756 kvm_page_track_init(kvm); 7757 kvm_mmu_init_vm(kvm); 7758 7759 if (kvm_x86_ops->vm_init) 7760 return kvm_x86_ops->vm_init(kvm); 7761 7762 return 0; 7763 } 7764 7765 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 7766 { 7767 int r; 7768 r = vcpu_load(vcpu); 7769 BUG_ON(r); 7770 kvm_mmu_unload(vcpu); 7771 vcpu_put(vcpu); 7772 } 7773 7774 static void kvm_free_vcpus(struct kvm *kvm) 7775 { 7776 unsigned int i; 7777 struct kvm_vcpu *vcpu; 7778 7779 /* 7780 * Unpin any mmu pages first. 7781 */ 7782 kvm_for_each_vcpu(i, vcpu, kvm) { 7783 kvm_clear_async_pf_completion_queue(vcpu); 7784 kvm_unload_vcpu_mmu(vcpu); 7785 } 7786 kvm_for_each_vcpu(i, vcpu, kvm) 7787 kvm_arch_vcpu_free(vcpu); 7788 7789 mutex_lock(&kvm->lock); 7790 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 7791 kvm->vcpus[i] = NULL; 7792 7793 atomic_set(&kvm->online_vcpus, 0); 7794 mutex_unlock(&kvm->lock); 7795 } 7796 7797 void kvm_arch_sync_events(struct kvm *kvm) 7798 { 7799 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 7800 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 7801 kvm_free_all_assigned_devices(kvm); 7802 kvm_free_pit(kvm); 7803 } 7804 7805 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 7806 { 7807 int i, r; 7808 unsigned long hva; 7809 struct kvm_memslots *slots = kvm_memslots(kvm); 7810 struct kvm_memory_slot *slot, old; 7811 7812 /* Called with kvm->slots_lock held. */ 7813 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 7814 return -EINVAL; 7815 7816 slot = id_to_memslot(slots, id); 7817 if (size) { 7818 if (WARN_ON(slot->npages)) 7819 return -EEXIST; 7820 7821 /* 7822 * MAP_SHARED to prevent internal slot pages from being moved 7823 * by fork()/COW. 7824 */ 7825 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 7826 MAP_SHARED | MAP_ANONYMOUS, 0); 7827 if (IS_ERR((void *)hva)) 7828 return PTR_ERR((void *)hva); 7829 } else { 7830 if (!slot->npages) 7831 return 0; 7832 7833 hva = 0; 7834 } 7835 7836 old = *slot; 7837 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 7838 struct kvm_userspace_memory_region m; 7839 7840 m.slot = id | (i << 16); 7841 m.flags = 0; 7842 m.guest_phys_addr = gpa; 7843 m.userspace_addr = hva; 7844 m.memory_size = size; 7845 r = __kvm_set_memory_region(kvm, &m); 7846 if (r < 0) 7847 return r; 7848 } 7849 7850 if (!size) { 7851 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); 7852 WARN_ON(r < 0); 7853 } 7854 7855 return 0; 7856 } 7857 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 7858 7859 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 7860 { 7861 int r; 7862 7863 mutex_lock(&kvm->slots_lock); 7864 r = __x86_set_memory_region(kvm, id, gpa, size); 7865 mutex_unlock(&kvm->slots_lock); 7866 7867 return r; 7868 } 7869 EXPORT_SYMBOL_GPL(x86_set_memory_region); 7870 7871 void kvm_arch_destroy_vm(struct kvm *kvm) 7872 { 7873 if (current->mm == kvm->mm) { 7874 /* 7875 * Free memory regions allocated on behalf of userspace, 7876 * unless the the memory map has changed due to process exit 7877 * or fd copying. 7878 */ 7879 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); 7880 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); 7881 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 7882 } 7883 if (kvm_x86_ops->vm_destroy) 7884 kvm_x86_ops->vm_destroy(kvm); 7885 kvm_iommu_unmap_guest(kvm); 7886 kfree(kvm->arch.vpic); 7887 kfree(kvm->arch.vioapic); 7888 kvm_free_vcpus(kvm); 7889 kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 7890 kvm_mmu_uninit_vm(kvm); 7891 } 7892 7893 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 7894 struct kvm_memory_slot *dont) 7895 { 7896 int i; 7897 7898 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7899 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 7900 kvfree(free->arch.rmap[i]); 7901 free->arch.rmap[i] = NULL; 7902 } 7903 if (i == 0) 7904 continue; 7905 7906 if (!dont || free->arch.lpage_info[i - 1] != 7907 dont->arch.lpage_info[i - 1]) { 7908 kvfree(free->arch.lpage_info[i - 1]); 7909 free->arch.lpage_info[i - 1] = NULL; 7910 } 7911 } 7912 7913 kvm_page_track_free_memslot(free, dont); 7914 } 7915 7916 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 7917 unsigned long npages) 7918 { 7919 int i; 7920 7921 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7922 struct kvm_lpage_info *linfo; 7923 unsigned long ugfn; 7924 int lpages; 7925 int level = i + 1; 7926 7927 lpages = gfn_to_index(slot->base_gfn + npages - 1, 7928 slot->base_gfn, level) + 1; 7929 7930 slot->arch.rmap[i] = 7931 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); 7932 if (!slot->arch.rmap[i]) 7933 goto out_free; 7934 if (i == 0) 7935 continue; 7936 7937 linfo = kvm_kvzalloc(lpages * sizeof(*linfo)); 7938 if (!linfo) 7939 goto out_free; 7940 7941 slot->arch.lpage_info[i - 1] = linfo; 7942 7943 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 7944 linfo[0].disallow_lpage = 1; 7945 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 7946 linfo[lpages - 1].disallow_lpage = 1; 7947 ugfn = slot->userspace_addr >> PAGE_SHIFT; 7948 /* 7949 * If the gfn and userspace address are not aligned wrt each 7950 * other, or if explicitly asked to, disable large page 7951 * support for this slot 7952 */ 7953 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 7954 !kvm_largepages_enabled()) { 7955 unsigned long j; 7956 7957 for (j = 0; j < lpages; ++j) 7958 linfo[j].disallow_lpage = 1; 7959 } 7960 } 7961 7962 if (kvm_page_track_create_memslot(slot, npages)) 7963 goto out_free; 7964 7965 return 0; 7966 7967 out_free: 7968 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7969 kvfree(slot->arch.rmap[i]); 7970 slot->arch.rmap[i] = NULL; 7971 if (i == 0) 7972 continue; 7973 7974 kvfree(slot->arch.lpage_info[i - 1]); 7975 slot->arch.lpage_info[i - 1] = NULL; 7976 } 7977 return -ENOMEM; 7978 } 7979 7980 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) 7981 { 7982 /* 7983 * memslots->generation has been incremented. 7984 * mmio generation may have reached its maximum value. 7985 */ 7986 kvm_mmu_invalidate_mmio_sptes(kvm, slots); 7987 } 7988 7989 int kvm_arch_prepare_memory_region(struct kvm *kvm, 7990 struct kvm_memory_slot *memslot, 7991 const struct kvm_userspace_memory_region *mem, 7992 enum kvm_mr_change change) 7993 { 7994 return 0; 7995 } 7996 7997 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 7998 struct kvm_memory_slot *new) 7999 { 8000 /* Still write protect RO slot */ 8001 if (new->flags & KVM_MEM_READONLY) { 8002 kvm_mmu_slot_remove_write_access(kvm, new); 8003 return; 8004 } 8005 8006 /* 8007 * Call kvm_x86_ops dirty logging hooks when they are valid. 8008 * 8009 * kvm_x86_ops->slot_disable_log_dirty is called when: 8010 * 8011 * - KVM_MR_CREATE with dirty logging is disabled 8012 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 8013 * 8014 * The reason is, in case of PML, we need to set D-bit for any slots 8015 * with dirty logging disabled in order to eliminate unnecessary GPA 8016 * logging in PML buffer (and potential PML buffer full VMEXT). This 8017 * guarantees leaving PML enabled during guest's lifetime won't have 8018 * any additonal overhead from PML when guest is running with dirty 8019 * logging disabled for memory slots. 8020 * 8021 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 8022 * to dirty logging mode. 8023 * 8024 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 8025 * 8026 * In case of write protect: 8027 * 8028 * Write protect all pages for dirty logging. 8029 * 8030 * All the sptes including the large sptes which point to this 8031 * slot are set to readonly. We can not create any new large 8032 * spte on this slot until the end of the logging. 8033 * 8034 * See the comments in fast_page_fault(). 8035 */ 8036 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 8037 if (kvm_x86_ops->slot_enable_log_dirty) 8038 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 8039 else 8040 kvm_mmu_slot_remove_write_access(kvm, new); 8041 } else { 8042 if (kvm_x86_ops->slot_disable_log_dirty) 8043 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 8044 } 8045 } 8046 8047 void kvm_arch_commit_memory_region(struct kvm *kvm, 8048 const struct kvm_userspace_memory_region *mem, 8049 const struct kvm_memory_slot *old, 8050 const struct kvm_memory_slot *new, 8051 enum kvm_mr_change change) 8052 { 8053 int nr_mmu_pages = 0; 8054 8055 if (!kvm->arch.n_requested_mmu_pages) 8056 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 8057 8058 if (nr_mmu_pages) 8059 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 8060 8061 /* 8062 * Dirty logging tracks sptes in 4k granularity, meaning that large 8063 * sptes have to be split. If live migration is successful, the guest 8064 * in the source machine will be destroyed and large sptes will be 8065 * created in the destination. However, if the guest continues to run 8066 * in the source machine (for example if live migration fails), small 8067 * sptes will remain around and cause bad performance. 8068 * 8069 * Scan sptes if dirty logging has been stopped, dropping those 8070 * which can be collapsed into a single large-page spte. Later 8071 * page faults will create the large-page sptes. 8072 */ 8073 if ((change != KVM_MR_DELETE) && 8074 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 8075 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 8076 kvm_mmu_zap_collapsible_sptes(kvm, new); 8077 8078 /* 8079 * Set up write protection and/or dirty logging for the new slot. 8080 * 8081 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 8082 * been zapped so no dirty logging staff is needed for old slot. For 8083 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 8084 * new and it's also covered when dealing with the new slot. 8085 * 8086 * FIXME: const-ify all uses of struct kvm_memory_slot. 8087 */ 8088 if (change != KVM_MR_DELETE) 8089 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 8090 } 8091 8092 void kvm_arch_flush_shadow_all(struct kvm *kvm) 8093 { 8094 kvm_mmu_invalidate_zap_all_pages(kvm); 8095 } 8096 8097 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 8098 struct kvm_memory_slot *slot) 8099 { 8100 kvm_mmu_invalidate_zap_all_pages(kvm); 8101 } 8102 8103 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 8104 { 8105 if (!list_empty_careful(&vcpu->async_pf.done)) 8106 return true; 8107 8108 if (kvm_apic_has_events(vcpu)) 8109 return true; 8110 8111 if (vcpu->arch.pv.pv_unhalted) 8112 return true; 8113 8114 if (atomic_read(&vcpu->arch.nmi_queued)) 8115 return true; 8116 8117 if (test_bit(KVM_REQ_SMI, &vcpu->requests)) 8118 return true; 8119 8120 if (kvm_arch_interrupt_allowed(vcpu) && 8121 kvm_cpu_has_interrupt(vcpu)) 8122 return true; 8123 8124 if (kvm_hv_has_stimer_pending(vcpu)) 8125 return true; 8126 8127 return false; 8128 } 8129 8130 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 8131 { 8132 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 8133 kvm_x86_ops->check_nested_events(vcpu, false); 8134 8135 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 8136 } 8137 8138 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 8139 { 8140 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 8141 } 8142 8143 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 8144 { 8145 return kvm_x86_ops->interrupt_allowed(vcpu); 8146 } 8147 8148 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 8149 { 8150 if (is_64_bit_mode(vcpu)) 8151 return kvm_rip_read(vcpu); 8152 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 8153 kvm_rip_read(vcpu)); 8154 } 8155 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 8156 8157 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 8158 { 8159 return kvm_get_linear_rip(vcpu) == linear_rip; 8160 } 8161 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 8162 8163 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 8164 { 8165 unsigned long rflags; 8166 8167 rflags = kvm_x86_ops->get_rflags(vcpu); 8168 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 8169 rflags &= ~X86_EFLAGS_TF; 8170 return rflags; 8171 } 8172 EXPORT_SYMBOL_GPL(kvm_get_rflags); 8173 8174 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8175 { 8176 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 8177 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 8178 rflags |= X86_EFLAGS_TF; 8179 kvm_x86_ops->set_rflags(vcpu, rflags); 8180 } 8181 8182 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8183 { 8184 __kvm_set_rflags(vcpu, rflags); 8185 kvm_make_request(KVM_REQ_EVENT, vcpu); 8186 } 8187 EXPORT_SYMBOL_GPL(kvm_set_rflags); 8188 8189 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 8190 { 8191 int r; 8192 8193 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 8194 work->wakeup_all) 8195 return; 8196 8197 r = kvm_mmu_reload(vcpu); 8198 if (unlikely(r)) 8199 return; 8200 8201 if (!vcpu->arch.mmu.direct_map && 8202 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 8203 return; 8204 8205 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 8206 } 8207 8208 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 8209 { 8210 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 8211 } 8212 8213 static inline u32 kvm_async_pf_next_probe(u32 key) 8214 { 8215 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 8216 } 8217 8218 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8219 { 8220 u32 key = kvm_async_pf_hash_fn(gfn); 8221 8222 while (vcpu->arch.apf.gfns[key] != ~0) 8223 key = kvm_async_pf_next_probe(key); 8224 8225 vcpu->arch.apf.gfns[key] = gfn; 8226 } 8227 8228 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 8229 { 8230 int i; 8231 u32 key = kvm_async_pf_hash_fn(gfn); 8232 8233 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 8234 (vcpu->arch.apf.gfns[key] != gfn && 8235 vcpu->arch.apf.gfns[key] != ~0); i++) 8236 key = kvm_async_pf_next_probe(key); 8237 8238 return key; 8239 } 8240 8241 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8242 { 8243 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 8244 } 8245 8246 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8247 { 8248 u32 i, j, k; 8249 8250 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 8251 while (true) { 8252 vcpu->arch.apf.gfns[i] = ~0; 8253 do { 8254 j = kvm_async_pf_next_probe(j); 8255 if (vcpu->arch.apf.gfns[j] == ~0) 8256 return; 8257 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 8258 /* 8259 * k lies cyclically in ]i,j] 8260 * | i.k.j | 8261 * |....j i.k.| or |.k..j i...| 8262 */ 8263 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 8264 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 8265 i = j; 8266 } 8267 } 8268 8269 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 8270 { 8271 8272 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 8273 sizeof(val)); 8274 } 8275 8276 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 8277 struct kvm_async_pf *work) 8278 { 8279 struct x86_exception fault; 8280 8281 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 8282 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 8283 8284 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 8285 (vcpu->arch.apf.send_user_only && 8286 kvm_x86_ops->get_cpl(vcpu) == 0)) 8287 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 8288 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 8289 fault.vector = PF_VECTOR; 8290 fault.error_code_valid = true; 8291 fault.error_code = 0; 8292 fault.nested_page_fault = false; 8293 fault.address = work->arch.token; 8294 kvm_inject_page_fault(vcpu, &fault); 8295 } 8296 } 8297 8298 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 8299 struct kvm_async_pf *work) 8300 { 8301 struct x86_exception fault; 8302 8303 trace_kvm_async_pf_ready(work->arch.token, work->gva); 8304 if (work->wakeup_all) 8305 work->arch.token = ~0; /* broadcast wakeup */ 8306 else 8307 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 8308 8309 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && 8310 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 8311 fault.vector = PF_VECTOR; 8312 fault.error_code_valid = true; 8313 fault.error_code = 0; 8314 fault.nested_page_fault = false; 8315 fault.address = work->arch.token; 8316 kvm_inject_page_fault(vcpu, &fault); 8317 } 8318 vcpu->arch.apf.halted = false; 8319 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8320 } 8321 8322 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 8323 { 8324 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 8325 return true; 8326 else 8327 return !kvm_event_needs_reinjection(vcpu) && 8328 kvm_x86_ops->interrupt_allowed(vcpu); 8329 } 8330 8331 void kvm_arch_start_assignment(struct kvm *kvm) 8332 { 8333 atomic_inc(&kvm->arch.assigned_device_count); 8334 } 8335 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 8336 8337 void kvm_arch_end_assignment(struct kvm *kvm) 8338 { 8339 atomic_dec(&kvm->arch.assigned_device_count); 8340 } 8341 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 8342 8343 bool kvm_arch_has_assigned_device(struct kvm *kvm) 8344 { 8345 return atomic_read(&kvm->arch.assigned_device_count); 8346 } 8347 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 8348 8349 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 8350 { 8351 atomic_inc(&kvm->arch.noncoherent_dma_count); 8352 } 8353 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 8354 8355 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 8356 { 8357 atomic_dec(&kvm->arch.noncoherent_dma_count); 8358 } 8359 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 8360 8361 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 8362 { 8363 return atomic_read(&kvm->arch.noncoherent_dma_count); 8364 } 8365 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 8366 8367 bool kvm_arch_has_irq_bypass(void) 8368 { 8369 return kvm_x86_ops->update_pi_irte != NULL; 8370 } 8371 8372 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 8373 struct irq_bypass_producer *prod) 8374 { 8375 struct kvm_kernel_irqfd *irqfd = 8376 container_of(cons, struct kvm_kernel_irqfd, consumer); 8377 8378 irqfd->producer = prod; 8379 8380 return kvm_x86_ops->update_pi_irte(irqfd->kvm, 8381 prod->irq, irqfd->gsi, 1); 8382 } 8383 8384 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 8385 struct irq_bypass_producer *prod) 8386 { 8387 int ret; 8388 struct kvm_kernel_irqfd *irqfd = 8389 container_of(cons, struct kvm_kernel_irqfd, consumer); 8390 8391 WARN_ON(irqfd->producer != prod); 8392 irqfd->producer = NULL; 8393 8394 /* 8395 * When producer of consumer is unregistered, we change back to 8396 * remapped mode, so we can re-use the current implementation 8397 * when the irq is masked/disabed or the consumer side (KVM 8398 * int this case doesn't want to receive the interrupts. 8399 */ 8400 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 8401 if (ret) 8402 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 8403 " fails: %d\n", irqfd->consumer.token, ret); 8404 } 8405 8406 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 8407 uint32_t guest_irq, bool set) 8408 { 8409 if (!kvm_x86_ops->update_pi_irte) 8410 return -EINVAL; 8411 8412 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); 8413 } 8414 8415 bool kvm_vector_hashing_enabled(void) 8416 { 8417 return vector_hashing; 8418 } 8419 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled); 8420 8421 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 8422 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 8423 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 8424 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 8425 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 8426 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 8427 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 8428 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 8429 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 8430 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 8431 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 8432 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 8433 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 8434 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 8435 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 8436 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 8437 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 8438 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 8439 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 8440