xref: /openbmc/linux/arch/x86/kvm/x86.c (revision 95777591)
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * derived from drivers/kvm/kvm_main.c
5  *
6  * Copyright (C) 2006 Qumranet, Inc.
7  * Copyright (C) 2008 Qumranet, Inc.
8  * Copyright IBM Corporation, 2008
9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10  *
11  * Authors:
12  *   Avi Kivity   <avi@qumranet.com>
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  *   Amit Shah    <amit.shah@qumranet.com>
15  *   Ben-Ami Yassour <benami@il.ibm.com>
16  *
17  * This work is licensed under the terms of the GNU GPL, version 2.  See
18  * the COPYING file in the top-level directory.
19  *
20  */
21 
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "pmu.h"
31 #include "hyperv.h"
32 
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
36 #include <linux/fs.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/mem_encrypt.h>
58 
59 #include <trace/events/kvm.h>
60 
61 #include <asm/debugreg.h>
62 #include <asm/msr.h>
63 #include <asm/desc.h>
64 #include <asm/mce.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70 #include <asm/mshyperv.h>
71 #include <asm/hypervisor.h>
72 #include <asm/intel_pt.h>
73 
74 #define CREATE_TRACE_POINTS
75 #include "trace.h"
76 
77 #define MAX_IO_MSRS 256
78 #define KVM_MAX_MCE_BANKS 32
79 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
80 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
81 
82 #define emul_to_vcpu(ctxt) \
83 	container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
84 
85 /* EFER defaults:
86  * - enable syscall per default because its emulated by KVM
87  * - enable LME and LMA per default on 64 bit KVM
88  */
89 #ifdef CONFIG_X86_64
90 static
91 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
92 #else
93 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
94 #endif
95 
96 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
97 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
98 
99 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
100                                     KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
101 
102 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
103 static void process_nmi(struct kvm_vcpu *vcpu);
104 static void enter_smm(struct kvm_vcpu *vcpu);
105 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
106 static void store_regs(struct kvm_vcpu *vcpu);
107 static int sync_regs(struct kvm_vcpu *vcpu);
108 
109 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
110 EXPORT_SYMBOL_GPL(kvm_x86_ops);
111 
112 static bool __read_mostly ignore_msrs = 0;
113 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
114 
115 static bool __read_mostly report_ignored_msrs = true;
116 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
117 
118 unsigned int min_timer_period_us = 200;
119 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
120 
121 static bool __read_mostly kvmclock_periodic_sync = true;
122 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
123 
124 bool __read_mostly kvm_has_tsc_control;
125 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
126 u32  __read_mostly kvm_max_guest_tsc_khz;
127 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
128 u8   __read_mostly kvm_tsc_scaling_ratio_frac_bits;
129 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
130 u64  __read_mostly kvm_max_tsc_scaling_ratio;
131 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
132 u64 __read_mostly kvm_default_tsc_scaling_ratio;
133 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
134 
135 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
136 static u32 __read_mostly tsc_tolerance_ppm = 250;
137 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
138 
139 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
140 unsigned int __read_mostly lapic_timer_advance_ns = 1000;
141 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
142 EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
143 
144 static bool __read_mostly vector_hashing = true;
145 module_param(vector_hashing, bool, S_IRUGO);
146 
147 bool __read_mostly enable_vmware_backdoor = false;
148 module_param(enable_vmware_backdoor, bool, S_IRUGO);
149 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
150 
151 static bool __read_mostly force_emulation_prefix = false;
152 module_param(force_emulation_prefix, bool, S_IRUGO);
153 
154 #define KVM_NR_SHARED_MSRS 16
155 
156 struct kvm_shared_msrs_global {
157 	int nr;
158 	u32 msrs[KVM_NR_SHARED_MSRS];
159 };
160 
161 struct kvm_shared_msrs {
162 	struct user_return_notifier urn;
163 	bool registered;
164 	struct kvm_shared_msr_values {
165 		u64 host;
166 		u64 curr;
167 	} values[KVM_NR_SHARED_MSRS];
168 };
169 
170 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
171 static struct kvm_shared_msrs __percpu *shared_msrs;
172 
173 struct kvm_stats_debugfs_item debugfs_entries[] = {
174 	{ "pf_fixed", VCPU_STAT(pf_fixed) },
175 	{ "pf_guest", VCPU_STAT(pf_guest) },
176 	{ "tlb_flush", VCPU_STAT(tlb_flush) },
177 	{ "invlpg", VCPU_STAT(invlpg) },
178 	{ "exits", VCPU_STAT(exits) },
179 	{ "io_exits", VCPU_STAT(io_exits) },
180 	{ "mmio_exits", VCPU_STAT(mmio_exits) },
181 	{ "signal_exits", VCPU_STAT(signal_exits) },
182 	{ "irq_window", VCPU_STAT(irq_window_exits) },
183 	{ "nmi_window", VCPU_STAT(nmi_window_exits) },
184 	{ "halt_exits", VCPU_STAT(halt_exits) },
185 	{ "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
186 	{ "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
187 	{ "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
188 	{ "halt_wakeup", VCPU_STAT(halt_wakeup) },
189 	{ "hypercalls", VCPU_STAT(hypercalls) },
190 	{ "request_irq", VCPU_STAT(request_irq_exits) },
191 	{ "irq_exits", VCPU_STAT(irq_exits) },
192 	{ "host_state_reload", VCPU_STAT(host_state_reload) },
193 	{ "fpu_reload", VCPU_STAT(fpu_reload) },
194 	{ "insn_emulation", VCPU_STAT(insn_emulation) },
195 	{ "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
196 	{ "irq_injections", VCPU_STAT(irq_injections) },
197 	{ "nmi_injections", VCPU_STAT(nmi_injections) },
198 	{ "req_event", VCPU_STAT(req_event) },
199 	{ "l1d_flush", VCPU_STAT(l1d_flush) },
200 	{ "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
201 	{ "mmu_pte_write", VM_STAT(mmu_pte_write) },
202 	{ "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
203 	{ "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
204 	{ "mmu_flooded", VM_STAT(mmu_flooded) },
205 	{ "mmu_recycled", VM_STAT(mmu_recycled) },
206 	{ "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
207 	{ "mmu_unsync", VM_STAT(mmu_unsync) },
208 	{ "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
209 	{ "largepages", VM_STAT(lpages) },
210 	{ "max_mmu_page_hash_collisions",
211 		VM_STAT(max_mmu_page_hash_collisions) },
212 	{ NULL }
213 };
214 
215 u64 __read_mostly host_xcr0;
216 
217 struct kmem_cache *x86_fpu_cache;
218 EXPORT_SYMBOL_GPL(x86_fpu_cache);
219 
220 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
221 
222 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
223 {
224 	int i;
225 	for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
226 		vcpu->arch.apf.gfns[i] = ~0;
227 }
228 
229 static void kvm_on_user_return(struct user_return_notifier *urn)
230 {
231 	unsigned slot;
232 	struct kvm_shared_msrs *locals
233 		= container_of(urn, struct kvm_shared_msrs, urn);
234 	struct kvm_shared_msr_values *values;
235 	unsigned long flags;
236 
237 	/*
238 	 * Disabling irqs at this point since the following code could be
239 	 * interrupted and executed through kvm_arch_hardware_disable()
240 	 */
241 	local_irq_save(flags);
242 	if (locals->registered) {
243 		locals->registered = false;
244 		user_return_notifier_unregister(urn);
245 	}
246 	local_irq_restore(flags);
247 	for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
248 		values = &locals->values[slot];
249 		if (values->host != values->curr) {
250 			wrmsrl(shared_msrs_global.msrs[slot], values->host);
251 			values->curr = values->host;
252 		}
253 	}
254 }
255 
256 static void shared_msr_update(unsigned slot, u32 msr)
257 {
258 	u64 value;
259 	unsigned int cpu = smp_processor_id();
260 	struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
261 
262 	/* only read, and nobody should modify it at this time,
263 	 * so don't need lock */
264 	if (slot >= shared_msrs_global.nr) {
265 		printk(KERN_ERR "kvm: invalid MSR slot!");
266 		return;
267 	}
268 	rdmsrl_safe(msr, &value);
269 	smsr->values[slot].host = value;
270 	smsr->values[slot].curr = value;
271 }
272 
273 void kvm_define_shared_msr(unsigned slot, u32 msr)
274 {
275 	BUG_ON(slot >= KVM_NR_SHARED_MSRS);
276 	shared_msrs_global.msrs[slot] = msr;
277 	if (slot >= shared_msrs_global.nr)
278 		shared_msrs_global.nr = slot + 1;
279 }
280 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
281 
282 static void kvm_shared_msr_cpu_online(void)
283 {
284 	unsigned i;
285 
286 	for (i = 0; i < shared_msrs_global.nr; ++i)
287 		shared_msr_update(i, shared_msrs_global.msrs[i]);
288 }
289 
290 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
291 {
292 	unsigned int cpu = smp_processor_id();
293 	struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
294 	int err;
295 
296 	if (((value ^ smsr->values[slot].curr) & mask) == 0)
297 		return 0;
298 	smsr->values[slot].curr = value;
299 	err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
300 	if (err)
301 		return 1;
302 
303 	if (!smsr->registered) {
304 		smsr->urn.on_user_return = kvm_on_user_return;
305 		user_return_notifier_register(&smsr->urn);
306 		smsr->registered = true;
307 	}
308 	return 0;
309 }
310 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
311 
312 static void drop_user_return_notifiers(void)
313 {
314 	unsigned int cpu = smp_processor_id();
315 	struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
316 
317 	if (smsr->registered)
318 		kvm_on_user_return(&smsr->urn);
319 }
320 
321 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
322 {
323 	return vcpu->arch.apic_base;
324 }
325 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
326 
327 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
328 {
329 	return kvm_apic_mode(kvm_get_apic_base(vcpu));
330 }
331 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
332 
333 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
334 {
335 	enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
336 	enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
337 	u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
338 		(guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
339 
340 	if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
341 		return 1;
342 	if (!msr_info->host_initiated) {
343 		if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
344 			return 1;
345 		if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
346 			return 1;
347 	}
348 
349 	kvm_lapic_set_base(vcpu, msr_info->data);
350 	return 0;
351 }
352 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
353 
354 asmlinkage __visible void kvm_spurious_fault(void)
355 {
356 	/* Fault while not rebooting.  We want the trace. */
357 	BUG();
358 }
359 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
360 
361 #define EXCPT_BENIGN		0
362 #define EXCPT_CONTRIBUTORY	1
363 #define EXCPT_PF		2
364 
365 static int exception_class(int vector)
366 {
367 	switch (vector) {
368 	case PF_VECTOR:
369 		return EXCPT_PF;
370 	case DE_VECTOR:
371 	case TS_VECTOR:
372 	case NP_VECTOR:
373 	case SS_VECTOR:
374 	case GP_VECTOR:
375 		return EXCPT_CONTRIBUTORY;
376 	default:
377 		break;
378 	}
379 	return EXCPT_BENIGN;
380 }
381 
382 #define EXCPT_FAULT		0
383 #define EXCPT_TRAP		1
384 #define EXCPT_ABORT		2
385 #define EXCPT_INTERRUPT		3
386 
387 static int exception_type(int vector)
388 {
389 	unsigned int mask;
390 
391 	if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
392 		return EXCPT_INTERRUPT;
393 
394 	mask = 1 << vector;
395 
396 	/* #DB is trap, as instruction watchpoints are handled elsewhere */
397 	if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
398 		return EXCPT_TRAP;
399 
400 	if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
401 		return EXCPT_ABORT;
402 
403 	/* Reserved exceptions will result in fault */
404 	return EXCPT_FAULT;
405 }
406 
407 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
408 {
409 	unsigned nr = vcpu->arch.exception.nr;
410 	bool has_payload = vcpu->arch.exception.has_payload;
411 	unsigned long payload = vcpu->arch.exception.payload;
412 
413 	if (!has_payload)
414 		return;
415 
416 	switch (nr) {
417 	case DB_VECTOR:
418 		/*
419 		 * "Certain debug exceptions may clear bit 0-3.  The
420 		 * remaining contents of the DR6 register are never
421 		 * cleared by the processor".
422 		 */
423 		vcpu->arch.dr6 &= ~DR_TRAP_BITS;
424 		/*
425 		 * DR6.RTM is set by all #DB exceptions that don't clear it.
426 		 */
427 		vcpu->arch.dr6 |= DR6_RTM;
428 		vcpu->arch.dr6 |= payload;
429 		/*
430 		 * Bit 16 should be set in the payload whenever the #DB
431 		 * exception should clear DR6.RTM. This makes the payload
432 		 * compatible with the pending debug exceptions under VMX.
433 		 * Though not currently documented in the SDM, this also
434 		 * makes the payload compatible with the exit qualification
435 		 * for #DB exceptions under VMX.
436 		 */
437 		vcpu->arch.dr6 ^= payload & DR6_RTM;
438 		break;
439 	case PF_VECTOR:
440 		vcpu->arch.cr2 = payload;
441 		break;
442 	}
443 
444 	vcpu->arch.exception.has_payload = false;
445 	vcpu->arch.exception.payload = 0;
446 }
447 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
448 
449 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
450 		unsigned nr, bool has_error, u32 error_code,
451 	        bool has_payload, unsigned long payload, bool reinject)
452 {
453 	u32 prev_nr;
454 	int class1, class2;
455 
456 	kvm_make_request(KVM_REQ_EVENT, vcpu);
457 
458 	if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
459 	queue:
460 		if (has_error && !is_protmode(vcpu))
461 			has_error = false;
462 		if (reinject) {
463 			/*
464 			 * On vmentry, vcpu->arch.exception.pending is only
465 			 * true if an event injection was blocked by
466 			 * nested_run_pending.  In that case, however,
467 			 * vcpu_enter_guest requests an immediate exit,
468 			 * and the guest shouldn't proceed far enough to
469 			 * need reinjection.
470 			 */
471 			WARN_ON_ONCE(vcpu->arch.exception.pending);
472 			vcpu->arch.exception.injected = true;
473 			if (WARN_ON_ONCE(has_payload)) {
474 				/*
475 				 * A reinjected event has already
476 				 * delivered its payload.
477 				 */
478 				has_payload = false;
479 				payload = 0;
480 			}
481 		} else {
482 			vcpu->arch.exception.pending = true;
483 			vcpu->arch.exception.injected = false;
484 		}
485 		vcpu->arch.exception.has_error_code = has_error;
486 		vcpu->arch.exception.nr = nr;
487 		vcpu->arch.exception.error_code = error_code;
488 		vcpu->arch.exception.has_payload = has_payload;
489 		vcpu->arch.exception.payload = payload;
490 		/*
491 		 * In guest mode, payload delivery should be deferred,
492 		 * so that the L1 hypervisor can intercept #PF before
493 		 * CR2 is modified (or intercept #DB before DR6 is
494 		 * modified under nVMX).  However, for ABI
495 		 * compatibility with KVM_GET_VCPU_EVENTS and
496 		 * KVM_SET_VCPU_EVENTS, we can't delay payload
497 		 * delivery unless userspace has enabled this
498 		 * functionality via the per-VM capability,
499 		 * KVM_CAP_EXCEPTION_PAYLOAD.
500 		 */
501 		if (!vcpu->kvm->arch.exception_payload_enabled ||
502 		    !is_guest_mode(vcpu))
503 			kvm_deliver_exception_payload(vcpu);
504 		return;
505 	}
506 
507 	/* to check exception */
508 	prev_nr = vcpu->arch.exception.nr;
509 	if (prev_nr == DF_VECTOR) {
510 		/* triple fault -> shutdown */
511 		kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
512 		return;
513 	}
514 	class1 = exception_class(prev_nr);
515 	class2 = exception_class(nr);
516 	if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
517 		|| (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
518 		/*
519 		 * Generate double fault per SDM Table 5-5.  Set
520 		 * exception.pending = true so that the double fault
521 		 * can trigger a nested vmexit.
522 		 */
523 		vcpu->arch.exception.pending = true;
524 		vcpu->arch.exception.injected = false;
525 		vcpu->arch.exception.has_error_code = true;
526 		vcpu->arch.exception.nr = DF_VECTOR;
527 		vcpu->arch.exception.error_code = 0;
528 		vcpu->arch.exception.has_payload = false;
529 		vcpu->arch.exception.payload = 0;
530 	} else
531 		/* replace previous exception with a new one in a hope
532 		   that instruction re-execution will regenerate lost
533 		   exception */
534 		goto queue;
535 }
536 
537 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
538 {
539 	kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
540 }
541 EXPORT_SYMBOL_GPL(kvm_queue_exception);
542 
543 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
544 {
545 	kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
546 }
547 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
548 
549 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
550 				  unsigned long payload)
551 {
552 	kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
553 }
554 
555 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
556 				    u32 error_code, unsigned long payload)
557 {
558 	kvm_multiple_exception(vcpu, nr, true, error_code,
559 			       true, payload, false);
560 }
561 
562 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
563 {
564 	if (err)
565 		kvm_inject_gp(vcpu, 0);
566 	else
567 		return kvm_skip_emulated_instruction(vcpu);
568 
569 	return 1;
570 }
571 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
572 
573 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
574 {
575 	++vcpu->stat.pf_guest;
576 	vcpu->arch.exception.nested_apf =
577 		is_guest_mode(vcpu) && fault->async_page_fault;
578 	if (vcpu->arch.exception.nested_apf) {
579 		vcpu->arch.apf.nested_apf_token = fault->address;
580 		kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
581 	} else {
582 		kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
583 					fault->address);
584 	}
585 }
586 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
587 
588 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
589 {
590 	if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
591 		vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
592 	else
593 		vcpu->arch.mmu->inject_page_fault(vcpu, fault);
594 
595 	return fault->nested_page_fault;
596 }
597 
598 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
599 {
600 	atomic_inc(&vcpu->arch.nmi_queued);
601 	kvm_make_request(KVM_REQ_NMI, vcpu);
602 }
603 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
604 
605 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
606 {
607 	kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
608 }
609 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
610 
611 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
612 {
613 	kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
614 }
615 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
616 
617 /*
618  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
619  * a #GP and return false.
620  */
621 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
622 {
623 	if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
624 		return true;
625 	kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
626 	return false;
627 }
628 EXPORT_SYMBOL_GPL(kvm_require_cpl);
629 
630 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
631 {
632 	if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
633 		return true;
634 
635 	kvm_queue_exception(vcpu, UD_VECTOR);
636 	return false;
637 }
638 EXPORT_SYMBOL_GPL(kvm_require_dr);
639 
640 /*
641  * This function will be used to read from the physical memory of the currently
642  * running guest. The difference to kvm_vcpu_read_guest_page is that this function
643  * can read from guest physical or from the guest's guest physical memory.
644  */
645 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
646 			    gfn_t ngfn, void *data, int offset, int len,
647 			    u32 access)
648 {
649 	struct x86_exception exception;
650 	gfn_t real_gfn;
651 	gpa_t ngpa;
652 
653 	ngpa     = gfn_to_gpa(ngfn);
654 	real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
655 	if (real_gfn == UNMAPPED_GVA)
656 		return -EFAULT;
657 
658 	real_gfn = gpa_to_gfn(real_gfn);
659 
660 	return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
661 }
662 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
663 
664 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
665 			       void *data, int offset, int len, u32 access)
666 {
667 	return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
668 				       data, offset, len, access);
669 }
670 
671 /*
672  * Load the pae pdptrs.  Return true is they are all valid.
673  */
674 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
675 {
676 	gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
677 	unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
678 	int i;
679 	int ret;
680 	u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
681 
682 	ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
683 				      offset * sizeof(u64), sizeof(pdpte),
684 				      PFERR_USER_MASK|PFERR_WRITE_MASK);
685 	if (ret < 0) {
686 		ret = 0;
687 		goto out;
688 	}
689 	for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
690 		if ((pdpte[i] & PT_PRESENT_MASK) &&
691 		    (pdpte[i] &
692 		     vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
693 			ret = 0;
694 			goto out;
695 		}
696 	}
697 	ret = 1;
698 
699 	memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
700 	__set_bit(VCPU_EXREG_PDPTR,
701 		  (unsigned long *)&vcpu->arch.regs_avail);
702 	__set_bit(VCPU_EXREG_PDPTR,
703 		  (unsigned long *)&vcpu->arch.regs_dirty);
704 out:
705 
706 	return ret;
707 }
708 EXPORT_SYMBOL_GPL(load_pdptrs);
709 
710 bool pdptrs_changed(struct kvm_vcpu *vcpu)
711 {
712 	u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
713 	bool changed = true;
714 	int offset;
715 	gfn_t gfn;
716 	int r;
717 
718 	if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu))
719 		return false;
720 
721 	if (!test_bit(VCPU_EXREG_PDPTR,
722 		      (unsigned long *)&vcpu->arch.regs_avail))
723 		return true;
724 
725 	gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
726 	offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
727 	r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
728 				       PFERR_USER_MASK | PFERR_WRITE_MASK);
729 	if (r < 0)
730 		goto out;
731 	changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
732 out:
733 
734 	return changed;
735 }
736 EXPORT_SYMBOL_GPL(pdptrs_changed);
737 
738 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
739 {
740 	unsigned long old_cr0 = kvm_read_cr0(vcpu);
741 	unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
742 
743 	cr0 |= X86_CR0_ET;
744 
745 #ifdef CONFIG_X86_64
746 	if (cr0 & 0xffffffff00000000UL)
747 		return 1;
748 #endif
749 
750 	cr0 &= ~CR0_RESERVED_BITS;
751 
752 	if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
753 		return 1;
754 
755 	if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
756 		return 1;
757 
758 	if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
759 #ifdef CONFIG_X86_64
760 		if ((vcpu->arch.efer & EFER_LME)) {
761 			int cs_db, cs_l;
762 
763 			if (!is_pae(vcpu))
764 				return 1;
765 			kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
766 			if (cs_l)
767 				return 1;
768 		} else
769 #endif
770 		if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
771 						 kvm_read_cr3(vcpu)))
772 			return 1;
773 	}
774 
775 	if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
776 		return 1;
777 
778 	kvm_x86_ops->set_cr0(vcpu, cr0);
779 
780 	if ((cr0 ^ old_cr0) & X86_CR0_PG) {
781 		kvm_clear_async_pf_completion_queue(vcpu);
782 		kvm_async_pf_hash_reset(vcpu);
783 	}
784 
785 	if ((cr0 ^ old_cr0) & update_bits)
786 		kvm_mmu_reset_context(vcpu);
787 
788 	if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
789 	    kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
790 	    !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
791 		kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
792 
793 	return 0;
794 }
795 EXPORT_SYMBOL_GPL(kvm_set_cr0);
796 
797 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
798 {
799 	(void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
800 }
801 EXPORT_SYMBOL_GPL(kvm_lmsw);
802 
803 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
804 {
805 	if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
806 			!vcpu->guest_xcr0_loaded) {
807 		/* kvm_set_xcr() also depends on this */
808 		if (vcpu->arch.xcr0 != host_xcr0)
809 			xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
810 		vcpu->guest_xcr0_loaded = 1;
811 	}
812 }
813 
814 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
815 {
816 	if (vcpu->guest_xcr0_loaded) {
817 		if (vcpu->arch.xcr0 != host_xcr0)
818 			xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
819 		vcpu->guest_xcr0_loaded = 0;
820 	}
821 }
822 
823 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
824 {
825 	u64 xcr0 = xcr;
826 	u64 old_xcr0 = vcpu->arch.xcr0;
827 	u64 valid_bits;
828 
829 	/* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
830 	if (index != XCR_XFEATURE_ENABLED_MASK)
831 		return 1;
832 	if (!(xcr0 & XFEATURE_MASK_FP))
833 		return 1;
834 	if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
835 		return 1;
836 
837 	/*
838 	 * Do not allow the guest to set bits that we do not support
839 	 * saving.  However, xcr0 bit 0 is always set, even if the
840 	 * emulated CPU does not support XSAVE (see fx_init).
841 	 */
842 	valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
843 	if (xcr0 & ~valid_bits)
844 		return 1;
845 
846 	if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
847 	    (!(xcr0 & XFEATURE_MASK_BNDCSR)))
848 		return 1;
849 
850 	if (xcr0 & XFEATURE_MASK_AVX512) {
851 		if (!(xcr0 & XFEATURE_MASK_YMM))
852 			return 1;
853 		if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
854 			return 1;
855 	}
856 	vcpu->arch.xcr0 = xcr0;
857 
858 	if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
859 		kvm_update_cpuid(vcpu);
860 	return 0;
861 }
862 
863 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
864 {
865 	if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
866 	    __kvm_set_xcr(vcpu, index, xcr)) {
867 		kvm_inject_gp(vcpu, 0);
868 		return 1;
869 	}
870 	return 0;
871 }
872 EXPORT_SYMBOL_GPL(kvm_set_xcr);
873 
874 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
875 {
876 	unsigned long old_cr4 = kvm_read_cr4(vcpu);
877 	unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
878 				   X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
879 
880 	if (cr4 & CR4_RESERVED_BITS)
881 		return 1;
882 
883 	if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
884 		return 1;
885 
886 	if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
887 		return 1;
888 
889 	if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
890 		return 1;
891 
892 	if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
893 		return 1;
894 
895 	if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
896 		return 1;
897 
898 	if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
899 		return 1;
900 
901 	if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
902 		return 1;
903 
904 	if (is_long_mode(vcpu)) {
905 		if (!(cr4 & X86_CR4_PAE))
906 			return 1;
907 	} else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
908 		   && ((cr4 ^ old_cr4) & pdptr_bits)
909 		   && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
910 				   kvm_read_cr3(vcpu)))
911 		return 1;
912 
913 	if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
914 		if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
915 			return 1;
916 
917 		/* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
918 		if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
919 			return 1;
920 	}
921 
922 	if (kvm_x86_ops->set_cr4(vcpu, cr4))
923 		return 1;
924 
925 	if (((cr4 ^ old_cr4) & pdptr_bits) ||
926 	    (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
927 		kvm_mmu_reset_context(vcpu);
928 
929 	if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
930 		kvm_update_cpuid(vcpu);
931 
932 	return 0;
933 }
934 EXPORT_SYMBOL_GPL(kvm_set_cr4);
935 
936 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
937 {
938 	bool skip_tlb_flush = false;
939 #ifdef CONFIG_X86_64
940 	bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
941 
942 	if (pcid_enabled) {
943 		skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
944 		cr3 &= ~X86_CR3_PCID_NOFLUSH;
945 	}
946 #endif
947 
948 	if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
949 		if (!skip_tlb_flush) {
950 			kvm_mmu_sync_roots(vcpu);
951 			kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
952 		}
953 		return 0;
954 	}
955 
956 	if (is_long_mode(vcpu) &&
957 	    (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
958 		return 1;
959 	else if (is_pae(vcpu) && is_paging(vcpu) &&
960 		   !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
961 		return 1;
962 
963 	kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
964 	vcpu->arch.cr3 = cr3;
965 	__set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
966 
967 	return 0;
968 }
969 EXPORT_SYMBOL_GPL(kvm_set_cr3);
970 
971 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
972 {
973 	if (cr8 & CR8_RESERVED_BITS)
974 		return 1;
975 	if (lapic_in_kernel(vcpu))
976 		kvm_lapic_set_tpr(vcpu, cr8);
977 	else
978 		vcpu->arch.cr8 = cr8;
979 	return 0;
980 }
981 EXPORT_SYMBOL_GPL(kvm_set_cr8);
982 
983 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
984 {
985 	if (lapic_in_kernel(vcpu))
986 		return kvm_lapic_get_cr8(vcpu);
987 	else
988 		return vcpu->arch.cr8;
989 }
990 EXPORT_SYMBOL_GPL(kvm_get_cr8);
991 
992 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
993 {
994 	int i;
995 
996 	if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
997 		for (i = 0; i < KVM_NR_DB_REGS; i++)
998 			vcpu->arch.eff_db[i] = vcpu->arch.db[i];
999 		vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1000 	}
1001 }
1002 
1003 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1004 {
1005 	if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1006 		kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1007 }
1008 
1009 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1010 {
1011 	unsigned long dr7;
1012 
1013 	if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1014 		dr7 = vcpu->arch.guest_debug_dr7;
1015 	else
1016 		dr7 = vcpu->arch.dr7;
1017 	kvm_x86_ops->set_dr7(vcpu, dr7);
1018 	vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1019 	if (dr7 & DR7_BP_EN_MASK)
1020 		vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1021 }
1022 
1023 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1024 {
1025 	u64 fixed = DR6_FIXED_1;
1026 
1027 	if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1028 		fixed |= DR6_RTM;
1029 	return fixed;
1030 }
1031 
1032 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1033 {
1034 	switch (dr) {
1035 	case 0 ... 3:
1036 		vcpu->arch.db[dr] = val;
1037 		if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1038 			vcpu->arch.eff_db[dr] = val;
1039 		break;
1040 	case 4:
1041 		/* fall through */
1042 	case 6:
1043 		if (val & 0xffffffff00000000ULL)
1044 			return -1; /* #GP */
1045 		vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1046 		kvm_update_dr6(vcpu);
1047 		break;
1048 	case 5:
1049 		/* fall through */
1050 	default: /* 7 */
1051 		if (val & 0xffffffff00000000ULL)
1052 			return -1; /* #GP */
1053 		vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1054 		kvm_update_dr7(vcpu);
1055 		break;
1056 	}
1057 
1058 	return 0;
1059 }
1060 
1061 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1062 {
1063 	if (__kvm_set_dr(vcpu, dr, val)) {
1064 		kvm_inject_gp(vcpu, 0);
1065 		return 1;
1066 	}
1067 	return 0;
1068 }
1069 EXPORT_SYMBOL_GPL(kvm_set_dr);
1070 
1071 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1072 {
1073 	switch (dr) {
1074 	case 0 ... 3:
1075 		*val = vcpu->arch.db[dr];
1076 		break;
1077 	case 4:
1078 		/* fall through */
1079 	case 6:
1080 		if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1081 			*val = vcpu->arch.dr6;
1082 		else
1083 			*val = kvm_x86_ops->get_dr6(vcpu);
1084 		break;
1085 	case 5:
1086 		/* fall through */
1087 	default: /* 7 */
1088 		*val = vcpu->arch.dr7;
1089 		break;
1090 	}
1091 	return 0;
1092 }
1093 EXPORT_SYMBOL_GPL(kvm_get_dr);
1094 
1095 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1096 {
1097 	u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1098 	u64 data;
1099 	int err;
1100 
1101 	err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1102 	if (err)
1103 		return err;
1104 	kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1105 	kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1106 	return err;
1107 }
1108 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1109 
1110 /*
1111  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1112  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1113  *
1114  * This list is modified at module load time to reflect the
1115  * capabilities of the host cpu. This capabilities test skips MSRs that are
1116  * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1117  * may depend on host virtualization features rather than host cpu features.
1118  */
1119 
1120 static u32 msrs_to_save[] = {
1121 	MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1122 	MSR_STAR,
1123 #ifdef CONFIG_X86_64
1124 	MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1125 #endif
1126 	MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1127 	MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1128 	MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES,
1129 	MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1130 	MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1131 	MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1132 	MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1133 	MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1134 	MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1135 };
1136 
1137 static unsigned num_msrs_to_save;
1138 
1139 static u32 emulated_msrs[] = {
1140 	MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1141 	MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1142 	HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1143 	HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1144 	HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1145 	HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1146 	HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1147 	HV_X64_MSR_RESET,
1148 	HV_X64_MSR_VP_INDEX,
1149 	HV_X64_MSR_VP_RUNTIME,
1150 	HV_X64_MSR_SCONTROL,
1151 	HV_X64_MSR_STIMER0_CONFIG,
1152 	HV_X64_MSR_VP_ASSIST_PAGE,
1153 	HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1154 	HV_X64_MSR_TSC_EMULATION_STATUS,
1155 
1156 	MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1157 	MSR_KVM_PV_EOI_EN,
1158 
1159 	MSR_IA32_TSC_ADJUST,
1160 	MSR_IA32_TSCDEADLINE,
1161 	MSR_IA32_MISC_ENABLE,
1162 	MSR_IA32_MCG_STATUS,
1163 	MSR_IA32_MCG_CTL,
1164 	MSR_IA32_MCG_EXT_CTL,
1165 	MSR_IA32_SMBASE,
1166 	MSR_SMI_COUNT,
1167 	MSR_PLATFORM_INFO,
1168 	MSR_MISC_FEATURES_ENABLES,
1169 	MSR_AMD64_VIRT_SPEC_CTRL,
1170 };
1171 
1172 static unsigned num_emulated_msrs;
1173 
1174 /*
1175  * List of msr numbers which are used to expose MSR-based features that
1176  * can be used by a hypervisor to validate requested CPU features.
1177  */
1178 static u32 msr_based_features[] = {
1179 	MSR_IA32_VMX_BASIC,
1180 	MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1181 	MSR_IA32_VMX_PINBASED_CTLS,
1182 	MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1183 	MSR_IA32_VMX_PROCBASED_CTLS,
1184 	MSR_IA32_VMX_TRUE_EXIT_CTLS,
1185 	MSR_IA32_VMX_EXIT_CTLS,
1186 	MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1187 	MSR_IA32_VMX_ENTRY_CTLS,
1188 	MSR_IA32_VMX_MISC,
1189 	MSR_IA32_VMX_CR0_FIXED0,
1190 	MSR_IA32_VMX_CR0_FIXED1,
1191 	MSR_IA32_VMX_CR4_FIXED0,
1192 	MSR_IA32_VMX_CR4_FIXED1,
1193 	MSR_IA32_VMX_VMCS_ENUM,
1194 	MSR_IA32_VMX_PROCBASED_CTLS2,
1195 	MSR_IA32_VMX_EPT_VPID_CAP,
1196 	MSR_IA32_VMX_VMFUNC,
1197 
1198 	MSR_F10H_DECFG,
1199 	MSR_IA32_UCODE_REV,
1200 	MSR_IA32_ARCH_CAPABILITIES,
1201 };
1202 
1203 static unsigned int num_msr_based_features;
1204 
1205 u64 kvm_get_arch_capabilities(void)
1206 {
1207 	u64 data;
1208 
1209 	rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1210 
1211 	/*
1212 	 * If we're doing cache flushes (either "always" or "cond")
1213 	 * we will do one whenever the guest does a vmlaunch/vmresume.
1214 	 * If an outer hypervisor is doing the cache flush for us
1215 	 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1216 	 * capability to the guest too, and if EPT is disabled we're not
1217 	 * vulnerable.  Overall, only VMENTER_L1D_FLUSH_NEVER will
1218 	 * require a nested hypervisor to do a flush of its own.
1219 	 */
1220 	if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1221 		data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1222 
1223 	return data;
1224 }
1225 EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1226 
1227 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1228 {
1229 	switch (msr->index) {
1230 	case MSR_IA32_ARCH_CAPABILITIES:
1231 		msr->data = kvm_get_arch_capabilities();
1232 		break;
1233 	case MSR_IA32_UCODE_REV:
1234 		rdmsrl_safe(msr->index, &msr->data);
1235 		break;
1236 	default:
1237 		if (kvm_x86_ops->get_msr_feature(msr))
1238 			return 1;
1239 	}
1240 	return 0;
1241 }
1242 
1243 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1244 {
1245 	struct kvm_msr_entry msr;
1246 	int r;
1247 
1248 	msr.index = index;
1249 	r = kvm_get_msr_feature(&msr);
1250 	if (r)
1251 		return r;
1252 
1253 	*data = msr.data;
1254 
1255 	return 0;
1256 }
1257 
1258 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1259 {
1260 	if (efer & efer_reserved_bits)
1261 		return false;
1262 
1263 	if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1264 			return false;
1265 
1266 	if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1267 			return false;
1268 
1269 	return true;
1270 }
1271 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1272 
1273 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1274 {
1275 	u64 old_efer = vcpu->arch.efer;
1276 
1277 	if (!kvm_valid_efer(vcpu, efer))
1278 		return 1;
1279 
1280 	if (is_paging(vcpu)
1281 	    && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1282 		return 1;
1283 
1284 	efer &= ~EFER_LMA;
1285 	efer |= vcpu->arch.efer & EFER_LMA;
1286 
1287 	kvm_x86_ops->set_efer(vcpu, efer);
1288 
1289 	/* Update reserved bits */
1290 	if ((efer ^ old_efer) & EFER_NX)
1291 		kvm_mmu_reset_context(vcpu);
1292 
1293 	return 0;
1294 }
1295 
1296 void kvm_enable_efer_bits(u64 mask)
1297 {
1298        efer_reserved_bits &= ~mask;
1299 }
1300 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1301 
1302 /*
1303  * Writes msr value into into the appropriate "register".
1304  * Returns 0 on success, non-0 otherwise.
1305  * Assumes vcpu_load() was already called.
1306  */
1307 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1308 {
1309 	switch (msr->index) {
1310 	case MSR_FS_BASE:
1311 	case MSR_GS_BASE:
1312 	case MSR_KERNEL_GS_BASE:
1313 	case MSR_CSTAR:
1314 	case MSR_LSTAR:
1315 		if (is_noncanonical_address(msr->data, vcpu))
1316 			return 1;
1317 		break;
1318 	case MSR_IA32_SYSENTER_EIP:
1319 	case MSR_IA32_SYSENTER_ESP:
1320 		/*
1321 		 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1322 		 * non-canonical address is written on Intel but not on
1323 		 * AMD (which ignores the top 32-bits, because it does
1324 		 * not implement 64-bit SYSENTER).
1325 		 *
1326 		 * 64-bit code should hence be able to write a non-canonical
1327 		 * value on AMD.  Making the address canonical ensures that
1328 		 * vmentry does not fail on Intel after writing a non-canonical
1329 		 * value, and that something deterministic happens if the guest
1330 		 * invokes 64-bit SYSENTER.
1331 		 */
1332 		msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
1333 	}
1334 	return kvm_x86_ops->set_msr(vcpu, msr);
1335 }
1336 EXPORT_SYMBOL_GPL(kvm_set_msr);
1337 
1338 /*
1339  * Adapt set_msr() to msr_io()'s calling convention
1340  */
1341 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1342 {
1343 	struct msr_data msr;
1344 	int r;
1345 
1346 	msr.index = index;
1347 	msr.host_initiated = true;
1348 	r = kvm_get_msr(vcpu, &msr);
1349 	if (r)
1350 		return r;
1351 
1352 	*data = msr.data;
1353 	return 0;
1354 }
1355 
1356 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1357 {
1358 	struct msr_data msr;
1359 
1360 	msr.data = *data;
1361 	msr.index = index;
1362 	msr.host_initiated = true;
1363 	return kvm_set_msr(vcpu, &msr);
1364 }
1365 
1366 #ifdef CONFIG_X86_64
1367 struct pvclock_gtod_data {
1368 	seqcount_t	seq;
1369 
1370 	struct { /* extract of a clocksource struct */
1371 		int vclock_mode;
1372 		u64	cycle_last;
1373 		u64	mask;
1374 		u32	mult;
1375 		u32	shift;
1376 	} clock;
1377 
1378 	u64		boot_ns;
1379 	u64		nsec_base;
1380 	u64		wall_time_sec;
1381 };
1382 
1383 static struct pvclock_gtod_data pvclock_gtod_data;
1384 
1385 static void update_pvclock_gtod(struct timekeeper *tk)
1386 {
1387 	struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1388 	u64 boot_ns;
1389 
1390 	boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1391 
1392 	write_seqcount_begin(&vdata->seq);
1393 
1394 	/* copy pvclock gtod data */
1395 	vdata->clock.vclock_mode	= tk->tkr_mono.clock->archdata.vclock_mode;
1396 	vdata->clock.cycle_last		= tk->tkr_mono.cycle_last;
1397 	vdata->clock.mask		= tk->tkr_mono.mask;
1398 	vdata->clock.mult		= tk->tkr_mono.mult;
1399 	vdata->clock.shift		= tk->tkr_mono.shift;
1400 
1401 	vdata->boot_ns			= boot_ns;
1402 	vdata->nsec_base		= tk->tkr_mono.xtime_nsec;
1403 
1404 	vdata->wall_time_sec            = tk->xtime_sec;
1405 
1406 	write_seqcount_end(&vdata->seq);
1407 }
1408 #endif
1409 
1410 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1411 {
1412 	/*
1413 	 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1414 	 * vcpu_enter_guest.  This function is only called from
1415 	 * the physical CPU that is running vcpu.
1416 	 */
1417 	kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1418 }
1419 
1420 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1421 {
1422 	int version;
1423 	int r;
1424 	struct pvclock_wall_clock wc;
1425 	struct timespec64 boot;
1426 
1427 	if (!wall_clock)
1428 		return;
1429 
1430 	r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1431 	if (r)
1432 		return;
1433 
1434 	if (version & 1)
1435 		++version;  /* first time write, random junk */
1436 
1437 	++version;
1438 
1439 	if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1440 		return;
1441 
1442 	/*
1443 	 * The guest calculates current wall clock time by adding
1444 	 * system time (updated by kvm_guest_time_update below) to the
1445 	 * wall clock specified here.  guest system time equals host
1446 	 * system time for us, thus we must fill in host boot time here.
1447 	 */
1448 	getboottime64(&boot);
1449 
1450 	if (kvm->arch.kvmclock_offset) {
1451 		struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1452 		boot = timespec64_sub(boot, ts);
1453 	}
1454 	wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1455 	wc.nsec = boot.tv_nsec;
1456 	wc.version = version;
1457 
1458 	kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1459 
1460 	version++;
1461 	kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1462 }
1463 
1464 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1465 {
1466 	do_shl32_div32(dividend, divisor);
1467 	return dividend;
1468 }
1469 
1470 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1471 			       s8 *pshift, u32 *pmultiplier)
1472 {
1473 	uint64_t scaled64;
1474 	int32_t  shift = 0;
1475 	uint64_t tps64;
1476 	uint32_t tps32;
1477 
1478 	tps64 = base_hz;
1479 	scaled64 = scaled_hz;
1480 	while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1481 		tps64 >>= 1;
1482 		shift--;
1483 	}
1484 
1485 	tps32 = (uint32_t)tps64;
1486 	while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1487 		if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1488 			scaled64 >>= 1;
1489 		else
1490 			tps32 <<= 1;
1491 		shift++;
1492 	}
1493 
1494 	*pshift = shift;
1495 	*pmultiplier = div_frac(scaled64, tps32);
1496 
1497 	pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1498 		 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1499 }
1500 
1501 #ifdef CONFIG_X86_64
1502 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1503 #endif
1504 
1505 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1506 static unsigned long max_tsc_khz;
1507 
1508 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1509 {
1510 	u64 v = (u64)khz * (1000000 + ppm);
1511 	do_div(v, 1000000);
1512 	return v;
1513 }
1514 
1515 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1516 {
1517 	u64 ratio;
1518 
1519 	/* Guest TSC same frequency as host TSC? */
1520 	if (!scale) {
1521 		vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1522 		return 0;
1523 	}
1524 
1525 	/* TSC scaling supported? */
1526 	if (!kvm_has_tsc_control) {
1527 		if (user_tsc_khz > tsc_khz) {
1528 			vcpu->arch.tsc_catchup = 1;
1529 			vcpu->arch.tsc_always_catchup = 1;
1530 			return 0;
1531 		} else {
1532 			WARN(1, "user requested TSC rate below hardware speed\n");
1533 			return -1;
1534 		}
1535 	}
1536 
1537 	/* TSC scaling required  - calculate ratio */
1538 	ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1539 				user_tsc_khz, tsc_khz);
1540 
1541 	if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1542 		WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1543 			  user_tsc_khz);
1544 		return -1;
1545 	}
1546 
1547 	vcpu->arch.tsc_scaling_ratio = ratio;
1548 	return 0;
1549 }
1550 
1551 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1552 {
1553 	u32 thresh_lo, thresh_hi;
1554 	int use_scaling = 0;
1555 
1556 	/* tsc_khz can be zero if TSC calibration fails */
1557 	if (user_tsc_khz == 0) {
1558 		/* set tsc_scaling_ratio to a safe value */
1559 		vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1560 		return -1;
1561 	}
1562 
1563 	/* Compute a scale to convert nanoseconds in TSC cycles */
1564 	kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1565 			   &vcpu->arch.virtual_tsc_shift,
1566 			   &vcpu->arch.virtual_tsc_mult);
1567 	vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1568 
1569 	/*
1570 	 * Compute the variation in TSC rate which is acceptable
1571 	 * within the range of tolerance and decide if the
1572 	 * rate being applied is within that bounds of the hardware
1573 	 * rate.  If so, no scaling or compensation need be done.
1574 	 */
1575 	thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1576 	thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1577 	if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1578 		pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1579 		use_scaling = 1;
1580 	}
1581 	return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1582 }
1583 
1584 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1585 {
1586 	u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1587 				      vcpu->arch.virtual_tsc_mult,
1588 				      vcpu->arch.virtual_tsc_shift);
1589 	tsc += vcpu->arch.this_tsc_write;
1590 	return tsc;
1591 }
1592 
1593 static inline int gtod_is_based_on_tsc(int mode)
1594 {
1595 	return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1596 }
1597 
1598 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1599 {
1600 #ifdef CONFIG_X86_64
1601 	bool vcpus_matched;
1602 	struct kvm_arch *ka = &vcpu->kvm->arch;
1603 	struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1604 
1605 	vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1606 			 atomic_read(&vcpu->kvm->online_vcpus));
1607 
1608 	/*
1609 	 * Once the masterclock is enabled, always perform request in
1610 	 * order to update it.
1611 	 *
1612 	 * In order to enable masterclock, the host clocksource must be TSC
1613 	 * and the vcpus need to have matched TSCs.  When that happens,
1614 	 * perform request to enable masterclock.
1615 	 */
1616 	if (ka->use_master_clock ||
1617 	    (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1618 		kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1619 
1620 	trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1621 			    atomic_read(&vcpu->kvm->online_vcpus),
1622 		            ka->use_master_clock, gtod->clock.vclock_mode);
1623 #endif
1624 }
1625 
1626 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1627 {
1628 	u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1629 	vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1630 }
1631 
1632 /*
1633  * Multiply tsc by a fixed point number represented by ratio.
1634  *
1635  * The most significant 64-N bits (mult) of ratio represent the
1636  * integral part of the fixed point number; the remaining N bits
1637  * (frac) represent the fractional part, ie. ratio represents a fixed
1638  * point number (mult + frac * 2^(-N)).
1639  *
1640  * N equals to kvm_tsc_scaling_ratio_frac_bits.
1641  */
1642 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1643 {
1644 	return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1645 }
1646 
1647 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1648 {
1649 	u64 _tsc = tsc;
1650 	u64 ratio = vcpu->arch.tsc_scaling_ratio;
1651 
1652 	if (ratio != kvm_default_tsc_scaling_ratio)
1653 		_tsc = __scale_tsc(ratio, tsc);
1654 
1655 	return _tsc;
1656 }
1657 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1658 
1659 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1660 {
1661 	u64 tsc;
1662 
1663 	tsc = kvm_scale_tsc(vcpu, rdtsc());
1664 
1665 	return target_tsc - tsc;
1666 }
1667 
1668 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1669 {
1670 	u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1671 
1672 	return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1673 }
1674 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1675 
1676 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1677 {
1678 	vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1679 }
1680 
1681 static inline bool kvm_check_tsc_unstable(void)
1682 {
1683 #ifdef CONFIG_X86_64
1684 	/*
1685 	 * TSC is marked unstable when we're running on Hyper-V,
1686 	 * 'TSC page' clocksource is good.
1687 	 */
1688 	if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1689 		return false;
1690 #endif
1691 	return check_tsc_unstable();
1692 }
1693 
1694 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1695 {
1696 	struct kvm *kvm = vcpu->kvm;
1697 	u64 offset, ns, elapsed;
1698 	unsigned long flags;
1699 	bool matched;
1700 	bool already_matched;
1701 	u64 data = msr->data;
1702 	bool synchronizing = false;
1703 
1704 	raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1705 	offset = kvm_compute_tsc_offset(vcpu, data);
1706 	ns = ktime_get_boot_ns();
1707 	elapsed = ns - kvm->arch.last_tsc_nsec;
1708 
1709 	if (vcpu->arch.virtual_tsc_khz) {
1710 		if (data == 0 && msr->host_initiated) {
1711 			/*
1712 			 * detection of vcpu initialization -- need to sync
1713 			 * with other vCPUs. This particularly helps to keep
1714 			 * kvm_clock stable after CPU hotplug
1715 			 */
1716 			synchronizing = true;
1717 		} else {
1718 			u64 tsc_exp = kvm->arch.last_tsc_write +
1719 						nsec_to_cycles(vcpu, elapsed);
1720 			u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1721 			/*
1722 			 * Special case: TSC write with a small delta (1 second)
1723 			 * of virtual cycle time against real time is
1724 			 * interpreted as an attempt to synchronize the CPU.
1725 			 */
1726 			synchronizing = data < tsc_exp + tsc_hz &&
1727 					data + tsc_hz > tsc_exp;
1728 		}
1729 	}
1730 
1731 	/*
1732 	 * For a reliable TSC, we can match TSC offsets, and for an unstable
1733 	 * TSC, we add elapsed time in this computation.  We could let the
1734 	 * compensation code attempt to catch up if we fall behind, but
1735 	 * it's better to try to match offsets from the beginning.
1736          */
1737 	if (synchronizing &&
1738 	    vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1739 		if (!kvm_check_tsc_unstable()) {
1740 			offset = kvm->arch.cur_tsc_offset;
1741 			pr_debug("kvm: matched tsc offset for %llu\n", data);
1742 		} else {
1743 			u64 delta = nsec_to_cycles(vcpu, elapsed);
1744 			data += delta;
1745 			offset = kvm_compute_tsc_offset(vcpu, data);
1746 			pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1747 		}
1748 		matched = true;
1749 		already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1750 	} else {
1751 		/*
1752 		 * We split periods of matched TSC writes into generations.
1753 		 * For each generation, we track the original measured
1754 		 * nanosecond time, offset, and write, so if TSCs are in
1755 		 * sync, we can match exact offset, and if not, we can match
1756 		 * exact software computation in compute_guest_tsc()
1757 		 *
1758 		 * These values are tracked in kvm->arch.cur_xxx variables.
1759 		 */
1760 		kvm->arch.cur_tsc_generation++;
1761 		kvm->arch.cur_tsc_nsec = ns;
1762 		kvm->arch.cur_tsc_write = data;
1763 		kvm->arch.cur_tsc_offset = offset;
1764 		matched = false;
1765 		pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1766 			 kvm->arch.cur_tsc_generation, data);
1767 	}
1768 
1769 	/*
1770 	 * We also track th most recent recorded KHZ, write and time to
1771 	 * allow the matching interval to be extended at each write.
1772 	 */
1773 	kvm->arch.last_tsc_nsec = ns;
1774 	kvm->arch.last_tsc_write = data;
1775 	kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1776 
1777 	vcpu->arch.last_guest_tsc = data;
1778 
1779 	/* Keep track of which generation this VCPU has synchronized to */
1780 	vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1781 	vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1782 	vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1783 
1784 	if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1785 		update_ia32_tsc_adjust_msr(vcpu, offset);
1786 
1787 	kvm_vcpu_write_tsc_offset(vcpu, offset);
1788 	raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1789 
1790 	spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1791 	if (!matched) {
1792 		kvm->arch.nr_vcpus_matched_tsc = 0;
1793 	} else if (!already_matched) {
1794 		kvm->arch.nr_vcpus_matched_tsc++;
1795 	}
1796 
1797 	kvm_track_tsc_matching(vcpu);
1798 	spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1799 }
1800 
1801 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1802 
1803 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1804 					   s64 adjustment)
1805 {
1806 	u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1807 	kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
1808 }
1809 
1810 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1811 {
1812 	if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1813 		WARN_ON(adjustment < 0);
1814 	adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1815 	adjust_tsc_offset_guest(vcpu, adjustment);
1816 }
1817 
1818 #ifdef CONFIG_X86_64
1819 
1820 static u64 read_tsc(void)
1821 {
1822 	u64 ret = (u64)rdtsc_ordered();
1823 	u64 last = pvclock_gtod_data.clock.cycle_last;
1824 
1825 	if (likely(ret >= last))
1826 		return ret;
1827 
1828 	/*
1829 	 * GCC likes to generate cmov here, but this branch is extremely
1830 	 * predictable (it's just a function of time and the likely is
1831 	 * very likely) and there's a data dependence, so force GCC
1832 	 * to generate a branch instead.  I don't barrier() because
1833 	 * we don't actually need a barrier, and if this function
1834 	 * ever gets inlined it will generate worse code.
1835 	 */
1836 	asm volatile ("");
1837 	return last;
1838 }
1839 
1840 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
1841 {
1842 	long v;
1843 	struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1844 	u64 tsc_pg_val;
1845 
1846 	switch (gtod->clock.vclock_mode) {
1847 	case VCLOCK_HVCLOCK:
1848 		tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1849 						  tsc_timestamp);
1850 		if (tsc_pg_val != U64_MAX) {
1851 			/* TSC page valid */
1852 			*mode = VCLOCK_HVCLOCK;
1853 			v = (tsc_pg_val - gtod->clock.cycle_last) &
1854 				gtod->clock.mask;
1855 		} else {
1856 			/* TSC page invalid */
1857 			*mode = VCLOCK_NONE;
1858 		}
1859 		break;
1860 	case VCLOCK_TSC:
1861 		*mode = VCLOCK_TSC;
1862 		*tsc_timestamp = read_tsc();
1863 		v = (*tsc_timestamp - gtod->clock.cycle_last) &
1864 			gtod->clock.mask;
1865 		break;
1866 	default:
1867 		*mode = VCLOCK_NONE;
1868 	}
1869 
1870 	if (*mode == VCLOCK_NONE)
1871 		*tsc_timestamp = v = 0;
1872 
1873 	return v * gtod->clock.mult;
1874 }
1875 
1876 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
1877 {
1878 	struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1879 	unsigned long seq;
1880 	int mode;
1881 	u64 ns;
1882 
1883 	do {
1884 		seq = read_seqcount_begin(&gtod->seq);
1885 		ns = gtod->nsec_base;
1886 		ns += vgettsc(tsc_timestamp, &mode);
1887 		ns >>= gtod->clock.shift;
1888 		ns += gtod->boot_ns;
1889 	} while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1890 	*t = ns;
1891 
1892 	return mode;
1893 }
1894 
1895 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
1896 {
1897 	struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1898 	unsigned long seq;
1899 	int mode;
1900 	u64 ns;
1901 
1902 	do {
1903 		seq = read_seqcount_begin(&gtod->seq);
1904 		ts->tv_sec = gtod->wall_time_sec;
1905 		ns = gtod->nsec_base;
1906 		ns += vgettsc(tsc_timestamp, &mode);
1907 		ns >>= gtod->clock.shift;
1908 	} while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1909 
1910 	ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1911 	ts->tv_nsec = ns;
1912 
1913 	return mode;
1914 }
1915 
1916 /* returns true if host is using TSC based clocksource */
1917 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
1918 {
1919 	/* checked again under seqlock below */
1920 	if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1921 		return false;
1922 
1923 	return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1924 						      tsc_timestamp));
1925 }
1926 
1927 /* returns true if host is using TSC based clocksource */
1928 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
1929 					   u64 *tsc_timestamp)
1930 {
1931 	/* checked again under seqlock below */
1932 	if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1933 		return false;
1934 
1935 	return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
1936 }
1937 #endif
1938 
1939 /*
1940  *
1941  * Assuming a stable TSC across physical CPUS, and a stable TSC
1942  * across virtual CPUs, the following condition is possible.
1943  * Each numbered line represents an event visible to both
1944  * CPUs at the next numbered event.
1945  *
1946  * "timespecX" represents host monotonic time. "tscX" represents
1947  * RDTSC value.
1948  *
1949  * 		VCPU0 on CPU0		|	VCPU1 on CPU1
1950  *
1951  * 1.  read timespec0,tsc0
1952  * 2.					| timespec1 = timespec0 + N
1953  * 					| tsc1 = tsc0 + M
1954  * 3. transition to guest		| transition to guest
1955  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1956  * 5.				        | ret1 = timespec1 + (rdtsc - tsc1)
1957  * 				        | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1958  *
1959  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1960  *
1961  * 	- ret0 < ret1
1962  *	- timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1963  *		...
1964  *	- 0 < N - M => M < N
1965  *
1966  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1967  * always the case (the difference between two distinct xtime instances
1968  * might be smaller then the difference between corresponding TSC reads,
1969  * when updating guest vcpus pvclock areas).
1970  *
1971  * To avoid that problem, do not allow visibility of distinct
1972  * system_timestamp/tsc_timestamp values simultaneously: use a master
1973  * copy of host monotonic time values. Update that master copy
1974  * in lockstep.
1975  *
1976  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1977  *
1978  */
1979 
1980 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1981 {
1982 #ifdef CONFIG_X86_64
1983 	struct kvm_arch *ka = &kvm->arch;
1984 	int vclock_mode;
1985 	bool host_tsc_clocksource, vcpus_matched;
1986 
1987 	vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1988 			atomic_read(&kvm->online_vcpus));
1989 
1990 	/*
1991 	 * If the host uses TSC clock, then passthrough TSC as stable
1992 	 * to the guest.
1993 	 */
1994 	host_tsc_clocksource = kvm_get_time_and_clockread(
1995 					&ka->master_kernel_ns,
1996 					&ka->master_cycle_now);
1997 
1998 	ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1999 				&& !ka->backwards_tsc_observed
2000 				&& !ka->boot_vcpu_runs_old_kvmclock;
2001 
2002 	if (ka->use_master_clock)
2003 		atomic_set(&kvm_guest_has_master_clock, 1);
2004 
2005 	vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2006 	trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2007 					vcpus_matched);
2008 #endif
2009 }
2010 
2011 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2012 {
2013 	kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2014 }
2015 
2016 static void kvm_gen_update_masterclock(struct kvm *kvm)
2017 {
2018 #ifdef CONFIG_X86_64
2019 	int i;
2020 	struct kvm_vcpu *vcpu;
2021 	struct kvm_arch *ka = &kvm->arch;
2022 
2023 	spin_lock(&ka->pvclock_gtod_sync_lock);
2024 	kvm_make_mclock_inprogress_request(kvm);
2025 	/* no guest entries from this point */
2026 	pvclock_update_vm_gtod_copy(kvm);
2027 
2028 	kvm_for_each_vcpu(i, vcpu, kvm)
2029 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2030 
2031 	/* guest entries allowed */
2032 	kvm_for_each_vcpu(i, vcpu, kvm)
2033 		kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2034 
2035 	spin_unlock(&ka->pvclock_gtod_sync_lock);
2036 #endif
2037 }
2038 
2039 u64 get_kvmclock_ns(struct kvm *kvm)
2040 {
2041 	struct kvm_arch *ka = &kvm->arch;
2042 	struct pvclock_vcpu_time_info hv_clock;
2043 	u64 ret;
2044 
2045 	spin_lock(&ka->pvclock_gtod_sync_lock);
2046 	if (!ka->use_master_clock) {
2047 		spin_unlock(&ka->pvclock_gtod_sync_lock);
2048 		return ktime_get_boot_ns() + ka->kvmclock_offset;
2049 	}
2050 
2051 	hv_clock.tsc_timestamp = ka->master_cycle_now;
2052 	hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2053 	spin_unlock(&ka->pvclock_gtod_sync_lock);
2054 
2055 	/* both __this_cpu_read() and rdtsc() should be on the same cpu */
2056 	get_cpu();
2057 
2058 	if (__this_cpu_read(cpu_tsc_khz)) {
2059 		kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2060 				   &hv_clock.tsc_shift,
2061 				   &hv_clock.tsc_to_system_mul);
2062 		ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2063 	} else
2064 		ret = ktime_get_boot_ns() + ka->kvmclock_offset;
2065 
2066 	put_cpu();
2067 
2068 	return ret;
2069 }
2070 
2071 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2072 {
2073 	struct kvm_vcpu_arch *vcpu = &v->arch;
2074 	struct pvclock_vcpu_time_info guest_hv_clock;
2075 
2076 	if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2077 		&guest_hv_clock, sizeof(guest_hv_clock))))
2078 		return;
2079 
2080 	/* This VCPU is paused, but it's legal for a guest to read another
2081 	 * VCPU's kvmclock, so we really have to follow the specification where
2082 	 * it says that version is odd if data is being modified, and even after
2083 	 * it is consistent.
2084 	 *
2085 	 * Version field updates must be kept separate.  This is because
2086 	 * kvm_write_guest_cached might use a "rep movs" instruction, and
2087 	 * writes within a string instruction are weakly ordered.  So there
2088 	 * are three writes overall.
2089 	 *
2090 	 * As a small optimization, only write the version field in the first
2091 	 * and third write.  The vcpu->pv_time cache is still valid, because the
2092 	 * version field is the first in the struct.
2093 	 */
2094 	BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2095 
2096 	if (guest_hv_clock.version & 1)
2097 		++guest_hv_clock.version;  /* first time write, random junk */
2098 
2099 	vcpu->hv_clock.version = guest_hv_clock.version + 1;
2100 	kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2101 				&vcpu->hv_clock,
2102 				sizeof(vcpu->hv_clock.version));
2103 
2104 	smp_wmb();
2105 
2106 	/* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2107 	vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2108 
2109 	if (vcpu->pvclock_set_guest_stopped_request) {
2110 		vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2111 		vcpu->pvclock_set_guest_stopped_request = false;
2112 	}
2113 
2114 	trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2115 
2116 	kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2117 				&vcpu->hv_clock,
2118 				sizeof(vcpu->hv_clock));
2119 
2120 	smp_wmb();
2121 
2122 	vcpu->hv_clock.version++;
2123 	kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2124 				&vcpu->hv_clock,
2125 				sizeof(vcpu->hv_clock.version));
2126 }
2127 
2128 static int kvm_guest_time_update(struct kvm_vcpu *v)
2129 {
2130 	unsigned long flags, tgt_tsc_khz;
2131 	struct kvm_vcpu_arch *vcpu = &v->arch;
2132 	struct kvm_arch *ka = &v->kvm->arch;
2133 	s64 kernel_ns;
2134 	u64 tsc_timestamp, host_tsc;
2135 	u8 pvclock_flags;
2136 	bool use_master_clock;
2137 
2138 	kernel_ns = 0;
2139 	host_tsc = 0;
2140 
2141 	/*
2142 	 * If the host uses TSC clock, then passthrough TSC as stable
2143 	 * to the guest.
2144 	 */
2145 	spin_lock(&ka->pvclock_gtod_sync_lock);
2146 	use_master_clock = ka->use_master_clock;
2147 	if (use_master_clock) {
2148 		host_tsc = ka->master_cycle_now;
2149 		kernel_ns = ka->master_kernel_ns;
2150 	}
2151 	spin_unlock(&ka->pvclock_gtod_sync_lock);
2152 
2153 	/* Keep irq disabled to prevent changes to the clock */
2154 	local_irq_save(flags);
2155 	tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2156 	if (unlikely(tgt_tsc_khz == 0)) {
2157 		local_irq_restore(flags);
2158 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2159 		return 1;
2160 	}
2161 	if (!use_master_clock) {
2162 		host_tsc = rdtsc();
2163 		kernel_ns = ktime_get_boot_ns();
2164 	}
2165 
2166 	tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2167 
2168 	/*
2169 	 * We may have to catch up the TSC to match elapsed wall clock
2170 	 * time for two reasons, even if kvmclock is used.
2171 	 *   1) CPU could have been running below the maximum TSC rate
2172 	 *   2) Broken TSC compensation resets the base at each VCPU
2173 	 *      entry to avoid unknown leaps of TSC even when running
2174 	 *      again on the same CPU.  This may cause apparent elapsed
2175 	 *      time to disappear, and the guest to stand still or run
2176 	 *	very slowly.
2177 	 */
2178 	if (vcpu->tsc_catchup) {
2179 		u64 tsc = compute_guest_tsc(v, kernel_ns);
2180 		if (tsc > tsc_timestamp) {
2181 			adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2182 			tsc_timestamp = tsc;
2183 		}
2184 	}
2185 
2186 	local_irq_restore(flags);
2187 
2188 	/* With all the info we got, fill in the values */
2189 
2190 	if (kvm_has_tsc_control)
2191 		tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2192 
2193 	if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2194 		kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2195 				   &vcpu->hv_clock.tsc_shift,
2196 				   &vcpu->hv_clock.tsc_to_system_mul);
2197 		vcpu->hw_tsc_khz = tgt_tsc_khz;
2198 	}
2199 
2200 	vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2201 	vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2202 	vcpu->last_guest_tsc = tsc_timestamp;
2203 
2204 	/* If the host uses TSC clocksource, then it is stable */
2205 	pvclock_flags = 0;
2206 	if (use_master_clock)
2207 		pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2208 
2209 	vcpu->hv_clock.flags = pvclock_flags;
2210 
2211 	if (vcpu->pv_time_enabled)
2212 		kvm_setup_pvclock_page(v);
2213 	if (v == kvm_get_vcpu(v->kvm, 0))
2214 		kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2215 	return 0;
2216 }
2217 
2218 /*
2219  * kvmclock updates which are isolated to a given vcpu, such as
2220  * vcpu->cpu migration, should not allow system_timestamp from
2221  * the rest of the vcpus to remain static. Otherwise ntp frequency
2222  * correction applies to one vcpu's system_timestamp but not
2223  * the others.
2224  *
2225  * So in those cases, request a kvmclock update for all vcpus.
2226  * We need to rate-limit these requests though, as they can
2227  * considerably slow guests that have a large number of vcpus.
2228  * The time for a remote vcpu to update its kvmclock is bound
2229  * by the delay we use to rate-limit the updates.
2230  */
2231 
2232 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2233 
2234 static void kvmclock_update_fn(struct work_struct *work)
2235 {
2236 	int i;
2237 	struct delayed_work *dwork = to_delayed_work(work);
2238 	struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2239 					   kvmclock_update_work);
2240 	struct kvm *kvm = container_of(ka, struct kvm, arch);
2241 	struct kvm_vcpu *vcpu;
2242 
2243 	kvm_for_each_vcpu(i, vcpu, kvm) {
2244 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2245 		kvm_vcpu_kick(vcpu);
2246 	}
2247 }
2248 
2249 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2250 {
2251 	struct kvm *kvm = v->kvm;
2252 
2253 	kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2254 	schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2255 					KVMCLOCK_UPDATE_DELAY);
2256 }
2257 
2258 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2259 
2260 static void kvmclock_sync_fn(struct work_struct *work)
2261 {
2262 	struct delayed_work *dwork = to_delayed_work(work);
2263 	struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2264 					   kvmclock_sync_work);
2265 	struct kvm *kvm = container_of(ka, struct kvm, arch);
2266 
2267 	if (!kvmclock_periodic_sync)
2268 		return;
2269 
2270 	schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2271 	schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2272 					KVMCLOCK_SYNC_PERIOD);
2273 }
2274 
2275 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2276 {
2277 	u64 mcg_cap = vcpu->arch.mcg_cap;
2278 	unsigned bank_num = mcg_cap & 0xff;
2279 	u32 msr = msr_info->index;
2280 	u64 data = msr_info->data;
2281 
2282 	switch (msr) {
2283 	case MSR_IA32_MCG_STATUS:
2284 		vcpu->arch.mcg_status = data;
2285 		break;
2286 	case MSR_IA32_MCG_CTL:
2287 		if (!(mcg_cap & MCG_CTL_P) &&
2288 		    (data || !msr_info->host_initiated))
2289 			return 1;
2290 		if (data != 0 && data != ~(u64)0)
2291 			return 1;
2292 		vcpu->arch.mcg_ctl = data;
2293 		break;
2294 	default:
2295 		if (msr >= MSR_IA32_MC0_CTL &&
2296 		    msr < MSR_IA32_MCx_CTL(bank_num)) {
2297 			u32 offset = msr - MSR_IA32_MC0_CTL;
2298 			/* only 0 or all 1s can be written to IA32_MCi_CTL
2299 			 * some Linux kernels though clear bit 10 in bank 4 to
2300 			 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2301 			 * this to avoid an uncatched #GP in the guest
2302 			 */
2303 			if ((offset & 0x3) == 0 &&
2304 			    data != 0 && (data | (1 << 10)) != ~(u64)0)
2305 				return -1;
2306 			if (!msr_info->host_initiated &&
2307 				(offset & 0x3) == 1 && data != 0)
2308 				return -1;
2309 			vcpu->arch.mce_banks[offset] = data;
2310 			break;
2311 		}
2312 		return 1;
2313 	}
2314 	return 0;
2315 }
2316 
2317 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2318 {
2319 	struct kvm *kvm = vcpu->kvm;
2320 	int lm = is_long_mode(vcpu);
2321 	u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2322 		: (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2323 	u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2324 		: kvm->arch.xen_hvm_config.blob_size_32;
2325 	u32 page_num = data & ~PAGE_MASK;
2326 	u64 page_addr = data & PAGE_MASK;
2327 	u8 *page;
2328 	int r;
2329 
2330 	r = -E2BIG;
2331 	if (page_num >= blob_size)
2332 		goto out;
2333 	r = -ENOMEM;
2334 	page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2335 	if (IS_ERR(page)) {
2336 		r = PTR_ERR(page);
2337 		goto out;
2338 	}
2339 	if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2340 		goto out_free;
2341 	r = 0;
2342 out_free:
2343 	kfree(page);
2344 out:
2345 	return r;
2346 }
2347 
2348 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2349 {
2350 	gpa_t gpa = data & ~0x3f;
2351 
2352 	/* Bits 3:5 are reserved, Should be zero */
2353 	if (data & 0x38)
2354 		return 1;
2355 
2356 	vcpu->arch.apf.msr_val = data;
2357 
2358 	if (!(data & KVM_ASYNC_PF_ENABLED)) {
2359 		kvm_clear_async_pf_completion_queue(vcpu);
2360 		kvm_async_pf_hash_reset(vcpu);
2361 		return 0;
2362 	}
2363 
2364 	if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2365 					sizeof(u32)))
2366 		return 1;
2367 
2368 	vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2369 	vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2370 	kvm_async_pf_wakeup_all(vcpu);
2371 	return 0;
2372 }
2373 
2374 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2375 {
2376 	vcpu->arch.pv_time_enabled = false;
2377 }
2378 
2379 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2380 {
2381 	++vcpu->stat.tlb_flush;
2382 	kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2383 }
2384 
2385 static void record_steal_time(struct kvm_vcpu *vcpu)
2386 {
2387 	if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2388 		return;
2389 
2390 	if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2391 		&vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2392 		return;
2393 
2394 	/*
2395 	 * Doing a TLB flush here, on the guest's behalf, can avoid
2396 	 * expensive IPIs.
2397 	 */
2398 	if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2399 		kvm_vcpu_flush_tlb(vcpu, false);
2400 
2401 	if (vcpu->arch.st.steal.version & 1)
2402 		vcpu->arch.st.steal.version += 1;  /* first time write, random junk */
2403 
2404 	vcpu->arch.st.steal.version += 1;
2405 
2406 	kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2407 		&vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2408 
2409 	smp_wmb();
2410 
2411 	vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2412 		vcpu->arch.st.last_steal;
2413 	vcpu->arch.st.last_steal = current->sched_info.run_delay;
2414 
2415 	kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2416 		&vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2417 
2418 	smp_wmb();
2419 
2420 	vcpu->arch.st.steal.version += 1;
2421 
2422 	kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2423 		&vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2424 }
2425 
2426 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2427 {
2428 	bool pr = false;
2429 	u32 msr = msr_info->index;
2430 	u64 data = msr_info->data;
2431 
2432 	switch (msr) {
2433 	case MSR_AMD64_NB_CFG:
2434 	case MSR_IA32_UCODE_WRITE:
2435 	case MSR_VM_HSAVE_PA:
2436 	case MSR_AMD64_PATCH_LOADER:
2437 	case MSR_AMD64_BU_CFG2:
2438 	case MSR_AMD64_DC_CFG:
2439 	case MSR_F15H_EX_CFG:
2440 		break;
2441 
2442 	case MSR_IA32_UCODE_REV:
2443 		if (msr_info->host_initiated)
2444 			vcpu->arch.microcode_version = data;
2445 		break;
2446 	case MSR_EFER:
2447 		return set_efer(vcpu, data);
2448 	case MSR_K7_HWCR:
2449 		data &= ~(u64)0x40;	/* ignore flush filter disable */
2450 		data &= ~(u64)0x100;	/* ignore ignne emulation enable */
2451 		data &= ~(u64)0x8;	/* ignore TLB cache disable */
2452 		data &= ~(u64)0x40000;  /* ignore Mc status write enable */
2453 		if (data != 0) {
2454 			vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2455 				    data);
2456 			return 1;
2457 		}
2458 		break;
2459 	case MSR_FAM10H_MMIO_CONF_BASE:
2460 		if (data != 0) {
2461 			vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2462 				    "0x%llx\n", data);
2463 			return 1;
2464 		}
2465 		break;
2466 	case MSR_IA32_DEBUGCTLMSR:
2467 		if (!data) {
2468 			/* We support the non-activated case already */
2469 			break;
2470 		} else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2471 			/* Values other than LBR and BTF are vendor-specific,
2472 			   thus reserved and should throw a #GP */
2473 			return 1;
2474 		}
2475 		vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2476 			    __func__, data);
2477 		break;
2478 	case 0x200 ... 0x2ff:
2479 		return kvm_mtrr_set_msr(vcpu, msr, data);
2480 	case MSR_IA32_APICBASE:
2481 		return kvm_set_apic_base(vcpu, msr_info);
2482 	case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2483 		return kvm_x2apic_msr_write(vcpu, msr, data);
2484 	case MSR_IA32_TSCDEADLINE:
2485 		kvm_set_lapic_tscdeadline_msr(vcpu, data);
2486 		break;
2487 	case MSR_IA32_TSC_ADJUST:
2488 		if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2489 			if (!msr_info->host_initiated) {
2490 				s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2491 				adjust_tsc_offset_guest(vcpu, adj);
2492 			}
2493 			vcpu->arch.ia32_tsc_adjust_msr = data;
2494 		}
2495 		break;
2496 	case MSR_IA32_MISC_ENABLE:
2497 		vcpu->arch.ia32_misc_enable_msr = data;
2498 		break;
2499 	case MSR_IA32_SMBASE:
2500 		if (!msr_info->host_initiated)
2501 			return 1;
2502 		vcpu->arch.smbase = data;
2503 		break;
2504 	case MSR_IA32_TSC:
2505 		kvm_write_tsc(vcpu, msr_info);
2506 		break;
2507 	case MSR_SMI_COUNT:
2508 		if (!msr_info->host_initiated)
2509 			return 1;
2510 		vcpu->arch.smi_count = data;
2511 		break;
2512 	case MSR_KVM_WALL_CLOCK_NEW:
2513 	case MSR_KVM_WALL_CLOCK:
2514 		vcpu->kvm->arch.wall_clock = data;
2515 		kvm_write_wall_clock(vcpu->kvm, data);
2516 		break;
2517 	case MSR_KVM_SYSTEM_TIME_NEW:
2518 	case MSR_KVM_SYSTEM_TIME: {
2519 		struct kvm_arch *ka = &vcpu->kvm->arch;
2520 
2521 		kvmclock_reset(vcpu);
2522 
2523 		if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2524 			bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2525 
2526 			if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2527 				kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2528 
2529 			ka->boot_vcpu_runs_old_kvmclock = tmp;
2530 		}
2531 
2532 		vcpu->arch.time = data;
2533 		kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2534 
2535 		/* we verify if the enable bit is set... */
2536 		if (!(data & 1))
2537 			break;
2538 
2539 		if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2540 		     &vcpu->arch.pv_time, data & ~1ULL,
2541 		     sizeof(struct pvclock_vcpu_time_info)))
2542 			vcpu->arch.pv_time_enabled = false;
2543 		else
2544 			vcpu->arch.pv_time_enabled = true;
2545 
2546 		break;
2547 	}
2548 	case MSR_KVM_ASYNC_PF_EN:
2549 		if (kvm_pv_enable_async_pf(vcpu, data))
2550 			return 1;
2551 		break;
2552 	case MSR_KVM_STEAL_TIME:
2553 
2554 		if (unlikely(!sched_info_on()))
2555 			return 1;
2556 
2557 		if (data & KVM_STEAL_RESERVED_MASK)
2558 			return 1;
2559 
2560 		if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2561 						data & KVM_STEAL_VALID_BITS,
2562 						sizeof(struct kvm_steal_time)))
2563 			return 1;
2564 
2565 		vcpu->arch.st.msr_val = data;
2566 
2567 		if (!(data & KVM_MSR_ENABLED))
2568 			break;
2569 
2570 		kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2571 
2572 		break;
2573 	case MSR_KVM_PV_EOI_EN:
2574 		if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2575 			return 1;
2576 		break;
2577 
2578 	case MSR_IA32_MCG_CTL:
2579 	case MSR_IA32_MCG_STATUS:
2580 	case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2581 		return set_msr_mce(vcpu, msr_info);
2582 
2583 	case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2584 	case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2585 		pr = true; /* fall through */
2586 	case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2587 	case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2588 		if (kvm_pmu_is_valid_msr(vcpu, msr))
2589 			return kvm_pmu_set_msr(vcpu, msr_info);
2590 
2591 		if (pr || data != 0)
2592 			vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2593 				    "0x%x data 0x%llx\n", msr, data);
2594 		break;
2595 	case MSR_K7_CLK_CTL:
2596 		/*
2597 		 * Ignore all writes to this no longer documented MSR.
2598 		 * Writes are only relevant for old K7 processors,
2599 		 * all pre-dating SVM, but a recommended workaround from
2600 		 * AMD for these chips. It is possible to specify the
2601 		 * affected processor models on the command line, hence
2602 		 * the need to ignore the workaround.
2603 		 */
2604 		break;
2605 	case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2606 	case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2607 	case HV_X64_MSR_CRASH_CTL:
2608 	case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2609 	case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2610 	case HV_X64_MSR_TSC_EMULATION_CONTROL:
2611 	case HV_X64_MSR_TSC_EMULATION_STATUS:
2612 		return kvm_hv_set_msr_common(vcpu, msr, data,
2613 					     msr_info->host_initiated);
2614 	case MSR_IA32_BBL_CR_CTL3:
2615 		/* Drop writes to this legacy MSR -- see rdmsr
2616 		 * counterpart for further detail.
2617 		 */
2618 		if (report_ignored_msrs)
2619 			vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2620 				msr, data);
2621 		break;
2622 	case MSR_AMD64_OSVW_ID_LENGTH:
2623 		if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2624 			return 1;
2625 		vcpu->arch.osvw.length = data;
2626 		break;
2627 	case MSR_AMD64_OSVW_STATUS:
2628 		if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2629 			return 1;
2630 		vcpu->arch.osvw.status = data;
2631 		break;
2632 	case MSR_PLATFORM_INFO:
2633 		if (!msr_info->host_initiated ||
2634 		    (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2635 		     cpuid_fault_enabled(vcpu)))
2636 			return 1;
2637 		vcpu->arch.msr_platform_info = data;
2638 		break;
2639 	case MSR_MISC_FEATURES_ENABLES:
2640 		if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2641 		    (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2642 		     !supports_cpuid_fault(vcpu)))
2643 			return 1;
2644 		vcpu->arch.msr_misc_features_enables = data;
2645 		break;
2646 	default:
2647 		if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2648 			return xen_hvm_config(vcpu, data);
2649 		if (kvm_pmu_is_valid_msr(vcpu, msr))
2650 			return kvm_pmu_set_msr(vcpu, msr_info);
2651 		if (!ignore_msrs) {
2652 			vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2653 				    msr, data);
2654 			return 1;
2655 		} else {
2656 			if (report_ignored_msrs)
2657 				vcpu_unimpl(vcpu,
2658 					"ignored wrmsr: 0x%x data 0x%llx\n",
2659 					msr, data);
2660 			break;
2661 		}
2662 	}
2663 	return 0;
2664 }
2665 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2666 
2667 
2668 /*
2669  * Reads an msr value (of 'msr_index') into 'pdata'.
2670  * Returns 0 on success, non-0 otherwise.
2671  * Assumes vcpu_load() was already called.
2672  */
2673 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2674 {
2675 	return kvm_x86_ops->get_msr(vcpu, msr);
2676 }
2677 EXPORT_SYMBOL_GPL(kvm_get_msr);
2678 
2679 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2680 {
2681 	u64 data;
2682 	u64 mcg_cap = vcpu->arch.mcg_cap;
2683 	unsigned bank_num = mcg_cap & 0xff;
2684 
2685 	switch (msr) {
2686 	case MSR_IA32_P5_MC_ADDR:
2687 	case MSR_IA32_P5_MC_TYPE:
2688 		data = 0;
2689 		break;
2690 	case MSR_IA32_MCG_CAP:
2691 		data = vcpu->arch.mcg_cap;
2692 		break;
2693 	case MSR_IA32_MCG_CTL:
2694 		if (!(mcg_cap & MCG_CTL_P) && !host)
2695 			return 1;
2696 		data = vcpu->arch.mcg_ctl;
2697 		break;
2698 	case MSR_IA32_MCG_STATUS:
2699 		data = vcpu->arch.mcg_status;
2700 		break;
2701 	default:
2702 		if (msr >= MSR_IA32_MC0_CTL &&
2703 		    msr < MSR_IA32_MCx_CTL(bank_num)) {
2704 			u32 offset = msr - MSR_IA32_MC0_CTL;
2705 			data = vcpu->arch.mce_banks[offset];
2706 			break;
2707 		}
2708 		return 1;
2709 	}
2710 	*pdata = data;
2711 	return 0;
2712 }
2713 
2714 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2715 {
2716 	switch (msr_info->index) {
2717 	case MSR_IA32_PLATFORM_ID:
2718 	case MSR_IA32_EBL_CR_POWERON:
2719 	case MSR_IA32_DEBUGCTLMSR:
2720 	case MSR_IA32_LASTBRANCHFROMIP:
2721 	case MSR_IA32_LASTBRANCHTOIP:
2722 	case MSR_IA32_LASTINTFROMIP:
2723 	case MSR_IA32_LASTINTTOIP:
2724 	case MSR_K8_SYSCFG:
2725 	case MSR_K8_TSEG_ADDR:
2726 	case MSR_K8_TSEG_MASK:
2727 	case MSR_K7_HWCR:
2728 	case MSR_VM_HSAVE_PA:
2729 	case MSR_K8_INT_PENDING_MSG:
2730 	case MSR_AMD64_NB_CFG:
2731 	case MSR_FAM10H_MMIO_CONF_BASE:
2732 	case MSR_AMD64_BU_CFG2:
2733 	case MSR_IA32_PERF_CTL:
2734 	case MSR_AMD64_DC_CFG:
2735 	case MSR_F15H_EX_CFG:
2736 		msr_info->data = 0;
2737 		break;
2738 	case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
2739 	case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2740 	case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2741 	case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2742 	case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2743 		if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2744 			return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2745 		msr_info->data = 0;
2746 		break;
2747 	case MSR_IA32_UCODE_REV:
2748 		msr_info->data = vcpu->arch.microcode_version;
2749 		break;
2750 	case MSR_IA32_TSC:
2751 		msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2752 		break;
2753 	case MSR_MTRRcap:
2754 	case 0x200 ... 0x2ff:
2755 		return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2756 	case 0xcd: /* fsb frequency */
2757 		msr_info->data = 3;
2758 		break;
2759 		/*
2760 		 * MSR_EBC_FREQUENCY_ID
2761 		 * Conservative value valid for even the basic CPU models.
2762 		 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2763 		 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2764 		 * and 266MHz for model 3, or 4. Set Core Clock
2765 		 * Frequency to System Bus Frequency Ratio to 1 (bits
2766 		 * 31:24) even though these are only valid for CPU
2767 		 * models > 2, however guests may end up dividing or
2768 		 * multiplying by zero otherwise.
2769 		 */
2770 	case MSR_EBC_FREQUENCY_ID:
2771 		msr_info->data = 1 << 24;
2772 		break;
2773 	case MSR_IA32_APICBASE:
2774 		msr_info->data = kvm_get_apic_base(vcpu);
2775 		break;
2776 	case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2777 		return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2778 		break;
2779 	case MSR_IA32_TSCDEADLINE:
2780 		msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2781 		break;
2782 	case MSR_IA32_TSC_ADJUST:
2783 		msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2784 		break;
2785 	case MSR_IA32_MISC_ENABLE:
2786 		msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2787 		break;
2788 	case MSR_IA32_SMBASE:
2789 		if (!msr_info->host_initiated)
2790 			return 1;
2791 		msr_info->data = vcpu->arch.smbase;
2792 		break;
2793 	case MSR_SMI_COUNT:
2794 		msr_info->data = vcpu->arch.smi_count;
2795 		break;
2796 	case MSR_IA32_PERF_STATUS:
2797 		/* TSC increment by tick */
2798 		msr_info->data = 1000ULL;
2799 		/* CPU multiplier */
2800 		msr_info->data |= (((uint64_t)4ULL) << 40);
2801 		break;
2802 	case MSR_EFER:
2803 		msr_info->data = vcpu->arch.efer;
2804 		break;
2805 	case MSR_KVM_WALL_CLOCK:
2806 	case MSR_KVM_WALL_CLOCK_NEW:
2807 		msr_info->data = vcpu->kvm->arch.wall_clock;
2808 		break;
2809 	case MSR_KVM_SYSTEM_TIME:
2810 	case MSR_KVM_SYSTEM_TIME_NEW:
2811 		msr_info->data = vcpu->arch.time;
2812 		break;
2813 	case MSR_KVM_ASYNC_PF_EN:
2814 		msr_info->data = vcpu->arch.apf.msr_val;
2815 		break;
2816 	case MSR_KVM_STEAL_TIME:
2817 		msr_info->data = vcpu->arch.st.msr_val;
2818 		break;
2819 	case MSR_KVM_PV_EOI_EN:
2820 		msr_info->data = vcpu->arch.pv_eoi.msr_val;
2821 		break;
2822 	case MSR_IA32_P5_MC_ADDR:
2823 	case MSR_IA32_P5_MC_TYPE:
2824 	case MSR_IA32_MCG_CAP:
2825 	case MSR_IA32_MCG_CTL:
2826 	case MSR_IA32_MCG_STATUS:
2827 	case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2828 		return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2829 				   msr_info->host_initiated);
2830 	case MSR_K7_CLK_CTL:
2831 		/*
2832 		 * Provide expected ramp-up count for K7. All other
2833 		 * are set to zero, indicating minimum divisors for
2834 		 * every field.
2835 		 *
2836 		 * This prevents guest kernels on AMD host with CPU
2837 		 * type 6, model 8 and higher from exploding due to
2838 		 * the rdmsr failing.
2839 		 */
2840 		msr_info->data = 0x20000000;
2841 		break;
2842 	case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2843 	case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2844 	case HV_X64_MSR_CRASH_CTL:
2845 	case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2846 	case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2847 	case HV_X64_MSR_TSC_EMULATION_CONTROL:
2848 	case HV_X64_MSR_TSC_EMULATION_STATUS:
2849 		return kvm_hv_get_msr_common(vcpu,
2850 					     msr_info->index, &msr_info->data,
2851 					     msr_info->host_initiated);
2852 		break;
2853 	case MSR_IA32_BBL_CR_CTL3:
2854 		/* This legacy MSR exists but isn't fully documented in current
2855 		 * silicon.  It is however accessed by winxp in very narrow
2856 		 * scenarios where it sets bit #19, itself documented as
2857 		 * a "reserved" bit.  Best effort attempt to source coherent
2858 		 * read data here should the balance of the register be
2859 		 * interpreted by the guest:
2860 		 *
2861 		 * L2 cache control register 3: 64GB range, 256KB size,
2862 		 * enabled, latency 0x1, configured
2863 		 */
2864 		msr_info->data = 0xbe702111;
2865 		break;
2866 	case MSR_AMD64_OSVW_ID_LENGTH:
2867 		if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2868 			return 1;
2869 		msr_info->data = vcpu->arch.osvw.length;
2870 		break;
2871 	case MSR_AMD64_OSVW_STATUS:
2872 		if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2873 			return 1;
2874 		msr_info->data = vcpu->arch.osvw.status;
2875 		break;
2876 	case MSR_PLATFORM_INFO:
2877 		if (!msr_info->host_initiated &&
2878 		    !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2879 			return 1;
2880 		msr_info->data = vcpu->arch.msr_platform_info;
2881 		break;
2882 	case MSR_MISC_FEATURES_ENABLES:
2883 		msr_info->data = vcpu->arch.msr_misc_features_enables;
2884 		break;
2885 	default:
2886 		if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2887 			return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2888 		if (!ignore_msrs) {
2889 			vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2890 					       msr_info->index);
2891 			return 1;
2892 		} else {
2893 			if (report_ignored_msrs)
2894 				vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2895 					msr_info->index);
2896 			msr_info->data = 0;
2897 		}
2898 		break;
2899 	}
2900 	return 0;
2901 }
2902 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2903 
2904 /*
2905  * Read or write a bunch of msrs. All parameters are kernel addresses.
2906  *
2907  * @return number of msrs set successfully.
2908  */
2909 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2910 		    struct kvm_msr_entry *entries,
2911 		    int (*do_msr)(struct kvm_vcpu *vcpu,
2912 				  unsigned index, u64 *data))
2913 {
2914 	int i;
2915 
2916 	for (i = 0; i < msrs->nmsrs; ++i)
2917 		if (do_msr(vcpu, entries[i].index, &entries[i].data))
2918 			break;
2919 
2920 	return i;
2921 }
2922 
2923 /*
2924  * Read or write a bunch of msrs. Parameters are user addresses.
2925  *
2926  * @return number of msrs set successfully.
2927  */
2928 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2929 		  int (*do_msr)(struct kvm_vcpu *vcpu,
2930 				unsigned index, u64 *data),
2931 		  int writeback)
2932 {
2933 	struct kvm_msrs msrs;
2934 	struct kvm_msr_entry *entries;
2935 	int r, n;
2936 	unsigned size;
2937 
2938 	r = -EFAULT;
2939 	if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
2940 		goto out;
2941 
2942 	r = -E2BIG;
2943 	if (msrs.nmsrs >= MAX_IO_MSRS)
2944 		goto out;
2945 
2946 	size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2947 	entries = memdup_user(user_msrs->entries, size);
2948 	if (IS_ERR(entries)) {
2949 		r = PTR_ERR(entries);
2950 		goto out;
2951 	}
2952 
2953 	r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2954 	if (r < 0)
2955 		goto out_free;
2956 
2957 	r = -EFAULT;
2958 	if (writeback && copy_to_user(user_msrs->entries, entries, size))
2959 		goto out_free;
2960 
2961 	r = n;
2962 
2963 out_free:
2964 	kfree(entries);
2965 out:
2966 	return r;
2967 }
2968 
2969 static inline bool kvm_can_mwait_in_guest(void)
2970 {
2971 	return boot_cpu_has(X86_FEATURE_MWAIT) &&
2972 		!boot_cpu_has_bug(X86_BUG_MONITOR) &&
2973 		boot_cpu_has(X86_FEATURE_ARAT);
2974 }
2975 
2976 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2977 {
2978 	int r = 0;
2979 
2980 	switch (ext) {
2981 	case KVM_CAP_IRQCHIP:
2982 	case KVM_CAP_HLT:
2983 	case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2984 	case KVM_CAP_SET_TSS_ADDR:
2985 	case KVM_CAP_EXT_CPUID:
2986 	case KVM_CAP_EXT_EMUL_CPUID:
2987 	case KVM_CAP_CLOCKSOURCE:
2988 	case KVM_CAP_PIT:
2989 	case KVM_CAP_NOP_IO_DELAY:
2990 	case KVM_CAP_MP_STATE:
2991 	case KVM_CAP_SYNC_MMU:
2992 	case KVM_CAP_USER_NMI:
2993 	case KVM_CAP_REINJECT_CONTROL:
2994 	case KVM_CAP_IRQ_INJECT_STATUS:
2995 	case KVM_CAP_IOEVENTFD:
2996 	case KVM_CAP_IOEVENTFD_NO_LENGTH:
2997 	case KVM_CAP_PIT2:
2998 	case KVM_CAP_PIT_STATE2:
2999 	case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3000 	case KVM_CAP_XEN_HVM:
3001 	case KVM_CAP_VCPU_EVENTS:
3002 	case KVM_CAP_HYPERV:
3003 	case KVM_CAP_HYPERV_VAPIC:
3004 	case KVM_CAP_HYPERV_SPIN:
3005 	case KVM_CAP_HYPERV_SYNIC:
3006 	case KVM_CAP_HYPERV_SYNIC2:
3007 	case KVM_CAP_HYPERV_VP_INDEX:
3008 	case KVM_CAP_HYPERV_EVENTFD:
3009 	case KVM_CAP_HYPERV_TLBFLUSH:
3010 	case KVM_CAP_HYPERV_SEND_IPI:
3011 	case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3012 	case KVM_CAP_HYPERV_CPUID:
3013 	case KVM_CAP_PCI_SEGMENT:
3014 	case KVM_CAP_DEBUGREGS:
3015 	case KVM_CAP_X86_ROBUST_SINGLESTEP:
3016 	case KVM_CAP_XSAVE:
3017 	case KVM_CAP_ASYNC_PF:
3018 	case KVM_CAP_GET_TSC_KHZ:
3019 	case KVM_CAP_KVMCLOCK_CTRL:
3020 	case KVM_CAP_READONLY_MEM:
3021 	case KVM_CAP_HYPERV_TIME:
3022 	case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3023 	case KVM_CAP_TSC_DEADLINE_TIMER:
3024 	case KVM_CAP_DISABLE_QUIRKS:
3025 	case KVM_CAP_SET_BOOT_CPU_ID:
3026  	case KVM_CAP_SPLIT_IRQCHIP:
3027 	case KVM_CAP_IMMEDIATE_EXIT:
3028 	case KVM_CAP_GET_MSR_FEATURES:
3029 	case KVM_CAP_MSR_PLATFORM_INFO:
3030 	case KVM_CAP_EXCEPTION_PAYLOAD:
3031 		r = 1;
3032 		break;
3033 	case KVM_CAP_SYNC_REGS:
3034 		r = KVM_SYNC_X86_VALID_FIELDS;
3035 		break;
3036 	case KVM_CAP_ADJUST_CLOCK:
3037 		r = KVM_CLOCK_TSC_STABLE;
3038 		break;
3039 	case KVM_CAP_X86_DISABLE_EXITS:
3040 		r |=  KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
3041 		if(kvm_can_mwait_in_guest())
3042 			r |= KVM_X86_DISABLE_EXITS_MWAIT;
3043 		break;
3044 	case KVM_CAP_X86_SMM:
3045 		/* SMBASE is usually relocated above 1M on modern chipsets,
3046 		 * and SMM handlers might indeed rely on 4G segment limits,
3047 		 * so do not report SMM to be available if real mode is
3048 		 * emulated via vm86 mode.  Still, do not go to great lengths
3049 		 * to avoid userspace's usage of the feature, because it is a
3050 		 * fringe case that is not enabled except via specific settings
3051 		 * of the module parameters.
3052 		 */
3053 		r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3054 		break;
3055 	case KVM_CAP_VAPIC:
3056 		r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3057 		break;
3058 	case KVM_CAP_NR_VCPUS:
3059 		r = KVM_SOFT_MAX_VCPUS;
3060 		break;
3061 	case KVM_CAP_MAX_VCPUS:
3062 		r = KVM_MAX_VCPUS;
3063 		break;
3064 	case KVM_CAP_NR_MEMSLOTS:
3065 		r = KVM_USER_MEM_SLOTS;
3066 		break;
3067 	case KVM_CAP_PV_MMU:	/* obsolete */
3068 		r = 0;
3069 		break;
3070 	case KVM_CAP_MCE:
3071 		r = KVM_MAX_MCE_BANKS;
3072 		break;
3073 	case KVM_CAP_XCRS:
3074 		r = boot_cpu_has(X86_FEATURE_XSAVE);
3075 		break;
3076 	case KVM_CAP_TSC_CONTROL:
3077 		r = kvm_has_tsc_control;
3078 		break;
3079 	case KVM_CAP_X2APIC_API:
3080 		r = KVM_X2APIC_API_VALID_FLAGS;
3081 		break;
3082 	case KVM_CAP_NESTED_STATE:
3083 		r = kvm_x86_ops->get_nested_state ?
3084 			kvm_x86_ops->get_nested_state(NULL, 0, 0) : 0;
3085 		break;
3086 	default:
3087 		break;
3088 	}
3089 	return r;
3090 
3091 }
3092 
3093 long kvm_arch_dev_ioctl(struct file *filp,
3094 			unsigned int ioctl, unsigned long arg)
3095 {
3096 	void __user *argp = (void __user *)arg;
3097 	long r;
3098 
3099 	switch (ioctl) {
3100 	case KVM_GET_MSR_INDEX_LIST: {
3101 		struct kvm_msr_list __user *user_msr_list = argp;
3102 		struct kvm_msr_list msr_list;
3103 		unsigned n;
3104 
3105 		r = -EFAULT;
3106 		if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3107 			goto out;
3108 		n = msr_list.nmsrs;
3109 		msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3110 		if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3111 			goto out;
3112 		r = -E2BIG;
3113 		if (n < msr_list.nmsrs)
3114 			goto out;
3115 		r = -EFAULT;
3116 		if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3117 				 num_msrs_to_save * sizeof(u32)))
3118 			goto out;
3119 		if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3120 				 &emulated_msrs,
3121 				 num_emulated_msrs * sizeof(u32)))
3122 			goto out;
3123 		r = 0;
3124 		break;
3125 	}
3126 	case KVM_GET_SUPPORTED_CPUID:
3127 	case KVM_GET_EMULATED_CPUID: {
3128 		struct kvm_cpuid2 __user *cpuid_arg = argp;
3129 		struct kvm_cpuid2 cpuid;
3130 
3131 		r = -EFAULT;
3132 		if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3133 			goto out;
3134 
3135 		r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3136 					    ioctl);
3137 		if (r)
3138 			goto out;
3139 
3140 		r = -EFAULT;
3141 		if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3142 			goto out;
3143 		r = 0;
3144 		break;
3145 	}
3146 	case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3147 		r = -EFAULT;
3148 		if (copy_to_user(argp, &kvm_mce_cap_supported,
3149 				 sizeof(kvm_mce_cap_supported)))
3150 			goto out;
3151 		r = 0;
3152 		break;
3153 	case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3154 		struct kvm_msr_list __user *user_msr_list = argp;
3155 		struct kvm_msr_list msr_list;
3156 		unsigned int n;
3157 
3158 		r = -EFAULT;
3159 		if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3160 			goto out;
3161 		n = msr_list.nmsrs;
3162 		msr_list.nmsrs = num_msr_based_features;
3163 		if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3164 			goto out;
3165 		r = -E2BIG;
3166 		if (n < msr_list.nmsrs)
3167 			goto out;
3168 		r = -EFAULT;
3169 		if (copy_to_user(user_msr_list->indices, &msr_based_features,
3170 				 num_msr_based_features * sizeof(u32)))
3171 			goto out;
3172 		r = 0;
3173 		break;
3174 	}
3175 	case KVM_GET_MSRS:
3176 		r = msr_io(NULL, argp, do_get_msr_feature, 1);
3177 		break;
3178 	}
3179 	default:
3180 		r = -EINVAL;
3181 	}
3182 out:
3183 	return r;
3184 }
3185 
3186 static void wbinvd_ipi(void *garbage)
3187 {
3188 	wbinvd();
3189 }
3190 
3191 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3192 {
3193 	return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3194 }
3195 
3196 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3197 {
3198 	/* Address WBINVD may be executed by guest */
3199 	if (need_emulate_wbinvd(vcpu)) {
3200 		if (kvm_x86_ops->has_wbinvd_exit())
3201 			cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3202 		else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3203 			smp_call_function_single(vcpu->cpu,
3204 					wbinvd_ipi, NULL, 1);
3205 	}
3206 
3207 	kvm_x86_ops->vcpu_load(vcpu, cpu);
3208 
3209 	/* Apply any externally detected TSC adjustments (due to suspend) */
3210 	if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3211 		adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3212 		vcpu->arch.tsc_offset_adjustment = 0;
3213 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3214 	}
3215 
3216 	if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3217 		s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3218 				rdtsc() - vcpu->arch.last_host_tsc;
3219 		if (tsc_delta < 0)
3220 			mark_tsc_unstable("KVM discovered backwards TSC");
3221 
3222 		if (kvm_check_tsc_unstable()) {
3223 			u64 offset = kvm_compute_tsc_offset(vcpu,
3224 						vcpu->arch.last_guest_tsc);
3225 			kvm_vcpu_write_tsc_offset(vcpu, offset);
3226 			vcpu->arch.tsc_catchup = 1;
3227 		}
3228 
3229 		if (kvm_lapic_hv_timer_in_use(vcpu))
3230 			kvm_lapic_restart_hv_timer(vcpu);
3231 
3232 		/*
3233 		 * On a host with synchronized TSC, there is no need to update
3234 		 * kvmclock on vcpu->cpu migration
3235 		 */
3236 		if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3237 			kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3238 		if (vcpu->cpu != cpu)
3239 			kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3240 		vcpu->cpu = cpu;
3241 	}
3242 
3243 	kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3244 }
3245 
3246 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3247 {
3248 	if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3249 		return;
3250 
3251 	vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
3252 
3253 	kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3254 			&vcpu->arch.st.steal.preempted,
3255 			offsetof(struct kvm_steal_time, preempted),
3256 			sizeof(vcpu->arch.st.steal.preempted));
3257 }
3258 
3259 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3260 {
3261 	int idx;
3262 
3263 	if (vcpu->preempted)
3264 		vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3265 
3266 	/*
3267 	 * Disable page faults because we're in atomic context here.
3268 	 * kvm_write_guest_offset_cached() would call might_fault()
3269 	 * that relies on pagefault_disable() to tell if there's a
3270 	 * bug. NOTE: the write to guest memory may not go through if
3271 	 * during postcopy live migration or if there's heavy guest
3272 	 * paging.
3273 	 */
3274 	pagefault_disable();
3275 	/*
3276 	 * kvm_memslots() will be called by
3277 	 * kvm_write_guest_offset_cached() so take the srcu lock.
3278 	 */
3279 	idx = srcu_read_lock(&vcpu->kvm->srcu);
3280 	kvm_steal_time_set_preempted(vcpu);
3281 	srcu_read_unlock(&vcpu->kvm->srcu, idx);
3282 	pagefault_enable();
3283 	kvm_x86_ops->vcpu_put(vcpu);
3284 	vcpu->arch.last_host_tsc = rdtsc();
3285 	/*
3286 	 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3287 	 * on every vmexit, but if not, we might have a stale dr6 from the
3288 	 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3289 	 */
3290 	set_debugreg(0, 6);
3291 }
3292 
3293 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3294 				    struct kvm_lapic_state *s)
3295 {
3296 	if (vcpu->arch.apicv_active)
3297 		kvm_x86_ops->sync_pir_to_irr(vcpu);
3298 
3299 	return kvm_apic_get_state(vcpu, s);
3300 }
3301 
3302 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3303 				    struct kvm_lapic_state *s)
3304 {
3305 	int r;
3306 
3307 	r = kvm_apic_set_state(vcpu, s);
3308 	if (r)
3309 		return r;
3310 	update_cr8_intercept(vcpu);
3311 
3312 	return 0;
3313 }
3314 
3315 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3316 {
3317 	return (!lapic_in_kernel(vcpu) ||
3318 		kvm_apic_accept_pic_intr(vcpu));
3319 }
3320 
3321 /*
3322  * if userspace requested an interrupt window, check that the
3323  * interrupt window is open.
3324  *
3325  * No need to exit to userspace if we already have an interrupt queued.
3326  */
3327 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3328 {
3329 	return kvm_arch_interrupt_allowed(vcpu) &&
3330 		!kvm_cpu_has_interrupt(vcpu) &&
3331 		!kvm_event_needs_reinjection(vcpu) &&
3332 		kvm_cpu_accept_dm_intr(vcpu);
3333 }
3334 
3335 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3336 				    struct kvm_interrupt *irq)
3337 {
3338 	if (irq->irq >= KVM_NR_INTERRUPTS)
3339 		return -EINVAL;
3340 
3341 	if (!irqchip_in_kernel(vcpu->kvm)) {
3342 		kvm_queue_interrupt(vcpu, irq->irq, false);
3343 		kvm_make_request(KVM_REQ_EVENT, vcpu);
3344 		return 0;
3345 	}
3346 
3347 	/*
3348 	 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3349 	 * fail for in-kernel 8259.
3350 	 */
3351 	if (pic_in_kernel(vcpu->kvm))
3352 		return -ENXIO;
3353 
3354 	if (vcpu->arch.pending_external_vector != -1)
3355 		return -EEXIST;
3356 
3357 	vcpu->arch.pending_external_vector = irq->irq;
3358 	kvm_make_request(KVM_REQ_EVENT, vcpu);
3359 	return 0;
3360 }
3361 
3362 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3363 {
3364 	kvm_inject_nmi(vcpu);
3365 
3366 	return 0;
3367 }
3368 
3369 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3370 {
3371 	kvm_make_request(KVM_REQ_SMI, vcpu);
3372 
3373 	return 0;
3374 }
3375 
3376 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3377 					   struct kvm_tpr_access_ctl *tac)
3378 {
3379 	if (tac->flags)
3380 		return -EINVAL;
3381 	vcpu->arch.tpr_access_reporting = !!tac->enabled;
3382 	return 0;
3383 }
3384 
3385 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3386 					u64 mcg_cap)
3387 {
3388 	int r;
3389 	unsigned bank_num = mcg_cap & 0xff, bank;
3390 
3391 	r = -EINVAL;
3392 	if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3393 		goto out;
3394 	if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3395 		goto out;
3396 	r = 0;
3397 	vcpu->arch.mcg_cap = mcg_cap;
3398 	/* Init IA32_MCG_CTL to all 1s */
3399 	if (mcg_cap & MCG_CTL_P)
3400 		vcpu->arch.mcg_ctl = ~(u64)0;
3401 	/* Init IA32_MCi_CTL to all 1s */
3402 	for (bank = 0; bank < bank_num; bank++)
3403 		vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3404 
3405 	if (kvm_x86_ops->setup_mce)
3406 		kvm_x86_ops->setup_mce(vcpu);
3407 out:
3408 	return r;
3409 }
3410 
3411 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3412 				      struct kvm_x86_mce *mce)
3413 {
3414 	u64 mcg_cap = vcpu->arch.mcg_cap;
3415 	unsigned bank_num = mcg_cap & 0xff;
3416 	u64 *banks = vcpu->arch.mce_banks;
3417 
3418 	if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3419 		return -EINVAL;
3420 	/*
3421 	 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3422 	 * reporting is disabled
3423 	 */
3424 	if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3425 	    vcpu->arch.mcg_ctl != ~(u64)0)
3426 		return 0;
3427 	banks += 4 * mce->bank;
3428 	/*
3429 	 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3430 	 * reporting is disabled for the bank
3431 	 */
3432 	if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3433 		return 0;
3434 	if (mce->status & MCI_STATUS_UC) {
3435 		if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3436 		    !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3437 			kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3438 			return 0;
3439 		}
3440 		if (banks[1] & MCI_STATUS_VAL)
3441 			mce->status |= MCI_STATUS_OVER;
3442 		banks[2] = mce->addr;
3443 		banks[3] = mce->misc;
3444 		vcpu->arch.mcg_status = mce->mcg_status;
3445 		banks[1] = mce->status;
3446 		kvm_queue_exception(vcpu, MC_VECTOR);
3447 	} else if (!(banks[1] & MCI_STATUS_VAL)
3448 		   || !(banks[1] & MCI_STATUS_UC)) {
3449 		if (banks[1] & MCI_STATUS_VAL)
3450 			mce->status |= MCI_STATUS_OVER;
3451 		banks[2] = mce->addr;
3452 		banks[3] = mce->misc;
3453 		banks[1] = mce->status;
3454 	} else
3455 		banks[1] |= MCI_STATUS_OVER;
3456 	return 0;
3457 }
3458 
3459 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3460 					       struct kvm_vcpu_events *events)
3461 {
3462 	process_nmi(vcpu);
3463 
3464 	/*
3465 	 * The API doesn't provide the instruction length for software
3466 	 * exceptions, so don't report them. As long as the guest RIP
3467 	 * isn't advanced, we should expect to encounter the exception
3468 	 * again.
3469 	 */
3470 	if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3471 		events->exception.injected = 0;
3472 		events->exception.pending = 0;
3473 	} else {
3474 		events->exception.injected = vcpu->arch.exception.injected;
3475 		events->exception.pending = vcpu->arch.exception.pending;
3476 		/*
3477 		 * For ABI compatibility, deliberately conflate
3478 		 * pending and injected exceptions when
3479 		 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3480 		 */
3481 		if (!vcpu->kvm->arch.exception_payload_enabled)
3482 			events->exception.injected |=
3483 				vcpu->arch.exception.pending;
3484 	}
3485 	events->exception.nr = vcpu->arch.exception.nr;
3486 	events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3487 	events->exception.error_code = vcpu->arch.exception.error_code;
3488 	events->exception_has_payload = vcpu->arch.exception.has_payload;
3489 	events->exception_payload = vcpu->arch.exception.payload;
3490 
3491 	events->interrupt.injected =
3492 		vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3493 	events->interrupt.nr = vcpu->arch.interrupt.nr;
3494 	events->interrupt.soft = 0;
3495 	events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3496 
3497 	events->nmi.injected = vcpu->arch.nmi_injected;
3498 	events->nmi.pending = vcpu->arch.nmi_pending != 0;
3499 	events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3500 	events->nmi.pad = 0;
3501 
3502 	events->sipi_vector = 0; /* never valid when reporting to user space */
3503 
3504 	events->smi.smm = is_smm(vcpu);
3505 	events->smi.pending = vcpu->arch.smi_pending;
3506 	events->smi.smm_inside_nmi =
3507 		!!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3508 	events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3509 
3510 	events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3511 			 | KVM_VCPUEVENT_VALID_SHADOW
3512 			 | KVM_VCPUEVENT_VALID_SMM);
3513 	if (vcpu->kvm->arch.exception_payload_enabled)
3514 		events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3515 
3516 	memset(&events->reserved, 0, sizeof(events->reserved));
3517 }
3518 
3519 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3520 
3521 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3522 					      struct kvm_vcpu_events *events)
3523 {
3524 	if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3525 			      | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3526 			      | KVM_VCPUEVENT_VALID_SHADOW
3527 			      | KVM_VCPUEVENT_VALID_SMM
3528 			      | KVM_VCPUEVENT_VALID_PAYLOAD))
3529 		return -EINVAL;
3530 
3531 	if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3532 		if (!vcpu->kvm->arch.exception_payload_enabled)
3533 			return -EINVAL;
3534 		if (events->exception.pending)
3535 			events->exception.injected = 0;
3536 		else
3537 			events->exception_has_payload = 0;
3538 	} else {
3539 		events->exception.pending = 0;
3540 		events->exception_has_payload = 0;
3541 	}
3542 
3543 	if ((events->exception.injected || events->exception.pending) &&
3544 	    (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3545 		return -EINVAL;
3546 
3547 	/* INITs are latched while in SMM */
3548 	if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3549 	    (events->smi.smm || events->smi.pending) &&
3550 	    vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3551 		return -EINVAL;
3552 
3553 	process_nmi(vcpu);
3554 	vcpu->arch.exception.injected = events->exception.injected;
3555 	vcpu->arch.exception.pending = events->exception.pending;
3556 	vcpu->arch.exception.nr = events->exception.nr;
3557 	vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3558 	vcpu->arch.exception.error_code = events->exception.error_code;
3559 	vcpu->arch.exception.has_payload = events->exception_has_payload;
3560 	vcpu->arch.exception.payload = events->exception_payload;
3561 
3562 	vcpu->arch.interrupt.injected = events->interrupt.injected;
3563 	vcpu->arch.interrupt.nr = events->interrupt.nr;
3564 	vcpu->arch.interrupt.soft = events->interrupt.soft;
3565 	if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3566 		kvm_x86_ops->set_interrupt_shadow(vcpu,
3567 						  events->interrupt.shadow);
3568 
3569 	vcpu->arch.nmi_injected = events->nmi.injected;
3570 	if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3571 		vcpu->arch.nmi_pending = events->nmi.pending;
3572 	kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3573 
3574 	if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3575 	    lapic_in_kernel(vcpu))
3576 		vcpu->arch.apic->sipi_vector = events->sipi_vector;
3577 
3578 	if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3579 		u32 hflags = vcpu->arch.hflags;
3580 		if (events->smi.smm)
3581 			hflags |= HF_SMM_MASK;
3582 		else
3583 			hflags &= ~HF_SMM_MASK;
3584 		kvm_set_hflags(vcpu, hflags);
3585 
3586 		vcpu->arch.smi_pending = events->smi.pending;
3587 
3588 		if (events->smi.smm) {
3589 			if (events->smi.smm_inside_nmi)
3590 				vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3591 			else
3592 				vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3593 			if (lapic_in_kernel(vcpu)) {
3594 				if (events->smi.latched_init)
3595 					set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3596 				else
3597 					clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3598 			}
3599 		}
3600 	}
3601 
3602 	kvm_make_request(KVM_REQ_EVENT, vcpu);
3603 
3604 	return 0;
3605 }
3606 
3607 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3608 					     struct kvm_debugregs *dbgregs)
3609 {
3610 	unsigned long val;
3611 
3612 	memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3613 	kvm_get_dr(vcpu, 6, &val);
3614 	dbgregs->dr6 = val;
3615 	dbgregs->dr7 = vcpu->arch.dr7;
3616 	dbgregs->flags = 0;
3617 	memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3618 }
3619 
3620 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3621 					    struct kvm_debugregs *dbgregs)
3622 {
3623 	if (dbgregs->flags)
3624 		return -EINVAL;
3625 
3626 	if (dbgregs->dr6 & ~0xffffffffull)
3627 		return -EINVAL;
3628 	if (dbgregs->dr7 & ~0xffffffffull)
3629 		return -EINVAL;
3630 
3631 	memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3632 	kvm_update_dr0123(vcpu);
3633 	vcpu->arch.dr6 = dbgregs->dr6;
3634 	kvm_update_dr6(vcpu);
3635 	vcpu->arch.dr7 = dbgregs->dr7;
3636 	kvm_update_dr7(vcpu);
3637 
3638 	return 0;
3639 }
3640 
3641 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3642 
3643 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3644 {
3645 	struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3646 	u64 xstate_bv = xsave->header.xfeatures;
3647 	u64 valid;
3648 
3649 	/*
3650 	 * Copy legacy XSAVE area, to avoid complications with CPUID
3651 	 * leaves 0 and 1 in the loop below.
3652 	 */
3653 	memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3654 
3655 	/* Set XSTATE_BV */
3656 	xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3657 	*(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3658 
3659 	/*
3660 	 * Copy each region from the possibly compacted offset to the
3661 	 * non-compacted offset.
3662 	 */
3663 	valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3664 	while (valid) {
3665 		u64 feature = valid & -valid;
3666 		int index = fls64(feature) - 1;
3667 		void *src = get_xsave_addr(xsave, feature);
3668 
3669 		if (src) {
3670 			u32 size, offset, ecx, edx;
3671 			cpuid_count(XSTATE_CPUID, index,
3672 				    &size, &offset, &ecx, &edx);
3673 			if (feature == XFEATURE_MASK_PKRU)
3674 				memcpy(dest + offset, &vcpu->arch.pkru,
3675 				       sizeof(vcpu->arch.pkru));
3676 			else
3677 				memcpy(dest + offset, src, size);
3678 
3679 		}
3680 
3681 		valid -= feature;
3682 	}
3683 }
3684 
3685 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3686 {
3687 	struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3688 	u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3689 	u64 valid;
3690 
3691 	/*
3692 	 * Copy legacy XSAVE area, to avoid complications with CPUID
3693 	 * leaves 0 and 1 in the loop below.
3694 	 */
3695 	memcpy(xsave, src, XSAVE_HDR_OFFSET);
3696 
3697 	/* Set XSTATE_BV and possibly XCOMP_BV.  */
3698 	xsave->header.xfeatures = xstate_bv;
3699 	if (boot_cpu_has(X86_FEATURE_XSAVES))
3700 		xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3701 
3702 	/*
3703 	 * Copy each region from the non-compacted offset to the
3704 	 * possibly compacted offset.
3705 	 */
3706 	valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3707 	while (valid) {
3708 		u64 feature = valid & -valid;
3709 		int index = fls64(feature) - 1;
3710 		void *dest = get_xsave_addr(xsave, feature);
3711 
3712 		if (dest) {
3713 			u32 size, offset, ecx, edx;
3714 			cpuid_count(XSTATE_CPUID, index,
3715 				    &size, &offset, &ecx, &edx);
3716 			if (feature == XFEATURE_MASK_PKRU)
3717 				memcpy(&vcpu->arch.pkru, src + offset,
3718 				       sizeof(vcpu->arch.pkru));
3719 			else
3720 				memcpy(dest, src + offset, size);
3721 		}
3722 
3723 		valid -= feature;
3724 	}
3725 }
3726 
3727 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3728 					 struct kvm_xsave *guest_xsave)
3729 {
3730 	if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3731 		memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3732 		fill_xsave((u8 *) guest_xsave->region, vcpu);
3733 	} else {
3734 		memcpy(guest_xsave->region,
3735 			&vcpu->arch.guest_fpu->state.fxsave,
3736 			sizeof(struct fxregs_state));
3737 		*(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3738 			XFEATURE_MASK_FPSSE;
3739 	}
3740 }
3741 
3742 #define XSAVE_MXCSR_OFFSET 24
3743 
3744 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3745 					struct kvm_xsave *guest_xsave)
3746 {
3747 	u64 xstate_bv =
3748 		*(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3749 	u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3750 
3751 	if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3752 		/*
3753 		 * Here we allow setting states that are not present in
3754 		 * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
3755 		 * with old userspace.
3756 		 */
3757 		if (xstate_bv & ~kvm_supported_xcr0() ||
3758 			mxcsr & ~mxcsr_feature_mask)
3759 			return -EINVAL;
3760 		load_xsave(vcpu, (u8 *)guest_xsave->region);
3761 	} else {
3762 		if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3763 			mxcsr & ~mxcsr_feature_mask)
3764 			return -EINVAL;
3765 		memcpy(&vcpu->arch.guest_fpu->state.fxsave,
3766 			guest_xsave->region, sizeof(struct fxregs_state));
3767 	}
3768 	return 0;
3769 }
3770 
3771 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3772 					struct kvm_xcrs *guest_xcrs)
3773 {
3774 	if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3775 		guest_xcrs->nr_xcrs = 0;
3776 		return;
3777 	}
3778 
3779 	guest_xcrs->nr_xcrs = 1;
3780 	guest_xcrs->flags = 0;
3781 	guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3782 	guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3783 }
3784 
3785 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3786 				       struct kvm_xcrs *guest_xcrs)
3787 {
3788 	int i, r = 0;
3789 
3790 	if (!boot_cpu_has(X86_FEATURE_XSAVE))
3791 		return -EINVAL;
3792 
3793 	if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3794 		return -EINVAL;
3795 
3796 	for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3797 		/* Only support XCR0 currently */
3798 		if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3799 			r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3800 				guest_xcrs->xcrs[i].value);
3801 			break;
3802 		}
3803 	if (r)
3804 		r = -EINVAL;
3805 	return r;
3806 }
3807 
3808 /*
3809  * kvm_set_guest_paused() indicates to the guest kernel that it has been
3810  * stopped by the hypervisor.  This function will be called from the host only.
3811  * EINVAL is returned when the host attempts to set the flag for a guest that
3812  * does not support pv clocks.
3813  */
3814 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3815 {
3816 	if (!vcpu->arch.pv_time_enabled)
3817 		return -EINVAL;
3818 	vcpu->arch.pvclock_set_guest_stopped_request = true;
3819 	kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3820 	return 0;
3821 }
3822 
3823 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3824 				     struct kvm_enable_cap *cap)
3825 {
3826 	int r;
3827 	uint16_t vmcs_version;
3828 	void __user *user_ptr;
3829 
3830 	if (cap->flags)
3831 		return -EINVAL;
3832 
3833 	switch (cap->cap) {
3834 	case KVM_CAP_HYPERV_SYNIC2:
3835 		if (cap->args[0])
3836 			return -EINVAL;
3837 		/* fall through */
3838 
3839 	case KVM_CAP_HYPERV_SYNIC:
3840 		if (!irqchip_in_kernel(vcpu->kvm))
3841 			return -EINVAL;
3842 		return kvm_hv_activate_synic(vcpu, cap->cap ==
3843 					     KVM_CAP_HYPERV_SYNIC2);
3844 	case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3845 		if (!kvm_x86_ops->nested_enable_evmcs)
3846 			return -ENOTTY;
3847 		r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3848 		if (!r) {
3849 			user_ptr = (void __user *)(uintptr_t)cap->args[0];
3850 			if (copy_to_user(user_ptr, &vmcs_version,
3851 					 sizeof(vmcs_version)))
3852 				r = -EFAULT;
3853 		}
3854 		return r;
3855 
3856 	default:
3857 		return -EINVAL;
3858 	}
3859 }
3860 
3861 long kvm_arch_vcpu_ioctl(struct file *filp,
3862 			 unsigned int ioctl, unsigned long arg)
3863 {
3864 	struct kvm_vcpu *vcpu = filp->private_data;
3865 	void __user *argp = (void __user *)arg;
3866 	int r;
3867 	union {
3868 		struct kvm_lapic_state *lapic;
3869 		struct kvm_xsave *xsave;
3870 		struct kvm_xcrs *xcrs;
3871 		void *buffer;
3872 	} u;
3873 
3874 	vcpu_load(vcpu);
3875 
3876 	u.buffer = NULL;
3877 	switch (ioctl) {
3878 	case KVM_GET_LAPIC: {
3879 		r = -EINVAL;
3880 		if (!lapic_in_kernel(vcpu))
3881 			goto out;
3882 		u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3883 
3884 		r = -ENOMEM;
3885 		if (!u.lapic)
3886 			goto out;
3887 		r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3888 		if (r)
3889 			goto out;
3890 		r = -EFAULT;
3891 		if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3892 			goto out;
3893 		r = 0;
3894 		break;
3895 	}
3896 	case KVM_SET_LAPIC: {
3897 		r = -EINVAL;
3898 		if (!lapic_in_kernel(vcpu))
3899 			goto out;
3900 		u.lapic = memdup_user(argp, sizeof(*u.lapic));
3901 		if (IS_ERR(u.lapic)) {
3902 			r = PTR_ERR(u.lapic);
3903 			goto out_nofree;
3904 		}
3905 
3906 		r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3907 		break;
3908 	}
3909 	case KVM_INTERRUPT: {
3910 		struct kvm_interrupt irq;
3911 
3912 		r = -EFAULT;
3913 		if (copy_from_user(&irq, argp, sizeof(irq)))
3914 			goto out;
3915 		r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3916 		break;
3917 	}
3918 	case KVM_NMI: {
3919 		r = kvm_vcpu_ioctl_nmi(vcpu);
3920 		break;
3921 	}
3922 	case KVM_SMI: {
3923 		r = kvm_vcpu_ioctl_smi(vcpu);
3924 		break;
3925 	}
3926 	case KVM_SET_CPUID: {
3927 		struct kvm_cpuid __user *cpuid_arg = argp;
3928 		struct kvm_cpuid cpuid;
3929 
3930 		r = -EFAULT;
3931 		if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3932 			goto out;
3933 		r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3934 		break;
3935 	}
3936 	case KVM_SET_CPUID2: {
3937 		struct kvm_cpuid2 __user *cpuid_arg = argp;
3938 		struct kvm_cpuid2 cpuid;
3939 
3940 		r = -EFAULT;
3941 		if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3942 			goto out;
3943 		r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3944 					      cpuid_arg->entries);
3945 		break;
3946 	}
3947 	case KVM_GET_CPUID2: {
3948 		struct kvm_cpuid2 __user *cpuid_arg = argp;
3949 		struct kvm_cpuid2 cpuid;
3950 
3951 		r = -EFAULT;
3952 		if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3953 			goto out;
3954 		r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3955 					      cpuid_arg->entries);
3956 		if (r)
3957 			goto out;
3958 		r = -EFAULT;
3959 		if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3960 			goto out;
3961 		r = 0;
3962 		break;
3963 	}
3964 	case KVM_GET_MSRS: {
3965 		int idx = srcu_read_lock(&vcpu->kvm->srcu);
3966 		r = msr_io(vcpu, argp, do_get_msr, 1);
3967 		srcu_read_unlock(&vcpu->kvm->srcu, idx);
3968 		break;
3969 	}
3970 	case KVM_SET_MSRS: {
3971 		int idx = srcu_read_lock(&vcpu->kvm->srcu);
3972 		r = msr_io(vcpu, argp, do_set_msr, 0);
3973 		srcu_read_unlock(&vcpu->kvm->srcu, idx);
3974 		break;
3975 	}
3976 	case KVM_TPR_ACCESS_REPORTING: {
3977 		struct kvm_tpr_access_ctl tac;
3978 
3979 		r = -EFAULT;
3980 		if (copy_from_user(&tac, argp, sizeof(tac)))
3981 			goto out;
3982 		r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3983 		if (r)
3984 			goto out;
3985 		r = -EFAULT;
3986 		if (copy_to_user(argp, &tac, sizeof(tac)))
3987 			goto out;
3988 		r = 0;
3989 		break;
3990 	};
3991 	case KVM_SET_VAPIC_ADDR: {
3992 		struct kvm_vapic_addr va;
3993 		int idx;
3994 
3995 		r = -EINVAL;
3996 		if (!lapic_in_kernel(vcpu))
3997 			goto out;
3998 		r = -EFAULT;
3999 		if (copy_from_user(&va, argp, sizeof(va)))
4000 			goto out;
4001 		idx = srcu_read_lock(&vcpu->kvm->srcu);
4002 		r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4003 		srcu_read_unlock(&vcpu->kvm->srcu, idx);
4004 		break;
4005 	}
4006 	case KVM_X86_SETUP_MCE: {
4007 		u64 mcg_cap;
4008 
4009 		r = -EFAULT;
4010 		if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4011 			goto out;
4012 		r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4013 		break;
4014 	}
4015 	case KVM_X86_SET_MCE: {
4016 		struct kvm_x86_mce mce;
4017 
4018 		r = -EFAULT;
4019 		if (copy_from_user(&mce, argp, sizeof(mce)))
4020 			goto out;
4021 		r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4022 		break;
4023 	}
4024 	case KVM_GET_VCPU_EVENTS: {
4025 		struct kvm_vcpu_events events;
4026 
4027 		kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4028 
4029 		r = -EFAULT;
4030 		if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4031 			break;
4032 		r = 0;
4033 		break;
4034 	}
4035 	case KVM_SET_VCPU_EVENTS: {
4036 		struct kvm_vcpu_events events;
4037 
4038 		r = -EFAULT;
4039 		if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4040 			break;
4041 
4042 		r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4043 		break;
4044 	}
4045 	case KVM_GET_DEBUGREGS: {
4046 		struct kvm_debugregs dbgregs;
4047 
4048 		kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4049 
4050 		r = -EFAULT;
4051 		if (copy_to_user(argp, &dbgregs,
4052 				 sizeof(struct kvm_debugregs)))
4053 			break;
4054 		r = 0;
4055 		break;
4056 	}
4057 	case KVM_SET_DEBUGREGS: {
4058 		struct kvm_debugregs dbgregs;
4059 
4060 		r = -EFAULT;
4061 		if (copy_from_user(&dbgregs, argp,
4062 				   sizeof(struct kvm_debugregs)))
4063 			break;
4064 
4065 		r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4066 		break;
4067 	}
4068 	case KVM_GET_XSAVE: {
4069 		u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
4070 		r = -ENOMEM;
4071 		if (!u.xsave)
4072 			break;
4073 
4074 		kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4075 
4076 		r = -EFAULT;
4077 		if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4078 			break;
4079 		r = 0;
4080 		break;
4081 	}
4082 	case KVM_SET_XSAVE: {
4083 		u.xsave = memdup_user(argp, sizeof(*u.xsave));
4084 		if (IS_ERR(u.xsave)) {
4085 			r = PTR_ERR(u.xsave);
4086 			goto out_nofree;
4087 		}
4088 
4089 		r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4090 		break;
4091 	}
4092 	case KVM_GET_XCRS: {
4093 		u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
4094 		r = -ENOMEM;
4095 		if (!u.xcrs)
4096 			break;
4097 
4098 		kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4099 
4100 		r = -EFAULT;
4101 		if (copy_to_user(argp, u.xcrs,
4102 				 sizeof(struct kvm_xcrs)))
4103 			break;
4104 		r = 0;
4105 		break;
4106 	}
4107 	case KVM_SET_XCRS: {
4108 		u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4109 		if (IS_ERR(u.xcrs)) {
4110 			r = PTR_ERR(u.xcrs);
4111 			goto out_nofree;
4112 		}
4113 
4114 		r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4115 		break;
4116 	}
4117 	case KVM_SET_TSC_KHZ: {
4118 		u32 user_tsc_khz;
4119 
4120 		r = -EINVAL;
4121 		user_tsc_khz = (u32)arg;
4122 
4123 		if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4124 			goto out;
4125 
4126 		if (user_tsc_khz == 0)
4127 			user_tsc_khz = tsc_khz;
4128 
4129 		if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4130 			r = 0;
4131 
4132 		goto out;
4133 	}
4134 	case KVM_GET_TSC_KHZ: {
4135 		r = vcpu->arch.virtual_tsc_khz;
4136 		goto out;
4137 	}
4138 	case KVM_KVMCLOCK_CTRL: {
4139 		r = kvm_set_guest_paused(vcpu);
4140 		goto out;
4141 	}
4142 	case KVM_ENABLE_CAP: {
4143 		struct kvm_enable_cap cap;
4144 
4145 		r = -EFAULT;
4146 		if (copy_from_user(&cap, argp, sizeof(cap)))
4147 			goto out;
4148 		r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4149 		break;
4150 	}
4151 	case KVM_GET_NESTED_STATE: {
4152 		struct kvm_nested_state __user *user_kvm_nested_state = argp;
4153 		u32 user_data_size;
4154 
4155 		r = -EINVAL;
4156 		if (!kvm_x86_ops->get_nested_state)
4157 			break;
4158 
4159 		BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4160 		r = -EFAULT;
4161 		if (get_user(user_data_size, &user_kvm_nested_state->size))
4162 			break;
4163 
4164 		r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4165 						  user_data_size);
4166 		if (r < 0)
4167 			break;
4168 
4169 		if (r > user_data_size) {
4170 			if (put_user(r, &user_kvm_nested_state->size))
4171 				r = -EFAULT;
4172 			else
4173 				r = -E2BIG;
4174 			break;
4175 		}
4176 
4177 		r = 0;
4178 		break;
4179 	}
4180 	case KVM_SET_NESTED_STATE: {
4181 		struct kvm_nested_state __user *user_kvm_nested_state = argp;
4182 		struct kvm_nested_state kvm_state;
4183 
4184 		r = -EINVAL;
4185 		if (!kvm_x86_ops->set_nested_state)
4186 			break;
4187 
4188 		r = -EFAULT;
4189 		if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4190 			break;
4191 
4192 		r = -EINVAL;
4193 		if (kvm_state.size < sizeof(kvm_state))
4194 			break;
4195 
4196 		if (kvm_state.flags &
4197 		    ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4198 		      | KVM_STATE_NESTED_EVMCS))
4199 			break;
4200 
4201 		/* nested_run_pending implies guest_mode.  */
4202 		if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4203 		    && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4204 			break;
4205 
4206 		r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4207 		break;
4208 	}
4209 	case KVM_GET_SUPPORTED_HV_CPUID: {
4210 		struct kvm_cpuid2 __user *cpuid_arg = argp;
4211 		struct kvm_cpuid2 cpuid;
4212 
4213 		r = -EFAULT;
4214 		if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4215 			goto out;
4216 
4217 		r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4218 						cpuid_arg->entries);
4219 		if (r)
4220 			goto out;
4221 
4222 		r = -EFAULT;
4223 		if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4224 			goto out;
4225 		r = 0;
4226 		break;
4227 	}
4228 	default:
4229 		r = -EINVAL;
4230 	}
4231 out:
4232 	kfree(u.buffer);
4233 out_nofree:
4234 	vcpu_put(vcpu);
4235 	return r;
4236 }
4237 
4238 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4239 {
4240 	return VM_FAULT_SIGBUS;
4241 }
4242 
4243 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4244 {
4245 	int ret;
4246 
4247 	if (addr > (unsigned int)(-3 * PAGE_SIZE))
4248 		return -EINVAL;
4249 	ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4250 	return ret;
4251 }
4252 
4253 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4254 					      u64 ident_addr)
4255 {
4256 	return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4257 }
4258 
4259 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4260 					  u32 kvm_nr_mmu_pages)
4261 {
4262 	if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4263 		return -EINVAL;
4264 
4265 	mutex_lock(&kvm->slots_lock);
4266 
4267 	kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4268 	kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4269 
4270 	mutex_unlock(&kvm->slots_lock);
4271 	return 0;
4272 }
4273 
4274 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4275 {
4276 	return kvm->arch.n_max_mmu_pages;
4277 }
4278 
4279 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4280 {
4281 	struct kvm_pic *pic = kvm->arch.vpic;
4282 	int r;
4283 
4284 	r = 0;
4285 	switch (chip->chip_id) {
4286 	case KVM_IRQCHIP_PIC_MASTER:
4287 		memcpy(&chip->chip.pic, &pic->pics[0],
4288 			sizeof(struct kvm_pic_state));
4289 		break;
4290 	case KVM_IRQCHIP_PIC_SLAVE:
4291 		memcpy(&chip->chip.pic, &pic->pics[1],
4292 			sizeof(struct kvm_pic_state));
4293 		break;
4294 	case KVM_IRQCHIP_IOAPIC:
4295 		kvm_get_ioapic(kvm, &chip->chip.ioapic);
4296 		break;
4297 	default:
4298 		r = -EINVAL;
4299 		break;
4300 	}
4301 	return r;
4302 }
4303 
4304 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4305 {
4306 	struct kvm_pic *pic = kvm->arch.vpic;
4307 	int r;
4308 
4309 	r = 0;
4310 	switch (chip->chip_id) {
4311 	case KVM_IRQCHIP_PIC_MASTER:
4312 		spin_lock(&pic->lock);
4313 		memcpy(&pic->pics[0], &chip->chip.pic,
4314 			sizeof(struct kvm_pic_state));
4315 		spin_unlock(&pic->lock);
4316 		break;
4317 	case KVM_IRQCHIP_PIC_SLAVE:
4318 		spin_lock(&pic->lock);
4319 		memcpy(&pic->pics[1], &chip->chip.pic,
4320 			sizeof(struct kvm_pic_state));
4321 		spin_unlock(&pic->lock);
4322 		break;
4323 	case KVM_IRQCHIP_IOAPIC:
4324 		kvm_set_ioapic(kvm, &chip->chip.ioapic);
4325 		break;
4326 	default:
4327 		r = -EINVAL;
4328 		break;
4329 	}
4330 	kvm_pic_update_irq(pic);
4331 	return r;
4332 }
4333 
4334 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4335 {
4336 	struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4337 
4338 	BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4339 
4340 	mutex_lock(&kps->lock);
4341 	memcpy(ps, &kps->channels, sizeof(*ps));
4342 	mutex_unlock(&kps->lock);
4343 	return 0;
4344 }
4345 
4346 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4347 {
4348 	int i;
4349 	struct kvm_pit *pit = kvm->arch.vpit;
4350 
4351 	mutex_lock(&pit->pit_state.lock);
4352 	memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4353 	for (i = 0; i < 3; i++)
4354 		kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4355 	mutex_unlock(&pit->pit_state.lock);
4356 	return 0;
4357 }
4358 
4359 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4360 {
4361 	mutex_lock(&kvm->arch.vpit->pit_state.lock);
4362 	memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4363 		sizeof(ps->channels));
4364 	ps->flags = kvm->arch.vpit->pit_state.flags;
4365 	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4366 	memset(&ps->reserved, 0, sizeof(ps->reserved));
4367 	return 0;
4368 }
4369 
4370 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4371 {
4372 	int start = 0;
4373 	int i;
4374 	u32 prev_legacy, cur_legacy;
4375 	struct kvm_pit *pit = kvm->arch.vpit;
4376 
4377 	mutex_lock(&pit->pit_state.lock);
4378 	prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4379 	cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4380 	if (!prev_legacy && cur_legacy)
4381 		start = 1;
4382 	memcpy(&pit->pit_state.channels, &ps->channels,
4383 	       sizeof(pit->pit_state.channels));
4384 	pit->pit_state.flags = ps->flags;
4385 	for (i = 0; i < 3; i++)
4386 		kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4387 				   start && i == 0);
4388 	mutex_unlock(&pit->pit_state.lock);
4389 	return 0;
4390 }
4391 
4392 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4393 				 struct kvm_reinject_control *control)
4394 {
4395 	struct kvm_pit *pit = kvm->arch.vpit;
4396 
4397 	if (!pit)
4398 		return -ENXIO;
4399 
4400 	/* pit->pit_state.lock was overloaded to prevent userspace from getting
4401 	 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4402 	 * ioctls in parallel.  Use a separate lock if that ioctl isn't rare.
4403 	 */
4404 	mutex_lock(&pit->pit_state.lock);
4405 	kvm_pit_set_reinject(pit, control->pit_reinject);
4406 	mutex_unlock(&pit->pit_state.lock);
4407 
4408 	return 0;
4409 }
4410 
4411 /**
4412  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4413  * @kvm: kvm instance
4414  * @log: slot id and address to which we copy the log
4415  *
4416  * Steps 1-4 below provide general overview of dirty page logging. See
4417  * kvm_get_dirty_log_protect() function description for additional details.
4418  *
4419  * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4420  * always flush the TLB (step 4) even if previous step failed  and the dirty
4421  * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4422  * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4423  * writes will be marked dirty for next log read.
4424  *
4425  *   1. Take a snapshot of the bit and clear it if needed.
4426  *   2. Write protect the corresponding page.
4427  *   3. Copy the snapshot to the userspace.
4428  *   4. Flush TLB's if needed.
4429  */
4430 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4431 {
4432 	bool flush = false;
4433 	int r;
4434 
4435 	mutex_lock(&kvm->slots_lock);
4436 
4437 	/*
4438 	 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4439 	 */
4440 	if (kvm_x86_ops->flush_log_dirty)
4441 		kvm_x86_ops->flush_log_dirty(kvm);
4442 
4443 	r = kvm_get_dirty_log_protect(kvm, log, &flush);
4444 
4445 	/*
4446 	 * All the TLBs can be flushed out of mmu lock, see the comments in
4447 	 * kvm_mmu_slot_remove_write_access().
4448 	 */
4449 	lockdep_assert_held(&kvm->slots_lock);
4450 	if (flush)
4451 		kvm_flush_remote_tlbs(kvm);
4452 
4453 	mutex_unlock(&kvm->slots_lock);
4454 	return r;
4455 }
4456 
4457 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4458 {
4459 	bool flush = false;
4460 	int r;
4461 
4462 	mutex_lock(&kvm->slots_lock);
4463 
4464 	/*
4465 	 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4466 	 */
4467 	if (kvm_x86_ops->flush_log_dirty)
4468 		kvm_x86_ops->flush_log_dirty(kvm);
4469 
4470 	r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4471 
4472 	/*
4473 	 * All the TLBs can be flushed out of mmu lock, see the comments in
4474 	 * kvm_mmu_slot_remove_write_access().
4475 	 */
4476 	lockdep_assert_held(&kvm->slots_lock);
4477 	if (flush)
4478 		kvm_flush_remote_tlbs(kvm);
4479 
4480 	mutex_unlock(&kvm->slots_lock);
4481 	return r;
4482 }
4483 
4484 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4485 			bool line_status)
4486 {
4487 	if (!irqchip_in_kernel(kvm))
4488 		return -ENXIO;
4489 
4490 	irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4491 					irq_event->irq, irq_event->level,
4492 					line_status);
4493 	return 0;
4494 }
4495 
4496 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4497 			    struct kvm_enable_cap *cap)
4498 {
4499 	int r;
4500 
4501 	if (cap->flags)
4502 		return -EINVAL;
4503 
4504 	switch (cap->cap) {
4505 	case KVM_CAP_DISABLE_QUIRKS:
4506 		kvm->arch.disabled_quirks = cap->args[0];
4507 		r = 0;
4508 		break;
4509 	case KVM_CAP_SPLIT_IRQCHIP: {
4510 		mutex_lock(&kvm->lock);
4511 		r = -EINVAL;
4512 		if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4513 			goto split_irqchip_unlock;
4514 		r = -EEXIST;
4515 		if (irqchip_in_kernel(kvm))
4516 			goto split_irqchip_unlock;
4517 		if (kvm->created_vcpus)
4518 			goto split_irqchip_unlock;
4519 		r = kvm_setup_empty_irq_routing(kvm);
4520 		if (r)
4521 			goto split_irqchip_unlock;
4522 		/* Pairs with irqchip_in_kernel. */
4523 		smp_wmb();
4524 		kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4525 		kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4526 		r = 0;
4527 split_irqchip_unlock:
4528 		mutex_unlock(&kvm->lock);
4529 		break;
4530 	}
4531 	case KVM_CAP_X2APIC_API:
4532 		r = -EINVAL;
4533 		if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4534 			break;
4535 
4536 		if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4537 			kvm->arch.x2apic_format = true;
4538 		if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4539 			kvm->arch.x2apic_broadcast_quirk_disabled = true;
4540 
4541 		r = 0;
4542 		break;
4543 	case KVM_CAP_X86_DISABLE_EXITS:
4544 		r = -EINVAL;
4545 		if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4546 			break;
4547 
4548 		if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4549 			kvm_can_mwait_in_guest())
4550 			kvm->arch.mwait_in_guest = true;
4551 		if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4552 			kvm->arch.hlt_in_guest = true;
4553 		if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4554 			kvm->arch.pause_in_guest = true;
4555 		r = 0;
4556 		break;
4557 	case KVM_CAP_MSR_PLATFORM_INFO:
4558 		kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4559 		r = 0;
4560 		break;
4561 	case KVM_CAP_EXCEPTION_PAYLOAD:
4562 		kvm->arch.exception_payload_enabled = cap->args[0];
4563 		r = 0;
4564 		break;
4565 	default:
4566 		r = -EINVAL;
4567 		break;
4568 	}
4569 	return r;
4570 }
4571 
4572 long kvm_arch_vm_ioctl(struct file *filp,
4573 		       unsigned int ioctl, unsigned long arg)
4574 {
4575 	struct kvm *kvm = filp->private_data;
4576 	void __user *argp = (void __user *)arg;
4577 	int r = -ENOTTY;
4578 	/*
4579 	 * This union makes it completely explicit to gcc-3.x
4580 	 * that these two variables' stack usage should be
4581 	 * combined, not added together.
4582 	 */
4583 	union {
4584 		struct kvm_pit_state ps;
4585 		struct kvm_pit_state2 ps2;
4586 		struct kvm_pit_config pit_config;
4587 	} u;
4588 
4589 	switch (ioctl) {
4590 	case KVM_SET_TSS_ADDR:
4591 		r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4592 		break;
4593 	case KVM_SET_IDENTITY_MAP_ADDR: {
4594 		u64 ident_addr;
4595 
4596 		mutex_lock(&kvm->lock);
4597 		r = -EINVAL;
4598 		if (kvm->created_vcpus)
4599 			goto set_identity_unlock;
4600 		r = -EFAULT;
4601 		if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4602 			goto set_identity_unlock;
4603 		r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4604 set_identity_unlock:
4605 		mutex_unlock(&kvm->lock);
4606 		break;
4607 	}
4608 	case KVM_SET_NR_MMU_PAGES:
4609 		r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4610 		break;
4611 	case KVM_GET_NR_MMU_PAGES:
4612 		r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4613 		break;
4614 	case KVM_CREATE_IRQCHIP: {
4615 		mutex_lock(&kvm->lock);
4616 
4617 		r = -EEXIST;
4618 		if (irqchip_in_kernel(kvm))
4619 			goto create_irqchip_unlock;
4620 
4621 		r = -EINVAL;
4622 		if (kvm->created_vcpus)
4623 			goto create_irqchip_unlock;
4624 
4625 		r = kvm_pic_init(kvm);
4626 		if (r)
4627 			goto create_irqchip_unlock;
4628 
4629 		r = kvm_ioapic_init(kvm);
4630 		if (r) {
4631 			kvm_pic_destroy(kvm);
4632 			goto create_irqchip_unlock;
4633 		}
4634 
4635 		r = kvm_setup_default_irq_routing(kvm);
4636 		if (r) {
4637 			kvm_ioapic_destroy(kvm);
4638 			kvm_pic_destroy(kvm);
4639 			goto create_irqchip_unlock;
4640 		}
4641 		/* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4642 		smp_wmb();
4643 		kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4644 	create_irqchip_unlock:
4645 		mutex_unlock(&kvm->lock);
4646 		break;
4647 	}
4648 	case KVM_CREATE_PIT:
4649 		u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4650 		goto create_pit;
4651 	case KVM_CREATE_PIT2:
4652 		r = -EFAULT;
4653 		if (copy_from_user(&u.pit_config, argp,
4654 				   sizeof(struct kvm_pit_config)))
4655 			goto out;
4656 	create_pit:
4657 		mutex_lock(&kvm->lock);
4658 		r = -EEXIST;
4659 		if (kvm->arch.vpit)
4660 			goto create_pit_unlock;
4661 		r = -ENOMEM;
4662 		kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4663 		if (kvm->arch.vpit)
4664 			r = 0;
4665 	create_pit_unlock:
4666 		mutex_unlock(&kvm->lock);
4667 		break;
4668 	case KVM_GET_IRQCHIP: {
4669 		/* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4670 		struct kvm_irqchip *chip;
4671 
4672 		chip = memdup_user(argp, sizeof(*chip));
4673 		if (IS_ERR(chip)) {
4674 			r = PTR_ERR(chip);
4675 			goto out;
4676 		}
4677 
4678 		r = -ENXIO;
4679 		if (!irqchip_kernel(kvm))
4680 			goto get_irqchip_out;
4681 		r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4682 		if (r)
4683 			goto get_irqchip_out;
4684 		r = -EFAULT;
4685 		if (copy_to_user(argp, chip, sizeof(*chip)))
4686 			goto get_irqchip_out;
4687 		r = 0;
4688 	get_irqchip_out:
4689 		kfree(chip);
4690 		break;
4691 	}
4692 	case KVM_SET_IRQCHIP: {
4693 		/* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4694 		struct kvm_irqchip *chip;
4695 
4696 		chip = memdup_user(argp, sizeof(*chip));
4697 		if (IS_ERR(chip)) {
4698 			r = PTR_ERR(chip);
4699 			goto out;
4700 		}
4701 
4702 		r = -ENXIO;
4703 		if (!irqchip_kernel(kvm))
4704 			goto set_irqchip_out;
4705 		r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4706 		if (r)
4707 			goto set_irqchip_out;
4708 		r = 0;
4709 	set_irqchip_out:
4710 		kfree(chip);
4711 		break;
4712 	}
4713 	case KVM_GET_PIT: {
4714 		r = -EFAULT;
4715 		if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4716 			goto out;
4717 		r = -ENXIO;
4718 		if (!kvm->arch.vpit)
4719 			goto out;
4720 		r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4721 		if (r)
4722 			goto out;
4723 		r = -EFAULT;
4724 		if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4725 			goto out;
4726 		r = 0;
4727 		break;
4728 	}
4729 	case KVM_SET_PIT: {
4730 		r = -EFAULT;
4731 		if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
4732 			goto out;
4733 		r = -ENXIO;
4734 		if (!kvm->arch.vpit)
4735 			goto out;
4736 		r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4737 		break;
4738 	}
4739 	case KVM_GET_PIT2: {
4740 		r = -ENXIO;
4741 		if (!kvm->arch.vpit)
4742 			goto out;
4743 		r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4744 		if (r)
4745 			goto out;
4746 		r = -EFAULT;
4747 		if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4748 			goto out;
4749 		r = 0;
4750 		break;
4751 	}
4752 	case KVM_SET_PIT2: {
4753 		r = -EFAULT;
4754 		if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4755 			goto out;
4756 		r = -ENXIO;
4757 		if (!kvm->arch.vpit)
4758 			goto out;
4759 		r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4760 		break;
4761 	}
4762 	case KVM_REINJECT_CONTROL: {
4763 		struct kvm_reinject_control control;
4764 		r =  -EFAULT;
4765 		if (copy_from_user(&control, argp, sizeof(control)))
4766 			goto out;
4767 		r = kvm_vm_ioctl_reinject(kvm, &control);
4768 		break;
4769 	}
4770 	case KVM_SET_BOOT_CPU_ID:
4771 		r = 0;
4772 		mutex_lock(&kvm->lock);
4773 		if (kvm->created_vcpus)
4774 			r = -EBUSY;
4775 		else
4776 			kvm->arch.bsp_vcpu_id = arg;
4777 		mutex_unlock(&kvm->lock);
4778 		break;
4779 	case KVM_XEN_HVM_CONFIG: {
4780 		struct kvm_xen_hvm_config xhc;
4781 		r = -EFAULT;
4782 		if (copy_from_user(&xhc, argp, sizeof(xhc)))
4783 			goto out;
4784 		r = -EINVAL;
4785 		if (xhc.flags)
4786 			goto out;
4787 		memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
4788 		r = 0;
4789 		break;
4790 	}
4791 	case KVM_SET_CLOCK: {
4792 		struct kvm_clock_data user_ns;
4793 		u64 now_ns;
4794 
4795 		r = -EFAULT;
4796 		if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4797 			goto out;
4798 
4799 		r = -EINVAL;
4800 		if (user_ns.flags)
4801 			goto out;
4802 
4803 		r = 0;
4804 		/*
4805 		 * TODO: userspace has to take care of races with VCPU_RUN, so
4806 		 * kvm_gen_update_masterclock() can be cut down to locked
4807 		 * pvclock_update_vm_gtod_copy().
4808 		 */
4809 		kvm_gen_update_masterclock(kvm);
4810 		now_ns = get_kvmclock_ns(kvm);
4811 		kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
4812 		kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
4813 		break;
4814 	}
4815 	case KVM_GET_CLOCK: {
4816 		struct kvm_clock_data user_ns;
4817 		u64 now_ns;
4818 
4819 		now_ns = get_kvmclock_ns(kvm);
4820 		user_ns.clock = now_ns;
4821 		user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4822 		memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4823 
4824 		r = -EFAULT;
4825 		if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4826 			goto out;
4827 		r = 0;
4828 		break;
4829 	}
4830 	case KVM_MEMORY_ENCRYPT_OP: {
4831 		r = -ENOTTY;
4832 		if (kvm_x86_ops->mem_enc_op)
4833 			r = kvm_x86_ops->mem_enc_op(kvm, argp);
4834 		break;
4835 	}
4836 	case KVM_MEMORY_ENCRYPT_REG_REGION: {
4837 		struct kvm_enc_region region;
4838 
4839 		r = -EFAULT;
4840 		if (copy_from_user(&region, argp, sizeof(region)))
4841 			goto out;
4842 
4843 		r = -ENOTTY;
4844 		if (kvm_x86_ops->mem_enc_reg_region)
4845 			r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4846 		break;
4847 	}
4848 	case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4849 		struct kvm_enc_region region;
4850 
4851 		r = -EFAULT;
4852 		if (copy_from_user(&region, argp, sizeof(region)))
4853 			goto out;
4854 
4855 		r = -ENOTTY;
4856 		if (kvm_x86_ops->mem_enc_unreg_region)
4857 			r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4858 		break;
4859 	}
4860 	case KVM_HYPERV_EVENTFD: {
4861 		struct kvm_hyperv_eventfd hvevfd;
4862 
4863 		r = -EFAULT;
4864 		if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4865 			goto out;
4866 		r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4867 		break;
4868 	}
4869 	default:
4870 		r = -ENOTTY;
4871 	}
4872 out:
4873 	return r;
4874 }
4875 
4876 static void kvm_init_msr_list(void)
4877 {
4878 	u32 dummy[2];
4879 	unsigned i, j;
4880 
4881 	for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4882 		if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4883 			continue;
4884 
4885 		/*
4886 		 * Even MSRs that are valid in the host may not be exposed
4887 		 * to the guests in some cases.
4888 		 */
4889 		switch (msrs_to_save[i]) {
4890 		case MSR_IA32_BNDCFGS:
4891 			if (!kvm_mpx_supported())
4892 				continue;
4893 			break;
4894 		case MSR_TSC_AUX:
4895 			if (!kvm_x86_ops->rdtscp_supported())
4896 				continue;
4897 			break;
4898 		case MSR_IA32_RTIT_CTL:
4899 		case MSR_IA32_RTIT_STATUS:
4900 			if (!kvm_x86_ops->pt_supported())
4901 				continue;
4902 			break;
4903 		case MSR_IA32_RTIT_CR3_MATCH:
4904 			if (!kvm_x86_ops->pt_supported() ||
4905 			    !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
4906 				continue;
4907 			break;
4908 		case MSR_IA32_RTIT_OUTPUT_BASE:
4909 		case MSR_IA32_RTIT_OUTPUT_MASK:
4910 			if (!kvm_x86_ops->pt_supported() ||
4911 				(!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
4912 				 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
4913 				continue;
4914 			break;
4915 		case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
4916 			if (!kvm_x86_ops->pt_supported() ||
4917 				msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
4918 				intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
4919 				continue;
4920 			break;
4921 		}
4922 		default:
4923 			break;
4924 		}
4925 
4926 		if (j < i)
4927 			msrs_to_save[j] = msrs_to_save[i];
4928 		j++;
4929 	}
4930 	num_msrs_to_save = j;
4931 
4932 	for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4933 		if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4934 			continue;
4935 
4936 		if (j < i)
4937 			emulated_msrs[j] = emulated_msrs[i];
4938 		j++;
4939 	}
4940 	num_emulated_msrs = j;
4941 
4942 	for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4943 		struct kvm_msr_entry msr;
4944 
4945 		msr.index = msr_based_features[i];
4946 		if (kvm_get_msr_feature(&msr))
4947 			continue;
4948 
4949 		if (j < i)
4950 			msr_based_features[j] = msr_based_features[i];
4951 		j++;
4952 	}
4953 	num_msr_based_features = j;
4954 }
4955 
4956 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4957 			   const void *v)
4958 {
4959 	int handled = 0;
4960 	int n;
4961 
4962 	do {
4963 		n = min(len, 8);
4964 		if (!(lapic_in_kernel(vcpu) &&
4965 		      !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4966 		    && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4967 			break;
4968 		handled += n;
4969 		addr += n;
4970 		len -= n;
4971 		v += n;
4972 	} while (len);
4973 
4974 	return handled;
4975 }
4976 
4977 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4978 {
4979 	int handled = 0;
4980 	int n;
4981 
4982 	do {
4983 		n = min(len, 8);
4984 		if (!(lapic_in_kernel(vcpu) &&
4985 		      !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4986 					 addr, n, v))
4987 		    && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4988 			break;
4989 		trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
4990 		handled += n;
4991 		addr += n;
4992 		len -= n;
4993 		v += n;
4994 	} while (len);
4995 
4996 	return handled;
4997 }
4998 
4999 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5000 			struct kvm_segment *var, int seg)
5001 {
5002 	kvm_x86_ops->set_segment(vcpu, var, seg);
5003 }
5004 
5005 void kvm_get_segment(struct kvm_vcpu *vcpu,
5006 		     struct kvm_segment *var, int seg)
5007 {
5008 	kvm_x86_ops->get_segment(vcpu, var, seg);
5009 }
5010 
5011 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5012 			   struct x86_exception *exception)
5013 {
5014 	gpa_t t_gpa;
5015 
5016 	BUG_ON(!mmu_is_nested(vcpu));
5017 
5018 	/* NPT walks are always user-walks */
5019 	access |= PFERR_USER_MASK;
5020 	t_gpa  = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5021 
5022 	return t_gpa;
5023 }
5024 
5025 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5026 			      struct x86_exception *exception)
5027 {
5028 	u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5029 	return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5030 }
5031 
5032  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5033 				struct x86_exception *exception)
5034 {
5035 	u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5036 	access |= PFERR_FETCH_MASK;
5037 	return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5038 }
5039 
5040 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5041 			       struct x86_exception *exception)
5042 {
5043 	u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5044 	access |= PFERR_WRITE_MASK;
5045 	return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5046 }
5047 
5048 /* uses this to access any guest's mapped memory without checking CPL */
5049 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5050 				struct x86_exception *exception)
5051 {
5052 	return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5053 }
5054 
5055 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5056 				      struct kvm_vcpu *vcpu, u32 access,
5057 				      struct x86_exception *exception)
5058 {
5059 	void *data = val;
5060 	int r = X86EMUL_CONTINUE;
5061 
5062 	while (bytes) {
5063 		gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5064 							    exception);
5065 		unsigned offset = addr & (PAGE_SIZE-1);
5066 		unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5067 		int ret;
5068 
5069 		if (gpa == UNMAPPED_GVA)
5070 			return X86EMUL_PROPAGATE_FAULT;
5071 		ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5072 					       offset, toread);
5073 		if (ret < 0) {
5074 			r = X86EMUL_IO_NEEDED;
5075 			goto out;
5076 		}
5077 
5078 		bytes -= toread;
5079 		data += toread;
5080 		addr += toread;
5081 	}
5082 out:
5083 	return r;
5084 }
5085 
5086 /* used for instruction fetching */
5087 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5088 				gva_t addr, void *val, unsigned int bytes,
5089 				struct x86_exception *exception)
5090 {
5091 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5092 	u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5093 	unsigned offset;
5094 	int ret;
5095 
5096 	/* Inline kvm_read_guest_virt_helper for speed.  */
5097 	gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5098 						    exception);
5099 	if (unlikely(gpa == UNMAPPED_GVA))
5100 		return X86EMUL_PROPAGATE_FAULT;
5101 
5102 	offset = addr & (PAGE_SIZE-1);
5103 	if (WARN_ON(offset + bytes > PAGE_SIZE))
5104 		bytes = (unsigned)PAGE_SIZE - offset;
5105 	ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5106 				       offset, bytes);
5107 	if (unlikely(ret < 0))
5108 		return X86EMUL_IO_NEEDED;
5109 
5110 	return X86EMUL_CONTINUE;
5111 }
5112 
5113 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5114 			       gva_t addr, void *val, unsigned int bytes,
5115 			       struct x86_exception *exception)
5116 {
5117 	u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5118 
5119 	/*
5120 	 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5121 	 * is returned, but our callers are not ready for that and they blindly
5122 	 * call kvm_inject_page_fault.  Ensure that they at least do not leak
5123 	 * uninitialized kernel stack memory into cr2 and error code.
5124 	 */
5125 	memset(exception, 0, sizeof(*exception));
5126 	return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5127 					  exception);
5128 }
5129 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5130 
5131 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5132 			     gva_t addr, void *val, unsigned int bytes,
5133 			     struct x86_exception *exception, bool system)
5134 {
5135 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5136 	u32 access = 0;
5137 
5138 	if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5139 		access |= PFERR_USER_MASK;
5140 
5141 	return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5142 }
5143 
5144 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5145 		unsigned long addr, void *val, unsigned int bytes)
5146 {
5147 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5148 	int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5149 
5150 	return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5151 }
5152 
5153 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5154 				      struct kvm_vcpu *vcpu, u32 access,
5155 				      struct x86_exception *exception)
5156 {
5157 	void *data = val;
5158 	int r = X86EMUL_CONTINUE;
5159 
5160 	while (bytes) {
5161 		gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5162 							     access,
5163 							     exception);
5164 		unsigned offset = addr & (PAGE_SIZE-1);
5165 		unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5166 		int ret;
5167 
5168 		if (gpa == UNMAPPED_GVA)
5169 			return X86EMUL_PROPAGATE_FAULT;
5170 		ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5171 		if (ret < 0) {
5172 			r = X86EMUL_IO_NEEDED;
5173 			goto out;
5174 		}
5175 
5176 		bytes -= towrite;
5177 		data += towrite;
5178 		addr += towrite;
5179 	}
5180 out:
5181 	return r;
5182 }
5183 
5184 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5185 			      unsigned int bytes, struct x86_exception *exception,
5186 			      bool system)
5187 {
5188 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5189 	u32 access = PFERR_WRITE_MASK;
5190 
5191 	if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5192 		access |= PFERR_USER_MASK;
5193 
5194 	return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5195 					   access, exception);
5196 }
5197 
5198 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5199 				unsigned int bytes, struct x86_exception *exception)
5200 {
5201 	/* kvm_write_guest_virt_system can pull in tons of pages. */
5202 	vcpu->arch.l1tf_flush_l1d = true;
5203 
5204 	return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5205 					   PFERR_WRITE_MASK, exception);
5206 }
5207 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5208 
5209 int handle_ud(struct kvm_vcpu *vcpu)
5210 {
5211 	int emul_type = EMULTYPE_TRAP_UD;
5212 	enum emulation_result er;
5213 	char sig[5]; /* ud2; .ascii "kvm" */
5214 	struct x86_exception e;
5215 
5216 	if (force_emulation_prefix &&
5217 	    kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5218 				sig, sizeof(sig), &e) == 0 &&
5219 	    memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5220 		kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5221 		emul_type = 0;
5222 	}
5223 
5224 	er = kvm_emulate_instruction(vcpu, emul_type);
5225 	if (er == EMULATE_USER_EXIT)
5226 		return 0;
5227 	if (er != EMULATE_DONE)
5228 		kvm_queue_exception(vcpu, UD_VECTOR);
5229 	return 1;
5230 }
5231 EXPORT_SYMBOL_GPL(handle_ud);
5232 
5233 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5234 			    gpa_t gpa, bool write)
5235 {
5236 	/* For APIC access vmexit */
5237 	if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5238 		return 1;
5239 
5240 	if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5241 		trace_vcpu_match_mmio(gva, gpa, write, true);
5242 		return 1;
5243 	}
5244 
5245 	return 0;
5246 }
5247 
5248 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5249 				gpa_t *gpa, struct x86_exception *exception,
5250 				bool write)
5251 {
5252 	u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5253 		| (write ? PFERR_WRITE_MASK : 0);
5254 
5255 	/*
5256 	 * currently PKRU is only applied to ept enabled guest so
5257 	 * there is no pkey in EPT page table for L1 guest or EPT
5258 	 * shadow page table for L2 guest.
5259 	 */
5260 	if (vcpu_match_mmio_gva(vcpu, gva)
5261 	    && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5262 				 vcpu->arch.access, 0, access)) {
5263 		*gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5264 					(gva & (PAGE_SIZE - 1));
5265 		trace_vcpu_match_mmio(gva, *gpa, write, false);
5266 		return 1;
5267 	}
5268 
5269 	*gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5270 
5271 	if (*gpa == UNMAPPED_GVA)
5272 		return -1;
5273 
5274 	return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5275 }
5276 
5277 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5278 			const void *val, int bytes)
5279 {
5280 	int ret;
5281 
5282 	ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5283 	if (ret < 0)
5284 		return 0;
5285 	kvm_page_track_write(vcpu, gpa, val, bytes);
5286 	return 1;
5287 }
5288 
5289 struct read_write_emulator_ops {
5290 	int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5291 				  int bytes);
5292 	int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5293 				  void *val, int bytes);
5294 	int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5295 			       int bytes, void *val);
5296 	int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5297 				    void *val, int bytes);
5298 	bool write;
5299 };
5300 
5301 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5302 {
5303 	if (vcpu->mmio_read_completed) {
5304 		trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5305 			       vcpu->mmio_fragments[0].gpa, val);
5306 		vcpu->mmio_read_completed = 0;
5307 		return 1;
5308 	}
5309 
5310 	return 0;
5311 }
5312 
5313 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5314 			void *val, int bytes)
5315 {
5316 	return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5317 }
5318 
5319 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5320 			 void *val, int bytes)
5321 {
5322 	return emulator_write_phys(vcpu, gpa, val, bytes);
5323 }
5324 
5325 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5326 {
5327 	trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5328 	return vcpu_mmio_write(vcpu, gpa, bytes, val);
5329 }
5330 
5331 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5332 			  void *val, int bytes)
5333 {
5334 	trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5335 	return X86EMUL_IO_NEEDED;
5336 }
5337 
5338 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5339 			   void *val, int bytes)
5340 {
5341 	struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5342 
5343 	memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5344 	return X86EMUL_CONTINUE;
5345 }
5346 
5347 static const struct read_write_emulator_ops read_emultor = {
5348 	.read_write_prepare = read_prepare,
5349 	.read_write_emulate = read_emulate,
5350 	.read_write_mmio = vcpu_mmio_read,
5351 	.read_write_exit_mmio = read_exit_mmio,
5352 };
5353 
5354 static const struct read_write_emulator_ops write_emultor = {
5355 	.read_write_emulate = write_emulate,
5356 	.read_write_mmio = write_mmio,
5357 	.read_write_exit_mmio = write_exit_mmio,
5358 	.write = true,
5359 };
5360 
5361 static int emulator_read_write_onepage(unsigned long addr, void *val,
5362 				       unsigned int bytes,
5363 				       struct x86_exception *exception,
5364 				       struct kvm_vcpu *vcpu,
5365 				       const struct read_write_emulator_ops *ops)
5366 {
5367 	gpa_t gpa;
5368 	int handled, ret;
5369 	bool write = ops->write;
5370 	struct kvm_mmio_fragment *frag;
5371 	struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5372 
5373 	/*
5374 	 * If the exit was due to a NPF we may already have a GPA.
5375 	 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5376 	 * Note, this cannot be used on string operations since string
5377 	 * operation using rep will only have the initial GPA from the NPF
5378 	 * occurred.
5379 	 */
5380 	if (vcpu->arch.gpa_available &&
5381 	    emulator_can_use_gpa(ctxt) &&
5382 	    (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5383 		gpa = vcpu->arch.gpa_val;
5384 		ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5385 	} else {
5386 		ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5387 		if (ret < 0)
5388 			return X86EMUL_PROPAGATE_FAULT;
5389 	}
5390 
5391 	if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5392 		return X86EMUL_CONTINUE;
5393 
5394 	/*
5395 	 * Is this MMIO handled locally?
5396 	 */
5397 	handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5398 	if (handled == bytes)
5399 		return X86EMUL_CONTINUE;
5400 
5401 	gpa += handled;
5402 	bytes -= handled;
5403 	val += handled;
5404 
5405 	WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5406 	frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5407 	frag->gpa = gpa;
5408 	frag->data = val;
5409 	frag->len = bytes;
5410 	return X86EMUL_CONTINUE;
5411 }
5412 
5413 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5414 			unsigned long addr,
5415 			void *val, unsigned int bytes,
5416 			struct x86_exception *exception,
5417 			const struct read_write_emulator_ops *ops)
5418 {
5419 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5420 	gpa_t gpa;
5421 	int rc;
5422 
5423 	if (ops->read_write_prepare &&
5424 		  ops->read_write_prepare(vcpu, val, bytes))
5425 		return X86EMUL_CONTINUE;
5426 
5427 	vcpu->mmio_nr_fragments = 0;
5428 
5429 	/* Crossing a page boundary? */
5430 	if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5431 		int now;
5432 
5433 		now = -addr & ~PAGE_MASK;
5434 		rc = emulator_read_write_onepage(addr, val, now, exception,
5435 						 vcpu, ops);
5436 
5437 		if (rc != X86EMUL_CONTINUE)
5438 			return rc;
5439 		addr += now;
5440 		if (ctxt->mode != X86EMUL_MODE_PROT64)
5441 			addr = (u32)addr;
5442 		val += now;
5443 		bytes -= now;
5444 	}
5445 
5446 	rc = emulator_read_write_onepage(addr, val, bytes, exception,
5447 					 vcpu, ops);
5448 	if (rc != X86EMUL_CONTINUE)
5449 		return rc;
5450 
5451 	if (!vcpu->mmio_nr_fragments)
5452 		return rc;
5453 
5454 	gpa = vcpu->mmio_fragments[0].gpa;
5455 
5456 	vcpu->mmio_needed = 1;
5457 	vcpu->mmio_cur_fragment = 0;
5458 
5459 	vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5460 	vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5461 	vcpu->run->exit_reason = KVM_EXIT_MMIO;
5462 	vcpu->run->mmio.phys_addr = gpa;
5463 
5464 	return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5465 }
5466 
5467 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5468 				  unsigned long addr,
5469 				  void *val,
5470 				  unsigned int bytes,
5471 				  struct x86_exception *exception)
5472 {
5473 	return emulator_read_write(ctxt, addr, val, bytes,
5474 				   exception, &read_emultor);
5475 }
5476 
5477 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5478 			    unsigned long addr,
5479 			    const void *val,
5480 			    unsigned int bytes,
5481 			    struct x86_exception *exception)
5482 {
5483 	return emulator_read_write(ctxt, addr, (void *)val, bytes,
5484 				   exception, &write_emultor);
5485 }
5486 
5487 #define CMPXCHG_TYPE(t, ptr, old, new) \
5488 	(cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5489 
5490 #ifdef CONFIG_X86_64
5491 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5492 #else
5493 #  define CMPXCHG64(ptr, old, new) \
5494 	(cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5495 #endif
5496 
5497 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5498 				     unsigned long addr,
5499 				     const void *old,
5500 				     const void *new,
5501 				     unsigned int bytes,
5502 				     struct x86_exception *exception)
5503 {
5504 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5505 	gpa_t gpa;
5506 	struct page *page;
5507 	char *kaddr;
5508 	bool exchanged;
5509 
5510 	/* guests cmpxchg8b have to be emulated atomically */
5511 	if (bytes > 8 || (bytes & (bytes - 1)))
5512 		goto emul_write;
5513 
5514 	gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5515 
5516 	if (gpa == UNMAPPED_GVA ||
5517 	    (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5518 		goto emul_write;
5519 
5520 	if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5521 		goto emul_write;
5522 
5523 	page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
5524 	if (is_error_page(page))
5525 		goto emul_write;
5526 
5527 	kaddr = kmap_atomic(page);
5528 	kaddr += offset_in_page(gpa);
5529 	switch (bytes) {
5530 	case 1:
5531 		exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5532 		break;
5533 	case 2:
5534 		exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5535 		break;
5536 	case 4:
5537 		exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5538 		break;
5539 	case 8:
5540 		exchanged = CMPXCHG64(kaddr, old, new);
5541 		break;
5542 	default:
5543 		BUG();
5544 	}
5545 	kunmap_atomic(kaddr);
5546 	kvm_release_page_dirty(page);
5547 
5548 	if (!exchanged)
5549 		return X86EMUL_CMPXCHG_FAILED;
5550 
5551 	kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
5552 	kvm_page_track_write(vcpu, gpa, new, bytes);
5553 
5554 	return X86EMUL_CONTINUE;
5555 
5556 emul_write:
5557 	printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5558 
5559 	return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5560 }
5561 
5562 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5563 {
5564 	int r = 0, i;
5565 
5566 	for (i = 0; i < vcpu->arch.pio.count; i++) {
5567 		if (vcpu->arch.pio.in)
5568 			r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5569 					    vcpu->arch.pio.size, pd);
5570 		else
5571 			r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5572 					     vcpu->arch.pio.port, vcpu->arch.pio.size,
5573 					     pd);
5574 		if (r)
5575 			break;
5576 		pd += vcpu->arch.pio.size;
5577 	}
5578 	return r;
5579 }
5580 
5581 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5582 			       unsigned short port, void *val,
5583 			       unsigned int count, bool in)
5584 {
5585 	vcpu->arch.pio.port = port;
5586 	vcpu->arch.pio.in = in;
5587 	vcpu->arch.pio.count  = count;
5588 	vcpu->arch.pio.size = size;
5589 
5590 	if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5591 		vcpu->arch.pio.count = 0;
5592 		return 1;
5593 	}
5594 
5595 	vcpu->run->exit_reason = KVM_EXIT_IO;
5596 	vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5597 	vcpu->run->io.size = size;
5598 	vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5599 	vcpu->run->io.count = count;
5600 	vcpu->run->io.port = port;
5601 
5602 	return 0;
5603 }
5604 
5605 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5606 				    int size, unsigned short port, void *val,
5607 				    unsigned int count)
5608 {
5609 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5610 	int ret;
5611 
5612 	if (vcpu->arch.pio.count)
5613 		goto data_avail;
5614 
5615 	memset(vcpu->arch.pio_data, 0, size * count);
5616 
5617 	ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5618 	if (ret) {
5619 data_avail:
5620 		memcpy(val, vcpu->arch.pio_data, size * count);
5621 		trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5622 		vcpu->arch.pio.count = 0;
5623 		return 1;
5624 	}
5625 
5626 	return 0;
5627 }
5628 
5629 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5630 				     int size, unsigned short port,
5631 				     const void *val, unsigned int count)
5632 {
5633 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5634 
5635 	memcpy(vcpu->arch.pio_data, val, size * count);
5636 	trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5637 	return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5638 }
5639 
5640 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5641 {
5642 	return kvm_x86_ops->get_segment_base(vcpu, seg);
5643 }
5644 
5645 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5646 {
5647 	kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5648 }
5649 
5650 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5651 {
5652 	if (!need_emulate_wbinvd(vcpu))
5653 		return X86EMUL_CONTINUE;
5654 
5655 	if (kvm_x86_ops->has_wbinvd_exit()) {
5656 		int cpu = get_cpu();
5657 
5658 		cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5659 		smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5660 				wbinvd_ipi, NULL, 1);
5661 		put_cpu();
5662 		cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5663 	} else
5664 		wbinvd();
5665 	return X86EMUL_CONTINUE;
5666 }
5667 
5668 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5669 {
5670 	kvm_emulate_wbinvd_noskip(vcpu);
5671 	return kvm_skip_emulated_instruction(vcpu);
5672 }
5673 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5674 
5675 
5676 
5677 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5678 {
5679 	kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5680 }
5681 
5682 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5683 			   unsigned long *dest)
5684 {
5685 	return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5686 }
5687 
5688 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5689 			   unsigned long value)
5690 {
5691 
5692 	return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5693 }
5694 
5695 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5696 {
5697 	return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5698 }
5699 
5700 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5701 {
5702 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5703 	unsigned long value;
5704 
5705 	switch (cr) {
5706 	case 0:
5707 		value = kvm_read_cr0(vcpu);
5708 		break;
5709 	case 2:
5710 		value = vcpu->arch.cr2;
5711 		break;
5712 	case 3:
5713 		value = kvm_read_cr3(vcpu);
5714 		break;
5715 	case 4:
5716 		value = kvm_read_cr4(vcpu);
5717 		break;
5718 	case 8:
5719 		value = kvm_get_cr8(vcpu);
5720 		break;
5721 	default:
5722 		kvm_err("%s: unexpected cr %u\n", __func__, cr);
5723 		return 0;
5724 	}
5725 
5726 	return value;
5727 }
5728 
5729 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5730 {
5731 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5732 	int res = 0;
5733 
5734 	switch (cr) {
5735 	case 0:
5736 		res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5737 		break;
5738 	case 2:
5739 		vcpu->arch.cr2 = val;
5740 		break;
5741 	case 3:
5742 		res = kvm_set_cr3(vcpu, val);
5743 		break;
5744 	case 4:
5745 		res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5746 		break;
5747 	case 8:
5748 		res = kvm_set_cr8(vcpu, val);
5749 		break;
5750 	default:
5751 		kvm_err("%s: unexpected cr %u\n", __func__, cr);
5752 		res = -1;
5753 	}
5754 
5755 	return res;
5756 }
5757 
5758 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5759 {
5760 	return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5761 }
5762 
5763 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5764 {
5765 	kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5766 }
5767 
5768 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5769 {
5770 	kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5771 }
5772 
5773 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5774 {
5775 	kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5776 }
5777 
5778 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5779 {
5780 	kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5781 }
5782 
5783 static unsigned long emulator_get_cached_segment_base(
5784 	struct x86_emulate_ctxt *ctxt, int seg)
5785 {
5786 	return get_segment_base(emul_to_vcpu(ctxt), seg);
5787 }
5788 
5789 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5790 				 struct desc_struct *desc, u32 *base3,
5791 				 int seg)
5792 {
5793 	struct kvm_segment var;
5794 
5795 	kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
5796 	*selector = var.selector;
5797 
5798 	if (var.unusable) {
5799 		memset(desc, 0, sizeof(*desc));
5800 		if (base3)
5801 			*base3 = 0;
5802 		return false;
5803 	}
5804 
5805 	if (var.g)
5806 		var.limit >>= 12;
5807 	set_desc_limit(desc, var.limit);
5808 	set_desc_base(desc, (unsigned long)var.base);
5809 #ifdef CONFIG_X86_64
5810 	if (base3)
5811 		*base3 = var.base >> 32;
5812 #endif
5813 	desc->type = var.type;
5814 	desc->s = var.s;
5815 	desc->dpl = var.dpl;
5816 	desc->p = var.present;
5817 	desc->avl = var.avl;
5818 	desc->l = var.l;
5819 	desc->d = var.db;
5820 	desc->g = var.g;
5821 
5822 	return true;
5823 }
5824 
5825 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5826 				 struct desc_struct *desc, u32 base3,
5827 				 int seg)
5828 {
5829 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5830 	struct kvm_segment var;
5831 
5832 	var.selector = selector;
5833 	var.base = get_desc_base(desc);
5834 #ifdef CONFIG_X86_64
5835 	var.base |= ((u64)base3) << 32;
5836 #endif
5837 	var.limit = get_desc_limit(desc);
5838 	if (desc->g)
5839 		var.limit = (var.limit << 12) | 0xfff;
5840 	var.type = desc->type;
5841 	var.dpl = desc->dpl;
5842 	var.db = desc->d;
5843 	var.s = desc->s;
5844 	var.l = desc->l;
5845 	var.g = desc->g;
5846 	var.avl = desc->avl;
5847 	var.present = desc->p;
5848 	var.unusable = !var.present;
5849 	var.padding = 0;
5850 
5851 	kvm_set_segment(vcpu, &var, seg);
5852 	return;
5853 }
5854 
5855 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5856 			    u32 msr_index, u64 *pdata)
5857 {
5858 	struct msr_data msr;
5859 	int r;
5860 
5861 	msr.index = msr_index;
5862 	msr.host_initiated = false;
5863 	r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5864 	if (r)
5865 		return r;
5866 
5867 	*pdata = msr.data;
5868 	return 0;
5869 }
5870 
5871 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5872 			    u32 msr_index, u64 data)
5873 {
5874 	struct msr_data msr;
5875 
5876 	msr.data = data;
5877 	msr.index = msr_index;
5878 	msr.host_initiated = false;
5879 	return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
5880 }
5881 
5882 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5883 {
5884 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5885 
5886 	return vcpu->arch.smbase;
5887 }
5888 
5889 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5890 {
5891 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5892 
5893 	vcpu->arch.smbase = smbase;
5894 }
5895 
5896 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5897 			      u32 pmc)
5898 {
5899 	return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
5900 }
5901 
5902 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5903 			     u32 pmc, u64 *pdata)
5904 {
5905 	return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
5906 }
5907 
5908 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5909 {
5910 	emul_to_vcpu(ctxt)->arch.halt_request = 1;
5911 }
5912 
5913 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5914 			      struct x86_instruction_info *info,
5915 			      enum x86_intercept_stage stage)
5916 {
5917 	return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5918 }
5919 
5920 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5921 			u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
5922 {
5923 	return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
5924 }
5925 
5926 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5927 {
5928 	return kvm_register_read(emul_to_vcpu(ctxt), reg);
5929 }
5930 
5931 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5932 {
5933 	kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5934 }
5935 
5936 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5937 {
5938 	kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5939 }
5940 
5941 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5942 {
5943 	return emul_to_vcpu(ctxt)->arch.hflags;
5944 }
5945 
5946 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5947 {
5948 	kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5949 }
5950 
5951 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5952 {
5953 	return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5954 }
5955 
5956 static const struct x86_emulate_ops emulate_ops = {
5957 	.read_gpr            = emulator_read_gpr,
5958 	.write_gpr           = emulator_write_gpr,
5959 	.read_std            = emulator_read_std,
5960 	.write_std           = emulator_write_std,
5961 	.read_phys           = kvm_read_guest_phys_system,
5962 	.fetch               = kvm_fetch_guest_virt,
5963 	.read_emulated       = emulator_read_emulated,
5964 	.write_emulated      = emulator_write_emulated,
5965 	.cmpxchg_emulated    = emulator_cmpxchg_emulated,
5966 	.invlpg              = emulator_invlpg,
5967 	.pio_in_emulated     = emulator_pio_in_emulated,
5968 	.pio_out_emulated    = emulator_pio_out_emulated,
5969 	.get_segment         = emulator_get_segment,
5970 	.set_segment         = emulator_set_segment,
5971 	.get_cached_segment_base = emulator_get_cached_segment_base,
5972 	.get_gdt             = emulator_get_gdt,
5973 	.get_idt	     = emulator_get_idt,
5974 	.set_gdt             = emulator_set_gdt,
5975 	.set_idt	     = emulator_set_idt,
5976 	.get_cr              = emulator_get_cr,
5977 	.set_cr              = emulator_set_cr,
5978 	.cpl                 = emulator_get_cpl,
5979 	.get_dr              = emulator_get_dr,
5980 	.set_dr              = emulator_set_dr,
5981 	.get_smbase          = emulator_get_smbase,
5982 	.set_smbase          = emulator_set_smbase,
5983 	.set_msr             = emulator_set_msr,
5984 	.get_msr             = emulator_get_msr,
5985 	.check_pmc	     = emulator_check_pmc,
5986 	.read_pmc            = emulator_read_pmc,
5987 	.halt                = emulator_halt,
5988 	.wbinvd              = emulator_wbinvd,
5989 	.fix_hypercall       = emulator_fix_hypercall,
5990 	.intercept           = emulator_intercept,
5991 	.get_cpuid           = emulator_get_cpuid,
5992 	.set_nmi_mask        = emulator_set_nmi_mask,
5993 	.get_hflags          = emulator_get_hflags,
5994 	.set_hflags          = emulator_set_hflags,
5995 	.pre_leave_smm       = emulator_pre_leave_smm,
5996 };
5997 
5998 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5999 {
6000 	u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6001 	/*
6002 	 * an sti; sti; sequence only disable interrupts for the first
6003 	 * instruction. So, if the last instruction, be it emulated or
6004 	 * not, left the system with the INT_STI flag enabled, it
6005 	 * means that the last instruction is an sti. We should not
6006 	 * leave the flag on in this case. The same goes for mov ss
6007 	 */
6008 	if (int_shadow & mask)
6009 		mask = 0;
6010 	if (unlikely(int_shadow || mask)) {
6011 		kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6012 		if (!mask)
6013 			kvm_make_request(KVM_REQ_EVENT, vcpu);
6014 	}
6015 }
6016 
6017 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6018 {
6019 	struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6020 	if (ctxt->exception.vector == PF_VECTOR)
6021 		return kvm_propagate_fault(vcpu, &ctxt->exception);
6022 
6023 	if (ctxt->exception.error_code_valid)
6024 		kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6025 				      ctxt->exception.error_code);
6026 	else
6027 		kvm_queue_exception(vcpu, ctxt->exception.vector);
6028 	return false;
6029 }
6030 
6031 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6032 {
6033 	struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6034 	int cs_db, cs_l;
6035 
6036 	kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6037 
6038 	ctxt->eflags = kvm_get_rflags(vcpu);
6039 	ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6040 
6041 	ctxt->eip = kvm_rip_read(vcpu);
6042 	ctxt->mode = (!is_protmode(vcpu))		? X86EMUL_MODE_REAL :
6043 		     (ctxt->eflags & X86_EFLAGS_VM)	? X86EMUL_MODE_VM86 :
6044 		     (cs_l && is_long_mode(vcpu))	? X86EMUL_MODE_PROT64 :
6045 		     cs_db				? X86EMUL_MODE_PROT32 :
6046 							  X86EMUL_MODE_PROT16;
6047 	BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6048 	BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6049 	BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6050 
6051 	init_decode_cache(ctxt);
6052 	vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6053 }
6054 
6055 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6056 {
6057 	struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6058 	int ret;
6059 
6060 	init_emulate_ctxt(vcpu);
6061 
6062 	ctxt->op_bytes = 2;
6063 	ctxt->ad_bytes = 2;
6064 	ctxt->_eip = ctxt->eip + inc_eip;
6065 	ret = emulate_int_real(ctxt, irq);
6066 
6067 	if (ret != X86EMUL_CONTINUE)
6068 		return EMULATE_FAIL;
6069 
6070 	ctxt->eip = ctxt->_eip;
6071 	kvm_rip_write(vcpu, ctxt->eip);
6072 	kvm_set_rflags(vcpu, ctxt->eflags);
6073 
6074 	return EMULATE_DONE;
6075 }
6076 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6077 
6078 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6079 {
6080 	int r = EMULATE_DONE;
6081 
6082 	++vcpu->stat.insn_emulation_fail;
6083 	trace_kvm_emulate_insn_failed(vcpu);
6084 
6085 	if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6086 		return EMULATE_FAIL;
6087 
6088 	if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6089 		vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6090 		vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6091 		vcpu->run->internal.ndata = 0;
6092 		r = EMULATE_USER_EXIT;
6093 	}
6094 
6095 	kvm_queue_exception(vcpu, UD_VECTOR);
6096 
6097 	return r;
6098 }
6099 
6100 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
6101 				  bool write_fault_to_shadow_pgtable,
6102 				  int emulation_type)
6103 {
6104 	gpa_t gpa = cr2;
6105 	kvm_pfn_t pfn;
6106 
6107 	if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6108 		return false;
6109 
6110 	if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6111 		return false;
6112 
6113 	if (!vcpu->arch.mmu->direct_map) {
6114 		/*
6115 		 * Write permission should be allowed since only
6116 		 * write access need to be emulated.
6117 		 */
6118 		gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6119 
6120 		/*
6121 		 * If the mapping is invalid in guest, let cpu retry
6122 		 * it to generate fault.
6123 		 */
6124 		if (gpa == UNMAPPED_GVA)
6125 			return true;
6126 	}
6127 
6128 	/*
6129 	 * Do not retry the unhandleable instruction if it faults on the
6130 	 * readonly host memory, otherwise it will goto a infinite loop:
6131 	 * retry instruction -> write #PF -> emulation fail -> retry
6132 	 * instruction -> ...
6133 	 */
6134 	pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6135 
6136 	/*
6137 	 * If the instruction failed on the error pfn, it can not be fixed,
6138 	 * report the error to userspace.
6139 	 */
6140 	if (is_error_noslot_pfn(pfn))
6141 		return false;
6142 
6143 	kvm_release_pfn_clean(pfn);
6144 
6145 	/* The instructions are well-emulated on direct mmu. */
6146 	if (vcpu->arch.mmu->direct_map) {
6147 		unsigned int indirect_shadow_pages;
6148 
6149 		spin_lock(&vcpu->kvm->mmu_lock);
6150 		indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6151 		spin_unlock(&vcpu->kvm->mmu_lock);
6152 
6153 		if (indirect_shadow_pages)
6154 			kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6155 
6156 		return true;
6157 	}
6158 
6159 	/*
6160 	 * if emulation was due to access to shadowed page table
6161 	 * and it failed try to unshadow page and re-enter the
6162 	 * guest to let CPU execute the instruction.
6163 	 */
6164 	kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6165 
6166 	/*
6167 	 * If the access faults on its page table, it can not
6168 	 * be fixed by unprotecting shadow page and it should
6169 	 * be reported to userspace.
6170 	 */
6171 	return !write_fault_to_shadow_pgtable;
6172 }
6173 
6174 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6175 			      unsigned long cr2,  int emulation_type)
6176 {
6177 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6178 	unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6179 
6180 	last_retry_eip = vcpu->arch.last_retry_eip;
6181 	last_retry_addr = vcpu->arch.last_retry_addr;
6182 
6183 	/*
6184 	 * If the emulation is caused by #PF and it is non-page_table
6185 	 * writing instruction, it means the VM-EXIT is caused by shadow
6186 	 * page protected, we can zap the shadow page and retry this
6187 	 * instruction directly.
6188 	 *
6189 	 * Note: if the guest uses a non-page-table modifying instruction
6190 	 * on the PDE that points to the instruction, then we will unmap
6191 	 * the instruction and go to an infinite loop. So, we cache the
6192 	 * last retried eip and the last fault address, if we meet the eip
6193 	 * and the address again, we can break out of the potential infinite
6194 	 * loop.
6195 	 */
6196 	vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6197 
6198 	if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6199 		return false;
6200 
6201 	if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6202 		return false;
6203 
6204 	if (x86_page_table_writing_insn(ctxt))
6205 		return false;
6206 
6207 	if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6208 		return false;
6209 
6210 	vcpu->arch.last_retry_eip = ctxt->eip;
6211 	vcpu->arch.last_retry_addr = cr2;
6212 
6213 	if (!vcpu->arch.mmu->direct_map)
6214 		gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6215 
6216 	kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6217 
6218 	return true;
6219 }
6220 
6221 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6222 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6223 
6224 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6225 {
6226 	if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6227 		/* This is a good place to trace that we are exiting SMM.  */
6228 		trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6229 
6230 		/* Process a latched INIT or SMI, if any.  */
6231 		kvm_make_request(KVM_REQ_EVENT, vcpu);
6232 	}
6233 
6234 	kvm_mmu_reset_context(vcpu);
6235 }
6236 
6237 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
6238 {
6239 	unsigned changed = vcpu->arch.hflags ^ emul_flags;
6240 
6241 	vcpu->arch.hflags = emul_flags;
6242 
6243 	if (changed & HF_SMM_MASK)
6244 		kvm_smm_changed(vcpu);
6245 }
6246 
6247 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6248 				unsigned long *db)
6249 {
6250 	u32 dr6 = 0;
6251 	int i;
6252 	u32 enable, rwlen;
6253 
6254 	enable = dr7;
6255 	rwlen = dr7 >> 16;
6256 	for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6257 		if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6258 			dr6 |= (1 << i);
6259 	return dr6;
6260 }
6261 
6262 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
6263 {
6264 	struct kvm_run *kvm_run = vcpu->run;
6265 
6266 	if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6267 		kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6268 		kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6269 		kvm_run->debug.arch.exception = DB_VECTOR;
6270 		kvm_run->exit_reason = KVM_EXIT_DEBUG;
6271 		*r = EMULATE_USER_EXIT;
6272 	} else {
6273 		kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6274 	}
6275 }
6276 
6277 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6278 {
6279 	unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6280 	int r = EMULATE_DONE;
6281 
6282 	kvm_x86_ops->skip_emulated_instruction(vcpu);
6283 
6284 	/*
6285 	 * rflags is the old, "raw" value of the flags.  The new value has
6286 	 * not been saved yet.
6287 	 *
6288 	 * This is correct even for TF set by the guest, because "the
6289 	 * processor will not generate this exception after the instruction
6290 	 * that sets the TF flag".
6291 	 */
6292 	if (unlikely(rflags & X86_EFLAGS_TF))
6293 		kvm_vcpu_do_singlestep(vcpu, &r);
6294 	return r == EMULATE_DONE;
6295 }
6296 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6297 
6298 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6299 {
6300 	if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6301 	    (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6302 		struct kvm_run *kvm_run = vcpu->run;
6303 		unsigned long eip = kvm_get_linear_rip(vcpu);
6304 		u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6305 					   vcpu->arch.guest_debug_dr7,
6306 					   vcpu->arch.eff_db);
6307 
6308 		if (dr6 != 0) {
6309 			kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6310 			kvm_run->debug.arch.pc = eip;
6311 			kvm_run->debug.arch.exception = DB_VECTOR;
6312 			kvm_run->exit_reason = KVM_EXIT_DEBUG;
6313 			*r = EMULATE_USER_EXIT;
6314 			return true;
6315 		}
6316 	}
6317 
6318 	if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6319 	    !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6320 		unsigned long eip = kvm_get_linear_rip(vcpu);
6321 		u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6322 					   vcpu->arch.dr7,
6323 					   vcpu->arch.db);
6324 
6325 		if (dr6 != 0) {
6326 			vcpu->arch.dr6 &= ~15;
6327 			vcpu->arch.dr6 |= dr6 | DR6_RTM;
6328 			kvm_queue_exception(vcpu, DB_VECTOR);
6329 			*r = EMULATE_DONE;
6330 			return true;
6331 		}
6332 	}
6333 
6334 	return false;
6335 }
6336 
6337 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6338 {
6339 	switch (ctxt->opcode_len) {
6340 	case 1:
6341 		switch (ctxt->b) {
6342 		case 0xe4:	/* IN */
6343 		case 0xe5:
6344 		case 0xec:
6345 		case 0xed:
6346 		case 0xe6:	/* OUT */
6347 		case 0xe7:
6348 		case 0xee:
6349 		case 0xef:
6350 		case 0x6c:	/* INS */
6351 		case 0x6d:
6352 		case 0x6e:	/* OUTS */
6353 		case 0x6f:
6354 			return true;
6355 		}
6356 		break;
6357 	case 2:
6358 		switch (ctxt->b) {
6359 		case 0x33:	/* RDPMC */
6360 			return true;
6361 		}
6362 		break;
6363 	}
6364 
6365 	return false;
6366 }
6367 
6368 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6369 			    unsigned long cr2,
6370 			    int emulation_type,
6371 			    void *insn,
6372 			    int insn_len)
6373 {
6374 	int r;
6375 	struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6376 	bool writeback = true;
6377 	bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6378 
6379 	vcpu->arch.l1tf_flush_l1d = true;
6380 
6381 	/*
6382 	 * Clear write_fault_to_shadow_pgtable here to ensure it is
6383 	 * never reused.
6384 	 */
6385 	vcpu->arch.write_fault_to_shadow_pgtable = false;
6386 	kvm_clear_exception_queue(vcpu);
6387 
6388 	if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6389 		init_emulate_ctxt(vcpu);
6390 
6391 		/*
6392 		 * We will reenter on the same instruction since
6393 		 * we do not set complete_userspace_io.  This does not
6394 		 * handle watchpoints yet, those would be handled in
6395 		 * the emulate_ops.
6396 		 */
6397 		if (!(emulation_type & EMULTYPE_SKIP) &&
6398 		    kvm_vcpu_check_breakpoint(vcpu, &r))
6399 			return r;
6400 
6401 		ctxt->interruptibility = 0;
6402 		ctxt->have_exception = false;
6403 		ctxt->exception.vector = -1;
6404 		ctxt->perm_ok = false;
6405 
6406 		ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6407 
6408 		r = x86_decode_insn(ctxt, insn, insn_len);
6409 
6410 		trace_kvm_emulate_insn_start(vcpu);
6411 		++vcpu->stat.insn_emulation;
6412 		if (r != EMULATION_OK)  {
6413 			if (emulation_type & EMULTYPE_TRAP_UD)
6414 				return EMULATE_FAIL;
6415 			if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6416 						emulation_type))
6417 				return EMULATE_DONE;
6418 			if (ctxt->have_exception && inject_emulated_exception(vcpu))
6419 				return EMULATE_DONE;
6420 			if (emulation_type & EMULTYPE_SKIP)
6421 				return EMULATE_FAIL;
6422 			return handle_emulation_failure(vcpu, emulation_type);
6423 		}
6424 	}
6425 
6426 	if ((emulation_type & EMULTYPE_VMWARE) &&
6427 	    !is_vmware_backdoor_opcode(ctxt))
6428 		return EMULATE_FAIL;
6429 
6430 	if (emulation_type & EMULTYPE_SKIP) {
6431 		kvm_rip_write(vcpu, ctxt->_eip);
6432 		if (ctxt->eflags & X86_EFLAGS_RF)
6433 			kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6434 		return EMULATE_DONE;
6435 	}
6436 
6437 	if (retry_instruction(ctxt, cr2, emulation_type))
6438 		return EMULATE_DONE;
6439 
6440 	/* this is needed for vmware backdoor interface to work since it
6441 	   changes registers values  during IO operation */
6442 	if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6443 		vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6444 		emulator_invalidate_register_cache(ctxt);
6445 	}
6446 
6447 restart:
6448 	/* Save the faulting GPA (cr2) in the address field */
6449 	ctxt->exception.address = cr2;
6450 
6451 	r = x86_emulate_insn(ctxt);
6452 
6453 	if (r == EMULATION_INTERCEPTED)
6454 		return EMULATE_DONE;
6455 
6456 	if (r == EMULATION_FAILED) {
6457 		if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6458 					emulation_type))
6459 			return EMULATE_DONE;
6460 
6461 		return handle_emulation_failure(vcpu, emulation_type);
6462 	}
6463 
6464 	if (ctxt->have_exception) {
6465 		r = EMULATE_DONE;
6466 		if (inject_emulated_exception(vcpu))
6467 			return r;
6468 	} else if (vcpu->arch.pio.count) {
6469 		if (!vcpu->arch.pio.in) {
6470 			/* FIXME: return into emulator if single-stepping.  */
6471 			vcpu->arch.pio.count = 0;
6472 		} else {
6473 			writeback = false;
6474 			vcpu->arch.complete_userspace_io = complete_emulated_pio;
6475 		}
6476 		r = EMULATE_USER_EXIT;
6477 	} else if (vcpu->mmio_needed) {
6478 		if (!vcpu->mmio_is_write)
6479 			writeback = false;
6480 		r = EMULATE_USER_EXIT;
6481 		vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6482 	} else if (r == EMULATION_RESTART)
6483 		goto restart;
6484 	else
6485 		r = EMULATE_DONE;
6486 
6487 	if (writeback) {
6488 		unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6489 		toggle_interruptibility(vcpu, ctxt->interruptibility);
6490 		vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6491 		kvm_rip_write(vcpu, ctxt->eip);
6492 		if (r == EMULATE_DONE && ctxt->tf)
6493 			kvm_vcpu_do_singlestep(vcpu, &r);
6494 		if (!ctxt->have_exception ||
6495 		    exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6496 			__kvm_set_rflags(vcpu, ctxt->eflags);
6497 
6498 		/*
6499 		 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6500 		 * do nothing, and it will be requested again as soon as
6501 		 * the shadow expires.  But we still need to check here,
6502 		 * because POPF has no interrupt shadow.
6503 		 */
6504 		if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6505 			kvm_make_request(KVM_REQ_EVENT, vcpu);
6506 	} else
6507 		vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6508 
6509 	return r;
6510 }
6511 
6512 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6513 {
6514 	return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6515 }
6516 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6517 
6518 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6519 					void *insn, int insn_len)
6520 {
6521 	return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6522 }
6523 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6524 
6525 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6526 			    unsigned short port)
6527 {
6528 	unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
6529 	int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6530 					    size, port, &val, 1);
6531 	/* do not return to emulator after return from userspace */
6532 	vcpu->arch.pio.count = 0;
6533 	return ret;
6534 }
6535 
6536 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6537 {
6538 	unsigned long val;
6539 
6540 	/* We should only ever be called with arch.pio.count equal to 1 */
6541 	BUG_ON(vcpu->arch.pio.count != 1);
6542 
6543 	/* For size less than 4 we merge, else we zero extend */
6544 	val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6545 					: 0;
6546 
6547 	/*
6548 	 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6549 	 * the copy and tracing
6550 	 */
6551 	emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6552 				 vcpu->arch.pio.port, &val, 1);
6553 	kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6554 
6555 	return 1;
6556 }
6557 
6558 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6559 			   unsigned short port)
6560 {
6561 	unsigned long val;
6562 	int ret;
6563 
6564 	/* For size less than 4 we merge, else we zero extend */
6565 	val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6566 
6567 	ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6568 				       &val, 1);
6569 	if (ret) {
6570 		kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6571 		return ret;
6572 	}
6573 
6574 	vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6575 
6576 	return 0;
6577 }
6578 
6579 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6580 {
6581 	int ret = kvm_skip_emulated_instruction(vcpu);
6582 
6583 	/*
6584 	 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6585 	 * KVM_EXIT_DEBUG here.
6586 	 */
6587 	if (in)
6588 		return kvm_fast_pio_in(vcpu, size, port) && ret;
6589 	else
6590 		return kvm_fast_pio_out(vcpu, size, port) && ret;
6591 }
6592 EXPORT_SYMBOL_GPL(kvm_fast_pio);
6593 
6594 static int kvmclock_cpu_down_prep(unsigned int cpu)
6595 {
6596 	__this_cpu_write(cpu_tsc_khz, 0);
6597 	return 0;
6598 }
6599 
6600 static void tsc_khz_changed(void *data)
6601 {
6602 	struct cpufreq_freqs *freq = data;
6603 	unsigned long khz = 0;
6604 
6605 	if (data)
6606 		khz = freq->new;
6607 	else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6608 		khz = cpufreq_quick_get(raw_smp_processor_id());
6609 	if (!khz)
6610 		khz = tsc_khz;
6611 	__this_cpu_write(cpu_tsc_khz, khz);
6612 }
6613 
6614 #ifdef CONFIG_X86_64
6615 static void kvm_hyperv_tsc_notifier(void)
6616 {
6617 	struct kvm *kvm;
6618 	struct kvm_vcpu *vcpu;
6619 	int cpu;
6620 
6621 	spin_lock(&kvm_lock);
6622 	list_for_each_entry(kvm, &vm_list, vm_list)
6623 		kvm_make_mclock_inprogress_request(kvm);
6624 
6625 	hyperv_stop_tsc_emulation();
6626 
6627 	/* TSC frequency always matches when on Hyper-V */
6628 	for_each_present_cpu(cpu)
6629 		per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6630 	kvm_max_guest_tsc_khz = tsc_khz;
6631 
6632 	list_for_each_entry(kvm, &vm_list, vm_list) {
6633 		struct kvm_arch *ka = &kvm->arch;
6634 
6635 		spin_lock(&ka->pvclock_gtod_sync_lock);
6636 
6637 		pvclock_update_vm_gtod_copy(kvm);
6638 
6639 		kvm_for_each_vcpu(cpu, vcpu, kvm)
6640 			kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6641 
6642 		kvm_for_each_vcpu(cpu, vcpu, kvm)
6643 			kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6644 
6645 		spin_unlock(&ka->pvclock_gtod_sync_lock);
6646 	}
6647 	spin_unlock(&kvm_lock);
6648 }
6649 #endif
6650 
6651 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6652 				     void *data)
6653 {
6654 	struct cpufreq_freqs *freq = data;
6655 	struct kvm *kvm;
6656 	struct kvm_vcpu *vcpu;
6657 	int i, send_ipi = 0;
6658 
6659 	/*
6660 	 * We allow guests to temporarily run on slowing clocks,
6661 	 * provided we notify them after, or to run on accelerating
6662 	 * clocks, provided we notify them before.  Thus time never
6663 	 * goes backwards.
6664 	 *
6665 	 * However, we have a problem.  We can't atomically update
6666 	 * the frequency of a given CPU from this function; it is
6667 	 * merely a notifier, which can be called from any CPU.
6668 	 * Changing the TSC frequency at arbitrary points in time
6669 	 * requires a recomputation of local variables related to
6670 	 * the TSC for each VCPU.  We must flag these local variables
6671 	 * to be updated and be sure the update takes place with the
6672 	 * new frequency before any guests proceed.
6673 	 *
6674 	 * Unfortunately, the combination of hotplug CPU and frequency
6675 	 * change creates an intractable locking scenario; the order
6676 	 * of when these callouts happen is undefined with respect to
6677 	 * CPU hotplug, and they can race with each other.  As such,
6678 	 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6679 	 * undefined; you can actually have a CPU frequency change take
6680 	 * place in between the computation of X and the setting of the
6681 	 * variable.  To protect against this problem, all updates of
6682 	 * the per_cpu tsc_khz variable are done in an interrupt
6683 	 * protected IPI, and all callers wishing to update the value
6684 	 * must wait for a synchronous IPI to complete (which is trivial
6685 	 * if the caller is on the CPU already).  This establishes the
6686 	 * necessary total order on variable updates.
6687 	 *
6688 	 * Note that because a guest time update may take place
6689 	 * anytime after the setting of the VCPU's request bit, the
6690 	 * correct TSC value must be set before the request.  However,
6691 	 * to ensure the update actually makes it to any guest which
6692 	 * starts running in hardware virtualization between the set
6693 	 * and the acquisition of the spinlock, we must also ping the
6694 	 * CPU after setting the request bit.
6695 	 *
6696 	 */
6697 
6698 	if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6699 		return 0;
6700 	if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6701 		return 0;
6702 
6703 	smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6704 
6705 	spin_lock(&kvm_lock);
6706 	list_for_each_entry(kvm, &vm_list, vm_list) {
6707 		kvm_for_each_vcpu(i, vcpu, kvm) {
6708 			if (vcpu->cpu != freq->cpu)
6709 				continue;
6710 			kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6711 			if (vcpu->cpu != smp_processor_id())
6712 				send_ipi = 1;
6713 		}
6714 	}
6715 	spin_unlock(&kvm_lock);
6716 
6717 	if (freq->old < freq->new && send_ipi) {
6718 		/*
6719 		 * We upscale the frequency.  Must make the guest
6720 		 * doesn't see old kvmclock values while running with
6721 		 * the new frequency, otherwise we risk the guest sees
6722 		 * time go backwards.
6723 		 *
6724 		 * In case we update the frequency for another cpu
6725 		 * (which might be in guest context) send an interrupt
6726 		 * to kick the cpu out of guest context.  Next time
6727 		 * guest context is entered kvmclock will be updated,
6728 		 * so the guest will not see stale values.
6729 		 */
6730 		smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
6731 	}
6732 	return 0;
6733 }
6734 
6735 static struct notifier_block kvmclock_cpufreq_notifier_block = {
6736 	.notifier_call  = kvmclock_cpufreq_notifier
6737 };
6738 
6739 static int kvmclock_cpu_online(unsigned int cpu)
6740 {
6741 	tsc_khz_changed(NULL);
6742 	return 0;
6743 }
6744 
6745 static void kvm_timer_init(void)
6746 {
6747 	max_tsc_khz = tsc_khz;
6748 
6749 	if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
6750 #ifdef CONFIG_CPU_FREQ
6751 		struct cpufreq_policy policy;
6752 		int cpu;
6753 
6754 		memset(&policy, 0, sizeof(policy));
6755 		cpu = get_cpu();
6756 		cpufreq_get_policy(&policy, cpu);
6757 		if (policy.cpuinfo.max_freq)
6758 			max_tsc_khz = policy.cpuinfo.max_freq;
6759 		put_cpu();
6760 #endif
6761 		cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6762 					  CPUFREQ_TRANSITION_NOTIFIER);
6763 	}
6764 	pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
6765 
6766 	cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
6767 			  kvmclock_cpu_online, kvmclock_cpu_down_prep);
6768 }
6769 
6770 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6771 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
6772 
6773 int kvm_is_in_guest(void)
6774 {
6775 	return __this_cpu_read(current_vcpu) != NULL;
6776 }
6777 
6778 static int kvm_is_user_mode(void)
6779 {
6780 	int user_mode = 3;
6781 
6782 	if (__this_cpu_read(current_vcpu))
6783 		user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
6784 
6785 	return user_mode != 0;
6786 }
6787 
6788 static unsigned long kvm_get_guest_ip(void)
6789 {
6790 	unsigned long ip = 0;
6791 
6792 	if (__this_cpu_read(current_vcpu))
6793 		ip = kvm_rip_read(__this_cpu_read(current_vcpu));
6794 
6795 	return ip;
6796 }
6797 
6798 static struct perf_guest_info_callbacks kvm_guest_cbs = {
6799 	.is_in_guest		= kvm_is_in_guest,
6800 	.is_user_mode		= kvm_is_user_mode,
6801 	.get_guest_ip		= kvm_get_guest_ip,
6802 };
6803 
6804 static void kvm_set_mmio_spte_mask(void)
6805 {
6806 	u64 mask;
6807 	int maxphyaddr = boot_cpu_data.x86_phys_bits;
6808 
6809 	/*
6810 	 * Set the reserved bits and the present bit of an paging-structure
6811 	 * entry to generate page fault with PFER.RSV = 1.
6812 	 */
6813 
6814 	/*
6815 	 * Mask the uppermost physical address bit, which would be reserved as
6816 	 * long as the supported physical address width is less than 52.
6817 	 */
6818 	mask = 1ull << 51;
6819 
6820 	/* Set the present bit. */
6821 	mask |= 1ull;
6822 
6823 	/*
6824 	 * If reserved bit is not supported, clear the present bit to disable
6825 	 * mmio page fault.
6826 	 */
6827 	if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52)
6828 		mask &= ~1ull;
6829 
6830 	kvm_mmu_set_mmio_spte_mask(mask, mask);
6831 }
6832 
6833 #ifdef CONFIG_X86_64
6834 static void pvclock_gtod_update_fn(struct work_struct *work)
6835 {
6836 	struct kvm *kvm;
6837 
6838 	struct kvm_vcpu *vcpu;
6839 	int i;
6840 
6841 	spin_lock(&kvm_lock);
6842 	list_for_each_entry(kvm, &vm_list, vm_list)
6843 		kvm_for_each_vcpu(i, vcpu, kvm)
6844 			kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
6845 	atomic_set(&kvm_guest_has_master_clock, 0);
6846 	spin_unlock(&kvm_lock);
6847 }
6848 
6849 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6850 
6851 /*
6852  * Notification about pvclock gtod data update.
6853  */
6854 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6855 			       void *priv)
6856 {
6857 	struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6858 	struct timekeeper *tk = priv;
6859 
6860 	update_pvclock_gtod(tk);
6861 
6862 	/* disable master clock if host does not trust, or does not
6863 	 * use, TSC based clocksource.
6864 	 */
6865 	if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
6866 	    atomic_read(&kvm_guest_has_master_clock) != 0)
6867 		queue_work(system_long_wq, &pvclock_gtod_work);
6868 
6869 	return 0;
6870 }
6871 
6872 static struct notifier_block pvclock_gtod_notifier = {
6873 	.notifier_call = pvclock_gtod_notify,
6874 };
6875 #endif
6876 
6877 int kvm_arch_init(void *opaque)
6878 {
6879 	int r;
6880 	struct kvm_x86_ops *ops = opaque;
6881 
6882 	if (kvm_x86_ops) {
6883 		printk(KERN_ERR "kvm: already loaded the other module\n");
6884 		r = -EEXIST;
6885 		goto out;
6886 	}
6887 
6888 	if (!ops->cpu_has_kvm_support()) {
6889 		printk(KERN_ERR "kvm: no hardware support\n");
6890 		r = -EOPNOTSUPP;
6891 		goto out;
6892 	}
6893 	if (ops->disabled_by_bios()) {
6894 		printk(KERN_ERR "kvm: disabled by bios\n");
6895 		r = -EOPNOTSUPP;
6896 		goto out;
6897 	}
6898 
6899 	/*
6900 	 * KVM explicitly assumes that the guest has an FPU and
6901 	 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
6902 	 * vCPU's FPU state as a fxregs_state struct.
6903 	 */
6904 	if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
6905 		printk(KERN_ERR "kvm: inadequate fpu\n");
6906 		r = -EOPNOTSUPP;
6907 		goto out;
6908 	}
6909 
6910 	r = -ENOMEM;
6911 	x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
6912 					  __alignof__(struct fpu), SLAB_ACCOUNT,
6913 					  NULL);
6914 	if (!x86_fpu_cache) {
6915 		printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
6916 		goto out;
6917 	}
6918 
6919 	shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6920 	if (!shared_msrs) {
6921 		printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6922 		goto out_free_x86_fpu_cache;
6923 	}
6924 
6925 	r = kvm_mmu_module_init();
6926 	if (r)
6927 		goto out_free_percpu;
6928 
6929 	kvm_set_mmio_spte_mask();
6930 
6931 	kvm_x86_ops = ops;
6932 
6933 	kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
6934 			PT_DIRTY_MASK, PT64_NX_MASK, 0,
6935 			PT_PRESENT_MASK, 0, sme_me_mask);
6936 	kvm_timer_init();
6937 
6938 	perf_register_guest_info_callbacks(&kvm_guest_cbs);
6939 
6940 	if (boot_cpu_has(X86_FEATURE_XSAVE))
6941 		host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6942 
6943 	kvm_lapic_init();
6944 #ifdef CONFIG_X86_64
6945 	pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6946 
6947 	if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
6948 		set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
6949 #endif
6950 
6951 	return 0;
6952 
6953 out_free_percpu:
6954 	free_percpu(shared_msrs);
6955 out_free_x86_fpu_cache:
6956 	kmem_cache_destroy(x86_fpu_cache);
6957 out:
6958 	return r;
6959 }
6960 
6961 void kvm_arch_exit(void)
6962 {
6963 #ifdef CONFIG_X86_64
6964 	if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
6965 		clear_hv_tscchange_cb();
6966 #endif
6967 	kvm_lapic_exit();
6968 	perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6969 
6970 	if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6971 		cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6972 					    CPUFREQ_TRANSITION_NOTIFIER);
6973 	cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
6974 #ifdef CONFIG_X86_64
6975 	pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6976 #endif
6977 	kvm_x86_ops = NULL;
6978 	kvm_mmu_module_exit();
6979 	free_percpu(shared_msrs);
6980 	kmem_cache_destroy(x86_fpu_cache);
6981 }
6982 
6983 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
6984 {
6985 	++vcpu->stat.halt_exits;
6986 	if (lapic_in_kernel(vcpu)) {
6987 		vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
6988 		return 1;
6989 	} else {
6990 		vcpu->run->exit_reason = KVM_EXIT_HLT;
6991 		return 0;
6992 	}
6993 }
6994 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6995 
6996 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6997 {
6998 	int ret = kvm_skip_emulated_instruction(vcpu);
6999 	/*
7000 	 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7001 	 * KVM_EXIT_DEBUG here.
7002 	 */
7003 	return kvm_vcpu_halt(vcpu) && ret;
7004 }
7005 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7006 
7007 #ifdef CONFIG_X86_64
7008 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7009 			        unsigned long clock_type)
7010 {
7011 	struct kvm_clock_pairing clock_pairing;
7012 	struct timespec64 ts;
7013 	u64 cycle;
7014 	int ret;
7015 
7016 	if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7017 		return -KVM_EOPNOTSUPP;
7018 
7019 	if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7020 		return -KVM_EOPNOTSUPP;
7021 
7022 	clock_pairing.sec = ts.tv_sec;
7023 	clock_pairing.nsec = ts.tv_nsec;
7024 	clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7025 	clock_pairing.flags = 0;
7026 	memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7027 
7028 	ret = 0;
7029 	if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7030 			    sizeof(struct kvm_clock_pairing)))
7031 		ret = -KVM_EFAULT;
7032 
7033 	return ret;
7034 }
7035 #endif
7036 
7037 /*
7038  * kvm_pv_kick_cpu_op:  Kick a vcpu.
7039  *
7040  * @apicid - apicid of vcpu to be kicked.
7041  */
7042 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7043 {
7044 	struct kvm_lapic_irq lapic_irq;
7045 
7046 	lapic_irq.shorthand = 0;
7047 	lapic_irq.dest_mode = 0;
7048 	lapic_irq.level = 0;
7049 	lapic_irq.dest_id = apicid;
7050 	lapic_irq.msi_redir_hint = false;
7051 
7052 	lapic_irq.delivery_mode = APIC_DM_REMRD;
7053 	kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7054 }
7055 
7056 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7057 {
7058 	vcpu->arch.apicv_active = false;
7059 	kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7060 }
7061 
7062 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7063 {
7064 	unsigned long nr, a0, a1, a2, a3, ret;
7065 	int op_64_bit;
7066 
7067 	if (kvm_hv_hypercall_enabled(vcpu->kvm))
7068 		return kvm_hv_hypercall(vcpu);
7069 
7070 	nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
7071 	a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
7072 	a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
7073 	a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
7074 	a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
7075 
7076 	trace_kvm_hypercall(nr, a0, a1, a2, a3);
7077 
7078 	op_64_bit = is_64_bit_mode(vcpu);
7079 	if (!op_64_bit) {
7080 		nr &= 0xFFFFFFFF;
7081 		a0 &= 0xFFFFFFFF;
7082 		a1 &= 0xFFFFFFFF;
7083 		a2 &= 0xFFFFFFFF;
7084 		a3 &= 0xFFFFFFFF;
7085 	}
7086 
7087 	if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7088 		ret = -KVM_EPERM;
7089 		goto out;
7090 	}
7091 
7092 	switch (nr) {
7093 	case KVM_HC_VAPIC_POLL_IRQ:
7094 		ret = 0;
7095 		break;
7096 	case KVM_HC_KICK_CPU:
7097 		kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7098 		ret = 0;
7099 		break;
7100 #ifdef CONFIG_X86_64
7101 	case KVM_HC_CLOCK_PAIRING:
7102 		ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7103 		break;
7104 #endif
7105 	case KVM_HC_SEND_IPI:
7106 		ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7107 		break;
7108 	default:
7109 		ret = -KVM_ENOSYS;
7110 		break;
7111 	}
7112 out:
7113 	if (!op_64_bit)
7114 		ret = (u32)ret;
7115 	kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
7116 
7117 	++vcpu->stat.hypercalls;
7118 	return kvm_skip_emulated_instruction(vcpu);
7119 }
7120 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7121 
7122 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7123 {
7124 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7125 	char instruction[3];
7126 	unsigned long rip = kvm_rip_read(vcpu);
7127 
7128 	kvm_x86_ops->patch_hypercall(vcpu, instruction);
7129 
7130 	return emulator_write_emulated(ctxt, rip, instruction, 3,
7131 		&ctxt->exception);
7132 }
7133 
7134 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7135 {
7136 	return vcpu->run->request_interrupt_window &&
7137 		likely(!pic_in_kernel(vcpu->kvm));
7138 }
7139 
7140 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7141 {
7142 	struct kvm_run *kvm_run = vcpu->run;
7143 
7144 	kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7145 	kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7146 	kvm_run->cr8 = kvm_get_cr8(vcpu);
7147 	kvm_run->apic_base = kvm_get_apic_base(vcpu);
7148 	kvm_run->ready_for_interrupt_injection =
7149 		pic_in_kernel(vcpu->kvm) ||
7150 		kvm_vcpu_ready_for_interrupt_injection(vcpu);
7151 }
7152 
7153 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7154 {
7155 	int max_irr, tpr;
7156 
7157 	if (!kvm_x86_ops->update_cr8_intercept)
7158 		return;
7159 
7160 	if (!lapic_in_kernel(vcpu))
7161 		return;
7162 
7163 	if (vcpu->arch.apicv_active)
7164 		return;
7165 
7166 	if (!vcpu->arch.apic->vapic_addr)
7167 		max_irr = kvm_lapic_find_highest_irr(vcpu);
7168 	else
7169 		max_irr = -1;
7170 
7171 	if (max_irr != -1)
7172 		max_irr >>= 4;
7173 
7174 	tpr = kvm_lapic_get_cr8(vcpu);
7175 
7176 	kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7177 }
7178 
7179 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7180 {
7181 	int r;
7182 
7183 	/* try to reinject previous events if any */
7184 
7185 	if (vcpu->arch.exception.injected)
7186 		kvm_x86_ops->queue_exception(vcpu);
7187 	/*
7188 	 * Do not inject an NMI or interrupt if there is a pending
7189 	 * exception.  Exceptions and interrupts are recognized at
7190 	 * instruction boundaries, i.e. the start of an instruction.
7191 	 * Trap-like exceptions, e.g. #DB, have higher priority than
7192 	 * NMIs and interrupts, i.e. traps are recognized before an
7193 	 * NMI/interrupt that's pending on the same instruction.
7194 	 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7195 	 * priority, but are only generated (pended) during instruction
7196 	 * execution, i.e. a pending fault-like exception means the
7197 	 * fault occurred on the *previous* instruction and must be
7198 	 * serviced prior to recognizing any new events in order to
7199 	 * fully complete the previous instruction.
7200 	 */
7201 	else if (!vcpu->arch.exception.pending) {
7202 		if (vcpu->arch.nmi_injected)
7203 			kvm_x86_ops->set_nmi(vcpu);
7204 		else if (vcpu->arch.interrupt.injected)
7205 			kvm_x86_ops->set_irq(vcpu);
7206 	}
7207 
7208 	/*
7209 	 * Call check_nested_events() even if we reinjected a previous event
7210 	 * in order for caller to determine if it should require immediate-exit
7211 	 * from L2 to L1 due to pending L1 events which require exit
7212 	 * from L2 to L1.
7213 	 */
7214 	if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7215 		r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7216 		if (r != 0)
7217 			return r;
7218 	}
7219 
7220 	/* try to inject new event if pending */
7221 	if (vcpu->arch.exception.pending) {
7222 		trace_kvm_inj_exception(vcpu->arch.exception.nr,
7223 					vcpu->arch.exception.has_error_code,
7224 					vcpu->arch.exception.error_code);
7225 
7226 		WARN_ON_ONCE(vcpu->arch.exception.injected);
7227 		vcpu->arch.exception.pending = false;
7228 		vcpu->arch.exception.injected = true;
7229 
7230 		if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7231 			__kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7232 					     X86_EFLAGS_RF);
7233 
7234 		if (vcpu->arch.exception.nr == DB_VECTOR) {
7235 			/*
7236 			 * This code assumes that nSVM doesn't use
7237 			 * check_nested_events(). If it does, the
7238 			 * DR6/DR7 changes should happen before L1
7239 			 * gets a #VMEXIT for an intercepted #DB in
7240 			 * L2.  (Under VMX, on the other hand, the
7241 			 * DR6/DR7 changes should not happen in the
7242 			 * event of a VM-exit to L1 for an intercepted
7243 			 * #DB in L2.)
7244 			 */
7245 			kvm_deliver_exception_payload(vcpu);
7246 			if (vcpu->arch.dr7 & DR7_GD) {
7247 				vcpu->arch.dr7 &= ~DR7_GD;
7248 				kvm_update_dr7(vcpu);
7249 			}
7250 		}
7251 
7252 		kvm_x86_ops->queue_exception(vcpu);
7253 	}
7254 
7255 	/* Don't consider new event if we re-injected an event */
7256 	if (kvm_event_needs_reinjection(vcpu))
7257 		return 0;
7258 
7259 	if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7260 	    kvm_x86_ops->smi_allowed(vcpu)) {
7261 		vcpu->arch.smi_pending = false;
7262 		++vcpu->arch.smi_count;
7263 		enter_smm(vcpu);
7264 	} else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7265 		--vcpu->arch.nmi_pending;
7266 		vcpu->arch.nmi_injected = true;
7267 		kvm_x86_ops->set_nmi(vcpu);
7268 	} else if (kvm_cpu_has_injectable_intr(vcpu)) {
7269 		/*
7270 		 * Because interrupts can be injected asynchronously, we are
7271 		 * calling check_nested_events again here to avoid a race condition.
7272 		 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7273 		 * proposal and current concerns.  Perhaps we should be setting
7274 		 * KVM_REQ_EVENT only on certain events and not unconditionally?
7275 		 */
7276 		if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7277 			r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7278 			if (r != 0)
7279 				return r;
7280 		}
7281 		if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7282 			kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7283 					    false);
7284 			kvm_x86_ops->set_irq(vcpu);
7285 		}
7286 	}
7287 
7288 	return 0;
7289 }
7290 
7291 static void process_nmi(struct kvm_vcpu *vcpu)
7292 {
7293 	unsigned limit = 2;
7294 
7295 	/*
7296 	 * x86 is limited to one NMI running, and one NMI pending after it.
7297 	 * If an NMI is already in progress, limit further NMIs to just one.
7298 	 * Otherwise, allow two (and we'll inject the first one immediately).
7299 	 */
7300 	if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7301 		limit = 1;
7302 
7303 	vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7304 	vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7305 	kvm_make_request(KVM_REQ_EVENT, vcpu);
7306 }
7307 
7308 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7309 {
7310 	u32 flags = 0;
7311 	flags |= seg->g       << 23;
7312 	flags |= seg->db      << 22;
7313 	flags |= seg->l       << 21;
7314 	flags |= seg->avl     << 20;
7315 	flags |= seg->present << 15;
7316 	flags |= seg->dpl     << 13;
7317 	flags |= seg->s       << 12;
7318 	flags |= seg->type    << 8;
7319 	return flags;
7320 }
7321 
7322 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7323 {
7324 	struct kvm_segment seg;
7325 	int offset;
7326 
7327 	kvm_get_segment(vcpu, &seg, n);
7328 	put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7329 
7330 	if (n < 3)
7331 		offset = 0x7f84 + n * 12;
7332 	else
7333 		offset = 0x7f2c + (n - 3) * 12;
7334 
7335 	put_smstate(u32, buf, offset + 8, seg.base);
7336 	put_smstate(u32, buf, offset + 4, seg.limit);
7337 	put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7338 }
7339 
7340 #ifdef CONFIG_X86_64
7341 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7342 {
7343 	struct kvm_segment seg;
7344 	int offset;
7345 	u16 flags;
7346 
7347 	kvm_get_segment(vcpu, &seg, n);
7348 	offset = 0x7e00 + n * 16;
7349 
7350 	flags = enter_smm_get_segment_flags(&seg) >> 8;
7351 	put_smstate(u16, buf, offset, seg.selector);
7352 	put_smstate(u16, buf, offset + 2, flags);
7353 	put_smstate(u32, buf, offset + 4, seg.limit);
7354 	put_smstate(u64, buf, offset + 8, seg.base);
7355 }
7356 #endif
7357 
7358 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7359 {
7360 	struct desc_ptr dt;
7361 	struct kvm_segment seg;
7362 	unsigned long val;
7363 	int i;
7364 
7365 	put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7366 	put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7367 	put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7368 	put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7369 
7370 	for (i = 0; i < 8; i++)
7371 		put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7372 
7373 	kvm_get_dr(vcpu, 6, &val);
7374 	put_smstate(u32, buf, 0x7fcc, (u32)val);
7375 	kvm_get_dr(vcpu, 7, &val);
7376 	put_smstate(u32, buf, 0x7fc8, (u32)val);
7377 
7378 	kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7379 	put_smstate(u32, buf, 0x7fc4, seg.selector);
7380 	put_smstate(u32, buf, 0x7f64, seg.base);
7381 	put_smstate(u32, buf, 0x7f60, seg.limit);
7382 	put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7383 
7384 	kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7385 	put_smstate(u32, buf, 0x7fc0, seg.selector);
7386 	put_smstate(u32, buf, 0x7f80, seg.base);
7387 	put_smstate(u32, buf, 0x7f7c, seg.limit);
7388 	put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7389 
7390 	kvm_x86_ops->get_gdt(vcpu, &dt);
7391 	put_smstate(u32, buf, 0x7f74, dt.address);
7392 	put_smstate(u32, buf, 0x7f70, dt.size);
7393 
7394 	kvm_x86_ops->get_idt(vcpu, &dt);
7395 	put_smstate(u32, buf, 0x7f58, dt.address);
7396 	put_smstate(u32, buf, 0x7f54, dt.size);
7397 
7398 	for (i = 0; i < 6; i++)
7399 		enter_smm_save_seg_32(vcpu, buf, i);
7400 
7401 	put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7402 
7403 	/* revision id */
7404 	put_smstate(u32, buf, 0x7efc, 0x00020000);
7405 	put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7406 }
7407 
7408 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7409 {
7410 #ifdef CONFIG_X86_64
7411 	struct desc_ptr dt;
7412 	struct kvm_segment seg;
7413 	unsigned long val;
7414 	int i;
7415 
7416 	for (i = 0; i < 16; i++)
7417 		put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7418 
7419 	put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7420 	put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7421 
7422 	kvm_get_dr(vcpu, 6, &val);
7423 	put_smstate(u64, buf, 0x7f68, val);
7424 	kvm_get_dr(vcpu, 7, &val);
7425 	put_smstate(u64, buf, 0x7f60, val);
7426 
7427 	put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7428 	put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7429 	put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7430 
7431 	put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7432 
7433 	/* revision id */
7434 	put_smstate(u32, buf, 0x7efc, 0x00020064);
7435 
7436 	put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7437 
7438 	kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7439 	put_smstate(u16, buf, 0x7e90, seg.selector);
7440 	put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7441 	put_smstate(u32, buf, 0x7e94, seg.limit);
7442 	put_smstate(u64, buf, 0x7e98, seg.base);
7443 
7444 	kvm_x86_ops->get_idt(vcpu, &dt);
7445 	put_smstate(u32, buf, 0x7e84, dt.size);
7446 	put_smstate(u64, buf, 0x7e88, dt.address);
7447 
7448 	kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7449 	put_smstate(u16, buf, 0x7e70, seg.selector);
7450 	put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7451 	put_smstate(u32, buf, 0x7e74, seg.limit);
7452 	put_smstate(u64, buf, 0x7e78, seg.base);
7453 
7454 	kvm_x86_ops->get_gdt(vcpu, &dt);
7455 	put_smstate(u32, buf, 0x7e64, dt.size);
7456 	put_smstate(u64, buf, 0x7e68, dt.address);
7457 
7458 	for (i = 0; i < 6; i++)
7459 		enter_smm_save_seg_64(vcpu, buf, i);
7460 #else
7461 	WARN_ON_ONCE(1);
7462 #endif
7463 }
7464 
7465 static void enter_smm(struct kvm_vcpu *vcpu)
7466 {
7467 	struct kvm_segment cs, ds;
7468 	struct desc_ptr dt;
7469 	char buf[512];
7470 	u32 cr0;
7471 
7472 	trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7473 	memset(buf, 0, 512);
7474 	if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7475 		enter_smm_save_state_64(vcpu, buf);
7476 	else
7477 		enter_smm_save_state_32(vcpu, buf);
7478 
7479 	/*
7480 	 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7481 	 * vCPU state (e.g. leave guest mode) after we've saved the state into
7482 	 * the SMM state-save area.
7483 	 */
7484 	kvm_x86_ops->pre_enter_smm(vcpu, buf);
7485 
7486 	vcpu->arch.hflags |= HF_SMM_MASK;
7487 	kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7488 
7489 	if (kvm_x86_ops->get_nmi_mask(vcpu))
7490 		vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7491 	else
7492 		kvm_x86_ops->set_nmi_mask(vcpu, true);
7493 
7494 	kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7495 	kvm_rip_write(vcpu, 0x8000);
7496 
7497 	cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7498 	kvm_x86_ops->set_cr0(vcpu, cr0);
7499 	vcpu->arch.cr0 = cr0;
7500 
7501 	kvm_x86_ops->set_cr4(vcpu, 0);
7502 
7503 	/* Undocumented: IDT limit is set to zero on entry to SMM.  */
7504 	dt.address = dt.size = 0;
7505 	kvm_x86_ops->set_idt(vcpu, &dt);
7506 
7507 	__kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7508 
7509 	cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7510 	cs.base = vcpu->arch.smbase;
7511 
7512 	ds.selector = 0;
7513 	ds.base = 0;
7514 
7515 	cs.limit    = ds.limit = 0xffffffff;
7516 	cs.type     = ds.type = 0x3;
7517 	cs.dpl      = ds.dpl = 0;
7518 	cs.db       = ds.db = 0;
7519 	cs.s        = ds.s = 1;
7520 	cs.l        = ds.l = 0;
7521 	cs.g        = ds.g = 1;
7522 	cs.avl      = ds.avl = 0;
7523 	cs.present  = ds.present = 1;
7524 	cs.unusable = ds.unusable = 0;
7525 	cs.padding  = ds.padding = 0;
7526 
7527 	kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7528 	kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7529 	kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7530 	kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7531 	kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7532 	kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7533 
7534 	if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7535 		kvm_x86_ops->set_efer(vcpu, 0);
7536 
7537 	kvm_update_cpuid(vcpu);
7538 	kvm_mmu_reset_context(vcpu);
7539 }
7540 
7541 static void process_smi(struct kvm_vcpu *vcpu)
7542 {
7543 	vcpu->arch.smi_pending = true;
7544 	kvm_make_request(KVM_REQ_EVENT, vcpu);
7545 }
7546 
7547 void kvm_make_scan_ioapic_request(struct kvm *kvm)
7548 {
7549 	kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7550 }
7551 
7552 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
7553 {
7554 	if (!kvm_apic_present(vcpu))
7555 		return;
7556 
7557 	bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
7558 
7559 	if (irqchip_split(vcpu->kvm))
7560 		kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
7561 	else {
7562 		if (vcpu->arch.apicv_active)
7563 			kvm_x86_ops->sync_pir_to_irr(vcpu);
7564 		if (ioapic_in_kernel(vcpu->kvm))
7565 			kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
7566 	}
7567 
7568 	if (is_guest_mode(vcpu))
7569 		vcpu->arch.load_eoi_exitmap_pending = true;
7570 	else
7571 		kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7572 }
7573 
7574 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7575 {
7576 	u64 eoi_exit_bitmap[4];
7577 
7578 	if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7579 		return;
7580 
7581 	bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7582 		  vcpu_to_synic(vcpu)->vec_bitmap, 256);
7583 	kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
7584 }
7585 
7586 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7587 		unsigned long start, unsigned long end,
7588 		bool blockable)
7589 {
7590 	unsigned long apic_address;
7591 
7592 	/*
7593 	 * The physical address of apic access page is stored in the VMCS.
7594 	 * Update it when it becomes invalid.
7595 	 */
7596 	apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7597 	if (start <= apic_address && apic_address < end)
7598 		kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7599 
7600 	return 0;
7601 }
7602 
7603 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7604 {
7605 	struct page *page = NULL;
7606 
7607 	if (!lapic_in_kernel(vcpu))
7608 		return;
7609 
7610 	if (!kvm_x86_ops->set_apic_access_page_addr)
7611 		return;
7612 
7613 	page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7614 	if (is_error_page(page))
7615 		return;
7616 	kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7617 
7618 	/*
7619 	 * Do not pin apic access page in memory, the MMU notifier
7620 	 * will call us again if it is migrated or swapped out.
7621 	 */
7622 	put_page(page);
7623 }
7624 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7625 
7626 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7627 {
7628 	smp_send_reschedule(vcpu->cpu);
7629 }
7630 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7631 
7632 /*
7633  * Returns 1 to let vcpu_run() continue the guest execution loop without
7634  * exiting to the userspace.  Otherwise, the value will be returned to the
7635  * userspace.
7636  */
7637 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
7638 {
7639 	int r;
7640 	bool req_int_win =
7641 		dm_request_for_irq_injection(vcpu) &&
7642 		kvm_cpu_accept_dm_intr(vcpu);
7643 
7644 	bool req_immediate_exit = false;
7645 
7646 	if (kvm_request_pending(vcpu)) {
7647 		if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7648 			kvm_x86_ops->get_vmcs12_pages(vcpu);
7649 		if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
7650 			kvm_mmu_unload(vcpu);
7651 		if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
7652 			__kvm_migrate_timers(vcpu);
7653 		if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7654 			kvm_gen_update_masterclock(vcpu->kvm);
7655 		if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7656 			kvm_gen_kvmclock_update(vcpu);
7657 		if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7658 			r = kvm_guest_time_update(vcpu);
7659 			if (unlikely(r))
7660 				goto out;
7661 		}
7662 		if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
7663 			kvm_mmu_sync_roots(vcpu);
7664 		if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7665 			kvm_mmu_load_cr3(vcpu);
7666 		if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
7667 			kvm_vcpu_flush_tlb(vcpu, true);
7668 		if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
7669 			vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
7670 			r = 0;
7671 			goto out;
7672 		}
7673 		if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
7674 			vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7675 			vcpu->mmio_needed = 0;
7676 			r = 0;
7677 			goto out;
7678 		}
7679 		if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7680 			/* Page is swapped out. Do synthetic halt */
7681 			vcpu->arch.apf.halted = true;
7682 			r = 1;
7683 			goto out;
7684 		}
7685 		if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7686 			record_steal_time(vcpu);
7687 		if (kvm_check_request(KVM_REQ_SMI, vcpu))
7688 			process_smi(vcpu);
7689 		if (kvm_check_request(KVM_REQ_NMI, vcpu))
7690 			process_nmi(vcpu);
7691 		if (kvm_check_request(KVM_REQ_PMU, vcpu))
7692 			kvm_pmu_handle_event(vcpu);
7693 		if (kvm_check_request(KVM_REQ_PMI, vcpu))
7694 			kvm_pmu_deliver_pmi(vcpu);
7695 		if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7696 			BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7697 			if (test_bit(vcpu->arch.pending_ioapic_eoi,
7698 				     vcpu->arch.ioapic_handled_vectors)) {
7699 				vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7700 				vcpu->run->eoi.vector =
7701 						vcpu->arch.pending_ioapic_eoi;
7702 				r = 0;
7703 				goto out;
7704 			}
7705 		}
7706 		if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7707 			vcpu_scan_ioapic(vcpu);
7708 		if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7709 			vcpu_load_eoi_exitmap(vcpu);
7710 		if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7711 			kvm_vcpu_reload_apic_access_page(vcpu);
7712 		if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7713 			vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7714 			vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7715 			r = 0;
7716 			goto out;
7717 		}
7718 		if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7719 			vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7720 			vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7721 			r = 0;
7722 			goto out;
7723 		}
7724 		if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7725 			vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7726 			vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7727 			r = 0;
7728 			goto out;
7729 		}
7730 
7731 		/*
7732 		 * KVM_REQ_HV_STIMER has to be processed after
7733 		 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7734 		 * depend on the guest clock being up-to-date
7735 		 */
7736 		if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7737 			kvm_hv_process_stimers(vcpu);
7738 	}
7739 
7740 	if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
7741 		++vcpu->stat.req_event;
7742 		kvm_apic_accept_events(vcpu);
7743 		if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7744 			r = 1;
7745 			goto out;
7746 		}
7747 
7748 		if (inject_pending_event(vcpu, req_int_win) != 0)
7749 			req_immediate_exit = true;
7750 		else {
7751 			/* Enable SMI/NMI/IRQ window open exits if needed.
7752 			 *
7753 			 * SMIs have three cases:
7754 			 * 1) They can be nested, and then there is nothing to
7755 			 *    do here because RSM will cause a vmexit anyway.
7756 			 * 2) There is an ISA-specific reason why SMI cannot be
7757 			 *    injected, and the moment when this changes can be
7758 			 *    intercepted.
7759 			 * 3) Or the SMI can be pending because
7760 			 *    inject_pending_event has completed the injection
7761 			 *    of an IRQ or NMI from the previous vmexit, and
7762 			 *    then we request an immediate exit to inject the
7763 			 *    SMI.
7764 			 */
7765 			if (vcpu->arch.smi_pending && !is_smm(vcpu))
7766 				if (!kvm_x86_ops->enable_smi_window(vcpu))
7767 					req_immediate_exit = true;
7768 			if (vcpu->arch.nmi_pending)
7769 				kvm_x86_ops->enable_nmi_window(vcpu);
7770 			if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7771 				kvm_x86_ops->enable_irq_window(vcpu);
7772 			WARN_ON(vcpu->arch.exception.pending);
7773 		}
7774 
7775 		if (kvm_lapic_enabled(vcpu)) {
7776 			update_cr8_intercept(vcpu);
7777 			kvm_lapic_sync_to_vapic(vcpu);
7778 		}
7779 	}
7780 
7781 	r = kvm_mmu_reload(vcpu);
7782 	if (unlikely(r)) {
7783 		goto cancel_injection;
7784 	}
7785 
7786 	preempt_disable();
7787 
7788 	kvm_x86_ops->prepare_guest_switch(vcpu);
7789 
7790 	/*
7791 	 * Disable IRQs before setting IN_GUEST_MODE.  Posted interrupt
7792 	 * IPI are then delayed after guest entry, which ensures that they
7793 	 * result in virtual interrupt delivery.
7794 	 */
7795 	local_irq_disable();
7796 	vcpu->mode = IN_GUEST_MODE;
7797 
7798 	srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7799 
7800 	/*
7801 	 * 1) We should set ->mode before checking ->requests.  Please see
7802 	 * the comment in kvm_vcpu_exiting_guest_mode().
7803 	 *
7804 	 * 2) For APICv, we should set ->mode before checking PID.ON. This
7805 	 * pairs with the memory barrier implicit in pi_test_and_set_on
7806 	 * (see vmx_deliver_posted_interrupt).
7807 	 *
7808 	 * 3) This also orders the write to mode from any reads to the page
7809 	 * tables done while the VCPU is running.  Please see the comment
7810 	 * in kvm_flush_remote_tlbs.
7811 	 */
7812 	smp_mb__after_srcu_read_unlock();
7813 
7814 	/*
7815 	 * This handles the case where a posted interrupt was
7816 	 * notified with kvm_vcpu_kick.
7817 	 */
7818 	if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7819 		kvm_x86_ops->sync_pir_to_irr(vcpu);
7820 
7821 	if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
7822 	    || need_resched() || signal_pending(current)) {
7823 		vcpu->mode = OUTSIDE_GUEST_MODE;
7824 		smp_wmb();
7825 		local_irq_enable();
7826 		preempt_enable();
7827 		vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7828 		r = 1;
7829 		goto cancel_injection;
7830 	}
7831 
7832 	kvm_load_guest_xcr0(vcpu);
7833 
7834 	if (req_immediate_exit) {
7835 		kvm_make_request(KVM_REQ_EVENT, vcpu);
7836 		kvm_x86_ops->request_immediate_exit(vcpu);
7837 	}
7838 
7839 	trace_kvm_entry(vcpu->vcpu_id);
7840 	if (lapic_timer_advance_ns)
7841 		wait_lapic_expire(vcpu);
7842 	guest_enter_irqoff();
7843 
7844 	if (unlikely(vcpu->arch.switch_db_regs)) {
7845 		set_debugreg(0, 7);
7846 		set_debugreg(vcpu->arch.eff_db[0], 0);
7847 		set_debugreg(vcpu->arch.eff_db[1], 1);
7848 		set_debugreg(vcpu->arch.eff_db[2], 2);
7849 		set_debugreg(vcpu->arch.eff_db[3], 3);
7850 		set_debugreg(vcpu->arch.dr6, 6);
7851 		vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7852 	}
7853 
7854 	kvm_x86_ops->run(vcpu);
7855 
7856 	/*
7857 	 * Do this here before restoring debug registers on the host.  And
7858 	 * since we do this before handling the vmexit, a DR access vmexit
7859 	 * can (a) read the correct value of the debug registers, (b) set
7860 	 * KVM_DEBUGREG_WONT_EXIT again.
7861 	 */
7862 	if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
7863 		WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7864 		kvm_x86_ops->sync_dirty_debug_regs(vcpu);
7865 		kvm_update_dr0123(vcpu);
7866 		kvm_update_dr6(vcpu);
7867 		kvm_update_dr7(vcpu);
7868 		vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
7869 	}
7870 
7871 	/*
7872 	 * If the guest has used debug registers, at least dr7
7873 	 * will be disabled while returning to the host.
7874 	 * If we don't have active breakpoints in the host, we don't
7875 	 * care about the messed up debug address registers. But if
7876 	 * we have some of them active, restore the old state.
7877 	 */
7878 	if (hw_breakpoint_active())
7879 		hw_breakpoint_restore();
7880 
7881 	vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
7882 
7883 	vcpu->mode = OUTSIDE_GUEST_MODE;
7884 	smp_wmb();
7885 
7886 	kvm_put_guest_xcr0(vcpu);
7887 
7888 	kvm_before_interrupt(vcpu);
7889 	kvm_x86_ops->handle_external_intr(vcpu);
7890 	kvm_after_interrupt(vcpu);
7891 
7892 	++vcpu->stat.exits;
7893 
7894 	guest_exit_irqoff();
7895 
7896 	local_irq_enable();
7897 	preempt_enable();
7898 
7899 	vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7900 
7901 	/*
7902 	 * Profile KVM exit RIPs:
7903 	 */
7904 	if (unlikely(prof_on == KVM_PROFILING)) {
7905 		unsigned long rip = kvm_rip_read(vcpu);
7906 		profile_hit(KVM_PROFILING, (void *)rip);
7907 	}
7908 
7909 	if (unlikely(vcpu->arch.tsc_always_catchup))
7910 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7911 
7912 	if (vcpu->arch.apic_attention)
7913 		kvm_lapic_sync_from_vapic(vcpu);
7914 
7915 	vcpu->arch.gpa_available = false;
7916 	r = kvm_x86_ops->handle_exit(vcpu);
7917 	return r;
7918 
7919 cancel_injection:
7920 	kvm_x86_ops->cancel_injection(vcpu);
7921 	if (unlikely(vcpu->arch.apic_attention))
7922 		kvm_lapic_sync_from_vapic(vcpu);
7923 out:
7924 	return r;
7925 }
7926 
7927 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7928 {
7929 	if (!kvm_arch_vcpu_runnable(vcpu) &&
7930 	    (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
7931 		srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7932 		kvm_vcpu_block(vcpu);
7933 		vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7934 
7935 		if (kvm_x86_ops->post_block)
7936 			kvm_x86_ops->post_block(vcpu);
7937 
7938 		if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7939 			return 1;
7940 	}
7941 
7942 	kvm_apic_accept_events(vcpu);
7943 	switch(vcpu->arch.mp_state) {
7944 	case KVM_MP_STATE_HALTED:
7945 		vcpu->arch.pv.pv_unhalted = false;
7946 		vcpu->arch.mp_state =
7947 			KVM_MP_STATE_RUNNABLE;
7948 		/* fall through */
7949 	case KVM_MP_STATE_RUNNABLE:
7950 		vcpu->arch.apf.halted = false;
7951 		break;
7952 	case KVM_MP_STATE_INIT_RECEIVED:
7953 		break;
7954 	default:
7955 		return -EINTR;
7956 		break;
7957 	}
7958 	return 1;
7959 }
7960 
7961 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7962 {
7963 	if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7964 		kvm_x86_ops->check_nested_events(vcpu, false);
7965 
7966 	return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7967 		!vcpu->arch.apf.halted);
7968 }
7969 
7970 static int vcpu_run(struct kvm_vcpu *vcpu)
7971 {
7972 	int r;
7973 	struct kvm *kvm = vcpu->kvm;
7974 
7975 	vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
7976 	vcpu->arch.l1tf_flush_l1d = true;
7977 
7978 	for (;;) {
7979 		if (kvm_vcpu_running(vcpu)) {
7980 			r = vcpu_enter_guest(vcpu);
7981 		} else {
7982 			r = vcpu_block(kvm, vcpu);
7983 		}
7984 
7985 		if (r <= 0)
7986 			break;
7987 
7988 		kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
7989 		if (kvm_cpu_has_pending_timer(vcpu))
7990 			kvm_inject_pending_timer_irqs(vcpu);
7991 
7992 		if (dm_request_for_irq_injection(vcpu) &&
7993 			kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
7994 			r = 0;
7995 			vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
7996 			++vcpu->stat.request_irq_exits;
7997 			break;
7998 		}
7999 
8000 		kvm_check_async_pf_completion(vcpu);
8001 
8002 		if (signal_pending(current)) {
8003 			r = -EINTR;
8004 			vcpu->run->exit_reason = KVM_EXIT_INTR;
8005 			++vcpu->stat.signal_exits;
8006 			break;
8007 		}
8008 		if (need_resched()) {
8009 			srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8010 			cond_resched();
8011 			vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8012 		}
8013 	}
8014 
8015 	srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8016 
8017 	return r;
8018 }
8019 
8020 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8021 {
8022 	int r;
8023 	vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8024 	r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8025 	srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8026 	if (r != EMULATE_DONE)
8027 		return 0;
8028 	return 1;
8029 }
8030 
8031 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8032 {
8033 	BUG_ON(!vcpu->arch.pio.count);
8034 
8035 	return complete_emulated_io(vcpu);
8036 }
8037 
8038 /*
8039  * Implements the following, as a state machine:
8040  *
8041  * read:
8042  *   for each fragment
8043  *     for each mmio piece in the fragment
8044  *       write gpa, len
8045  *       exit
8046  *       copy data
8047  *   execute insn
8048  *
8049  * write:
8050  *   for each fragment
8051  *     for each mmio piece in the fragment
8052  *       write gpa, len
8053  *       copy data
8054  *       exit
8055  */
8056 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8057 {
8058 	struct kvm_run *run = vcpu->run;
8059 	struct kvm_mmio_fragment *frag;
8060 	unsigned len;
8061 
8062 	BUG_ON(!vcpu->mmio_needed);
8063 
8064 	/* Complete previous fragment */
8065 	frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8066 	len = min(8u, frag->len);
8067 	if (!vcpu->mmio_is_write)
8068 		memcpy(frag->data, run->mmio.data, len);
8069 
8070 	if (frag->len <= 8) {
8071 		/* Switch to the next fragment. */
8072 		frag++;
8073 		vcpu->mmio_cur_fragment++;
8074 	} else {
8075 		/* Go forward to the next mmio piece. */
8076 		frag->data += len;
8077 		frag->gpa += len;
8078 		frag->len -= len;
8079 	}
8080 
8081 	if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8082 		vcpu->mmio_needed = 0;
8083 
8084 		/* FIXME: return into emulator if single-stepping.  */
8085 		if (vcpu->mmio_is_write)
8086 			return 1;
8087 		vcpu->mmio_read_completed = 1;
8088 		return complete_emulated_io(vcpu);
8089 	}
8090 
8091 	run->exit_reason = KVM_EXIT_MMIO;
8092 	run->mmio.phys_addr = frag->gpa;
8093 	if (vcpu->mmio_is_write)
8094 		memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8095 	run->mmio.len = min(8u, frag->len);
8096 	run->mmio.is_write = vcpu->mmio_is_write;
8097 	vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8098 	return 0;
8099 }
8100 
8101 /* Swap (qemu) user FPU context for the guest FPU context. */
8102 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8103 {
8104 	preempt_disable();
8105 	copy_fpregs_to_fpstate(&current->thread.fpu);
8106 	/* PKRU is separately restored in kvm_x86_ops->run.  */
8107 	__copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8108 				~XFEATURE_MASK_PKRU);
8109 	preempt_enable();
8110 	trace_kvm_fpu(1);
8111 }
8112 
8113 /* When vcpu_run ends, restore user space FPU context. */
8114 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8115 {
8116 	preempt_disable();
8117 	copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
8118 	copy_kernel_to_fpregs(&current->thread.fpu.state);
8119 	preempt_enable();
8120 	++vcpu->stat.fpu_reload;
8121 	trace_kvm_fpu(0);
8122 }
8123 
8124 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8125 {
8126 	int r;
8127 
8128 	vcpu_load(vcpu);
8129 	kvm_sigset_activate(vcpu);
8130 	kvm_load_guest_fpu(vcpu);
8131 
8132 	if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8133 		if (kvm_run->immediate_exit) {
8134 			r = -EINTR;
8135 			goto out;
8136 		}
8137 		kvm_vcpu_block(vcpu);
8138 		kvm_apic_accept_events(vcpu);
8139 		kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8140 		r = -EAGAIN;
8141 		if (signal_pending(current)) {
8142 			r = -EINTR;
8143 			vcpu->run->exit_reason = KVM_EXIT_INTR;
8144 			++vcpu->stat.signal_exits;
8145 		}
8146 		goto out;
8147 	}
8148 
8149 	if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8150 		r = -EINVAL;
8151 		goto out;
8152 	}
8153 
8154 	if (vcpu->run->kvm_dirty_regs) {
8155 		r = sync_regs(vcpu);
8156 		if (r != 0)
8157 			goto out;
8158 	}
8159 
8160 	/* re-sync apic's tpr */
8161 	if (!lapic_in_kernel(vcpu)) {
8162 		if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8163 			r = -EINVAL;
8164 			goto out;
8165 		}
8166 	}
8167 
8168 	if (unlikely(vcpu->arch.complete_userspace_io)) {
8169 		int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8170 		vcpu->arch.complete_userspace_io = NULL;
8171 		r = cui(vcpu);
8172 		if (r <= 0)
8173 			goto out;
8174 	} else
8175 		WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8176 
8177 	if (kvm_run->immediate_exit)
8178 		r = -EINTR;
8179 	else
8180 		r = vcpu_run(vcpu);
8181 
8182 out:
8183 	kvm_put_guest_fpu(vcpu);
8184 	if (vcpu->run->kvm_valid_regs)
8185 		store_regs(vcpu);
8186 	post_kvm_run_save(vcpu);
8187 	kvm_sigset_deactivate(vcpu);
8188 
8189 	vcpu_put(vcpu);
8190 	return r;
8191 }
8192 
8193 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8194 {
8195 	if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8196 		/*
8197 		 * We are here if userspace calls get_regs() in the middle of
8198 		 * instruction emulation. Registers state needs to be copied
8199 		 * back from emulation context to vcpu. Userspace shouldn't do
8200 		 * that usually, but some bad designed PV devices (vmware
8201 		 * backdoor interface) need this to work
8202 		 */
8203 		emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
8204 		vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8205 	}
8206 	regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
8207 	regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
8208 	regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
8209 	regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
8210 	regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
8211 	regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
8212 	regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8213 	regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
8214 #ifdef CONFIG_X86_64
8215 	regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
8216 	regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
8217 	regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
8218 	regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
8219 	regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
8220 	regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
8221 	regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
8222 	regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
8223 #endif
8224 
8225 	regs->rip = kvm_rip_read(vcpu);
8226 	regs->rflags = kvm_get_rflags(vcpu);
8227 }
8228 
8229 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8230 {
8231 	vcpu_load(vcpu);
8232 	__get_regs(vcpu, regs);
8233 	vcpu_put(vcpu);
8234 	return 0;
8235 }
8236 
8237 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8238 {
8239 	vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8240 	vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8241 
8242 	kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
8243 	kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
8244 	kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
8245 	kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
8246 	kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
8247 	kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
8248 	kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
8249 	kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
8250 #ifdef CONFIG_X86_64
8251 	kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
8252 	kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
8253 	kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
8254 	kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
8255 	kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
8256 	kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
8257 	kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
8258 	kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
8259 #endif
8260 
8261 	kvm_rip_write(vcpu, regs->rip);
8262 	kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8263 
8264 	vcpu->arch.exception.pending = false;
8265 
8266 	kvm_make_request(KVM_REQ_EVENT, vcpu);
8267 }
8268 
8269 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8270 {
8271 	vcpu_load(vcpu);
8272 	__set_regs(vcpu, regs);
8273 	vcpu_put(vcpu);
8274 	return 0;
8275 }
8276 
8277 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8278 {
8279 	struct kvm_segment cs;
8280 
8281 	kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8282 	*db = cs.db;
8283 	*l = cs.l;
8284 }
8285 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8286 
8287 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8288 {
8289 	struct desc_ptr dt;
8290 
8291 	kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8292 	kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8293 	kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8294 	kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8295 	kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8296 	kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8297 
8298 	kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8299 	kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8300 
8301 	kvm_x86_ops->get_idt(vcpu, &dt);
8302 	sregs->idt.limit = dt.size;
8303 	sregs->idt.base = dt.address;
8304 	kvm_x86_ops->get_gdt(vcpu, &dt);
8305 	sregs->gdt.limit = dt.size;
8306 	sregs->gdt.base = dt.address;
8307 
8308 	sregs->cr0 = kvm_read_cr0(vcpu);
8309 	sregs->cr2 = vcpu->arch.cr2;
8310 	sregs->cr3 = kvm_read_cr3(vcpu);
8311 	sregs->cr4 = kvm_read_cr4(vcpu);
8312 	sregs->cr8 = kvm_get_cr8(vcpu);
8313 	sregs->efer = vcpu->arch.efer;
8314 	sregs->apic_base = kvm_get_apic_base(vcpu);
8315 
8316 	memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8317 
8318 	if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8319 		set_bit(vcpu->arch.interrupt.nr,
8320 			(unsigned long *)sregs->interrupt_bitmap);
8321 }
8322 
8323 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8324 				  struct kvm_sregs *sregs)
8325 {
8326 	vcpu_load(vcpu);
8327 	__get_sregs(vcpu, sregs);
8328 	vcpu_put(vcpu);
8329 	return 0;
8330 }
8331 
8332 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8333 				    struct kvm_mp_state *mp_state)
8334 {
8335 	vcpu_load(vcpu);
8336 
8337 	kvm_apic_accept_events(vcpu);
8338 	if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8339 					vcpu->arch.pv.pv_unhalted)
8340 		mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8341 	else
8342 		mp_state->mp_state = vcpu->arch.mp_state;
8343 
8344 	vcpu_put(vcpu);
8345 	return 0;
8346 }
8347 
8348 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8349 				    struct kvm_mp_state *mp_state)
8350 {
8351 	int ret = -EINVAL;
8352 
8353 	vcpu_load(vcpu);
8354 
8355 	if (!lapic_in_kernel(vcpu) &&
8356 	    mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8357 		goto out;
8358 
8359 	/* INITs are latched while in SMM */
8360 	if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8361 	    (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8362 	     mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8363 		goto out;
8364 
8365 	if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8366 		vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8367 		set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8368 	} else
8369 		vcpu->arch.mp_state = mp_state->mp_state;
8370 	kvm_make_request(KVM_REQ_EVENT, vcpu);
8371 
8372 	ret = 0;
8373 out:
8374 	vcpu_put(vcpu);
8375 	return ret;
8376 }
8377 
8378 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8379 		    int reason, bool has_error_code, u32 error_code)
8380 {
8381 	struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8382 	int ret;
8383 
8384 	init_emulate_ctxt(vcpu);
8385 
8386 	ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8387 				   has_error_code, error_code);
8388 
8389 	if (ret)
8390 		return EMULATE_FAIL;
8391 
8392 	kvm_rip_write(vcpu, ctxt->eip);
8393 	kvm_set_rflags(vcpu, ctxt->eflags);
8394 	kvm_make_request(KVM_REQ_EVENT, vcpu);
8395 	return EMULATE_DONE;
8396 }
8397 EXPORT_SYMBOL_GPL(kvm_task_switch);
8398 
8399 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8400 {
8401 	if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8402 			(sregs->cr4 & X86_CR4_OSXSAVE))
8403 		return  -EINVAL;
8404 
8405 	if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8406 		/*
8407 		 * When EFER.LME and CR0.PG are set, the processor is in
8408 		 * 64-bit mode (though maybe in a 32-bit code segment).
8409 		 * CR4.PAE and EFER.LMA must be set.
8410 		 */
8411 		if (!(sregs->cr4 & X86_CR4_PAE)
8412 		    || !(sregs->efer & EFER_LMA))
8413 			return -EINVAL;
8414 	} else {
8415 		/*
8416 		 * Not in 64-bit mode: EFER.LMA is clear and the code
8417 		 * segment cannot be 64-bit.
8418 		 */
8419 		if (sregs->efer & EFER_LMA || sregs->cs.l)
8420 			return -EINVAL;
8421 	}
8422 
8423 	return 0;
8424 }
8425 
8426 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8427 {
8428 	struct msr_data apic_base_msr;
8429 	int mmu_reset_needed = 0;
8430 	int cpuid_update_needed = 0;
8431 	int pending_vec, max_bits, idx;
8432 	struct desc_ptr dt;
8433 	int ret = -EINVAL;
8434 
8435 	if (kvm_valid_sregs(vcpu, sregs))
8436 		goto out;
8437 
8438 	apic_base_msr.data = sregs->apic_base;
8439 	apic_base_msr.host_initiated = true;
8440 	if (kvm_set_apic_base(vcpu, &apic_base_msr))
8441 		goto out;
8442 
8443 	dt.size = sregs->idt.limit;
8444 	dt.address = sregs->idt.base;
8445 	kvm_x86_ops->set_idt(vcpu, &dt);
8446 	dt.size = sregs->gdt.limit;
8447 	dt.address = sregs->gdt.base;
8448 	kvm_x86_ops->set_gdt(vcpu, &dt);
8449 
8450 	vcpu->arch.cr2 = sregs->cr2;
8451 	mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
8452 	vcpu->arch.cr3 = sregs->cr3;
8453 	__set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
8454 
8455 	kvm_set_cr8(vcpu, sregs->cr8);
8456 
8457 	mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
8458 	kvm_x86_ops->set_efer(vcpu, sregs->efer);
8459 
8460 	mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
8461 	kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
8462 	vcpu->arch.cr0 = sregs->cr0;
8463 
8464 	mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
8465 	cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8466 				(X86_CR4_OSXSAVE | X86_CR4_PKE));
8467 	kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
8468 	if (cpuid_update_needed)
8469 		kvm_update_cpuid(vcpu);
8470 
8471 	idx = srcu_read_lock(&vcpu->kvm->srcu);
8472 	if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) {
8473 		load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
8474 		mmu_reset_needed = 1;
8475 	}
8476 	srcu_read_unlock(&vcpu->kvm->srcu, idx);
8477 
8478 	if (mmu_reset_needed)
8479 		kvm_mmu_reset_context(vcpu);
8480 
8481 	max_bits = KVM_NR_INTERRUPTS;
8482 	pending_vec = find_first_bit(
8483 		(const unsigned long *)sregs->interrupt_bitmap, max_bits);
8484 	if (pending_vec < max_bits) {
8485 		kvm_queue_interrupt(vcpu, pending_vec, false);
8486 		pr_debug("Set back pending irq %d\n", pending_vec);
8487 	}
8488 
8489 	kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8490 	kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8491 	kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8492 	kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8493 	kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8494 	kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8495 
8496 	kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8497 	kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8498 
8499 	update_cr8_intercept(vcpu);
8500 
8501 	/* Older userspace won't unhalt the vcpu on reset. */
8502 	if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
8503 	    sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
8504 	    !is_protmode(vcpu))
8505 		vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8506 
8507 	kvm_make_request(KVM_REQ_EVENT, vcpu);
8508 
8509 	ret = 0;
8510 out:
8511 	return ret;
8512 }
8513 
8514 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8515 				  struct kvm_sregs *sregs)
8516 {
8517 	int ret;
8518 
8519 	vcpu_load(vcpu);
8520 	ret = __set_sregs(vcpu, sregs);
8521 	vcpu_put(vcpu);
8522 	return ret;
8523 }
8524 
8525 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8526 					struct kvm_guest_debug *dbg)
8527 {
8528 	unsigned long rflags;
8529 	int i, r;
8530 
8531 	vcpu_load(vcpu);
8532 
8533 	if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8534 		r = -EBUSY;
8535 		if (vcpu->arch.exception.pending)
8536 			goto out;
8537 		if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8538 			kvm_queue_exception(vcpu, DB_VECTOR);
8539 		else
8540 			kvm_queue_exception(vcpu, BP_VECTOR);
8541 	}
8542 
8543 	/*
8544 	 * Read rflags as long as potentially injected trace flags are still
8545 	 * filtered out.
8546 	 */
8547 	rflags = kvm_get_rflags(vcpu);
8548 
8549 	vcpu->guest_debug = dbg->control;
8550 	if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8551 		vcpu->guest_debug = 0;
8552 
8553 	if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
8554 		for (i = 0; i < KVM_NR_DB_REGS; ++i)
8555 			vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
8556 		vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
8557 	} else {
8558 		for (i = 0; i < KVM_NR_DB_REGS; i++)
8559 			vcpu->arch.eff_db[i] = vcpu->arch.db[i];
8560 	}
8561 	kvm_update_dr7(vcpu);
8562 
8563 	if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8564 		vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8565 			get_segment_base(vcpu, VCPU_SREG_CS);
8566 
8567 	/*
8568 	 * Trigger an rflags update that will inject or remove the trace
8569 	 * flags.
8570 	 */
8571 	kvm_set_rflags(vcpu, rflags);
8572 
8573 	kvm_x86_ops->update_bp_intercept(vcpu);
8574 
8575 	r = 0;
8576 
8577 out:
8578 	vcpu_put(vcpu);
8579 	return r;
8580 }
8581 
8582 /*
8583  * Translate a guest virtual address to a guest physical address.
8584  */
8585 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8586 				    struct kvm_translation *tr)
8587 {
8588 	unsigned long vaddr = tr->linear_address;
8589 	gpa_t gpa;
8590 	int idx;
8591 
8592 	vcpu_load(vcpu);
8593 
8594 	idx = srcu_read_lock(&vcpu->kvm->srcu);
8595 	gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
8596 	srcu_read_unlock(&vcpu->kvm->srcu, idx);
8597 	tr->physical_address = gpa;
8598 	tr->valid = gpa != UNMAPPED_GVA;
8599 	tr->writeable = 1;
8600 	tr->usermode = 0;
8601 
8602 	vcpu_put(vcpu);
8603 	return 0;
8604 }
8605 
8606 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8607 {
8608 	struct fxregs_state *fxsave;
8609 
8610 	vcpu_load(vcpu);
8611 
8612 	fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8613 	memcpy(fpu->fpr, fxsave->st_space, 128);
8614 	fpu->fcw = fxsave->cwd;
8615 	fpu->fsw = fxsave->swd;
8616 	fpu->ftwx = fxsave->twd;
8617 	fpu->last_opcode = fxsave->fop;
8618 	fpu->last_ip = fxsave->rip;
8619 	fpu->last_dp = fxsave->rdp;
8620 	memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
8621 
8622 	vcpu_put(vcpu);
8623 	return 0;
8624 }
8625 
8626 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8627 {
8628 	struct fxregs_state *fxsave;
8629 
8630 	vcpu_load(vcpu);
8631 
8632 	fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8633 
8634 	memcpy(fxsave->st_space, fpu->fpr, 128);
8635 	fxsave->cwd = fpu->fcw;
8636 	fxsave->swd = fpu->fsw;
8637 	fxsave->twd = fpu->ftwx;
8638 	fxsave->fop = fpu->last_opcode;
8639 	fxsave->rip = fpu->last_ip;
8640 	fxsave->rdp = fpu->last_dp;
8641 	memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
8642 
8643 	vcpu_put(vcpu);
8644 	return 0;
8645 }
8646 
8647 static void store_regs(struct kvm_vcpu *vcpu)
8648 {
8649 	BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8650 
8651 	if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8652 		__get_regs(vcpu, &vcpu->run->s.regs.regs);
8653 
8654 	if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8655 		__get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8656 
8657 	if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8658 		kvm_vcpu_ioctl_x86_get_vcpu_events(
8659 				vcpu, &vcpu->run->s.regs.events);
8660 }
8661 
8662 static int sync_regs(struct kvm_vcpu *vcpu)
8663 {
8664 	if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8665 		return -EINVAL;
8666 
8667 	if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8668 		__set_regs(vcpu, &vcpu->run->s.regs.regs);
8669 		vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8670 	}
8671 	if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8672 		if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8673 			return -EINVAL;
8674 		vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8675 	}
8676 	if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8677 		if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8678 				vcpu, &vcpu->run->s.regs.events))
8679 			return -EINVAL;
8680 		vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8681 	}
8682 
8683 	return 0;
8684 }
8685 
8686 static void fx_init(struct kvm_vcpu *vcpu)
8687 {
8688 	fpstate_init(&vcpu->arch.guest_fpu->state);
8689 	if (boot_cpu_has(X86_FEATURE_XSAVES))
8690 		vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
8691 			host_xcr0 | XSTATE_COMPACTION_ENABLED;
8692 
8693 	/*
8694 	 * Ensure guest xcr0 is valid for loading
8695 	 */
8696 	vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8697 
8698 	vcpu->arch.cr0 |= X86_CR0_ET;
8699 }
8700 
8701 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8702 {
8703 	void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8704 
8705 	kvmclock_reset(vcpu);
8706 
8707 	kvm_x86_ops->vcpu_free(vcpu);
8708 	free_cpumask_var(wbinvd_dirty_mask);
8709 }
8710 
8711 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8712 						unsigned int id)
8713 {
8714 	struct kvm_vcpu *vcpu;
8715 
8716 	if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
8717 		printk_once(KERN_WARNING
8718 		"kvm: SMP vm created on host with unstable TSC; "
8719 		"guest TSC will not be reliable\n");
8720 
8721 	vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8722 
8723 	return vcpu;
8724 }
8725 
8726 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8727 {
8728 	vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8729 	kvm_vcpu_mtrr_init(vcpu);
8730 	vcpu_load(vcpu);
8731 	kvm_vcpu_reset(vcpu, false);
8732 	kvm_init_mmu(vcpu, false);
8733 	vcpu_put(vcpu);
8734 	return 0;
8735 }
8736 
8737 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
8738 {
8739 	struct msr_data msr;
8740 	struct kvm *kvm = vcpu->kvm;
8741 
8742 	kvm_hv_vcpu_postcreate(vcpu);
8743 
8744 	if (mutex_lock_killable(&vcpu->mutex))
8745 		return;
8746 	vcpu_load(vcpu);
8747 	msr.data = 0x0;
8748 	msr.index = MSR_IA32_TSC;
8749 	msr.host_initiated = true;
8750 	kvm_write_tsc(vcpu, &msr);
8751 	vcpu_put(vcpu);
8752 	mutex_unlock(&vcpu->mutex);
8753 
8754 	if (!kvmclock_periodic_sync)
8755 		return;
8756 
8757 	schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8758 					KVMCLOCK_SYNC_PERIOD);
8759 }
8760 
8761 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
8762 {
8763 	vcpu->arch.apf.msr_val = 0;
8764 
8765 	vcpu_load(vcpu);
8766 	kvm_mmu_unload(vcpu);
8767 	vcpu_put(vcpu);
8768 
8769 	kvm_x86_ops->vcpu_free(vcpu);
8770 }
8771 
8772 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
8773 {
8774 	kvm_lapic_reset(vcpu, init_event);
8775 
8776 	vcpu->arch.hflags = 0;
8777 
8778 	vcpu->arch.smi_pending = 0;
8779 	vcpu->arch.smi_count = 0;
8780 	atomic_set(&vcpu->arch.nmi_queued, 0);
8781 	vcpu->arch.nmi_pending = 0;
8782 	vcpu->arch.nmi_injected = false;
8783 	kvm_clear_interrupt_queue(vcpu);
8784 	kvm_clear_exception_queue(vcpu);
8785 	vcpu->arch.exception.pending = false;
8786 
8787 	memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
8788 	kvm_update_dr0123(vcpu);
8789 	vcpu->arch.dr6 = DR6_INIT;
8790 	kvm_update_dr6(vcpu);
8791 	vcpu->arch.dr7 = DR7_FIXED_1;
8792 	kvm_update_dr7(vcpu);
8793 
8794 	vcpu->arch.cr2 = 0;
8795 
8796 	kvm_make_request(KVM_REQ_EVENT, vcpu);
8797 	vcpu->arch.apf.msr_val = 0;
8798 	vcpu->arch.st.msr_val = 0;
8799 
8800 	kvmclock_reset(vcpu);
8801 
8802 	kvm_clear_async_pf_completion_queue(vcpu);
8803 	kvm_async_pf_hash_reset(vcpu);
8804 	vcpu->arch.apf.halted = false;
8805 
8806 	if (kvm_mpx_supported()) {
8807 		void *mpx_state_buffer;
8808 
8809 		/*
8810 		 * To avoid have the INIT path from kvm_apic_has_events() that be
8811 		 * called with loaded FPU and does not let userspace fix the state.
8812 		 */
8813 		if (init_event)
8814 			kvm_put_guest_fpu(vcpu);
8815 		mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
8816 					XFEATURE_MASK_BNDREGS);
8817 		if (mpx_state_buffer)
8818 			memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8819 		mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
8820 					XFEATURE_MASK_BNDCSR);
8821 		if (mpx_state_buffer)
8822 			memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
8823 		if (init_event)
8824 			kvm_load_guest_fpu(vcpu);
8825 	}
8826 
8827 	if (!init_event) {
8828 		kvm_pmu_reset(vcpu);
8829 		vcpu->arch.smbase = 0x30000;
8830 
8831 		vcpu->arch.msr_misc_features_enables = 0;
8832 
8833 		vcpu->arch.xcr0 = XFEATURE_MASK_FP;
8834 	}
8835 
8836 	memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8837 	vcpu->arch.regs_avail = ~0;
8838 	vcpu->arch.regs_dirty = ~0;
8839 
8840 	vcpu->arch.ia32_xss = 0;
8841 
8842 	kvm_x86_ops->vcpu_reset(vcpu, init_event);
8843 }
8844 
8845 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
8846 {
8847 	struct kvm_segment cs;
8848 
8849 	kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8850 	cs.selector = vector << 8;
8851 	cs.base = vector << 12;
8852 	kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8853 	kvm_rip_write(vcpu, 0);
8854 }
8855 
8856 int kvm_arch_hardware_enable(void)
8857 {
8858 	struct kvm *kvm;
8859 	struct kvm_vcpu *vcpu;
8860 	int i;
8861 	int ret;
8862 	u64 local_tsc;
8863 	u64 max_tsc = 0;
8864 	bool stable, backwards_tsc = false;
8865 
8866 	kvm_shared_msr_cpu_online();
8867 	ret = kvm_x86_ops->hardware_enable();
8868 	if (ret != 0)
8869 		return ret;
8870 
8871 	local_tsc = rdtsc();
8872 	stable = !kvm_check_tsc_unstable();
8873 	list_for_each_entry(kvm, &vm_list, vm_list) {
8874 		kvm_for_each_vcpu(i, vcpu, kvm) {
8875 			if (!stable && vcpu->cpu == smp_processor_id())
8876 				kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8877 			if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8878 				backwards_tsc = true;
8879 				if (vcpu->arch.last_host_tsc > max_tsc)
8880 					max_tsc = vcpu->arch.last_host_tsc;
8881 			}
8882 		}
8883 	}
8884 
8885 	/*
8886 	 * Sometimes, even reliable TSCs go backwards.  This happens on
8887 	 * platforms that reset TSC during suspend or hibernate actions, but
8888 	 * maintain synchronization.  We must compensate.  Fortunately, we can
8889 	 * detect that condition here, which happens early in CPU bringup,
8890 	 * before any KVM threads can be running.  Unfortunately, we can't
8891 	 * bring the TSCs fully up to date with real time, as we aren't yet far
8892 	 * enough into CPU bringup that we know how much real time has actually
8893 	 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
8894 	 * variables that haven't been updated yet.
8895 	 *
8896 	 * So we simply find the maximum observed TSC above, then record the
8897 	 * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
8898 	 * the adjustment will be applied.  Note that we accumulate
8899 	 * adjustments, in case multiple suspend cycles happen before some VCPU
8900 	 * gets a chance to run again.  In the event that no KVM threads get a
8901 	 * chance to run, we will miss the entire elapsed period, as we'll have
8902 	 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8903 	 * loose cycle time.  This isn't too big a deal, since the loss will be
8904 	 * uniform across all VCPUs (not to mention the scenario is extremely
8905 	 * unlikely). It is possible that a second hibernate recovery happens
8906 	 * much faster than a first, causing the observed TSC here to be
8907 	 * smaller; this would require additional padding adjustment, which is
8908 	 * why we set last_host_tsc to the local tsc observed here.
8909 	 *
8910 	 * N.B. - this code below runs only on platforms with reliable TSC,
8911 	 * as that is the only way backwards_tsc is set above.  Also note
8912 	 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8913 	 * have the same delta_cyc adjustment applied if backwards_tsc
8914 	 * is detected.  Note further, this adjustment is only done once,
8915 	 * as we reset last_host_tsc on all VCPUs to stop this from being
8916 	 * called multiple times (one for each physical CPU bringup).
8917 	 *
8918 	 * Platforms with unreliable TSCs don't have to deal with this, they
8919 	 * will be compensated by the logic in vcpu_load, which sets the TSC to
8920 	 * catchup mode.  This will catchup all VCPUs to real time, but cannot
8921 	 * guarantee that they stay in perfect synchronization.
8922 	 */
8923 	if (backwards_tsc) {
8924 		u64 delta_cyc = max_tsc - local_tsc;
8925 		list_for_each_entry(kvm, &vm_list, vm_list) {
8926 			kvm->arch.backwards_tsc_observed = true;
8927 			kvm_for_each_vcpu(i, vcpu, kvm) {
8928 				vcpu->arch.tsc_offset_adjustment += delta_cyc;
8929 				vcpu->arch.last_host_tsc = local_tsc;
8930 				kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
8931 			}
8932 
8933 			/*
8934 			 * We have to disable TSC offset matching.. if you were
8935 			 * booting a VM while issuing an S4 host suspend....
8936 			 * you may have some problem.  Solving this issue is
8937 			 * left as an exercise to the reader.
8938 			 */
8939 			kvm->arch.last_tsc_nsec = 0;
8940 			kvm->arch.last_tsc_write = 0;
8941 		}
8942 
8943 	}
8944 	return 0;
8945 }
8946 
8947 void kvm_arch_hardware_disable(void)
8948 {
8949 	kvm_x86_ops->hardware_disable();
8950 	drop_user_return_notifiers();
8951 }
8952 
8953 int kvm_arch_hardware_setup(void)
8954 {
8955 	int r;
8956 
8957 	r = kvm_x86_ops->hardware_setup();
8958 	if (r != 0)
8959 		return r;
8960 
8961 	if (kvm_has_tsc_control) {
8962 		/*
8963 		 * Make sure the user can only configure tsc_khz values that
8964 		 * fit into a signed integer.
8965 		 * A min value is not calculated because it will always
8966 		 * be 1 on all machines.
8967 		 */
8968 		u64 max = min(0x7fffffffULL,
8969 			      __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8970 		kvm_max_guest_tsc_khz = max;
8971 
8972 		kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
8973 	}
8974 
8975 	kvm_init_msr_list();
8976 	return 0;
8977 }
8978 
8979 void kvm_arch_hardware_unsetup(void)
8980 {
8981 	kvm_x86_ops->hardware_unsetup();
8982 }
8983 
8984 void kvm_arch_check_processor_compat(void *rtn)
8985 {
8986 	kvm_x86_ops->check_processor_compatibility(rtn);
8987 }
8988 
8989 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8990 {
8991 	return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8992 }
8993 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8994 
8995 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8996 {
8997 	return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
8998 }
8999 
9000 struct static_key kvm_no_apic_vcpu __read_mostly;
9001 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9002 
9003 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9004 {
9005 	struct page *page;
9006 	int r;
9007 
9008 	vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9009 	vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9010 	if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9011 		vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9012 	else
9013 		vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9014 
9015 	page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9016 	if (!page) {
9017 		r = -ENOMEM;
9018 		goto fail;
9019 	}
9020 	vcpu->arch.pio_data = page_address(page);
9021 
9022 	kvm_set_tsc_khz(vcpu, max_tsc_khz);
9023 
9024 	r = kvm_mmu_create(vcpu);
9025 	if (r < 0)
9026 		goto fail_free_pio_data;
9027 
9028 	if (irqchip_in_kernel(vcpu->kvm)) {
9029 		r = kvm_create_lapic(vcpu);
9030 		if (r < 0)
9031 			goto fail_mmu_destroy;
9032 	} else
9033 		static_key_slow_inc(&kvm_no_apic_vcpu);
9034 
9035 	vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9036 				       GFP_KERNEL);
9037 	if (!vcpu->arch.mce_banks) {
9038 		r = -ENOMEM;
9039 		goto fail_free_lapic;
9040 	}
9041 	vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9042 
9043 	if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
9044 		r = -ENOMEM;
9045 		goto fail_free_mce_banks;
9046 	}
9047 
9048 	fx_init(vcpu);
9049 
9050 	vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9051 
9052 	vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9053 
9054 	vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9055 
9056 	kvm_async_pf_hash_reset(vcpu);
9057 	kvm_pmu_init(vcpu);
9058 
9059 	vcpu->arch.pending_external_vector = -1;
9060 	vcpu->arch.preempted_in_kernel = false;
9061 
9062 	kvm_hv_vcpu_init(vcpu);
9063 
9064 	return 0;
9065 
9066 fail_free_mce_banks:
9067 	kfree(vcpu->arch.mce_banks);
9068 fail_free_lapic:
9069 	kvm_free_lapic(vcpu);
9070 fail_mmu_destroy:
9071 	kvm_mmu_destroy(vcpu);
9072 fail_free_pio_data:
9073 	free_page((unsigned long)vcpu->arch.pio_data);
9074 fail:
9075 	return r;
9076 }
9077 
9078 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9079 {
9080 	int idx;
9081 
9082 	kvm_hv_vcpu_uninit(vcpu);
9083 	kvm_pmu_destroy(vcpu);
9084 	kfree(vcpu->arch.mce_banks);
9085 	kvm_free_lapic(vcpu);
9086 	idx = srcu_read_lock(&vcpu->kvm->srcu);
9087 	kvm_mmu_destroy(vcpu);
9088 	srcu_read_unlock(&vcpu->kvm->srcu, idx);
9089 	free_page((unsigned long)vcpu->arch.pio_data);
9090 	if (!lapic_in_kernel(vcpu))
9091 		static_key_slow_dec(&kvm_no_apic_vcpu);
9092 }
9093 
9094 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9095 {
9096 	vcpu->arch.l1tf_flush_l1d = true;
9097 	kvm_x86_ops->sched_in(vcpu, cpu);
9098 }
9099 
9100 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9101 {
9102 	if (type)
9103 		return -EINVAL;
9104 
9105 	INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9106 	INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9107 	INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9108 	INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9109 	atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9110 
9111 	/* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9112 	set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9113 	/* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9114 	set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9115 		&kvm->arch.irq_sources_bitmap);
9116 
9117 	raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9118 	mutex_init(&kvm->arch.apic_map_lock);
9119 	spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9120 
9121 	kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
9122 	pvclock_update_vm_gtod_copy(kvm);
9123 
9124 	kvm->arch.guest_can_read_msr_platform_info = true;
9125 
9126 	INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9127 	INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9128 
9129 	kvm_hv_init_vm(kvm);
9130 	kvm_page_track_init(kvm);
9131 	kvm_mmu_init_vm(kvm);
9132 
9133 	if (kvm_x86_ops->vm_init)
9134 		return kvm_x86_ops->vm_init(kvm);
9135 
9136 	return 0;
9137 }
9138 
9139 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9140 {
9141 	vcpu_load(vcpu);
9142 	kvm_mmu_unload(vcpu);
9143 	vcpu_put(vcpu);
9144 }
9145 
9146 static void kvm_free_vcpus(struct kvm *kvm)
9147 {
9148 	unsigned int i;
9149 	struct kvm_vcpu *vcpu;
9150 
9151 	/*
9152 	 * Unpin any mmu pages first.
9153 	 */
9154 	kvm_for_each_vcpu(i, vcpu, kvm) {
9155 		kvm_clear_async_pf_completion_queue(vcpu);
9156 		kvm_unload_vcpu_mmu(vcpu);
9157 	}
9158 	kvm_for_each_vcpu(i, vcpu, kvm)
9159 		kvm_arch_vcpu_free(vcpu);
9160 
9161 	mutex_lock(&kvm->lock);
9162 	for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9163 		kvm->vcpus[i] = NULL;
9164 
9165 	atomic_set(&kvm->online_vcpus, 0);
9166 	mutex_unlock(&kvm->lock);
9167 }
9168 
9169 void kvm_arch_sync_events(struct kvm *kvm)
9170 {
9171 	cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9172 	cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9173 	kvm_free_pit(kvm);
9174 }
9175 
9176 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9177 {
9178 	int i, r;
9179 	unsigned long hva;
9180 	struct kvm_memslots *slots = kvm_memslots(kvm);
9181 	struct kvm_memory_slot *slot, old;
9182 
9183 	/* Called with kvm->slots_lock held.  */
9184 	if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9185 		return -EINVAL;
9186 
9187 	slot = id_to_memslot(slots, id);
9188 	if (size) {
9189 		if (slot->npages)
9190 			return -EEXIST;
9191 
9192 		/*
9193 		 * MAP_SHARED to prevent internal slot pages from being moved
9194 		 * by fork()/COW.
9195 		 */
9196 		hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9197 			      MAP_SHARED | MAP_ANONYMOUS, 0);
9198 		if (IS_ERR((void *)hva))
9199 			return PTR_ERR((void *)hva);
9200 	} else {
9201 		if (!slot->npages)
9202 			return 0;
9203 
9204 		hva = 0;
9205 	}
9206 
9207 	old = *slot;
9208 	for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9209 		struct kvm_userspace_memory_region m;
9210 
9211 		m.slot = id | (i << 16);
9212 		m.flags = 0;
9213 		m.guest_phys_addr = gpa;
9214 		m.userspace_addr = hva;
9215 		m.memory_size = size;
9216 		r = __kvm_set_memory_region(kvm, &m);
9217 		if (r < 0)
9218 			return r;
9219 	}
9220 
9221 	if (!size)
9222 		vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
9223 
9224 	return 0;
9225 }
9226 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9227 
9228 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9229 {
9230 	int r;
9231 
9232 	mutex_lock(&kvm->slots_lock);
9233 	r = __x86_set_memory_region(kvm, id, gpa, size);
9234 	mutex_unlock(&kvm->slots_lock);
9235 
9236 	return r;
9237 }
9238 EXPORT_SYMBOL_GPL(x86_set_memory_region);
9239 
9240 void kvm_arch_destroy_vm(struct kvm *kvm)
9241 {
9242 	if (current->mm == kvm->mm) {
9243 		/*
9244 		 * Free memory regions allocated on behalf of userspace,
9245 		 * unless the the memory map has changed due to process exit
9246 		 * or fd copying.
9247 		 */
9248 		x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9249 		x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9250 		x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9251 	}
9252 	if (kvm_x86_ops->vm_destroy)
9253 		kvm_x86_ops->vm_destroy(kvm);
9254 	kvm_pic_destroy(kvm);
9255 	kvm_ioapic_destroy(kvm);
9256 	kvm_free_vcpus(kvm);
9257 	kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9258 	kvm_mmu_uninit_vm(kvm);
9259 	kvm_page_track_cleanup(kvm);
9260 	kvm_hv_destroy_vm(kvm);
9261 }
9262 
9263 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
9264 			   struct kvm_memory_slot *dont)
9265 {
9266 	int i;
9267 
9268 	for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9269 		if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
9270 			kvfree(free->arch.rmap[i]);
9271 			free->arch.rmap[i] = NULL;
9272 		}
9273 		if (i == 0)
9274 			continue;
9275 
9276 		if (!dont || free->arch.lpage_info[i - 1] !=
9277 			     dont->arch.lpage_info[i - 1]) {
9278 			kvfree(free->arch.lpage_info[i - 1]);
9279 			free->arch.lpage_info[i - 1] = NULL;
9280 		}
9281 	}
9282 
9283 	kvm_page_track_free_memslot(free, dont);
9284 }
9285 
9286 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9287 			    unsigned long npages)
9288 {
9289 	int i;
9290 
9291 	for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9292 		struct kvm_lpage_info *linfo;
9293 		unsigned long ugfn;
9294 		int lpages;
9295 		int level = i + 1;
9296 
9297 		lpages = gfn_to_index(slot->base_gfn + npages - 1,
9298 				      slot->base_gfn, level) + 1;
9299 
9300 		slot->arch.rmap[i] =
9301 			kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9302 				 GFP_KERNEL);
9303 		if (!slot->arch.rmap[i])
9304 			goto out_free;
9305 		if (i == 0)
9306 			continue;
9307 
9308 		linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL);
9309 		if (!linfo)
9310 			goto out_free;
9311 
9312 		slot->arch.lpage_info[i - 1] = linfo;
9313 
9314 		if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9315 			linfo[0].disallow_lpage = 1;
9316 		if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9317 			linfo[lpages - 1].disallow_lpage = 1;
9318 		ugfn = slot->userspace_addr >> PAGE_SHIFT;
9319 		/*
9320 		 * If the gfn and userspace address are not aligned wrt each
9321 		 * other, or if explicitly asked to, disable large page
9322 		 * support for this slot
9323 		 */
9324 		if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9325 		    !kvm_largepages_enabled()) {
9326 			unsigned long j;
9327 
9328 			for (j = 0; j < lpages; ++j)
9329 				linfo[j].disallow_lpage = 1;
9330 		}
9331 	}
9332 
9333 	if (kvm_page_track_create_memslot(slot, npages))
9334 		goto out_free;
9335 
9336 	return 0;
9337 
9338 out_free:
9339 	for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9340 		kvfree(slot->arch.rmap[i]);
9341 		slot->arch.rmap[i] = NULL;
9342 		if (i == 0)
9343 			continue;
9344 
9345 		kvfree(slot->arch.lpage_info[i - 1]);
9346 		slot->arch.lpage_info[i - 1] = NULL;
9347 	}
9348 	return -ENOMEM;
9349 }
9350 
9351 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
9352 {
9353 	/*
9354 	 * memslots->generation has been incremented.
9355 	 * mmio generation may have reached its maximum value.
9356 	 */
9357 	kvm_mmu_invalidate_mmio_sptes(kvm, slots);
9358 }
9359 
9360 int kvm_arch_prepare_memory_region(struct kvm *kvm,
9361 				struct kvm_memory_slot *memslot,
9362 				const struct kvm_userspace_memory_region *mem,
9363 				enum kvm_mr_change change)
9364 {
9365 	return 0;
9366 }
9367 
9368 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9369 				     struct kvm_memory_slot *new)
9370 {
9371 	/* Still write protect RO slot */
9372 	if (new->flags & KVM_MEM_READONLY) {
9373 		kvm_mmu_slot_remove_write_access(kvm, new);
9374 		return;
9375 	}
9376 
9377 	/*
9378 	 * Call kvm_x86_ops dirty logging hooks when they are valid.
9379 	 *
9380 	 * kvm_x86_ops->slot_disable_log_dirty is called when:
9381 	 *
9382 	 *  - KVM_MR_CREATE with dirty logging is disabled
9383 	 *  - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9384 	 *
9385 	 * The reason is, in case of PML, we need to set D-bit for any slots
9386 	 * with dirty logging disabled in order to eliminate unnecessary GPA
9387 	 * logging in PML buffer (and potential PML buffer full VMEXT). This
9388 	 * guarantees leaving PML enabled during guest's lifetime won't have
9389 	 * any additional overhead from PML when guest is running with dirty
9390 	 * logging disabled for memory slots.
9391 	 *
9392 	 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9393 	 * to dirty logging mode.
9394 	 *
9395 	 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9396 	 *
9397 	 * In case of write protect:
9398 	 *
9399 	 * Write protect all pages for dirty logging.
9400 	 *
9401 	 * All the sptes including the large sptes which point to this
9402 	 * slot are set to readonly. We can not create any new large
9403 	 * spte on this slot until the end of the logging.
9404 	 *
9405 	 * See the comments in fast_page_fault().
9406 	 */
9407 	if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9408 		if (kvm_x86_ops->slot_enable_log_dirty)
9409 			kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9410 		else
9411 			kvm_mmu_slot_remove_write_access(kvm, new);
9412 	} else {
9413 		if (kvm_x86_ops->slot_disable_log_dirty)
9414 			kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9415 	}
9416 }
9417 
9418 void kvm_arch_commit_memory_region(struct kvm *kvm,
9419 				const struct kvm_userspace_memory_region *mem,
9420 				const struct kvm_memory_slot *old,
9421 				const struct kvm_memory_slot *new,
9422 				enum kvm_mr_change change)
9423 {
9424 	int nr_mmu_pages = 0;
9425 
9426 	if (!kvm->arch.n_requested_mmu_pages)
9427 		nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9428 
9429 	if (nr_mmu_pages)
9430 		kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
9431 
9432 	/*
9433 	 * Dirty logging tracks sptes in 4k granularity, meaning that large
9434 	 * sptes have to be split.  If live migration is successful, the guest
9435 	 * in the source machine will be destroyed and large sptes will be
9436 	 * created in the destination. However, if the guest continues to run
9437 	 * in the source machine (for example if live migration fails), small
9438 	 * sptes will remain around and cause bad performance.
9439 	 *
9440 	 * Scan sptes if dirty logging has been stopped, dropping those
9441 	 * which can be collapsed into a single large-page spte.  Later
9442 	 * page faults will create the large-page sptes.
9443 	 */
9444 	if ((change != KVM_MR_DELETE) &&
9445 		(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9446 		!(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9447 		kvm_mmu_zap_collapsible_sptes(kvm, new);
9448 
9449 	/*
9450 	 * Set up write protection and/or dirty logging for the new slot.
9451 	 *
9452 	 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9453 	 * been zapped so no dirty logging staff is needed for old slot. For
9454 	 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9455 	 * new and it's also covered when dealing with the new slot.
9456 	 *
9457 	 * FIXME: const-ify all uses of struct kvm_memory_slot.
9458 	 */
9459 	if (change != KVM_MR_DELETE)
9460 		kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
9461 }
9462 
9463 void kvm_arch_flush_shadow_all(struct kvm *kvm)
9464 {
9465 	kvm_mmu_invalidate_zap_all_pages(kvm);
9466 }
9467 
9468 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9469 				   struct kvm_memory_slot *slot)
9470 {
9471 	kvm_page_track_flush_slot(kvm, slot);
9472 }
9473 
9474 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9475 {
9476 	return (is_guest_mode(vcpu) &&
9477 			kvm_x86_ops->guest_apic_has_interrupt &&
9478 			kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9479 }
9480 
9481 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9482 {
9483 	if (!list_empty_careful(&vcpu->async_pf.done))
9484 		return true;
9485 
9486 	if (kvm_apic_has_events(vcpu))
9487 		return true;
9488 
9489 	if (vcpu->arch.pv.pv_unhalted)
9490 		return true;
9491 
9492 	if (vcpu->arch.exception.pending)
9493 		return true;
9494 
9495 	if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9496 	    (vcpu->arch.nmi_pending &&
9497 	     kvm_x86_ops->nmi_allowed(vcpu)))
9498 		return true;
9499 
9500 	if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9501 	    (vcpu->arch.smi_pending && !is_smm(vcpu)))
9502 		return true;
9503 
9504 	if (kvm_arch_interrupt_allowed(vcpu) &&
9505 	    (kvm_cpu_has_interrupt(vcpu) ||
9506 	    kvm_guest_apic_has_interrupt(vcpu)))
9507 		return true;
9508 
9509 	if (kvm_hv_has_stimer_pending(vcpu))
9510 		return true;
9511 
9512 	return false;
9513 }
9514 
9515 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9516 {
9517 	return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
9518 }
9519 
9520 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9521 {
9522 	return vcpu->arch.preempted_in_kernel;
9523 }
9524 
9525 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
9526 {
9527 	return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
9528 }
9529 
9530 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9531 {
9532 	return kvm_x86_ops->interrupt_allowed(vcpu);
9533 }
9534 
9535 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
9536 {
9537 	if (is_64_bit_mode(vcpu))
9538 		return kvm_rip_read(vcpu);
9539 	return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9540 		     kvm_rip_read(vcpu));
9541 }
9542 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
9543 
9544 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9545 {
9546 	return kvm_get_linear_rip(vcpu) == linear_rip;
9547 }
9548 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9549 
9550 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9551 {
9552 	unsigned long rflags;
9553 
9554 	rflags = kvm_x86_ops->get_rflags(vcpu);
9555 	if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9556 		rflags &= ~X86_EFLAGS_TF;
9557 	return rflags;
9558 }
9559 EXPORT_SYMBOL_GPL(kvm_get_rflags);
9560 
9561 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9562 {
9563 	if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
9564 	    kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
9565 		rflags |= X86_EFLAGS_TF;
9566 	kvm_x86_ops->set_rflags(vcpu, rflags);
9567 }
9568 
9569 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9570 {
9571 	__kvm_set_rflags(vcpu, rflags);
9572 	kvm_make_request(KVM_REQ_EVENT, vcpu);
9573 }
9574 EXPORT_SYMBOL_GPL(kvm_set_rflags);
9575 
9576 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9577 {
9578 	int r;
9579 
9580 	if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
9581 	      work->wakeup_all)
9582 		return;
9583 
9584 	r = kvm_mmu_reload(vcpu);
9585 	if (unlikely(r))
9586 		return;
9587 
9588 	if (!vcpu->arch.mmu->direct_map &&
9589 	      work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
9590 		return;
9591 
9592 	vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
9593 }
9594 
9595 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9596 {
9597 	return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9598 }
9599 
9600 static inline u32 kvm_async_pf_next_probe(u32 key)
9601 {
9602 	return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9603 }
9604 
9605 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9606 {
9607 	u32 key = kvm_async_pf_hash_fn(gfn);
9608 
9609 	while (vcpu->arch.apf.gfns[key] != ~0)
9610 		key = kvm_async_pf_next_probe(key);
9611 
9612 	vcpu->arch.apf.gfns[key] = gfn;
9613 }
9614 
9615 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9616 {
9617 	int i;
9618 	u32 key = kvm_async_pf_hash_fn(gfn);
9619 
9620 	for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
9621 		     (vcpu->arch.apf.gfns[key] != gfn &&
9622 		      vcpu->arch.apf.gfns[key] != ~0); i++)
9623 		key = kvm_async_pf_next_probe(key);
9624 
9625 	return key;
9626 }
9627 
9628 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9629 {
9630 	return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9631 }
9632 
9633 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9634 {
9635 	u32 i, j, k;
9636 
9637 	i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9638 	while (true) {
9639 		vcpu->arch.apf.gfns[i] = ~0;
9640 		do {
9641 			j = kvm_async_pf_next_probe(j);
9642 			if (vcpu->arch.apf.gfns[j] == ~0)
9643 				return;
9644 			k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9645 			/*
9646 			 * k lies cyclically in ]i,j]
9647 			 * |    i.k.j |
9648 			 * |....j i.k.| or  |.k..j i...|
9649 			 */
9650 		} while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9651 		vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9652 		i = j;
9653 	}
9654 }
9655 
9656 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9657 {
9658 
9659 	return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9660 				      sizeof(val));
9661 }
9662 
9663 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9664 {
9665 
9666 	return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9667 				      sizeof(u32));
9668 }
9669 
9670 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9671 				     struct kvm_async_pf *work)
9672 {
9673 	struct x86_exception fault;
9674 
9675 	trace_kvm_async_pf_not_present(work->arch.token, work->gva);
9676 	kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
9677 
9678 	if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
9679 	    (vcpu->arch.apf.send_user_only &&
9680 	     kvm_x86_ops->get_cpl(vcpu) == 0))
9681 		kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9682 	else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
9683 		fault.vector = PF_VECTOR;
9684 		fault.error_code_valid = true;
9685 		fault.error_code = 0;
9686 		fault.nested_page_fault = false;
9687 		fault.address = work->arch.token;
9688 		fault.async_page_fault = true;
9689 		kvm_inject_page_fault(vcpu, &fault);
9690 	}
9691 }
9692 
9693 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9694 				 struct kvm_async_pf *work)
9695 {
9696 	struct x86_exception fault;
9697 	u32 val;
9698 
9699 	if (work->wakeup_all)
9700 		work->arch.token = ~0; /* broadcast wakeup */
9701 	else
9702 		kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
9703 	trace_kvm_async_pf_ready(work->arch.token, work->gva);
9704 
9705 	if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9706 	    !apf_get_user(vcpu, &val)) {
9707 		if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9708 		    vcpu->arch.exception.pending &&
9709 		    vcpu->arch.exception.nr == PF_VECTOR &&
9710 		    !apf_put_user(vcpu, 0)) {
9711 			vcpu->arch.exception.injected = false;
9712 			vcpu->arch.exception.pending = false;
9713 			vcpu->arch.exception.nr = 0;
9714 			vcpu->arch.exception.has_error_code = false;
9715 			vcpu->arch.exception.error_code = 0;
9716 			vcpu->arch.exception.has_payload = false;
9717 			vcpu->arch.exception.payload = 0;
9718 		} else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9719 			fault.vector = PF_VECTOR;
9720 			fault.error_code_valid = true;
9721 			fault.error_code = 0;
9722 			fault.nested_page_fault = false;
9723 			fault.address = work->arch.token;
9724 			fault.async_page_fault = true;
9725 			kvm_inject_page_fault(vcpu, &fault);
9726 		}
9727 	}
9728 	vcpu->arch.apf.halted = false;
9729 	vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9730 }
9731 
9732 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9733 {
9734 	if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9735 		return true;
9736 	else
9737 		return kvm_can_do_async_pf(vcpu);
9738 }
9739 
9740 void kvm_arch_start_assignment(struct kvm *kvm)
9741 {
9742 	atomic_inc(&kvm->arch.assigned_device_count);
9743 }
9744 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9745 
9746 void kvm_arch_end_assignment(struct kvm *kvm)
9747 {
9748 	atomic_dec(&kvm->arch.assigned_device_count);
9749 }
9750 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9751 
9752 bool kvm_arch_has_assigned_device(struct kvm *kvm)
9753 {
9754 	return atomic_read(&kvm->arch.assigned_device_count);
9755 }
9756 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9757 
9758 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9759 {
9760 	atomic_inc(&kvm->arch.noncoherent_dma_count);
9761 }
9762 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9763 
9764 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9765 {
9766 	atomic_dec(&kvm->arch.noncoherent_dma_count);
9767 }
9768 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9769 
9770 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9771 {
9772 	return atomic_read(&kvm->arch.noncoherent_dma_count);
9773 }
9774 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9775 
9776 bool kvm_arch_has_irq_bypass(void)
9777 {
9778 	return kvm_x86_ops->update_pi_irte != NULL;
9779 }
9780 
9781 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9782 				      struct irq_bypass_producer *prod)
9783 {
9784 	struct kvm_kernel_irqfd *irqfd =
9785 		container_of(cons, struct kvm_kernel_irqfd, consumer);
9786 
9787 	irqfd->producer = prod;
9788 
9789 	return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9790 					   prod->irq, irqfd->gsi, 1);
9791 }
9792 
9793 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9794 				      struct irq_bypass_producer *prod)
9795 {
9796 	int ret;
9797 	struct kvm_kernel_irqfd *irqfd =
9798 		container_of(cons, struct kvm_kernel_irqfd, consumer);
9799 
9800 	WARN_ON(irqfd->producer != prod);
9801 	irqfd->producer = NULL;
9802 
9803 	/*
9804 	 * When producer of consumer is unregistered, we change back to
9805 	 * remapped mode, so we can re-use the current implementation
9806 	 * when the irq is masked/disabled or the consumer side (KVM
9807 	 * int this case doesn't want to receive the interrupts.
9808 	*/
9809 	ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9810 	if (ret)
9811 		printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9812 		       " fails: %d\n", irqfd->consumer.token, ret);
9813 }
9814 
9815 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9816 				   uint32_t guest_irq, bool set)
9817 {
9818 	if (!kvm_x86_ops->update_pi_irte)
9819 		return -EINVAL;
9820 
9821 	return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9822 }
9823 
9824 bool kvm_vector_hashing_enabled(void)
9825 {
9826 	return vector_hashing;
9827 }
9828 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9829 
9830 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
9831 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
9832 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9833 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9834 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9835 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
9836 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
9837 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
9838 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
9839 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
9840 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
9841 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
9842 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
9843 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
9844 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
9845 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
9846 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
9847 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9848 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
9849