1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "pmu.h" 31 #include "hyperv.h" 32 33 #include <linux/clocksource.h> 34 #include <linux/interrupt.h> 35 #include <linux/kvm.h> 36 #include <linux/fs.h> 37 #include <linux/vmalloc.h> 38 #include <linux/export.h> 39 #include <linux/moduleparam.h> 40 #include <linux/mman.h> 41 #include <linux/highmem.h> 42 #include <linux/iommu.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/cpufreq.h> 45 #include <linux/user-return-notifier.h> 46 #include <linux/srcu.h> 47 #include <linux/slab.h> 48 #include <linux/perf_event.h> 49 #include <linux/uaccess.h> 50 #include <linux/hash.h> 51 #include <linux/pci.h> 52 #include <linux/timekeeper_internal.h> 53 #include <linux/pvclock_gtod.h> 54 #include <linux/kvm_irqfd.h> 55 #include <linux/irqbypass.h> 56 #include <linux/sched/stat.h> 57 #include <linux/mem_encrypt.h> 58 59 #include <trace/events/kvm.h> 60 61 #include <asm/debugreg.h> 62 #include <asm/msr.h> 63 #include <asm/desc.h> 64 #include <asm/mce.h> 65 #include <linux/kernel_stat.h> 66 #include <asm/fpu/internal.h> /* Ugh! */ 67 #include <asm/pvclock.h> 68 #include <asm/div64.h> 69 #include <asm/irq_remapping.h> 70 #include <asm/mshyperv.h> 71 #include <asm/hypervisor.h> 72 73 #define CREATE_TRACE_POINTS 74 #include "trace.h" 75 76 #define MAX_IO_MSRS 256 77 #define KVM_MAX_MCE_BANKS 32 78 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 79 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 80 81 #define emul_to_vcpu(ctxt) \ 82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 83 84 /* EFER defaults: 85 * - enable syscall per default because its emulated by KVM 86 * - enable LME and LMA per default on 64 bit KVM 87 */ 88 #ifdef CONFIG_X86_64 89 static 90 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 91 #else 92 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 93 #endif 94 95 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 96 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 97 98 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 100 101 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 102 static void process_nmi(struct kvm_vcpu *vcpu); 103 static void enter_smm(struct kvm_vcpu *vcpu); 104 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 105 106 struct kvm_x86_ops *kvm_x86_ops __read_mostly; 107 EXPORT_SYMBOL_GPL(kvm_x86_ops); 108 109 static bool __read_mostly ignore_msrs = 0; 110 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 111 112 static bool __read_mostly report_ignored_msrs = true; 113 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 114 115 unsigned int min_timer_period_us = 500; 116 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 117 118 static bool __read_mostly kvmclock_periodic_sync = true; 119 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 120 121 bool __read_mostly kvm_has_tsc_control; 122 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 123 u32 __read_mostly kvm_max_guest_tsc_khz; 124 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 125 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 126 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 127 u64 __read_mostly kvm_max_tsc_scaling_ratio; 128 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 129 u64 __read_mostly kvm_default_tsc_scaling_ratio; 130 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 131 132 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 133 static u32 __read_mostly tsc_tolerance_ppm = 250; 134 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 135 136 /* lapic timer advance (tscdeadline mode only) in nanoseconds */ 137 unsigned int __read_mostly lapic_timer_advance_ns = 0; 138 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 139 140 static bool __read_mostly vector_hashing = true; 141 module_param(vector_hashing, bool, S_IRUGO); 142 143 #define KVM_NR_SHARED_MSRS 16 144 145 struct kvm_shared_msrs_global { 146 int nr; 147 u32 msrs[KVM_NR_SHARED_MSRS]; 148 }; 149 150 struct kvm_shared_msrs { 151 struct user_return_notifier urn; 152 bool registered; 153 struct kvm_shared_msr_values { 154 u64 host; 155 u64 curr; 156 } values[KVM_NR_SHARED_MSRS]; 157 }; 158 159 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 160 static struct kvm_shared_msrs __percpu *shared_msrs; 161 162 struct kvm_stats_debugfs_item debugfs_entries[] = { 163 { "pf_fixed", VCPU_STAT(pf_fixed) }, 164 { "pf_guest", VCPU_STAT(pf_guest) }, 165 { "tlb_flush", VCPU_STAT(tlb_flush) }, 166 { "invlpg", VCPU_STAT(invlpg) }, 167 { "exits", VCPU_STAT(exits) }, 168 { "io_exits", VCPU_STAT(io_exits) }, 169 { "mmio_exits", VCPU_STAT(mmio_exits) }, 170 { "signal_exits", VCPU_STAT(signal_exits) }, 171 { "irq_window", VCPU_STAT(irq_window_exits) }, 172 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 173 { "halt_exits", VCPU_STAT(halt_exits) }, 174 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 175 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 176 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, 177 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 178 { "hypercalls", VCPU_STAT(hypercalls) }, 179 { "request_irq", VCPU_STAT(request_irq_exits) }, 180 { "irq_exits", VCPU_STAT(irq_exits) }, 181 { "host_state_reload", VCPU_STAT(host_state_reload) }, 182 { "fpu_reload", VCPU_STAT(fpu_reload) }, 183 { "insn_emulation", VCPU_STAT(insn_emulation) }, 184 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 185 { "irq_injections", VCPU_STAT(irq_injections) }, 186 { "nmi_injections", VCPU_STAT(nmi_injections) }, 187 { "req_event", VCPU_STAT(req_event) }, 188 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 189 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 190 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 191 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 192 { "mmu_flooded", VM_STAT(mmu_flooded) }, 193 { "mmu_recycled", VM_STAT(mmu_recycled) }, 194 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 195 { "mmu_unsync", VM_STAT(mmu_unsync) }, 196 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 197 { "largepages", VM_STAT(lpages) }, 198 { "max_mmu_page_hash_collisions", 199 VM_STAT(max_mmu_page_hash_collisions) }, 200 { NULL } 201 }; 202 203 u64 __read_mostly host_xcr0; 204 205 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 206 207 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 208 { 209 int i; 210 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 211 vcpu->arch.apf.gfns[i] = ~0; 212 } 213 214 static void kvm_on_user_return(struct user_return_notifier *urn) 215 { 216 unsigned slot; 217 struct kvm_shared_msrs *locals 218 = container_of(urn, struct kvm_shared_msrs, urn); 219 struct kvm_shared_msr_values *values; 220 unsigned long flags; 221 222 /* 223 * Disabling irqs at this point since the following code could be 224 * interrupted and executed through kvm_arch_hardware_disable() 225 */ 226 local_irq_save(flags); 227 if (locals->registered) { 228 locals->registered = false; 229 user_return_notifier_unregister(urn); 230 } 231 local_irq_restore(flags); 232 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 233 values = &locals->values[slot]; 234 if (values->host != values->curr) { 235 wrmsrl(shared_msrs_global.msrs[slot], values->host); 236 values->curr = values->host; 237 } 238 } 239 } 240 241 static void shared_msr_update(unsigned slot, u32 msr) 242 { 243 u64 value; 244 unsigned int cpu = smp_processor_id(); 245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 246 247 /* only read, and nobody should modify it at this time, 248 * so don't need lock */ 249 if (slot >= shared_msrs_global.nr) { 250 printk(KERN_ERR "kvm: invalid MSR slot!"); 251 return; 252 } 253 rdmsrl_safe(msr, &value); 254 smsr->values[slot].host = value; 255 smsr->values[slot].curr = value; 256 } 257 258 void kvm_define_shared_msr(unsigned slot, u32 msr) 259 { 260 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 261 shared_msrs_global.msrs[slot] = msr; 262 if (slot >= shared_msrs_global.nr) 263 shared_msrs_global.nr = slot + 1; 264 } 265 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 266 267 static void kvm_shared_msr_cpu_online(void) 268 { 269 unsigned i; 270 271 for (i = 0; i < shared_msrs_global.nr; ++i) 272 shared_msr_update(i, shared_msrs_global.msrs[i]); 273 } 274 275 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 276 { 277 unsigned int cpu = smp_processor_id(); 278 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 279 int err; 280 281 if (((value ^ smsr->values[slot].curr) & mask) == 0) 282 return 0; 283 smsr->values[slot].curr = value; 284 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 285 if (err) 286 return 1; 287 288 if (!smsr->registered) { 289 smsr->urn.on_user_return = kvm_on_user_return; 290 user_return_notifier_register(&smsr->urn); 291 smsr->registered = true; 292 } 293 return 0; 294 } 295 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 296 297 static void drop_user_return_notifiers(void) 298 { 299 unsigned int cpu = smp_processor_id(); 300 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 301 302 if (smsr->registered) 303 kvm_on_user_return(&smsr->urn); 304 } 305 306 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 307 { 308 return vcpu->arch.apic_base; 309 } 310 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 311 312 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 313 { 314 u64 old_state = vcpu->arch.apic_base & 315 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 316 u64 new_state = msr_info->data & 317 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 318 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | 319 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 320 321 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE) 322 return 1; 323 if (!msr_info->host_initiated && 324 ((new_state == MSR_IA32_APICBASE_ENABLE && 325 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 326 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 327 old_state == 0))) 328 return 1; 329 330 kvm_lapic_set_base(vcpu, msr_info->data); 331 return 0; 332 } 333 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 334 335 asmlinkage __visible void kvm_spurious_fault(void) 336 { 337 /* Fault while not rebooting. We want the trace. */ 338 BUG(); 339 } 340 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 341 342 #define EXCPT_BENIGN 0 343 #define EXCPT_CONTRIBUTORY 1 344 #define EXCPT_PF 2 345 346 static int exception_class(int vector) 347 { 348 switch (vector) { 349 case PF_VECTOR: 350 return EXCPT_PF; 351 case DE_VECTOR: 352 case TS_VECTOR: 353 case NP_VECTOR: 354 case SS_VECTOR: 355 case GP_VECTOR: 356 return EXCPT_CONTRIBUTORY; 357 default: 358 break; 359 } 360 return EXCPT_BENIGN; 361 } 362 363 #define EXCPT_FAULT 0 364 #define EXCPT_TRAP 1 365 #define EXCPT_ABORT 2 366 #define EXCPT_INTERRUPT 3 367 368 static int exception_type(int vector) 369 { 370 unsigned int mask; 371 372 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 373 return EXCPT_INTERRUPT; 374 375 mask = 1 << vector; 376 377 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 378 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 379 return EXCPT_TRAP; 380 381 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 382 return EXCPT_ABORT; 383 384 /* Reserved exceptions will result in fault */ 385 return EXCPT_FAULT; 386 } 387 388 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 389 unsigned nr, bool has_error, u32 error_code, 390 bool reinject) 391 { 392 u32 prev_nr; 393 int class1, class2; 394 395 kvm_make_request(KVM_REQ_EVENT, vcpu); 396 397 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 398 queue: 399 if (has_error && !is_protmode(vcpu)) 400 has_error = false; 401 if (reinject) { 402 /* 403 * On vmentry, vcpu->arch.exception.pending is only 404 * true if an event injection was blocked by 405 * nested_run_pending. In that case, however, 406 * vcpu_enter_guest requests an immediate exit, 407 * and the guest shouldn't proceed far enough to 408 * need reinjection. 409 */ 410 WARN_ON_ONCE(vcpu->arch.exception.pending); 411 vcpu->arch.exception.injected = true; 412 } else { 413 vcpu->arch.exception.pending = true; 414 vcpu->arch.exception.injected = false; 415 } 416 vcpu->arch.exception.has_error_code = has_error; 417 vcpu->arch.exception.nr = nr; 418 vcpu->arch.exception.error_code = error_code; 419 return; 420 } 421 422 /* to check exception */ 423 prev_nr = vcpu->arch.exception.nr; 424 if (prev_nr == DF_VECTOR) { 425 /* triple fault -> shutdown */ 426 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 427 return; 428 } 429 class1 = exception_class(prev_nr); 430 class2 = exception_class(nr); 431 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 432 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 433 /* 434 * Generate double fault per SDM Table 5-5. Set 435 * exception.pending = true so that the double fault 436 * can trigger a nested vmexit. 437 */ 438 vcpu->arch.exception.pending = true; 439 vcpu->arch.exception.injected = false; 440 vcpu->arch.exception.has_error_code = true; 441 vcpu->arch.exception.nr = DF_VECTOR; 442 vcpu->arch.exception.error_code = 0; 443 } else 444 /* replace previous exception with a new one in a hope 445 that instruction re-execution will regenerate lost 446 exception */ 447 goto queue; 448 } 449 450 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 451 { 452 kvm_multiple_exception(vcpu, nr, false, 0, false); 453 } 454 EXPORT_SYMBOL_GPL(kvm_queue_exception); 455 456 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 457 { 458 kvm_multiple_exception(vcpu, nr, false, 0, true); 459 } 460 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 461 462 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 463 { 464 if (err) 465 kvm_inject_gp(vcpu, 0); 466 else 467 return kvm_skip_emulated_instruction(vcpu); 468 469 return 1; 470 } 471 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 472 473 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 474 { 475 ++vcpu->stat.pf_guest; 476 vcpu->arch.exception.nested_apf = 477 is_guest_mode(vcpu) && fault->async_page_fault; 478 if (vcpu->arch.exception.nested_apf) 479 vcpu->arch.apf.nested_apf_token = fault->address; 480 else 481 vcpu->arch.cr2 = fault->address; 482 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 483 } 484 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 485 486 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 487 { 488 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 489 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 490 else 491 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 492 493 return fault->nested_page_fault; 494 } 495 496 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 497 { 498 atomic_inc(&vcpu->arch.nmi_queued); 499 kvm_make_request(KVM_REQ_NMI, vcpu); 500 } 501 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 502 503 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 504 { 505 kvm_multiple_exception(vcpu, nr, true, error_code, false); 506 } 507 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 508 509 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 510 { 511 kvm_multiple_exception(vcpu, nr, true, error_code, true); 512 } 513 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 514 515 /* 516 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 517 * a #GP and return false. 518 */ 519 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 520 { 521 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 522 return true; 523 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 524 return false; 525 } 526 EXPORT_SYMBOL_GPL(kvm_require_cpl); 527 528 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 529 { 530 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 531 return true; 532 533 kvm_queue_exception(vcpu, UD_VECTOR); 534 return false; 535 } 536 EXPORT_SYMBOL_GPL(kvm_require_dr); 537 538 /* 539 * This function will be used to read from the physical memory of the currently 540 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 541 * can read from guest physical or from the guest's guest physical memory. 542 */ 543 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 544 gfn_t ngfn, void *data, int offset, int len, 545 u32 access) 546 { 547 struct x86_exception exception; 548 gfn_t real_gfn; 549 gpa_t ngpa; 550 551 ngpa = gfn_to_gpa(ngfn); 552 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 553 if (real_gfn == UNMAPPED_GVA) 554 return -EFAULT; 555 556 real_gfn = gpa_to_gfn(real_gfn); 557 558 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 559 } 560 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 561 562 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 563 void *data, int offset, int len, u32 access) 564 { 565 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 566 data, offset, len, access); 567 } 568 569 /* 570 * Load the pae pdptrs. Return true is they are all valid. 571 */ 572 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 573 { 574 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 575 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 576 int i; 577 int ret; 578 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 579 580 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 581 offset * sizeof(u64), sizeof(pdpte), 582 PFERR_USER_MASK|PFERR_WRITE_MASK); 583 if (ret < 0) { 584 ret = 0; 585 goto out; 586 } 587 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 588 if ((pdpte[i] & PT_PRESENT_MASK) && 589 (pdpte[i] & 590 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) { 591 ret = 0; 592 goto out; 593 } 594 } 595 ret = 1; 596 597 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 598 __set_bit(VCPU_EXREG_PDPTR, 599 (unsigned long *)&vcpu->arch.regs_avail); 600 __set_bit(VCPU_EXREG_PDPTR, 601 (unsigned long *)&vcpu->arch.regs_dirty); 602 out: 603 604 return ret; 605 } 606 EXPORT_SYMBOL_GPL(load_pdptrs); 607 608 bool pdptrs_changed(struct kvm_vcpu *vcpu) 609 { 610 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 611 bool changed = true; 612 int offset; 613 gfn_t gfn; 614 int r; 615 616 if (is_long_mode(vcpu) || !is_pae(vcpu)) 617 return false; 618 619 if (!test_bit(VCPU_EXREG_PDPTR, 620 (unsigned long *)&vcpu->arch.regs_avail)) 621 return true; 622 623 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; 624 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); 625 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 626 PFERR_USER_MASK | PFERR_WRITE_MASK); 627 if (r < 0) 628 goto out; 629 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 630 out: 631 632 return changed; 633 } 634 EXPORT_SYMBOL_GPL(pdptrs_changed); 635 636 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 637 { 638 unsigned long old_cr0 = kvm_read_cr0(vcpu); 639 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 640 641 cr0 |= X86_CR0_ET; 642 643 #ifdef CONFIG_X86_64 644 if (cr0 & 0xffffffff00000000UL) 645 return 1; 646 #endif 647 648 cr0 &= ~CR0_RESERVED_BITS; 649 650 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 651 return 1; 652 653 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 654 return 1; 655 656 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 657 #ifdef CONFIG_X86_64 658 if ((vcpu->arch.efer & EFER_LME)) { 659 int cs_db, cs_l; 660 661 if (!is_pae(vcpu)) 662 return 1; 663 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 664 if (cs_l) 665 return 1; 666 } else 667 #endif 668 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 669 kvm_read_cr3(vcpu))) 670 return 1; 671 } 672 673 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 674 return 1; 675 676 kvm_x86_ops->set_cr0(vcpu, cr0); 677 678 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 679 kvm_clear_async_pf_completion_queue(vcpu); 680 kvm_async_pf_hash_reset(vcpu); 681 } 682 683 if ((cr0 ^ old_cr0) & update_bits) 684 kvm_mmu_reset_context(vcpu); 685 686 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 687 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 688 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 689 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 690 691 return 0; 692 } 693 EXPORT_SYMBOL_GPL(kvm_set_cr0); 694 695 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 696 { 697 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 698 } 699 EXPORT_SYMBOL_GPL(kvm_lmsw); 700 701 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 702 { 703 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 704 !vcpu->guest_xcr0_loaded) { 705 /* kvm_set_xcr() also depends on this */ 706 if (vcpu->arch.xcr0 != host_xcr0) 707 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 708 vcpu->guest_xcr0_loaded = 1; 709 } 710 } 711 712 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 713 { 714 if (vcpu->guest_xcr0_loaded) { 715 if (vcpu->arch.xcr0 != host_xcr0) 716 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 717 vcpu->guest_xcr0_loaded = 0; 718 } 719 } 720 721 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 722 { 723 u64 xcr0 = xcr; 724 u64 old_xcr0 = vcpu->arch.xcr0; 725 u64 valid_bits; 726 727 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 728 if (index != XCR_XFEATURE_ENABLED_MASK) 729 return 1; 730 if (!(xcr0 & XFEATURE_MASK_FP)) 731 return 1; 732 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 733 return 1; 734 735 /* 736 * Do not allow the guest to set bits that we do not support 737 * saving. However, xcr0 bit 0 is always set, even if the 738 * emulated CPU does not support XSAVE (see fx_init). 739 */ 740 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 741 if (xcr0 & ~valid_bits) 742 return 1; 743 744 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 745 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 746 return 1; 747 748 if (xcr0 & XFEATURE_MASK_AVX512) { 749 if (!(xcr0 & XFEATURE_MASK_YMM)) 750 return 1; 751 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 752 return 1; 753 } 754 vcpu->arch.xcr0 = xcr0; 755 756 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 757 kvm_update_cpuid(vcpu); 758 return 0; 759 } 760 761 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 762 { 763 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 764 __kvm_set_xcr(vcpu, index, xcr)) { 765 kvm_inject_gp(vcpu, 0); 766 return 1; 767 } 768 return 0; 769 } 770 EXPORT_SYMBOL_GPL(kvm_set_xcr); 771 772 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 773 { 774 unsigned long old_cr4 = kvm_read_cr4(vcpu); 775 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 776 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 777 778 if (cr4 & CR4_RESERVED_BITS) 779 return 1; 780 781 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE)) 782 return 1; 783 784 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP)) 785 return 1; 786 787 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP)) 788 return 1; 789 790 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE)) 791 return 1; 792 793 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE)) 794 return 1; 795 796 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57)) 797 return 1; 798 799 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP)) 800 return 1; 801 802 if (is_long_mode(vcpu)) { 803 if (!(cr4 & X86_CR4_PAE)) 804 return 1; 805 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 806 && ((cr4 ^ old_cr4) & pdptr_bits) 807 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 808 kvm_read_cr3(vcpu))) 809 return 1; 810 811 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 812 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 813 return 1; 814 815 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 816 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 817 return 1; 818 } 819 820 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 821 return 1; 822 823 if (((cr4 ^ old_cr4) & pdptr_bits) || 824 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 825 kvm_mmu_reset_context(vcpu); 826 827 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 828 kvm_update_cpuid(vcpu); 829 830 return 0; 831 } 832 EXPORT_SYMBOL_GPL(kvm_set_cr4); 833 834 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 835 { 836 #ifdef CONFIG_X86_64 837 cr3 &= ~CR3_PCID_INVD; 838 #endif 839 840 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 841 kvm_mmu_sync_roots(vcpu); 842 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 843 return 0; 844 } 845 846 if (is_long_mode(vcpu) && 847 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62))) 848 return 1; 849 else if (is_pae(vcpu) && is_paging(vcpu) && 850 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 851 return 1; 852 853 vcpu->arch.cr3 = cr3; 854 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 855 kvm_mmu_new_cr3(vcpu); 856 return 0; 857 } 858 EXPORT_SYMBOL_GPL(kvm_set_cr3); 859 860 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 861 { 862 if (cr8 & CR8_RESERVED_BITS) 863 return 1; 864 if (lapic_in_kernel(vcpu)) 865 kvm_lapic_set_tpr(vcpu, cr8); 866 else 867 vcpu->arch.cr8 = cr8; 868 return 0; 869 } 870 EXPORT_SYMBOL_GPL(kvm_set_cr8); 871 872 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 873 { 874 if (lapic_in_kernel(vcpu)) 875 return kvm_lapic_get_cr8(vcpu); 876 else 877 return vcpu->arch.cr8; 878 } 879 EXPORT_SYMBOL_GPL(kvm_get_cr8); 880 881 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 882 { 883 int i; 884 885 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 886 for (i = 0; i < KVM_NR_DB_REGS; i++) 887 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 888 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 889 } 890 } 891 892 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 893 { 894 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 895 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 896 } 897 898 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 899 { 900 unsigned long dr7; 901 902 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 903 dr7 = vcpu->arch.guest_debug_dr7; 904 else 905 dr7 = vcpu->arch.dr7; 906 kvm_x86_ops->set_dr7(vcpu, dr7); 907 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 908 if (dr7 & DR7_BP_EN_MASK) 909 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 910 } 911 912 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 913 { 914 u64 fixed = DR6_FIXED_1; 915 916 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 917 fixed |= DR6_RTM; 918 return fixed; 919 } 920 921 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 922 { 923 switch (dr) { 924 case 0 ... 3: 925 vcpu->arch.db[dr] = val; 926 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 927 vcpu->arch.eff_db[dr] = val; 928 break; 929 case 4: 930 /* fall through */ 931 case 6: 932 if (val & 0xffffffff00000000ULL) 933 return -1; /* #GP */ 934 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 935 kvm_update_dr6(vcpu); 936 break; 937 case 5: 938 /* fall through */ 939 default: /* 7 */ 940 if (val & 0xffffffff00000000ULL) 941 return -1; /* #GP */ 942 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 943 kvm_update_dr7(vcpu); 944 break; 945 } 946 947 return 0; 948 } 949 950 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 951 { 952 if (__kvm_set_dr(vcpu, dr, val)) { 953 kvm_inject_gp(vcpu, 0); 954 return 1; 955 } 956 return 0; 957 } 958 EXPORT_SYMBOL_GPL(kvm_set_dr); 959 960 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 961 { 962 switch (dr) { 963 case 0 ... 3: 964 *val = vcpu->arch.db[dr]; 965 break; 966 case 4: 967 /* fall through */ 968 case 6: 969 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 970 *val = vcpu->arch.dr6; 971 else 972 *val = kvm_x86_ops->get_dr6(vcpu); 973 break; 974 case 5: 975 /* fall through */ 976 default: /* 7 */ 977 *val = vcpu->arch.dr7; 978 break; 979 } 980 return 0; 981 } 982 EXPORT_SYMBOL_GPL(kvm_get_dr); 983 984 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 985 { 986 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 987 u64 data; 988 int err; 989 990 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 991 if (err) 992 return err; 993 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 994 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 995 return err; 996 } 997 EXPORT_SYMBOL_GPL(kvm_rdpmc); 998 999 /* 1000 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1001 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1002 * 1003 * This list is modified at module load time to reflect the 1004 * capabilities of the host cpu. This capabilities test skips MSRs that are 1005 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs 1006 * may depend on host virtualization features rather than host cpu features. 1007 */ 1008 1009 static u32 msrs_to_save[] = { 1010 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1011 MSR_STAR, 1012 #ifdef CONFIG_X86_64 1013 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1014 #endif 1015 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1016 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1017 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES 1018 }; 1019 1020 static unsigned num_msrs_to_save; 1021 1022 static u32 emulated_msrs[] = { 1023 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1024 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1025 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1026 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1027 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1028 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1029 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1030 HV_X64_MSR_RESET, 1031 HV_X64_MSR_VP_INDEX, 1032 HV_X64_MSR_VP_RUNTIME, 1033 HV_X64_MSR_SCONTROL, 1034 HV_X64_MSR_STIMER0_CONFIG, 1035 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1036 MSR_KVM_PV_EOI_EN, 1037 1038 MSR_IA32_TSC_ADJUST, 1039 MSR_IA32_TSCDEADLINE, 1040 MSR_IA32_MISC_ENABLE, 1041 MSR_IA32_MCG_STATUS, 1042 MSR_IA32_MCG_CTL, 1043 MSR_IA32_MCG_EXT_CTL, 1044 MSR_IA32_SMBASE, 1045 MSR_SMI_COUNT, 1046 MSR_PLATFORM_INFO, 1047 MSR_MISC_FEATURES_ENABLES, 1048 }; 1049 1050 static unsigned num_emulated_msrs; 1051 1052 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1053 { 1054 if (efer & efer_reserved_bits) 1055 return false; 1056 1057 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1058 return false; 1059 1060 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1061 return false; 1062 1063 return true; 1064 } 1065 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1066 1067 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 1068 { 1069 u64 old_efer = vcpu->arch.efer; 1070 1071 if (!kvm_valid_efer(vcpu, efer)) 1072 return 1; 1073 1074 if (is_paging(vcpu) 1075 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1076 return 1; 1077 1078 efer &= ~EFER_LMA; 1079 efer |= vcpu->arch.efer & EFER_LMA; 1080 1081 kvm_x86_ops->set_efer(vcpu, efer); 1082 1083 /* Update reserved bits */ 1084 if ((efer ^ old_efer) & EFER_NX) 1085 kvm_mmu_reset_context(vcpu); 1086 1087 return 0; 1088 } 1089 1090 void kvm_enable_efer_bits(u64 mask) 1091 { 1092 efer_reserved_bits &= ~mask; 1093 } 1094 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1095 1096 /* 1097 * Writes msr value into into the appropriate "register". 1098 * Returns 0 on success, non-0 otherwise. 1099 * Assumes vcpu_load() was already called. 1100 */ 1101 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1102 { 1103 switch (msr->index) { 1104 case MSR_FS_BASE: 1105 case MSR_GS_BASE: 1106 case MSR_KERNEL_GS_BASE: 1107 case MSR_CSTAR: 1108 case MSR_LSTAR: 1109 if (is_noncanonical_address(msr->data, vcpu)) 1110 return 1; 1111 break; 1112 case MSR_IA32_SYSENTER_EIP: 1113 case MSR_IA32_SYSENTER_ESP: 1114 /* 1115 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1116 * non-canonical address is written on Intel but not on 1117 * AMD (which ignores the top 32-bits, because it does 1118 * not implement 64-bit SYSENTER). 1119 * 1120 * 64-bit code should hence be able to write a non-canonical 1121 * value on AMD. Making the address canonical ensures that 1122 * vmentry does not fail on Intel after writing a non-canonical 1123 * value, and that something deterministic happens if the guest 1124 * invokes 64-bit SYSENTER. 1125 */ 1126 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu)); 1127 } 1128 return kvm_x86_ops->set_msr(vcpu, msr); 1129 } 1130 EXPORT_SYMBOL_GPL(kvm_set_msr); 1131 1132 /* 1133 * Adapt set_msr() to msr_io()'s calling convention 1134 */ 1135 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1136 { 1137 struct msr_data msr; 1138 int r; 1139 1140 msr.index = index; 1141 msr.host_initiated = true; 1142 r = kvm_get_msr(vcpu, &msr); 1143 if (r) 1144 return r; 1145 1146 *data = msr.data; 1147 return 0; 1148 } 1149 1150 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1151 { 1152 struct msr_data msr; 1153 1154 msr.data = *data; 1155 msr.index = index; 1156 msr.host_initiated = true; 1157 return kvm_set_msr(vcpu, &msr); 1158 } 1159 1160 #ifdef CONFIG_X86_64 1161 struct pvclock_gtod_data { 1162 seqcount_t seq; 1163 1164 struct { /* extract of a clocksource struct */ 1165 int vclock_mode; 1166 u64 cycle_last; 1167 u64 mask; 1168 u32 mult; 1169 u32 shift; 1170 } clock; 1171 1172 u64 boot_ns; 1173 u64 nsec_base; 1174 u64 wall_time_sec; 1175 }; 1176 1177 static struct pvclock_gtod_data pvclock_gtod_data; 1178 1179 static void update_pvclock_gtod(struct timekeeper *tk) 1180 { 1181 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1182 u64 boot_ns; 1183 1184 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1185 1186 write_seqcount_begin(&vdata->seq); 1187 1188 /* copy pvclock gtod data */ 1189 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1190 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1191 vdata->clock.mask = tk->tkr_mono.mask; 1192 vdata->clock.mult = tk->tkr_mono.mult; 1193 vdata->clock.shift = tk->tkr_mono.shift; 1194 1195 vdata->boot_ns = boot_ns; 1196 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1197 1198 vdata->wall_time_sec = tk->xtime_sec; 1199 1200 write_seqcount_end(&vdata->seq); 1201 } 1202 #endif 1203 1204 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1205 { 1206 /* 1207 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1208 * vcpu_enter_guest. This function is only called from 1209 * the physical CPU that is running vcpu. 1210 */ 1211 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1212 } 1213 1214 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1215 { 1216 int version; 1217 int r; 1218 struct pvclock_wall_clock wc; 1219 struct timespec64 boot; 1220 1221 if (!wall_clock) 1222 return; 1223 1224 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1225 if (r) 1226 return; 1227 1228 if (version & 1) 1229 ++version; /* first time write, random junk */ 1230 1231 ++version; 1232 1233 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1234 return; 1235 1236 /* 1237 * The guest calculates current wall clock time by adding 1238 * system time (updated by kvm_guest_time_update below) to the 1239 * wall clock specified here. guest system time equals host 1240 * system time for us, thus we must fill in host boot time here. 1241 */ 1242 getboottime64(&boot); 1243 1244 if (kvm->arch.kvmclock_offset) { 1245 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset); 1246 boot = timespec64_sub(boot, ts); 1247 } 1248 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */ 1249 wc.nsec = boot.tv_nsec; 1250 wc.version = version; 1251 1252 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1253 1254 version++; 1255 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1256 } 1257 1258 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1259 { 1260 do_shl32_div32(dividend, divisor); 1261 return dividend; 1262 } 1263 1264 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 1265 s8 *pshift, u32 *pmultiplier) 1266 { 1267 uint64_t scaled64; 1268 int32_t shift = 0; 1269 uint64_t tps64; 1270 uint32_t tps32; 1271 1272 tps64 = base_hz; 1273 scaled64 = scaled_hz; 1274 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1275 tps64 >>= 1; 1276 shift--; 1277 } 1278 1279 tps32 = (uint32_t)tps64; 1280 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1281 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1282 scaled64 >>= 1; 1283 else 1284 tps32 <<= 1; 1285 shift++; 1286 } 1287 1288 *pshift = shift; 1289 *pmultiplier = div_frac(scaled64, tps32); 1290 1291 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n", 1292 __func__, base_hz, scaled_hz, shift, *pmultiplier); 1293 } 1294 1295 #ifdef CONFIG_X86_64 1296 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1297 #endif 1298 1299 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1300 static unsigned long max_tsc_khz; 1301 1302 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1303 { 1304 u64 v = (u64)khz * (1000000 + ppm); 1305 do_div(v, 1000000); 1306 return v; 1307 } 1308 1309 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 1310 { 1311 u64 ratio; 1312 1313 /* Guest TSC same frequency as host TSC? */ 1314 if (!scale) { 1315 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1316 return 0; 1317 } 1318 1319 /* TSC scaling supported? */ 1320 if (!kvm_has_tsc_control) { 1321 if (user_tsc_khz > tsc_khz) { 1322 vcpu->arch.tsc_catchup = 1; 1323 vcpu->arch.tsc_always_catchup = 1; 1324 return 0; 1325 } else { 1326 WARN(1, "user requested TSC rate below hardware speed\n"); 1327 return -1; 1328 } 1329 } 1330 1331 /* TSC scaling required - calculate ratio */ 1332 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 1333 user_tsc_khz, tsc_khz); 1334 1335 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 1336 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 1337 user_tsc_khz); 1338 return -1; 1339 } 1340 1341 vcpu->arch.tsc_scaling_ratio = ratio; 1342 return 0; 1343 } 1344 1345 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 1346 { 1347 u32 thresh_lo, thresh_hi; 1348 int use_scaling = 0; 1349 1350 /* tsc_khz can be zero if TSC calibration fails */ 1351 if (user_tsc_khz == 0) { 1352 /* set tsc_scaling_ratio to a safe value */ 1353 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1354 return -1; 1355 } 1356 1357 /* Compute a scale to convert nanoseconds in TSC cycles */ 1358 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 1359 &vcpu->arch.virtual_tsc_shift, 1360 &vcpu->arch.virtual_tsc_mult); 1361 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 1362 1363 /* 1364 * Compute the variation in TSC rate which is acceptable 1365 * within the range of tolerance and decide if the 1366 * rate being applied is within that bounds of the hardware 1367 * rate. If so, no scaling or compensation need be done. 1368 */ 1369 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1370 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1371 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 1372 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 1373 use_scaling = 1; 1374 } 1375 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 1376 } 1377 1378 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1379 { 1380 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1381 vcpu->arch.virtual_tsc_mult, 1382 vcpu->arch.virtual_tsc_shift); 1383 tsc += vcpu->arch.this_tsc_write; 1384 return tsc; 1385 } 1386 1387 static inline int gtod_is_based_on_tsc(int mode) 1388 { 1389 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK; 1390 } 1391 1392 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1393 { 1394 #ifdef CONFIG_X86_64 1395 bool vcpus_matched; 1396 struct kvm_arch *ka = &vcpu->kvm->arch; 1397 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1398 1399 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1400 atomic_read(&vcpu->kvm->online_vcpus)); 1401 1402 /* 1403 * Once the masterclock is enabled, always perform request in 1404 * order to update it. 1405 * 1406 * In order to enable masterclock, the host clocksource must be TSC 1407 * and the vcpus need to have matched TSCs. When that happens, 1408 * perform request to enable masterclock. 1409 */ 1410 if (ka->use_master_clock || 1411 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 1412 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1413 1414 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1415 atomic_read(&vcpu->kvm->online_vcpus), 1416 ka->use_master_clock, gtod->clock.vclock_mode); 1417 #endif 1418 } 1419 1420 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1421 { 1422 u64 curr_offset = vcpu->arch.tsc_offset; 1423 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1424 } 1425 1426 /* 1427 * Multiply tsc by a fixed point number represented by ratio. 1428 * 1429 * The most significant 64-N bits (mult) of ratio represent the 1430 * integral part of the fixed point number; the remaining N bits 1431 * (frac) represent the fractional part, ie. ratio represents a fixed 1432 * point number (mult + frac * 2^(-N)). 1433 * 1434 * N equals to kvm_tsc_scaling_ratio_frac_bits. 1435 */ 1436 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 1437 { 1438 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 1439 } 1440 1441 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 1442 { 1443 u64 _tsc = tsc; 1444 u64 ratio = vcpu->arch.tsc_scaling_ratio; 1445 1446 if (ratio != kvm_default_tsc_scaling_ratio) 1447 _tsc = __scale_tsc(ratio, tsc); 1448 1449 return _tsc; 1450 } 1451 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 1452 1453 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 1454 { 1455 u64 tsc; 1456 1457 tsc = kvm_scale_tsc(vcpu, rdtsc()); 1458 1459 return target_tsc - tsc; 1460 } 1461 1462 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 1463 { 1464 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc); 1465 } 1466 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 1467 1468 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1469 { 1470 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1471 vcpu->arch.tsc_offset = offset; 1472 } 1473 1474 static inline bool kvm_check_tsc_unstable(void) 1475 { 1476 #ifdef CONFIG_X86_64 1477 /* 1478 * TSC is marked unstable when we're running on Hyper-V, 1479 * 'TSC page' clocksource is good. 1480 */ 1481 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK) 1482 return false; 1483 #endif 1484 return check_tsc_unstable(); 1485 } 1486 1487 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1488 { 1489 struct kvm *kvm = vcpu->kvm; 1490 u64 offset, ns, elapsed; 1491 unsigned long flags; 1492 bool matched; 1493 bool already_matched; 1494 u64 data = msr->data; 1495 bool synchronizing = false; 1496 1497 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1498 offset = kvm_compute_tsc_offset(vcpu, data); 1499 ns = ktime_get_boot_ns(); 1500 elapsed = ns - kvm->arch.last_tsc_nsec; 1501 1502 if (vcpu->arch.virtual_tsc_khz) { 1503 if (data == 0 && msr->host_initiated) { 1504 /* 1505 * detection of vcpu initialization -- need to sync 1506 * with other vCPUs. This particularly helps to keep 1507 * kvm_clock stable after CPU hotplug 1508 */ 1509 synchronizing = true; 1510 } else { 1511 u64 tsc_exp = kvm->arch.last_tsc_write + 1512 nsec_to_cycles(vcpu, elapsed); 1513 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 1514 /* 1515 * Special case: TSC write with a small delta (1 second) 1516 * of virtual cycle time against real time is 1517 * interpreted as an attempt to synchronize the CPU. 1518 */ 1519 synchronizing = data < tsc_exp + tsc_hz && 1520 data + tsc_hz > tsc_exp; 1521 } 1522 } 1523 1524 /* 1525 * For a reliable TSC, we can match TSC offsets, and for an unstable 1526 * TSC, we add elapsed time in this computation. We could let the 1527 * compensation code attempt to catch up if we fall behind, but 1528 * it's better to try to match offsets from the beginning. 1529 */ 1530 if (synchronizing && 1531 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1532 if (!kvm_check_tsc_unstable()) { 1533 offset = kvm->arch.cur_tsc_offset; 1534 pr_debug("kvm: matched tsc offset for %llu\n", data); 1535 } else { 1536 u64 delta = nsec_to_cycles(vcpu, elapsed); 1537 data += delta; 1538 offset = kvm_compute_tsc_offset(vcpu, data); 1539 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1540 } 1541 matched = true; 1542 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1543 } else { 1544 /* 1545 * We split periods of matched TSC writes into generations. 1546 * For each generation, we track the original measured 1547 * nanosecond time, offset, and write, so if TSCs are in 1548 * sync, we can match exact offset, and if not, we can match 1549 * exact software computation in compute_guest_tsc() 1550 * 1551 * These values are tracked in kvm->arch.cur_xxx variables. 1552 */ 1553 kvm->arch.cur_tsc_generation++; 1554 kvm->arch.cur_tsc_nsec = ns; 1555 kvm->arch.cur_tsc_write = data; 1556 kvm->arch.cur_tsc_offset = offset; 1557 matched = false; 1558 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1559 kvm->arch.cur_tsc_generation, data); 1560 } 1561 1562 /* 1563 * We also track th most recent recorded KHZ, write and time to 1564 * allow the matching interval to be extended at each write. 1565 */ 1566 kvm->arch.last_tsc_nsec = ns; 1567 kvm->arch.last_tsc_write = data; 1568 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1569 1570 vcpu->arch.last_guest_tsc = data; 1571 1572 /* Keep track of which generation this VCPU has synchronized to */ 1573 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1574 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1575 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1576 1577 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) 1578 update_ia32_tsc_adjust_msr(vcpu, offset); 1579 1580 kvm_vcpu_write_tsc_offset(vcpu, offset); 1581 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1582 1583 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1584 if (!matched) { 1585 kvm->arch.nr_vcpus_matched_tsc = 0; 1586 } else if (!already_matched) { 1587 kvm->arch.nr_vcpus_matched_tsc++; 1588 } 1589 1590 kvm_track_tsc_matching(vcpu); 1591 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1592 } 1593 1594 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1595 1596 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 1597 s64 adjustment) 1598 { 1599 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment); 1600 } 1601 1602 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 1603 { 1604 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 1605 WARN_ON(adjustment < 0); 1606 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 1607 adjust_tsc_offset_guest(vcpu, adjustment); 1608 } 1609 1610 #ifdef CONFIG_X86_64 1611 1612 static u64 read_tsc(void) 1613 { 1614 u64 ret = (u64)rdtsc_ordered(); 1615 u64 last = pvclock_gtod_data.clock.cycle_last; 1616 1617 if (likely(ret >= last)) 1618 return ret; 1619 1620 /* 1621 * GCC likes to generate cmov here, but this branch is extremely 1622 * predictable (it's just a function of time and the likely is 1623 * very likely) and there's a data dependence, so force GCC 1624 * to generate a branch instead. I don't barrier() because 1625 * we don't actually need a barrier, and if this function 1626 * ever gets inlined it will generate worse code. 1627 */ 1628 asm volatile (""); 1629 return last; 1630 } 1631 1632 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode) 1633 { 1634 long v; 1635 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1636 u64 tsc_pg_val; 1637 1638 switch (gtod->clock.vclock_mode) { 1639 case VCLOCK_HVCLOCK: 1640 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 1641 tsc_timestamp); 1642 if (tsc_pg_val != U64_MAX) { 1643 /* TSC page valid */ 1644 *mode = VCLOCK_HVCLOCK; 1645 v = (tsc_pg_val - gtod->clock.cycle_last) & 1646 gtod->clock.mask; 1647 } else { 1648 /* TSC page invalid */ 1649 *mode = VCLOCK_NONE; 1650 } 1651 break; 1652 case VCLOCK_TSC: 1653 *mode = VCLOCK_TSC; 1654 *tsc_timestamp = read_tsc(); 1655 v = (*tsc_timestamp - gtod->clock.cycle_last) & 1656 gtod->clock.mask; 1657 break; 1658 default: 1659 *mode = VCLOCK_NONE; 1660 } 1661 1662 if (*mode == VCLOCK_NONE) 1663 *tsc_timestamp = v = 0; 1664 1665 return v * gtod->clock.mult; 1666 } 1667 1668 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp) 1669 { 1670 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1671 unsigned long seq; 1672 int mode; 1673 u64 ns; 1674 1675 do { 1676 seq = read_seqcount_begin(>od->seq); 1677 ns = gtod->nsec_base; 1678 ns += vgettsc(tsc_timestamp, &mode); 1679 ns >>= gtod->clock.shift; 1680 ns += gtod->boot_ns; 1681 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1682 *t = ns; 1683 1684 return mode; 1685 } 1686 1687 static int do_realtime(struct timespec *ts, u64 *tsc_timestamp) 1688 { 1689 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1690 unsigned long seq; 1691 int mode; 1692 u64 ns; 1693 1694 do { 1695 seq = read_seqcount_begin(>od->seq); 1696 ts->tv_sec = gtod->wall_time_sec; 1697 ns = gtod->nsec_base; 1698 ns += vgettsc(tsc_timestamp, &mode); 1699 ns >>= gtod->clock.shift; 1700 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1701 1702 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 1703 ts->tv_nsec = ns; 1704 1705 return mode; 1706 } 1707 1708 /* returns true if host is using TSC based clocksource */ 1709 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 1710 { 1711 /* checked again under seqlock below */ 1712 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 1713 return false; 1714 1715 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns, 1716 tsc_timestamp)); 1717 } 1718 1719 /* returns true if host is using TSC based clocksource */ 1720 static bool kvm_get_walltime_and_clockread(struct timespec *ts, 1721 u64 *tsc_timestamp) 1722 { 1723 /* checked again under seqlock below */ 1724 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 1725 return false; 1726 1727 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 1728 } 1729 #endif 1730 1731 /* 1732 * 1733 * Assuming a stable TSC across physical CPUS, and a stable TSC 1734 * across virtual CPUs, the following condition is possible. 1735 * Each numbered line represents an event visible to both 1736 * CPUs at the next numbered event. 1737 * 1738 * "timespecX" represents host monotonic time. "tscX" represents 1739 * RDTSC value. 1740 * 1741 * VCPU0 on CPU0 | VCPU1 on CPU1 1742 * 1743 * 1. read timespec0,tsc0 1744 * 2. | timespec1 = timespec0 + N 1745 * | tsc1 = tsc0 + M 1746 * 3. transition to guest | transition to guest 1747 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1748 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1749 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1750 * 1751 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1752 * 1753 * - ret0 < ret1 1754 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1755 * ... 1756 * - 0 < N - M => M < N 1757 * 1758 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1759 * always the case (the difference between two distinct xtime instances 1760 * might be smaller then the difference between corresponding TSC reads, 1761 * when updating guest vcpus pvclock areas). 1762 * 1763 * To avoid that problem, do not allow visibility of distinct 1764 * system_timestamp/tsc_timestamp values simultaneously: use a master 1765 * copy of host monotonic time values. Update that master copy 1766 * in lockstep. 1767 * 1768 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1769 * 1770 */ 1771 1772 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1773 { 1774 #ifdef CONFIG_X86_64 1775 struct kvm_arch *ka = &kvm->arch; 1776 int vclock_mode; 1777 bool host_tsc_clocksource, vcpus_matched; 1778 1779 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1780 atomic_read(&kvm->online_vcpus)); 1781 1782 /* 1783 * If the host uses TSC clock, then passthrough TSC as stable 1784 * to the guest. 1785 */ 1786 host_tsc_clocksource = kvm_get_time_and_clockread( 1787 &ka->master_kernel_ns, 1788 &ka->master_cycle_now); 1789 1790 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 1791 && !ka->backwards_tsc_observed 1792 && !ka->boot_vcpu_runs_old_kvmclock; 1793 1794 if (ka->use_master_clock) 1795 atomic_set(&kvm_guest_has_master_clock, 1); 1796 1797 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1798 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1799 vcpus_matched); 1800 #endif 1801 } 1802 1803 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 1804 { 1805 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 1806 } 1807 1808 static void kvm_gen_update_masterclock(struct kvm *kvm) 1809 { 1810 #ifdef CONFIG_X86_64 1811 int i; 1812 struct kvm_vcpu *vcpu; 1813 struct kvm_arch *ka = &kvm->arch; 1814 1815 spin_lock(&ka->pvclock_gtod_sync_lock); 1816 kvm_make_mclock_inprogress_request(kvm); 1817 /* no guest entries from this point */ 1818 pvclock_update_vm_gtod_copy(kvm); 1819 1820 kvm_for_each_vcpu(i, vcpu, kvm) 1821 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1822 1823 /* guest entries allowed */ 1824 kvm_for_each_vcpu(i, vcpu, kvm) 1825 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 1826 1827 spin_unlock(&ka->pvclock_gtod_sync_lock); 1828 #endif 1829 } 1830 1831 u64 get_kvmclock_ns(struct kvm *kvm) 1832 { 1833 struct kvm_arch *ka = &kvm->arch; 1834 struct pvclock_vcpu_time_info hv_clock; 1835 u64 ret; 1836 1837 spin_lock(&ka->pvclock_gtod_sync_lock); 1838 if (!ka->use_master_clock) { 1839 spin_unlock(&ka->pvclock_gtod_sync_lock); 1840 return ktime_get_boot_ns() + ka->kvmclock_offset; 1841 } 1842 1843 hv_clock.tsc_timestamp = ka->master_cycle_now; 1844 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 1845 spin_unlock(&ka->pvclock_gtod_sync_lock); 1846 1847 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 1848 get_cpu(); 1849 1850 if (__this_cpu_read(cpu_tsc_khz)) { 1851 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 1852 &hv_clock.tsc_shift, 1853 &hv_clock.tsc_to_system_mul); 1854 ret = __pvclock_read_cycles(&hv_clock, rdtsc()); 1855 } else 1856 ret = ktime_get_boot_ns() + ka->kvmclock_offset; 1857 1858 put_cpu(); 1859 1860 return ret; 1861 } 1862 1863 static void kvm_setup_pvclock_page(struct kvm_vcpu *v) 1864 { 1865 struct kvm_vcpu_arch *vcpu = &v->arch; 1866 struct pvclock_vcpu_time_info guest_hv_clock; 1867 1868 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1869 &guest_hv_clock, sizeof(guest_hv_clock)))) 1870 return; 1871 1872 /* This VCPU is paused, but it's legal for a guest to read another 1873 * VCPU's kvmclock, so we really have to follow the specification where 1874 * it says that version is odd if data is being modified, and even after 1875 * it is consistent. 1876 * 1877 * Version field updates must be kept separate. This is because 1878 * kvm_write_guest_cached might use a "rep movs" instruction, and 1879 * writes within a string instruction are weakly ordered. So there 1880 * are three writes overall. 1881 * 1882 * As a small optimization, only write the version field in the first 1883 * and third write. The vcpu->pv_time cache is still valid, because the 1884 * version field is the first in the struct. 1885 */ 1886 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 1887 1888 if (guest_hv_clock.version & 1) 1889 ++guest_hv_clock.version; /* first time write, random junk */ 1890 1891 vcpu->hv_clock.version = guest_hv_clock.version + 1; 1892 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1893 &vcpu->hv_clock, 1894 sizeof(vcpu->hv_clock.version)); 1895 1896 smp_wmb(); 1897 1898 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1899 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1900 1901 if (vcpu->pvclock_set_guest_stopped_request) { 1902 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 1903 vcpu->pvclock_set_guest_stopped_request = false; 1904 } 1905 1906 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 1907 1908 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1909 &vcpu->hv_clock, 1910 sizeof(vcpu->hv_clock)); 1911 1912 smp_wmb(); 1913 1914 vcpu->hv_clock.version++; 1915 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1916 &vcpu->hv_clock, 1917 sizeof(vcpu->hv_clock.version)); 1918 } 1919 1920 static int kvm_guest_time_update(struct kvm_vcpu *v) 1921 { 1922 unsigned long flags, tgt_tsc_khz; 1923 struct kvm_vcpu_arch *vcpu = &v->arch; 1924 struct kvm_arch *ka = &v->kvm->arch; 1925 s64 kernel_ns; 1926 u64 tsc_timestamp, host_tsc; 1927 u8 pvclock_flags; 1928 bool use_master_clock; 1929 1930 kernel_ns = 0; 1931 host_tsc = 0; 1932 1933 /* 1934 * If the host uses TSC clock, then passthrough TSC as stable 1935 * to the guest. 1936 */ 1937 spin_lock(&ka->pvclock_gtod_sync_lock); 1938 use_master_clock = ka->use_master_clock; 1939 if (use_master_clock) { 1940 host_tsc = ka->master_cycle_now; 1941 kernel_ns = ka->master_kernel_ns; 1942 } 1943 spin_unlock(&ka->pvclock_gtod_sync_lock); 1944 1945 /* Keep irq disabled to prevent changes to the clock */ 1946 local_irq_save(flags); 1947 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 1948 if (unlikely(tgt_tsc_khz == 0)) { 1949 local_irq_restore(flags); 1950 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1951 return 1; 1952 } 1953 if (!use_master_clock) { 1954 host_tsc = rdtsc(); 1955 kernel_ns = ktime_get_boot_ns(); 1956 } 1957 1958 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 1959 1960 /* 1961 * We may have to catch up the TSC to match elapsed wall clock 1962 * time for two reasons, even if kvmclock is used. 1963 * 1) CPU could have been running below the maximum TSC rate 1964 * 2) Broken TSC compensation resets the base at each VCPU 1965 * entry to avoid unknown leaps of TSC even when running 1966 * again on the same CPU. This may cause apparent elapsed 1967 * time to disappear, and the guest to stand still or run 1968 * very slowly. 1969 */ 1970 if (vcpu->tsc_catchup) { 1971 u64 tsc = compute_guest_tsc(v, kernel_ns); 1972 if (tsc > tsc_timestamp) { 1973 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 1974 tsc_timestamp = tsc; 1975 } 1976 } 1977 1978 local_irq_restore(flags); 1979 1980 /* With all the info we got, fill in the values */ 1981 1982 if (kvm_has_tsc_control) 1983 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 1984 1985 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 1986 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 1987 &vcpu->hv_clock.tsc_shift, 1988 &vcpu->hv_clock.tsc_to_system_mul); 1989 vcpu->hw_tsc_khz = tgt_tsc_khz; 1990 } 1991 1992 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 1993 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 1994 vcpu->last_guest_tsc = tsc_timestamp; 1995 1996 /* If the host uses TSC clocksource, then it is stable */ 1997 pvclock_flags = 0; 1998 if (use_master_clock) 1999 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 2000 2001 vcpu->hv_clock.flags = pvclock_flags; 2002 2003 if (vcpu->pv_time_enabled) 2004 kvm_setup_pvclock_page(v); 2005 if (v == kvm_get_vcpu(v->kvm, 0)) 2006 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 2007 return 0; 2008 } 2009 2010 /* 2011 * kvmclock updates which are isolated to a given vcpu, such as 2012 * vcpu->cpu migration, should not allow system_timestamp from 2013 * the rest of the vcpus to remain static. Otherwise ntp frequency 2014 * correction applies to one vcpu's system_timestamp but not 2015 * the others. 2016 * 2017 * So in those cases, request a kvmclock update for all vcpus. 2018 * We need to rate-limit these requests though, as they can 2019 * considerably slow guests that have a large number of vcpus. 2020 * The time for a remote vcpu to update its kvmclock is bound 2021 * by the delay we use to rate-limit the updates. 2022 */ 2023 2024 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 2025 2026 static void kvmclock_update_fn(struct work_struct *work) 2027 { 2028 int i; 2029 struct delayed_work *dwork = to_delayed_work(work); 2030 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2031 kvmclock_update_work); 2032 struct kvm *kvm = container_of(ka, struct kvm, arch); 2033 struct kvm_vcpu *vcpu; 2034 2035 kvm_for_each_vcpu(i, vcpu, kvm) { 2036 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2037 kvm_vcpu_kick(vcpu); 2038 } 2039 } 2040 2041 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 2042 { 2043 struct kvm *kvm = v->kvm; 2044 2045 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2046 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 2047 KVMCLOCK_UPDATE_DELAY); 2048 } 2049 2050 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 2051 2052 static void kvmclock_sync_fn(struct work_struct *work) 2053 { 2054 struct delayed_work *dwork = to_delayed_work(work); 2055 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2056 kvmclock_sync_work); 2057 struct kvm *kvm = container_of(ka, struct kvm, arch); 2058 2059 if (!kvmclock_periodic_sync) 2060 return; 2061 2062 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 2063 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 2064 KVMCLOCK_SYNC_PERIOD); 2065 } 2066 2067 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2068 { 2069 u64 mcg_cap = vcpu->arch.mcg_cap; 2070 unsigned bank_num = mcg_cap & 0xff; 2071 u32 msr = msr_info->index; 2072 u64 data = msr_info->data; 2073 2074 switch (msr) { 2075 case MSR_IA32_MCG_STATUS: 2076 vcpu->arch.mcg_status = data; 2077 break; 2078 case MSR_IA32_MCG_CTL: 2079 if (!(mcg_cap & MCG_CTL_P)) 2080 return 1; 2081 if (data != 0 && data != ~(u64)0) 2082 return -1; 2083 vcpu->arch.mcg_ctl = data; 2084 break; 2085 default: 2086 if (msr >= MSR_IA32_MC0_CTL && 2087 msr < MSR_IA32_MCx_CTL(bank_num)) { 2088 u32 offset = msr - MSR_IA32_MC0_CTL; 2089 /* only 0 or all 1s can be written to IA32_MCi_CTL 2090 * some Linux kernels though clear bit 10 in bank 4 to 2091 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 2092 * this to avoid an uncatched #GP in the guest 2093 */ 2094 if ((offset & 0x3) == 0 && 2095 data != 0 && (data | (1 << 10)) != ~(u64)0) 2096 return -1; 2097 if (!msr_info->host_initiated && 2098 (offset & 0x3) == 1 && data != 0) 2099 return -1; 2100 vcpu->arch.mce_banks[offset] = data; 2101 break; 2102 } 2103 return 1; 2104 } 2105 return 0; 2106 } 2107 2108 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 2109 { 2110 struct kvm *kvm = vcpu->kvm; 2111 int lm = is_long_mode(vcpu); 2112 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 2113 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 2114 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 2115 : kvm->arch.xen_hvm_config.blob_size_32; 2116 u32 page_num = data & ~PAGE_MASK; 2117 u64 page_addr = data & PAGE_MASK; 2118 u8 *page; 2119 int r; 2120 2121 r = -E2BIG; 2122 if (page_num >= blob_size) 2123 goto out; 2124 r = -ENOMEM; 2125 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 2126 if (IS_ERR(page)) { 2127 r = PTR_ERR(page); 2128 goto out; 2129 } 2130 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 2131 goto out_free; 2132 r = 0; 2133 out_free: 2134 kfree(page); 2135 out: 2136 return r; 2137 } 2138 2139 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2140 { 2141 gpa_t gpa = data & ~0x3f; 2142 2143 /* Bits 3:5 are reserved, Should be zero */ 2144 if (data & 0x38) 2145 return 1; 2146 2147 vcpu->arch.apf.msr_val = data; 2148 2149 if (!(data & KVM_ASYNC_PF_ENABLED)) { 2150 kvm_clear_async_pf_completion_queue(vcpu); 2151 kvm_async_pf_hash_reset(vcpu); 2152 return 0; 2153 } 2154 2155 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2156 sizeof(u32))) 2157 return 1; 2158 2159 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2160 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 2161 kvm_async_pf_wakeup_all(vcpu); 2162 return 0; 2163 } 2164 2165 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2166 { 2167 vcpu->arch.pv_time_enabled = false; 2168 } 2169 2170 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) 2171 { 2172 ++vcpu->stat.tlb_flush; 2173 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa); 2174 } 2175 2176 static void record_steal_time(struct kvm_vcpu *vcpu) 2177 { 2178 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2179 return; 2180 2181 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2182 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2183 return; 2184 2185 /* 2186 * Doing a TLB flush here, on the guest's behalf, can avoid 2187 * expensive IPIs. 2188 */ 2189 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB) 2190 kvm_vcpu_flush_tlb(vcpu, false); 2191 2192 if (vcpu->arch.st.steal.version & 1) 2193 vcpu->arch.st.steal.version += 1; /* first time write, random junk */ 2194 2195 vcpu->arch.st.steal.version += 1; 2196 2197 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2198 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2199 2200 smp_wmb(); 2201 2202 vcpu->arch.st.steal.steal += current->sched_info.run_delay - 2203 vcpu->arch.st.last_steal; 2204 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2205 2206 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2207 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2208 2209 smp_wmb(); 2210 2211 vcpu->arch.st.steal.version += 1; 2212 2213 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2214 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2215 } 2216 2217 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2218 { 2219 bool pr = false; 2220 u32 msr = msr_info->index; 2221 u64 data = msr_info->data; 2222 2223 switch (msr) { 2224 case MSR_AMD64_NB_CFG: 2225 case MSR_IA32_UCODE_REV: 2226 case MSR_IA32_UCODE_WRITE: 2227 case MSR_VM_HSAVE_PA: 2228 case MSR_AMD64_PATCH_LOADER: 2229 case MSR_AMD64_BU_CFG2: 2230 case MSR_AMD64_DC_CFG: 2231 break; 2232 2233 case MSR_EFER: 2234 return set_efer(vcpu, data); 2235 case MSR_K7_HWCR: 2236 data &= ~(u64)0x40; /* ignore flush filter disable */ 2237 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2238 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2239 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2240 if (data != 0) { 2241 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2242 data); 2243 return 1; 2244 } 2245 break; 2246 case MSR_FAM10H_MMIO_CONF_BASE: 2247 if (data != 0) { 2248 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2249 "0x%llx\n", data); 2250 return 1; 2251 } 2252 break; 2253 case MSR_IA32_DEBUGCTLMSR: 2254 if (!data) { 2255 /* We support the non-activated case already */ 2256 break; 2257 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2258 /* Values other than LBR and BTF are vendor-specific, 2259 thus reserved and should throw a #GP */ 2260 return 1; 2261 } 2262 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2263 __func__, data); 2264 break; 2265 case 0x200 ... 0x2ff: 2266 return kvm_mtrr_set_msr(vcpu, msr, data); 2267 case MSR_IA32_APICBASE: 2268 return kvm_set_apic_base(vcpu, msr_info); 2269 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2270 return kvm_x2apic_msr_write(vcpu, msr, data); 2271 case MSR_IA32_TSCDEADLINE: 2272 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2273 break; 2274 case MSR_IA32_TSC_ADJUST: 2275 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 2276 if (!msr_info->host_initiated) { 2277 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2278 adjust_tsc_offset_guest(vcpu, adj); 2279 } 2280 vcpu->arch.ia32_tsc_adjust_msr = data; 2281 } 2282 break; 2283 case MSR_IA32_MISC_ENABLE: 2284 vcpu->arch.ia32_misc_enable_msr = data; 2285 break; 2286 case MSR_IA32_SMBASE: 2287 if (!msr_info->host_initiated) 2288 return 1; 2289 vcpu->arch.smbase = data; 2290 break; 2291 case MSR_SMI_COUNT: 2292 if (!msr_info->host_initiated) 2293 return 1; 2294 vcpu->arch.smi_count = data; 2295 break; 2296 case MSR_KVM_WALL_CLOCK_NEW: 2297 case MSR_KVM_WALL_CLOCK: 2298 vcpu->kvm->arch.wall_clock = data; 2299 kvm_write_wall_clock(vcpu->kvm, data); 2300 break; 2301 case MSR_KVM_SYSTEM_TIME_NEW: 2302 case MSR_KVM_SYSTEM_TIME: { 2303 struct kvm_arch *ka = &vcpu->kvm->arch; 2304 2305 kvmclock_reset(vcpu); 2306 2307 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2308 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2309 2310 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2311 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2312 2313 ka->boot_vcpu_runs_old_kvmclock = tmp; 2314 } 2315 2316 vcpu->arch.time = data; 2317 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2318 2319 /* we verify if the enable bit is set... */ 2320 if (!(data & 1)) 2321 break; 2322 2323 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2324 &vcpu->arch.pv_time, data & ~1ULL, 2325 sizeof(struct pvclock_vcpu_time_info))) 2326 vcpu->arch.pv_time_enabled = false; 2327 else 2328 vcpu->arch.pv_time_enabled = true; 2329 2330 break; 2331 } 2332 case MSR_KVM_ASYNC_PF_EN: 2333 if (kvm_pv_enable_async_pf(vcpu, data)) 2334 return 1; 2335 break; 2336 case MSR_KVM_STEAL_TIME: 2337 2338 if (unlikely(!sched_info_on())) 2339 return 1; 2340 2341 if (data & KVM_STEAL_RESERVED_MASK) 2342 return 1; 2343 2344 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2345 data & KVM_STEAL_VALID_BITS, 2346 sizeof(struct kvm_steal_time))) 2347 return 1; 2348 2349 vcpu->arch.st.msr_val = data; 2350 2351 if (!(data & KVM_MSR_ENABLED)) 2352 break; 2353 2354 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2355 2356 break; 2357 case MSR_KVM_PV_EOI_EN: 2358 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2359 return 1; 2360 break; 2361 2362 case MSR_IA32_MCG_CTL: 2363 case MSR_IA32_MCG_STATUS: 2364 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2365 return set_msr_mce(vcpu, msr_info); 2366 2367 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2368 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2369 pr = true; /* fall through */ 2370 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2371 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2372 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2373 return kvm_pmu_set_msr(vcpu, msr_info); 2374 2375 if (pr || data != 0) 2376 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2377 "0x%x data 0x%llx\n", msr, data); 2378 break; 2379 case MSR_K7_CLK_CTL: 2380 /* 2381 * Ignore all writes to this no longer documented MSR. 2382 * Writes are only relevant for old K7 processors, 2383 * all pre-dating SVM, but a recommended workaround from 2384 * AMD for these chips. It is possible to specify the 2385 * affected processor models on the command line, hence 2386 * the need to ignore the workaround. 2387 */ 2388 break; 2389 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2390 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2391 case HV_X64_MSR_CRASH_CTL: 2392 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2393 return kvm_hv_set_msr_common(vcpu, msr, data, 2394 msr_info->host_initiated); 2395 case MSR_IA32_BBL_CR_CTL3: 2396 /* Drop writes to this legacy MSR -- see rdmsr 2397 * counterpart for further detail. 2398 */ 2399 if (report_ignored_msrs) 2400 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 2401 msr, data); 2402 break; 2403 case MSR_AMD64_OSVW_ID_LENGTH: 2404 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2405 return 1; 2406 vcpu->arch.osvw.length = data; 2407 break; 2408 case MSR_AMD64_OSVW_STATUS: 2409 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2410 return 1; 2411 vcpu->arch.osvw.status = data; 2412 break; 2413 case MSR_PLATFORM_INFO: 2414 if (!msr_info->host_initiated || 2415 data & ~MSR_PLATFORM_INFO_CPUID_FAULT || 2416 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 2417 cpuid_fault_enabled(vcpu))) 2418 return 1; 2419 vcpu->arch.msr_platform_info = data; 2420 break; 2421 case MSR_MISC_FEATURES_ENABLES: 2422 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 2423 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 2424 !supports_cpuid_fault(vcpu))) 2425 return 1; 2426 vcpu->arch.msr_misc_features_enables = data; 2427 break; 2428 default: 2429 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2430 return xen_hvm_config(vcpu, data); 2431 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2432 return kvm_pmu_set_msr(vcpu, msr_info); 2433 if (!ignore_msrs) { 2434 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n", 2435 msr, data); 2436 return 1; 2437 } else { 2438 if (report_ignored_msrs) 2439 vcpu_unimpl(vcpu, 2440 "ignored wrmsr: 0x%x data 0x%llx\n", 2441 msr, data); 2442 break; 2443 } 2444 } 2445 return 0; 2446 } 2447 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2448 2449 2450 /* 2451 * Reads an msr value (of 'msr_index') into 'pdata'. 2452 * Returns 0 on success, non-0 otherwise. 2453 * Assumes vcpu_load() was already called. 2454 */ 2455 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 2456 { 2457 return kvm_x86_ops->get_msr(vcpu, msr); 2458 } 2459 EXPORT_SYMBOL_GPL(kvm_get_msr); 2460 2461 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2462 { 2463 u64 data; 2464 u64 mcg_cap = vcpu->arch.mcg_cap; 2465 unsigned bank_num = mcg_cap & 0xff; 2466 2467 switch (msr) { 2468 case MSR_IA32_P5_MC_ADDR: 2469 case MSR_IA32_P5_MC_TYPE: 2470 data = 0; 2471 break; 2472 case MSR_IA32_MCG_CAP: 2473 data = vcpu->arch.mcg_cap; 2474 break; 2475 case MSR_IA32_MCG_CTL: 2476 if (!(mcg_cap & MCG_CTL_P)) 2477 return 1; 2478 data = vcpu->arch.mcg_ctl; 2479 break; 2480 case MSR_IA32_MCG_STATUS: 2481 data = vcpu->arch.mcg_status; 2482 break; 2483 default: 2484 if (msr >= MSR_IA32_MC0_CTL && 2485 msr < MSR_IA32_MCx_CTL(bank_num)) { 2486 u32 offset = msr - MSR_IA32_MC0_CTL; 2487 data = vcpu->arch.mce_banks[offset]; 2488 break; 2489 } 2490 return 1; 2491 } 2492 *pdata = data; 2493 return 0; 2494 } 2495 2496 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2497 { 2498 switch (msr_info->index) { 2499 case MSR_IA32_PLATFORM_ID: 2500 case MSR_IA32_EBL_CR_POWERON: 2501 case MSR_IA32_DEBUGCTLMSR: 2502 case MSR_IA32_LASTBRANCHFROMIP: 2503 case MSR_IA32_LASTBRANCHTOIP: 2504 case MSR_IA32_LASTINTFROMIP: 2505 case MSR_IA32_LASTINTTOIP: 2506 case MSR_K8_SYSCFG: 2507 case MSR_K8_TSEG_ADDR: 2508 case MSR_K8_TSEG_MASK: 2509 case MSR_K7_HWCR: 2510 case MSR_VM_HSAVE_PA: 2511 case MSR_K8_INT_PENDING_MSG: 2512 case MSR_AMD64_NB_CFG: 2513 case MSR_FAM10H_MMIO_CONF_BASE: 2514 case MSR_AMD64_BU_CFG2: 2515 case MSR_IA32_PERF_CTL: 2516 case MSR_AMD64_DC_CFG: 2517 msr_info->data = 0; 2518 break; 2519 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2520 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2521 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2522 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2523 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2524 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2525 msr_info->data = 0; 2526 break; 2527 case MSR_IA32_UCODE_REV: 2528 msr_info->data = 0x100000000ULL; 2529 break; 2530 case MSR_MTRRcap: 2531 case 0x200 ... 0x2ff: 2532 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 2533 case 0xcd: /* fsb frequency */ 2534 msr_info->data = 3; 2535 break; 2536 /* 2537 * MSR_EBC_FREQUENCY_ID 2538 * Conservative value valid for even the basic CPU models. 2539 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2540 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2541 * and 266MHz for model 3, or 4. Set Core Clock 2542 * Frequency to System Bus Frequency Ratio to 1 (bits 2543 * 31:24) even though these are only valid for CPU 2544 * models > 2, however guests may end up dividing or 2545 * multiplying by zero otherwise. 2546 */ 2547 case MSR_EBC_FREQUENCY_ID: 2548 msr_info->data = 1 << 24; 2549 break; 2550 case MSR_IA32_APICBASE: 2551 msr_info->data = kvm_get_apic_base(vcpu); 2552 break; 2553 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2554 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 2555 break; 2556 case MSR_IA32_TSCDEADLINE: 2557 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 2558 break; 2559 case MSR_IA32_TSC_ADJUST: 2560 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2561 break; 2562 case MSR_IA32_MISC_ENABLE: 2563 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 2564 break; 2565 case MSR_IA32_SMBASE: 2566 if (!msr_info->host_initiated) 2567 return 1; 2568 msr_info->data = vcpu->arch.smbase; 2569 break; 2570 case MSR_SMI_COUNT: 2571 msr_info->data = vcpu->arch.smi_count; 2572 break; 2573 case MSR_IA32_PERF_STATUS: 2574 /* TSC increment by tick */ 2575 msr_info->data = 1000ULL; 2576 /* CPU multiplier */ 2577 msr_info->data |= (((uint64_t)4ULL) << 40); 2578 break; 2579 case MSR_EFER: 2580 msr_info->data = vcpu->arch.efer; 2581 break; 2582 case MSR_KVM_WALL_CLOCK: 2583 case MSR_KVM_WALL_CLOCK_NEW: 2584 msr_info->data = vcpu->kvm->arch.wall_clock; 2585 break; 2586 case MSR_KVM_SYSTEM_TIME: 2587 case MSR_KVM_SYSTEM_TIME_NEW: 2588 msr_info->data = vcpu->arch.time; 2589 break; 2590 case MSR_KVM_ASYNC_PF_EN: 2591 msr_info->data = vcpu->arch.apf.msr_val; 2592 break; 2593 case MSR_KVM_STEAL_TIME: 2594 msr_info->data = vcpu->arch.st.msr_val; 2595 break; 2596 case MSR_KVM_PV_EOI_EN: 2597 msr_info->data = vcpu->arch.pv_eoi.msr_val; 2598 break; 2599 case MSR_IA32_P5_MC_ADDR: 2600 case MSR_IA32_P5_MC_TYPE: 2601 case MSR_IA32_MCG_CAP: 2602 case MSR_IA32_MCG_CTL: 2603 case MSR_IA32_MCG_STATUS: 2604 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2605 return get_msr_mce(vcpu, msr_info->index, &msr_info->data); 2606 case MSR_K7_CLK_CTL: 2607 /* 2608 * Provide expected ramp-up count for K7. All other 2609 * are set to zero, indicating minimum divisors for 2610 * every field. 2611 * 2612 * This prevents guest kernels on AMD host with CPU 2613 * type 6, model 8 and higher from exploding due to 2614 * the rdmsr failing. 2615 */ 2616 msr_info->data = 0x20000000; 2617 break; 2618 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2619 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2620 case HV_X64_MSR_CRASH_CTL: 2621 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2622 return kvm_hv_get_msr_common(vcpu, 2623 msr_info->index, &msr_info->data); 2624 break; 2625 case MSR_IA32_BBL_CR_CTL3: 2626 /* This legacy MSR exists but isn't fully documented in current 2627 * silicon. It is however accessed by winxp in very narrow 2628 * scenarios where it sets bit #19, itself documented as 2629 * a "reserved" bit. Best effort attempt to source coherent 2630 * read data here should the balance of the register be 2631 * interpreted by the guest: 2632 * 2633 * L2 cache control register 3: 64GB range, 256KB size, 2634 * enabled, latency 0x1, configured 2635 */ 2636 msr_info->data = 0xbe702111; 2637 break; 2638 case MSR_AMD64_OSVW_ID_LENGTH: 2639 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2640 return 1; 2641 msr_info->data = vcpu->arch.osvw.length; 2642 break; 2643 case MSR_AMD64_OSVW_STATUS: 2644 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2645 return 1; 2646 msr_info->data = vcpu->arch.osvw.status; 2647 break; 2648 case MSR_PLATFORM_INFO: 2649 msr_info->data = vcpu->arch.msr_platform_info; 2650 break; 2651 case MSR_MISC_FEATURES_ENABLES: 2652 msr_info->data = vcpu->arch.msr_misc_features_enables; 2653 break; 2654 default: 2655 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2656 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2657 if (!ignore_msrs) { 2658 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n", 2659 msr_info->index); 2660 return 1; 2661 } else { 2662 if (report_ignored_msrs) 2663 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", 2664 msr_info->index); 2665 msr_info->data = 0; 2666 } 2667 break; 2668 } 2669 return 0; 2670 } 2671 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2672 2673 /* 2674 * Read or write a bunch of msrs. All parameters are kernel addresses. 2675 * 2676 * @return number of msrs set successfully. 2677 */ 2678 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2679 struct kvm_msr_entry *entries, 2680 int (*do_msr)(struct kvm_vcpu *vcpu, 2681 unsigned index, u64 *data)) 2682 { 2683 int i, idx; 2684 2685 idx = srcu_read_lock(&vcpu->kvm->srcu); 2686 for (i = 0; i < msrs->nmsrs; ++i) 2687 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2688 break; 2689 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2690 2691 return i; 2692 } 2693 2694 /* 2695 * Read or write a bunch of msrs. Parameters are user addresses. 2696 * 2697 * @return number of msrs set successfully. 2698 */ 2699 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2700 int (*do_msr)(struct kvm_vcpu *vcpu, 2701 unsigned index, u64 *data), 2702 int writeback) 2703 { 2704 struct kvm_msrs msrs; 2705 struct kvm_msr_entry *entries; 2706 int r, n; 2707 unsigned size; 2708 2709 r = -EFAULT; 2710 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2711 goto out; 2712 2713 r = -E2BIG; 2714 if (msrs.nmsrs >= MAX_IO_MSRS) 2715 goto out; 2716 2717 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2718 entries = memdup_user(user_msrs->entries, size); 2719 if (IS_ERR(entries)) { 2720 r = PTR_ERR(entries); 2721 goto out; 2722 } 2723 2724 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2725 if (r < 0) 2726 goto out_free; 2727 2728 r = -EFAULT; 2729 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2730 goto out_free; 2731 2732 r = n; 2733 2734 out_free: 2735 kfree(entries); 2736 out: 2737 return r; 2738 } 2739 2740 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2741 { 2742 int r; 2743 2744 switch (ext) { 2745 case KVM_CAP_IRQCHIP: 2746 case KVM_CAP_HLT: 2747 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2748 case KVM_CAP_SET_TSS_ADDR: 2749 case KVM_CAP_EXT_CPUID: 2750 case KVM_CAP_EXT_EMUL_CPUID: 2751 case KVM_CAP_CLOCKSOURCE: 2752 case KVM_CAP_PIT: 2753 case KVM_CAP_NOP_IO_DELAY: 2754 case KVM_CAP_MP_STATE: 2755 case KVM_CAP_SYNC_MMU: 2756 case KVM_CAP_USER_NMI: 2757 case KVM_CAP_REINJECT_CONTROL: 2758 case KVM_CAP_IRQ_INJECT_STATUS: 2759 case KVM_CAP_IOEVENTFD: 2760 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2761 case KVM_CAP_PIT2: 2762 case KVM_CAP_PIT_STATE2: 2763 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2764 case KVM_CAP_XEN_HVM: 2765 case KVM_CAP_VCPU_EVENTS: 2766 case KVM_CAP_HYPERV: 2767 case KVM_CAP_HYPERV_VAPIC: 2768 case KVM_CAP_HYPERV_SPIN: 2769 case KVM_CAP_HYPERV_SYNIC: 2770 case KVM_CAP_HYPERV_SYNIC2: 2771 case KVM_CAP_HYPERV_VP_INDEX: 2772 case KVM_CAP_PCI_SEGMENT: 2773 case KVM_CAP_DEBUGREGS: 2774 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2775 case KVM_CAP_XSAVE: 2776 case KVM_CAP_ASYNC_PF: 2777 case KVM_CAP_GET_TSC_KHZ: 2778 case KVM_CAP_KVMCLOCK_CTRL: 2779 case KVM_CAP_READONLY_MEM: 2780 case KVM_CAP_HYPERV_TIME: 2781 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2782 case KVM_CAP_TSC_DEADLINE_TIMER: 2783 case KVM_CAP_ENABLE_CAP_VM: 2784 case KVM_CAP_DISABLE_QUIRKS: 2785 case KVM_CAP_SET_BOOT_CPU_ID: 2786 case KVM_CAP_SPLIT_IRQCHIP: 2787 case KVM_CAP_IMMEDIATE_EXIT: 2788 r = 1; 2789 break; 2790 case KVM_CAP_ADJUST_CLOCK: 2791 r = KVM_CLOCK_TSC_STABLE; 2792 break; 2793 case KVM_CAP_X86_GUEST_MWAIT: 2794 r = kvm_mwait_in_guest(); 2795 break; 2796 case KVM_CAP_X86_SMM: 2797 /* SMBASE is usually relocated above 1M on modern chipsets, 2798 * and SMM handlers might indeed rely on 4G segment limits, 2799 * so do not report SMM to be available if real mode is 2800 * emulated via vm86 mode. Still, do not go to great lengths 2801 * to avoid userspace's usage of the feature, because it is a 2802 * fringe case that is not enabled except via specific settings 2803 * of the module parameters. 2804 */ 2805 r = kvm_x86_ops->cpu_has_high_real_mode_segbase(); 2806 break; 2807 case KVM_CAP_VAPIC: 2808 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2809 break; 2810 case KVM_CAP_NR_VCPUS: 2811 r = KVM_SOFT_MAX_VCPUS; 2812 break; 2813 case KVM_CAP_MAX_VCPUS: 2814 r = KVM_MAX_VCPUS; 2815 break; 2816 case KVM_CAP_NR_MEMSLOTS: 2817 r = KVM_USER_MEM_SLOTS; 2818 break; 2819 case KVM_CAP_PV_MMU: /* obsolete */ 2820 r = 0; 2821 break; 2822 case KVM_CAP_MCE: 2823 r = KVM_MAX_MCE_BANKS; 2824 break; 2825 case KVM_CAP_XCRS: 2826 r = boot_cpu_has(X86_FEATURE_XSAVE); 2827 break; 2828 case KVM_CAP_TSC_CONTROL: 2829 r = kvm_has_tsc_control; 2830 break; 2831 case KVM_CAP_X2APIC_API: 2832 r = KVM_X2APIC_API_VALID_FLAGS; 2833 break; 2834 default: 2835 r = 0; 2836 break; 2837 } 2838 return r; 2839 2840 } 2841 2842 long kvm_arch_dev_ioctl(struct file *filp, 2843 unsigned int ioctl, unsigned long arg) 2844 { 2845 void __user *argp = (void __user *)arg; 2846 long r; 2847 2848 switch (ioctl) { 2849 case KVM_GET_MSR_INDEX_LIST: { 2850 struct kvm_msr_list __user *user_msr_list = argp; 2851 struct kvm_msr_list msr_list; 2852 unsigned n; 2853 2854 r = -EFAULT; 2855 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2856 goto out; 2857 n = msr_list.nmsrs; 2858 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 2859 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2860 goto out; 2861 r = -E2BIG; 2862 if (n < msr_list.nmsrs) 2863 goto out; 2864 r = -EFAULT; 2865 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2866 num_msrs_to_save * sizeof(u32))) 2867 goto out; 2868 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2869 &emulated_msrs, 2870 num_emulated_msrs * sizeof(u32))) 2871 goto out; 2872 r = 0; 2873 break; 2874 } 2875 case KVM_GET_SUPPORTED_CPUID: 2876 case KVM_GET_EMULATED_CPUID: { 2877 struct kvm_cpuid2 __user *cpuid_arg = argp; 2878 struct kvm_cpuid2 cpuid; 2879 2880 r = -EFAULT; 2881 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2882 goto out; 2883 2884 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2885 ioctl); 2886 if (r) 2887 goto out; 2888 2889 r = -EFAULT; 2890 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2891 goto out; 2892 r = 0; 2893 break; 2894 } 2895 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2896 r = -EFAULT; 2897 if (copy_to_user(argp, &kvm_mce_cap_supported, 2898 sizeof(kvm_mce_cap_supported))) 2899 goto out; 2900 r = 0; 2901 break; 2902 } 2903 default: 2904 r = -EINVAL; 2905 } 2906 out: 2907 return r; 2908 } 2909 2910 static void wbinvd_ipi(void *garbage) 2911 { 2912 wbinvd(); 2913 } 2914 2915 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 2916 { 2917 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 2918 } 2919 2920 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 2921 { 2922 /* Address WBINVD may be executed by guest */ 2923 if (need_emulate_wbinvd(vcpu)) { 2924 if (kvm_x86_ops->has_wbinvd_exit()) 2925 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 2926 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 2927 smp_call_function_single(vcpu->cpu, 2928 wbinvd_ipi, NULL, 1); 2929 } 2930 2931 kvm_x86_ops->vcpu_load(vcpu, cpu); 2932 2933 /* Apply any externally detected TSC adjustments (due to suspend) */ 2934 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 2935 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 2936 vcpu->arch.tsc_offset_adjustment = 0; 2937 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2938 } 2939 2940 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 2941 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 2942 rdtsc() - vcpu->arch.last_host_tsc; 2943 if (tsc_delta < 0) 2944 mark_tsc_unstable("KVM discovered backwards TSC"); 2945 2946 if (kvm_check_tsc_unstable()) { 2947 u64 offset = kvm_compute_tsc_offset(vcpu, 2948 vcpu->arch.last_guest_tsc); 2949 kvm_vcpu_write_tsc_offset(vcpu, offset); 2950 vcpu->arch.tsc_catchup = 1; 2951 } 2952 2953 if (kvm_lapic_hv_timer_in_use(vcpu)) 2954 kvm_lapic_restart_hv_timer(vcpu); 2955 2956 /* 2957 * On a host with synchronized TSC, there is no need to update 2958 * kvmclock on vcpu->cpu migration 2959 */ 2960 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 2961 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2962 if (vcpu->cpu != cpu) 2963 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 2964 vcpu->cpu = cpu; 2965 } 2966 2967 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2968 } 2969 2970 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 2971 { 2972 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2973 return; 2974 2975 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED; 2976 2977 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime, 2978 &vcpu->arch.st.steal.preempted, 2979 offsetof(struct kvm_steal_time, preempted), 2980 sizeof(vcpu->arch.st.steal.preempted)); 2981 } 2982 2983 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 2984 { 2985 int idx; 2986 2987 if (vcpu->preempted) 2988 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu); 2989 2990 /* 2991 * Disable page faults because we're in atomic context here. 2992 * kvm_write_guest_offset_cached() would call might_fault() 2993 * that relies on pagefault_disable() to tell if there's a 2994 * bug. NOTE: the write to guest memory may not go through if 2995 * during postcopy live migration or if there's heavy guest 2996 * paging. 2997 */ 2998 pagefault_disable(); 2999 /* 3000 * kvm_memslots() will be called by 3001 * kvm_write_guest_offset_cached() so take the srcu lock. 3002 */ 3003 idx = srcu_read_lock(&vcpu->kvm->srcu); 3004 kvm_steal_time_set_preempted(vcpu); 3005 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3006 pagefault_enable(); 3007 kvm_x86_ops->vcpu_put(vcpu); 3008 vcpu->arch.last_host_tsc = rdtsc(); 3009 /* 3010 * If userspace has set any breakpoints or watchpoints, dr6 is restored 3011 * on every vmexit, but if not, we might have a stale dr6 from the 3012 * guest. do_debug expects dr6 to be cleared after it runs, do the same. 3013 */ 3014 set_debugreg(0, 6); 3015 } 3016 3017 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 3018 struct kvm_lapic_state *s) 3019 { 3020 if (vcpu->arch.apicv_active) 3021 kvm_x86_ops->sync_pir_to_irr(vcpu); 3022 3023 return kvm_apic_get_state(vcpu, s); 3024 } 3025 3026 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 3027 struct kvm_lapic_state *s) 3028 { 3029 int r; 3030 3031 r = kvm_apic_set_state(vcpu, s); 3032 if (r) 3033 return r; 3034 update_cr8_intercept(vcpu); 3035 3036 return 0; 3037 } 3038 3039 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 3040 { 3041 return (!lapic_in_kernel(vcpu) || 3042 kvm_apic_accept_pic_intr(vcpu)); 3043 } 3044 3045 /* 3046 * if userspace requested an interrupt window, check that the 3047 * interrupt window is open. 3048 * 3049 * No need to exit to userspace if we already have an interrupt queued. 3050 */ 3051 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 3052 { 3053 return kvm_arch_interrupt_allowed(vcpu) && 3054 !kvm_cpu_has_interrupt(vcpu) && 3055 !kvm_event_needs_reinjection(vcpu) && 3056 kvm_cpu_accept_dm_intr(vcpu); 3057 } 3058 3059 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 3060 struct kvm_interrupt *irq) 3061 { 3062 if (irq->irq >= KVM_NR_INTERRUPTS) 3063 return -EINVAL; 3064 3065 if (!irqchip_in_kernel(vcpu->kvm)) { 3066 kvm_queue_interrupt(vcpu, irq->irq, false); 3067 kvm_make_request(KVM_REQ_EVENT, vcpu); 3068 return 0; 3069 } 3070 3071 /* 3072 * With in-kernel LAPIC, we only use this to inject EXTINT, so 3073 * fail for in-kernel 8259. 3074 */ 3075 if (pic_in_kernel(vcpu->kvm)) 3076 return -ENXIO; 3077 3078 if (vcpu->arch.pending_external_vector != -1) 3079 return -EEXIST; 3080 3081 vcpu->arch.pending_external_vector = irq->irq; 3082 kvm_make_request(KVM_REQ_EVENT, vcpu); 3083 return 0; 3084 } 3085 3086 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 3087 { 3088 kvm_inject_nmi(vcpu); 3089 3090 return 0; 3091 } 3092 3093 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 3094 { 3095 kvm_make_request(KVM_REQ_SMI, vcpu); 3096 3097 return 0; 3098 } 3099 3100 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 3101 struct kvm_tpr_access_ctl *tac) 3102 { 3103 if (tac->flags) 3104 return -EINVAL; 3105 vcpu->arch.tpr_access_reporting = !!tac->enabled; 3106 return 0; 3107 } 3108 3109 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 3110 u64 mcg_cap) 3111 { 3112 int r; 3113 unsigned bank_num = mcg_cap & 0xff, bank; 3114 3115 r = -EINVAL; 3116 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 3117 goto out; 3118 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 3119 goto out; 3120 r = 0; 3121 vcpu->arch.mcg_cap = mcg_cap; 3122 /* Init IA32_MCG_CTL to all 1s */ 3123 if (mcg_cap & MCG_CTL_P) 3124 vcpu->arch.mcg_ctl = ~(u64)0; 3125 /* Init IA32_MCi_CTL to all 1s */ 3126 for (bank = 0; bank < bank_num; bank++) 3127 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 3128 3129 if (kvm_x86_ops->setup_mce) 3130 kvm_x86_ops->setup_mce(vcpu); 3131 out: 3132 return r; 3133 } 3134 3135 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 3136 struct kvm_x86_mce *mce) 3137 { 3138 u64 mcg_cap = vcpu->arch.mcg_cap; 3139 unsigned bank_num = mcg_cap & 0xff; 3140 u64 *banks = vcpu->arch.mce_banks; 3141 3142 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 3143 return -EINVAL; 3144 /* 3145 * if IA32_MCG_CTL is not all 1s, the uncorrected error 3146 * reporting is disabled 3147 */ 3148 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 3149 vcpu->arch.mcg_ctl != ~(u64)0) 3150 return 0; 3151 banks += 4 * mce->bank; 3152 /* 3153 * if IA32_MCi_CTL is not all 1s, the uncorrected error 3154 * reporting is disabled for the bank 3155 */ 3156 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 3157 return 0; 3158 if (mce->status & MCI_STATUS_UC) { 3159 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 3160 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 3161 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 3162 return 0; 3163 } 3164 if (banks[1] & MCI_STATUS_VAL) 3165 mce->status |= MCI_STATUS_OVER; 3166 banks[2] = mce->addr; 3167 banks[3] = mce->misc; 3168 vcpu->arch.mcg_status = mce->mcg_status; 3169 banks[1] = mce->status; 3170 kvm_queue_exception(vcpu, MC_VECTOR); 3171 } else if (!(banks[1] & MCI_STATUS_VAL) 3172 || !(banks[1] & MCI_STATUS_UC)) { 3173 if (banks[1] & MCI_STATUS_VAL) 3174 mce->status |= MCI_STATUS_OVER; 3175 banks[2] = mce->addr; 3176 banks[3] = mce->misc; 3177 banks[1] = mce->status; 3178 } else 3179 banks[1] |= MCI_STATUS_OVER; 3180 return 0; 3181 } 3182 3183 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 3184 struct kvm_vcpu_events *events) 3185 { 3186 process_nmi(vcpu); 3187 /* 3188 * FIXME: pass injected and pending separately. This is only 3189 * needed for nested virtualization, whose state cannot be 3190 * migrated yet. For now we can combine them. 3191 */ 3192 events->exception.injected = 3193 (vcpu->arch.exception.pending || 3194 vcpu->arch.exception.injected) && 3195 !kvm_exception_is_soft(vcpu->arch.exception.nr); 3196 events->exception.nr = vcpu->arch.exception.nr; 3197 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 3198 events->exception.pad = 0; 3199 events->exception.error_code = vcpu->arch.exception.error_code; 3200 3201 events->interrupt.injected = 3202 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; 3203 events->interrupt.nr = vcpu->arch.interrupt.nr; 3204 events->interrupt.soft = 0; 3205 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 3206 3207 events->nmi.injected = vcpu->arch.nmi_injected; 3208 events->nmi.pending = vcpu->arch.nmi_pending != 0; 3209 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 3210 events->nmi.pad = 0; 3211 3212 events->sipi_vector = 0; /* never valid when reporting to user space */ 3213 3214 events->smi.smm = is_smm(vcpu); 3215 events->smi.pending = vcpu->arch.smi_pending; 3216 events->smi.smm_inside_nmi = 3217 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 3218 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 3219 3220 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 3221 | KVM_VCPUEVENT_VALID_SHADOW 3222 | KVM_VCPUEVENT_VALID_SMM); 3223 memset(&events->reserved, 0, sizeof(events->reserved)); 3224 } 3225 3226 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags); 3227 3228 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 3229 struct kvm_vcpu_events *events) 3230 { 3231 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 3232 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 3233 | KVM_VCPUEVENT_VALID_SHADOW 3234 | KVM_VCPUEVENT_VALID_SMM)) 3235 return -EINVAL; 3236 3237 if (events->exception.injected && 3238 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR || 3239 is_guest_mode(vcpu))) 3240 return -EINVAL; 3241 3242 /* INITs are latched while in SMM */ 3243 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 3244 (events->smi.smm || events->smi.pending) && 3245 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 3246 return -EINVAL; 3247 3248 process_nmi(vcpu); 3249 vcpu->arch.exception.injected = false; 3250 vcpu->arch.exception.pending = events->exception.injected; 3251 vcpu->arch.exception.nr = events->exception.nr; 3252 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 3253 vcpu->arch.exception.error_code = events->exception.error_code; 3254 3255 vcpu->arch.interrupt.pending = events->interrupt.injected; 3256 vcpu->arch.interrupt.nr = events->interrupt.nr; 3257 vcpu->arch.interrupt.soft = events->interrupt.soft; 3258 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3259 kvm_x86_ops->set_interrupt_shadow(vcpu, 3260 events->interrupt.shadow); 3261 3262 vcpu->arch.nmi_injected = events->nmi.injected; 3263 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3264 vcpu->arch.nmi_pending = events->nmi.pending; 3265 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 3266 3267 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3268 lapic_in_kernel(vcpu)) 3269 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3270 3271 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 3272 u32 hflags = vcpu->arch.hflags; 3273 if (events->smi.smm) 3274 hflags |= HF_SMM_MASK; 3275 else 3276 hflags &= ~HF_SMM_MASK; 3277 kvm_set_hflags(vcpu, hflags); 3278 3279 vcpu->arch.smi_pending = events->smi.pending; 3280 3281 if (events->smi.smm) { 3282 if (events->smi.smm_inside_nmi) 3283 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 3284 else 3285 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 3286 if (lapic_in_kernel(vcpu)) { 3287 if (events->smi.latched_init) 3288 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3289 else 3290 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3291 } 3292 } 3293 } 3294 3295 kvm_make_request(KVM_REQ_EVENT, vcpu); 3296 3297 return 0; 3298 } 3299 3300 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3301 struct kvm_debugregs *dbgregs) 3302 { 3303 unsigned long val; 3304 3305 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3306 kvm_get_dr(vcpu, 6, &val); 3307 dbgregs->dr6 = val; 3308 dbgregs->dr7 = vcpu->arch.dr7; 3309 dbgregs->flags = 0; 3310 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3311 } 3312 3313 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3314 struct kvm_debugregs *dbgregs) 3315 { 3316 if (dbgregs->flags) 3317 return -EINVAL; 3318 3319 if (dbgregs->dr6 & ~0xffffffffull) 3320 return -EINVAL; 3321 if (dbgregs->dr7 & ~0xffffffffull) 3322 return -EINVAL; 3323 3324 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3325 kvm_update_dr0123(vcpu); 3326 vcpu->arch.dr6 = dbgregs->dr6; 3327 kvm_update_dr6(vcpu); 3328 vcpu->arch.dr7 = dbgregs->dr7; 3329 kvm_update_dr7(vcpu); 3330 3331 return 0; 3332 } 3333 3334 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3335 3336 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3337 { 3338 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3339 u64 xstate_bv = xsave->header.xfeatures; 3340 u64 valid; 3341 3342 /* 3343 * Copy legacy XSAVE area, to avoid complications with CPUID 3344 * leaves 0 and 1 in the loop below. 3345 */ 3346 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3347 3348 /* Set XSTATE_BV */ 3349 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; 3350 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3351 3352 /* 3353 * Copy each region from the possibly compacted offset to the 3354 * non-compacted offset. 3355 */ 3356 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3357 while (valid) { 3358 u64 feature = valid & -valid; 3359 int index = fls64(feature) - 1; 3360 void *src = get_xsave_addr(xsave, feature); 3361 3362 if (src) { 3363 u32 size, offset, ecx, edx; 3364 cpuid_count(XSTATE_CPUID, index, 3365 &size, &offset, &ecx, &edx); 3366 if (feature == XFEATURE_MASK_PKRU) 3367 memcpy(dest + offset, &vcpu->arch.pkru, 3368 sizeof(vcpu->arch.pkru)); 3369 else 3370 memcpy(dest + offset, src, size); 3371 3372 } 3373 3374 valid -= feature; 3375 } 3376 } 3377 3378 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3379 { 3380 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3381 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3382 u64 valid; 3383 3384 /* 3385 * Copy legacy XSAVE area, to avoid complications with CPUID 3386 * leaves 0 and 1 in the loop below. 3387 */ 3388 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3389 3390 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3391 xsave->header.xfeatures = xstate_bv; 3392 if (boot_cpu_has(X86_FEATURE_XSAVES)) 3393 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3394 3395 /* 3396 * Copy each region from the non-compacted offset to the 3397 * possibly compacted offset. 3398 */ 3399 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3400 while (valid) { 3401 u64 feature = valid & -valid; 3402 int index = fls64(feature) - 1; 3403 void *dest = get_xsave_addr(xsave, feature); 3404 3405 if (dest) { 3406 u32 size, offset, ecx, edx; 3407 cpuid_count(XSTATE_CPUID, index, 3408 &size, &offset, &ecx, &edx); 3409 if (feature == XFEATURE_MASK_PKRU) 3410 memcpy(&vcpu->arch.pkru, src + offset, 3411 sizeof(vcpu->arch.pkru)); 3412 else 3413 memcpy(dest, src + offset, size); 3414 } 3415 3416 valid -= feature; 3417 } 3418 } 3419 3420 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3421 struct kvm_xsave *guest_xsave) 3422 { 3423 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3424 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3425 fill_xsave((u8 *) guest_xsave->region, vcpu); 3426 } else { 3427 memcpy(guest_xsave->region, 3428 &vcpu->arch.guest_fpu.state.fxsave, 3429 sizeof(struct fxregs_state)); 3430 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3431 XFEATURE_MASK_FPSSE; 3432 } 3433 } 3434 3435 #define XSAVE_MXCSR_OFFSET 24 3436 3437 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3438 struct kvm_xsave *guest_xsave) 3439 { 3440 u64 xstate_bv = 3441 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3442 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; 3443 3444 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3445 /* 3446 * Here we allow setting states that are not present in 3447 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3448 * with old userspace. 3449 */ 3450 if (xstate_bv & ~kvm_supported_xcr0() || 3451 mxcsr & ~mxcsr_feature_mask) 3452 return -EINVAL; 3453 load_xsave(vcpu, (u8 *)guest_xsave->region); 3454 } else { 3455 if (xstate_bv & ~XFEATURE_MASK_FPSSE || 3456 mxcsr & ~mxcsr_feature_mask) 3457 return -EINVAL; 3458 memcpy(&vcpu->arch.guest_fpu.state.fxsave, 3459 guest_xsave->region, sizeof(struct fxregs_state)); 3460 } 3461 return 0; 3462 } 3463 3464 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3465 struct kvm_xcrs *guest_xcrs) 3466 { 3467 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 3468 guest_xcrs->nr_xcrs = 0; 3469 return; 3470 } 3471 3472 guest_xcrs->nr_xcrs = 1; 3473 guest_xcrs->flags = 0; 3474 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3475 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3476 } 3477 3478 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3479 struct kvm_xcrs *guest_xcrs) 3480 { 3481 int i, r = 0; 3482 3483 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 3484 return -EINVAL; 3485 3486 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3487 return -EINVAL; 3488 3489 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3490 /* Only support XCR0 currently */ 3491 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3492 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3493 guest_xcrs->xcrs[i].value); 3494 break; 3495 } 3496 if (r) 3497 r = -EINVAL; 3498 return r; 3499 } 3500 3501 /* 3502 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3503 * stopped by the hypervisor. This function will be called from the host only. 3504 * EINVAL is returned when the host attempts to set the flag for a guest that 3505 * does not support pv clocks. 3506 */ 3507 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3508 { 3509 if (!vcpu->arch.pv_time_enabled) 3510 return -EINVAL; 3511 vcpu->arch.pvclock_set_guest_stopped_request = true; 3512 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3513 return 0; 3514 } 3515 3516 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 3517 struct kvm_enable_cap *cap) 3518 { 3519 if (cap->flags) 3520 return -EINVAL; 3521 3522 switch (cap->cap) { 3523 case KVM_CAP_HYPERV_SYNIC2: 3524 if (cap->args[0]) 3525 return -EINVAL; 3526 case KVM_CAP_HYPERV_SYNIC: 3527 if (!irqchip_in_kernel(vcpu->kvm)) 3528 return -EINVAL; 3529 return kvm_hv_activate_synic(vcpu, cap->cap == 3530 KVM_CAP_HYPERV_SYNIC2); 3531 default: 3532 return -EINVAL; 3533 } 3534 } 3535 3536 long kvm_arch_vcpu_ioctl(struct file *filp, 3537 unsigned int ioctl, unsigned long arg) 3538 { 3539 struct kvm_vcpu *vcpu = filp->private_data; 3540 void __user *argp = (void __user *)arg; 3541 int r; 3542 union { 3543 struct kvm_lapic_state *lapic; 3544 struct kvm_xsave *xsave; 3545 struct kvm_xcrs *xcrs; 3546 void *buffer; 3547 } u; 3548 3549 vcpu_load(vcpu); 3550 3551 u.buffer = NULL; 3552 switch (ioctl) { 3553 case KVM_GET_LAPIC: { 3554 r = -EINVAL; 3555 if (!lapic_in_kernel(vcpu)) 3556 goto out; 3557 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3558 3559 r = -ENOMEM; 3560 if (!u.lapic) 3561 goto out; 3562 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3563 if (r) 3564 goto out; 3565 r = -EFAULT; 3566 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3567 goto out; 3568 r = 0; 3569 break; 3570 } 3571 case KVM_SET_LAPIC: { 3572 r = -EINVAL; 3573 if (!lapic_in_kernel(vcpu)) 3574 goto out; 3575 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3576 if (IS_ERR(u.lapic)) { 3577 r = PTR_ERR(u.lapic); 3578 goto out_nofree; 3579 } 3580 3581 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3582 break; 3583 } 3584 case KVM_INTERRUPT: { 3585 struct kvm_interrupt irq; 3586 3587 r = -EFAULT; 3588 if (copy_from_user(&irq, argp, sizeof irq)) 3589 goto out; 3590 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3591 break; 3592 } 3593 case KVM_NMI: { 3594 r = kvm_vcpu_ioctl_nmi(vcpu); 3595 break; 3596 } 3597 case KVM_SMI: { 3598 r = kvm_vcpu_ioctl_smi(vcpu); 3599 break; 3600 } 3601 case KVM_SET_CPUID: { 3602 struct kvm_cpuid __user *cpuid_arg = argp; 3603 struct kvm_cpuid cpuid; 3604 3605 r = -EFAULT; 3606 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3607 goto out; 3608 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3609 break; 3610 } 3611 case KVM_SET_CPUID2: { 3612 struct kvm_cpuid2 __user *cpuid_arg = argp; 3613 struct kvm_cpuid2 cpuid; 3614 3615 r = -EFAULT; 3616 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3617 goto out; 3618 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3619 cpuid_arg->entries); 3620 break; 3621 } 3622 case KVM_GET_CPUID2: { 3623 struct kvm_cpuid2 __user *cpuid_arg = argp; 3624 struct kvm_cpuid2 cpuid; 3625 3626 r = -EFAULT; 3627 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3628 goto out; 3629 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3630 cpuid_arg->entries); 3631 if (r) 3632 goto out; 3633 r = -EFAULT; 3634 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3635 goto out; 3636 r = 0; 3637 break; 3638 } 3639 case KVM_GET_MSRS: 3640 r = msr_io(vcpu, argp, do_get_msr, 1); 3641 break; 3642 case KVM_SET_MSRS: 3643 r = msr_io(vcpu, argp, do_set_msr, 0); 3644 break; 3645 case KVM_TPR_ACCESS_REPORTING: { 3646 struct kvm_tpr_access_ctl tac; 3647 3648 r = -EFAULT; 3649 if (copy_from_user(&tac, argp, sizeof tac)) 3650 goto out; 3651 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3652 if (r) 3653 goto out; 3654 r = -EFAULT; 3655 if (copy_to_user(argp, &tac, sizeof tac)) 3656 goto out; 3657 r = 0; 3658 break; 3659 }; 3660 case KVM_SET_VAPIC_ADDR: { 3661 struct kvm_vapic_addr va; 3662 int idx; 3663 3664 r = -EINVAL; 3665 if (!lapic_in_kernel(vcpu)) 3666 goto out; 3667 r = -EFAULT; 3668 if (copy_from_user(&va, argp, sizeof va)) 3669 goto out; 3670 idx = srcu_read_lock(&vcpu->kvm->srcu); 3671 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3672 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3673 break; 3674 } 3675 case KVM_X86_SETUP_MCE: { 3676 u64 mcg_cap; 3677 3678 r = -EFAULT; 3679 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3680 goto out; 3681 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3682 break; 3683 } 3684 case KVM_X86_SET_MCE: { 3685 struct kvm_x86_mce mce; 3686 3687 r = -EFAULT; 3688 if (copy_from_user(&mce, argp, sizeof mce)) 3689 goto out; 3690 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3691 break; 3692 } 3693 case KVM_GET_VCPU_EVENTS: { 3694 struct kvm_vcpu_events events; 3695 3696 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3697 3698 r = -EFAULT; 3699 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3700 break; 3701 r = 0; 3702 break; 3703 } 3704 case KVM_SET_VCPU_EVENTS: { 3705 struct kvm_vcpu_events events; 3706 3707 r = -EFAULT; 3708 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3709 break; 3710 3711 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3712 break; 3713 } 3714 case KVM_GET_DEBUGREGS: { 3715 struct kvm_debugregs dbgregs; 3716 3717 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3718 3719 r = -EFAULT; 3720 if (copy_to_user(argp, &dbgregs, 3721 sizeof(struct kvm_debugregs))) 3722 break; 3723 r = 0; 3724 break; 3725 } 3726 case KVM_SET_DEBUGREGS: { 3727 struct kvm_debugregs dbgregs; 3728 3729 r = -EFAULT; 3730 if (copy_from_user(&dbgregs, argp, 3731 sizeof(struct kvm_debugregs))) 3732 break; 3733 3734 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3735 break; 3736 } 3737 case KVM_GET_XSAVE: { 3738 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3739 r = -ENOMEM; 3740 if (!u.xsave) 3741 break; 3742 3743 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3744 3745 r = -EFAULT; 3746 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3747 break; 3748 r = 0; 3749 break; 3750 } 3751 case KVM_SET_XSAVE: { 3752 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3753 if (IS_ERR(u.xsave)) { 3754 r = PTR_ERR(u.xsave); 3755 goto out_nofree; 3756 } 3757 3758 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3759 break; 3760 } 3761 case KVM_GET_XCRS: { 3762 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3763 r = -ENOMEM; 3764 if (!u.xcrs) 3765 break; 3766 3767 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3768 3769 r = -EFAULT; 3770 if (copy_to_user(argp, u.xcrs, 3771 sizeof(struct kvm_xcrs))) 3772 break; 3773 r = 0; 3774 break; 3775 } 3776 case KVM_SET_XCRS: { 3777 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3778 if (IS_ERR(u.xcrs)) { 3779 r = PTR_ERR(u.xcrs); 3780 goto out_nofree; 3781 } 3782 3783 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3784 break; 3785 } 3786 case KVM_SET_TSC_KHZ: { 3787 u32 user_tsc_khz; 3788 3789 r = -EINVAL; 3790 user_tsc_khz = (u32)arg; 3791 3792 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3793 goto out; 3794 3795 if (user_tsc_khz == 0) 3796 user_tsc_khz = tsc_khz; 3797 3798 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 3799 r = 0; 3800 3801 goto out; 3802 } 3803 case KVM_GET_TSC_KHZ: { 3804 r = vcpu->arch.virtual_tsc_khz; 3805 goto out; 3806 } 3807 case KVM_KVMCLOCK_CTRL: { 3808 r = kvm_set_guest_paused(vcpu); 3809 goto out; 3810 } 3811 case KVM_ENABLE_CAP: { 3812 struct kvm_enable_cap cap; 3813 3814 r = -EFAULT; 3815 if (copy_from_user(&cap, argp, sizeof(cap))) 3816 goto out; 3817 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 3818 break; 3819 } 3820 default: 3821 r = -EINVAL; 3822 } 3823 out: 3824 kfree(u.buffer); 3825 out_nofree: 3826 vcpu_put(vcpu); 3827 return r; 3828 } 3829 3830 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3831 { 3832 return VM_FAULT_SIGBUS; 3833 } 3834 3835 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3836 { 3837 int ret; 3838 3839 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3840 return -EINVAL; 3841 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3842 return ret; 3843 } 3844 3845 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3846 u64 ident_addr) 3847 { 3848 kvm->arch.ept_identity_map_addr = ident_addr; 3849 return 0; 3850 } 3851 3852 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3853 u32 kvm_nr_mmu_pages) 3854 { 3855 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3856 return -EINVAL; 3857 3858 mutex_lock(&kvm->slots_lock); 3859 3860 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3861 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3862 3863 mutex_unlock(&kvm->slots_lock); 3864 return 0; 3865 } 3866 3867 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 3868 { 3869 return kvm->arch.n_max_mmu_pages; 3870 } 3871 3872 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3873 { 3874 struct kvm_pic *pic = kvm->arch.vpic; 3875 int r; 3876 3877 r = 0; 3878 switch (chip->chip_id) { 3879 case KVM_IRQCHIP_PIC_MASTER: 3880 memcpy(&chip->chip.pic, &pic->pics[0], 3881 sizeof(struct kvm_pic_state)); 3882 break; 3883 case KVM_IRQCHIP_PIC_SLAVE: 3884 memcpy(&chip->chip.pic, &pic->pics[1], 3885 sizeof(struct kvm_pic_state)); 3886 break; 3887 case KVM_IRQCHIP_IOAPIC: 3888 kvm_get_ioapic(kvm, &chip->chip.ioapic); 3889 break; 3890 default: 3891 r = -EINVAL; 3892 break; 3893 } 3894 return r; 3895 } 3896 3897 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3898 { 3899 struct kvm_pic *pic = kvm->arch.vpic; 3900 int r; 3901 3902 r = 0; 3903 switch (chip->chip_id) { 3904 case KVM_IRQCHIP_PIC_MASTER: 3905 spin_lock(&pic->lock); 3906 memcpy(&pic->pics[0], &chip->chip.pic, 3907 sizeof(struct kvm_pic_state)); 3908 spin_unlock(&pic->lock); 3909 break; 3910 case KVM_IRQCHIP_PIC_SLAVE: 3911 spin_lock(&pic->lock); 3912 memcpy(&pic->pics[1], &chip->chip.pic, 3913 sizeof(struct kvm_pic_state)); 3914 spin_unlock(&pic->lock); 3915 break; 3916 case KVM_IRQCHIP_IOAPIC: 3917 kvm_set_ioapic(kvm, &chip->chip.ioapic); 3918 break; 3919 default: 3920 r = -EINVAL; 3921 break; 3922 } 3923 kvm_pic_update_irq(pic); 3924 return r; 3925 } 3926 3927 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3928 { 3929 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 3930 3931 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 3932 3933 mutex_lock(&kps->lock); 3934 memcpy(ps, &kps->channels, sizeof(*ps)); 3935 mutex_unlock(&kps->lock); 3936 return 0; 3937 } 3938 3939 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3940 { 3941 int i; 3942 struct kvm_pit *pit = kvm->arch.vpit; 3943 3944 mutex_lock(&pit->pit_state.lock); 3945 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 3946 for (i = 0; i < 3; i++) 3947 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 3948 mutex_unlock(&pit->pit_state.lock); 3949 return 0; 3950 } 3951 3952 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3953 { 3954 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3955 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 3956 sizeof(ps->channels)); 3957 ps->flags = kvm->arch.vpit->pit_state.flags; 3958 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3959 memset(&ps->reserved, 0, sizeof(ps->reserved)); 3960 return 0; 3961 } 3962 3963 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3964 { 3965 int start = 0; 3966 int i; 3967 u32 prev_legacy, cur_legacy; 3968 struct kvm_pit *pit = kvm->arch.vpit; 3969 3970 mutex_lock(&pit->pit_state.lock); 3971 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 3972 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 3973 if (!prev_legacy && cur_legacy) 3974 start = 1; 3975 memcpy(&pit->pit_state.channels, &ps->channels, 3976 sizeof(pit->pit_state.channels)); 3977 pit->pit_state.flags = ps->flags; 3978 for (i = 0; i < 3; i++) 3979 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 3980 start && i == 0); 3981 mutex_unlock(&pit->pit_state.lock); 3982 return 0; 3983 } 3984 3985 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 3986 struct kvm_reinject_control *control) 3987 { 3988 struct kvm_pit *pit = kvm->arch.vpit; 3989 3990 if (!pit) 3991 return -ENXIO; 3992 3993 /* pit->pit_state.lock was overloaded to prevent userspace from getting 3994 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 3995 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 3996 */ 3997 mutex_lock(&pit->pit_state.lock); 3998 kvm_pit_set_reinject(pit, control->pit_reinject); 3999 mutex_unlock(&pit->pit_state.lock); 4000 4001 return 0; 4002 } 4003 4004 /** 4005 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 4006 * @kvm: kvm instance 4007 * @log: slot id and address to which we copy the log 4008 * 4009 * Steps 1-4 below provide general overview of dirty page logging. See 4010 * kvm_get_dirty_log_protect() function description for additional details. 4011 * 4012 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 4013 * always flush the TLB (step 4) even if previous step failed and the dirty 4014 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 4015 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 4016 * writes will be marked dirty for next log read. 4017 * 4018 * 1. Take a snapshot of the bit and clear it if needed. 4019 * 2. Write protect the corresponding page. 4020 * 3. Copy the snapshot to the userspace. 4021 * 4. Flush TLB's if needed. 4022 */ 4023 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 4024 { 4025 bool is_dirty = false; 4026 int r; 4027 4028 mutex_lock(&kvm->slots_lock); 4029 4030 /* 4031 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 4032 */ 4033 if (kvm_x86_ops->flush_log_dirty) 4034 kvm_x86_ops->flush_log_dirty(kvm); 4035 4036 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 4037 4038 /* 4039 * All the TLBs can be flushed out of mmu lock, see the comments in 4040 * kvm_mmu_slot_remove_write_access(). 4041 */ 4042 lockdep_assert_held(&kvm->slots_lock); 4043 if (is_dirty) 4044 kvm_flush_remote_tlbs(kvm); 4045 4046 mutex_unlock(&kvm->slots_lock); 4047 return r; 4048 } 4049 4050 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 4051 bool line_status) 4052 { 4053 if (!irqchip_in_kernel(kvm)) 4054 return -ENXIO; 4055 4056 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 4057 irq_event->irq, irq_event->level, 4058 line_status); 4059 return 0; 4060 } 4061 4062 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 4063 struct kvm_enable_cap *cap) 4064 { 4065 int r; 4066 4067 if (cap->flags) 4068 return -EINVAL; 4069 4070 switch (cap->cap) { 4071 case KVM_CAP_DISABLE_QUIRKS: 4072 kvm->arch.disabled_quirks = cap->args[0]; 4073 r = 0; 4074 break; 4075 case KVM_CAP_SPLIT_IRQCHIP: { 4076 mutex_lock(&kvm->lock); 4077 r = -EINVAL; 4078 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 4079 goto split_irqchip_unlock; 4080 r = -EEXIST; 4081 if (irqchip_in_kernel(kvm)) 4082 goto split_irqchip_unlock; 4083 if (kvm->created_vcpus) 4084 goto split_irqchip_unlock; 4085 r = kvm_setup_empty_irq_routing(kvm); 4086 if (r) 4087 goto split_irqchip_unlock; 4088 /* Pairs with irqchip_in_kernel. */ 4089 smp_wmb(); 4090 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 4091 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 4092 r = 0; 4093 split_irqchip_unlock: 4094 mutex_unlock(&kvm->lock); 4095 break; 4096 } 4097 case KVM_CAP_X2APIC_API: 4098 r = -EINVAL; 4099 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 4100 break; 4101 4102 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 4103 kvm->arch.x2apic_format = true; 4104 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 4105 kvm->arch.x2apic_broadcast_quirk_disabled = true; 4106 4107 r = 0; 4108 break; 4109 default: 4110 r = -EINVAL; 4111 break; 4112 } 4113 return r; 4114 } 4115 4116 long kvm_arch_vm_ioctl(struct file *filp, 4117 unsigned int ioctl, unsigned long arg) 4118 { 4119 struct kvm *kvm = filp->private_data; 4120 void __user *argp = (void __user *)arg; 4121 int r = -ENOTTY; 4122 /* 4123 * This union makes it completely explicit to gcc-3.x 4124 * that these two variables' stack usage should be 4125 * combined, not added together. 4126 */ 4127 union { 4128 struct kvm_pit_state ps; 4129 struct kvm_pit_state2 ps2; 4130 struct kvm_pit_config pit_config; 4131 } u; 4132 4133 switch (ioctl) { 4134 case KVM_SET_TSS_ADDR: 4135 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 4136 break; 4137 case KVM_SET_IDENTITY_MAP_ADDR: { 4138 u64 ident_addr; 4139 4140 mutex_lock(&kvm->lock); 4141 r = -EINVAL; 4142 if (kvm->created_vcpus) 4143 goto set_identity_unlock; 4144 r = -EFAULT; 4145 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 4146 goto set_identity_unlock; 4147 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 4148 set_identity_unlock: 4149 mutex_unlock(&kvm->lock); 4150 break; 4151 } 4152 case KVM_SET_NR_MMU_PAGES: 4153 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 4154 break; 4155 case KVM_GET_NR_MMU_PAGES: 4156 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 4157 break; 4158 case KVM_CREATE_IRQCHIP: { 4159 mutex_lock(&kvm->lock); 4160 4161 r = -EEXIST; 4162 if (irqchip_in_kernel(kvm)) 4163 goto create_irqchip_unlock; 4164 4165 r = -EINVAL; 4166 if (kvm->created_vcpus) 4167 goto create_irqchip_unlock; 4168 4169 r = kvm_pic_init(kvm); 4170 if (r) 4171 goto create_irqchip_unlock; 4172 4173 r = kvm_ioapic_init(kvm); 4174 if (r) { 4175 kvm_pic_destroy(kvm); 4176 goto create_irqchip_unlock; 4177 } 4178 4179 r = kvm_setup_default_irq_routing(kvm); 4180 if (r) { 4181 kvm_ioapic_destroy(kvm); 4182 kvm_pic_destroy(kvm); 4183 goto create_irqchip_unlock; 4184 } 4185 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 4186 smp_wmb(); 4187 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 4188 create_irqchip_unlock: 4189 mutex_unlock(&kvm->lock); 4190 break; 4191 } 4192 case KVM_CREATE_PIT: 4193 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 4194 goto create_pit; 4195 case KVM_CREATE_PIT2: 4196 r = -EFAULT; 4197 if (copy_from_user(&u.pit_config, argp, 4198 sizeof(struct kvm_pit_config))) 4199 goto out; 4200 create_pit: 4201 mutex_lock(&kvm->lock); 4202 r = -EEXIST; 4203 if (kvm->arch.vpit) 4204 goto create_pit_unlock; 4205 r = -ENOMEM; 4206 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 4207 if (kvm->arch.vpit) 4208 r = 0; 4209 create_pit_unlock: 4210 mutex_unlock(&kvm->lock); 4211 break; 4212 case KVM_GET_IRQCHIP: { 4213 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4214 struct kvm_irqchip *chip; 4215 4216 chip = memdup_user(argp, sizeof(*chip)); 4217 if (IS_ERR(chip)) { 4218 r = PTR_ERR(chip); 4219 goto out; 4220 } 4221 4222 r = -ENXIO; 4223 if (!irqchip_kernel(kvm)) 4224 goto get_irqchip_out; 4225 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 4226 if (r) 4227 goto get_irqchip_out; 4228 r = -EFAULT; 4229 if (copy_to_user(argp, chip, sizeof *chip)) 4230 goto get_irqchip_out; 4231 r = 0; 4232 get_irqchip_out: 4233 kfree(chip); 4234 break; 4235 } 4236 case KVM_SET_IRQCHIP: { 4237 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4238 struct kvm_irqchip *chip; 4239 4240 chip = memdup_user(argp, sizeof(*chip)); 4241 if (IS_ERR(chip)) { 4242 r = PTR_ERR(chip); 4243 goto out; 4244 } 4245 4246 r = -ENXIO; 4247 if (!irqchip_kernel(kvm)) 4248 goto set_irqchip_out; 4249 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 4250 if (r) 4251 goto set_irqchip_out; 4252 r = 0; 4253 set_irqchip_out: 4254 kfree(chip); 4255 break; 4256 } 4257 case KVM_GET_PIT: { 4258 r = -EFAULT; 4259 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 4260 goto out; 4261 r = -ENXIO; 4262 if (!kvm->arch.vpit) 4263 goto out; 4264 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 4265 if (r) 4266 goto out; 4267 r = -EFAULT; 4268 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 4269 goto out; 4270 r = 0; 4271 break; 4272 } 4273 case KVM_SET_PIT: { 4274 r = -EFAULT; 4275 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 4276 goto out; 4277 r = -ENXIO; 4278 if (!kvm->arch.vpit) 4279 goto out; 4280 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 4281 break; 4282 } 4283 case KVM_GET_PIT2: { 4284 r = -ENXIO; 4285 if (!kvm->arch.vpit) 4286 goto out; 4287 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 4288 if (r) 4289 goto out; 4290 r = -EFAULT; 4291 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 4292 goto out; 4293 r = 0; 4294 break; 4295 } 4296 case KVM_SET_PIT2: { 4297 r = -EFAULT; 4298 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 4299 goto out; 4300 r = -ENXIO; 4301 if (!kvm->arch.vpit) 4302 goto out; 4303 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 4304 break; 4305 } 4306 case KVM_REINJECT_CONTROL: { 4307 struct kvm_reinject_control control; 4308 r = -EFAULT; 4309 if (copy_from_user(&control, argp, sizeof(control))) 4310 goto out; 4311 r = kvm_vm_ioctl_reinject(kvm, &control); 4312 break; 4313 } 4314 case KVM_SET_BOOT_CPU_ID: 4315 r = 0; 4316 mutex_lock(&kvm->lock); 4317 if (kvm->created_vcpus) 4318 r = -EBUSY; 4319 else 4320 kvm->arch.bsp_vcpu_id = arg; 4321 mutex_unlock(&kvm->lock); 4322 break; 4323 case KVM_XEN_HVM_CONFIG: { 4324 struct kvm_xen_hvm_config xhc; 4325 r = -EFAULT; 4326 if (copy_from_user(&xhc, argp, sizeof(xhc))) 4327 goto out; 4328 r = -EINVAL; 4329 if (xhc.flags) 4330 goto out; 4331 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); 4332 r = 0; 4333 break; 4334 } 4335 case KVM_SET_CLOCK: { 4336 struct kvm_clock_data user_ns; 4337 u64 now_ns; 4338 4339 r = -EFAULT; 4340 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 4341 goto out; 4342 4343 r = -EINVAL; 4344 if (user_ns.flags) 4345 goto out; 4346 4347 r = 0; 4348 /* 4349 * TODO: userspace has to take care of races with VCPU_RUN, so 4350 * kvm_gen_update_masterclock() can be cut down to locked 4351 * pvclock_update_vm_gtod_copy(). 4352 */ 4353 kvm_gen_update_masterclock(kvm); 4354 now_ns = get_kvmclock_ns(kvm); 4355 kvm->arch.kvmclock_offset += user_ns.clock - now_ns; 4356 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); 4357 break; 4358 } 4359 case KVM_GET_CLOCK: { 4360 struct kvm_clock_data user_ns; 4361 u64 now_ns; 4362 4363 now_ns = get_kvmclock_ns(kvm); 4364 user_ns.clock = now_ns; 4365 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 4366 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 4367 4368 r = -EFAULT; 4369 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 4370 goto out; 4371 r = 0; 4372 break; 4373 } 4374 case KVM_ENABLE_CAP: { 4375 struct kvm_enable_cap cap; 4376 4377 r = -EFAULT; 4378 if (copy_from_user(&cap, argp, sizeof(cap))) 4379 goto out; 4380 r = kvm_vm_ioctl_enable_cap(kvm, &cap); 4381 break; 4382 } 4383 case KVM_MEMORY_ENCRYPT_OP: { 4384 r = -ENOTTY; 4385 if (kvm_x86_ops->mem_enc_op) 4386 r = kvm_x86_ops->mem_enc_op(kvm, argp); 4387 break; 4388 } 4389 case KVM_MEMORY_ENCRYPT_REG_REGION: { 4390 struct kvm_enc_region region; 4391 4392 r = -EFAULT; 4393 if (copy_from_user(®ion, argp, sizeof(region))) 4394 goto out; 4395 4396 r = -ENOTTY; 4397 if (kvm_x86_ops->mem_enc_reg_region) 4398 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion); 4399 break; 4400 } 4401 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 4402 struct kvm_enc_region region; 4403 4404 r = -EFAULT; 4405 if (copy_from_user(®ion, argp, sizeof(region))) 4406 goto out; 4407 4408 r = -ENOTTY; 4409 if (kvm_x86_ops->mem_enc_unreg_region) 4410 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion); 4411 break; 4412 } 4413 default: 4414 r = -ENOTTY; 4415 } 4416 out: 4417 return r; 4418 } 4419 4420 static void kvm_init_msr_list(void) 4421 { 4422 u32 dummy[2]; 4423 unsigned i, j; 4424 4425 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { 4426 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4427 continue; 4428 4429 /* 4430 * Even MSRs that are valid in the host may not be exposed 4431 * to the guests in some cases. 4432 */ 4433 switch (msrs_to_save[i]) { 4434 case MSR_IA32_BNDCFGS: 4435 if (!kvm_x86_ops->mpx_supported()) 4436 continue; 4437 break; 4438 case MSR_TSC_AUX: 4439 if (!kvm_x86_ops->rdtscp_supported()) 4440 continue; 4441 break; 4442 default: 4443 break; 4444 } 4445 4446 if (j < i) 4447 msrs_to_save[j] = msrs_to_save[i]; 4448 j++; 4449 } 4450 num_msrs_to_save = j; 4451 4452 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { 4453 switch (emulated_msrs[i]) { 4454 case MSR_IA32_SMBASE: 4455 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase()) 4456 continue; 4457 break; 4458 default: 4459 break; 4460 } 4461 4462 if (j < i) 4463 emulated_msrs[j] = emulated_msrs[i]; 4464 j++; 4465 } 4466 num_emulated_msrs = j; 4467 } 4468 4469 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 4470 const void *v) 4471 { 4472 int handled = 0; 4473 int n; 4474 4475 do { 4476 n = min(len, 8); 4477 if (!(lapic_in_kernel(vcpu) && 4478 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 4479 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 4480 break; 4481 handled += n; 4482 addr += n; 4483 len -= n; 4484 v += n; 4485 } while (len); 4486 4487 return handled; 4488 } 4489 4490 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4491 { 4492 int handled = 0; 4493 int n; 4494 4495 do { 4496 n = min(len, 8); 4497 if (!(lapic_in_kernel(vcpu) && 4498 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 4499 addr, n, v)) 4500 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 4501 break; 4502 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 4503 handled += n; 4504 addr += n; 4505 len -= n; 4506 v += n; 4507 } while (len); 4508 4509 return handled; 4510 } 4511 4512 static void kvm_set_segment(struct kvm_vcpu *vcpu, 4513 struct kvm_segment *var, int seg) 4514 { 4515 kvm_x86_ops->set_segment(vcpu, var, seg); 4516 } 4517 4518 void kvm_get_segment(struct kvm_vcpu *vcpu, 4519 struct kvm_segment *var, int seg) 4520 { 4521 kvm_x86_ops->get_segment(vcpu, var, seg); 4522 } 4523 4524 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 4525 struct x86_exception *exception) 4526 { 4527 gpa_t t_gpa; 4528 4529 BUG_ON(!mmu_is_nested(vcpu)); 4530 4531 /* NPT walks are always user-walks */ 4532 access |= PFERR_USER_MASK; 4533 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); 4534 4535 return t_gpa; 4536 } 4537 4538 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 4539 struct x86_exception *exception) 4540 { 4541 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4542 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4543 } 4544 4545 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 4546 struct x86_exception *exception) 4547 { 4548 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4549 access |= PFERR_FETCH_MASK; 4550 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4551 } 4552 4553 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 4554 struct x86_exception *exception) 4555 { 4556 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4557 access |= PFERR_WRITE_MASK; 4558 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4559 } 4560 4561 /* uses this to access any guest's mapped memory without checking CPL */ 4562 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 4563 struct x86_exception *exception) 4564 { 4565 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 4566 } 4567 4568 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 4569 struct kvm_vcpu *vcpu, u32 access, 4570 struct x86_exception *exception) 4571 { 4572 void *data = val; 4573 int r = X86EMUL_CONTINUE; 4574 4575 while (bytes) { 4576 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 4577 exception); 4578 unsigned offset = addr & (PAGE_SIZE-1); 4579 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 4580 int ret; 4581 4582 if (gpa == UNMAPPED_GVA) 4583 return X86EMUL_PROPAGATE_FAULT; 4584 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 4585 offset, toread); 4586 if (ret < 0) { 4587 r = X86EMUL_IO_NEEDED; 4588 goto out; 4589 } 4590 4591 bytes -= toread; 4592 data += toread; 4593 addr += toread; 4594 } 4595 out: 4596 return r; 4597 } 4598 4599 /* used for instruction fetching */ 4600 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4601 gva_t addr, void *val, unsigned int bytes, 4602 struct x86_exception *exception) 4603 { 4604 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4605 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4606 unsigned offset; 4607 int ret; 4608 4609 /* Inline kvm_read_guest_virt_helper for speed. */ 4610 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 4611 exception); 4612 if (unlikely(gpa == UNMAPPED_GVA)) 4613 return X86EMUL_PROPAGATE_FAULT; 4614 4615 offset = addr & (PAGE_SIZE-1); 4616 if (WARN_ON(offset + bytes > PAGE_SIZE)) 4617 bytes = (unsigned)PAGE_SIZE - offset; 4618 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 4619 offset, bytes); 4620 if (unlikely(ret < 0)) 4621 return X86EMUL_IO_NEEDED; 4622 4623 return X86EMUL_CONTINUE; 4624 } 4625 4626 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4627 gva_t addr, void *val, unsigned int bytes, 4628 struct x86_exception *exception) 4629 { 4630 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4631 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4632 4633 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4634 exception); 4635 } 4636 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4637 4638 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4639 gva_t addr, void *val, unsigned int bytes, 4640 struct x86_exception *exception) 4641 { 4642 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4643 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4644 } 4645 4646 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 4647 unsigned long addr, void *val, unsigned int bytes) 4648 { 4649 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4650 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 4651 4652 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 4653 } 4654 4655 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4656 gva_t addr, void *val, 4657 unsigned int bytes, 4658 struct x86_exception *exception) 4659 { 4660 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4661 void *data = val; 4662 int r = X86EMUL_CONTINUE; 4663 4664 while (bytes) { 4665 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4666 PFERR_WRITE_MASK, 4667 exception); 4668 unsigned offset = addr & (PAGE_SIZE-1); 4669 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4670 int ret; 4671 4672 if (gpa == UNMAPPED_GVA) 4673 return X86EMUL_PROPAGATE_FAULT; 4674 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 4675 if (ret < 0) { 4676 r = X86EMUL_IO_NEEDED; 4677 goto out; 4678 } 4679 4680 bytes -= towrite; 4681 data += towrite; 4682 addr += towrite; 4683 } 4684 out: 4685 return r; 4686 } 4687 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4688 4689 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4690 gpa_t gpa, bool write) 4691 { 4692 /* For APIC access vmexit */ 4693 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4694 return 1; 4695 4696 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 4697 trace_vcpu_match_mmio(gva, gpa, write, true); 4698 return 1; 4699 } 4700 4701 return 0; 4702 } 4703 4704 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4705 gpa_t *gpa, struct x86_exception *exception, 4706 bool write) 4707 { 4708 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4709 | (write ? PFERR_WRITE_MASK : 0); 4710 4711 /* 4712 * currently PKRU is only applied to ept enabled guest so 4713 * there is no pkey in EPT page table for L1 guest or EPT 4714 * shadow page table for L2 guest. 4715 */ 4716 if (vcpu_match_mmio_gva(vcpu, gva) 4717 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4718 vcpu->arch.access, 0, access)) { 4719 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4720 (gva & (PAGE_SIZE - 1)); 4721 trace_vcpu_match_mmio(gva, *gpa, write, false); 4722 return 1; 4723 } 4724 4725 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4726 4727 if (*gpa == UNMAPPED_GVA) 4728 return -1; 4729 4730 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 4731 } 4732 4733 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4734 const void *val, int bytes) 4735 { 4736 int ret; 4737 4738 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 4739 if (ret < 0) 4740 return 0; 4741 kvm_page_track_write(vcpu, gpa, val, bytes); 4742 return 1; 4743 } 4744 4745 struct read_write_emulator_ops { 4746 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4747 int bytes); 4748 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4749 void *val, int bytes); 4750 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4751 int bytes, void *val); 4752 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4753 void *val, int bytes); 4754 bool write; 4755 }; 4756 4757 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4758 { 4759 if (vcpu->mmio_read_completed) { 4760 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4761 vcpu->mmio_fragments[0].gpa, val); 4762 vcpu->mmio_read_completed = 0; 4763 return 1; 4764 } 4765 4766 return 0; 4767 } 4768 4769 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4770 void *val, int bytes) 4771 { 4772 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 4773 } 4774 4775 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4776 void *val, int bytes) 4777 { 4778 return emulator_write_phys(vcpu, gpa, val, bytes); 4779 } 4780 4781 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4782 { 4783 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 4784 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4785 } 4786 4787 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4788 void *val, int bytes) 4789 { 4790 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 4791 return X86EMUL_IO_NEEDED; 4792 } 4793 4794 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4795 void *val, int bytes) 4796 { 4797 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4798 4799 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4800 return X86EMUL_CONTINUE; 4801 } 4802 4803 static const struct read_write_emulator_ops read_emultor = { 4804 .read_write_prepare = read_prepare, 4805 .read_write_emulate = read_emulate, 4806 .read_write_mmio = vcpu_mmio_read, 4807 .read_write_exit_mmio = read_exit_mmio, 4808 }; 4809 4810 static const struct read_write_emulator_ops write_emultor = { 4811 .read_write_emulate = write_emulate, 4812 .read_write_mmio = write_mmio, 4813 .read_write_exit_mmio = write_exit_mmio, 4814 .write = true, 4815 }; 4816 4817 static int emulator_read_write_onepage(unsigned long addr, void *val, 4818 unsigned int bytes, 4819 struct x86_exception *exception, 4820 struct kvm_vcpu *vcpu, 4821 const struct read_write_emulator_ops *ops) 4822 { 4823 gpa_t gpa; 4824 int handled, ret; 4825 bool write = ops->write; 4826 struct kvm_mmio_fragment *frag; 4827 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 4828 4829 /* 4830 * If the exit was due to a NPF we may already have a GPA. 4831 * If the GPA is present, use it to avoid the GVA to GPA table walk. 4832 * Note, this cannot be used on string operations since string 4833 * operation using rep will only have the initial GPA from the NPF 4834 * occurred. 4835 */ 4836 if (vcpu->arch.gpa_available && 4837 emulator_can_use_gpa(ctxt) && 4838 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) { 4839 gpa = vcpu->arch.gpa_val; 4840 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 4841 } else { 4842 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 4843 if (ret < 0) 4844 return X86EMUL_PROPAGATE_FAULT; 4845 } 4846 4847 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 4848 return X86EMUL_CONTINUE; 4849 4850 /* 4851 * Is this MMIO handled locally? 4852 */ 4853 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 4854 if (handled == bytes) 4855 return X86EMUL_CONTINUE; 4856 4857 gpa += handled; 4858 bytes -= handled; 4859 val += handled; 4860 4861 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 4862 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 4863 frag->gpa = gpa; 4864 frag->data = val; 4865 frag->len = bytes; 4866 return X86EMUL_CONTINUE; 4867 } 4868 4869 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 4870 unsigned long addr, 4871 void *val, unsigned int bytes, 4872 struct x86_exception *exception, 4873 const struct read_write_emulator_ops *ops) 4874 { 4875 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4876 gpa_t gpa; 4877 int rc; 4878 4879 if (ops->read_write_prepare && 4880 ops->read_write_prepare(vcpu, val, bytes)) 4881 return X86EMUL_CONTINUE; 4882 4883 vcpu->mmio_nr_fragments = 0; 4884 4885 /* Crossing a page boundary? */ 4886 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 4887 int now; 4888 4889 now = -addr & ~PAGE_MASK; 4890 rc = emulator_read_write_onepage(addr, val, now, exception, 4891 vcpu, ops); 4892 4893 if (rc != X86EMUL_CONTINUE) 4894 return rc; 4895 addr += now; 4896 if (ctxt->mode != X86EMUL_MODE_PROT64) 4897 addr = (u32)addr; 4898 val += now; 4899 bytes -= now; 4900 } 4901 4902 rc = emulator_read_write_onepage(addr, val, bytes, exception, 4903 vcpu, ops); 4904 if (rc != X86EMUL_CONTINUE) 4905 return rc; 4906 4907 if (!vcpu->mmio_nr_fragments) 4908 return rc; 4909 4910 gpa = vcpu->mmio_fragments[0].gpa; 4911 4912 vcpu->mmio_needed = 1; 4913 vcpu->mmio_cur_fragment = 0; 4914 4915 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 4916 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 4917 vcpu->run->exit_reason = KVM_EXIT_MMIO; 4918 vcpu->run->mmio.phys_addr = gpa; 4919 4920 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 4921 } 4922 4923 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 4924 unsigned long addr, 4925 void *val, 4926 unsigned int bytes, 4927 struct x86_exception *exception) 4928 { 4929 return emulator_read_write(ctxt, addr, val, bytes, 4930 exception, &read_emultor); 4931 } 4932 4933 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 4934 unsigned long addr, 4935 const void *val, 4936 unsigned int bytes, 4937 struct x86_exception *exception) 4938 { 4939 return emulator_read_write(ctxt, addr, (void *)val, bytes, 4940 exception, &write_emultor); 4941 } 4942 4943 #define CMPXCHG_TYPE(t, ptr, old, new) \ 4944 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 4945 4946 #ifdef CONFIG_X86_64 4947 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 4948 #else 4949 # define CMPXCHG64(ptr, old, new) \ 4950 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 4951 #endif 4952 4953 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 4954 unsigned long addr, 4955 const void *old, 4956 const void *new, 4957 unsigned int bytes, 4958 struct x86_exception *exception) 4959 { 4960 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4961 gpa_t gpa; 4962 struct page *page; 4963 char *kaddr; 4964 bool exchanged; 4965 4966 /* guests cmpxchg8b have to be emulated atomically */ 4967 if (bytes > 8 || (bytes & (bytes - 1))) 4968 goto emul_write; 4969 4970 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 4971 4972 if (gpa == UNMAPPED_GVA || 4973 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4974 goto emul_write; 4975 4976 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 4977 goto emul_write; 4978 4979 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); 4980 if (is_error_page(page)) 4981 goto emul_write; 4982 4983 kaddr = kmap_atomic(page); 4984 kaddr += offset_in_page(gpa); 4985 switch (bytes) { 4986 case 1: 4987 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 4988 break; 4989 case 2: 4990 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 4991 break; 4992 case 4: 4993 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 4994 break; 4995 case 8: 4996 exchanged = CMPXCHG64(kaddr, old, new); 4997 break; 4998 default: 4999 BUG(); 5000 } 5001 kunmap_atomic(kaddr); 5002 kvm_release_page_dirty(page); 5003 5004 if (!exchanged) 5005 return X86EMUL_CMPXCHG_FAILED; 5006 5007 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5008 kvm_page_track_write(vcpu, gpa, new, bytes); 5009 5010 return X86EMUL_CONTINUE; 5011 5012 emul_write: 5013 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 5014 5015 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 5016 } 5017 5018 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 5019 { 5020 int r = 0, i; 5021 5022 for (i = 0; i < vcpu->arch.pio.count; i++) { 5023 if (vcpu->arch.pio.in) 5024 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 5025 vcpu->arch.pio.size, pd); 5026 else 5027 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 5028 vcpu->arch.pio.port, vcpu->arch.pio.size, 5029 pd); 5030 if (r) 5031 break; 5032 pd += vcpu->arch.pio.size; 5033 } 5034 return r; 5035 } 5036 5037 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 5038 unsigned short port, void *val, 5039 unsigned int count, bool in) 5040 { 5041 vcpu->arch.pio.port = port; 5042 vcpu->arch.pio.in = in; 5043 vcpu->arch.pio.count = count; 5044 vcpu->arch.pio.size = size; 5045 5046 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 5047 vcpu->arch.pio.count = 0; 5048 return 1; 5049 } 5050 5051 vcpu->run->exit_reason = KVM_EXIT_IO; 5052 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 5053 vcpu->run->io.size = size; 5054 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 5055 vcpu->run->io.count = count; 5056 vcpu->run->io.port = port; 5057 5058 return 0; 5059 } 5060 5061 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 5062 int size, unsigned short port, void *val, 5063 unsigned int count) 5064 { 5065 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5066 int ret; 5067 5068 if (vcpu->arch.pio.count) 5069 goto data_avail; 5070 5071 memset(vcpu->arch.pio_data, 0, size * count); 5072 5073 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 5074 if (ret) { 5075 data_avail: 5076 memcpy(val, vcpu->arch.pio_data, size * count); 5077 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 5078 vcpu->arch.pio.count = 0; 5079 return 1; 5080 } 5081 5082 return 0; 5083 } 5084 5085 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 5086 int size, unsigned short port, 5087 const void *val, unsigned int count) 5088 { 5089 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5090 5091 memcpy(vcpu->arch.pio_data, val, size * count); 5092 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 5093 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 5094 } 5095 5096 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 5097 { 5098 return kvm_x86_ops->get_segment_base(vcpu, seg); 5099 } 5100 5101 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 5102 { 5103 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 5104 } 5105 5106 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 5107 { 5108 if (!need_emulate_wbinvd(vcpu)) 5109 return X86EMUL_CONTINUE; 5110 5111 if (kvm_x86_ops->has_wbinvd_exit()) { 5112 int cpu = get_cpu(); 5113 5114 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 5115 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 5116 wbinvd_ipi, NULL, 1); 5117 put_cpu(); 5118 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 5119 } else 5120 wbinvd(); 5121 return X86EMUL_CONTINUE; 5122 } 5123 5124 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 5125 { 5126 kvm_emulate_wbinvd_noskip(vcpu); 5127 return kvm_skip_emulated_instruction(vcpu); 5128 } 5129 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 5130 5131 5132 5133 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 5134 { 5135 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 5136 } 5137 5138 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 5139 unsigned long *dest) 5140 { 5141 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 5142 } 5143 5144 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 5145 unsigned long value) 5146 { 5147 5148 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 5149 } 5150 5151 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 5152 { 5153 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 5154 } 5155 5156 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 5157 { 5158 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5159 unsigned long value; 5160 5161 switch (cr) { 5162 case 0: 5163 value = kvm_read_cr0(vcpu); 5164 break; 5165 case 2: 5166 value = vcpu->arch.cr2; 5167 break; 5168 case 3: 5169 value = kvm_read_cr3(vcpu); 5170 break; 5171 case 4: 5172 value = kvm_read_cr4(vcpu); 5173 break; 5174 case 8: 5175 value = kvm_get_cr8(vcpu); 5176 break; 5177 default: 5178 kvm_err("%s: unexpected cr %u\n", __func__, cr); 5179 return 0; 5180 } 5181 5182 return value; 5183 } 5184 5185 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 5186 { 5187 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5188 int res = 0; 5189 5190 switch (cr) { 5191 case 0: 5192 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 5193 break; 5194 case 2: 5195 vcpu->arch.cr2 = val; 5196 break; 5197 case 3: 5198 res = kvm_set_cr3(vcpu, val); 5199 break; 5200 case 4: 5201 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 5202 break; 5203 case 8: 5204 res = kvm_set_cr8(vcpu, val); 5205 break; 5206 default: 5207 kvm_err("%s: unexpected cr %u\n", __func__, cr); 5208 res = -1; 5209 } 5210 5211 return res; 5212 } 5213 5214 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 5215 { 5216 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 5217 } 5218 5219 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5220 { 5221 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 5222 } 5223 5224 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5225 { 5226 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 5227 } 5228 5229 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5230 { 5231 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 5232 } 5233 5234 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5235 { 5236 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 5237 } 5238 5239 static unsigned long emulator_get_cached_segment_base( 5240 struct x86_emulate_ctxt *ctxt, int seg) 5241 { 5242 return get_segment_base(emul_to_vcpu(ctxt), seg); 5243 } 5244 5245 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 5246 struct desc_struct *desc, u32 *base3, 5247 int seg) 5248 { 5249 struct kvm_segment var; 5250 5251 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 5252 *selector = var.selector; 5253 5254 if (var.unusable) { 5255 memset(desc, 0, sizeof(*desc)); 5256 if (base3) 5257 *base3 = 0; 5258 return false; 5259 } 5260 5261 if (var.g) 5262 var.limit >>= 12; 5263 set_desc_limit(desc, var.limit); 5264 set_desc_base(desc, (unsigned long)var.base); 5265 #ifdef CONFIG_X86_64 5266 if (base3) 5267 *base3 = var.base >> 32; 5268 #endif 5269 desc->type = var.type; 5270 desc->s = var.s; 5271 desc->dpl = var.dpl; 5272 desc->p = var.present; 5273 desc->avl = var.avl; 5274 desc->l = var.l; 5275 desc->d = var.db; 5276 desc->g = var.g; 5277 5278 return true; 5279 } 5280 5281 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 5282 struct desc_struct *desc, u32 base3, 5283 int seg) 5284 { 5285 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5286 struct kvm_segment var; 5287 5288 var.selector = selector; 5289 var.base = get_desc_base(desc); 5290 #ifdef CONFIG_X86_64 5291 var.base |= ((u64)base3) << 32; 5292 #endif 5293 var.limit = get_desc_limit(desc); 5294 if (desc->g) 5295 var.limit = (var.limit << 12) | 0xfff; 5296 var.type = desc->type; 5297 var.dpl = desc->dpl; 5298 var.db = desc->d; 5299 var.s = desc->s; 5300 var.l = desc->l; 5301 var.g = desc->g; 5302 var.avl = desc->avl; 5303 var.present = desc->p; 5304 var.unusable = !var.present; 5305 var.padding = 0; 5306 5307 kvm_set_segment(vcpu, &var, seg); 5308 return; 5309 } 5310 5311 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 5312 u32 msr_index, u64 *pdata) 5313 { 5314 struct msr_data msr; 5315 int r; 5316 5317 msr.index = msr_index; 5318 msr.host_initiated = false; 5319 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); 5320 if (r) 5321 return r; 5322 5323 *pdata = msr.data; 5324 return 0; 5325 } 5326 5327 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 5328 u32 msr_index, u64 data) 5329 { 5330 struct msr_data msr; 5331 5332 msr.data = data; 5333 msr.index = msr_index; 5334 msr.host_initiated = false; 5335 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 5336 } 5337 5338 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 5339 { 5340 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5341 5342 return vcpu->arch.smbase; 5343 } 5344 5345 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 5346 { 5347 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5348 5349 vcpu->arch.smbase = smbase; 5350 } 5351 5352 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 5353 u32 pmc) 5354 { 5355 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); 5356 } 5357 5358 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 5359 u32 pmc, u64 *pdata) 5360 { 5361 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 5362 } 5363 5364 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 5365 { 5366 emul_to_vcpu(ctxt)->arch.halt_request = 1; 5367 } 5368 5369 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 5370 struct x86_instruction_info *info, 5371 enum x86_intercept_stage stage) 5372 { 5373 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 5374 } 5375 5376 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 5377 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit) 5378 { 5379 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit); 5380 } 5381 5382 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 5383 { 5384 return kvm_register_read(emul_to_vcpu(ctxt), reg); 5385 } 5386 5387 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 5388 { 5389 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 5390 } 5391 5392 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 5393 { 5394 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 5395 } 5396 5397 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 5398 { 5399 return emul_to_vcpu(ctxt)->arch.hflags; 5400 } 5401 5402 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) 5403 { 5404 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags); 5405 } 5406 5407 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase) 5408 { 5409 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase); 5410 } 5411 5412 static const struct x86_emulate_ops emulate_ops = { 5413 .read_gpr = emulator_read_gpr, 5414 .write_gpr = emulator_write_gpr, 5415 .read_std = kvm_read_guest_virt_system, 5416 .write_std = kvm_write_guest_virt_system, 5417 .read_phys = kvm_read_guest_phys_system, 5418 .fetch = kvm_fetch_guest_virt, 5419 .read_emulated = emulator_read_emulated, 5420 .write_emulated = emulator_write_emulated, 5421 .cmpxchg_emulated = emulator_cmpxchg_emulated, 5422 .invlpg = emulator_invlpg, 5423 .pio_in_emulated = emulator_pio_in_emulated, 5424 .pio_out_emulated = emulator_pio_out_emulated, 5425 .get_segment = emulator_get_segment, 5426 .set_segment = emulator_set_segment, 5427 .get_cached_segment_base = emulator_get_cached_segment_base, 5428 .get_gdt = emulator_get_gdt, 5429 .get_idt = emulator_get_idt, 5430 .set_gdt = emulator_set_gdt, 5431 .set_idt = emulator_set_idt, 5432 .get_cr = emulator_get_cr, 5433 .set_cr = emulator_set_cr, 5434 .cpl = emulator_get_cpl, 5435 .get_dr = emulator_get_dr, 5436 .set_dr = emulator_set_dr, 5437 .get_smbase = emulator_get_smbase, 5438 .set_smbase = emulator_set_smbase, 5439 .set_msr = emulator_set_msr, 5440 .get_msr = emulator_get_msr, 5441 .check_pmc = emulator_check_pmc, 5442 .read_pmc = emulator_read_pmc, 5443 .halt = emulator_halt, 5444 .wbinvd = emulator_wbinvd, 5445 .fix_hypercall = emulator_fix_hypercall, 5446 .intercept = emulator_intercept, 5447 .get_cpuid = emulator_get_cpuid, 5448 .set_nmi_mask = emulator_set_nmi_mask, 5449 .get_hflags = emulator_get_hflags, 5450 .set_hflags = emulator_set_hflags, 5451 .pre_leave_smm = emulator_pre_leave_smm, 5452 }; 5453 5454 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 5455 { 5456 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 5457 /* 5458 * an sti; sti; sequence only disable interrupts for the first 5459 * instruction. So, if the last instruction, be it emulated or 5460 * not, left the system with the INT_STI flag enabled, it 5461 * means that the last instruction is an sti. We should not 5462 * leave the flag on in this case. The same goes for mov ss 5463 */ 5464 if (int_shadow & mask) 5465 mask = 0; 5466 if (unlikely(int_shadow || mask)) { 5467 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 5468 if (!mask) 5469 kvm_make_request(KVM_REQ_EVENT, vcpu); 5470 } 5471 } 5472 5473 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 5474 { 5475 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5476 if (ctxt->exception.vector == PF_VECTOR) 5477 return kvm_propagate_fault(vcpu, &ctxt->exception); 5478 5479 if (ctxt->exception.error_code_valid) 5480 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 5481 ctxt->exception.error_code); 5482 else 5483 kvm_queue_exception(vcpu, ctxt->exception.vector); 5484 return false; 5485 } 5486 5487 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 5488 { 5489 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5490 int cs_db, cs_l; 5491 5492 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 5493 5494 ctxt->eflags = kvm_get_rflags(vcpu); 5495 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 5496 5497 ctxt->eip = kvm_rip_read(vcpu); 5498 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 5499 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 5500 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 5501 cs_db ? X86EMUL_MODE_PROT32 : 5502 X86EMUL_MODE_PROT16; 5503 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 5504 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 5505 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 5506 5507 init_decode_cache(ctxt); 5508 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5509 } 5510 5511 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 5512 { 5513 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5514 int ret; 5515 5516 init_emulate_ctxt(vcpu); 5517 5518 ctxt->op_bytes = 2; 5519 ctxt->ad_bytes = 2; 5520 ctxt->_eip = ctxt->eip + inc_eip; 5521 ret = emulate_int_real(ctxt, irq); 5522 5523 if (ret != X86EMUL_CONTINUE) 5524 return EMULATE_FAIL; 5525 5526 ctxt->eip = ctxt->_eip; 5527 kvm_rip_write(vcpu, ctxt->eip); 5528 kvm_set_rflags(vcpu, ctxt->eflags); 5529 5530 if (irq == NMI_VECTOR) 5531 vcpu->arch.nmi_pending = 0; 5532 else 5533 vcpu->arch.interrupt.pending = false; 5534 5535 return EMULATE_DONE; 5536 } 5537 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 5538 5539 static int handle_emulation_failure(struct kvm_vcpu *vcpu) 5540 { 5541 int r = EMULATE_DONE; 5542 5543 ++vcpu->stat.insn_emulation_fail; 5544 trace_kvm_emulate_insn_failed(vcpu); 5545 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 5546 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5547 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 5548 vcpu->run->internal.ndata = 0; 5549 r = EMULATE_USER_EXIT; 5550 } 5551 kvm_queue_exception(vcpu, UD_VECTOR); 5552 5553 return r; 5554 } 5555 5556 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 5557 bool write_fault_to_shadow_pgtable, 5558 int emulation_type) 5559 { 5560 gpa_t gpa = cr2; 5561 kvm_pfn_t pfn; 5562 5563 if (emulation_type & EMULTYPE_NO_REEXECUTE) 5564 return false; 5565 5566 if (!vcpu->arch.mmu.direct_map) { 5567 /* 5568 * Write permission should be allowed since only 5569 * write access need to be emulated. 5570 */ 5571 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5572 5573 /* 5574 * If the mapping is invalid in guest, let cpu retry 5575 * it to generate fault. 5576 */ 5577 if (gpa == UNMAPPED_GVA) 5578 return true; 5579 } 5580 5581 /* 5582 * Do not retry the unhandleable instruction if it faults on the 5583 * readonly host memory, otherwise it will goto a infinite loop: 5584 * retry instruction -> write #PF -> emulation fail -> retry 5585 * instruction -> ... 5586 */ 5587 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 5588 5589 /* 5590 * If the instruction failed on the error pfn, it can not be fixed, 5591 * report the error to userspace. 5592 */ 5593 if (is_error_noslot_pfn(pfn)) 5594 return false; 5595 5596 kvm_release_pfn_clean(pfn); 5597 5598 /* The instructions are well-emulated on direct mmu. */ 5599 if (vcpu->arch.mmu.direct_map) { 5600 unsigned int indirect_shadow_pages; 5601 5602 spin_lock(&vcpu->kvm->mmu_lock); 5603 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 5604 spin_unlock(&vcpu->kvm->mmu_lock); 5605 5606 if (indirect_shadow_pages) 5607 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5608 5609 return true; 5610 } 5611 5612 /* 5613 * if emulation was due to access to shadowed page table 5614 * and it failed try to unshadow page and re-enter the 5615 * guest to let CPU execute the instruction. 5616 */ 5617 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5618 5619 /* 5620 * If the access faults on its page table, it can not 5621 * be fixed by unprotecting shadow page and it should 5622 * be reported to userspace. 5623 */ 5624 return !write_fault_to_shadow_pgtable; 5625 } 5626 5627 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5628 unsigned long cr2, int emulation_type) 5629 { 5630 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5631 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5632 5633 last_retry_eip = vcpu->arch.last_retry_eip; 5634 last_retry_addr = vcpu->arch.last_retry_addr; 5635 5636 /* 5637 * If the emulation is caused by #PF and it is non-page_table 5638 * writing instruction, it means the VM-EXIT is caused by shadow 5639 * page protected, we can zap the shadow page and retry this 5640 * instruction directly. 5641 * 5642 * Note: if the guest uses a non-page-table modifying instruction 5643 * on the PDE that points to the instruction, then we will unmap 5644 * the instruction and go to an infinite loop. So, we cache the 5645 * last retried eip and the last fault address, if we meet the eip 5646 * and the address again, we can break out of the potential infinite 5647 * loop. 5648 */ 5649 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5650 5651 if (!(emulation_type & EMULTYPE_RETRY)) 5652 return false; 5653 5654 if (x86_page_table_writing_insn(ctxt)) 5655 return false; 5656 5657 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5658 return false; 5659 5660 vcpu->arch.last_retry_eip = ctxt->eip; 5661 vcpu->arch.last_retry_addr = cr2; 5662 5663 if (!vcpu->arch.mmu.direct_map) 5664 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5665 5666 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5667 5668 return true; 5669 } 5670 5671 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5672 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5673 5674 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 5675 { 5676 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 5677 /* This is a good place to trace that we are exiting SMM. */ 5678 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 5679 5680 /* Process a latched INIT or SMI, if any. */ 5681 kvm_make_request(KVM_REQ_EVENT, vcpu); 5682 } 5683 5684 kvm_mmu_reset_context(vcpu); 5685 } 5686 5687 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) 5688 { 5689 unsigned changed = vcpu->arch.hflags ^ emul_flags; 5690 5691 vcpu->arch.hflags = emul_flags; 5692 5693 if (changed & HF_SMM_MASK) 5694 kvm_smm_changed(vcpu); 5695 } 5696 5697 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5698 unsigned long *db) 5699 { 5700 u32 dr6 = 0; 5701 int i; 5702 u32 enable, rwlen; 5703 5704 enable = dr7; 5705 rwlen = dr7 >> 16; 5706 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5707 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5708 dr6 |= (1 << i); 5709 return dr6; 5710 } 5711 5712 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r) 5713 { 5714 struct kvm_run *kvm_run = vcpu->run; 5715 5716 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5717 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; 5718 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5719 kvm_run->debug.arch.exception = DB_VECTOR; 5720 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5721 *r = EMULATE_USER_EXIT; 5722 } else { 5723 /* 5724 * "Certain debug exceptions may clear bit 0-3. The 5725 * remaining contents of the DR6 register are never 5726 * cleared by the processor". 5727 */ 5728 vcpu->arch.dr6 &= ~15; 5729 vcpu->arch.dr6 |= DR6_BS | DR6_RTM; 5730 kvm_queue_exception(vcpu, DB_VECTOR); 5731 } 5732 } 5733 5734 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 5735 { 5736 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5737 int r = EMULATE_DONE; 5738 5739 kvm_x86_ops->skip_emulated_instruction(vcpu); 5740 5741 /* 5742 * rflags is the old, "raw" value of the flags. The new value has 5743 * not been saved yet. 5744 * 5745 * This is correct even for TF set by the guest, because "the 5746 * processor will not generate this exception after the instruction 5747 * that sets the TF flag". 5748 */ 5749 if (unlikely(rflags & X86_EFLAGS_TF)) 5750 kvm_vcpu_do_singlestep(vcpu, &r); 5751 return r == EMULATE_DONE; 5752 } 5753 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 5754 5755 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5756 { 5757 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5758 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5759 struct kvm_run *kvm_run = vcpu->run; 5760 unsigned long eip = kvm_get_linear_rip(vcpu); 5761 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5762 vcpu->arch.guest_debug_dr7, 5763 vcpu->arch.eff_db); 5764 5765 if (dr6 != 0) { 5766 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 5767 kvm_run->debug.arch.pc = eip; 5768 kvm_run->debug.arch.exception = DB_VECTOR; 5769 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5770 *r = EMULATE_USER_EXIT; 5771 return true; 5772 } 5773 } 5774 5775 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 5776 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 5777 unsigned long eip = kvm_get_linear_rip(vcpu); 5778 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5779 vcpu->arch.dr7, 5780 vcpu->arch.db); 5781 5782 if (dr6 != 0) { 5783 vcpu->arch.dr6 &= ~15; 5784 vcpu->arch.dr6 |= dr6 | DR6_RTM; 5785 kvm_queue_exception(vcpu, DB_VECTOR); 5786 *r = EMULATE_DONE; 5787 return true; 5788 } 5789 } 5790 5791 return false; 5792 } 5793 5794 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 5795 unsigned long cr2, 5796 int emulation_type, 5797 void *insn, 5798 int insn_len) 5799 { 5800 int r; 5801 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5802 bool writeback = true; 5803 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 5804 5805 /* 5806 * Clear write_fault_to_shadow_pgtable here to ensure it is 5807 * never reused. 5808 */ 5809 vcpu->arch.write_fault_to_shadow_pgtable = false; 5810 kvm_clear_exception_queue(vcpu); 5811 5812 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 5813 init_emulate_ctxt(vcpu); 5814 5815 /* 5816 * We will reenter on the same instruction since 5817 * we do not set complete_userspace_io. This does not 5818 * handle watchpoints yet, those would be handled in 5819 * the emulate_ops. 5820 */ 5821 if (!(emulation_type & EMULTYPE_SKIP) && 5822 kvm_vcpu_check_breakpoint(vcpu, &r)) 5823 return r; 5824 5825 ctxt->interruptibility = 0; 5826 ctxt->have_exception = false; 5827 ctxt->exception.vector = -1; 5828 ctxt->perm_ok = false; 5829 5830 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 5831 5832 r = x86_decode_insn(ctxt, insn, insn_len); 5833 5834 trace_kvm_emulate_insn_start(vcpu); 5835 ++vcpu->stat.insn_emulation; 5836 if (r != EMULATION_OK) { 5837 if (emulation_type & EMULTYPE_TRAP_UD) 5838 return EMULATE_FAIL; 5839 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5840 emulation_type)) 5841 return EMULATE_DONE; 5842 if (ctxt->have_exception && inject_emulated_exception(vcpu)) 5843 return EMULATE_DONE; 5844 if (emulation_type & EMULTYPE_SKIP) 5845 return EMULATE_FAIL; 5846 return handle_emulation_failure(vcpu); 5847 } 5848 } 5849 5850 if (emulation_type & EMULTYPE_SKIP) { 5851 kvm_rip_write(vcpu, ctxt->_eip); 5852 if (ctxt->eflags & X86_EFLAGS_RF) 5853 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 5854 return EMULATE_DONE; 5855 } 5856 5857 if (retry_instruction(ctxt, cr2, emulation_type)) 5858 return EMULATE_DONE; 5859 5860 /* this is needed for vmware backdoor interface to work since it 5861 changes registers values during IO operation */ 5862 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 5863 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5864 emulator_invalidate_register_cache(ctxt); 5865 } 5866 5867 restart: 5868 /* Save the faulting GPA (cr2) in the address field */ 5869 ctxt->exception.address = cr2; 5870 5871 r = x86_emulate_insn(ctxt); 5872 5873 if (r == EMULATION_INTERCEPTED) 5874 return EMULATE_DONE; 5875 5876 if (r == EMULATION_FAILED) { 5877 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5878 emulation_type)) 5879 return EMULATE_DONE; 5880 5881 return handle_emulation_failure(vcpu); 5882 } 5883 5884 if (ctxt->have_exception) { 5885 r = EMULATE_DONE; 5886 if (inject_emulated_exception(vcpu)) 5887 return r; 5888 } else if (vcpu->arch.pio.count) { 5889 if (!vcpu->arch.pio.in) { 5890 /* FIXME: return into emulator if single-stepping. */ 5891 vcpu->arch.pio.count = 0; 5892 } else { 5893 writeback = false; 5894 vcpu->arch.complete_userspace_io = complete_emulated_pio; 5895 } 5896 r = EMULATE_USER_EXIT; 5897 } else if (vcpu->mmio_needed) { 5898 if (!vcpu->mmio_is_write) 5899 writeback = false; 5900 r = EMULATE_USER_EXIT; 5901 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 5902 } else if (r == EMULATION_RESTART) 5903 goto restart; 5904 else 5905 r = EMULATE_DONE; 5906 5907 if (writeback) { 5908 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5909 toggle_interruptibility(vcpu, ctxt->interruptibility); 5910 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 5911 kvm_rip_write(vcpu, ctxt->eip); 5912 if (r == EMULATE_DONE && 5913 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 5914 kvm_vcpu_do_singlestep(vcpu, &r); 5915 if (!ctxt->have_exception || 5916 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 5917 __kvm_set_rflags(vcpu, ctxt->eflags); 5918 5919 /* 5920 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 5921 * do nothing, and it will be requested again as soon as 5922 * the shadow expires. But we still need to check here, 5923 * because POPF has no interrupt shadow. 5924 */ 5925 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 5926 kvm_make_request(KVM_REQ_EVENT, vcpu); 5927 } else 5928 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 5929 5930 return r; 5931 } 5932 EXPORT_SYMBOL_GPL(x86_emulate_instruction); 5933 5934 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) 5935 { 5936 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 5937 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 5938 size, port, &val, 1); 5939 /* do not return to emulator after return from userspace */ 5940 vcpu->arch.pio.count = 0; 5941 return ret; 5942 } 5943 EXPORT_SYMBOL_GPL(kvm_fast_pio_out); 5944 5945 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 5946 { 5947 unsigned long val; 5948 5949 /* We should only ever be called with arch.pio.count equal to 1 */ 5950 BUG_ON(vcpu->arch.pio.count != 1); 5951 5952 /* For size less than 4 we merge, else we zero extend */ 5953 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) 5954 : 0; 5955 5956 /* 5957 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform 5958 * the copy and tracing 5959 */ 5960 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size, 5961 vcpu->arch.pio.port, &val, 1); 5962 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 5963 5964 return 1; 5965 } 5966 5967 int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port) 5968 { 5969 unsigned long val; 5970 int ret; 5971 5972 /* For size less than 4 we merge, else we zero extend */ 5973 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0; 5974 5975 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port, 5976 &val, 1); 5977 if (ret) { 5978 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 5979 return ret; 5980 } 5981 5982 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 5983 5984 return 0; 5985 } 5986 EXPORT_SYMBOL_GPL(kvm_fast_pio_in); 5987 5988 static int kvmclock_cpu_down_prep(unsigned int cpu) 5989 { 5990 __this_cpu_write(cpu_tsc_khz, 0); 5991 return 0; 5992 } 5993 5994 static void tsc_khz_changed(void *data) 5995 { 5996 struct cpufreq_freqs *freq = data; 5997 unsigned long khz = 0; 5998 5999 if (data) 6000 khz = freq->new; 6001 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 6002 khz = cpufreq_quick_get(raw_smp_processor_id()); 6003 if (!khz) 6004 khz = tsc_khz; 6005 __this_cpu_write(cpu_tsc_khz, khz); 6006 } 6007 6008 #ifdef CONFIG_X86_64 6009 static void kvm_hyperv_tsc_notifier(void) 6010 { 6011 struct kvm *kvm; 6012 struct kvm_vcpu *vcpu; 6013 int cpu; 6014 6015 spin_lock(&kvm_lock); 6016 list_for_each_entry(kvm, &vm_list, vm_list) 6017 kvm_make_mclock_inprogress_request(kvm); 6018 6019 hyperv_stop_tsc_emulation(); 6020 6021 /* TSC frequency always matches when on Hyper-V */ 6022 for_each_present_cpu(cpu) 6023 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 6024 kvm_max_guest_tsc_khz = tsc_khz; 6025 6026 list_for_each_entry(kvm, &vm_list, vm_list) { 6027 struct kvm_arch *ka = &kvm->arch; 6028 6029 spin_lock(&ka->pvclock_gtod_sync_lock); 6030 6031 pvclock_update_vm_gtod_copy(kvm); 6032 6033 kvm_for_each_vcpu(cpu, vcpu, kvm) 6034 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6035 6036 kvm_for_each_vcpu(cpu, vcpu, kvm) 6037 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 6038 6039 spin_unlock(&ka->pvclock_gtod_sync_lock); 6040 } 6041 spin_unlock(&kvm_lock); 6042 } 6043 #endif 6044 6045 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 6046 void *data) 6047 { 6048 struct cpufreq_freqs *freq = data; 6049 struct kvm *kvm; 6050 struct kvm_vcpu *vcpu; 6051 int i, send_ipi = 0; 6052 6053 /* 6054 * We allow guests to temporarily run on slowing clocks, 6055 * provided we notify them after, or to run on accelerating 6056 * clocks, provided we notify them before. Thus time never 6057 * goes backwards. 6058 * 6059 * However, we have a problem. We can't atomically update 6060 * the frequency of a given CPU from this function; it is 6061 * merely a notifier, which can be called from any CPU. 6062 * Changing the TSC frequency at arbitrary points in time 6063 * requires a recomputation of local variables related to 6064 * the TSC for each VCPU. We must flag these local variables 6065 * to be updated and be sure the update takes place with the 6066 * new frequency before any guests proceed. 6067 * 6068 * Unfortunately, the combination of hotplug CPU and frequency 6069 * change creates an intractable locking scenario; the order 6070 * of when these callouts happen is undefined with respect to 6071 * CPU hotplug, and they can race with each other. As such, 6072 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 6073 * undefined; you can actually have a CPU frequency change take 6074 * place in between the computation of X and the setting of the 6075 * variable. To protect against this problem, all updates of 6076 * the per_cpu tsc_khz variable are done in an interrupt 6077 * protected IPI, and all callers wishing to update the value 6078 * must wait for a synchronous IPI to complete (which is trivial 6079 * if the caller is on the CPU already). This establishes the 6080 * necessary total order on variable updates. 6081 * 6082 * Note that because a guest time update may take place 6083 * anytime after the setting of the VCPU's request bit, the 6084 * correct TSC value must be set before the request. However, 6085 * to ensure the update actually makes it to any guest which 6086 * starts running in hardware virtualization between the set 6087 * and the acquisition of the spinlock, we must also ping the 6088 * CPU after setting the request bit. 6089 * 6090 */ 6091 6092 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 6093 return 0; 6094 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 6095 return 0; 6096 6097 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 6098 6099 spin_lock(&kvm_lock); 6100 list_for_each_entry(kvm, &vm_list, vm_list) { 6101 kvm_for_each_vcpu(i, vcpu, kvm) { 6102 if (vcpu->cpu != freq->cpu) 6103 continue; 6104 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6105 if (vcpu->cpu != smp_processor_id()) 6106 send_ipi = 1; 6107 } 6108 } 6109 spin_unlock(&kvm_lock); 6110 6111 if (freq->old < freq->new && send_ipi) { 6112 /* 6113 * We upscale the frequency. Must make the guest 6114 * doesn't see old kvmclock values while running with 6115 * the new frequency, otherwise we risk the guest sees 6116 * time go backwards. 6117 * 6118 * In case we update the frequency for another cpu 6119 * (which might be in guest context) send an interrupt 6120 * to kick the cpu out of guest context. Next time 6121 * guest context is entered kvmclock will be updated, 6122 * so the guest will not see stale values. 6123 */ 6124 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 6125 } 6126 return 0; 6127 } 6128 6129 static struct notifier_block kvmclock_cpufreq_notifier_block = { 6130 .notifier_call = kvmclock_cpufreq_notifier 6131 }; 6132 6133 static int kvmclock_cpu_online(unsigned int cpu) 6134 { 6135 tsc_khz_changed(NULL); 6136 return 0; 6137 } 6138 6139 static void kvm_timer_init(void) 6140 { 6141 max_tsc_khz = tsc_khz; 6142 6143 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 6144 #ifdef CONFIG_CPU_FREQ 6145 struct cpufreq_policy policy; 6146 int cpu; 6147 6148 memset(&policy, 0, sizeof(policy)); 6149 cpu = get_cpu(); 6150 cpufreq_get_policy(&policy, cpu); 6151 if (policy.cpuinfo.max_freq) 6152 max_tsc_khz = policy.cpuinfo.max_freq; 6153 put_cpu(); 6154 #endif 6155 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 6156 CPUFREQ_TRANSITION_NOTIFIER); 6157 } 6158 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 6159 6160 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 6161 kvmclock_cpu_online, kvmclock_cpu_down_prep); 6162 } 6163 6164 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 6165 6166 int kvm_is_in_guest(void) 6167 { 6168 return __this_cpu_read(current_vcpu) != NULL; 6169 } 6170 6171 static int kvm_is_user_mode(void) 6172 { 6173 int user_mode = 3; 6174 6175 if (__this_cpu_read(current_vcpu)) 6176 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 6177 6178 return user_mode != 0; 6179 } 6180 6181 static unsigned long kvm_get_guest_ip(void) 6182 { 6183 unsigned long ip = 0; 6184 6185 if (__this_cpu_read(current_vcpu)) 6186 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 6187 6188 return ip; 6189 } 6190 6191 static struct perf_guest_info_callbacks kvm_guest_cbs = { 6192 .is_in_guest = kvm_is_in_guest, 6193 .is_user_mode = kvm_is_user_mode, 6194 .get_guest_ip = kvm_get_guest_ip, 6195 }; 6196 6197 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) 6198 { 6199 __this_cpu_write(current_vcpu, vcpu); 6200 } 6201 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); 6202 6203 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) 6204 { 6205 __this_cpu_write(current_vcpu, NULL); 6206 } 6207 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); 6208 6209 static void kvm_set_mmio_spte_mask(void) 6210 { 6211 u64 mask; 6212 int maxphyaddr = boot_cpu_data.x86_phys_bits; 6213 6214 /* 6215 * Set the reserved bits and the present bit of an paging-structure 6216 * entry to generate page fault with PFER.RSV = 1. 6217 */ 6218 /* Mask the reserved physical address bits. */ 6219 mask = rsvd_bits(maxphyaddr, 51); 6220 6221 /* Set the present bit. */ 6222 mask |= 1ull; 6223 6224 #ifdef CONFIG_X86_64 6225 /* 6226 * If reserved bit is not supported, clear the present bit to disable 6227 * mmio page fault. 6228 */ 6229 if (maxphyaddr == 52) 6230 mask &= ~1ull; 6231 #endif 6232 6233 kvm_mmu_set_mmio_spte_mask(mask, mask); 6234 } 6235 6236 #ifdef CONFIG_X86_64 6237 static void pvclock_gtod_update_fn(struct work_struct *work) 6238 { 6239 struct kvm *kvm; 6240 6241 struct kvm_vcpu *vcpu; 6242 int i; 6243 6244 spin_lock(&kvm_lock); 6245 list_for_each_entry(kvm, &vm_list, vm_list) 6246 kvm_for_each_vcpu(i, vcpu, kvm) 6247 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 6248 atomic_set(&kvm_guest_has_master_clock, 0); 6249 spin_unlock(&kvm_lock); 6250 } 6251 6252 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 6253 6254 /* 6255 * Notification about pvclock gtod data update. 6256 */ 6257 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 6258 void *priv) 6259 { 6260 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 6261 struct timekeeper *tk = priv; 6262 6263 update_pvclock_gtod(tk); 6264 6265 /* disable master clock if host does not trust, or does not 6266 * use, TSC based clocksource. 6267 */ 6268 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 6269 atomic_read(&kvm_guest_has_master_clock) != 0) 6270 queue_work(system_long_wq, &pvclock_gtod_work); 6271 6272 return 0; 6273 } 6274 6275 static struct notifier_block pvclock_gtod_notifier = { 6276 .notifier_call = pvclock_gtod_notify, 6277 }; 6278 #endif 6279 6280 int kvm_arch_init(void *opaque) 6281 { 6282 int r; 6283 struct kvm_x86_ops *ops = opaque; 6284 6285 if (kvm_x86_ops) { 6286 printk(KERN_ERR "kvm: already loaded the other module\n"); 6287 r = -EEXIST; 6288 goto out; 6289 } 6290 6291 if (!ops->cpu_has_kvm_support()) { 6292 printk(KERN_ERR "kvm: no hardware support\n"); 6293 r = -EOPNOTSUPP; 6294 goto out; 6295 } 6296 if (ops->disabled_by_bios()) { 6297 printk(KERN_ERR "kvm: disabled by bios\n"); 6298 r = -EOPNOTSUPP; 6299 goto out; 6300 } 6301 6302 r = -ENOMEM; 6303 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 6304 if (!shared_msrs) { 6305 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 6306 goto out; 6307 } 6308 6309 r = kvm_mmu_module_init(); 6310 if (r) 6311 goto out_free_percpu; 6312 6313 kvm_set_mmio_spte_mask(); 6314 6315 kvm_x86_ops = ops; 6316 6317 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 6318 PT_DIRTY_MASK, PT64_NX_MASK, 0, 6319 PT_PRESENT_MASK, 0, sme_me_mask); 6320 kvm_timer_init(); 6321 6322 perf_register_guest_info_callbacks(&kvm_guest_cbs); 6323 6324 if (boot_cpu_has(X86_FEATURE_XSAVE)) 6325 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 6326 6327 kvm_lapic_init(); 6328 #ifdef CONFIG_X86_64 6329 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 6330 6331 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 6332 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 6333 #endif 6334 6335 return 0; 6336 6337 out_free_percpu: 6338 free_percpu(shared_msrs); 6339 out: 6340 return r; 6341 } 6342 6343 void kvm_arch_exit(void) 6344 { 6345 #ifdef CONFIG_X86_64 6346 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 6347 clear_hv_tscchange_cb(); 6348 #endif 6349 kvm_lapic_exit(); 6350 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 6351 6352 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 6353 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 6354 CPUFREQ_TRANSITION_NOTIFIER); 6355 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 6356 #ifdef CONFIG_X86_64 6357 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 6358 #endif 6359 kvm_x86_ops = NULL; 6360 kvm_mmu_module_exit(); 6361 free_percpu(shared_msrs); 6362 } 6363 6364 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 6365 { 6366 ++vcpu->stat.halt_exits; 6367 if (lapic_in_kernel(vcpu)) { 6368 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 6369 return 1; 6370 } else { 6371 vcpu->run->exit_reason = KVM_EXIT_HLT; 6372 return 0; 6373 } 6374 } 6375 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 6376 6377 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 6378 { 6379 int ret = kvm_skip_emulated_instruction(vcpu); 6380 /* 6381 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 6382 * KVM_EXIT_DEBUG here. 6383 */ 6384 return kvm_vcpu_halt(vcpu) && ret; 6385 } 6386 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 6387 6388 #ifdef CONFIG_X86_64 6389 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 6390 unsigned long clock_type) 6391 { 6392 struct kvm_clock_pairing clock_pairing; 6393 struct timespec ts; 6394 u64 cycle; 6395 int ret; 6396 6397 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 6398 return -KVM_EOPNOTSUPP; 6399 6400 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) 6401 return -KVM_EOPNOTSUPP; 6402 6403 clock_pairing.sec = ts.tv_sec; 6404 clock_pairing.nsec = ts.tv_nsec; 6405 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 6406 clock_pairing.flags = 0; 6407 6408 ret = 0; 6409 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 6410 sizeof(struct kvm_clock_pairing))) 6411 ret = -KVM_EFAULT; 6412 6413 return ret; 6414 } 6415 #endif 6416 6417 /* 6418 * kvm_pv_kick_cpu_op: Kick a vcpu. 6419 * 6420 * @apicid - apicid of vcpu to be kicked. 6421 */ 6422 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 6423 { 6424 struct kvm_lapic_irq lapic_irq; 6425 6426 lapic_irq.shorthand = 0; 6427 lapic_irq.dest_mode = 0; 6428 lapic_irq.level = 0; 6429 lapic_irq.dest_id = apicid; 6430 lapic_irq.msi_redir_hint = false; 6431 6432 lapic_irq.delivery_mode = APIC_DM_REMRD; 6433 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 6434 } 6435 6436 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) 6437 { 6438 vcpu->arch.apicv_active = false; 6439 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); 6440 } 6441 6442 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 6443 { 6444 unsigned long nr, a0, a1, a2, a3, ret; 6445 int op_64_bit, r; 6446 6447 r = kvm_skip_emulated_instruction(vcpu); 6448 6449 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 6450 return kvm_hv_hypercall(vcpu); 6451 6452 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 6453 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 6454 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 6455 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 6456 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 6457 6458 trace_kvm_hypercall(nr, a0, a1, a2, a3); 6459 6460 op_64_bit = is_64_bit_mode(vcpu); 6461 if (!op_64_bit) { 6462 nr &= 0xFFFFFFFF; 6463 a0 &= 0xFFFFFFFF; 6464 a1 &= 0xFFFFFFFF; 6465 a2 &= 0xFFFFFFFF; 6466 a3 &= 0xFFFFFFFF; 6467 } 6468 6469 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 6470 ret = -KVM_EPERM; 6471 goto out; 6472 } 6473 6474 switch (nr) { 6475 case KVM_HC_VAPIC_POLL_IRQ: 6476 ret = 0; 6477 break; 6478 case KVM_HC_KICK_CPU: 6479 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 6480 ret = 0; 6481 break; 6482 #ifdef CONFIG_X86_64 6483 case KVM_HC_CLOCK_PAIRING: 6484 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 6485 break; 6486 #endif 6487 default: 6488 ret = -KVM_ENOSYS; 6489 break; 6490 } 6491 out: 6492 if (!op_64_bit) 6493 ret = (u32)ret; 6494 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 6495 ++vcpu->stat.hypercalls; 6496 return r; 6497 } 6498 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 6499 6500 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 6501 { 6502 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6503 char instruction[3]; 6504 unsigned long rip = kvm_rip_read(vcpu); 6505 6506 kvm_x86_ops->patch_hypercall(vcpu, instruction); 6507 6508 return emulator_write_emulated(ctxt, rip, instruction, 3, 6509 &ctxt->exception); 6510 } 6511 6512 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 6513 { 6514 return vcpu->run->request_interrupt_window && 6515 likely(!pic_in_kernel(vcpu->kvm)); 6516 } 6517 6518 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 6519 { 6520 struct kvm_run *kvm_run = vcpu->run; 6521 6522 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 6523 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 6524 kvm_run->cr8 = kvm_get_cr8(vcpu); 6525 kvm_run->apic_base = kvm_get_apic_base(vcpu); 6526 kvm_run->ready_for_interrupt_injection = 6527 pic_in_kernel(vcpu->kvm) || 6528 kvm_vcpu_ready_for_interrupt_injection(vcpu); 6529 } 6530 6531 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 6532 { 6533 int max_irr, tpr; 6534 6535 if (!kvm_x86_ops->update_cr8_intercept) 6536 return; 6537 6538 if (!lapic_in_kernel(vcpu)) 6539 return; 6540 6541 if (vcpu->arch.apicv_active) 6542 return; 6543 6544 if (!vcpu->arch.apic->vapic_addr) 6545 max_irr = kvm_lapic_find_highest_irr(vcpu); 6546 else 6547 max_irr = -1; 6548 6549 if (max_irr != -1) 6550 max_irr >>= 4; 6551 6552 tpr = kvm_lapic_get_cr8(vcpu); 6553 6554 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 6555 } 6556 6557 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 6558 { 6559 int r; 6560 6561 /* try to reinject previous events if any */ 6562 if (vcpu->arch.exception.injected) { 6563 kvm_x86_ops->queue_exception(vcpu); 6564 return 0; 6565 } 6566 6567 /* 6568 * Exceptions must be injected immediately, or the exception 6569 * frame will have the address of the NMI or interrupt handler. 6570 */ 6571 if (!vcpu->arch.exception.pending) { 6572 if (vcpu->arch.nmi_injected) { 6573 kvm_x86_ops->set_nmi(vcpu); 6574 return 0; 6575 } 6576 6577 if (vcpu->arch.interrupt.pending) { 6578 kvm_x86_ops->set_irq(vcpu); 6579 return 0; 6580 } 6581 } 6582 6583 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6584 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6585 if (r != 0) 6586 return r; 6587 } 6588 6589 /* try to inject new event if pending */ 6590 if (vcpu->arch.exception.pending) { 6591 trace_kvm_inj_exception(vcpu->arch.exception.nr, 6592 vcpu->arch.exception.has_error_code, 6593 vcpu->arch.exception.error_code); 6594 6595 vcpu->arch.exception.pending = false; 6596 vcpu->arch.exception.injected = true; 6597 6598 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 6599 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 6600 X86_EFLAGS_RF); 6601 6602 if (vcpu->arch.exception.nr == DB_VECTOR && 6603 (vcpu->arch.dr7 & DR7_GD)) { 6604 vcpu->arch.dr7 &= ~DR7_GD; 6605 kvm_update_dr7(vcpu); 6606 } 6607 6608 kvm_x86_ops->queue_exception(vcpu); 6609 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) { 6610 vcpu->arch.smi_pending = false; 6611 ++vcpu->arch.smi_count; 6612 enter_smm(vcpu); 6613 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { 6614 --vcpu->arch.nmi_pending; 6615 vcpu->arch.nmi_injected = true; 6616 kvm_x86_ops->set_nmi(vcpu); 6617 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 6618 /* 6619 * Because interrupts can be injected asynchronously, we are 6620 * calling check_nested_events again here to avoid a race condition. 6621 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 6622 * proposal and current concerns. Perhaps we should be setting 6623 * KVM_REQ_EVENT only on certain events and not unconditionally? 6624 */ 6625 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6626 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6627 if (r != 0) 6628 return r; 6629 } 6630 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 6631 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 6632 false); 6633 kvm_x86_ops->set_irq(vcpu); 6634 } 6635 } 6636 6637 return 0; 6638 } 6639 6640 static void process_nmi(struct kvm_vcpu *vcpu) 6641 { 6642 unsigned limit = 2; 6643 6644 /* 6645 * x86 is limited to one NMI running, and one NMI pending after it. 6646 * If an NMI is already in progress, limit further NMIs to just one. 6647 * Otherwise, allow two (and we'll inject the first one immediately). 6648 */ 6649 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 6650 limit = 1; 6651 6652 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 6653 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 6654 kvm_make_request(KVM_REQ_EVENT, vcpu); 6655 } 6656 6657 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 6658 { 6659 u32 flags = 0; 6660 flags |= seg->g << 23; 6661 flags |= seg->db << 22; 6662 flags |= seg->l << 21; 6663 flags |= seg->avl << 20; 6664 flags |= seg->present << 15; 6665 flags |= seg->dpl << 13; 6666 flags |= seg->s << 12; 6667 flags |= seg->type << 8; 6668 return flags; 6669 } 6670 6671 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 6672 { 6673 struct kvm_segment seg; 6674 int offset; 6675 6676 kvm_get_segment(vcpu, &seg, n); 6677 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 6678 6679 if (n < 3) 6680 offset = 0x7f84 + n * 12; 6681 else 6682 offset = 0x7f2c + (n - 3) * 12; 6683 6684 put_smstate(u32, buf, offset + 8, seg.base); 6685 put_smstate(u32, buf, offset + 4, seg.limit); 6686 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 6687 } 6688 6689 #ifdef CONFIG_X86_64 6690 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 6691 { 6692 struct kvm_segment seg; 6693 int offset; 6694 u16 flags; 6695 6696 kvm_get_segment(vcpu, &seg, n); 6697 offset = 0x7e00 + n * 16; 6698 6699 flags = enter_smm_get_segment_flags(&seg) >> 8; 6700 put_smstate(u16, buf, offset, seg.selector); 6701 put_smstate(u16, buf, offset + 2, flags); 6702 put_smstate(u32, buf, offset + 4, seg.limit); 6703 put_smstate(u64, buf, offset + 8, seg.base); 6704 } 6705 #endif 6706 6707 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 6708 { 6709 struct desc_ptr dt; 6710 struct kvm_segment seg; 6711 unsigned long val; 6712 int i; 6713 6714 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 6715 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 6716 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 6717 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 6718 6719 for (i = 0; i < 8; i++) 6720 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 6721 6722 kvm_get_dr(vcpu, 6, &val); 6723 put_smstate(u32, buf, 0x7fcc, (u32)val); 6724 kvm_get_dr(vcpu, 7, &val); 6725 put_smstate(u32, buf, 0x7fc8, (u32)val); 6726 6727 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6728 put_smstate(u32, buf, 0x7fc4, seg.selector); 6729 put_smstate(u32, buf, 0x7f64, seg.base); 6730 put_smstate(u32, buf, 0x7f60, seg.limit); 6731 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 6732 6733 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6734 put_smstate(u32, buf, 0x7fc0, seg.selector); 6735 put_smstate(u32, buf, 0x7f80, seg.base); 6736 put_smstate(u32, buf, 0x7f7c, seg.limit); 6737 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 6738 6739 kvm_x86_ops->get_gdt(vcpu, &dt); 6740 put_smstate(u32, buf, 0x7f74, dt.address); 6741 put_smstate(u32, buf, 0x7f70, dt.size); 6742 6743 kvm_x86_ops->get_idt(vcpu, &dt); 6744 put_smstate(u32, buf, 0x7f58, dt.address); 6745 put_smstate(u32, buf, 0x7f54, dt.size); 6746 6747 for (i = 0; i < 6; i++) 6748 enter_smm_save_seg_32(vcpu, buf, i); 6749 6750 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 6751 6752 /* revision id */ 6753 put_smstate(u32, buf, 0x7efc, 0x00020000); 6754 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 6755 } 6756 6757 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 6758 { 6759 #ifdef CONFIG_X86_64 6760 struct desc_ptr dt; 6761 struct kvm_segment seg; 6762 unsigned long val; 6763 int i; 6764 6765 for (i = 0; i < 16; i++) 6766 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 6767 6768 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 6769 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 6770 6771 kvm_get_dr(vcpu, 6, &val); 6772 put_smstate(u64, buf, 0x7f68, val); 6773 kvm_get_dr(vcpu, 7, &val); 6774 put_smstate(u64, buf, 0x7f60, val); 6775 6776 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 6777 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 6778 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 6779 6780 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 6781 6782 /* revision id */ 6783 put_smstate(u32, buf, 0x7efc, 0x00020064); 6784 6785 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 6786 6787 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6788 put_smstate(u16, buf, 0x7e90, seg.selector); 6789 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 6790 put_smstate(u32, buf, 0x7e94, seg.limit); 6791 put_smstate(u64, buf, 0x7e98, seg.base); 6792 6793 kvm_x86_ops->get_idt(vcpu, &dt); 6794 put_smstate(u32, buf, 0x7e84, dt.size); 6795 put_smstate(u64, buf, 0x7e88, dt.address); 6796 6797 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6798 put_smstate(u16, buf, 0x7e70, seg.selector); 6799 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 6800 put_smstate(u32, buf, 0x7e74, seg.limit); 6801 put_smstate(u64, buf, 0x7e78, seg.base); 6802 6803 kvm_x86_ops->get_gdt(vcpu, &dt); 6804 put_smstate(u32, buf, 0x7e64, dt.size); 6805 put_smstate(u64, buf, 0x7e68, dt.address); 6806 6807 for (i = 0; i < 6; i++) 6808 enter_smm_save_seg_64(vcpu, buf, i); 6809 #else 6810 WARN_ON_ONCE(1); 6811 #endif 6812 } 6813 6814 static void enter_smm(struct kvm_vcpu *vcpu) 6815 { 6816 struct kvm_segment cs, ds; 6817 struct desc_ptr dt; 6818 char buf[512]; 6819 u32 cr0; 6820 6821 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 6822 memset(buf, 0, 512); 6823 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 6824 enter_smm_save_state_64(vcpu, buf); 6825 else 6826 enter_smm_save_state_32(vcpu, buf); 6827 6828 /* 6829 * Give pre_enter_smm() a chance to make ISA-specific changes to the 6830 * vCPU state (e.g. leave guest mode) after we've saved the state into 6831 * the SMM state-save area. 6832 */ 6833 kvm_x86_ops->pre_enter_smm(vcpu, buf); 6834 6835 vcpu->arch.hflags |= HF_SMM_MASK; 6836 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 6837 6838 if (kvm_x86_ops->get_nmi_mask(vcpu)) 6839 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 6840 else 6841 kvm_x86_ops->set_nmi_mask(vcpu, true); 6842 6843 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 6844 kvm_rip_write(vcpu, 0x8000); 6845 6846 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 6847 kvm_x86_ops->set_cr0(vcpu, cr0); 6848 vcpu->arch.cr0 = cr0; 6849 6850 kvm_x86_ops->set_cr4(vcpu, 0); 6851 6852 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 6853 dt.address = dt.size = 0; 6854 kvm_x86_ops->set_idt(vcpu, &dt); 6855 6856 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 6857 6858 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 6859 cs.base = vcpu->arch.smbase; 6860 6861 ds.selector = 0; 6862 ds.base = 0; 6863 6864 cs.limit = ds.limit = 0xffffffff; 6865 cs.type = ds.type = 0x3; 6866 cs.dpl = ds.dpl = 0; 6867 cs.db = ds.db = 0; 6868 cs.s = ds.s = 1; 6869 cs.l = ds.l = 0; 6870 cs.g = ds.g = 1; 6871 cs.avl = ds.avl = 0; 6872 cs.present = ds.present = 1; 6873 cs.unusable = ds.unusable = 0; 6874 cs.padding = ds.padding = 0; 6875 6876 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 6877 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 6878 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 6879 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 6880 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 6881 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 6882 6883 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 6884 kvm_x86_ops->set_efer(vcpu, 0); 6885 6886 kvm_update_cpuid(vcpu); 6887 kvm_mmu_reset_context(vcpu); 6888 } 6889 6890 static void process_smi(struct kvm_vcpu *vcpu) 6891 { 6892 vcpu->arch.smi_pending = true; 6893 kvm_make_request(KVM_REQ_EVENT, vcpu); 6894 } 6895 6896 void kvm_make_scan_ioapic_request(struct kvm *kvm) 6897 { 6898 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 6899 } 6900 6901 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 6902 { 6903 u64 eoi_exit_bitmap[4]; 6904 6905 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 6906 return; 6907 6908 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 6909 6910 if (irqchip_split(vcpu->kvm)) 6911 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 6912 else { 6913 if (vcpu->arch.apicv_active) 6914 kvm_x86_ops->sync_pir_to_irr(vcpu); 6915 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 6916 } 6917 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, 6918 vcpu_to_synic(vcpu)->vec_bitmap, 256); 6919 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 6920 } 6921 6922 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 6923 unsigned long start, unsigned long end) 6924 { 6925 unsigned long apic_address; 6926 6927 /* 6928 * The physical address of apic access page is stored in the VMCS. 6929 * Update it when it becomes invalid. 6930 */ 6931 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 6932 if (start <= apic_address && apic_address < end) 6933 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 6934 } 6935 6936 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 6937 { 6938 struct page *page = NULL; 6939 6940 if (!lapic_in_kernel(vcpu)) 6941 return; 6942 6943 if (!kvm_x86_ops->set_apic_access_page_addr) 6944 return; 6945 6946 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 6947 if (is_error_page(page)) 6948 return; 6949 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 6950 6951 /* 6952 * Do not pin apic access page in memory, the MMU notifier 6953 * will call us again if it is migrated or swapped out. 6954 */ 6955 put_page(page); 6956 } 6957 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 6958 6959 /* 6960 * Returns 1 to let vcpu_run() continue the guest execution loop without 6961 * exiting to the userspace. Otherwise, the value will be returned to the 6962 * userspace. 6963 */ 6964 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 6965 { 6966 int r; 6967 bool req_int_win = 6968 dm_request_for_irq_injection(vcpu) && 6969 kvm_cpu_accept_dm_intr(vcpu); 6970 6971 bool req_immediate_exit = false; 6972 6973 if (kvm_request_pending(vcpu)) { 6974 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 6975 kvm_mmu_unload(vcpu); 6976 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 6977 __kvm_migrate_timers(vcpu); 6978 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 6979 kvm_gen_update_masterclock(vcpu->kvm); 6980 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 6981 kvm_gen_kvmclock_update(vcpu); 6982 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 6983 r = kvm_guest_time_update(vcpu); 6984 if (unlikely(r)) 6985 goto out; 6986 } 6987 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 6988 kvm_mmu_sync_roots(vcpu); 6989 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 6990 kvm_vcpu_flush_tlb(vcpu, true); 6991 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 6992 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 6993 r = 0; 6994 goto out; 6995 } 6996 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 6997 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 6998 vcpu->mmio_needed = 0; 6999 r = 0; 7000 goto out; 7001 } 7002 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 7003 /* Page is swapped out. Do synthetic halt */ 7004 vcpu->arch.apf.halted = true; 7005 r = 1; 7006 goto out; 7007 } 7008 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 7009 record_steal_time(vcpu); 7010 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 7011 process_smi(vcpu); 7012 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 7013 process_nmi(vcpu); 7014 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 7015 kvm_pmu_handle_event(vcpu); 7016 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 7017 kvm_pmu_deliver_pmi(vcpu); 7018 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 7019 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 7020 if (test_bit(vcpu->arch.pending_ioapic_eoi, 7021 vcpu->arch.ioapic_handled_vectors)) { 7022 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 7023 vcpu->run->eoi.vector = 7024 vcpu->arch.pending_ioapic_eoi; 7025 r = 0; 7026 goto out; 7027 } 7028 } 7029 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 7030 vcpu_scan_ioapic(vcpu); 7031 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 7032 kvm_vcpu_reload_apic_access_page(vcpu); 7033 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 7034 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 7035 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 7036 r = 0; 7037 goto out; 7038 } 7039 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 7040 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 7041 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 7042 r = 0; 7043 goto out; 7044 } 7045 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 7046 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 7047 vcpu->run->hyperv = vcpu->arch.hyperv.exit; 7048 r = 0; 7049 goto out; 7050 } 7051 7052 /* 7053 * KVM_REQ_HV_STIMER has to be processed after 7054 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 7055 * depend on the guest clock being up-to-date 7056 */ 7057 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 7058 kvm_hv_process_stimers(vcpu); 7059 } 7060 7061 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 7062 ++vcpu->stat.req_event; 7063 kvm_apic_accept_events(vcpu); 7064 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 7065 r = 1; 7066 goto out; 7067 } 7068 7069 if (inject_pending_event(vcpu, req_int_win) != 0) 7070 req_immediate_exit = true; 7071 else { 7072 /* Enable SMI/NMI/IRQ window open exits if needed. 7073 * 7074 * SMIs have three cases: 7075 * 1) They can be nested, and then there is nothing to 7076 * do here because RSM will cause a vmexit anyway. 7077 * 2) There is an ISA-specific reason why SMI cannot be 7078 * injected, and the moment when this changes can be 7079 * intercepted. 7080 * 3) Or the SMI can be pending because 7081 * inject_pending_event has completed the injection 7082 * of an IRQ or NMI from the previous vmexit, and 7083 * then we request an immediate exit to inject the 7084 * SMI. 7085 */ 7086 if (vcpu->arch.smi_pending && !is_smm(vcpu)) 7087 if (!kvm_x86_ops->enable_smi_window(vcpu)) 7088 req_immediate_exit = true; 7089 if (vcpu->arch.nmi_pending) 7090 kvm_x86_ops->enable_nmi_window(vcpu); 7091 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 7092 kvm_x86_ops->enable_irq_window(vcpu); 7093 WARN_ON(vcpu->arch.exception.pending); 7094 } 7095 7096 if (kvm_lapic_enabled(vcpu)) { 7097 update_cr8_intercept(vcpu); 7098 kvm_lapic_sync_to_vapic(vcpu); 7099 } 7100 } 7101 7102 r = kvm_mmu_reload(vcpu); 7103 if (unlikely(r)) { 7104 goto cancel_injection; 7105 } 7106 7107 preempt_disable(); 7108 7109 kvm_x86_ops->prepare_guest_switch(vcpu); 7110 7111 /* 7112 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 7113 * IPI are then delayed after guest entry, which ensures that they 7114 * result in virtual interrupt delivery. 7115 */ 7116 local_irq_disable(); 7117 vcpu->mode = IN_GUEST_MODE; 7118 7119 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 7120 7121 /* 7122 * 1) We should set ->mode before checking ->requests. Please see 7123 * the comment in kvm_vcpu_exiting_guest_mode(). 7124 * 7125 * 2) For APICv, we should set ->mode before checking PIR.ON. This 7126 * pairs with the memory barrier implicit in pi_test_and_set_on 7127 * (see vmx_deliver_posted_interrupt). 7128 * 7129 * 3) This also orders the write to mode from any reads to the page 7130 * tables done while the VCPU is running. Please see the comment 7131 * in kvm_flush_remote_tlbs. 7132 */ 7133 smp_mb__after_srcu_read_unlock(); 7134 7135 /* 7136 * This handles the case where a posted interrupt was 7137 * notified with kvm_vcpu_kick. 7138 */ 7139 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) 7140 kvm_x86_ops->sync_pir_to_irr(vcpu); 7141 7142 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) 7143 || need_resched() || signal_pending(current)) { 7144 vcpu->mode = OUTSIDE_GUEST_MODE; 7145 smp_wmb(); 7146 local_irq_enable(); 7147 preempt_enable(); 7148 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7149 r = 1; 7150 goto cancel_injection; 7151 } 7152 7153 kvm_load_guest_xcr0(vcpu); 7154 7155 if (req_immediate_exit) { 7156 kvm_make_request(KVM_REQ_EVENT, vcpu); 7157 smp_send_reschedule(vcpu->cpu); 7158 } 7159 7160 trace_kvm_entry(vcpu->vcpu_id); 7161 if (lapic_timer_advance_ns) 7162 wait_lapic_expire(vcpu); 7163 guest_enter_irqoff(); 7164 7165 if (unlikely(vcpu->arch.switch_db_regs)) { 7166 set_debugreg(0, 7); 7167 set_debugreg(vcpu->arch.eff_db[0], 0); 7168 set_debugreg(vcpu->arch.eff_db[1], 1); 7169 set_debugreg(vcpu->arch.eff_db[2], 2); 7170 set_debugreg(vcpu->arch.eff_db[3], 3); 7171 set_debugreg(vcpu->arch.dr6, 6); 7172 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 7173 } 7174 7175 kvm_x86_ops->run(vcpu); 7176 7177 /* 7178 * Do this here before restoring debug registers on the host. And 7179 * since we do this before handling the vmexit, a DR access vmexit 7180 * can (a) read the correct value of the debug registers, (b) set 7181 * KVM_DEBUGREG_WONT_EXIT again. 7182 */ 7183 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 7184 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 7185 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 7186 kvm_update_dr0123(vcpu); 7187 kvm_update_dr6(vcpu); 7188 kvm_update_dr7(vcpu); 7189 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 7190 } 7191 7192 /* 7193 * If the guest has used debug registers, at least dr7 7194 * will be disabled while returning to the host. 7195 * If we don't have active breakpoints in the host, we don't 7196 * care about the messed up debug address registers. But if 7197 * we have some of them active, restore the old state. 7198 */ 7199 if (hw_breakpoint_active()) 7200 hw_breakpoint_restore(); 7201 7202 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 7203 7204 vcpu->mode = OUTSIDE_GUEST_MODE; 7205 smp_wmb(); 7206 7207 kvm_put_guest_xcr0(vcpu); 7208 7209 kvm_x86_ops->handle_external_intr(vcpu); 7210 7211 ++vcpu->stat.exits; 7212 7213 guest_exit_irqoff(); 7214 7215 local_irq_enable(); 7216 preempt_enable(); 7217 7218 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7219 7220 /* 7221 * Profile KVM exit RIPs: 7222 */ 7223 if (unlikely(prof_on == KVM_PROFILING)) { 7224 unsigned long rip = kvm_rip_read(vcpu); 7225 profile_hit(KVM_PROFILING, (void *)rip); 7226 } 7227 7228 if (unlikely(vcpu->arch.tsc_always_catchup)) 7229 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7230 7231 if (vcpu->arch.apic_attention) 7232 kvm_lapic_sync_from_vapic(vcpu); 7233 7234 vcpu->arch.gpa_available = false; 7235 r = kvm_x86_ops->handle_exit(vcpu); 7236 return r; 7237 7238 cancel_injection: 7239 kvm_x86_ops->cancel_injection(vcpu); 7240 if (unlikely(vcpu->arch.apic_attention)) 7241 kvm_lapic_sync_from_vapic(vcpu); 7242 out: 7243 return r; 7244 } 7245 7246 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 7247 { 7248 if (!kvm_arch_vcpu_runnable(vcpu) && 7249 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { 7250 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7251 kvm_vcpu_block(vcpu); 7252 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7253 7254 if (kvm_x86_ops->post_block) 7255 kvm_x86_ops->post_block(vcpu); 7256 7257 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 7258 return 1; 7259 } 7260 7261 kvm_apic_accept_events(vcpu); 7262 switch(vcpu->arch.mp_state) { 7263 case KVM_MP_STATE_HALTED: 7264 vcpu->arch.pv.pv_unhalted = false; 7265 vcpu->arch.mp_state = 7266 KVM_MP_STATE_RUNNABLE; 7267 case KVM_MP_STATE_RUNNABLE: 7268 vcpu->arch.apf.halted = false; 7269 break; 7270 case KVM_MP_STATE_INIT_RECEIVED: 7271 break; 7272 default: 7273 return -EINTR; 7274 break; 7275 } 7276 return 1; 7277 } 7278 7279 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 7280 { 7281 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 7282 kvm_x86_ops->check_nested_events(vcpu, false); 7283 7284 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 7285 !vcpu->arch.apf.halted); 7286 } 7287 7288 static int vcpu_run(struct kvm_vcpu *vcpu) 7289 { 7290 int r; 7291 struct kvm *kvm = vcpu->kvm; 7292 7293 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7294 7295 for (;;) { 7296 if (kvm_vcpu_running(vcpu)) { 7297 r = vcpu_enter_guest(vcpu); 7298 } else { 7299 r = vcpu_block(kvm, vcpu); 7300 } 7301 7302 if (r <= 0) 7303 break; 7304 7305 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); 7306 if (kvm_cpu_has_pending_timer(vcpu)) 7307 kvm_inject_pending_timer_irqs(vcpu); 7308 7309 if (dm_request_for_irq_injection(vcpu) && 7310 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 7311 r = 0; 7312 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 7313 ++vcpu->stat.request_irq_exits; 7314 break; 7315 } 7316 7317 kvm_check_async_pf_completion(vcpu); 7318 7319 if (signal_pending(current)) { 7320 r = -EINTR; 7321 vcpu->run->exit_reason = KVM_EXIT_INTR; 7322 ++vcpu->stat.signal_exits; 7323 break; 7324 } 7325 if (need_resched()) { 7326 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7327 cond_resched(); 7328 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7329 } 7330 } 7331 7332 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7333 7334 return r; 7335 } 7336 7337 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 7338 { 7339 int r; 7340 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7341 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 7342 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 7343 if (r != EMULATE_DONE) 7344 return 0; 7345 return 1; 7346 } 7347 7348 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 7349 { 7350 BUG_ON(!vcpu->arch.pio.count); 7351 7352 return complete_emulated_io(vcpu); 7353 } 7354 7355 /* 7356 * Implements the following, as a state machine: 7357 * 7358 * read: 7359 * for each fragment 7360 * for each mmio piece in the fragment 7361 * write gpa, len 7362 * exit 7363 * copy data 7364 * execute insn 7365 * 7366 * write: 7367 * for each fragment 7368 * for each mmio piece in the fragment 7369 * write gpa, len 7370 * copy data 7371 * exit 7372 */ 7373 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 7374 { 7375 struct kvm_run *run = vcpu->run; 7376 struct kvm_mmio_fragment *frag; 7377 unsigned len; 7378 7379 BUG_ON(!vcpu->mmio_needed); 7380 7381 /* Complete previous fragment */ 7382 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 7383 len = min(8u, frag->len); 7384 if (!vcpu->mmio_is_write) 7385 memcpy(frag->data, run->mmio.data, len); 7386 7387 if (frag->len <= 8) { 7388 /* Switch to the next fragment. */ 7389 frag++; 7390 vcpu->mmio_cur_fragment++; 7391 } else { 7392 /* Go forward to the next mmio piece. */ 7393 frag->data += len; 7394 frag->gpa += len; 7395 frag->len -= len; 7396 } 7397 7398 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 7399 vcpu->mmio_needed = 0; 7400 7401 /* FIXME: return into emulator if single-stepping. */ 7402 if (vcpu->mmio_is_write) 7403 return 1; 7404 vcpu->mmio_read_completed = 1; 7405 return complete_emulated_io(vcpu); 7406 } 7407 7408 run->exit_reason = KVM_EXIT_MMIO; 7409 run->mmio.phys_addr = frag->gpa; 7410 if (vcpu->mmio_is_write) 7411 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 7412 run->mmio.len = min(8u, frag->len); 7413 run->mmio.is_write = vcpu->mmio_is_write; 7414 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 7415 return 0; 7416 } 7417 7418 7419 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 7420 { 7421 int r; 7422 7423 vcpu_load(vcpu); 7424 kvm_sigset_activate(vcpu); 7425 kvm_load_guest_fpu(vcpu); 7426 7427 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 7428 if (kvm_run->immediate_exit) { 7429 r = -EINTR; 7430 goto out; 7431 } 7432 kvm_vcpu_block(vcpu); 7433 kvm_apic_accept_events(vcpu); 7434 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 7435 r = -EAGAIN; 7436 if (signal_pending(current)) { 7437 r = -EINTR; 7438 vcpu->run->exit_reason = KVM_EXIT_INTR; 7439 ++vcpu->stat.signal_exits; 7440 } 7441 goto out; 7442 } 7443 7444 /* re-sync apic's tpr */ 7445 if (!lapic_in_kernel(vcpu)) { 7446 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 7447 r = -EINVAL; 7448 goto out; 7449 } 7450 } 7451 7452 if (unlikely(vcpu->arch.complete_userspace_io)) { 7453 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 7454 vcpu->arch.complete_userspace_io = NULL; 7455 r = cui(vcpu); 7456 if (r <= 0) 7457 goto out; 7458 } else 7459 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 7460 7461 if (kvm_run->immediate_exit) 7462 r = -EINTR; 7463 else 7464 r = vcpu_run(vcpu); 7465 7466 out: 7467 kvm_put_guest_fpu(vcpu); 7468 post_kvm_run_save(vcpu); 7469 kvm_sigset_deactivate(vcpu); 7470 7471 vcpu_put(vcpu); 7472 return r; 7473 } 7474 7475 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7476 { 7477 vcpu_load(vcpu); 7478 7479 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 7480 /* 7481 * We are here if userspace calls get_regs() in the middle of 7482 * instruction emulation. Registers state needs to be copied 7483 * back from emulation context to vcpu. Userspace shouldn't do 7484 * that usually, but some bad designed PV devices (vmware 7485 * backdoor interface) need this to work 7486 */ 7487 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 7488 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7489 } 7490 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 7491 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 7492 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 7493 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 7494 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 7495 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 7496 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 7497 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 7498 #ifdef CONFIG_X86_64 7499 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 7500 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 7501 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 7502 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 7503 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 7504 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 7505 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 7506 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 7507 #endif 7508 7509 regs->rip = kvm_rip_read(vcpu); 7510 regs->rflags = kvm_get_rflags(vcpu); 7511 7512 vcpu_put(vcpu); 7513 return 0; 7514 } 7515 7516 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7517 { 7518 vcpu_load(vcpu); 7519 7520 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 7521 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7522 7523 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 7524 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 7525 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 7526 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 7527 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 7528 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 7529 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 7530 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 7531 #ifdef CONFIG_X86_64 7532 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 7533 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 7534 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 7535 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 7536 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 7537 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 7538 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 7539 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 7540 #endif 7541 7542 kvm_rip_write(vcpu, regs->rip); 7543 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 7544 7545 vcpu->arch.exception.pending = false; 7546 7547 kvm_make_request(KVM_REQ_EVENT, vcpu); 7548 7549 vcpu_put(vcpu); 7550 return 0; 7551 } 7552 7553 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 7554 { 7555 struct kvm_segment cs; 7556 7557 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7558 *db = cs.db; 7559 *l = cs.l; 7560 } 7561 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 7562 7563 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 7564 struct kvm_sregs *sregs) 7565 { 7566 struct desc_ptr dt; 7567 7568 vcpu_load(vcpu); 7569 7570 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7571 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7572 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7573 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7574 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7575 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7576 7577 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7578 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7579 7580 kvm_x86_ops->get_idt(vcpu, &dt); 7581 sregs->idt.limit = dt.size; 7582 sregs->idt.base = dt.address; 7583 kvm_x86_ops->get_gdt(vcpu, &dt); 7584 sregs->gdt.limit = dt.size; 7585 sregs->gdt.base = dt.address; 7586 7587 sregs->cr0 = kvm_read_cr0(vcpu); 7588 sregs->cr2 = vcpu->arch.cr2; 7589 sregs->cr3 = kvm_read_cr3(vcpu); 7590 sregs->cr4 = kvm_read_cr4(vcpu); 7591 sregs->cr8 = kvm_get_cr8(vcpu); 7592 sregs->efer = vcpu->arch.efer; 7593 sregs->apic_base = kvm_get_apic_base(vcpu); 7594 7595 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 7596 7597 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) 7598 set_bit(vcpu->arch.interrupt.nr, 7599 (unsigned long *)sregs->interrupt_bitmap); 7600 7601 vcpu_put(vcpu); 7602 return 0; 7603 } 7604 7605 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 7606 struct kvm_mp_state *mp_state) 7607 { 7608 vcpu_load(vcpu); 7609 7610 kvm_apic_accept_events(vcpu); 7611 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 7612 vcpu->arch.pv.pv_unhalted) 7613 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 7614 else 7615 mp_state->mp_state = vcpu->arch.mp_state; 7616 7617 vcpu_put(vcpu); 7618 return 0; 7619 } 7620 7621 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 7622 struct kvm_mp_state *mp_state) 7623 { 7624 int ret = -EINVAL; 7625 7626 vcpu_load(vcpu); 7627 7628 if (!lapic_in_kernel(vcpu) && 7629 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 7630 goto out; 7631 7632 /* INITs are latched while in SMM */ 7633 if ((is_smm(vcpu) || vcpu->arch.smi_pending) && 7634 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 7635 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 7636 goto out; 7637 7638 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 7639 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 7640 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 7641 } else 7642 vcpu->arch.mp_state = mp_state->mp_state; 7643 kvm_make_request(KVM_REQ_EVENT, vcpu); 7644 7645 ret = 0; 7646 out: 7647 vcpu_put(vcpu); 7648 return ret; 7649 } 7650 7651 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 7652 int reason, bool has_error_code, u32 error_code) 7653 { 7654 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 7655 int ret; 7656 7657 init_emulate_ctxt(vcpu); 7658 7659 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 7660 has_error_code, error_code); 7661 7662 if (ret) 7663 return EMULATE_FAIL; 7664 7665 kvm_rip_write(vcpu, ctxt->eip); 7666 kvm_set_rflags(vcpu, ctxt->eflags); 7667 kvm_make_request(KVM_REQ_EVENT, vcpu); 7668 return EMULATE_DONE; 7669 } 7670 EXPORT_SYMBOL_GPL(kvm_task_switch); 7671 7672 int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 7673 { 7674 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 7675 /* 7676 * When EFER.LME and CR0.PG are set, the processor is in 7677 * 64-bit mode (though maybe in a 32-bit code segment). 7678 * CR4.PAE and EFER.LMA must be set. 7679 */ 7680 if (!(sregs->cr4 & X86_CR4_PAE) 7681 || !(sregs->efer & EFER_LMA)) 7682 return -EINVAL; 7683 } else { 7684 /* 7685 * Not in 64-bit mode: EFER.LMA is clear and the code 7686 * segment cannot be 64-bit. 7687 */ 7688 if (sregs->efer & EFER_LMA || sregs->cs.l) 7689 return -EINVAL; 7690 } 7691 7692 return 0; 7693 } 7694 7695 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 7696 struct kvm_sregs *sregs) 7697 { 7698 struct msr_data apic_base_msr; 7699 int mmu_reset_needed = 0; 7700 int pending_vec, max_bits, idx; 7701 struct desc_ptr dt; 7702 int ret = -EINVAL; 7703 7704 vcpu_load(vcpu); 7705 7706 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 7707 (sregs->cr4 & X86_CR4_OSXSAVE)) 7708 goto out; 7709 7710 if (kvm_valid_sregs(vcpu, sregs)) 7711 goto out; 7712 7713 apic_base_msr.data = sregs->apic_base; 7714 apic_base_msr.host_initiated = true; 7715 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 7716 goto out; 7717 7718 dt.size = sregs->idt.limit; 7719 dt.address = sregs->idt.base; 7720 kvm_x86_ops->set_idt(vcpu, &dt); 7721 dt.size = sregs->gdt.limit; 7722 dt.address = sregs->gdt.base; 7723 kvm_x86_ops->set_gdt(vcpu, &dt); 7724 7725 vcpu->arch.cr2 = sregs->cr2; 7726 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 7727 vcpu->arch.cr3 = sregs->cr3; 7728 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 7729 7730 kvm_set_cr8(vcpu, sregs->cr8); 7731 7732 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 7733 kvm_x86_ops->set_efer(vcpu, sregs->efer); 7734 7735 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 7736 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 7737 vcpu->arch.cr0 = sregs->cr0; 7738 7739 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 7740 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 7741 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 7742 kvm_update_cpuid(vcpu); 7743 7744 idx = srcu_read_lock(&vcpu->kvm->srcu); 7745 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 7746 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 7747 mmu_reset_needed = 1; 7748 } 7749 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7750 7751 if (mmu_reset_needed) 7752 kvm_mmu_reset_context(vcpu); 7753 7754 max_bits = KVM_NR_INTERRUPTS; 7755 pending_vec = find_first_bit( 7756 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 7757 if (pending_vec < max_bits) { 7758 kvm_queue_interrupt(vcpu, pending_vec, false); 7759 pr_debug("Set back pending irq %d\n", pending_vec); 7760 } 7761 7762 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7763 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7764 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7765 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7766 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7767 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7768 7769 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7770 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7771 7772 update_cr8_intercept(vcpu); 7773 7774 /* Older userspace won't unhalt the vcpu on reset. */ 7775 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 7776 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 7777 !is_protmode(vcpu)) 7778 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7779 7780 kvm_make_request(KVM_REQ_EVENT, vcpu); 7781 7782 ret = 0; 7783 out: 7784 vcpu_put(vcpu); 7785 return ret; 7786 } 7787 7788 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 7789 struct kvm_guest_debug *dbg) 7790 { 7791 unsigned long rflags; 7792 int i, r; 7793 7794 vcpu_load(vcpu); 7795 7796 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 7797 r = -EBUSY; 7798 if (vcpu->arch.exception.pending) 7799 goto out; 7800 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 7801 kvm_queue_exception(vcpu, DB_VECTOR); 7802 else 7803 kvm_queue_exception(vcpu, BP_VECTOR); 7804 } 7805 7806 /* 7807 * Read rflags as long as potentially injected trace flags are still 7808 * filtered out. 7809 */ 7810 rflags = kvm_get_rflags(vcpu); 7811 7812 vcpu->guest_debug = dbg->control; 7813 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 7814 vcpu->guest_debug = 0; 7815 7816 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 7817 for (i = 0; i < KVM_NR_DB_REGS; ++i) 7818 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 7819 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 7820 } else { 7821 for (i = 0; i < KVM_NR_DB_REGS; i++) 7822 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 7823 } 7824 kvm_update_dr7(vcpu); 7825 7826 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 7827 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 7828 get_segment_base(vcpu, VCPU_SREG_CS); 7829 7830 /* 7831 * Trigger an rflags update that will inject or remove the trace 7832 * flags. 7833 */ 7834 kvm_set_rflags(vcpu, rflags); 7835 7836 kvm_x86_ops->update_bp_intercept(vcpu); 7837 7838 r = 0; 7839 7840 out: 7841 vcpu_put(vcpu); 7842 return r; 7843 } 7844 7845 /* 7846 * Translate a guest virtual address to a guest physical address. 7847 */ 7848 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 7849 struct kvm_translation *tr) 7850 { 7851 unsigned long vaddr = tr->linear_address; 7852 gpa_t gpa; 7853 int idx; 7854 7855 vcpu_load(vcpu); 7856 7857 idx = srcu_read_lock(&vcpu->kvm->srcu); 7858 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 7859 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7860 tr->physical_address = gpa; 7861 tr->valid = gpa != UNMAPPED_GVA; 7862 tr->writeable = 1; 7863 tr->usermode = 0; 7864 7865 vcpu_put(vcpu); 7866 return 0; 7867 } 7868 7869 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7870 { 7871 struct fxregs_state *fxsave; 7872 7873 vcpu_load(vcpu); 7874 7875 fxsave = &vcpu->arch.guest_fpu.state.fxsave; 7876 memcpy(fpu->fpr, fxsave->st_space, 128); 7877 fpu->fcw = fxsave->cwd; 7878 fpu->fsw = fxsave->swd; 7879 fpu->ftwx = fxsave->twd; 7880 fpu->last_opcode = fxsave->fop; 7881 fpu->last_ip = fxsave->rip; 7882 fpu->last_dp = fxsave->rdp; 7883 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 7884 7885 vcpu_put(vcpu); 7886 return 0; 7887 } 7888 7889 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7890 { 7891 struct fxregs_state *fxsave; 7892 7893 vcpu_load(vcpu); 7894 7895 fxsave = &vcpu->arch.guest_fpu.state.fxsave; 7896 7897 memcpy(fxsave->st_space, fpu->fpr, 128); 7898 fxsave->cwd = fpu->fcw; 7899 fxsave->swd = fpu->fsw; 7900 fxsave->twd = fpu->ftwx; 7901 fxsave->fop = fpu->last_opcode; 7902 fxsave->rip = fpu->last_ip; 7903 fxsave->rdp = fpu->last_dp; 7904 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 7905 7906 vcpu_put(vcpu); 7907 return 0; 7908 } 7909 7910 static void fx_init(struct kvm_vcpu *vcpu) 7911 { 7912 fpstate_init(&vcpu->arch.guest_fpu.state); 7913 if (boot_cpu_has(X86_FEATURE_XSAVES)) 7914 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv = 7915 host_xcr0 | XSTATE_COMPACTION_ENABLED; 7916 7917 /* 7918 * Ensure guest xcr0 is valid for loading 7919 */ 7920 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 7921 7922 vcpu->arch.cr0 |= X86_CR0_ET; 7923 } 7924 7925 /* Swap (qemu) user FPU context for the guest FPU context. */ 7926 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 7927 { 7928 preempt_disable(); 7929 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu); 7930 /* PKRU is separately restored in kvm_x86_ops->run. */ 7931 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state, 7932 ~XFEATURE_MASK_PKRU); 7933 preempt_enable(); 7934 trace_kvm_fpu(1); 7935 } 7936 7937 /* When vcpu_run ends, restore user space FPU context. */ 7938 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 7939 { 7940 preempt_disable(); 7941 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu); 7942 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state); 7943 preempt_enable(); 7944 ++vcpu->stat.fpu_reload; 7945 trace_kvm_fpu(0); 7946 } 7947 7948 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 7949 { 7950 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask; 7951 7952 kvmclock_reset(vcpu); 7953 7954 kvm_x86_ops->vcpu_free(vcpu); 7955 free_cpumask_var(wbinvd_dirty_mask); 7956 } 7957 7958 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 7959 unsigned int id) 7960 { 7961 struct kvm_vcpu *vcpu; 7962 7963 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 7964 printk_once(KERN_WARNING 7965 "kvm: SMP vm created on host with unstable TSC; " 7966 "guest TSC will not be reliable\n"); 7967 7968 vcpu = kvm_x86_ops->vcpu_create(kvm, id); 7969 7970 return vcpu; 7971 } 7972 7973 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 7974 { 7975 kvm_vcpu_mtrr_init(vcpu); 7976 vcpu_load(vcpu); 7977 kvm_vcpu_reset(vcpu, false); 7978 kvm_mmu_setup(vcpu); 7979 vcpu_put(vcpu); 7980 return 0; 7981 } 7982 7983 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 7984 { 7985 struct msr_data msr; 7986 struct kvm *kvm = vcpu->kvm; 7987 7988 kvm_hv_vcpu_postcreate(vcpu); 7989 7990 if (mutex_lock_killable(&vcpu->mutex)) 7991 return; 7992 vcpu_load(vcpu); 7993 msr.data = 0x0; 7994 msr.index = MSR_IA32_TSC; 7995 msr.host_initiated = true; 7996 kvm_write_tsc(vcpu, &msr); 7997 vcpu_put(vcpu); 7998 mutex_unlock(&vcpu->mutex); 7999 8000 if (!kvmclock_periodic_sync) 8001 return; 8002 8003 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 8004 KVMCLOCK_SYNC_PERIOD); 8005 } 8006 8007 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 8008 { 8009 vcpu->arch.apf.msr_val = 0; 8010 8011 vcpu_load(vcpu); 8012 kvm_mmu_unload(vcpu); 8013 vcpu_put(vcpu); 8014 8015 kvm_x86_ops->vcpu_free(vcpu); 8016 } 8017 8018 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 8019 { 8020 vcpu->arch.hflags = 0; 8021 8022 vcpu->arch.smi_pending = 0; 8023 vcpu->arch.smi_count = 0; 8024 atomic_set(&vcpu->arch.nmi_queued, 0); 8025 vcpu->arch.nmi_pending = 0; 8026 vcpu->arch.nmi_injected = false; 8027 kvm_clear_interrupt_queue(vcpu); 8028 kvm_clear_exception_queue(vcpu); 8029 vcpu->arch.exception.pending = false; 8030 8031 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 8032 kvm_update_dr0123(vcpu); 8033 vcpu->arch.dr6 = DR6_INIT; 8034 kvm_update_dr6(vcpu); 8035 vcpu->arch.dr7 = DR7_FIXED_1; 8036 kvm_update_dr7(vcpu); 8037 8038 vcpu->arch.cr2 = 0; 8039 8040 kvm_make_request(KVM_REQ_EVENT, vcpu); 8041 vcpu->arch.apf.msr_val = 0; 8042 vcpu->arch.st.msr_val = 0; 8043 8044 kvmclock_reset(vcpu); 8045 8046 kvm_clear_async_pf_completion_queue(vcpu); 8047 kvm_async_pf_hash_reset(vcpu); 8048 vcpu->arch.apf.halted = false; 8049 8050 if (kvm_mpx_supported()) { 8051 void *mpx_state_buffer; 8052 8053 /* 8054 * To avoid have the INIT path from kvm_apic_has_events() that be 8055 * called with loaded FPU and does not let userspace fix the state. 8056 */ 8057 if (init_event) 8058 kvm_put_guest_fpu(vcpu); 8059 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave, 8060 XFEATURE_MASK_BNDREGS); 8061 if (mpx_state_buffer) 8062 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); 8063 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave, 8064 XFEATURE_MASK_BNDCSR); 8065 if (mpx_state_buffer) 8066 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); 8067 if (init_event) 8068 kvm_load_guest_fpu(vcpu); 8069 } 8070 8071 if (!init_event) { 8072 kvm_pmu_reset(vcpu); 8073 vcpu->arch.smbase = 0x30000; 8074 8075 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 8076 vcpu->arch.msr_misc_features_enables = 0; 8077 8078 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 8079 } 8080 8081 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 8082 vcpu->arch.regs_avail = ~0; 8083 vcpu->arch.regs_dirty = ~0; 8084 8085 vcpu->arch.ia32_xss = 0; 8086 8087 kvm_x86_ops->vcpu_reset(vcpu, init_event); 8088 } 8089 8090 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 8091 { 8092 struct kvm_segment cs; 8093 8094 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 8095 cs.selector = vector << 8; 8096 cs.base = vector << 12; 8097 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 8098 kvm_rip_write(vcpu, 0); 8099 } 8100 8101 int kvm_arch_hardware_enable(void) 8102 { 8103 struct kvm *kvm; 8104 struct kvm_vcpu *vcpu; 8105 int i; 8106 int ret; 8107 u64 local_tsc; 8108 u64 max_tsc = 0; 8109 bool stable, backwards_tsc = false; 8110 8111 kvm_shared_msr_cpu_online(); 8112 ret = kvm_x86_ops->hardware_enable(); 8113 if (ret != 0) 8114 return ret; 8115 8116 local_tsc = rdtsc(); 8117 stable = !kvm_check_tsc_unstable(); 8118 list_for_each_entry(kvm, &vm_list, vm_list) { 8119 kvm_for_each_vcpu(i, vcpu, kvm) { 8120 if (!stable && vcpu->cpu == smp_processor_id()) 8121 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 8122 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 8123 backwards_tsc = true; 8124 if (vcpu->arch.last_host_tsc > max_tsc) 8125 max_tsc = vcpu->arch.last_host_tsc; 8126 } 8127 } 8128 } 8129 8130 /* 8131 * Sometimes, even reliable TSCs go backwards. This happens on 8132 * platforms that reset TSC during suspend or hibernate actions, but 8133 * maintain synchronization. We must compensate. Fortunately, we can 8134 * detect that condition here, which happens early in CPU bringup, 8135 * before any KVM threads can be running. Unfortunately, we can't 8136 * bring the TSCs fully up to date with real time, as we aren't yet far 8137 * enough into CPU bringup that we know how much real time has actually 8138 * elapsed; our helper function, ktime_get_boot_ns() will be using boot 8139 * variables that haven't been updated yet. 8140 * 8141 * So we simply find the maximum observed TSC above, then record the 8142 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 8143 * the adjustment will be applied. Note that we accumulate 8144 * adjustments, in case multiple suspend cycles happen before some VCPU 8145 * gets a chance to run again. In the event that no KVM threads get a 8146 * chance to run, we will miss the entire elapsed period, as we'll have 8147 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 8148 * loose cycle time. This isn't too big a deal, since the loss will be 8149 * uniform across all VCPUs (not to mention the scenario is extremely 8150 * unlikely). It is possible that a second hibernate recovery happens 8151 * much faster than a first, causing the observed TSC here to be 8152 * smaller; this would require additional padding adjustment, which is 8153 * why we set last_host_tsc to the local tsc observed here. 8154 * 8155 * N.B. - this code below runs only on platforms with reliable TSC, 8156 * as that is the only way backwards_tsc is set above. Also note 8157 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 8158 * have the same delta_cyc adjustment applied if backwards_tsc 8159 * is detected. Note further, this adjustment is only done once, 8160 * as we reset last_host_tsc on all VCPUs to stop this from being 8161 * called multiple times (one for each physical CPU bringup). 8162 * 8163 * Platforms with unreliable TSCs don't have to deal with this, they 8164 * will be compensated by the logic in vcpu_load, which sets the TSC to 8165 * catchup mode. This will catchup all VCPUs to real time, but cannot 8166 * guarantee that they stay in perfect synchronization. 8167 */ 8168 if (backwards_tsc) { 8169 u64 delta_cyc = max_tsc - local_tsc; 8170 list_for_each_entry(kvm, &vm_list, vm_list) { 8171 kvm->arch.backwards_tsc_observed = true; 8172 kvm_for_each_vcpu(i, vcpu, kvm) { 8173 vcpu->arch.tsc_offset_adjustment += delta_cyc; 8174 vcpu->arch.last_host_tsc = local_tsc; 8175 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 8176 } 8177 8178 /* 8179 * We have to disable TSC offset matching.. if you were 8180 * booting a VM while issuing an S4 host suspend.... 8181 * you may have some problem. Solving this issue is 8182 * left as an exercise to the reader. 8183 */ 8184 kvm->arch.last_tsc_nsec = 0; 8185 kvm->arch.last_tsc_write = 0; 8186 } 8187 8188 } 8189 return 0; 8190 } 8191 8192 void kvm_arch_hardware_disable(void) 8193 { 8194 kvm_x86_ops->hardware_disable(); 8195 drop_user_return_notifiers(); 8196 } 8197 8198 int kvm_arch_hardware_setup(void) 8199 { 8200 int r; 8201 8202 r = kvm_x86_ops->hardware_setup(); 8203 if (r != 0) 8204 return r; 8205 8206 if (kvm_has_tsc_control) { 8207 /* 8208 * Make sure the user can only configure tsc_khz values that 8209 * fit into a signed integer. 8210 * A min value is not calculated needed because it will always 8211 * be 1 on all machines. 8212 */ 8213 u64 max = min(0x7fffffffULL, 8214 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 8215 kvm_max_guest_tsc_khz = max; 8216 8217 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 8218 } 8219 8220 kvm_init_msr_list(); 8221 return 0; 8222 } 8223 8224 void kvm_arch_hardware_unsetup(void) 8225 { 8226 kvm_x86_ops->hardware_unsetup(); 8227 } 8228 8229 void kvm_arch_check_processor_compat(void *rtn) 8230 { 8231 kvm_x86_ops->check_processor_compatibility(rtn); 8232 } 8233 8234 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 8235 { 8236 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 8237 } 8238 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 8239 8240 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 8241 { 8242 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 8243 } 8244 8245 struct static_key kvm_no_apic_vcpu __read_mostly; 8246 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); 8247 8248 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 8249 { 8250 struct page *page; 8251 int r; 8252 8253 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu); 8254 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 8255 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 8256 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8257 else 8258 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 8259 8260 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 8261 if (!page) { 8262 r = -ENOMEM; 8263 goto fail; 8264 } 8265 vcpu->arch.pio_data = page_address(page); 8266 8267 kvm_set_tsc_khz(vcpu, max_tsc_khz); 8268 8269 r = kvm_mmu_create(vcpu); 8270 if (r < 0) 8271 goto fail_free_pio_data; 8272 8273 if (irqchip_in_kernel(vcpu->kvm)) { 8274 r = kvm_create_lapic(vcpu); 8275 if (r < 0) 8276 goto fail_mmu_destroy; 8277 } else 8278 static_key_slow_inc(&kvm_no_apic_vcpu); 8279 8280 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 8281 GFP_KERNEL); 8282 if (!vcpu->arch.mce_banks) { 8283 r = -ENOMEM; 8284 goto fail_free_lapic; 8285 } 8286 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 8287 8288 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 8289 r = -ENOMEM; 8290 goto fail_free_mce_banks; 8291 } 8292 8293 fx_init(vcpu); 8294 8295 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 8296 8297 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 8298 8299 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 8300 8301 kvm_async_pf_hash_reset(vcpu); 8302 kvm_pmu_init(vcpu); 8303 8304 vcpu->arch.pending_external_vector = -1; 8305 vcpu->arch.preempted_in_kernel = false; 8306 8307 kvm_hv_vcpu_init(vcpu); 8308 8309 return 0; 8310 8311 fail_free_mce_banks: 8312 kfree(vcpu->arch.mce_banks); 8313 fail_free_lapic: 8314 kvm_free_lapic(vcpu); 8315 fail_mmu_destroy: 8316 kvm_mmu_destroy(vcpu); 8317 fail_free_pio_data: 8318 free_page((unsigned long)vcpu->arch.pio_data); 8319 fail: 8320 return r; 8321 } 8322 8323 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 8324 { 8325 int idx; 8326 8327 kvm_hv_vcpu_uninit(vcpu); 8328 kvm_pmu_destroy(vcpu); 8329 kfree(vcpu->arch.mce_banks); 8330 kvm_free_lapic(vcpu); 8331 idx = srcu_read_lock(&vcpu->kvm->srcu); 8332 kvm_mmu_destroy(vcpu); 8333 srcu_read_unlock(&vcpu->kvm->srcu, idx); 8334 free_page((unsigned long)vcpu->arch.pio_data); 8335 if (!lapic_in_kernel(vcpu)) 8336 static_key_slow_dec(&kvm_no_apic_vcpu); 8337 } 8338 8339 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 8340 { 8341 kvm_x86_ops->sched_in(vcpu, cpu); 8342 } 8343 8344 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 8345 { 8346 if (type) 8347 return -EINVAL; 8348 8349 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 8350 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 8351 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 8352 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 8353 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 8354 8355 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 8356 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 8357 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 8358 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 8359 &kvm->arch.irq_sources_bitmap); 8360 8361 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 8362 mutex_init(&kvm->arch.apic_map_lock); 8363 mutex_init(&kvm->arch.hyperv.hv_lock); 8364 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 8365 8366 kvm->arch.kvmclock_offset = -ktime_get_boot_ns(); 8367 pvclock_update_vm_gtod_copy(kvm); 8368 8369 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 8370 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 8371 8372 kvm_page_track_init(kvm); 8373 kvm_mmu_init_vm(kvm); 8374 8375 if (kvm_x86_ops->vm_init) 8376 return kvm_x86_ops->vm_init(kvm); 8377 8378 return 0; 8379 } 8380 8381 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 8382 { 8383 vcpu_load(vcpu); 8384 kvm_mmu_unload(vcpu); 8385 vcpu_put(vcpu); 8386 } 8387 8388 static void kvm_free_vcpus(struct kvm *kvm) 8389 { 8390 unsigned int i; 8391 struct kvm_vcpu *vcpu; 8392 8393 /* 8394 * Unpin any mmu pages first. 8395 */ 8396 kvm_for_each_vcpu(i, vcpu, kvm) { 8397 kvm_clear_async_pf_completion_queue(vcpu); 8398 kvm_unload_vcpu_mmu(vcpu); 8399 } 8400 kvm_for_each_vcpu(i, vcpu, kvm) 8401 kvm_arch_vcpu_free(vcpu); 8402 8403 mutex_lock(&kvm->lock); 8404 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 8405 kvm->vcpus[i] = NULL; 8406 8407 atomic_set(&kvm->online_vcpus, 0); 8408 mutex_unlock(&kvm->lock); 8409 } 8410 8411 void kvm_arch_sync_events(struct kvm *kvm) 8412 { 8413 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 8414 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 8415 kvm_free_pit(kvm); 8416 } 8417 8418 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 8419 { 8420 int i, r; 8421 unsigned long hva; 8422 struct kvm_memslots *slots = kvm_memslots(kvm); 8423 struct kvm_memory_slot *slot, old; 8424 8425 /* Called with kvm->slots_lock held. */ 8426 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 8427 return -EINVAL; 8428 8429 slot = id_to_memslot(slots, id); 8430 if (size) { 8431 if (slot->npages) 8432 return -EEXIST; 8433 8434 /* 8435 * MAP_SHARED to prevent internal slot pages from being moved 8436 * by fork()/COW. 8437 */ 8438 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 8439 MAP_SHARED | MAP_ANONYMOUS, 0); 8440 if (IS_ERR((void *)hva)) 8441 return PTR_ERR((void *)hva); 8442 } else { 8443 if (!slot->npages) 8444 return 0; 8445 8446 hva = 0; 8447 } 8448 8449 old = *slot; 8450 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 8451 struct kvm_userspace_memory_region m; 8452 8453 m.slot = id | (i << 16); 8454 m.flags = 0; 8455 m.guest_phys_addr = gpa; 8456 m.userspace_addr = hva; 8457 m.memory_size = size; 8458 r = __kvm_set_memory_region(kvm, &m); 8459 if (r < 0) 8460 return r; 8461 } 8462 8463 if (!size) { 8464 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); 8465 WARN_ON(r < 0); 8466 } 8467 8468 return 0; 8469 } 8470 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 8471 8472 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 8473 { 8474 int r; 8475 8476 mutex_lock(&kvm->slots_lock); 8477 r = __x86_set_memory_region(kvm, id, gpa, size); 8478 mutex_unlock(&kvm->slots_lock); 8479 8480 return r; 8481 } 8482 EXPORT_SYMBOL_GPL(x86_set_memory_region); 8483 8484 void kvm_arch_destroy_vm(struct kvm *kvm) 8485 { 8486 if (current->mm == kvm->mm) { 8487 /* 8488 * Free memory regions allocated on behalf of userspace, 8489 * unless the the memory map has changed due to process exit 8490 * or fd copying. 8491 */ 8492 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); 8493 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); 8494 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 8495 } 8496 if (kvm_x86_ops->vm_destroy) 8497 kvm_x86_ops->vm_destroy(kvm); 8498 kvm_pic_destroy(kvm); 8499 kvm_ioapic_destroy(kvm); 8500 kvm_free_vcpus(kvm); 8501 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 8502 kvm_mmu_uninit_vm(kvm); 8503 kvm_page_track_cleanup(kvm); 8504 } 8505 8506 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 8507 struct kvm_memory_slot *dont) 8508 { 8509 int i; 8510 8511 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8512 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 8513 kvfree(free->arch.rmap[i]); 8514 free->arch.rmap[i] = NULL; 8515 } 8516 if (i == 0) 8517 continue; 8518 8519 if (!dont || free->arch.lpage_info[i - 1] != 8520 dont->arch.lpage_info[i - 1]) { 8521 kvfree(free->arch.lpage_info[i - 1]); 8522 free->arch.lpage_info[i - 1] = NULL; 8523 } 8524 } 8525 8526 kvm_page_track_free_memslot(free, dont); 8527 } 8528 8529 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 8530 unsigned long npages) 8531 { 8532 int i; 8533 8534 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8535 struct kvm_lpage_info *linfo; 8536 unsigned long ugfn; 8537 int lpages; 8538 int level = i + 1; 8539 8540 lpages = gfn_to_index(slot->base_gfn + npages - 1, 8541 slot->base_gfn, level) + 1; 8542 8543 slot->arch.rmap[i] = 8544 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL); 8545 if (!slot->arch.rmap[i]) 8546 goto out_free; 8547 if (i == 0) 8548 continue; 8549 8550 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL); 8551 if (!linfo) 8552 goto out_free; 8553 8554 slot->arch.lpage_info[i - 1] = linfo; 8555 8556 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 8557 linfo[0].disallow_lpage = 1; 8558 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 8559 linfo[lpages - 1].disallow_lpage = 1; 8560 ugfn = slot->userspace_addr >> PAGE_SHIFT; 8561 /* 8562 * If the gfn and userspace address are not aligned wrt each 8563 * other, or if explicitly asked to, disable large page 8564 * support for this slot 8565 */ 8566 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 8567 !kvm_largepages_enabled()) { 8568 unsigned long j; 8569 8570 for (j = 0; j < lpages; ++j) 8571 linfo[j].disallow_lpage = 1; 8572 } 8573 } 8574 8575 if (kvm_page_track_create_memslot(slot, npages)) 8576 goto out_free; 8577 8578 return 0; 8579 8580 out_free: 8581 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8582 kvfree(slot->arch.rmap[i]); 8583 slot->arch.rmap[i] = NULL; 8584 if (i == 0) 8585 continue; 8586 8587 kvfree(slot->arch.lpage_info[i - 1]); 8588 slot->arch.lpage_info[i - 1] = NULL; 8589 } 8590 return -ENOMEM; 8591 } 8592 8593 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) 8594 { 8595 /* 8596 * memslots->generation has been incremented. 8597 * mmio generation may have reached its maximum value. 8598 */ 8599 kvm_mmu_invalidate_mmio_sptes(kvm, slots); 8600 } 8601 8602 int kvm_arch_prepare_memory_region(struct kvm *kvm, 8603 struct kvm_memory_slot *memslot, 8604 const struct kvm_userspace_memory_region *mem, 8605 enum kvm_mr_change change) 8606 { 8607 return 0; 8608 } 8609 8610 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 8611 struct kvm_memory_slot *new) 8612 { 8613 /* Still write protect RO slot */ 8614 if (new->flags & KVM_MEM_READONLY) { 8615 kvm_mmu_slot_remove_write_access(kvm, new); 8616 return; 8617 } 8618 8619 /* 8620 * Call kvm_x86_ops dirty logging hooks when they are valid. 8621 * 8622 * kvm_x86_ops->slot_disable_log_dirty is called when: 8623 * 8624 * - KVM_MR_CREATE with dirty logging is disabled 8625 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 8626 * 8627 * The reason is, in case of PML, we need to set D-bit for any slots 8628 * with dirty logging disabled in order to eliminate unnecessary GPA 8629 * logging in PML buffer (and potential PML buffer full VMEXT). This 8630 * guarantees leaving PML enabled during guest's lifetime won't have 8631 * any additonal overhead from PML when guest is running with dirty 8632 * logging disabled for memory slots. 8633 * 8634 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 8635 * to dirty logging mode. 8636 * 8637 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 8638 * 8639 * In case of write protect: 8640 * 8641 * Write protect all pages for dirty logging. 8642 * 8643 * All the sptes including the large sptes which point to this 8644 * slot are set to readonly. We can not create any new large 8645 * spte on this slot until the end of the logging. 8646 * 8647 * See the comments in fast_page_fault(). 8648 */ 8649 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 8650 if (kvm_x86_ops->slot_enable_log_dirty) 8651 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 8652 else 8653 kvm_mmu_slot_remove_write_access(kvm, new); 8654 } else { 8655 if (kvm_x86_ops->slot_disable_log_dirty) 8656 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 8657 } 8658 } 8659 8660 void kvm_arch_commit_memory_region(struct kvm *kvm, 8661 const struct kvm_userspace_memory_region *mem, 8662 const struct kvm_memory_slot *old, 8663 const struct kvm_memory_slot *new, 8664 enum kvm_mr_change change) 8665 { 8666 int nr_mmu_pages = 0; 8667 8668 if (!kvm->arch.n_requested_mmu_pages) 8669 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 8670 8671 if (nr_mmu_pages) 8672 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 8673 8674 /* 8675 * Dirty logging tracks sptes in 4k granularity, meaning that large 8676 * sptes have to be split. If live migration is successful, the guest 8677 * in the source machine will be destroyed and large sptes will be 8678 * created in the destination. However, if the guest continues to run 8679 * in the source machine (for example if live migration fails), small 8680 * sptes will remain around and cause bad performance. 8681 * 8682 * Scan sptes if dirty logging has been stopped, dropping those 8683 * which can be collapsed into a single large-page spte. Later 8684 * page faults will create the large-page sptes. 8685 */ 8686 if ((change != KVM_MR_DELETE) && 8687 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 8688 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 8689 kvm_mmu_zap_collapsible_sptes(kvm, new); 8690 8691 /* 8692 * Set up write protection and/or dirty logging for the new slot. 8693 * 8694 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 8695 * been zapped so no dirty logging staff is needed for old slot. For 8696 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 8697 * new and it's also covered when dealing with the new slot. 8698 * 8699 * FIXME: const-ify all uses of struct kvm_memory_slot. 8700 */ 8701 if (change != KVM_MR_DELETE) 8702 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 8703 } 8704 8705 void kvm_arch_flush_shadow_all(struct kvm *kvm) 8706 { 8707 kvm_mmu_invalidate_zap_all_pages(kvm); 8708 } 8709 8710 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 8711 struct kvm_memory_slot *slot) 8712 { 8713 kvm_page_track_flush_slot(kvm, slot); 8714 } 8715 8716 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 8717 { 8718 if (!list_empty_careful(&vcpu->async_pf.done)) 8719 return true; 8720 8721 if (kvm_apic_has_events(vcpu)) 8722 return true; 8723 8724 if (vcpu->arch.pv.pv_unhalted) 8725 return true; 8726 8727 if (vcpu->arch.exception.pending) 8728 return true; 8729 8730 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 8731 (vcpu->arch.nmi_pending && 8732 kvm_x86_ops->nmi_allowed(vcpu))) 8733 return true; 8734 8735 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 8736 (vcpu->arch.smi_pending && !is_smm(vcpu))) 8737 return true; 8738 8739 if (kvm_arch_interrupt_allowed(vcpu) && 8740 kvm_cpu_has_interrupt(vcpu)) 8741 return true; 8742 8743 if (kvm_hv_has_stimer_pending(vcpu)) 8744 return true; 8745 8746 return false; 8747 } 8748 8749 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 8750 { 8751 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 8752 } 8753 8754 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 8755 { 8756 return vcpu->arch.preempted_in_kernel; 8757 } 8758 8759 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 8760 { 8761 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 8762 } 8763 8764 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 8765 { 8766 return kvm_x86_ops->interrupt_allowed(vcpu); 8767 } 8768 8769 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 8770 { 8771 if (is_64_bit_mode(vcpu)) 8772 return kvm_rip_read(vcpu); 8773 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 8774 kvm_rip_read(vcpu)); 8775 } 8776 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 8777 8778 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 8779 { 8780 return kvm_get_linear_rip(vcpu) == linear_rip; 8781 } 8782 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 8783 8784 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 8785 { 8786 unsigned long rflags; 8787 8788 rflags = kvm_x86_ops->get_rflags(vcpu); 8789 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 8790 rflags &= ~X86_EFLAGS_TF; 8791 return rflags; 8792 } 8793 EXPORT_SYMBOL_GPL(kvm_get_rflags); 8794 8795 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8796 { 8797 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 8798 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 8799 rflags |= X86_EFLAGS_TF; 8800 kvm_x86_ops->set_rflags(vcpu, rflags); 8801 } 8802 8803 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8804 { 8805 __kvm_set_rflags(vcpu, rflags); 8806 kvm_make_request(KVM_REQ_EVENT, vcpu); 8807 } 8808 EXPORT_SYMBOL_GPL(kvm_set_rflags); 8809 8810 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 8811 { 8812 int r; 8813 8814 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 8815 work->wakeup_all) 8816 return; 8817 8818 r = kvm_mmu_reload(vcpu); 8819 if (unlikely(r)) 8820 return; 8821 8822 if (!vcpu->arch.mmu.direct_map && 8823 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 8824 return; 8825 8826 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 8827 } 8828 8829 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 8830 { 8831 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 8832 } 8833 8834 static inline u32 kvm_async_pf_next_probe(u32 key) 8835 { 8836 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 8837 } 8838 8839 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8840 { 8841 u32 key = kvm_async_pf_hash_fn(gfn); 8842 8843 while (vcpu->arch.apf.gfns[key] != ~0) 8844 key = kvm_async_pf_next_probe(key); 8845 8846 vcpu->arch.apf.gfns[key] = gfn; 8847 } 8848 8849 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 8850 { 8851 int i; 8852 u32 key = kvm_async_pf_hash_fn(gfn); 8853 8854 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 8855 (vcpu->arch.apf.gfns[key] != gfn && 8856 vcpu->arch.apf.gfns[key] != ~0); i++) 8857 key = kvm_async_pf_next_probe(key); 8858 8859 return key; 8860 } 8861 8862 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8863 { 8864 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 8865 } 8866 8867 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8868 { 8869 u32 i, j, k; 8870 8871 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 8872 while (true) { 8873 vcpu->arch.apf.gfns[i] = ~0; 8874 do { 8875 j = kvm_async_pf_next_probe(j); 8876 if (vcpu->arch.apf.gfns[j] == ~0) 8877 return; 8878 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 8879 /* 8880 * k lies cyclically in ]i,j] 8881 * | i.k.j | 8882 * |....j i.k.| or |.k..j i...| 8883 */ 8884 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 8885 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 8886 i = j; 8887 } 8888 } 8889 8890 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 8891 { 8892 8893 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 8894 sizeof(val)); 8895 } 8896 8897 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val) 8898 { 8899 8900 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val, 8901 sizeof(u32)); 8902 } 8903 8904 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 8905 struct kvm_async_pf *work) 8906 { 8907 struct x86_exception fault; 8908 8909 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 8910 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 8911 8912 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 8913 (vcpu->arch.apf.send_user_only && 8914 kvm_x86_ops->get_cpl(vcpu) == 0)) 8915 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 8916 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 8917 fault.vector = PF_VECTOR; 8918 fault.error_code_valid = true; 8919 fault.error_code = 0; 8920 fault.nested_page_fault = false; 8921 fault.address = work->arch.token; 8922 fault.async_page_fault = true; 8923 kvm_inject_page_fault(vcpu, &fault); 8924 } 8925 } 8926 8927 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 8928 struct kvm_async_pf *work) 8929 { 8930 struct x86_exception fault; 8931 u32 val; 8932 8933 if (work->wakeup_all) 8934 work->arch.token = ~0; /* broadcast wakeup */ 8935 else 8936 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 8937 trace_kvm_async_pf_ready(work->arch.token, work->gva); 8938 8939 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED && 8940 !apf_get_user(vcpu, &val)) { 8941 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT && 8942 vcpu->arch.exception.pending && 8943 vcpu->arch.exception.nr == PF_VECTOR && 8944 !apf_put_user(vcpu, 0)) { 8945 vcpu->arch.exception.injected = false; 8946 vcpu->arch.exception.pending = false; 8947 vcpu->arch.exception.nr = 0; 8948 vcpu->arch.exception.has_error_code = false; 8949 vcpu->arch.exception.error_code = 0; 8950 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 8951 fault.vector = PF_VECTOR; 8952 fault.error_code_valid = true; 8953 fault.error_code = 0; 8954 fault.nested_page_fault = false; 8955 fault.address = work->arch.token; 8956 fault.async_page_fault = true; 8957 kvm_inject_page_fault(vcpu, &fault); 8958 } 8959 } 8960 vcpu->arch.apf.halted = false; 8961 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8962 } 8963 8964 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 8965 { 8966 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 8967 return true; 8968 else 8969 return kvm_can_do_async_pf(vcpu); 8970 } 8971 8972 void kvm_arch_start_assignment(struct kvm *kvm) 8973 { 8974 atomic_inc(&kvm->arch.assigned_device_count); 8975 } 8976 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 8977 8978 void kvm_arch_end_assignment(struct kvm *kvm) 8979 { 8980 atomic_dec(&kvm->arch.assigned_device_count); 8981 } 8982 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 8983 8984 bool kvm_arch_has_assigned_device(struct kvm *kvm) 8985 { 8986 return atomic_read(&kvm->arch.assigned_device_count); 8987 } 8988 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 8989 8990 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 8991 { 8992 atomic_inc(&kvm->arch.noncoherent_dma_count); 8993 } 8994 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 8995 8996 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 8997 { 8998 atomic_dec(&kvm->arch.noncoherent_dma_count); 8999 } 9000 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 9001 9002 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 9003 { 9004 return atomic_read(&kvm->arch.noncoherent_dma_count); 9005 } 9006 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 9007 9008 bool kvm_arch_has_irq_bypass(void) 9009 { 9010 return kvm_x86_ops->update_pi_irte != NULL; 9011 } 9012 9013 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 9014 struct irq_bypass_producer *prod) 9015 { 9016 struct kvm_kernel_irqfd *irqfd = 9017 container_of(cons, struct kvm_kernel_irqfd, consumer); 9018 9019 irqfd->producer = prod; 9020 9021 return kvm_x86_ops->update_pi_irte(irqfd->kvm, 9022 prod->irq, irqfd->gsi, 1); 9023 } 9024 9025 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 9026 struct irq_bypass_producer *prod) 9027 { 9028 int ret; 9029 struct kvm_kernel_irqfd *irqfd = 9030 container_of(cons, struct kvm_kernel_irqfd, consumer); 9031 9032 WARN_ON(irqfd->producer != prod); 9033 irqfd->producer = NULL; 9034 9035 /* 9036 * When producer of consumer is unregistered, we change back to 9037 * remapped mode, so we can re-use the current implementation 9038 * when the irq is masked/disabled or the consumer side (KVM 9039 * int this case doesn't want to receive the interrupts. 9040 */ 9041 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 9042 if (ret) 9043 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 9044 " fails: %d\n", irqfd->consumer.token, ret); 9045 } 9046 9047 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 9048 uint32_t guest_irq, bool set) 9049 { 9050 if (!kvm_x86_ops->update_pi_irte) 9051 return -EINVAL; 9052 9053 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); 9054 } 9055 9056 bool kvm_vector_hashing_enabled(void) 9057 { 9058 return vector_hashing; 9059 } 9060 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled); 9061 9062 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 9063 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 9064 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 9065 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 9066 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 9067 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 9068 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 9069 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 9070 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 9071 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 9072 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 9073 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 9074 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 9075 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 9076 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 9077 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 9078 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 9079 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 9080 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 9081