1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "assigned-dev.h" 31 #include "pmu.h" 32 #include "hyperv.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/module.h> 40 #include <linux/mman.h> 41 #include <linux/highmem.h> 42 #include <linux/iommu.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/cpufreq.h> 45 #include <linux/user-return-notifier.h> 46 #include <linux/srcu.h> 47 #include <linux/slab.h> 48 #include <linux/perf_event.h> 49 #include <linux/uaccess.h> 50 #include <linux/hash.h> 51 #include <linux/pci.h> 52 #include <linux/timekeeper_internal.h> 53 #include <linux/pvclock_gtod.h> 54 #include <linux/kvm_irqfd.h> 55 #include <linux/irqbypass.h> 56 #include <trace/events/kvm.h> 57 58 #define CREATE_TRACE_POINTS 59 #include "trace.h" 60 61 #include <asm/debugreg.h> 62 #include <asm/msr.h> 63 #include <asm/desc.h> 64 #include <asm/mce.h> 65 #include <linux/kernel_stat.h> 66 #include <asm/fpu/internal.h> /* Ugh! */ 67 #include <asm/pvclock.h> 68 #include <asm/div64.h> 69 #include <asm/irq_remapping.h> 70 71 #define MAX_IO_MSRS 256 72 #define KVM_MAX_MCE_BANKS 32 73 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) 74 75 #define emul_to_vcpu(ctxt) \ 76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 77 78 /* EFER defaults: 79 * - enable syscall per default because its emulated by KVM 80 * - enable LME and LMA per default on 64 bit KVM 81 */ 82 #ifdef CONFIG_X86_64 83 static 84 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 85 #else 86 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 87 #endif 88 89 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 90 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 91 92 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 93 static void process_nmi(struct kvm_vcpu *vcpu); 94 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 95 96 struct kvm_x86_ops *kvm_x86_ops __read_mostly; 97 EXPORT_SYMBOL_GPL(kvm_x86_ops); 98 99 static bool __read_mostly ignore_msrs = 0; 100 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 101 102 unsigned int min_timer_period_us = 500; 103 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 104 105 static bool __read_mostly kvmclock_periodic_sync = true; 106 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 107 108 bool __read_mostly kvm_has_tsc_control; 109 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 110 u32 __read_mostly kvm_max_guest_tsc_khz; 111 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 112 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 113 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 114 u64 __read_mostly kvm_max_tsc_scaling_ratio; 115 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 116 static u64 __read_mostly kvm_default_tsc_scaling_ratio; 117 118 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 119 static u32 __read_mostly tsc_tolerance_ppm = 250; 120 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 121 122 /* lapic timer advance (tscdeadline mode only) in nanoseconds */ 123 unsigned int __read_mostly lapic_timer_advance_ns = 0; 124 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 125 126 static bool __read_mostly vector_hashing = true; 127 module_param(vector_hashing, bool, S_IRUGO); 128 129 static bool __read_mostly backwards_tsc_observed = false; 130 131 #define KVM_NR_SHARED_MSRS 16 132 133 struct kvm_shared_msrs_global { 134 int nr; 135 u32 msrs[KVM_NR_SHARED_MSRS]; 136 }; 137 138 struct kvm_shared_msrs { 139 struct user_return_notifier urn; 140 bool registered; 141 struct kvm_shared_msr_values { 142 u64 host; 143 u64 curr; 144 } values[KVM_NR_SHARED_MSRS]; 145 }; 146 147 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 148 static struct kvm_shared_msrs __percpu *shared_msrs; 149 150 struct kvm_stats_debugfs_item debugfs_entries[] = { 151 { "pf_fixed", VCPU_STAT(pf_fixed) }, 152 { "pf_guest", VCPU_STAT(pf_guest) }, 153 { "tlb_flush", VCPU_STAT(tlb_flush) }, 154 { "invlpg", VCPU_STAT(invlpg) }, 155 { "exits", VCPU_STAT(exits) }, 156 { "io_exits", VCPU_STAT(io_exits) }, 157 { "mmio_exits", VCPU_STAT(mmio_exits) }, 158 { "signal_exits", VCPU_STAT(signal_exits) }, 159 { "irq_window", VCPU_STAT(irq_window_exits) }, 160 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 161 { "halt_exits", VCPU_STAT(halt_exits) }, 162 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 163 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 164 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, 165 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 166 { "hypercalls", VCPU_STAT(hypercalls) }, 167 { "request_irq", VCPU_STAT(request_irq_exits) }, 168 { "irq_exits", VCPU_STAT(irq_exits) }, 169 { "host_state_reload", VCPU_STAT(host_state_reload) }, 170 { "efer_reload", VCPU_STAT(efer_reload) }, 171 { "fpu_reload", VCPU_STAT(fpu_reload) }, 172 { "insn_emulation", VCPU_STAT(insn_emulation) }, 173 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 174 { "irq_injections", VCPU_STAT(irq_injections) }, 175 { "nmi_injections", VCPU_STAT(nmi_injections) }, 176 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 177 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 178 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 179 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 180 { "mmu_flooded", VM_STAT(mmu_flooded) }, 181 { "mmu_recycled", VM_STAT(mmu_recycled) }, 182 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 183 { "mmu_unsync", VM_STAT(mmu_unsync) }, 184 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 185 { "largepages", VM_STAT(lpages) }, 186 { NULL } 187 }; 188 189 u64 __read_mostly host_xcr0; 190 191 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 192 193 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 194 { 195 int i; 196 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 197 vcpu->arch.apf.gfns[i] = ~0; 198 } 199 200 static void kvm_on_user_return(struct user_return_notifier *urn) 201 { 202 unsigned slot; 203 struct kvm_shared_msrs *locals 204 = container_of(urn, struct kvm_shared_msrs, urn); 205 struct kvm_shared_msr_values *values; 206 207 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 208 values = &locals->values[slot]; 209 if (values->host != values->curr) { 210 wrmsrl(shared_msrs_global.msrs[slot], values->host); 211 values->curr = values->host; 212 } 213 } 214 locals->registered = false; 215 user_return_notifier_unregister(urn); 216 } 217 218 static void shared_msr_update(unsigned slot, u32 msr) 219 { 220 u64 value; 221 unsigned int cpu = smp_processor_id(); 222 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 223 224 /* only read, and nobody should modify it at this time, 225 * so don't need lock */ 226 if (slot >= shared_msrs_global.nr) { 227 printk(KERN_ERR "kvm: invalid MSR slot!"); 228 return; 229 } 230 rdmsrl_safe(msr, &value); 231 smsr->values[slot].host = value; 232 smsr->values[slot].curr = value; 233 } 234 235 void kvm_define_shared_msr(unsigned slot, u32 msr) 236 { 237 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 238 shared_msrs_global.msrs[slot] = msr; 239 if (slot >= shared_msrs_global.nr) 240 shared_msrs_global.nr = slot + 1; 241 } 242 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 243 244 static void kvm_shared_msr_cpu_online(void) 245 { 246 unsigned i; 247 248 for (i = 0; i < shared_msrs_global.nr; ++i) 249 shared_msr_update(i, shared_msrs_global.msrs[i]); 250 } 251 252 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 253 { 254 unsigned int cpu = smp_processor_id(); 255 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 256 int err; 257 258 if (((value ^ smsr->values[slot].curr) & mask) == 0) 259 return 0; 260 smsr->values[slot].curr = value; 261 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 262 if (err) 263 return 1; 264 265 if (!smsr->registered) { 266 smsr->urn.on_user_return = kvm_on_user_return; 267 user_return_notifier_register(&smsr->urn); 268 smsr->registered = true; 269 } 270 return 0; 271 } 272 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 273 274 static void drop_user_return_notifiers(void) 275 { 276 unsigned int cpu = smp_processor_id(); 277 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 278 279 if (smsr->registered) 280 kvm_on_user_return(&smsr->urn); 281 } 282 283 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 284 { 285 return vcpu->arch.apic_base; 286 } 287 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 288 289 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 290 { 291 u64 old_state = vcpu->arch.apic_base & 292 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 293 u64 new_state = msr_info->data & 294 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 295 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 296 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); 297 298 if (!msr_info->host_initiated && 299 ((msr_info->data & reserved_bits) != 0 || 300 new_state == X2APIC_ENABLE || 301 (new_state == MSR_IA32_APICBASE_ENABLE && 302 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 303 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 304 old_state == 0))) 305 return 1; 306 307 kvm_lapic_set_base(vcpu, msr_info->data); 308 return 0; 309 } 310 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 311 312 asmlinkage __visible void kvm_spurious_fault(void) 313 { 314 /* Fault while not rebooting. We want the trace. */ 315 BUG(); 316 } 317 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 318 319 #define EXCPT_BENIGN 0 320 #define EXCPT_CONTRIBUTORY 1 321 #define EXCPT_PF 2 322 323 static int exception_class(int vector) 324 { 325 switch (vector) { 326 case PF_VECTOR: 327 return EXCPT_PF; 328 case DE_VECTOR: 329 case TS_VECTOR: 330 case NP_VECTOR: 331 case SS_VECTOR: 332 case GP_VECTOR: 333 return EXCPT_CONTRIBUTORY; 334 default: 335 break; 336 } 337 return EXCPT_BENIGN; 338 } 339 340 #define EXCPT_FAULT 0 341 #define EXCPT_TRAP 1 342 #define EXCPT_ABORT 2 343 #define EXCPT_INTERRUPT 3 344 345 static int exception_type(int vector) 346 { 347 unsigned int mask; 348 349 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 350 return EXCPT_INTERRUPT; 351 352 mask = 1 << vector; 353 354 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 355 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 356 return EXCPT_TRAP; 357 358 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 359 return EXCPT_ABORT; 360 361 /* Reserved exceptions will result in fault */ 362 return EXCPT_FAULT; 363 } 364 365 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 366 unsigned nr, bool has_error, u32 error_code, 367 bool reinject) 368 { 369 u32 prev_nr; 370 int class1, class2; 371 372 kvm_make_request(KVM_REQ_EVENT, vcpu); 373 374 if (!vcpu->arch.exception.pending) { 375 queue: 376 if (has_error && !is_protmode(vcpu)) 377 has_error = false; 378 vcpu->arch.exception.pending = true; 379 vcpu->arch.exception.has_error_code = has_error; 380 vcpu->arch.exception.nr = nr; 381 vcpu->arch.exception.error_code = error_code; 382 vcpu->arch.exception.reinject = reinject; 383 return; 384 } 385 386 /* to check exception */ 387 prev_nr = vcpu->arch.exception.nr; 388 if (prev_nr == DF_VECTOR) { 389 /* triple fault -> shutdown */ 390 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 391 return; 392 } 393 class1 = exception_class(prev_nr); 394 class2 = exception_class(nr); 395 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 396 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 397 /* generate double fault per SDM Table 5-5 */ 398 vcpu->arch.exception.pending = true; 399 vcpu->arch.exception.has_error_code = true; 400 vcpu->arch.exception.nr = DF_VECTOR; 401 vcpu->arch.exception.error_code = 0; 402 } else 403 /* replace previous exception with a new one in a hope 404 that instruction re-execution will regenerate lost 405 exception */ 406 goto queue; 407 } 408 409 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 410 { 411 kvm_multiple_exception(vcpu, nr, false, 0, false); 412 } 413 EXPORT_SYMBOL_GPL(kvm_queue_exception); 414 415 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 416 { 417 kvm_multiple_exception(vcpu, nr, false, 0, true); 418 } 419 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 420 421 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 422 { 423 if (err) 424 kvm_inject_gp(vcpu, 0); 425 else 426 kvm_x86_ops->skip_emulated_instruction(vcpu); 427 } 428 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 429 430 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 431 { 432 ++vcpu->stat.pf_guest; 433 vcpu->arch.cr2 = fault->address; 434 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 435 } 436 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 437 438 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 439 { 440 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 441 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 442 else 443 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 444 445 return fault->nested_page_fault; 446 } 447 448 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 449 { 450 atomic_inc(&vcpu->arch.nmi_queued); 451 kvm_make_request(KVM_REQ_NMI, vcpu); 452 } 453 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 454 455 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 456 { 457 kvm_multiple_exception(vcpu, nr, true, error_code, false); 458 } 459 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 460 461 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 462 { 463 kvm_multiple_exception(vcpu, nr, true, error_code, true); 464 } 465 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 466 467 /* 468 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 469 * a #GP and return false. 470 */ 471 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 472 { 473 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 474 return true; 475 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 476 return false; 477 } 478 EXPORT_SYMBOL_GPL(kvm_require_cpl); 479 480 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 481 { 482 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 483 return true; 484 485 kvm_queue_exception(vcpu, UD_VECTOR); 486 return false; 487 } 488 EXPORT_SYMBOL_GPL(kvm_require_dr); 489 490 /* 491 * This function will be used to read from the physical memory of the currently 492 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 493 * can read from guest physical or from the guest's guest physical memory. 494 */ 495 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 496 gfn_t ngfn, void *data, int offset, int len, 497 u32 access) 498 { 499 struct x86_exception exception; 500 gfn_t real_gfn; 501 gpa_t ngpa; 502 503 ngpa = gfn_to_gpa(ngfn); 504 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 505 if (real_gfn == UNMAPPED_GVA) 506 return -EFAULT; 507 508 real_gfn = gpa_to_gfn(real_gfn); 509 510 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 511 } 512 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 513 514 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 515 void *data, int offset, int len, u32 access) 516 { 517 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 518 data, offset, len, access); 519 } 520 521 /* 522 * Load the pae pdptrs. Return true is they are all valid. 523 */ 524 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 525 { 526 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 527 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 528 int i; 529 int ret; 530 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 531 532 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 533 offset * sizeof(u64), sizeof(pdpte), 534 PFERR_USER_MASK|PFERR_WRITE_MASK); 535 if (ret < 0) { 536 ret = 0; 537 goto out; 538 } 539 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 540 if (is_present_gpte(pdpte[i]) && 541 (pdpte[i] & 542 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) { 543 ret = 0; 544 goto out; 545 } 546 } 547 ret = 1; 548 549 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 550 __set_bit(VCPU_EXREG_PDPTR, 551 (unsigned long *)&vcpu->arch.regs_avail); 552 __set_bit(VCPU_EXREG_PDPTR, 553 (unsigned long *)&vcpu->arch.regs_dirty); 554 out: 555 556 return ret; 557 } 558 EXPORT_SYMBOL_GPL(load_pdptrs); 559 560 static bool pdptrs_changed(struct kvm_vcpu *vcpu) 561 { 562 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 563 bool changed = true; 564 int offset; 565 gfn_t gfn; 566 int r; 567 568 if (is_long_mode(vcpu) || !is_pae(vcpu)) 569 return false; 570 571 if (!test_bit(VCPU_EXREG_PDPTR, 572 (unsigned long *)&vcpu->arch.regs_avail)) 573 return true; 574 575 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; 576 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); 577 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 578 PFERR_USER_MASK | PFERR_WRITE_MASK); 579 if (r < 0) 580 goto out; 581 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 582 out: 583 584 return changed; 585 } 586 587 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 588 { 589 unsigned long old_cr0 = kvm_read_cr0(vcpu); 590 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 591 592 cr0 |= X86_CR0_ET; 593 594 #ifdef CONFIG_X86_64 595 if (cr0 & 0xffffffff00000000UL) 596 return 1; 597 #endif 598 599 cr0 &= ~CR0_RESERVED_BITS; 600 601 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 602 return 1; 603 604 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 605 return 1; 606 607 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 608 #ifdef CONFIG_X86_64 609 if ((vcpu->arch.efer & EFER_LME)) { 610 int cs_db, cs_l; 611 612 if (!is_pae(vcpu)) 613 return 1; 614 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 615 if (cs_l) 616 return 1; 617 } else 618 #endif 619 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 620 kvm_read_cr3(vcpu))) 621 return 1; 622 } 623 624 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 625 return 1; 626 627 kvm_x86_ops->set_cr0(vcpu, cr0); 628 629 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 630 kvm_clear_async_pf_completion_queue(vcpu); 631 kvm_async_pf_hash_reset(vcpu); 632 } 633 634 if ((cr0 ^ old_cr0) & update_bits) 635 kvm_mmu_reset_context(vcpu); 636 637 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 638 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 639 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 640 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 641 642 return 0; 643 } 644 EXPORT_SYMBOL_GPL(kvm_set_cr0); 645 646 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 647 { 648 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 649 } 650 EXPORT_SYMBOL_GPL(kvm_lmsw); 651 652 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 653 { 654 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 655 !vcpu->guest_xcr0_loaded) { 656 /* kvm_set_xcr() also depends on this */ 657 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 658 vcpu->guest_xcr0_loaded = 1; 659 } 660 } 661 662 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 663 { 664 if (vcpu->guest_xcr0_loaded) { 665 if (vcpu->arch.xcr0 != host_xcr0) 666 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 667 vcpu->guest_xcr0_loaded = 0; 668 } 669 } 670 671 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 672 { 673 u64 xcr0 = xcr; 674 u64 old_xcr0 = vcpu->arch.xcr0; 675 u64 valid_bits; 676 677 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 678 if (index != XCR_XFEATURE_ENABLED_MASK) 679 return 1; 680 if (!(xcr0 & XFEATURE_MASK_FP)) 681 return 1; 682 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 683 return 1; 684 685 /* 686 * Do not allow the guest to set bits that we do not support 687 * saving. However, xcr0 bit 0 is always set, even if the 688 * emulated CPU does not support XSAVE (see fx_init). 689 */ 690 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 691 if (xcr0 & ~valid_bits) 692 return 1; 693 694 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 695 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 696 return 1; 697 698 if (xcr0 & XFEATURE_MASK_AVX512) { 699 if (!(xcr0 & XFEATURE_MASK_YMM)) 700 return 1; 701 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 702 return 1; 703 } 704 vcpu->arch.xcr0 = xcr0; 705 706 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 707 kvm_update_cpuid(vcpu); 708 return 0; 709 } 710 711 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 712 { 713 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 714 __kvm_set_xcr(vcpu, index, xcr)) { 715 kvm_inject_gp(vcpu, 0); 716 return 1; 717 } 718 return 0; 719 } 720 EXPORT_SYMBOL_GPL(kvm_set_xcr); 721 722 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 723 { 724 unsigned long old_cr4 = kvm_read_cr4(vcpu); 725 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 726 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 727 728 if (cr4 & CR4_RESERVED_BITS) 729 return 1; 730 731 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) 732 return 1; 733 734 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) 735 return 1; 736 737 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) 738 return 1; 739 740 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) 741 return 1; 742 743 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE)) 744 return 1; 745 746 if (is_long_mode(vcpu)) { 747 if (!(cr4 & X86_CR4_PAE)) 748 return 1; 749 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 750 && ((cr4 ^ old_cr4) & pdptr_bits) 751 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 752 kvm_read_cr3(vcpu))) 753 return 1; 754 755 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 756 if (!guest_cpuid_has_pcid(vcpu)) 757 return 1; 758 759 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 760 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 761 return 1; 762 } 763 764 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 765 return 1; 766 767 if (((cr4 ^ old_cr4) & pdptr_bits) || 768 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 769 kvm_mmu_reset_context(vcpu); 770 771 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 772 kvm_update_cpuid(vcpu); 773 774 return 0; 775 } 776 EXPORT_SYMBOL_GPL(kvm_set_cr4); 777 778 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 779 { 780 #ifdef CONFIG_X86_64 781 cr3 &= ~CR3_PCID_INVD; 782 #endif 783 784 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 785 kvm_mmu_sync_roots(vcpu); 786 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 787 return 0; 788 } 789 790 if (is_long_mode(vcpu)) { 791 if (cr3 & CR3_L_MODE_RESERVED_BITS) 792 return 1; 793 } else if (is_pae(vcpu) && is_paging(vcpu) && 794 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 795 return 1; 796 797 vcpu->arch.cr3 = cr3; 798 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 799 kvm_mmu_new_cr3(vcpu); 800 return 0; 801 } 802 EXPORT_SYMBOL_GPL(kvm_set_cr3); 803 804 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 805 { 806 if (cr8 & CR8_RESERVED_BITS) 807 return 1; 808 if (lapic_in_kernel(vcpu)) 809 kvm_lapic_set_tpr(vcpu, cr8); 810 else 811 vcpu->arch.cr8 = cr8; 812 return 0; 813 } 814 EXPORT_SYMBOL_GPL(kvm_set_cr8); 815 816 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 817 { 818 if (lapic_in_kernel(vcpu)) 819 return kvm_lapic_get_cr8(vcpu); 820 else 821 return vcpu->arch.cr8; 822 } 823 EXPORT_SYMBOL_GPL(kvm_get_cr8); 824 825 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 826 { 827 int i; 828 829 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 830 for (i = 0; i < KVM_NR_DB_REGS; i++) 831 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 832 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 833 } 834 } 835 836 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 837 { 838 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 839 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 840 } 841 842 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 843 { 844 unsigned long dr7; 845 846 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 847 dr7 = vcpu->arch.guest_debug_dr7; 848 else 849 dr7 = vcpu->arch.dr7; 850 kvm_x86_ops->set_dr7(vcpu, dr7); 851 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 852 if (dr7 & DR7_BP_EN_MASK) 853 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 854 } 855 856 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 857 { 858 u64 fixed = DR6_FIXED_1; 859 860 if (!guest_cpuid_has_rtm(vcpu)) 861 fixed |= DR6_RTM; 862 return fixed; 863 } 864 865 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 866 { 867 switch (dr) { 868 case 0 ... 3: 869 vcpu->arch.db[dr] = val; 870 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 871 vcpu->arch.eff_db[dr] = val; 872 break; 873 case 4: 874 /* fall through */ 875 case 6: 876 if (val & 0xffffffff00000000ULL) 877 return -1; /* #GP */ 878 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 879 kvm_update_dr6(vcpu); 880 break; 881 case 5: 882 /* fall through */ 883 default: /* 7 */ 884 if (val & 0xffffffff00000000ULL) 885 return -1; /* #GP */ 886 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 887 kvm_update_dr7(vcpu); 888 break; 889 } 890 891 return 0; 892 } 893 894 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 895 { 896 if (__kvm_set_dr(vcpu, dr, val)) { 897 kvm_inject_gp(vcpu, 0); 898 return 1; 899 } 900 return 0; 901 } 902 EXPORT_SYMBOL_GPL(kvm_set_dr); 903 904 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 905 { 906 switch (dr) { 907 case 0 ... 3: 908 *val = vcpu->arch.db[dr]; 909 break; 910 case 4: 911 /* fall through */ 912 case 6: 913 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 914 *val = vcpu->arch.dr6; 915 else 916 *val = kvm_x86_ops->get_dr6(vcpu); 917 break; 918 case 5: 919 /* fall through */ 920 default: /* 7 */ 921 *val = vcpu->arch.dr7; 922 break; 923 } 924 return 0; 925 } 926 EXPORT_SYMBOL_GPL(kvm_get_dr); 927 928 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 929 { 930 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 931 u64 data; 932 int err; 933 934 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 935 if (err) 936 return err; 937 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 938 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 939 return err; 940 } 941 EXPORT_SYMBOL_GPL(kvm_rdpmc); 942 943 /* 944 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 945 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 946 * 947 * This list is modified at module load time to reflect the 948 * capabilities of the host cpu. This capabilities test skips MSRs that are 949 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs 950 * may depend on host virtualization features rather than host cpu features. 951 */ 952 953 static u32 msrs_to_save[] = { 954 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 955 MSR_STAR, 956 #ifdef CONFIG_X86_64 957 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 958 #endif 959 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 960 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 961 }; 962 963 static unsigned num_msrs_to_save; 964 965 static u32 emulated_msrs[] = { 966 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 967 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 968 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 969 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 970 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 971 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 972 HV_X64_MSR_RESET, 973 HV_X64_MSR_VP_INDEX, 974 HV_X64_MSR_VP_RUNTIME, 975 HV_X64_MSR_SCONTROL, 976 HV_X64_MSR_STIMER0_CONFIG, 977 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 978 MSR_KVM_PV_EOI_EN, 979 980 MSR_IA32_TSC_ADJUST, 981 MSR_IA32_TSCDEADLINE, 982 MSR_IA32_MISC_ENABLE, 983 MSR_IA32_MCG_STATUS, 984 MSR_IA32_MCG_CTL, 985 MSR_IA32_SMBASE, 986 }; 987 988 static unsigned num_emulated_msrs; 989 990 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 991 { 992 if (efer & efer_reserved_bits) 993 return false; 994 995 if (efer & EFER_FFXSR) { 996 struct kvm_cpuid_entry2 *feat; 997 998 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 999 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) 1000 return false; 1001 } 1002 1003 if (efer & EFER_SVME) { 1004 struct kvm_cpuid_entry2 *feat; 1005 1006 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 1007 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) 1008 return false; 1009 } 1010 1011 return true; 1012 } 1013 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1014 1015 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 1016 { 1017 u64 old_efer = vcpu->arch.efer; 1018 1019 if (!kvm_valid_efer(vcpu, efer)) 1020 return 1; 1021 1022 if (is_paging(vcpu) 1023 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1024 return 1; 1025 1026 efer &= ~EFER_LMA; 1027 efer |= vcpu->arch.efer & EFER_LMA; 1028 1029 kvm_x86_ops->set_efer(vcpu, efer); 1030 1031 /* Update reserved bits */ 1032 if ((efer ^ old_efer) & EFER_NX) 1033 kvm_mmu_reset_context(vcpu); 1034 1035 return 0; 1036 } 1037 1038 void kvm_enable_efer_bits(u64 mask) 1039 { 1040 efer_reserved_bits &= ~mask; 1041 } 1042 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1043 1044 /* 1045 * Writes msr value into into the appropriate "register". 1046 * Returns 0 on success, non-0 otherwise. 1047 * Assumes vcpu_load() was already called. 1048 */ 1049 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1050 { 1051 switch (msr->index) { 1052 case MSR_FS_BASE: 1053 case MSR_GS_BASE: 1054 case MSR_KERNEL_GS_BASE: 1055 case MSR_CSTAR: 1056 case MSR_LSTAR: 1057 if (is_noncanonical_address(msr->data)) 1058 return 1; 1059 break; 1060 case MSR_IA32_SYSENTER_EIP: 1061 case MSR_IA32_SYSENTER_ESP: 1062 /* 1063 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1064 * non-canonical address is written on Intel but not on 1065 * AMD (which ignores the top 32-bits, because it does 1066 * not implement 64-bit SYSENTER). 1067 * 1068 * 64-bit code should hence be able to write a non-canonical 1069 * value on AMD. Making the address canonical ensures that 1070 * vmentry does not fail on Intel after writing a non-canonical 1071 * value, and that something deterministic happens if the guest 1072 * invokes 64-bit SYSENTER. 1073 */ 1074 msr->data = get_canonical(msr->data); 1075 } 1076 return kvm_x86_ops->set_msr(vcpu, msr); 1077 } 1078 EXPORT_SYMBOL_GPL(kvm_set_msr); 1079 1080 /* 1081 * Adapt set_msr() to msr_io()'s calling convention 1082 */ 1083 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1084 { 1085 struct msr_data msr; 1086 int r; 1087 1088 msr.index = index; 1089 msr.host_initiated = true; 1090 r = kvm_get_msr(vcpu, &msr); 1091 if (r) 1092 return r; 1093 1094 *data = msr.data; 1095 return 0; 1096 } 1097 1098 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1099 { 1100 struct msr_data msr; 1101 1102 msr.data = *data; 1103 msr.index = index; 1104 msr.host_initiated = true; 1105 return kvm_set_msr(vcpu, &msr); 1106 } 1107 1108 #ifdef CONFIG_X86_64 1109 struct pvclock_gtod_data { 1110 seqcount_t seq; 1111 1112 struct { /* extract of a clocksource struct */ 1113 int vclock_mode; 1114 cycle_t cycle_last; 1115 cycle_t mask; 1116 u32 mult; 1117 u32 shift; 1118 } clock; 1119 1120 u64 boot_ns; 1121 u64 nsec_base; 1122 }; 1123 1124 static struct pvclock_gtod_data pvclock_gtod_data; 1125 1126 static void update_pvclock_gtod(struct timekeeper *tk) 1127 { 1128 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1129 u64 boot_ns; 1130 1131 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1132 1133 write_seqcount_begin(&vdata->seq); 1134 1135 /* copy pvclock gtod data */ 1136 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1137 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1138 vdata->clock.mask = tk->tkr_mono.mask; 1139 vdata->clock.mult = tk->tkr_mono.mult; 1140 vdata->clock.shift = tk->tkr_mono.shift; 1141 1142 vdata->boot_ns = boot_ns; 1143 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1144 1145 write_seqcount_end(&vdata->seq); 1146 } 1147 #endif 1148 1149 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1150 { 1151 /* 1152 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1153 * vcpu_enter_guest. This function is only called from 1154 * the physical CPU that is running vcpu. 1155 */ 1156 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1157 } 1158 1159 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1160 { 1161 int version; 1162 int r; 1163 struct pvclock_wall_clock wc; 1164 struct timespec boot; 1165 1166 if (!wall_clock) 1167 return; 1168 1169 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1170 if (r) 1171 return; 1172 1173 if (version & 1) 1174 ++version; /* first time write, random junk */ 1175 1176 ++version; 1177 1178 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1179 return; 1180 1181 /* 1182 * The guest calculates current wall clock time by adding 1183 * system time (updated by kvm_guest_time_update below) to the 1184 * wall clock specified here. guest system time equals host 1185 * system time for us, thus we must fill in host boot time here. 1186 */ 1187 getboottime(&boot); 1188 1189 if (kvm->arch.kvmclock_offset) { 1190 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); 1191 boot = timespec_sub(boot, ts); 1192 } 1193 wc.sec = boot.tv_sec; 1194 wc.nsec = boot.tv_nsec; 1195 wc.version = version; 1196 1197 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1198 1199 version++; 1200 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1201 } 1202 1203 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1204 { 1205 do_shl32_div32(dividend, divisor); 1206 return dividend; 1207 } 1208 1209 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 1210 s8 *pshift, u32 *pmultiplier) 1211 { 1212 uint64_t scaled64; 1213 int32_t shift = 0; 1214 uint64_t tps64; 1215 uint32_t tps32; 1216 1217 tps64 = base_hz; 1218 scaled64 = scaled_hz; 1219 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1220 tps64 >>= 1; 1221 shift--; 1222 } 1223 1224 tps32 = (uint32_t)tps64; 1225 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1226 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1227 scaled64 >>= 1; 1228 else 1229 tps32 <<= 1; 1230 shift++; 1231 } 1232 1233 *pshift = shift; 1234 *pmultiplier = div_frac(scaled64, tps32); 1235 1236 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n", 1237 __func__, base_hz, scaled_hz, shift, *pmultiplier); 1238 } 1239 1240 #ifdef CONFIG_X86_64 1241 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1242 #endif 1243 1244 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1245 static unsigned long max_tsc_khz; 1246 1247 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1248 { 1249 u64 v = (u64)khz * (1000000 + ppm); 1250 do_div(v, 1000000); 1251 return v; 1252 } 1253 1254 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 1255 { 1256 u64 ratio; 1257 1258 /* Guest TSC same frequency as host TSC? */ 1259 if (!scale) { 1260 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1261 return 0; 1262 } 1263 1264 /* TSC scaling supported? */ 1265 if (!kvm_has_tsc_control) { 1266 if (user_tsc_khz > tsc_khz) { 1267 vcpu->arch.tsc_catchup = 1; 1268 vcpu->arch.tsc_always_catchup = 1; 1269 return 0; 1270 } else { 1271 WARN(1, "user requested TSC rate below hardware speed\n"); 1272 return -1; 1273 } 1274 } 1275 1276 /* TSC scaling required - calculate ratio */ 1277 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 1278 user_tsc_khz, tsc_khz); 1279 1280 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 1281 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 1282 user_tsc_khz); 1283 return -1; 1284 } 1285 1286 vcpu->arch.tsc_scaling_ratio = ratio; 1287 return 0; 1288 } 1289 1290 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 1291 { 1292 u32 thresh_lo, thresh_hi; 1293 int use_scaling = 0; 1294 1295 /* tsc_khz can be zero if TSC calibration fails */ 1296 if (user_tsc_khz == 0) { 1297 /* set tsc_scaling_ratio to a safe value */ 1298 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1299 return -1; 1300 } 1301 1302 /* Compute a scale to convert nanoseconds in TSC cycles */ 1303 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 1304 &vcpu->arch.virtual_tsc_shift, 1305 &vcpu->arch.virtual_tsc_mult); 1306 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 1307 1308 /* 1309 * Compute the variation in TSC rate which is acceptable 1310 * within the range of tolerance and decide if the 1311 * rate being applied is within that bounds of the hardware 1312 * rate. If so, no scaling or compensation need be done. 1313 */ 1314 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1315 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1316 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 1317 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 1318 use_scaling = 1; 1319 } 1320 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 1321 } 1322 1323 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1324 { 1325 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1326 vcpu->arch.virtual_tsc_mult, 1327 vcpu->arch.virtual_tsc_shift); 1328 tsc += vcpu->arch.this_tsc_write; 1329 return tsc; 1330 } 1331 1332 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1333 { 1334 #ifdef CONFIG_X86_64 1335 bool vcpus_matched; 1336 struct kvm_arch *ka = &vcpu->kvm->arch; 1337 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1338 1339 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1340 atomic_read(&vcpu->kvm->online_vcpus)); 1341 1342 /* 1343 * Once the masterclock is enabled, always perform request in 1344 * order to update it. 1345 * 1346 * In order to enable masterclock, the host clocksource must be TSC 1347 * and the vcpus need to have matched TSCs. When that happens, 1348 * perform request to enable masterclock. 1349 */ 1350 if (ka->use_master_clock || 1351 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) 1352 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1353 1354 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1355 atomic_read(&vcpu->kvm->online_vcpus), 1356 ka->use_master_clock, gtod->clock.vclock_mode); 1357 #endif 1358 } 1359 1360 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1361 { 1362 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); 1363 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1364 } 1365 1366 /* 1367 * Multiply tsc by a fixed point number represented by ratio. 1368 * 1369 * The most significant 64-N bits (mult) of ratio represent the 1370 * integral part of the fixed point number; the remaining N bits 1371 * (frac) represent the fractional part, ie. ratio represents a fixed 1372 * point number (mult + frac * 2^(-N)). 1373 * 1374 * N equals to kvm_tsc_scaling_ratio_frac_bits. 1375 */ 1376 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 1377 { 1378 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 1379 } 1380 1381 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 1382 { 1383 u64 _tsc = tsc; 1384 u64 ratio = vcpu->arch.tsc_scaling_ratio; 1385 1386 if (ratio != kvm_default_tsc_scaling_ratio) 1387 _tsc = __scale_tsc(ratio, tsc); 1388 1389 return _tsc; 1390 } 1391 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 1392 1393 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 1394 { 1395 u64 tsc; 1396 1397 tsc = kvm_scale_tsc(vcpu, rdtsc()); 1398 1399 return target_tsc - tsc; 1400 } 1401 1402 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 1403 { 1404 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc)); 1405 } 1406 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 1407 1408 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1409 { 1410 struct kvm *kvm = vcpu->kvm; 1411 u64 offset, ns, elapsed; 1412 unsigned long flags; 1413 s64 usdiff; 1414 bool matched; 1415 bool already_matched; 1416 u64 data = msr->data; 1417 1418 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1419 offset = kvm_compute_tsc_offset(vcpu, data); 1420 ns = get_kernel_ns(); 1421 elapsed = ns - kvm->arch.last_tsc_nsec; 1422 1423 if (vcpu->arch.virtual_tsc_khz) { 1424 int faulted = 0; 1425 1426 /* n.b - signed multiplication and division required */ 1427 usdiff = data - kvm->arch.last_tsc_write; 1428 #ifdef CONFIG_X86_64 1429 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; 1430 #else 1431 /* do_div() only does unsigned */ 1432 asm("1: idivl %[divisor]\n" 1433 "2: xor %%edx, %%edx\n" 1434 " movl $0, %[faulted]\n" 1435 "3:\n" 1436 ".section .fixup,\"ax\"\n" 1437 "4: movl $1, %[faulted]\n" 1438 " jmp 3b\n" 1439 ".previous\n" 1440 1441 _ASM_EXTABLE(1b, 4b) 1442 1443 : "=A"(usdiff), [faulted] "=r" (faulted) 1444 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); 1445 1446 #endif 1447 do_div(elapsed, 1000); 1448 usdiff -= elapsed; 1449 if (usdiff < 0) 1450 usdiff = -usdiff; 1451 1452 /* idivl overflow => difference is larger than USEC_PER_SEC */ 1453 if (faulted) 1454 usdiff = USEC_PER_SEC; 1455 } else 1456 usdiff = USEC_PER_SEC; /* disable TSC match window below */ 1457 1458 /* 1459 * Special case: TSC write with a small delta (1 second) of virtual 1460 * cycle time against real time is interpreted as an attempt to 1461 * synchronize the CPU. 1462 * 1463 * For a reliable TSC, we can match TSC offsets, and for an unstable 1464 * TSC, we add elapsed time in this computation. We could let the 1465 * compensation code attempt to catch up if we fall behind, but 1466 * it's better to try to match offsets from the beginning. 1467 */ 1468 if (usdiff < USEC_PER_SEC && 1469 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1470 if (!check_tsc_unstable()) { 1471 offset = kvm->arch.cur_tsc_offset; 1472 pr_debug("kvm: matched tsc offset for %llu\n", data); 1473 } else { 1474 u64 delta = nsec_to_cycles(vcpu, elapsed); 1475 data += delta; 1476 offset = kvm_compute_tsc_offset(vcpu, data); 1477 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1478 } 1479 matched = true; 1480 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1481 } else { 1482 /* 1483 * We split periods of matched TSC writes into generations. 1484 * For each generation, we track the original measured 1485 * nanosecond time, offset, and write, so if TSCs are in 1486 * sync, we can match exact offset, and if not, we can match 1487 * exact software computation in compute_guest_tsc() 1488 * 1489 * These values are tracked in kvm->arch.cur_xxx variables. 1490 */ 1491 kvm->arch.cur_tsc_generation++; 1492 kvm->arch.cur_tsc_nsec = ns; 1493 kvm->arch.cur_tsc_write = data; 1494 kvm->arch.cur_tsc_offset = offset; 1495 matched = false; 1496 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1497 kvm->arch.cur_tsc_generation, data); 1498 } 1499 1500 /* 1501 * We also track th most recent recorded KHZ, write and time to 1502 * allow the matching interval to be extended at each write. 1503 */ 1504 kvm->arch.last_tsc_nsec = ns; 1505 kvm->arch.last_tsc_write = data; 1506 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1507 1508 vcpu->arch.last_guest_tsc = data; 1509 1510 /* Keep track of which generation this VCPU has synchronized to */ 1511 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1512 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1513 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1514 1515 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) 1516 update_ia32_tsc_adjust_msr(vcpu, offset); 1517 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1518 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1519 1520 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1521 if (!matched) { 1522 kvm->arch.nr_vcpus_matched_tsc = 0; 1523 } else if (!already_matched) { 1524 kvm->arch.nr_vcpus_matched_tsc++; 1525 } 1526 1527 kvm_track_tsc_matching(vcpu); 1528 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1529 } 1530 1531 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1532 1533 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 1534 s64 adjustment) 1535 { 1536 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment); 1537 } 1538 1539 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 1540 { 1541 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 1542 WARN_ON(adjustment < 0); 1543 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 1544 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment); 1545 } 1546 1547 #ifdef CONFIG_X86_64 1548 1549 static cycle_t read_tsc(void) 1550 { 1551 cycle_t ret = (cycle_t)rdtsc_ordered(); 1552 u64 last = pvclock_gtod_data.clock.cycle_last; 1553 1554 if (likely(ret >= last)) 1555 return ret; 1556 1557 /* 1558 * GCC likes to generate cmov here, but this branch is extremely 1559 * predictable (it's just a function of time and the likely is 1560 * very likely) and there's a data dependence, so force GCC 1561 * to generate a branch instead. I don't barrier() because 1562 * we don't actually need a barrier, and if this function 1563 * ever gets inlined it will generate worse code. 1564 */ 1565 asm volatile (""); 1566 return last; 1567 } 1568 1569 static inline u64 vgettsc(cycle_t *cycle_now) 1570 { 1571 long v; 1572 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1573 1574 *cycle_now = read_tsc(); 1575 1576 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; 1577 return v * gtod->clock.mult; 1578 } 1579 1580 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now) 1581 { 1582 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1583 unsigned long seq; 1584 int mode; 1585 u64 ns; 1586 1587 do { 1588 seq = read_seqcount_begin(>od->seq); 1589 mode = gtod->clock.vclock_mode; 1590 ns = gtod->nsec_base; 1591 ns += vgettsc(cycle_now); 1592 ns >>= gtod->clock.shift; 1593 ns += gtod->boot_ns; 1594 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1595 *t = ns; 1596 1597 return mode; 1598 } 1599 1600 /* returns true if host is using tsc clocksource */ 1601 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) 1602 { 1603 /* checked again under seqlock below */ 1604 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) 1605 return false; 1606 1607 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; 1608 } 1609 #endif 1610 1611 /* 1612 * 1613 * Assuming a stable TSC across physical CPUS, and a stable TSC 1614 * across virtual CPUs, the following condition is possible. 1615 * Each numbered line represents an event visible to both 1616 * CPUs at the next numbered event. 1617 * 1618 * "timespecX" represents host monotonic time. "tscX" represents 1619 * RDTSC value. 1620 * 1621 * VCPU0 on CPU0 | VCPU1 on CPU1 1622 * 1623 * 1. read timespec0,tsc0 1624 * 2. | timespec1 = timespec0 + N 1625 * | tsc1 = tsc0 + M 1626 * 3. transition to guest | transition to guest 1627 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1628 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1629 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1630 * 1631 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1632 * 1633 * - ret0 < ret1 1634 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1635 * ... 1636 * - 0 < N - M => M < N 1637 * 1638 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1639 * always the case (the difference between two distinct xtime instances 1640 * might be smaller then the difference between corresponding TSC reads, 1641 * when updating guest vcpus pvclock areas). 1642 * 1643 * To avoid that problem, do not allow visibility of distinct 1644 * system_timestamp/tsc_timestamp values simultaneously: use a master 1645 * copy of host monotonic time values. Update that master copy 1646 * in lockstep. 1647 * 1648 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1649 * 1650 */ 1651 1652 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1653 { 1654 #ifdef CONFIG_X86_64 1655 struct kvm_arch *ka = &kvm->arch; 1656 int vclock_mode; 1657 bool host_tsc_clocksource, vcpus_matched; 1658 1659 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1660 atomic_read(&kvm->online_vcpus)); 1661 1662 /* 1663 * If the host uses TSC clock, then passthrough TSC as stable 1664 * to the guest. 1665 */ 1666 host_tsc_clocksource = kvm_get_time_and_clockread( 1667 &ka->master_kernel_ns, 1668 &ka->master_cycle_now); 1669 1670 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 1671 && !backwards_tsc_observed 1672 && !ka->boot_vcpu_runs_old_kvmclock; 1673 1674 if (ka->use_master_clock) 1675 atomic_set(&kvm_guest_has_master_clock, 1); 1676 1677 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1678 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1679 vcpus_matched); 1680 #endif 1681 } 1682 1683 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 1684 { 1685 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 1686 } 1687 1688 static void kvm_gen_update_masterclock(struct kvm *kvm) 1689 { 1690 #ifdef CONFIG_X86_64 1691 int i; 1692 struct kvm_vcpu *vcpu; 1693 struct kvm_arch *ka = &kvm->arch; 1694 1695 spin_lock(&ka->pvclock_gtod_sync_lock); 1696 kvm_make_mclock_inprogress_request(kvm); 1697 /* no guest entries from this point */ 1698 pvclock_update_vm_gtod_copy(kvm); 1699 1700 kvm_for_each_vcpu(i, vcpu, kvm) 1701 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1702 1703 /* guest entries allowed */ 1704 kvm_for_each_vcpu(i, vcpu, kvm) 1705 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); 1706 1707 spin_unlock(&ka->pvclock_gtod_sync_lock); 1708 #endif 1709 } 1710 1711 static int kvm_guest_time_update(struct kvm_vcpu *v) 1712 { 1713 unsigned long flags, tgt_tsc_khz; 1714 struct kvm_vcpu_arch *vcpu = &v->arch; 1715 struct kvm_arch *ka = &v->kvm->arch; 1716 s64 kernel_ns; 1717 u64 tsc_timestamp, host_tsc; 1718 struct pvclock_vcpu_time_info guest_hv_clock; 1719 u8 pvclock_flags; 1720 bool use_master_clock; 1721 1722 kernel_ns = 0; 1723 host_tsc = 0; 1724 1725 /* 1726 * If the host uses TSC clock, then passthrough TSC as stable 1727 * to the guest. 1728 */ 1729 spin_lock(&ka->pvclock_gtod_sync_lock); 1730 use_master_clock = ka->use_master_clock; 1731 if (use_master_clock) { 1732 host_tsc = ka->master_cycle_now; 1733 kernel_ns = ka->master_kernel_ns; 1734 } 1735 spin_unlock(&ka->pvclock_gtod_sync_lock); 1736 1737 /* Keep irq disabled to prevent changes to the clock */ 1738 local_irq_save(flags); 1739 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 1740 if (unlikely(tgt_tsc_khz == 0)) { 1741 local_irq_restore(flags); 1742 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1743 return 1; 1744 } 1745 if (!use_master_clock) { 1746 host_tsc = rdtsc(); 1747 kernel_ns = get_kernel_ns(); 1748 } 1749 1750 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 1751 1752 /* 1753 * We may have to catch up the TSC to match elapsed wall clock 1754 * time for two reasons, even if kvmclock is used. 1755 * 1) CPU could have been running below the maximum TSC rate 1756 * 2) Broken TSC compensation resets the base at each VCPU 1757 * entry to avoid unknown leaps of TSC even when running 1758 * again on the same CPU. This may cause apparent elapsed 1759 * time to disappear, and the guest to stand still or run 1760 * very slowly. 1761 */ 1762 if (vcpu->tsc_catchup) { 1763 u64 tsc = compute_guest_tsc(v, kernel_ns); 1764 if (tsc > tsc_timestamp) { 1765 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 1766 tsc_timestamp = tsc; 1767 } 1768 } 1769 1770 local_irq_restore(flags); 1771 1772 if (!vcpu->pv_time_enabled) 1773 return 0; 1774 1775 if (kvm_has_tsc_control) 1776 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 1777 1778 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 1779 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 1780 &vcpu->hv_clock.tsc_shift, 1781 &vcpu->hv_clock.tsc_to_system_mul); 1782 vcpu->hw_tsc_khz = tgt_tsc_khz; 1783 } 1784 1785 /* With all the info we got, fill in the values */ 1786 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 1787 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 1788 vcpu->last_guest_tsc = tsc_timestamp; 1789 1790 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1791 &guest_hv_clock, sizeof(guest_hv_clock)))) 1792 return 0; 1793 1794 /* This VCPU is paused, but it's legal for a guest to read another 1795 * VCPU's kvmclock, so we really have to follow the specification where 1796 * it says that version is odd if data is being modified, and even after 1797 * it is consistent. 1798 * 1799 * Version field updates must be kept separate. This is because 1800 * kvm_write_guest_cached might use a "rep movs" instruction, and 1801 * writes within a string instruction are weakly ordered. So there 1802 * are three writes overall. 1803 * 1804 * As a small optimization, only write the version field in the first 1805 * and third write. The vcpu->pv_time cache is still valid, because the 1806 * version field is the first in the struct. 1807 */ 1808 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 1809 1810 vcpu->hv_clock.version = guest_hv_clock.version + 1; 1811 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1812 &vcpu->hv_clock, 1813 sizeof(vcpu->hv_clock.version)); 1814 1815 smp_wmb(); 1816 1817 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1818 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1819 1820 if (vcpu->pvclock_set_guest_stopped_request) { 1821 pvclock_flags |= PVCLOCK_GUEST_STOPPED; 1822 vcpu->pvclock_set_guest_stopped_request = false; 1823 } 1824 1825 /* If the host uses TSC clocksource, then it is stable */ 1826 if (use_master_clock) 1827 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 1828 1829 vcpu->hv_clock.flags = pvclock_flags; 1830 1831 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 1832 1833 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1834 &vcpu->hv_clock, 1835 sizeof(vcpu->hv_clock)); 1836 1837 smp_wmb(); 1838 1839 vcpu->hv_clock.version++; 1840 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1841 &vcpu->hv_clock, 1842 sizeof(vcpu->hv_clock.version)); 1843 return 0; 1844 } 1845 1846 /* 1847 * kvmclock updates which are isolated to a given vcpu, such as 1848 * vcpu->cpu migration, should not allow system_timestamp from 1849 * the rest of the vcpus to remain static. Otherwise ntp frequency 1850 * correction applies to one vcpu's system_timestamp but not 1851 * the others. 1852 * 1853 * So in those cases, request a kvmclock update for all vcpus. 1854 * We need to rate-limit these requests though, as they can 1855 * considerably slow guests that have a large number of vcpus. 1856 * The time for a remote vcpu to update its kvmclock is bound 1857 * by the delay we use to rate-limit the updates. 1858 */ 1859 1860 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 1861 1862 static void kvmclock_update_fn(struct work_struct *work) 1863 { 1864 int i; 1865 struct delayed_work *dwork = to_delayed_work(work); 1866 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1867 kvmclock_update_work); 1868 struct kvm *kvm = container_of(ka, struct kvm, arch); 1869 struct kvm_vcpu *vcpu; 1870 1871 kvm_for_each_vcpu(i, vcpu, kvm) { 1872 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1873 kvm_vcpu_kick(vcpu); 1874 } 1875 } 1876 1877 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 1878 { 1879 struct kvm *kvm = v->kvm; 1880 1881 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1882 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 1883 KVMCLOCK_UPDATE_DELAY); 1884 } 1885 1886 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 1887 1888 static void kvmclock_sync_fn(struct work_struct *work) 1889 { 1890 struct delayed_work *dwork = to_delayed_work(work); 1891 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1892 kvmclock_sync_work); 1893 struct kvm *kvm = container_of(ka, struct kvm, arch); 1894 1895 if (!kvmclock_periodic_sync) 1896 return; 1897 1898 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 1899 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 1900 KVMCLOCK_SYNC_PERIOD); 1901 } 1902 1903 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1904 { 1905 u64 mcg_cap = vcpu->arch.mcg_cap; 1906 unsigned bank_num = mcg_cap & 0xff; 1907 1908 switch (msr) { 1909 case MSR_IA32_MCG_STATUS: 1910 vcpu->arch.mcg_status = data; 1911 break; 1912 case MSR_IA32_MCG_CTL: 1913 if (!(mcg_cap & MCG_CTL_P)) 1914 return 1; 1915 if (data != 0 && data != ~(u64)0) 1916 return -1; 1917 vcpu->arch.mcg_ctl = data; 1918 break; 1919 default: 1920 if (msr >= MSR_IA32_MC0_CTL && 1921 msr < MSR_IA32_MCx_CTL(bank_num)) { 1922 u32 offset = msr - MSR_IA32_MC0_CTL; 1923 /* only 0 or all 1s can be written to IA32_MCi_CTL 1924 * some Linux kernels though clear bit 10 in bank 4 to 1925 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 1926 * this to avoid an uncatched #GP in the guest 1927 */ 1928 if ((offset & 0x3) == 0 && 1929 data != 0 && (data | (1 << 10)) != ~(u64)0) 1930 return -1; 1931 vcpu->arch.mce_banks[offset] = data; 1932 break; 1933 } 1934 return 1; 1935 } 1936 return 0; 1937 } 1938 1939 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 1940 { 1941 struct kvm *kvm = vcpu->kvm; 1942 int lm = is_long_mode(vcpu); 1943 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 1944 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 1945 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 1946 : kvm->arch.xen_hvm_config.blob_size_32; 1947 u32 page_num = data & ~PAGE_MASK; 1948 u64 page_addr = data & PAGE_MASK; 1949 u8 *page; 1950 int r; 1951 1952 r = -E2BIG; 1953 if (page_num >= blob_size) 1954 goto out; 1955 r = -ENOMEM; 1956 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 1957 if (IS_ERR(page)) { 1958 r = PTR_ERR(page); 1959 goto out; 1960 } 1961 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 1962 goto out_free; 1963 r = 0; 1964 out_free: 1965 kfree(page); 1966 out: 1967 return r; 1968 } 1969 1970 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 1971 { 1972 gpa_t gpa = data & ~0x3f; 1973 1974 /* Bits 2:5 are reserved, Should be zero */ 1975 if (data & 0x3c) 1976 return 1; 1977 1978 vcpu->arch.apf.msr_val = data; 1979 1980 if (!(data & KVM_ASYNC_PF_ENABLED)) { 1981 kvm_clear_async_pf_completion_queue(vcpu); 1982 kvm_async_pf_hash_reset(vcpu); 1983 return 0; 1984 } 1985 1986 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 1987 sizeof(u32))) 1988 return 1; 1989 1990 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 1991 kvm_async_pf_wakeup_all(vcpu); 1992 return 0; 1993 } 1994 1995 static void kvmclock_reset(struct kvm_vcpu *vcpu) 1996 { 1997 vcpu->arch.pv_time_enabled = false; 1998 } 1999 2000 static void record_steal_time(struct kvm_vcpu *vcpu) 2001 { 2002 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2003 return; 2004 2005 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2006 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2007 return; 2008 2009 if (vcpu->arch.st.steal.version & 1) 2010 vcpu->arch.st.steal.version += 1; /* first time write, random junk */ 2011 2012 vcpu->arch.st.steal.version += 1; 2013 2014 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2015 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2016 2017 smp_wmb(); 2018 2019 vcpu->arch.st.steal.steal += current->sched_info.run_delay - 2020 vcpu->arch.st.last_steal; 2021 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2022 2023 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2024 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2025 2026 smp_wmb(); 2027 2028 vcpu->arch.st.steal.version += 1; 2029 2030 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2031 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2032 } 2033 2034 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2035 { 2036 bool pr = false; 2037 u32 msr = msr_info->index; 2038 u64 data = msr_info->data; 2039 2040 switch (msr) { 2041 case MSR_AMD64_NB_CFG: 2042 case MSR_IA32_UCODE_REV: 2043 case MSR_IA32_UCODE_WRITE: 2044 case MSR_VM_HSAVE_PA: 2045 case MSR_AMD64_PATCH_LOADER: 2046 case MSR_AMD64_BU_CFG2: 2047 break; 2048 2049 case MSR_EFER: 2050 return set_efer(vcpu, data); 2051 case MSR_K7_HWCR: 2052 data &= ~(u64)0x40; /* ignore flush filter disable */ 2053 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2054 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2055 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2056 if (data != 0) { 2057 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2058 data); 2059 return 1; 2060 } 2061 break; 2062 case MSR_FAM10H_MMIO_CONF_BASE: 2063 if (data != 0) { 2064 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2065 "0x%llx\n", data); 2066 return 1; 2067 } 2068 break; 2069 case MSR_IA32_DEBUGCTLMSR: 2070 if (!data) { 2071 /* We support the non-activated case already */ 2072 break; 2073 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2074 /* Values other than LBR and BTF are vendor-specific, 2075 thus reserved and should throw a #GP */ 2076 return 1; 2077 } 2078 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2079 __func__, data); 2080 break; 2081 case 0x200 ... 0x2ff: 2082 return kvm_mtrr_set_msr(vcpu, msr, data); 2083 case MSR_IA32_APICBASE: 2084 return kvm_set_apic_base(vcpu, msr_info); 2085 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2086 return kvm_x2apic_msr_write(vcpu, msr, data); 2087 case MSR_IA32_TSCDEADLINE: 2088 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2089 break; 2090 case MSR_IA32_TSC_ADJUST: 2091 if (guest_cpuid_has_tsc_adjust(vcpu)) { 2092 if (!msr_info->host_initiated) { 2093 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2094 adjust_tsc_offset_guest(vcpu, adj); 2095 } 2096 vcpu->arch.ia32_tsc_adjust_msr = data; 2097 } 2098 break; 2099 case MSR_IA32_MISC_ENABLE: 2100 vcpu->arch.ia32_misc_enable_msr = data; 2101 break; 2102 case MSR_IA32_SMBASE: 2103 if (!msr_info->host_initiated) 2104 return 1; 2105 vcpu->arch.smbase = data; 2106 break; 2107 case MSR_KVM_WALL_CLOCK_NEW: 2108 case MSR_KVM_WALL_CLOCK: 2109 vcpu->kvm->arch.wall_clock = data; 2110 kvm_write_wall_clock(vcpu->kvm, data); 2111 break; 2112 case MSR_KVM_SYSTEM_TIME_NEW: 2113 case MSR_KVM_SYSTEM_TIME: { 2114 u64 gpa_offset; 2115 struct kvm_arch *ka = &vcpu->kvm->arch; 2116 2117 kvmclock_reset(vcpu); 2118 2119 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2120 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2121 2122 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2123 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, 2124 &vcpu->requests); 2125 2126 ka->boot_vcpu_runs_old_kvmclock = tmp; 2127 } 2128 2129 vcpu->arch.time = data; 2130 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2131 2132 /* we verify if the enable bit is set... */ 2133 if (!(data & 1)) 2134 break; 2135 2136 gpa_offset = data & ~(PAGE_MASK | 1); 2137 2138 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2139 &vcpu->arch.pv_time, data & ~1ULL, 2140 sizeof(struct pvclock_vcpu_time_info))) 2141 vcpu->arch.pv_time_enabled = false; 2142 else 2143 vcpu->arch.pv_time_enabled = true; 2144 2145 break; 2146 } 2147 case MSR_KVM_ASYNC_PF_EN: 2148 if (kvm_pv_enable_async_pf(vcpu, data)) 2149 return 1; 2150 break; 2151 case MSR_KVM_STEAL_TIME: 2152 2153 if (unlikely(!sched_info_on())) 2154 return 1; 2155 2156 if (data & KVM_STEAL_RESERVED_MASK) 2157 return 1; 2158 2159 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2160 data & KVM_STEAL_VALID_BITS, 2161 sizeof(struct kvm_steal_time))) 2162 return 1; 2163 2164 vcpu->arch.st.msr_val = data; 2165 2166 if (!(data & KVM_MSR_ENABLED)) 2167 break; 2168 2169 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2170 2171 break; 2172 case MSR_KVM_PV_EOI_EN: 2173 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2174 return 1; 2175 break; 2176 2177 case MSR_IA32_MCG_CTL: 2178 case MSR_IA32_MCG_STATUS: 2179 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2180 return set_msr_mce(vcpu, msr, data); 2181 2182 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2183 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2184 pr = true; /* fall through */ 2185 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2186 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2187 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2188 return kvm_pmu_set_msr(vcpu, msr_info); 2189 2190 if (pr || data != 0) 2191 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2192 "0x%x data 0x%llx\n", msr, data); 2193 break; 2194 case MSR_K7_CLK_CTL: 2195 /* 2196 * Ignore all writes to this no longer documented MSR. 2197 * Writes are only relevant for old K7 processors, 2198 * all pre-dating SVM, but a recommended workaround from 2199 * AMD for these chips. It is possible to specify the 2200 * affected processor models on the command line, hence 2201 * the need to ignore the workaround. 2202 */ 2203 break; 2204 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2205 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2206 case HV_X64_MSR_CRASH_CTL: 2207 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2208 return kvm_hv_set_msr_common(vcpu, msr, data, 2209 msr_info->host_initiated); 2210 case MSR_IA32_BBL_CR_CTL3: 2211 /* Drop writes to this legacy MSR -- see rdmsr 2212 * counterpart for further detail. 2213 */ 2214 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); 2215 break; 2216 case MSR_AMD64_OSVW_ID_LENGTH: 2217 if (!guest_cpuid_has_osvw(vcpu)) 2218 return 1; 2219 vcpu->arch.osvw.length = data; 2220 break; 2221 case MSR_AMD64_OSVW_STATUS: 2222 if (!guest_cpuid_has_osvw(vcpu)) 2223 return 1; 2224 vcpu->arch.osvw.status = data; 2225 break; 2226 default: 2227 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2228 return xen_hvm_config(vcpu, data); 2229 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2230 return kvm_pmu_set_msr(vcpu, msr_info); 2231 if (!ignore_msrs) { 2232 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", 2233 msr, data); 2234 return 1; 2235 } else { 2236 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", 2237 msr, data); 2238 break; 2239 } 2240 } 2241 return 0; 2242 } 2243 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2244 2245 2246 /* 2247 * Reads an msr value (of 'msr_index') into 'pdata'. 2248 * Returns 0 on success, non-0 otherwise. 2249 * Assumes vcpu_load() was already called. 2250 */ 2251 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 2252 { 2253 return kvm_x86_ops->get_msr(vcpu, msr); 2254 } 2255 EXPORT_SYMBOL_GPL(kvm_get_msr); 2256 2257 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2258 { 2259 u64 data; 2260 u64 mcg_cap = vcpu->arch.mcg_cap; 2261 unsigned bank_num = mcg_cap & 0xff; 2262 2263 switch (msr) { 2264 case MSR_IA32_P5_MC_ADDR: 2265 case MSR_IA32_P5_MC_TYPE: 2266 data = 0; 2267 break; 2268 case MSR_IA32_MCG_CAP: 2269 data = vcpu->arch.mcg_cap; 2270 break; 2271 case MSR_IA32_MCG_CTL: 2272 if (!(mcg_cap & MCG_CTL_P)) 2273 return 1; 2274 data = vcpu->arch.mcg_ctl; 2275 break; 2276 case MSR_IA32_MCG_STATUS: 2277 data = vcpu->arch.mcg_status; 2278 break; 2279 default: 2280 if (msr >= MSR_IA32_MC0_CTL && 2281 msr < MSR_IA32_MCx_CTL(bank_num)) { 2282 u32 offset = msr - MSR_IA32_MC0_CTL; 2283 data = vcpu->arch.mce_banks[offset]; 2284 break; 2285 } 2286 return 1; 2287 } 2288 *pdata = data; 2289 return 0; 2290 } 2291 2292 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2293 { 2294 switch (msr_info->index) { 2295 case MSR_IA32_PLATFORM_ID: 2296 case MSR_IA32_EBL_CR_POWERON: 2297 case MSR_IA32_DEBUGCTLMSR: 2298 case MSR_IA32_LASTBRANCHFROMIP: 2299 case MSR_IA32_LASTBRANCHTOIP: 2300 case MSR_IA32_LASTINTFROMIP: 2301 case MSR_IA32_LASTINTTOIP: 2302 case MSR_K8_SYSCFG: 2303 case MSR_K8_TSEG_ADDR: 2304 case MSR_K8_TSEG_MASK: 2305 case MSR_K7_HWCR: 2306 case MSR_VM_HSAVE_PA: 2307 case MSR_K8_INT_PENDING_MSG: 2308 case MSR_AMD64_NB_CFG: 2309 case MSR_FAM10H_MMIO_CONF_BASE: 2310 case MSR_AMD64_BU_CFG2: 2311 case MSR_IA32_PERF_CTL: 2312 msr_info->data = 0; 2313 break; 2314 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2315 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2316 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2317 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2318 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2319 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2320 msr_info->data = 0; 2321 break; 2322 case MSR_IA32_UCODE_REV: 2323 msr_info->data = 0x100000000ULL; 2324 break; 2325 case MSR_MTRRcap: 2326 case 0x200 ... 0x2ff: 2327 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 2328 case 0xcd: /* fsb frequency */ 2329 msr_info->data = 3; 2330 break; 2331 /* 2332 * MSR_EBC_FREQUENCY_ID 2333 * Conservative value valid for even the basic CPU models. 2334 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2335 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2336 * and 266MHz for model 3, or 4. Set Core Clock 2337 * Frequency to System Bus Frequency Ratio to 1 (bits 2338 * 31:24) even though these are only valid for CPU 2339 * models > 2, however guests may end up dividing or 2340 * multiplying by zero otherwise. 2341 */ 2342 case MSR_EBC_FREQUENCY_ID: 2343 msr_info->data = 1 << 24; 2344 break; 2345 case MSR_IA32_APICBASE: 2346 msr_info->data = kvm_get_apic_base(vcpu); 2347 break; 2348 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2349 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 2350 break; 2351 case MSR_IA32_TSCDEADLINE: 2352 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 2353 break; 2354 case MSR_IA32_TSC_ADJUST: 2355 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2356 break; 2357 case MSR_IA32_MISC_ENABLE: 2358 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 2359 break; 2360 case MSR_IA32_SMBASE: 2361 if (!msr_info->host_initiated) 2362 return 1; 2363 msr_info->data = vcpu->arch.smbase; 2364 break; 2365 case MSR_IA32_PERF_STATUS: 2366 /* TSC increment by tick */ 2367 msr_info->data = 1000ULL; 2368 /* CPU multiplier */ 2369 msr_info->data |= (((uint64_t)4ULL) << 40); 2370 break; 2371 case MSR_EFER: 2372 msr_info->data = vcpu->arch.efer; 2373 break; 2374 case MSR_KVM_WALL_CLOCK: 2375 case MSR_KVM_WALL_CLOCK_NEW: 2376 msr_info->data = vcpu->kvm->arch.wall_clock; 2377 break; 2378 case MSR_KVM_SYSTEM_TIME: 2379 case MSR_KVM_SYSTEM_TIME_NEW: 2380 msr_info->data = vcpu->arch.time; 2381 break; 2382 case MSR_KVM_ASYNC_PF_EN: 2383 msr_info->data = vcpu->arch.apf.msr_val; 2384 break; 2385 case MSR_KVM_STEAL_TIME: 2386 msr_info->data = vcpu->arch.st.msr_val; 2387 break; 2388 case MSR_KVM_PV_EOI_EN: 2389 msr_info->data = vcpu->arch.pv_eoi.msr_val; 2390 break; 2391 case MSR_IA32_P5_MC_ADDR: 2392 case MSR_IA32_P5_MC_TYPE: 2393 case MSR_IA32_MCG_CAP: 2394 case MSR_IA32_MCG_CTL: 2395 case MSR_IA32_MCG_STATUS: 2396 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2397 return get_msr_mce(vcpu, msr_info->index, &msr_info->data); 2398 case MSR_K7_CLK_CTL: 2399 /* 2400 * Provide expected ramp-up count for K7. All other 2401 * are set to zero, indicating minimum divisors for 2402 * every field. 2403 * 2404 * This prevents guest kernels on AMD host with CPU 2405 * type 6, model 8 and higher from exploding due to 2406 * the rdmsr failing. 2407 */ 2408 msr_info->data = 0x20000000; 2409 break; 2410 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2411 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2412 case HV_X64_MSR_CRASH_CTL: 2413 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2414 return kvm_hv_get_msr_common(vcpu, 2415 msr_info->index, &msr_info->data); 2416 break; 2417 case MSR_IA32_BBL_CR_CTL3: 2418 /* This legacy MSR exists but isn't fully documented in current 2419 * silicon. It is however accessed by winxp in very narrow 2420 * scenarios where it sets bit #19, itself documented as 2421 * a "reserved" bit. Best effort attempt to source coherent 2422 * read data here should the balance of the register be 2423 * interpreted by the guest: 2424 * 2425 * L2 cache control register 3: 64GB range, 256KB size, 2426 * enabled, latency 0x1, configured 2427 */ 2428 msr_info->data = 0xbe702111; 2429 break; 2430 case MSR_AMD64_OSVW_ID_LENGTH: 2431 if (!guest_cpuid_has_osvw(vcpu)) 2432 return 1; 2433 msr_info->data = vcpu->arch.osvw.length; 2434 break; 2435 case MSR_AMD64_OSVW_STATUS: 2436 if (!guest_cpuid_has_osvw(vcpu)) 2437 return 1; 2438 msr_info->data = vcpu->arch.osvw.status; 2439 break; 2440 default: 2441 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2442 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2443 if (!ignore_msrs) { 2444 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index); 2445 return 1; 2446 } else { 2447 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index); 2448 msr_info->data = 0; 2449 } 2450 break; 2451 } 2452 return 0; 2453 } 2454 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2455 2456 /* 2457 * Read or write a bunch of msrs. All parameters are kernel addresses. 2458 * 2459 * @return number of msrs set successfully. 2460 */ 2461 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2462 struct kvm_msr_entry *entries, 2463 int (*do_msr)(struct kvm_vcpu *vcpu, 2464 unsigned index, u64 *data)) 2465 { 2466 int i, idx; 2467 2468 idx = srcu_read_lock(&vcpu->kvm->srcu); 2469 for (i = 0; i < msrs->nmsrs; ++i) 2470 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2471 break; 2472 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2473 2474 return i; 2475 } 2476 2477 /* 2478 * Read or write a bunch of msrs. Parameters are user addresses. 2479 * 2480 * @return number of msrs set successfully. 2481 */ 2482 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2483 int (*do_msr)(struct kvm_vcpu *vcpu, 2484 unsigned index, u64 *data), 2485 int writeback) 2486 { 2487 struct kvm_msrs msrs; 2488 struct kvm_msr_entry *entries; 2489 int r, n; 2490 unsigned size; 2491 2492 r = -EFAULT; 2493 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2494 goto out; 2495 2496 r = -E2BIG; 2497 if (msrs.nmsrs >= MAX_IO_MSRS) 2498 goto out; 2499 2500 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2501 entries = memdup_user(user_msrs->entries, size); 2502 if (IS_ERR(entries)) { 2503 r = PTR_ERR(entries); 2504 goto out; 2505 } 2506 2507 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2508 if (r < 0) 2509 goto out_free; 2510 2511 r = -EFAULT; 2512 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2513 goto out_free; 2514 2515 r = n; 2516 2517 out_free: 2518 kfree(entries); 2519 out: 2520 return r; 2521 } 2522 2523 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2524 { 2525 int r; 2526 2527 switch (ext) { 2528 case KVM_CAP_IRQCHIP: 2529 case KVM_CAP_HLT: 2530 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2531 case KVM_CAP_SET_TSS_ADDR: 2532 case KVM_CAP_EXT_CPUID: 2533 case KVM_CAP_EXT_EMUL_CPUID: 2534 case KVM_CAP_CLOCKSOURCE: 2535 case KVM_CAP_PIT: 2536 case KVM_CAP_NOP_IO_DELAY: 2537 case KVM_CAP_MP_STATE: 2538 case KVM_CAP_SYNC_MMU: 2539 case KVM_CAP_USER_NMI: 2540 case KVM_CAP_REINJECT_CONTROL: 2541 case KVM_CAP_IRQ_INJECT_STATUS: 2542 case KVM_CAP_IOEVENTFD: 2543 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2544 case KVM_CAP_PIT2: 2545 case KVM_CAP_PIT_STATE2: 2546 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2547 case KVM_CAP_XEN_HVM: 2548 case KVM_CAP_ADJUST_CLOCK: 2549 case KVM_CAP_VCPU_EVENTS: 2550 case KVM_CAP_HYPERV: 2551 case KVM_CAP_HYPERV_VAPIC: 2552 case KVM_CAP_HYPERV_SPIN: 2553 case KVM_CAP_HYPERV_SYNIC: 2554 case KVM_CAP_PCI_SEGMENT: 2555 case KVM_CAP_DEBUGREGS: 2556 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2557 case KVM_CAP_XSAVE: 2558 case KVM_CAP_ASYNC_PF: 2559 case KVM_CAP_GET_TSC_KHZ: 2560 case KVM_CAP_KVMCLOCK_CTRL: 2561 case KVM_CAP_READONLY_MEM: 2562 case KVM_CAP_HYPERV_TIME: 2563 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2564 case KVM_CAP_TSC_DEADLINE_TIMER: 2565 case KVM_CAP_ENABLE_CAP_VM: 2566 case KVM_CAP_DISABLE_QUIRKS: 2567 case KVM_CAP_SET_BOOT_CPU_ID: 2568 case KVM_CAP_SPLIT_IRQCHIP: 2569 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2570 case KVM_CAP_ASSIGN_DEV_IRQ: 2571 case KVM_CAP_PCI_2_3: 2572 #endif 2573 r = 1; 2574 break; 2575 case KVM_CAP_X86_SMM: 2576 /* SMBASE is usually relocated above 1M on modern chipsets, 2577 * and SMM handlers might indeed rely on 4G segment limits, 2578 * so do not report SMM to be available if real mode is 2579 * emulated via vm86 mode. Still, do not go to great lengths 2580 * to avoid userspace's usage of the feature, because it is a 2581 * fringe case that is not enabled except via specific settings 2582 * of the module parameters. 2583 */ 2584 r = kvm_x86_ops->cpu_has_high_real_mode_segbase(); 2585 break; 2586 case KVM_CAP_COALESCED_MMIO: 2587 r = KVM_COALESCED_MMIO_PAGE_OFFSET; 2588 break; 2589 case KVM_CAP_VAPIC: 2590 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2591 break; 2592 case KVM_CAP_NR_VCPUS: 2593 r = KVM_SOFT_MAX_VCPUS; 2594 break; 2595 case KVM_CAP_MAX_VCPUS: 2596 r = KVM_MAX_VCPUS; 2597 break; 2598 case KVM_CAP_NR_MEMSLOTS: 2599 r = KVM_USER_MEM_SLOTS; 2600 break; 2601 case KVM_CAP_PV_MMU: /* obsolete */ 2602 r = 0; 2603 break; 2604 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2605 case KVM_CAP_IOMMU: 2606 r = iommu_present(&pci_bus_type); 2607 break; 2608 #endif 2609 case KVM_CAP_MCE: 2610 r = KVM_MAX_MCE_BANKS; 2611 break; 2612 case KVM_CAP_XCRS: 2613 r = boot_cpu_has(X86_FEATURE_XSAVE); 2614 break; 2615 case KVM_CAP_TSC_CONTROL: 2616 r = kvm_has_tsc_control; 2617 break; 2618 default: 2619 r = 0; 2620 break; 2621 } 2622 return r; 2623 2624 } 2625 2626 long kvm_arch_dev_ioctl(struct file *filp, 2627 unsigned int ioctl, unsigned long arg) 2628 { 2629 void __user *argp = (void __user *)arg; 2630 long r; 2631 2632 switch (ioctl) { 2633 case KVM_GET_MSR_INDEX_LIST: { 2634 struct kvm_msr_list __user *user_msr_list = argp; 2635 struct kvm_msr_list msr_list; 2636 unsigned n; 2637 2638 r = -EFAULT; 2639 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2640 goto out; 2641 n = msr_list.nmsrs; 2642 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 2643 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2644 goto out; 2645 r = -E2BIG; 2646 if (n < msr_list.nmsrs) 2647 goto out; 2648 r = -EFAULT; 2649 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2650 num_msrs_to_save * sizeof(u32))) 2651 goto out; 2652 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2653 &emulated_msrs, 2654 num_emulated_msrs * sizeof(u32))) 2655 goto out; 2656 r = 0; 2657 break; 2658 } 2659 case KVM_GET_SUPPORTED_CPUID: 2660 case KVM_GET_EMULATED_CPUID: { 2661 struct kvm_cpuid2 __user *cpuid_arg = argp; 2662 struct kvm_cpuid2 cpuid; 2663 2664 r = -EFAULT; 2665 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2666 goto out; 2667 2668 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2669 ioctl); 2670 if (r) 2671 goto out; 2672 2673 r = -EFAULT; 2674 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2675 goto out; 2676 r = 0; 2677 break; 2678 } 2679 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2680 u64 mce_cap; 2681 2682 mce_cap = KVM_MCE_CAP_SUPPORTED; 2683 r = -EFAULT; 2684 if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) 2685 goto out; 2686 r = 0; 2687 break; 2688 } 2689 default: 2690 r = -EINVAL; 2691 } 2692 out: 2693 return r; 2694 } 2695 2696 static void wbinvd_ipi(void *garbage) 2697 { 2698 wbinvd(); 2699 } 2700 2701 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 2702 { 2703 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 2704 } 2705 2706 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu) 2707 { 2708 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests); 2709 } 2710 2711 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 2712 { 2713 /* Address WBINVD may be executed by guest */ 2714 if (need_emulate_wbinvd(vcpu)) { 2715 if (kvm_x86_ops->has_wbinvd_exit()) 2716 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 2717 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 2718 smp_call_function_single(vcpu->cpu, 2719 wbinvd_ipi, NULL, 1); 2720 } 2721 2722 kvm_x86_ops->vcpu_load(vcpu, cpu); 2723 2724 /* Apply any externally detected TSC adjustments (due to suspend) */ 2725 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 2726 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 2727 vcpu->arch.tsc_offset_adjustment = 0; 2728 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2729 } 2730 2731 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { 2732 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 2733 rdtsc() - vcpu->arch.last_host_tsc; 2734 if (tsc_delta < 0) 2735 mark_tsc_unstable("KVM discovered backwards TSC"); 2736 if (check_tsc_unstable()) { 2737 u64 offset = kvm_compute_tsc_offset(vcpu, 2738 vcpu->arch.last_guest_tsc); 2739 kvm_x86_ops->write_tsc_offset(vcpu, offset); 2740 vcpu->arch.tsc_catchup = 1; 2741 } 2742 /* 2743 * On a host with synchronized TSC, there is no need to update 2744 * kvmclock on vcpu->cpu migration 2745 */ 2746 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 2747 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2748 if (vcpu->cpu != cpu) 2749 kvm_migrate_timers(vcpu); 2750 vcpu->cpu = cpu; 2751 } 2752 2753 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2754 } 2755 2756 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 2757 { 2758 kvm_x86_ops->vcpu_put(vcpu); 2759 kvm_put_guest_fpu(vcpu); 2760 vcpu->arch.last_host_tsc = rdtsc(); 2761 } 2762 2763 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 2764 struct kvm_lapic_state *s) 2765 { 2766 if (vcpu->arch.apicv_active) 2767 kvm_x86_ops->sync_pir_to_irr(vcpu); 2768 2769 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); 2770 2771 return 0; 2772 } 2773 2774 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 2775 struct kvm_lapic_state *s) 2776 { 2777 kvm_apic_post_state_restore(vcpu, s); 2778 update_cr8_intercept(vcpu); 2779 2780 return 0; 2781 } 2782 2783 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 2784 { 2785 return (!lapic_in_kernel(vcpu) || 2786 kvm_apic_accept_pic_intr(vcpu)); 2787 } 2788 2789 /* 2790 * if userspace requested an interrupt window, check that the 2791 * interrupt window is open. 2792 * 2793 * No need to exit to userspace if we already have an interrupt queued. 2794 */ 2795 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 2796 { 2797 return kvm_arch_interrupt_allowed(vcpu) && 2798 !kvm_cpu_has_interrupt(vcpu) && 2799 !kvm_event_needs_reinjection(vcpu) && 2800 kvm_cpu_accept_dm_intr(vcpu); 2801 } 2802 2803 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 2804 struct kvm_interrupt *irq) 2805 { 2806 if (irq->irq >= KVM_NR_INTERRUPTS) 2807 return -EINVAL; 2808 2809 if (!irqchip_in_kernel(vcpu->kvm)) { 2810 kvm_queue_interrupt(vcpu, irq->irq, false); 2811 kvm_make_request(KVM_REQ_EVENT, vcpu); 2812 return 0; 2813 } 2814 2815 /* 2816 * With in-kernel LAPIC, we only use this to inject EXTINT, so 2817 * fail for in-kernel 8259. 2818 */ 2819 if (pic_in_kernel(vcpu->kvm)) 2820 return -ENXIO; 2821 2822 if (vcpu->arch.pending_external_vector != -1) 2823 return -EEXIST; 2824 2825 vcpu->arch.pending_external_vector = irq->irq; 2826 kvm_make_request(KVM_REQ_EVENT, vcpu); 2827 return 0; 2828 } 2829 2830 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 2831 { 2832 kvm_inject_nmi(vcpu); 2833 2834 return 0; 2835 } 2836 2837 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 2838 { 2839 kvm_make_request(KVM_REQ_SMI, vcpu); 2840 2841 return 0; 2842 } 2843 2844 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 2845 struct kvm_tpr_access_ctl *tac) 2846 { 2847 if (tac->flags) 2848 return -EINVAL; 2849 vcpu->arch.tpr_access_reporting = !!tac->enabled; 2850 return 0; 2851 } 2852 2853 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 2854 u64 mcg_cap) 2855 { 2856 int r; 2857 unsigned bank_num = mcg_cap & 0xff, bank; 2858 2859 r = -EINVAL; 2860 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 2861 goto out; 2862 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) 2863 goto out; 2864 r = 0; 2865 vcpu->arch.mcg_cap = mcg_cap; 2866 /* Init IA32_MCG_CTL to all 1s */ 2867 if (mcg_cap & MCG_CTL_P) 2868 vcpu->arch.mcg_ctl = ~(u64)0; 2869 /* Init IA32_MCi_CTL to all 1s */ 2870 for (bank = 0; bank < bank_num; bank++) 2871 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 2872 out: 2873 return r; 2874 } 2875 2876 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 2877 struct kvm_x86_mce *mce) 2878 { 2879 u64 mcg_cap = vcpu->arch.mcg_cap; 2880 unsigned bank_num = mcg_cap & 0xff; 2881 u64 *banks = vcpu->arch.mce_banks; 2882 2883 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 2884 return -EINVAL; 2885 /* 2886 * if IA32_MCG_CTL is not all 1s, the uncorrected error 2887 * reporting is disabled 2888 */ 2889 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 2890 vcpu->arch.mcg_ctl != ~(u64)0) 2891 return 0; 2892 banks += 4 * mce->bank; 2893 /* 2894 * if IA32_MCi_CTL is not all 1s, the uncorrected error 2895 * reporting is disabled for the bank 2896 */ 2897 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 2898 return 0; 2899 if (mce->status & MCI_STATUS_UC) { 2900 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 2901 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 2902 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 2903 return 0; 2904 } 2905 if (banks[1] & MCI_STATUS_VAL) 2906 mce->status |= MCI_STATUS_OVER; 2907 banks[2] = mce->addr; 2908 banks[3] = mce->misc; 2909 vcpu->arch.mcg_status = mce->mcg_status; 2910 banks[1] = mce->status; 2911 kvm_queue_exception(vcpu, MC_VECTOR); 2912 } else if (!(banks[1] & MCI_STATUS_VAL) 2913 || !(banks[1] & MCI_STATUS_UC)) { 2914 if (banks[1] & MCI_STATUS_VAL) 2915 mce->status |= MCI_STATUS_OVER; 2916 banks[2] = mce->addr; 2917 banks[3] = mce->misc; 2918 banks[1] = mce->status; 2919 } else 2920 banks[1] |= MCI_STATUS_OVER; 2921 return 0; 2922 } 2923 2924 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 2925 struct kvm_vcpu_events *events) 2926 { 2927 process_nmi(vcpu); 2928 events->exception.injected = 2929 vcpu->arch.exception.pending && 2930 !kvm_exception_is_soft(vcpu->arch.exception.nr); 2931 events->exception.nr = vcpu->arch.exception.nr; 2932 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 2933 events->exception.pad = 0; 2934 events->exception.error_code = vcpu->arch.exception.error_code; 2935 2936 events->interrupt.injected = 2937 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; 2938 events->interrupt.nr = vcpu->arch.interrupt.nr; 2939 events->interrupt.soft = 0; 2940 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 2941 2942 events->nmi.injected = vcpu->arch.nmi_injected; 2943 events->nmi.pending = vcpu->arch.nmi_pending != 0; 2944 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 2945 events->nmi.pad = 0; 2946 2947 events->sipi_vector = 0; /* never valid when reporting to user space */ 2948 2949 events->smi.smm = is_smm(vcpu); 2950 events->smi.pending = vcpu->arch.smi_pending; 2951 events->smi.smm_inside_nmi = 2952 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 2953 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 2954 2955 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 2956 | KVM_VCPUEVENT_VALID_SHADOW 2957 | KVM_VCPUEVENT_VALID_SMM); 2958 memset(&events->reserved, 0, sizeof(events->reserved)); 2959 } 2960 2961 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 2962 struct kvm_vcpu_events *events) 2963 { 2964 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 2965 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 2966 | KVM_VCPUEVENT_VALID_SHADOW 2967 | KVM_VCPUEVENT_VALID_SMM)) 2968 return -EINVAL; 2969 2970 if (events->exception.injected && 2971 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 2972 return -EINVAL; 2973 2974 process_nmi(vcpu); 2975 vcpu->arch.exception.pending = events->exception.injected; 2976 vcpu->arch.exception.nr = events->exception.nr; 2977 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 2978 vcpu->arch.exception.error_code = events->exception.error_code; 2979 2980 vcpu->arch.interrupt.pending = events->interrupt.injected; 2981 vcpu->arch.interrupt.nr = events->interrupt.nr; 2982 vcpu->arch.interrupt.soft = events->interrupt.soft; 2983 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 2984 kvm_x86_ops->set_interrupt_shadow(vcpu, 2985 events->interrupt.shadow); 2986 2987 vcpu->arch.nmi_injected = events->nmi.injected; 2988 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 2989 vcpu->arch.nmi_pending = events->nmi.pending; 2990 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 2991 2992 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 2993 lapic_in_kernel(vcpu)) 2994 vcpu->arch.apic->sipi_vector = events->sipi_vector; 2995 2996 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 2997 if (events->smi.smm) 2998 vcpu->arch.hflags |= HF_SMM_MASK; 2999 else 3000 vcpu->arch.hflags &= ~HF_SMM_MASK; 3001 vcpu->arch.smi_pending = events->smi.pending; 3002 if (events->smi.smm_inside_nmi) 3003 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 3004 else 3005 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 3006 if (lapic_in_kernel(vcpu)) { 3007 if (events->smi.latched_init) 3008 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3009 else 3010 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3011 } 3012 } 3013 3014 kvm_make_request(KVM_REQ_EVENT, vcpu); 3015 3016 return 0; 3017 } 3018 3019 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3020 struct kvm_debugregs *dbgregs) 3021 { 3022 unsigned long val; 3023 3024 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3025 kvm_get_dr(vcpu, 6, &val); 3026 dbgregs->dr6 = val; 3027 dbgregs->dr7 = vcpu->arch.dr7; 3028 dbgregs->flags = 0; 3029 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3030 } 3031 3032 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3033 struct kvm_debugregs *dbgregs) 3034 { 3035 if (dbgregs->flags) 3036 return -EINVAL; 3037 3038 if (dbgregs->dr6 & ~0xffffffffull) 3039 return -EINVAL; 3040 if (dbgregs->dr7 & ~0xffffffffull) 3041 return -EINVAL; 3042 3043 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3044 kvm_update_dr0123(vcpu); 3045 vcpu->arch.dr6 = dbgregs->dr6; 3046 kvm_update_dr6(vcpu); 3047 vcpu->arch.dr7 = dbgregs->dr7; 3048 kvm_update_dr7(vcpu); 3049 3050 return 0; 3051 } 3052 3053 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3054 3055 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3056 { 3057 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3058 u64 xstate_bv = xsave->header.xfeatures; 3059 u64 valid; 3060 3061 /* 3062 * Copy legacy XSAVE area, to avoid complications with CPUID 3063 * leaves 0 and 1 in the loop below. 3064 */ 3065 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3066 3067 /* Set XSTATE_BV */ 3068 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3069 3070 /* 3071 * Copy each region from the possibly compacted offset to the 3072 * non-compacted offset. 3073 */ 3074 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3075 while (valid) { 3076 u64 feature = valid & -valid; 3077 int index = fls64(feature) - 1; 3078 void *src = get_xsave_addr(xsave, feature); 3079 3080 if (src) { 3081 u32 size, offset, ecx, edx; 3082 cpuid_count(XSTATE_CPUID, index, 3083 &size, &offset, &ecx, &edx); 3084 memcpy(dest + offset, src, size); 3085 } 3086 3087 valid -= feature; 3088 } 3089 } 3090 3091 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3092 { 3093 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3094 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3095 u64 valid; 3096 3097 /* 3098 * Copy legacy XSAVE area, to avoid complications with CPUID 3099 * leaves 0 and 1 in the loop below. 3100 */ 3101 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3102 3103 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3104 xsave->header.xfeatures = xstate_bv; 3105 if (boot_cpu_has(X86_FEATURE_XSAVES)) 3106 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3107 3108 /* 3109 * Copy each region from the non-compacted offset to the 3110 * possibly compacted offset. 3111 */ 3112 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3113 while (valid) { 3114 u64 feature = valid & -valid; 3115 int index = fls64(feature) - 1; 3116 void *dest = get_xsave_addr(xsave, feature); 3117 3118 if (dest) { 3119 u32 size, offset, ecx, edx; 3120 cpuid_count(XSTATE_CPUID, index, 3121 &size, &offset, &ecx, &edx); 3122 memcpy(dest, src + offset, size); 3123 } 3124 3125 valid -= feature; 3126 } 3127 } 3128 3129 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3130 struct kvm_xsave *guest_xsave) 3131 { 3132 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3133 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3134 fill_xsave((u8 *) guest_xsave->region, vcpu); 3135 } else { 3136 memcpy(guest_xsave->region, 3137 &vcpu->arch.guest_fpu.state.fxsave, 3138 sizeof(struct fxregs_state)); 3139 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3140 XFEATURE_MASK_FPSSE; 3141 } 3142 } 3143 3144 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3145 struct kvm_xsave *guest_xsave) 3146 { 3147 u64 xstate_bv = 3148 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3149 3150 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3151 /* 3152 * Here we allow setting states that are not present in 3153 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3154 * with old userspace. 3155 */ 3156 if (xstate_bv & ~kvm_supported_xcr0()) 3157 return -EINVAL; 3158 load_xsave(vcpu, (u8 *)guest_xsave->region); 3159 } else { 3160 if (xstate_bv & ~XFEATURE_MASK_FPSSE) 3161 return -EINVAL; 3162 memcpy(&vcpu->arch.guest_fpu.state.fxsave, 3163 guest_xsave->region, sizeof(struct fxregs_state)); 3164 } 3165 return 0; 3166 } 3167 3168 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3169 struct kvm_xcrs *guest_xcrs) 3170 { 3171 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 3172 guest_xcrs->nr_xcrs = 0; 3173 return; 3174 } 3175 3176 guest_xcrs->nr_xcrs = 1; 3177 guest_xcrs->flags = 0; 3178 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3179 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3180 } 3181 3182 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3183 struct kvm_xcrs *guest_xcrs) 3184 { 3185 int i, r = 0; 3186 3187 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 3188 return -EINVAL; 3189 3190 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3191 return -EINVAL; 3192 3193 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3194 /* Only support XCR0 currently */ 3195 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3196 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3197 guest_xcrs->xcrs[i].value); 3198 break; 3199 } 3200 if (r) 3201 r = -EINVAL; 3202 return r; 3203 } 3204 3205 /* 3206 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3207 * stopped by the hypervisor. This function will be called from the host only. 3208 * EINVAL is returned when the host attempts to set the flag for a guest that 3209 * does not support pv clocks. 3210 */ 3211 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3212 { 3213 if (!vcpu->arch.pv_time_enabled) 3214 return -EINVAL; 3215 vcpu->arch.pvclock_set_guest_stopped_request = true; 3216 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3217 return 0; 3218 } 3219 3220 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 3221 struct kvm_enable_cap *cap) 3222 { 3223 if (cap->flags) 3224 return -EINVAL; 3225 3226 switch (cap->cap) { 3227 case KVM_CAP_HYPERV_SYNIC: 3228 return kvm_hv_activate_synic(vcpu); 3229 default: 3230 return -EINVAL; 3231 } 3232 } 3233 3234 long kvm_arch_vcpu_ioctl(struct file *filp, 3235 unsigned int ioctl, unsigned long arg) 3236 { 3237 struct kvm_vcpu *vcpu = filp->private_data; 3238 void __user *argp = (void __user *)arg; 3239 int r; 3240 union { 3241 struct kvm_lapic_state *lapic; 3242 struct kvm_xsave *xsave; 3243 struct kvm_xcrs *xcrs; 3244 void *buffer; 3245 } u; 3246 3247 u.buffer = NULL; 3248 switch (ioctl) { 3249 case KVM_GET_LAPIC: { 3250 r = -EINVAL; 3251 if (!lapic_in_kernel(vcpu)) 3252 goto out; 3253 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3254 3255 r = -ENOMEM; 3256 if (!u.lapic) 3257 goto out; 3258 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3259 if (r) 3260 goto out; 3261 r = -EFAULT; 3262 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3263 goto out; 3264 r = 0; 3265 break; 3266 } 3267 case KVM_SET_LAPIC: { 3268 r = -EINVAL; 3269 if (!lapic_in_kernel(vcpu)) 3270 goto out; 3271 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3272 if (IS_ERR(u.lapic)) 3273 return PTR_ERR(u.lapic); 3274 3275 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3276 break; 3277 } 3278 case KVM_INTERRUPT: { 3279 struct kvm_interrupt irq; 3280 3281 r = -EFAULT; 3282 if (copy_from_user(&irq, argp, sizeof irq)) 3283 goto out; 3284 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3285 break; 3286 } 3287 case KVM_NMI: { 3288 r = kvm_vcpu_ioctl_nmi(vcpu); 3289 break; 3290 } 3291 case KVM_SMI: { 3292 r = kvm_vcpu_ioctl_smi(vcpu); 3293 break; 3294 } 3295 case KVM_SET_CPUID: { 3296 struct kvm_cpuid __user *cpuid_arg = argp; 3297 struct kvm_cpuid cpuid; 3298 3299 r = -EFAULT; 3300 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3301 goto out; 3302 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3303 break; 3304 } 3305 case KVM_SET_CPUID2: { 3306 struct kvm_cpuid2 __user *cpuid_arg = argp; 3307 struct kvm_cpuid2 cpuid; 3308 3309 r = -EFAULT; 3310 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3311 goto out; 3312 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3313 cpuid_arg->entries); 3314 break; 3315 } 3316 case KVM_GET_CPUID2: { 3317 struct kvm_cpuid2 __user *cpuid_arg = argp; 3318 struct kvm_cpuid2 cpuid; 3319 3320 r = -EFAULT; 3321 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3322 goto out; 3323 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3324 cpuid_arg->entries); 3325 if (r) 3326 goto out; 3327 r = -EFAULT; 3328 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3329 goto out; 3330 r = 0; 3331 break; 3332 } 3333 case KVM_GET_MSRS: 3334 r = msr_io(vcpu, argp, do_get_msr, 1); 3335 break; 3336 case KVM_SET_MSRS: 3337 r = msr_io(vcpu, argp, do_set_msr, 0); 3338 break; 3339 case KVM_TPR_ACCESS_REPORTING: { 3340 struct kvm_tpr_access_ctl tac; 3341 3342 r = -EFAULT; 3343 if (copy_from_user(&tac, argp, sizeof tac)) 3344 goto out; 3345 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3346 if (r) 3347 goto out; 3348 r = -EFAULT; 3349 if (copy_to_user(argp, &tac, sizeof tac)) 3350 goto out; 3351 r = 0; 3352 break; 3353 }; 3354 case KVM_SET_VAPIC_ADDR: { 3355 struct kvm_vapic_addr va; 3356 3357 r = -EINVAL; 3358 if (!lapic_in_kernel(vcpu)) 3359 goto out; 3360 r = -EFAULT; 3361 if (copy_from_user(&va, argp, sizeof va)) 3362 goto out; 3363 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3364 break; 3365 } 3366 case KVM_X86_SETUP_MCE: { 3367 u64 mcg_cap; 3368 3369 r = -EFAULT; 3370 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3371 goto out; 3372 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3373 break; 3374 } 3375 case KVM_X86_SET_MCE: { 3376 struct kvm_x86_mce mce; 3377 3378 r = -EFAULT; 3379 if (copy_from_user(&mce, argp, sizeof mce)) 3380 goto out; 3381 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3382 break; 3383 } 3384 case KVM_GET_VCPU_EVENTS: { 3385 struct kvm_vcpu_events events; 3386 3387 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3388 3389 r = -EFAULT; 3390 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3391 break; 3392 r = 0; 3393 break; 3394 } 3395 case KVM_SET_VCPU_EVENTS: { 3396 struct kvm_vcpu_events events; 3397 3398 r = -EFAULT; 3399 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3400 break; 3401 3402 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3403 break; 3404 } 3405 case KVM_GET_DEBUGREGS: { 3406 struct kvm_debugregs dbgregs; 3407 3408 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3409 3410 r = -EFAULT; 3411 if (copy_to_user(argp, &dbgregs, 3412 sizeof(struct kvm_debugregs))) 3413 break; 3414 r = 0; 3415 break; 3416 } 3417 case KVM_SET_DEBUGREGS: { 3418 struct kvm_debugregs dbgregs; 3419 3420 r = -EFAULT; 3421 if (copy_from_user(&dbgregs, argp, 3422 sizeof(struct kvm_debugregs))) 3423 break; 3424 3425 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3426 break; 3427 } 3428 case KVM_GET_XSAVE: { 3429 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3430 r = -ENOMEM; 3431 if (!u.xsave) 3432 break; 3433 3434 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3435 3436 r = -EFAULT; 3437 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3438 break; 3439 r = 0; 3440 break; 3441 } 3442 case KVM_SET_XSAVE: { 3443 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3444 if (IS_ERR(u.xsave)) 3445 return PTR_ERR(u.xsave); 3446 3447 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3448 break; 3449 } 3450 case KVM_GET_XCRS: { 3451 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3452 r = -ENOMEM; 3453 if (!u.xcrs) 3454 break; 3455 3456 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3457 3458 r = -EFAULT; 3459 if (copy_to_user(argp, u.xcrs, 3460 sizeof(struct kvm_xcrs))) 3461 break; 3462 r = 0; 3463 break; 3464 } 3465 case KVM_SET_XCRS: { 3466 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3467 if (IS_ERR(u.xcrs)) 3468 return PTR_ERR(u.xcrs); 3469 3470 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3471 break; 3472 } 3473 case KVM_SET_TSC_KHZ: { 3474 u32 user_tsc_khz; 3475 3476 r = -EINVAL; 3477 user_tsc_khz = (u32)arg; 3478 3479 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3480 goto out; 3481 3482 if (user_tsc_khz == 0) 3483 user_tsc_khz = tsc_khz; 3484 3485 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 3486 r = 0; 3487 3488 goto out; 3489 } 3490 case KVM_GET_TSC_KHZ: { 3491 r = vcpu->arch.virtual_tsc_khz; 3492 goto out; 3493 } 3494 case KVM_KVMCLOCK_CTRL: { 3495 r = kvm_set_guest_paused(vcpu); 3496 goto out; 3497 } 3498 case KVM_ENABLE_CAP: { 3499 struct kvm_enable_cap cap; 3500 3501 r = -EFAULT; 3502 if (copy_from_user(&cap, argp, sizeof(cap))) 3503 goto out; 3504 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 3505 break; 3506 } 3507 default: 3508 r = -EINVAL; 3509 } 3510 out: 3511 kfree(u.buffer); 3512 return r; 3513 } 3514 3515 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3516 { 3517 return VM_FAULT_SIGBUS; 3518 } 3519 3520 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3521 { 3522 int ret; 3523 3524 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3525 return -EINVAL; 3526 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3527 return ret; 3528 } 3529 3530 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3531 u64 ident_addr) 3532 { 3533 kvm->arch.ept_identity_map_addr = ident_addr; 3534 return 0; 3535 } 3536 3537 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3538 u32 kvm_nr_mmu_pages) 3539 { 3540 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3541 return -EINVAL; 3542 3543 mutex_lock(&kvm->slots_lock); 3544 3545 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3546 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3547 3548 mutex_unlock(&kvm->slots_lock); 3549 return 0; 3550 } 3551 3552 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 3553 { 3554 return kvm->arch.n_max_mmu_pages; 3555 } 3556 3557 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3558 { 3559 int r; 3560 3561 r = 0; 3562 switch (chip->chip_id) { 3563 case KVM_IRQCHIP_PIC_MASTER: 3564 memcpy(&chip->chip.pic, 3565 &pic_irqchip(kvm)->pics[0], 3566 sizeof(struct kvm_pic_state)); 3567 break; 3568 case KVM_IRQCHIP_PIC_SLAVE: 3569 memcpy(&chip->chip.pic, 3570 &pic_irqchip(kvm)->pics[1], 3571 sizeof(struct kvm_pic_state)); 3572 break; 3573 case KVM_IRQCHIP_IOAPIC: 3574 r = kvm_get_ioapic(kvm, &chip->chip.ioapic); 3575 break; 3576 default: 3577 r = -EINVAL; 3578 break; 3579 } 3580 return r; 3581 } 3582 3583 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3584 { 3585 int r; 3586 3587 r = 0; 3588 switch (chip->chip_id) { 3589 case KVM_IRQCHIP_PIC_MASTER: 3590 spin_lock(&pic_irqchip(kvm)->lock); 3591 memcpy(&pic_irqchip(kvm)->pics[0], 3592 &chip->chip.pic, 3593 sizeof(struct kvm_pic_state)); 3594 spin_unlock(&pic_irqchip(kvm)->lock); 3595 break; 3596 case KVM_IRQCHIP_PIC_SLAVE: 3597 spin_lock(&pic_irqchip(kvm)->lock); 3598 memcpy(&pic_irqchip(kvm)->pics[1], 3599 &chip->chip.pic, 3600 sizeof(struct kvm_pic_state)); 3601 spin_unlock(&pic_irqchip(kvm)->lock); 3602 break; 3603 case KVM_IRQCHIP_IOAPIC: 3604 r = kvm_set_ioapic(kvm, &chip->chip.ioapic); 3605 break; 3606 default: 3607 r = -EINVAL; 3608 break; 3609 } 3610 kvm_pic_update_irq(pic_irqchip(kvm)); 3611 return r; 3612 } 3613 3614 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3615 { 3616 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 3617 3618 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 3619 3620 mutex_lock(&kps->lock); 3621 memcpy(ps, &kps->channels, sizeof(*ps)); 3622 mutex_unlock(&kps->lock); 3623 return 0; 3624 } 3625 3626 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3627 { 3628 int i; 3629 struct kvm_pit *pit = kvm->arch.vpit; 3630 3631 mutex_lock(&pit->pit_state.lock); 3632 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 3633 for (i = 0; i < 3; i++) 3634 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 3635 mutex_unlock(&pit->pit_state.lock); 3636 return 0; 3637 } 3638 3639 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3640 { 3641 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3642 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 3643 sizeof(ps->channels)); 3644 ps->flags = kvm->arch.vpit->pit_state.flags; 3645 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3646 memset(&ps->reserved, 0, sizeof(ps->reserved)); 3647 return 0; 3648 } 3649 3650 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3651 { 3652 int start = 0; 3653 int i; 3654 u32 prev_legacy, cur_legacy; 3655 struct kvm_pit *pit = kvm->arch.vpit; 3656 3657 mutex_lock(&pit->pit_state.lock); 3658 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 3659 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 3660 if (!prev_legacy && cur_legacy) 3661 start = 1; 3662 memcpy(&pit->pit_state.channels, &ps->channels, 3663 sizeof(pit->pit_state.channels)); 3664 pit->pit_state.flags = ps->flags; 3665 for (i = 0; i < 3; i++) 3666 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 3667 start && i == 0); 3668 mutex_unlock(&pit->pit_state.lock); 3669 return 0; 3670 } 3671 3672 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 3673 struct kvm_reinject_control *control) 3674 { 3675 struct kvm_pit *pit = kvm->arch.vpit; 3676 3677 if (!pit) 3678 return -ENXIO; 3679 3680 /* pit->pit_state.lock was overloaded to prevent userspace from getting 3681 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 3682 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 3683 */ 3684 mutex_lock(&pit->pit_state.lock); 3685 kvm_pit_set_reinject(pit, control->pit_reinject); 3686 mutex_unlock(&pit->pit_state.lock); 3687 3688 return 0; 3689 } 3690 3691 /** 3692 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 3693 * @kvm: kvm instance 3694 * @log: slot id and address to which we copy the log 3695 * 3696 * Steps 1-4 below provide general overview of dirty page logging. See 3697 * kvm_get_dirty_log_protect() function description for additional details. 3698 * 3699 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 3700 * always flush the TLB (step 4) even if previous step failed and the dirty 3701 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 3702 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 3703 * writes will be marked dirty for next log read. 3704 * 3705 * 1. Take a snapshot of the bit and clear it if needed. 3706 * 2. Write protect the corresponding page. 3707 * 3. Copy the snapshot to the userspace. 3708 * 4. Flush TLB's if needed. 3709 */ 3710 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 3711 { 3712 bool is_dirty = false; 3713 int r; 3714 3715 mutex_lock(&kvm->slots_lock); 3716 3717 /* 3718 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 3719 */ 3720 if (kvm_x86_ops->flush_log_dirty) 3721 kvm_x86_ops->flush_log_dirty(kvm); 3722 3723 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 3724 3725 /* 3726 * All the TLBs can be flushed out of mmu lock, see the comments in 3727 * kvm_mmu_slot_remove_write_access(). 3728 */ 3729 lockdep_assert_held(&kvm->slots_lock); 3730 if (is_dirty) 3731 kvm_flush_remote_tlbs(kvm); 3732 3733 mutex_unlock(&kvm->slots_lock); 3734 return r; 3735 } 3736 3737 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 3738 bool line_status) 3739 { 3740 if (!irqchip_in_kernel(kvm)) 3741 return -ENXIO; 3742 3743 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 3744 irq_event->irq, irq_event->level, 3745 line_status); 3746 return 0; 3747 } 3748 3749 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 3750 struct kvm_enable_cap *cap) 3751 { 3752 int r; 3753 3754 if (cap->flags) 3755 return -EINVAL; 3756 3757 switch (cap->cap) { 3758 case KVM_CAP_DISABLE_QUIRKS: 3759 kvm->arch.disabled_quirks = cap->args[0]; 3760 r = 0; 3761 break; 3762 case KVM_CAP_SPLIT_IRQCHIP: { 3763 mutex_lock(&kvm->lock); 3764 r = -EINVAL; 3765 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 3766 goto split_irqchip_unlock; 3767 r = -EEXIST; 3768 if (irqchip_in_kernel(kvm)) 3769 goto split_irqchip_unlock; 3770 if (atomic_read(&kvm->online_vcpus)) 3771 goto split_irqchip_unlock; 3772 r = kvm_setup_empty_irq_routing(kvm); 3773 if (r) 3774 goto split_irqchip_unlock; 3775 /* Pairs with irqchip_in_kernel. */ 3776 smp_wmb(); 3777 kvm->arch.irqchip_split = true; 3778 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 3779 r = 0; 3780 split_irqchip_unlock: 3781 mutex_unlock(&kvm->lock); 3782 break; 3783 } 3784 default: 3785 r = -EINVAL; 3786 break; 3787 } 3788 return r; 3789 } 3790 3791 long kvm_arch_vm_ioctl(struct file *filp, 3792 unsigned int ioctl, unsigned long arg) 3793 { 3794 struct kvm *kvm = filp->private_data; 3795 void __user *argp = (void __user *)arg; 3796 int r = -ENOTTY; 3797 /* 3798 * This union makes it completely explicit to gcc-3.x 3799 * that these two variables' stack usage should be 3800 * combined, not added together. 3801 */ 3802 union { 3803 struct kvm_pit_state ps; 3804 struct kvm_pit_state2 ps2; 3805 struct kvm_pit_config pit_config; 3806 } u; 3807 3808 switch (ioctl) { 3809 case KVM_SET_TSS_ADDR: 3810 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 3811 break; 3812 case KVM_SET_IDENTITY_MAP_ADDR: { 3813 u64 ident_addr; 3814 3815 r = -EFAULT; 3816 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 3817 goto out; 3818 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 3819 break; 3820 } 3821 case KVM_SET_NR_MMU_PAGES: 3822 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 3823 break; 3824 case KVM_GET_NR_MMU_PAGES: 3825 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 3826 break; 3827 case KVM_CREATE_IRQCHIP: { 3828 struct kvm_pic *vpic; 3829 3830 mutex_lock(&kvm->lock); 3831 r = -EEXIST; 3832 if (kvm->arch.vpic) 3833 goto create_irqchip_unlock; 3834 r = -EINVAL; 3835 if (atomic_read(&kvm->online_vcpus)) 3836 goto create_irqchip_unlock; 3837 r = -ENOMEM; 3838 vpic = kvm_create_pic(kvm); 3839 if (vpic) { 3840 r = kvm_ioapic_init(kvm); 3841 if (r) { 3842 mutex_lock(&kvm->slots_lock); 3843 kvm_destroy_pic(vpic); 3844 mutex_unlock(&kvm->slots_lock); 3845 goto create_irqchip_unlock; 3846 } 3847 } else 3848 goto create_irqchip_unlock; 3849 r = kvm_setup_default_irq_routing(kvm); 3850 if (r) { 3851 mutex_lock(&kvm->slots_lock); 3852 mutex_lock(&kvm->irq_lock); 3853 kvm_ioapic_destroy(kvm); 3854 kvm_destroy_pic(vpic); 3855 mutex_unlock(&kvm->irq_lock); 3856 mutex_unlock(&kvm->slots_lock); 3857 goto create_irqchip_unlock; 3858 } 3859 /* Write kvm->irq_routing before kvm->arch.vpic. */ 3860 smp_wmb(); 3861 kvm->arch.vpic = vpic; 3862 create_irqchip_unlock: 3863 mutex_unlock(&kvm->lock); 3864 break; 3865 } 3866 case KVM_CREATE_PIT: 3867 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 3868 goto create_pit; 3869 case KVM_CREATE_PIT2: 3870 r = -EFAULT; 3871 if (copy_from_user(&u.pit_config, argp, 3872 sizeof(struct kvm_pit_config))) 3873 goto out; 3874 create_pit: 3875 mutex_lock(&kvm->slots_lock); 3876 r = -EEXIST; 3877 if (kvm->arch.vpit) 3878 goto create_pit_unlock; 3879 r = -ENOMEM; 3880 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 3881 if (kvm->arch.vpit) 3882 r = 0; 3883 create_pit_unlock: 3884 mutex_unlock(&kvm->slots_lock); 3885 break; 3886 case KVM_GET_IRQCHIP: { 3887 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3888 struct kvm_irqchip *chip; 3889 3890 chip = memdup_user(argp, sizeof(*chip)); 3891 if (IS_ERR(chip)) { 3892 r = PTR_ERR(chip); 3893 goto out; 3894 } 3895 3896 r = -ENXIO; 3897 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm)) 3898 goto get_irqchip_out; 3899 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 3900 if (r) 3901 goto get_irqchip_out; 3902 r = -EFAULT; 3903 if (copy_to_user(argp, chip, sizeof *chip)) 3904 goto get_irqchip_out; 3905 r = 0; 3906 get_irqchip_out: 3907 kfree(chip); 3908 break; 3909 } 3910 case KVM_SET_IRQCHIP: { 3911 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3912 struct kvm_irqchip *chip; 3913 3914 chip = memdup_user(argp, sizeof(*chip)); 3915 if (IS_ERR(chip)) { 3916 r = PTR_ERR(chip); 3917 goto out; 3918 } 3919 3920 r = -ENXIO; 3921 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm)) 3922 goto set_irqchip_out; 3923 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 3924 if (r) 3925 goto set_irqchip_out; 3926 r = 0; 3927 set_irqchip_out: 3928 kfree(chip); 3929 break; 3930 } 3931 case KVM_GET_PIT: { 3932 r = -EFAULT; 3933 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 3934 goto out; 3935 r = -ENXIO; 3936 if (!kvm->arch.vpit) 3937 goto out; 3938 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 3939 if (r) 3940 goto out; 3941 r = -EFAULT; 3942 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 3943 goto out; 3944 r = 0; 3945 break; 3946 } 3947 case KVM_SET_PIT: { 3948 r = -EFAULT; 3949 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 3950 goto out; 3951 r = -ENXIO; 3952 if (!kvm->arch.vpit) 3953 goto out; 3954 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 3955 break; 3956 } 3957 case KVM_GET_PIT2: { 3958 r = -ENXIO; 3959 if (!kvm->arch.vpit) 3960 goto out; 3961 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 3962 if (r) 3963 goto out; 3964 r = -EFAULT; 3965 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 3966 goto out; 3967 r = 0; 3968 break; 3969 } 3970 case KVM_SET_PIT2: { 3971 r = -EFAULT; 3972 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 3973 goto out; 3974 r = -ENXIO; 3975 if (!kvm->arch.vpit) 3976 goto out; 3977 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 3978 break; 3979 } 3980 case KVM_REINJECT_CONTROL: { 3981 struct kvm_reinject_control control; 3982 r = -EFAULT; 3983 if (copy_from_user(&control, argp, sizeof(control))) 3984 goto out; 3985 r = kvm_vm_ioctl_reinject(kvm, &control); 3986 break; 3987 } 3988 case KVM_SET_BOOT_CPU_ID: 3989 r = 0; 3990 mutex_lock(&kvm->lock); 3991 if (atomic_read(&kvm->online_vcpus) != 0) 3992 r = -EBUSY; 3993 else 3994 kvm->arch.bsp_vcpu_id = arg; 3995 mutex_unlock(&kvm->lock); 3996 break; 3997 case KVM_XEN_HVM_CONFIG: { 3998 r = -EFAULT; 3999 if (copy_from_user(&kvm->arch.xen_hvm_config, argp, 4000 sizeof(struct kvm_xen_hvm_config))) 4001 goto out; 4002 r = -EINVAL; 4003 if (kvm->arch.xen_hvm_config.flags) 4004 goto out; 4005 r = 0; 4006 break; 4007 } 4008 case KVM_SET_CLOCK: { 4009 struct kvm_clock_data user_ns; 4010 u64 now_ns; 4011 s64 delta; 4012 4013 r = -EFAULT; 4014 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 4015 goto out; 4016 4017 r = -EINVAL; 4018 if (user_ns.flags) 4019 goto out; 4020 4021 r = 0; 4022 local_irq_disable(); 4023 now_ns = get_kernel_ns(); 4024 delta = user_ns.clock - now_ns; 4025 local_irq_enable(); 4026 kvm->arch.kvmclock_offset = delta; 4027 kvm_gen_update_masterclock(kvm); 4028 break; 4029 } 4030 case KVM_GET_CLOCK: { 4031 struct kvm_clock_data user_ns; 4032 u64 now_ns; 4033 4034 local_irq_disable(); 4035 now_ns = get_kernel_ns(); 4036 user_ns.clock = kvm->arch.kvmclock_offset + now_ns; 4037 local_irq_enable(); 4038 user_ns.flags = 0; 4039 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 4040 4041 r = -EFAULT; 4042 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 4043 goto out; 4044 r = 0; 4045 break; 4046 } 4047 case KVM_ENABLE_CAP: { 4048 struct kvm_enable_cap cap; 4049 4050 r = -EFAULT; 4051 if (copy_from_user(&cap, argp, sizeof(cap))) 4052 goto out; 4053 r = kvm_vm_ioctl_enable_cap(kvm, &cap); 4054 break; 4055 } 4056 default: 4057 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg); 4058 } 4059 out: 4060 return r; 4061 } 4062 4063 static void kvm_init_msr_list(void) 4064 { 4065 u32 dummy[2]; 4066 unsigned i, j; 4067 4068 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { 4069 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4070 continue; 4071 4072 /* 4073 * Even MSRs that are valid in the host may not be exposed 4074 * to the guests in some cases. 4075 */ 4076 switch (msrs_to_save[i]) { 4077 case MSR_IA32_BNDCFGS: 4078 if (!kvm_x86_ops->mpx_supported()) 4079 continue; 4080 break; 4081 case MSR_TSC_AUX: 4082 if (!kvm_x86_ops->rdtscp_supported()) 4083 continue; 4084 break; 4085 default: 4086 break; 4087 } 4088 4089 if (j < i) 4090 msrs_to_save[j] = msrs_to_save[i]; 4091 j++; 4092 } 4093 num_msrs_to_save = j; 4094 4095 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { 4096 switch (emulated_msrs[i]) { 4097 case MSR_IA32_SMBASE: 4098 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase()) 4099 continue; 4100 break; 4101 default: 4102 break; 4103 } 4104 4105 if (j < i) 4106 emulated_msrs[j] = emulated_msrs[i]; 4107 j++; 4108 } 4109 num_emulated_msrs = j; 4110 } 4111 4112 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 4113 const void *v) 4114 { 4115 int handled = 0; 4116 int n; 4117 4118 do { 4119 n = min(len, 8); 4120 if (!(lapic_in_kernel(vcpu) && 4121 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 4122 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 4123 break; 4124 handled += n; 4125 addr += n; 4126 len -= n; 4127 v += n; 4128 } while (len); 4129 4130 return handled; 4131 } 4132 4133 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4134 { 4135 int handled = 0; 4136 int n; 4137 4138 do { 4139 n = min(len, 8); 4140 if (!(lapic_in_kernel(vcpu) && 4141 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 4142 addr, n, v)) 4143 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 4144 break; 4145 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); 4146 handled += n; 4147 addr += n; 4148 len -= n; 4149 v += n; 4150 } while (len); 4151 4152 return handled; 4153 } 4154 4155 static void kvm_set_segment(struct kvm_vcpu *vcpu, 4156 struct kvm_segment *var, int seg) 4157 { 4158 kvm_x86_ops->set_segment(vcpu, var, seg); 4159 } 4160 4161 void kvm_get_segment(struct kvm_vcpu *vcpu, 4162 struct kvm_segment *var, int seg) 4163 { 4164 kvm_x86_ops->get_segment(vcpu, var, seg); 4165 } 4166 4167 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 4168 struct x86_exception *exception) 4169 { 4170 gpa_t t_gpa; 4171 4172 BUG_ON(!mmu_is_nested(vcpu)); 4173 4174 /* NPT walks are always user-walks */ 4175 access |= PFERR_USER_MASK; 4176 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); 4177 4178 return t_gpa; 4179 } 4180 4181 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 4182 struct x86_exception *exception) 4183 { 4184 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4185 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4186 } 4187 4188 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 4189 struct x86_exception *exception) 4190 { 4191 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4192 access |= PFERR_FETCH_MASK; 4193 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4194 } 4195 4196 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 4197 struct x86_exception *exception) 4198 { 4199 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4200 access |= PFERR_WRITE_MASK; 4201 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4202 } 4203 4204 /* uses this to access any guest's mapped memory without checking CPL */ 4205 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 4206 struct x86_exception *exception) 4207 { 4208 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 4209 } 4210 4211 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 4212 struct kvm_vcpu *vcpu, u32 access, 4213 struct x86_exception *exception) 4214 { 4215 void *data = val; 4216 int r = X86EMUL_CONTINUE; 4217 4218 while (bytes) { 4219 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 4220 exception); 4221 unsigned offset = addr & (PAGE_SIZE-1); 4222 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 4223 int ret; 4224 4225 if (gpa == UNMAPPED_GVA) 4226 return X86EMUL_PROPAGATE_FAULT; 4227 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 4228 offset, toread); 4229 if (ret < 0) { 4230 r = X86EMUL_IO_NEEDED; 4231 goto out; 4232 } 4233 4234 bytes -= toread; 4235 data += toread; 4236 addr += toread; 4237 } 4238 out: 4239 return r; 4240 } 4241 4242 /* used for instruction fetching */ 4243 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4244 gva_t addr, void *val, unsigned int bytes, 4245 struct x86_exception *exception) 4246 { 4247 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4248 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4249 unsigned offset; 4250 int ret; 4251 4252 /* Inline kvm_read_guest_virt_helper for speed. */ 4253 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 4254 exception); 4255 if (unlikely(gpa == UNMAPPED_GVA)) 4256 return X86EMUL_PROPAGATE_FAULT; 4257 4258 offset = addr & (PAGE_SIZE-1); 4259 if (WARN_ON(offset + bytes > PAGE_SIZE)) 4260 bytes = (unsigned)PAGE_SIZE - offset; 4261 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 4262 offset, bytes); 4263 if (unlikely(ret < 0)) 4264 return X86EMUL_IO_NEEDED; 4265 4266 return X86EMUL_CONTINUE; 4267 } 4268 4269 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4270 gva_t addr, void *val, unsigned int bytes, 4271 struct x86_exception *exception) 4272 { 4273 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4274 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4275 4276 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4277 exception); 4278 } 4279 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4280 4281 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4282 gva_t addr, void *val, unsigned int bytes, 4283 struct x86_exception *exception) 4284 { 4285 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4286 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4287 } 4288 4289 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 4290 unsigned long addr, void *val, unsigned int bytes) 4291 { 4292 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4293 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 4294 4295 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 4296 } 4297 4298 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4299 gva_t addr, void *val, 4300 unsigned int bytes, 4301 struct x86_exception *exception) 4302 { 4303 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4304 void *data = val; 4305 int r = X86EMUL_CONTINUE; 4306 4307 while (bytes) { 4308 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4309 PFERR_WRITE_MASK, 4310 exception); 4311 unsigned offset = addr & (PAGE_SIZE-1); 4312 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4313 int ret; 4314 4315 if (gpa == UNMAPPED_GVA) 4316 return X86EMUL_PROPAGATE_FAULT; 4317 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 4318 if (ret < 0) { 4319 r = X86EMUL_IO_NEEDED; 4320 goto out; 4321 } 4322 4323 bytes -= towrite; 4324 data += towrite; 4325 addr += towrite; 4326 } 4327 out: 4328 return r; 4329 } 4330 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4331 4332 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4333 gpa_t *gpa, struct x86_exception *exception, 4334 bool write) 4335 { 4336 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4337 | (write ? PFERR_WRITE_MASK : 0); 4338 4339 /* 4340 * currently PKRU is only applied to ept enabled guest so 4341 * there is no pkey in EPT page table for L1 guest or EPT 4342 * shadow page table for L2 guest. 4343 */ 4344 if (vcpu_match_mmio_gva(vcpu, gva) 4345 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4346 vcpu->arch.access, 0, access)) { 4347 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4348 (gva & (PAGE_SIZE - 1)); 4349 trace_vcpu_match_mmio(gva, *gpa, write, false); 4350 return 1; 4351 } 4352 4353 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4354 4355 if (*gpa == UNMAPPED_GVA) 4356 return -1; 4357 4358 /* For APIC access vmexit */ 4359 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4360 return 1; 4361 4362 if (vcpu_match_mmio_gpa(vcpu, *gpa)) { 4363 trace_vcpu_match_mmio(gva, *gpa, write, true); 4364 return 1; 4365 } 4366 4367 return 0; 4368 } 4369 4370 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4371 const void *val, int bytes) 4372 { 4373 int ret; 4374 4375 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 4376 if (ret < 0) 4377 return 0; 4378 kvm_page_track_write(vcpu, gpa, val, bytes); 4379 return 1; 4380 } 4381 4382 struct read_write_emulator_ops { 4383 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4384 int bytes); 4385 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4386 void *val, int bytes); 4387 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4388 int bytes, void *val); 4389 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4390 void *val, int bytes); 4391 bool write; 4392 }; 4393 4394 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4395 { 4396 if (vcpu->mmio_read_completed) { 4397 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4398 vcpu->mmio_fragments[0].gpa, *(u64 *)val); 4399 vcpu->mmio_read_completed = 0; 4400 return 1; 4401 } 4402 4403 return 0; 4404 } 4405 4406 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4407 void *val, int bytes) 4408 { 4409 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 4410 } 4411 4412 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4413 void *val, int bytes) 4414 { 4415 return emulator_write_phys(vcpu, gpa, val, bytes); 4416 } 4417 4418 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4419 { 4420 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); 4421 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4422 } 4423 4424 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4425 void *val, int bytes) 4426 { 4427 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); 4428 return X86EMUL_IO_NEEDED; 4429 } 4430 4431 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4432 void *val, int bytes) 4433 { 4434 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4435 4436 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4437 return X86EMUL_CONTINUE; 4438 } 4439 4440 static const struct read_write_emulator_ops read_emultor = { 4441 .read_write_prepare = read_prepare, 4442 .read_write_emulate = read_emulate, 4443 .read_write_mmio = vcpu_mmio_read, 4444 .read_write_exit_mmio = read_exit_mmio, 4445 }; 4446 4447 static const struct read_write_emulator_ops write_emultor = { 4448 .read_write_emulate = write_emulate, 4449 .read_write_mmio = write_mmio, 4450 .read_write_exit_mmio = write_exit_mmio, 4451 .write = true, 4452 }; 4453 4454 static int emulator_read_write_onepage(unsigned long addr, void *val, 4455 unsigned int bytes, 4456 struct x86_exception *exception, 4457 struct kvm_vcpu *vcpu, 4458 const struct read_write_emulator_ops *ops) 4459 { 4460 gpa_t gpa; 4461 int handled, ret; 4462 bool write = ops->write; 4463 struct kvm_mmio_fragment *frag; 4464 4465 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 4466 4467 if (ret < 0) 4468 return X86EMUL_PROPAGATE_FAULT; 4469 4470 /* For APIC access vmexit */ 4471 if (ret) 4472 goto mmio; 4473 4474 if (ops->read_write_emulate(vcpu, gpa, val, bytes)) 4475 return X86EMUL_CONTINUE; 4476 4477 mmio: 4478 /* 4479 * Is this MMIO handled locally? 4480 */ 4481 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 4482 if (handled == bytes) 4483 return X86EMUL_CONTINUE; 4484 4485 gpa += handled; 4486 bytes -= handled; 4487 val += handled; 4488 4489 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 4490 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 4491 frag->gpa = gpa; 4492 frag->data = val; 4493 frag->len = bytes; 4494 return X86EMUL_CONTINUE; 4495 } 4496 4497 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 4498 unsigned long addr, 4499 void *val, unsigned int bytes, 4500 struct x86_exception *exception, 4501 const struct read_write_emulator_ops *ops) 4502 { 4503 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4504 gpa_t gpa; 4505 int rc; 4506 4507 if (ops->read_write_prepare && 4508 ops->read_write_prepare(vcpu, val, bytes)) 4509 return X86EMUL_CONTINUE; 4510 4511 vcpu->mmio_nr_fragments = 0; 4512 4513 /* Crossing a page boundary? */ 4514 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 4515 int now; 4516 4517 now = -addr & ~PAGE_MASK; 4518 rc = emulator_read_write_onepage(addr, val, now, exception, 4519 vcpu, ops); 4520 4521 if (rc != X86EMUL_CONTINUE) 4522 return rc; 4523 addr += now; 4524 if (ctxt->mode != X86EMUL_MODE_PROT64) 4525 addr = (u32)addr; 4526 val += now; 4527 bytes -= now; 4528 } 4529 4530 rc = emulator_read_write_onepage(addr, val, bytes, exception, 4531 vcpu, ops); 4532 if (rc != X86EMUL_CONTINUE) 4533 return rc; 4534 4535 if (!vcpu->mmio_nr_fragments) 4536 return rc; 4537 4538 gpa = vcpu->mmio_fragments[0].gpa; 4539 4540 vcpu->mmio_needed = 1; 4541 vcpu->mmio_cur_fragment = 0; 4542 4543 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 4544 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 4545 vcpu->run->exit_reason = KVM_EXIT_MMIO; 4546 vcpu->run->mmio.phys_addr = gpa; 4547 4548 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 4549 } 4550 4551 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 4552 unsigned long addr, 4553 void *val, 4554 unsigned int bytes, 4555 struct x86_exception *exception) 4556 { 4557 return emulator_read_write(ctxt, addr, val, bytes, 4558 exception, &read_emultor); 4559 } 4560 4561 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 4562 unsigned long addr, 4563 const void *val, 4564 unsigned int bytes, 4565 struct x86_exception *exception) 4566 { 4567 return emulator_read_write(ctxt, addr, (void *)val, bytes, 4568 exception, &write_emultor); 4569 } 4570 4571 #define CMPXCHG_TYPE(t, ptr, old, new) \ 4572 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 4573 4574 #ifdef CONFIG_X86_64 4575 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 4576 #else 4577 # define CMPXCHG64(ptr, old, new) \ 4578 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 4579 #endif 4580 4581 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 4582 unsigned long addr, 4583 const void *old, 4584 const void *new, 4585 unsigned int bytes, 4586 struct x86_exception *exception) 4587 { 4588 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4589 gpa_t gpa; 4590 struct page *page; 4591 char *kaddr; 4592 bool exchanged; 4593 4594 /* guests cmpxchg8b have to be emulated atomically */ 4595 if (bytes > 8 || (bytes & (bytes - 1))) 4596 goto emul_write; 4597 4598 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 4599 4600 if (gpa == UNMAPPED_GVA || 4601 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4602 goto emul_write; 4603 4604 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 4605 goto emul_write; 4606 4607 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); 4608 if (is_error_page(page)) 4609 goto emul_write; 4610 4611 kaddr = kmap_atomic(page); 4612 kaddr += offset_in_page(gpa); 4613 switch (bytes) { 4614 case 1: 4615 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 4616 break; 4617 case 2: 4618 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 4619 break; 4620 case 4: 4621 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 4622 break; 4623 case 8: 4624 exchanged = CMPXCHG64(kaddr, old, new); 4625 break; 4626 default: 4627 BUG(); 4628 } 4629 kunmap_atomic(kaddr); 4630 kvm_release_page_dirty(page); 4631 4632 if (!exchanged) 4633 return X86EMUL_CMPXCHG_FAILED; 4634 4635 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 4636 kvm_page_track_write(vcpu, gpa, new, bytes); 4637 4638 return X86EMUL_CONTINUE; 4639 4640 emul_write: 4641 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 4642 4643 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 4644 } 4645 4646 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 4647 { 4648 /* TODO: String I/O for in kernel device */ 4649 int r; 4650 4651 if (vcpu->arch.pio.in) 4652 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 4653 vcpu->arch.pio.size, pd); 4654 else 4655 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 4656 vcpu->arch.pio.port, vcpu->arch.pio.size, 4657 pd); 4658 return r; 4659 } 4660 4661 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 4662 unsigned short port, void *val, 4663 unsigned int count, bool in) 4664 { 4665 vcpu->arch.pio.port = port; 4666 vcpu->arch.pio.in = in; 4667 vcpu->arch.pio.count = count; 4668 vcpu->arch.pio.size = size; 4669 4670 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 4671 vcpu->arch.pio.count = 0; 4672 return 1; 4673 } 4674 4675 vcpu->run->exit_reason = KVM_EXIT_IO; 4676 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 4677 vcpu->run->io.size = size; 4678 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 4679 vcpu->run->io.count = count; 4680 vcpu->run->io.port = port; 4681 4682 return 0; 4683 } 4684 4685 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 4686 int size, unsigned short port, void *val, 4687 unsigned int count) 4688 { 4689 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4690 int ret; 4691 4692 if (vcpu->arch.pio.count) 4693 goto data_avail; 4694 4695 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 4696 if (ret) { 4697 data_avail: 4698 memcpy(val, vcpu->arch.pio_data, size * count); 4699 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 4700 vcpu->arch.pio.count = 0; 4701 return 1; 4702 } 4703 4704 return 0; 4705 } 4706 4707 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 4708 int size, unsigned short port, 4709 const void *val, unsigned int count) 4710 { 4711 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4712 4713 memcpy(vcpu->arch.pio_data, val, size * count); 4714 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 4715 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 4716 } 4717 4718 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 4719 { 4720 return kvm_x86_ops->get_segment_base(vcpu, seg); 4721 } 4722 4723 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 4724 { 4725 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 4726 } 4727 4728 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 4729 { 4730 if (!need_emulate_wbinvd(vcpu)) 4731 return X86EMUL_CONTINUE; 4732 4733 if (kvm_x86_ops->has_wbinvd_exit()) { 4734 int cpu = get_cpu(); 4735 4736 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4737 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 4738 wbinvd_ipi, NULL, 1); 4739 put_cpu(); 4740 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 4741 } else 4742 wbinvd(); 4743 return X86EMUL_CONTINUE; 4744 } 4745 4746 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 4747 { 4748 kvm_x86_ops->skip_emulated_instruction(vcpu); 4749 return kvm_emulate_wbinvd_noskip(vcpu); 4750 } 4751 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 4752 4753 4754 4755 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 4756 { 4757 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 4758 } 4759 4760 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 4761 unsigned long *dest) 4762 { 4763 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 4764 } 4765 4766 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 4767 unsigned long value) 4768 { 4769 4770 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 4771 } 4772 4773 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 4774 { 4775 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 4776 } 4777 4778 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 4779 { 4780 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4781 unsigned long value; 4782 4783 switch (cr) { 4784 case 0: 4785 value = kvm_read_cr0(vcpu); 4786 break; 4787 case 2: 4788 value = vcpu->arch.cr2; 4789 break; 4790 case 3: 4791 value = kvm_read_cr3(vcpu); 4792 break; 4793 case 4: 4794 value = kvm_read_cr4(vcpu); 4795 break; 4796 case 8: 4797 value = kvm_get_cr8(vcpu); 4798 break; 4799 default: 4800 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4801 return 0; 4802 } 4803 4804 return value; 4805 } 4806 4807 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 4808 { 4809 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4810 int res = 0; 4811 4812 switch (cr) { 4813 case 0: 4814 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 4815 break; 4816 case 2: 4817 vcpu->arch.cr2 = val; 4818 break; 4819 case 3: 4820 res = kvm_set_cr3(vcpu, val); 4821 break; 4822 case 4: 4823 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 4824 break; 4825 case 8: 4826 res = kvm_set_cr8(vcpu, val); 4827 break; 4828 default: 4829 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4830 res = -1; 4831 } 4832 4833 return res; 4834 } 4835 4836 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 4837 { 4838 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 4839 } 4840 4841 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4842 { 4843 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 4844 } 4845 4846 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4847 { 4848 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 4849 } 4850 4851 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4852 { 4853 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 4854 } 4855 4856 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4857 { 4858 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 4859 } 4860 4861 static unsigned long emulator_get_cached_segment_base( 4862 struct x86_emulate_ctxt *ctxt, int seg) 4863 { 4864 return get_segment_base(emul_to_vcpu(ctxt), seg); 4865 } 4866 4867 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 4868 struct desc_struct *desc, u32 *base3, 4869 int seg) 4870 { 4871 struct kvm_segment var; 4872 4873 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 4874 *selector = var.selector; 4875 4876 if (var.unusable) { 4877 memset(desc, 0, sizeof(*desc)); 4878 return false; 4879 } 4880 4881 if (var.g) 4882 var.limit >>= 12; 4883 set_desc_limit(desc, var.limit); 4884 set_desc_base(desc, (unsigned long)var.base); 4885 #ifdef CONFIG_X86_64 4886 if (base3) 4887 *base3 = var.base >> 32; 4888 #endif 4889 desc->type = var.type; 4890 desc->s = var.s; 4891 desc->dpl = var.dpl; 4892 desc->p = var.present; 4893 desc->avl = var.avl; 4894 desc->l = var.l; 4895 desc->d = var.db; 4896 desc->g = var.g; 4897 4898 return true; 4899 } 4900 4901 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 4902 struct desc_struct *desc, u32 base3, 4903 int seg) 4904 { 4905 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4906 struct kvm_segment var; 4907 4908 var.selector = selector; 4909 var.base = get_desc_base(desc); 4910 #ifdef CONFIG_X86_64 4911 var.base |= ((u64)base3) << 32; 4912 #endif 4913 var.limit = get_desc_limit(desc); 4914 if (desc->g) 4915 var.limit = (var.limit << 12) | 0xfff; 4916 var.type = desc->type; 4917 var.dpl = desc->dpl; 4918 var.db = desc->d; 4919 var.s = desc->s; 4920 var.l = desc->l; 4921 var.g = desc->g; 4922 var.avl = desc->avl; 4923 var.present = desc->p; 4924 var.unusable = !var.present; 4925 var.padding = 0; 4926 4927 kvm_set_segment(vcpu, &var, seg); 4928 return; 4929 } 4930 4931 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 4932 u32 msr_index, u64 *pdata) 4933 { 4934 struct msr_data msr; 4935 int r; 4936 4937 msr.index = msr_index; 4938 msr.host_initiated = false; 4939 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); 4940 if (r) 4941 return r; 4942 4943 *pdata = msr.data; 4944 return 0; 4945 } 4946 4947 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 4948 u32 msr_index, u64 data) 4949 { 4950 struct msr_data msr; 4951 4952 msr.data = data; 4953 msr.index = msr_index; 4954 msr.host_initiated = false; 4955 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 4956 } 4957 4958 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 4959 { 4960 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4961 4962 return vcpu->arch.smbase; 4963 } 4964 4965 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 4966 { 4967 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4968 4969 vcpu->arch.smbase = smbase; 4970 } 4971 4972 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 4973 u32 pmc) 4974 { 4975 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); 4976 } 4977 4978 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 4979 u32 pmc, u64 *pdata) 4980 { 4981 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 4982 } 4983 4984 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 4985 { 4986 emul_to_vcpu(ctxt)->arch.halt_request = 1; 4987 } 4988 4989 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) 4990 { 4991 preempt_disable(); 4992 kvm_load_guest_fpu(emul_to_vcpu(ctxt)); 4993 /* 4994 * CR0.TS may reference the host fpu state, not the guest fpu state, 4995 * so it may be clear at this point. 4996 */ 4997 clts(); 4998 } 4999 5000 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) 5001 { 5002 preempt_enable(); 5003 } 5004 5005 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 5006 struct x86_instruction_info *info, 5007 enum x86_intercept_stage stage) 5008 { 5009 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 5010 } 5011 5012 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 5013 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) 5014 { 5015 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); 5016 } 5017 5018 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 5019 { 5020 return kvm_register_read(emul_to_vcpu(ctxt), reg); 5021 } 5022 5023 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 5024 { 5025 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 5026 } 5027 5028 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 5029 { 5030 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 5031 } 5032 5033 static const struct x86_emulate_ops emulate_ops = { 5034 .read_gpr = emulator_read_gpr, 5035 .write_gpr = emulator_write_gpr, 5036 .read_std = kvm_read_guest_virt_system, 5037 .write_std = kvm_write_guest_virt_system, 5038 .read_phys = kvm_read_guest_phys_system, 5039 .fetch = kvm_fetch_guest_virt, 5040 .read_emulated = emulator_read_emulated, 5041 .write_emulated = emulator_write_emulated, 5042 .cmpxchg_emulated = emulator_cmpxchg_emulated, 5043 .invlpg = emulator_invlpg, 5044 .pio_in_emulated = emulator_pio_in_emulated, 5045 .pio_out_emulated = emulator_pio_out_emulated, 5046 .get_segment = emulator_get_segment, 5047 .set_segment = emulator_set_segment, 5048 .get_cached_segment_base = emulator_get_cached_segment_base, 5049 .get_gdt = emulator_get_gdt, 5050 .get_idt = emulator_get_idt, 5051 .set_gdt = emulator_set_gdt, 5052 .set_idt = emulator_set_idt, 5053 .get_cr = emulator_get_cr, 5054 .set_cr = emulator_set_cr, 5055 .cpl = emulator_get_cpl, 5056 .get_dr = emulator_get_dr, 5057 .set_dr = emulator_set_dr, 5058 .get_smbase = emulator_get_smbase, 5059 .set_smbase = emulator_set_smbase, 5060 .set_msr = emulator_set_msr, 5061 .get_msr = emulator_get_msr, 5062 .check_pmc = emulator_check_pmc, 5063 .read_pmc = emulator_read_pmc, 5064 .halt = emulator_halt, 5065 .wbinvd = emulator_wbinvd, 5066 .fix_hypercall = emulator_fix_hypercall, 5067 .get_fpu = emulator_get_fpu, 5068 .put_fpu = emulator_put_fpu, 5069 .intercept = emulator_intercept, 5070 .get_cpuid = emulator_get_cpuid, 5071 .set_nmi_mask = emulator_set_nmi_mask, 5072 }; 5073 5074 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 5075 { 5076 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 5077 /* 5078 * an sti; sti; sequence only disable interrupts for the first 5079 * instruction. So, if the last instruction, be it emulated or 5080 * not, left the system with the INT_STI flag enabled, it 5081 * means that the last instruction is an sti. We should not 5082 * leave the flag on in this case. The same goes for mov ss 5083 */ 5084 if (int_shadow & mask) 5085 mask = 0; 5086 if (unlikely(int_shadow || mask)) { 5087 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 5088 if (!mask) 5089 kvm_make_request(KVM_REQ_EVENT, vcpu); 5090 } 5091 } 5092 5093 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 5094 { 5095 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5096 if (ctxt->exception.vector == PF_VECTOR) 5097 return kvm_propagate_fault(vcpu, &ctxt->exception); 5098 5099 if (ctxt->exception.error_code_valid) 5100 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 5101 ctxt->exception.error_code); 5102 else 5103 kvm_queue_exception(vcpu, ctxt->exception.vector); 5104 return false; 5105 } 5106 5107 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 5108 { 5109 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5110 int cs_db, cs_l; 5111 5112 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 5113 5114 ctxt->eflags = kvm_get_rflags(vcpu); 5115 ctxt->eip = kvm_rip_read(vcpu); 5116 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 5117 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 5118 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 5119 cs_db ? X86EMUL_MODE_PROT32 : 5120 X86EMUL_MODE_PROT16; 5121 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 5122 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 5123 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 5124 ctxt->emul_flags = vcpu->arch.hflags; 5125 5126 init_decode_cache(ctxt); 5127 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5128 } 5129 5130 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 5131 { 5132 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5133 int ret; 5134 5135 init_emulate_ctxt(vcpu); 5136 5137 ctxt->op_bytes = 2; 5138 ctxt->ad_bytes = 2; 5139 ctxt->_eip = ctxt->eip + inc_eip; 5140 ret = emulate_int_real(ctxt, irq); 5141 5142 if (ret != X86EMUL_CONTINUE) 5143 return EMULATE_FAIL; 5144 5145 ctxt->eip = ctxt->_eip; 5146 kvm_rip_write(vcpu, ctxt->eip); 5147 kvm_set_rflags(vcpu, ctxt->eflags); 5148 5149 if (irq == NMI_VECTOR) 5150 vcpu->arch.nmi_pending = 0; 5151 else 5152 vcpu->arch.interrupt.pending = false; 5153 5154 return EMULATE_DONE; 5155 } 5156 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 5157 5158 static int handle_emulation_failure(struct kvm_vcpu *vcpu) 5159 { 5160 int r = EMULATE_DONE; 5161 5162 ++vcpu->stat.insn_emulation_fail; 5163 trace_kvm_emulate_insn_failed(vcpu); 5164 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 5165 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5166 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 5167 vcpu->run->internal.ndata = 0; 5168 r = EMULATE_FAIL; 5169 } 5170 kvm_queue_exception(vcpu, UD_VECTOR); 5171 5172 return r; 5173 } 5174 5175 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 5176 bool write_fault_to_shadow_pgtable, 5177 int emulation_type) 5178 { 5179 gpa_t gpa = cr2; 5180 kvm_pfn_t pfn; 5181 5182 if (emulation_type & EMULTYPE_NO_REEXECUTE) 5183 return false; 5184 5185 if (!vcpu->arch.mmu.direct_map) { 5186 /* 5187 * Write permission should be allowed since only 5188 * write access need to be emulated. 5189 */ 5190 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5191 5192 /* 5193 * If the mapping is invalid in guest, let cpu retry 5194 * it to generate fault. 5195 */ 5196 if (gpa == UNMAPPED_GVA) 5197 return true; 5198 } 5199 5200 /* 5201 * Do not retry the unhandleable instruction if it faults on the 5202 * readonly host memory, otherwise it will goto a infinite loop: 5203 * retry instruction -> write #PF -> emulation fail -> retry 5204 * instruction -> ... 5205 */ 5206 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 5207 5208 /* 5209 * If the instruction failed on the error pfn, it can not be fixed, 5210 * report the error to userspace. 5211 */ 5212 if (is_error_noslot_pfn(pfn)) 5213 return false; 5214 5215 kvm_release_pfn_clean(pfn); 5216 5217 /* The instructions are well-emulated on direct mmu. */ 5218 if (vcpu->arch.mmu.direct_map) { 5219 unsigned int indirect_shadow_pages; 5220 5221 spin_lock(&vcpu->kvm->mmu_lock); 5222 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 5223 spin_unlock(&vcpu->kvm->mmu_lock); 5224 5225 if (indirect_shadow_pages) 5226 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5227 5228 return true; 5229 } 5230 5231 /* 5232 * if emulation was due to access to shadowed page table 5233 * and it failed try to unshadow page and re-enter the 5234 * guest to let CPU execute the instruction. 5235 */ 5236 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5237 5238 /* 5239 * If the access faults on its page table, it can not 5240 * be fixed by unprotecting shadow page and it should 5241 * be reported to userspace. 5242 */ 5243 return !write_fault_to_shadow_pgtable; 5244 } 5245 5246 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5247 unsigned long cr2, int emulation_type) 5248 { 5249 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5250 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5251 5252 last_retry_eip = vcpu->arch.last_retry_eip; 5253 last_retry_addr = vcpu->arch.last_retry_addr; 5254 5255 /* 5256 * If the emulation is caused by #PF and it is non-page_table 5257 * writing instruction, it means the VM-EXIT is caused by shadow 5258 * page protected, we can zap the shadow page and retry this 5259 * instruction directly. 5260 * 5261 * Note: if the guest uses a non-page-table modifying instruction 5262 * on the PDE that points to the instruction, then we will unmap 5263 * the instruction and go to an infinite loop. So, we cache the 5264 * last retried eip and the last fault address, if we meet the eip 5265 * and the address again, we can break out of the potential infinite 5266 * loop. 5267 */ 5268 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5269 5270 if (!(emulation_type & EMULTYPE_RETRY)) 5271 return false; 5272 5273 if (x86_page_table_writing_insn(ctxt)) 5274 return false; 5275 5276 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5277 return false; 5278 5279 vcpu->arch.last_retry_eip = ctxt->eip; 5280 vcpu->arch.last_retry_addr = cr2; 5281 5282 if (!vcpu->arch.mmu.direct_map) 5283 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5284 5285 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5286 5287 return true; 5288 } 5289 5290 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5291 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5292 5293 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 5294 { 5295 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 5296 /* This is a good place to trace that we are exiting SMM. */ 5297 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 5298 5299 if (unlikely(vcpu->arch.smi_pending)) { 5300 kvm_make_request(KVM_REQ_SMI, vcpu); 5301 vcpu->arch.smi_pending = 0; 5302 } else { 5303 /* Process a latched INIT, if any. */ 5304 kvm_make_request(KVM_REQ_EVENT, vcpu); 5305 } 5306 } 5307 5308 kvm_mmu_reset_context(vcpu); 5309 } 5310 5311 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) 5312 { 5313 unsigned changed = vcpu->arch.hflags ^ emul_flags; 5314 5315 vcpu->arch.hflags = emul_flags; 5316 5317 if (changed & HF_SMM_MASK) 5318 kvm_smm_changed(vcpu); 5319 } 5320 5321 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5322 unsigned long *db) 5323 { 5324 u32 dr6 = 0; 5325 int i; 5326 u32 enable, rwlen; 5327 5328 enable = dr7; 5329 rwlen = dr7 >> 16; 5330 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5331 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5332 dr6 |= (1 << i); 5333 return dr6; 5334 } 5335 5336 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) 5337 { 5338 struct kvm_run *kvm_run = vcpu->run; 5339 5340 /* 5341 * rflags is the old, "raw" value of the flags. The new value has 5342 * not been saved yet. 5343 * 5344 * This is correct even for TF set by the guest, because "the 5345 * processor will not generate this exception after the instruction 5346 * that sets the TF flag". 5347 */ 5348 if (unlikely(rflags & X86_EFLAGS_TF)) { 5349 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5350 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | 5351 DR6_RTM; 5352 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5353 kvm_run->debug.arch.exception = DB_VECTOR; 5354 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5355 *r = EMULATE_USER_EXIT; 5356 } else { 5357 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; 5358 /* 5359 * "Certain debug exceptions may clear bit 0-3. The 5360 * remaining contents of the DR6 register are never 5361 * cleared by the processor". 5362 */ 5363 vcpu->arch.dr6 &= ~15; 5364 vcpu->arch.dr6 |= DR6_BS | DR6_RTM; 5365 kvm_queue_exception(vcpu, DB_VECTOR); 5366 } 5367 } 5368 } 5369 5370 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5371 { 5372 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5373 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5374 struct kvm_run *kvm_run = vcpu->run; 5375 unsigned long eip = kvm_get_linear_rip(vcpu); 5376 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5377 vcpu->arch.guest_debug_dr7, 5378 vcpu->arch.eff_db); 5379 5380 if (dr6 != 0) { 5381 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 5382 kvm_run->debug.arch.pc = eip; 5383 kvm_run->debug.arch.exception = DB_VECTOR; 5384 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5385 *r = EMULATE_USER_EXIT; 5386 return true; 5387 } 5388 } 5389 5390 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 5391 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 5392 unsigned long eip = kvm_get_linear_rip(vcpu); 5393 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5394 vcpu->arch.dr7, 5395 vcpu->arch.db); 5396 5397 if (dr6 != 0) { 5398 vcpu->arch.dr6 &= ~15; 5399 vcpu->arch.dr6 |= dr6 | DR6_RTM; 5400 kvm_queue_exception(vcpu, DB_VECTOR); 5401 *r = EMULATE_DONE; 5402 return true; 5403 } 5404 } 5405 5406 return false; 5407 } 5408 5409 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 5410 unsigned long cr2, 5411 int emulation_type, 5412 void *insn, 5413 int insn_len) 5414 { 5415 int r; 5416 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5417 bool writeback = true; 5418 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 5419 5420 /* 5421 * Clear write_fault_to_shadow_pgtable here to ensure it is 5422 * never reused. 5423 */ 5424 vcpu->arch.write_fault_to_shadow_pgtable = false; 5425 kvm_clear_exception_queue(vcpu); 5426 5427 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 5428 init_emulate_ctxt(vcpu); 5429 5430 /* 5431 * We will reenter on the same instruction since 5432 * we do not set complete_userspace_io. This does not 5433 * handle watchpoints yet, those would be handled in 5434 * the emulate_ops. 5435 */ 5436 if (kvm_vcpu_check_breakpoint(vcpu, &r)) 5437 return r; 5438 5439 ctxt->interruptibility = 0; 5440 ctxt->have_exception = false; 5441 ctxt->exception.vector = -1; 5442 ctxt->perm_ok = false; 5443 5444 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 5445 5446 r = x86_decode_insn(ctxt, insn, insn_len); 5447 5448 trace_kvm_emulate_insn_start(vcpu); 5449 ++vcpu->stat.insn_emulation; 5450 if (r != EMULATION_OK) { 5451 if (emulation_type & EMULTYPE_TRAP_UD) 5452 return EMULATE_FAIL; 5453 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5454 emulation_type)) 5455 return EMULATE_DONE; 5456 if (emulation_type & EMULTYPE_SKIP) 5457 return EMULATE_FAIL; 5458 return handle_emulation_failure(vcpu); 5459 } 5460 } 5461 5462 if (emulation_type & EMULTYPE_SKIP) { 5463 kvm_rip_write(vcpu, ctxt->_eip); 5464 if (ctxt->eflags & X86_EFLAGS_RF) 5465 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 5466 return EMULATE_DONE; 5467 } 5468 5469 if (retry_instruction(ctxt, cr2, emulation_type)) 5470 return EMULATE_DONE; 5471 5472 /* this is needed for vmware backdoor interface to work since it 5473 changes registers values during IO operation */ 5474 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 5475 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5476 emulator_invalidate_register_cache(ctxt); 5477 } 5478 5479 restart: 5480 r = x86_emulate_insn(ctxt); 5481 5482 if (r == EMULATION_INTERCEPTED) 5483 return EMULATE_DONE; 5484 5485 if (r == EMULATION_FAILED) { 5486 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5487 emulation_type)) 5488 return EMULATE_DONE; 5489 5490 return handle_emulation_failure(vcpu); 5491 } 5492 5493 if (ctxt->have_exception) { 5494 r = EMULATE_DONE; 5495 if (inject_emulated_exception(vcpu)) 5496 return r; 5497 } else if (vcpu->arch.pio.count) { 5498 if (!vcpu->arch.pio.in) { 5499 /* FIXME: return into emulator if single-stepping. */ 5500 vcpu->arch.pio.count = 0; 5501 } else { 5502 writeback = false; 5503 vcpu->arch.complete_userspace_io = complete_emulated_pio; 5504 } 5505 r = EMULATE_USER_EXIT; 5506 } else if (vcpu->mmio_needed) { 5507 if (!vcpu->mmio_is_write) 5508 writeback = false; 5509 r = EMULATE_USER_EXIT; 5510 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 5511 } else if (r == EMULATION_RESTART) 5512 goto restart; 5513 else 5514 r = EMULATE_DONE; 5515 5516 if (writeback) { 5517 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5518 toggle_interruptibility(vcpu, ctxt->interruptibility); 5519 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 5520 if (vcpu->arch.hflags != ctxt->emul_flags) 5521 kvm_set_hflags(vcpu, ctxt->emul_flags); 5522 kvm_rip_write(vcpu, ctxt->eip); 5523 if (r == EMULATE_DONE) 5524 kvm_vcpu_check_singlestep(vcpu, rflags, &r); 5525 if (!ctxt->have_exception || 5526 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 5527 __kvm_set_rflags(vcpu, ctxt->eflags); 5528 5529 /* 5530 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 5531 * do nothing, and it will be requested again as soon as 5532 * the shadow expires. But we still need to check here, 5533 * because POPF has no interrupt shadow. 5534 */ 5535 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 5536 kvm_make_request(KVM_REQ_EVENT, vcpu); 5537 } else 5538 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 5539 5540 return r; 5541 } 5542 EXPORT_SYMBOL_GPL(x86_emulate_instruction); 5543 5544 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) 5545 { 5546 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 5547 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 5548 size, port, &val, 1); 5549 /* do not return to emulator after return from userspace */ 5550 vcpu->arch.pio.count = 0; 5551 return ret; 5552 } 5553 EXPORT_SYMBOL_GPL(kvm_fast_pio_out); 5554 5555 static void tsc_bad(void *info) 5556 { 5557 __this_cpu_write(cpu_tsc_khz, 0); 5558 } 5559 5560 static void tsc_khz_changed(void *data) 5561 { 5562 struct cpufreq_freqs *freq = data; 5563 unsigned long khz = 0; 5564 5565 if (data) 5566 khz = freq->new; 5567 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5568 khz = cpufreq_quick_get(raw_smp_processor_id()); 5569 if (!khz) 5570 khz = tsc_khz; 5571 __this_cpu_write(cpu_tsc_khz, khz); 5572 } 5573 5574 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 5575 void *data) 5576 { 5577 struct cpufreq_freqs *freq = data; 5578 struct kvm *kvm; 5579 struct kvm_vcpu *vcpu; 5580 int i, send_ipi = 0; 5581 5582 /* 5583 * We allow guests to temporarily run on slowing clocks, 5584 * provided we notify them after, or to run on accelerating 5585 * clocks, provided we notify them before. Thus time never 5586 * goes backwards. 5587 * 5588 * However, we have a problem. We can't atomically update 5589 * the frequency of a given CPU from this function; it is 5590 * merely a notifier, which can be called from any CPU. 5591 * Changing the TSC frequency at arbitrary points in time 5592 * requires a recomputation of local variables related to 5593 * the TSC for each VCPU. We must flag these local variables 5594 * to be updated and be sure the update takes place with the 5595 * new frequency before any guests proceed. 5596 * 5597 * Unfortunately, the combination of hotplug CPU and frequency 5598 * change creates an intractable locking scenario; the order 5599 * of when these callouts happen is undefined with respect to 5600 * CPU hotplug, and they can race with each other. As such, 5601 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 5602 * undefined; you can actually have a CPU frequency change take 5603 * place in between the computation of X and the setting of the 5604 * variable. To protect against this problem, all updates of 5605 * the per_cpu tsc_khz variable are done in an interrupt 5606 * protected IPI, and all callers wishing to update the value 5607 * must wait for a synchronous IPI to complete (which is trivial 5608 * if the caller is on the CPU already). This establishes the 5609 * necessary total order on variable updates. 5610 * 5611 * Note that because a guest time update may take place 5612 * anytime after the setting of the VCPU's request bit, the 5613 * correct TSC value must be set before the request. However, 5614 * to ensure the update actually makes it to any guest which 5615 * starts running in hardware virtualization between the set 5616 * and the acquisition of the spinlock, we must also ping the 5617 * CPU after setting the request bit. 5618 * 5619 */ 5620 5621 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 5622 return 0; 5623 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 5624 return 0; 5625 5626 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5627 5628 spin_lock(&kvm_lock); 5629 list_for_each_entry(kvm, &vm_list, vm_list) { 5630 kvm_for_each_vcpu(i, vcpu, kvm) { 5631 if (vcpu->cpu != freq->cpu) 5632 continue; 5633 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5634 if (vcpu->cpu != smp_processor_id()) 5635 send_ipi = 1; 5636 } 5637 } 5638 spin_unlock(&kvm_lock); 5639 5640 if (freq->old < freq->new && send_ipi) { 5641 /* 5642 * We upscale the frequency. Must make the guest 5643 * doesn't see old kvmclock values while running with 5644 * the new frequency, otherwise we risk the guest sees 5645 * time go backwards. 5646 * 5647 * In case we update the frequency for another cpu 5648 * (which might be in guest context) send an interrupt 5649 * to kick the cpu out of guest context. Next time 5650 * guest context is entered kvmclock will be updated, 5651 * so the guest will not see stale values. 5652 */ 5653 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5654 } 5655 return 0; 5656 } 5657 5658 static struct notifier_block kvmclock_cpufreq_notifier_block = { 5659 .notifier_call = kvmclock_cpufreq_notifier 5660 }; 5661 5662 static int kvmclock_cpu_notifier(struct notifier_block *nfb, 5663 unsigned long action, void *hcpu) 5664 { 5665 unsigned int cpu = (unsigned long)hcpu; 5666 5667 switch (action) { 5668 case CPU_ONLINE: 5669 case CPU_DOWN_FAILED: 5670 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5671 break; 5672 case CPU_DOWN_PREPARE: 5673 smp_call_function_single(cpu, tsc_bad, NULL, 1); 5674 break; 5675 } 5676 return NOTIFY_OK; 5677 } 5678 5679 static struct notifier_block kvmclock_cpu_notifier_block = { 5680 .notifier_call = kvmclock_cpu_notifier, 5681 .priority = -INT_MAX 5682 }; 5683 5684 static void kvm_timer_init(void) 5685 { 5686 int cpu; 5687 5688 max_tsc_khz = tsc_khz; 5689 5690 cpu_notifier_register_begin(); 5691 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 5692 #ifdef CONFIG_CPU_FREQ 5693 struct cpufreq_policy policy; 5694 memset(&policy, 0, sizeof(policy)); 5695 cpu = get_cpu(); 5696 cpufreq_get_policy(&policy, cpu); 5697 if (policy.cpuinfo.max_freq) 5698 max_tsc_khz = policy.cpuinfo.max_freq; 5699 put_cpu(); 5700 #endif 5701 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 5702 CPUFREQ_TRANSITION_NOTIFIER); 5703 } 5704 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 5705 for_each_online_cpu(cpu) 5706 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5707 5708 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5709 cpu_notifier_register_done(); 5710 5711 } 5712 5713 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 5714 5715 int kvm_is_in_guest(void) 5716 { 5717 return __this_cpu_read(current_vcpu) != NULL; 5718 } 5719 5720 static int kvm_is_user_mode(void) 5721 { 5722 int user_mode = 3; 5723 5724 if (__this_cpu_read(current_vcpu)) 5725 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 5726 5727 return user_mode != 0; 5728 } 5729 5730 static unsigned long kvm_get_guest_ip(void) 5731 { 5732 unsigned long ip = 0; 5733 5734 if (__this_cpu_read(current_vcpu)) 5735 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 5736 5737 return ip; 5738 } 5739 5740 static struct perf_guest_info_callbacks kvm_guest_cbs = { 5741 .is_in_guest = kvm_is_in_guest, 5742 .is_user_mode = kvm_is_user_mode, 5743 .get_guest_ip = kvm_get_guest_ip, 5744 }; 5745 5746 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) 5747 { 5748 __this_cpu_write(current_vcpu, vcpu); 5749 } 5750 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); 5751 5752 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) 5753 { 5754 __this_cpu_write(current_vcpu, NULL); 5755 } 5756 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); 5757 5758 static void kvm_set_mmio_spte_mask(void) 5759 { 5760 u64 mask; 5761 int maxphyaddr = boot_cpu_data.x86_phys_bits; 5762 5763 /* 5764 * Set the reserved bits and the present bit of an paging-structure 5765 * entry to generate page fault with PFER.RSV = 1. 5766 */ 5767 /* Mask the reserved physical address bits. */ 5768 mask = rsvd_bits(maxphyaddr, 51); 5769 5770 /* Bit 62 is always reserved for 32bit host. */ 5771 mask |= 0x3ull << 62; 5772 5773 /* Set the present bit. */ 5774 mask |= 1ull; 5775 5776 #ifdef CONFIG_X86_64 5777 /* 5778 * If reserved bit is not supported, clear the present bit to disable 5779 * mmio page fault. 5780 */ 5781 if (maxphyaddr == 52) 5782 mask &= ~1ull; 5783 #endif 5784 5785 kvm_mmu_set_mmio_spte_mask(mask); 5786 } 5787 5788 #ifdef CONFIG_X86_64 5789 static void pvclock_gtod_update_fn(struct work_struct *work) 5790 { 5791 struct kvm *kvm; 5792 5793 struct kvm_vcpu *vcpu; 5794 int i; 5795 5796 spin_lock(&kvm_lock); 5797 list_for_each_entry(kvm, &vm_list, vm_list) 5798 kvm_for_each_vcpu(i, vcpu, kvm) 5799 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 5800 atomic_set(&kvm_guest_has_master_clock, 0); 5801 spin_unlock(&kvm_lock); 5802 } 5803 5804 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 5805 5806 /* 5807 * Notification about pvclock gtod data update. 5808 */ 5809 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 5810 void *priv) 5811 { 5812 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 5813 struct timekeeper *tk = priv; 5814 5815 update_pvclock_gtod(tk); 5816 5817 /* disable master clock if host does not trust, or does not 5818 * use, TSC clocksource 5819 */ 5820 if (gtod->clock.vclock_mode != VCLOCK_TSC && 5821 atomic_read(&kvm_guest_has_master_clock) != 0) 5822 queue_work(system_long_wq, &pvclock_gtod_work); 5823 5824 return 0; 5825 } 5826 5827 static struct notifier_block pvclock_gtod_notifier = { 5828 .notifier_call = pvclock_gtod_notify, 5829 }; 5830 #endif 5831 5832 int kvm_arch_init(void *opaque) 5833 { 5834 int r; 5835 struct kvm_x86_ops *ops = opaque; 5836 5837 if (kvm_x86_ops) { 5838 printk(KERN_ERR "kvm: already loaded the other module\n"); 5839 r = -EEXIST; 5840 goto out; 5841 } 5842 5843 if (!ops->cpu_has_kvm_support()) { 5844 printk(KERN_ERR "kvm: no hardware support\n"); 5845 r = -EOPNOTSUPP; 5846 goto out; 5847 } 5848 if (ops->disabled_by_bios()) { 5849 printk(KERN_ERR "kvm: disabled by bios\n"); 5850 r = -EOPNOTSUPP; 5851 goto out; 5852 } 5853 5854 r = -ENOMEM; 5855 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 5856 if (!shared_msrs) { 5857 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 5858 goto out; 5859 } 5860 5861 r = kvm_mmu_module_init(); 5862 if (r) 5863 goto out_free_percpu; 5864 5865 kvm_set_mmio_spte_mask(); 5866 5867 kvm_x86_ops = ops; 5868 5869 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 5870 PT_DIRTY_MASK, PT64_NX_MASK, 0); 5871 5872 kvm_timer_init(); 5873 5874 perf_register_guest_info_callbacks(&kvm_guest_cbs); 5875 5876 if (boot_cpu_has(X86_FEATURE_XSAVE)) 5877 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 5878 5879 kvm_lapic_init(); 5880 #ifdef CONFIG_X86_64 5881 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 5882 #endif 5883 5884 return 0; 5885 5886 out_free_percpu: 5887 free_percpu(shared_msrs); 5888 out: 5889 return r; 5890 } 5891 5892 void kvm_arch_exit(void) 5893 { 5894 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 5895 5896 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5897 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 5898 CPUFREQ_TRANSITION_NOTIFIER); 5899 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5900 #ifdef CONFIG_X86_64 5901 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 5902 #endif 5903 kvm_x86_ops = NULL; 5904 kvm_mmu_module_exit(); 5905 free_percpu(shared_msrs); 5906 } 5907 5908 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 5909 { 5910 ++vcpu->stat.halt_exits; 5911 if (lapic_in_kernel(vcpu)) { 5912 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 5913 return 1; 5914 } else { 5915 vcpu->run->exit_reason = KVM_EXIT_HLT; 5916 return 0; 5917 } 5918 } 5919 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 5920 5921 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 5922 { 5923 kvm_x86_ops->skip_emulated_instruction(vcpu); 5924 return kvm_vcpu_halt(vcpu); 5925 } 5926 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 5927 5928 /* 5929 * kvm_pv_kick_cpu_op: Kick a vcpu. 5930 * 5931 * @apicid - apicid of vcpu to be kicked. 5932 */ 5933 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 5934 { 5935 struct kvm_lapic_irq lapic_irq; 5936 5937 lapic_irq.shorthand = 0; 5938 lapic_irq.dest_mode = 0; 5939 lapic_irq.dest_id = apicid; 5940 lapic_irq.msi_redir_hint = false; 5941 5942 lapic_irq.delivery_mode = APIC_DM_REMRD; 5943 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 5944 } 5945 5946 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) 5947 { 5948 vcpu->arch.apicv_active = false; 5949 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); 5950 } 5951 5952 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 5953 { 5954 unsigned long nr, a0, a1, a2, a3, ret; 5955 int op_64_bit, r = 1; 5956 5957 kvm_x86_ops->skip_emulated_instruction(vcpu); 5958 5959 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 5960 return kvm_hv_hypercall(vcpu); 5961 5962 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 5963 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 5964 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 5965 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 5966 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 5967 5968 trace_kvm_hypercall(nr, a0, a1, a2, a3); 5969 5970 op_64_bit = is_64_bit_mode(vcpu); 5971 if (!op_64_bit) { 5972 nr &= 0xFFFFFFFF; 5973 a0 &= 0xFFFFFFFF; 5974 a1 &= 0xFFFFFFFF; 5975 a2 &= 0xFFFFFFFF; 5976 a3 &= 0xFFFFFFFF; 5977 } 5978 5979 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 5980 ret = -KVM_EPERM; 5981 goto out; 5982 } 5983 5984 switch (nr) { 5985 case KVM_HC_VAPIC_POLL_IRQ: 5986 ret = 0; 5987 break; 5988 case KVM_HC_KICK_CPU: 5989 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 5990 ret = 0; 5991 break; 5992 default: 5993 ret = -KVM_ENOSYS; 5994 break; 5995 } 5996 out: 5997 if (!op_64_bit) 5998 ret = (u32)ret; 5999 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 6000 ++vcpu->stat.hypercalls; 6001 return r; 6002 } 6003 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 6004 6005 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 6006 { 6007 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6008 char instruction[3]; 6009 unsigned long rip = kvm_rip_read(vcpu); 6010 6011 kvm_x86_ops->patch_hypercall(vcpu, instruction); 6012 6013 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); 6014 } 6015 6016 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 6017 { 6018 return vcpu->run->request_interrupt_window && 6019 likely(!pic_in_kernel(vcpu->kvm)); 6020 } 6021 6022 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 6023 { 6024 struct kvm_run *kvm_run = vcpu->run; 6025 6026 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 6027 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 6028 kvm_run->cr8 = kvm_get_cr8(vcpu); 6029 kvm_run->apic_base = kvm_get_apic_base(vcpu); 6030 kvm_run->ready_for_interrupt_injection = 6031 pic_in_kernel(vcpu->kvm) || 6032 kvm_vcpu_ready_for_interrupt_injection(vcpu); 6033 } 6034 6035 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 6036 { 6037 int max_irr, tpr; 6038 6039 if (!kvm_x86_ops->update_cr8_intercept) 6040 return; 6041 6042 if (!lapic_in_kernel(vcpu)) 6043 return; 6044 6045 if (vcpu->arch.apicv_active) 6046 return; 6047 6048 if (!vcpu->arch.apic->vapic_addr) 6049 max_irr = kvm_lapic_find_highest_irr(vcpu); 6050 else 6051 max_irr = -1; 6052 6053 if (max_irr != -1) 6054 max_irr >>= 4; 6055 6056 tpr = kvm_lapic_get_cr8(vcpu); 6057 6058 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 6059 } 6060 6061 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 6062 { 6063 int r; 6064 6065 /* try to reinject previous events if any */ 6066 if (vcpu->arch.exception.pending) { 6067 trace_kvm_inj_exception(vcpu->arch.exception.nr, 6068 vcpu->arch.exception.has_error_code, 6069 vcpu->arch.exception.error_code); 6070 6071 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 6072 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 6073 X86_EFLAGS_RF); 6074 6075 if (vcpu->arch.exception.nr == DB_VECTOR && 6076 (vcpu->arch.dr7 & DR7_GD)) { 6077 vcpu->arch.dr7 &= ~DR7_GD; 6078 kvm_update_dr7(vcpu); 6079 } 6080 6081 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, 6082 vcpu->arch.exception.has_error_code, 6083 vcpu->arch.exception.error_code, 6084 vcpu->arch.exception.reinject); 6085 return 0; 6086 } 6087 6088 if (vcpu->arch.nmi_injected) { 6089 kvm_x86_ops->set_nmi(vcpu); 6090 return 0; 6091 } 6092 6093 if (vcpu->arch.interrupt.pending) { 6094 kvm_x86_ops->set_irq(vcpu); 6095 return 0; 6096 } 6097 6098 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6099 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6100 if (r != 0) 6101 return r; 6102 } 6103 6104 /* try to inject new event if pending */ 6105 if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { 6106 --vcpu->arch.nmi_pending; 6107 vcpu->arch.nmi_injected = true; 6108 kvm_x86_ops->set_nmi(vcpu); 6109 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 6110 /* 6111 * Because interrupts can be injected asynchronously, we are 6112 * calling check_nested_events again here to avoid a race condition. 6113 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 6114 * proposal and current concerns. Perhaps we should be setting 6115 * KVM_REQ_EVENT only on certain events and not unconditionally? 6116 */ 6117 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6118 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6119 if (r != 0) 6120 return r; 6121 } 6122 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 6123 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 6124 false); 6125 kvm_x86_ops->set_irq(vcpu); 6126 } 6127 } 6128 return 0; 6129 } 6130 6131 static void process_nmi(struct kvm_vcpu *vcpu) 6132 { 6133 unsigned limit = 2; 6134 6135 /* 6136 * x86 is limited to one NMI running, and one NMI pending after it. 6137 * If an NMI is already in progress, limit further NMIs to just one. 6138 * Otherwise, allow two (and we'll inject the first one immediately). 6139 */ 6140 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 6141 limit = 1; 6142 6143 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 6144 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 6145 kvm_make_request(KVM_REQ_EVENT, vcpu); 6146 } 6147 6148 #define put_smstate(type, buf, offset, val) \ 6149 *(type *)((buf) + (offset) - 0x7e00) = val 6150 6151 static u32 process_smi_get_segment_flags(struct kvm_segment *seg) 6152 { 6153 u32 flags = 0; 6154 flags |= seg->g << 23; 6155 flags |= seg->db << 22; 6156 flags |= seg->l << 21; 6157 flags |= seg->avl << 20; 6158 flags |= seg->present << 15; 6159 flags |= seg->dpl << 13; 6160 flags |= seg->s << 12; 6161 flags |= seg->type << 8; 6162 return flags; 6163 } 6164 6165 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 6166 { 6167 struct kvm_segment seg; 6168 int offset; 6169 6170 kvm_get_segment(vcpu, &seg, n); 6171 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 6172 6173 if (n < 3) 6174 offset = 0x7f84 + n * 12; 6175 else 6176 offset = 0x7f2c + (n - 3) * 12; 6177 6178 put_smstate(u32, buf, offset + 8, seg.base); 6179 put_smstate(u32, buf, offset + 4, seg.limit); 6180 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg)); 6181 } 6182 6183 #ifdef CONFIG_X86_64 6184 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 6185 { 6186 struct kvm_segment seg; 6187 int offset; 6188 u16 flags; 6189 6190 kvm_get_segment(vcpu, &seg, n); 6191 offset = 0x7e00 + n * 16; 6192 6193 flags = process_smi_get_segment_flags(&seg) >> 8; 6194 put_smstate(u16, buf, offset, seg.selector); 6195 put_smstate(u16, buf, offset + 2, flags); 6196 put_smstate(u32, buf, offset + 4, seg.limit); 6197 put_smstate(u64, buf, offset + 8, seg.base); 6198 } 6199 #endif 6200 6201 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf) 6202 { 6203 struct desc_ptr dt; 6204 struct kvm_segment seg; 6205 unsigned long val; 6206 int i; 6207 6208 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 6209 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 6210 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 6211 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 6212 6213 for (i = 0; i < 8; i++) 6214 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 6215 6216 kvm_get_dr(vcpu, 6, &val); 6217 put_smstate(u32, buf, 0x7fcc, (u32)val); 6218 kvm_get_dr(vcpu, 7, &val); 6219 put_smstate(u32, buf, 0x7fc8, (u32)val); 6220 6221 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6222 put_smstate(u32, buf, 0x7fc4, seg.selector); 6223 put_smstate(u32, buf, 0x7f64, seg.base); 6224 put_smstate(u32, buf, 0x7f60, seg.limit); 6225 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg)); 6226 6227 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6228 put_smstate(u32, buf, 0x7fc0, seg.selector); 6229 put_smstate(u32, buf, 0x7f80, seg.base); 6230 put_smstate(u32, buf, 0x7f7c, seg.limit); 6231 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg)); 6232 6233 kvm_x86_ops->get_gdt(vcpu, &dt); 6234 put_smstate(u32, buf, 0x7f74, dt.address); 6235 put_smstate(u32, buf, 0x7f70, dt.size); 6236 6237 kvm_x86_ops->get_idt(vcpu, &dt); 6238 put_smstate(u32, buf, 0x7f58, dt.address); 6239 put_smstate(u32, buf, 0x7f54, dt.size); 6240 6241 for (i = 0; i < 6; i++) 6242 process_smi_save_seg_32(vcpu, buf, i); 6243 6244 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 6245 6246 /* revision id */ 6247 put_smstate(u32, buf, 0x7efc, 0x00020000); 6248 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 6249 } 6250 6251 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf) 6252 { 6253 #ifdef CONFIG_X86_64 6254 struct desc_ptr dt; 6255 struct kvm_segment seg; 6256 unsigned long val; 6257 int i; 6258 6259 for (i = 0; i < 16; i++) 6260 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 6261 6262 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 6263 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 6264 6265 kvm_get_dr(vcpu, 6, &val); 6266 put_smstate(u64, buf, 0x7f68, val); 6267 kvm_get_dr(vcpu, 7, &val); 6268 put_smstate(u64, buf, 0x7f60, val); 6269 6270 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 6271 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 6272 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 6273 6274 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 6275 6276 /* revision id */ 6277 put_smstate(u32, buf, 0x7efc, 0x00020064); 6278 6279 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 6280 6281 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6282 put_smstate(u16, buf, 0x7e90, seg.selector); 6283 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8); 6284 put_smstate(u32, buf, 0x7e94, seg.limit); 6285 put_smstate(u64, buf, 0x7e98, seg.base); 6286 6287 kvm_x86_ops->get_idt(vcpu, &dt); 6288 put_smstate(u32, buf, 0x7e84, dt.size); 6289 put_smstate(u64, buf, 0x7e88, dt.address); 6290 6291 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6292 put_smstate(u16, buf, 0x7e70, seg.selector); 6293 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8); 6294 put_smstate(u32, buf, 0x7e74, seg.limit); 6295 put_smstate(u64, buf, 0x7e78, seg.base); 6296 6297 kvm_x86_ops->get_gdt(vcpu, &dt); 6298 put_smstate(u32, buf, 0x7e64, dt.size); 6299 put_smstate(u64, buf, 0x7e68, dt.address); 6300 6301 for (i = 0; i < 6; i++) 6302 process_smi_save_seg_64(vcpu, buf, i); 6303 #else 6304 WARN_ON_ONCE(1); 6305 #endif 6306 } 6307 6308 static void process_smi(struct kvm_vcpu *vcpu) 6309 { 6310 struct kvm_segment cs, ds; 6311 struct desc_ptr dt; 6312 char buf[512]; 6313 u32 cr0; 6314 6315 if (is_smm(vcpu)) { 6316 vcpu->arch.smi_pending = true; 6317 return; 6318 } 6319 6320 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 6321 vcpu->arch.hflags |= HF_SMM_MASK; 6322 memset(buf, 0, 512); 6323 if (guest_cpuid_has_longmode(vcpu)) 6324 process_smi_save_state_64(vcpu, buf); 6325 else 6326 process_smi_save_state_32(vcpu, buf); 6327 6328 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 6329 6330 if (kvm_x86_ops->get_nmi_mask(vcpu)) 6331 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 6332 else 6333 kvm_x86_ops->set_nmi_mask(vcpu, true); 6334 6335 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 6336 kvm_rip_write(vcpu, 0x8000); 6337 6338 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 6339 kvm_x86_ops->set_cr0(vcpu, cr0); 6340 vcpu->arch.cr0 = cr0; 6341 6342 kvm_x86_ops->set_cr4(vcpu, 0); 6343 6344 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 6345 dt.address = dt.size = 0; 6346 kvm_x86_ops->set_idt(vcpu, &dt); 6347 6348 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 6349 6350 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 6351 cs.base = vcpu->arch.smbase; 6352 6353 ds.selector = 0; 6354 ds.base = 0; 6355 6356 cs.limit = ds.limit = 0xffffffff; 6357 cs.type = ds.type = 0x3; 6358 cs.dpl = ds.dpl = 0; 6359 cs.db = ds.db = 0; 6360 cs.s = ds.s = 1; 6361 cs.l = ds.l = 0; 6362 cs.g = ds.g = 1; 6363 cs.avl = ds.avl = 0; 6364 cs.present = ds.present = 1; 6365 cs.unusable = ds.unusable = 0; 6366 cs.padding = ds.padding = 0; 6367 6368 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 6369 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 6370 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 6371 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 6372 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 6373 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 6374 6375 if (guest_cpuid_has_longmode(vcpu)) 6376 kvm_x86_ops->set_efer(vcpu, 0); 6377 6378 kvm_update_cpuid(vcpu); 6379 kvm_mmu_reset_context(vcpu); 6380 } 6381 6382 void kvm_make_scan_ioapic_request(struct kvm *kvm) 6383 { 6384 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 6385 } 6386 6387 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 6388 { 6389 u64 eoi_exit_bitmap[4]; 6390 6391 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 6392 return; 6393 6394 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 6395 6396 if (irqchip_split(vcpu->kvm)) 6397 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 6398 else { 6399 if (vcpu->arch.apicv_active) 6400 kvm_x86_ops->sync_pir_to_irr(vcpu); 6401 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 6402 } 6403 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, 6404 vcpu_to_synic(vcpu)->vec_bitmap, 256); 6405 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 6406 } 6407 6408 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) 6409 { 6410 ++vcpu->stat.tlb_flush; 6411 kvm_x86_ops->tlb_flush(vcpu); 6412 } 6413 6414 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 6415 { 6416 struct page *page = NULL; 6417 6418 if (!lapic_in_kernel(vcpu)) 6419 return; 6420 6421 if (!kvm_x86_ops->set_apic_access_page_addr) 6422 return; 6423 6424 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 6425 if (is_error_page(page)) 6426 return; 6427 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 6428 6429 /* 6430 * Do not pin apic access page in memory, the MMU notifier 6431 * will call us again if it is migrated or swapped out. 6432 */ 6433 put_page(page); 6434 } 6435 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 6436 6437 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, 6438 unsigned long address) 6439 { 6440 /* 6441 * The physical address of apic access page is stored in the VMCS. 6442 * Update it when it becomes invalid. 6443 */ 6444 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT)) 6445 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 6446 } 6447 6448 /* 6449 * Returns 1 to let vcpu_run() continue the guest execution loop without 6450 * exiting to the userspace. Otherwise, the value will be returned to the 6451 * userspace. 6452 */ 6453 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 6454 { 6455 int r; 6456 bool req_int_win = 6457 dm_request_for_irq_injection(vcpu) && 6458 kvm_cpu_accept_dm_intr(vcpu); 6459 6460 bool req_immediate_exit = false; 6461 6462 if (vcpu->requests) { 6463 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 6464 kvm_mmu_unload(vcpu); 6465 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 6466 __kvm_migrate_timers(vcpu); 6467 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 6468 kvm_gen_update_masterclock(vcpu->kvm); 6469 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 6470 kvm_gen_kvmclock_update(vcpu); 6471 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 6472 r = kvm_guest_time_update(vcpu); 6473 if (unlikely(r)) 6474 goto out; 6475 } 6476 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 6477 kvm_mmu_sync_roots(vcpu); 6478 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 6479 kvm_vcpu_flush_tlb(vcpu); 6480 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 6481 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 6482 r = 0; 6483 goto out; 6484 } 6485 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 6486 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 6487 r = 0; 6488 goto out; 6489 } 6490 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { 6491 vcpu->fpu_active = 0; 6492 kvm_x86_ops->fpu_deactivate(vcpu); 6493 } 6494 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 6495 /* Page is swapped out. Do synthetic halt */ 6496 vcpu->arch.apf.halted = true; 6497 r = 1; 6498 goto out; 6499 } 6500 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 6501 record_steal_time(vcpu); 6502 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 6503 process_smi(vcpu); 6504 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 6505 process_nmi(vcpu); 6506 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 6507 kvm_pmu_handle_event(vcpu); 6508 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 6509 kvm_pmu_deliver_pmi(vcpu); 6510 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 6511 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 6512 if (test_bit(vcpu->arch.pending_ioapic_eoi, 6513 vcpu->arch.ioapic_handled_vectors)) { 6514 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 6515 vcpu->run->eoi.vector = 6516 vcpu->arch.pending_ioapic_eoi; 6517 r = 0; 6518 goto out; 6519 } 6520 } 6521 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 6522 vcpu_scan_ioapic(vcpu); 6523 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 6524 kvm_vcpu_reload_apic_access_page(vcpu); 6525 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 6526 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 6527 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 6528 r = 0; 6529 goto out; 6530 } 6531 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 6532 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 6533 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 6534 r = 0; 6535 goto out; 6536 } 6537 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 6538 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 6539 vcpu->run->hyperv = vcpu->arch.hyperv.exit; 6540 r = 0; 6541 goto out; 6542 } 6543 6544 /* 6545 * KVM_REQ_HV_STIMER has to be processed after 6546 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 6547 * depend on the guest clock being up-to-date 6548 */ 6549 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 6550 kvm_hv_process_stimers(vcpu); 6551 } 6552 6553 /* 6554 * KVM_REQ_EVENT is not set when posted interrupts are set by 6555 * VT-d hardware, so we have to update RVI unconditionally. 6556 */ 6557 if (kvm_lapic_enabled(vcpu)) { 6558 /* 6559 * Update architecture specific hints for APIC 6560 * virtual interrupt delivery. 6561 */ 6562 if (vcpu->arch.apicv_active) 6563 kvm_x86_ops->hwapic_irr_update(vcpu, 6564 kvm_lapic_find_highest_irr(vcpu)); 6565 } 6566 6567 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 6568 kvm_apic_accept_events(vcpu); 6569 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 6570 r = 1; 6571 goto out; 6572 } 6573 6574 if (inject_pending_event(vcpu, req_int_win) != 0) 6575 req_immediate_exit = true; 6576 /* enable NMI/IRQ window open exits if needed */ 6577 else { 6578 if (vcpu->arch.nmi_pending) 6579 kvm_x86_ops->enable_nmi_window(vcpu); 6580 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 6581 kvm_x86_ops->enable_irq_window(vcpu); 6582 } 6583 6584 if (kvm_lapic_enabled(vcpu)) { 6585 update_cr8_intercept(vcpu); 6586 kvm_lapic_sync_to_vapic(vcpu); 6587 } 6588 } 6589 6590 r = kvm_mmu_reload(vcpu); 6591 if (unlikely(r)) { 6592 goto cancel_injection; 6593 } 6594 6595 preempt_disable(); 6596 6597 kvm_x86_ops->prepare_guest_switch(vcpu); 6598 if (vcpu->fpu_active) 6599 kvm_load_guest_fpu(vcpu); 6600 vcpu->mode = IN_GUEST_MODE; 6601 6602 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6603 6604 /* 6605 * We should set ->mode before check ->requests, 6606 * Please see the comment in kvm_make_all_cpus_request. 6607 * This also orders the write to mode from any reads 6608 * to the page tables done while the VCPU is running. 6609 * Please see the comment in kvm_flush_remote_tlbs. 6610 */ 6611 smp_mb__after_srcu_read_unlock(); 6612 6613 local_irq_disable(); 6614 6615 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests 6616 || need_resched() || signal_pending(current)) { 6617 vcpu->mode = OUTSIDE_GUEST_MODE; 6618 smp_wmb(); 6619 local_irq_enable(); 6620 preempt_enable(); 6621 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6622 r = 1; 6623 goto cancel_injection; 6624 } 6625 6626 kvm_load_guest_xcr0(vcpu); 6627 6628 if (req_immediate_exit) 6629 smp_send_reschedule(vcpu->cpu); 6630 6631 trace_kvm_entry(vcpu->vcpu_id); 6632 wait_lapic_expire(vcpu); 6633 __kvm_guest_enter(); 6634 6635 if (unlikely(vcpu->arch.switch_db_regs)) { 6636 set_debugreg(0, 7); 6637 set_debugreg(vcpu->arch.eff_db[0], 0); 6638 set_debugreg(vcpu->arch.eff_db[1], 1); 6639 set_debugreg(vcpu->arch.eff_db[2], 2); 6640 set_debugreg(vcpu->arch.eff_db[3], 3); 6641 set_debugreg(vcpu->arch.dr6, 6); 6642 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 6643 } 6644 6645 kvm_x86_ops->run(vcpu); 6646 6647 /* 6648 * Do this here before restoring debug registers on the host. And 6649 * since we do this before handling the vmexit, a DR access vmexit 6650 * can (a) read the correct value of the debug registers, (b) set 6651 * KVM_DEBUGREG_WONT_EXIT again. 6652 */ 6653 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 6654 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 6655 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 6656 kvm_update_dr0123(vcpu); 6657 kvm_update_dr6(vcpu); 6658 kvm_update_dr7(vcpu); 6659 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 6660 } 6661 6662 /* 6663 * If the guest has used debug registers, at least dr7 6664 * will be disabled while returning to the host. 6665 * If we don't have active breakpoints in the host, we don't 6666 * care about the messed up debug address registers. But if 6667 * we have some of them active, restore the old state. 6668 */ 6669 if (hw_breakpoint_active()) 6670 hw_breakpoint_restore(); 6671 6672 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 6673 6674 vcpu->mode = OUTSIDE_GUEST_MODE; 6675 smp_wmb(); 6676 6677 kvm_put_guest_xcr0(vcpu); 6678 6679 /* Interrupt is enabled by handle_external_intr() */ 6680 kvm_x86_ops->handle_external_intr(vcpu); 6681 6682 ++vcpu->stat.exits; 6683 6684 /* 6685 * We must have an instruction between local_irq_enable() and 6686 * kvm_guest_exit(), so the timer interrupt isn't delayed by 6687 * the interrupt shadow. The stat.exits increment will do nicely. 6688 * But we need to prevent reordering, hence this barrier(): 6689 */ 6690 barrier(); 6691 6692 kvm_guest_exit(); 6693 6694 preempt_enable(); 6695 6696 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6697 6698 /* 6699 * Profile KVM exit RIPs: 6700 */ 6701 if (unlikely(prof_on == KVM_PROFILING)) { 6702 unsigned long rip = kvm_rip_read(vcpu); 6703 profile_hit(KVM_PROFILING, (void *)rip); 6704 } 6705 6706 if (unlikely(vcpu->arch.tsc_always_catchup)) 6707 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6708 6709 if (vcpu->arch.apic_attention) 6710 kvm_lapic_sync_from_vapic(vcpu); 6711 6712 r = kvm_x86_ops->handle_exit(vcpu); 6713 return r; 6714 6715 cancel_injection: 6716 kvm_x86_ops->cancel_injection(vcpu); 6717 if (unlikely(vcpu->arch.apic_attention)) 6718 kvm_lapic_sync_from_vapic(vcpu); 6719 out: 6720 return r; 6721 } 6722 6723 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 6724 { 6725 if (!kvm_arch_vcpu_runnable(vcpu) && 6726 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { 6727 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6728 kvm_vcpu_block(vcpu); 6729 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6730 6731 if (kvm_x86_ops->post_block) 6732 kvm_x86_ops->post_block(vcpu); 6733 6734 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 6735 return 1; 6736 } 6737 6738 kvm_apic_accept_events(vcpu); 6739 switch(vcpu->arch.mp_state) { 6740 case KVM_MP_STATE_HALTED: 6741 vcpu->arch.pv.pv_unhalted = false; 6742 vcpu->arch.mp_state = 6743 KVM_MP_STATE_RUNNABLE; 6744 case KVM_MP_STATE_RUNNABLE: 6745 vcpu->arch.apf.halted = false; 6746 break; 6747 case KVM_MP_STATE_INIT_RECEIVED: 6748 break; 6749 default: 6750 return -EINTR; 6751 break; 6752 } 6753 return 1; 6754 } 6755 6756 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 6757 { 6758 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 6759 !vcpu->arch.apf.halted); 6760 } 6761 6762 static int vcpu_run(struct kvm_vcpu *vcpu) 6763 { 6764 int r; 6765 struct kvm *kvm = vcpu->kvm; 6766 6767 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6768 6769 for (;;) { 6770 if (kvm_vcpu_running(vcpu)) { 6771 r = vcpu_enter_guest(vcpu); 6772 } else { 6773 r = vcpu_block(kvm, vcpu); 6774 } 6775 6776 if (r <= 0) 6777 break; 6778 6779 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); 6780 if (kvm_cpu_has_pending_timer(vcpu)) 6781 kvm_inject_pending_timer_irqs(vcpu); 6782 6783 if (dm_request_for_irq_injection(vcpu) && 6784 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 6785 r = 0; 6786 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 6787 ++vcpu->stat.request_irq_exits; 6788 break; 6789 } 6790 6791 kvm_check_async_pf_completion(vcpu); 6792 6793 if (signal_pending(current)) { 6794 r = -EINTR; 6795 vcpu->run->exit_reason = KVM_EXIT_INTR; 6796 ++vcpu->stat.signal_exits; 6797 break; 6798 } 6799 if (need_resched()) { 6800 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6801 cond_resched(); 6802 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6803 } 6804 } 6805 6806 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6807 6808 return r; 6809 } 6810 6811 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 6812 { 6813 int r; 6814 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6815 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 6816 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6817 if (r != EMULATE_DONE) 6818 return 0; 6819 return 1; 6820 } 6821 6822 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 6823 { 6824 BUG_ON(!vcpu->arch.pio.count); 6825 6826 return complete_emulated_io(vcpu); 6827 } 6828 6829 /* 6830 * Implements the following, as a state machine: 6831 * 6832 * read: 6833 * for each fragment 6834 * for each mmio piece in the fragment 6835 * write gpa, len 6836 * exit 6837 * copy data 6838 * execute insn 6839 * 6840 * write: 6841 * for each fragment 6842 * for each mmio piece in the fragment 6843 * write gpa, len 6844 * copy data 6845 * exit 6846 */ 6847 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 6848 { 6849 struct kvm_run *run = vcpu->run; 6850 struct kvm_mmio_fragment *frag; 6851 unsigned len; 6852 6853 BUG_ON(!vcpu->mmio_needed); 6854 6855 /* Complete previous fragment */ 6856 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 6857 len = min(8u, frag->len); 6858 if (!vcpu->mmio_is_write) 6859 memcpy(frag->data, run->mmio.data, len); 6860 6861 if (frag->len <= 8) { 6862 /* Switch to the next fragment. */ 6863 frag++; 6864 vcpu->mmio_cur_fragment++; 6865 } else { 6866 /* Go forward to the next mmio piece. */ 6867 frag->data += len; 6868 frag->gpa += len; 6869 frag->len -= len; 6870 } 6871 6872 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 6873 vcpu->mmio_needed = 0; 6874 6875 /* FIXME: return into emulator if single-stepping. */ 6876 if (vcpu->mmio_is_write) 6877 return 1; 6878 vcpu->mmio_read_completed = 1; 6879 return complete_emulated_io(vcpu); 6880 } 6881 6882 run->exit_reason = KVM_EXIT_MMIO; 6883 run->mmio.phys_addr = frag->gpa; 6884 if (vcpu->mmio_is_write) 6885 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 6886 run->mmio.len = min(8u, frag->len); 6887 run->mmio.is_write = vcpu->mmio_is_write; 6888 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6889 return 0; 6890 } 6891 6892 6893 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 6894 { 6895 struct fpu *fpu = ¤t->thread.fpu; 6896 int r; 6897 sigset_t sigsaved; 6898 6899 fpu__activate_curr(fpu); 6900 6901 if (vcpu->sigset_active) 6902 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); 6903 6904 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 6905 kvm_vcpu_block(vcpu); 6906 kvm_apic_accept_events(vcpu); 6907 clear_bit(KVM_REQ_UNHALT, &vcpu->requests); 6908 r = -EAGAIN; 6909 goto out; 6910 } 6911 6912 /* re-sync apic's tpr */ 6913 if (!lapic_in_kernel(vcpu)) { 6914 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 6915 r = -EINVAL; 6916 goto out; 6917 } 6918 } 6919 6920 if (unlikely(vcpu->arch.complete_userspace_io)) { 6921 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 6922 vcpu->arch.complete_userspace_io = NULL; 6923 r = cui(vcpu); 6924 if (r <= 0) 6925 goto out; 6926 } else 6927 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 6928 6929 r = vcpu_run(vcpu); 6930 6931 out: 6932 post_kvm_run_save(vcpu); 6933 if (vcpu->sigset_active) 6934 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 6935 6936 return r; 6937 } 6938 6939 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6940 { 6941 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 6942 /* 6943 * We are here if userspace calls get_regs() in the middle of 6944 * instruction emulation. Registers state needs to be copied 6945 * back from emulation context to vcpu. Userspace shouldn't do 6946 * that usually, but some bad designed PV devices (vmware 6947 * backdoor interface) need this to work 6948 */ 6949 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 6950 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6951 } 6952 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 6953 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 6954 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 6955 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 6956 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 6957 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 6958 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 6959 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 6960 #ifdef CONFIG_X86_64 6961 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 6962 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 6963 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 6964 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 6965 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 6966 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 6967 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 6968 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 6969 #endif 6970 6971 regs->rip = kvm_rip_read(vcpu); 6972 regs->rflags = kvm_get_rflags(vcpu); 6973 6974 return 0; 6975 } 6976 6977 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6978 { 6979 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 6980 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6981 6982 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 6983 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 6984 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 6985 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 6986 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 6987 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 6988 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 6989 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 6990 #ifdef CONFIG_X86_64 6991 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 6992 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 6993 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 6994 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 6995 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 6996 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 6997 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 6998 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 6999 #endif 7000 7001 kvm_rip_write(vcpu, regs->rip); 7002 kvm_set_rflags(vcpu, regs->rflags); 7003 7004 vcpu->arch.exception.pending = false; 7005 7006 kvm_make_request(KVM_REQ_EVENT, vcpu); 7007 7008 return 0; 7009 } 7010 7011 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 7012 { 7013 struct kvm_segment cs; 7014 7015 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7016 *db = cs.db; 7017 *l = cs.l; 7018 } 7019 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 7020 7021 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 7022 struct kvm_sregs *sregs) 7023 { 7024 struct desc_ptr dt; 7025 7026 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7027 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7028 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7029 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7030 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7031 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7032 7033 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7034 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7035 7036 kvm_x86_ops->get_idt(vcpu, &dt); 7037 sregs->idt.limit = dt.size; 7038 sregs->idt.base = dt.address; 7039 kvm_x86_ops->get_gdt(vcpu, &dt); 7040 sregs->gdt.limit = dt.size; 7041 sregs->gdt.base = dt.address; 7042 7043 sregs->cr0 = kvm_read_cr0(vcpu); 7044 sregs->cr2 = vcpu->arch.cr2; 7045 sregs->cr3 = kvm_read_cr3(vcpu); 7046 sregs->cr4 = kvm_read_cr4(vcpu); 7047 sregs->cr8 = kvm_get_cr8(vcpu); 7048 sregs->efer = vcpu->arch.efer; 7049 sregs->apic_base = kvm_get_apic_base(vcpu); 7050 7051 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 7052 7053 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) 7054 set_bit(vcpu->arch.interrupt.nr, 7055 (unsigned long *)sregs->interrupt_bitmap); 7056 7057 return 0; 7058 } 7059 7060 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 7061 struct kvm_mp_state *mp_state) 7062 { 7063 kvm_apic_accept_events(vcpu); 7064 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 7065 vcpu->arch.pv.pv_unhalted) 7066 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 7067 else 7068 mp_state->mp_state = vcpu->arch.mp_state; 7069 7070 return 0; 7071 } 7072 7073 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 7074 struct kvm_mp_state *mp_state) 7075 { 7076 if (!lapic_in_kernel(vcpu) && 7077 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 7078 return -EINVAL; 7079 7080 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 7081 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 7082 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 7083 } else 7084 vcpu->arch.mp_state = mp_state->mp_state; 7085 kvm_make_request(KVM_REQ_EVENT, vcpu); 7086 return 0; 7087 } 7088 7089 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 7090 int reason, bool has_error_code, u32 error_code) 7091 { 7092 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 7093 int ret; 7094 7095 init_emulate_ctxt(vcpu); 7096 7097 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 7098 has_error_code, error_code); 7099 7100 if (ret) 7101 return EMULATE_FAIL; 7102 7103 kvm_rip_write(vcpu, ctxt->eip); 7104 kvm_set_rflags(vcpu, ctxt->eflags); 7105 kvm_make_request(KVM_REQ_EVENT, vcpu); 7106 return EMULATE_DONE; 7107 } 7108 EXPORT_SYMBOL_GPL(kvm_task_switch); 7109 7110 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 7111 struct kvm_sregs *sregs) 7112 { 7113 struct msr_data apic_base_msr; 7114 int mmu_reset_needed = 0; 7115 int pending_vec, max_bits, idx; 7116 struct desc_ptr dt; 7117 7118 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) 7119 return -EINVAL; 7120 7121 dt.size = sregs->idt.limit; 7122 dt.address = sregs->idt.base; 7123 kvm_x86_ops->set_idt(vcpu, &dt); 7124 dt.size = sregs->gdt.limit; 7125 dt.address = sregs->gdt.base; 7126 kvm_x86_ops->set_gdt(vcpu, &dt); 7127 7128 vcpu->arch.cr2 = sregs->cr2; 7129 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 7130 vcpu->arch.cr3 = sregs->cr3; 7131 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 7132 7133 kvm_set_cr8(vcpu, sregs->cr8); 7134 7135 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 7136 kvm_x86_ops->set_efer(vcpu, sregs->efer); 7137 apic_base_msr.data = sregs->apic_base; 7138 apic_base_msr.host_initiated = true; 7139 kvm_set_apic_base(vcpu, &apic_base_msr); 7140 7141 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 7142 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 7143 vcpu->arch.cr0 = sregs->cr0; 7144 7145 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 7146 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 7147 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 7148 kvm_update_cpuid(vcpu); 7149 7150 idx = srcu_read_lock(&vcpu->kvm->srcu); 7151 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 7152 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 7153 mmu_reset_needed = 1; 7154 } 7155 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7156 7157 if (mmu_reset_needed) 7158 kvm_mmu_reset_context(vcpu); 7159 7160 max_bits = KVM_NR_INTERRUPTS; 7161 pending_vec = find_first_bit( 7162 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 7163 if (pending_vec < max_bits) { 7164 kvm_queue_interrupt(vcpu, pending_vec, false); 7165 pr_debug("Set back pending irq %d\n", pending_vec); 7166 } 7167 7168 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7169 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7170 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7171 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7172 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7173 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7174 7175 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7176 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7177 7178 update_cr8_intercept(vcpu); 7179 7180 /* Older userspace won't unhalt the vcpu on reset. */ 7181 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 7182 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 7183 !is_protmode(vcpu)) 7184 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7185 7186 kvm_make_request(KVM_REQ_EVENT, vcpu); 7187 7188 return 0; 7189 } 7190 7191 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 7192 struct kvm_guest_debug *dbg) 7193 { 7194 unsigned long rflags; 7195 int i, r; 7196 7197 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 7198 r = -EBUSY; 7199 if (vcpu->arch.exception.pending) 7200 goto out; 7201 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 7202 kvm_queue_exception(vcpu, DB_VECTOR); 7203 else 7204 kvm_queue_exception(vcpu, BP_VECTOR); 7205 } 7206 7207 /* 7208 * Read rflags as long as potentially injected trace flags are still 7209 * filtered out. 7210 */ 7211 rflags = kvm_get_rflags(vcpu); 7212 7213 vcpu->guest_debug = dbg->control; 7214 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 7215 vcpu->guest_debug = 0; 7216 7217 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 7218 for (i = 0; i < KVM_NR_DB_REGS; ++i) 7219 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 7220 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 7221 } else { 7222 for (i = 0; i < KVM_NR_DB_REGS; i++) 7223 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 7224 } 7225 kvm_update_dr7(vcpu); 7226 7227 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 7228 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 7229 get_segment_base(vcpu, VCPU_SREG_CS); 7230 7231 /* 7232 * Trigger an rflags update that will inject or remove the trace 7233 * flags. 7234 */ 7235 kvm_set_rflags(vcpu, rflags); 7236 7237 kvm_x86_ops->update_bp_intercept(vcpu); 7238 7239 r = 0; 7240 7241 out: 7242 7243 return r; 7244 } 7245 7246 /* 7247 * Translate a guest virtual address to a guest physical address. 7248 */ 7249 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 7250 struct kvm_translation *tr) 7251 { 7252 unsigned long vaddr = tr->linear_address; 7253 gpa_t gpa; 7254 int idx; 7255 7256 idx = srcu_read_lock(&vcpu->kvm->srcu); 7257 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 7258 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7259 tr->physical_address = gpa; 7260 tr->valid = gpa != UNMAPPED_GVA; 7261 tr->writeable = 1; 7262 tr->usermode = 0; 7263 7264 return 0; 7265 } 7266 7267 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7268 { 7269 struct fxregs_state *fxsave = 7270 &vcpu->arch.guest_fpu.state.fxsave; 7271 7272 memcpy(fpu->fpr, fxsave->st_space, 128); 7273 fpu->fcw = fxsave->cwd; 7274 fpu->fsw = fxsave->swd; 7275 fpu->ftwx = fxsave->twd; 7276 fpu->last_opcode = fxsave->fop; 7277 fpu->last_ip = fxsave->rip; 7278 fpu->last_dp = fxsave->rdp; 7279 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 7280 7281 return 0; 7282 } 7283 7284 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7285 { 7286 struct fxregs_state *fxsave = 7287 &vcpu->arch.guest_fpu.state.fxsave; 7288 7289 memcpy(fxsave->st_space, fpu->fpr, 128); 7290 fxsave->cwd = fpu->fcw; 7291 fxsave->swd = fpu->fsw; 7292 fxsave->twd = fpu->ftwx; 7293 fxsave->fop = fpu->last_opcode; 7294 fxsave->rip = fpu->last_ip; 7295 fxsave->rdp = fpu->last_dp; 7296 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 7297 7298 return 0; 7299 } 7300 7301 static void fx_init(struct kvm_vcpu *vcpu) 7302 { 7303 fpstate_init(&vcpu->arch.guest_fpu.state); 7304 if (boot_cpu_has(X86_FEATURE_XSAVES)) 7305 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv = 7306 host_xcr0 | XSTATE_COMPACTION_ENABLED; 7307 7308 /* 7309 * Ensure guest xcr0 is valid for loading 7310 */ 7311 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 7312 7313 vcpu->arch.cr0 |= X86_CR0_ET; 7314 } 7315 7316 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 7317 { 7318 if (vcpu->guest_fpu_loaded) 7319 return; 7320 7321 /* 7322 * Restore all possible states in the guest, 7323 * and assume host would use all available bits. 7324 * Guest xcr0 would be loaded later. 7325 */ 7326 vcpu->guest_fpu_loaded = 1; 7327 __kernel_fpu_begin(); 7328 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state); 7329 trace_kvm_fpu(1); 7330 } 7331 7332 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 7333 { 7334 if (!vcpu->guest_fpu_loaded) { 7335 vcpu->fpu_counter = 0; 7336 return; 7337 } 7338 7339 vcpu->guest_fpu_loaded = 0; 7340 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu); 7341 __kernel_fpu_end(); 7342 ++vcpu->stat.fpu_reload; 7343 /* 7344 * If using eager FPU mode, or if the guest is a frequent user 7345 * of the FPU, just leave the FPU active for next time. 7346 * Every 255 times fpu_counter rolls over to 0; a guest that uses 7347 * the FPU in bursts will revert to loading it on demand. 7348 */ 7349 if (!use_eager_fpu()) { 7350 if (++vcpu->fpu_counter < 5) 7351 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); 7352 } 7353 trace_kvm_fpu(0); 7354 } 7355 7356 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 7357 { 7358 kvmclock_reset(vcpu); 7359 7360 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 7361 kvm_x86_ops->vcpu_free(vcpu); 7362 } 7363 7364 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 7365 unsigned int id) 7366 { 7367 struct kvm_vcpu *vcpu; 7368 7369 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 7370 printk_once(KERN_WARNING 7371 "kvm: SMP vm created on host with unstable TSC; " 7372 "guest TSC will not be reliable\n"); 7373 7374 vcpu = kvm_x86_ops->vcpu_create(kvm, id); 7375 7376 return vcpu; 7377 } 7378 7379 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 7380 { 7381 int r; 7382 7383 kvm_vcpu_mtrr_init(vcpu); 7384 r = vcpu_load(vcpu); 7385 if (r) 7386 return r; 7387 kvm_vcpu_reset(vcpu, false); 7388 kvm_mmu_setup(vcpu); 7389 vcpu_put(vcpu); 7390 return r; 7391 } 7392 7393 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 7394 { 7395 struct msr_data msr; 7396 struct kvm *kvm = vcpu->kvm; 7397 7398 if (vcpu_load(vcpu)) 7399 return; 7400 msr.data = 0x0; 7401 msr.index = MSR_IA32_TSC; 7402 msr.host_initiated = true; 7403 kvm_write_tsc(vcpu, &msr); 7404 vcpu_put(vcpu); 7405 7406 if (!kvmclock_periodic_sync) 7407 return; 7408 7409 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 7410 KVMCLOCK_SYNC_PERIOD); 7411 } 7412 7413 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 7414 { 7415 int r; 7416 vcpu->arch.apf.msr_val = 0; 7417 7418 r = vcpu_load(vcpu); 7419 BUG_ON(r); 7420 kvm_mmu_unload(vcpu); 7421 vcpu_put(vcpu); 7422 7423 kvm_x86_ops->vcpu_free(vcpu); 7424 } 7425 7426 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 7427 { 7428 vcpu->arch.hflags = 0; 7429 7430 atomic_set(&vcpu->arch.nmi_queued, 0); 7431 vcpu->arch.nmi_pending = 0; 7432 vcpu->arch.nmi_injected = false; 7433 kvm_clear_interrupt_queue(vcpu); 7434 kvm_clear_exception_queue(vcpu); 7435 7436 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 7437 kvm_update_dr0123(vcpu); 7438 vcpu->arch.dr6 = DR6_INIT; 7439 kvm_update_dr6(vcpu); 7440 vcpu->arch.dr7 = DR7_FIXED_1; 7441 kvm_update_dr7(vcpu); 7442 7443 vcpu->arch.cr2 = 0; 7444 7445 kvm_make_request(KVM_REQ_EVENT, vcpu); 7446 vcpu->arch.apf.msr_val = 0; 7447 vcpu->arch.st.msr_val = 0; 7448 7449 kvmclock_reset(vcpu); 7450 7451 kvm_clear_async_pf_completion_queue(vcpu); 7452 kvm_async_pf_hash_reset(vcpu); 7453 vcpu->arch.apf.halted = false; 7454 7455 if (!init_event) { 7456 kvm_pmu_reset(vcpu); 7457 vcpu->arch.smbase = 0x30000; 7458 } 7459 7460 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 7461 vcpu->arch.regs_avail = ~0; 7462 vcpu->arch.regs_dirty = ~0; 7463 7464 kvm_x86_ops->vcpu_reset(vcpu, init_event); 7465 } 7466 7467 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 7468 { 7469 struct kvm_segment cs; 7470 7471 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7472 cs.selector = vector << 8; 7473 cs.base = vector << 12; 7474 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7475 kvm_rip_write(vcpu, 0); 7476 } 7477 7478 int kvm_arch_hardware_enable(void) 7479 { 7480 struct kvm *kvm; 7481 struct kvm_vcpu *vcpu; 7482 int i; 7483 int ret; 7484 u64 local_tsc; 7485 u64 max_tsc = 0; 7486 bool stable, backwards_tsc = false; 7487 7488 kvm_shared_msr_cpu_online(); 7489 ret = kvm_x86_ops->hardware_enable(); 7490 if (ret != 0) 7491 return ret; 7492 7493 local_tsc = rdtsc(); 7494 stable = !check_tsc_unstable(); 7495 list_for_each_entry(kvm, &vm_list, vm_list) { 7496 kvm_for_each_vcpu(i, vcpu, kvm) { 7497 if (!stable && vcpu->cpu == smp_processor_id()) 7498 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7499 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 7500 backwards_tsc = true; 7501 if (vcpu->arch.last_host_tsc > max_tsc) 7502 max_tsc = vcpu->arch.last_host_tsc; 7503 } 7504 } 7505 } 7506 7507 /* 7508 * Sometimes, even reliable TSCs go backwards. This happens on 7509 * platforms that reset TSC during suspend or hibernate actions, but 7510 * maintain synchronization. We must compensate. Fortunately, we can 7511 * detect that condition here, which happens early in CPU bringup, 7512 * before any KVM threads can be running. Unfortunately, we can't 7513 * bring the TSCs fully up to date with real time, as we aren't yet far 7514 * enough into CPU bringup that we know how much real time has actually 7515 * elapsed; our helper function, get_kernel_ns() will be using boot 7516 * variables that haven't been updated yet. 7517 * 7518 * So we simply find the maximum observed TSC above, then record the 7519 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 7520 * the adjustment will be applied. Note that we accumulate 7521 * adjustments, in case multiple suspend cycles happen before some VCPU 7522 * gets a chance to run again. In the event that no KVM threads get a 7523 * chance to run, we will miss the entire elapsed period, as we'll have 7524 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 7525 * loose cycle time. This isn't too big a deal, since the loss will be 7526 * uniform across all VCPUs (not to mention the scenario is extremely 7527 * unlikely). It is possible that a second hibernate recovery happens 7528 * much faster than a first, causing the observed TSC here to be 7529 * smaller; this would require additional padding adjustment, which is 7530 * why we set last_host_tsc to the local tsc observed here. 7531 * 7532 * N.B. - this code below runs only on platforms with reliable TSC, 7533 * as that is the only way backwards_tsc is set above. Also note 7534 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 7535 * have the same delta_cyc adjustment applied if backwards_tsc 7536 * is detected. Note further, this adjustment is only done once, 7537 * as we reset last_host_tsc on all VCPUs to stop this from being 7538 * called multiple times (one for each physical CPU bringup). 7539 * 7540 * Platforms with unreliable TSCs don't have to deal with this, they 7541 * will be compensated by the logic in vcpu_load, which sets the TSC to 7542 * catchup mode. This will catchup all VCPUs to real time, but cannot 7543 * guarantee that they stay in perfect synchronization. 7544 */ 7545 if (backwards_tsc) { 7546 u64 delta_cyc = max_tsc - local_tsc; 7547 backwards_tsc_observed = true; 7548 list_for_each_entry(kvm, &vm_list, vm_list) { 7549 kvm_for_each_vcpu(i, vcpu, kvm) { 7550 vcpu->arch.tsc_offset_adjustment += delta_cyc; 7551 vcpu->arch.last_host_tsc = local_tsc; 7552 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7553 } 7554 7555 /* 7556 * We have to disable TSC offset matching.. if you were 7557 * booting a VM while issuing an S4 host suspend.... 7558 * you may have some problem. Solving this issue is 7559 * left as an exercise to the reader. 7560 */ 7561 kvm->arch.last_tsc_nsec = 0; 7562 kvm->arch.last_tsc_write = 0; 7563 } 7564 7565 } 7566 return 0; 7567 } 7568 7569 void kvm_arch_hardware_disable(void) 7570 { 7571 kvm_x86_ops->hardware_disable(); 7572 drop_user_return_notifiers(); 7573 } 7574 7575 int kvm_arch_hardware_setup(void) 7576 { 7577 int r; 7578 7579 r = kvm_x86_ops->hardware_setup(); 7580 if (r != 0) 7581 return r; 7582 7583 if (kvm_has_tsc_control) { 7584 /* 7585 * Make sure the user can only configure tsc_khz values that 7586 * fit into a signed integer. 7587 * A min value is not calculated needed because it will always 7588 * be 1 on all machines. 7589 */ 7590 u64 max = min(0x7fffffffULL, 7591 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 7592 kvm_max_guest_tsc_khz = max; 7593 7594 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 7595 } 7596 7597 kvm_init_msr_list(); 7598 return 0; 7599 } 7600 7601 void kvm_arch_hardware_unsetup(void) 7602 { 7603 kvm_x86_ops->hardware_unsetup(); 7604 } 7605 7606 void kvm_arch_check_processor_compat(void *rtn) 7607 { 7608 kvm_x86_ops->check_processor_compatibility(rtn); 7609 } 7610 7611 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 7612 { 7613 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 7614 } 7615 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 7616 7617 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 7618 { 7619 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 7620 } 7621 7622 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) 7623 { 7624 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu); 7625 } 7626 7627 struct static_key kvm_no_apic_vcpu __read_mostly; 7628 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); 7629 7630 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 7631 { 7632 struct page *page; 7633 struct kvm *kvm; 7634 int r; 7635 7636 BUG_ON(vcpu->kvm == NULL); 7637 kvm = vcpu->kvm; 7638 7639 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(); 7640 vcpu->arch.pv.pv_unhalted = false; 7641 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 7642 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 7643 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7644 else 7645 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 7646 7647 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 7648 if (!page) { 7649 r = -ENOMEM; 7650 goto fail; 7651 } 7652 vcpu->arch.pio_data = page_address(page); 7653 7654 kvm_set_tsc_khz(vcpu, max_tsc_khz); 7655 7656 r = kvm_mmu_create(vcpu); 7657 if (r < 0) 7658 goto fail_free_pio_data; 7659 7660 if (irqchip_in_kernel(kvm)) { 7661 r = kvm_create_lapic(vcpu); 7662 if (r < 0) 7663 goto fail_mmu_destroy; 7664 } else 7665 static_key_slow_inc(&kvm_no_apic_vcpu); 7666 7667 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 7668 GFP_KERNEL); 7669 if (!vcpu->arch.mce_banks) { 7670 r = -ENOMEM; 7671 goto fail_free_lapic; 7672 } 7673 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 7674 7675 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 7676 r = -ENOMEM; 7677 goto fail_free_mce_banks; 7678 } 7679 7680 fx_init(vcpu); 7681 7682 vcpu->arch.ia32_tsc_adjust_msr = 0x0; 7683 vcpu->arch.pv_time_enabled = false; 7684 7685 vcpu->arch.guest_supported_xcr0 = 0; 7686 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 7687 7688 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 7689 7690 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 7691 7692 kvm_async_pf_hash_reset(vcpu); 7693 kvm_pmu_init(vcpu); 7694 7695 vcpu->arch.pending_external_vector = -1; 7696 7697 kvm_hv_vcpu_init(vcpu); 7698 7699 return 0; 7700 7701 fail_free_mce_banks: 7702 kfree(vcpu->arch.mce_banks); 7703 fail_free_lapic: 7704 kvm_free_lapic(vcpu); 7705 fail_mmu_destroy: 7706 kvm_mmu_destroy(vcpu); 7707 fail_free_pio_data: 7708 free_page((unsigned long)vcpu->arch.pio_data); 7709 fail: 7710 return r; 7711 } 7712 7713 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 7714 { 7715 int idx; 7716 7717 kvm_hv_vcpu_uninit(vcpu); 7718 kvm_pmu_destroy(vcpu); 7719 kfree(vcpu->arch.mce_banks); 7720 kvm_free_lapic(vcpu); 7721 idx = srcu_read_lock(&vcpu->kvm->srcu); 7722 kvm_mmu_destroy(vcpu); 7723 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7724 free_page((unsigned long)vcpu->arch.pio_data); 7725 if (!lapic_in_kernel(vcpu)) 7726 static_key_slow_dec(&kvm_no_apic_vcpu); 7727 } 7728 7729 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 7730 { 7731 kvm_x86_ops->sched_in(vcpu, cpu); 7732 } 7733 7734 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 7735 { 7736 if (type) 7737 return -EINVAL; 7738 7739 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 7740 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 7741 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 7742 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 7743 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 7744 7745 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 7746 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 7747 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 7748 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 7749 &kvm->arch.irq_sources_bitmap); 7750 7751 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 7752 mutex_init(&kvm->arch.apic_map_lock); 7753 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 7754 7755 pvclock_update_vm_gtod_copy(kvm); 7756 7757 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 7758 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 7759 7760 kvm_page_track_init(kvm); 7761 kvm_mmu_init_vm(kvm); 7762 7763 if (kvm_x86_ops->vm_init) 7764 return kvm_x86_ops->vm_init(kvm); 7765 7766 return 0; 7767 } 7768 7769 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 7770 { 7771 int r; 7772 r = vcpu_load(vcpu); 7773 BUG_ON(r); 7774 kvm_mmu_unload(vcpu); 7775 vcpu_put(vcpu); 7776 } 7777 7778 static void kvm_free_vcpus(struct kvm *kvm) 7779 { 7780 unsigned int i; 7781 struct kvm_vcpu *vcpu; 7782 7783 /* 7784 * Unpin any mmu pages first. 7785 */ 7786 kvm_for_each_vcpu(i, vcpu, kvm) { 7787 kvm_clear_async_pf_completion_queue(vcpu); 7788 kvm_unload_vcpu_mmu(vcpu); 7789 } 7790 kvm_for_each_vcpu(i, vcpu, kvm) 7791 kvm_arch_vcpu_free(vcpu); 7792 7793 mutex_lock(&kvm->lock); 7794 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 7795 kvm->vcpus[i] = NULL; 7796 7797 atomic_set(&kvm->online_vcpus, 0); 7798 mutex_unlock(&kvm->lock); 7799 } 7800 7801 void kvm_arch_sync_events(struct kvm *kvm) 7802 { 7803 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 7804 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 7805 kvm_free_all_assigned_devices(kvm); 7806 kvm_free_pit(kvm); 7807 } 7808 7809 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 7810 { 7811 int i, r; 7812 unsigned long hva; 7813 struct kvm_memslots *slots = kvm_memslots(kvm); 7814 struct kvm_memory_slot *slot, old; 7815 7816 /* Called with kvm->slots_lock held. */ 7817 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 7818 return -EINVAL; 7819 7820 slot = id_to_memslot(slots, id); 7821 if (size) { 7822 if (slot->npages) 7823 return -EEXIST; 7824 7825 /* 7826 * MAP_SHARED to prevent internal slot pages from being moved 7827 * by fork()/COW. 7828 */ 7829 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 7830 MAP_SHARED | MAP_ANONYMOUS, 0); 7831 if (IS_ERR((void *)hva)) 7832 return PTR_ERR((void *)hva); 7833 } else { 7834 if (!slot->npages) 7835 return 0; 7836 7837 hva = 0; 7838 } 7839 7840 old = *slot; 7841 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 7842 struct kvm_userspace_memory_region m; 7843 7844 m.slot = id | (i << 16); 7845 m.flags = 0; 7846 m.guest_phys_addr = gpa; 7847 m.userspace_addr = hva; 7848 m.memory_size = size; 7849 r = __kvm_set_memory_region(kvm, &m); 7850 if (r < 0) 7851 return r; 7852 } 7853 7854 if (!size) { 7855 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); 7856 WARN_ON(r < 0); 7857 } 7858 7859 return 0; 7860 } 7861 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 7862 7863 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 7864 { 7865 int r; 7866 7867 mutex_lock(&kvm->slots_lock); 7868 r = __x86_set_memory_region(kvm, id, gpa, size); 7869 mutex_unlock(&kvm->slots_lock); 7870 7871 return r; 7872 } 7873 EXPORT_SYMBOL_GPL(x86_set_memory_region); 7874 7875 void kvm_arch_destroy_vm(struct kvm *kvm) 7876 { 7877 if (current->mm == kvm->mm) { 7878 /* 7879 * Free memory regions allocated on behalf of userspace, 7880 * unless the the memory map has changed due to process exit 7881 * or fd copying. 7882 */ 7883 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); 7884 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); 7885 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 7886 } 7887 if (kvm_x86_ops->vm_destroy) 7888 kvm_x86_ops->vm_destroy(kvm); 7889 kvm_iommu_unmap_guest(kvm); 7890 kfree(kvm->arch.vpic); 7891 kfree(kvm->arch.vioapic); 7892 kvm_free_vcpus(kvm); 7893 kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 7894 kvm_mmu_uninit_vm(kvm); 7895 } 7896 7897 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 7898 struct kvm_memory_slot *dont) 7899 { 7900 int i; 7901 7902 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7903 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 7904 kvfree(free->arch.rmap[i]); 7905 free->arch.rmap[i] = NULL; 7906 } 7907 if (i == 0) 7908 continue; 7909 7910 if (!dont || free->arch.lpage_info[i - 1] != 7911 dont->arch.lpage_info[i - 1]) { 7912 kvfree(free->arch.lpage_info[i - 1]); 7913 free->arch.lpage_info[i - 1] = NULL; 7914 } 7915 } 7916 7917 kvm_page_track_free_memslot(free, dont); 7918 } 7919 7920 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 7921 unsigned long npages) 7922 { 7923 int i; 7924 7925 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7926 struct kvm_lpage_info *linfo; 7927 unsigned long ugfn; 7928 int lpages; 7929 int level = i + 1; 7930 7931 lpages = gfn_to_index(slot->base_gfn + npages - 1, 7932 slot->base_gfn, level) + 1; 7933 7934 slot->arch.rmap[i] = 7935 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); 7936 if (!slot->arch.rmap[i]) 7937 goto out_free; 7938 if (i == 0) 7939 continue; 7940 7941 linfo = kvm_kvzalloc(lpages * sizeof(*linfo)); 7942 if (!linfo) 7943 goto out_free; 7944 7945 slot->arch.lpage_info[i - 1] = linfo; 7946 7947 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 7948 linfo[0].disallow_lpage = 1; 7949 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 7950 linfo[lpages - 1].disallow_lpage = 1; 7951 ugfn = slot->userspace_addr >> PAGE_SHIFT; 7952 /* 7953 * If the gfn and userspace address are not aligned wrt each 7954 * other, or if explicitly asked to, disable large page 7955 * support for this slot 7956 */ 7957 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 7958 !kvm_largepages_enabled()) { 7959 unsigned long j; 7960 7961 for (j = 0; j < lpages; ++j) 7962 linfo[j].disallow_lpage = 1; 7963 } 7964 } 7965 7966 if (kvm_page_track_create_memslot(slot, npages)) 7967 goto out_free; 7968 7969 return 0; 7970 7971 out_free: 7972 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7973 kvfree(slot->arch.rmap[i]); 7974 slot->arch.rmap[i] = NULL; 7975 if (i == 0) 7976 continue; 7977 7978 kvfree(slot->arch.lpage_info[i - 1]); 7979 slot->arch.lpage_info[i - 1] = NULL; 7980 } 7981 return -ENOMEM; 7982 } 7983 7984 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) 7985 { 7986 /* 7987 * memslots->generation has been incremented. 7988 * mmio generation may have reached its maximum value. 7989 */ 7990 kvm_mmu_invalidate_mmio_sptes(kvm, slots); 7991 } 7992 7993 int kvm_arch_prepare_memory_region(struct kvm *kvm, 7994 struct kvm_memory_slot *memslot, 7995 const struct kvm_userspace_memory_region *mem, 7996 enum kvm_mr_change change) 7997 { 7998 return 0; 7999 } 8000 8001 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 8002 struct kvm_memory_slot *new) 8003 { 8004 /* Still write protect RO slot */ 8005 if (new->flags & KVM_MEM_READONLY) { 8006 kvm_mmu_slot_remove_write_access(kvm, new); 8007 return; 8008 } 8009 8010 /* 8011 * Call kvm_x86_ops dirty logging hooks when they are valid. 8012 * 8013 * kvm_x86_ops->slot_disable_log_dirty is called when: 8014 * 8015 * - KVM_MR_CREATE with dirty logging is disabled 8016 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 8017 * 8018 * The reason is, in case of PML, we need to set D-bit for any slots 8019 * with dirty logging disabled in order to eliminate unnecessary GPA 8020 * logging in PML buffer (and potential PML buffer full VMEXT). This 8021 * guarantees leaving PML enabled during guest's lifetime won't have 8022 * any additonal overhead from PML when guest is running with dirty 8023 * logging disabled for memory slots. 8024 * 8025 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 8026 * to dirty logging mode. 8027 * 8028 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 8029 * 8030 * In case of write protect: 8031 * 8032 * Write protect all pages for dirty logging. 8033 * 8034 * All the sptes including the large sptes which point to this 8035 * slot are set to readonly. We can not create any new large 8036 * spte on this slot until the end of the logging. 8037 * 8038 * See the comments in fast_page_fault(). 8039 */ 8040 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 8041 if (kvm_x86_ops->slot_enable_log_dirty) 8042 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 8043 else 8044 kvm_mmu_slot_remove_write_access(kvm, new); 8045 } else { 8046 if (kvm_x86_ops->slot_disable_log_dirty) 8047 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 8048 } 8049 } 8050 8051 void kvm_arch_commit_memory_region(struct kvm *kvm, 8052 const struct kvm_userspace_memory_region *mem, 8053 const struct kvm_memory_slot *old, 8054 const struct kvm_memory_slot *new, 8055 enum kvm_mr_change change) 8056 { 8057 int nr_mmu_pages = 0; 8058 8059 if (!kvm->arch.n_requested_mmu_pages) 8060 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 8061 8062 if (nr_mmu_pages) 8063 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 8064 8065 /* 8066 * Dirty logging tracks sptes in 4k granularity, meaning that large 8067 * sptes have to be split. If live migration is successful, the guest 8068 * in the source machine will be destroyed and large sptes will be 8069 * created in the destination. However, if the guest continues to run 8070 * in the source machine (for example if live migration fails), small 8071 * sptes will remain around and cause bad performance. 8072 * 8073 * Scan sptes if dirty logging has been stopped, dropping those 8074 * which can be collapsed into a single large-page spte. Later 8075 * page faults will create the large-page sptes. 8076 */ 8077 if ((change != KVM_MR_DELETE) && 8078 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 8079 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 8080 kvm_mmu_zap_collapsible_sptes(kvm, new); 8081 8082 /* 8083 * Set up write protection and/or dirty logging for the new slot. 8084 * 8085 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 8086 * been zapped so no dirty logging staff is needed for old slot. For 8087 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 8088 * new and it's also covered when dealing with the new slot. 8089 * 8090 * FIXME: const-ify all uses of struct kvm_memory_slot. 8091 */ 8092 if (change != KVM_MR_DELETE) 8093 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 8094 } 8095 8096 void kvm_arch_flush_shadow_all(struct kvm *kvm) 8097 { 8098 kvm_mmu_invalidate_zap_all_pages(kvm); 8099 } 8100 8101 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 8102 struct kvm_memory_slot *slot) 8103 { 8104 kvm_mmu_invalidate_zap_all_pages(kvm); 8105 } 8106 8107 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 8108 { 8109 if (!list_empty_careful(&vcpu->async_pf.done)) 8110 return true; 8111 8112 if (kvm_apic_has_events(vcpu)) 8113 return true; 8114 8115 if (vcpu->arch.pv.pv_unhalted) 8116 return true; 8117 8118 if (atomic_read(&vcpu->arch.nmi_queued)) 8119 return true; 8120 8121 if (test_bit(KVM_REQ_SMI, &vcpu->requests)) 8122 return true; 8123 8124 if (kvm_arch_interrupt_allowed(vcpu) && 8125 kvm_cpu_has_interrupt(vcpu)) 8126 return true; 8127 8128 if (kvm_hv_has_stimer_pending(vcpu)) 8129 return true; 8130 8131 return false; 8132 } 8133 8134 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 8135 { 8136 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 8137 kvm_x86_ops->check_nested_events(vcpu, false); 8138 8139 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 8140 } 8141 8142 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 8143 { 8144 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 8145 } 8146 8147 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 8148 { 8149 return kvm_x86_ops->interrupt_allowed(vcpu); 8150 } 8151 8152 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 8153 { 8154 if (is_64_bit_mode(vcpu)) 8155 return kvm_rip_read(vcpu); 8156 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 8157 kvm_rip_read(vcpu)); 8158 } 8159 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 8160 8161 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 8162 { 8163 return kvm_get_linear_rip(vcpu) == linear_rip; 8164 } 8165 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 8166 8167 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 8168 { 8169 unsigned long rflags; 8170 8171 rflags = kvm_x86_ops->get_rflags(vcpu); 8172 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 8173 rflags &= ~X86_EFLAGS_TF; 8174 return rflags; 8175 } 8176 EXPORT_SYMBOL_GPL(kvm_get_rflags); 8177 8178 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8179 { 8180 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 8181 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 8182 rflags |= X86_EFLAGS_TF; 8183 kvm_x86_ops->set_rflags(vcpu, rflags); 8184 } 8185 8186 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8187 { 8188 __kvm_set_rflags(vcpu, rflags); 8189 kvm_make_request(KVM_REQ_EVENT, vcpu); 8190 } 8191 EXPORT_SYMBOL_GPL(kvm_set_rflags); 8192 8193 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 8194 { 8195 int r; 8196 8197 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 8198 work->wakeup_all) 8199 return; 8200 8201 r = kvm_mmu_reload(vcpu); 8202 if (unlikely(r)) 8203 return; 8204 8205 if (!vcpu->arch.mmu.direct_map && 8206 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 8207 return; 8208 8209 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 8210 } 8211 8212 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 8213 { 8214 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 8215 } 8216 8217 static inline u32 kvm_async_pf_next_probe(u32 key) 8218 { 8219 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 8220 } 8221 8222 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8223 { 8224 u32 key = kvm_async_pf_hash_fn(gfn); 8225 8226 while (vcpu->arch.apf.gfns[key] != ~0) 8227 key = kvm_async_pf_next_probe(key); 8228 8229 vcpu->arch.apf.gfns[key] = gfn; 8230 } 8231 8232 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 8233 { 8234 int i; 8235 u32 key = kvm_async_pf_hash_fn(gfn); 8236 8237 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 8238 (vcpu->arch.apf.gfns[key] != gfn && 8239 vcpu->arch.apf.gfns[key] != ~0); i++) 8240 key = kvm_async_pf_next_probe(key); 8241 8242 return key; 8243 } 8244 8245 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8246 { 8247 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 8248 } 8249 8250 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8251 { 8252 u32 i, j, k; 8253 8254 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 8255 while (true) { 8256 vcpu->arch.apf.gfns[i] = ~0; 8257 do { 8258 j = kvm_async_pf_next_probe(j); 8259 if (vcpu->arch.apf.gfns[j] == ~0) 8260 return; 8261 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 8262 /* 8263 * k lies cyclically in ]i,j] 8264 * | i.k.j | 8265 * |....j i.k.| or |.k..j i...| 8266 */ 8267 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 8268 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 8269 i = j; 8270 } 8271 } 8272 8273 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 8274 { 8275 8276 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 8277 sizeof(val)); 8278 } 8279 8280 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 8281 struct kvm_async_pf *work) 8282 { 8283 struct x86_exception fault; 8284 8285 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 8286 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 8287 8288 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 8289 (vcpu->arch.apf.send_user_only && 8290 kvm_x86_ops->get_cpl(vcpu) == 0)) 8291 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 8292 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 8293 fault.vector = PF_VECTOR; 8294 fault.error_code_valid = true; 8295 fault.error_code = 0; 8296 fault.nested_page_fault = false; 8297 fault.address = work->arch.token; 8298 kvm_inject_page_fault(vcpu, &fault); 8299 } 8300 } 8301 8302 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 8303 struct kvm_async_pf *work) 8304 { 8305 struct x86_exception fault; 8306 8307 trace_kvm_async_pf_ready(work->arch.token, work->gva); 8308 if (work->wakeup_all) 8309 work->arch.token = ~0; /* broadcast wakeup */ 8310 else 8311 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 8312 8313 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && 8314 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 8315 fault.vector = PF_VECTOR; 8316 fault.error_code_valid = true; 8317 fault.error_code = 0; 8318 fault.nested_page_fault = false; 8319 fault.address = work->arch.token; 8320 kvm_inject_page_fault(vcpu, &fault); 8321 } 8322 vcpu->arch.apf.halted = false; 8323 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8324 } 8325 8326 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 8327 { 8328 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 8329 return true; 8330 else 8331 return !kvm_event_needs_reinjection(vcpu) && 8332 kvm_x86_ops->interrupt_allowed(vcpu); 8333 } 8334 8335 void kvm_arch_start_assignment(struct kvm *kvm) 8336 { 8337 atomic_inc(&kvm->arch.assigned_device_count); 8338 } 8339 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 8340 8341 void kvm_arch_end_assignment(struct kvm *kvm) 8342 { 8343 atomic_dec(&kvm->arch.assigned_device_count); 8344 } 8345 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 8346 8347 bool kvm_arch_has_assigned_device(struct kvm *kvm) 8348 { 8349 return atomic_read(&kvm->arch.assigned_device_count); 8350 } 8351 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 8352 8353 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 8354 { 8355 atomic_inc(&kvm->arch.noncoherent_dma_count); 8356 } 8357 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 8358 8359 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 8360 { 8361 atomic_dec(&kvm->arch.noncoherent_dma_count); 8362 } 8363 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 8364 8365 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 8366 { 8367 return atomic_read(&kvm->arch.noncoherent_dma_count); 8368 } 8369 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 8370 8371 bool kvm_arch_has_irq_bypass(void) 8372 { 8373 return kvm_x86_ops->update_pi_irte != NULL; 8374 } 8375 8376 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 8377 struct irq_bypass_producer *prod) 8378 { 8379 struct kvm_kernel_irqfd *irqfd = 8380 container_of(cons, struct kvm_kernel_irqfd, consumer); 8381 8382 irqfd->producer = prod; 8383 8384 return kvm_x86_ops->update_pi_irte(irqfd->kvm, 8385 prod->irq, irqfd->gsi, 1); 8386 } 8387 8388 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 8389 struct irq_bypass_producer *prod) 8390 { 8391 int ret; 8392 struct kvm_kernel_irqfd *irqfd = 8393 container_of(cons, struct kvm_kernel_irqfd, consumer); 8394 8395 WARN_ON(irqfd->producer != prod); 8396 irqfd->producer = NULL; 8397 8398 /* 8399 * When producer of consumer is unregistered, we change back to 8400 * remapped mode, so we can re-use the current implementation 8401 * when the irq is masked/disabed or the consumer side (KVM 8402 * int this case doesn't want to receive the interrupts. 8403 */ 8404 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 8405 if (ret) 8406 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 8407 " fails: %d\n", irqfd->consumer.token, ret); 8408 } 8409 8410 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 8411 uint32_t guest_irq, bool set) 8412 { 8413 if (!kvm_x86_ops->update_pi_irte) 8414 return -EINVAL; 8415 8416 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); 8417 } 8418 8419 bool kvm_vector_hashing_enabled(void) 8420 { 8421 return vector_hashing; 8422 } 8423 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled); 8424 8425 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 8426 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 8427 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 8428 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 8429 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 8430 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 8431 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 8432 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 8433 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 8434 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 8435 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 8436 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 8437 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 8438 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 8439 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 8440 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 8441 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 8442 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 8443 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 8444