1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * derived from drivers/kvm/kvm_main.c 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright (C) 2008 Qumranet, Inc. 9 * Copyright IBM Corporation, 2008 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 11 * 12 * Authors: 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * Amit Shah <amit.shah@qumranet.com> 16 * Ben-Ami Yassour <benami@il.ibm.com> 17 */ 18 19 #include <linux/kvm_host.h> 20 #include "irq.h" 21 #include "ioapic.h" 22 #include "mmu.h" 23 #include "i8254.h" 24 #include "tss.h" 25 #include "kvm_cache_regs.h" 26 #include "kvm_emulate.h" 27 #include "x86.h" 28 #include "cpuid.h" 29 #include "pmu.h" 30 #include "hyperv.h" 31 #include "lapic.h" 32 #include "xen.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/export.h> 40 #include <linux/moduleparam.h> 41 #include <linux/mman.h> 42 #include <linux/highmem.h> 43 #include <linux/iommu.h> 44 #include <linux/intel-iommu.h> 45 #include <linux/cpufreq.h> 46 #include <linux/user-return-notifier.h> 47 #include <linux/srcu.h> 48 #include <linux/slab.h> 49 #include <linux/perf_event.h> 50 #include <linux/uaccess.h> 51 #include <linux/hash.h> 52 #include <linux/pci.h> 53 #include <linux/timekeeper_internal.h> 54 #include <linux/pvclock_gtod.h> 55 #include <linux/kvm_irqfd.h> 56 #include <linux/irqbypass.h> 57 #include <linux/sched/stat.h> 58 #include <linux/sched/isolation.h> 59 #include <linux/mem_encrypt.h> 60 #include <linux/entry-kvm.h> 61 #include <linux/suspend.h> 62 63 #include <trace/events/kvm.h> 64 65 #include <asm/debugreg.h> 66 #include <asm/msr.h> 67 #include <asm/desc.h> 68 #include <asm/mce.h> 69 #include <asm/pkru.h> 70 #include <linux/kernel_stat.h> 71 #include <asm/fpu/api.h> 72 #include <asm/fpu/xcr.h> 73 #include <asm/fpu/xstate.h> 74 #include <asm/pvclock.h> 75 #include <asm/div64.h> 76 #include <asm/irq_remapping.h> 77 #include <asm/mshyperv.h> 78 #include <asm/hypervisor.h> 79 #include <asm/tlbflush.h> 80 #include <asm/intel_pt.h> 81 #include <asm/emulate_prefix.h> 82 #include <asm/sgx.h> 83 #include <clocksource/hyperv_timer.h> 84 85 #define CREATE_TRACE_POINTS 86 #include "trace.h" 87 88 #define MAX_IO_MSRS 256 89 #define KVM_MAX_MCE_BANKS 32 90 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 91 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 92 93 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) 94 95 #define emul_to_vcpu(ctxt) \ 96 ((struct kvm_vcpu *)(ctxt)->vcpu) 97 98 /* EFER defaults: 99 * - enable syscall per default because its emulated by KVM 100 * - enable LME and LMA per default on 64 bit KVM 101 */ 102 #ifdef CONFIG_X86_64 103 static 104 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 105 #else 106 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 107 #endif 108 109 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; 110 111 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) 112 113 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE 114 115 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 116 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 117 118 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 119 static void process_nmi(struct kvm_vcpu *vcpu); 120 static void process_smi(struct kvm_vcpu *vcpu); 121 static void enter_smm(struct kvm_vcpu *vcpu); 122 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 123 static void store_regs(struct kvm_vcpu *vcpu); 124 static int sync_regs(struct kvm_vcpu *vcpu); 125 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu); 126 127 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 128 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 129 130 struct kvm_x86_ops kvm_x86_ops __read_mostly; 131 132 #define KVM_X86_OP(func) \ 133 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ 134 *(((struct kvm_x86_ops *)0)->func)); 135 #define KVM_X86_OP_OPTIONAL KVM_X86_OP 136 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP 137 #include <asm/kvm-x86-ops.h> 138 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); 139 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); 140 141 static bool __read_mostly ignore_msrs = 0; 142 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 143 144 bool __read_mostly report_ignored_msrs = true; 145 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 146 EXPORT_SYMBOL_GPL(report_ignored_msrs); 147 148 unsigned int min_timer_period_us = 200; 149 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 150 151 static bool __read_mostly kvmclock_periodic_sync = true; 152 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 153 154 bool __read_mostly kvm_has_tsc_control; 155 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 156 u32 __read_mostly kvm_max_guest_tsc_khz; 157 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 158 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 159 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 160 u64 __read_mostly kvm_max_tsc_scaling_ratio; 161 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 162 u64 __read_mostly kvm_default_tsc_scaling_ratio; 163 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 164 bool __read_mostly kvm_has_bus_lock_exit; 165 EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit); 166 167 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 168 static u32 __read_mostly tsc_tolerance_ppm = 250; 169 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 170 171 /* 172 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 173 * adaptive tuning starting from default advancement of 1000ns. '0' disables 174 * advancement entirely. Any other value is used as-is and disables adaptive 175 * tuning, i.e. allows privileged userspace to set an exact advancement time. 176 */ 177 static int __read_mostly lapic_timer_advance_ns = -1; 178 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); 179 180 static bool __read_mostly vector_hashing = true; 181 module_param(vector_hashing, bool, S_IRUGO); 182 183 bool __read_mostly enable_vmware_backdoor = false; 184 module_param(enable_vmware_backdoor, bool, S_IRUGO); 185 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 186 187 static bool __read_mostly force_emulation_prefix = false; 188 module_param(force_emulation_prefix, bool, S_IRUGO); 189 190 int __read_mostly pi_inject_timer = -1; 191 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); 192 193 /* Enable/disable PMU virtualization */ 194 bool __read_mostly enable_pmu = true; 195 EXPORT_SYMBOL_GPL(enable_pmu); 196 module_param(enable_pmu, bool, 0444); 197 198 bool __read_mostly eager_page_split = true; 199 module_param(eager_page_split, bool, 0644); 200 201 /* 202 * Restoring the host value for MSRs that are only consumed when running in 203 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU 204 * returns to userspace, i.e. the kernel can run with the guest's value. 205 */ 206 #define KVM_MAX_NR_USER_RETURN_MSRS 16 207 208 struct kvm_user_return_msrs { 209 struct user_return_notifier urn; 210 bool registered; 211 struct kvm_user_return_msr_values { 212 u64 host; 213 u64 curr; 214 } values[KVM_MAX_NR_USER_RETURN_MSRS]; 215 }; 216 217 u32 __read_mostly kvm_nr_uret_msrs; 218 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); 219 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; 220 static struct kvm_user_return_msrs __percpu *user_return_msrs; 221 222 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 223 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 224 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 225 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE) 226 227 u64 __read_mostly host_efer; 228 EXPORT_SYMBOL_GPL(host_efer); 229 230 bool __read_mostly allow_smaller_maxphyaddr = 0; 231 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); 232 233 bool __read_mostly enable_apicv = true; 234 EXPORT_SYMBOL_GPL(enable_apicv); 235 236 u64 __read_mostly host_xss; 237 EXPORT_SYMBOL_GPL(host_xss); 238 u64 __read_mostly supported_xss; 239 EXPORT_SYMBOL_GPL(supported_xss); 240 241 const struct _kvm_stats_desc kvm_vm_stats_desc[] = { 242 KVM_GENERIC_VM_STATS(), 243 STATS_DESC_COUNTER(VM, mmu_shadow_zapped), 244 STATS_DESC_COUNTER(VM, mmu_pte_write), 245 STATS_DESC_COUNTER(VM, mmu_pde_zapped), 246 STATS_DESC_COUNTER(VM, mmu_flooded), 247 STATS_DESC_COUNTER(VM, mmu_recycled), 248 STATS_DESC_COUNTER(VM, mmu_cache_miss), 249 STATS_DESC_ICOUNTER(VM, mmu_unsync), 250 STATS_DESC_ICOUNTER(VM, pages_4k), 251 STATS_DESC_ICOUNTER(VM, pages_2m), 252 STATS_DESC_ICOUNTER(VM, pages_1g), 253 STATS_DESC_ICOUNTER(VM, nx_lpage_splits), 254 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size), 255 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions) 256 }; 257 258 const struct kvm_stats_header kvm_vm_stats_header = { 259 .name_size = KVM_STATS_NAME_SIZE, 260 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), 261 .id_offset = sizeof(struct kvm_stats_header), 262 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 263 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 264 sizeof(kvm_vm_stats_desc), 265 }; 266 267 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { 268 KVM_GENERIC_VCPU_STATS(), 269 STATS_DESC_COUNTER(VCPU, pf_taken), 270 STATS_DESC_COUNTER(VCPU, pf_fixed), 271 STATS_DESC_COUNTER(VCPU, pf_emulate), 272 STATS_DESC_COUNTER(VCPU, pf_spurious), 273 STATS_DESC_COUNTER(VCPU, pf_fast), 274 STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created), 275 STATS_DESC_COUNTER(VCPU, pf_guest), 276 STATS_DESC_COUNTER(VCPU, tlb_flush), 277 STATS_DESC_COUNTER(VCPU, invlpg), 278 STATS_DESC_COUNTER(VCPU, exits), 279 STATS_DESC_COUNTER(VCPU, io_exits), 280 STATS_DESC_COUNTER(VCPU, mmio_exits), 281 STATS_DESC_COUNTER(VCPU, signal_exits), 282 STATS_DESC_COUNTER(VCPU, irq_window_exits), 283 STATS_DESC_COUNTER(VCPU, nmi_window_exits), 284 STATS_DESC_COUNTER(VCPU, l1d_flush), 285 STATS_DESC_COUNTER(VCPU, halt_exits), 286 STATS_DESC_COUNTER(VCPU, request_irq_exits), 287 STATS_DESC_COUNTER(VCPU, irq_exits), 288 STATS_DESC_COUNTER(VCPU, host_state_reload), 289 STATS_DESC_COUNTER(VCPU, fpu_reload), 290 STATS_DESC_COUNTER(VCPU, insn_emulation), 291 STATS_DESC_COUNTER(VCPU, insn_emulation_fail), 292 STATS_DESC_COUNTER(VCPU, hypercalls), 293 STATS_DESC_COUNTER(VCPU, irq_injections), 294 STATS_DESC_COUNTER(VCPU, nmi_injections), 295 STATS_DESC_COUNTER(VCPU, req_event), 296 STATS_DESC_COUNTER(VCPU, nested_run), 297 STATS_DESC_COUNTER(VCPU, directed_yield_attempted), 298 STATS_DESC_COUNTER(VCPU, directed_yield_successful), 299 STATS_DESC_COUNTER(VCPU, preemption_reported), 300 STATS_DESC_COUNTER(VCPU, preemption_other), 301 STATS_DESC_IBOOLEAN(VCPU, guest_mode) 302 }; 303 304 const struct kvm_stats_header kvm_vcpu_stats_header = { 305 .name_size = KVM_STATS_NAME_SIZE, 306 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), 307 .id_offset = sizeof(struct kvm_stats_header), 308 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 309 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 310 sizeof(kvm_vcpu_stats_desc), 311 }; 312 313 u64 __read_mostly host_xcr0; 314 u64 __read_mostly supported_xcr0; 315 EXPORT_SYMBOL_GPL(supported_xcr0); 316 317 static struct kmem_cache *x86_emulator_cache; 318 319 /* 320 * When called, it means the previous get/set msr reached an invalid msr. 321 * Return true if we want to ignore/silent this failed msr access. 322 */ 323 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) 324 { 325 const char *op = write ? "wrmsr" : "rdmsr"; 326 327 if (ignore_msrs) { 328 if (report_ignored_msrs) 329 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", 330 op, msr, data); 331 /* Mask the error */ 332 return true; 333 } else { 334 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", 335 op, msr, data); 336 return false; 337 } 338 } 339 340 static struct kmem_cache *kvm_alloc_emulator_cache(void) 341 { 342 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); 343 unsigned int size = sizeof(struct x86_emulate_ctxt); 344 345 return kmem_cache_create_usercopy("x86_emulator", size, 346 __alignof__(struct x86_emulate_ctxt), 347 SLAB_ACCOUNT, useroffset, 348 size - useroffset, NULL); 349 } 350 351 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 352 353 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 354 { 355 int i; 356 for (i = 0; i < ASYNC_PF_PER_VCPU; i++) 357 vcpu->arch.apf.gfns[i] = ~0; 358 } 359 360 static void kvm_on_user_return(struct user_return_notifier *urn) 361 { 362 unsigned slot; 363 struct kvm_user_return_msrs *msrs 364 = container_of(urn, struct kvm_user_return_msrs, urn); 365 struct kvm_user_return_msr_values *values; 366 unsigned long flags; 367 368 /* 369 * Disabling irqs at this point since the following code could be 370 * interrupted and executed through kvm_arch_hardware_disable() 371 */ 372 local_irq_save(flags); 373 if (msrs->registered) { 374 msrs->registered = false; 375 user_return_notifier_unregister(urn); 376 } 377 local_irq_restore(flags); 378 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { 379 values = &msrs->values[slot]; 380 if (values->host != values->curr) { 381 wrmsrl(kvm_uret_msrs_list[slot], values->host); 382 values->curr = values->host; 383 } 384 } 385 } 386 387 static int kvm_probe_user_return_msr(u32 msr) 388 { 389 u64 val; 390 int ret; 391 392 preempt_disable(); 393 ret = rdmsrl_safe(msr, &val); 394 if (ret) 395 goto out; 396 ret = wrmsrl_safe(msr, val); 397 out: 398 preempt_enable(); 399 return ret; 400 } 401 402 int kvm_add_user_return_msr(u32 msr) 403 { 404 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); 405 406 if (kvm_probe_user_return_msr(msr)) 407 return -1; 408 409 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; 410 return kvm_nr_uret_msrs++; 411 } 412 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); 413 414 int kvm_find_user_return_msr(u32 msr) 415 { 416 int i; 417 418 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 419 if (kvm_uret_msrs_list[i] == msr) 420 return i; 421 } 422 return -1; 423 } 424 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); 425 426 static void kvm_user_return_msr_cpu_online(void) 427 { 428 unsigned int cpu = smp_processor_id(); 429 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 430 u64 value; 431 int i; 432 433 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 434 rdmsrl_safe(kvm_uret_msrs_list[i], &value); 435 msrs->values[i].host = value; 436 msrs->values[i].curr = value; 437 } 438 } 439 440 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) 441 { 442 unsigned int cpu = smp_processor_id(); 443 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 444 int err; 445 446 value = (value & mask) | (msrs->values[slot].host & ~mask); 447 if (value == msrs->values[slot].curr) 448 return 0; 449 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); 450 if (err) 451 return 1; 452 453 msrs->values[slot].curr = value; 454 if (!msrs->registered) { 455 msrs->urn.on_user_return = kvm_on_user_return; 456 user_return_notifier_register(&msrs->urn); 457 msrs->registered = true; 458 } 459 return 0; 460 } 461 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); 462 463 static void drop_user_return_notifiers(void) 464 { 465 unsigned int cpu = smp_processor_id(); 466 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 467 468 if (msrs->registered) 469 kvm_on_user_return(&msrs->urn); 470 } 471 472 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 473 { 474 return vcpu->arch.apic_base; 475 } 476 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 477 478 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 479 { 480 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 481 } 482 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 483 484 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 485 { 486 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 487 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 488 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | 489 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 490 491 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 492 return 1; 493 if (!msr_info->host_initiated) { 494 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 495 return 1; 496 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 497 return 1; 498 } 499 500 kvm_lapic_set_base(vcpu, msr_info->data); 501 kvm_recalculate_apic_map(vcpu->kvm); 502 return 0; 503 } 504 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 505 506 /* 507 * Handle a fault on a hardware virtualization (VMX or SVM) instruction. 508 * 509 * Hardware virtualization extension instructions may fault if a reboot turns 510 * off virtualization while processes are running. Usually after catching the 511 * fault we just panic; during reboot instead the instruction is ignored. 512 */ 513 noinstr void kvm_spurious_fault(void) 514 { 515 /* Fault while not rebooting. We want the trace. */ 516 BUG_ON(!kvm_rebooting); 517 } 518 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 519 520 #define EXCPT_BENIGN 0 521 #define EXCPT_CONTRIBUTORY 1 522 #define EXCPT_PF 2 523 524 static int exception_class(int vector) 525 { 526 switch (vector) { 527 case PF_VECTOR: 528 return EXCPT_PF; 529 case DE_VECTOR: 530 case TS_VECTOR: 531 case NP_VECTOR: 532 case SS_VECTOR: 533 case GP_VECTOR: 534 return EXCPT_CONTRIBUTORY; 535 default: 536 break; 537 } 538 return EXCPT_BENIGN; 539 } 540 541 #define EXCPT_FAULT 0 542 #define EXCPT_TRAP 1 543 #define EXCPT_ABORT 2 544 #define EXCPT_INTERRUPT 3 545 546 static int exception_type(int vector) 547 { 548 unsigned int mask; 549 550 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 551 return EXCPT_INTERRUPT; 552 553 mask = 1 << vector; 554 555 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 556 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 557 return EXCPT_TRAP; 558 559 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 560 return EXCPT_ABORT; 561 562 /* Reserved exceptions will result in fault */ 563 return EXCPT_FAULT; 564 } 565 566 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 567 { 568 unsigned nr = vcpu->arch.exception.nr; 569 bool has_payload = vcpu->arch.exception.has_payload; 570 unsigned long payload = vcpu->arch.exception.payload; 571 572 if (!has_payload) 573 return; 574 575 switch (nr) { 576 case DB_VECTOR: 577 /* 578 * "Certain debug exceptions may clear bit 0-3. The 579 * remaining contents of the DR6 register are never 580 * cleared by the processor". 581 */ 582 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 583 /* 584 * In order to reflect the #DB exception payload in guest 585 * dr6, three components need to be considered: active low 586 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, 587 * DR6_BS and DR6_BT) 588 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. 589 * In the target guest dr6: 590 * FIXED_1 bits should always be set. 591 * Active low bits should be cleared if 1-setting in payload. 592 * Active high bits should be set if 1-setting in payload. 593 * 594 * Note, the payload is compatible with the pending debug 595 * exceptions/exit qualification under VMX, that active_low bits 596 * are active high in payload. 597 * So they need to be flipped for DR6. 598 */ 599 vcpu->arch.dr6 |= DR6_ACTIVE_LOW; 600 vcpu->arch.dr6 |= payload; 601 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; 602 603 /* 604 * The #DB payload is defined as compatible with the 'pending 605 * debug exceptions' field under VMX, not DR6. While bit 12 is 606 * defined in the 'pending debug exceptions' field (enabled 607 * breakpoint), it is reserved and must be zero in DR6. 608 */ 609 vcpu->arch.dr6 &= ~BIT(12); 610 break; 611 case PF_VECTOR: 612 vcpu->arch.cr2 = payload; 613 break; 614 } 615 616 vcpu->arch.exception.has_payload = false; 617 vcpu->arch.exception.payload = 0; 618 } 619 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 620 621 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 622 unsigned nr, bool has_error, u32 error_code, 623 bool has_payload, unsigned long payload, bool reinject) 624 { 625 u32 prev_nr; 626 int class1, class2; 627 628 kvm_make_request(KVM_REQ_EVENT, vcpu); 629 630 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 631 queue: 632 if (reinject) { 633 /* 634 * On vmentry, vcpu->arch.exception.pending is only 635 * true if an event injection was blocked by 636 * nested_run_pending. In that case, however, 637 * vcpu_enter_guest requests an immediate exit, 638 * and the guest shouldn't proceed far enough to 639 * need reinjection. 640 */ 641 WARN_ON_ONCE(vcpu->arch.exception.pending); 642 vcpu->arch.exception.injected = true; 643 if (WARN_ON_ONCE(has_payload)) { 644 /* 645 * A reinjected event has already 646 * delivered its payload. 647 */ 648 has_payload = false; 649 payload = 0; 650 } 651 } else { 652 vcpu->arch.exception.pending = true; 653 vcpu->arch.exception.injected = false; 654 } 655 vcpu->arch.exception.has_error_code = has_error; 656 vcpu->arch.exception.nr = nr; 657 vcpu->arch.exception.error_code = error_code; 658 vcpu->arch.exception.has_payload = has_payload; 659 vcpu->arch.exception.payload = payload; 660 if (!is_guest_mode(vcpu)) 661 kvm_deliver_exception_payload(vcpu); 662 return; 663 } 664 665 /* to check exception */ 666 prev_nr = vcpu->arch.exception.nr; 667 if (prev_nr == DF_VECTOR) { 668 /* triple fault -> shutdown */ 669 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 670 return; 671 } 672 class1 = exception_class(prev_nr); 673 class2 = exception_class(nr); 674 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 675 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 676 /* 677 * Generate double fault per SDM Table 5-5. Set 678 * exception.pending = true so that the double fault 679 * can trigger a nested vmexit. 680 */ 681 vcpu->arch.exception.pending = true; 682 vcpu->arch.exception.injected = false; 683 vcpu->arch.exception.has_error_code = true; 684 vcpu->arch.exception.nr = DF_VECTOR; 685 vcpu->arch.exception.error_code = 0; 686 vcpu->arch.exception.has_payload = false; 687 vcpu->arch.exception.payload = 0; 688 } else 689 /* replace previous exception with a new one in a hope 690 that instruction re-execution will regenerate lost 691 exception */ 692 goto queue; 693 } 694 695 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 696 { 697 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 698 } 699 EXPORT_SYMBOL_GPL(kvm_queue_exception); 700 701 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 702 { 703 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 704 } 705 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 706 707 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 708 unsigned long payload) 709 { 710 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 711 } 712 EXPORT_SYMBOL_GPL(kvm_queue_exception_p); 713 714 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 715 u32 error_code, unsigned long payload) 716 { 717 kvm_multiple_exception(vcpu, nr, true, error_code, 718 true, payload, false); 719 } 720 721 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 722 { 723 if (err) 724 kvm_inject_gp(vcpu, 0); 725 else 726 return kvm_skip_emulated_instruction(vcpu); 727 728 return 1; 729 } 730 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 731 732 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err) 733 { 734 if (err) { 735 kvm_inject_gp(vcpu, 0); 736 return 1; 737 } 738 739 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP | 740 EMULTYPE_COMPLETE_USER_EXIT); 741 } 742 743 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 744 { 745 ++vcpu->stat.pf_guest; 746 vcpu->arch.exception.nested_apf = 747 is_guest_mode(vcpu) && fault->async_page_fault; 748 if (vcpu->arch.exception.nested_apf) { 749 vcpu->arch.apf.nested_apf_token = fault->address; 750 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 751 } else { 752 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 753 fault->address); 754 } 755 } 756 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 757 758 /* Returns true if the page fault was immediately morphed into a VM-Exit. */ 759 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 760 struct x86_exception *fault) 761 { 762 struct kvm_mmu *fault_mmu; 763 WARN_ON_ONCE(fault->vector != PF_VECTOR); 764 765 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : 766 vcpu->arch.walk_mmu; 767 768 /* 769 * Invalidate the TLB entry for the faulting address, if it exists, 770 * else the access will fault indefinitely (and to emulate hardware). 771 */ 772 if ((fault->error_code & PFERR_PRESENT_MASK) && 773 !(fault->error_code & PFERR_RSVD_MASK)) 774 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, 775 fault_mmu->root.hpa); 776 777 /* 778 * A workaround for KVM's bad exception handling. If KVM injected an 779 * exception into L2, and L2 encountered a #PF while vectoring the 780 * injected exception, manually check to see if L1 wants to intercept 781 * #PF, otherwise queuing the #PF will lead to #DF or a lost exception. 782 * In all other cases, defer the check to nested_ops->check_events(), 783 * which will correctly handle priority (this does not). Note, other 784 * exceptions, e.g. #GP, are theoretically affected, #PF is simply the 785 * most problematic, e.g. when L0 and L1 are both intercepting #PF for 786 * shadow paging. 787 * 788 * TODO: Rewrite exception handling to track injected and pending 789 * (VM-Exit) exceptions separately. 790 */ 791 if (unlikely(vcpu->arch.exception.injected && is_guest_mode(vcpu)) && 792 kvm_x86_ops.nested_ops->handle_page_fault_workaround(vcpu, fault)) 793 return true; 794 795 fault_mmu->inject_page_fault(vcpu, fault); 796 return false; 797 } 798 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); 799 800 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 801 { 802 atomic_inc(&vcpu->arch.nmi_queued); 803 kvm_make_request(KVM_REQ_NMI, vcpu); 804 } 805 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 806 807 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 808 { 809 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 810 } 811 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 812 813 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 814 { 815 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 816 } 817 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 818 819 /* 820 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 821 * a #GP and return false. 822 */ 823 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 824 { 825 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) 826 return true; 827 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 828 return false; 829 } 830 EXPORT_SYMBOL_GPL(kvm_require_cpl); 831 832 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 833 { 834 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 835 return true; 836 837 kvm_queue_exception(vcpu, UD_VECTOR); 838 return false; 839 } 840 EXPORT_SYMBOL_GPL(kvm_require_dr); 841 842 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) 843 { 844 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); 845 } 846 847 /* 848 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. 849 */ 850 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3) 851 { 852 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 853 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 854 gpa_t real_gpa; 855 int i; 856 int ret; 857 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 858 859 /* 860 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated 861 * to an L1 GPA. 862 */ 863 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn), 864 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL); 865 if (real_gpa == UNMAPPED_GVA) 866 return 0; 867 868 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */ 869 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte, 870 cr3 & GENMASK(11, 5), sizeof(pdpte)); 871 if (ret < 0) 872 return 0; 873 874 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 875 if ((pdpte[i] & PT_PRESENT_MASK) && 876 (pdpte[i] & pdptr_rsvd_bits(vcpu))) { 877 return 0; 878 } 879 } 880 881 /* 882 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled. 883 * Shadow page roots need to be reconstructed instead. 884 */ 885 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs))) 886 kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT); 887 888 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 889 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 890 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); 891 vcpu->arch.pdptrs_from_userspace = false; 892 893 return 1; 894 } 895 EXPORT_SYMBOL_GPL(load_pdptrs); 896 897 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) 898 { 899 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 900 kvm_clear_async_pf_completion_queue(vcpu); 901 kvm_async_pf_hash_reset(vcpu); 902 903 /* 904 * Clearing CR0.PG is defined to flush the TLB from the guest's 905 * perspective. 906 */ 907 if (!(cr0 & X86_CR0_PG)) 908 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 909 } 910 911 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS) 912 kvm_mmu_reset_context(vcpu); 913 914 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 915 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 916 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 917 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 918 } 919 EXPORT_SYMBOL_GPL(kvm_post_set_cr0); 920 921 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 922 { 923 unsigned long old_cr0 = kvm_read_cr0(vcpu); 924 925 cr0 |= X86_CR0_ET; 926 927 #ifdef CONFIG_X86_64 928 if (cr0 & 0xffffffff00000000UL) 929 return 1; 930 #endif 931 932 cr0 &= ~CR0_RESERVED_BITS; 933 934 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 935 return 1; 936 937 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 938 return 1; 939 940 #ifdef CONFIG_X86_64 941 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && 942 (cr0 & X86_CR0_PG)) { 943 int cs_db, cs_l; 944 945 if (!is_pae(vcpu)) 946 return 1; 947 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 948 if (cs_l) 949 return 1; 950 } 951 #endif 952 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && 953 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) && 954 !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) 955 return 1; 956 957 if (!(cr0 & X86_CR0_PG) && 958 (is_64_bit_mode(vcpu) || kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))) 959 return 1; 960 961 static_call(kvm_x86_set_cr0)(vcpu, cr0); 962 963 kvm_post_set_cr0(vcpu, old_cr0, cr0); 964 965 return 0; 966 } 967 EXPORT_SYMBOL_GPL(kvm_set_cr0); 968 969 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 970 { 971 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 972 } 973 EXPORT_SYMBOL_GPL(kvm_lmsw); 974 975 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) 976 { 977 if (vcpu->arch.guest_state_protected) 978 return; 979 980 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 981 982 if (vcpu->arch.xcr0 != host_xcr0) 983 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 984 985 if (vcpu->arch.xsaves_enabled && 986 vcpu->arch.ia32_xss != host_xss) 987 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 988 } 989 990 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 991 if (static_cpu_has(X86_FEATURE_PKU) && 992 vcpu->arch.pkru != vcpu->arch.host_pkru && 993 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) || 994 kvm_read_cr4_bits(vcpu, X86_CR4_PKE))) 995 write_pkru(vcpu->arch.pkru); 996 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */ 997 } 998 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); 999 1000 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) 1001 { 1002 if (vcpu->arch.guest_state_protected) 1003 return; 1004 1005 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 1006 if (static_cpu_has(X86_FEATURE_PKU) && 1007 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) || 1008 kvm_read_cr4_bits(vcpu, X86_CR4_PKE))) { 1009 vcpu->arch.pkru = rdpkru(); 1010 if (vcpu->arch.pkru != vcpu->arch.host_pkru) 1011 write_pkru(vcpu->arch.host_pkru); 1012 } 1013 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */ 1014 1015 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 1016 1017 if (vcpu->arch.xcr0 != host_xcr0) 1018 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 1019 1020 if (vcpu->arch.xsaves_enabled && 1021 vcpu->arch.ia32_xss != host_xss) 1022 wrmsrl(MSR_IA32_XSS, host_xss); 1023 } 1024 1025 } 1026 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); 1027 1028 static inline u64 kvm_guest_supported_xcr0(struct kvm_vcpu *vcpu) 1029 { 1030 return vcpu->arch.guest_fpu.fpstate->user_xfeatures; 1031 } 1032 1033 #ifdef CONFIG_X86_64 1034 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu) 1035 { 1036 return kvm_guest_supported_xcr0(vcpu) & XFEATURE_MASK_USER_DYNAMIC; 1037 } 1038 #endif 1039 1040 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 1041 { 1042 u64 xcr0 = xcr; 1043 u64 old_xcr0 = vcpu->arch.xcr0; 1044 u64 valid_bits; 1045 1046 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 1047 if (index != XCR_XFEATURE_ENABLED_MASK) 1048 return 1; 1049 if (!(xcr0 & XFEATURE_MASK_FP)) 1050 return 1; 1051 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 1052 return 1; 1053 1054 /* 1055 * Do not allow the guest to set bits that we do not support 1056 * saving. However, xcr0 bit 0 is always set, even if the 1057 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()). 1058 */ 1059 valid_bits = kvm_guest_supported_xcr0(vcpu) | XFEATURE_MASK_FP; 1060 if (xcr0 & ~valid_bits) 1061 return 1; 1062 1063 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 1064 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 1065 return 1; 1066 1067 if (xcr0 & XFEATURE_MASK_AVX512) { 1068 if (!(xcr0 & XFEATURE_MASK_YMM)) 1069 return 1; 1070 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 1071 return 1; 1072 } 1073 1074 if ((xcr0 & XFEATURE_MASK_XTILE) && 1075 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE)) 1076 return 1; 1077 1078 vcpu->arch.xcr0 = xcr0; 1079 1080 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 1081 kvm_update_cpuid_runtime(vcpu); 1082 return 0; 1083 } 1084 1085 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) 1086 { 1087 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || 1088 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { 1089 kvm_inject_gp(vcpu, 0); 1090 return 1; 1091 } 1092 1093 return kvm_skip_emulated_instruction(vcpu); 1094 } 1095 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); 1096 1097 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1098 { 1099 if (cr4 & cr4_reserved_bits) 1100 return false; 1101 1102 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) 1103 return false; 1104 1105 return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); 1106 } 1107 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); 1108 1109 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) 1110 { 1111 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) 1112 kvm_mmu_reset_context(vcpu); 1113 1114 /* 1115 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB 1116 * according to the SDM; however, stale prev_roots could be reused 1117 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we 1118 * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST 1119 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed, 1120 * so fall through. 1121 */ 1122 if (!tdp_enabled && 1123 (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) 1124 kvm_mmu_unload(vcpu); 1125 1126 /* 1127 * The TLB has to be flushed for all PCIDs if any of the following 1128 * (architecturally required) changes happen: 1129 * - CR4.PCIDE is changed from 1 to 0 1130 * - CR4.PGE is toggled 1131 * 1132 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT. 1133 */ 1134 if (((cr4 ^ old_cr4) & X86_CR4_PGE) || 1135 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 1136 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1137 1138 /* 1139 * The TLB has to be flushed for the current PCID if any of the 1140 * following (architecturally required) changes happen: 1141 * - CR4.SMEP is changed from 0 to 1 1142 * - CR4.PAE is toggled 1143 */ 1144 else if (((cr4 ^ old_cr4) & X86_CR4_PAE) || 1145 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP))) 1146 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1147 1148 } 1149 EXPORT_SYMBOL_GPL(kvm_post_set_cr4); 1150 1151 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1152 { 1153 unsigned long old_cr4 = kvm_read_cr4(vcpu); 1154 1155 if (!kvm_is_valid_cr4(vcpu, cr4)) 1156 return 1; 1157 1158 if (is_long_mode(vcpu)) { 1159 if (!(cr4 & X86_CR4_PAE)) 1160 return 1; 1161 if ((cr4 ^ old_cr4) & X86_CR4_LA57) 1162 return 1; 1163 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 1164 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS) 1165 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) 1166 return 1; 1167 1168 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 1169 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 1170 return 1; 1171 1172 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 1173 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 1174 return 1; 1175 } 1176 1177 static_call(kvm_x86_set_cr4)(vcpu, cr4); 1178 1179 kvm_post_set_cr4(vcpu, old_cr4, cr4); 1180 1181 return 0; 1182 } 1183 EXPORT_SYMBOL_GPL(kvm_set_cr4); 1184 1185 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) 1186 { 1187 struct kvm_mmu *mmu = vcpu->arch.mmu; 1188 unsigned long roots_to_free = 0; 1189 int i; 1190 1191 /* 1192 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but 1193 * this is reachable when running EPT=1 and unrestricted_guest=0, and 1194 * also via the emulator. KVM's TDP page tables are not in the scope of 1195 * the invalidation, but the guest's TLB entries need to be flushed as 1196 * the CPU may have cached entries in its TLB for the target PCID. 1197 */ 1198 if (unlikely(tdp_enabled)) { 1199 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1200 return; 1201 } 1202 1203 /* 1204 * If neither the current CR3 nor any of the prev_roots use the given 1205 * PCID, then nothing needs to be done here because a resync will 1206 * happen anyway before switching to any other CR3. 1207 */ 1208 if (kvm_get_active_pcid(vcpu) == pcid) { 1209 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); 1210 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1211 } 1212 1213 /* 1214 * If PCID is disabled, there is no need to free prev_roots even if the 1215 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB 1216 * with PCIDE=0. 1217 */ 1218 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 1219 return; 1220 1221 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 1222 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid) 1223 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 1224 1225 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free); 1226 } 1227 1228 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 1229 { 1230 bool skip_tlb_flush = false; 1231 unsigned long pcid = 0; 1232 #ifdef CONFIG_X86_64 1233 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 1234 1235 if (pcid_enabled) { 1236 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 1237 cr3 &= ~X86_CR3_PCID_NOFLUSH; 1238 pcid = cr3 & X86_CR3_PCID_MASK; 1239 } 1240 #endif 1241 1242 /* PDPTRs are always reloaded for PAE paging. */ 1243 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) 1244 goto handle_tlb_flush; 1245 1246 /* 1247 * Do not condition the GPA check on long mode, this helper is used to 1248 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that 1249 * the current vCPU mode is accurate. 1250 */ 1251 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) 1252 return 1; 1253 1254 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3)) 1255 return 1; 1256 1257 if (cr3 != kvm_read_cr3(vcpu)) 1258 kvm_mmu_new_pgd(vcpu, cr3); 1259 1260 vcpu->arch.cr3 = cr3; 1261 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 1262 /* Do not call post_set_cr3, we do not get here for confidential guests. */ 1263 1264 handle_tlb_flush: 1265 /* 1266 * A load of CR3 that flushes the TLB flushes only the current PCID, 1267 * even if PCID is disabled, in which case PCID=0 is flushed. It's a 1268 * moot point in the end because _disabling_ PCID will flush all PCIDs, 1269 * and it's impossible to use a non-zero PCID when PCID is disabled, 1270 * i.e. only PCID=0 can be relevant. 1271 */ 1272 if (!skip_tlb_flush) 1273 kvm_invalidate_pcid(vcpu, pcid); 1274 1275 return 0; 1276 } 1277 EXPORT_SYMBOL_GPL(kvm_set_cr3); 1278 1279 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 1280 { 1281 if (cr8 & CR8_RESERVED_BITS) 1282 return 1; 1283 if (lapic_in_kernel(vcpu)) 1284 kvm_lapic_set_tpr(vcpu, cr8); 1285 else 1286 vcpu->arch.cr8 = cr8; 1287 return 0; 1288 } 1289 EXPORT_SYMBOL_GPL(kvm_set_cr8); 1290 1291 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 1292 { 1293 if (lapic_in_kernel(vcpu)) 1294 return kvm_lapic_get_cr8(vcpu); 1295 else 1296 return vcpu->arch.cr8; 1297 } 1298 EXPORT_SYMBOL_GPL(kvm_get_cr8); 1299 1300 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 1301 { 1302 int i; 1303 1304 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1305 for (i = 0; i < KVM_NR_DB_REGS; i++) 1306 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1307 } 1308 } 1309 1310 void kvm_update_dr7(struct kvm_vcpu *vcpu) 1311 { 1312 unsigned long dr7; 1313 1314 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1315 dr7 = vcpu->arch.guest_debug_dr7; 1316 else 1317 dr7 = vcpu->arch.dr7; 1318 static_call(kvm_x86_set_dr7)(vcpu, dr7); 1319 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1320 if (dr7 & DR7_BP_EN_MASK) 1321 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1322 } 1323 EXPORT_SYMBOL_GPL(kvm_update_dr7); 1324 1325 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1326 { 1327 u64 fixed = DR6_FIXED_1; 1328 1329 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1330 fixed |= DR6_RTM; 1331 1332 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) 1333 fixed |= DR6_BUS_LOCK; 1334 return fixed; 1335 } 1336 1337 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1338 { 1339 size_t size = ARRAY_SIZE(vcpu->arch.db); 1340 1341 switch (dr) { 1342 case 0 ... 3: 1343 vcpu->arch.db[array_index_nospec(dr, size)] = val; 1344 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1345 vcpu->arch.eff_db[dr] = val; 1346 break; 1347 case 4: 1348 case 6: 1349 if (!kvm_dr6_valid(val)) 1350 return 1; /* #GP */ 1351 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1352 break; 1353 case 5: 1354 default: /* 7 */ 1355 if (!kvm_dr7_valid(val)) 1356 return 1; /* #GP */ 1357 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1358 kvm_update_dr7(vcpu); 1359 break; 1360 } 1361 1362 return 0; 1363 } 1364 EXPORT_SYMBOL_GPL(kvm_set_dr); 1365 1366 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1367 { 1368 size_t size = ARRAY_SIZE(vcpu->arch.db); 1369 1370 switch (dr) { 1371 case 0 ... 3: 1372 *val = vcpu->arch.db[array_index_nospec(dr, size)]; 1373 break; 1374 case 4: 1375 case 6: 1376 *val = vcpu->arch.dr6; 1377 break; 1378 case 5: 1379 default: /* 7 */ 1380 *val = vcpu->arch.dr7; 1381 break; 1382 } 1383 } 1384 EXPORT_SYMBOL_GPL(kvm_get_dr); 1385 1386 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) 1387 { 1388 u32 ecx = kvm_rcx_read(vcpu); 1389 u64 data; 1390 1391 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { 1392 kvm_inject_gp(vcpu, 0); 1393 return 1; 1394 } 1395 1396 kvm_rax_write(vcpu, (u32)data); 1397 kvm_rdx_write(vcpu, data >> 32); 1398 return kvm_skip_emulated_instruction(vcpu); 1399 } 1400 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); 1401 1402 /* 1403 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1404 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1405 * 1406 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) 1407 * extract the supported MSRs from the related const lists. 1408 * msrs_to_save is selected from the msrs_to_save_all to reflect the 1409 * capabilities of the host cpu. This capabilities test skips MSRs that are 1410 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs 1411 * may depend on host virtualization features rather than host cpu features. 1412 */ 1413 1414 static const u32 msrs_to_save_all[] = { 1415 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1416 MSR_STAR, 1417 #ifdef CONFIG_X86_64 1418 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1419 #endif 1420 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1421 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1422 MSR_IA32_SPEC_CTRL, 1423 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1424 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1425 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1426 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1427 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1428 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1429 MSR_IA32_UMWAIT_CONTROL, 1430 1431 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, 1432 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, 1433 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, 1434 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 1435 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, 1436 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, 1437 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, 1438 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, 1439 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, 1440 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, 1441 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, 1442 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, 1443 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, 1444 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, 1445 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, 1446 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, 1447 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, 1448 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, 1449 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, 1450 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, 1451 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, 1452 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, 1453 1454 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3, 1455 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3, 1456 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2, 1457 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, 1458 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, 1459 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, 1460 MSR_IA32_XFD, MSR_IA32_XFD_ERR, 1461 }; 1462 1463 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; 1464 static unsigned num_msrs_to_save; 1465 1466 static const u32 emulated_msrs_all[] = { 1467 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1468 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1469 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1470 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1471 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1472 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1473 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1474 HV_X64_MSR_RESET, 1475 HV_X64_MSR_VP_INDEX, 1476 HV_X64_MSR_VP_RUNTIME, 1477 HV_X64_MSR_SCONTROL, 1478 HV_X64_MSR_STIMER0_CONFIG, 1479 HV_X64_MSR_VP_ASSIST_PAGE, 1480 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1481 HV_X64_MSR_TSC_EMULATION_STATUS, 1482 HV_X64_MSR_SYNDBG_OPTIONS, 1483 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, 1484 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, 1485 HV_X64_MSR_SYNDBG_PENDING_BUFFER, 1486 1487 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1488 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, 1489 1490 MSR_IA32_TSC_ADJUST, 1491 MSR_IA32_TSC_DEADLINE, 1492 MSR_IA32_ARCH_CAPABILITIES, 1493 MSR_IA32_PERF_CAPABILITIES, 1494 MSR_IA32_MISC_ENABLE, 1495 MSR_IA32_MCG_STATUS, 1496 MSR_IA32_MCG_CTL, 1497 MSR_IA32_MCG_EXT_CTL, 1498 MSR_IA32_SMBASE, 1499 MSR_SMI_COUNT, 1500 MSR_PLATFORM_INFO, 1501 MSR_MISC_FEATURES_ENABLES, 1502 MSR_AMD64_VIRT_SPEC_CTRL, 1503 MSR_AMD64_TSC_RATIO, 1504 MSR_IA32_POWER_CTL, 1505 MSR_IA32_UCODE_REV, 1506 1507 /* 1508 * The following list leaves out MSRs whose values are determined 1509 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. 1510 * We always support the "true" VMX control MSRs, even if the host 1511 * processor does not, so I am putting these registers here rather 1512 * than in msrs_to_save_all. 1513 */ 1514 MSR_IA32_VMX_BASIC, 1515 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1516 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1517 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1518 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1519 MSR_IA32_VMX_MISC, 1520 MSR_IA32_VMX_CR0_FIXED0, 1521 MSR_IA32_VMX_CR4_FIXED0, 1522 MSR_IA32_VMX_VMCS_ENUM, 1523 MSR_IA32_VMX_PROCBASED_CTLS2, 1524 MSR_IA32_VMX_EPT_VPID_CAP, 1525 MSR_IA32_VMX_VMFUNC, 1526 1527 MSR_K7_HWCR, 1528 MSR_KVM_POLL_CONTROL, 1529 }; 1530 1531 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; 1532 static unsigned num_emulated_msrs; 1533 1534 /* 1535 * List of msr numbers which are used to expose MSR-based features that 1536 * can be used by a hypervisor to validate requested CPU features. 1537 */ 1538 static const u32 msr_based_features_all[] = { 1539 MSR_IA32_VMX_BASIC, 1540 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1541 MSR_IA32_VMX_PINBASED_CTLS, 1542 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1543 MSR_IA32_VMX_PROCBASED_CTLS, 1544 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1545 MSR_IA32_VMX_EXIT_CTLS, 1546 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1547 MSR_IA32_VMX_ENTRY_CTLS, 1548 MSR_IA32_VMX_MISC, 1549 MSR_IA32_VMX_CR0_FIXED0, 1550 MSR_IA32_VMX_CR0_FIXED1, 1551 MSR_IA32_VMX_CR4_FIXED0, 1552 MSR_IA32_VMX_CR4_FIXED1, 1553 MSR_IA32_VMX_VMCS_ENUM, 1554 MSR_IA32_VMX_PROCBASED_CTLS2, 1555 MSR_IA32_VMX_EPT_VPID_CAP, 1556 MSR_IA32_VMX_VMFUNC, 1557 1558 MSR_F10H_DECFG, 1559 MSR_IA32_UCODE_REV, 1560 MSR_IA32_ARCH_CAPABILITIES, 1561 MSR_IA32_PERF_CAPABILITIES, 1562 }; 1563 1564 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; 1565 static unsigned int num_msr_based_features; 1566 1567 static u64 kvm_get_arch_capabilities(void) 1568 { 1569 u64 data = 0; 1570 1571 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1572 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); 1573 1574 /* 1575 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that 1576 * the nested hypervisor runs with NX huge pages. If it is not, 1577 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other 1578 * L1 guests, so it need not worry about its own (L2) guests. 1579 */ 1580 data |= ARCH_CAP_PSCHANGE_MC_NO; 1581 1582 /* 1583 * If we're doing cache flushes (either "always" or "cond") 1584 * we will do one whenever the guest does a vmlaunch/vmresume. 1585 * If an outer hypervisor is doing the cache flush for us 1586 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1587 * capability to the guest too, and if EPT is disabled we're not 1588 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1589 * require a nested hypervisor to do a flush of its own. 1590 */ 1591 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1592 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1593 1594 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) 1595 data |= ARCH_CAP_RDCL_NO; 1596 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1597 data |= ARCH_CAP_SSB_NO; 1598 if (!boot_cpu_has_bug(X86_BUG_MDS)) 1599 data |= ARCH_CAP_MDS_NO; 1600 1601 if (!boot_cpu_has(X86_FEATURE_RTM)) { 1602 /* 1603 * If RTM=0 because the kernel has disabled TSX, the host might 1604 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 1605 * and therefore knows that there cannot be TAA) but keep 1606 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, 1607 * and we want to allow migrating those guests to tsx=off hosts. 1608 */ 1609 data &= ~ARCH_CAP_TAA_NO; 1610 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { 1611 data |= ARCH_CAP_TAA_NO; 1612 } else { 1613 /* 1614 * Nothing to do here; we emulate TSX_CTRL if present on the 1615 * host so the guest can choose between disabling TSX or 1616 * using VERW to clear CPU buffers. 1617 */ 1618 } 1619 1620 /* Guests don't need to know "Fill buffer clear control" exists */ 1621 data &= ~ARCH_CAP_FB_CLEAR_CTRL; 1622 1623 return data; 1624 } 1625 1626 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1627 { 1628 switch (msr->index) { 1629 case MSR_IA32_ARCH_CAPABILITIES: 1630 msr->data = kvm_get_arch_capabilities(); 1631 break; 1632 case MSR_IA32_UCODE_REV: 1633 rdmsrl_safe(msr->index, &msr->data); 1634 break; 1635 default: 1636 return static_call(kvm_x86_get_msr_feature)(msr); 1637 } 1638 return 0; 1639 } 1640 1641 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1642 { 1643 struct kvm_msr_entry msr; 1644 int r; 1645 1646 msr.index = index; 1647 r = kvm_get_msr_feature(&msr); 1648 1649 if (r == KVM_MSR_RET_INVALID) { 1650 /* Unconditionally clear the output for simplicity */ 1651 *data = 0; 1652 if (kvm_msr_ignored_check(index, 0, false)) 1653 r = 0; 1654 } 1655 1656 if (r) 1657 return r; 1658 1659 *data = msr.data; 1660 1661 return 0; 1662 } 1663 1664 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1665 { 1666 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1667 return false; 1668 1669 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1670 return false; 1671 1672 if (efer & (EFER_LME | EFER_LMA) && 1673 !guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1674 return false; 1675 1676 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) 1677 return false; 1678 1679 return true; 1680 1681 } 1682 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1683 { 1684 if (efer & efer_reserved_bits) 1685 return false; 1686 1687 return __kvm_valid_efer(vcpu, efer); 1688 } 1689 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1690 1691 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1692 { 1693 u64 old_efer = vcpu->arch.efer; 1694 u64 efer = msr_info->data; 1695 int r; 1696 1697 if (efer & efer_reserved_bits) 1698 return 1; 1699 1700 if (!msr_info->host_initiated) { 1701 if (!__kvm_valid_efer(vcpu, efer)) 1702 return 1; 1703 1704 if (is_paging(vcpu) && 1705 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1706 return 1; 1707 } 1708 1709 efer &= ~EFER_LMA; 1710 efer |= vcpu->arch.efer & EFER_LMA; 1711 1712 r = static_call(kvm_x86_set_efer)(vcpu, efer); 1713 if (r) { 1714 WARN_ON(r > 0); 1715 return r; 1716 } 1717 1718 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS) 1719 kvm_mmu_reset_context(vcpu); 1720 1721 return 0; 1722 } 1723 1724 void kvm_enable_efer_bits(u64 mask) 1725 { 1726 efer_reserved_bits &= ~mask; 1727 } 1728 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1729 1730 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) 1731 { 1732 struct kvm_x86_msr_filter *msr_filter; 1733 struct msr_bitmap_range *ranges; 1734 struct kvm *kvm = vcpu->kvm; 1735 bool allowed; 1736 int idx; 1737 u32 i; 1738 1739 /* x2APIC MSRs do not support filtering. */ 1740 if (index >= 0x800 && index <= 0x8ff) 1741 return true; 1742 1743 idx = srcu_read_lock(&kvm->srcu); 1744 1745 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); 1746 if (!msr_filter) { 1747 allowed = true; 1748 goto out; 1749 } 1750 1751 allowed = msr_filter->default_allow; 1752 ranges = msr_filter->ranges; 1753 1754 for (i = 0; i < msr_filter->count; i++) { 1755 u32 start = ranges[i].base; 1756 u32 end = start + ranges[i].nmsrs; 1757 u32 flags = ranges[i].flags; 1758 unsigned long *bitmap = ranges[i].bitmap; 1759 1760 if ((index >= start) && (index < end) && (flags & type)) { 1761 allowed = !!test_bit(index - start, bitmap); 1762 break; 1763 } 1764 } 1765 1766 out: 1767 srcu_read_unlock(&kvm->srcu, idx); 1768 1769 return allowed; 1770 } 1771 EXPORT_SYMBOL_GPL(kvm_msr_allowed); 1772 1773 /* 1774 * Write @data into the MSR specified by @index. Select MSR specific fault 1775 * checks are bypassed if @host_initiated is %true. 1776 * Returns 0 on success, non-0 otherwise. 1777 * Assumes vcpu_load() was already called. 1778 */ 1779 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, 1780 bool host_initiated) 1781 { 1782 struct msr_data msr; 1783 1784 switch (index) { 1785 case MSR_FS_BASE: 1786 case MSR_GS_BASE: 1787 case MSR_KERNEL_GS_BASE: 1788 case MSR_CSTAR: 1789 case MSR_LSTAR: 1790 if (is_noncanonical_address(data, vcpu)) 1791 return 1; 1792 break; 1793 case MSR_IA32_SYSENTER_EIP: 1794 case MSR_IA32_SYSENTER_ESP: 1795 /* 1796 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1797 * non-canonical address is written on Intel but not on 1798 * AMD (which ignores the top 32-bits, because it does 1799 * not implement 64-bit SYSENTER). 1800 * 1801 * 64-bit code should hence be able to write a non-canonical 1802 * value on AMD. Making the address canonical ensures that 1803 * vmentry does not fail on Intel after writing a non-canonical 1804 * value, and that something deterministic happens if the guest 1805 * invokes 64-bit SYSENTER. 1806 */ 1807 data = __canonical_address(data, vcpu_virt_addr_bits(vcpu)); 1808 break; 1809 case MSR_TSC_AUX: 1810 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1811 return 1; 1812 1813 if (!host_initiated && 1814 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1815 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1816 return 1; 1817 1818 /* 1819 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has 1820 * incomplete and conflicting architectural behavior. Current 1821 * AMD CPUs completely ignore bits 63:32, i.e. they aren't 1822 * reserved and always read as zeros. Enforce Intel's reserved 1823 * bits check if and only if the guest CPU is Intel, and clear 1824 * the bits in all other cases. This ensures cross-vendor 1825 * migration will provide consistent behavior for the guest. 1826 */ 1827 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) 1828 return 1; 1829 1830 data = (u32)data; 1831 break; 1832 } 1833 1834 msr.data = data; 1835 msr.index = index; 1836 msr.host_initiated = host_initiated; 1837 1838 return static_call(kvm_x86_set_msr)(vcpu, &msr); 1839 } 1840 1841 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, 1842 u32 index, u64 data, bool host_initiated) 1843 { 1844 int ret = __kvm_set_msr(vcpu, index, data, host_initiated); 1845 1846 if (ret == KVM_MSR_RET_INVALID) 1847 if (kvm_msr_ignored_check(index, data, true)) 1848 ret = 0; 1849 1850 return ret; 1851 } 1852 1853 /* 1854 * Read the MSR specified by @index into @data. Select MSR specific fault 1855 * checks are bypassed if @host_initiated is %true. 1856 * Returns 0 on success, non-0 otherwise. 1857 * Assumes vcpu_load() was already called. 1858 */ 1859 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1860 bool host_initiated) 1861 { 1862 struct msr_data msr; 1863 int ret; 1864 1865 switch (index) { 1866 case MSR_TSC_AUX: 1867 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1868 return 1; 1869 1870 if (!host_initiated && 1871 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1872 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1873 return 1; 1874 break; 1875 } 1876 1877 msr.index = index; 1878 msr.host_initiated = host_initiated; 1879 1880 ret = static_call(kvm_x86_get_msr)(vcpu, &msr); 1881 if (!ret) 1882 *data = msr.data; 1883 return ret; 1884 } 1885 1886 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, 1887 u32 index, u64 *data, bool host_initiated) 1888 { 1889 int ret = __kvm_get_msr(vcpu, index, data, host_initiated); 1890 1891 if (ret == KVM_MSR_RET_INVALID) { 1892 /* Unconditionally clear *data for simplicity */ 1893 *data = 0; 1894 if (kvm_msr_ignored_check(index, 0, false)) 1895 ret = 0; 1896 } 1897 1898 return ret; 1899 } 1900 1901 static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1902 { 1903 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) 1904 return KVM_MSR_RET_FILTERED; 1905 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1906 } 1907 1908 static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data) 1909 { 1910 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) 1911 return KVM_MSR_RET_FILTERED; 1912 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1913 } 1914 1915 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1916 { 1917 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1918 } 1919 EXPORT_SYMBOL_GPL(kvm_get_msr); 1920 1921 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) 1922 { 1923 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1924 } 1925 EXPORT_SYMBOL_GPL(kvm_set_msr); 1926 1927 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu) 1928 { 1929 if (!vcpu->run->msr.error) { 1930 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); 1931 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); 1932 } 1933 } 1934 1935 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu) 1936 { 1937 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error); 1938 } 1939 1940 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) 1941 { 1942 complete_userspace_rdmsr(vcpu); 1943 return complete_emulated_msr_access(vcpu); 1944 } 1945 1946 static int complete_fast_msr_access(struct kvm_vcpu *vcpu) 1947 { 1948 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); 1949 } 1950 1951 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu) 1952 { 1953 complete_userspace_rdmsr(vcpu); 1954 return complete_fast_msr_access(vcpu); 1955 } 1956 1957 static u64 kvm_msr_reason(int r) 1958 { 1959 switch (r) { 1960 case KVM_MSR_RET_INVALID: 1961 return KVM_MSR_EXIT_REASON_UNKNOWN; 1962 case KVM_MSR_RET_FILTERED: 1963 return KVM_MSR_EXIT_REASON_FILTER; 1964 default: 1965 return KVM_MSR_EXIT_REASON_INVAL; 1966 } 1967 } 1968 1969 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, 1970 u32 exit_reason, u64 data, 1971 int (*completion)(struct kvm_vcpu *vcpu), 1972 int r) 1973 { 1974 u64 msr_reason = kvm_msr_reason(r); 1975 1976 /* Check if the user wanted to know about this MSR fault */ 1977 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) 1978 return 0; 1979 1980 vcpu->run->exit_reason = exit_reason; 1981 vcpu->run->msr.error = 0; 1982 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); 1983 vcpu->run->msr.reason = msr_reason; 1984 vcpu->run->msr.index = index; 1985 vcpu->run->msr.data = data; 1986 vcpu->arch.complete_userspace_io = completion; 1987 1988 return 1; 1989 } 1990 1991 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) 1992 { 1993 u32 ecx = kvm_rcx_read(vcpu); 1994 u64 data; 1995 int r; 1996 1997 r = kvm_get_msr_with_filter(vcpu, ecx, &data); 1998 1999 if (!r) { 2000 trace_kvm_msr_read(ecx, data); 2001 2002 kvm_rax_write(vcpu, data & -1u); 2003 kvm_rdx_write(vcpu, (data >> 32) & -1u); 2004 } else { 2005 /* MSR read failed? See if we should ask user space */ 2006 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0, 2007 complete_fast_rdmsr, r)) 2008 return 0; 2009 trace_kvm_msr_read_ex(ecx); 2010 } 2011 2012 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 2013 } 2014 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); 2015 2016 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) 2017 { 2018 u32 ecx = kvm_rcx_read(vcpu); 2019 u64 data = kvm_read_edx_eax(vcpu); 2020 int r; 2021 2022 r = kvm_set_msr_with_filter(vcpu, ecx, data); 2023 2024 if (!r) { 2025 trace_kvm_msr_write(ecx, data); 2026 } else { 2027 /* MSR write failed? See if we should ask user space */ 2028 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data, 2029 complete_fast_msr_access, r)) 2030 return 0; 2031 /* Signal all other negative errors to userspace */ 2032 if (r < 0) 2033 return r; 2034 trace_kvm_msr_write_ex(ecx, data); 2035 } 2036 2037 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 2038 } 2039 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); 2040 2041 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) 2042 { 2043 return kvm_skip_emulated_instruction(vcpu); 2044 } 2045 EXPORT_SYMBOL_GPL(kvm_emulate_as_nop); 2046 2047 int kvm_emulate_invd(struct kvm_vcpu *vcpu) 2048 { 2049 /* Treat an INVD instruction as a NOP and just skip it. */ 2050 return kvm_emulate_as_nop(vcpu); 2051 } 2052 EXPORT_SYMBOL_GPL(kvm_emulate_invd); 2053 2054 int kvm_emulate_mwait(struct kvm_vcpu *vcpu) 2055 { 2056 pr_warn_once("kvm: MWAIT instruction emulated as NOP!\n"); 2057 return kvm_emulate_as_nop(vcpu); 2058 } 2059 EXPORT_SYMBOL_GPL(kvm_emulate_mwait); 2060 2061 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) 2062 { 2063 kvm_queue_exception(vcpu, UD_VECTOR); 2064 return 1; 2065 } 2066 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); 2067 2068 int kvm_emulate_monitor(struct kvm_vcpu *vcpu) 2069 { 2070 pr_warn_once("kvm: MONITOR instruction emulated as NOP!\n"); 2071 return kvm_emulate_as_nop(vcpu); 2072 } 2073 EXPORT_SYMBOL_GPL(kvm_emulate_monitor); 2074 2075 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) 2076 { 2077 xfer_to_guest_mode_prepare(); 2078 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || 2079 xfer_to_guest_mode_work_pending(); 2080 } 2081 2082 /* 2083 * The fast path for frequent and performance sensitive wrmsr emulation, 2084 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces 2085 * the latency of virtual IPI by avoiding the expensive bits of transitioning 2086 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the 2087 * other cases which must be called after interrupts are enabled on the host. 2088 */ 2089 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) 2090 { 2091 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) 2092 return 1; 2093 2094 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && 2095 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && 2096 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && 2097 ((u32)(data >> 32) != X2APIC_BROADCAST)) 2098 return kvm_x2apic_icr_write(vcpu->arch.apic, data); 2099 2100 return 1; 2101 } 2102 2103 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) 2104 { 2105 if (!kvm_can_use_hv_timer(vcpu)) 2106 return 1; 2107 2108 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2109 return 0; 2110 } 2111 2112 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) 2113 { 2114 u32 msr = kvm_rcx_read(vcpu); 2115 u64 data; 2116 fastpath_t ret = EXIT_FASTPATH_NONE; 2117 2118 switch (msr) { 2119 case APIC_BASE_MSR + (APIC_ICR >> 4): 2120 data = kvm_read_edx_eax(vcpu); 2121 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { 2122 kvm_skip_emulated_instruction(vcpu); 2123 ret = EXIT_FASTPATH_EXIT_HANDLED; 2124 } 2125 break; 2126 case MSR_IA32_TSC_DEADLINE: 2127 data = kvm_read_edx_eax(vcpu); 2128 if (!handle_fastpath_set_tscdeadline(vcpu, data)) { 2129 kvm_skip_emulated_instruction(vcpu); 2130 ret = EXIT_FASTPATH_REENTER_GUEST; 2131 } 2132 break; 2133 default: 2134 break; 2135 } 2136 2137 if (ret != EXIT_FASTPATH_NONE) 2138 trace_kvm_msr_write(msr, data); 2139 2140 return ret; 2141 } 2142 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); 2143 2144 /* 2145 * Adapt set_msr() to msr_io()'s calling convention 2146 */ 2147 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2148 { 2149 return kvm_get_msr_ignored_check(vcpu, index, data, true); 2150 } 2151 2152 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2153 { 2154 return kvm_set_msr_ignored_check(vcpu, index, *data, true); 2155 } 2156 2157 #ifdef CONFIG_X86_64 2158 struct pvclock_clock { 2159 int vclock_mode; 2160 u64 cycle_last; 2161 u64 mask; 2162 u32 mult; 2163 u32 shift; 2164 u64 base_cycles; 2165 u64 offset; 2166 }; 2167 2168 struct pvclock_gtod_data { 2169 seqcount_t seq; 2170 2171 struct pvclock_clock clock; /* extract of a clocksource struct */ 2172 struct pvclock_clock raw_clock; /* extract of a clocksource struct */ 2173 2174 ktime_t offs_boot; 2175 u64 wall_time_sec; 2176 }; 2177 2178 static struct pvclock_gtod_data pvclock_gtod_data; 2179 2180 static void update_pvclock_gtod(struct timekeeper *tk) 2181 { 2182 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 2183 2184 write_seqcount_begin(&vdata->seq); 2185 2186 /* copy pvclock gtod data */ 2187 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; 2188 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 2189 vdata->clock.mask = tk->tkr_mono.mask; 2190 vdata->clock.mult = tk->tkr_mono.mult; 2191 vdata->clock.shift = tk->tkr_mono.shift; 2192 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 2193 vdata->clock.offset = tk->tkr_mono.base; 2194 2195 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; 2196 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; 2197 vdata->raw_clock.mask = tk->tkr_raw.mask; 2198 vdata->raw_clock.mult = tk->tkr_raw.mult; 2199 vdata->raw_clock.shift = tk->tkr_raw.shift; 2200 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; 2201 vdata->raw_clock.offset = tk->tkr_raw.base; 2202 2203 vdata->wall_time_sec = tk->xtime_sec; 2204 2205 vdata->offs_boot = tk->offs_boot; 2206 2207 write_seqcount_end(&vdata->seq); 2208 } 2209 2210 static s64 get_kvmclock_base_ns(void) 2211 { 2212 /* Count up from boot time, but with the frequency of the raw clock. */ 2213 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); 2214 } 2215 #else 2216 static s64 get_kvmclock_base_ns(void) 2217 { 2218 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ 2219 return ktime_get_boottime_ns(); 2220 } 2221 #endif 2222 2223 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) 2224 { 2225 int version; 2226 int r; 2227 struct pvclock_wall_clock wc; 2228 u32 wc_sec_hi; 2229 u64 wall_nsec; 2230 2231 if (!wall_clock) 2232 return; 2233 2234 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 2235 if (r) 2236 return; 2237 2238 if (version & 1) 2239 ++version; /* first time write, random junk */ 2240 2241 ++version; 2242 2243 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 2244 return; 2245 2246 /* 2247 * The guest calculates current wall clock time by adding 2248 * system time (updated by kvm_guest_time_update below) to the 2249 * wall clock specified here. We do the reverse here. 2250 */ 2251 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); 2252 2253 wc.nsec = do_div(wall_nsec, 1000000000); 2254 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ 2255 wc.version = version; 2256 2257 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 2258 2259 if (sec_hi_ofs) { 2260 wc_sec_hi = wall_nsec >> 32; 2261 kvm_write_guest(kvm, wall_clock + sec_hi_ofs, 2262 &wc_sec_hi, sizeof(wc_sec_hi)); 2263 } 2264 2265 version++; 2266 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 2267 } 2268 2269 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, 2270 bool old_msr, bool host_initiated) 2271 { 2272 struct kvm_arch *ka = &vcpu->kvm->arch; 2273 2274 if (vcpu->vcpu_id == 0 && !host_initiated) { 2275 if (ka->boot_vcpu_runs_old_kvmclock != old_msr) 2276 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2277 2278 ka->boot_vcpu_runs_old_kvmclock = old_msr; 2279 } 2280 2281 vcpu->arch.time = system_time; 2282 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2283 2284 /* we verify if the enable bit is set... */ 2285 if (system_time & 1) { 2286 kvm_gfn_to_pfn_cache_init(vcpu->kvm, &vcpu->arch.pv_time, vcpu, 2287 KVM_HOST_USES_PFN, system_time & ~1ULL, 2288 sizeof(struct pvclock_vcpu_time_info)); 2289 } else { 2290 kvm_gfn_to_pfn_cache_destroy(vcpu->kvm, &vcpu->arch.pv_time); 2291 } 2292 2293 return; 2294 } 2295 2296 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 2297 { 2298 do_shl32_div32(dividend, divisor); 2299 return dividend; 2300 } 2301 2302 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 2303 s8 *pshift, u32 *pmultiplier) 2304 { 2305 uint64_t scaled64; 2306 int32_t shift = 0; 2307 uint64_t tps64; 2308 uint32_t tps32; 2309 2310 tps64 = base_hz; 2311 scaled64 = scaled_hz; 2312 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 2313 tps64 >>= 1; 2314 shift--; 2315 } 2316 2317 tps32 = (uint32_t)tps64; 2318 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 2319 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 2320 scaled64 >>= 1; 2321 else 2322 tps32 <<= 1; 2323 shift++; 2324 } 2325 2326 *pshift = shift; 2327 *pmultiplier = div_frac(scaled64, tps32); 2328 } 2329 2330 #ifdef CONFIG_X86_64 2331 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 2332 #endif 2333 2334 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 2335 static unsigned long max_tsc_khz; 2336 2337 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 2338 { 2339 u64 v = (u64)khz * (1000000 + ppm); 2340 do_div(v, 1000000); 2341 return v; 2342 } 2343 2344 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier); 2345 2346 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 2347 { 2348 u64 ratio; 2349 2350 /* Guest TSC same frequency as host TSC? */ 2351 if (!scale) { 2352 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); 2353 return 0; 2354 } 2355 2356 /* TSC scaling supported? */ 2357 if (!kvm_has_tsc_control) { 2358 if (user_tsc_khz > tsc_khz) { 2359 vcpu->arch.tsc_catchup = 1; 2360 vcpu->arch.tsc_always_catchup = 1; 2361 return 0; 2362 } else { 2363 pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); 2364 return -1; 2365 } 2366 } 2367 2368 /* TSC scaling required - calculate ratio */ 2369 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 2370 user_tsc_khz, tsc_khz); 2371 2372 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 2373 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 2374 user_tsc_khz); 2375 return -1; 2376 } 2377 2378 kvm_vcpu_write_tsc_multiplier(vcpu, ratio); 2379 return 0; 2380 } 2381 2382 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 2383 { 2384 u32 thresh_lo, thresh_hi; 2385 int use_scaling = 0; 2386 2387 /* tsc_khz can be zero if TSC calibration fails */ 2388 if (user_tsc_khz == 0) { 2389 /* set tsc_scaling_ratio to a safe value */ 2390 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); 2391 return -1; 2392 } 2393 2394 /* Compute a scale to convert nanoseconds in TSC cycles */ 2395 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 2396 &vcpu->arch.virtual_tsc_shift, 2397 &vcpu->arch.virtual_tsc_mult); 2398 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 2399 2400 /* 2401 * Compute the variation in TSC rate which is acceptable 2402 * within the range of tolerance and decide if the 2403 * rate being applied is within that bounds of the hardware 2404 * rate. If so, no scaling or compensation need be done. 2405 */ 2406 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 2407 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 2408 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 2409 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 2410 use_scaling = 1; 2411 } 2412 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 2413 } 2414 2415 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 2416 { 2417 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 2418 vcpu->arch.virtual_tsc_mult, 2419 vcpu->arch.virtual_tsc_shift); 2420 tsc += vcpu->arch.this_tsc_write; 2421 return tsc; 2422 } 2423 2424 #ifdef CONFIG_X86_64 2425 static inline int gtod_is_based_on_tsc(int mode) 2426 { 2427 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; 2428 } 2429 #endif 2430 2431 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 2432 { 2433 #ifdef CONFIG_X86_64 2434 bool vcpus_matched; 2435 struct kvm_arch *ka = &vcpu->kvm->arch; 2436 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2437 2438 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2439 atomic_read(&vcpu->kvm->online_vcpus)); 2440 2441 /* 2442 * Once the masterclock is enabled, always perform request in 2443 * order to update it. 2444 * 2445 * In order to enable masterclock, the host clocksource must be TSC 2446 * and the vcpus need to have matched TSCs. When that happens, 2447 * perform request to enable masterclock. 2448 */ 2449 if (ka->use_master_clock || 2450 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 2451 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2452 2453 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 2454 atomic_read(&vcpu->kvm->online_vcpus), 2455 ka->use_master_clock, gtod->clock.vclock_mode); 2456 #endif 2457 } 2458 2459 /* 2460 * Multiply tsc by a fixed point number represented by ratio. 2461 * 2462 * The most significant 64-N bits (mult) of ratio represent the 2463 * integral part of the fixed point number; the remaining N bits 2464 * (frac) represent the fractional part, ie. ratio represents a fixed 2465 * point number (mult + frac * 2^(-N)). 2466 * 2467 * N equals to kvm_tsc_scaling_ratio_frac_bits. 2468 */ 2469 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 2470 { 2471 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 2472 } 2473 2474 u64 kvm_scale_tsc(u64 tsc, u64 ratio) 2475 { 2476 u64 _tsc = tsc; 2477 2478 if (ratio != kvm_default_tsc_scaling_ratio) 2479 _tsc = __scale_tsc(ratio, tsc); 2480 2481 return _tsc; 2482 } 2483 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 2484 2485 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 2486 { 2487 u64 tsc; 2488 2489 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio); 2490 2491 return target_tsc - tsc; 2492 } 2493 2494 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 2495 { 2496 return vcpu->arch.l1_tsc_offset + 2497 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio); 2498 } 2499 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 2500 2501 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier) 2502 { 2503 u64 nested_offset; 2504 2505 if (l2_multiplier == kvm_default_tsc_scaling_ratio) 2506 nested_offset = l1_offset; 2507 else 2508 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier, 2509 kvm_tsc_scaling_ratio_frac_bits); 2510 2511 nested_offset += l2_offset; 2512 return nested_offset; 2513 } 2514 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset); 2515 2516 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier) 2517 { 2518 if (l2_multiplier != kvm_default_tsc_scaling_ratio) 2519 return mul_u64_u64_shr(l1_multiplier, l2_multiplier, 2520 kvm_tsc_scaling_ratio_frac_bits); 2521 2522 return l1_multiplier; 2523 } 2524 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier); 2525 2526 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset) 2527 { 2528 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 2529 vcpu->arch.l1_tsc_offset, 2530 l1_offset); 2531 2532 vcpu->arch.l1_tsc_offset = l1_offset; 2533 2534 /* 2535 * If we are here because L1 chose not to trap WRMSR to TSC then 2536 * according to the spec this should set L1's TSC (as opposed to 2537 * setting L1's offset for L2). 2538 */ 2539 if (is_guest_mode(vcpu)) 2540 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( 2541 l1_offset, 2542 static_call(kvm_x86_get_l2_tsc_offset)(vcpu), 2543 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2544 else 2545 vcpu->arch.tsc_offset = l1_offset; 2546 2547 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset); 2548 } 2549 2550 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier) 2551 { 2552 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier; 2553 2554 /* Userspace is changing the multiplier while L2 is active */ 2555 if (is_guest_mode(vcpu)) 2556 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( 2557 l1_multiplier, 2558 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2559 else 2560 vcpu->arch.tsc_scaling_ratio = l1_multiplier; 2561 2562 if (kvm_has_tsc_control) 2563 static_call(kvm_x86_write_tsc_multiplier)( 2564 vcpu, vcpu->arch.tsc_scaling_ratio); 2565 } 2566 2567 static inline bool kvm_check_tsc_unstable(void) 2568 { 2569 #ifdef CONFIG_X86_64 2570 /* 2571 * TSC is marked unstable when we're running on Hyper-V, 2572 * 'TSC page' clocksource is good. 2573 */ 2574 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) 2575 return false; 2576 #endif 2577 return check_tsc_unstable(); 2578 } 2579 2580 /* 2581 * Infers attempts to synchronize the guest's tsc from host writes. Sets the 2582 * offset for the vcpu and tracks the TSC matching generation that the vcpu 2583 * participates in. 2584 */ 2585 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc, 2586 u64 ns, bool matched) 2587 { 2588 struct kvm *kvm = vcpu->kvm; 2589 2590 lockdep_assert_held(&kvm->arch.tsc_write_lock); 2591 2592 /* 2593 * We also track th most recent recorded KHZ, write and time to 2594 * allow the matching interval to be extended at each write. 2595 */ 2596 kvm->arch.last_tsc_nsec = ns; 2597 kvm->arch.last_tsc_write = tsc; 2598 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 2599 kvm->arch.last_tsc_offset = offset; 2600 2601 vcpu->arch.last_guest_tsc = tsc; 2602 2603 kvm_vcpu_write_tsc_offset(vcpu, offset); 2604 2605 if (!matched) { 2606 /* 2607 * We split periods of matched TSC writes into generations. 2608 * For each generation, we track the original measured 2609 * nanosecond time, offset, and write, so if TSCs are in 2610 * sync, we can match exact offset, and if not, we can match 2611 * exact software computation in compute_guest_tsc() 2612 * 2613 * These values are tracked in kvm->arch.cur_xxx variables. 2614 */ 2615 kvm->arch.cur_tsc_generation++; 2616 kvm->arch.cur_tsc_nsec = ns; 2617 kvm->arch.cur_tsc_write = tsc; 2618 kvm->arch.cur_tsc_offset = offset; 2619 kvm->arch.nr_vcpus_matched_tsc = 0; 2620 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) { 2621 kvm->arch.nr_vcpus_matched_tsc++; 2622 } 2623 2624 /* Keep track of which generation this VCPU has synchronized to */ 2625 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 2626 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 2627 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 2628 2629 kvm_track_tsc_matching(vcpu); 2630 } 2631 2632 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) 2633 { 2634 struct kvm *kvm = vcpu->kvm; 2635 u64 offset, ns, elapsed; 2636 unsigned long flags; 2637 bool matched = false; 2638 bool synchronizing = false; 2639 2640 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 2641 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2642 ns = get_kvmclock_base_ns(); 2643 elapsed = ns - kvm->arch.last_tsc_nsec; 2644 2645 if (vcpu->arch.virtual_tsc_khz) { 2646 if (data == 0) { 2647 /* 2648 * detection of vcpu initialization -- need to sync 2649 * with other vCPUs. This particularly helps to keep 2650 * kvm_clock stable after CPU hotplug 2651 */ 2652 synchronizing = true; 2653 } else { 2654 u64 tsc_exp = kvm->arch.last_tsc_write + 2655 nsec_to_cycles(vcpu, elapsed); 2656 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 2657 /* 2658 * Special case: TSC write with a small delta (1 second) 2659 * of virtual cycle time against real time is 2660 * interpreted as an attempt to synchronize the CPU. 2661 */ 2662 synchronizing = data < tsc_exp + tsc_hz && 2663 data + tsc_hz > tsc_exp; 2664 } 2665 } 2666 2667 /* 2668 * For a reliable TSC, we can match TSC offsets, and for an unstable 2669 * TSC, we add elapsed time in this computation. We could let the 2670 * compensation code attempt to catch up if we fall behind, but 2671 * it's better to try to match offsets from the beginning. 2672 */ 2673 if (synchronizing && 2674 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 2675 if (!kvm_check_tsc_unstable()) { 2676 offset = kvm->arch.cur_tsc_offset; 2677 } else { 2678 u64 delta = nsec_to_cycles(vcpu, elapsed); 2679 data += delta; 2680 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2681 } 2682 matched = true; 2683 } 2684 2685 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched); 2686 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 2687 } 2688 2689 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 2690 s64 adjustment) 2691 { 2692 u64 tsc_offset = vcpu->arch.l1_tsc_offset; 2693 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 2694 } 2695 2696 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 2697 { 2698 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 2699 WARN_ON(adjustment < 0); 2700 adjustment = kvm_scale_tsc((u64) adjustment, 2701 vcpu->arch.l1_tsc_scaling_ratio); 2702 adjust_tsc_offset_guest(vcpu, adjustment); 2703 } 2704 2705 #ifdef CONFIG_X86_64 2706 2707 static u64 read_tsc(void) 2708 { 2709 u64 ret = (u64)rdtsc_ordered(); 2710 u64 last = pvclock_gtod_data.clock.cycle_last; 2711 2712 if (likely(ret >= last)) 2713 return ret; 2714 2715 /* 2716 * GCC likes to generate cmov here, but this branch is extremely 2717 * predictable (it's just a function of time and the likely is 2718 * very likely) and there's a data dependence, so force GCC 2719 * to generate a branch instead. I don't barrier() because 2720 * we don't actually need a barrier, and if this function 2721 * ever gets inlined it will generate worse code. 2722 */ 2723 asm volatile (""); 2724 return last; 2725 } 2726 2727 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, 2728 int *mode) 2729 { 2730 long v; 2731 u64 tsc_pg_val; 2732 2733 switch (clock->vclock_mode) { 2734 case VDSO_CLOCKMODE_HVCLOCK: 2735 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 2736 tsc_timestamp); 2737 if (tsc_pg_val != U64_MAX) { 2738 /* TSC page valid */ 2739 *mode = VDSO_CLOCKMODE_HVCLOCK; 2740 v = (tsc_pg_val - clock->cycle_last) & 2741 clock->mask; 2742 } else { 2743 /* TSC page invalid */ 2744 *mode = VDSO_CLOCKMODE_NONE; 2745 } 2746 break; 2747 case VDSO_CLOCKMODE_TSC: 2748 *mode = VDSO_CLOCKMODE_TSC; 2749 *tsc_timestamp = read_tsc(); 2750 v = (*tsc_timestamp - clock->cycle_last) & 2751 clock->mask; 2752 break; 2753 default: 2754 *mode = VDSO_CLOCKMODE_NONE; 2755 } 2756 2757 if (*mode == VDSO_CLOCKMODE_NONE) 2758 *tsc_timestamp = v = 0; 2759 2760 return v * clock->mult; 2761 } 2762 2763 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) 2764 { 2765 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2766 unsigned long seq; 2767 int mode; 2768 u64 ns; 2769 2770 do { 2771 seq = read_seqcount_begin(>od->seq); 2772 ns = gtod->raw_clock.base_cycles; 2773 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); 2774 ns >>= gtod->raw_clock.shift; 2775 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); 2776 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2777 *t = ns; 2778 2779 return mode; 2780 } 2781 2782 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 2783 { 2784 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2785 unsigned long seq; 2786 int mode; 2787 u64 ns; 2788 2789 do { 2790 seq = read_seqcount_begin(>od->seq); 2791 ts->tv_sec = gtod->wall_time_sec; 2792 ns = gtod->clock.base_cycles; 2793 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2794 ns >>= gtod->clock.shift; 2795 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2796 2797 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 2798 ts->tv_nsec = ns; 2799 2800 return mode; 2801 } 2802 2803 /* returns true if host is using TSC based clocksource */ 2804 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2805 { 2806 /* checked again under seqlock below */ 2807 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2808 return false; 2809 2810 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, 2811 tsc_timestamp)); 2812 } 2813 2814 /* returns true if host is using TSC based clocksource */ 2815 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 2816 u64 *tsc_timestamp) 2817 { 2818 /* checked again under seqlock below */ 2819 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2820 return false; 2821 2822 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 2823 } 2824 #endif 2825 2826 /* 2827 * 2828 * Assuming a stable TSC across physical CPUS, and a stable TSC 2829 * across virtual CPUs, the following condition is possible. 2830 * Each numbered line represents an event visible to both 2831 * CPUs at the next numbered event. 2832 * 2833 * "timespecX" represents host monotonic time. "tscX" represents 2834 * RDTSC value. 2835 * 2836 * VCPU0 on CPU0 | VCPU1 on CPU1 2837 * 2838 * 1. read timespec0,tsc0 2839 * 2. | timespec1 = timespec0 + N 2840 * | tsc1 = tsc0 + M 2841 * 3. transition to guest | transition to guest 2842 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 2843 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 2844 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 2845 * 2846 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 2847 * 2848 * - ret0 < ret1 2849 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 2850 * ... 2851 * - 0 < N - M => M < N 2852 * 2853 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 2854 * always the case (the difference between two distinct xtime instances 2855 * might be smaller then the difference between corresponding TSC reads, 2856 * when updating guest vcpus pvclock areas). 2857 * 2858 * To avoid that problem, do not allow visibility of distinct 2859 * system_timestamp/tsc_timestamp values simultaneously: use a master 2860 * copy of host monotonic time values. Update that master copy 2861 * in lockstep. 2862 * 2863 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2864 * 2865 */ 2866 2867 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2868 { 2869 #ifdef CONFIG_X86_64 2870 struct kvm_arch *ka = &kvm->arch; 2871 int vclock_mode; 2872 bool host_tsc_clocksource, vcpus_matched; 2873 2874 lockdep_assert_held(&kvm->arch.tsc_write_lock); 2875 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2876 atomic_read(&kvm->online_vcpus)); 2877 2878 /* 2879 * If the host uses TSC clock, then passthrough TSC as stable 2880 * to the guest. 2881 */ 2882 host_tsc_clocksource = kvm_get_time_and_clockread( 2883 &ka->master_kernel_ns, 2884 &ka->master_cycle_now); 2885 2886 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2887 && !ka->backwards_tsc_observed 2888 && !ka->boot_vcpu_runs_old_kvmclock; 2889 2890 if (ka->use_master_clock) 2891 atomic_set(&kvm_guest_has_master_clock, 1); 2892 2893 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2894 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2895 vcpus_matched); 2896 #endif 2897 } 2898 2899 static void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2900 { 2901 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2902 } 2903 2904 static void __kvm_start_pvclock_update(struct kvm *kvm) 2905 { 2906 raw_spin_lock_irq(&kvm->arch.tsc_write_lock); 2907 write_seqcount_begin(&kvm->arch.pvclock_sc); 2908 } 2909 2910 static void kvm_start_pvclock_update(struct kvm *kvm) 2911 { 2912 kvm_make_mclock_inprogress_request(kvm); 2913 2914 /* no guest entries from this point */ 2915 __kvm_start_pvclock_update(kvm); 2916 } 2917 2918 static void kvm_end_pvclock_update(struct kvm *kvm) 2919 { 2920 struct kvm_arch *ka = &kvm->arch; 2921 struct kvm_vcpu *vcpu; 2922 unsigned long i; 2923 2924 write_seqcount_end(&ka->pvclock_sc); 2925 raw_spin_unlock_irq(&ka->tsc_write_lock); 2926 kvm_for_each_vcpu(i, vcpu, kvm) 2927 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2928 2929 /* guest entries allowed */ 2930 kvm_for_each_vcpu(i, vcpu, kvm) 2931 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2932 } 2933 2934 static void kvm_update_masterclock(struct kvm *kvm) 2935 { 2936 kvm_hv_request_tsc_page_update(kvm); 2937 kvm_start_pvclock_update(kvm); 2938 pvclock_update_vm_gtod_copy(kvm); 2939 kvm_end_pvclock_update(kvm); 2940 } 2941 2942 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */ 2943 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) 2944 { 2945 struct kvm_arch *ka = &kvm->arch; 2946 struct pvclock_vcpu_time_info hv_clock; 2947 2948 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2949 get_cpu(); 2950 2951 data->flags = 0; 2952 if (ka->use_master_clock && __this_cpu_read(cpu_tsc_khz)) { 2953 #ifdef CONFIG_X86_64 2954 struct timespec64 ts; 2955 2956 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) { 2957 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec; 2958 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC; 2959 } else 2960 #endif 2961 data->host_tsc = rdtsc(); 2962 2963 data->flags |= KVM_CLOCK_TSC_STABLE; 2964 hv_clock.tsc_timestamp = ka->master_cycle_now; 2965 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2966 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2967 &hv_clock.tsc_shift, 2968 &hv_clock.tsc_to_system_mul); 2969 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc); 2970 } else { 2971 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset; 2972 } 2973 2974 put_cpu(); 2975 } 2976 2977 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) 2978 { 2979 struct kvm_arch *ka = &kvm->arch; 2980 unsigned seq; 2981 2982 do { 2983 seq = read_seqcount_begin(&ka->pvclock_sc); 2984 __get_kvmclock(kvm, data); 2985 } while (read_seqcount_retry(&ka->pvclock_sc, seq)); 2986 } 2987 2988 u64 get_kvmclock_ns(struct kvm *kvm) 2989 { 2990 struct kvm_clock_data data; 2991 2992 get_kvmclock(kvm, &data); 2993 return data.clock; 2994 } 2995 2996 static void kvm_setup_guest_pvclock(struct kvm_vcpu *v, 2997 struct gfn_to_pfn_cache *gpc, 2998 unsigned int offset) 2999 { 3000 struct kvm_vcpu_arch *vcpu = &v->arch; 3001 struct pvclock_vcpu_time_info *guest_hv_clock; 3002 unsigned long flags; 3003 3004 read_lock_irqsave(&gpc->lock, flags); 3005 while (!kvm_gfn_to_pfn_cache_check(v->kvm, gpc, gpc->gpa, 3006 offset + sizeof(*guest_hv_clock))) { 3007 read_unlock_irqrestore(&gpc->lock, flags); 3008 3009 if (kvm_gfn_to_pfn_cache_refresh(v->kvm, gpc, gpc->gpa, 3010 offset + sizeof(*guest_hv_clock))) 3011 return; 3012 3013 read_lock_irqsave(&gpc->lock, flags); 3014 } 3015 3016 guest_hv_clock = (void *)(gpc->khva + offset); 3017 3018 /* 3019 * This VCPU is paused, but it's legal for a guest to read another 3020 * VCPU's kvmclock, so we really have to follow the specification where 3021 * it says that version is odd if data is being modified, and even after 3022 * it is consistent. 3023 */ 3024 3025 guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1; 3026 smp_wmb(); 3027 3028 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 3029 vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED); 3030 3031 if (vcpu->pvclock_set_guest_stopped_request) { 3032 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 3033 vcpu->pvclock_set_guest_stopped_request = false; 3034 } 3035 3036 memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock)); 3037 smp_wmb(); 3038 3039 guest_hv_clock->version = ++vcpu->hv_clock.version; 3040 3041 mark_page_dirty_in_slot(v->kvm, gpc->memslot, gpc->gpa >> PAGE_SHIFT); 3042 read_unlock_irqrestore(&gpc->lock, flags); 3043 3044 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 3045 } 3046 3047 static int kvm_guest_time_update(struct kvm_vcpu *v) 3048 { 3049 unsigned long flags, tgt_tsc_khz; 3050 unsigned seq; 3051 struct kvm_vcpu_arch *vcpu = &v->arch; 3052 struct kvm_arch *ka = &v->kvm->arch; 3053 s64 kernel_ns; 3054 u64 tsc_timestamp, host_tsc; 3055 u8 pvclock_flags; 3056 bool use_master_clock; 3057 3058 kernel_ns = 0; 3059 host_tsc = 0; 3060 3061 /* 3062 * If the host uses TSC clock, then passthrough TSC as stable 3063 * to the guest. 3064 */ 3065 do { 3066 seq = read_seqcount_begin(&ka->pvclock_sc); 3067 use_master_clock = ka->use_master_clock; 3068 if (use_master_clock) { 3069 host_tsc = ka->master_cycle_now; 3070 kernel_ns = ka->master_kernel_ns; 3071 } 3072 } while (read_seqcount_retry(&ka->pvclock_sc, seq)); 3073 3074 /* Keep irq disabled to prevent changes to the clock */ 3075 local_irq_save(flags); 3076 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 3077 if (unlikely(tgt_tsc_khz == 0)) { 3078 local_irq_restore(flags); 3079 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 3080 return 1; 3081 } 3082 if (!use_master_clock) { 3083 host_tsc = rdtsc(); 3084 kernel_ns = get_kvmclock_base_ns(); 3085 } 3086 3087 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 3088 3089 /* 3090 * We may have to catch up the TSC to match elapsed wall clock 3091 * time for two reasons, even if kvmclock is used. 3092 * 1) CPU could have been running below the maximum TSC rate 3093 * 2) Broken TSC compensation resets the base at each VCPU 3094 * entry to avoid unknown leaps of TSC even when running 3095 * again on the same CPU. This may cause apparent elapsed 3096 * time to disappear, and the guest to stand still or run 3097 * very slowly. 3098 */ 3099 if (vcpu->tsc_catchup) { 3100 u64 tsc = compute_guest_tsc(v, kernel_ns); 3101 if (tsc > tsc_timestamp) { 3102 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 3103 tsc_timestamp = tsc; 3104 } 3105 } 3106 3107 local_irq_restore(flags); 3108 3109 /* With all the info we got, fill in the values */ 3110 3111 if (kvm_has_tsc_control) 3112 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz, 3113 v->arch.l1_tsc_scaling_ratio); 3114 3115 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 3116 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 3117 &vcpu->hv_clock.tsc_shift, 3118 &vcpu->hv_clock.tsc_to_system_mul); 3119 vcpu->hw_tsc_khz = tgt_tsc_khz; 3120 } 3121 3122 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 3123 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 3124 vcpu->last_guest_tsc = tsc_timestamp; 3125 3126 /* If the host uses TSC clocksource, then it is stable */ 3127 pvclock_flags = 0; 3128 if (use_master_clock) 3129 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 3130 3131 vcpu->hv_clock.flags = pvclock_flags; 3132 3133 if (vcpu->pv_time.active) 3134 kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0); 3135 if (vcpu->xen.vcpu_info_cache.active) 3136 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache, 3137 offsetof(struct compat_vcpu_info, time)); 3138 if (vcpu->xen.vcpu_time_info_cache.active) 3139 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0); 3140 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 3141 return 0; 3142 } 3143 3144 /* 3145 * kvmclock updates which are isolated to a given vcpu, such as 3146 * vcpu->cpu migration, should not allow system_timestamp from 3147 * the rest of the vcpus to remain static. Otherwise ntp frequency 3148 * correction applies to one vcpu's system_timestamp but not 3149 * the others. 3150 * 3151 * So in those cases, request a kvmclock update for all vcpus. 3152 * We need to rate-limit these requests though, as they can 3153 * considerably slow guests that have a large number of vcpus. 3154 * The time for a remote vcpu to update its kvmclock is bound 3155 * by the delay we use to rate-limit the updates. 3156 */ 3157 3158 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 3159 3160 static void kvmclock_update_fn(struct work_struct *work) 3161 { 3162 unsigned long i; 3163 struct delayed_work *dwork = to_delayed_work(work); 3164 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3165 kvmclock_update_work); 3166 struct kvm *kvm = container_of(ka, struct kvm, arch); 3167 struct kvm_vcpu *vcpu; 3168 3169 kvm_for_each_vcpu(i, vcpu, kvm) { 3170 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3171 kvm_vcpu_kick(vcpu); 3172 } 3173 } 3174 3175 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 3176 { 3177 struct kvm *kvm = v->kvm; 3178 3179 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 3180 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 3181 KVMCLOCK_UPDATE_DELAY); 3182 } 3183 3184 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 3185 3186 static void kvmclock_sync_fn(struct work_struct *work) 3187 { 3188 struct delayed_work *dwork = to_delayed_work(work); 3189 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3190 kvmclock_sync_work); 3191 struct kvm *kvm = container_of(ka, struct kvm, arch); 3192 3193 if (!kvmclock_periodic_sync) 3194 return; 3195 3196 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 3197 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 3198 KVMCLOCK_SYNC_PERIOD); 3199 } 3200 3201 /* 3202 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 3203 */ 3204 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 3205 { 3206 /* McStatusWrEn enabled? */ 3207 if (guest_cpuid_is_amd_or_hygon(vcpu)) 3208 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 3209 3210 return false; 3211 } 3212 3213 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3214 { 3215 u64 mcg_cap = vcpu->arch.mcg_cap; 3216 unsigned bank_num = mcg_cap & 0xff; 3217 u32 msr = msr_info->index; 3218 u64 data = msr_info->data; 3219 3220 switch (msr) { 3221 case MSR_IA32_MCG_STATUS: 3222 vcpu->arch.mcg_status = data; 3223 break; 3224 case MSR_IA32_MCG_CTL: 3225 if (!(mcg_cap & MCG_CTL_P) && 3226 (data || !msr_info->host_initiated)) 3227 return 1; 3228 if (data != 0 && data != ~(u64)0) 3229 return 1; 3230 vcpu->arch.mcg_ctl = data; 3231 break; 3232 default: 3233 if (msr >= MSR_IA32_MC0_CTL && 3234 msr < MSR_IA32_MCx_CTL(bank_num)) { 3235 u32 offset = array_index_nospec( 3236 msr - MSR_IA32_MC0_CTL, 3237 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3238 3239 /* only 0 or all 1s can be written to IA32_MCi_CTL 3240 * some Linux kernels though clear bit 10 in bank 4 to 3241 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 3242 * this to avoid an uncatched #GP in the guest 3243 */ 3244 if ((offset & 0x3) == 0 && 3245 data != 0 && (data | (1 << 10)) != ~(u64)0) 3246 return -1; 3247 3248 /* MCi_STATUS */ 3249 if (!msr_info->host_initiated && 3250 (offset & 0x3) == 1 && data != 0) { 3251 if (!can_set_mci_status(vcpu)) 3252 return -1; 3253 } 3254 3255 vcpu->arch.mce_banks[offset] = data; 3256 break; 3257 } 3258 return 1; 3259 } 3260 return 0; 3261 } 3262 3263 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) 3264 { 3265 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; 3266 3267 return (vcpu->arch.apf.msr_en_val & mask) == mask; 3268 } 3269 3270 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 3271 { 3272 gpa_t gpa = data & ~0x3f; 3273 3274 /* Bits 4:5 are reserved, Should be zero */ 3275 if (data & 0x30) 3276 return 1; 3277 3278 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && 3279 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) 3280 return 1; 3281 3282 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && 3283 (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) 3284 return 1; 3285 3286 if (!lapic_in_kernel(vcpu)) 3287 return data ? 1 : 0; 3288 3289 vcpu->arch.apf.msr_en_val = data; 3290 3291 if (!kvm_pv_async_pf_enabled(vcpu)) { 3292 kvm_clear_async_pf_completion_queue(vcpu); 3293 kvm_async_pf_hash_reset(vcpu); 3294 return 0; 3295 } 3296 3297 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 3298 sizeof(u64))) 3299 return 1; 3300 3301 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 3302 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 3303 3304 kvm_async_pf_wakeup_all(vcpu); 3305 3306 return 0; 3307 } 3308 3309 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) 3310 { 3311 /* Bits 8-63 are reserved */ 3312 if (data >> 8) 3313 return 1; 3314 3315 if (!lapic_in_kernel(vcpu)) 3316 return 1; 3317 3318 vcpu->arch.apf.msr_int_val = data; 3319 3320 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; 3321 3322 return 0; 3323 } 3324 3325 static void kvmclock_reset(struct kvm_vcpu *vcpu) 3326 { 3327 kvm_gfn_to_pfn_cache_destroy(vcpu->kvm, &vcpu->arch.pv_time); 3328 vcpu->arch.time = 0; 3329 } 3330 3331 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) 3332 { 3333 ++vcpu->stat.tlb_flush; 3334 static_call(kvm_x86_flush_tlb_all)(vcpu); 3335 } 3336 3337 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) 3338 { 3339 ++vcpu->stat.tlb_flush; 3340 3341 if (!tdp_enabled) { 3342 /* 3343 * A TLB flush on behalf of the guest is equivalent to 3344 * INVPCID(all), toggling CR4.PGE, etc., which requires 3345 * a forced sync of the shadow page tables. Ensure all the 3346 * roots are synced and the guest TLB in hardware is clean. 3347 */ 3348 kvm_mmu_sync_roots(vcpu); 3349 kvm_mmu_sync_prev_roots(vcpu); 3350 } 3351 3352 static_call(kvm_x86_flush_tlb_guest)(vcpu); 3353 } 3354 3355 3356 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu) 3357 { 3358 ++vcpu->stat.tlb_flush; 3359 static_call(kvm_x86_flush_tlb_current)(vcpu); 3360 } 3361 3362 /* 3363 * Service "local" TLB flush requests, which are specific to the current MMU 3364 * context. In addition to the generic event handling in vcpu_enter_guest(), 3365 * TLB flushes that are targeted at an MMU context also need to be serviced 3366 * prior before nested VM-Enter/VM-Exit. 3367 */ 3368 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu) 3369 { 3370 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) 3371 kvm_vcpu_flush_tlb_current(vcpu); 3372 3373 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu)) 3374 kvm_vcpu_flush_tlb_guest(vcpu); 3375 } 3376 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests); 3377 3378 static void record_steal_time(struct kvm_vcpu *vcpu) 3379 { 3380 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; 3381 struct kvm_steal_time __user *st; 3382 struct kvm_memslots *slots; 3383 u64 steal; 3384 u32 version; 3385 3386 if (kvm_xen_msr_enabled(vcpu->kvm)) { 3387 kvm_xen_runstate_set_running(vcpu); 3388 return; 3389 } 3390 3391 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3392 return; 3393 3394 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm)) 3395 return; 3396 3397 slots = kvm_memslots(vcpu->kvm); 3398 3399 if (unlikely(slots->generation != ghc->generation || 3400 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) { 3401 gfn_t gfn = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; 3402 3403 /* We rely on the fact that it fits in a single page. */ 3404 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS); 3405 3406 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gfn, sizeof(*st)) || 3407 kvm_is_error_hva(ghc->hva) || !ghc->memslot) 3408 return; 3409 } 3410 3411 st = (struct kvm_steal_time __user *)ghc->hva; 3412 /* 3413 * Doing a TLB flush here, on the guest's behalf, can avoid 3414 * expensive IPIs. 3415 */ 3416 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { 3417 u8 st_preempted = 0; 3418 int err = -EFAULT; 3419 3420 if (!user_access_begin(st, sizeof(*st))) 3421 return; 3422 3423 asm volatile("1: xchgb %0, %2\n" 3424 "xor %1, %1\n" 3425 "2:\n" 3426 _ASM_EXTABLE_UA(1b, 2b) 3427 : "+q" (st_preempted), 3428 "+&r" (err), 3429 "+m" (st->preempted)); 3430 if (err) 3431 goto out; 3432 3433 user_access_end(); 3434 3435 vcpu->arch.st.preempted = 0; 3436 3437 trace_kvm_pv_tlb_flush(vcpu->vcpu_id, 3438 st_preempted & KVM_VCPU_FLUSH_TLB); 3439 if (st_preempted & KVM_VCPU_FLUSH_TLB) 3440 kvm_vcpu_flush_tlb_guest(vcpu); 3441 3442 if (!user_access_begin(st, sizeof(*st))) 3443 goto dirty; 3444 } else { 3445 if (!user_access_begin(st, sizeof(*st))) 3446 return; 3447 3448 unsafe_put_user(0, &st->preempted, out); 3449 vcpu->arch.st.preempted = 0; 3450 } 3451 3452 unsafe_get_user(version, &st->version, out); 3453 if (version & 1) 3454 version += 1; /* first time write, random junk */ 3455 3456 version += 1; 3457 unsafe_put_user(version, &st->version, out); 3458 3459 smp_wmb(); 3460 3461 unsafe_get_user(steal, &st->steal, out); 3462 steal += current->sched_info.run_delay - 3463 vcpu->arch.st.last_steal; 3464 vcpu->arch.st.last_steal = current->sched_info.run_delay; 3465 unsafe_put_user(steal, &st->steal, out); 3466 3467 version += 1; 3468 unsafe_put_user(version, &st->version, out); 3469 3470 out: 3471 user_access_end(); 3472 dirty: 3473 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 3474 } 3475 3476 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3477 { 3478 bool pr = false; 3479 u32 msr = msr_info->index; 3480 u64 data = msr_info->data; 3481 3482 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) 3483 return kvm_xen_write_hypercall_page(vcpu, data); 3484 3485 switch (msr) { 3486 case MSR_AMD64_NB_CFG: 3487 case MSR_IA32_UCODE_WRITE: 3488 case MSR_VM_HSAVE_PA: 3489 case MSR_AMD64_PATCH_LOADER: 3490 case MSR_AMD64_BU_CFG2: 3491 case MSR_AMD64_DC_CFG: 3492 case MSR_F15H_EX_CFG: 3493 break; 3494 3495 case MSR_IA32_UCODE_REV: 3496 if (msr_info->host_initiated) 3497 vcpu->arch.microcode_version = data; 3498 break; 3499 case MSR_IA32_ARCH_CAPABILITIES: 3500 if (!msr_info->host_initiated) 3501 return 1; 3502 vcpu->arch.arch_capabilities = data; 3503 break; 3504 case MSR_IA32_PERF_CAPABILITIES: { 3505 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; 3506 3507 if (!msr_info->host_initiated) 3508 return 1; 3509 if (kvm_get_msr_feature(&msr_ent)) 3510 return 1; 3511 if (data & ~msr_ent.data) 3512 return 1; 3513 3514 vcpu->arch.perf_capabilities = data; 3515 3516 return 0; 3517 } 3518 case MSR_EFER: 3519 return set_efer(vcpu, msr_info); 3520 case MSR_K7_HWCR: 3521 data &= ~(u64)0x40; /* ignore flush filter disable */ 3522 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 3523 data &= ~(u64)0x8; /* ignore TLB cache disable */ 3524 3525 /* Handle McStatusWrEn */ 3526 if (data == BIT_ULL(18)) { 3527 vcpu->arch.msr_hwcr = data; 3528 } else if (data != 0) { 3529 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 3530 data); 3531 return 1; 3532 } 3533 break; 3534 case MSR_FAM10H_MMIO_CONF_BASE: 3535 if (data != 0) { 3536 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 3537 "0x%llx\n", data); 3538 return 1; 3539 } 3540 break; 3541 case 0x200 ... 0x2ff: 3542 return kvm_mtrr_set_msr(vcpu, msr, data); 3543 case MSR_IA32_APICBASE: 3544 return kvm_set_apic_base(vcpu, msr_info); 3545 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3546 return kvm_x2apic_msr_write(vcpu, msr, data); 3547 case MSR_IA32_TSC_DEADLINE: 3548 kvm_set_lapic_tscdeadline_msr(vcpu, data); 3549 break; 3550 case MSR_IA32_TSC_ADJUST: 3551 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 3552 if (!msr_info->host_initiated) { 3553 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 3554 adjust_tsc_offset_guest(vcpu, adj); 3555 /* Before back to guest, tsc_timestamp must be adjusted 3556 * as well, otherwise guest's percpu pvclock time could jump. 3557 */ 3558 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3559 } 3560 vcpu->arch.ia32_tsc_adjust_msr = data; 3561 } 3562 break; 3563 case MSR_IA32_MISC_ENABLE: 3564 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && 3565 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { 3566 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) 3567 return 1; 3568 vcpu->arch.ia32_misc_enable_msr = data; 3569 kvm_update_cpuid_runtime(vcpu); 3570 } else { 3571 vcpu->arch.ia32_misc_enable_msr = data; 3572 } 3573 break; 3574 case MSR_IA32_SMBASE: 3575 if (!msr_info->host_initiated) 3576 return 1; 3577 vcpu->arch.smbase = data; 3578 break; 3579 case MSR_IA32_POWER_CTL: 3580 vcpu->arch.msr_ia32_power_ctl = data; 3581 break; 3582 case MSR_IA32_TSC: 3583 if (msr_info->host_initiated) { 3584 kvm_synchronize_tsc(vcpu, data); 3585 } else { 3586 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; 3587 adjust_tsc_offset_guest(vcpu, adj); 3588 vcpu->arch.ia32_tsc_adjust_msr += adj; 3589 } 3590 break; 3591 case MSR_IA32_XSS: 3592 if (!msr_info->host_initiated && 3593 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3594 return 1; 3595 /* 3596 * KVM supports exposing PT to the guest, but does not support 3597 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than 3598 * XSAVES/XRSTORS to save/restore PT MSRs. 3599 */ 3600 if (data & ~supported_xss) 3601 return 1; 3602 vcpu->arch.ia32_xss = data; 3603 kvm_update_cpuid_runtime(vcpu); 3604 break; 3605 case MSR_SMI_COUNT: 3606 if (!msr_info->host_initiated) 3607 return 1; 3608 vcpu->arch.smi_count = data; 3609 break; 3610 case MSR_KVM_WALL_CLOCK_NEW: 3611 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3612 return 1; 3613 3614 vcpu->kvm->arch.wall_clock = data; 3615 kvm_write_wall_clock(vcpu->kvm, data, 0); 3616 break; 3617 case MSR_KVM_WALL_CLOCK: 3618 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3619 return 1; 3620 3621 vcpu->kvm->arch.wall_clock = data; 3622 kvm_write_wall_clock(vcpu->kvm, data, 0); 3623 break; 3624 case MSR_KVM_SYSTEM_TIME_NEW: 3625 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3626 return 1; 3627 3628 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); 3629 break; 3630 case MSR_KVM_SYSTEM_TIME: 3631 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3632 return 1; 3633 3634 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); 3635 break; 3636 case MSR_KVM_ASYNC_PF_EN: 3637 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3638 return 1; 3639 3640 if (kvm_pv_enable_async_pf(vcpu, data)) 3641 return 1; 3642 break; 3643 case MSR_KVM_ASYNC_PF_INT: 3644 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3645 return 1; 3646 3647 if (kvm_pv_enable_async_pf_int(vcpu, data)) 3648 return 1; 3649 break; 3650 case MSR_KVM_ASYNC_PF_ACK: 3651 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3652 return 1; 3653 if (data & 0x1) { 3654 vcpu->arch.apf.pageready_pending = false; 3655 kvm_check_async_pf_completion(vcpu); 3656 } 3657 break; 3658 case MSR_KVM_STEAL_TIME: 3659 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3660 return 1; 3661 3662 if (unlikely(!sched_info_on())) 3663 return 1; 3664 3665 if (data & KVM_STEAL_RESERVED_MASK) 3666 return 1; 3667 3668 vcpu->arch.st.msr_val = data; 3669 3670 if (!(data & KVM_MSR_ENABLED)) 3671 break; 3672 3673 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3674 3675 break; 3676 case MSR_KVM_PV_EOI_EN: 3677 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3678 return 1; 3679 3680 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8))) 3681 return 1; 3682 break; 3683 3684 case MSR_KVM_POLL_CONTROL: 3685 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3686 return 1; 3687 3688 /* only enable bit supported */ 3689 if (data & (-1ULL << 1)) 3690 return 1; 3691 3692 vcpu->arch.msr_kvm_poll_control = data; 3693 break; 3694 3695 case MSR_IA32_MCG_CTL: 3696 case MSR_IA32_MCG_STATUS: 3697 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3698 return set_msr_mce(vcpu, msr_info); 3699 3700 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3701 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3702 pr = true; 3703 fallthrough; 3704 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3705 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3706 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3707 return kvm_pmu_set_msr(vcpu, msr_info); 3708 3709 if (pr || data != 0) 3710 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 3711 "0x%x data 0x%llx\n", msr, data); 3712 break; 3713 case MSR_K7_CLK_CTL: 3714 /* 3715 * Ignore all writes to this no longer documented MSR. 3716 * Writes are only relevant for old K7 processors, 3717 * all pre-dating SVM, but a recommended workaround from 3718 * AMD for these chips. It is possible to specify the 3719 * affected processor models on the command line, hence 3720 * the need to ignore the workaround. 3721 */ 3722 break; 3723 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3724 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3725 case HV_X64_MSR_SYNDBG_OPTIONS: 3726 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3727 case HV_X64_MSR_CRASH_CTL: 3728 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3729 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3730 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3731 case HV_X64_MSR_TSC_EMULATION_STATUS: 3732 return kvm_hv_set_msr_common(vcpu, msr, data, 3733 msr_info->host_initiated); 3734 case MSR_IA32_BBL_CR_CTL3: 3735 /* Drop writes to this legacy MSR -- see rdmsr 3736 * counterpart for further detail. 3737 */ 3738 if (report_ignored_msrs) 3739 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 3740 msr, data); 3741 break; 3742 case MSR_AMD64_OSVW_ID_LENGTH: 3743 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3744 return 1; 3745 vcpu->arch.osvw.length = data; 3746 break; 3747 case MSR_AMD64_OSVW_STATUS: 3748 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3749 return 1; 3750 vcpu->arch.osvw.status = data; 3751 break; 3752 case MSR_PLATFORM_INFO: 3753 if (!msr_info->host_initiated || 3754 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 3755 cpuid_fault_enabled(vcpu))) 3756 return 1; 3757 vcpu->arch.msr_platform_info = data; 3758 break; 3759 case MSR_MISC_FEATURES_ENABLES: 3760 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 3761 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3762 !supports_cpuid_fault(vcpu))) 3763 return 1; 3764 vcpu->arch.msr_misc_features_enables = data; 3765 break; 3766 #ifdef CONFIG_X86_64 3767 case MSR_IA32_XFD: 3768 if (!msr_info->host_initiated && 3769 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 3770 return 1; 3771 3772 if (data & ~kvm_guest_supported_xfd(vcpu)) 3773 return 1; 3774 3775 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data); 3776 break; 3777 case MSR_IA32_XFD_ERR: 3778 if (!msr_info->host_initiated && 3779 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 3780 return 1; 3781 3782 if (data & ~kvm_guest_supported_xfd(vcpu)) 3783 return 1; 3784 3785 vcpu->arch.guest_fpu.xfd_err = data; 3786 break; 3787 #endif 3788 default: 3789 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3790 return kvm_pmu_set_msr(vcpu, msr_info); 3791 return KVM_MSR_RET_INVALID; 3792 } 3793 return 0; 3794 } 3795 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 3796 3797 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 3798 { 3799 u64 data; 3800 u64 mcg_cap = vcpu->arch.mcg_cap; 3801 unsigned bank_num = mcg_cap & 0xff; 3802 3803 switch (msr) { 3804 case MSR_IA32_P5_MC_ADDR: 3805 case MSR_IA32_P5_MC_TYPE: 3806 data = 0; 3807 break; 3808 case MSR_IA32_MCG_CAP: 3809 data = vcpu->arch.mcg_cap; 3810 break; 3811 case MSR_IA32_MCG_CTL: 3812 if (!(mcg_cap & MCG_CTL_P) && !host) 3813 return 1; 3814 data = vcpu->arch.mcg_ctl; 3815 break; 3816 case MSR_IA32_MCG_STATUS: 3817 data = vcpu->arch.mcg_status; 3818 break; 3819 default: 3820 if (msr >= MSR_IA32_MC0_CTL && 3821 msr < MSR_IA32_MCx_CTL(bank_num)) { 3822 u32 offset = array_index_nospec( 3823 msr - MSR_IA32_MC0_CTL, 3824 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3825 3826 data = vcpu->arch.mce_banks[offset]; 3827 break; 3828 } 3829 return 1; 3830 } 3831 *pdata = data; 3832 return 0; 3833 } 3834 3835 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3836 { 3837 switch (msr_info->index) { 3838 case MSR_IA32_PLATFORM_ID: 3839 case MSR_IA32_EBL_CR_POWERON: 3840 case MSR_IA32_LASTBRANCHFROMIP: 3841 case MSR_IA32_LASTBRANCHTOIP: 3842 case MSR_IA32_LASTINTFROMIP: 3843 case MSR_IA32_LASTINTTOIP: 3844 case MSR_AMD64_SYSCFG: 3845 case MSR_K8_TSEG_ADDR: 3846 case MSR_K8_TSEG_MASK: 3847 case MSR_VM_HSAVE_PA: 3848 case MSR_K8_INT_PENDING_MSG: 3849 case MSR_AMD64_NB_CFG: 3850 case MSR_FAM10H_MMIO_CONF_BASE: 3851 case MSR_AMD64_BU_CFG2: 3852 case MSR_IA32_PERF_CTL: 3853 case MSR_AMD64_DC_CFG: 3854 case MSR_F15H_EX_CFG: 3855 /* 3856 * Intel Sandy Bridge CPUs must support the RAPL (running average power 3857 * limit) MSRs. Just return 0, as we do not want to expose the host 3858 * data here. Do not conditionalize this on CPUID, as KVM does not do 3859 * so for existing CPU-specific MSRs. 3860 */ 3861 case MSR_RAPL_POWER_UNIT: 3862 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ 3863 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ 3864 case MSR_PKG_ENERGY_STATUS: /* Total package */ 3865 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ 3866 msr_info->data = 0; 3867 break; 3868 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3869 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3870 return kvm_pmu_get_msr(vcpu, msr_info); 3871 if (!msr_info->host_initiated) 3872 return 1; 3873 msr_info->data = 0; 3874 break; 3875 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3876 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3877 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3878 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3879 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3880 return kvm_pmu_get_msr(vcpu, msr_info); 3881 msr_info->data = 0; 3882 break; 3883 case MSR_IA32_UCODE_REV: 3884 msr_info->data = vcpu->arch.microcode_version; 3885 break; 3886 case MSR_IA32_ARCH_CAPABILITIES: 3887 if (!msr_info->host_initiated && 3888 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 3889 return 1; 3890 msr_info->data = vcpu->arch.arch_capabilities; 3891 break; 3892 case MSR_IA32_PERF_CAPABILITIES: 3893 if (!msr_info->host_initiated && 3894 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) 3895 return 1; 3896 msr_info->data = vcpu->arch.perf_capabilities; 3897 break; 3898 case MSR_IA32_POWER_CTL: 3899 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 3900 break; 3901 case MSR_IA32_TSC: { 3902 /* 3903 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset 3904 * even when not intercepted. AMD manual doesn't explicitly 3905 * state this but appears to behave the same. 3906 * 3907 * On userspace reads and writes, however, we unconditionally 3908 * return L1's TSC value to ensure backwards-compatible 3909 * behavior for migration. 3910 */ 3911 u64 offset, ratio; 3912 3913 if (msr_info->host_initiated) { 3914 offset = vcpu->arch.l1_tsc_offset; 3915 ratio = vcpu->arch.l1_tsc_scaling_ratio; 3916 } else { 3917 offset = vcpu->arch.tsc_offset; 3918 ratio = vcpu->arch.tsc_scaling_ratio; 3919 } 3920 3921 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset; 3922 break; 3923 } 3924 case MSR_MTRRcap: 3925 case 0x200 ... 0x2ff: 3926 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 3927 case 0xcd: /* fsb frequency */ 3928 msr_info->data = 3; 3929 break; 3930 /* 3931 * MSR_EBC_FREQUENCY_ID 3932 * Conservative value valid for even the basic CPU models. 3933 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 3934 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 3935 * and 266MHz for model 3, or 4. Set Core Clock 3936 * Frequency to System Bus Frequency Ratio to 1 (bits 3937 * 31:24) even though these are only valid for CPU 3938 * models > 2, however guests may end up dividing or 3939 * multiplying by zero otherwise. 3940 */ 3941 case MSR_EBC_FREQUENCY_ID: 3942 msr_info->data = 1 << 24; 3943 break; 3944 case MSR_IA32_APICBASE: 3945 msr_info->data = kvm_get_apic_base(vcpu); 3946 break; 3947 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3948 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 3949 case MSR_IA32_TSC_DEADLINE: 3950 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 3951 break; 3952 case MSR_IA32_TSC_ADJUST: 3953 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 3954 break; 3955 case MSR_IA32_MISC_ENABLE: 3956 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 3957 break; 3958 case MSR_IA32_SMBASE: 3959 if (!msr_info->host_initiated) 3960 return 1; 3961 msr_info->data = vcpu->arch.smbase; 3962 break; 3963 case MSR_SMI_COUNT: 3964 msr_info->data = vcpu->arch.smi_count; 3965 break; 3966 case MSR_IA32_PERF_STATUS: 3967 /* TSC increment by tick */ 3968 msr_info->data = 1000ULL; 3969 /* CPU multiplier */ 3970 msr_info->data |= (((uint64_t)4ULL) << 40); 3971 break; 3972 case MSR_EFER: 3973 msr_info->data = vcpu->arch.efer; 3974 break; 3975 case MSR_KVM_WALL_CLOCK: 3976 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3977 return 1; 3978 3979 msr_info->data = vcpu->kvm->arch.wall_clock; 3980 break; 3981 case MSR_KVM_WALL_CLOCK_NEW: 3982 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3983 return 1; 3984 3985 msr_info->data = vcpu->kvm->arch.wall_clock; 3986 break; 3987 case MSR_KVM_SYSTEM_TIME: 3988 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3989 return 1; 3990 3991 msr_info->data = vcpu->arch.time; 3992 break; 3993 case MSR_KVM_SYSTEM_TIME_NEW: 3994 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3995 return 1; 3996 3997 msr_info->data = vcpu->arch.time; 3998 break; 3999 case MSR_KVM_ASYNC_PF_EN: 4000 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 4001 return 1; 4002 4003 msr_info->data = vcpu->arch.apf.msr_en_val; 4004 break; 4005 case MSR_KVM_ASYNC_PF_INT: 4006 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 4007 return 1; 4008 4009 msr_info->data = vcpu->arch.apf.msr_int_val; 4010 break; 4011 case MSR_KVM_ASYNC_PF_ACK: 4012 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 4013 return 1; 4014 4015 msr_info->data = 0; 4016 break; 4017 case MSR_KVM_STEAL_TIME: 4018 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 4019 return 1; 4020 4021 msr_info->data = vcpu->arch.st.msr_val; 4022 break; 4023 case MSR_KVM_PV_EOI_EN: 4024 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 4025 return 1; 4026 4027 msr_info->data = vcpu->arch.pv_eoi.msr_val; 4028 break; 4029 case MSR_KVM_POLL_CONTROL: 4030 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 4031 return 1; 4032 4033 msr_info->data = vcpu->arch.msr_kvm_poll_control; 4034 break; 4035 case MSR_IA32_P5_MC_ADDR: 4036 case MSR_IA32_P5_MC_TYPE: 4037 case MSR_IA32_MCG_CAP: 4038 case MSR_IA32_MCG_CTL: 4039 case MSR_IA32_MCG_STATUS: 4040 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 4041 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 4042 msr_info->host_initiated); 4043 case MSR_IA32_XSS: 4044 if (!msr_info->host_initiated && 4045 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 4046 return 1; 4047 msr_info->data = vcpu->arch.ia32_xss; 4048 break; 4049 case MSR_K7_CLK_CTL: 4050 /* 4051 * Provide expected ramp-up count for K7. All other 4052 * are set to zero, indicating minimum divisors for 4053 * every field. 4054 * 4055 * This prevents guest kernels on AMD host with CPU 4056 * type 6, model 8 and higher from exploding due to 4057 * the rdmsr failing. 4058 */ 4059 msr_info->data = 0x20000000; 4060 break; 4061 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 4062 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 4063 case HV_X64_MSR_SYNDBG_OPTIONS: 4064 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 4065 case HV_X64_MSR_CRASH_CTL: 4066 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 4067 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 4068 case HV_X64_MSR_TSC_EMULATION_CONTROL: 4069 case HV_X64_MSR_TSC_EMULATION_STATUS: 4070 return kvm_hv_get_msr_common(vcpu, 4071 msr_info->index, &msr_info->data, 4072 msr_info->host_initiated); 4073 case MSR_IA32_BBL_CR_CTL3: 4074 /* This legacy MSR exists but isn't fully documented in current 4075 * silicon. It is however accessed by winxp in very narrow 4076 * scenarios where it sets bit #19, itself documented as 4077 * a "reserved" bit. Best effort attempt to source coherent 4078 * read data here should the balance of the register be 4079 * interpreted by the guest: 4080 * 4081 * L2 cache control register 3: 64GB range, 256KB size, 4082 * enabled, latency 0x1, configured 4083 */ 4084 msr_info->data = 0xbe702111; 4085 break; 4086 case MSR_AMD64_OSVW_ID_LENGTH: 4087 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 4088 return 1; 4089 msr_info->data = vcpu->arch.osvw.length; 4090 break; 4091 case MSR_AMD64_OSVW_STATUS: 4092 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 4093 return 1; 4094 msr_info->data = vcpu->arch.osvw.status; 4095 break; 4096 case MSR_PLATFORM_INFO: 4097 if (!msr_info->host_initiated && 4098 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 4099 return 1; 4100 msr_info->data = vcpu->arch.msr_platform_info; 4101 break; 4102 case MSR_MISC_FEATURES_ENABLES: 4103 msr_info->data = vcpu->arch.msr_misc_features_enables; 4104 break; 4105 case MSR_K7_HWCR: 4106 msr_info->data = vcpu->arch.msr_hwcr; 4107 break; 4108 #ifdef CONFIG_X86_64 4109 case MSR_IA32_XFD: 4110 if (!msr_info->host_initiated && 4111 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 4112 return 1; 4113 4114 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd; 4115 break; 4116 case MSR_IA32_XFD_ERR: 4117 if (!msr_info->host_initiated && 4118 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 4119 return 1; 4120 4121 msr_info->data = vcpu->arch.guest_fpu.xfd_err; 4122 break; 4123 #endif 4124 default: 4125 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 4126 return kvm_pmu_get_msr(vcpu, msr_info); 4127 return KVM_MSR_RET_INVALID; 4128 } 4129 return 0; 4130 } 4131 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 4132 4133 /* 4134 * Read or write a bunch of msrs. All parameters are kernel addresses. 4135 * 4136 * @return number of msrs set successfully. 4137 */ 4138 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 4139 struct kvm_msr_entry *entries, 4140 int (*do_msr)(struct kvm_vcpu *vcpu, 4141 unsigned index, u64 *data)) 4142 { 4143 int i; 4144 4145 for (i = 0; i < msrs->nmsrs; ++i) 4146 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 4147 break; 4148 4149 return i; 4150 } 4151 4152 /* 4153 * Read or write a bunch of msrs. Parameters are user addresses. 4154 * 4155 * @return number of msrs set successfully. 4156 */ 4157 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 4158 int (*do_msr)(struct kvm_vcpu *vcpu, 4159 unsigned index, u64 *data), 4160 int writeback) 4161 { 4162 struct kvm_msrs msrs; 4163 struct kvm_msr_entry *entries; 4164 int r, n; 4165 unsigned size; 4166 4167 r = -EFAULT; 4168 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 4169 goto out; 4170 4171 r = -E2BIG; 4172 if (msrs.nmsrs >= MAX_IO_MSRS) 4173 goto out; 4174 4175 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 4176 entries = memdup_user(user_msrs->entries, size); 4177 if (IS_ERR(entries)) { 4178 r = PTR_ERR(entries); 4179 goto out; 4180 } 4181 4182 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 4183 if (r < 0) 4184 goto out_free; 4185 4186 r = -EFAULT; 4187 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 4188 goto out_free; 4189 4190 r = n; 4191 4192 out_free: 4193 kfree(entries); 4194 out: 4195 return r; 4196 } 4197 4198 static inline bool kvm_can_mwait_in_guest(void) 4199 { 4200 return boot_cpu_has(X86_FEATURE_MWAIT) && 4201 !boot_cpu_has_bug(X86_BUG_MONITOR) && 4202 boot_cpu_has(X86_FEATURE_ARAT); 4203 } 4204 4205 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, 4206 struct kvm_cpuid2 __user *cpuid_arg) 4207 { 4208 struct kvm_cpuid2 cpuid; 4209 int r; 4210 4211 r = -EFAULT; 4212 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4213 return r; 4214 4215 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); 4216 if (r) 4217 return r; 4218 4219 r = -EFAULT; 4220 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4221 return r; 4222 4223 return 0; 4224 } 4225 4226 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 4227 { 4228 int r = 0; 4229 4230 switch (ext) { 4231 case KVM_CAP_IRQCHIP: 4232 case KVM_CAP_HLT: 4233 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 4234 case KVM_CAP_SET_TSS_ADDR: 4235 case KVM_CAP_EXT_CPUID: 4236 case KVM_CAP_EXT_EMUL_CPUID: 4237 case KVM_CAP_CLOCKSOURCE: 4238 case KVM_CAP_PIT: 4239 case KVM_CAP_NOP_IO_DELAY: 4240 case KVM_CAP_MP_STATE: 4241 case KVM_CAP_SYNC_MMU: 4242 case KVM_CAP_USER_NMI: 4243 case KVM_CAP_REINJECT_CONTROL: 4244 case KVM_CAP_IRQ_INJECT_STATUS: 4245 case KVM_CAP_IOEVENTFD: 4246 case KVM_CAP_IOEVENTFD_NO_LENGTH: 4247 case KVM_CAP_PIT2: 4248 case KVM_CAP_PIT_STATE2: 4249 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 4250 case KVM_CAP_VCPU_EVENTS: 4251 case KVM_CAP_HYPERV: 4252 case KVM_CAP_HYPERV_VAPIC: 4253 case KVM_CAP_HYPERV_SPIN: 4254 case KVM_CAP_HYPERV_SYNIC: 4255 case KVM_CAP_HYPERV_SYNIC2: 4256 case KVM_CAP_HYPERV_VP_INDEX: 4257 case KVM_CAP_HYPERV_EVENTFD: 4258 case KVM_CAP_HYPERV_TLBFLUSH: 4259 case KVM_CAP_HYPERV_SEND_IPI: 4260 case KVM_CAP_HYPERV_CPUID: 4261 case KVM_CAP_HYPERV_ENFORCE_CPUID: 4262 case KVM_CAP_SYS_HYPERV_CPUID: 4263 case KVM_CAP_PCI_SEGMENT: 4264 case KVM_CAP_DEBUGREGS: 4265 case KVM_CAP_X86_ROBUST_SINGLESTEP: 4266 case KVM_CAP_XSAVE: 4267 case KVM_CAP_ASYNC_PF: 4268 case KVM_CAP_ASYNC_PF_INT: 4269 case KVM_CAP_GET_TSC_KHZ: 4270 case KVM_CAP_KVMCLOCK_CTRL: 4271 case KVM_CAP_READONLY_MEM: 4272 case KVM_CAP_HYPERV_TIME: 4273 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 4274 case KVM_CAP_TSC_DEADLINE_TIMER: 4275 case KVM_CAP_DISABLE_QUIRKS: 4276 case KVM_CAP_SET_BOOT_CPU_ID: 4277 case KVM_CAP_SPLIT_IRQCHIP: 4278 case KVM_CAP_IMMEDIATE_EXIT: 4279 case KVM_CAP_PMU_EVENT_FILTER: 4280 case KVM_CAP_GET_MSR_FEATURES: 4281 case KVM_CAP_MSR_PLATFORM_INFO: 4282 case KVM_CAP_EXCEPTION_PAYLOAD: 4283 case KVM_CAP_SET_GUEST_DEBUG: 4284 case KVM_CAP_LAST_CPU: 4285 case KVM_CAP_X86_USER_SPACE_MSR: 4286 case KVM_CAP_X86_MSR_FILTER: 4287 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 4288 #ifdef CONFIG_X86_SGX_KVM 4289 case KVM_CAP_SGX_ATTRIBUTE: 4290 #endif 4291 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 4292 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: 4293 case KVM_CAP_SREGS2: 4294 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 4295 case KVM_CAP_VCPU_ATTRIBUTES: 4296 case KVM_CAP_SYS_ATTRIBUTES: 4297 case KVM_CAP_VAPIC: 4298 case KVM_CAP_ENABLE_CAP: 4299 r = 1; 4300 break; 4301 case KVM_CAP_EXIT_HYPERCALL: 4302 r = KVM_EXIT_HYPERCALL_VALID_MASK; 4303 break; 4304 case KVM_CAP_SET_GUEST_DEBUG2: 4305 return KVM_GUESTDBG_VALID_MASK; 4306 #ifdef CONFIG_KVM_XEN 4307 case KVM_CAP_XEN_HVM: 4308 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | 4309 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | 4310 KVM_XEN_HVM_CONFIG_SHARED_INFO | 4311 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL | 4312 KVM_XEN_HVM_CONFIG_EVTCHN_SEND; 4313 if (sched_info_on()) 4314 r |= KVM_XEN_HVM_CONFIG_RUNSTATE; 4315 break; 4316 #endif 4317 case KVM_CAP_SYNC_REGS: 4318 r = KVM_SYNC_X86_VALID_FIELDS; 4319 break; 4320 case KVM_CAP_ADJUST_CLOCK: 4321 r = KVM_CLOCK_VALID_FLAGS; 4322 break; 4323 case KVM_CAP_X86_DISABLE_EXITS: 4324 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | 4325 KVM_X86_DISABLE_EXITS_CSTATE; 4326 if(kvm_can_mwait_in_guest()) 4327 r |= KVM_X86_DISABLE_EXITS_MWAIT; 4328 break; 4329 case KVM_CAP_X86_SMM: 4330 /* SMBASE is usually relocated above 1M on modern chipsets, 4331 * and SMM handlers might indeed rely on 4G segment limits, 4332 * so do not report SMM to be available if real mode is 4333 * emulated via vm86 mode. Still, do not go to great lengths 4334 * to avoid userspace's usage of the feature, because it is a 4335 * fringe case that is not enabled except via specific settings 4336 * of the module parameters. 4337 */ 4338 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); 4339 break; 4340 case KVM_CAP_NR_VCPUS: 4341 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS); 4342 break; 4343 case KVM_CAP_MAX_VCPUS: 4344 r = KVM_MAX_VCPUS; 4345 break; 4346 case KVM_CAP_MAX_VCPU_ID: 4347 r = KVM_MAX_VCPU_IDS; 4348 break; 4349 case KVM_CAP_PV_MMU: /* obsolete */ 4350 r = 0; 4351 break; 4352 case KVM_CAP_MCE: 4353 r = KVM_MAX_MCE_BANKS; 4354 break; 4355 case KVM_CAP_XCRS: 4356 r = boot_cpu_has(X86_FEATURE_XSAVE); 4357 break; 4358 case KVM_CAP_TSC_CONTROL: 4359 case KVM_CAP_VM_TSC_CONTROL: 4360 r = kvm_has_tsc_control; 4361 break; 4362 case KVM_CAP_X2APIC_API: 4363 r = KVM_X2APIC_API_VALID_FLAGS; 4364 break; 4365 case KVM_CAP_NESTED_STATE: 4366 r = kvm_x86_ops.nested_ops->get_state ? 4367 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; 4368 break; 4369 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4370 r = kvm_x86_ops.enable_direct_tlbflush != NULL; 4371 break; 4372 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4373 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; 4374 break; 4375 case KVM_CAP_SMALLER_MAXPHYADDR: 4376 r = (int) allow_smaller_maxphyaddr; 4377 break; 4378 case KVM_CAP_STEAL_TIME: 4379 r = sched_info_on(); 4380 break; 4381 case KVM_CAP_X86_BUS_LOCK_EXIT: 4382 if (kvm_has_bus_lock_exit) 4383 r = KVM_BUS_LOCK_DETECTION_OFF | 4384 KVM_BUS_LOCK_DETECTION_EXIT; 4385 else 4386 r = 0; 4387 break; 4388 case KVM_CAP_XSAVE2: { 4389 u64 guest_perm = xstate_get_guest_group_perm(); 4390 4391 r = xstate_required_size(supported_xcr0 & guest_perm, false); 4392 if (r < sizeof(struct kvm_xsave)) 4393 r = sizeof(struct kvm_xsave); 4394 break; 4395 case KVM_CAP_PMU_CAPABILITY: 4396 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0; 4397 break; 4398 } 4399 case KVM_CAP_DISABLE_QUIRKS2: 4400 r = KVM_X86_VALID_QUIRKS; 4401 break; 4402 default: 4403 break; 4404 } 4405 return r; 4406 } 4407 4408 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr) 4409 { 4410 void __user *uaddr = (void __user*)(unsigned long)attr->addr; 4411 4412 if ((u64)(unsigned long)uaddr != attr->addr) 4413 return ERR_PTR_USR(-EFAULT); 4414 return uaddr; 4415 } 4416 4417 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr) 4418 { 4419 u64 __user *uaddr = kvm_get_attr_addr(attr); 4420 4421 if (attr->group) 4422 return -ENXIO; 4423 4424 if (IS_ERR(uaddr)) 4425 return PTR_ERR(uaddr); 4426 4427 switch (attr->attr) { 4428 case KVM_X86_XCOMP_GUEST_SUPP: 4429 if (put_user(supported_xcr0, uaddr)) 4430 return -EFAULT; 4431 return 0; 4432 default: 4433 return -ENXIO; 4434 break; 4435 } 4436 } 4437 4438 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr) 4439 { 4440 if (attr->group) 4441 return -ENXIO; 4442 4443 switch (attr->attr) { 4444 case KVM_X86_XCOMP_GUEST_SUPP: 4445 return 0; 4446 default: 4447 return -ENXIO; 4448 } 4449 } 4450 4451 long kvm_arch_dev_ioctl(struct file *filp, 4452 unsigned int ioctl, unsigned long arg) 4453 { 4454 void __user *argp = (void __user *)arg; 4455 long r; 4456 4457 switch (ioctl) { 4458 case KVM_GET_MSR_INDEX_LIST: { 4459 struct kvm_msr_list __user *user_msr_list = argp; 4460 struct kvm_msr_list msr_list; 4461 unsigned n; 4462 4463 r = -EFAULT; 4464 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4465 goto out; 4466 n = msr_list.nmsrs; 4467 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 4468 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4469 goto out; 4470 r = -E2BIG; 4471 if (n < msr_list.nmsrs) 4472 goto out; 4473 r = -EFAULT; 4474 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 4475 num_msrs_to_save * sizeof(u32))) 4476 goto out; 4477 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 4478 &emulated_msrs, 4479 num_emulated_msrs * sizeof(u32))) 4480 goto out; 4481 r = 0; 4482 break; 4483 } 4484 case KVM_GET_SUPPORTED_CPUID: 4485 case KVM_GET_EMULATED_CPUID: { 4486 struct kvm_cpuid2 __user *cpuid_arg = argp; 4487 struct kvm_cpuid2 cpuid; 4488 4489 r = -EFAULT; 4490 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4491 goto out; 4492 4493 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 4494 ioctl); 4495 if (r) 4496 goto out; 4497 4498 r = -EFAULT; 4499 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4500 goto out; 4501 r = 0; 4502 break; 4503 } 4504 case KVM_X86_GET_MCE_CAP_SUPPORTED: 4505 r = -EFAULT; 4506 if (copy_to_user(argp, &kvm_mce_cap_supported, 4507 sizeof(kvm_mce_cap_supported))) 4508 goto out; 4509 r = 0; 4510 break; 4511 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 4512 struct kvm_msr_list __user *user_msr_list = argp; 4513 struct kvm_msr_list msr_list; 4514 unsigned int n; 4515 4516 r = -EFAULT; 4517 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4518 goto out; 4519 n = msr_list.nmsrs; 4520 msr_list.nmsrs = num_msr_based_features; 4521 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4522 goto out; 4523 r = -E2BIG; 4524 if (n < msr_list.nmsrs) 4525 goto out; 4526 r = -EFAULT; 4527 if (copy_to_user(user_msr_list->indices, &msr_based_features, 4528 num_msr_based_features * sizeof(u32))) 4529 goto out; 4530 r = 0; 4531 break; 4532 } 4533 case KVM_GET_MSRS: 4534 r = msr_io(NULL, argp, do_get_msr_feature, 1); 4535 break; 4536 case KVM_GET_SUPPORTED_HV_CPUID: 4537 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); 4538 break; 4539 case KVM_GET_DEVICE_ATTR: { 4540 struct kvm_device_attr attr; 4541 r = -EFAULT; 4542 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) 4543 break; 4544 r = kvm_x86_dev_get_attr(&attr); 4545 break; 4546 } 4547 case KVM_HAS_DEVICE_ATTR: { 4548 struct kvm_device_attr attr; 4549 r = -EFAULT; 4550 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) 4551 break; 4552 r = kvm_x86_dev_has_attr(&attr); 4553 break; 4554 } 4555 default: 4556 r = -EINVAL; 4557 break; 4558 } 4559 out: 4560 return r; 4561 } 4562 4563 static void wbinvd_ipi(void *garbage) 4564 { 4565 wbinvd(); 4566 } 4567 4568 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 4569 { 4570 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 4571 } 4572 4573 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 4574 { 4575 /* Address WBINVD may be executed by guest */ 4576 if (need_emulate_wbinvd(vcpu)) { 4577 if (static_call(kvm_x86_has_wbinvd_exit)()) 4578 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4579 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 4580 smp_call_function_single(vcpu->cpu, 4581 wbinvd_ipi, NULL, 1); 4582 } 4583 4584 static_call(kvm_x86_vcpu_load)(vcpu, cpu); 4585 4586 /* Save host pkru register if supported */ 4587 vcpu->arch.host_pkru = read_pkru(); 4588 4589 /* Apply any externally detected TSC adjustments (due to suspend) */ 4590 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 4591 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 4592 vcpu->arch.tsc_offset_adjustment = 0; 4593 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4594 } 4595 4596 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 4597 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 4598 rdtsc() - vcpu->arch.last_host_tsc; 4599 if (tsc_delta < 0) 4600 mark_tsc_unstable("KVM discovered backwards TSC"); 4601 4602 if (kvm_check_tsc_unstable()) { 4603 u64 offset = kvm_compute_l1_tsc_offset(vcpu, 4604 vcpu->arch.last_guest_tsc); 4605 kvm_vcpu_write_tsc_offset(vcpu, offset); 4606 vcpu->arch.tsc_catchup = 1; 4607 } 4608 4609 if (kvm_lapic_hv_timer_in_use(vcpu)) 4610 kvm_lapic_restart_hv_timer(vcpu); 4611 4612 /* 4613 * On a host with synchronized TSC, there is no need to update 4614 * kvmclock on vcpu->cpu migration 4615 */ 4616 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 4617 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 4618 if (vcpu->cpu != cpu) 4619 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 4620 vcpu->cpu = cpu; 4621 } 4622 4623 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 4624 } 4625 4626 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 4627 { 4628 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; 4629 struct kvm_steal_time __user *st; 4630 struct kvm_memslots *slots; 4631 static const u8 preempted = KVM_VCPU_PREEMPTED; 4632 4633 /* 4634 * The vCPU can be marked preempted if and only if the VM-Exit was on 4635 * an instruction boundary and will not trigger guest emulation of any 4636 * kind (see vcpu_run). Vendor specific code controls (conservatively) 4637 * when this is true, for example allowing the vCPU to be marked 4638 * preempted if and only if the VM-Exit was due to a host interrupt. 4639 */ 4640 if (!vcpu->arch.at_instruction_boundary) { 4641 vcpu->stat.preemption_other++; 4642 return; 4643 } 4644 4645 vcpu->stat.preemption_reported++; 4646 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 4647 return; 4648 4649 if (vcpu->arch.st.preempted) 4650 return; 4651 4652 /* This happens on process exit */ 4653 if (unlikely(current->mm != vcpu->kvm->mm)) 4654 return; 4655 4656 slots = kvm_memslots(vcpu->kvm); 4657 4658 if (unlikely(slots->generation != ghc->generation || 4659 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) 4660 return; 4661 4662 st = (struct kvm_steal_time __user *)ghc->hva; 4663 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted)); 4664 4665 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted))) 4666 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 4667 4668 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 4669 } 4670 4671 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 4672 { 4673 int idx; 4674 4675 if (vcpu->preempted) { 4676 if (!vcpu->arch.guest_state_protected) 4677 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); 4678 4679 /* 4680 * Take the srcu lock as memslots will be accessed to check the gfn 4681 * cache generation against the memslots generation. 4682 */ 4683 idx = srcu_read_lock(&vcpu->kvm->srcu); 4684 if (kvm_xen_msr_enabled(vcpu->kvm)) 4685 kvm_xen_runstate_set_preempted(vcpu); 4686 else 4687 kvm_steal_time_set_preempted(vcpu); 4688 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4689 } 4690 4691 static_call(kvm_x86_vcpu_put)(vcpu); 4692 vcpu->arch.last_host_tsc = rdtsc(); 4693 } 4694 4695 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 4696 struct kvm_lapic_state *s) 4697 { 4698 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 4699 4700 return kvm_apic_get_state(vcpu, s); 4701 } 4702 4703 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 4704 struct kvm_lapic_state *s) 4705 { 4706 int r; 4707 4708 r = kvm_apic_set_state(vcpu, s); 4709 if (r) 4710 return r; 4711 update_cr8_intercept(vcpu); 4712 4713 return 0; 4714 } 4715 4716 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 4717 { 4718 /* 4719 * We can accept userspace's request for interrupt injection 4720 * as long as we have a place to store the interrupt number. 4721 * The actual injection will happen when the CPU is able to 4722 * deliver the interrupt. 4723 */ 4724 if (kvm_cpu_has_extint(vcpu)) 4725 return false; 4726 4727 /* Acknowledging ExtINT does not happen if LINT0 is masked. */ 4728 return (!lapic_in_kernel(vcpu) || 4729 kvm_apic_accept_pic_intr(vcpu)); 4730 } 4731 4732 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 4733 { 4734 /* 4735 * Do not cause an interrupt window exit if an exception 4736 * is pending or an event needs reinjection; userspace 4737 * might want to inject the interrupt manually using KVM_SET_REGS 4738 * or KVM_SET_SREGS. For that to work, we must be at an 4739 * instruction boundary and with no events half-injected. 4740 */ 4741 return (kvm_arch_interrupt_allowed(vcpu) && 4742 kvm_cpu_accept_dm_intr(vcpu) && 4743 !kvm_event_needs_reinjection(vcpu) && 4744 !vcpu->arch.exception.pending); 4745 } 4746 4747 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 4748 struct kvm_interrupt *irq) 4749 { 4750 if (irq->irq >= KVM_NR_INTERRUPTS) 4751 return -EINVAL; 4752 4753 if (!irqchip_in_kernel(vcpu->kvm)) { 4754 kvm_queue_interrupt(vcpu, irq->irq, false); 4755 kvm_make_request(KVM_REQ_EVENT, vcpu); 4756 return 0; 4757 } 4758 4759 /* 4760 * With in-kernel LAPIC, we only use this to inject EXTINT, so 4761 * fail for in-kernel 8259. 4762 */ 4763 if (pic_in_kernel(vcpu->kvm)) 4764 return -ENXIO; 4765 4766 if (vcpu->arch.pending_external_vector != -1) 4767 return -EEXIST; 4768 4769 vcpu->arch.pending_external_vector = irq->irq; 4770 kvm_make_request(KVM_REQ_EVENT, vcpu); 4771 return 0; 4772 } 4773 4774 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 4775 { 4776 kvm_inject_nmi(vcpu); 4777 4778 return 0; 4779 } 4780 4781 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 4782 { 4783 kvm_make_request(KVM_REQ_SMI, vcpu); 4784 4785 return 0; 4786 } 4787 4788 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 4789 struct kvm_tpr_access_ctl *tac) 4790 { 4791 if (tac->flags) 4792 return -EINVAL; 4793 vcpu->arch.tpr_access_reporting = !!tac->enabled; 4794 return 0; 4795 } 4796 4797 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 4798 u64 mcg_cap) 4799 { 4800 int r; 4801 unsigned bank_num = mcg_cap & 0xff, bank; 4802 4803 r = -EINVAL; 4804 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) 4805 goto out; 4806 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 4807 goto out; 4808 r = 0; 4809 vcpu->arch.mcg_cap = mcg_cap; 4810 /* Init IA32_MCG_CTL to all 1s */ 4811 if (mcg_cap & MCG_CTL_P) 4812 vcpu->arch.mcg_ctl = ~(u64)0; 4813 /* Init IA32_MCi_CTL to all 1s */ 4814 for (bank = 0; bank < bank_num; bank++) 4815 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 4816 4817 static_call(kvm_x86_setup_mce)(vcpu); 4818 out: 4819 return r; 4820 } 4821 4822 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 4823 struct kvm_x86_mce *mce) 4824 { 4825 u64 mcg_cap = vcpu->arch.mcg_cap; 4826 unsigned bank_num = mcg_cap & 0xff; 4827 u64 *banks = vcpu->arch.mce_banks; 4828 4829 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 4830 return -EINVAL; 4831 /* 4832 * if IA32_MCG_CTL is not all 1s, the uncorrected error 4833 * reporting is disabled 4834 */ 4835 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 4836 vcpu->arch.mcg_ctl != ~(u64)0) 4837 return 0; 4838 banks += 4 * mce->bank; 4839 /* 4840 * if IA32_MCi_CTL is not all 1s, the uncorrected error 4841 * reporting is disabled for the bank 4842 */ 4843 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 4844 return 0; 4845 if (mce->status & MCI_STATUS_UC) { 4846 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 4847 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 4848 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 4849 return 0; 4850 } 4851 if (banks[1] & MCI_STATUS_VAL) 4852 mce->status |= MCI_STATUS_OVER; 4853 banks[2] = mce->addr; 4854 banks[3] = mce->misc; 4855 vcpu->arch.mcg_status = mce->mcg_status; 4856 banks[1] = mce->status; 4857 kvm_queue_exception(vcpu, MC_VECTOR); 4858 } else if (!(banks[1] & MCI_STATUS_VAL) 4859 || !(banks[1] & MCI_STATUS_UC)) { 4860 if (banks[1] & MCI_STATUS_VAL) 4861 mce->status |= MCI_STATUS_OVER; 4862 banks[2] = mce->addr; 4863 banks[3] = mce->misc; 4864 banks[1] = mce->status; 4865 } else 4866 banks[1] |= MCI_STATUS_OVER; 4867 return 0; 4868 } 4869 4870 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 4871 struct kvm_vcpu_events *events) 4872 { 4873 process_nmi(vcpu); 4874 4875 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 4876 process_smi(vcpu); 4877 4878 /* 4879 * In guest mode, payload delivery should be deferred, 4880 * so that the L1 hypervisor can intercept #PF before 4881 * CR2 is modified (or intercept #DB before DR6 is 4882 * modified under nVMX). Unless the per-VM capability, 4883 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of 4884 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we 4885 * opportunistically defer the exception payload, deliver it if the 4886 * capability hasn't been requested before processing a 4887 * KVM_GET_VCPU_EVENTS. 4888 */ 4889 if (!vcpu->kvm->arch.exception_payload_enabled && 4890 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) 4891 kvm_deliver_exception_payload(vcpu); 4892 4893 /* 4894 * The API doesn't provide the instruction length for software 4895 * exceptions, so don't report them. As long as the guest RIP 4896 * isn't advanced, we should expect to encounter the exception 4897 * again. 4898 */ 4899 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 4900 events->exception.injected = 0; 4901 events->exception.pending = 0; 4902 } else { 4903 events->exception.injected = vcpu->arch.exception.injected; 4904 events->exception.pending = vcpu->arch.exception.pending; 4905 /* 4906 * For ABI compatibility, deliberately conflate 4907 * pending and injected exceptions when 4908 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 4909 */ 4910 if (!vcpu->kvm->arch.exception_payload_enabled) 4911 events->exception.injected |= 4912 vcpu->arch.exception.pending; 4913 } 4914 events->exception.nr = vcpu->arch.exception.nr; 4915 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 4916 events->exception.error_code = vcpu->arch.exception.error_code; 4917 events->exception_has_payload = vcpu->arch.exception.has_payload; 4918 events->exception_payload = vcpu->arch.exception.payload; 4919 4920 events->interrupt.injected = 4921 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 4922 events->interrupt.nr = vcpu->arch.interrupt.nr; 4923 events->interrupt.soft = 0; 4924 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 4925 4926 events->nmi.injected = vcpu->arch.nmi_injected; 4927 events->nmi.pending = vcpu->arch.nmi_pending != 0; 4928 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); 4929 events->nmi.pad = 0; 4930 4931 events->sipi_vector = 0; /* never valid when reporting to user space */ 4932 4933 events->smi.smm = is_smm(vcpu); 4934 events->smi.pending = vcpu->arch.smi_pending; 4935 events->smi.smm_inside_nmi = 4936 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 4937 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 4938 4939 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 4940 | KVM_VCPUEVENT_VALID_SHADOW 4941 | KVM_VCPUEVENT_VALID_SMM); 4942 if (vcpu->kvm->arch.exception_payload_enabled) 4943 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 4944 4945 memset(&events->reserved, 0, sizeof(events->reserved)); 4946 } 4947 4948 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm); 4949 4950 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 4951 struct kvm_vcpu_events *events) 4952 { 4953 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 4954 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 4955 | KVM_VCPUEVENT_VALID_SHADOW 4956 | KVM_VCPUEVENT_VALID_SMM 4957 | KVM_VCPUEVENT_VALID_PAYLOAD)) 4958 return -EINVAL; 4959 4960 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 4961 if (!vcpu->kvm->arch.exception_payload_enabled) 4962 return -EINVAL; 4963 if (events->exception.pending) 4964 events->exception.injected = 0; 4965 else 4966 events->exception_has_payload = 0; 4967 } else { 4968 events->exception.pending = 0; 4969 events->exception_has_payload = 0; 4970 } 4971 4972 if ((events->exception.injected || events->exception.pending) && 4973 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 4974 return -EINVAL; 4975 4976 /* INITs are latched while in SMM */ 4977 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 4978 (events->smi.smm || events->smi.pending) && 4979 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 4980 return -EINVAL; 4981 4982 process_nmi(vcpu); 4983 vcpu->arch.exception.injected = events->exception.injected; 4984 vcpu->arch.exception.pending = events->exception.pending; 4985 vcpu->arch.exception.nr = events->exception.nr; 4986 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 4987 vcpu->arch.exception.error_code = events->exception.error_code; 4988 vcpu->arch.exception.has_payload = events->exception_has_payload; 4989 vcpu->arch.exception.payload = events->exception_payload; 4990 4991 vcpu->arch.interrupt.injected = events->interrupt.injected; 4992 vcpu->arch.interrupt.nr = events->interrupt.nr; 4993 vcpu->arch.interrupt.soft = events->interrupt.soft; 4994 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 4995 static_call(kvm_x86_set_interrupt_shadow)(vcpu, 4996 events->interrupt.shadow); 4997 4998 vcpu->arch.nmi_injected = events->nmi.injected; 4999 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 5000 vcpu->arch.nmi_pending = events->nmi.pending; 5001 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); 5002 5003 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 5004 lapic_in_kernel(vcpu)) 5005 vcpu->arch.apic->sipi_vector = events->sipi_vector; 5006 5007 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 5008 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { 5009 kvm_x86_ops.nested_ops->leave_nested(vcpu); 5010 kvm_smm_changed(vcpu, events->smi.smm); 5011 } 5012 5013 vcpu->arch.smi_pending = events->smi.pending; 5014 5015 if (events->smi.smm) { 5016 if (events->smi.smm_inside_nmi) 5017 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 5018 else 5019 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 5020 } 5021 5022 if (lapic_in_kernel(vcpu)) { 5023 if (events->smi.latched_init) 5024 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 5025 else 5026 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 5027 } 5028 } 5029 5030 kvm_make_request(KVM_REQ_EVENT, vcpu); 5031 5032 return 0; 5033 } 5034 5035 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 5036 struct kvm_debugregs *dbgregs) 5037 { 5038 unsigned long val; 5039 5040 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 5041 kvm_get_dr(vcpu, 6, &val); 5042 dbgregs->dr6 = val; 5043 dbgregs->dr7 = vcpu->arch.dr7; 5044 dbgregs->flags = 0; 5045 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 5046 } 5047 5048 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 5049 struct kvm_debugregs *dbgregs) 5050 { 5051 if (dbgregs->flags) 5052 return -EINVAL; 5053 5054 if (!kvm_dr6_valid(dbgregs->dr6)) 5055 return -EINVAL; 5056 if (!kvm_dr7_valid(dbgregs->dr7)) 5057 return -EINVAL; 5058 5059 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 5060 kvm_update_dr0123(vcpu); 5061 vcpu->arch.dr6 = dbgregs->dr6; 5062 vcpu->arch.dr7 = dbgregs->dr7; 5063 kvm_update_dr7(vcpu); 5064 5065 return 0; 5066 } 5067 5068 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 5069 struct kvm_xsave *guest_xsave) 5070 { 5071 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 5072 return; 5073 5074 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, 5075 guest_xsave->region, 5076 sizeof(guest_xsave->region), 5077 vcpu->arch.pkru); 5078 } 5079 5080 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu, 5081 u8 *state, unsigned int size) 5082 { 5083 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 5084 return; 5085 5086 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, 5087 state, size, vcpu->arch.pkru); 5088 } 5089 5090 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 5091 struct kvm_xsave *guest_xsave) 5092 { 5093 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 5094 return 0; 5095 5096 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu, 5097 guest_xsave->region, 5098 supported_xcr0, &vcpu->arch.pkru); 5099 } 5100 5101 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 5102 struct kvm_xcrs *guest_xcrs) 5103 { 5104 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 5105 guest_xcrs->nr_xcrs = 0; 5106 return; 5107 } 5108 5109 guest_xcrs->nr_xcrs = 1; 5110 guest_xcrs->flags = 0; 5111 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 5112 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 5113 } 5114 5115 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 5116 struct kvm_xcrs *guest_xcrs) 5117 { 5118 int i, r = 0; 5119 5120 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 5121 return -EINVAL; 5122 5123 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 5124 return -EINVAL; 5125 5126 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 5127 /* Only support XCR0 currently */ 5128 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 5129 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 5130 guest_xcrs->xcrs[i].value); 5131 break; 5132 } 5133 if (r) 5134 r = -EINVAL; 5135 return r; 5136 } 5137 5138 /* 5139 * kvm_set_guest_paused() indicates to the guest kernel that it has been 5140 * stopped by the hypervisor. This function will be called from the host only. 5141 * EINVAL is returned when the host attempts to set the flag for a guest that 5142 * does not support pv clocks. 5143 */ 5144 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 5145 { 5146 if (!vcpu->arch.pv_time.active) 5147 return -EINVAL; 5148 vcpu->arch.pvclock_set_guest_stopped_request = true; 5149 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5150 return 0; 5151 } 5152 5153 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu, 5154 struct kvm_device_attr *attr) 5155 { 5156 int r; 5157 5158 switch (attr->attr) { 5159 case KVM_VCPU_TSC_OFFSET: 5160 r = 0; 5161 break; 5162 default: 5163 r = -ENXIO; 5164 } 5165 5166 return r; 5167 } 5168 5169 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu, 5170 struct kvm_device_attr *attr) 5171 { 5172 u64 __user *uaddr = kvm_get_attr_addr(attr); 5173 int r; 5174 5175 if (IS_ERR(uaddr)) 5176 return PTR_ERR(uaddr); 5177 5178 switch (attr->attr) { 5179 case KVM_VCPU_TSC_OFFSET: 5180 r = -EFAULT; 5181 if (put_user(vcpu->arch.l1_tsc_offset, uaddr)) 5182 break; 5183 r = 0; 5184 break; 5185 default: 5186 r = -ENXIO; 5187 } 5188 5189 return r; 5190 } 5191 5192 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu, 5193 struct kvm_device_attr *attr) 5194 { 5195 u64 __user *uaddr = kvm_get_attr_addr(attr); 5196 struct kvm *kvm = vcpu->kvm; 5197 int r; 5198 5199 if (IS_ERR(uaddr)) 5200 return PTR_ERR(uaddr); 5201 5202 switch (attr->attr) { 5203 case KVM_VCPU_TSC_OFFSET: { 5204 u64 offset, tsc, ns; 5205 unsigned long flags; 5206 bool matched; 5207 5208 r = -EFAULT; 5209 if (get_user(offset, uaddr)) 5210 break; 5211 5212 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 5213 5214 matched = (vcpu->arch.virtual_tsc_khz && 5215 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz && 5216 kvm->arch.last_tsc_offset == offset); 5217 5218 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset; 5219 ns = get_kvmclock_base_ns(); 5220 5221 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched); 5222 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 5223 5224 r = 0; 5225 break; 5226 } 5227 default: 5228 r = -ENXIO; 5229 } 5230 5231 return r; 5232 } 5233 5234 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu, 5235 unsigned int ioctl, 5236 void __user *argp) 5237 { 5238 struct kvm_device_attr attr; 5239 int r; 5240 5241 if (copy_from_user(&attr, argp, sizeof(attr))) 5242 return -EFAULT; 5243 5244 if (attr.group != KVM_VCPU_TSC_CTRL) 5245 return -ENXIO; 5246 5247 switch (ioctl) { 5248 case KVM_HAS_DEVICE_ATTR: 5249 r = kvm_arch_tsc_has_attr(vcpu, &attr); 5250 break; 5251 case KVM_GET_DEVICE_ATTR: 5252 r = kvm_arch_tsc_get_attr(vcpu, &attr); 5253 break; 5254 case KVM_SET_DEVICE_ATTR: 5255 r = kvm_arch_tsc_set_attr(vcpu, &attr); 5256 break; 5257 } 5258 5259 return r; 5260 } 5261 5262 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 5263 struct kvm_enable_cap *cap) 5264 { 5265 int r; 5266 uint16_t vmcs_version; 5267 void __user *user_ptr; 5268 5269 if (cap->flags) 5270 return -EINVAL; 5271 5272 switch (cap->cap) { 5273 case KVM_CAP_HYPERV_SYNIC2: 5274 if (cap->args[0]) 5275 return -EINVAL; 5276 fallthrough; 5277 5278 case KVM_CAP_HYPERV_SYNIC: 5279 if (!irqchip_in_kernel(vcpu->kvm)) 5280 return -EINVAL; 5281 return kvm_hv_activate_synic(vcpu, cap->cap == 5282 KVM_CAP_HYPERV_SYNIC2); 5283 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 5284 if (!kvm_x86_ops.nested_ops->enable_evmcs) 5285 return -ENOTTY; 5286 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); 5287 if (!r) { 5288 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 5289 if (copy_to_user(user_ptr, &vmcs_version, 5290 sizeof(vmcs_version))) 5291 r = -EFAULT; 5292 } 5293 return r; 5294 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 5295 if (!kvm_x86_ops.enable_direct_tlbflush) 5296 return -ENOTTY; 5297 5298 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); 5299 5300 case KVM_CAP_HYPERV_ENFORCE_CPUID: 5301 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]); 5302 5303 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 5304 vcpu->arch.pv_cpuid.enforce = cap->args[0]; 5305 if (vcpu->arch.pv_cpuid.enforce) 5306 kvm_update_pv_runtime(vcpu); 5307 5308 return 0; 5309 default: 5310 return -EINVAL; 5311 } 5312 } 5313 5314 long kvm_arch_vcpu_ioctl(struct file *filp, 5315 unsigned int ioctl, unsigned long arg) 5316 { 5317 struct kvm_vcpu *vcpu = filp->private_data; 5318 void __user *argp = (void __user *)arg; 5319 int r; 5320 union { 5321 struct kvm_sregs2 *sregs2; 5322 struct kvm_lapic_state *lapic; 5323 struct kvm_xsave *xsave; 5324 struct kvm_xcrs *xcrs; 5325 void *buffer; 5326 } u; 5327 5328 vcpu_load(vcpu); 5329 5330 u.buffer = NULL; 5331 switch (ioctl) { 5332 case KVM_GET_LAPIC: { 5333 r = -EINVAL; 5334 if (!lapic_in_kernel(vcpu)) 5335 goto out; 5336 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 5337 GFP_KERNEL_ACCOUNT); 5338 5339 r = -ENOMEM; 5340 if (!u.lapic) 5341 goto out; 5342 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 5343 if (r) 5344 goto out; 5345 r = -EFAULT; 5346 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 5347 goto out; 5348 r = 0; 5349 break; 5350 } 5351 case KVM_SET_LAPIC: { 5352 r = -EINVAL; 5353 if (!lapic_in_kernel(vcpu)) 5354 goto out; 5355 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 5356 if (IS_ERR(u.lapic)) { 5357 r = PTR_ERR(u.lapic); 5358 goto out_nofree; 5359 } 5360 5361 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 5362 break; 5363 } 5364 case KVM_INTERRUPT: { 5365 struct kvm_interrupt irq; 5366 5367 r = -EFAULT; 5368 if (copy_from_user(&irq, argp, sizeof(irq))) 5369 goto out; 5370 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 5371 break; 5372 } 5373 case KVM_NMI: { 5374 r = kvm_vcpu_ioctl_nmi(vcpu); 5375 break; 5376 } 5377 case KVM_SMI: { 5378 r = kvm_vcpu_ioctl_smi(vcpu); 5379 break; 5380 } 5381 case KVM_SET_CPUID: { 5382 struct kvm_cpuid __user *cpuid_arg = argp; 5383 struct kvm_cpuid cpuid; 5384 5385 r = -EFAULT; 5386 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5387 goto out; 5388 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 5389 break; 5390 } 5391 case KVM_SET_CPUID2: { 5392 struct kvm_cpuid2 __user *cpuid_arg = argp; 5393 struct kvm_cpuid2 cpuid; 5394 5395 r = -EFAULT; 5396 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5397 goto out; 5398 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 5399 cpuid_arg->entries); 5400 break; 5401 } 5402 case KVM_GET_CPUID2: { 5403 struct kvm_cpuid2 __user *cpuid_arg = argp; 5404 struct kvm_cpuid2 cpuid; 5405 5406 r = -EFAULT; 5407 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5408 goto out; 5409 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 5410 cpuid_arg->entries); 5411 if (r) 5412 goto out; 5413 r = -EFAULT; 5414 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 5415 goto out; 5416 r = 0; 5417 break; 5418 } 5419 case KVM_GET_MSRS: { 5420 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5421 r = msr_io(vcpu, argp, do_get_msr, 1); 5422 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5423 break; 5424 } 5425 case KVM_SET_MSRS: { 5426 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5427 r = msr_io(vcpu, argp, do_set_msr, 0); 5428 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5429 break; 5430 } 5431 case KVM_TPR_ACCESS_REPORTING: { 5432 struct kvm_tpr_access_ctl tac; 5433 5434 r = -EFAULT; 5435 if (copy_from_user(&tac, argp, sizeof(tac))) 5436 goto out; 5437 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 5438 if (r) 5439 goto out; 5440 r = -EFAULT; 5441 if (copy_to_user(argp, &tac, sizeof(tac))) 5442 goto out; 5443 r = 0; 5444 break; 5445 }; 5446 case KVM_SET_VAPIC_ADDR: { 5447 struct kvm_vapic_addr va; 5448 int idx; 5449 5450 r = -EINVAL; 5451 if (!lapic_in_kernel(vcpu)) 5452 goto out; 5453 r = -EFAULT; 5454 if (copy_from_user(&va, argp, sizeof(va))) 5455 goto out; 5456 idx = srcu_read_lock(&vcpu->kvm->srcu); 5457 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 5458 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5459 break; 5460 } 5461 case KVM_X86_SETUP_MCE: { 5462 u64 mcg_cap; 5463 5464 r = -EFAULT; 5465 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 5466 goto out; 5467 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 5468 break; 5469 } 5470 case KVM_X86_SET_MCE: { 5471 struct kvm_x86_mce mce; 5472 5473 r = -EFAULT; 5474 if (copy_from_user(&mce, argp, sizeof(mce))) 5475 goto out; 5476 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 5477 break; 5478 } 5479 case KVM_GET_VCPU_EVENTS: { 5480 struct kvm_vcpu_events events; 5481 5482 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 5483 5484 r = -EFAULT; 5485 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 5486 break; 5487 r = 0; 5488 break; 5489 } 5490 case KVM_SET_VCPU_EVENTS: { 5491 struct kvm_vcpu_events events; 5492 5493 r = -EFAULT; 5494 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 5495 break; 5496 5497 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 5498 break; 5499 } 5500 case KVM_GET_DEBUGREGS: { 5501 struct kvm_debugregs dbgregs; 5502 5503 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 5504 5505 r = -EFAULT; 5506 if (copy_to_user(argp, &dbgregs, 5507 sizeof(struct kvm_debugregs))) 5508 break; 5509 r = 0; 5510 break; 5511 } 5512 case KVM_SET_DEBUGREGS: { 5513 struct kvm_debugregs dbgregs; 5514 5515 r = -EFAULT; 5516 if (copy_from_user(&dbgregs, argp, 5517 sizeof(struct kvm_debugregs))) 5518 break; 5519 5520 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 5521 break; 5522 } 5523 case KVM_GET_XSAVE: { 5524 r = -EINVAL; 5525 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave)) 5526 break; 5527 5528 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 5529 r = -ENOMEM; 5530 if (!u.xsave) 5531 break; 5532 5533 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 5534 5535 r = -EFAULT; 5536 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 5537 break; 5538 r = 0; 5539 break; 5540 } 5541 case KVM_SET_XSAVE: { 5542 int size = vcpu->arch.guest_fpu.uabi_size; 5543 5544 u.xsave = memdup_user(argp, size); 5545 if (IS_ERR(u.xsave)) { 5546 r = PTR_ERR(u.xsave); 5547 goto out_nofree; 5548 } 5549 5550 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 5551 break; 5552 } 5553 5554 case KVM_GET_XSAVE2: { 5555 int size = vcpu->arch.guest_fpu.uabi_size; 5556 5557 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT); 5558 r = -ENOMEM; 5559 if (!u.xsave) 5560 break; 5561 5562 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size); 5563 5564 r = -EFAULT; 5565 if (copy_to_user(argp, u.xsave, size)) 5566 break; 5567 5568 r = 0; 5569 break; 5570 } 5571 5572 case KVM_GET_XCRS: { 5573 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 5574 r = -ENOMEM; 5575 if (!u.xcrs) 5576 break; 5577 5578 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 5579 5580 r = -EFAULT; 5581 if (copy_to_user(argp, u.xcrs, 5582 sizeof(struct kvm_xcrs))) 5583 break; 5584 r = 0; 5585 break; 5586 } 5587 case KVM_SET_XCRS: { 5588 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 5589 if (IS_ERR(u.xcrs)) { 5590 r = PTR_ERR(u.xcrs); 5591 goto out_nofree; 5592 } 5593 5594 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 5595 break; 5596 } 5597 case KVM_SET_TSC_KHZ: { 5598 u32 user_tsc_khz; 5599 5600 r = -EINVAL; 5601 user_tsc_khz = (u32)arg; 5602 5603 if (kvm_has_tsc_control && 5604 user_tsc_khz >= kvm_max_guest_tsc_khz) 5605 goto out; 5606 5607 if (user_tsc_khz == 0) 5608 user_tsc_khz = tsc_khz; 5609 5610 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 5611 r = 0; 5612 5613 goto out; 5614 } 5615 case KVM_GET_TSC_KHZ: { 5616 r = vcpu->arch.virtual_tsc_khz; 5617 goto out; 5618 } 5619 case KVM_KVMCLOCK_CTRL: { 5620 r = kvm_set_guest_paused(vcpu); 5621 goto out; 5622 } 5623 case KVM_ENABLE_CAP: { 5624 struct kvm_enable_cap cap; 5625 5626 r = -EFAULT; 5627 if (copy_from_user(&cap, argp, sizeof(cap))) 5628 goto out; 5629 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 5630 break; 5631 } 5632 case KVM_GET_NESTED_STATE: { 5633 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5634 u32 user_data_size; 5635 5636 r = -EINVAL; 5637 if (!kvm_x86_ops.nested_ops->get_state) 5638 break; 5639 5640 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 5641 r = -EFAULT; 5642 if (get_user(user_data_size, &user_kvm_nested_state->size)) 5643 break; 5644 5645 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, 5646 user_data_size); 5647 if (r < 0) 5648 break; 5649 5650 if (r > user_data_size) { 5651 if (put_user(r, &user_kvm_nested_state->size)) 5652 r = -EFAULT; 5653 else 5654 r = -E2BIG; 5655 break; 5656 } 5657 5658 r = 0; 5659 break; 5660 } 5661 case KVM_SET_NESTED_STATE: { 5662 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5663 struct kvm_nested_state kvm_state; 5664 int idx; 5665 5666 r = -EINVAL; 5667 if (!kvm_x86_ops.nested_ops->set_state) 5668 break; 5669 5670 r = -EFAULT; 5671 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 5672 break; 5673 5674 r = -EINVAL; 5675 if (kvm_state.size < sizeof(kvm_state)) 5676 break; 5677 5678 if (kvm_state.flags & 5679 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 5680 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING 5681 | KVM_STATE_NESTED_GIF_SET)) 5682 break; 5683 5684 /* nested_run_pending implies guest_mode. */ 5685 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 5686 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 5687 break; 5688 5689 idx = srcu_read_lock(&vcpu->kvm->srcu); 5690 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); 5691 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5692 break; 5693 } 5694 case KVM_GET_SUPPORTED_HV_CPUID: 5695 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); 5696 break; 5697 #ifdef CONFIG_KVM_XEN 5698 case KVM_XEN_VCPU_GET_ATTR: { 5699 struct kvm_xen_vcpu_attr xva; 5700 5701 r = -EFAULT; 5702 if (copy_from_user(&xva, argp, sizeof(xva))) 5703 goto out; 5704 r = kvm_xen_vcpu_get_attr(vcpu, &xva); 5705 if (!r && copy_to_user(argp, &xva, sizeof(xva))) 5706 r = -EFAULT; 5707 break; 5708 } 5709 case KVM_XEN_VCPU_SET_ATTR: { 5710 struct kvm_xen_vcpu_attr xva; 5711 5712 r = -EFAULT; 5713 if (copy_from_user(&xva, argp, sizeof(xva))) 5714 goto out; 5715 r = kvm_xen_vcpu_set_attr(vcpu, &xva); 5716 break; 5717 } 5718 #endif 5719 case KVM_GET_SREGS2: { 5720 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL); 5721 r = -ENOMEM; 5722 if (!u.sregs2) 5723 goto out; 5724 __get_sregs2(vcpu, u.sregs2); 5725 r = -EFAULT; 5726 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2))) 5727 goto out; 5728 r = 0; 5729 break; 5730 } 5731 case KVM_SET_SREGS2: { 5732 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2)); 5733 if (IS_ERR(u.sregs2)) { 5734 r = PTR_ERR(u.sregs2); 5735 u.sregs2 = NULL; 5736 goto out; 5737 } 5738 r = __set_sregs2(vcpu, u.sregs2); 5739 break; 5740 } 5741 case KVM_HAS_DEVICE_ATTR: 5742 case KVM_GET_DEVICE_ATTR: 5743 case KVM_SET_DEVICE_ATTR: 5744 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp); 5745 break; 5746 default: 5747 r = -EINVAL; 5748 } 5749 out: 5750 kfree(u.buffer); 5751 out_nofree: 5752 vcpu_put(vcpu); 5753 return r; 5754 } 5755 5756 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 5757 { 5758 return VM_FAULT_SIGBUS; 5759 } 5760 5761 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 5762 { 5763 int ret; 5764 5765 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 5766 return -EINVAL; 5767 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); 5768 return ret; 5769 } 5770 5771 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 5772 u64 ident_addr) 5773 { 5774 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); 5775 } 5776 5777 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 5778 unsigned long kvm_nr_mmu_pages) 5779 { 5780 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 5781 return -EINVAL; 5782 5783 mutex_lock(&kvm->slots_lock); 5784 5785 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 5786 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 5787 5788 mutex_unlock(&kvm->slots_lock); 5789 return 0; 5790 } 5791 5792 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 5793 { 5794 return kvm->arch.n_max_mmu_pages; 5795 } 5796 5797 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5798 { 5799 struct kvm_pic *pic = kvm->arch.vpic; 5800 int r; 5801 5802 r = 0; 5803 switch (chip->chip_id) { 5804 case KVM_IRQCHIP_PIC_MASTER: 5805 memcpy(&chip->chip.pic, &pic->pics[0], 5806 sizeof(struct kvm_pic_state)); 5807 break; 5808 case KVM_IRQCHIP_PIC_SLAVE: 5809 memcpy(&chip->chip.pic, &pic->pics[1], 5810 sizeof(struct kvm_pic_state)); 5811 break; 5812 case KVM_IRQCHIP_IOAPIC: 5813 kvm_get_ioapic(kvm, &chip->chip.ioapic); 5814 break; 5815 default: 5816 r = -EINVAL; 5817 break; 5818 } 5819 return r; 5820 } 5821 5822 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5823 { 5824 struct kvm_pic *pic = kvm->arch.vpic; 5825 int r; 5826 5827 r = 0; 5828 switch (chip->chip_id) { 5829 case KVM_IRQCHIP_PIC_MASTER: 5830 spin_lock(&pic->lock); 5831 memcpy(&pic->pics[0], &chip->chip.pic, 5832 sizeof(struct kvm_pic_state)); 5833 spin_unlock(&pic->lock); 5834 break; 5835 case KVM_IRQCHIP_PIC_SLAVE: 5836 spin_lock(&pic->lock); 5837 memcpy(&pic->pics[1], &chip->chip.pic, 5838 sizeof(struct kvm_pic_state)); 5839 spin_unlock(&pic->lock); 5840 break; 5841 case KVM_IRQCHIP_IOAPIC: 5842 kvm_set_ioapic(kvm, &chip->chip.ioapic); 5843 break; 5844 default: 5845 r = -EINVAL; 5846 break; 5847 } 5848 kvm_pic_update_irq(pic); 5849 return r; 5850 } 5851 5852 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5853 { 5854 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 5855 5856 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 5857 5858 mutex_lock(&kps->lock); 5859 memcpy(ps, &kps->channels, sizeof(*ps)); 5860 mutex_unlock(&kps->lock); 5861 return 0; 5862 } 5863 5864 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5865 { 5866 int i; 5867 struct kvm_pit *pit = kvm->arch.vpit; 5868 5869 mutex_lock(&pit->pit_state.lock); 5870 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 5871 for (i = 0; i < 3; i++) 5872 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 5873 mutex_unlock(&pit->pit_state.lock); 5874 return 0; 5875 } 5876 5877 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5878 { 5879 mutex_lock(&kvm->arch.vpit->pit_state.lock); 5880 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 5881 sizeof(ps->channels)); 5882 ps->flags = kvm->arch.vpit->pit_state.flags; 5883 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 5884 memset(&ps->reserved, 0, sizeof(ps->reserved)); 5885 return 0; 5886 } 5887 5888 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5889 { 5890 int start = 0; 5891 int i; 5892 u32 prev_legacy, cur_legacy; 5893 struct kvm_pit *pit = kvm->arch.vpit; 5894 5895 mutex_lock(&pit->pit_state.lock); 5896 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 5897 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 5898 if (!prev_legacy && cur_legacy) 5899 start = 1; 5900 memcpy(&pit->pit_state.channels, &ps->channels, 5901 sizeof(pit->pit_state.channels)); 5902 pit->pit_state.flags = ps->flags; 5903 for (i = 0; i < 3; i++) 5904 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 5905 start && i == 0); 5906 mutex_unlock(&pit->pit_state.lock); 5907 return 0; 5908 } 5909 5910 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 5911 struct kvm_reinject_control *control) 5912 { 5913 struct kvm_pit *pit = kvm->arch.vpit; 5914 5915 /* pit->pit_state.lock was overloaded to prevent userspace from getting 5916 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 5917 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 5918 */ 5919 mutex_lock(&pit->pit_state.lock); 5920 kvm_pit_set_reinject(pit, control->pit_reinject); 5921 mutex_unlock(&pit->pit_state.lock); 5922 5923 return 0; 5924 } 5925 5926 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 5927 { 5928 5929 /* 5930 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called 5931 * before reporting dirty_bitmap to userspace. KVM flushes the buffers 5932 * on all VM-Exits, thus we only need to kick running vCPUs to force a 5933 * VM-Exit. 5934 */ 5935 struct kvm_vcpu *vcpu; 5936 unsigned long i; 5937 5938 kvm_for_each_vcpu(i, vcpu, kvm) 5939 kvm_vcpu_kick(vcpu); 5940 } 5941 5942 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 5943 bool line_status) 5944 { 5945 if (!irqchip_in_kernel(kvm)) 5946 return -ENXIO; 5947 5948 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 5949 irq_event->irq, irq_event->level, 5950 line_status); 5951 return 0; 5952 } 5953 5954 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 5955 struct kvm_enable_cap *cap) 5956 { 5957 int r; 5958 5959 if (cap->flags) 5960 return -EINVAL; 5961 5962 switch (cap->cap) { 5963 case KVM_CAP_DISABLE_QUIRKS2: 5964 r = -EINVAL; 5965 if (cap->args[0] & ~KVM_X86_VALID_QUIRKS) 5966 break; 5967 fallthrough; 5968 case KVM_CAP_DISABLE_QUIRKS: 5969 kvm->arch.disabled_quirks = cap->args[0]; 5970 r = 0; 5971 break; 5972 case KVM_CAP_SPLIT_IRQCHIP: { 5973 mutex_lock(&kvm->lock); 5974 r = -EINVAL; 5975 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 5976 goto split_irqchip_unlock; 5977 r = -EEXIST; 5978 if (irqchip_in_kernel(kvm)) 5979 goto split_irqchip_unlock; 5980 if (kvm->created_vcpus) 5981 goto split_irqchip_unlock; 5982 r = kvm_setup_empty_irq_routing(kvm); 5983 if (r) 5984 goto split_irqchip_unlock; 5985 /* Pairs with irqchip_in_kernel. */ 5986 smp_wmb(); 5987 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 5988 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 5989 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT); 5990 r = 0; 5991 split_irqchip_unlock: 5992 mutex_unlock(&kvm->lock); 5993 break; 5994 } 5995 case KVM_CAP_X2APIC_API: 5996 r = -EINVAL; 5997 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 5998 break; 5999 6000 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 6001 kvm->arch.x2apic_format = true; 6002 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 6003 kvm->arch.x2apic_broadcast_quirk_disabled = true; 6004 6005 r = 0; 6006 break; 6007 case KVM_CAP_X86_DISABLE_EXITS: 6008 r = -EINVAL; 6009 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 6010 break; 6011 6012 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 6013 kvm_can_mwait_in_guest()) 6014 kvm->arch.mwait_in_guest = true; 6015 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 6016 kvm->arch.hlt_in_guest = true; 6017 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 6018 kvm->arch.pause_in_guest = true; 6019 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) 6020 kvm->arch.cstate_in_guest = true; 6021 r = 0; 6022 break; 6023 case KVM_CAP_MSR_PLATFORM_INFO: 6024 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 6025 r = 0; 6026 break; 6027 case KVM_CAP_EXCEPTION_PAYLOAD: 6028 kvm->arch.exception_payload_enabled = cap->args[0]; 6029 r = 0; 6030 break; 6031 case KVM_CAP_X86_USER_SPACE_MSR: 6032 kvm->arch.user_space_msr_mask = cap->args[0]; 6033 r = 0; 6034 break; 6035 case KVM_CAP_X86_BUS_LOCK_EXIT: 6036 r = -EINVAL; 6037 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) 6038 break; 6039 6040 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && 6041 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) 6042 break; 6043 6044 if (kvm_has_bus_lock_exit && 6045 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) 6046 kvm->arch.bus_lock_detection_enabled = true; 6047 r = 0; 6048 break; 6049 #ifdef CONFIG_X86_SGX_KVM 6050 case KVM_CAP_SGX_ATTRIBUTE: { 6051 unsigned long allowed_attributes = 0; 6052 6053 r = sgx_set_attribute(&allowed_attributes, cap->args[0]); 6054 if (r) 6055 break; 6056 6057 /* KVM only supports the PROVISIONKEY privileged attribute. */ 6058 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && 6059 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) 6060 kvm->arch.sgx_provisioning_allowed = true; 6061 else 6062 r = -EINVAL; 6063 break; 6064 } 6065 #endif 6066 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 6067 r = -EINVAL; 6068 if (!kvm_x86_ops.vm_copy_enc_context_from) 6069 break; 6070 6071 r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]); 6072 break; 6073 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: 6074 r = -EINVAL; 6075 if (!kvm_x86_ops.vm_move_enc_context_from) 6076 break; 6077 6078 r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]); 6079 break; 6080 case KVM_CAP_EXIT_HYPERCALL: 6081 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) { 6082 r = -EINVAL; 6083 break; 6084 } 6085 kvm->arch.hypercall_exit_enabled = cap->args[0]; 6086 r = 0; 6087 break; 6088 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 6089 r = -EINVAL; 6090 if (cap->args[0] & ~1) 6091 break; 6092 kvm->arch.exit_on_emulation_error = cap->args[0]; 6093 r = 0; 6094 break; 6095 case KVM_CAP_PMU_CAPABILITY: 6096 r = -EINVAL; 6097 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK)) 6098 break; 6099 6100 mutex_lock(&kvm->lock); 6101 if (!kvm->created_vcpus) { 6102 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE); 6103 r = 0; 6104 } 6105 mutex_unlock(&kvm->lock); 6106 break; 6107 default: 6108 r = -EINVAL; 6109 break; 6110 } 6111 return r; 6112 } 6113 6114 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) 6115 { 6116 struct kvm_x86_msr_filter *msr_filter; 6117 6118 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); 6119 if (!msr_filter) 6120 return NULL; 6121 6122 msr_filter->default_allow = default_allow; 6123 return msr_filter; 6124 } 6125 6126 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) 6127 { 6128 u32 i; 6129 6130 if (!msr_filter) 6131 return; 6132 6133 for (i = 0; i < msr_filter->count; i++) 6134 kfree(msr_filter->ranges[i].bitmap); 6135 6136 kfree(msr_filter); 6137 } 6138 6139 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, 6140 struct kvm_msr_filter_range *user_range) 6141 { 6142 unsigned long *bitmap = NULL; 6143 size_t bitmap_size; 6144 6145 if (!user_range->nmsrs) 6146 return 0; 6147 6148 if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) 6149 return -EINVAL; 6150 6151 if (!user_range->flags) 6152 return -EINVAL; 6153 6154 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); 6155 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) 6156 return -EINVAL; 6157 6158 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); 6159 if (IS_ERR(bitmap)) 6160 return PTR_ERR(bitmap); 6161 6162 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { 6163 .flags = user_range->flags, 6164 .base = user_range->base, 6165 .nmsrs = user_range->nmsrs, 6166 .bitmap = bitmap, 6167 }; 6168 6169 msr_filter->count++; 6170 return 0; 6171 } 6172 6173 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) 6174 { 6175 struct kvm_msr_filter __user *user_msr_filter = argp; 6176 struct kvm_x86_msr_filter *new_filter, *old_filter; 6177 struct kvm_msr_filter filter; 6178 bool default_allow; 6179 bool empty = true; 6180 int r = 0; 6181 u32 i; 6182 6183 if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) 6184 return -EFAULT; 6185 6186 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) 6187 empty &= !filter.ranges[i].nmsrs; 6188 6189 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); 6190 if (empty && !default_allow) 6191 return -EINVAL; 6192 6193 new_filter = kvm_alloc_msr_filter(default_allow); 6194 if (!new_filter) 6195 return -ENOMEM; 6196 6197 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { 6198 r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); 6199 if (r) { 6200 kvm_free_msr_filter(new_filter); 6201 return r; 6202 } 6203 } 6204 6205 mutex_lock(&kvm->lock); 6206 6207 /* The per-VM filter is protected by kvm->lock... */ 6208 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1); 6209 6210 rcu_assign_pointer(kvm->arch.msr_filter, new_filter); 6211 synchronize_srcu(&kvm->srcu); 6212 6213 kvm_free_msr_filter(old_filter); 6214 6215 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); 6216 mutex_unlock(&kvm->lock); 6217 6218 return 0; 6219 } 6220 6221 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER 6222 static int kvm_arch_suspend_notifier(struct kvm *kvm) 6223 { 6224 struct kvm_vcpu *vcpu; 6225 unsigned long i; 6226 int ret = 0; 6227 6228 mutex_lock(&kvm->lock); 6229 kvm_for_each_vcpu(i, vcpu, kvm) { 6230 if (!vcpu->arch.pv_time.active) 6231 continue; 6232 6233 ret = kvm_set_guest_paused(vcpu); 6234 if (ret) { 6235 kvm_err("Failed to pause guest VCPU%d: %d\n", 6236 vcpu->vcpu_id, ret); 6237 break; 6238 } 6239 } 6240 mutex_unlock(&kvm->lock); 6241 6242 return ret ? NOTIFY_BAD : NOTIFY_DONE; 6243 } 6244 6245 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state) 6246 { 6247 switch (state) { 6248 case PM_HIBERNATION_PREPARE: 6249 case PM_SUSPEND_PREPARE: 6250 return kvm_arch_suspend_notifier(kvm); 6251 } 6252 6253 return NOTIFY_DONE; 6254 } 6255 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */ 6256 6257 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp) 6258 { 6259 struct kvm_clock_data data = { 0 }; 6260 6261 get_kvmclock(kvm, &data); 6262 if (copy_to_user(argp, &data, sizeof(data))) 6263 return -EFAULT; 6264 6265 return 0; 6266 } 6267 6268 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp) 6269 { 6270 struct kvm_arch *ka = &kvm->arch; 6271 struct kvm_clock_data data; 6272 u64 now_raw_ns; 6273 6274 if (copy_from_user(&data, argp, sizeof(data))) 6275 return -EFAULT; 6276 6277 /* 6278 * Only KVM_CLOCK_REALTIME is used, but allow passing the 6279 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK. 6280 */ 6281 if (data.flags & ~KVM_CLOCK_VALID_FLAGS) 6282 return -EINVAL; 6283 6284 kvm_hv_request_tsc_page_update(kvm); 6285 kvm_start_pvclock_update(kvm); 6286 pvclock_update_vm_gtod_copy(kvm); 6287 6288 /* 6289 * This pairs with kvm_guest_time_update(): when masterclock is 6290 * in use, we use master_kernel_ns + kvmclock_offset to set 6291 * unsigned 'system_time' so if we use get_kvmclock_ns() (which 6292 * is slightly ahead) here we risk going negative on unsigned 6293 * 'system_time' when 'data.clock' is very small. 6294 */ 6295 if (data.flags & KVM_CLOCK_REALTIME) { 6296 u64 now_real_ns = ktime_get_real_ns(); 6297 6298 /* 6299 * Avoid stepping the kvmclock backwards. 6300 */ 6301 if (now_real_ns > data.realtime) 6302 data.clock += now_real_ns - data.realtime; 6303 } 6304 6305 if (ka->use_master_clock) 6306 now_raw_ns = ka->master_kernel_ns; 6307 else 6308 now_raw_ns = get_kvmclock_base_ns(); 6309 ka->kvmclock_offset = data.clock - now_raw_ns; 6310 kvm_end_pvclock_update(kvm); 6311 return 0; 6312 } 6313 6314 long kvm_arch_vm_ioctl(struct file *filp, 6315 unsigned int ioctl, unsigned long arg) 6316 { 6317 struct kvm *kvm = filp->private_data; 6318 void __user *argp = (void __user *)arg; 6319 int r = -ENOTTY; 6320 /* 6321 * This union makes it completely explicit to gcc-3.x 6322 * that these two variables' stack usage should be 6323 * combined, not added together. 6324 */ 6325 union { 6326 struct kvm_pit_state ps; 6327 struct kvm_pit_state2 ps2; 6328 struct kvm_pit_config pit_config; 6329 } u; 6330 6331 switch (ioctl) { 6332 case KVM_SET_TSS_ADDR: 6333 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 6334 break; 6335 case KVM_SET_IDENTITY_MAP_ADDR: { 6336 u64 ident_addr; 6337 6338 mutex_lock(&kvm->lock); 6339 r = -EINVAL; 6340 if (kvm->created_vcpus) 6341 goto set_identity_unlock; 6342 r = -EFAULT; 6343 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 6344 goto set_identity_unlock; 6345 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 6346 set_identity_unlock: 6347 mutex_unlock(&kvm->lock); 6348 break; 6349 } 6350 case KVM_SET_NR_MMU_PAGES: 6351 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 6352 break; 6353 case KVM_GET_NR_MMU_PAGES: 6354 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 6355 break; 6356 case KVM_CREATE_IRQCHIP: { 6357 mutex_lock(&kvm->lock); 6358 6359 r = -EEXIST; 6360 if (irqchip_in_kernel(kvm)) 6361 goto create_irqchip_unlock; 6362 6363 r = -EINVAL; 6364 if (kvm->created_vcpus) 6365 goto create_irqchip_unlock; 6366 6367 r = kvm_pic_init(kvm); 6368 if (r) 6369 goto create_irqchip_unlock; 6370 6371 r = kvm_ioapic_init(kvm); 6372 if (r) { 6373 kvm_pic_destroy(kvm); 6374 goto create_irqchip_unlock; 6375 } 6376 6377 r = kvm_setup_default_irq_routing(kvm); 6378 if (r) { 6379 kvm_ioapic_destroy(kvm); 6380 kvm_pic_destroy(kvm); 6381 goto create_irqchip_unlock; 6382 } 6383 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 6384 smp_wmb(); 6385 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 6386 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT); 6387 create_irqchip_unlock: 6388 mutex_unlock(&kvm->lock); 6389 break; 6390 } 6391 case KVM_CREATE_PIT: 6392 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 6393 goto create_pit; 6394 case KVM_CREATE_PIT2: 6395 r = -EFAULT; 6396 if (copy_from_user(&u.pit_config, argp, 6397 sizeof(struct kvm_pit_config))) 6398 goto out; 6399 create_pit: 6400 mutex_lock(&kvm->lock); 6401 r = -EEXIST; 6402 if (kvm->arch.vpit) 6403 goto create_pit_unlock; 6404 r = -ENOMEM; 6405 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 6406 if (kvm->arch.vpit) 6407 r = 0; 6408 create_pit_unlock: 6409 mutex_unlock(&kvm->lock); 6410 break; 6411 case KVM_GET_IRQCHIP: { 6412 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 6413 struct kvm_irqchip *chip; 6414 6415 chip = memdup_user(argp, sizeof(*chip)); 6416 if (IS_ERR(chip)) { 6417 r = PTR_ERR(chip); 6418 goto out; 6419 } 6420 6421 r = -ENXIO; 6422 if (!irqchip_kernel(kvm)) 6423 goto get_irqchip_out; 6424 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 6425 if (r) 6426 goto get_irqchip_out; 6427 r = -EFAULT; 6428 if (copy_to_user(argp, chip, sizeof(*chip))) 6429 goto get_irqchip_out; 6430 r = 0; 6431 get_irqchip_out: 6432 kfree(chip); 6433 break; 6434 } 6435 case KVM_SET_IRQCHIP: { 6436 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 6437 struct kvm_irqchip *chip; 6438 6439 chip = memdup_user(argp, sizeof(*chip)); 6440 if (IS_ERR(chip)) { 6441 r = PTR_ERR(chip); 6442 goto out; 6443 } 6444 6445 r = -ENXIO; 6446 if (!irqchip_kernel(kvm)) 6447 goto set_irqchip_out; 6448 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 6449 set_irqchip_out: 6450 kfree(chip); 6451 break; 6452 } 6453 case KVM_GET_PIT: { 6454 r = -EFAULT; 6455 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 6456 goto out; 6457 r = -ENXIO; 6458 if (!kvm->arch.vpit) 6459 goto out; 6460 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 6461 if (r) 6462 goto out; 6463 r = -EFAULT; 6464 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 6465 goto out; 6466 r = 0; 6467 break; 6468 } 6469 case KVM_SET_PIT: { 6470 r = -EFAULT; 6471 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 6472 goto out; 6473 mutex_lock(&kvm->lock); 6474 r = -ENXIO; 6475 if (!kvm->arch.vpit) 6476 goto set_pit_out; 6477 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 6478 set_pit_out: 6479 mutex_unlock(&kvm->lock); 6480 break; 6481 } 6482 case KVM_GET_PIT2: { 6483 r = -ENXIO; 6484 if (!kvm->arch.vpit) 6485 goto out; 6486 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 6487 if (r) 6488 goto out; 6489 r = -EFAULT; 6490 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 6491 goto out; 6492 r = 0; 6493 break; 6494 } 6495 case KVM_SET_PIT2: { 6496 r = -EFAULT; 6497 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 6498 goto out; 6499 mutex_lock(&kvm->lock); 6500 r = -ENXIO; 6501 if (!kvm->arch.vpit) 6502 goto set_pit2_out; 6503 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 6504 set_pit2_out: 6505 mutex_unlock(&kvm->lock); 6506 break; 6507 } 6508 case KVM_REINJECT_CONTROL: { 6509 struct kvm_reinject_control control; 6510 r = -EFAULT; 6511 if (copy_from_user(&control, argp, sizeof(control))) 6512 goto out; 6513 r = -ENXIO; 6514 if (!kvm->arch.vpit) 6515 goto out; 6516 r = kvm_vm_ioctl_reinject(kvm, &control); 6517 break; 6518 } 6519 case KVM_SET_BOOT_CPU_ID: 6520 r = 0; 6521 mutex_lock(&kvm->lock); 6522 if (kvm->created_vcpus) 6523 r = -EBUSY; 6524 else 6525 kvm->arch.bsp_vcpu_id = arg; 6526 mutex_unlock(&kvm->lock); 6527 break; 6528 #ifdef CONFIG_KVM_XEN 6529 case KVM_XEN_HVM_CONFIG: { 6530 struct kvm_xen_hvm_config xhc; 6531 r = -EFAULT; 6532 if (copy_from_user(&xhc, argp, sizeof(xhc))) 6533 goto out; 6534 r = kvm_xen_hvm_config(kvm, &xhc); 6535 break; 6536 } 6537 case KVM_XEN_HVM_GET_ATTR: { 6538 struct kvm_xen_hvm_attr xha; 6539 6540 r = -EFAULT; 6541 if (copy_from_user(&xha, argp, sizeof(xha))) 6542 goto out; 6543 r = kvm_xen_hvm_get_attr(kvm, &xha); 6544 if (!r && copy_to_user(argp, &xha, sizeof(xha))) 6545 r = -EFAULT; 6546 break; 6547 } 6548 case KVM_XEN_HVM_SET_ATTR: { 6549 struct kvm_xen_hvm_attr xha; 6550 6551 r = -EFAULT; 6552 if (copy_from_user(&xha, argp, sizeof(xha))) 6553 goto out; 6554 r = kvm_xen_hvm_set_attr(kvm, &xha); 6555 break; 6556 } 6557 case KVM_XEN_HVM_EVTCHN_SEND: { 6558 struct kvm_irq_routing_xen_evtchn uxe; 6559 6560 r = -EFAULT; 6561 if (copy_from_user(&uxe, argp, sizeof(uxe))) 6562 goto out; 6563 r = kvm_xen_hvm_evtchn_send(kvm, &uxe); 6564 break; 6565 } 6566 #endif 6567 case KVM_SET_CLOCK: 6568 r = kvm_vm_ioctl_set_clock(kvm, argp); 6569 break; 6570 case KVM_GET_CLOCK: 6571 r = kvm_vm_ioctl_get_clock(kvm, argp); 6572 break; 6573 case KVM_SET_TSC_KHZ: { 6574 u32 user_tsc_khz; 6575 6576 r = -EINVAL; 6577 user_tsc_khz = (u32)arg; 6578 6579 if (kvm_has_tsc_control && 6580 user_tsc_khz >= kvm_max_guest_tsc_khz) 6581 goto out; 6582 6583 if (user_tsc_khz == 0) 6584 user_tsc_khz = tsc_khz; 6585 6586 WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz); 6587 r = 0; 6588 6589 goto out; 6590 } 6591 case KVM_GET_TSC_KHZ: { 6592 r = READ_ONCE(kvm->arch.default_tsc_khz); 6593 goto out; 6594 } 6595 case KVM_MEMORY_ENCRYPT_OP: { 6596 r = -ENOTTY; 6597 if (!kvm_x86_ops.mem_enc_ioctl) 6598 goto out; 6599 6600 r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp); 6601 break; 6602 } 6603 case KVM_MEMORY_ENCRYPT_REG_REGION: { 6604 struct kvm_enc_region region; 6605 6606 r = -EFAULT; 6607 if (copy_from_user(®ion, argp, sizeof(region))) 6608 goto out; 6609 6610 r = -ENOTTY; 6611 if (!kvm_x86_ops.mem_enc_register_region) 6612 goto out; 6613 6614 r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion); 6615 break; 6616 } 6617 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 6618 struct kvm_enc_region region; 6619 6620 r = -EFAULT; 6621 if (copy_from_user(®ion, argp, sizeof(region))) 6622 goto out; 6623 6624 r = -ENOTTY; 6625 if (!kvm_x86_ops.mem_enc_unregister_region) 6626 goto out; 6627 6628 r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion); 6629 break; 6630 } 6631 case KVM_HYPERV_EVENTFD: { 6632 struct kvm_hyperv_eventfd hvevfd; 6633 6634 r = -EFAULT; 6635 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 6636 goto out; 6637 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 6638 break; 6639 } 6640 case KVM_SET_PMU_EVENT_FILTER: 6641 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); 6642 break; 6643 case KVM_X86_SET_MSR_FILTER: 6644 r = kvm_vm_ioctl_set_msr_filter(kvm, argp); 6645 break; 6646 default: 6647 r = -ENOTTY; 6648 } 6649 out: 6650 return r; 6651 } 6652 6653 static void kvm_init_msr_list(void) 6654 { 6655 struct x86_pmu_capability x86_pmu; 6656 u32 dummy[2]; 6657 unsigned i; 6658 6659 BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3, 6660 "Please update the fixed PMCs in msrs_to_saved_all[]"); 6661 6662 perf_get_x86_pmu_capability(&x86_pmu); 6663 6664 num_msrs_to_save = 0; 6665 num_emulated_msrs = 0; 6666 num_msr_based_features = 0; 6667 6668 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { 6669 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) 6670 continue; 6671 6672 /* 6673 * Even MSRs that are valid in the host may not be exposed 6674 * to the guests in some cases. 6675 */ 6676 switch (msrs_to_save_all[i]) { 6677 case MSR_IA32_BNDCFGS: 6678 if (!kvm_mpx_supported()) 6679 continue; 6680 break; 6681 case MSR_TSC_AUX: 6682 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && 6683 !kvm_cpu_cap_has(X86_FEATURE_RDPID)) 6684 continue; 6685 break; 6686 case MSR_IA32_UMWAIT_CONTROL: 6687 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) 6688 continue; 6689 break; 6690 case MSR_IA32_RTIT_CTL: 6691 case MSR_IA32_RTIT_STATUS: 6692 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) 6693 continue; 6694 break; 6695 case MSR_IA32_RTIT_CR3_MATCH: 6696 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6697 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 6698 continue; 6699 break; 6700 case MSR_IA32_RTIT_OUTPUT_BASE: 6701 case MSR_IA32_RTIT_OUTPUT_MASK: 6702 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6703 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 6704 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 6705 continue; 6706 break; 6707 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 6708 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6709 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= 6710 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 6711 continue; 6712 break; 6713 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: 6714 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= 6715 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 6716 continue; 6717 break; 6718 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: 6719 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= 6720 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 6721 continue; 6722 break; 6723 case MSR_IA32_XFD: 6724 case MSR_IA32_XFD_ERR: 6725 if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) 6726 continue; 6727 break; 6728 default: 6729 break; 6730 } 6731 6732 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; 6733 } 6734 6735 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { 6736 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) 6737 continue; 6738 6739 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; 6740 } 6741 6742 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { 6743 struct kvm_msr_entry msr; 6744 6745 msr.index = msr_based_features_all[i]; 6746 if (kvm_get_msr_feature(&msr)) 6747 continue; 6748 6749 msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; 6750 } 6751 } 6752 6753 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 6754 const void *v) 6755 { 6756 int handled = 0; 6757 int n; 6758 6759 do { 6760 n = min(len, 8); 6761 if (!(lapic_in_kernel(vcpu) && 6762 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 6763 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 6764 break; 6765 handled += n; 6766 addr += n; 6767 len -= n; 6768 v += n; 6769 } while (len); 6770 6771 return handled; 6772 } 6773 6774 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 6775 { 6776 int handled = 0; 6777 int n; 6778 6779 do { 6780 n = min(len, 8); 6781 if (!(lapic_in_kernel(vcpu) && 6782 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 6783 addr, n, v)) 6784 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 6785 break; 6786 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 6787 handled += n; 6788 addr += n; 6789 len -= n; 6790 v += n; 6791 } while (len); 6792 6793 return handled; 6794 } 6795 6796 static void kvm_set_segment(struct kvm_vcpu *vcpu, 6797 struct kvm_segment *var, int seg) 6798 { 6799 static_call(kvm_x86_set_segment)(vcpu, var, seg); 6800 } 6801 6802 void kvm_get_segment(struct kvm_vcpu *vcpu, 6803 struct kvm_segment *var, int seg) 6804 { 6805 static_call(kvm_x86_get_segment)(vcpu, var, seg); 6806 } 6807 6808 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access, 6809 struct x86_exception *exception) 6810 { 6811 struct kvm_mmu *mmu = vcpu->arch.mmu; 6812 gpa_t t_gpa; 6813 6814 BUG_ON(!mmu_is_nested(vcpu)); 6815 6816 /* NPT walks are always user-walks */ 6817 access |= PFERR_USER_MASK; 6818 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception); 6819 6820 return t_gpa; 6821 } 6822 6823 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 6824 struct x86_exception *exception) 6825 { 6826 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6827 6828 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6829 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 6830 } 6831 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); 6832 6833 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 6834 struct x86_exception *exception) 6835 { 6836 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6837 6838 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6839 access |= PFERR_FETCH_MASK; 6840 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 6841 } 6842 6843 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 6844 struct x86_exception *exception) 6845 { 6846 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6847 6848 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6849 access |= PFERR_WRITE_MASK; 6850 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 6851 } 6852 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); 6853 6854 /* uses this to access any guest's mapped memory without checking CPL */ 6855 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 6856 struct x86_exception *exception) 6857 { 6858 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6859 6860 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception); 6861 } 6862 6863 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6864 struct kvm_vcpu *vcpu, u64 access, 6865 struct x86_exception *exception) 6866 { 6867 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6868 void *data = val; 6869 int r = X86EMUL_CONTINUE; 6870 6871 while (bytes) { 6872 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); 6873 unsigned offset = addr & (PAGE_SIZE-1); 6874 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 6875 int ret; 6876 6877 if (gpa == UNMAPPED_GVA) 6878 return X86EMUL_PROPAGATE_FAULT; 6879 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 6880 offset, toread); 6881 if (ret < 0) { 6882 r = X86EMUL_IO_NEEDED; 6883 goto out; 6884 } 6885 6886 bytes -= toread; 6887 data += toread; 6888 addr += toread; 6889 } 6890 out: 6891 return r; 6892 } 6893 6894 /* used for instruction fetching */ 6895 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 6896 gva_t addr, void *val, unsigned int bytes, 6897 struct x86_exception *exception) 6898 { 6899 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6900 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6901 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6902 unsigned offset; 6903 int ret; 6904 6905 /* Inline kvm_read_guest_virt_helper for speed. */ 6906 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK, 6907 exception); 6908 if (unlikely(gpa == UNMAPPED_GVA)) 6909 return X86EMUL_PROPAGATE_FAULT; 6910 6911 offset = addr & (PAGE_SIZE-1); 6912 if (WARN_ON(offset + bytes > PAGE_SIZE)) 6913 bytes = (unsigned)PAGE_SIZE - offset; 6914 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 6915 offset, bytes); 6916 if (unlikely(ret < 0)) 6917 return X86EMUL_IO_NEEDED; 6918 6919 return X86EMUL_CONTINUE; 6920 } 6921 6922 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 6923 gva_t addr, void *val, unsigned int bytes, 6924 struct x86_exception *exception) 6925 { 6926 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6927 6928 /* 6929 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 6930 * is returned, but our callers are not ready for that and they blindly 6931 * call kvm_inject_page_fault. Ensure that they at least do not leak 6932 * uninitialized kernel stack memory into cr2 and error code. 6933 */ 6934 memset(exception, 0, sizeof(*exception)); 6935 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 6936 exception); 6937 } 6938 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 6939 6940 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 6941 gva_t addr, void *val, unsigned int bytes, 6942 struct x86_exception *exception, bool system) 6943 { 6944 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6945 u64 access = 0; 6946 6947 if (system) 6948 access |= PFERR_IMPLICIT_ACCESS; 6949 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3) 6950 access |= PFERR_USER_MASK; 6951 6952 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 6953 } 6954 6955 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 6956 unsigned long addr, void *val, unsigned int bytes) 6957 { 6958 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6959 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 6960 6961 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 6962 } 6963 6964 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6965 struct kvm_vcpu *vcpu, u64 access, 6966 struct x86_exception *exception) 6967 { 6968 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6969 void *data = val; 6970 int r = X86EMUL_CONTINUE; 6971 6972 while (bytes) { 6973 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); 6974 unsigned offset = addr & (PAGE_SIZE-1); 6975 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 6976 int ret; 6977 6978 if (gpa == UNMAPPED_GVA) 6979 return X86EMUL_PROPAGATE_FAULT; 6980 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 6981 if (ret < 0) { 6982 r = X86EMUL_IO_NEEDED; 6983 goto out; 6984 } 6985 6986 bytes -= towrite; 6987 data += towrite; 6988 addr += towrite; 6989 } 6990 out: 6991 return r; 6992 } 6993 6994 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 6995 unsigned int bytes, struct x86_exception *exception, 6996 bool system) 6997 { 6998 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6999 u64 access = PFERR_WRITE_MASK; 7000 7001 if (system) 7002 access |= PFERR_IMPLICIT_ACCESS; 7003 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3) 7004 access |= PFERR_USER_MASK; 7005 7006 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 7007 access, exception); 7008 } 7009 7010 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 7011 unsigned int bytes, struct x86_exception *exception) 7012 { 7013 /* kvm_write_guest_virt_system can pull in tons of pages. */ 7014 vcpu->arch.l1tf_flush_l1d = true; 7015 7016 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 7017 PFERR_WRITE_MASK, exception); 7018 } 7019 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 7020 7021 static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type, 7022 void *insn, int insn_len) 7023 { 7024 return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type, 7025 insn, insn_len); 7026 } 7027 7028 int handle_ud(struct kvm_vcpu *vcpu) 7029 { 7030 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; 7031 int emul_type = EMULTYPE_TRAP_UD; 7032 char sig[5]; /* ud2; .ascii "kvm" */ 7033 struct x86_exception e; 7034 7035 if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0))) 7036 return 1; 7037 7038 if (force_emulation_prefix && 7039 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 7040 sig, sizeof(sig), &e) == 0 && 7041 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { 7042 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 7043 emul_type = EMULTYPE_TRAP_UD_FORCED; 7044 } 7045 7046 return kvm_emulate_instruction(vcpu, emul_type); 7047 } 7048 EXPORT_SYMBOL_GPL(handle_ud); 7049 7050 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 7051 gpa_t gpa, bool write) 7052 { 7053 /* For APIC access vmexit */ 7054 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 7055 return 1; 7056 7057 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 7058 trace_vcpu_match_mmio(gva, gpa, write, true); 7059 return 1; 7060 } 7061 7062 return 0; 7063 } 7064 7065 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 7066 gpa_t *gpa, struct x86_exception *exception, 7067 bool write) 7068 { 7069 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7070 u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) 7071 | (write ? PFERR_WRITE_MASK : 0); 7072 7073 /* 7074 * currently PKRU is only applied to ept enabled guest so 7075 * there is no pkey in EPT page table for L1 guest or EPT 7076 * shadow page table for L2 guest. 7077 */ 7078 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) || 7079 !permission_fault(vcpu, vcpu->arch.walk_mmu, 7080 vcpu->arch.mmio_access, 0, access))) { 7081 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 7082 (gva & (PAGE_SIZE - 1)); 7083 trace_vcpu_match_mmio(gva, *gpa, write, false); 7084 return 1; 7085 } 7086 7087 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 7088 7089 if (*gpa == UNMAPPED_GVA) 7090 return -1; 7091 7092 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 7093 } 7094 7095 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 7096 const void *val, int bytes) 7097 { 7098 int ret; 7099 7100 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 7101 if (ret < 0) 7102 return 0; 7103 kvm_page_track_write(vcpu, gpa, val, bytes); 7104 return 1; 7105 } 7106 7107 struct read_write_emulator_ops { 7108 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 7109 int bytes); 7110 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 7111 void *val, int bytes); 7112 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 7113 int bytes, void *val); 7114 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 7115 void *val, int bytes); 7116 bool write; 7117 }; 7118 7119 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 7120 { 7121 if (vcpu->mmio_read_completed) { 7122 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 7123 vcpu->mmio_fragments[0].gpa, val); 7124 vcpu->mmio_read_completed = 0; 7125 return 1; 7126 } 7127 7128 return 0; 7129 } 7130 7131 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 7132 void *val, int bytes) 7133 { 7134 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 7135 } 7136 7137 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 7138 void *val, int bytes) 7139 { 7140 return emulator_write_phys(vcpu, gpa, val, bytes); 7141 } 7142 7143 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 7144 { 7145 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 7146 return vcpu_mmio_write(vcpu, gpa, bytes, val); 7147 } 7148 7149 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 7150 void *val, int bytes) 7151 { 7152 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 7153 return X86EMUL_IO_NEEDED; 7154 } 7155 7156 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 7157 void *val, int bytes) 7158 { 7159 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 7160 7161 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 7162 return X86EMUL_CONTINUE; 7163 } 7164 7165 static const struct read_write_emulator_ops read_emultor = { 7166 .read_write_prepare = read_prepare, 7167 .read_write_emulate = read_emulate, 7168 .read_write_mmio = vcpu_mmio_read, 7169 .read_write_exit_mmio = read_exit_mmio, 7170 }; 7171 7172 static const struct read_write_emulator_ops write_emultor = { 7173 .read_write_emulate = write_emulate, 7174 .read_write_mmio = write_mmio, 7175 .read_write_exit_mmio = write_exit_mmio, 7176 .write = true, 7177 }; 7178 7179 static int emulator_read_write_onepage(unsigned long addr, void *val, 7180 unsigned int bytes, 7181 struct x86_exception *exception, 7182 struct kvm_vcpu *vcpu, 7183 const struct read_write_emulator_ops *ops) 7184 { 7185 gpa_t gpa; 7186 int handled, ret; 7187 bool write = ops->write; 7188 struct kvm_mmio_fragment *frag; 7189 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7190 7191 /* 7192 * If the exit was due to a NPF we may already have a GPA. 7193 * If the GPA is present, use it to avoid the GVA to GPA table walk. 7194 * Note, this cannot be used on string operations since string 7195 * operation using rep will only have the initial GPA from the NPF 7196 * occurred. 7197 */ 7198 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && 7199 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { 7200 gpa = ctxt->gpa_val; 7201 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 7202 } else { 7203 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 7204 if (ret < 0) 7205 return X86EMUL_PROPAGATE_FAULT; 7206 } 7207 7208 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 7209 return X86EMUL_CONTINUE; 7210 7211 /* 7212 * Is this MMIO handled locally? 7213 */ 7214 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 7215 if (handled == bytes) 7216 return X86EMUL_CONTINUE; 7217 7218 gpa += handled; 7219 bytes -= handled; 7220 val += handled; 7221 7222 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 7223 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 7224 frag->gpa = gpa; 7225 frag->data = val; 7226 frag->len = bytes; 7227 return X86EMUL_CONTINUE; 7228 } 7229 7230 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 7231 unsigned long addr, 7232 void *val, unsigned int bytes, 7233 struct x86_exception *exception, 7234 const struct read_write_emulator_ops *ops) 7235 { 7236 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7237 gpa_t gpa; 7238 int rc; 7239 7240 if (ops->read_write_prepare && 7241 ops->read_write_prepare(vcpu, val, bytes)) 7242 return X86EMUL_CONTINUE; 7243 7244 vcpu->mmio_nr_fragments = 0; 7245 7246 /* Crossing a page boundary? */ 7247 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 7248 int now; 7249 7250 now = -addr & ~PAGE_MASK; 7251 rc = emulator_read_write_onepage(addr, val, now, exception, 7252 vcpu, ops); 7253 7254 if (rc != X86EMUL_CONTINUE) 7255 return rc; 7256 addr += now; 7257 if (ctxt->mode != X86EMUL_MODE_PROT64) 7258 addr = (u32)addr; 7259 val += now; 7260 bytes -= now; 7261 } 7262 7263 rc = emulator_read_write_onepage(addr, val, bytes, exception, 7264 vcpu, ops); 7265 if (rc != X86EMUL_CONTINUE) 7266 return rc; 7267 7268 if (!vcpu->mmio_nr_fragments) 7269 return rc; 7270 7271 gpa = vcpu->mmio_fragments[0].gpa; 7272 7273 vcpu->mmio_needed = 1; 7274 vcpu->mmio_cur_fragment = 0; 7275 7276 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 7277 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 7278 vcpu->run->exit_reason = KVM_EXIT_MMIO; 7279 vcpu->run->mmio.phys_addr = gpa; 7280 7281 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 7282 } 7283 7284 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 7285 unsigned long addr, 7286 void *val, 7287 unsigned int bytes, 7288 struct x86_exception *exception) 7289 { 7290 return emulator_read_write(ctxt, addr, val, bytes, 7291 exception, &read_emultor); 7292 } 7293 7294 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 7295 unsigned long addr, 7296 const void *val, 7297 unsigned int bytes, 7298 struct x86_exception *exception) 7299 { 7300 return emulator_read_write(ctxt, addr, (void *)val, bytes, 7301 exception, &write_emultor); 7302 } 7303 7304 #define emulator_try_cmpxchg_user(t, ptr, old, new) \ 7305 (__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t)) 7306 7307 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 7308 unsigned long addr, 7309 const void *old, 7310 const void *new, 7311 unsigned int bytes, 7312 struct x86_exception *exception) 7313 { 7314 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7315 u64 page_line_mask; 7316 unsigned long hva; 7317 gpa_t gpa; 7318 int r; 7319 7320 /* guests cmpxchg8b have to be emulated atomically */ 7321 if (bytes > 8 || (bytes & (bytes - 1))) 7322 goto emul_write; 7323 7324 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 7325 7326 if (gpa == UNMAPPED_GVA || 7327 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 7328 goto emul_write; 7329 7330 /* 7331 * Emulate the atomic as a straight write to avoid #AC if SLD is 7332 * enabled in the host and the access splits a cache line. 7333 */ 7334 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 7335 page_line_mask = ~(cache_line_size() - 1); 7336 else 7337 page_line_mask = PAGE_MASK; 7338 7339 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) 7340 goto emul_write; 7341 7342 hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa)); 7343 if (kvm_is_error_hva(hva)) 7344 goto emul_write; 7345 7346 hva += offset_in_page(gpa); 7347 7348 switch (bytes) { 7349 case 1: 7350 r = emulator_try_cmpxchg_user(u8, hva, old, new); 7351 break; 7352 case 2: 7353 r = emulator_try_cmpxchg_user(u16, hva, old, new); 7354 break; 7355 case 4: 7356 r = emulator_try_cmpxchg_user(u32, hva, old, new); 7357 break; 7358 case 8: 7359 r = emulator_try_cmpxchg_user(u64, hva, old, new); 7360 break; 7361 default: 7362 BUG(); 7363 } 7364 7365 if (r < 0) 7366 return X86EMUL_UNHANDLEABLE; 7367 if (r) 7368 return X86EMUL_CMPXCHG_FAILED; 7369 7370 kvm_page_track_write(vcpu, gpa, new, bytes); 7371 7372 return X86EMUL_CONTINUE; 7373 7374 emul_write: 7375 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 7376 7377 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 7378 } 7379 7380 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 7381 { 7382 int r = 0, i; 7383 7384 for (i = 0; i < vcpu->arch.pio.count; i++) { 7385 if (vcpu->arch.pio.in) 7386 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 7387 vcpu->arch.pio.size, pd); 7388 else 7389 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 7390 vcpu->arch.pio.port, vcpu->arch.pio.size, 7391 pd); 7392 if (r) 7393 break; 7394 pd += vcpu->arch.pio.size; 7395 } 7396 return r; 7397 } 7398 7399 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 7400 unsigned short port, 7401 unsigned int count, bool in) 7402 { 7403 vcpu->arch.pio.port = port; 7404 vcpu->arch.pio.in = in; 7405 vcpu->arch.pio.count = count; 7406 vcpu->arch.pio.size = size; 7407 7408 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) 7409 return 1; 7410 7411 vcpu->run->exit_reason = KVM_EXIT_IO; 7412 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 7413 vcpu->run->io.size = size; 7414 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 7415 vcpu->run->io.count = count; 7416 vcpu->run->io.port = port; 7417 7418 return 0; 7419 } 7420 7421 static int __emulator_pio_in(struct kvm_vcpu *vcpu, int size, 7422 unsigned short port, unsigned int count) 7423 { 7424 WARN_ON(vcpu->arch.pio.count); 7425 memset(vcpu->arch.pio_data, 0, size * count); 7426 return emulator_pio_in_out(vcpu, size, port, count, true); 7427 } 7428 7429 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val) 7430 { 7431 int size = vcpu->arch.pio.size; 7432 unsigned count = vcpu->arch.pio.count; 7433 memcpy(val, vcpu->arch.pio_data, size * count); 7434 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data); 7435 vcpu->arch.pio.count = 0; 7436 } 7437 7438 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, 7439 unsigned short port, void *val, unsigned int count) 7440 { 7441 if (vcpu->arch.pio.count) { 7442 /* 7443 * Complete a previous iteration that required userspace I/O. 7444 * Note, @count isn't guaranteed to match pio.count as userspace 7445 * can modify ECX before rerunning the vCPU. Ignore any such 7446 * shenanigans as KVM doesn't support modifying the rep count, 7447 * and the emulator ensures @count doesn't overflow the buffer. 7448 */ 7449 } else { 7450 int r = __emulator_pio_in(vcpu, size, port, count); 7451 if (!r) 7452 return r; 7453 7454 /* Results already available, fall through. */ 7455 } 7456 7457 complete_emulator_pio_in(vcpu, val); 7458 return 1; 7459 } 7460 7461 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 7462 int size, unsigned short port, void *val, 7463 unsigned int count) 7464 { 7465 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); 7466 7467 } 7468 7469 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, 7470 unsigned short port, const void *val, 7471 unsigned int count) 7472 { 7473 int ret; 7474 7475 memcpy(vcpu->arch.pio_data, val, size * count); 7476 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 7477 ret = emulator_pio_in_out(vcpu, size, port, count, false); 7478 if (ret) 7479 vcpu->arch.pio.count = 0; 7480 7481 return ret; 7482 } 7483 7484 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 7485 int size, unsigned short port, 7486 const void *val, unsigned int count) 7487 { 7488 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); 7489 } 7490 7491 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 7492 { 7493 return static_call(kvm_x86_get_segment_base)(vcpu, seg); 7494 } 7495 7496 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 7497 { 7498 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 7499 } 7500 7501 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 7502 { 7503 if (!need_emulate_wbinvd(vcpu)) 7504 return X86EMUL_CONTINUE; 7505 7506 if (static_call(kvm_x86_has_wbinvd_exit)()) { 7507 int cpu = get_cpu(); 7508 7509 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 7510 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, 7511 wbinvd_ipi, NULL, 1); 7512 put_cpu(); 7513 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 7514 } else 7515 wbinvd(); 7516 return X86EMUL_CONTINUE; 7517 } 7518 7519 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 7520 { 7521 kvm_emulate_wbinvd_noskip(vcpu); 7522 return kvm_skip_emulated_instruction(vcpu); 7523 } 7524 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 7525 7526 7527 7528 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 7529 { 7530 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 7531 } 7532 7533 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 7534 unsigned long *dest) 7535 { 7536 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 7537 } 7538 7539 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 7540 unsigned long value) 7541 { 7542 7543 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 7544 } 7545 7546 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 7547 { 7548 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 7549 } 7550 7551 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 7552 { 7553 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7554 unsigned long value; 7555 7556 switch (cr) { 7557 case 0: 7558 value = kvm_read_cr0(vcpu); 7559 break; 7560 case 2: 7561 value = vcpu->arch.cr2; 7562 break; 7563 case 3: 7564 value = kvm_read_cr3(vcpu); 7565 break; 7566 case 4: 7567 value = kvm_read_cr4(vcpu); 7568 break; 7569 case 8: 7570 value = kvm_get_cr8(vcpu); 7571 break; 7572 default: 7573 kvm_err("%s: unexpected cr %u\n", __func__, cr); 7574 return 0; 7575 } 7576 7577 return value; 7578 } 7579 7580 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 7581 { 7582 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7583 int res = 0; 7584 7585 switch (cr) { 7586 case 0: 7587 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 7588 break; 7589 case 2: 7590 vcpu->arch.cr2 = val; 7591 break; 7592 case 3: 7593 res = kvm_set_cr3(vcpu, val); 7594 break; 7595 case 4: 7596 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 7597 break; 7598 case 8: 7599 res = kvm_set_cr8(vcpu, val); 7600 break; 7601 default: 7602 kvm_err("%s: unexpected cr %u\n", __func__, cr); 7603 res = -1; 7604 } 7605 7606 return res; 7607 } 7608 7609 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 7610 { 7611 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); 7612 } 7613 7614 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7615 { 7616 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); 7617 } 7618 7619 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7620 { 7621 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); 7622 } 7623 7624 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7625 { 7626 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); 7627 } 7628 7629 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7630 { 7631 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); 7632 } 7633 7634 static unsigned long emulator_get_cached_segment_base( 7635 struct x86_emulate_ctxt *ctxt, int seg) 7636 { 7637 return get_segment_base(emul_to_vcpu(ctxt), seg); 7638 } 7639 7640 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 7641 struct desc_struct *desc, u32 *base3, 7642 int seg) 7643 { 7644 struct kvm_segment var; 7645 7646 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 7647 *selector = var.selector; 7648 7649 if (var.unusable) { 7650 memset(desc, 0, sizeof(*desc)); 7651 if (base3) 7652 *base3 = 0; 7653 return false; 7654 } 7655 7656 if (var.g) 7657 var.limit >>= 12; 7658 set_desc_limit(desc, var.limit); 7659 set_desc_base(desc, (unsigned long)var.base); 7660 #ifdef CONFIG_X86_64 7661 if (base3) 7662 *base3 = var.base >> 32; 7663 #endif 7664 desc->type = var.type; 7665 desc->s = var.s; 7666 desc->dpl = var.dpl; 7667 desc->p = var.present; 7668 desc->avl = var.avl; 7669 desc->l = var.l; 7670 desc->d = var.db; 7671 desc->g = var.g; 7672 7673 return true; 7674 } 7675 7676 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 7677 struct desc_struct *desc, u32 base3, 7678 int seg) 7679 { 7680 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7681 struct kvm_segment var; 7682 7683 var.selector = selector; 7684 var.base = get_desc_base(desc); 7685 #ifdef CONFIG_X86_64 7686 var.base |= ((u64)base3) << 32; 7687 #endif 7688 var.limit = get_desc_limit(desc); 7689 if (desc->g) 7690 var.limit = (var.limit << 12) | 0xfff; 7691 var.type = desc->type; 7692 var.dpl = desc->dpl; 7693 var.db = desc->d; 7694 var.s = desc->s; 7695 var.l = desc->l; 7696 var.g = desc->g; 7697 var.avl = desc->avl; 7698 var.present = desc->p; 7699 var.unusable = !var.present; 7700 var.padding = 0; 7701 7702 kvm_set_segment(vcpu, &var, seg); 7703 return; 7704 } 7705 7706 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt, 7707 u32 msr_index, u64 *pdata) 7708 { 7709 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7710 int r; 7711 7712 r = kvm_get_msr_with_filter(vcpu, msr_index, pdata); 7713 7714 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0, 7715 complete_emulated_rdmsr, r)) { 7716 /* Bounce to user space */ 7717 return X86EMUL_IO_NEEDED; 7718 } 7719 7720 return r; 7721 } 7722 7723 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt, 7724 u32 msr_index, u64 data) 7725 { 7726 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7727 int r; 7728 7729 r = kvm_set_msr_with_filter(vcpu, msr_index, data); 7730 7731 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data, 7732 complete_emulated_msr_access, r)) { 7733 /* Bounce to user space */ 7734 return X86EMUL_IO_NEEDED; 7735 } 7736 7737 return r; 7738 } 7739 7740 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 7741 u32 msr_index, u64 *pdata) 7742 { 7743 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); 7744 } 7745 7746 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 7747 u32 msr_index, u64 data) 7748 { 7749 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data); 7750 } 7751 7752 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 7753 { 7754 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7755 7756 return vcpu->arch.smbase; 7757 } 7758 7759 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 7760 { 7761 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7762 7763 vcpu->arch.smbase = smbase; 7764 } 7765 7766 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 7767 u32 pmc) 7768 { 7769 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc)) 7770 return 0; 7771 return -EINVAL; 7772 } 7773 7774 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 7775 u32 pmc, u64 *pdata) 7776 { 7777 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 7778 } 7779 7780 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 7781 { 7782 emul_to_vcpu(ctxt)->arch.halt_request = 1; 7783 } 7784 7785 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 7786 struct x86_instruction_info *info, 7787 enum x86_intercept_stage stage) 7788 { 7789 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, 7790 &ctxt->exception); 7791 } 7792 7793 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 7794 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, 7795 bool exact_only) 7796 { 7797 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); 7798 } 7799 7800 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) 7801 { 7802 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); 7803 } 7804 7805 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) 7806 { 7807 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); 7808 } 7809 7810 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) 7811 { 7812 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); 7813 } 7814 7815 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt) 7816 { 7817 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID); 7818 } 7819 7820 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 7821 { 7822 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); 7823 } 7824 7825 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 7826 { 7827 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); 7828 } 7829 7830 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 7831 { 7832 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); 7833 } 7834 7835 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 7836 { 7837 return emul_to_vcpu(ctxt)->arch.hflags; 7838 } 7839 7840 static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt) 7841 { 7842 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7843 7844 kvm_smm_changed(vcpu, false); 7845 } 7846 7847 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt, 7848 const char *smstate) 7849 { 7850 return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate); 7851 } 7852 7853 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) 7854 { 7855 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); 7856 } 7857 7858 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) 7859 { 7860 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); 7861 } 7862 7863 static const struct x86_emulate_ops emulate_ops = { 7864 .read_gpr = emulator_read_gpr, 7865 .write_gpr = emulator_write_gpr, 7866 .read_std = emulator_read_std, 7867 .write_std = emulator_write_std, 7868 .read_phys = kvm_read_guest_phys_system, 7869 .fetch = kvm_fetch_guest_virt, 7870 .read_emulated = emulator_read_emulated, 7871 .write_emulated = emulator_write_emulated, 7872 .cmpxchg_emulated = emulator_cmpxchg_emulated, 7873 .invlpg = emulator_invlpg, 7874 .pio_in_emulated = emulator_pio_in_emulated, 7875 .pio_out_emulated = emulator_pio_out_emulated, 7876 .get_segment = emulator_get_segment, 7877 .set_segment = emulator_set_segment, 7878 .get_cached_segment_base = emulator_get_cached_segment_base, 7879 .get_gdt = emulator_get_gdt, 7880 .get_idt = emulator_get_idt, 7881 .set_gdt = emulator_set_gdt, 7882 .set_idt = emulator_set_idt, 7883 .get_cr = emulator_get_cr, 7884 .set_cr = emulator_set_cr, 7885 .cpl = emulator_get_cpl, 7886 .get_dr = emulator_get_dr, 7887 .set_dr = emulator_set_dr, 7888 .get_smbase = emulator_get_smbase, 7889 .set_smbase = emulator_set_smbase, 7890 .set_msr_with_filter = emulator_set_msr_with_filter, 7891 .get_msr_with_filter = emulator_get_msr_with_filter, 7892 .set_msr = emulator_set_msr, 7893 .get_msr = emulator_get_msr, 7894 .check_pmc = emulator_check_pmc, 7895 .read_pmc = emulator_read_pmc, 7896 .halt = emulator_halt, 7897 .wbinvd = emulator_wbinvd, 7898 .fix_hypercall = emulator_fix_hypercall, 7899 .intercept = emulator_intercept, 7900 .get_cpuid = emulator_get_cpuid, 7901 .guest_has_long_mode = emulator_guest_has_long_mode, 7902 .guest_has_movbe = emulator_guest_has_movbe, 7903 .guest_has_fxsr = emulator_guest_has_fxsr, 7904 .guest_has_rdpid = emulator_guest_has_rdpid, 7905 .set_nmi_mask = emulator_set_nmi_mask, 7906 .get_hflags = emulator_get_hflags, 7907 .exiting_smm = emulator_exiting_smm, 7908 .leave_smm = emulator_leave_smm, 7909 .triple_fault = emulator_triple_fault, 7910 .set_xcr = emulator_set_xcr, 7911 }; 7912 7913 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 7914 { 7915 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 7916 /* 7917 * an sti; sti; sequence only disable interrupts for the first 7918 * instruction. So, if the last instruction, be it emulated or 7919 * not, left the system with the INT_STI flag enabled, it 7920 * means that the last instruction is an sti. We should not 7921 * leave the flag on in this case. The same goes for mov ss 7922 */ 7923 if (int_shadow & mask) 7924 mask = 0; 7925 if (unlikely(int_shadow || mask)) { 7926 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); 7927 if (!mask) 7928 kvm_make_request(KVM_REQ_EVENT, vcpu); 7929 } 7930 } 7931 7932 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 7933 { 7934 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7935 if (ctxt->exception.vector == PF_VECTOR) 7936 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); 7937 7938 if (ctxt->exception.error_code_valid) 7939 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 7940 ctxt->exception.error_code); 7941 else 7942 kvm_queue_exception(vcpu, ctxt->exception.vector); 7943 return false; 7944 } 7945 7946 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) 7947 { 7948 struct x86_emulate_ctxt *ctxt; 7949 7950 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); 7951 if (!ctxt) { 7952 pr_err("kvm: failed to allocate vcpu's emulator\n"); 7953 return NULL; 7954 } 7955 7956 ctxt->vcpu = vcpu; 7957 ctxt->ops = &emulate_ops; 7958 vcpu->arch.emulate_ctxt = ctxt; 7959 7960 return ctxt; 7961 } 7962 7963 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 7964 { 7965 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7966 int cs_db, cs_l; 7967 7968 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 7969 7970 ctxt->gpa_available = false; 7971 ctxt->eflags = kvm_get_rflags(vcpu); 7972 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 7973 7974 ctxt->eip = kvm_rip_read(vcpu); 7975 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 7976 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 7977 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 7978 cs_db ? X86EMUL_MODE_PROT32 : 7979 X86EMUL_MODE_PROT16; 7980 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 7981 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 7982 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 7983 7984 ctxt->interruptibility = 0; 7985 ctxt->have_exception = false; 7986 ctxt->exception.vector = -1; 7987 ctxt->perm_ok = false; 7988 7989 init_decode_cache(ctxt); 7990 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 7991 } 7992 7993 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 7994 { 7995 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7996 int ret; 7997 7998 init_emulate_ctxt(vcpu); 7999 8000 ctxt->op_bytes = 2; 8001 ctxt->ad_bytes = 2; 8002 ctxt->_eip = ctxt->eip + inc_eip; 8003 ret = emulate_int_real(ctxt, irq); 8004 8005 if (ret != X86EMUL_CONTINUE) { 8006 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 8007 } else { 8008 ctxt->eip = ctxt->_eip; 8009 kvm_rip_write(vcpu, ctxt->eip); 8010 kvm_set_rflags(vcpu, ctxt->eflags); 8011 } 8012 } 8013 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 8014 8015 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, 8016 u8 ndata, u8 *insn_bytes, u8 insn_size) 8017 { 8018 struct kvm_run *run = vcpu->run; 8019 u64 info[5]; 8020 u8 info_start; 8021 8022 /* 8023 * Zero the whole array used to retrieve the exit info, as casting to 8024 * u32 for select entries will leave some chunks uninitialized. 8025 */ 8026 memset(&info, 0, sizeof(info)); 8027 8028 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1], 8029 &info[2], (u32 *)&info[3], 8030 (u32 *)&info[4]); 8031 8032 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 8033 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION; 8034 8035 /* 8036 * There's currently space for 13 entries, but 5 are used for the exit 8037 * reason and info. Restrict to 4 to reduce the maintenance burden 8038 * when expanding kvm_run.emulation_failure in the future. 8039 */ 8040 if (WARN_ON_ONCE(ndata > 4)) 8041 ndata = 4; 8042 8043 /* Always include the flags as a 'data' entry. */ 8044 info_start = 1; 8045 run->emulation_failure.flags = 0; 8046 8047 if (insn_size) { 8048 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) + 8049 sizeof(run->emulation_failure.insn_bytes) != 16)); 8050 info_start += 2; 8051 run->emulation_failure.flags |= 8052 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES; 8053 run->emulation_failure.insn_size = insn_size; 8054 memset(run->emulation_failure.insn_bytes, 0x90, 8055 sizeof(run->emulation_failure.insn_bytes)); 8056 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size); 8057 } 8058 8059 memcpy(&run->internal.data[info_start], info, sizeof(info)); 8060 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data, 8061 ndata * sizeof(data[0])); 8062 8063 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata; 8064 } 8065 8066 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu) 8067 { 8068 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8069 8070 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data, 8071 ctxt->fetch.end - ctxt->fetch.data); 8072 } 8073 8074 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, 8075 u8 ndata) 8076 { 8077 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0); 8078 } 8079 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit); 8080 8081 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu) 8082 { 8083 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0); 8084 } 8085 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit); 8086 8087 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 8088 { 8089 struct kvm *kvm = vcpu->kvm; 8090 8091 ++vcpu->stat.insn_emulation_fail; 8092 trace_kvm_emulate_insn_failed(vcpu); 8093 8094 if (emulation_type & EMULTYPE_VMWARE_GP) { 8095 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 8096 return 1; 8097 } 8098 8099 if (kvm->arch.exit_on_emulation_error || 8100 (emulation_type & EMULTYPE_SKIP)) { 8101 prepare_emulation_ctxt_failure_exit(vcpu); 8102 return 0; 8103 } 8104 8105 kvm_queue_exception(vcpu, UD_VECTOR); 8106 8107 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { 8108 prepare_emulation_ctxt_failure_exit(vcpu); 8109 return 0; 8110 } 8111 8112 return 1; 8113 } 8114 8115 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 8116 bool write_fault_to_shadow_pgtable, 8117 int emulation_type) 8118 { 8119 gpa_t gpa = cr2_or_gpa; 8120 kvm_pfn_t pfn; 8121 8122 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 8123 return false; 8124 8125 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 8126 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 8127 return false; 8128 8129 if (!vcpu->arch.mmu->root_role.direct) { 8130 /* 8131 * Write permission should be allowed since only 8132 * write access need to be emulated. 8133 */ 8134 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 8135 8136 /* 8137 * If the mapping is invalid in guest, let cpu retry 8138 * it to generate fault. 8139 */ 8140 if (gpa == UNMAPPED_GVA) 8141 return true; 8142 } 8143 8144 /* 8145 * Do not retry the unhandleable instruction if it faults on the 8146 * readonly host memory, otherwise it will goto a infinite loop: 8147 * retry instruction -> write #PF -> emulation fail -> retry 8148 * instruction -> ... 8149 */ 8150 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 8151 8152 /* 8153 * If the instruction failed on the error pfn, it can not be fixed, 8154 * report the error to userspace. 8155 */ 8156 if (is_error_noslot_pfn(pfn)) 8157 return false; 8158 8159 kvm_release_pfn_clean(pfn); 8160 8161 /* The instructions are well-emulated on direct mmu. */ 8162 if (vcpu->arch.mmu->root_role.direct) { 8163 unsigned int indirect_shadow_pages; 8164 8165 write_lock(&vcpu->kvm->mmu_lock); 8166 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 8167 write_unlock(&vcpu->kvm->mmu_lock); 8168 8169 if (indirect_shadow_pages) 8170 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 8171 8172 return true; 8173 } 8174 8175 /* 8176 * if emulation was due to access to shadowed page table 8177 * and it failed try to unshadow page and re-enter the 8178 * guest to let CPU execute the instruction. 8179 */ 8180 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 8181 8182 /* 8183 * If the access faults on its page table, it can not 8184 * be fixed by unprotecting shadow page and it should 8185 * be reported to userspace. 8186 */ 8187 return !write_fault_to_shadow_pgtable; 8188 } 8189 8190 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 8191 gpa_t cr2_or_gpa, int emulation_type) 8192 { 8193 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8194 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; 8195 8196 last_retry_eip = vcpu->arch.last_retry_eip; 8197 last_retry_addr = vcpu->arch.last_retry_addr; 8198 8199 /* 8200 * If the emulation is caused by #PF and it is non-page_table 8201 * writing instruction, it means the VM-EXIT is caused by shadow 8202 * page protected, we can zap the shadow page and retry this 8203 * instruction directly. 8204 * 8205 * Note: if the guest uses a non-page-table modifying instruction 8206 * on the PDE that points to the instruction, then we will unmap 8207 * the instruction and go to an infinite loop. So, we cache the 8208 * last retried eip and the last fault address, if we meet the eip 8209 * and the address again, we can break out of the potential infinite 8210 * loop. 8211 */ 8212 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 8213 8214 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 8215 return false; 8216 8217 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 8218 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 8219 return false; 8220 8221 if (x86_page_table_writing_insn(ctxt)) 8222 return false; 8223 8224 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) 8225 return false; 8226 8227 vcpu->arch.last_retry_eip = ctxt->eip; 8228 vcpu->arch.last_retry_addr = cr2_or_gpa; 8229 8230 if (!vcpu->arch.mmu->root_role.direct) 8231 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 8232 8233 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 8234 8235 return true; 8236 } 8237 8238 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 8239 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 8240 8241 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm) 8242 { 8243 trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm); 8244 8245 if (entering_smm) { 8246 vcpu->arch.hflags |= HF_SMM_MASK; 8247 } else { 8248 vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK); 8249 8250 /* Process a latched INIT or SMI, if any. */ 8251 kvm_make_request(KVM_REQ_EVENT, vcpu); 8252 8253 /* 8254 * Even if KVM_SET_SREGS2 loaded PDPTRs out of band, 8255 * on SMM exit we still need to reload them from 8256 * guest memory 8257 */ 8258 vcpu->arch.pdptrs_from_userspace = false; 8259 } 8260 8261 kvm_mmu_reset_context(vcpu); 8262 } 8263 8264 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 8265 unsigned long *db) 8266 { 8267 u32 dr6 = 0; 8268 int i; 8269 u32 enable, rwlen; 8270 8271 enable = dr7; 8272 rwlen = dr7 >> 16; 8273 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 8274 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 8275 dr6 |= (1 << i); 8276 return dr6; 8277 } 8278 8279 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) 8280 { 8281 struct kvm_run *kvm_run = vcpu->run; 8282 8283 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 8284 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; 8285 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); 8286 kvm_run->debug.arch.exception = DB_VECTOR; 8287 kvm_run->exit_reason = KVM_EXIT_DEBUG; 8288 return 0; 8289 } 8290 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 8291 return 1; 8292 } 8293 8294 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 8295 { 8296 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 8297 int r; 8298 8299 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); 8300 if (unlikely(!r)) 8301 return 0; 8302 8303 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS); 8304 8305 /* 8306 * rflags is the old, "raw" value of the flags. The new value has 8307 * not been saved yet. 8308 * 8309 * This is correct even for TF set by the guest, because "the 8310 * processor will not generate this exception after the instruction 8311 * that sets the TF flag". 8312 */ 8313 if (unlikely(rflags & X86_EFLAGS_TF)) 8314 r = kvm_vcpu_do_singlestep(vcpu); 8315 return r; 8316 } 8317 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 8318 8319 static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu, int *r) 8320 { 8321 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 8322 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 8323 struct kvm_run *kvm_run = vcpu->run; 8324 unsigned long eip = kvm_get_linear_rip(vcpu); 8325 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 8326 vcpu->arch.guest_debug_dr7, 8327 vcpu->arch.eff_db); 8328 8329 if (dr6 != 0) { 8330 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; 8331 kvm_run->debug.arch.pc = eip; 8332 kvm_run->debug.arch.exception = DB_VECTOR; 8333 kvm_run->exit_reason = KVM_EXIT_DEBUG; 8334 *r = 0; 8335 return true; 8336 } 8337 } 8338 8339 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 8340 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 8341 unsigned long eip = kvm_get_linear_rip(vcpu); 8342 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 8343 vcpu->arch.dr7, 8344 vcpu->arch.db); 8345 8346 if (dr6 != 0) { 8347 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); 8348 *r = 1; 8349 return true; 8350 } 8351 } 8352 8353 return false; 8354 } 8355 8356 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 8357 { 8358 switch (ctxt->opcode_len) { 8359 case 1: 8360 switch (ctxt->b) { 8361 case 0xe4: /* IN */ 8362 case 0xe5: 8363 case 0xec: 8364 case 0xed: 8365 case 0xe6: /* OUT */ 8366 case 0xe7: 8367 case 0xee: 8368 case 0xef: 8369 case 0x6c: /* INS */ 8370 case 0x6d: 8371 case 0x6e: /* OUTS */ 8372 case 0x6f: 8373 return true; 8374 } 8375 break; 8376 case 2: 8377 switch (ctxt->b) { 8378 case 0x33: /* RDPMC */ 8379 return true; 8380 } 8381 break; 8382 } 8383 8384 return false; 8385 } 8386 8387 /* 8388 * Decode an instruction for emulation. The caller is responsible for handling 8389 * code breakpoints. Note, manually detecting code breakpoints is unnecessary 8390 * (and wrong) when emulating on an intercepted fault-like exception[*], as 8391 * code breakpoints have higher priority and thus have already been done by 8392 * hardware. 8393 * 8394 * [*] Except #MC, which is higher priority, but KVM should never emulate in 8395 * response to a machine check. 8396 */ 8397 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 8398 void *insn, int insn_len) 8399 { 8400 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8401 int r; 8402 8403 init_emulate_ctxt(vcpu); 8404 8405 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); 8406 8407 trace_kvm_emulate_insn_start(vcpu); 8408 ++vcpu->stat.insn_emulation; 8409 8410 return r; 8411 } 8412 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); 8413 8414 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 8415 int emulation_type, void *insn, int insn_len) 8416 { 8417 int r; 8418 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8419 bool writeback = true; 8420 bool write_fault_to_spt; 8421 8422 if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len))) 8423 return 1; 8424 8425 vcpu->arch.l1tf_flush_l1d = true; 8426 8427 /* 8428 * Clear write_fault_to_shadow_pgtable here to ensure it is 8429 * never reused. 8430 */ 8431 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 8432 vcpu->arch.write_fault_to_shadow_pgtable = false; 8433 8434 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 8435 kvm_clear_exception_queue(vcpu); 8436 8437 /* 8438 * Return immediately if RIP hits a code breakpoint, such #DBs 8439 * are fault-like and are higher priority than any faults on 8440 * the code fetch itself. 8441 */ 8442 if (!(emulation_type & EMULTYPE_SKIP) && 8443 kvm_vcpu_check_code_breakpoint(vcpu, &r)) 8444 return r; 8445 8446 r = x86_decode_emulated_instruction(vcpu, emulation_type, 8447 insn, insn_len); 8448 if (r != EMULATION_OK) { 8449 if ((emulation_type & EMULTYPE_TRAP_UD) || 8450 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { 8451 kvm_queue_exception(vcpu, UD_VECTOR); 8452 return 1; 8453 } 8454 if (reexecute_instruction(vcpu, cr2_or_gpa, 8455 write_fault_to_spt, 8456 emulation_type)) 8457 return 1; 8458 if (ctxt->have_exception) { 8459 /* 8460 * #UD should result in just EMULATION_FAILED, and trap-like 8461 * exception should not be encountered during decode. 8462 */ 8463 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || 8464 exception_type(ctxt->exception.vector) == EXCPT_TRAP); 8465 inject_emulated_exception(vcpu); 8466 return 1; 8467 } 8468 return handle_emulation_failure(vcpu, emulation_type); 8469 } 8470 } 8471 8472 if ((emulation_type & EMULTYPE_VMWARE_GP) && 8473 !is_vmware_backdoor_opcode(ctxt)) { 8474 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 8475 return 1; 8476 } 8477 8478 /* 8479 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for 8480 * use *only* by vendor callbacks for kvm_skip_emulated_instruction(). 8481 * The caller is responsible for updating interruptibility state and 8482 * injecting single-step #DBs. 8483 */ 8484 if (emulation_type & EMULTYPE_SKIP) { 8485 if (ctxt->mode != X86EMUL_MODE_PROT64) 8486 ctxt->eip = (u32)ctxt->_eip; 8487 else 8488 ctxt->eip = ctxt->_eip; 8489 8490 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) { 8491 r = 1; 8492 goto writeback; 8493 } 8494 8495 kvm_rip_write(vcpu, ctxt->eip); 8496 if (ctxt->eflags & X86_EFLAGS_RF) 8497 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 8498 return 1; 8499 } 8500 8501 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) 8502 return 1; 8503 8504 /* this is needed for vmware backdoor interface to work since it 8505 changes registers values during IO operation */ 8506 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 8507 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 8508 emulator_invalidate_register_cache(ctxt); 8509 } 8510 8511 restart: 8512 if (emulation_type & EMULTYPE_PF) { 8513 /* Save the faulting GPA (cr2) in the address field */ 8514 ctxt->exception.address = cr2_or_gpa; 8515 8516 /* With shadow page tables, cr2 contains a GVA or nGPA. */ 8517 if (vcpu->arch.mmu->root_role.direct) { 8518 ctxt->gpa_available = true; 8519 ctxt->gpa_val = cr2_or_gpa; 8520 } 8521 } else { 8522 /* Sanitize the address out of an abundance of paranoia. */ 8523 ctxt->exception.address = 0; 8524 } 8525 8526 r = x86_emulate_insn(ctxt); 8527 8528 if (r == EMULATION_INTERCEPTED) 8529 return 1; 8530 8531 if (r == EMULATION_FAILED) { 8532 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, 8533 emulation_type)) 8534 return 1; 8535 8536 return handle_emulation_failure(vcpu, emulation_type); 8537 } 8538 8539 if (ctxt->have_exception) { 8540 r = 1; 8541 if (inject_emulated_exception(vcpu)) 8542 return r; 8543 } else if (vcpu->arch.pio.count) { 8544 if (!vcpu->arch.pio.in) { 8545 /* FIXME: return into emulator if single-stepping. */ 8546 vcpu->arch.pio.count = 0; 8547 } else { 8548 writeback = false; 8549 vcpu->arch.complete_userspace_io = complete_emulated_pio; 8550 } 8551 r = 0; 8552 } else if (vcpu->mmio_needed) { 8553 ++vcpu->stat.mmio_exits; 8554 8555 if (!vcpu->mmio_is_write) 8556 writeback = false; 8557 r = 0; 8558 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 8559 } else if (vcpu->arch.complete_userspace_io) { 8560 writeback = false; 8561 r = 0; 8562 } else if (r == EMULATION_RESTART) 8563 goto restart; 8564 else 8565 r = 1; 8566 8567 writeback: 8568 if (writeback) { 8569 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 8570 toggle_interruptibility(vcpu, ctxt->interruptibility); 8571 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 8572 if (!ctxt->have_exception || 8573 exception_type(ctxt->exception.vector) == EXCPT_TRAP) { 8574 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS); 8575 if (ctxt->is_branch) 8576 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 8577 kvm_rip_write(vcpu, ctxt->eip); 8578 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 8579 r = kvm_vcpu_do_singlestep(vcpu); 8580 static_call_cond(kvm_x86_update_emulated_instruction)(vcpu); 8581 __kvm_set_rflags(vcpu, ctxt->eflags); 8582 } 8583 8584 /* 8585 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 8586 * do nothing, and it will be requested again as soon as 8587 * the shadow expires. But we still need to check here, 8588 * because POPF has no interrupt shadow. 8589 */ 8590 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 8591 kvm_make_request(KVM_REQ_EVENT, vcpu); 8592 } else 8593 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 8594 8595 return r; 8596 } 8597 8598 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 8599 { 8600 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 8601 } 8602 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 8603 8604 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 8605 void *insn, int insn_len) 8606 { 8607 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 8608 } 8609 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 8610 8611 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 8612 { 8613 vcpu->arch.pio.count = 0; 8614 return 1; 8615 } 8616 8617 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 8618 { 8619 vcpu->arch.pio.count = 0; 8620 8621 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 8622 return 1; 8623 8624 return kvm_skip_emulated_instruction(vcpu); 8625 } 8626 8627 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 8628 unsigned short port) 8629 { 8630 unsigned long val = kvm_rax_read(vcpu); 8631 int ret = emulator_pio_out(vcpu, size, port, &val, 1); 8632 8633 if (ret) 8634 return ret; 8635 8636 /* 8637 * Workaround userspace that relies on old KVM behavior of %rip being 8638 * incremented prior to exiting to userspace to handle "OUT 0x7e". 8639 */ 8640 if (port == 0x7e && 8641 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 8642 vcpu->arch.complete_userspace_io = 8643 complete_fast_pio_out_port_0x7e; 8644 kvm_skip_emulated_instruction(vcpu); 8645 } else { 8646 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 8647 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 8648 } 8649 return 0; 8650 } 8651 8652 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 8653 { 8654 unsigned long val; 8655 8656 /* We should only ever be called with arch.pio.count equal to 1 */ 8657 BUG_ON(vcpu->arch.pio.count != 1); 8658 8659 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 8660 vcpu->arch.pio.count = 0; 8661 return 1; 8662 } 8663 8664 /* For size less than 4 we merge, else we zero extend */ 8665 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 8666 8667 /* 8668 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform 8669 * the copy and tracing 8670 */ 8671 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); 8672 kvm_rax_write(vcpu, val); 8673 8674 return kvm_skip_emulated_instruction(vcpu); 8675 } 8676 8677 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 8678 unsigned short port) 8679 { 8680 unsigned long val; 8681 int ret; 8682 8683 /* For size less than 4 we merge, else we zero extend */ 8684 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 8685 8686 ret = emulator_pio_in(vcpu, size, port, &val, 1); 8687 if (ret) { 8688 kvm_rax_write(vcpu, val); 8689 return ret; 8690 } 8691 8692 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 8693 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 8694 8695 return 0; 8696 } 8697 8698 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 8699 { 8700 int ret; 8701 8702 if (in) 8703 ret = kvm_fast_pio_in(vcpu, size, port); 8704 else 8705 ret = kvm_fast_pio_out(vcpu, size, port); 8706 return ret && kvm_skip_emulated_instruction(vcpu); 8707 } 8708 EXPORT_SYMBOL_GPL(kvm_fast_pio); 8709 8710 static int kvmclock_cpu_down_prep(unsigned int cpu) 8711 { 8712 __this_cpu_write(cpu_tsc_khz, 0); 8713 return 0; 8714 } 8715 8716 static void tsc_khz_changed(void *data) 8717 { 8718 struct cpufreq_freqs *freq = data; 8719 unsigned long khz = 0; 8720 8721 if (data) 8722 khz = freq->new; 8723 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 8724 khz = cpufreq_quick_get(raw_smp_processor_id()); 8725 if (!khz) 8726 khz = tsc_khz; 8727 __this_cpu_write(cpu_tsc_khz, khz); 8728 } 8729 8730 #ifdef CONFIG_X86_64 8731 static void kvm_hyperv_tsc_notifier(void) 8732 { 8733 struct kvm *kvm; 8734 int cpu; 8735 8736 mutex_lock(&kvm_lock); 8737 list_for_each_entry(kvm, &vm_list, vm_list) 8738 kvm_make_mclock_inprogress_request(kvm); 8739 8740 /* no guest entries from this point */ 8741 hyperv_stop_tsc_emulation(); 8742 8743 /* TSC frequency always matches when on Hyper-V */ 8744 for_each_present_cpu(cpu) 8745 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 8746 kvm_max_guest_tsc_khz = tsc_khz; 8747 8748 list_for_each_entry(kvm, &vm_list, vm_list) { 8749 __kvm_start_pvclock_update(kvm); 8750 pvclock_update_vm_gtod_copy(kvm); 8751 kvm_end_pvclock_update(kvm); 8752 } 8753 8754 mutex_unlock(&kvm_lock); 8755 } 8756 #endif 8757 8758 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 8759 { 8760 struct kvm *kvm; 8761 struct kvm_vcpu *vcpu; 8762 int send_ipi = 0; 8763 unsigned long i; 8764 8765 /* 8766 * We allow guests to temporarily run on slowing clocks, 8767 * provided we notify them after, or to run on accelerating 8768 * clocks, provided we notify them before. Thus time never 8769 * goes backwards. 8770 * 8771 * However, we have a problem. We can't atomically update 8772 * the frequency of a given CPU from this function; it is 8773 * merely a notifier, which can be called from any CPU. 8774 * Changing the TSC frequency at arbitrary points in time 8775 * requires a recomputation of local variables related to 8776 * the TSC for each VCPU. We must flag these local variables 8777 * to be updated and be sure the update takes place with the 8778 * new frequency before any guests proceed. 8779 * 8780 * Unfortunately, the combination of hotplug CPU and frequency 8781 * change creates an intractable locking scenario; the order 8782 * of when these callouts happen is undefined with respect to 8783 * CPU hotplug, and they can race with each other. As such, 8784 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 8785 * undefined; you can actually have a CPU frequency change take 8786 * place in between the computation of X and the setting of the 8787 * variable. To protect against this problem, all updates of 8788 * the per_cpu tsc_khz variable are done in an interrupt 8789 * protected IPI, and all callers wishing to update the value 8790 * must wait for a synchronous IPI to complete (which is trivial 8791 * if the caller is on the CPU already). This establishes the 8792 * necessary total order on variable updates. 8793 * 8794 * Note that because a guest time update may take place 8795 * anytime after the setting of the VCPU's request bit, the 8796 * correct TSC value must be set before the request. However, 8797 * to ensure the update actually makes it to any guest which 8798 * starts running in hardware virtualization between the set 8799 * and the acquisition of the spinlock, we must also ping the 8800 * CPU after setting the request bit. 8801 * 8802 */ 8803 8804 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 8805 8806 mutex_lock(&kvm_lock); 8807 list_for_each_entry(kvm, &vm_list, vm_list) { 8808 kvm_for_each_vcpu(i, vcpu, kvm) { 8809 if (vcpu->cpu != cpu) 8810 continue; 8811 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 8812 if (vcpu->cpu != raw_smp_processor_id()) 8813 send_ipi = 1; 8814 } 8815 } 8816 mutex_unlock(&kvm_lock); 8817 8818 if (freq->old < freq->new && send_ipi) { 8819 /* 8820 * We upscale the frequency. Must make the guest 8821 * doesn't see old kvmclock values while running with 8822 * the new frequency, otherwise we risk the guest sees 8823 * time go backwards. 8824 * 8825 * In case we update the frequency for another cpu 8826 * (which might be in guest context) send an interrupt 8827 * to kick the cpu out of guest context. Next time 8828 * guest context is entered kvmclock will be updated, 8829 * so the guest will not see stale values. 8830 */ 8831 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 8832 } 8833 } 8834 8835 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 8836 void *data) 8837 { 8838 struct cpufreq_freqs *freq = data; 8839 int cpu; 8840 8841 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 8842 return 0; 8843 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 8844 return 0; 8845 8846 for_each_cpu(cpu, freq->policy->cpus) 8847 __kvmclock_cpufreq_notifier(freq, cpu); 8848 8849 return 0; 8850 } 8851 8852 static struct notifier_block kvmclock_cpufreq_notifier_block = { 8853 .notifier_call = kvmclock_cpufreq_notifier 8854 }; 8855 8856 static int kvmclock_cpu_online(unsigned int cpu) 8857 { 8858 tsc_khz_changed(NULL); 8859 return 0; 8860 } 8861 8862 static void kvm_timer_init(void) 8863 { 8864 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 8865 max_tsc_khz = tsc_khz; 8866 8867 if (IS_ENABLED(CONFIG_CPU_FREQ)) { 8868 struct cpufreq_policy *policy; 8869 int cpu; 8870 8871 cpu = get_cpu(); 8872 policy = cpufreq_cpu_get(cpu); 8873 if (policy) { 8874 if (policy->cpuinfo.max_freq) 8875 max_tsc_khz = policy->cpuinfo.max_freq; 8876 cpufreq_cpu_put(policy); 8877 } 8878 put_cpu(); 8879 } 8880 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 8881 CPUFREQ_TRANSITION_NOTIFIER); 8882 } 8883 8884 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 8885 kvmclock_cpu_online, kvmclock_cpu_down_prep); 8886 } 8887 8888 #ifdef CONFIG_X86_64 8889 static void pvclock_gtod_update_fn(struct work_struct *work) 8890 { 8891 struct kvm *kvm; 8892 struct kvm_vcpu *vcpu; 8893 unsigned long i; 8894 8895 mutex_lock(&kvm_lock); 8896 list_for_each_entry(kvm, &vm_list, vm_list) 8897 kvm_for_each_vcpu(i, vcpu, kvm) 8898 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 8899 atomic_set(&kvm_guest_has_master_clock, 0); 8900 mutex_unlock(&kvm_lock); 8901 } 8902 8903 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 8904 8905 /* 8906 * Indirection to move queue_work() out of the tk_core.seq write held 8907 * region to prevent possible deadlocks against time accessors which 8908 * are invoked with work related locks held. 8909 */ 8910 static void pvclock_irq_work_fn(struct irq_work *w) 8911 { 8912 queue_work(system_long_wq, &pvclock_gtod_work); 8913 } 8914 8915 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); 8916 8917 /* 8918 * Notification about pvclock gtod data update. 8919 */ 8920 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 8921 void *priv) 8922 { 8923 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 8924 struct timekeeper *tk = priv; 8925 8926 update_pvclock_gtod(tk); 8927 8928 /* 8929 * Disable master clock if host does not trust, or does not use, 8930 * TSC based clocksource. Delegate queue_work() to irq_work as 8931 * this is invoked with tk_core.seq write held. 8932 */ 8933 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 8934 atomic_read(&kvm_guest_has_master_clock) != 0) 8935 irq_work_queue(&pvclock_irq_work); 8936 return 0; 8937 } 8938 8939 static struct notifier_block pvclock_gtod_notifier = { 8940 .notifier_call = pvclock_gtod_notify, 8941 }; 8942 #endif 8943 8944 int kvm_arch_init(void *opaque) 8945 { 8946 struct kvm_x86_init_ops *ops = opaque; 8947 int r; 8948 8949 if (kvm_x86_ops.hardware_enable) { 8950 pr_err("kvm: already loaded vendor module '%s'\n", kvm_x86_ops.name); 8951 r = -EEXIST; 8952 goto out; 8953 } 8954 8955 if (!ops->cpu_has_kvm_support()) { 8956 pr_err_ratelimited("kvm: no hardware support for '%s'\n", 8957 ops->runtime_ops->name); 8958 r = -EOPNOTSUPP; 8959 goto out; 8960 } 8961 if (ops->disabled_by_bios()) { 8962 pr_err_ratelimited("kvm: support for '%s' disabled by bios\n", 8963 ops->runtime_ops->name); 8964 r = -EOPNOTSUPP; 8965 goto out; 8966 } 8967 8968 /* 8969 * KVM explicitly assumes that the guest has an FPU and 8970 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 8971 * vCPU's FPU state as a fxregs_state struct. 8972 */ 8973 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 8974 printk(KERN_ERR "kvm: inadequate fpu\n"); 8975 r = -EOPNOTSUPP; 8976 goto out; 8977 } 8978 8979 if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 8980 pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n"); 8981 r = -EOPNOTSUPP; 8982 goto out; 8983 } 8984 8985 r = -ENOMEM; 8986 8987 x86_emulator_cache = kvm_alloc_emulator_cache(); 8988 if (!x86_emulator_cache) { 8989 pr_err("kvm: failed to allocate cache for x86 emulator\n"); 8990 goto out; 8991 } 8992 8993 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); 8994 if (!user_return_msrs) { 8995 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); 8996 goto out_free_x86_emulator_cache; 8997 } 8998 kvm_nr_uret_msrs = 0; 8999 9000 r = kvm_mmu_vendor_module_init(); 9001 if (r) 9002 goto out_free_percpu; 9003 9004 kvm_timer_init(); 9005 9006 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 9007 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 9008 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; 9009 } 9010 9011 if (pi_inject_timer == -1) 9012 pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER); 9013 #ifdef CONFIG_X86_64 9014 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 9015 9016 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 9017 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 9018 #endif 9019 9020 return 0; 9021 9022 out_free_percpu: 9023 free_percpu(user_return_msrs); 9024 out_free_x86_emulator_cache: 9025 kmem_cache_destroy(x86_emulator_cache); 9026 out: 9027 return r; 9028 } 9029 9030 void kvm_arch_exit(void) 9031 { 9032 #ifdef CONFIG_X86_64 9033 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 9034 clear_hv_tscchange_cb(); 9035 #endif 9036 kvm_lapic_exit(); 9037 9038 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 9039 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 9040 CPUFREQ_TRANSITION_NOTIFIER); 9041 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 9042 #ifdef CONFIG_X86_64 9043 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 9044 irq_work_sync(&pvclock_irq_work); 9045 cancel_work_sync(&pvclock_gtod_work); 9046 #endif 9047 kvm_x86_ops.hardware_enable = NULL; 9048 kvm_mmu_vendor_module_exit(); 9049 free_percpu(user_return_msrs); 9050 kmem_cache_destroy(x86_emulator_cache); 9051 #ifdef CONFIG_KVM_XEN 9052 static_key_deferred_flush(&kvm_xen_enabled); 9053 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); 9054 #endif 9055 } 9056 9057 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason) 9058 { 9059 /* 9060 * The vCPU has halted, e.g. executed HLT. Update the run state if the 9061 * local APIC is in-kernel, the run loop will detect the non-runnable 9062 * state and halt the vCPU. Exit to userspace if the local APIC is 9063 * managed by userspace, in which case userspace is responsible for 9064 * handling wake events. 9065 */ 9066 ++vcpu->stat.halt_exits; 9067 if (lapic_in_kernel(vcpu)) { 9068 vcpu->arch.mp_state = state; 9069 return 1; 9070 } else { 9071 vcpu->run->exit_reason = reason; 9072 return 0; 9073 } 9074 } 9075 9076 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu) 9077 { 9078 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); 9079 } 9080 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip); 9081 9082 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 9083 { 9084 int ret = kvm_skip_emulated_instruction(vcpu); 9085 /* 9086 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 9087 * KVM_EXIT_DEBUG here. 9088 */ 9089 return kvm_emulate_halt_noskip(vcpu) && ret; 9090 } 9091 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 9092 9093 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) 9094 { 9095 int ret = kvm_skip_emulated_instruction(vcpu); 9096 9097 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, 9098 KVM_EXIT_AP_RESET_HOLD) && ret; 9099 } 9100 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); 9101 9102 #ifdef CONFIG_X86_64 9103 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 9104 unsigned long clock_type) 9105 { 9106 struct kvm_clock_pairing clock_pairing; 9107 struct timespec64 ts; 9108 u64 cycle; 9109 int ret; 9110 9111 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 9112 return -KVM_EOPNOTSUPP; 9113 9114 /* 9115 * When tsc is in permanent catchup mode guests won't be able to use 9116 * pvclock_read_retry loop to get consistent view of pvclock 9117 */ 9118 if (vcpu->arch.tsc_always_catchup) 9119 return -KVM_EOPNOTSUPP; 9120 9121 if (!kvm_get_walltime_and_clockread(&ts, &cycle)) 9122 return -KVM_EOPNOTSUPP; 9123 9124 clock_pairing.sec = ts.tv_sec; 9125 clock_pairing.nsec = ts.tv_nsec; 9126 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 9127 clock_pairing.flags = 0; 9128 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 9129 9130 ret = 0; 9131 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 9132 sizeof(struct kvm_clock_pairing))) 9133 ret = -KVM_EFAULT; 9134 9135 return ret; 9136 } 9137 #endif 9138 9139 /* 9140 * kvm_pv_kick_cpu_op: Kick a vcpu. 9141 * 9142 * @apicid - apicid of vcpu to be kicked. 9143 */ 9144 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid) 9145 { 9146 /* 9147 * All other fields are unused for APIC_DM_REMRD, but may be consumed by 9148 * common code, e.g. for tracing. Defer initialization to the compiler. 9149 */ 9150 struct kvm_lapic_irq lapic_irq = { 9151 .delivery_mode = APIC_DM_REMRD, 9152 .dest_mode = APIC_DEST_PHYSICAL, 9153 .shorthand = APIC_DEST_NOSHORT, 9154 .dest_id = apicid, 9155 }; 9156 9157 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 9158 } 9159 9160 bool kvm_apicv_activated(struct kvm *kvm) 9161 { 9162 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); 9163 } 9164 EXPORT_SYMBOL_GPL(kvm_apicv_activated); 9165 9166 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu) 9167 { 9168 ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons); 9169 ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu); 9170 9171 return (vm_reasons | vcpu_reasons) == 0; 9172 } 9173 EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated); 9174 9175 static void set_or_clear_apicv_inhibit(unsigned long *inhibits, 9176 enum kvm_apicv_inhibit reason, bool set) 9177 { 9178 if (set) 9179 __set_bit(reason, inhibits); 9180 else 9181 __clear_bit(reason, inhibits); 9182 9183 trace_kvm_apicv_inhibit_changed(reason, set, *inhibits); 9184 } 9185 9186 static void kvm_apicv_init(struct kvm *kvm) 9187 { 9188 unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons; 9189 9190 init_rwsem(&kvm->arch.apicv_update_lock); 9191 9192 set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true); 9193 9194 if (!enable_apicv) 9195 set_or_clear_apicv_inhibit(inhibits, 9196 APICV_INHIBIT_REASON_DISABLE, true); 9197 } 9198 9199 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) 9200 { 9201 struct kvm_vcpu *target = NULL; 9202 struct kvm_apic_map *map; 9203 9204 vcpu->stat.directed_yield_attempted++; 9205 9206 if (single_task_running()) 9207 goto no_yield; 9208 9209 rcu_read_lock(); 9210 map = rcu_dereference(vcpu->kvm->arch.apic_map); 9211 9212 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 9213 target = map->phys_map[dest_id]->vcpu; 9214 9215 rcu_read_unlock(); 9216 9217 if (!target || !READ_ONCE(target->ready)) 9218 goto no_yield; 9219 9220 /* Ignore requests to yield to self */ 9221 if (vcpu == target) 9222 goto no_yield; 9223 9224 if (kvm_vcpu_yield_to(target) <= 0) 9225 goto no_yield; 9226 9227 vcpu->stat.directed_yield_successful++; 9228 9229 no_yield: 9230 return; 9231 } 9232 9233 static int complete_hypercall_exit(struct kvm_vcpu *vcpu) 9234 { 9235 u64 ret = vcpu->run->hypercall.ret; 9236 9237 if (!is_64_bit_mode(vcpu)) 9238 ret = (u32)ret; 9239 kvm_rax_write(vcpu, ret); 9240 ++vcpu->stat.hypercalls; 9241 return kvm_skip_emulated_instruction(vcpu); 9242 } 9243 9244 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 9245 { 9246 unsigned long nr, a0, a1, a2, a3, ret; 9247 int op_64_bit; 9248 9249 if (kvm_xen_hypercall_enabled(vcpu->kvm)) 9250 return kvm_xen_hypercall(vcpu); 9251 9252 if (kvm_hv_hypercall_enabled(vcpu)) 9253 return kvm_hv_hypercall(vcpu); 9254 9255 nr = kvm_rax_read(vcpu); 9256 a0 = kvm_rbx_read(vcpu); 9257 a1 = kvm_rcx_read(vcpu); 9258 a2 = kvm_rdx_read(vcpu); 9259 a3 = kvm_rsi_read(vcpu); 9260 9261 trace_kvm_hypercall(nr, a0, a1, a2, a3); 9262 9263 op_64_bit = is_64_bit_hypercall(vcpu); 9264 if (!op_64_bit) { 9265 nr &= 0xFFFFFFFF; 9266 a0 &= 0xFFFFFFFF; 9267 a1 &= 0xFFFFFFFF; 9268 a2 &= 0xFFFFFFFF; 9269 a3 &= 0xFFFFFFFF; 9270 } 9271 9272 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { 9273 ret = -KVM_EPERM; 9274 goto out; 9275 } 9276 9277 ret = -KVM_ENOSYS; 9278 9279 switch (nr) { 9280 case KVM_HC_VAPIC_POLL_IRQ: 9281 ret = 0; 9282 break; 9283 case KVM_HC_KICK_CPU: 9284 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) 9285 break; 9286 9287 kvm_pv_kick_cpu_op(vcpu->kvm, a1); 9288 kvm_sched_yield(vcpu, a1); 9289 ret = 0; 9290 break; 9291 #ifdef CONFIG_X86_64 9292 case KVM_HC_CLOCK_PAIRING: 9293 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 9294 break; 9295 #endif 9296 case KVM_HC_SEND_IPI: 9297 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) 9298 break; 9299 9300 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 9301 break; 9302 case KVM_HC_SCHED_YIELD: 9303 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) 9304 break; 9305 9306 kvm_sched_yield(vcpu, a0); 9307 ret = 0; 9308 break; 9309 case KVM_HC_MAP_GPA_RANGE: { 9310 u64 gpa = a0, npages = a1, attrs = a2; 9311 9312 ret = -KVM_ENOSYS; 9313 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE))) 9314 break; 9315 9316 if (!PAGE_ALIGNED(gpa) || !npages || 9317 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) { 9318 ret = -KVM_EINVAL; 9319 break; 9320 } 9321 9322 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL; 9323 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE; 9324 vcpu->run->hypercall.args[0] = gpa; 9325 vcpu->run->hypercall.args[1] = npages; 9326 vcpu->run->hypercall.args[2] = attrs; 9327 vcpu->run->hypercall.longmode = op_64_bit; 9328 vcpu->arch.complete_userspace_io = complete_hypercall_exit; 9329 return 0; 9330 } 9331 default: 9332 ret = -KVM_ENOSYS; 9333 break; 9334 } 9335 out: 9336 if (!op_64_bit) 9337 ret = (u32)ret; 9338 kvm_rax_write(vcpu, ret); 9339 9340 ++vcpu->stat.hypercalls; 9341 return kvm_skip_emulated_instruction(vcpu); 9342 } 9343 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 9344 9345 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 9346 { 9347 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 9348 char instruction[3]; 9349 unsigned long rip = kvm_rip_read(vcpu); 9350 9351 /* 9352 * If the quirk is disabled, synthesize a #UD and let the guest pick up 9353 * the pieces. 9354 */ 9355 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) { 9356 ctxt->exception.error_code_valid = false; 9357 ctxt->exception.vector = UD_VECTOR; 9358 ctxt->have_exception = true; 9359 return X86EMUL_PROPAGATE_FAULT; 9360 } 9361 9362 static_call(kvm_x86_patch_hypercall)(vcpu, instruction); 9363 9364 return emulator_write_emulated(ctxt, rip, instruction, 3, 9365 &ctxt->exception); 9366 } 9367 9368 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 9369 { 9370 return vcpu->run->request_interrupt_window && 9371 likely(!pic_in_kernel(vcpu->kvm)); 9372 } 9373 9374 /* Called within kvm->srcu read side. */ 9375 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 9376 { 9377 struct kvm_run *kvm_run = vcpu->run; 9378 9379 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu); 9380 kvm_run->cr8 = kvm_get_cr8(vcpu); 9381 kvm_run->apic_base = kvm_get_apic_base(vcpu); 9382 9383 kvm_run->ready_for_interrupt_injection = 9384 pic_in_kernel(vcpu->kvm) || 9385 kvm_vcpu_ready_for_interrupt_injection(vcpu); 9386 9387 if (is_smm(vcpu)) 9388 kvm_run->flags |= KVM_RUN_X86_SMM; 9389 } 9390 9391 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 9392 { 9393 int max_irr, tpr; 9394 9395 if (!kvm_x86_ops.update_cr8_intercept) 9396 return; 9397 9398 if (!lapic_in_kernel(vcpu)) 9399 return; 9400 9401 if (vcpu->arch.apicv_active) 9402 return; 9403 9404 if (!vcpu->arch.apic->vapic_addr) 9405 max_irr = kvm_lapic_find_highest_irr(vcpu); 9406 else 9407 max_irr = -1; 9408 9409 if (max_irr != -1) 9410 max_irr >>= 4; 9411 9412 tpr = kvm_lapic_get_cr8(vcpu); 9413 9414 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); 9415 } 9416 9417 9418 int kvm_check_nested_events(struct kvm_vcpu *vcpu) 9419 { 9420 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 9421 kvm_x86_ops.nested_ops->triple_fault(vcpu); 9422 return 1; 9423 } 9424 9425 return kvm_x86_ops.nested_ops->check_events(vcpu); 9426 } 9427 9428 static void kvm_inject_exception(struct kvm_vcpu *vcpu) 9429 { 9430 if (vcpu->arch.exception.error_code && !is_protmode(vcpu)) 9431 vcpu->arch.exception.error_code = false; 9432 static_call(kvm_x86_queue_exception)(vcpu); 9433 } 9434 9435 static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) 9436 { 9437 int r; 9438 bool can_inject = true; 9439 9440 /* try to reinject previous events if any */ 9441 9442 if (vcpu->arch.exception.injected) { 9443 kvm_inject_exception(vcpu); 9444 can_inject = false; 9445 } 9446 /* 9447 * Do not inject an NMI or interrupt if there is a pending 9448 * exception. Exceptions and interrupts are recognized at 9449 * instruction boundaries, i.e. the start of an instruction. 9450 * Trap-like exceptions, e.g. #DB, have higher priority than 9451 * NMIs and interrupts, i.e. traps are recognized before an 9452 * NMI/interrupt that's pending on the same instruction. 9453 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 9454 * priority, but are only generated (pended) during instruction 9455 * execution, i.e. a pending fault-like exception means the 9456 * fault occurred on the *previous* instruction and must be 9457 * serviced prior to recognizing any new events in order to 9458 * fully complete the previous instruction. 9459 */ 9460 else if (!vcpu->arch.exception.pending) { 9461 if (vcpu->arch.nmi_injected) { 9462 static_call(kvm_x86_inject_nmi)(vcpu); 9463 can_inject = false; 9464 } else if (vcpu->arch.interrupt.injected) { 9465 static_call(kvm_x86_inject_irq)(vcpu); 9466 can_inject = false; 9467 } 9468 } 9469 9470 WARN_ON_ONCE(vcpu->arch.exception.injected && 9471 vcpu->arch.exception.pending); 9472 9473 /* 9474 * Call check_nested_events() even if we reinjected a previous event 9475 * in order for caller to determine if it should require immediate-exit 9476 * from L2 to L1 due to pending L1 events which require exit 9477 * from L2 to L1. 9478 */ 9479 if (is_guest_mode(vcpu)) { 9480 r = kvm_check_nested_events(vcpu); 9481 if (r < 0) 9482 goto out; 9483 } 9484 9485 /* try to inject new event if pending */ 9486 if (vcpu->arch.exception.pending) { 9487 trace_kvm_inj_exception(vcpu->arch.exception.nr, 9488 vcpu->arch.exception.has_error_code, 9489 vcpu->arch.exception.error_code); 9490 9491 vcpu->arch.exception.pending = false; 9492 vcpu->arch.exception.injected = true; 9493 9494 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 9495 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 9496 X86_EFLAGS_RF); 9497 9498 if (vcpu->arch.exception.nr == DB_VECTOR) { 9499 kvm_deliver_exception_payload(vcpu); 9500 if (vcpu->arch.dr7 & DR7_GD) { 9501 vcpu->arch.dr7 &= ~DR7_GD; 9502 kvm_update_dr7(vcpu); 9503 } 9504 } 9505 9506 kvm_inject_exception(vcpu); 9507 can_inject = false; 9508 } 9509 9510 /* Don't inject interrupts if the user asked to avoid doing so */ 9511 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) 9512 return 0; 9513 9514 /* 9515 * Finally, inject interrupt events. If an event cannot be injected 9516 * due to architectural conditions (e.g. IF=0) a window-open exit 9517 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending 9518 * and can architecturally be injected, but we cannot do it right now: 9519 * an interrupt could have arrived just now and we have to inject it 9520 * as a vmexit, or there could already an event in the queue, which is 9521 * indicated by can_inject. In that case we request an immediate exit 9522 * in order to make progress and get back here for another iteration. 9523 * The kvm_x86_ops hooks communicate this by returning -EBUSY. 9524 */ 9525 if (vcpu->arch.smi_pending) { 9526 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; 9527 if (r < 0) 9528 goto out; 9529 if (r) { 9530 vcpu->arch.smi_pending = false; 9531 ++vcpu->arch.smi_count; 9532 enter_smm(vcpu); 9533 can_inject = false; 9534 } else 9535 static_call(kvm_x86_enable_smi_window)(vcpu); 9536 } 9537 9538 if (vcpu->arch.nmi_pending) { 9539 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; 9540 if (r < 0) 9541 goto out; 9542 if (r) { 9543 --vcpu->arch.nmi_pending; 9544 vcpu->arch.nmi_injected = true; 9545 static_call(kvm_x86_inject_nmi)(vcpu); 9546 can_inject = false; 9547 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); 9548 } 9549 if (vcpu->arch.nmi_pending) 9550 static_call(kvm_x86_enable_nmi_window)(vcpu); 9551 } 9552 9553 if (kvm_cpu_has_injectable_intr(vcpu)) { 9554 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; 9555 if (r < 0) 9556 goto out; 9557 if (r) { 9558 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); 9559 static_call(kvm_x86_inject_irq)(vcpu); 9560 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); 9561 } 9562 if (kvm_cpu_has_injectable_intr(vcpu)) 9563 static_call(kvm_x86_enable_irq_window)(vcpu); 9564 } 9565 9566 if (is_guest_mode(vcpu) && 9567 kvm_x86_ops.nested_ops->hv_timer_pending && 9568 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 9569 *req_immediate_exit = true; 9570 9571 WARN_ON(vcpu->arch.exception.pending); 9572 return 0; 9573 9574 out: 9575 if (r == -EBUSY) { 9576 *req_immediate_exit = true; 9577 r = 0; 9578 } 9579 return r; 9580 } 9581 9582 static void process_nmi(struct kvm_vcpu *vcpu) 9583 { 9584 unsigned limit = 2; 9585 9586 /* 9587 * x86 is limited to one NMI running, and one NMI pending after it. 9588 * If an NMI is already in progress, limit further NMIs to just one. 9589 * Otherwise, allow two (and we'll inject the first one immediately). 9590 */ 9591 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) 9592 limit = 1; 9593 9594 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 9595 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 9596 kvm_make_request(KVM_REQ_EVENT, vcpu); 9597 } 9598 9599 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 9600 { 9601 u32 flags = 0; 9602 flags |= seg->g << 23; 9603 flags |= seg->db << 22; 9604 flags |= seg->l << 21; 9605 flags |= seg->avl << 20; 9606 flags |= seg->present << 15; 9607 flags |= seg->dpl << 13; 9608 flags |= seg->s << 12; 9609 flags |= seg->type << 8; 9610 return flags; 9611 } 9612 9613 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 9614 { 9615 struct kvm_segment seg; 9616 int offset; 9617 9618 kvm_get_segment(vcpu, &seg, n); 9619 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 9620 9621 if (n < 3) 9622 offset = 0x7f84 + n * 12; 9623 else 9624 offset = 0x7f2c + (n - 3) * 12; 9625 9626 put_smstate(u32, buf, offset + 8, seg.base); 9627 put_smstate(u32, buf, offset + 4, seg.limit); 9628 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 9629 } 9630 9631 #ifdef CONFIG_X86_64 9632 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 9633 { 9634 struct kvm_segment seg; 9635 int offset; 9636 u16 flags; 9637 9638 kvm_get_segment(vcpu, &seg, n); 9639 offset = 0x7e00 + n * 16; 9640 9641 flags = enter_smm_get_segment_flags(&seg) >> 8; 9642 put_smstate(u16, buf, offset, seg.selector); 9643 put_smstate(u16, buf, offset + 2, flags); 9644 put_smstate(u32, buf, offset + 4, seg.limit); 9645 put_smstate(u64, buf, offset + 8, seg.base); 9646 } 9647 #endif 9648 9649 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 9650 { 9651 struct desc_ptr dt; 9652 struct kvm_segment seg; 9653 unsigned long val; 9654 int i; 9655 9656 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 9657 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 9658 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 9659 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 9660 9661 for (i = 0; i < 8; i++) 9662 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i)); 9663 9664 kvm_get_dr(vcpu, 6, &val); 9665 put_smstate(u32, buf, 0x7fcc, (u32)val); 9666 kvm_get_dr(vcpu, 7, &val); 9667 put_smstate(u32, buf, 0x7fc8, (u32)val); 9668 9669 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 9670 put_smstate(u32, buf, 0x7fc4, seg.selector); 9671 put_smstate(u32, buf, 0x7f64, seg.base); 9672 put_smstate(u32, buf, 0x7f60, seg.limit); 9673 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 9674 9675 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 9676 put_smstate(u32, buf, 0x7fc0, seg.selector); 9677 put_smstate(u32, buf, 0x7f80, seg.base); 9678 put_smstate(u32, buf, 0x7f7c, seg.limit); 9679 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 9680 9681 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9682 put_smstate(u32, buf, 0x7f74, dt.address); 9683 put_smstate(u32, buf, 0x7f70, dt.size); 9684 9685 static_call(kvm_x86_get_idt)(vcpu, &dt); 9686 put_smstate(u32, buf, 0x7f58, dt.address); 9687 put_smstate(u32, buf, 0x7f54, dt.size); 9688 9689 for (i = 0; i < 6; i++) 9690 enter_smm_save_seg_32(vcpu, buf, i); 9691 9692 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 9693 9694 /* revision id */ 9695 put_smstate(u32, buf, 0x7efc, 0x00020000); 9696 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 9697 } 9698 9699 #ifdef CONFIG_X86_64 9700 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 9701 { 9702 struct desc_ptr dt; 9703 struct kvm_segment seg; 9704 unsigned long val; 9705 int i; 9706 9707 for (i = 0; i < 16; i++) 9708 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i)); 9709 9710 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 9711 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 9712 9713 kvm_get_dr(vcpu, 6, &val); 9714 put_smstate(u64, buf, 0x7f68, val); 9715 kvm_get_dr(vcpu, 7, &val); 9716 put_smstate(u64, buf, 0x7f60, val); 9717 9718 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 9719 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 9720 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 9721 9722 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 9723 9724 /* revision id */ 9725 put_smstate(u32, buf, 0x7efc, 0x00020064); 9726 9727 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 9728 9729 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 9730 put_smstate(u16, buf, 0x7e90, seg.selector); 9731 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 9732 put_smstate(u32, buf, 0x7e94, seg.limit); 9733 put_smstate(u64, buf, 0x7e98, seg.base); 9734 9735 static_call(kvm_x86_get_idt)(vcpu, &dt); 9736 put_smstate(u32, buf, 0x7e84, dt.size); 9737 put_smstate(u64, buf, 0x7e88, dt.address); 9738 9739 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 9740 put_smstate(u16, buf, 0x7e70, seg.selector); 9741 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 9742 put_smstate(u32, buf, 0x7e74, seg.limit); 9743 put_smstate(u64, buf, 0x7e78, seg.base); 9744 9745 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9746 put_smstate(u32, buf, 0x7e64, dt.size); 9747 put_smstate(u64, buf, 0x7e68, dt.address); 9748 9749 for (i = 0; i < 6; i++) 9750 enter_smm_save_seg_64(vcpu, buf, i); 9751 } 9752 #endif 9753 9754 static void enter_smm(struct kvm_vcpu *vcpu) 9755 { 9756 struct kvm_segment cs, ds; 9757 struct desc_ptr dt; 9758 unsigned long cr0; 9759 char buf[512]; 9760 9761 memset(buf, 0, 512); 9762 #ifdef CONFIG_X86_64 9763 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 9764 enter_smm_save_state_64(vcpu, buf); 9765 else 9766 #endif 9767 enter_smm_save_state_32(vcpu, buf); 9768 9769 /* 9770 * Give enter_smm() a chance to make ISA-specific changes to the vCPU 9771 * state (e.g. leave guest mode) after we've saved the state into the 9772 * SMM state-save area. 9773 */ 9774 static_call(kvm_x86_enter_smm)(vcpu, buf); 9775 9776 kvm_smm_changed(vcpu, true); 9777 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 9778 9779 if (static_call(kvm_x86_get_nmi_mask)(vcpu)) 9780 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 9781 else 9782 static_call(kvm_x86_set_nmi_mask)(vcpu, true); 9783 9784 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 9785 kvm_rip_write(vcpu, 0x8000); 9786 9787 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 9788 static_call(kvm_x86_set_cr0)(vcpu, cr0); 9789 vcpu->arch.cr0 = cr0; 9790 9791 static_call(kvm_x86_set_cr4)(vcpu, 0); 9792 9793 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 9794 dt.address = dt.size = 0; 9795 static_call(kvm_x86_set_idt)(vcpu, &dt); 9796 9797 kvm_set_dr(vcpu, 7, DR7_FIXED_1); 9798 9799 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 9800 cs.base = vcpu->arch.smbase; 9801 9802 ds.selector = 0; 9803 ds.base = 0; 9804 9805 cs.limit = ds.limit = 0xffffffff; 9806 cs.type = ds.type = 0x3; 9807 cs.dpl = ds.dpl = 0; 9808 cs.db = ds.db = 0; 9809 cs.s = ds.s = 1; 9810 cs.l = ds.l = 0; 9811 cs.g = ds.g = 1; 9812 cs.avl = ds.avl = 0; 9813 cs.present = ds.present = 1; 9814 cs.unusable = ds.unusable = 0; 9815 cs.padding = ds.padding = 0; 9816 9817 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 9818 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 9819 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 9820 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 9821 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 9822 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 9823 9824 #ifdef CONFIG_X86_64 9825 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 9826 static_call(kvm_x86_set_efer)(vcpu, 0); 9827 #endif 9828 9829 kvm_update_cpuid_runtime(vcpu); 9830 kvm_mmu_reset_context(vcpu); 9831 } 9832 9833 static void process_smi(struct kvm_vcpu *vcpu) 9834 { 9835 vcpu->arch.smi_pending = true; 9836 kvm_make_request(KVM_REQ_EVENT, vcpu); 9837 } 9838 9839 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 9840 unsigned long *vcpu_bitmap) 9841 { 9842 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap); 9843 } 9844 9845 void kvm_make_scan_ioapic_request(struct kvm *kvm) 9846 { 9847 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 9848 } 9849 9850 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 9851 { 9852 bool activate; 9853 9854 if (!lapic_in_kernel(vcpu)) 9855 return; 9856 9857 down_read(&vcpu->kvm->arch.apicv_update_lock); 9858 preempt_disable(); 9859 9860 activate = kvm_vcpu_apicv_activated(vcpu); 9861 9862 if (vcpu->arch.apicv_active == activate) 9863 goto out; 9864 9865 vcpu->arch.apicv_active = activate; 9866 kvm_apic_update_apicv(vcpu); 9867 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); 9868 9869 /* 9870 * When APICv gets disabled, we may still have injected interrupts 9871 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was 9872 * still active when the interrupt got accepted. Make sure 9873 * inject_pending_event() is called to check for that. 9874 */ 9875 if (!vcpu->arch.apicv_active) 9876 kvm_make_request(KVM_REQ_EVENT, vcpu); 9877 9878 out: 9879 preempt_enable(); 9880 up_read(&vcpu->kvm->arch.apicv_update_lock); 9881 } 9882 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); 9883 9884 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, 9885 enum kvm_apicv_inhibit reason, bool set) 9886 { 9887 unsigned long old, new; 9888 9889 lockdep_assert_held_write(&kvm->arch.apicv_update_lock); 9890 9891 if (!static_call(kvm_x86_check_apicv_inhibit_reasons)(reason)) 9892 return; 9893 9894 old = new = kvm->arch.apicv_inhibit_reasons; 9895 9896 set_or_clear_apicv_inhibit(&new, reason, set); 9897 9898 if (!!old != !!new) { 9899 /* 9900 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid 9901 * false positives in the sanity check WARN in svm_vcpu_run(). 9902 * This task will wait for all vCPUs to ack the kick IRQ before 9903 * updating apicv_inhibit_reasons, and all other vCPUs will 9904 * block on acquiring apicv_update_lock so that vCPUs can't 9905 * redo svm_vcpu_run() without seeing the new inhibit state. 9906 * 9907 * Note, holding apicv_update_lock and taking it in the read 9908 * side (handling the request) also prevents other vCPUs from 9909 * servicing the request with a stale apicv_inhibit_reasons. 9910 */ 9911 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); 9912 kvm->arch.apicv_inhibit_reasons = new; 9913 if (new) { 9914 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE); 9915 kvm_zap_gfn_range(kvm, gfn, gfn+1); 9916 } 9917 } else { 9918 kvm->arch.apicv_inhibit_reasons = new; 9919 } 9920 } 9921 9922 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, 9923 enum kvm_apicv_inhibit reason, bool set) 9924 { 9925 if (!enable_apicv) 9926 return; 9927 9928 down_write(&kvm->arch.apicv_update_lock); 9929 __kvm_set_or_clear_apicv_inhibit(kvm, reason, set); 9930 up_write(&kvm->arch.apicv_update_lock); 9931 } 9932 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit); 9933 9934 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 9935 { 9936 if (!kvm_apic_present(vcpu)) 9937 return; 9938 9939 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 9940 9941 if (irqchip_split(vcpu->kvm)) 9942 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 9943 else { 9944 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 9945 if (ioapic_in_kernel(vcpu->kvm)) 9946 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 9947 } 9948 9949 if (is_guest_mode(vcpu)) 9950 vcpu->arch.load_eoi_exitmap_pending = true; 9951 else 9952 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 9953 } 9954 9955 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 9956 { 9957 u64 eoi_exit_bitmap[4]; 9958 9959 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 9960 return; 9961 9962 if (to_hv_vcpu(vcpu)) { 9963 bitmap_or((ulong *)eoi_exit_bitmap, 9964 vcpu->arch.ioapic_handled_vectors, 9965 to_hv_synic(vcpu)->vec_bitmap, 256); 9966 static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); 9967 return; 9968 } 9969 9970 static_call_cond(kvm_x86_load_eoi_exitmap)( 9971 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors); 9972 } 9973 9974 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 9975 unsigned long start, unsigned long end) 9976 { 9977 unsigned long apic_address; 9978 9979 /* 9980 * The physical address of apic access page is stored in the VMCS. 9981 * Update it when it becomes invalid. 9982 */ 9983 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 9984 if (start <= apic_address && apic_address < end) 9985 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 9986 } 9987 9988 void kvm_arch_guest_memory_reclaimed(struct kvm *kvm) 9989 { 9990 static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm); 9991 } 9992 9993 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 9994 { 9995 if (!lapic_in_kernel(vcpu)) 9996 return; 9997 9998 static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu); 9999 } 10000 10001 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 10002 { 10003 smp_send_reschedule(vcpu->cpu); 10004 } 10005 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 10006 10007 /* 10008 * Called within kvm->srcu read side. 10009 * Returns 1 to let vcpu_run() continue the guest execution loop without 10010 * exiting to the userspace. Otherwise, the value will be returned to the 10011 * userspace. 10012 */ 10013 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 10014 { 10015 int r; 10016 bool req_int_win = 10017 dm_request_for_irq_injection(vcpu) && 10018 kvm_cpu_accept_dm_intr(vcpu); 10019 fastpath_t exit_fastpath; 10020 10021 bool req_immediate_exit = false; 10022 10023 /* Forbid vmenter if vcpu dirty ring is soft-full */ 10024 if (unlikely(vcpu->kvm->dirty_ring_size && 10025 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { 10026 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; 10027 trace_kvm_dirty_ring_exit(vcpu); 10028 r = 0; 10029 goto out; 10030 } 10031 10032 if (kvm_request_pending(vcpu)) { 10033 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) { 10034 r = -EIO; 10035 goto out; 10036 } 10037 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { 10038 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { 10039 r = 0; 10040 goto out; 10041 } 10042 } 10043 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu)) 10044 kvm_mmu_free_obsolete_roots(vcpu); 10045 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 10046 __kvm_migrate_timers(vcpu); 10047 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 10048 kvm_update_masterclock(vcpu->kvm); 10049 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 10050 kvm_gen_kvmclock_update(vcpu); 10051 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 10052 r = kvm_guest_time_update(vcpu); 10053 if (unlikely(r)) 10054 goto out; 10055 } 10056 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 10057 kvm_mmu_sync_roots(vcpu); 10058 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) 10059 kvm_mmu_load_pgd(vcpu); 10060 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { 10061 kvm_vcpu_flush_tlb_all(vcpu); 10062 10063 /* Flushing all ASIDs flushes the current ASID... */ 10064 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 10065 } 10066 kvm_service_local_tlb_flush_requests(vcpu); 10067 10068 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 10069 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 10070 r = 0; 10071 goto out; 10072 } 10073 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 10074 if (is_guest_mode(vcpu)) { 10075 kvm_x86_ops.nested_ops->triple_fault(vcpu); 10076 } else { 10077 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 10078 vcpu->mmio_needed = 0; 10079 r = 0; 10080 goto out; 10081 } 10082 } 10083 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 10084 /* Page is swapped out. Do synthetic halt */ 10085 vcpu->arch.apf.halted = true; 10086 r = 1; 10087 goto out; 10088 } 10089 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 10090 record_steal_time(vcpu); 10091 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 10092 process_smi(vcpu); 10093 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 10094 process_nmi(vcpu); 10095 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 10096 kvm_pmu_handle_event(vcpu); 10097 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 10098 kvm_pmu_deliver_pmi(vcpu); 10099 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 10100 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 10101 if (test_bit(vcpu->arch.pending_ioapic_eoi, 10102 vcpu->arch.ioapic_handled_vectors)) { 10103 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 10104 vcpu->run->eoi.vector = 10105 vcpu->arch.pending_ioapic_eoi; 10106 r = 0; 10107 goto out; 10108 } 10109 } 10110 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 10111 vcpu_scan_ioapic(vcpu); 10112 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 10113 vcpu_load_eoi_exitmap(vcpu); 10114 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 10115 kvm_vcpu_reload_apic_access_page(vcpu); 10116 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 10117 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 10118 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 10119 vcpu->run->system_event.ndata = 0; 10120 r = 0; 10121 goto out; 10122 } 10123 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 10124 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 10125 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 10126 vcpu->run->system_event.ndata = 0; 10127 r = 0; 10128 goto out; 10129 } 10130 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 10131 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); 10132 10133 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 10134 vcpu->run->hyperv = hv_vcpu->exit; 10135 r = 0; 10136 goto out; 10137 } 10138 10139 /* 10140 * KVM_REQ_HV_STIMER has to be processed after 10141 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 10142 * depend on the guest clock being up-to-date 10143 */ 10144 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 10145 kvm_hv_process_stimers(vcpu); 10146 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 10147 kvm_vcpu_update_apicv(vcpu); 10148 if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) 10149 kvm_check_async_pf_completion(vcpu); 10150 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) 10151 static_call(kvm_x86_msr_filter_changed)(vcpu); 10152 10153 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) 10154 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); 10155 } 10156 10157 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || 10158 kvm_xen_has_interrupt(vcpu)) { 10159 ++vcpu->stat.req_event; 10160 r = kvm_apic_accept_events(vcpu); 10161 if (r < 0) { 10162 r = 0; 10163 goto out; 10164 } 10165 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 10166 r = 1; 10167 goto out; 10168 } 10169 10170 r = inject_pending_event(vcpu, &req_immediate_exit); 10171 if (r < 0) { 10172 r = 0; 10173 goto out; 10174 } 10175 if (req_int_win) 10176 static_call(kvm_x86_enable_irq_window)(vcpu); 10177 10178 if (kvm_lapic_enabled(vcpu)) { 10179 update_cr8_intercept(vcpu); 10180 kvm_lapic_sync_to_vapic(vcpu); 10181 } 10182 } 10183 10184 r = kvm_mmu_reload(vcpu); 10185 if (unlikely(r)) { 10186 goto cancel_injection; 10187 } 10188 10189 preempt_disable(); 10190 10191 static_call(kvm_x86_prepare_switch_to_guest)(vcpu); 10192 10193 /* 10194 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 10195 * IPI are then delayed after guest entry, which ensures that they 10196 * result in virtual interrupt delivery. 10197 */ 10198 local_irq_disable(); 10199 10200 /* Store vcpu->apicv_active before vcpu->mode. */ 10201 smp_store_release(&vcpu->mode, IN_GUEST_MODE); 10202 10203 kvm_vcpu_srcu_read_unlock(vcpu); 10204 10205 /* 10206 * 1) We should set ->mode before checking ->requests. Please see 10207 * the comment in kvm_vcpu_exiting_guest_mode(). 10208 * 10209 * 2) For APICv, we should set ->mode before checking PID.ON. This 10210 * pairs with the memory barrier implicit in pi_test_and_set_on 10211 * (see vmx_deliver_posted_interrupt). 10212 * 10213 * 3) This also orders the write to mode from any reads to the page 10214 * tables done while the VCPU is running. Please see the comment 10215 * in kvm_flush_remote_tlbs. 10216 */ 10217 smp_mb__after_srcu_read_unlock(); 10218 10219 /* 10220 * Process pending posted interrupts to handle the case where the 10221 * notification IRQ arrived in the host, or was never sent (because the 10222 * target vCPU wasn't running). Do this regardless of the vCPU's APICv 10223 * status, KVM doesn't update assigned devices when APICv is inhibited, 10224 * i.e. they can post interrupts even if APICv is temporarily disabled. 10225 */ 10226 if (kvm_lapic_enabled(vcpu)) 10227 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 10228 10229 if (kvm_vcpu_exit_request(vcpu)) { 10230 vcpu->mode = OUTSIDE_GUEST_MODE; 10231 smp_wmb(); 10232 local_irq_enable(); 10233 preempt_enable(); 10234 kvm_vcpu_srcu_read_lock(vcpu); 10235 r = 1; 10236 goto cancel_injection; 10237 } 10238 10239 if (req_immediate_exit) { 10240 kvm_make_request(KVM_REQ_EVENT, vcpu); 10241 static_call(kvm_x86_request_immediate_exit)(vcpu); 10242 } 10243 10244 fpregs_assert_state_consistent(); 10245 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 10246 switch_fpu_return(); 10247 10248 if (vcpu->arch.guest_fpu.xfd_err) 10249 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err); 10250 10251 if (unlikely(vcpu->arch.switch_db_regs)) { 10252 set_debugreg(0, 7); 10253 set_debugreg(vcpu->arch.eff_db[0], 0); 10254 set_debugreg(vcpu->arch.eff_db[1], 1); 10255 set_debugreg(vcpu->arch.eff_db[2], 2); 10256 set_debugreg(vcpu->arch.eff_db[3], 3); 10257 } else if (unlikely(hw_breakpoint_active())) { 10258 set_debugreg(0, 7); 10259 } 10260 10261 guest_timing_enter_irqoff(); 10262 10263 for (;;) { 10264 /* 10265 * Assert that vCPU vs. VM APICv state is consistent. An APICv 10266 * update must kick and wait for all vCPUs before toggling the 10267 * per-VM state, and responsing vCPUs must wait for the update 10268 * to complete before servicing KVM_REQ_APICV_UPDATE. 10269 */ 10270 WARN_ON_ONCE(kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)); 10271 10272 exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu); 10273 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) 10274 break; 10275 10276 if (kvm_lapic_enabled(vcpu)) 10277 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 10278 10279 if (unlikely(kvm_vcpu_exit_request(vcpu))) { 10280 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; 10281 break; 10282 } 10283 } 10284 10285 /* 10286 * Do this here before restoring debug registers on the host. And 10287 * since we do this before handling the vmexit, a DR access vmexit 10288 * can (a) read the correct value of the debug registers, (b) set 10289 * KVM_DEBUGREG_WONT_EXIT again. 10290 */ 10291 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 10292 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 10293 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); 10294 kvm_update_dr0123(vcpu); 10295 kvm_update_dr7(vcpu); 10296 } 10297 10298 /* 10299 * If the guest has used debug registers, at least dr7 10300 * will be disabled while returning to the host. 10301 * If we don't have active breakpoints in the host, we don't 10302 * care about the messed up debug address registers. But if 10303 * we have some of them active, restore the old state. 10304 */ 10305 if (hw_breakpoint_active()) 10306 hw_breakpoint_restore(); 10307 10308 vcpu->arch.last_vmentry_cpu = vcpu->cpu; 10309 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 10310 10311 vcpu->mode = OUTSIDE_GUEST_MODE; 10312 smp_wmb(); 10313 10314 /* 10315 * Sync xfd before calling handle_exit_irqoff() which may 10316 * rely on the fact that guest_fpu::xfd is up-to-date (e.g. 10317 * in #NM irqoff handler). 10318 */ 10319 if (vcpu->arch.xfd_no_write_intercept) 10320 fpu_sync_guest_vmexit_xfd_state(); 10321 10322 static_call(kvm_x86_handle_exit_irqoff)(vcpu); 10323 10324 if (vcpu->arch.guest_fpu.xfd_err) 10325 wrmsrl(MSR_IA32_XFD_ERR, 0); 10326 10327 /* 10328 * Consume any pending interrupts, including the possible source of 10329 * VM-Exit on SVM and any ticks that occur between VM-Exit and now. 10330 * An instruction is required after local_irq_enable() to fully unblock 10331 * interrupts on processors that implement an interrupt shadow, the 10332 * stat.exits increment will do nicely. 10333 */ 10334 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ); 10335 local_irq_enable(); 10336 ++vcpu->stat.exits; 10337 local_irq_disable(); 10338 kvm_after_interrupt(vcpu); 10339 10340 /* 10341 * Wait until after servicing IRQs to account guest time so that any 10342 * ticks that occurred while running the guest are properly accounted 10343 * to the guest. Waiting until IRQs are enabled degrades the accuracy 10344 * of accounting via context tracking, but the loss of accuracy is 10345 * acceptable for all known use cases. 10346 */ 10347 guest_timing_exit_irqoff(); 10348 10349 local_irq_enable(); 10350 preempt_enable(); 10351 10352 kvm_vcpu_srcu_read_lock(vcpu); 10353 10354 /* 10355 * Profile KVM exit RIPs: 10356 */ 10357 if (unlikely(prof_on == KVM_PROFILING)) { 10358 unsigned long rip = kvm_rip_read(vcpu); 10359 profile_hit(KVM_PROFILING, (void *)rip); 10360 } 10361 10362 if (unlikely(vcpu->arch.tsc_always_catchup)) 10363 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 10364 10365 if (vcpu->arch.apic_attention) 10366 kvm_lapic_sync_from_vapic(vcpu); 10367 10368 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); 10369 return r; 10370 10371 cancel_injection: 10372 if (req_immediate_exit) 10373 kvm_make_request(KVM_REQ_EVENT, vcpu); 10374 static_call(kvm_x86_cancel_injection)(vcpu); 10375 if (unlikely(vcpu->arch.apic_attention)) 10376 kvm_lapic_sync_from_vapic(vcpu); 10377 out: 10378 return r; 10379 } 10380 10381 /* Called within kvm->srcu read side. */ 10382 static inline int vcpu_block(struct kvm_vcpu *vcpu) 10383 { 10384 bool hv_timer; 10385 10386 if (!kvm_arch_vcpu_runnable(vcpu)) { 10387 /* 10388 * Switch to the software timer before halt-polling/blocking as 10389 * the guest's timer may be a break event for the vCPU, and the 10390 * hypervisor timer runs only when the CPU is in guest mode. 10391 * Switch before halt-polling so that KVM recognizes an expired 10392 * timer before blocking. 10393 */ 10394 hv_timer = kvm_lapic_hv_timer_in_use(vcpu); 10395 if (hv_timer) 10396 kvm_lapic_switch_to_sw_timer(vcpu); 10397 10398 kvm_vcpu_srcu_read_unlock(vcpu); 10399 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) 10400 kvm_vcpu_halt(vcpu); 10401 else 10402 kvm_vcpu_block(vcpu); 10403 kvm_vcpu_srcu_read_lock(vcpu); 10404 10405 if (hv_timer) 10406 kvm_lapic_switch_to_hv_timer(vcpu); 10407 10408 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 10409 return 1; 10410 } 10411 10412 if (kvm_apic_accept_events(vcpu) < 0) 10413 return 0; 10414 switch(vcpu->arch.mp_state) { 10415 case KVM_MP_STATE_HALTED: 10416 case KVM_MP_STATE_AP_RESET_HOLD: 10417 vcpu->arch.pv.pv_unhalted = false; 10418 vcpu->arch.mp_state = 10419 KVM_MP_STATE_RUNNABLE; 10420 fallthrough; 10421 case KVM_MP_STATE_RUNNABLE: 10422 vcpu->arch.apf.halted = false; 10423 break; 10424 case KVM_MP_STATE_INIT_RECEIVED: 10425 break; 10426 default: 10427 return -EINTR; 10428 } 10429 return 1; 10430 } 10431 10432 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 10433 { 10434 if (is_guest_mode(vcpu)) 10435 kvm_check_nested_events(vcpu); 10436 10437 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 10438 !vcpu->arch.apf.halted); 10439 } 10440 10441 /* Called within kvm->srcu read side. */ 10442 static int vcpu_run(struct kvm_vcpu *vcpu) 10443 { 10444 int r; 10445 10446 vcpu->arch.l1tf_flush_l1d = true; 10447 10448 for (;;) { 10449 /* 10450 * If another guest vCPU requests a PV TLB flush in the middle 10451 * of instruction emulation, the rest of the emulation could 10452 * use a stale page translation. Assume that any code after 10453 * this point can start executing an instruction. 10454 */ 10455 vcpu->arch.at_instruction_boundary = false; 10456 if (kvm_vcpu_running(vcpu)) { 10457 r = vcpu_enter_guest(vcpu); 10458 } else { 10459 r = vcpu_block(vcpu); 10460 } 10461 10462 if (r <= 0) 10463 break; 10464 10465 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); 10466 if (kvm_xen_has_pending_events(vcpu)) 10467 kvm_xen_inject_pending_events(vcpu); 10468 10469 if (kvm_cpu_has_pending_timer(vcpu)) 10470 kvm_inject_pending_timer_irqs(vcpu); 10471 10472 if (dm_request_for_irq_injection(vcpu) && 10473 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 10474 r = 0; 10475 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 10476 ++vcpu->stat.request_irq_exits; 10477 break; 10478 } 10479 10480 if (__xfer_to_guest_mode_work_pending()) { 10481 kvm_vcpu_srcu_read_unlock(vcpu); 10482 r = xfer_to_guest_mode_handle_work(vcpu); 10483 kvm_vcpu_srcu_read_lock(vcpu); 10484 if (r) 10485 return r; 10486 } 10487 } 10488 10489 return r; 10490 } 10491 10492 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 10493 { 10494 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 10495 } 10496 10497 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 10498 { 10499 BUG_ON(!vcpu->arch.pio.count); 10500 10501 return complete_emulated_io(vcpu); 10502 } 10503 10504 /* 10505 * Implements the following, as a state machine: 10506 * 10507 * read: 10508 * for each fragment 10509 * for each mmio piece in the fragment 10510 * write gpa, len 10511 * exit 10512 * copy data 10513 * execute insn 10514 * 10515 * write: 10516 * for each fragment 10517 * for each mmio piece in the fragment 10518 * write gpa, len 10519 * copy data 10520 * exit 10521 */ 10522 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 10523 { 10524 struct kvm_run *run = vcpu->run; 10525 struct kvm_mmio_fragment *frag; 10526 unsigned len; 10527 10528 BUG_ON(!vcpu->mmio_needed); 10529 10530 /* Complete previous fragment */ 10531 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 10532 len = min(8u, frag->len); 10533 if (!vcpu->mmio_is_write) 10534 memcpy(frag->data, run->mmio.data, len); 10535 10536 if (frag->len <= 8) { 10537 /* Switch to the next fragment. */ 10538 frag++; 10539 vcpu->mmio_cur_fragment++; 10540 } else { 10541 /* Go forward to the next mmio piece. */ 10542 frag->data += len; 10543 frag->gpa += len; 10544 frag->len -= len; 10545 } 10546 10547 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 10548 vcpu->mmio_needed = 0; 10549 10550 /* FIXME: return into emulator if single-stepping. */ 10551 if (vcpu->mmio_is_write) 10552 return 1; 10553 vcpu->mmio_read_completed = 1; 10554 return complete_emulated_io(vcpu); 10555 } 10556 10557 run->exit_reason = KVM_EXIT_MMIO; 10558 run->mmio.phys_addr = frag->gpa; 10559 if (vcpu->mmio_is_write) 10560 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 10561 run->mmio.len = min(8u, frag->len); 10562 run->mmio.is_write = vcpu->mmio_is_write; 10563 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 10564 return 0; 10565 } 10566 10567 /* Swap (qemu) user FPU context for the guest FPU context. */ 10568 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 10569 { 10570 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */ 10571 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true); 10572 trace_kvm_fpu(1); 10573 } 10574 10575 /* When vcpu_run ends, restore user space FPU context. */ 10576 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 10577 { 10578 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false); 10579 ++vcpu->stat.fpu_reload; 10580 trace_kvm_fpu(0); 10581 } 10582 10583 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 10584 { 10585 struct kvm_run *kvm_run = vcpu->run; 10586 int r; 10587 10588 vcpu_load(vcpu); 10589 kvm_sigset_activate(vcpu); 10590 kvm_run->flags = 0; 10591 kvm_load_guest_fpu(vcpu); 10592 10593 kvm_vcpu_srcu_read_lock(vcpu); 10594 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 10595 if (kvm_run->immediate_exit) { 10596 r = -EINTR; 10597 goto out; 10598 } 10599 /* 10600 * It should be impossible for the hypervisor timer to be in 10601 * use before KVM has ever run the vCPU. 10602 */ 10603 WARN_ON_ONCE(kvm_lapic_hv_timer_in_use(vcpu)); 10604 10605 kvm_vcpu_srcu_read_unlock(vcpu); 10606 kvm_vcpu_block(vcpu); 10607 kvm_vcpu_srcu_read_lock(vcpu); 10608 10609 if (kvm_apic_accept_events(vcpu) < 0) { 10610 r = 0; 10611 goto out; 10612 } 10613 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 10614 r = -EAGAIN; 10615 if (signal_pending(current)) { 10616 r = -EINTR; 10617 kvm_run->exit_reason = KVM_EXIT_INTR; 10618 ++vcpu->stat.signal_exits; 10619 } 10620 goto out; 10621 } 10622 10623 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) || 10624 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) { 10625 r = -EINVAL; 10626 goto out; 10627 } 10628 10629 if (kvm_run->kvm_dirty_regs) { 10630 r = sync_regs(vcpu); 10631 if (r != 0) 10632 goto out; 10633 } 10634 10635 /* re-sync apic's tpr */ 10636 if (!lapic_in_kernel(vcpu)) { 10637 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 10638 r = -EINVAL; 10639 goto out; 10640 } 10641 } 10642 10643 if (unlikely(vcpu->arch.complete_userspace_io)) { 10644 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 10645 vcpu->arch.complete_userspace_io = NULL; 10646 r = cui(vcpu); 10647 if (r <= 0) 10648 goto out; 10649 } else 10650 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 10651 10652 if (kvm_run->immediate_exit) { 10653 r = -EINTR; 10654 goto out; 10655 } 10656 10657 r = static_call(kvm_x86_vcpu_pre_run)(vcpu); 10658 if (r <= 0) 10659 goto out; 10660 10661 r = vcpu_run(vcpu); 10662 10663 out: 10664 kvm_put_guest_fpu(vcpu); 10665 if (kvm_run->kvm_valid_regs) 10666 store_regs(vcpu); 10667 post_kvm_run_save(vcpu); 10668 kvm_vcpu_srcu_read_unlock(vcpu); 10669 10670 kvm_sigset_deactivate(vcpu); 10671 vcpu_put(vcpu); 10672 return r; 10673 } 10674 10675 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10676 { 10677 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 10678 /* 10679 * We are here if userspace calls get_regs() in the middle of 10680 * instruction emulation. Registers state needs to be copied 10681 * back from emulation context to vcpu. Userspace shouldn't do 10682 * that usually, but some bad designed PV devices (vmware 10683 * backdoor interface) need this to work 10684 */ 10685 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); 10686 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 10687 } 10688 regs->rax = kvm_rax_read(vcpu); 10689 regs->rbx = kvm_rbx_read(vcpu); 10690 regs->rcx = kvm_rcx_read(vcpu); 10691 regs->rdx = kvm_rdx_read(vcpu); 10692 regs->rsi = kvm_rsi_read(vcpu); 10693 regs->rdi = kvm_rdi_read(vcpu); 10694 regs->rsp = kvm_rsp_read(vcpu); 10695 regs->rbp = kvm_rbp_read(vcpu); 10696 #ifdef CONFIG_X86_64 10697 regs->r8 = kvm_r8_read(vcpu); 10698 regs->r9 = kvm_r9_read(vcpu); 10699 regs->r10 = kvm_r10_read(vcpu); 10700 regs->r11 = kvm_r11_read(vcpu); 10701 regs->r12 = kvm_r12_read(vcpu); 10702 regs->r13 = kvm_r13_read(vcpu); 10703 regs->r14 = kvm_r14_read(vcpu); 10704 regs->r15 = kvm_r15_read(vcpu); 10705 #endif 10706 10707 regs->rip = kvm_rip_read(vcpu); 10708 regs->rflags = kvm_get_rflags(vcpu); 10709 } 10710 10711 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10712 { 10713 vcpu_load(vcpu); 10714 __get_regs(vcpu, regs); 10715 vcpu_put(vcpu); 10716 return 0; 10717 } 10718 10719 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10720 { 10721 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 10722 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 10723 10724 kvm_rax_write(vcpu, regs->rax); 10725 kvm_rbx_write(vcpu, regs->rbx); 10726 kvm_rcx_write(vcpu, regs->rcx); 10727 kvm_rdx_write(vcpu, regs->rdx); 10728 kvm_rsi_write(vcpu, regs->rsi); 10729 kvm_rdi_write(vcpu, regs->rdi); 10730 kvm_rsp_write(vcpu, regs->rsp); 10731 kvm_rbp_write(vcpu, regs->rbp); 10732 #ifdef CONFIG_X86_64 10733 kvm_r8_write(vcpu, regs->r8); 10734 kvm_r9_write(vcpu, regs->r9); 10735 kvm_r10_write(vcpu, regs->r10); 10736 kvm_r11_write(vcpu, regs->r11); 10737 kvm_r12_write(vcpu, regs->r12); 10738 kvm_r13_write(vcpu, regs->r13); 10739 kvm_r14_write(vcpu, regs->r14); 10740 kvm_r15_write(vcpu, regs->r15); 10741 #endif 10742 10743 kvm_rip_write(vcpu, regs->rip); 10744 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 10745 10746 vcpu->arch.exception.pending = false; 10747 10748 kvm_make_request(KVM_REQ_EVENT, vcpu); 10749 } 10750 10751 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10752 { 10753 vcpu_load(vcpu); 10754 __set_regs(vcpu, regs); 10755 vcpu_put(vcpu); 10756 return 0; 10757 } 10758 10759 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10760 { 10761 struct desc_ptr dt; 10762 10763 if (vcpu->arch.guest_state_protected) 10764 goto skip_protected_regs; 10765 10766 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 10767 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 10768 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 10769 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 10770 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 10771 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 10772 10773 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 10774 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 10775 10776 static_call(kvm_x86_get_idt)(vcpu, &dt); 10777 sregs->idt.limit = dt.size; 10778 sregs->idt.base = dt.address; 10779 static_call(kvm_x86_get_gdt)(vcpu, &dt); 10780 sregs->gdt.limit = dt.size; 10781 sregs->gdt.base = dt.address; 10782 10783 sregs->cr2 = vcpu->arch.cr2; 10784 sregs->cr3 = kvm_read_cr3(vcpu); 10785 10786 skip_protected_regs: 10787 sregs->cr0 = kvm_read_cr0(vcpu); 10788 sregs->cr4 = kvm_read_cr4(vcpu); 10789 sregs->cr8 = kvm_get_cr8(vcpu); 10790 sregs->efer = vcpu->arch.efer; 10791 sregs->apic_base = kvm_get_apic_base(vcpu); 10792 } 10793 10794 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10795 { 10796 __get_sregs_common(vcpu, sregs); 10797 10798 if (vcpu->arch.guest_state_protected) 10799 return; 10800 10801 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 10802 set_bit(vcpu->arch.interrupt.nr, 10803 (unsigned long *)sregs->interrupt_bitmap); 10804 } 10805 10806 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 10807 { 10808 int i; 10809 10810 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2); 10811 10812 if (vcpu->arch.guest_state_protected) 10813 return; 10814 10815 if (is_pae_paging(vcpu)) { 10816 for (i = 0 ; i < 4 ; i++) 10817 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i); 10818 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; 10819 } 10820 } 10821 10822 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 10823 struct kvm_sregs *sregs) 10824 { 10825 vcpu_load(vcpu); 10826 __get_sregs(vcpu, sregs); 10827 vcpu_put(vcpu); 10828 return 0; 10829 } 10830 10831 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 10832 struct kvm_mp_state *mp_state) 10833 { 10834 int r; 10835 10836 vcpu_load(vcpu); 10837 if (kvm_mpx_supported()) 10838 kvm_load_guest_fpu(vcpu); 10839 10840 r = kvm_apic_accept_events(vcpu); 10841 if (r < 0) 10842 goto out; 10843 r = 0; 10844 10845 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || 10846 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && 10847 vcpu->arch.pv.pv_unhalted) 10848 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 10849 else 10850 mp_state->mp_state = vcpu->arch.mp_state; 10851 10852 out: 10853 if (kvm_mpx_supported()) 10854 kvm_put_guest_fpu(vcpu); 10855 vcpu_put(vcpu); 10856 return r; 10857 } 10858 10859 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 10860 struct kvm_mp_state *mp_state) 10861 { 10862 int ret = -EINVAL; 10863 10864 vcpu_load(vcpu); 10865 10866 if (!lapic_in_kernel(vcpu) && 10867 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 10868 goto out; 10869 10870 /* 10871 * KVM_MP_STATE_INIT_RECEIVED means the processor is in 10872 * INIT state; latched init should be reported using 10873 * KVM_SET_VCPU_EVENTS, so reject it here. 10874 */ 10875 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && 10876 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 10877 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 10878 goto out; 10879 10880 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 10881 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 10882 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 10883 } else 10884 vcpu->arch.mp_state = mp_state->mp_state; 10885 kvm_make_request(KVM_REQ_EVENT, vcpu); 10886 10887 ret = 0; 10888 out: 10889 vcpu_put(vcpu); 10890 return ret; 10891 } 10892 10893 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 10894 int reason, bool has_error_code, u32 error_code) 10895 { 10896 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 10897 int ret; 10898 10899 init_emulate_ctxt(vcpu); 10900 10901 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 10902 has_error_code, error_code); 10903 if (ret) { 10904 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 10905 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 10906 vcpu->run->internal.ndata = 0; 10907 return 0; 10908 } 10909 10910 kvm_rip_write(vcpu, ctxt->eip); 10911 kvm_set_rflags(vcpu, ctxt->eflags); 10912 return 1; 10913 } 10914 EXPORT_SYMBOL_GPL(kvm_task_switch); 10915 10916 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10917 { 10918 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 10919 /* 10920 * When EFER.LME and CR0.PG are set, the processor is in 10921 * 64-bit mode (though maybe in a 32-bit code segment). 10922 * CR4.PAE and EFER.LMA must be set. 10923 */ 10924 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) 10925 return false; 10926 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) 10927 return false; 10928 } else { 10929 /* 10930 * Not in 64-bit mode: EFER.LMA is clear and the code 10931 * segment cannot be 64-bit. 10932 */ 10933 if (sregs->efer & EFER_LMA || sregs->cs.l) 10934 return false; 10935 } 10936 10937 return kvm_is_valid_cr4(vcpu, sregs->cr4); 10938 } 10939 10940 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs, 10941 int *mmu_reset_needed, bool update_pdptrs) 10942 { 10943 struct msr_data apic_base_msr; 10944 int idx; 10945 struct desc_ptr dt; 10946 10947 if (!kvm_is_valid_sregs(vcpu, sregs)) 10948 return -EINVAL; 10949 10950 apic_base_msr.data = sregs->apic_base; 10951 apic_base_msr.host_initiated = true; 10952 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 10953 return -EINVAL; 10954 10955 if (vcpu->arch.guest_state_protected) 10956 return 0; 10957 10958 dt.size = sregs->idt.limit; 10959 dt.address = sregs->idt.base; 10960 static_call(kvm_x86_set_idt)(vcpu, &dt); 10961 dt.size = sregs->gdt.limit; 10962 dt.address = sregs->gdt.base; 10963 static_call(kvm_x86_set_gdt)(vcpu, &dt); 10964 10965 vcpu->arch.cr2 = sregs->cr2; 10966 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 10967 vcpu->arch.cr3 = sregs->cr3; 10968 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 10969 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3); 10970 10971 kvm_set_cr8(vcpu, sregs->cr8); 10972 10973 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 10974 static_call(kvm_x86_set_efer)(vcpu, sregs->efer); 10975 10976 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 10977 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); 10978 vcpu->arch.cr0 = sregs->cr0; 10979 10980 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 10981 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); 10982 10983 if (update_pdptrs) { 10984 idx = srcu_read_lock(&vcpu->kvm->srcu); 10985 if (is_pae_paging(vcpu)) { 10986 load_pdptrs(vcpu, kvm_read_cr3(vcpu)); 10987 *mmu_reset_needed = 1; 10988 } 10989 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10990 } 10991 10992 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 10993 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 10994 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 10995 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 10996 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 10997 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 10998 10999 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 11000 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 11001 11002 update_cr8_intercept(vcpu); 11003 11004 /* Older userspace won't unhalt the vcpu on reset. */ 11005 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 11006 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 11007 !is_protmode(vcpu)) 11008 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 11009 11010 return 0; 11011 } 11012 11013 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 11014 { 11015 int pending_vec, max_bits; 11016 int mmu_reset_needed = 0; 11017 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true); 11018 11019 if (ret) 11020 return ret; 11021 11022 if (mmu_reset_needed) 11023 kvm_mmu_reset_context(vcpu); 11024 11025 max_bits = KVM_NR_INTERRUPTS; 11026 pending_vec = find_first_bit( 11027 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 11028 11029 if (pending_vec < max_bits) { 11030 kvm_queue_interrupt(vcpu, pending_vec, false); 11031 pr_debug("Set back pending irq %d\n", pending_vec); 11032 kvm_make_request(KVM_REQ_EVENT, vcpu); 11033 } 11034 return 0; 11035 } 11036 11037 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 11038 { 11039 int mmu_reset_needed = 0; 11040 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; 11041 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) && 11042 !(sregs2->efer & EFER_LMA); 11043 int i, ret; 11044 11045 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID) 11046 return -EINVAL; 11047 11048 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected)) 11049 return -EINVAL; 11050 11051 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2, 11052 &mmu_reset_needed, !valid_pdptrs); 11053 if (ret) 11054 return ret; 11055 11056 if (valid_pdptrs) { 11057 for (i = 0; i < 4 ; i++) 11058 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]); 11059 11060 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 11061 mmu_reset_needed = 1; 11062 vcpu->arch.pdptrs_from_userspace = true; 11063 } 11064 if (mmu_reset_needed) 11065 kvm_mmu_reset_context(vcpu); 11066 return 0; 11067 } 11068 11069 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 11070 struct kvm_sregs *sregs) 11071 { 11072 int ret; 11073 11074 vcpu_load(vcpu); 11075 ret = __set_sregs(vcpu, sregs); 11076 vcpu_put(vcpu); 11077 return ret; 11078 } 11079 11080 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm) 11081 { 11082 bool set = false; 11083 struct kvm_vcpu *vcpu; 11084 unsigned long i; 11085 11086 if (!enable_apicv) 11087 return; 11088 11089 down_write(&kvm->arch.apicv_update_lock); 11090 11091 kvm_for_each_vcpu(i, vcpu, kvm) { 11092 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) { 11093 set = true; 11094 break; 11095 } 11096 } 11097 __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set); 11098 up_write(&kvm->arch.apicv_update_lock); 11099 } 11100 11101 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 11102 struct kvm_guest_debug *dbg) 11103 { 11104 unsigned long rflags; 11105 int i, r; 11106 11107 if (vcpu->arch.guest_state_protected) 11108 return -EINVAL; 11109 11110 vcpu_load(vcpu); 11111 11112 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 11113 r = -EBUSY; 11114 if (vcpu->arch.exception.pending) 11115 goto out; 11116 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 11117 kvm_queue_exception(vcpu, DB_VECTOR); 11118 else 11119 kvm_queue_exception(vcpu, BP_VECTOR); 11120 } 11121 11122 /* 11123 * Read rflags as long as potentially injected trace flags are still 11124 * filtered out. 11125 */ 11126 rflags = kvm_get_rflags(vcpu); 11127 11128 vcpu->guest_debug = dbg->control; 11129 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 11130 vcpu->guest_debug = 0; 11131 11132 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 11133 for (i = 0; i < KVM_NR_DB_REGS; ++i) 11134 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 11135 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 11136 } else { 11137 for (i = 0; i < KVM_NR_DB_REGS; i++) 11138 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 11139 } 11140 kvm_update_dr7(vcpu); 11141 11142 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 11143 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); 11144 11145 /* 11146 * Trigger an rflags update that will inject or remove the trace 11147 * flags. 11148 */ 11149 kvm_set_rflags(vcpu, rflags); 11150 11151 static_call(kvm_x86_update_exception_bitmap)(vcpu); 11152 11153 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm); 11154 11155 r = 0; 11156 11157 out: 11158 vcpu_put(vcpu); 11159 return r; 11160 } 11161 11162 /* 11163 * Translate a guest virtual address to a guest physical address. 11164 */ 11165 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 11166 struct kvm_translation *tr) 11167 { 11168 unsigned long vaddr = tr->linear_address; 11169 gpa_t gpa; 11170 int idx; 11171 11172 vcpu_load(vcpu); 11173 11174 idx = srcu_read_lock(&vcpu->kvm->srcu); 11175 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 11176 srcu_read_unlock(&vcpu->kvm->srcu, idx); 11177 tr->physical_address = gpa; 11178 tr->valid = gpa != UNMAPPED_GVA; 11179 tr->writeable = 1; 11180 tr->usermode = 0; 11181 11182 vcpu_put(vcpu); 11183 return 0; 11184 } 11185 11186 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 11187 { 11188 struct fxregs_state *fxsave; 11189 11190 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 11191 return 0; 11192 11193 vcpu_load(vcpu); 11194 11195 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 11196 memcpy(fpu->fpr, fxsave->st_space, 128); 11197 fpu->fcw = fxsave->cwd; 11198 fpu->fsw = fxsave->swd; 11199 fpu->ftwx = fxsave->twd; 11200 fpu->last_opcode = fxsave->fop; 11201 fpu->last_ip = fxsave->rip; 11202 fpu->last_dp = fxsave->rdp; 11203 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 11204 11205 vcpu_put(vcpu); 11206 return 0; 11207 } 11208 11209 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 11210 { 11211 struct fxregs_state *fxsave; 11212 11213 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 11214 return 0; 11215 11216 vcpu_load(vcpu); 11217 11218 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 11219 11220 memcpy(fxsave->st_space, fpu->fpr, 128); 11221 fxsave->cwd = fpu->fcw; 11222 fxsave->swd = fpu->fsw; 11223 fxsave->twd = fpu->ftwx; 11224 fxsave->fop = fpu->last_opcode; 11225 fxsave->rip = fpu->last_ip; 11226 fxsave->rdp = fpu->last_dp; 11227 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 11228 11229 vcpu_put(vcpu); 11230 return 0; 11231 } 11232 11233 static void store_regs(struct kvm_vcpu *vcpu) 11234 { 11235 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 11236 11237 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 11238 __get_regs(vcpu, &vcpu->run->s.regs.regs); 11239 11240 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 11241 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 11242 11243 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 11244 kvm_vcpu_ioctl_x86_get_vcpu_events( 11245 vcpu, &vcpu->run->s.regs.events); 11246 } 11247 11248 static int sync_regs(struct kvm_vcpu *vcpu) 11249 { 11250 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 11251 __set_regs(vcpu, &vcpu->run->s.regs.regs); 11252 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 11253 } 11254 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 11255 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 11256 return -EINVAL; 11257 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 11258 } 11259 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 11260 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 11261 vcpu, &vcpu->run->s.regs.events)) 11262 return -EINVAL; 11263 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 11264 } 11265 11266 return 0; 11267 } 11268 11269 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 11270 { 11271 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 11272 pr_warn_once("kvm: SMP vm created on host with unstable TSC; " 11273 "guest TSC will not be reliable\n"); 11274 11275 return 0; 11276 } 11277 11278 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 11279 { 11280 struct page *page; 11281 int r; 11282 11283 vcpu->arch.last_vmentry_cpu = -1; 11284 vcpu->arch.regs_avail = ~0; 11285 vcpu->arch.regs_dirty = ~0; 11286 11287 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 11288 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 11289 else 11290 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 11291 11292 r = kvm_mmu_create(vcpu); 11293 if (r < 0) 11294 return r; 11295 11296 if (irqchip_in_kernel(vcpu->kvm)) { 11297 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 11298 if (r < 0) 11299 goto fail_mmu_destroy; 11300 11301 /* 11302 * Defer evaluating inhibits until the vCPU is first run, as 11303 * this vCPU will not get notified of any changes until this 11304 * vCPU is visible to other vCPUs (marked online and added to 11305 * the set of vCPUs). Opportunistically mark APICv active as 11306 * VMX in particularly is highly unlikely to have inhibits. 11307 * Ignore the current per-VM APICv state so that vCPU creation 11308 * is guaranteed to run with a deterministic value, the request 11309 * will ensure the vCPU gets the correct state before VM-Entry. 11310 */ 11311 if (enable_apicv) { 11312 vcpu->arch.apicv_active = true; 11313 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu); 11314 } 11315 } else 11316 static_branch_inc(&kvm_has_noapic_vcpu); 11317 11318 r = -ENOMEM; 11319 11320 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 11321 if (!page) 11322 goto fail_free_lapic; 11323 vcpu->arch.pio_data = page_address(page); 11324 11325 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 11326 GFP_KERNEL_ACCOUNT); 11327 if (!vcpu->arch.mce_banks) 11328 goto fail_free_pio_data; 11329 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 11330 11331 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 11332 GFP_KERNEL_ACCOUNT)) 11333 goto fail_free_mce_banks; 11334 11335 if (!alloc_emulate_ctxt(vcpu)) 11336 goto free_wbinvd_dirty_mask; 11337 11338 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) { 11339 pr_err("kvm: failed to allocate vcpu's fpu\n"); 11340 goto free_emulate_ctxt; 11341 } 11342 11343 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 11344 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 11345 11346 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 11347 11348 kvm_async_pf_hash_reset(vcpu); 11349 kvm_pmu_init(vcpu); 11350 11351 vcpu->arch.pending_external_vector = -1; 11352 vcpu->arch.preempted_in_kernel = false; 11353 11354 #if IS_ENABLED(CONFIG_HYPERV) 11355 vcpu->arch.hv_root_tdp = INVALID_PAGE; 11356 #endif 11357 11358 r = static_call(kvm_x86_vcpu_create)(vcpu); 11359 if (r) 11360 goto free_guest_fpu; 11361 11362 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 11363 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 11364 kvm_xen_init_vcpu(vcpu); 11365 kvm_vcpu_mtrr_init(vcpu); 11366 vcpu_load(vcpu); 11367 kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz); 11368 kvm_vcpu_reset(vcpu, false); 11369 kvm_init_mmu(vcpu); 11370 vcpu_put(vcpu); 11371 return 0; 11372 11373 free_guest_fpu: 11374 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 11375 free_emulate_ctxt: 11376 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 11377 free_wbinvd_dirty_mask: 11378 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 11379 fail_free_mce_banks: 11380 kfree(vcpu->arch.mce_banks); 11381 fail_free_pio_data: 11382 free_page((unsigned long)vcpu->arch.pio_data); 11383 fail_free_lapic: 11384 kvm_free_lapic(vcpu); 11385 fail_mmu_destroy: 11386 kvm_mmu_destroy(vcpu); 11387 return r; 11388 } 11389 11390 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 11391 { 11392 struct kvm *kvm = vcpu->kvm; 11393 11394 if (mutex_lock_killable(&vcpu->mutex)) 11395 return; 11396 vcpu_load(vcpu); 11397 kvm_synchronize_tsc(vcpu, 0); 11398 vcpu_put(vcpu); 11399 11400 /* poll control enabled by default */ 11401 vcpu->arch.msr_kvm_poll_control = 1; 11402 11403 mutex_unlock(&vcpu->mutex); 11404 11405 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) 11406 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 11407 KVMCLOCK_SYNC_PERIOD); 11408 } 11409 11410 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 11411 { 11412 int idx; 11413 11414 kvmclock_reset(vcpu); 11415 11416 static_call(kvm_x86_vcpu_free)(vcpu); 11417 11418 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 11419 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 11420 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 11421 11422 kvm_xen_destroy_vcpu(vcpu); 11423 kvm_hv_vcpu_uninit(vcpu); 11424 kvm_pmu_destroy(vcpu); 11425 kfree(vcpu->arch.mce_banks); 11426 kvm_free_lapic(vcpu); 11427 idx = srcu_read_lock(&vcpu->kvm->srcu); 11428 kvm_mmu_destroy(vcpu); 11429 srcu_read_unlock(&vcpu->kvm->srcu, idx); 11430 free_page((unsigned long)vcpu->arch.pio_data); 11431 kvfree(vcpu->arch.cpuid_entries); 11432 if (!lapic_in_kernel(vcpu)) 11433 static_branch_dec(&kvm_has_noapic_vcpu); 11434 } 11435 11436 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 11437 { 11438 struct kvm_cpuid_entry2 *cpuid_0x1; 11439 unsigned long old_cr0 = kvm_read_cr0(vcpu); 11440 unsigned long new_cr0; 11441 11442 /* 11443 * Several of the "set" flows, e.g. ->set_cr0(), read other registers 11444 * to handle side effects. RESET emulation hits those flows and relies 11445 * on emulated/virtualized registers, including those that are loaded 11446 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel 11447 * to detect improper or missing initialization. 11448 */ 11449 WARN_ON_ONCE(!init_event && 11450 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu))); 11451 11452 kvm_lapic_reset(vcpu, init_event); 11453 11454 vcpu->arch.hflags = 0; 11455 11456 vcpu->arch.smi_pending = 0; 11457 vcpu->arch.smi_count = 0; 11458 atomic_set(&vcpu->arch.nmi_queued, 0); 11459 vcpu->arch.nmi_pending = 0; 11460 vcpu->arch.nmi_injected = false; 11461 kvm_clear_interrupt_queue(vcpu); 11462 kvm_clear_exception_queue(vcpu); 11463 11464 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 11465 kvm_update_dr0123(vcpu); 11466 vcpu->arch.dr6 = DR6_ACTIVE_LOW; 11467 vcpu->arch.dr7 = DR7_FIXED_1; 11468 kvm_update_dr7(vcpu); 11469 11470 vcpu->arch.cr2 = 0; 11471 11472 kvm_make_request(KVM_REQ_EVENT, vcpu); 11473 vcpu->arch.apf.msr_en_val = 0; 11474 vcpu->arch.apf.msr_int_val = 0; 11475 vcpu->arch.st.msr_val = 0; 11476 11477 kvmclock_reset(vcpu); 11478 11479 kvm_clear_async_pf_completion_queue(vcpu); 11480 kvm_async_pf_hash_reset(vcpu); 11481 vcpu->arch.apf.halted = false; 11482 11483 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) { 11484 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate; 11485 11486 /* 11487 * To avoid have the INIT path from kvm_apic_has_events() that be 11488 * called with loaded FPU and does not let userspace fix the state. 11489 */ 11490 if (init_event) 11491 kvm_put_guest_fpu(vcpu); 11492 11493 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS); 11494 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR); 11495 11496 if (init_event) 11497 kvm_load_guest_fpu(vcpu); 11498 } 11499 11500 if (!init_event) { 11501 kvm_pmu_reset(vcpu); 11502 vcpu->arch.smbase = 0x30000; 11503 11504 vcpu->arch.msr_misc_features_enables = 0; 11505 11506 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP); 11507 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true); 11508 } 11509 11510 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */ 11511 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 11512 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP); 11513 11514 /* 11515 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon) 11516 * if no CPUID match is found. Note, it's impossible to get a match at 11517 * RESET since KVM emulates RESET before exposing the vCPU to userspace, 11518 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry 11519 * on RESET. But, go through the motions in case that's ever remedied. 11520 */ 11521 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1, 0); 11522 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600); 11523 11524 static_call(kvm_x86_vcpu_reset)(vcpu, init_event); 11525 11526 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 11527 kvm_rip_write(vcpu, 0xfff0); 11528 11529 vcpu->arch.cr3 = 0; 11530 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 11531 11532 /* 11533 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions 11534 * of Intel's SDM list CD/NW as being set on INIT, but they contradict 11535 * (or qualify) that with a footnote stating that CD/NW are preserved. 11536 */ 11537 new_cr0 = X86_CR0_ET; 11538 if (init_event) 11539 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD)); 11540 else 11541 new_cr0 |= X86_CR0_NW | X86_CR0_CD; 11542 11543 static_call(kvm_x86_set_cr0)(vcpu, new_cr0); 11544 static_call(kvm_x86_set_cr4)(vcpu, 0); 11545 static_call(kvm_x86_set_efer)(vcpu, 0); 11546 static_call(kvm_x86_update_exception_bitmap)(vcpu); 11547 11548 /* 11549 * On the standard CR0/CR4/EFER modification paths, there are several 11550 * complex conditions determining whether the MMU has to be reset and/or 11551 * which PCIDs have to be flushed. However, CR0.WP and the paging-related 11552 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush 11553 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as 11554 * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here. 11555 */ 11556 if (old_cr0 & X86_CR0_PG) { 11557 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 11558 kvm_mmu_reset_context(vcpu); 11559 } 11560 11561 /* 11562 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's 11563 * APM states the TLBs are untouched by INIT, but it also states that 11564 * the TLBs are flushed on "External initialization of the processor." 11565 * Flush the guest TLB regardless of vendor, there is no meaningful 11566 * benefit in relying on the guest to flush the TLB immediately after 11567 * INIT. A spurious TLB flush is benign and likely negligible from a 11568 * performance perspective. 11569 */ 11570 if (init_event) 11571 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 11572 } 11573 EXPORT_SYMBOL_GPL(kvm_vcpu_reset); 11574 11575 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 11576 { 11577 struct kvm_segment cs; 11578 11579 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 11580 cs.selector = vector << 8; 11581 cs.base = vector << 12; 11582 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 11583 kvm_rip_write(vcpu, 0); 11584 } 11585 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); 11586 11587 int kvm_arch_hardware_enable(void) 11588 { 11589 struct kvm *kvm; 11590 struct kvm_vcpu *vcpu; 11591 unsigned long i; 11592 int ret; 11593 u64 local_tsc; 11594 u64 max_tsc = 0; 11595 bool stable, backwards_tsc = false; 11596 11597 kvm_user_return_msr_cpu_online(); 11598 ret = static_call(kvm_x86_hardware_enable)(); 11599 if (ret != 0) 11600 return ret; 11601 11602 local_tsc = rdtsc(); 11603 stable = !kvm_check_tsc_unstable(); 11604 list_for_each_entry(kvm, &vm_list, vm_list) { 11605 kvm_for_each_vcpu(i, vcpu, kvm) { 11606 if (!stable && vcpu->cpu == smp_processor_id()) 11607 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 11608 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 11609 backwards_tsc = true; 11610 if (vcpu->arch.last_host_tsc > max_tsc) 11611 max_tsc = vcpu->arch.last_host_tsc; 11612 } 11613 } 11614 } 11615 11616 /* 11617 * Sometimes, even reliable TSCs go backwards. This happens on 11618 * platforms that reset TSC during suspend or hibernate actions, but 11619 * maintain synchronization. We must compensate. Fortunately, we can 11620 * detect that condition here, which happens early in CPU bringup, 11621 * before any KVM threads can be running. Unfortunately, we can't 11622 * bring the TSCs fully up to date with real time, as we aren't yet far 11623 * enough into CPU bringup that we know how much real time has actually 11624 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot 11625 * variables that haven't been updated yet. 11626 * 11627 * So we simply find the maximum observed TSC above, then record the 11628 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 11629 * the adjustment will be applied. Note that we accumulate 11630 * adjustments, in case multiple suspend cycles happen before some VCPU 11631 * gets a chance to run again. In the event that no KVM threads get a 11632 * chance to run, we will miss the entire elapsed period, as we'll have 11633 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 11634 * loose cycle time. This isn't too big a deal, since the loss will be 11635 * uniform across all VCPUs (not to mention the scenario is extremely 11636 * unlikely). It is possible that a second hibernate recovery happens 11637 * much faster than a first, causing the observed TSC here to be 11638 * smaller; this would require additional padding adjustment, which is 11639 * why we set last_host_tsc to the local tsc observed here. 11640 * 11641 * N.B. - this code below runs only on platforms with reliable TSC, 11642 * as that is the only way backwards_tsc is set above. Also note 11643 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 11644 * have the same delta_cyc adjustment applied if backwards_tsc 11645 * is detected. Note further, this adjustment is only done once, 11646 * as we reset last_host_tsc on all VCPUs to stop this from being 11647 * called multiple times (one for each physical CPU bringup). 11648 * 11649 * Platforms with unreliable TSCs don't have to deal with this, they 11650 * will be compensated by the logic in vcpu_load, which sets the TSC to 11651 * catchup mode. This will catchup all VCPUs to real time, but cannot 11652 * guarantee that they stay in perfect synchronization. 11653 */ 11654 if (backwards_tsc) { 11655 u64 delta_cyc = max_tsc - local_tsc; 11656 list_for_each_entry(kvm, &vm_list, vm_list) { 11657 kvm->arch.backwards_tsc_observed = true; 11658 kvm_for_each_vcpu(i, vcpu, kvm) { 11659 vcpu->arch.tsc_offset_adjustment += delta_cyc; 11660 vcpu->arch.last_host_tsc = local_tsc; 11661 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 11662 } 11663 11664 /* 11665 * We have to disable TSC offset matching.. if you were 11666 * booting a VM while issuing an S4 host suspend.... 11667 * you may have some problem. Solving this issue is 11668 * left as an exercise to the reader. 11669 */ 11670 kvm->arch.last_tsc_nsec = 0; 11671 kvm->arch.last_tsc_write = 0; 11672 } 11673 11674 } 11675 return 0; 11676 } 11677 11678 void kvm_arch_hardware_disable(void) 11679 { 11680 static_call(kvm_x86_hardware_disable)(); 11681 drop_user_return_notifiers(); 11682 } 11683 11684 static inline void kvm_ops_update(struct kvm_x86_init_ops *ops) 11685 { 11686 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); 11687 11688 #define __KVM_X86_OP(func) \ 11689 static_call_update(kvm_x86_##func, kvm_x86_ops.func); 11690 #define KVM_X86_OP(func) \ 11691 WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func) 11692 #define KVM_X86_OP_OPTIONAL __KVM_X86_OP 11693 #define KVM_X86_OP_OPTIONAL_RET0(func) \ 11694 static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \ 11695 (void *)__static_call_return0); 11696 #include <asm/kvm-x86-ops.h> 11697 #undef __KVM_X86_OP 11698 11699 kvm_pmu_ops_update(ops->pmu_ops); 11700 } 11701 11702 int kvm_arch_hardware_setup(void *opaque) 11703 { 11704 struct kvm_x86_init_ops *ops = opaque; 11705 int r; 11706 11707 rdmsrl_safe(MSR_EFER, &host_efer); 11708 11709 if (boot_cpu_has(X86_FEATURE_XSAVES)) 11710 rdmsrl(MSR_IA32_XSS, host_xss); 11711 11712 r = ops->hardware_setup(); 11713 if (r != 0) 11714 return r; 11715 11716 kvm_ops_update(ops); 11717 11718 kvm_register_perf_callbacks(ops->handle_intel_pt_intr); 11719 11720 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) 11721 supported_xss = 0; 11722 11723 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) 11724 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); 11725 #undef __kvm_cpu_cap_has 11726 11727 if (kvm_has_tsc_control) { 11728 /* 11729 * Make sure the user can only configure tsc_khz values that 11730 * fit into a signed integer. 11731 * A min value is not calculated because it will always 11732 * be 1 on all machines. 11733 */ 11734 u64 max = min(0x7fffffffULL, 11735 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 11736 kvm_max_guest_tsc_khz = max; 11737 } 11738 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 11739 kvm_init_msr_list(); 11740 return 0; 11741 } 11742 11743 void kvm_arch_hardware_unsetup(void) 11744 { 11745 kvm_unregister_perf_callbacks(); 11746 11747 static_call(kvm_x86_hardware_unsetup)(); 11748 } 11749 11750 int kvm_arch_check_processor_compat(void *opaque) 11751 { 11752 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 11753 struct kvm_x86_init_ops *ops = opaque; 11754 11755 WARN_ON(!irqs_disabled()); 11756 11757 if (__cr4_reserved_bits(cpu_has, c) != 11758 __cr4_reserved_bits(cpu_has, &boot_cpu_data)) 11759 return -EIO; 11760 11761 return ops->check_processor_compatibility(); 11762 } 11763 11764 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 11765 { 11766 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 11767 } 11768 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 11769 11770 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 11771 { 11772 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 11773 } 11774 11775 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); 11776 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); 11777 11778 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 11779 { 11780 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 11781 11782 vcpu->arch.l1tf_flush_l1d = true; 11783 if (pmu->version && unlikely(pmu->event_count)) { 11784 pmu->need_cleanup = true; 11785 kvm_make_request(KVM_REQ_PMU, vcpu); 11786 } 11787 static_call(kvm_x86_sched_in)(vcpu, cpu); 11788 } 11789 11790 void kvm_arch_free_vm(struct kvm *kvm) 11791 { 11792 kfree(to_kvm_hv(kvm)->hv_pa_pg); 11793 __kvm_arch_free_vm(kvm); 11794 } 11795 11796 11797 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 11798 { 11799 int ret; 11800 unsigned long flags; 11801 11802 if (type) 11803 return -EINVAL; 11804 11805 ret = kvm_page_track_init(kvm); 11806 if (ret) 11807 goto out; 11808 11809 ret = kvm_mmu_init_vm(kvm); 11810 if (ret) 11811 goto out_page_track; 11812 11813 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 11814 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 11815 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 11816 11817 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 11818 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 11819 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 11820 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 11821 &kvm->arch.irq_sources_bitmap); 11822 11823 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 11824 mutex_init(&kvm->arch.apic_map_lock); 11825 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock); 11826 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); 11827 11828 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 11829 pvclock_update_vm_gtod_copy(kvm); 11830 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 11831 11832 kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz; 11833 kvm->arch.guest_can_read_msr_platform_info = true; 11834 kvm->arch.enable_pmu = enable_pmu; 11835 11836 #if IS_ENABLED(CONFIG_HYPERV) 11837 spin_lock_init(&kvm->arch.hv_root_tdp_lock); 11838 kvm->arch.hv_root_tdp = INVALID_PAGE; 11839 #endif 11840 11841 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 11842 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 11843 11844 kvm_apicv_init(kvm); 11845 kvm_hv_init_vm(kvm); 11846 kvm_xen_init_vm(kvm); 11847 11848 return static_call(kvm_x86_vm_init)(kvm); 11849 11850 out_page_track: 11851 kvm_page_track_cleanup(kvm); 11852 out: 11853 return ret; 11854 } 11855 11856 int kvm_arch_post_init_vm(struct kvm *kvm) 11857 { 11858 return kvm_mmu_post_init_vm(kvm); 11859 } 11860 11861 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 11862 { 11863 vcpu_load(vcpu); 11864 kvm_mmu_unload(vcpu); 11865 vcpu_put(vcpu); 11866 } 11867 11868 static void kvm_unload_vcpu_mmus(struct kvm *kvm) 11869 { 11870 unsigned long i; 11871 struct kvm_vcpu *vcpu; 11872 11873 kvm_for_each_vcpu(i, vcpu, kvm) { 11874 kvm_clear_async_pf_completion_queue(vcpu); 11875 kvm_unload_vcpu_mmu(vcpu); 11876 } 11877 } 11878 11879 void kvm_arch_sync_events(struct kvm *kvm) 11880 { 11881 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 11882 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 11883 kvm_free_pit(kvm); 11884 } 11885 11886 /** 11887 * __x86_set_memory_region: Setup KVM internal memory slot 11888 * 11889 * @kvm: the kvm pointer to the VM. 11890 * @id: the slot ID to setup. 11891 * @gpa: the GPA to install the slot (unused when @size == 0). 11892 * @size: the size of the slot. Set to zero to uninstall a slot. 11893 * 11894 * This function helps to setup a KVM internal memory slot. Specify 11895 * @size > 0 to install a new slot, while @size == 0 to uninstall a 11896 * slot. The return code can be one of the following: 11897 * 11898 * HVA: on success (uninstall will return a bogus HVA) 11899 * -errno: on error 11900 * 11901 * The caller should always use IS_ERR() to check the return value 11902 * before use. Note, the KVM internal memory slots are guaranteed to 11903 * remain valid and unchanged until the VM is destroyed, i.e., the 11904 * GPA->HVA translation will not change. However, the HVA is a user 11905 * address, i.e. its accessibility is not guaranteed, and must be 11906 * accessed via __copy_{to,from}_user(). 11907 */ 11908 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, 11909 u32 size) 11910 { 11911 int i, r; 11912 unsigned long hva, old_npages; 11913 struct kvm_memslots *slots = kvm_memslots(kvm); 11914 struct kvm_memory_slot *slot; 11915 11916 /* Called with kvm->slots_lock held. */ 11917 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 11918 return ERR_PTR_USR(-EINVAL); 11919 11920 slot = id_to_memslot(slots, id); 11921 if (size) { 11922 if (slot && slot->npages) 11923 return ERR_PTR_USR(-EEXIST); 11924 11925 /* 11926 * MAP_SHARED to prevent internal slot pages from being moved 11927 * by fork()/COW. 11928 */ 11929 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 11930 MAP_SHARED | MAP_ANONYMOUS, 0); 11931 if (IS_ERR((void *)hva)) 11932 return (void __user *)hva; 11933 } else { 11934 if (!slot || !slot->npages) 11935 return NULL; 11936 11937 old_npages = slot->npages; 11938 hva = slot->userspace_addr; 11939 } 11940 11941 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 11942 struct kvm_userspace_memory_region m; 11943 11944 m.slot = id | (i << 16); 11945 m.flags = 0; 11946 m.guest_phys_addr = gpa; 11947 m.userspace_addr = hva; 11948 m.memory_size = size; 11949 r = __kvm_set_memory_region(kvm, &m); 11950 if (r < 0) 11951 return ERR_PTR_USR(r); 11952 } 11953 11954 if (!size) 11955 vm_munmap(hva, old_npages * PAGE_SIZE); 11956 11957 return (void __user *)hva; 11958 } 11959 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 11960 11961 void kvm_arch_pre_destroy_vm(struct kvm *kvm) 11962 { 11963 kvm_mmu_pre_destroy_vm(kvm); 11964 } 11965 11966 void kvm_arch_destroy_vm(struct kvm *kvm) 11967 { 11968 if (current->mm == kvm->mm) { 11969 /* 11970 * Free memory regions allocated on behalf of userspace, 11971 * unless the memory map has changed due to process exit 11972 * or fd copying. 11973 */ 11974 mutex_lock(&kvm->slots_lock); 11975 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 11976 0, 0); 11977 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 11978 0, 0); 11979 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 11980 mutex_unlock(&kvm->slots_lock); 11981 } 11982 kvm_unload_vcpu_mmus(kvm); 11983 static_call_cond(kvm_x86_vm_destroy)(kvm); 11984 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); 11985 kvm_pic_destroy(kvm); 11986 kvm_ioapic_destroy(kvm); 11987 kvm_destroy_vcpus(kvm); 11988 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 11989 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); 11990 kvm_mmu_uninit_vm(kvm); 11991 kvm_page_track_cleanup(kvm); 11992 kvm_xen_destroy_vm(kvm); 11993 kvm_hv_destroy_vm(kvm); 11994 } 11995 11996 static void memslot_rmap_free(struct kvm_memory_slot *slot) 11997 { 11998 int i; 11999 12000 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 12001 kvfree(slot->arch.rmap[i]); 12002 slot->arch.rmap[i] = NULL; 12003 } 12004 } 12005 12006 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) 12007 { 12008 int i; 12009 12010 memslot_rmap_free(slot); 12011 12012 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 12013 kvfree(slot->arch.lpage_info[i - 1]); 12014 slot->arch.lpage_info[i - 1] = NULL; 12015 } 12016 12017 kvm_page_track_free_memslot(slot); 12018 } 12019 12020 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages) 12021 { 12022 const int sz = sizeof(*slot->arch.rmap[0]); 12023 int i; 12024 12025 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 12026 int level = i + 1; 12027 int lpages = __kvm_mmu_slot_lpages(slot, npages, level); 12028 12029 if (slot->arch.rmap[i]) 12030 continue; 12031 12032 slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT); 12033 if (!slot->arch.rmap[i]) { 12034 memslot_rmap_free(slot); 12035 return -ENOMEM; 12036 } 12037 } 12038 12039 return 0; 12040 } 12041 12042 static int kvm_alloc_memslot_metadata(struct kvm *kvm, 12043 struct kvm_memory_slot *slot) 12044 { 12045 unsigned long npages = slot->npages; 12046 int i, r; 12047 12048 /* 12049 * Clear out the previous array pointers for the KVM_MR_MOVE case. The 12050 * old arrays will be freed by __kvm_set_memory_region() if installing 12051 * the new memslot is successful. 12052 */ 12053 memset(&slot->arch, 0, sizeof(slot->arch)); 12054 12055 if (kvm_memslots_have_rmaps(kvm)) { 12056 r = memslot_rmap_alloc(slot, npages); 12057 if (r) 12058 return r; 12059 } 12060 12061 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 12062 struct kvm_lpage_info *linfo; 12063 unsigned long ugfn; 12064 int lpages; 12065 int level = i + 1; 12066 12067 lpages = __kvm_mmu_slot_lpages(slot, npages, level); 12068 12069 linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 12070 if (!linfo) 12071 goto out_free; 12072 12073 slot->arch.lpage_info[i - 1] = linfo; 12074 12075 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 12076 linfo[0].disallow_lpage = 1; 12077 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 12078 linfo[lpages - 1].disallow_lpage = 1; 12079 ugfn = slot->userspace_addr >> PAGE_SHIFT; 12080 /* 12081 * If the gfn and userspace address are not aligned wrt each 12082 * other, disable large page support for this slot. 12083 */ 12084 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { 12085 unsigned long j; 12086 12087 for (j = 0; j < lpages; ++j) 12088 linfo[j].disallow_lpage = 1; 12089 } 12090 } 12091 12092 if (kvm_page_track_create_memslot(kvm, slot, npages)) 12093 goto out_free; 12094 12095 return 0; 12096 12097 out_free: 12098 memslot_rmap_free(slot); 12099 12100 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 12101 kvfree(slot->arch.lpage_info[i - 1]); 12102 slot->arch.lpage_info[i - 1] = NULL; 12103 } 12104 return -ENOMEM; 12105 } 12106 12107 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 12108 { 12109 struct kvm_vcpu *vcpu; 12110 unsigned long i; 12111 12112 /* 12113 * memslots->generation has been incremented. 12114 * mmio generation may have reached its maximum value. 12115 */ 12116 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 12117 12118 /* Force re-initialization of steal_time cache */ 12119 kvm_for_each_vcpu(i, vcpu, kvm) 12120 kvm_vcpu_kick(vcpu); 12121 } 12122 12123 int kvm_arch_prepare_memory_region(struct kvm *kvm, 12124 const struct kvm_memory_slot *old, 12125 struct kvm_memory_slot *new, 12126 enum kvm_mr_change change) 12127 { 12128 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) { 12129 if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn()) 12130 return -EINVAL; 12131 12132 return kvm_alloc_memslot_metadata(kvm, new); 12133 } 12134 12135 if (change == KVM_MR_FLAGS_ONLY) 12136 memcpy(&new->arch, &old->arch, sizeof(old->arch)); 12137 else if (WARN_ON_ONCE(change != KVM_MR_DELETE)) 12138 return -EIO; 12139 12140 return 0; 12141 } 12142 12143 12144 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) 12145 { 12146 struct kvm_arch *ka = &kvm->arch; 12147 12148 if (!kvm_x86_ops.cpu_dirty_log_size) 12149 return; 12150 12151 if ((enable && ++ka->cpu_dirty_logging_count == 1) || 12152 (!enable && --ka->cpu_dirty_logging_count == 0)) 12153 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); 12154 12155 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); 12156 } 12157 12158 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 12159 struct kvm_memory_slot *old, 12160 const struct kvm_memory_slot *new, 12161 enum kvm_mr_change change) 12162 { 12163 u32 old_flags = old ? old->flags : 0; 12164 u32 new_flags = new ? new->flags : 0; 12165 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES; 12166 12167 /* 12168 * Update CPU dirty logging if dirty logging is being toggled. This 12169 * applies to all operations. 12170 */ 12171 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES) 12172 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); 12173 12174 /* 12175 * Nothing more to do for RO slots (which can't be dirtied and can't be 12176 * made writable) or CREATE/MOVE/DELETE of a slot. 12177 * 12178 * For a memslot with dirty logging disabled: 12179 * CREATE: No dirty mappings will already exist. 12180 * MOVE/DELETE: The old mappings will already have been cleaned up by 12181 * kvm_arch_flush_shadow_memslot() 12182 * 12183 * For a memslot with dirty logging enabled: 12184 * CREATE: No shadow pages exist, thus nothing to write-protect 12185 * and no dirty bits to clear. 12186 * MOVE/DELETE: The old mappings will already have been cleaned up by 12187 * kvm_arch_flush_shadow_memslot(). 12188 */ 12189 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY)) 12190 return; 12191 12192 /* 12193 * READONLY and non-flags changes were filtered out above, and the only 12194 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty 12195 * logging isn't being toggled on or off. 12196 */ 12197 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES))) 12198 return; 12199 12200 if (!log_dirty_pages) { 12201 /* 12202 * Dirty logging tracks sptes in 4k granularity, meaning that 12203 * large sptes have to be split. If live migration succeeds, 12204 * the guest in the source machine will be destroyed and large 12205 * sptes will be created in the destination. However, if the 12206 * guest continues to run in the source machine (for example if 12207 * live migration fails), small sptes will remain around and 12208 * cause bad performance. 12209 * 12210 * Scan sptes if dirty logging has been stopped, dropping those 12211 * which can be collapsed into a single large-page spte. Later 12212 * page faults will create the large-page sptes. 12213 */ 12214 kvm_mmu_zap_collapsible_sptes(kvm, new); 12215 } else { 12216 /* 12217 * Initially-all-set does not require write protecting any page, 12218 * because they're all assumed to be dirty. 12219 */ 12220 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) 12221 return; 12222 12223 if (READ_ONCE(eager_page_split)) 12224 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K); 12225 12226 if (kvm_x86_ops.cpu_dirty_log_size) { 12227 kvm_mmu_slot_leaf_clear_dirty(kvm, new); 12228 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M); 12229 } else { 12230 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K); 12231 } 12232 } 12233 } 12234 12235 void kvm_arch_commit_memory_region(struct kvm *kvm, 12236 struct kvm_memory_slot *old, 12237 const struct kvm_memory_slot *new, 12238 enum kvm_mr_change change) 12239 { 12240 if (!kvm->arch.n_requested_mmu_pages && 12241 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) { 12242 unsigned long nr_mmu_pages; 12243 12244 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO; 12245 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES); 12246 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 12247 } 12248 12249 kvm_mmu_slot_apply_flags(kvm, old, new, change); 12250 12251 /* Free the arrays associated with the old memslot. */ 12252 if (change == KVM_MR_MOVE) 12253 kvm_arch_free_memslot(kvm, old); 12254 } 12255 12256 void kvm_arch_flush_shadow_all(struct kvm *kvm) 12257 { 12258 kvm_mmu_zap_all(kvm); 12259 } 12260 12261 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 12262 struct kvm_memory_slot *slot) 12263 { 12264 kvm_page_track_flush_slot(kvm, slot); 12265 } 12266 12267 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 12268 { 12269 return (is_guest_mode(vcpu) && 12270 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); 12271 } 12272 12273 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 12274 { 12275 if (!list_empty_careful(&vcpu->async_pf.done)) 12276 return true; 12277 12278 if (kvm_apic_has_events(vcpu)) 12279 return true; 12280 12281 if (vcpu->arch.pv.pv_unhalted) 12282 return true; 12283 12284 if (vcpu->arch.exception.pending) 12285 return true; 12286 12287 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 12288 (vcpu->arch.nmi_pending && 12289 static_call(kvm_x86_nmi_allowed)(vcpu, false))) 12290 return true; 12291 12292 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 12293 (vcpu->arch.smi_pending && 12294 static_call(kvm_x86_smi_allowed)(vcpu, false))) 12295 return true; 12296 12297 if (kvm_arch_interrupt_allowed(vcpu) && 12298 (kvm_cpu_has_interrupt(vcpu) || 12299 kvm_guest_apic_has_interrupt(vcpu))) 12300 return true; 12301 12302 if (kvm_hv_has_stimer_pending(vcpu)) 12303 return true; 12304 12305 if (is_guest_mode(vcpu) && 12306 kvm_x86_ops.nested_ops->hv_timer_pending && 12307 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 12308 return true; 12309 12310 if (kvm_xen_has_pending_events(vcpu)) 12311 return true; 12312 12313 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) 12314 return true; 12315 12316 return false; 12317 } 12318 12319 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 12320 { 12321 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 12322 } 12323 12324 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) 12325 { 12326 if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) 12327 return true; 12328 12329 return false; 12330 } 12331 12332 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) 12333 { 12334 if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) 12335 return true; 12336 12337 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 12338 kvm_test_request(KVM_REQ_SMI, vcpu) || 12339 kvm_test_request(KVM_REQ_EVENT, vcpu)) 12340 return true; 12341 12342 return kvm_arch_dy_has_pending_interrupt(vcpu); 12343 } 12344 12345 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 12346 { 12347 if (vcpu->arch.guest_state_protected) 12348 return true; 12349 12350 return vcpu->arch.preempted_in_kernel; 12351 } 12352 12353 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu) 12354 { 12355 return kvm_rip_read(vcpu); 12356 } 12357 12358 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 12359 { 12360 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 12361 } 12362 12363 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 12364 { 12365 return static_call(kvm_x86_interrupt_allowed)(vcpu, false); 12366 } 12367 12368 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 12369 { 12370 /* Can't read the RIP when guest state is protected, just return 0 */ 12371 if (vcpu->arch.guest_state_protected) 12372 return 0; 12373 12374 if (is_64_bit_mode(vcpu)) 12375 return kvm_rip_read(vcpu); 12376 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 12377 kvm_rip_read(vcpu)); 12378 } 12379 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 12380 12381 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 12382 { 12383 return kvm_get_linear_rip(vcpu) == linear_rip; 12384 } 12385 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 12386 12387 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 12388 { 12389 unsigned long rflags; 12390 12391 rflags = static_call(kvm_x86_get_rflags)(vcpu); 12392 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 12393 rflags &= ~X86_EFLAGS_TF; 12394 return rflags; 12395 } 12396 EXPORT_SYMBOL_GPL(kvm_get_rflags); 12397 12398 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 12399 { 12400 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 12401 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 12402 rflags |= X86_EFLAGS_TF; 12403 static_call(kvm_x86_set_rflags)(vcpu, rflags); 12404 } 12405 12406 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 12407 { 12408 __kvm_set_rflags(vcpu, rflags); 12409 kvm_make_request(KVM_REQ_EVENT, vcpu); 12410 } 12411 EXPORT_SYMBOL_GPL(kvm_set_rflags); 12412 12413 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 12414 { 12415 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); 12416 12417 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 12418 } 12419 12420 static inline u32 kvm_async_pf_next_probe(u32 key) 12421 { 12422 return (key + 1) & (ASYNC_PF_PER_VCPU - 1); 12423 } 12424 12425 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 12426 { 12427 u32 key = kvm_async_pf_hash_fn(gfn); 12428 12429 while (vcpu->arch.apf.gfns[key] != ~0) 12430 key = kvm_async_pf_next_probe(key); 12431 12432 vcpu->arch.apf.gfns[key] = gfn; 12433 } 12434 12435 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 12436 { 12437 int i; 12438 u32 key = kvm_async_pf_hash_fn(gfn); 12439 12440 for (i = 0; i < ASYNC_PF_PER_VCPU && 12441 (vcpu->arch.apf.gfns[key] != gfn && 12442 vcpu->arch.apf.gfns[key] != ~0); i++) 12443 key = kvm_async_pf_next_probe(key); 12444 12445 return key; 12446 } 12447 12448 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 12449 { 12450 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 12451 } 12452 12453 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 12454 { 12455 u32 i, j, k; 12456 12457 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 12458 12459 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) 12460 return; 12461 12462 while (true) { 12463 vcpu->arch.apf.gfns[i] = ~0; 12464 do { 12465 j = kvm_async_pf_next_probe(j); 12466 if (vcpu->arch.apf.gfns[j] == ~0) 12467 return; 12468 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 12469 /* 12470 * k lies cyclically in ]i,j] 12471 * | i.k.j | 12472 * |....j i.k.| or |.k..j i...| 12473 */ 12474 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 12475 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 12476 i = j; 12477 } 12478 } 12479 12480 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) 12481 { 12482 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; 12483 12484 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, 12485 sizeof(reason)); 12486 } 12487 12488 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) 12489 { 12490 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 12491 12492 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 12493 &token, offset, sizeof(token)); 12494 } 12495 12496 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) 12497 { 12498 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 12499 u32 val; 12500 12501 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 12502 &val, offset, sizeof(val))) 12503 return false; 12504 12505 return !val; 12506 } 12507 12508 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) 12509 { 12510 12511 if (!kvm_pv_async_pf_enabled(vcpu)) 12512 return false; 12513 12514 if (vcpu->arch.apf.send_user_only && 12515 static_call(kvm_x86_get_cpl)(vcpu) == 0) 12516 return false; 12517 12518 if (is_guest_mode(vcpu)) { 12519 /* 12520 * L1 needs to opt into the special #PF vmexits that are 12521 * used to deliver async page faults. 12522 */ 12523 return vcpu->arch.apf.delivery_as_pf_vmexit; 12524 } else { 12525 /* 12526 * Play it safe in case the guest temporarily disables paging. 12527 * The real mode IDT in particular is unlikely to have a #PF 12528 * exception setup. 12529 */ 12530 return is_paging(vcpu); 12531 } 12532 } 12533 12534 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) 12535 { 12536 if (unlikely(!lapic_in_kernel(vcpu) || 12537 kvm_event_needs_reinjection(vcpu) || 12538 vcpu->arch.exception.pending)) 12539 return false; 12540 12541 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) 12542 return false; 12543 12544 /* 12545 * If interrupts are off we cannot even use an artificial 12546 * halt state. 12547 */ 12548 return kvm_arch_interrupt_allowed(vcpu); 12549 } 12550 12551 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 12552 struct kvm_async_pf *work) 12553 { 12554 struct x86_exception fault; 12555 12556 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); 12557 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 12558 12559 if (kvm_can_deliver_async_pf(vcpu) && 12560 !apf_put_user_notpresent(vcpu)) { 12561 fault.vector = PF_VECTOR; 12562 fault.error_code_valid = true; 12563 fault.error_code = 0; 12564 fault.nested_page_fault = false; 12565 fault.address = work->arch.token; 12566 fault.async_page_fault = true; 12567 kvm_inject_page_fault(vcpu, &fault); 12568 return true; 12569 } else { 12570 /* 12571 * It is not possible to deliver a paravirtualized asynchronous 12572 * page fault, but putting the guest in an artificial halt state 12573 * can be beneficial nevertheless: if an interrupt arrives, we 12574 * can deliver it timely and perhaps the guest will schedule 12575 * another process. When the instruction that triggered a page 12576 * fault is retried, hopefully the page will be ready in the host. 12577 */ 12578 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 12579 return false; 12580 } 12581 } 12582 12583 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 12584 struct kvm_async_pf *work) 12585 { 12586 struct kvm_lapic_irq irq = { 12587 .delivery_mode = APIC_DM_FIXED, 12588 .vector = vcpu->arch.apf.vec 12589 }; 12590 12591 if (work->wakeup_all) 12592 work->arch.token = ~0; /* broadcast wakeup */ 12593 else 12594 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 12595 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); 12596 12597 if ((work->wakeup_all || work->notpresent_injected) && 12598 kvm_pv_async_pf_enabled(vcpu) && 12599 !apf_put_user_ready(vcpu, work->arch.token)) { 12600 vcpu->arch.apf.pageready_pending = true; 12601 kvm_apic_set_irq(vcpu, &irq, NULL); 12602 } 12603 12604 vcpu->arch.apf.halted = false; 12605 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 12606 } 12607 12608 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) 12609 { 12610 kvm_make_request(KVM_REQ_APF_READY, vcpu); 12611 if (!vcpu->arch.apf.pageready_pending) 12612 kvm_vcpu_kick(vcpu); 12613 } 12614 12615 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) 12616 { 12617 if (!kvm_pv_async_pf_enabled(vcpu)) 12618 return true; 12619 else 12620 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); 12621 } 12622 12623 void kvm_arch_start_assignment(struct kvm *kvm) 12624 { 12625 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) 12626 static_call_cond(kvm_x86_pi_start_assignment)(kvm); 12627 } 12628 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 12629 12630 void kvm_arch_end_assignment(struct kvm *kvm) 12631 { 12632 atomic_dec(&kvm->arch.assigned_device_count); 12633 } 12634 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 12635 12636 bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm) 12637 { 12638 return arch_atomic_read(&kvm->arch.assigned_device_count); 12639 } 12640 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 12641 12642 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 12643 { 12644 atomic_inc(&kvm->arch.noncoherent_dma_count); 12645 } 12646 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 12647 12648 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 12649 { 12650 atomic_dec(&kvm->arch.noncoherent_dma_count); 12651 } 12652 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 12653 12654 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 12655 { 12656 return atomic_read(&kvm->arch.noncoherent_dma_count); 12657 } 12658 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 12659 12660 bool kvm_arch_has_irq_bypass(void) 12661 { 12662 return true; 12663 } 12664 12665 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 12666 struct irq_bypass_producer *prod) 12667 { 12668 struct kvm_kernel_irqfd *irqfd = 12669 container_of(cons, struct kvm_kernel_irqfd, consumer); 12670 int ret; 12671 12672 irqfd->producer = prod; 12673 kvm_arch_start_assignment(irqfd->kvm); 12674 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, 12675 prod->irq, irqfd->gsi, 1); 12676 12677 if (ret) 12678 kvm_arch_end_assignment(irqfd->kvm); 12679 12680 return ret; 12681 } 12682 12683 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 12684 struct irq_bypass_producer *prod) 12685 { 12686 int ret; 12687 struct kvm_kernel_irqfd *irqfd = 12688 container_of(cons, struct kvm_kernel_irqfd, consumer); 12689 12690 WARN_ON(irqfd->producer != prod); 12691 irqfd->producer = NULL; 12692 12693 /* 12694 * When producer of consumer is unregistered, we change back to 12695 * remapped mode, so we can re-use the current implementation 12696 * when the irq is masked/disabled or the consumer side (KVM 12697 * int this case doesn't want to receive the interrupts. 12698 */ 12699 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); 12700 if (ret) 12701 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 12702 " fails: %d\n", irqfd->consumer.token, ret); 12703 12704 kvm_arch_end_assignment(irqfd->kvm); 12705 } 12706 12707 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 12708 uint32_t guest_irq, bool set) 12709 { 12710 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set); 12711 } 12712 12713 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old, 12714 struct kvm_kernel_irq_routing_entry *new) 12715 { 12716 if (new->type != KVM_IRQ_ROUTING_MSI) 12717 return true; 12718 12719 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi)); 12720 } 12721 12722 bool kvm_vector_hashing_enabled(void) 12723 { 12724 return vector_hashing; 12725 } 12726 12727 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) 12728 { 12729 return (vcpu->arch.msr_kvm_poll_control & 1) == 0; 12730 } 12731 EXPORT_SYMBOL_GPL(kvm_arch_no_poll); 12732 12733 12734 int kvm_spec_ctrl_test_value(u64 value) 12735 { 12736 /* 12737 * test that setting IA32_SPEC_CTRL to given value 12738 * is allowed by the host processor 12739 */ 12740 12741 u64 saved_value; 12742 unsigned long flags; 12743 int ret = 0; 12744 12745 local_irq_save(flags); 12746 12747 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) 12748 ret = 1; 12749 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) 12750 ret = 1; 12751 else 12752 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); 12753 12754 local_irq_restore(flags); 12755 12756 return ret; 12757 } 12758 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); 12759 12760 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) 12761 { 12762 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 12763 struct x86_exception fault; 12764 u64 access = error_code & 12765 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); 12766 12767 if (!(error_code & PFERR_PRESENT_MASK) || 12768 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != UNMAPPED_GVA) { 12769 /* 12770 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page 12771 * tables probably do not match the TLB. Just proceed 12772 * with the error code that the processor gave. 12773 */ 12774 fault.vector = PF_VECTOR; 12775 fault.error_code_valid = true; 12776 fault.error_code = error_code; 12777 fault.nested_page_fault = false; 12778 fault.address = gva; 12779 } 12780 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); 12781 } 12782 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); 12783 12784 /* 12785 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns 12786 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value 12787 * indicates whether exit to userspace is needed. 12788 */ 12789 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 12790 struct x86_exception *e) 12791 { 12792 if (r == X86EMUL_PROPAGATE_FAULT) { 12793 kvm_inject_emulated_page_fault(vcpu, e); 12794 return 1; 12795 } 12796 12797 /* 12798 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED 12799 * while handling a VMX instruction KVM could've handled the request 12800 * correctly by exiting to userspace and performing I/O but there 12801 * doesn't seem to be a real use-case behind such requests, just return 12802 * KVM_EXIT_INTERNAL_ERROR for now. 12803 */ 12804 kvm_prepare_emulation_failure_exit(vcpu); 12805 12806 return 0; 12807 } 12808 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); 12809 12810 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) 12811 { 12812 bool pcid_enabled; 12813 struct x86_exception e; 12814 struct { 12815 u64 pcid; 12816 u64 gla; 12817 } operand; 12818 int r; 12819 12820 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 12821 if (r != X86EMUL_CONTINUE) 12822 return kvm_handle_memory_failure(vcpu, r, &e); 12823 12824 if (operand.pcid >> 12 != 0) { 12825 kvm_inject_gp(vcpu, 0); 12826 return 1; 12827 } 12828 12829 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 12830 12831 switch (type) { 12832 case INVPCID_TYPE_INDIV_ADDR: 12833 if ((!pcid_enabled && (operand.pcid != 0)) || 12834 is_noncanonical_address(operand.gla, vcpu)) { 12835 kvm_inject_gp(vcpu, 0); 12836 return 1; 12837 } 12838 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 12839 return kvm_skip_emulated_instruction(vcpu); 12840 12841 case INVPCID_TYPE_SINGLE_CTXT: 12842 if (!pcid_enabled && (operand.pcid != 0)) { 12843 kvm_inject_gp(vcpu, 0); 12844 return 1; 12845 } 12846 12847 kvm_invalidate_pcid(vcpu, operand.pcid); 12848 return kvm_skip_emulated_instruction(vcpu); 12849 12850 case INVPCID_TYPE_ALL_NON_GLOBAL: 12851 /* 12852 * Currently, KVM doesn't mark global entries in the shadow 12853 * page tables, so a non-global flush just degenerates to a 12854 * global flush. If needed, we could optimize this later by 12855 * keeping track of global entries in shadow page tables. 12856 */ 12857 12858 fallthrough; 12859 case INVPCID_TYPE_ALL_INCL_GLOBAL: 12860 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 12861 return kvm_skip_emulated_instruction(vcpu); 12862 12863 default: 12864 kvm_inject_gp(vcpu, 0); 12865 return 1; 12866 } 12867 } 12868 EXPORT_SYMBOL_GPL(kvm_handle_invpcid); 12869 12870 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) 12871 { 12872 struct kvm_run *run = vcpu->run; 12873 struct kvm_mmio_fragment *frag; 12874 unsigned int len; 12875 12876 BUG_ON(!vcpu->mmio_needed); 12877 12878 /* Complete previous fragment */ 12879 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 12880 len = min(8u, frag->len); 12881 if (!vcpu->mmio_is_write) 12882 memcpy(frag->data, run->mmio.data, len); 12883 12884 if (frag->len <= 8) { 12885 /* Switch to the next fragment. */ 12886 frag++; 12887 vcpu->mmio_cur_fragment++; 12888 } else { 12889 /* Go forward to the next mmio piece. */ 12890 frag->data += len; 12891 frag->gpa += len; 12892 frag->len -= len; 12893 } 12894 12895 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 12896 vcpu->mmio_needed = 0; 12897 12898 // VMG change, at this point, we're always done 12899 // RIP has already been advanced 12900 return 1; 12901 } 12902 12903 // More MMIO is needed 12904 run->mmio.phys_addr = frag->gpa; 12905 run->mmio.len = min(8u, frag->len); 12906 run->mmio.is_write = vcpu->mmio_is_write; 12907 if (run->mmio.is_write) 12908 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 12909 run->exit_reason = KVM_EXIT_MMIO; 12910 12911 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12912 12913 return 0; 12914 } 12915 12916 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 12917 void *data) 12918 { 12919 int handled; 12920 struct kvm_mmio_fragment *frag; 12921 12922 if (!data) 12923 return -EINVAL; 12924 12925 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); 12926 if (handled == bytes) 12927 return 1; 12928 12929 bytes -= handled; 12930 gpa += handled; 12931 data += handled; 12932 12933 /*TODO: Check if need to increment number of frags */ 12934 frag = vcpu->mmio_fragments; 12935 vcpu->mmio_nr_fragments = 1; 12936 frag->len = bytes; 12937 frag->gpa = gpa; 12938 frag->data = data; 12939 12940 vcpu->mmio_needed = 1; 12941 vcpu->mmio_cur_fragment = 0; 12942 12943 vcpu->run->mmio.phys_addr = gpa; 12944 vcpu->run->mmio.len = min(8u, frag->len); 12945 vcpu->run->mmio.is_write = 1; 12946 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 12947 vcpu->run->exit_reason = KVM_EXIT_MMIO; 12948 12949 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12950 12951 return 0; 12952 } 12953 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); 12954 12955 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 12956 void *data) 12957 { 12958 int handled; 12959 struct kvm_mmio_fragment *frag; 12960 12961 if (!data) 12962 return -EINVAL; 12963 12964 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); 12965 if (handled == bytes) 12966 return 1; 12967 12968 bytes -= handled; 12969 gpa += handled; 12970 data += handled; 12971 12972 /*TODO: Check if need to increment number of frags */ 12973 frag = vcpu->mmio_fragments; 12974 vcpu->mmio_nr_fragments = 1; 12975 frag->len = bytes; 12976 frag->gpa = gpa; 12977 frag->data = data; 12978 12979 vcpu->mmio_needed = 1; 12980 vcpu->mmio_cur_fragment = 0; 12981 12982 vcpu->run->mmio.phys_addr = gpa; 12983 vcpu->run->mmio.len = min(8u, frag->len); 12984 vcpu->run->mmio.is_write = 0; 12985 vcpu->run->exit_reason = KVM_EXIT_MMIO; 12986 12987 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12988 12989 return 0; 12990 } 12991 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); 12992 12993 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 12994 unsigned int port); 12995 12996 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu) 12997 { 12998 int size = vcpu->arch.pio.size; 12999 int port = vcpu->arch.pio.port; 13000 13001 vcpu->arch.pio.count = 0; 13002 if (vcpu->arch.sev_pio_count) 13003 return kvm_sev_es_outs(vcpu, size, port); 13004 return 1; 13005 } 13006 13007 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 13008 unsigned int port) 13009 { 13010 for (;;) { 13011 unsigned int count = 13012 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 13013 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count); 13014 13015 /* memcpy done already by emulator_pio_out. */ 13016 vcpu->arch.sev_pio_count -= count; 13017 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size; 13018 if (!ret) 13019 break; 13020 13021 /* Emulation done by the kernel. */ 13022 if (!vcpu->arch.sev_pio_count) 13023 return 1; 13024 } 13025 13026 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs; 13027 return 0; 13028 } 13029 13030 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 13031 unsigned int port); 13032 13033 static void advance_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 13034 { 13035 unsigned count = vcpu->arch.pio.count; 13036 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data); 13037 vcpu->arch.sev_pio_count -= count; 13038 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size; 13039 } 13040 13041 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 13042 { 13043 int size = vcpu->arch.pio.size; 13044 int port = vcpu->arch.pio.port; 13045 13046 advance_sev_es_emulated_ins(vcpu); 13047 if (vcpu->arch.sev_pio_count) 13048 return kvm_sev_es_ins(vcpu, size, port); 13049 return 1; 13050 } 13051 13052 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 13053 unsigned int port) 13054 { 13055 for (;;) { 13056 unsigned int count = 13057 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 13058 if (!__emulator_pio_in(vcpu, size, port, count)) 13059 break; 13060 13061 /* Emulation done by the kernel. */ 13062 advance_sev_es_emulated_ins(vcpu); 13063 if (!vcpu->arch.sev_pio_count) 13064 return 1; 13065 } 13066 13067 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; 13068 return 0; 13069 } 13070 13071 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 13072 unsigned int port, void *data, unsigned int count, 13073 int in) 13074 { 13075 vcpu->arch.sev_pio_data = data; 13076 vcpu->arch.sev_pio_count = count; 13077 return in ? kvm_sev_es_ins(vcpu, size, port) 13078 : kvm_sev_es_outs(vcpu, size, port); 13079 } 13080 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); 13081 13082 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); 13083 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 13084 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 13085 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 13086 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 13087 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 13088 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 13089 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 13090 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 13091 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 13092 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 13093 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); 13094 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 13095 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 13096 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 13097 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 13098 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); 13099 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 13100 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 13101 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 13102 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 13103 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); 13104 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath); 13105 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq); 13106 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); 13107 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); 13108 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); 13109 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); 13110 13111 static int __init kvm_x86_init(void) 13112 { 13113 kvm_mmu_x86_module_init(); 13114 return 0; 13115 } 13116 module_init(kvm_x86_init); 13117 13118 static void __exit kvm_x86_exit(void) 13119 { 13120 /* 13121 * If module_init() is implemented, module_exit() must also be 13122 * implemented to allow module unload. 13123 */ 13124 } 13125 module_exit(kvm_x86_exit); 13126