1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * derived from drivers/kvm/kvm_main.c 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright (C) 2008 Qumranet, Inc. 9 * Copyright IBM Corporation, 2008 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 11 * 12 * Authors: 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * Amit Shah <amit.shah@qumranet.com> 16 * Ben-Ami Yassour <benami@il.ibm.com> 17 */ 18 19 #include <linux/kvm_host.h> 20 #include "irq.h" 21 #include "ioapic.h" 22 #include "mmu.h" 23 #include "i8254.h" 24 #include "tss.h" 25 #include "kvm_cache_regs.h" 26 #include "kvm_emulate.h" 27 #include "x86.h" 28 #include "cpuid.h" 29 #include "pmu.h" 30 #include "hyperv.h" 31 #include "lapic.h" 32 #include "xen.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/export.h> 40 #include <linux/moduleparam.h> 41 #include <linux/mman.h> 42 #include <linux/highmem.h> 43 #include <linux/iommu.h> 44 #include <linux/intel-iommu.h> 45 #include <linux/cpufreq.h> 46 #include <linux/user-return-notifier.h> 47 #include <linux/srcu.h> 48 #include <linux/slab.h> 49 #include <linux/perf_event.h> 50 #include <linux/uaccess.h> 51 #include <linux/hash.h> 52 #include <linux/pci.h> 53 #include <linux/timekeeper_internal.h> 54 #include <linux/pvclock_gtod.h> 55 #include <linux/kvm_irqfd.h> 56 #include <linux/irqbypass.h> 57 #include <linux/sched/stat.h> 58 #include <linux/sched/isolation.h> 59 #include <linux/mem_encrypt.h> 60 #include <linux/entry-kvm.h> 61 #include <linux/suspend.h> 62 63 #include <trace/events/kvm.h> 64 65 #include <asm/debugreg.h> 66 #include <asm/msr.h> 67 #include <asm/desc.h> 68 #include <asm/mce.h> 69 #include <asm/pkru.h> 70 #include <linux/kernel_stat.h> 71 #include <asm/fpu/api.h> 72 #include <asm/fpu/xcr.h> 73 #include <asm/fpu/xstate.h> 74 #include <asm/pvclock.h> 75 #include <asm/div64.h> 76 #include <asm/irq_remapping.h> 77 #include <asm/mshyperv.h> 78 #include <asm/hypervisor.h> 79 #include <asm/tlbflush.h> 80 #include <asm/intel_pt.h> 81 #include <asm/emulate_prefix.h> 82 #include <asm/sgx.h> 83 #include <clocksource/hyperv_timer.h> 84 85 #define CREATE_TRACE_POINTS 86 #include "trace.h" 87 88 #define MAX_IO_MSRS 256 89 #define KVM_MAX_MCE_BANKS 32 90 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 91 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 92 93 #define emul_to_vcpu(ctxt) \ 94 ((struct kvm_vcpu *)(ctxt)->vcpu) 95 96 /* EFER defaults: 97 * - enable syscall per default because its emulated by KVM 98 * - enable LME and LMA per default on 64 bit KVM 99 */ 100 #ifdef CONFIG_X86_64 101 static 102 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 103 #else 104 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 105 #endif 106 107 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; 108 109 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) 110 111 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 112 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 113 114 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 115 static void process_nmi(struct kvm_vcpu *vcpu); 116 static void process_smi(struct kvm_vcpu *vcpu); 117 static void enter_smm(struct kvm_vcpu *vcpu); 118 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 119 static void store_regs(struct kvm_vcpu *vcpu); 120 static int sync_regs(struct kvm_vcpu *vcpu); 121 122 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 123 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 124 125 struct kvm_x86_ops kvm_x86_ops __read_mostly; 126 EXPORT_SYMBOL_GPL(kvm_x86_ops); 127 128 #define KVM_X86_OP(func) \ 129 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ 130 *(((struct kvm_x86_ops *)0)->func)); 131 #define KVM_X86_OP_NULL KVM_X86_OP 132 #include <asm/kvm-x86-ops.h> 133 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); 134 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); 135 EXPORT_STATIC_CALL_GPL(kvm_x86_tlb_flush_current); 136 137 static bool __read_mostly ignore_msrs = 0; 138 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 139 140 bool __read_mostly report_ignored_msrs = true; 141 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 142 EXPORT_SYMBOL_GPL(report_ignored_msrs); 143 144 unsigned int min_timer_period_us = 200; 145 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 146 147 static bool __read_mostly kvmclock_periodic_sync = true; 148 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 149 150 bool __read_mostly kvm_has_tsc_control; 151 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 152 u32 __read_mostly kvm_max_guest_tsc_khz; 153 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 154 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 155 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 156 u64 __read_mostly kvm_max_tsc_scaling_ratio; 157 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 158 u64 __read_mostly kvm_default_tsc_scaling_ratio; 159 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 160 bool __read_mostly kvm_has_bus_lock_exit; 161 EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit); 162 163 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 164 static u32 __read_mostly tsc_tolerance_ppm = 250; 165 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 166 167 /* 168 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 169 * adaptive tuning starting from default advancement of 1000ns. '0' disables 170 * advancement entirely. Any other value is used as-is and disables adaptive 171 * tuning, i.e. allows privileged userspace to set an exact advancement time. 172 */ 173 static int __read_mostly lapic_timer_advance_ns = -1; 174 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); 175 176 static bool __read_mostly vector_hashing = true; 177 module_param(vector_hashing, bool, S_IRUGO); 178 179 bool __read_mostly enable_vmware_backdoor = false; 180 module_param(enable_vmware_backdoor, bool, S_IRUGO); 181 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 182 183 static bool __read_mostly force_emulation_prefix = false; 184 module_param(force_emulation_prefix, bool, S_IRUGO); 185 186 int __read_mostly pi_inject_timer = -1; 187 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); 188 189 /* 190 * Restoring the host value for MSRs that are only consumed when running in 191 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU 192 * returns to userspace, i.e. the kernel can run with the guest's value. 193 */ 194 #define KVM_MAX_NR_USER_RETURN_MSRS 16 195 196 struct kvm_user_return_msrs { 197 struct user_return_notifier urn; 198 bool registered; 199 struct kvm_user_return_msr_values { 200 u64 host; 201 u64 curr; 202 } values[KVM_MAX_NR_USER_RETURN_MSRS]; 203 }; 204 205 u32 __read_mostly kvm_nr_uret_msrs; 206 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); 207 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; 208 static struct kvm_user_return_msrs __percpu *user_return_msrs; 209 210 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 211 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 212 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 213 | XFEATURE_MASK_PKRU) 214 215 u64 __read_mostly host_efer; 216 EXPORT_SYMBOL_GPL(host_efer); 217 218 bool __read_mostly allow_smaller_maxphyaddr = 0; 219 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); 220 221 bool __read_mostly enable_apicv = true; 222 EXPORT_SYMBOL_GPL(enable_apicv); 223 224 u64 __read_mostly host_xss; 225 EXPORT_SYMBOL_GPL(host_xss); 226 u64 __read_mostly supported_xss; 227 EXPORT_SYMBOL_GPL(supported_xss); 228 229 const struct _kvm_stats_desc kvm_vm_stats_desc[] = { 230 KVM_GENERIC_VM_STATS(), 231 STATS_DESC_COUNTER(VM, mmu_shadow_zapped), 232 STATS_DESC_COUNTER(VM, mmu_pte_write), 233 STATS_DESC_COUNTER(VM, mmu_pde_zapped), 234 STATS_DESC_COUNTER(VM, mmu_flooded), 235 STATS_DESC_COUNTER(VM, mmu_recycled), 236 STATS_DESC_COUNTER(VM, mmu_cache_miss), 237 STATS_DESC_ICOUNTER(VM, mmu_unsync), 238 STATS_DESC_ICOUNTER(VM, pages_4k), 239 STATS_DESC_ICOUNTER(VM, pages_2m), 240 STATS_DESC_ICOUNTER(VM, pages_1g), 241 STATS_DESC_ICOUNTER(VM, nx_lpage_splits), 242 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size), 243 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions) 244 }; 245 246 const struct kvm_stats_header kvm_vm_stats_header = { 247 .name_size = KVM_STATS_NAME_SIZE, 248 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), 249 .id_offset = sizeof(struct kvm_stats_header), 250 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 251 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 252 sizeof(kvm_vm_stats_desc), 253 }; 254 255 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { 256 KVM_GENERIC_VCPU_STATS(), 257 STATS_DESC_COUNTER(VCPU, pf_fixed), 258 STATS_DESC_COUNTER(VCPU, pf_guest), 259 STATS_DESC_COUNTER(VCPU, tlb_flush), 260 STATS_DESC_COUNTER(VCPU, invlpg), 261 STATS_DESC_COUNTER(VCPU, exits), 262 STATS_DESC_COUNTER(VCPU, io_exits), 263 STATS_DESC_COUNTER(VCPU, mmio_exits), 264 STATS_DESC_COUNTER(VCPU, signal_exits), 265 STATS_DESC_COUNTER(VCPU, irq_window_exits), 266 STATS_DESC_COUNTER(VCPU, nmi_window_exits), 267 STATS_DESC_COUNTER(VCPU, l1d_flush), 268 STATS_DESC_COUNTER(VCPU, halt_exits), 269 STATS_DESC_COUNTER(VCPU, request_irq_exits), 270 STATS_DESC_COUNTER(VCPU, irq_exits), 271 STATS_DESC_COUNTER(VCPU, host_state_reload), 272 STATS_DESC_COUNTER(VCPU, fpu_reload), 273 STATS_DESC_COUNTER(VCPU, insn_emulation), 274 STATS_DESC_COUNTER(VCPU, insn_emulation_fail), 275 STATS_DESC_COUNTER(VCPU, hypercalls), 276 STATS_DESC_COUNTER(VCPU, irq_injections), 277 STATS_DESC_COUNTER(VCPU, nmi_injections), 278 STATS_DESC_COUNTER(VCPU, req_event), 279 STATS_DESC_COUNTER(VCPU, nested_run), 280 STATS_DESC_COUNTER(VCPU, directed_yield_attempted), 281 STATS_DESC_COUNTER(VCPU, directed_yield_successful), 282 STATS_DESC_ICOUNTER(VCPU, guest_mode) 283 }; 284 285 const struct kvm_stats_header kvm_vcpu_stats_header = { 286 .name_size = KVM_STATS_NAME_SIZE, 287 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), 288 .id_offset = sizeof(struct kvm_stats_header), 289 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 290 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 291 sizeof(kvm_vcpu_stats_desc), 292 }; 293 294 u64 __read_mostly host_xcr0; 295 u64 __read_mostly supported_xcr0; 296 EXPORT_SYMBOL_GPL(supported_xcr0); 297 298 static struct kmem_cache *x86_emulator_cache; 299 300 /* 301 * When called, it means the previous get/set msr reached an invalid msr. 302 * Return true if we want to ignore/silent this failed msr access. 303 */ 304 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) 305 { 306 const char *op = write ? "wrmsr" : "rdmsr"; 307 308 if (ignore_msrs) { 309 if (report_ignored_msrs) 310 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", 311 op, msr, data); 312 /* Mask the error */ 313 return true; 314 } else { 315 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", 316 op, msr, data); 317 return false; 318 } 319 } 320 321 static struct kmem_cache *kvm_alloc_emulator_cache(void) 322 { 323 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); 324 unsigned int size = sizeof(struct x86_emulate_ctxt); 325 326 return kmem_cache_create_usercopy("x86_emulator", size, 327 __alignof__(struct x86_emulate_ctxt), 328 SLAB_ACCOUNT, useroffset, 329 size - useroffset, NULL); 330 } 331 332 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 333 334 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 335 { 336 int i; 337 for (i = 0; i < ASYNC_PF_PER_VCPU; i++) 338 vcpu->arch.apf.gfns[i] = ~0; 339 } 340 341 static void kvm_on_user_return(struct user_return_notifier *urn) 342 { 343 unsigned slot; 344 struct kvm_user_return_msrs *msrs 345 = container_of(urn, struct kvm_user_return_msrs, urn); 346 struct kvm_user_return_msr_values *values; 347 unsigned long flags; 348 349 /* 350 * Disabling irqs at this point since the following code could be 351 * interrupted and executed through kvm_arch_hardware_disable() 352 */ 353 local_irq_save(flags); 354 if (msrs->registered) { 355 msrs->registered = false; 356 user_return_notifier_unregister(urn); 357 } 358 local_irq_restore(flags); 359 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { 360 values = &msrs->values[slot]; 361 if (values->host != values->curr) { 362 wrmsrl(kvm_uret_msrs_list[slot], values->host); 363 values->curr = values->host; 364 } 365 } 366 } 367 368 static int kvm_probe_user_return_msr(u32 msr) 369 { 370 u64 val; 371 int ret; 372 373 preempt_disable(); 374 ret = rdmsrl_safe(msr, &val); 375 if (ret) 376 goto out; 377 ret = wrmsrl_safe(msr, val); 378 out: 379 preempt_enable(); 380 return ret; 381 } 382 383 int kvm_add_user_return_msr(u32 msr) 384 { 385 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); 386 387 if (kvm_probe_user_return_msr(msr)) 388 return -1; 389 390 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; 391 return kvm_nr_uret_msrs++; 392 } 393 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); 394 395 int kvm_find_user_return_msr(u32 msr) 396 { 397 int i; 398 399 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 400 if (kvm_uret_msrs_list[i] == msr) 401 return i; 402 } 403 return -1; 404 } 405 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); 406 407 static void kvm_user_return_msr_cpu_online(void) 408 { 409 unsigned int cpu = smp_processor_id(); 410 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 411 u64 value; 412 int i; 413 414 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 415 rdmsrl_safe(kvm_uret_msrs_list[i], &value); 416 msrs->values[i].host = value; 417 msrs->values[i].curr = value; 418 } 419 } 420 421 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) 422 { 423 unsigned int cpu = smp_processor_id(); 424 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 425 int err; 426 427 value = (value & mask) | (msrs->values[slot].host & ~mask); 428 if (value == msrs->values[slot].curr) 429 return 0; 430 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); 431 if (err) 432 return 1; 433 434 msrs->values[slot].curr = value; 435 if (!msrs->registered) { 436 msrs->urn.on_user_return = kvm_on_user_return; 437 user_return_notifier_register(&msrs->urn); 438 msrs->registered = true; 439 } 440 return 0; 441 } 442 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); 443 444 static void drop_user_return_notifiers(void) 445 { 446 unsigned int cpu = smp_processor_id(); 447 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 448 449 if (msrs->registered) 450 kvm_on_user_return(&msrs->urn); 451 } 452 453 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 454 { 455 return vcpu->arch.apic_base; 456 } 457 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 458 459 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 460 { 461 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 462 } 463 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 464 465 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 466 { 467 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 468 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 469 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | 470 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 471 472 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 473 return 1; 474 if (!msr_info->host_initiated) { 475 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 476 return 1; 477 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 478 return 1; 479 } 480 481 kvm_lapic_set_base(vcpu, msr_info->data); 482 kvm_recalculate_apic_map(vcpu->kvm); 483 return 0; 484 } 485 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 486 487 /* 488 * Handle a fault on a hardware virtualization (VMX or SVM) instruction. 489 * 490 * Hardware virtualization extension instructions may fault if a reboot turns 491 * off virtualization while processes are running. Usually after catching the 492 * fault we just panic; during reboot instead the instruction is ignored. 493 */ 494 noinstr void kvm_spurious_fault(void) 495 { 496 /* Fault while not rebooting. We want the trace. */ 497 BUG_ON(!kvm_rebooting); 498 } 499 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 500 501 #define EXCPT_BENIGN 0 502 #define EXCPT_CONTRIBUTORY 1 503 #define EXCPT_PF 2 504 505 static int exception_class(int vector) 506 { 507 switch (vector) { 508 case PF_VECTOR: 509 return EXCPT_PF; 510 case DE_VECTOR: 511 case TS_VECTOR: 512 case NP_VECTOR: 513 case SS_VECTOR: 514 case GP_VECTOR: 515 return EXCPT_CONTRIBUTORY; 516 default: 517 break; 518 } 519 return EXCPT_BENIGN; 520 } 521 522 #define EXCPT_FAULT 0 523 #define EXCPT_TRAP 1 524 #define EXCPT_ABORT 2 525 #define EXCPT_INTERRUPT 3 526 527 static int exception_type(int vector) 528 { 529 unsigned int mask; 530 531 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 532 return EXCPT_INTERRUPT; 533 534 mask = 1 << vector; 535 536 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 537 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 538 return EXCPT_TRAP; 539 540 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 541 return EXCPT_ABORT; 542 543 /* Reserved exceptions will result in fault */ 544 return EXCPT_FAULT; 545 } 546 547 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 548 { 549 unsigned nr = vcpu->arch.exception.nr; 550 bool has_payload = vcpu->arch.exception.has_payload; 551 unsigned long payload = vcpu->arch.exception.payload; 552 553 if (!has_payload) 554 return; 555 556 switch (nr) { 557 case DB_VECTOR: 558 /* 559 * "Certain debug exceptions may clear bit 0-3. The 560 * remaining contents of the DR6 register are never 561 * cleared by the processor". 562 */ 563 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 564 /* 565 * In order to reflect the #DB exception payload in guest 566 * dr6, three components need to be considered: active low 567 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, 568 * DR6_BS and DR6_BT) 569 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. 570 * In the target guest dr6: 571 * FIXED_1 bits should always be set. 572 * Active low bits should be cleared if 1-setting in payload. 573 * Active high bits should be set if 1-setting in payload. 574 * 575 * Note, the payload is compatible with the pending debug 576 * exceptions/exit qualification under VMX, that active_low bits 577 * are active high in payload. 578 * So they need to be flipped for DR6. 579 */ 580 vcpu->arch.dr6 |= DR6_ACTIVE_LOW; 581 vcpu->arch.dr6 |= payload; 582 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; 583 584 /* 585 * The #DB payload is defined as compatible with the 'pending 586 * debug exceptions' field under VMX, not DR6. While bit 12 is 587 * defined in the 'pending debug exceptions' field (enabled 588 * breakpoint), it is reserved and must be zero in DR6. 589 */ 590 vcpu->arch.dr6 &= ~BIT(12); 591 break; 592 case PF_VECTOR: 593 vcpu->arch.cr2 = payload; 594 break; 595 } 596 597 vcpu->arch.exception.has_payload = false; 598 vcpu->arch.exception.payload = 0; 599 } 600 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 601 602 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 603 unsigned nr, bool has_error, u32 error_code, 604 bool has_payload, unsigned long payload, bool reinject) 605 { 606 u32 prev_nr; 607 int class1, class2; 608 609 kvm_make_request(KVM_REQ_EVENT, vcpu); 610 611 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 612 queue: 613 if (reinject) { 614 /* 615 * On vmentry, vcpu->arch.exception.pending is only 616 * true if an event injection was blocked by 617 * nested_run_pending. In that case, however, 618 * vcpu_enter_guest requests an immediate exit, 619 * and the guest shouldn't proceed far enough to 620 * need reinjection. 621 */ 622 WARN_ON_ONCE(vcpu->arch.exception.pending); 623 vcpu->arch.exception.injected = true; 624 if (WARN_ON_ONCE(has_payload)) { 625 /* 626 * A reinjected event has already 627 * delivered its payload. 628 */ 629 has_payload = false; 630 payload = 0; 631 } 632 } else { 633 vcpu->arch.exception.pending = true; 634 vcpu->arch.exception.injected = false; 635 } 636 vcpu->arch.exception.has_error_code = has_error; 637 vcpu->arch.exception.nr = nr; 638 vcpu->arch.exception.error_code = error_code; 639 vcpu->arch.exception.has_payload = has_payload; 640 vcpu->arch.exception.payload = payload; 641 if (!is_guest_mode(vcpu)) 642 kvm_deliver_exception_payload(vcpu); 643 return; 644 } 645 646 /* to check exception */ 647 prev_nr = vcpu->arch.exception.nr; 648 if (prev_nr == DF_VECTOR) { 649 /* triple fault -> shutdown */ 650 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 651 return; 652 } 653 class1 = exception_class(prev_nr); 654 class2 = exception_class(nr); 655 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 656 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 657 /* 658 * Generate double fault per SDM Table 5-5. Set 659 * exception.pending = true so that the double fault 660 * can trigger a nested vmexit. 661 */ 662 vcpu->arch.exception.pending = true; 663 vcpu->arch.exception.injected = false; 664 vcpu->arch.exception.has_error_code = true; 665 vcpu->arch.exception.nr = DF_VECTOR; 666 vcpu->arch.exception.error_code = 0; 667 vcpu->arch.exception.has_payload = false; 668 vcpu->arch.exception.payload = 0; 669 } else 670 /* replace previous exception with a new one in a hope 671 that instruction re-execution will regenerate lost 672 exception */ 673 goto queue; 674 } 675 676 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 677 { 678 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 679 } 680 EXPORT_SYMBOL_GPL(kvm_queue_exception); 681 682 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 683 { 684 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 685 } 686 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 687 688 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 689 unsigned long payload) 690 { 691 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 692 } 693 EXPORT_SYMBOL_GPL(kvm_queue_exception_p); 694 695 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 696 u32 error_code, unsigned long payload) 697 { 698 kvm_multiple_exception(vcpu, nr, true, error_code, 699 true, payload, false); 700 } 701 702 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 703 { 704 if (err) 705 kvm_inject_gp(vcpu, 0); 706 else 707 return kvm_skip_emulated_instruction(vcpu); 708 709 return 1; 710 } 711 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 712 713 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 714 { 715 ++vcpu->stat.pf_guest; 716 vcpu->arch.exception.nested_apf = 717 is_guest_mode(vcpu) && fault->async_page_fault; 718 if (vcpu->arch.exception.nested_apf) { 719 vcpu->arch.apf.nested_apf_token = fault->address; 720 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 721 } else { 722 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 723 fault->address); 724 } 725 } 726 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 727 728 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 729 struct x86_exception *fault) 730 { 731 struct kvm_mmu *fault_mmu; 732 WARN_ON_ONCE(fault->vector != PF_VECTOR); 733 734 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : 735 vcpu->arch.walk_mmu; 736 737 /* 738 * Invalidate the TLB entry for the faulting address, if it exists, 739 * else the access will fault indefinitely (and to emulate hardware). 740 */ 741 if ((fault->error_code & PFERR_PRESENT_MASK) && 742 !(fault->error_code & PFERR_RSVD_MASK)) 743 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, 744 fault_mmu->root_hpa); 745 746 fault_mmu->inject_page_fault(vcpu, fault); 747 return fault->nested_page_fault; 748 } 749 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); 750 751 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 752 { 753 atomic_inc(&vcpu->arch.nmi_queued); 754 kvm_make_request(KVM_REQ_NMI, vcpu); 755 } 756 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 757 758 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 759 { 760 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 761 } 762 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 763 764 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 765 { 766 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 767 } 768 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 769 770 /* 771 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 772 * a #GP and return false. 773 */ 774 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 775 { 776 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) 777 return true; 778 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 779 return false; 780 } 781 EXPORT_SYMBOL_GPL(kvm_require_cpl); 782 783 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 784 { 785 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 786 return true; 787 788 kvm_queue_exception(vcpu, UD_VECTOR); 789 return false; 790 } 791 EXPORT_SYMBOL_GPL(kvm_require_dr); 792 793 /* 794 * This function will be used to read from the physical memory of the currently 795 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 796 * can read from guest physical or from the guest's guest physical memory. 797 */ 798 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 799 gfn_t ngfn, void *data, int offset, int len, 800 u32 access) 801 { 802 struct x86_exception exception; 803 gfn_t real_gfn; 804 gpa_t ngpa; 805 806 ngpa = gfn_to_gpa(ngfn); 807 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 808 if (real_gfn == UNMAPPED_GVA) 809 return -EFAULT; 810 811 real_gfn = gpa_to_gfn(real_gfn); 812 813 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 814 } 815 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 816 817 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) 818 { 819 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); 820 } 821 822 /* 823 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. 824 */ 825 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 826 { 827 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 828 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 829 int i; 830 int ret; 831 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 832 833 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 834 offset * sizeof(u64), sizeof(pdpte), 835 PFERR_USER_MASK|PFERR_WRITE_MASK); 836 if (ret < 0) { 837 ret = 0; 838 goto out; 839 } 840 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 841 if ((pdpte[i] & PT_PRESENT_MASK) && 842 (pdpte[i] & pdptr_rsvd_bits(vcpu))) { 843 ret = 0; 844 goto out; 845 } 846 } 847 ret = 1; 848 849 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 850 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 851 vcpu->arch.pdptrs_from_userspace = false; 852 853 out: 854 855 return ret; 856 } 857 EXPORT_SYMBOL_GPL(load_pdptrs); 858 859 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) 860 { 861 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 862 kvm_clear_async_pf_completion_queue(vcpu); 863 kvm_async_pf_hash_reset(vcpu); 864 } 865 866 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS) 867 kvm_mmu_reset_context(vcpu); 868 869 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 870 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 871 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 872 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 873 } 874 EXPORT_SYMBOL_GPL(kvm_post_set_cr0); 875 876 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 877 { 878 unsigned long old_cr0 = kvm_read_cr0(vcpu); 879 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; 880 881 cr0 |= X86_CR0_ET; 882 883 #ifdef CONFIG_X86_64 884 if (cr0 & 0xffffffff00000000UL) 885 return 1; 886 #endif 887 888 cr0 &= ~CR0_RESERVED_BITS; 889 890 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 891 return 1; 892 893 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 894 return 1; 895 896 #ifdef CONFIG_X86_64 897 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && 898 (cr0 & X86_CR0_PG)) { 899 int cs_db, cs_l; 900 901 if (!is_pae(vcpu)) 902 return 1; 903 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 904 if (cs_l) 905 return 1; 906 } 907 #endif 908 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && 909 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && 910 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) 911 return 1; 912 913 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 914 return 1; 915 916 static_call(kvm_x86_set_cr0)(vcpu, cr0); 917 918 kvm_post_set_cr0(vcpu, old_cr0, cr0); 919 920 return 0; 921 } 922 EXPORT_SYMBOL_GPL(kvm_set_cr0); 923 924 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 925 { 926 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 927 } 928 EXPORT_SYMBOL_GPL(kvm_lmsw); 929 930 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) 931 { 932 if (vcpu->arch.guest_state_protected) 933 return; 934 935 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 936 937 if (vcpu->arch.xcr0 != host_xcr0) 938 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 939 940 if (vcpu->arch.xsaves_enabled && 941 vcpu->arch.ia32_xss != host_xss) 942 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 943 } 944 945 if (static_cpu_has(X86_FEATURE_PKU) && 946 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 947 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && 948 vcpu->arch.pkru != vcpu->arch.host_pkru) 949 write_pkru(vcpu->arch.pkru); 950 } 951 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); 952 953 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) 954 { 955 if (vcpu->arch.guest_state_protected) 956 return; 957 958 if (static_cpu_has(X86_FEATURE_PKU) && 959 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 960 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { 961 vcpu->arch.pkru = rdpkru(); 962 if (vcpu->arch.pkru != vcpu->arch.host_pkru) 963 write_pkru(vcpu->arch.host_pkru); 964 } 965 966 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 967 968 if (vcpu->arch.xcr0 != host_xcr0) 969 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 970 971 if (vcpu->arch.xsaves_enabled && 972 vcpu->arch.ia32_xss != host_xss) 973 wrmsrl(MSR_IA32_XSS, host_xss); 974 } 975 976 } 977 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); 978 979 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 980 { 981 u64 xcr0 = xcr; 982 u64 old_xcr0 = vcpu->arch.xcr0; 983 u64 valid_bits; 984 985 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 986 if (index != XCR_XFEATURE_ENABLED_MASK) 987 return 1; 988 if (!(xcr0 & XFEATURE_MASK_FP)) 989 return 1; 990 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 991 return 1; 992 993 /* 994 * Do not allow the guest to set bits that we do not support 995 * saving. However, xcr0 bit 0 is always set, even if the 996 * emulated CPU does not support XSAVE (see fx_init). 997 */ 998 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 999 if (xcr0 & ~valid_bits) 1000 return 1; 1001 1002 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 1003 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 1004 return 1; 1005 1006 if (xcr0 & XFEATURE_MASK_AVX512) { 1007 if (!(xcr0 & XFEATURE_MASK_YMM)) 1008 return 1; 1009 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 1010 return 1; 1011 } 1012 vcpu->arch.xcr0 = xcr0; 1013 1014 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 1015 kvm_update_cpuid_runtime(vcpu); 1016 return 0; 1017 } 1018 1019 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) 1020 { 1021 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || 1022 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { 1023 kvm_inject_gp(vcpu, 0); 1024 return 1; 1025 } 1026 1027 return kvm_skip_emulated_instruction(vcpu); 1028 } 1029 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); 1030 1031 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1032 { 1033 if (cr4 & cr4_reserved_bits) 1034 return false; 1035 1036 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) 1037 return false; 1038 1039 return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); 1040 } 1041 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); 1042 1043 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) 1044 { 1045 if (((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) || 1046 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 1047 kvm_mmu_reset_context(vcpu); 1048 } 1049 EXPORT_SYMBOL_GPL(kvm_post_set_cr4); 1050 1051 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1052 { 1053 unsigned long old_cr4 = kvm_read_cr4(vcpu); 1054 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 1055 X86_CR4_SMEP; 1056 1057 if (!kvm_is_valid_cr4(vcpu, cr4)) 1058 return 1; 1059 1060 if (is_long_mode(vcpu)) { 1061 if (!(cr4 & X86_CR4_PAE)) 1062 return 1; 1063 if ((cr4 ^ old_cr4) & X86_CR4_LA57) 1064 return 1; 1065 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 1066 && ((cr4 ^ old_cr4) & pdptr_bits) 1067 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 1068 kvm_read_cr3(vcpu))) 1069 return 1; 1070 1071 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 1072 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 1073 return 1; 1074 1075 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 1076 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 1077 return 1; 1078 } 1079 1080 static_call(kvm_x86_set_cr4)(vcpu, cr4); 1081 1082 kvm_post_set_cr4(vcpu, old_cr4, cr4); 1083 1084 return 0; 1085 } 1086 EXPORT_SYMBOL_GPL(kvm_set_cr4); 1087 1088 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) 1089 { 1090 struct kvm_mmu *mmu = vcpu->arch.mmu; 1091 unsigned long roots_to_free = 0; 1092 int i; 1093 1094 /* 1095 * If neither the current CR3 nor any of the prev_roots use the given 1096 * PCID, then nothing needs to be done here because a resync will 1097 * happen anyway before switching to any other CR3. 1098 */ 1099 if (kvm_get_active_pcid(vcpu) == pcid) { 1100 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); 1101 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1102 } 1103 1104 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 1105 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid) 1106 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 1107 1108 kvm_mmu_free_roots(vcpu, mmu, roots_to_free); 1109 } 1110 1111 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 1112 { 1113 bool skip_tlb_flush = false; 1114 unsigned long pcid = 0; 1115 #ifdef CONFIG_X86_64 1116 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 1117 1118 if (pcid_enabled) { 1119 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 1120 cr3 &= ~X86_CR3_PCID_NOFLUSH; 1121 pcid = cr3 & X86_CR3_PCID_MASK; 1122 } 1123 #endif 1124 1125 /* PDPTRs are always reloaded for PAE paging. */ 1126 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) 1127 goto handle_tlb_flush; 1128 1129 /* 1130 * Do not condition the GPA check on long mode, this helper is used to 1131 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that 1132 * the current vCPU mode is accurate. 1133 */ 1134 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) 1135 return 1; 1136 1137 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 1138 return 1; 1139 1140 if (cr3 != kvm_read_cr3(vcpu)) 1141 kvm_mmu_new_pgd(vcpu, cr3); 1142 1143 vcpu->arch.cr3 = cr3; 1144 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 1145 1146 handle_tlb_flush: 1147 /* 1148 * A load of CR3 that flushes the TLB flushes only the current PCID, 1149 * even if PCID is disabled, in which case PCID=0 is flushed. It's a 1150 * moot point in the end because _disabling_ PCID will flush all PCIDs, 1151 * and it's impossible to use a non-zero PCID when PCID is disabled, 1152 * i.e. only PCID=0 can be relevant. 1153 */ 1154 if (!skip_tlb_flush) 1155 kvm_invalidate_pcid(vcpu, pcid); 1156 1157 return 0; 1158 } 1159 EXPORT_SYMBOL_GPL(kvm_set_cr3); 1160 1161 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 1162 { 1163 if (cr8 & CR8_RESERVED_BITS) 1164 return 1; 1165 if (lapic_in_kernel(vcpu)) 1166 kvm_lapic_set_tpr(vcpu, cr8); 1167 else 1168 vcpu->arch.cr8 = cr8; 1169 return 0; 1170 } 1171 EXPORT_SYMBOL_GPL(kvm_set_cr8); 1172 1173 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 1174 { 1175 if (lapic_in_kernel(vcpu)) 1176 return kvm_lapic_get_cr8(vcpu); 1177 else 1178 return vcpu->arch.cr8; 1179 } 1180 EXPORT_SYMBOL_GPL(kvm_get_cr8); 1181 1182 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 1183 { 1184 int i; 1185 1186 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1187 for (i = 0; i < KVM_NR_DB_REGS; i++) 1188 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1189 } 1190 } 1191 1192 void kvm_update_dr7(struct kvm_vcpu *vcpu) 1193 { 1194 unsigned long dr7; 1195 1196 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1197 dr7 = vcpu->arch.guest_debug_dr7; 1198 else 1199 dr7 = vcpu->arch.dr7; 1200 static_call(kvm_x86_set_dr7)(vcpu, dr7); 1201 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1202 if (dr7 & DR7_BP_EN_MASK) 1203 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1204 } 1205 EXPORT_SYMBOL_GPL(kvm_update_dr7); 1206 1207 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1208 { 1209 u64 fixed = DR6_FIXED_1; 1210 1211 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1212 fixed |= DR6_RTM; 1213 1214 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) 1215 fixed |= DR6_BUS_LOCK; 1216 return fixed; 1217 } 1218 1219 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1220 { 1221 size_t size = ARRAY_SIZE(vcpu->arch.db); 1222 1223 switch (dr) { 1224 case 0 ... 3: 1225 vcpu->arch.db[array_index_nospec(dr, size)] = val; 1226 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1227 vcpu->arch.eff_db[dr] = val; 1228 break; 1229 case 4: 1230 case 6: 1231 if (!kvm_dr6_valid(val)) 1232 return 1; /* #GP */ 1233 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1234 break; 1235 case 5: 1236 default: /* 7 */ 1237 if (!kvm_dr7_valid(val)) 1238 return 1; /* #GP */ 1239 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1240 kvm_update_dr7(vcpu); 1241 break; 1242 } 1243 1244 return 0; 1245 } 1246 EXPORT_SYMBOL_GPL(kvm_set_dr); 1247 1248 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1249 { 1250 size_t size = ARRAY_SIZE(vcpu->arch.db); 1251 1252 switch (dr) { 1253 case 0 ... 3: 1254 *val = vcpu->arch.db[array_index_nospec(dr, size)]; 1255 break; 1256 case 4: 1257 case 6: 1258 *val = vcpu->arch.dr6; 1259 break; 1260 case 5: 1261 default: /* 7 */ 1262 *val = vcpu->arch.dr7; 1263 break; 1264 } 1265 } 1266 EXPORT_SYMBOL_GPL(kvm_get_dr); 1267 1268 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) 1269 { 1270 u32 ecx = kvm_rcx_read(vcpu); 1271 u64 data; 1272 1273 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { 1274 kvm_inject_gp(vcpu, 0); 1275 return 1; 1276 } 1277 1278 kvm_rax_write(vcpu, (u32)data); 1279 kvm_rdx_write(vcpu, data >> 32); 1280 return kvm_skip_emulated_instruction(vcpu); 1281 } 1282 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); 1283 1284 /* 1285 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1286 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1287 * 1288 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) 1289 * extract the supported MSRs from the related const lists. 1290 * msrs_to_save is selected from the msrs_to_save_all to reflect the 1291 * capabilities of the host cpu. This capabilities test skips MSRs that are 1292 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs 1293 * may depend on host virtualization features rather than host cpu features. 1294 */ 1295 1296 static const u32 msrs_to_save_all[] = { 1297 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1298 MSR_STAR, 1299 #ifdef CONFIG_X86_64 1300 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1301 #endif 1302 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1303 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1304 MSR_IA32_SPEC_CTRL, 1305 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1306 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1307 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1308 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1309 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1310 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1311 MSR_IA32_UMWAIT_CONTROL, 1312 1313 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, 1314 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, 1315 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, 1316 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 1317 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, 1318 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, 1319 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, 1320 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, 1321 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, 1322 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, 1323 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, 1324 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, 1325 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, 1326 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, 1327 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, 1328 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, 1329 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, 1330 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, 1331 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, 1332 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, 1333 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, 1334 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, 1335 1336 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3, 1337 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3, 1338 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2, 1339 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, 1340 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, 1341 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, 1342 }; 1343 1344 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; 1345 static unsigned num_msrs_to_save; 1346 1347 static const u32 emulated_msrs_all[] = { 1348 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1349 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1350 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1351 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1352 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1353 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1354 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1355 HV_X64_MSR_RESET, 1356 HV_X64_MSR_VP_INDEX, 1357 HV_X64_MSR_VP_RUNTIME, 1358 HV_X64_MSR_SCONTROL, 1359 HV_X64_MSR_STIMER0_CONFIG, 1360 HV_X64_MSR_VP_ASSIST_PAGE, 1361 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1362 HV_X64_MSR_TSC_EMULATION_STATUS, 1363 HV_X64_MSR_SYNDBG_OPTIONS, 1364 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, 1365 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, 1366 HV_X64_MSR_SYNDBG_PENDING_BUFFER, 1367 1368 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1369 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, 1370 1371 MSR_IA32_TSC_ADJUST, 1372 MSR_IA32_TSC_DEADLINE, 1373 MSR_IA32_ARCH_CAPABILITIES, 1374 MSR_IA32_PERF_CAPABILITIES, 1375 MSR_IA32_MISC_ENABLE, 1376 MSR_IA32_MCG_STATUS, 1377 MSR_IA32_MCG_CTL, 1378 MSR_IA32_MCG_EXT_CTL, 1379 MSR_IA32_SMBASE, 1380 MSR_SMI_COUNT, 1381 MSR_PLATFORM_INFO, 1382 MSR_MISC_FEATURES_ENABLES, 1383 MSR_AMD64_VIRT_SPEC_CTRL, 1384 MSR_IA32_POWER_CTL, 1385 MSR_IA32_UCODE_REV, 1386 1387 /* 1388 * The following list leaves out MSRs whose values are determined 1389 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. 1390 * We always support the "true" VMX control MSRs, even if the host 1391 * processor does not, so I am putting these registers here rather 1392 * than in msrs_to_save_all. 1393 */ 1394 MSR_IA32_VMX_BASIC, 1395 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1396 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1397 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1398 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1399 MSR_IA32_VMX_MISC, 1400 MSR_IA32_VMX_CR0_FIXED0, 1401 MSR_IA32_VMX_CR4_FIXED0, 1402 MSR_IA32_VMX_VMCS_ENUM, 1403 MSR_IA32_VMX_PROCBASED_CTLS2, 1404 MSR_IA32_VMX_EPT_VPID_CAP, 1405 MSR_IA32_VMX_VMFUNC, 1406 1407 MSR_K7_HWCR, 1408 MSR_KVM_POLL_CONTROL, 1409 }; 1410 1411 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; 1412 static unsigned num_emulated_msrs; 1413 1414 /* 1415 * List of msr numbers which are used to expose MSR-based features that 1416 * can be used by a hypervisor to validate requested CPU features. 1417 */ 1418 static const u32 msr_based_features_all[] = { 1419 MSR_IA32_VMX_BASIC, 1420 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1421 MSR_IA32_VMX_PINBASED_CTLS, 1422 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1423 MSR_IA32_VMX_PROCBASED_CTLS, 1424 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1425 MSR_IA32_VMX_EXIT_CTLS, 1426 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1427 MSR_IA32_VMX_ENTRY_CTLS, 1428 MSR_IA32_VMX_MISC, 1429 MSR_IA32_VMX_CR0_FIXED0, 1430 MSR_IA32_VMX_CR0_FIXED1, 1431 MSR_IA32_VMX_CR4_FIXED0, 1432 MSR_IA32_VMX_CR4_FIXED1, 1433 MSR_IA32_VMX_VMCS_ENUM, 1434 MSR_IA32_VMX_PROCBASED_CTLS2, 1435 MSR_IA32_VMX_EPT_VPID_CAP, 1436 MSR_IA32_VMX_VMFUNC, 1437 1438 MSR_F10H_DECFG, 1439 MSR_IA32_UCODE_REV, 1440 MSR_IA32_ARCH_CAPABILITIES, 1441 MSR_IA32_PERF_CAPABILITIES, 1442 }; 1443 1444 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; 1445 static unsigned int num_msr_based_features; 1446 1447 static u64 kvm_get_arch_capabilities(void) 1448 { 1449 u64 data = 0; 1450 1451 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1452 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); 1453 1454 /* 1455 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that 1456 * the nested hypervisor runs with NX huge pages. If it is not, 1457 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other 1458 * L1 guests, so it need not worry about its own (L2) guests. 1459 */ 1460 data |= ARCH_CAP_PSCHANGE_MC_NO; 1461 1462 /* 1463 * If we're doing cache flushes (either "always" or "cond") 1464 * we will do one whenever the guest does a vmlaunch/vmresume. 1465 * If an outer hypervisor is doing the cache flush for us 1466 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1467 * capability to the guest too, and if EPT is disabled we're not 1468 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1469 * require a nested hypervisor to do a flush of its own. 1470 */ 1471 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1472 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1473 1474 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) 1475 data |= ARCH_CAP_RDCL_NO; 1476 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1477 data |= ARCH_CAP_SSB_NO; 1478 if (!boot_cpu_has_bug(X86_BUG_MDS)) 1479 data |= ARCH_CAP_MDS_NO; 1480 1481 if (!boot_cpu_has(X86_FEATURE_RTM)) { 1482 /* 1483 * If RTM=0 because the kernel has disabled TSX, the host might 1484 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 1485 * and therefore knows that there cannot be TAA) but keep 1486 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, 1487 * and we want to allow migrating those guests to tsx=off hosts. 1488 */ 1489 data &= ~ARCH_CAP_TAA_NO; 1490 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { 1491 data |= ARCH_CAP_TAA_NO; 1492 } else { 1493 /* 1494 * Nothing to do here; we emulate TSX_CTRL if present on the 1495 * host so the guest can choose between disabling TSX or 1496 * using VERW to clear CPU buffers. 1497 */ 1498 } 1499 1500 return data; 1501 } 1502 1503 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1504 { 1505 switch (msr->index) { 1506 case MSR_IA32_ARCH_CAPABILITIES: 1507 msr->data = kvm_get_arch_capabilities(); 1508 break; 1509 case MSR_IA32_UCODE_REV: 1510 rdmsrl_safe(msr->index, &msr->data); 1511 break; 1512 default: 1513 return static_call(kvm_x86_get_msr_feature)(msr); 1514 } 1515 return 0; 1516 } 1517 1518 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1519 { 1520 struct kvm_msr_entry msr; 1521 int r; 1522 1523 msr.index = index; 1524 r = kvm_get_msr_feature(&msr); 1525 1526 if (r == KVM_MSR_RET_INVALID) { 1527 /* Unconditionally clear the output for simplicity */ 1528 *data = 0; 1529 if (kvm_msr_ignored_check(index, 0, false)) 1530 r = 0; 1531 } 1532 1533 if (r) 1534 return r; 1535 1536 *data = msr.data; 1537 1538 return 0; 1539 } 1540 1541 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1542 { 1543 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1544 return false; 1545 1546 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1547 return false; 1548 1549 if (efer & (EFER_LME | EFER_LMA) && 1550 !guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1551 return false; 1552 1553 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) 1554 return false; 1555 1556 return true; 1557 1558 } 1559 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1560 { 1561 if (efer & efer_reserved_bits) 1562 return false; 1563 1564 return __kvm_valid_efer(vcpu, efer); 1565 } 1566 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1567 1568 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1569 { 1570 u64 old_efer = vcpu->arch.efer; 1571 u64 efer = msr_info->data; 1572 int r; 1573 1574 if (efer & efer_reserved_bits) 1575 return 1; 1576 1577 if (!msr_info->host_initiated) { 1578 if (!__kvm_valid_efer(vcpu, efer)) 1579 return 1; 1580 1581 if (is_paging(vcpu) && 1582 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1583 return 1; 1584 } 1585 1586 efer &= ~EFER_LMA; 1587 efer |= vcpu->arch.efer & EFER_LMA; 1588 1589 r = static_call(kvm_x86_set_efer)(vcpu, efer); 1590 if (r) { 1591 WARN_ON(r > 0); 1592 return r; 1593 } 1594 1595 /* Update reserved bits */ 1596 if ((efer ^ old_efer) & EFER_NX) 1597 kvm_mmu_reset_context(vcpu); 1598 1599 return 0; 1600 } 1601 1602 void kvm_enable_efer_bits(u64 mask) 1603 { 1604 efer_reserved_bits &= ~mask; 1605 } 1606 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1607 1608 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) 1609 { 1610 struct kvm_x86_msr_filter *msr_filter; 1611 struct msr_bitmap_range *ranges; 1612 struct kvm *kvm = vcpu->kvm; 1613 bool allowed; 1614 int idx; 1615 u32 i; 1616 1617 /* x2APIC MSRs do not support filtering. */ 1618 if (index >= 0x800 && index <= 0x8ff) 1619 return true; 1620 1621 idx = srcu_read_lock(&kvm->srcu); 1622 1623 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); 1624 if (!msr_filter) { 1625 allowed = true; 1626 goto out; 1627 } 1628 1629 allowed = msr_filter->default_allow; 1630 ranges = msr_filter->ranges; 1631 1632 for (i = 0; i < msr_filter->count; i++) { 1633 u32 start = ranges[i].base; 1634 u32 end = start + ranges[i].nmsrs; 1635 u32 flags = ranges[i].flags; 1636 unsigned long *bitmap = ranges[i].bitmap; 1637 1638 if ((index >= start) && (index < end) && (flags & type)) { 1639 allowed = !!test_bit(index - start, bitmap); 1640 break; 1641 } 1642 } 1643 1644 out: 1645 srcu_read_unlock(&kvm->srcu, idx); 1646 1647 return allowed; 1648 } 1649 EXPORT_SYMBOL_GPL(kvm_msr_allowed); 1650 1651 /* 1652 * Write @data into the MSR specified by @index. Select MSR specific fault 1653 * checks are bypassed if @host_initiated is %true. 1654 * Returns 0 on success, non-0 otherwise. 1655 * Assumes vcpu_load() was already called. 1656 */ 1657 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, 1658 bool host_initiated) 1659 { 1660 struct msr_data msr; 1661 1662 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) 1663 return KVM_MSR_RET_FILTERED; 1664 1665 switch (index) { 1666 case MSR_FS_BASE: 1667 case MSR_GS_BASE: 1668 case MSR_KERNEL_GS_BASE: 1669 case MSR_CSTAR: 1670 case MSR_LSTAR: 1671 if (is_noncanonical_address(data, vcpu)) 1672 return 1; 1673 break; 1674 case MSR_IA32_SYSENTER_EIP: 1675 case MSR_IA32_SYSENTER_ESP: 1676 /* 1677 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1678 * non-canonical address is written on Intel but not on 1679 * AMD (which ignores the top 32-bits, because it does 1680 * not implement 64-bit SYSENTER). 1681 * 1682 * 64-bit code should hence be able to write a non-canonical 1683 * value on AMD. Making the address canonical ensures that 1684 * vmentry does not fail on Intel after writing a non-canonical 1685 * value, and that something deterministic happens if the guest 1686 * invokes 64-bit SYSENTER. 1687 */ 1688 data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); 1689 break; 1690 case MSR_TSC_AUX: 1691 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1692 return 1; 1693 1694 if (!host_initiated && 1695 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1696 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1697 return 1; 1698 1699 /* 1700 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has 1701 * incomplete and conflicting architectural behavior. Current 1702 * AMD CPUs completely ignore bits 63:32, i.e. they aren't 1703 * reserved and always read as zeros. Enforce Intel's reserved 1704 * bits check if and only if the guest CPU is Intel, and clear 1705 * the bits in all other cases. This ensures cross-vendor 1706 * migration will provide consistent behavior for the guest. 1707 */ 1708 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) 1709 return 1; 1710 1711 data = (u32)data; 1712 break; 1713 } 1714 1715 msr.data = data; 1716 msr.index = index; 1717 msr.host_initiated = host_initiated; 1718 1719 return static_call(kvm_x86_set_msr)(vcpu, &msr); 1720 } 1721 1722 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, 1723 u32 index, u64 data, bool host_initiated) 1724 { 1725 int ret = __kvm_set_msr(vcpu, index, data, host_initiated); 1726 1727 if (ret == KVM_MSR_RET_INVALID) 1728 if (kvm_msr_ignored_check(index, data, true)) 1729 ret = 0; 1730 1731 return ret; 1732 } 1733 1734 /* 1735 * Read the MSR specified by @index into @data. Select MSR specific fault 1736 * checks are bypassed if @host_initiated is %true. 1737 * Returns 0 on success, non-0 otherwise. 1738 * Assumes vcpu_load() was already called. 1739 */ 1740 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1741 bool host_initiated) 1742 { 1743 struct msr_data msr; 1744 int ret; 1745 1746 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) 1747 return KVM_MSR_RET_FILTERED; 1748 1749 switch (index) { 1750 case MSR_TSC_AUX: 1751 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1752 return 1; 1753 1754 if (!host_initiated && 1755 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1756 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1757 return 1; 1758 break; 1759 } 1760 1761 msr.index = index; 1762 msr.host_initiated = host_initiated; 1763 1764 ret = static_call(kvm_x86_get_msr)(vcpu, &msr); 1765 if (!ret) 1766 *data = msr.data; 1767 return ret; 1768 } 1769 1770 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, 1771 u32 index, u64 *data, bool host_initiated) 1772 { 1773 int ret = __kvm_get_msr(vcpu, index, data, host_initiated); 1774 1775 if (ret == KVM_MSR_RET_INVALID) { 1776 /* Unconditionally clear *data for simplicity */ 1777 *data = 0; 1778 if (kvm_msr_ignored_check(index, 0, false)) 1779 ret = 0; 1780 } 1781 1782 return ret; 1783 } 1784 1785 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1786 { 1787 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1788 } 1789 EXPORT_SYMBOL_GPL(kvm_get_msr); 1790 1791 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) 1792 { 1793 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1794 } 1795 EXPORT_SYMBOL_GPL(kvm_set_msr); 1796 1797 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) 1798 { 1799 int err = vcpu->run->msr.error; 1800 if (!err) { 1801 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); 1802 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); 1803 } 1804 1805 return static_call(kvm_x86_complete_emulated_msr)(vcpu, err); 1806 } 1807 1808 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu) 1809 { 1810 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); 1811 } 1812 1813 static u64 kvm_msr_reason(int r) 1814 { 1815 switch (r) { 1816 case KVM_MSR_RET_INVALID: 1817 return KVM_MSR_EXIT_REASON_UNKNOWN; 1818 case KVM_MSR_RET_FILTERED: 1819 return KVM_MSR_EXIT_REASON_FILTER; 1820 default: 1821 return KVM_MSR_EXIT_REASON_INVAL; 1822 } 1823 } 1824 1825 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, 1826 u32 exit_reason, u64 data, 1827 int (*completion)(struct kvm_vcpu *vcpu), 1828 int r) 1829 { 1830 u64 msr_reason = kvm_msr_reason(r); 1831 1832 /* Check if the user wanted to know about this MSR fault */ 1833 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) 1834 return 0; 1835 1836 vcpu->run->exit_reason = exit_reason; 1837 vcpu->run->msr.error = 0; 1838 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); 1839 vcpu->run->msr.reason = msr_reason; 1840 vcpu->run->msr.index = index; 1841 vcpu->run->msr.data = data; 1842 vcpu->arch.complete_userspace_io = completion; 1843 1844 return 1; 1845 } 1846 1847 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r) 1848 { 1849 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0, 1850 complete_emulated_rdmsr, r); 1851 } 1852 1853 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r) 1854 { 1855 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data, 1856 complete_emulated_wrmsr, r); 1857 } 1858 1859 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) 1860 { 1861 u32 ecx = kvm_rcx_read(vcpu); 1862 u64 data; 1863 int r; 1864 1865 r = kvm_get_msr(vcpu, ecx, &data); 1866 1867 /* MSR read failed? See if we should ask user space */ 1868 if (r && kvm_get_msr_user_space(vcpu, ecx, r)) { 1869 /* Bounce to user space */ 1870 return 0; 1871 } 1872 1873 if (!r) { 1874 trace_kvm_msr_read(ecx, data); 1875 1876 kvm_rax_write(vcpu, data & -1u); 1877 kvm_rdx_write(vcpu, (data >> 32) & -1u); 1878 } else { 1879 trace_kvm_msr_read_ex(ecx); 1880 } 1881 1882 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1883 } 1884 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); 1885 1886 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) 1887 { 1888 u32 ecx = kvm_rcx_read(vcpu); 1889 u64 data = kvm_read_edx_eax(vcpu); 1890 int r; 1891 1892 r = kvm_set_msr(vcpu, ecx, data); 1893 1894 /* MSR write failed? See if we should ask user space */ 1895 if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) 1896 /* Bounce to user space */ 1897 return 0; 1898 1899 /* Signal all other negative errors to userspace */ 1900 if (r < 0) 1901 return r; 1902 1903 if (!r) 1904 trace_kvm_msr_write(ecx, data); 1905 else 1906 trace_kvm_msr_write_ex(ecx, data); 1907 1908 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1909 } 1910 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); 1911 1912 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) 1913 { 1914 return kvm_skip_emulated_instruction(vcpu); 1915 } 1916 EXPORT_SYMBOL_GPL(kvm_emulate_as_nop); 1917 1918 int kvm_emulate_invd(struct kvm_vcpu *vcpu) 1919 { 1920 /* Treat an INVD instruction as a NOP and just skip it. */ 1921 return kvm_emulate_as_nop(vcpu); 1922 } 1923 EXPORT_SYMBOL_GPL(kvm_emulate_invd); 1924 1925 int kvm_emulate_mwait(struct kvm_vcpu *vcpu) 1926 { 1927 pr_warn_once("kvm: MWAIT instruction emulated as NOP!\n"); 1928 return kvm_emulate_as_nop(vcpu); 1929 } 1930 EXPORT_SYMBOL_GPL(kvm_emulate_mwait); 1931 1932 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) 1933 { 1934 kvm_queue_exception(vcpu, UD_VECTOR); 1935 return 1; 1936 } 1937 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); 1938 1939 int kvm_emulate_monitor(struct kvm_vcpu *vcpu) 1940 { 1941 pr_warn_once("kvm: MONITOR instruction emulated as NOP!\n"); 1942 return kvm_emulate_as_nop(vcpu); 1943 } 1944 EXPORT_SYMBOL_GPL(kvm_emulate_monitor); 1945 1946 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) 1947 { 1948 xfer_to_guest_mode_prepare(); 1949 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || 1950 xfer_to_guest_mode_work_pending(); 1951 } 1952 1953 /* 1954 * The fast path for frequent and performance sensitive wrmsr emulation, 1955 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces 1956 * the latency of virtual IPI by avoiding the expensive bits of transitioning 1957 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the 1958 * other cases which must be called after interrupts are enabled on the host. 1959 */ 1960 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) 1961 { 1962 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) 1963 return 1; 1964 1965 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && 1966 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && 1967 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && 1968 ((u32)(data >> 32) != X2APIC_BROADCAST)) { 1969 1970 data &= ~(1 << 12); 1971 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); 1972 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); 1973 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); 1974 trace_kvm_apic_write(APIC_ICR, (u32)data); 1975 return 0; 1976 } 1977 1978 return 1; 1979 } 1980 1981 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) 1982 { 1983 if (!kvm_can_use_hv_timer(vcpu)) 1984 return 1; 1985 1986 kvm_set_lapic_tscdeadline_msr(vcpu, data); 1987 return 0; 1988 } 1989 1990 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) 1991 { 1992 u32 msr = kvm_rcx_read(vcpu); 1993 u64 data; 1994 fastpath_t ret = EXIT_FASTPATH_NONE; 1995 1996 switch (msr) { 1997 case APIC_BASE_MSR + (APIC_ICR >> 4): 1998 data = kvm_read_edx_eax(vcpu); 1999 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { 2000 kvm_skip_emulated_instruction(vcpu); 2001 ret = EXIT_FASTPATH_EXIT_HANDLED; 2002 } 2003 break; 2004 case MSR_IA32_TSC_DEADLINE: 2005 data = kvm_read_edx_eax(vcpu); 2006 if (!handle_fastpath_set_tscdeadline(vcpu, data)) { 2007 kvm_skip_emulated_instruction(vcpu); 2008 ret = EXIT_FASTPATH_REENTER_GUEST; 2009 } 2010 break; 2011 default: 2012 break; 2013 } 2014 2015 if (ret != EXIT_FASTPATH_NONE) 2016 trace_kvm_msr_write(msr, data); 2017 2018 return ret; 2019 } 2020 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); 2021 2022 /* 2023 * Adapt set_msr() to msr_io()'s calling convention 2024 */ 2025 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2026 { 2027 return kvm_get_msr_ignored_check(vcpu, index, data, true); 2028 } 2029 2030 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2031 { 2032 return kvm_set_msr_ignored_check(vcpu, index, *data, true); 2033 } 2034 2035 #ifdef CONFIG_X86_64 2036 struct pvclock_clock { 2037 int vclock_mode; 2038 u64 cycle_last; 2039 u64 mask; 2040 u32 mult; 2041 u32 shift; 2042 u64 base_cycles; 2043 u64 offset; 2044 }; 2045 2046 struct pvclock_gtod_data { 2047 seqcount_t seq; 2048 2049 struct pvclock_clock clock; /* extract of a clocksource struct */ 2050 struct pvclock_clock raw_clock; /* extract of a clocksource struct */ 2051 2052 ktime_t offs_boot; 2053 u64 wall_time_sec; 2054 }; 2055 2056 static struct pvclock_gtod_data pvclock_gtod_data; 2057 2058 static void update_pvclock_gtod(struct timekeeper *tk) 2059 { 2060 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 2061 2062 write_seqcount_begin(&vdata->seq); 2063 2064 /* copy pvclock gtod data */ 2065 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; 2066 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 2067 vdata->clock.mask = tk->tkr_mono.mask; 2068 vdata->clock.mult = tk->tkr_mono.mult; 2069 vdata->clock.shift = tk->tkr_mono.shift; 2070 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 2071 vdata->clock.offset = tk->tkr_mono.base; 2072 2073 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; 2074 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; 2075 vdata->raw_clock.mask = tk->tkr_raw.mask; 2076 vdata->raw_clock.mult = tk->tkr_raw.mult; 2077 vdata->raw_clock.shift = tk->tkr_raw.shift; 2078 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; 2079 vdata->raw_clock.offset = tk->tkr_raw.base; 2080 2081 vdata->wall_time_sec = tk->xtime_sec; 2082 2083 vdata->offs_boot = tk->offs_boot; 2084 2085 write_seqcount_end(&vdata->seq); 2086 } 2087 2088 static s64 get_kvmclock_base_ns(void) 2089 { 2090 /* Count up from boot time, but with the frequency of the raw clock. */ 2091 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); 2092 } 2093 #else 2094 static s64 get_kvmclock_base_ns(void) 2095 { 2096 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ 2097 return ktime_get_boottime_ns(); 2098 } 2099 #endif 2100 2101 void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) 2102 { 2103 int version; 2104 int r; 2105 struct pvclock_wall_clock wc; 2106 u32 wc_sec_hi; 2107 u64 wall_nsec; 2108 2109 if (!wall_clock) 2110 return; 2111 2112 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 2113 if (r) 2114 return; 2115 2116 if (version & 1) 2117 ++version; /* first time write, random junk */ 2118 2119 ++version; 2120 2121 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 2122 return; 2123 2124 /* 2125 * The guest calculates current wall clock time by adding 2126 * system time (updated by kvm_guest_time_update below) to the 2127 * wall clock specified here. We do the reverse here. 2128 */ 2129 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); 2130 2131 wc.nsec = do_div(wall_nsec, 1000000000); 2132 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ 2133 wc.version = version; 2134 2135 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 2136 2137 if (sec_hi_ofs) { 2138 wc_sec_hi = wall_nsec >> 32; 2139 kvm_write_guest(kvm, wall_clock + sec_hi_ofs, 2140 &wc_sec_hi, sizeof(wc_sec_hi)); 2141 } 2142 2143 version++; 2144 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 2145 } 2146 2147 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, 2148 bool old_msr, bool host_initiated) 2149 { 2150 struct kvm_arch *ka = &vcpu->kvm->arch; 2151 2152 if (vcpu->vcpu_id == 0 && !host_initiated) { 2153 if (ka->boot_vcpu_runs_old_kvmclock != old_msr) 2154 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2155 2156 ka->boot_vcpu_runs_old_kvmclock = old_msr; 2157 } 2158 2159 vcpu->arch.time = system_time; 2160 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2161 2162 /* we verify if the enable bit is set... */ 2163 vcpu->arch.pv_time_enabled = false; 2164 if (!(system_time & 1)) 2165 return; 2166 2167 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, 2168 &vcpu->arch.pv_time, system_time & ~1ULL, 2169 sizeof(struct pvclock_vcpu_time_info))) 2170 vcpu->arch.pv_time_enabled = true; 2171 2172 return; 2173 } 2174 2175 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 2176 { 2177 do_shl32_div32(dividend, divisor); 2178 return dividend; 2179 } 2180 2181 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 2182 s8 *pshift, u32 *pmultiplier) 2183 { 2184 uint64_t scaled64; 2185 int32_t shift = 0; 2186 uint64_t tps64; 2187 uint32_t tps32; 2188 2189 tps64 = base_hz; 2190 scaled64 = scaled_hz; 2191 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 2192 tps64 >>= 1; 2193 shift--; 2194 } 2195 2196 tps32 = (uint32_t)tps64; 2197 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 2198 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 2199 scaled64 >>= 1; 2200 else 2201 tps32 <<= 1; 2202 shift++; 2203 } 2204 2205 *pshift = shift; 2206 *pmultiplier = div_frac(scaled64, tps32); 2207 } 2208 2209 #ifdef CONFIG_X86_64 2210 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 2211 #endif 2212 2213 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 2214 static unsigned long max_tsc_khz; 2215 2216 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 2217 { 2218 u64 v = (u64)khz * (1000000 + ppm); 2219 do_div(v, 1000000); 2220 return v; 2221 } 2222 2223 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier); 2224 2225 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 2226 { 2227 u64 ratio; 2228 2229 /* Guest TSC same frequency as host TSC? */ 2230 if (!scale) { 2231 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); 2232 return 0; 2233 } 2234 2235 /* TSC scaling supported? */ 2236 if (!kvm_has_tsc_control) { 2237 if (user_tsc_khz > tsc_khz) { 2238 vcpu->arch.tsc_catchup = 1; 2239 vcpu->arch.tsc_always_catchup = 1; 2240 return 0; 2241 } else { 2242 pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); 2243 return -1; 2244 } 2245 } 2246 2247 /* TSC scaling required - calculate ratio */ 2248 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 2249 user_tsc_khz, tsc_khz); 2250 2251 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 2252 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 2253 user_tsc_khz); 2254 return -1; 2255 } 2256 2257 kvm_vcpu_write_tsc_multiplier(vcpu, ratio); 2258 return 0; 2259 } 2260 2261 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 2262 { 2263 u32 thresh_lo, thresh_hi; 2264 int use_scaling = 0; 2265 2266 /* tsc_khz can be zero if TSC calibration fails */ 2267 if (user_tsc_khz == 0) { 2268 /* set tsc_scaling_ratio to a safe value */ 2269 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); 2270 return -1; 2271 } 2272 2273 /* Compute a scale to convert nanoseconds in TSC cycles */ 2274 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 2275 &vcpu->arch.virtual_tsc_shift, 2276 &vcpu->arch.virtual_tsc_mult); 2277 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 2278 2279 /* 2280 * Compute the variation in TSC rate which is acceptable 2281 * within the range of tolerance and decide if the 2282 * rate being applied is within that bounds of the hardware 2283 * rate. If so, no scaling or compensation need be done. 2284 */ 2285 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 2286 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 2287 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 2288 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 2289 use_scaling = 1; 2290 } 2291 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 2292 } 2293 2294 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 2295 { 2296 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 2297 vcpu->arch.virtual_tsc_mult, 2298 vcpu->arch.virtual_tsc_shift); 2299 tsc += vcpu->arch.this_tsc_write; 2300 return tsc; 2301 } 2302 2303 static inline int gtod_is_based_on_tsc(int mode) 2304 { 2305 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; 2306 } 2307 2308 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 2309 { 2310 #ifdef CONFIG_X86_64 2311 bool vcpus_matched; 2312 struct kvm_arch *ka = &vcpu->kvm->arch; 2313 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2314 2315 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2316 atomic_read(&vcpu->kvm->online_vcpus)); 2317 2318 /* 2319 * Once the masterclock is enabled, always perform request in 2320 * order to update it. 2321 * 2322 * In order to enable masterclock, the host clocksource must be TSC 2323 * and the vcpus need to have matched TSCs. When that happens, 2324 * perform request to enable masterclock. 2325 */ 2326 if (ka->use_master_clock || 2327 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 2328 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2329 2330 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 2331 atomic_read(&vcpu->kvm->online_vcpus), 2332 ka->use_master_clock, gtod->clock.vclock_mode); 2333 #endif 2334 } 2335 2336 /* 2337 * Multiply tsc by a fixed point number represented by ratio. 2338 * 2339 * The most significant 64-N bits (mult) of ratio represent the 2340 * integral part of the fixed point number; the remaining N bits 2341 * (frac) represent the fractional part, ie. ratio represents a fixed 2342 * point number (mult + frac * 2^(-N)). 2343 * 2344 * N equals to kvm_tsc_scaling_ratio_frac_bits. 2345 */ 2346 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 2347 { 2348 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 2349 } 2350 2351 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc, u64 ratio) 2352 { 2353 u64 _tsc = tsc; 2354 2355 if (ratio != kvm_default_tsc_scaling_ratio) 2356 _tsc = __scale_tsc(ratio, tsc); 2357 2358 return _tsc; 2359 } 2360 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 2361 2362 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 2363 { 2364 u64 tsc; 2365 2366 tsc = kvm_scale_tsc(vcpu, rdtsc(), vcpu->arch.l1_tsc_scaling_ratio); 2367 2368 return target_tsc - tsc; 2369 } 2370 2371 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 2372 { 2373 return vcpu->arch.l1_tsc_offset + 2374 kvm_scale_tsc(vcpu, host_tsc, vcpu->arch.l1_tsc_scaling_ratio); 2375 } 2376 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 2377 2378 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier) 2379 { 2380 u64 nested_offset; 2381 2382 if (l2_multiplier == kvm_default_tsc_scaling_ratio) 2383 nested_offset = l1_offset; 2384 else 2385 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier, 2386 kvm_tsc_scaling_ratio_frac_bits); 2387 2388 nested_offset += l2_offset; 2389 return nested_offset; 2390 } 2391 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset); 2392 2393 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier) 2394 { 2395 if (l2_multiplier != kvm_default_tsc_scaling_ratio) 2396 return mul_u64_u64_shr(l1_multiplier, l2_multiplier, 2397 kvm_tsc_scaling_ratio_frac_bits); 2398 2399 return l1_multiplier; 2400 } 2401 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier); 2402 2403 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset) 2404 { 2405 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 2406 vcpu->arch.l1_tsc_offset, 2407 l1_offset); 2408 2409 vcpu->arch.l1_tsc_offset = l1_offset; 2410 2411 /* 2412 * If we are here because L1 chose not to trap WRMSR to TSC then 2413 * according to the spec this should set L1's TSC (as opposed to 2414 * setting L1's offset for L2). 2415 */ 2416 if (is_guest_mode(vcpu)) 2417 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( 2418 l1_offset, 2419 static_call(kvm_x86_get_l2_tsc_offset)(vcpu), 2420 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2421 else 2422 vcpu->arch.tsc_offset = l1_offset; 2423 2424 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset); 2425 } 2426 2427 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier) 2428 { 2429 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier; 2430 2431 /* Userspace is changing the multiplier while L2 is active */ 2432 if (is_guest_mode(vcpu)) 2433 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( 2434 l1_multiplier, 2435 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2436 else 2437 vcpu->arch.tsc_scaling_ratio = l1_multiplier; 2438 2439 if (kvm_has_tsc_control) 2440 static_call(kvm_x86_write_tsc_multiplier)( 2441 vcpu, vcpu->arch.tsc_scaling_ratio); 2442 } 2443 2444 static inline bool kvm_check_tsc_unstable(void) 2445 { 2446 #ifdef CONFIG_X86_64 2447 /* 2448 * TSC is marked unstable when we're running on Hyper-V, 2449 * 'TSC page' clocksource is good. 2450 */ 2451 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) 2452 return false; 2453 #endif 2454 return check_tsc_unstable(); 2455 } 2456 2457 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) 2458 { 2459 struct kvm *kvm = vcpu->kvm; 2460 u64 offset, ns, elapsed; 2461 unsigned long flags; 2462 bool matched; 2463 bool already_matched; 2464 bool synchronizing = false; 2465 2466 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 2467 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2468 ns = get_kvmclock_base_ns(); 2469 elapsed = ns - kvm->arch.last_tsc_nsec; 2470 2471 if (vcpu->arch.virtual_tsc_khz) { 2472 if (data == 0) { 2473 /* 2474 * detection of vcpu initialization -- need to sync 2475 * with other vCPUs. This particularly helps to keep 2476 * kvm_clock stable after CPU hotplug 2477 */ 2478 synchronizing = true; 2479 } else { 2480 u64 tsc_exp = kvm->arch.last_tsc_write + 2481 nsec_to_cycles(vcpu, elapsed); 2482 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 2483 /* 2484 * Special case: TSC write with a small delta (1 second) 2485 * of virtual cycle time against real time is 2486 * interpreted as an attempt to synchronize the CPU. 2487 */ 2488 synchronizing = data < tsc_exp + tsc_hz && 2489 data + tsc_hz > tsc_exp; 2490 } 2491 } 2492 2493 /* 2494 * For a reliable TSC, we can match TSC offsets, and for an unstable 2495 * TSC, we add elapsed time in this computation. We could let the 2496 * compensation code attempt to catch up if we fall behind, but 2497 * it's better to try to match offsets from the beginning. 2498 */ 2499 if (synchronizing && 2500 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 2501 if (!kvm_check_tsc_unstable()) { 2502 offset = kvm->arch.cur_tsc_offset; 2503 } else { 2504 u64 delta = nsec_to_cycles(vcpu, elapsed); 2505 data += delta; 2506 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2507 } 2508 matched = true; 2509 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 2510 } else { 2511 /* 2512 * We split periods of matched TSC writes into generations. 2513 * For each generation, we track the original measured 2514 * nanosecond time, offset, and write, so if TSCs are in 2515 * sync, we can match exact offset, and if not, we can match 2516 * exact software computation in compute_guest_tsc() 2517 * 2518 * These values are tracked in kvm->arch.cur_xxx variables. 2519 */ 2520 kvm->arch.cur_tsc_generation++; 2521 kvm->arch.cur_tsc_nsec = ns; 2522 kvm->arch.cur_tsc_write = data; 2523 kvm->arch.cur_tsc_offset = offset; 2524 matched = false; 2525 } 2526 2527 /* 2528 * We also track th most recent recorded KHZ, write and time to 2529 * allow the matching interval to be extended at each write. 2530 */ 2531 kvm->arch.last_tsc_nsec = ns; 2532 kvm->arch.last_tsc_write = data; 2533 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 2534 2535 vcpu->arch.last_guest_tsc = data; 2536 2537 /* Keep track of which generation this VCPU has synchronized to */ 2538 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 2539 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 2540 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 2541 2542 kvm_vcpu_write_tsc_offset(vcpu, offset); 2543 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 2544 2545 raw_spin_lock_irqsave(&kvm->arch.pvclock_gtod_sync_lock, flags); 2546 if (!matched) { 2547 kvm->arch.nr_vcpus_matched_tsc = 0; 2548 } else if (!already_matched) { 2549 kvm->arch.nr_vcpus_matched_tsc++; 2550 } 2551 2552 kvm_track_tsc_matching(vcpu); 2553 raw_spin_unlock_irqrestore(&kvm->arch.pvclock_gtod_sync_lock, flags); 2554 } 2555 2556 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 2557 s64 adjustment) 2558 { 2559 u64 tsc_offset = vcpu->arch.l1_tsc_offset; 2560 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 2561 } 2562 2563 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 2564 { 2565 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 2566 WARN_ON(adjustment < 0); 2567 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment, 2568 vcpu->arch.l1_tsc_scaling_ratio); 2569 adjust_tsc_offset_guest(vcpu, adjustment); 2570 } 2571 2572 #ifdef CONFIG_X86_64 2573 2574 static u64 read_tsc(void) 2575 { 2576 u64 ret = (u64)rdtsc_ordered(); 2577 u64 last = pvclock_gtod_data.clock.cycle_last; 2578 2579 if (likely(ret >= last)) 2580 return ret; 2581 2582 /* 2583 * GCC likes to generate cmov here, but this branch is extremely 2584 * predictable (it's just a function of time and the likely is 2585 * very likely) and there's a data dependence, so force GCC 2586 * to generate a branch instead. I don't barrier() because 2587 * we don't actually need a barrier, and if this function 2588 * ever gets inlined it will generate worse code. 2589 */ 2590 asm volatile (""); 2591 return last; 2592 } 2593 2594 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, 2595 int *mode) 2596 { 2597 long v; 2598 u64 tsc_pg_val; 2599 2600 switch (clock->vclock_mode) { 2601 case VDSO_CLOCKMODE_HVCLOCK: 2602 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 2603 tsc_timestamp); 2604 if (tsc_pg_val != U64_MAX) { 2605 /* TSC page valid */ 2606 *mode = VDSO_CLOCKMODE_HVCLOCK; 2607 v = (tsc_pg_val - clock->cycle_last) & 2608 clock->mask; 2609 } else { 2610 /* TSC page invalid */ 2611 *mode = VDSO_CLOCKMODE_NONE; 2612 } 2613 break; 2614 case VDSO_CLOCKMODE_TSC: 2615 *mode = VDSO_CLOCKMODE_TSC; 2616 *tsc_timestamp = read_tsc(); 2617 v = (*tsc_timestamp - clock->cycle_last) & 2618 clock->mask; 2619 break; 2620 default: 2621 *mode = VDSO_CLOCKMODE_NONE; 2622 } 2623 2624 if (*mode == VDSO_CLOCKMODE_NONE) 2625 *tsc_timestamp = v = 0; 2626 2627 return v * clock->mult; 2628 } 2629 2630 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) 2631 { 2632 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2633 unsigned long seq; 2634 int mode; 2635 u64 ns; 2636 2637 do { 2638 seq = read_seqcount_begin(>od->seq); 2639 ns = gtod->raw_clock.base_cycles; 2640 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); 2641 ns >>= gtod->raw_clock.shift; 2642 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); 2643 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2644 *t = ns; 2645 2646 return mode; 2647 } 2648 2649 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 2650 { 2651 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2652 unsigned long seq; 2653 int mode; 2654 u64 ns; 2655 2656 do { 2657 seq = read_seqcount_begin(>od->seq); 2658 ts->tv_sec = gtod->wall_time_sec; 2659 ns = gtod->clock.base_cycles; 2660 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2661 ns >>= gtod->clock.shift; 2662 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2663 2664 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 2665 ts->tv_nsec = ns; 2666 2667 return mode; 2668 } 2669 2670 /* returns true if host is using TSC based clocksource */ 2671 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2672 { 2673 /* checked again under seqlock below */ 2674 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2675 return false; 2676 2677 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, 2678 tsc_timestamp)); 2679 } 2680 2681 /* returns true if host is using TSC based clocksource */ 2682 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 2683 u64 *tsc_timestamp) 2684 { 2685 /* checked again under seqlock below */ 2686 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2687 return false; 2688 2689 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 2690 } 2691 #endif 2692 2693 /* 2694 * 2695 * Assuming a stable TSC across physical CPUS, and a stable TSC 2696 * across virtual CPUs, the following condition is possible. 2697 * Each numbered line represents an event visible to both 2698 * CPUs at the next numbered event. 2699 * 2700 * "timespecX" represents host monotonic time. "tscX" represents 2701 * RDTSC value. 2702 * 2703 * VCPU0 on CPU0 | VCPU1 on CPU1 2704 * 2705 * 1. read timespec0,tsc0 2706 * 2. | timespec1 = timespec0 + N 2707 * | tsc1 = tsc0 + M 2708 * 3. transition to guest | transition to guest 2709 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 2710 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 2711 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 2712 * 2713 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 2714 * 2715 * - ret0 < ret1 2716 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 2717 * ... 2718 * - 0 < N - M => M < N 2719 * 2720 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 2721 * always the case (the difference between two distinct xtime instances 2722 * might be smaller then the difference between corresponding TSC reads, 2723 * when updating guest vcpus pvclock areas). 2724 * 2725 * To avoid that problem, do not allow visibility of distinct 2726 * system_timestamp/tsc_timestamp values simultaneously: use a master 2727 * copy of host monotonic time values. Update that master copy 2728 * in lockstep. 2729 * 2730 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2731 * 2732 */ 2733 2734 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2735 { 2736 #ifdef CONFIG_X86_64 2737 struct kvm_arch *ka = &kvm->arch; 2738 int vclock_mode; 2739 bool host_tsc_clocksource, vcpus_matched; 2740 2741 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2742 atomic_read(&kvm->online_vcpus)); 2743 2744 /* 2745 * If the host uses TSC clock, then passthrough TSC as stable 2746 * to the guest. 2747 */ 2748 host_tsc_clocksource = kvm_get_time_and_clockread( 2749 &ka->master_kernel_ns, 2750 &ka->master_cycle_now); 2751 2752 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2753 && !ka->backwards_tsc_observed 2754 && !ka->boot_vcpu_runs_old_kvmclock; 2755 2756 if (ka->use_master_clock) 2757 atomic_set(&kvm_guest_has_master_clock, 1); 2758 2759 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2760 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2761 vcpus_matched); 2762 #endif 2763 } 2764 2765 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2766 { 2767 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2768 } 2769 2770 static void kvm_gen_update_masterclock(struct kvm *kvm) 2771 { 2772 #ifdef CONFIG_X86_64 2773 int i; 2774 struct kvm_vcpu *vcpu; 2775 struct kvm_arch *ka = &kvm->arch; 2776 unsigned long flags; 2777 2778 kvm_hv_invalidate_tsc_page(kvm); 2779 2780 kvm_make_mclock_inprogress_request(kvm); 2781 2782 /* no guest entries from this point */ 2783 raw_spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 2784 pvclock_update_vm_gtod_copy(kvm); 2785 raw_spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2786 2787 kvm_for_each_vcpu(i, vcpu, kvm) 2788 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2789 2790 /* guest entries allowed */ 2791 kvm_for_each_vcpu(i, vcpu, kvm) 2792 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2793 #endif 2794 } 2795 2796 u64 get_kvmclock_ns(struct kvm *kvm) 2797 { 2798 struct kvm_arch *ka = &kvm->arch; 2799 struct pvclock_vcpu_time_info hv_clock; 2800 unsigned long flags; 2801 u64 ret; 2802 2803 raw_spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 2804 if (!ka->use_master_clock) { 2805 raw_spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2806 return get_kvmclock_base_ns() + ka->kvmclock_offset; 2807 } 2808 2809 hv_clock.tsc_timestamp = ka->master_cycle_now; 2810 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2811 raw_spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2812 2813 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2814 get_cpu(); 2815 2816 if (__this_cpu_read(cpu_tsc_khz)) { 2817 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2818 &hv_clock.tsc_shift, 2819 &hv_clock.tsc_to_system_mul); 2820 ret = __pvclock_read_cycles(&hv_clock, rdtsc()); 2821 } else 2822 ret = get_kvmclock_base_ns() + ka->kvmclock_offset; 2823 2824 put_cpu(); 2825 2826 return ret; 2827 } 2828 2829 static void kvm_setup_pvclock_page(struct kvm_vcpu *v, 2830 struct gfn_to_hva_cache *cache, 2831 unsigned int offset) 2832 { 2833 struct kvm_vcpu_arch *vcpu = &v->arch; 2834 struct pvclock_vcpu_time_info guest_hv_clock; 2835 2836 if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache, 2837 &guest_hv_clock, offset, sizeof(guest_hv_clock)))) 2838 return; 2839 2840 /* This VCPU is paused, but it's legal for a guest to read another 2841 * VCPU's kvmclock, so we really have to follow the specification where 2842 * it says that version is odd if data is being modified, and even after 2843 * it is consistent. 2844 * 2845 * Version field updates must be kept separate. This is because 2846 * kvm_write_guest_cached might use a "rep movs" instruction, and 2847 * writes within a string instruction are weakly ordered. So there 2848 * are three writes overall. 2849 * 2850 * As a small optimization, only write the version field in the first 2851 * and third write. The vcpu->pv_time cache is still valid, because the 2852 * version field is the first in the struct. 2853 */ 2854 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 2855 2856 if (guest_hv_clock.version & 1) 2857 ++guest_hv_clock.version; /* first time write, random junk */ 2858 2859 vcpu->hv_clock.version = guest_hv_clock.version + 1; 2860 kvm_write_guest_offset_cached(v->kvm, cache, 2861 &vcpu->hv_clock, offset, 2862 sizeof(vcpu->hv_clock.version)); 2863 2864 smp_wmb(); 2865 2866 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 2867 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 2868 2869 if (vcpu->pvclock_set_guest_stopped_request) { 2870 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 2871 vcpu->pvclock_set_guest_stopped_request = false; 2872 } 2873 2874 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 2875 2876 kvm_write_guest_offset_cached(v->kvm, cache, 2877 &vcpu->hv_clock, offset, 2878 sizeof(vcpu->hv_clock)); 2879 2880 smp_wmb(); 2881 2882 vcpu->hv_clock.version++; 2883 kvm_write_guest_offset_cached(v->kvm, cache, 2884 &vcpu->hv_clock, offset, 2885 sizeof(vcpu->hv_clock.version)); 2886 } 2887 2888 static int kvm_guest_time_update(struct kvm_vcpu *v) 2889 { 2890 unsigned long flags, tgt_tsc_khz; 2891 struct kvm_vcpu_arch *vcpu = &v->arch; 2892 struct kvm_arch *ka = &v->kvm->arch; 2893 s64 kernel_ns; 2894 u64 tsc_timestamp, host_tsc; 2895 u8 pvclock_flags; 2896 bool use_master_clock; 2897 2898 kernel_ns = 0; 2899 host_tsc = 0; 2900 2901 /* 2902 * If the host uses TSC clock, then passthrough TSC as stable 2903 * to the guest. 2904 */ 2905 raw_spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 2906 use_master_clock = ka->use_master_clock; 2907 if (use_master_clock) { 2908 host_tsc = ka->master_cycle_now; 2909 kernel_ns = ka->master_kernel_ns; 2910 } 2911 raw_spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2912 2913 /* Keep irq disabled to prevent changes to the clock */ 2914 local_irq_save(flags); 2915 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 2916 if (unlikely(tgt_tsc_khz == 0)) { 2917 local_irq_restore(flags); 2918 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2919 return 1; 2920 } 2921 if (!use_master_clock) { 2922 host_tsc = rdtsc(); 2923 kernel_ns = get_kvmclock_base_ns(); 2924 } 2925 2926 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 2927 2928 /* 2929 * We may have to catch up the TSC to match elapsed wall clock 2930 * time for two reasons, even if kvmclock is used. 2931 * 1) CPU could have been running below the maximum TSC rate 2932 * 2) Broken TSC compensation resets the base at each VCPU 2933 * entry to avoid unknown leaps of TSC even when running 2934 * again on the same CPU. This may cause apparent elapsed 2935 * time to disappear, and the guest to stand still or run 2936 * very slowly. 2937 */ 2938 if (vcpu->tsc_catchup) { 2939 u64 tsc = compute_guest_tsc(v, kernel_ns); 2940 if (tsc > tsc_timestamp) { 2941 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 2942 tsc_timestamp = tsc; 2943 } 2944 } 2945 2946 local_irq_restore(flags); 2947 2948 /* With all the info we got, fill in the values */ 2949 2950 if (kvm_has_tsc_control) 2951 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz, 2952 v->arch.l1_tsc_scaling_ratio); 2953 2954 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 2955 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 2956 &vcpu->hv_clock.tsc_shift, 2957 &vcpu->hv_clock.tsc_to_system_mul); 2958 vcpu->hw_tsc_khz = tgt_tsc_khz; 2959 } 2960 2961 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 2962 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 2963 vcpu->last_guest_tsc = tsc_timestamp; 2964 2965 /* If the host uses TSC clocksource, then it is stable */ 2966 pvclock_flags = 0; 2967 if (use_master_clock) 2968 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 2969 2970 vcpu->hv_clock.flags = pvclock_flags; 2971 2972 if (vcpu->pv_time_enabled) 2973 kvm_setup_pvclock_page(v, &vcpu->pv_time, 0); 2974 if (vcpu->xen.vcpu_info_set) 2975 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache, 2976 offsetof(struct compat_vcpu_info, time)); 2977 if (vcpu->xen.vcpu_time_info_set) 2978 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0); 2979 if (!v->vcpu_idx) 2980 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 2981 return 0; 2982 } 2983 2984 /* 2985 * kvmclock updates which are isolated to a given vcpu, such as 2986 * vcpu->cpu migration, should not allow system_timestamp from 2987 * the rest of the vcpus to remain static. Otherwise ntp frequency 2988 * correction applies to one vcpu's system_timestamp but not 2989 * the others. 2990 * 2991 * So in those cases, request a kvmclock update for all vcpus. 2992 * We need to rate-limit these requests though, as they can 2993 * considerably slow guests that have a large number of vcpus. 2994 * The time for a remote vcpu to update its kvmclock is bound 2995 * by the delay we use to rate-limit the updates. 2996 */ 2997 2998 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 2999 3000 static void kvmclock_update_fn(struct work_struct *work) 3001 { 3002 int i; 3003 struct delayed_work *dwork = to_delayed_work(work); 3004 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3005 kvmclock_update_work); 3006 struct kvm *kvm = container_of(ka, struct kvm, arch); 3007 struct kvm_vcpu *vcpu; 3008 3009 kvm_for_each_vcpu(i, vcpu, kvm) { 3010 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3011 kvm_vcpu_kick(vcpu); 3012 } 3013 } 3014 3015 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 3016 { 3017 struct kvm *kvm = v->kvm; 3018 3019 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 3020 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 3021 KVMCLOCK_UPDATE_DELAY); 3022 } 3023 3024 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 3025 3026 static void kvmclock_sync_fn(struct work_struct *work) 3027 { 3028 struct delayed_work *dwork = to_delayed_work(work); 3029 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3030 kvmclock_sync_work); 3031 struct kvm *kvm = container_of(ka, struct kvm, arch); 3032 3033 if (!kvmclock_periodic_sync) 3034 return; 3035 3036 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 3037 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 3038 KVMCLOCK_SYNC_PERIOD); 3039 } 3040 3041 /* 3042 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 3043 */ 3044 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 3045 { 3046 /* McStatusWrEn enabled? */ 3047 if (guest_cpuid_is_amd_or_hygon(vcpu)) 3048 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 3049 3050 return false; 3051 } 3052 3053 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3054 { 3055 u64 mcg_cap = vcpu->arch.mcg_cap; 3056 unsigned bank_num = mcg_cap & 0xff; 3057 u32 msr = msr_info->index; 3058 u64 data = msr_info->data; 3059 3060 switch (msr) { 3061 case MSR_IA32_MCG_STATUS: 3062 vcpu->arch.mcg_status = data; 3063 break; 3064 case MSR_IA32_MCG_CTL: 3065 if (!(mcg_cap & MCG_CTL_P) && 3066 (data || !msr_info->host_initiated)) 3067 return 1; 3068 if (data != 0 && data != ~(u64)0) 3069 return 1; 3070 vcpu->arch.mcg_ctl = data; 3071 break; 3072 default: 3073 if (msr >= MSR_IA32_MC0_CTL && 3074 msr < MSR_IA32_MCx_CTL(bank_num)) { 3075 u32 offset = array_index_nospec( 3076 msr - MSR_IA32_MC0_CTL, 3077 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3078 3079 /* only 0 or all 1s can be written to IA32_MCi_CTL 3080 * some Linux kernels though clear bit 10 in bank 4 to 3081 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 3082 * this to avoid an uncatched #GP in the guest 3083 */ 3084 if ((offset & 0x3) == 0 && 3085 data != 0 && (data | (1 << 10)) != ~(u64)0) 3086 return -1; 3087 3088 /* MCi_STATUS */ 3089 if (!msr_info->host_initiated && 3090 (offset & 0x3) == 1 && data != 0) { 3091 if (!can_set_mci_status(vcpu)) 3092 return -1; 3093 } 3094 3095 vcpu->arch.mce_banks[offset] = data; 3096 break; 3097 } 3098 return 1; 3099 } 3100 return 0; 3101 } 3102 3103 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) 3104 { 3105 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; 3106 3107 return (vcpu->arch.apf.msr_en_val & mask) == mask; 3108 } 3109 3110 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 3111 { 3112 gpa_t gpa = data & ~0x3f; 3113 3114 /* Bits 4:5 are reserved, Should be zero */ 3115 if (data & 0x30) 3116 return 1; 3117 3118 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && 3119 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) 3120 return 1; 3121 3122 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && 3123 (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) 3124 return 1; 3125 3126 if (!lapic_in_kernel(vcpu)) 3127 return data ? 1 : 0; 3128 3129 vcpu->arch.apf.msr_en_val = data; 3130 3131 if (!kvm_pv_async_pf_enabled(vcpu)) { 3132 kvm_clear_async_pf_completion_queue(vcpu); 3133 kvm_async_pf_hash_reset(vcpu); 3134 return 0; 3135 } 3136 3137 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 3138 sizeof(u64))) 3139 return 1; 3140 3141 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 3142 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 3143 3144 kvm_async_pf_wakeup_all(vcpu); 3145 3146 return 0; 3147 } 3148 3149 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) 3150 { 3151 /* Bits 8-63 are reserved */ 3152 if (data >> 8) 3153 return 1; 3154 3155 if (!lapic_in_kernel(vcpu)) 3156 return 1; 3157 3158 vcpu->arch.apf.msr_int_val = data; 3159 3160 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; 3161 3162 return 0; 3163 } 3164 3165 static void kvmclock_reset(struct kvm_vcpu *vcpu) 3166 { 3167 vcpu->arch.pv_time_enabled = false; 3168 vcpu->arch.time = 0; 3169 } 3170 3171 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) 3172 { 3173 ++vcpu->stat.tlb_flush; 3174 static_call(kvm_x86_tlb_flush_all)(vcpu); 3175 } 3176 3177 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) 3178 { 3179 ++vcpu->stat.tlb_flush; 3180 3181 if (!tdp_enabled) { 3182 /* 3183 * A TLB flush on behalf of the guest is equivalent to 3184 * INVPCID(all), toggling CR4.PGE, etc., which requires 3185 * a forced sync of the shadow page tables. Unload the 3186 * entire MMU here and the subsequent load will sync the 3187 * shadow page tables, and also flush the TLB. 3188 */ 3189 kvm_mmu_unload(vcpu); 3190 return; 3191 } 3192 3193 static_call(kvm_x86_tlb_flush_guest)(vcpu); 3194 } 3195 3196 static void record_steal_time(struct kvm_vcpu *vcpu) 3197 { 3198 struct kvm_host_map map; 3199 struct kvm_steal_time *st; 3200 3201 if (kvm_xen_msr_enabled(vcpu->kvm)) { 3202 kvm_xen_runstate_set_running(vcpu); 3203 return; 3204 } 3205 3206 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3207 return; 3208 3209 /* -EAGAIN is returned in atomic context so we can just return. */ 3210 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, 3211 &map, &vcpu->arch.st.cache, false)) 3212 return; 3213 3214 st = map.hva + 3215 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 3216 3217 /* 3218 * Doing a TLB flush here, on the guest's behalf, can avoid 3219 * expensive IPIs. 3220 */ 3221 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { 3222 u8 st_preempted = xchg(&st->preempted, 0); 3223 3224 trace_kvm_pv_tlb_flush(vcpu->vcpu_id, 3225 st_preempted & KVM_VCPU_FLUSH_TLB); 3226 if (st_preempted & KVM_VCPU_FLUSH_TLB) 3227 kvm_vcpu_flush_tlb_guest(vcpu); 3228 } else { 3229 st->preempted = 0; 3230 } 3231 3232 vcpu->arch.st.preempted = 0; 3233 3234 if (st->version & 1) 3235 st->version += 1; /* first time write, random junk */ 3236 3237 st->version += 1; 3238 3239 smp_wmb(); 3240 3241 st->steal += current->sched_info.run_delay - 3242 vcpu->arch.st.last_steal; 3243 vcpu->arch.st.last_steal = current->sched_info.run_delay; 3244 3245 smp_wmb(); 3246 3247 st->version += 1; 3248 3249 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); 3250 } 3251 3252 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3253 { 3254 bool pr = false; 3255 u32 msr = msr_info->index; 3256 u64 data = msr_info->data; 3257 3258 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) 3259 return kvm_xen_write_hypercall_page(vcpu, data); 3260 3261 switch (msr) { 3262 case MSR_AMD64_NB_CFG: 3263 case MSR_IA32_UCODE_WRITE: 3264 case MSR_VM_HSAVE_PA: 3265 case MSR_AMD64_PATCH_LOADER: 3266 case MSR_AMD64_BU_CFG2: 3267 case MSR_AMD64_DC_CFG: 3268 case MSR_F15H_EX_CFG: 3269 break; 3270 3271 case MSR_IA32_UCODE_REV: 3272 if (msr_info->host_initiated) 3273 vcpu->arch.microcode_version = data; 3274 break; 3275 case MSR_IA32_ARCH_CAPABILITIES: 3276 if (!msr_info->host_initiated) 3277 return 1; 3278 vcpu->arch.arch_capabilities = data; 3279 break; 3280 case MSR_IA32_PERF_CAPABILITIES: { 3281 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; 3282 3283 if (!msr_info->host_initiated) 3284 return 1; 3285 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent)) 3286 return 1; 3287 if (data & ~msr_ent.data) 3288 return 1; 3289 3290 vcpu->arch.perf_capabilities = data; 3291 3292 return 0; 3293 } 3294 case MSR_EFER: 3295 return set_efer(vcpu, msr_info); 3296 case MSR_K7_HWCR: 3297 data &= ~(u64)0x40; /* ignore flush filter disable */ 3298 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 3299 data &= ~(u64)0x8; /* ignore TLB cache disable */ 3300 3301 /* Handle McStatusWrEn */ 3302 if (data == BIT_ULL(18)) { 3303 vcpu->arch.msr_hwcr = data; 3304 } else if (data != 0) { 3305 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 3306 data); 3307 return 1; 3308 } 3309 break; 3310 case MSR_FAM10H_MMIO_CONF_BASE: 3311 if (data != 0) { 3312 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 3313 "0x%llx\n", data); 3314 return 1; 3315 } 3316 break; 3317 case 0x200 ... 0x2ff: 3318 return kvm_mtrr_set_msr(vcpu, msr, data); 3319 case MSR_IA32_APICBASE: 3320 return kvm_set_apic_base(vcpu, msr_info); 3321 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3322 return kvm_x2apic_msr_write(vcpu, msr, data); 3323 case MSR_IA32_TSC_DEADLINE: 3324 kvm_set_lapic_tscdeadline_msr(vcpu, data); 3325 break; 3326 case MSR_IA32_TSC_ADJUST: 3327 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 3328 if (!msr_info->host_initiated) { 3329 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 3330 adjust_tsc_offset_guest(vcpu, adj); 3331 /* Before back to guest, tsc_timestamp must be adjusted 3332 * as well, otherwise guest's percpu pvclock time could jump. 3333 */ 3334 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3335 } 3336 vcpu->arch.ia32_tsc_adjust_msr = data; 3337 } 3338 break; 3339 case MSR_IA32_MISC_ENABLE: 3340 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && 3341 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { 3342 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) 3343 return 1; 3344 vcpu->arch.ia32_misc_enable_msr = data; 3345 kvm_update_cpuid_runtime(vcpu); 3346 } else { 3347 vcpu->arch.ia32_misc_enable_msr = data; 3348 } 3349 break; 3350 case MSR_IA32_SMBASE: 3351 if (!msr_info->host_initiated) 3352 return 1; 3353 vcpu->arch.smbase = data; 3354 break; 3355 case MSR_IA32_POWER_CTL: 3356 vcpu->arch.msr_ia32_power_ctl = data; 3357 break; 3358 case MSR_IA32_TSC: 3359 if (msr_info->host_initiated) { 3360 kvm_synchronize_tsc(vcpu, data); 3361 } else { 3362 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; 3363 adjust_tsc_offset_guest(vcpu, adj); 3364 vcpu->arch.ia32_tsc_adjust_msr += adj; 3365 } 3366 break; 3367 case MSR_IA32_XSS: 3368 if (!msr_info->host_initiated && 3369 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3370 return 1; 3371 /* 3372 * KVM supports exposing PT to the guest, but does not support 3373 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than 3374 * XSAVES/XRSTORS to save/restore PT MSRs. 3375 */ 3376 if (data & ~supported_xss) 3377 return 1; 3378 vcpu->arch.ia32_xss = data; 3379 break; 3380 case MSR_SMI_COUNT: 3381 if (!msr_info->host_initiated) 3382 return 1; 3383 vcpu->arch.smi_count = data; 3384 break; 3385 case MSR_KVM_WALL_CLOCK_NEW: 3386 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3387 return 1; 3388 3389 vcpu->kvm->arch.wall_clock = data; 3390 kvm_write_wall_clock(vcpu->kvm, data, 0); 3391 break; 3392 case MSR_KVM_WALL_CLOCK: 3393 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3394 return 1; 3395 3396 vcpu->kvm->arch.wall_clock = data; 3397 kvm_write_wall_clock(vcpu->kvm, data, 0); 3398 break; 3399 case MSR_KVM_SYSTEM_TIME_NEW: 3400 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3401 return 1; 3402 3403 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); 3404 break; 3405 case MSR_KVM_SYSTEM_TIME: 3406 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3407 return 1; 3408 3409 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); 3410 break; 3411 case MSR_KVM_ASYNC_PF_EN: 3412 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3413 return 1; 3414 3415 if (kvm_pv_enable_async_pf(vcpu, data)) 3416 return 1; 3417 break; 3418 case MSR_KVM_ASYNC_PF_INT: 3419 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3420 return 1; 3421 3422 if (kvm_pv_enable_async_pf_int(vcpu, data)) 3423 return 1; 3424 break; 3425 case MSR_KVM_ASYNC_PF_ACK: 3426 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3427 return 1; 3428 if (data & 0x1) { 3429 vcpu->arch.apf.pageready_pending = false; 3430 kvm_check_async_pf_completion(vcpu); 3431 } 3432 break; 3433 case MSR_KVM_STEAL_TIME: 3434 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3435 return 1; 3436 3437 if (unlikely(!sched_info_on())) 3438 return 1; 3439 3440 if (data & KVM_STEAL_RESERVED_MASK) 3441 return 1; 3442 3443 vcpu->arch.st.msr_val = data; 3444 3445 if (!(data & KVM_MSR_ENABLED)) 3446 break; 3447 3448 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3449 3450 break; 3451 case MSR_KVM_PV_EOI_EN: 3452 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3453 return 1; 3454 3455 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) 3456 return 1; 3457 break; 3458 3459 case MSR_KVM_POLL_CONTROL: 3460 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3461 return 1; 3462 3463 /* only enable bit supported */ 3464 if (data & (-1ULL << 1)) 3465 return 1; 3466 3467 vcpu->arch.msr_kvm_poll_control = data; 3468 break; 3469 3470 case MSR_IA32_MCG_CTL: 3471 case MSR_IA32_MCG_STATUS: 3472 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3473 return set_msr_mce(vcpu, msr_info); 3474 3475 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3476 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3477 pr = true; 3478 fallthrough; 3479 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3480 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3481 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3482 return kvm_pmu_set_msr(vcpu, msr_info); 3483 3484 if (pr || data != 0) 3485 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 3486 "0x%x data 0x%llx\n", msr, data); 3487 break; 3488 case MSR_K7_CLK_CTL: 3489 /* 3490 * Ignore all writes to this no longer documented MSR. 3491 * Writes are only relevant for old K7 processors, 3492 * all pre-dating SVM, but a recommended workaround from 3493 * AMD for these chips. It is possible to specify the 3494 * affected processor models on the command line, hence 3495 * the need to ignore the workaround. 3496 */ 3497 break; 3498 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3499 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3500 case HV_X64_MSR_SYNDBG_OPTIONS: 3501 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3502 case HV_X64_MSR_CRASH_CTL: 3503 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3504 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3505 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3506 case HV_X64_MSR_TSC_EMULATION_STATUS: 3507 return kvm_hv_set_msr_common(vcpu, msr, data, 3508 msr_info->host_initiated); 3509 case MSR_IA32_BBL_CR_CTL3: 3510 /* Drop writes to this legacy MSR -- see rdmsr 3511 * counterpart for further detail. 3512 */ 3513 if (report_ignored_msrs) 3514 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 3515 msr, data); 3516 break; 3517 case MSR_AMD64_OSVW_ID_LENGTH: 3518 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3519 return 1; 3520 vcpu->arch.osvw.length = data; 3521 break; 3522 case MSR_AMD64_OSVW_STATUS: 3523 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3524 return 1; 3525 vcpu->arch.osvw.status = data; 3526 break; 3527 case MSR_PLATFORM_INFO: 3528 if (!msr_info->host_initiated || 3529 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 3530 cpuid_fault_enabled(vcpu))) 3531 return 1; 3532 vcpu->arch.msr_platform_info = data; 3533 break; 3534 case MSR_MISC_FEATURES_ENABLES: 3535 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 3536 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3537 !supports_cpuid_fault(vcpu))) 3538 return 1; 3539 vcpu->arch.msr_misc_features_enables = data; 3540 break; 3541 default: 3542 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3543 return kvm_pmu_set_msr(vcpu, msr_info); 3544 return KVM_MSR_RET_INVALID; 3545 } 3546 return 0; 3547 } 3548 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 3549 3550 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 3551 { 3552 u64 data; 3553 u64 mcg_cap = vcpu->arch.mcg_cap; 3554 unsigned bank_num = mcg_cap & 0xff; 3555 3556 switch (msr) { 3557 case MSR_IA32_P5_MC_ADDR: 3558 case MSR_IA32_P5_MC_TYPE: 3559 data = 0; 3560 break; 3561 case MSR_IA32_MCG_CAP: 3562 data = vcpu->arch.mcg_cap; 3563 break; 3564 case MSR_IA32_MCG_CTL: 3565 if (!(mcg_cap & MCG_CTL_P) && !host) 3566 return 1; 3567 data = vcpu->arch.mcg_ctl; 3568 break; 3569 case MSR_IA32_MCG_STATUS: 3570 data = vcpu->arch.mcg_status; 3571 break; 3572 default: 3573 if (msr >= MSR_IA32_MC0_CTL && 3574 msr < MSR_IA32_MCx_CTL(bank_num)) { 3575 u32 offset = array_index_nospec( 3576 msr - MSR_IA32_MC0_CTL, 3577 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3578 3579 data = vcpu->arch.mce_banks[offset]; 3580 break; 3581 } 3582 return 1; 3583 } 3584 *pdata = data; 3585 return 0; 3586 } 3587 3588 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3589 { 3590 switch (msr_info->index) { 3591 case MSR_IA32_PLATFORM_ID: 3592 case MSR_IA32_EBL_CR_POWERON: 3593 case MSR_IA32_LASTBRANCHFROMIP: 3594 case MSR_IA32_LASTBRANCHTOIP: 3595 case MSR_IA32_LASTINTFROMIP: 3596 case MSR_IA32_LASTINTTOIP: 3597 case MSR_AMD64_SYSCFG: 3598 case MSR_K8_TSEG_ADDR: 3599 case MSR_K8_TSEG_MASK: 3600 case MSR_VM_HSAVE_PA: 3601 case MSR_K8_INT_PENDING_MSG: 3602 case MSR_AMD64_NB_CFG: 3603 case MSR_FAM10H_MMIO_CONF_BASE: 3604 case MSR_AMD64_BU_CFG2: 3605 case MSR_IA32_PERF_CTL: 3606 case MSR_AMD64_DC_CFG: 3607 case MSR_F15H_EX_CFG: 3608 /* 3609 * Intel Sandy Bridge CPUs must support the RAPL (running average power 3610 * limit) MSRs. Just return 0, as we do not want to expose the host 3611 * data here. Do not conditionalize this on CPUID, as KVM does not do 3612 * so for existing CPU-specific MSRs. 3613 */ 3614 case MSR_RAPL_POWER_UNIT: 3615 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ 3616 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ 3617 case MSR_PKG_ENERGY_STATUS: /* Total package */ 3618 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ 3619 msr_info->data = 0; 3620 break; 3621 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3622 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3623 return kvm_pmu_get_msr(vcpu, msr_info); 3624 if (!msr_info->host_initiated) 3625 return 1; 3626 msr_info->data = 0; 3627 break; 3628 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3629 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3630 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3631 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3632 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3633 return kvm_pmu_get_msr(vcpu, msr_info); 3634 msr_info->data = 0; 3635 break; 3636 case MSR_IA32_UCODE_REV: 3637 msr_info->data = vcpu->arch.microcode_version; 3638 break; 3639 case MSR_IA32_ARCH_CAPABILITIES: 3640 if (!msr_info->host_initiated && 3641 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 3642 return 1; 3643 msr_info->data = vcpu->arch.arch_capabilities; 3644 break; 3645 case MSR_IA32_PERF_CAPABILITIES: 3646 if (!msr_info->host_initiated && 3647 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) 3648 return 1; 3649 msr_info->data = vcpu->arch.perf_capabilities; 3650 break; 3651 case MSR_IA32_POWER_CTL: 3652 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 3653 break; 3654 case MSR_IA32_TSC: { 3655 /* 3656 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset 3657 * even when not intercepted. AMD manual doesn't explicitly 3658 * state this but appears to behave the same. 3659 * 3660 * On userspace reads and writes, however, we unconditionally 3661 * return L1's TSC value to ensure backwards-compatible 3662 * behavior for migration. 3663 */ 3664 u64 offset, ratio; 3665 3666 if (msr_info->host_initiated) { 3667 offset = vcpu->arch.l1_tsc_offset; 3668 ratio = vcpu->arch.l1_tsc_scaling_ratio; 3669 } else { 3670 offset = vcpu->arch.tsc_offset; 3671 ratio = vcpu->arch.tsc_scaling_ratio; 3672 } 3673 3674 msr_info->data = kvm_scale_tsc(vcpu, rdtsc(), ratio) + offset; 3675 break; 3676 } 3677 case MSR_MTRRcap: 3678 case 0x200 ... 0x2ff: 3679 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 3680 case 0xcd: /* fsb frequency */ 3681 msr_info->data = 3; 3682 break; 3683 /* 3684 * MSR_EBC_FREQUENCY_ID 3685 * Conservative value valid for even the basic CPU models. 3686 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 3687 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 3688 * and 266MHz for model 3, or 4. Set Core Clock 3689 * Frequency to System Bus Frequency Ratio to 1 (bits 3690 * 31:24) even though these are only valid for CPU 3691 * models > 2, however guests may end up dividing or 3692 * multiplying by zero otherwise. 3693 */ 3694 case MSR_EBC_FREQUENCY_ID: 3695 msr_info->data = 1 << 24; 3696 break; 3697 case MSR_IA32_APICBASE: 3698 msr_info->data = kvm_get_apic_base(vcpu); 3699 break; 3700 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3701 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 3702 case MSR_IA32_TSC_DEADLINE: 3703 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 3704 break; 3705 case MSR_IA32_TSC_ADJUST: 3706 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 3707 break; 3708 case MSR_IA32_MISC_ENABLE: 3709 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 3710 break; 3711 case MSR_IA32_SMBASE: 3712 if (!msr_info->host_initiated) 3713 return 1; 3714 msr_info->data = vcpu->arch.smbase; 3715 break; 3716 case MSR_SMI_COUNT: 3717 msr_info->data = vcpu->arch.smi_count; 3718 break; 3719 case MSR_IA32_PERF_STATUS: 3720 /* TSC increment by tick */ 3721 msr_info->data = 1000ULL; 3722 /* CPU multiplier */ 3723 msr_info->data |= (((uint64_t)4ULL) << 40); 3724 break; 3725 case MSR_EFER: 3726 msr_info->data = vcpu->arch.efer; 3727 break; 3728 case MSR_KVM_WALL_CLOCK: 3729 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3730 return 1; 3731 3732 msr_info->data = vcpu->kvm->arch.wall_clock; 3733 break; 3734 case MSR_KVM_WALL_CLOCK_NEW: 3735 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3736 return 1; 3737 3738 msr_info->data = vcpu->kvm->arch.wall_clock; 3739 break; 3740 case MSR_KVM_SYSTEM_TIME: 3741 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3742 return 1; 3743 3744 msr_info->data = vcpu->arch.time; 3745 break; 3746 case MSR_KVM_SYSTEM_TIME_NEW: 3747 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3748 return 1; 3749 3750 msr_info->data = vcpu->arch.time; 3751 break; 3752 case MSR_KVM_ASYNC_PF_EN: 3753 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3754 return 1; 3755 3756 msr_info->data = vcpu->arch.apf.msr_en_val; 3757 break; 3758 case MSR_KVM_ASYNC_PF_INT: 3759 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3760 return 1; 3761 3762 msr_info->data = vcpu->arch.apf.msr_int_val; 3763 break; 3764 case MSR_KVM_ASYNC_PF_ACK: 3765 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3766 return 1; 3767 3768 msr_info->data = 0; 3769 break; 3770 case MSR_KVM_STEAL_TIME: 3771 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3772 return 1; 3773 3774 msr_info->data = vcpu->arch.st.msr_val; 3775 break; 3776 case MSR_KVM_PV_EOI_EN: 3777 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3778 return 1; 3779 3780 msr_info->data = vcpu->arch.pv_eoi.msr_val; 3781 break; 3782 case MSR_KVM_POLL_CONTROL: 3783 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3784 return 1; 3785 3786 msr_info->data = vcpu->arch.msr_kvm_poll_control; 3787 break; 3788 case MSR_IA32_P5_MC_ADDR: 3789 case MSR_IA32_P5_MC_TYPE: 3790 case MSR_IA32_MCG_CAP: 3791 case MSR_IA32_MCG_CTL: 3792 case MSR_IA32_MCG_STATUS: 3793 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3794 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 3795 msr_info->host_initiated); 3796 case MSR_IA32_XSS: 3797 if (!msr_info->host_initiated && 3798 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3799 return 1; 3800 msr_info->data = vcpu->arch.ia32_xss; 3801 break; 3802 case MSR_K7_CLK_CTL: 3803 /* 3804 * Provide expected ramp-up count for K7. All other 3805 * are set to zero, indicating minimum divisors for 3806 * every field. 3807 * 3808 * This prevents guest kernels on AMD host with CPU 3809 * type 6, model 8 and higher from exploding due to 3810 * the rdmsr failing. 3811 */ 3812 msr_info->data = 0x20000000; 3813 break; 3814 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3815 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3816 case HV_X64_MSR_SYNDBG_OPTIONS: 3817 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3818 case HV_X64_MSR_CRASH_CTL: 3819 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3820 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3821 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3822 case HV_X64_MSR_TSC_EMULATION_STATUS: 3823 return kvm_hv_get_msr_common(vcpu, 3824 msr_info->index, &msr_info->data, 3825 msr_info->host_initiated); 3826 case MSR_IA32_BBL_CR_CTL3: 3827 /* This legacy MSR exists but isn't fully documented in current 3828 * silicon. It is however accessed by winxp in very narrow 3829 * scenarios where it sets bit #19, itself documented as 3830 * a "reserved" bit. Best effort attempt to source coherent 3831 * read data here should the balance of the register be 3832 * interpreted by the guest: 3833 * 3834 * L2 cache control register 3: 64GB range, 256KB size, 3835 * enabled, latency 0x1, configured 3836 */ 3837 msr_info->data = 0xbe702111; 3838 break; 3839 case MSR_AMD64_OSVW_ID_LENGTH: 3840 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3841 return 1; 3842 msr_info->data = vcpu->arch.osvw.length; 3843 break; 3844 case MSR_AMD64_OSVW_STATUS: 3845 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3846 return 1; 3847 msr_info->data = vcpu->arch.osvw.status; 3848 break; 3849 case MSR_PLATFORM_INFO: 3850 if (!msr_info->host_initiated && 3851 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 3852 return 1; 3853 msr_info->data = vcpu->arch.msr_platform_info; 3854 break; 3855 case MSR_MISC_FEATURES_ENABLES: 3856 msr_info->data = vcpu->arch.msr_misc_features_enables; 3857 break; 3858 case MSR_K7_HWCR: 3859 msr_info->data = vcpu->arch.msr_hwcr; 3860 break; 3861 default: 3862 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3863 return kvm_pmu_get_msr(vcpu, msr_info); 3864 return KVM_MSR_RET_INVALID; 3865 } 3866 return 0; 3867 } 3868 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 3869 3870 /* 3871 * Read or write a bunch of msrs. All parameters are kernel addresses. 3872 * 3873 * @return number of msrs set successfully. 3874 */ 3875 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 3876 struct kvm_msr_entry *entries, 3877 int (*do_msr)(struct kvm_vcpu *vcpu, 3878 unsigned index, u64 *data)) 3879 { 3880 int i; 3881 3882 for (i = 0; i < msrs->nmsrs; ++i) 3883 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 3884 break; 3885 3886 return i; 3887 } 3888 3889 /* 3890 * Read or write a bunch of msrs. Parameters are user addresses. 3891 * 3892 * @return number of msrs set successfully. 3893 */ 3894 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 3895 int (*do_msr)(struct kvm_vcpu *vcpu, 3896 unsigned index, u64 *data), 3897 int writeback) 3898 { 3899 struct kvm_msrs msrs; 3900 struct kvm_msr_entry *entries; 3901 int r, n; 3902 unsigned size; 3903 3904 r = -EFAULT; 3905 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 3906 goto out; 3907 3908 r = -E2BIG; 3909 if (msrs.nmsrs >= MAX_IO_MSRS) 3910 goto out; 3911 3912 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 3913 entries = memdup_user(user_msrs->entries, size); 3914 if (IS_ERR(entries)) { 3915 r = PTR_ERR(entries); 3916 goto out; 3917 } 3918 3919 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 3920 if (r < 0) 3921 goto out_free; 3922 3923 r = -EFAULT; 3924 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 3925 goto out_free; 3926 3927 r = n; 3928 3929 out_free: 3930 kfree(entries); 3931 out: 3932 return r; 3933 } 3934 3935 static inline bool kvm_can_mwait_in_guest(void) 3936 { 3937 return boot_cpu_has(X86_FEATURE_MWAIT) && 3938 !boot_cpu_has_bug(X86_BUG_MONITOR) && 3939 boot_cpu_has(X86_FEATURE_ARAT); 3940 } 3941 3942 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, 3943 struct kvm_cpuid2 __user *cpuid_arg) 3944 { 3945 struct kvm_cpuid2 cpuid; 3946 int r; 3947 3948 r = -EFAULT; 3949 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3950 return r; 3951 3952 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3953 if (r) 3954 return r; 3955 3956 r = -EFAULT; 3957 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 3958 return r; 3959 3960 return 0; 3961 } 3962 3963 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 3964 { 3965 int r = 0; 3966 3967 switch (ext) { 3968 case KVM_CAP_IRQCHIP: 3969 case KVM_CAP_HLT: 3970 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 3971 case KVM_CAP_SET_TSS_ADDR: 3972 case KVM_CAP_EXT_CPUID: 3973 case KVM_CAP_EXT_EMUL_CPUID: 3974 case KVM_CAP_CLOCKSOURCE: 3975 case KVM_CAP_PIT: 3976 case KVM_CAP_NOP_IO_DELAY: 3977 case KVM_CAP_MP_STATE: 3978 case KVM_CAP_SYNC_MMU: 3979 case KVM_CAP_USER_NMI: 3980 case KVM_CAP_REINJECT_CONTROL: 3981 case KVM_CAP_IRQ_INJECT_STATUS: 3982 case KVM_CAP_IOEVENTFD: 3983 case KVM_CAP_IOEVENTFD_NO_LENGTH: 3984 case KVM_CAP_PIT2: 3985 case KVM_CAP_PIT_STATE2: 3986 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 3987 case KVM_CAP_VCPU_EVENTS: 3988 case KVM_CAP_HYPERV: 3989 case KVM_CAP_HYPERV_VAPIC: 3990 case KVM_CAP_HYPERV_SPIN: 3991 case KVM_CAP_HYPERV_SYNIC: 3992 case KVM_CAP_HYPERV_SYNIC2: 3993 case KVM_CAP_HYPERV_VP_INDEX: 3994 case KVM_CAP_HYPERV_EVENTFD: 3995 case KVM_CAP_HYPERV_TLBFLUSH: 3996 case KVM_CAP_HYPERV_SEND_IPI: 3997 case KVM_CAP_HYPERV_CPUID: 3998 case KVM_CAP_HYPERV_ENFORCE_CPUID: 3999 case KVM_CAP_SYS_HYPERV_CPUID: 4000 case KVM_CAP_PCI_SEGMENT: 4001 case KVM_CAP_DEBUGREGS: 4002 case KVM_CAP_X86_ROBUST_SINGLESTEP: 4003 case KVM_CAP_XSAVE: 4004 case KVM_CAP_ASYNC_PF: 4005 case KVM_CAP_ASYNC_PF_INT: 4006 case KVM_CAP_GET_TSC_KHZ: 4007 case KVM_CAP_KVMCLOCK_CTRL: 4008 case KVM_CAP_READONLY_MEM: 4009 case KVM_CAP_HYPERV_TIME: 4010 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 4011 case KVM_CAP_TSC_DEADLINE_TIMER: 4012 case KVM_CAP_DISABLE_QUIRKS: 4013 case KVM_CAP_SET_BOOT_CPU_ID: 4014 case KVM_CAP_SPLIT_IRQCHIP: 4015 case KVM_CAP_IMMEDIATE_EXIT: 4016 case KVM_CAP_PMU_EVENT_FILTER: 4017 case KVM_CAP_GET_MSR_FEATURES: 4018 case KVM_CAP_MSR_PLATFORM_INFO: 4019 case KVM_CAP_EXCEPTION_PAYLOAD: 4020 case KVM_CAP_SET_GUEST_DEBUG: 4021 case KVM_CAP_LAST_CPU: 4022 case KVM_CAP_X86_USER_SPACE_MSR: 4023 case KVM_CAP_X86_MSR_FILTER: 4024 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 4025 #ifdef CONFIG_X86_SGX_KVM 4026 case KVM_CAP_SGX_ATTRIBUTE: 4027 #endif 4028 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 4029 case KVM_CAP_SREGS2: 4030 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 4031 r = 1; 4032 break; 4033 case KVM_CAP_EXIT_HYPERCALL: 4034 r = KVM_EXIT_HYPERCALL_VALID_MASK; 4035 break; 4036 case KVM_CAP_SET_GUEST_DEBUG2: 4037 return KVM_GUESTDBG_VALID_MASK; 4038 #ifdef CONFIG_KVM_XEN 4039 case KVM_CAP_XEN_HVM: 4040 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | 4041 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | 4042 KVM_XEN_HVM_CONFIG_SHARED_INFO; 4043 if (sched_info_on()) 4044 r |= KVM_XEN_HVM_CONFIG_RUNSTATE; 4045 break; 4046 #endif 4047 case KVM_CAP_SYNC_REGS: 4048 r = KVM_SYNC_X86_VALID_FIELDS; 4049 break; 4050 case KVM_CAP_ADJUST_CLOCK: 4051 r = KVM_CLOCK_TSC_STABLE; 4052 break; 4053 case KVM_CAP_X86_DISABLE_EXITS: 4054 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | 4055 KVM_X86_DISABLE_EXITS_CSTATE; 4056 if(kvm_can_mwait_in_guest()) 4057 r |= KVM_X86_DISABLE_EXITS_MWAIT; 4058 break; 4059 case KVM_CAP_X86_SMM: 4060 /* SMBASE is usually relocated above 1M on modern chipsets, 4061 * and SMM handlers might indeed rely on 4G segment limits, 4062 * so do not report SMM to be available if real mode is 4063 * emulated via vm86 mode. Still, do not go to great lengths 4064 * to avoid userspace's usage of the feature, because it is a 4065 * fringe case that is not enabled except via specific settings 4066 * of the module parameters. 4067 */ 4068 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); 4069 break; 4070 case KVM_CAP_VAPIC: 4071 r = !static_call(kvm_x86_cpu_has_accelerated_tpr)(); 4072 break; 4073 case KVM_CAP_NR_VCPUS: 4074 r = KVM_SOFT_MAX_VCPUS; 4075 break; 4076 case KVM_CAP_MAX_VCPUS: 4077 r = KVM_MAX_VCPUS; 4078 break; 4079 case KVM_CAP_MAX_VCPU_ID: 4080 r = KVM_MAX_VCPU_ID; 4081 break; 4082 case KVM_CAP_PV_MMU: /* obsolete */ 4083 r = 0; 4084 break; 4085 case KVM_CAP_MCE: 4086 r = KVM_MAX_MCE_BANKS; 4087 break; 4088 case KVM_CAP_XCRS: 4089 r = boot_cpu_has(X86_FEATURE_XSAVE); 4090 break; 4091 case KVM_CAP_TSC_CONTROL: 4092 r = kvm_has_tsc_control; 4093 break; 4094 case KVM_CAP_X2APIC_API: 4095 r = KVM_X2APIC_API_VALID_FLAGS; 4096 break; 4097 case KVM_CAP_NESTED_STATE: 4098 r = kvm_x86_ops.nested_ops->get_state ? 4099 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; 4100 break; 4101 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4102 r = kvm_x86_ops.enable_direct_tlbflush != NULL; 4103 break; 4104 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4105 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; 4106 break; 4107 case KVM_CAP_SMALLER_MAXPHYADDR: 4108 r = (int) allow_smaller_maxphyaddr; 4109 break; 4110 case KVM_CAP_STEAL_TIME: 4111 r = sched_info_on(); 4112 break; 4113 case KVM_CAP_X86_BUS_LOCK_EXIT: 4114 if (kvm_has_bus_lock_exit) 4115 r = KVM_BUS_LOCK_DETECTION_OFF | 4116 KVM_BUS_LOCK_DETECTION_EXIT; 4117 else 4118 r = 0; 4119 break; 4120 default: 4121 break; 4122 } 4123 return r; 4124 4125 } 4126 4127 long kvm_arch_dev_ioctl(struct file *filp, 4128 unsigned int ioctl, unsigned long arg) 4129 { 4130 void __user *argp = (void __user *)arg; 4131 long r; 4132 4133 switch (ioctl) { 4134 case KVM_GET_MSR_INDEX_LIST: { 4135 struct kvm_msr_list __user *user_msr_list = argp; 4136 struct kvm_msr_list msr_list; 4137 unsigned n; 4138 4139 r = -EFAULT; 4140 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4141 goto out; 4142 n = msr_list.nmsrs; 4143 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 4144 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4145 goto out; 4146 r = -E2BIG; 4147 if (n < msr_list.nmsrs) 4148 goto out; 4149 r = -EFAULT; 4150 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 4151 num_msrs_to_save * sizeof(u32))) 4152 goto out; 4153 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 4154 &emulated_msrs, 4155 num_emulated_msrs * sizeof(u32))) 4156 goto out; 4157 r = 0; 4158 break; 4159 } 4160 case KVM_GET_SUPPORTED_CPUID: 4161 case KVM_GET_EMULATED_CPUID: { 4162 struct kvm_cpuid2 __user *cpuid_arg = argp; 4163 struct kvm_cpuid2 cpuid; 4164 4165 r = -EFAULT; 4166 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4167 goto out; 4168 4169 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 4170 ioctl); 4171 if (r) 4172 goto out; 4173 4174 r = -EFAULT; 4175 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4176 goto out; 4177 r = 0; 4178 break; 4179 } 4180 case KVM_X86_GET_MCE_CAP_SUPPORTED: 4181 r = -EFAULT; 4182 if (copy_to_user(argp, &kvm_mce_cap_supported, 4183 sizeof(kvm_mce_cap_supported))) 4184 goto out; 4185 r = 0; 4186 break; 4187 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 4188 struct kvm_msr_list __user *user_msr_list = argp; 4189 struct kvm_msr_list msr_list; 4190 unsigned int n; 4191 4192 r = -EFAULT; 4193 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4194 goto out; 4195 n = msr_list.nmsrs; 4196 msr_list.nmsrs = num_msr_based_features; 4197 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4198 goto out; 4199 r = -E2BIG; 4200 if (n < msr_list.nmsrs) 4201 goto out; 4202 r = -EFAULT; 4203 if (copy_to_user(user_msr_list->indices, &msr_based_features, 4204 num_msr_based_features * sizeof(u32))) 4205 goto out; 4206 r = 0; 4207 break; 4208 } 4209 case KVM_GET_MSRS: 4210 r = msr_io(NULL, argp, do_get_msr_feature, 1); 4211 break; 4212 case KVM_GET_SUPPORTED_HV_CPUID: 4213 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); 4214 break; 4215 default: 4216 r = -EINVAL; 4217 break; 4218 } 4219 out: 4220 return r; 4221 } 4222 4223 static void wbinvd_ipi(void *garbage) 4224 { 4225 wbinvd(); 4226 } 4227 4228 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 4229 { 4230 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 4231 } 4232 4233 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 4234 { 4235 /* Address WBINVD may be executed by guest */ 4236 if (need_emulate_wbinvd(vcpu)) { 4237 if (static_call(kvm_x86_has_wbinvd_exit)()) 4238 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4239 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 4240 smp_call_function_single(vcpu->cpu, 4241 wbinvd_ipi, NULL, 1); 4242 } 4243 4244 static_call(kvm_x86_vcpu_load)(vcpu, cpu); 4245 4246 /* Save host pkru register if supported */ 4247 vcpu->arch.host_pkru = read_pkru(); 4248 4249 /* Apply any externally detected TSC adjustments (due to suspend) */ 4250 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 4251 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 4252 vcpu->arch.tsc_offset_adjustment = 0; 4253 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4254 } 4255 4256 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 4257 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 4258 rdtsc() - vcpu->arch.last_host_tsc; 4259 if (tsc_delta < 0) 4260 mark_tsc_unstable("KVM discovered backwards TSC"); 4261 4262 if (kvm_check_tsc_unstable()) { 4263 u64 offset = kvm_compute_l1_tsc_offset(vcpu, 4264 vcpu->arch.last_guest_tsc); 4265 kvm_vcpu_write_tsc_offset(vcpu, offset); 4266 vcpu->arch.tsc_catchup = 1; 4267 } 4268 4269 if (kvm_lapic_hv_timer_in_use(vcpu)) 4270 kvm_lapic_restart_hv_timer(vcpu); 4271 4272 /* 4273 * On a host with synchronized TSC, there is no need to update 4274 * kvmclock on vcpu->cpu migration 4275 */ 4276 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 4277 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 4278 if (vcpu->cpu != cpu) 4279 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 4280 vcpu->cpu = cpu; 4281 } 4282 4283 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 4284 } 4285 4286 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 4287 { 4288 struct kvm_host_map map; 4289 struct kvm_steal_time *st; 4290 4291 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 4292 return; 4293 4294 if (vcpu->arch.st.preempted) 4295 return; 4296 4297 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, 4298 &vcpu->arch.st.cache, true)) 4299 return; 4300 4301 st = map.hva + 4302 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 4303 4304 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 4305 4306 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); 4307 } 4308 4309 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 4310 { 4311 int idx; 4312 4313 if (vcpu->preempted && !vcpu->arch.guest_state_protected) 4314 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); 4315 4316 /* 4317 * Take the srcu lock as memslots will be accessed to check the gfn 4318 * cache generation against the memslots generation. 4319 */ 4320 idx = srcu_read_lock(&vcpu->kvm->srcu); 4321 if (kvm_xen_msr_enabled(vcpu->kvm)) 4322 kvm_xen_runstate_set_preempted(vcpu); 4323 else 4324 kvm_steal_time_set_preempted(vcpu); 4325 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4326 4327 static_call(kvm_x86_vcpu_put)(vcpu); 4328 vcpu->arch.last_host_tsc = rdtsc(); 4329 } 4330 4331 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 4332 struct kvm_lapic_state *s) 4333 { 4334 if (vcpu->arch.apicv_active) 4335 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 4336 4337 return kvm_apic_get_state(vcpu, s); 4338 } 4339 4340 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 4341 struct kvm_lapic_state *s) 4342 { 4343 int r; 4344 4345 r = kvm_apic_set_state(vcpu, s); 4346 if (r) 4347 return r; 4348 update_cr8_intercept(vcpu); 4349 4350 return 0; 4351 } 4352 4353 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 4354 { 4355 /* 4356 * We can accept userspace's request for interrupt injection 4357 * as long as we have a place to store the interrupt number. 4358 * The actual injection will happen when the CPU is able to 4359 * deliver the interrupt. 4360 */ 4361 if (kvm_cpu_has_extint(vcpu)) 4362 return false; 4363 4364 /* Acknowledging ExtINT does not happen if LINT0 is masked. */ 4365 return (!lapic_in_kernel(vcpu) || 4366 kvm_apic_accept_pic_intr(vcpu)); 4367 } 4368 4369 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 4370 { 4371 /* 4372 * Do not cause an interrupt window exit if an exception 4373 * is pending or an event needs reinjection; userspace 4374 * might want to inject the interrupt manually using KVM_SET_REGS 4375 * or KVM_SET_SREGS. For that to work, we must be at an 4376 * instruction boundary and with no events half-injected. 4377 */ 4378 return (kvm_arch_interrupt_allowed(vcpu) && 4379 kvm_cpu_accept_dm_intr(vcpu) && 4380 !kvm_event_needs_reinjection(vcpu) && 4381 !vcpu->arch.exception.pending); 4382 } 4383 4384 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 4385 struct kvm_interrupt *irq) 4386 { 4387 if (irq->irq >= KVM_NR_INTERRUPTS) 4388 return -EINVAL; 4389 4390 if (!irqchip_in_kernel(vcpu->kvm)) { 4391 kvm_queue_interrupt(vcpu, irq->irq, false); 4392 kvm_make_request(KVM_REQ_EVENT, vcpu); 4393 return 0; 4394 } 4395 4396 /* 4397 * With in-kernel LAPIC, we only use this to inject EXTINT, so 4398 * fail for in-kernel 8259. 4399 */ 4400 if (pic_in_kernel(vcpu->kvm)) 4401 return -ENXIO; 4402 4403 if (vcpu->arch.pending_external_vector != -1) 4404 return -EEXIST; 4405 4406 vcpu->arch.pending_external_vector = irq->irq; 4407 kvm_make_request(KVM_REQ_EVENT, vcpu); 4408 return 0; 4409 } 4410 4411 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 4412 { 4413 kvm_inject_nmi(vcpu); 4414 4415 return 0; 4416 } 4417 4418 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 4419 { 4420 kvm_make_request(KVM_REQ_SMI, vcpu); 4421 4422 return 0; 4423 } 4424 4425 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 4426 struct kvm_tpr_access_ctl *tac) 4427 { 4428 if (tac->flags) 4429 return -EINVAL; 4430 vcpu->arch.tpr_access_reporting = !!tac->enabled; 4431 return 0; 4432 } 4433 4434 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 4435 u64 mcg_cap) 4436 { 4437 int r; 4438 unsigned bank_num = mcg_cap & 0xff, bank; 4439 4440 r = -EINVAL; 4441 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) 4442 goto out; 4443 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 4444 goto out; 4445 r = 0; 4446 vcpu->arch.mcg_cap = mcg_cap; 4447 /* Init IA32_MCG_CTL to all 1s */ 4448 if (mcg_cap & MCG_CTL_P) 4449 vcpu->arch.mcg_ctl = ~(u64)0; 4450 /* Init IA32_MCi_CTL to all 1s */ 4451 for (bank = 0; bank < bank_num; bank++) 4452 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 4453 4454 static_call(kvm_x86_setup_mce)(vcpu); 4455 out: 4456 return r; 4457 } 4458 4459 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 4460 struct kvm_x86_mce *mce) 4461 { 4462 u64 mcg_cap = vcpu->arch.mcg_cap; 4463 unsigned bank_num = mcg_cap & 0xff; 4464 u64 *banks = vcpu->arch.mce_banks; 4465 4466 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 4467 return -EINVAL; 4468 /* 4469 * if IA32_MCG_CTL is not all 1s, the uncorrected error 4470 * reporting is disabled 4471 */ 4472 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 4473 vcpu->arch.mcg_ctl != ~(u64)0) 4474 return 0; 4475 banks += 4 * mce->bank; 4476 /* 4477 * if IA32_MCi_CTL is not all 1s, the uncorrected error 4478 * reporting is disabled for the bank 4479 */ 4480 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 4481 return 0; 4482 if (mce->status & MCI_STATUS_UC) { 4483 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 4484 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 4485 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 4486 return 0; 4487 } 4488 if (banks[1] & MCI_STATUS_VAL) 4489 mce->status |= MCI_STATUS_OVER; 4490 banks[2] = mce->addr; 4491 banks[3] = mce->misc; 4492 vcpu->arch.mcg_status = mce->mcg_status; 4493 banks[1] = mce->status; 4494 kvm_queue_exception(vcpu, MC_VECTOR); 4495 } else if (!(banks[1] & MCI_STATUS_VAL) 4496 || !(banks[1] & MCI_STATUS_UC)) { 4497 if (banks[1] & MCI_STATUS_VAL) 4498 mce->status |= MCI_STATUS_OVER; 4499 banks[2] = mce->addr; 4500 banks[3] = mce->misc; 4501 banks[1] = mce->status; 4502 } else 4503 banks[1] |= MCI_STATUS_OVER; 4504 return 0; 4505 } 4506 4507 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 4508 struct kvm_vcpu_events *events) 4509 { 4510 process_nmi(vcpu); 4511 4512 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 4513 process_smi(vcpu); 4514 4515 /* 4516 * In guest mode, payload delivery should be deferred, 4517 * so that the L1 hypervisor can intercept #PF before 4518 * CR2 is modified (or intercept #DB before DR6 is 4519 * modified under nVMX). Unless the per-VM capability, 4520 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of 4521 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we 4522 * opportunistically defer the exception payload, deliver it if the 4523 * capability hasn't been requested before processing a 4524 * KVM_GET_VCPU_EVENTS. 4525 */ 4526 if (!vcpu->kvm->arch.exception_payload_enabled && 4527 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) 4528 kvm_deliver_exception_payload(vcpu); 4529 4530 /* 4531 * The API doesn't provide the instruction length for software 4532 * exceptions, so don't report them. As long as the guest RIP 4533 * isn't advanced, we should expect to encounter the exception 4534 * again. 4535 */ 4536 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 4537 events->exception.injected = 0; 4538 events->exception.pending = 0; 4539 } else { 4540 events->exception.injected = vcpu->arch.exception.injected; 4541 events->exception.pending = vcpu->arch.exception.pending; 4542 /* 4543 * For ABI compatibility, deliberately conflate 4544 * pending and injected exceptions when 4545 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 4546 */ 4547 if (!vcpu->kvm->arch.exception_payload_enabled) 4548 events->exception.injected |= 4549 vcpu->arch.exception.pending; 4550 } 4551 events->exception.nr = vcpu->arch.exception.nr; 4552 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 4553 events->exception.error_code = vcpu->arch.exception.error_code; 4554 events->exception_has_payload = vcpu->arch.exception.has_payload; 4555 events->exception_payload = vcpu->arch.exception.payload; 4556 4557 events->interrupt.injected = 4558 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 4559 events->interrupt.nr = vcpu->arch.interrupt.nr; 4560 events->interrupt.soft = 0; 4561 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 4562 4563 events->nmi.injected = vcpu->arch.nmi_injected; 4564 events->nmi.pending = vcpu->arch.nmi_pending != 0; 4565 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); 4566 events->nmi.pad = 0; 4567 4568 events->sipi_vector = 0; /* never valid when reporting to user space */ 4569 4570 events->smi.smm = is_smm(vcpu); 4571 events->smi.pending = vcpu->arch.smi_pending; 4572 events->smi.smm_inside_nmi = 4573 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 4574 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 4575 4576 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 4577 | KVM_VCPUEVENT_VALID_SHADOW 4578 | KVM_VCPUEVENT_VALID_SMM); 4579 if (vcpu->kvm->arch.exception_payload_enabled) 4580 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 4581 4582 memset(&events->reserved, 0, sizeof(events->reserved)); 4583 } 4584 4585 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm); 4586 4587 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 4588 struct kvm_vcpu_events *events) 4589 { 4590 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 4591 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 4592 | KVM_VCPUEVENT_VALID_SHADOW 4593 | KVM_VCPUEVENT_VALID_SMM 4594 | KVM_VCPUEVENT_VALID_PAYLOAD)) 4595 return -EINVAL; 4596 4597 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 4598 if (!vcpu->kvm->arch.exception_payload_enabled) 4599 return -EINVAL; 4600 if (events->exception.pending) 4601 events->exception.injected = 0; 4602 else 4603 events->exception_has_payload = 0; 4604 } else { 4605 events->exception.pending = 0; 4606 events->exception_has_payload = 0; 4607 } 4608 4609 if ((events->exception.injected || events->exception.pending) && 4610 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 4611 return -EINVAL; 4612 4613 /* INITs are latched while in SMM */ 4614 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 4615 (events->smi.smm || events->smi.pending) && 4616 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 4617 return -EINVAL; 4618 4619 process_nmi(vcpu); 4620 vcpu->arch.exception.injected = events->exception.injected; 4621 vcpu->arch.exception.pending = events->exception.pending; 4622 vcpu->arch.exception.nr = events->exception.nr; 4623 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 4624 vcpu->arch.exception.error_code = events->exception.error_code; 4625 vcpu->arch.exception.has_payload = events->exception_has_payload; 4626 vcpu->arch.exception.payload = events->exception_payload; 4627 4628 vcpu->arch.interrupt.injected = events->interrupt.injected; 4629 vcpu->arch.interrupt.nr = events->interrupt.nr; 4630 vcpu->arch.interrupt.soft = events->interrupt.soft; 4631 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 4632 static_call(kvm_x86_set_interrupt_shadow)(vcpu, 4633 events->interrupt.shadow); 4634 4635 vcpu->arch.nmi_injected = events->nmi.injected; 4636 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 4637 vcpu->arch.nmi_pending = events->nmi.pending; 4638 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); 4639 4640 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 4641 lapic_in_kernel(vcpu)) 4642 vcpu->arch.apic->sipi_vector = events->sipi_vector; 4643 4644 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 4645 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) 4646 kvm_smm_changed(vcpu, events->smi.smm); 4647 4648 vcpu->arch.smi_pending = events->smi.pending; 4649 4650 if (events->smi.smm) { 4651 if (events->smi.smm_inside_nmi) 4652 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 4653 else 4654 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 4655 } 4656 4657 if (lapic_in_kernel(vcpu)) { 4658 if (events->smi.latched_init) 4659 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4660 else 4661 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4662 } 4663 } 4664 4665 kvm_make_request(KVM_REQ_EVENT, vcpu); 4666 4667 return 0; 4668 } 4669 4670 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 4671 struct kvm_debugregs *dbgregs) 4672 { 4673 unsigned long val; 4674 4675 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 4676 kvm_get_dr(vcpu, 6, &val); 4677 dbgregs->dr6 = val; 4678 dbgregs->dr7 = vcpu->arch.dr7; 4679 dbgregs->flags = 0; 4680 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 4681 } 4682 4683 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 4684 struct kvm_debugregs *dbgregs) 4685 { 4686 if (dbgregs->flags) 4687 return -EINVAL; 4688 4689 if (!kvm_dr6_valid(dbgregs->dr6)) 4690 return -EINVAL; 4691 if (!kvm_dr7_valid(dbgregs->dr7)) 4692 return -EINVAL; 4693 4694 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 4695 kvm_update_dr0123(vcpu); 4696 vcpu->arch.dr6 = dbgregs->dr6; 4697 vcpu->arch.dr7 = dbgregs->dr7; 4698 kvm_update_dr7(vcpu); 4699 4700 return 0; 4701 } 4702 4703 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 4704 struct kvm_xsave *guest_xsave) 4705 { 4706 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 4707 return; 4708 4709 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, 4710 guest_xsave->region, 4711 sizeof(guest_xsave->region), 4712 vcpu->arch.pkru); 4713 } 4714 4715 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 4716 struct kvm_xsave *guest_xsave) 4717 { 4718 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 4719 return 0; 4720 4721 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu, 4722 guest_xsave->region, 4723 supported_xcr0, &vcpu->arch.pkru); 4724 } 4725 4726 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 4727 struct kvm_xcrs *guest_xcrs) 4728 { 4729 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 4730 guest_xcrs->nr_xcrs = 0; 4731 return; 4732 } 4733 4734 guest_xcrs->nr_xcrs = 1; 4735 guest_xcrs->flags = 0; 4736 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 4737 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 4738 } 4739 4740 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 4741 struct kvm_xcrs *guest_xcrs) 4742 { 4743 int i, r = 0; 4744 4745 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 4746 return -EINVAL; 4747 4748 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 4749 return -EINVAL; 4750 4751 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 4752 /* Only support XCR0 currently */ 4753 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 4754 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 4755 guest_xcrs->xcrs[i].value); 4756 break; 4757 } 4758 if (r) 4759 r = -EINVAL; 4760 return r; 4761 } 4762 4763 /* 4764 * kvm_set_guest_paused() indicates to the guest kernel that it has been 4765 * stopped by the hypervisor. This function will be called from the host only. 4766 * EINVAL is returned when the host attempts to set the flag for a guest that 4767 * does not support pv clocks. 4768 */ 4769 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 4770 { 4771 if (!vcpu->arch.pv_time_enabled) 4772 return -EINVAL; 4773 vcpu->arch.pvclock_set_guest_stopped_request = true; 4774 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4775 return 0; 4776 } 4777 4778 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 4779 struct kvm_enable_cap *cap) 4780 { 4781 int r; 4782 uint16_t vmcs_version; 4783 void __user *user_ptr; 4784 4785 if (cap->flags) 4786 return -EINVAL; 4787 4788 switch (cap->cap) { 4789 case KVM_CAP_HYPERV_SYNIC2: 4790 if (cap->args[0]) 4791 return -EINVAL; 4792 fallthrough; 4793 4794 case KVM_CAP_HYPERV_SYNIC: 4795 if (!irqchip_in_kernel(vcpu->kvm)) 4796 return -EINVAL; 4797 return kvm_hv_activate_synic(vcpu, cap->cap == 4798 KVM_CAP_HYPERV_SYNIC2); 4799 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4800 if (!kvm_x86_ops.nested_ops->enable_evmcs) 4801 return -ENOTTY; 4802 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); 4803 if (!r) { 4804 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 4805 if (copy_to_user(user_ptr, &vmcs_version, 4806 sizeof(vmcs_version))) 4807 r = -EFAULT; 4808 } 4809 return r; 4810 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4811 if (!kvm_x86_ops.enable_direct_tlbflush) 4812 return -ENOTTY; 4813 4814 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); 4815 4816 case KVM_CAP_HYPERV_ENFORCE_CPUID: 4817 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]); 4818 4819 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 4820 vcpu->arch.pv_cpuid.enforce = cap->args[0]; 4821 if (vcpu->arch.pv_cpuid.enforce) 4822 kvm_update_pv_runtime(vcpu); 4823 4824 return 0; 4825 default: 4826 return -EINVAL; 4827 } 4828 } 4829 4830 long kvm_arch_vcpu_ioctl(struct file *filp, 4831 unsigned int ioctl, unsigned long arg) 4832 { 4833 struct kvm_vcpu *vcpu = filp->private_data; 4834 void __user *argp = (void __user *)arg; 4835 int r; 4836 union { 4837 struct kvm_sregs2 *sregs2; 4838 struct kvm_lapic_state *lapic; 4839 struct kvm_xsave *xsave; 4840 struct kvm_xcrs *xcrs; 4841 void *buffer; 4842 } u; 4843 4844 vcpu_load(vcpu); 4845 4846 u.buffer = NULL; 4847 switch (ioctl) { 4848 case KVM_GET_LAPIC: { 4849 r = -EINVAL; 4850 if (!lapic_in_kernel(vcpu)) 4851 goto out; 4852 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 4853 GFP_KERNEL_ACCOUNT); 4854 4855 r = -ENOMEM; 4856 if (!u.lapic) 4857 goto out; 4858 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 4859 if (r) 4860 goto out; 4861 r = -EFAULT; 4862 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 4863 goto out; 4864 r = 0; 4865 break; 4866 } 4867 case KVM_SET_LAPIC: { 4868 r = -EINVAL; 4869 if (!lapic_in_kernel(vcpu)) 4870 goto out; 4871 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 4872 if (IS_ERR(u.lapic)) { 4873 r = PTR_ERR(u.lapic); 4874 goto out_nofree; 4875 } 4876 4877 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 4878 break; 4879 } 4880 case KVM_INTERRUPT: { 4881 struct kvm_interrupt irq; 4882 4883 r = -EFAULT; 4884 if (copy_from_user(&irq, argp, sizeof(irq))) 4885 goto out; 4886 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 4887 break; 4888 } 4889 case KVM_NMI: { 4890 r = kvm_vcpu_ioctl_nmi(vcpu); 4891 break; 4892 } 4893 case KVM_SMI: { 4894 r = kvm_vcpu_ioctl_smi(vcpu); 4895 break; 4896 } 4897 case KVM_SET_CPUID: { 4898 struct kvm_cpuid __user *cpuid_arg = argp; 4899 struct kvm_cpuid cpuid; 4900 4901 r = -EFAULT; 4902 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4903 goto out; 4904 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 4905 break; 4906 } 4907 case KVM_SET_CPUID2: { 4908 struct kvm_cpuid2 __user *cpuid_arg = argp; 4909 struct kvm_cpuid2 cpuid; 4910 4911 r = -EFAULT; 4912 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4913 goto out; 4914 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 4915 cpuid_arg->entries); 4916 break; 4917 } 4918 case KVM_GET_CPUID2: { 4919 struct kvm_cpuid2 __user *cpuid_arg = argp; 4920 struct kvm_cpuid2 cpuid; 4921 4922 r = -EFAULT; 4923 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4924 goto out; 4925 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 4926 cpuid_arg->entries); 4927 if (r) 4928 goto out; 4929 r = -EFAULT; 4930 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4931 goto out; 4932 r = 0; 4933 break; 4934 } 4935 case KVM_GET_MSRS: { 4936 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4937 r = msr_io(vcpu, argp, do_get_msr, 1); 4938 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4939 break; 4940 } 4941 case KVM_SET_MSRS: { 4942 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4943 r = msr_io(vcpu, argp, do_set_msr, 0); 4944 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4945 break; 4946 } 4947 case KVM_TPR_ACCESS_REPORTING: { 4948 struct kvm_tpr_access_ctl tac; 4949 4950 r = -EFAULT; 4951 if (copy_from_user(&tac, argp, sizeof(tac))) 4952 goto out; 4953 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 4954 if (r) 4955 goto out; 4956 r = -EFAULT; 4957 if (copy_to_user(argp, &tac, sizeof(tac))) 4958 goto out; 4959 r = 0; 4960 break; 4961 }; 4962 case KVM_SET_VAPIC_ADDR: { 4963 struct kvm_vapic_addr va; 4964 int idx; 4965 4966 r = -EINVAL; 4967 if (!lapic_in_kernel(vcpu)) 4968 goto out; 4969 r = -EFAULT; 4970 if (copy_from_user(&va, argp, sizeof(va))) 4971 goto out; 4972 idx = srcu_read_lock(&vcpu->kvm->srcu); 4973 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 4974 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4975 break; 4976 } 4977 case KVM_X86_SETUP_MCE: { 4978 u64 mcg_cap; 4979 4980 r = -EFAULT; 4981 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 4982 goto out; 4983 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 4984 break; 4985 } 4986 case KVM_X86_SET_MCE: { 4987 struct kvm_x86_mce mce; 4988 4989 r = -EFAULT; 4990 if (copy_from_user(&mce, argp, sizeof(mce))) 4991 goto out; 4992 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 4993 break; 4994 } 4995 case KVM_GET_VCPU_EVENTS: { 4996 struct kvm_vcpu_events events; 4997 4998 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 4999 5000 r = -EFAULT; 5001 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 5002 break; 5003 r = 0; 5004 break; 5005 } 5006 case KVM_SET_VCPU_EVENTS: { 5007 struct kvm_vcpu_events events; 5008 5009 r = -EFAULT; 5010 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 5011 break; 5012 5013 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 5014 break; 5015 } 5016 case KVM_GET_DEBUGREGS: { 5017 struct kvm_debugregs dbgregs; 5018 5019 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 5020 5021 r = -EFAULT; 5022 if (copy_to_user(argp, &dbgregs, 5023 sizeof(struct kvm_debugregs))) 5024 break; 5025 r = 0; 5026 break; 5027 } 5028 case KVM_SET_DEBUGREGS: { 5029 struct kvm_debugregs dbgregs; 5030 5031 r = -EFAULT; 5032 if (copy_from_user(&dbgregs, argp, 5033 sizeof(struct kvm_debugregs))) 5034 break; 5035 5036 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 5037 break; 5038 } 5039 case KVM_GET_XSAVE: { 5040 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 5041 r = -ENOMEM; 5042 if (!u.xsave) 5043 break; 5044 5045 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 5046 5047 r = -EFAULT; 5048 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 5049 break; 5050 r = 0; 5051 break; 5052 } 5053 case KVM_SET_XSAVE: { 5054 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 5055 if (IS_ERR(u.xsave)) { 5056 r = PTR_ERR(u.xsave); 5057 goto out_nofree; 5058 } 5059 5060 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 5061 break; 5062 } 5063 case KVM_GET_XCRS: { 5064 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 5065 r = -ENOMEM; 5066 if (!u.xcrs) 5067 break; 5068 5069 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 5070 5071 r = -EFAULT; 5072 if (copy_to_user(argp, u.xcrs, 5073 sizeof(struct kvm_xcrs))) 5074 break; 5075 r = 0; 5076 break; 5077 } 5078 case KVM_SET_XCRS: { 5079 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 5080 if (IS_ERR(u.xcrs)) { 5081 r = PTR_ERR(u.xcrs); 5082 goto out_nofree; 5083 } 5084 5085 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 5086 break; 5087 } 5088 case KVM_SET_TSC_KHZ: { 5089 u32 user_tsc_khz; 5090 5091 r = -EINVAL; 5092 user_tsc_khz = (u32)arg; 5093 5094 if (kvm_has_tsc_control && 5095 user_tsc_khz >= kvm_max_guest_tsc_khz) 5096 goto out; 5097 5098 if (user_tsc_khz == 0) 5099 user_tsc_khz = tsc_khz; 5100 5101 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 5102 r = 0; 5103 5104 goto out; 5105 } 5106 case KVM_GET_TSC_KHZ: { 5107 r = vcpu->arch.virtual_tsc_khz; 5108 goto out; 5109 } 5110 case KVM_KVMCLOCK_CTRL: { 5111 r = kvm_set_guest_paused(vcpu); 5112 goto out; 5113 } 5114 case KVM_ENABLE_CAP: { 5115 struct kvm_enable_cap cap; 5116 5117 r = -EFAULT; 5118 if (copy_from_user(&cap, argp, sizeof(cap))) 5119 goto out; 5120 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 5121 break; 5122 } 5123 case KVM_GET_NESTED_STATE: { 5124 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5125 u32 user_data_size; 5126 5127 r = -EINVAL; 5128 if (!kvm_x86_ops.nested_ops->get_state) 5129 break; 5130 5131 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 5132 r = -EFAULT; 5133 if (get_user(user_data_size, &user_kvm_nested_state->size)) 5134 break; 5135 5136 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, 5137 user_data_size); 5138 if (r < 0) 5139 break; 5140 5141 if (r > user_data_size) { 5142 if (put_user(r, &user_kvm_nested_state->size)) 5143 r = -EFAULT; 5144 else 5145 r = -E2BIG; 5146 break; 5147 } 5148 5149 r = 0; 5150 break; 5151 } 5152 case KVM_SET_NESTED_STATE: { 5153 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5154 struct kvm_nested_state kvm_state; 5155 int idx; 5156 5157 r = -EINVAL; 5158 if (!kvm_x86_ops.nested_ops->set_state) 5159 break; 5160 5161 r = -EFAULT; 5162 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 5163 break; 5164 5165 r = -EINVAL; 5166 if (kvm_state.size < sizeof(kvm_state)) 5167 break; 5168 5169 if (kvm_state.flags & 5170 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 5171 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING 5172 | KVM_STATE_NESTED_GIF_SET)) 5173 break; 5174 5175 /* nested_run_pending implies guest_mode. */ 5176 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 5177 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 5178 break; 5179 5180 idx = srcu_read_lock(&vcpu->kvm->srcu); 5181 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); 5182 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5183 break; 5184 } 5185 case KVM_GET_SUPPORTED_HV_CPUID: 5186 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); 5187 break; 5188 #ifdef CONFIG_KVM_XEN 5189 case KVM_XEN_VCPU_GET_ATTR: { 5190 struct kvm_xen_vcpu_attr xva; 5191 5192 r = -EFAULT; 5193 if (copy_from_user(&xva, argp, sizeof(xva))) 5194 goto out; 5195 r = kvm_xen_vcpu_get_attr(vcpu, &xva); 5196 if (!r && copy_to_user(argp, &xva, sizeof(xva))) 5197 r = -EFAULT; 5198 break; 5199 } 5200 case KVM_XEN_VCPU_SET_ATTR: { 5201 struct kvm_xen_vcpu_attr xva; 5202 5203 r = -EFAULT; 5204 if (copy_from_user(&xva, argp, sizeof(xva))) 5205 goto out; 5206 r = kvm_xen_vcpu_set_attr(vcpu, &xva); 5207 break; 5208 } 5209 #endif 5210 case KVM_GET_SREGS2: { 5211 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL); 5212 r = -ENOMEM; 5213 if (!u.sregs2) 5214 goto out; 5215 __get_sregs2(vcpu, u.sregs2); 5216 r = -EFAULT; 5217 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2))) 5218 goto out; 5219 r = 0; 5220 break; 5221 } 5222 case KVM_SET_SREGS2: { 5223 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2)); 5224 if (IS_ERR(u.sregs2)) { 5225 r = PTR_ERR(u.sregs2); 5226 u.sregs2 = NULL; 5227 goto out; 5228 } 5229 r = __set_sregs2(vcpu, u.sregs2); 5230 break; 5231 } 5232 default: 5233 r = -EINVAL; 5234 } 5235 out: 5236 kfree(u.buffer); 5237 out_nofree: 5238 vcpu_put(vcpu); 5239 return r; 5240 } 5241 5242 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 5243 { 5244 return VM_FAULT_SIGBUS; 5245 } 5246 5247 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 5248 { 5249 int ret; 5250 5251 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 5252 return -EINVAL; 5253 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); 5254 return ret; 5255 } 5256 5257 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 5258 u64 ident_addr) 5259 { 5260 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); 5261 } 5262 5263 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 5264 unsigned long kvm_nr_mmu_pages) 5265 { 5266 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 5267 return -EINVAL; 5268 5269 mutex_lock(&kvm->slots_lock); 5270 5271 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 5272 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 5273 5274 mutex_unlock(&kvm->slots_lock); 5275 return 0; 5276 } 5277 5278 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 5279 { 5280 return kvm->arch.n_max_mmu_pages; 5281 } 5282 5283 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5284 { 5285 struct kvm_pic *pic = kvm->arch.vpic; 5286 int r; 5287 5288 r = 0; 5289 switch (chip->chip_id) { 5290 case KVM_IRQCHIP_PIC_MASTER: 5291 memcpy(&chip->chip.pic, &pic->pics[0], 5292 sizeof(struct kvm_pic_state)); 5293 break; 5294 case KVM_IRQCHIP_PIC_SLAVE: 5295 memcpy(&chip->chip.pic, &pic->pics[1], 5296 sizeof(struct kvm_pic_state)); 5297 break; 5298 case KVM_IRQCHIP_IOAPIC: 5299 kvm_get_ioapic(kvm, &chip->chip.ioapic); 5300 break; 5301 default: 5302 r = -EINVAL; 5303 break; 5304 } 5305 return r; 5306 } 5307 5308 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5309 { 5310 struct kvm_pic *pic = kvm->arch.vpic; 5311 int r; 5312 5313 r = 0; 5314 switch (chip->chip_id) { 5315 case KVM_IRQCHIP_PIC_MASTER: 5316 spin_lock(&pic->lock); 5317 memcpy(&pic->pics[0], &chip->chip.pic, 5318 sizeof(struct kvm_pic_state)); 5319 spin_unlock(&pic->lock); 5320 break; 5321 case KVM_IRQCHIP_PIC_SLAVE: 5322 spin_lock(&pic->lock); 5323 memcpy(&pic->pics[1], &chip->chip.pic, 5324 sizeof(struct kvm_pic_state)); 5325 spin_unlock(&pic->lock); 5326 break; 5327 case KVM_IRQCHIP_IOAPIC: 5328 kvm_set_ioapic(kvm, &chip->chip.ioapic); 5329 break; 5330 default: 5331 r = -EINVAL; 5332 break; 5333 } 5334 kvm_pic_update_irq(pic); 5335 return r; 5336 } 5337 5338 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5339 { 5340 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 5341 5342 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 5343 5344 mutex_lock(&kps->lock); 5345 memcpy(ps, &kps->channels, sizeof(*ps)); 5346 mutex_unlock(&kps->lock); 5347 return 0; 5348 } 5349 5350 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5351 { 5352 int i; 5353 struct kvm_pit *pit = kvm->arch.vpit; 5354 5355 mutex_lock(&pit->pit_state.lock); 5356 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 5357 for (i = 0; i < 3; i++) 5358 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 5359 mutex_unlock(&pit->pit_state.lock); 5360 return 0; 5361 } 5362 5363 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5364 { 5365 mutex_lock(&kvm->arch.vpit->pit_state.lock); 5366 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 5367 sizeof(ps->channels)); 5368 ps->flags = kvm->arch.vpit->pit_state.flags; 5369 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 5370 memset(&ps->reserved, 0, sizeof(ps->reserved)); 5371 return 0; 5372 } 5373 5374 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5375 { 5376 int start = 0; 5377 int i; 5378 u32 prev_legacy, cur_legacy; 5379 struct kvm_pit *pit = kvm->arch.vpit; 5380 5381 mutex_lock(&pit->pit_state.lock); 5382 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 5383 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 5384 if (!prev_legacy && cur_legacy) 5385 start = 1; 5386 memcpy(&pit->pit_state.channels, &ps->channels, 5387 sizeof(pit->pit_state.channels)); 5388 pit->pit_state.flags = ps->flags; 5389 for (i = 0; i < 3; i++) 5390 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 5391 start && i == 0); 5392 mutex_unlock(&pit->pit_state.lock); 5393 return 0; 5394 } 5395 5396 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 5397 struct kvm_reinject_control *control) 5398 { 5399 struct kvm_pit *pit = kvm->arch.vpit; 5400 5401 /* pit->pit_state.lock was overloaded to prevent userspace from getting 5402 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 5403 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 5404 */ 5405 mutex_lock(&pit->pit_state.lock); 5406 kvm_pit_set_reinject(pit, control->pit_reinject); 5407 mutex_unlock(&pit->pit_state.lock); 5408 5409 return 0; 5410 } 5411 5412 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 5413 { 5414 5415 /* 5416 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called 5417 * before reporting dirty_bitmap to userspace. KVM flushes the buffers 5418 * on all VM-Exits, thus we only need to kick running vCPUs to force a 5419 * VM-Exit. 5420 */ 5421 struct kvm_vcpu *vcpu; 5422 int i; 5423 5424 kvm_for_each_vcpu(i, vcpu, kvm) 5425 kvm_vcpu_kick(vcpu); 5426 } 5427 5428 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 5429 bool line_status) 5430 { 5431 if (!irqchip_in_kernel(kvm)) 5432 return -ENXIO; 5433 5434 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 5435 irq_event->irq, irq_event->level, 5436 line_status); 5437 return 0; 5438 } 5439 5440 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 5441 struct kvm_enable_cap *cap) 5442 { 5443 int r; 5444 5445 if (cap->flags) 5446 return -EINVAL; 5447 5448 switch (cap->cap) { 5449 case KVM_CAP_DISABLE_QUIRKS: 5450 kvm->arch.disabled_quirks = cap->args[0]; 5451 r = 0; 5452 break; 5453 case KVM_CAP_SPLIT_IRQCHIP: { 5454 mutex_lock(&kvm->lock); 5455 r = -EINVAL; 5456 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 5457 goto split_irqchip_unlock; 5458 r = -EEXIST; 5459 if (irqchip_in_kernel(kvm)) 5460 goto split_irqchip_unlock; 5461 if (kvm->created_vcpus) 5462 goto split_irqchip_unlock; 5463 r = kvm_setup_empty_irq_routing(kvm); 5464 if (r) 5465 goto split_irqchip_unlock; 5466 /* Pairs with irqchip_in_kernel. */ 5467 smp_wmb(); 5468 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 5469 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 5470 r = 0; 5471 split_irqchip_unlock: 5472 mutex_unlock(&kvm->lock); 5473 break; 5474 } 5475 case KVM_CAP_X2APIC_API: 5476 r = -EINVAL; 5477 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 5478 break; 5479 5480 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 5481 kvm->arch.x2apic_format = true; 5482 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 5483 kvm->arch.x2apic_broadcast_quirk_disabled = true; 5484 5485 r = 0; 5486 break; 5487 case KVM_CAP_X86_DISABLE_EXITS: 5488 r = -EINVAL; 5489 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 5490 break; 5491 5492 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 5493 kvm_can_mwait_in_guest()) 5494 kvm->arch.mwait_in_guest = true; 5495 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 5496 kvm->arch.hlt_in_guest = true; 5497 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 5498 kvm->arch.pause_in_guest = true; 5499 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) 5500 kvm->arch.cstate_in_guest = true; 5501 r = 0; 5502 break; 5503 case KVM_CAP_MSR_PLATFORM_INFO: 5504 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 5505 r = 0; 5506 break; 5507 case KVM_CAP_EXCEPTION_PAYLOAD: 5508 kvm->arch.exception_payload_enabled = cap->args[0]; 5509 r = 0; 5510 break; 5511 case KVM_CAP_X86_USER_SPACE_MSR: 5512 kvm->arch.user_space_msr_mask = cap->args[0]; 5513 r = 0; 5514 break; 5515 case KVM_CAP_X86_BUS_LOCK_EXIT: 5516 r = -EINVAL; 5517 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) 5518 break; 5519 5520 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && 5521 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) 5522 break; 5523 5524 if (kvm_has_bus_lock_exit && 5525 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) 5526 kvm->arch.bus_lock_detection_enabled = true; 5527 r = 0; 5528 break; 5529 #ifdef CONFIG_X86_SGX_KVM 5530 case KVM_CAP_SGX_ATTRIBUTE: { 5531 unsigned long allowed_attributes = 0; 5532 5533 r = sgx_set_attribute(&allowed_attributes, cap->args[0]); 5534 if (r) 5535 break; 5536 5537 /* KVM only supports the PROVISIONKEY privileged attribute. */ 5538 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && 5539 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) 5540 kvm->arch.sgx_provisioning_allowed = true; 5541 else 5542 r = -EINVAL; 5543 break; 5544 } 5545 #endif 5546 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 5547 r = -EINVAL; 5548 if (kvm_x86_ops.vm_copy_enc_context_from) 5549 r = kvm_x86_ops.vm_copy_enc_context_from(kvm, cap->args[0]); 5550 return r; 5551 case KVM_CAP_EXIT_HYPERCALL: 5552 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) { 5553 r = -EINVAL; 5554 break; 5555 } 5556 kvm->arch.hypercall_exit_enabled = cap->args[0]; 5557 r = 0; 5558 break; 5559 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 5560 r = -EINVAL; 5561 if (cap->args[0] & ~1) 5562 break; 5563 kvm->arch.exit_on_emulation_error = cap->args[0]; 5564 r = 0; 5565 break; 5566 default: 5567 r = -EINVAL; 5568 break; 5569 } 5570 return r; 5571 } 5572 5573 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) 5574 { 5575 struct kvm_x86_msr_filter *msr_filter; 5576 5577 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); 5578 if (!msr_filter) 5579 return NULL; 5580 5581 msr_filter->default_allow = default_allow; 5582 return msr_filter; 5583 } 5584 5585 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) 5586 { 5587 u32 i; 5588 5589 if (!msr_filter) 5590 return; 5591 5592 for (i = 0; i < msr_filter->count; i++) 5593 kfree(msr_filter->ranges[i].bitmap); 5594 5595 kfree(msr_filter); 5596 } 5597 5598 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, 5599 struct kvm_msr_filter_range *user_range) 5600 { 5601 unsigned long *bitmap = NULL; 5602 size_t bitmap_size; 5603 5604 if (!user_range->nmsrs) 5605 return 0; 5606 5607 if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) 5608 return -EINVAL; 5609 5610 if (!user_range->flags) 5611 return -EINVAL; 5612 5613 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); 5614 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) 5615 return -EINVAL; 5616 5617 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); 5618 if (IS_ERR(bitmap)) 5619 return PTR_ERR(bitmap); 5620 5621 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { 5622 .flags = user_range->flags, 5623 .base = user_range->base, 5624 .nmsrs = user_range->nmsrs, 5625 .bitmap = bitmap, 5626 }; 5627 5628 msr_filter->count++; 5629 return 0; 5630 } 5631 5632 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) 5633 { 5634 struct kvm_msr_filter __user *user_msr_filter = argp; 5635 struct kvm_x86_msr_filter *new_filter, *old_filter; 5636 struct kvm_msr_filter filter; 5637 bool default_allow; 5638 bool empty = true; 5639 int r = 0; 5640 u32 i; 5641 5642 if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) 5643 return -EFAULT; 5644 5645 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) 5646 empty &= !filter.ranges[i].nmsrs; 5647 5648 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); 5649 if (empty && !default_allow) 5650 return -EINVAL; 5651 5652 new_filter = kvm_alloc_msr_filter(default_allow); 5653 if (!new_filter) 5654 return -ENOMEM; 5655 5656 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { 5657 r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); 5658 if (r) { 5659 kvm_free_msr_filter(new_filter); 5660 return r; 5661 } 5662 } 5663 5664 mutex_lock(&kvm->lock); 5665 5666 /* The per-VM filter is protected by kvm->lock... */ 5667 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1); 5668 5669 rcu_assign_pointer(kvm->arch.msr_filter, new_filter); 5670 synchronize_srcu(&kvm->srcu); 5671 5672 kvm_free_msr_filter(old_filter); 5673 5674 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); 5675 mutex_unlock(&kvm->lock); 5676 5677 return 0; 5678 } 5679 5680 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER 5681 static int kvm_arch_suspend_notifier(struct kvm *kvm) 5682 { 5683 struct kvm_vcpu *vcpu; 5684 int i, ret = 0; 5685 5686 mutex_lock(&kvm->lock); 5687 kvm_for_each_vcpu(i, vcpu, kvm) { 5688 if (!vcpu->arch.pv_time_enabled) 5689 continue; 5690 5691 ret = kvm_set_guest_paused(vcpu); 5692 if (ret) { 5693 kvm_err("Failed to pause guest VCPU%d: %d\n", 5694 vcpu->vcpu_id, ret); 5695 break; 5696 } 5697 } 5698 mutex_unlock(&kvm->lock); 5699 5700 return ret ? NOTIFY_BAD : NOTIFY_DONE; 5701 } 5702 5703 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state) 5704 { 5705 switch (state) { 5706 case PM_HIBERNATION_PREPARE: 5707 case PM_SUSPEND_PREPARE: 5708 return kvm_arch_suspend_notifier(kvm); 5709 } 5710 5711 return NOTIFY_DONE; 5712 } 5713 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */ 5714 5715 long kvm_arch_vm_ioctl(struct file *filp, 5716 unsigned int ioctl, unsigned long arg) 5717 { 5718 struct kvm *kvm = filp->private_data; 5719 void __user *argp = (void __user *)arg; 5720 int r = -ENOTTY; 5721 /* 5722 * This union makes it completely explicit to gcc-3.x 5723 * that these two variables' stack usage should be 5724 * combined, not added together. 5725 */ 5726 union { 5727 struct kvm_pit_state ps; 5728 struct kvm_pit_state2 ps2; 5729 struct kvm_pit_config pit_config; 5730 } u; 5731 5732 switch (ioctl) { 5733 case KVM_SET_TSS_ADDR: 5734 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 5735 break; 5736 case KVM_SET_IDENTITY_MAP_ADDR: { 5737 u64 ident_addr; 5738 5739 mutex_lock(&kvm->lock); 5740 r = -EINVAL; 5741 if (kvm->created_vcpus) 5742 goto set_identity_unlock; 5743 r = -EFAULT; 5744 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 5745 goto set_identity_unlock; 5746 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 5747 set_identity_unlock: 5748 mutex_unlock(&kvm->lock); 5749 break; 5750 } 5751 case KVM_SET_NR_MMU_PAGES: 5752 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 5753 break; 5754 case KVM_GET_NR_MMU_PAGES: 5755 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 5756 break; 5757 case KVM_CREATE_IRQCHIP: { 5758 mutex_lock(&kvm->lock); 5759 5760 r = -EEXIST; 5761 if (irqchip_in_kernel(kvm)) 5762 goto create_irqchip_unlock; 5763 5764 r = -EINVAL; 5765 if (kvm->created_vcpus) 5766 goto create_irqchip_unlock; 5767 5768 r = kvm_pic_init(kvm); 5769 if (r) 5770 goto create_irqchip_unlock; 5771 5772 r = kvm_ioapic_init(kvm); 5773 if (r) { 5774 kvm_pic_destroy(kvm); 5775 goto create_irqchip_unlock; 5776 } 5777 5778 r = kvm_setup_default_irq_routing(kvm); 5779 if (r) { 5780 kvm_ioapic_destroy(kvm); 5781 kvm_pic_destroy(kvm); 5782 goto create_irqchip_unlock; 5783 } 5784 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 5785 smp_wmb(); 5786 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 5787 create_irqchip_unlock: 5788 mutex_unlock(&kvm->lock); 5789 break; 5790 } 5791 case KVM_CREATE_PIT: 5792 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 5793 goto create_pit; 5794 case KVM_CREATE_PIT2: 5795 r = -EFAULT; 5796 if (copy_from_user(&u.pit_config, argp, 5797 sizeof(struct kvm_pit_config))) 5798 goto out; 5799 create_pit: 5800 mutex_lock(&kvm->lock); 5801 r = -EEXIST; 5802 if (kvm->arch.vpit) 5803 goto create_pit_unlock; 5804 r = -ENOMEM; 5805 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 5806 if (kvm->arch.vpit) 5807 r = 0; 5808 create_pit_unlock: 5809 mutex_unlock(&kvm->lock); 5810 break; 5811 case KVM_GET_IRQCHIP: { 5812 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 5813 struct kvm_irqchip *chip; 5814 5815 chip = memdup_user(argp, sizeof(*chip)); 5816 if (IS_ERR(chip)) { 5817 r = PTR_ERR(chip); 5818 goto out; 5819 } 5820 5821 r = -ENXIO; 5822 if (!irqchip_kernel(kvm)) 5823 goto get_irqchip_out; 5824 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 5825 if (r) 5826 goto get_irqchip_out; 5827 r = -EFAULT; 5828 if (copy_to_user(argp, chip, sizeof(*chip))) 5829 goto get_irqchip_out; 5830 r = 0; 5831 get_irqchip_out: 5832 kfree(chip); 5833 break; 5834 } 5835 case KVM_SET_IRQCHIP: { 5836 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 5837 struct kvm_irqchip *chip; 5838 5839 chip = memdup_user(argp, sizeof(*chip)); 5840 if (IS_ERR(chip)) { 5841 r = PTR_ERR(chip); 5842 goto out; 5843 } 5844 5845 r = -ENXIO; 5846 if (!irqchip_kernel(kvm)) 5847 goto set_irqchip_out; 5848 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 5849 set_irqchip_out: 5850 kfree(chip); 5851 break; 5852 } 5853 case KVM_GET_PIT: { 5854 r = -EFAULT; 5855 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 5856 goto out; 5857 r = -ENXIO; 5858 if (!kvm->arch.vpit) 5859 goto out; 5860 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 5861 if (r) 5862 goto out; 5863 r = -EFAULT; 5864 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 5865 goto out; 5866 r = 0; 5867 break; 5868 } 5869 case KVM_SET_PIT: { 5870 r = -EFAULT; 5871 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 5872 goto out; 5873 mutex_lock(&kvm->lock); 5874 r = -ENXIO; 5875 if (!kvm->arch.vpit) 5876 goto set_pit_out; 5877 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 5878 set_pit_out: 5879 mutex_unlock(&kvm->lock); 5880 break; 5881 } 5882 case KVM_GET_PIT2: { 5883 r = -ENXIO; 5884 if (!kvm->arch.vpit) 5885 goto out; 5886 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 5887 if (r) 5888 goto out; 5889 r = -EFAULT; 5890 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 5891 goto out; 5892 r = 0; 5893 break; 5894 } 5895 case KVM_SET_PIT2: { 5896 r = -EFAULT; 5897 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 5898 goto out; 5899 mutex_lock(&kvm->lock); 5900 r = -ENXIO; 5901 if (!kvm->arch.vpit) 5902 goto set_pit2_out; 5903 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 5904 set_pit2_out: 5905 mutex_unlock(&kvm->lock); 5906 break; 5907 } 5908 case KVM_REINJECT_CONTROL: { 5909 struct kvm_reinject_control control; 5910 r = -EFAULT; 5911 if (copy_from_user(&control, argp, sizeof(control))) 5912 goto out; 5913 r = -ENXIO; 5914 if (!kvm->arch.vpit) 5915 goto out; 5916 r = kvm_vm_ioctl_reinject(kvm, &control); 5917 break; 5918 } 5919 case KVM_SET_BOOT_CPU_ID: 5920 r = 0; 5921 mutex_lock(&kvm->lock); 5922 if (kvm->created_vcpus) 5923 r = -EBUSY; 5924 else 5925 kvm->arch.bsp_vcpu_id = arg; 5926 mutex_unlock(&kvm->lock); 5927 break; 5928 #ifdef CONFIG_KVM_XEN 5929 case KVM_XEN_HVM_CONFIG: { 5930 struct kvm_xen_hvm_config xhc; 5931 r = -EFAULT; 5932 if (copy_from_user(&xhc, argp, sizeof(xhc))) 5933 goto out; 5934 r = kvm_xen_hvm_config(kvm, &xhc); 5935 break; 5936 } 5937 case KVM_XEN_HVM_GET_ATTR: { 5938 struct kvm_xen_hvm_attr xha; 5939 5940 r = -EFAULT; 5941 if (copy_from_user(&xha, argp, sizeof(xha))) 5942 goto out; 5943 r = kvm_xen_hvm_get_attr(kvm, &xha); 5944 if (!r && copy_to_user(argp, &xha, sizeof(xha))) 5945 r = -EFAULT; 5946 break; 5947 } 5948 case KVM_XEN_HVM_SET_ATTR: { 5949 struct kvm_xen_hvm_attr xha; 5950 5951 r = -EFAULT; 5952 if (copy_from_user(&xha, argp, sizeof(xha))) 5953 goto out; 5954 r = kvm_xen_hvm_set_attr(kvm, &xha); 5955 break; 5956 } 5957 #endif 5958 case KVM_SET_CLOCK: { 5959 struct kvm_arch *ka = &kvm->arch; 5960 struct kvm_clock_data user_ns; 5961 u64 now_ns; 5962 5963 r = -EFAULT; 5964 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 5965 goto out; 5966 5967 r = -EINVAL; 5968 if (user_ns.flags) 5969 goto out; 5970 5971 r = 0; 5972 /* 5973 * TODO: userspace has to take care of races with VCPU_RUN, so 5974 * kvm_gen_update_masterclock() can be cut down to locked 5975 * pvclock_update_vm_gtod_copy(). 5976 */ 5977 kvm_gen_update_masterclock(kvm); 5978 5979 /* 5980 * This pairs with kvm_guest_time_update(): when masterclock is 5981 * in use, we use master_kernel_ns + kvmclock_offset to set 5982 * unsigned 'system_time' so if we use get_kvmclock_ns() (which 5983 * is slightly ahead) here we risk going negative on unsigned 5984 * 'system_time' when 'user_ns.clock' is very small. 5985 */ 5986 raw_spin_lock_irq(&ka->pvclock_gtod_sync_lock); 5987 if (kvm->arch.use_master_clock) 5988 now_ns = ka->master_kernel_ns; 5989 else 5990 now_ns = get_kvmclock_base_ns(); 5991 ka->kvmclock_offset = user_ns.clock - now_ns; 5992 raw_spin_unlock_irq(&ka->pvclock_gtod_sync_lock); 5993 5994 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); 5995 break; 5996 } 5997 case KVM_GET_CLOCK: { 5998 struct kvm_clock_data user_ns; 5999 u64 now_ns; 6000 6001 now_ns = get_kvmclock_ns(kvm); 6002 user_ns.clock = now_ns; 6003 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 6004 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 6005 6006 r = -EFAULT; 6007 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 6008 goto out; 6009 r = 0; 6010 break; 6011 } 6012 case KVM_MEMORY_ENCRYPT_OP: { 6013 r = -ENOTTY; 6014 if (kvm_x86_ops.mem_enc_op) 6015 r = static_call(kvm_x86_mem_enc_op)(kvm, argp); 6016 break; 6017 } 6018 case KVM_MEMORY_ENCRYPT_REG_REGION: { 6019 struct kvm_enc_region region; 6020 6021 r = -EFAULT; 6022 if (copy_from_user(®ion, argp, sizeof(region))) 6023 goto out; 6024 6025 r = -ENOTTY; 6026 if (kvm_x86_ops.mem_enc_reg_region) 6027 r = static_call(kvm_x86_mem_enc_reg_region)(kvm, ®ion); 6028 break; 6029 } 6030 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 6031 struct kvm_enc_region region; 6032 6033 r = -EFAULT; 6034 if (copy_from_user(®ion, argp, sizeof(region))) 6035 goto out; 6036 6037 r = -ENOTTY; 6038 if (kvm_x86_ops.mem_enc_unreg_region) 6039 r = static_call(kvm_x86_mem_enc_unreg_region)(kvm, ®ion); 6040 break; 6041 } 6042 case KVM_HYPERV_EVENTFD: { 6043 struct kvm_hyperv_eventfd hvevfd; 6044 6045 r = -EFAULT; 6046 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 6047 goto out; 6048 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 6049 break; 6050 } 6051 case KVM_SET_PMU_EVENT_FILTER: 6052 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); 6053 break; 6054 case KVM_X86_SET_MSR_FILTER: 6055 r = kvm_vm_ioctl_set_msr_filter(kvm, argp); 6056 break; 6057 default: 6058 r = -ENOTTY; 6059 } 6060 out: 6061 return r; 6062 } 6063 6064 static void kvm_init_msr_list(void) 6065 { 6066 struct x86_pmu_capability x86_pmu; 6067 u32 dummy[2]; 6068 unsigned i; 6069 6070 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, 6071 "Please update the fixed PMCs in msrs_to_saved_all[]"); 6072 6073 perf_get_x86_pmu_capability(&x86_pmu); 6074 6075 num_msrs_to_save = 0; 6076 num_emulated_msrs = 0; 6077 num_msr_based_features = 0; 6078 6079 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { 6080 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) 6081 continue; 6082 6083 /* 6084 * Even MSRs that are valid in the host may not be exposed 6085 * to the guests in some cases. 6086 */ 6087 switch (msrs_to_save_all[i]) { 6088 case MSR_IA32_BNDCFGS: 6089 if (!kvm_mpx_supported()) 6090 continue; 6091 break; 6092 case MSR_TSC_AUX: 6093 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && 6094 !kvm_cpu_cap_has(X86_FEATURE_RDPID)) 6095 continue; 6096 break; 6097 case MSR_IA32_UMWAIT_CONTROL: 6098 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) 6099 continue; 6100 break; 6101 case MSR_IA32_RTIT_CTL: 6102 case MSR_IA32_RTIT_STATUS: 6103 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) 6104 continue; 6105 break; 6106 case MSR_IA32_RTIT_CR3_MATCH: 6107 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6108 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 6109 continue; 6110 break; 6111 case MSR_IA32_RTIT_OUTPUT_BASE: 6112 case MSR_IA32_RTIT_OUTPUT_MASK: 6113 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6114 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 6115 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 6116 continue; 6117 break; 6118 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 6119 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6120 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= 6121 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 6122 continue; 6123 break; 6124 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: 6125 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= 6126 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 6127 continue; 6128 break; 6129 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: 6130 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= 6131 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 6132 continue; 6133 break; 6134 default: 6135 break; 6136 } 6137 6138 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; 6139 } 6140 6141 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { 6142 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) 6143 continue; 6144 6145 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; 6146 } 6147 6148 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { 6149 struct kvm_msr_entry msr; 6150 6151 msr.index = msr_based_features_all[i]; 6152 if (kvm_get_msr_feature(&msr)) 6153 continue; 6154 6155 msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; 6156 } 6157 } 6158 6159 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 6160 const void *v) 6161 { 6162 int handled = 0; 6163 int n; 6164 6165 do { 6166 n = min(len, 8); 6167 if (!(lapic_in_kernel(vcpu) && 6168 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 6169 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 6170 break; 6171 handled += n; 6172 addr += n; 6173 len -= n; 6174 v += n; 6175 } while (len); 6176 6177 return handled; 6178 } 6179 6180 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 6181 { 6182 int handled = 0; 6183 int n; 6184 6185 do { 6186 n = min(len, 8); 6187 if (!(lapic_in_kernel(vcpu) && 6188 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 6189 addr, n, v)) 6190 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 6191 break; 6192 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 6193 handled += n; 6194 addr += n; 6195 len -= n; 6196 v += n; 6197 } while (len); 6198 6199 return handled; 6200 } 6201 6202 static void kvm_set_segment(struct kvm_vcpu *vcpu, 6203 struct kvm_segment *var, int seg) 6204 { 6205 static_call(kvm_x86_set_segment)(vcpu, var, seg); 6206 } 6207 6208 void kvm_get_segment(struct kvm_vcpu *vcpu, 6209 struct kvm_segment *var, int seg) 6210 { 6211 static_call(kvm_x86_get_segment)(vcpu, var, seg); 6212 } 6213 6214 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 6215 struct x86_exception *exception) 6216 { 6217 gpa_t t_gpa; 6218 6219 BUG_ON(!mmu_is_nested(vcpu)); 6220 6221 /* NPT walks are always user-walks */ 6222 access |= PFERR_USER_MASK; 6223 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); 6224 6225 return t_gpa; 6226 } 6227 6228 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 6229 struct x86_exception *exception) 6230 { 6231 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6232 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6233 } 6234 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); 6235 6236 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 6237 struct x86_exception *exception) 6238 { 6239 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6240 access |= PFERR_FETCH_MASK; 6241 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6242 } 6243 6244 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 6245 struct x86_exception *exception) 6246 { 6247 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6248 access |= PFERR_WRITE_MASK; 6249 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6250 } 6251 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); 6252 6253 /* uses this to access any guest's mapped memory without checking CPL */ 6254 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 6255 struct x86_exception *exception) 6256 { 6257 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 6258 } 6259 6260 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6261 struct kvm_vcpu *vcpu, u32 access, 6262 struct x86_exception *exception) 6263 { 6264 void *data = val; 6265 int r = X86EMUL_CONTINUE; 6266 6267 while (bytes) { 6268 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 6269 exception); 6270 unsigned offset = addr & (PAGE_SIZE-1); 6271 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 6272 int ret; 6273 6274 if (gpa == UNMAPPED_GVA) 6275 return X86EMUL_PROPAGATE_FAULT; 6276 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 6277 offset, toread); 6278 if (ret < 0) { 6279 r = X86EMUL_IO_NEEDED; 6280 goto out; 6281 } 6282 6283 bytes -= toread; 6284 data += toread; 6285 addr += toread; 6286 } 6287 out: 6288 return r; 6289 } 6290 6291 /* used for instruction fetching */ 6292 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 6293 gva_t addr, void *val, unsigned int bytes, 6294 struct x86_exception *exception) 6295 { 6296 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6297 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6298 unsigned offset; 6299 int ret; 6300 6301 /* Inline kvm_read_guest_virt_helper for speed. */ 6302 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 6303 exception); 6304 if (unlikely(gpa == UNMAPPED_GVA)) 6305 return X86EMUL_PROPAGATE_FAULT; 6306 6307 offset = addr & (PAGE_SIZE-1); 6308 if (WARN_ON(offset + bytes > PAGE_SIZE)) 6309 bytes = (unsigned)PAGE_SIZE - offset; 6310 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 6311 offset, bytes); 6312 if (unlikely(ret < 0)) 6313 return X86EMUL_IO_NEEDED; 6314 6315 return X86EMUL_CONTINUE; 6316 } 6317 6318 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 6319 gva_t addr, void *val, unsigned int bytes, 6320 struct x86_exception *exception) 6321 { 6322 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6323 6324 /* 6325 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 6326 * is returned, but our callers are not ready for that and they blindly 6327 * call kvm_inject_page_fault. Ensure that they at least do not leak 6328 * uninitialized kernel stack memory into cr2 and error code. 6329 */ 6330 memset(exception, 0, sizeof(*exception)); 6331 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 6332 exception); 6333 } 6334 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 6335 6336 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 6337 gva_t addr, void *val, unsigned int bytes, 6338 struct x86_exception *exception, bool system) 6339 { 6340 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6341 u32 access = 0; 6342 6343 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6344 access |= PFERR_USER_MASK; 6345 6346 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 6347 } 6348 6349 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 6350 unsigned long addr, void *val, unsigned int bytes) 6351 { 6352 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6353 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 6354 6355 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 6356 } 6357 6358 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6359 struct kvm_vcpu *vcpu, u32 access, 6360 struct x86_exception *exception) 6361 { 6362 void *data = val; 6363 int r = X86EMUL_CONTINUE; 6364 6365 while (bytes) { 6366 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 6367 access, 6368 exception); 6369 unsigned offset = addr & (PAGE_SIZE-1); 6370 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 6371 int ret; 6372 6373 if (gpa == UNMAPPED_GVA) 6374 return X86EMUL_PROPAGATE_FAULT; 6375 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 6376 if (ret < 0) { 6377 r = X86EMUL_IO_NEEDED; 6378 goto out; 6379 } 6380 6381 bytes -= towrite; 6382 data += towrite; 6383 addr += towrite; 6384 } 6385 out: 6386 return r; 6387 } 6388 6389 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 6390 unsigned int bytes, struct x86_exception *exception, 6391 bool system) 6392 { 6393 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6394 u32 access = PFERR_WRITE_MASK; 6395 6396 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6397 access |= PFERR_USER_MASK; 6398 6399 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6400 access, exception); 6401 } 6402 6403 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 6404 unsigned int bytes, struct x86_exception *exception) 6405 { 6406 /* kvm_write_guest_virt_system can pull in tons of pages. */ 6407 vcpu->arch.l1tf_flush_l1d = true; 6408 6409 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6410 PFERR_WRITE_MASK, exception); 6411 } 6412 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 6413 6414 int handle_ud(struct kvm_vcpu *vcpu) 6415 { 6416 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; 6417 int emul_type = EMULTYPE_TRAP_UD; 6418 char sig[5]; /* ud2; .ascii "kvm" */ 6419 struct x86_exception e; 6420 6421 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, NULL, 0))) 6422 return 1; 6423 6424 if (force_emulation_prefix && 6425 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 6426 sig, sizeof(sig), &e) == 0 && 6427 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { 6428 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 6429 emul_type = EMULTYPE_TRAP_UD_FORCED; 6430 } 6431 6432 return kvm_emulate_instruction(vcpu, emul_type); 6433 } 6434 EXPORT_SYMBOL_GPL(handle_ud); 6435 6436 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6437 gpa_t gpa, bool write) 6438 { 6439 /* For APIC access vmexit */ 6440 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 6441 return 1; 6442 6443 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 6444 trace_vcpu_match_mmio(gva, gpa, write, true); 6445 return 1; 6446 } 6447 6448 return 0; 6449 } 6450 6451 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6452 gpa_t *gpa, struct x86_exception *exception, 6453 bool write) 6454 { 6455 u32 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) 6456 | (write ? PFERR_WRITE_MASK : 0); 6457 6458 /* 6459 * currently PKRU is only applied to ept enabled guest so 6460 * there is no pkey in EPT page table for L1 guest or EPT 6461 * shadow page table for L2 guest. 6462 */ 6463 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) || 6464 !permission_fault(vcpu, vcpu->arch.walk_mmu, 6465 vcpu->arch.mmio_access, 0, access))) { 6466 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 6467 (gva & (PAGE_SIZE - 1)); 6468 trace_vcpu_match_mmio(gva, *gpa, write, false); 6469 return 1; 6470 } 6471 6472 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6473 6474 if (*gpa == UNMAPPED_GVA) 6475 return -1; 6476 6477 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 6478 } 6479 6480 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 6481 const void *val, int bytes) 6482 { 6483 int ret; 6484 6485 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 6486 if (ret < 0) 6487 return 0; 6488 kvm_page_track_write(vcpu, gpa, val, bytes); 6489 return 1; 6490 } 6491 6492 struct read_write_emulator_ops { 6493 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 6494 int bytes); 6495 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 6496 void *val, int bytes); 6497 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6498 int bytes, void *val); 6499 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6500 void *val, int bytes); 6501 bool write; 6502 }; 6503 6504 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 6505 { 6506 if (vcpu->mmio_read_completed) { 6507 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 6508 vcpu->mmio_fragments[0].gpa, val); 6509 vcpu->mmio_read_completed = 0; 6510 return 1; 6511 } 6512 6513 return 0; 6514 } 6515 6516 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6517 void *val, int bytes) 6518 { 6519 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 6520 } 6521 6522 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6523 void *val, int bytes) 6524 { 6525 return emulator_write_phys(vcpu, gpa, val, bytes); 6526 } 6527 6528 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 6529 { 6530 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 6531 return vcpu_mmio_write(vcpu, gpa, bytes, val); 6532 } 6533 6534 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6535 void *val, int bytes) 6536 { 6537 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 6538 return X86EMUL_IO_NEEDED; 6539 } 6540 6541 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6542 void *val, int bytes) 6543 { 6544 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 6545 6546 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 6547 return X86EMUL_CONTINUE; 6548 } 6549 6550 static const struct read_write_emulator_ops read_emultor = { 6551 .read_write_prepare = read_prepare, 6552 .read_write_emulate = read_emulate, 6553 .read_write_mmio = vcpu_mmio_read, 6554 .read_write_exit_mmio = read_exit_mmio, 6555 }; 6556 6557 static const struct read_write_emulator_ops write_emultor = { 6558 .read_write_emulate = write_emulate, 6559 .read_write_mmio = write_mmio, 6560 .read_write_exit_mmio = write_exit_mmio, 6561 .write = true, 6562 }; 6563 6564 static int emulator_read_write_onepage(unsigned long addr, void *val, 6565 unsigned int bytes, 6566 struct x86_exception *exception, 6567 struct kvm_vcpu *vcpu, 6568 const struct read_write_emulator_ops *ops) 6569 { 6570 gpa_t gpa; 6571 int handled, ret; 6572 bool write = ops->write; 6573 struct kvm_mmio_fragment *frag; 6574 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6575 6576 /* 6577 * If the exit was due to a NPF we may already have a GPA. 6578 * If the GPA is present, use it to avoid the GVA to GPA table walk. 6579 * Note, this cannot be used on string operations since string 6580 * operation using rep will only have the initial GPA from the NPF 6581 * occurred. 6582 */ 6583 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && 6584 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { 6585 gpa = ctxt->gpa_val; 6586 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 6587 } else { 6588 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 6589 if (ret < 0) 6590 return X86EMUL_PROPAGATE_FAULT; 6591 } 6592 6593 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 6594 return X86EMUL_CONTINUE; 6595 6596 /* 6597 * Is this MMIO handled locally? 6598 */ 6599 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 6600 if (handled == bytes) 6601 return X86EMUL_CONTINUE; 6602 6603 gpa += handled; 6604 bytes -= handled; 6605 val += handled; 6606 6607 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 6608 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 6609 frag->gpa = gpa; 6610 frag->data = val; 6611 frag->len = bytes; 6612 return X86EMUL_CONTINUE; 6613 } 6614 6615 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 6616 unsigned long addr, 6617 void *val, unsigned int bytes, 6618 struct x86_exception *exception, 6619 const struct read_write_emulator_ops *ops) 6620 { 6621 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6622 gpa_t gpa; 6623 int rc; 6624 6625 if (ops->read_write_prepare && 6626 ops->read_write_prepare(vcpu, val, bytes)) 6627 return X86EMUL_CONTINUE; 6628 6629 vcpu->mmio_nr_fragments = 0; 6630 6631 /* Crossing a page boundary? */ 6632 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 6633 int now; 6634 6635 now = -addr & ~PAGE_MASK; 6636 rc = emulator_read_write_onepage(addr, val, now, exception, 6637 vcpu, ops); 6638 6639 if (rc != X86EMUL_CONTINUE) 6640 return rc; 6641 addr += now; 6642 if (ctxt->mode != X86EMUL_MODE_PROT64) 6643 addr = (u32)addr; 6644 val += now; 6645 bytes -= now; 6646 } 6647 6648 rc = emulator_read_write_onepage(addr, val, bytes, exception, 6649 vcpu, ops); 6650 if (rc != X86EMUL_CONTINUE) 6651 return rc; 6652 6653 if (!vcpu->mmio_nr_fragments) 6654 return rc; 6655 6656 gpa = vcpu->mmio_fragments[0].gpa; 6657 6658 vcpu->mmio_needed = 1; 6659 vcpu->mmio_cur_fragment = 0; 6660 6661 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 6662 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 6663 vcpu->run->exit_reason = KVM_EXIT_MMIO; 6664 vcpu->run->mmio.phys_addr = gpa; 6665 6666 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 6667 } 6668 6669 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 6670 unsigned long addr, 6671 void *val, 6672 unsigned int bytes, 6673 struct x86_exception *exception) 6674 { 6675 return emulator_read_write(ctxt, addr, val, bytes, 6676 exception, &read_emultor); 6677 } 6678 6679 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 6680 unsigned long addr, 6681 const void *val, 6682 unsigned int bytes, 6683 struct x86_exception *exception) 6684 { 6685 return emulator_read_write(ctxt, addr, (void *)val, bytes, 6686 exception, &write_emultor); 6687 } 6688 6689 #define CMPXCHG_TYPE(t, ptr, old, new) \ 6690 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 6691 6692 #ifdef CONFIG_X86_64 6693 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 6694 #else 6695 # define CMPXCHG64(ptr, old, new) \ 6696 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 6697 #endif 6698 6699 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 6700 unsigned long addr, 6701 const void *old, 6702 const void *new, 6703 unsigned int bytes, 6704 struct x86_exception *exception) 6705 { 6706 struct kvm_host_map map; 6707 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6708 u64 page_line_mask; 6709 gpa_t gpa; 6710 char *kaddr; 6711 bool exchanged; 6712 6713 /* guests cmpxchg8b have to be emulated atomically */ 6714 if (bytes > 8 || (bytes & (bytes - 1))) 6715 goto emul_write; 6716 6717 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 6718 6719 if (gpa == UNMAPPED_GVA || 6720 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 6721 goto emul_write; 6722 6723 /* 6724 * Emulate the atomic as a straight write to avoid #AC if SLD is 6725 * enabled in the host and the access splits a cache line. 6726 */ 6727 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 6728 page_line_mask = ~(cache_line_size() - 1); 6729 else 6730 page_line_mask = PAGE_MASK; 6731 6732 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) 6733 goto emul_write; 6734 6735 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) 6736 goto emul_write; 6737 6738 kaddr = map.hva + offset_in_page(gpa); 6739 6740 switch (bytes) { 6741 case 1: 6742 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 6743 break; 6744 case 2: 6745 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 6746 break; 6747 case 4: 6748 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 6749 break; 6750 case 8: 6751 exchanged = CMPXCHG64(kaddr, old, new); 6752 break; 6753 default: 6754 BUG(); 6755 } 6756 6757 kvm_vcpu_unmap(vcpu, &map, true); 6758 6759 if (!exchanged) 6760 return X86EMUL_CMPXCHG_FAILED; 6761 6762 kvm_page_track_write(vcpu, gpa, new, bytes); 6763 6764 return X86EMUL_CONTINUE; 6765 6766 emul_write: 6767 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 6768 6769 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 6770 } 6771 6772 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 6773 { 6774 int r = 0, i; 6775 6776 for (i = 0; i < vcpu->arch.pio.count; i++) { 6777 if (vcpu->arch.pio.in) 6778 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 6779 vcpu->arch.pio.size, pd); 6780 else 6781 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 6782 vcpu->arch.pio.port, vcpu->arch.pio.size, 6783 pd); 6784 if (r) 6785 break; 6786 pd += vcpu->arch.pio.size; 6787 } 6788 return r; 6789 } 6790 6791 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 6792 unsigned short port, 6793 unsigned int count, bool in) 6794 { 6795 vcpu->arch.pio.port = port; 6796 vcpu->arch.pio.in = in; 6797 vcpu->arch.pio.count = count; 6798 vcpu->arch.pio.size = size; 6799 6800 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) 6801 return 1; 6802 6803 vcpu->run->exit_reason = KVM_EXIT_IO; 6804 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 6805 vcpu->run->io.size = size; 6806 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 6807 vcpu->run->io.count = count; 6808 vcpu->run->io.port = port; 6809 6810 return 0; 6811 } 6812 6813 static int __emulator_pio_in(struct kvm_vcpu *vcpu, int size, 6814 unsigned short port, unsigned int count) 6815 { 6816 WARN_ON(vcpu->arch.pio.count); 6817 memset(vcpu->arch.pio_data, 0, size * count); 6818 return emulator_pio_in_out(vcpu, size, port, count, true); 6819 } 6820 6821 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val) 6822 { 6823 int size = vcpu->arch.pio.size; 6824 unsigned count = vcpu->arch.pio.count; 6825 memcpy(val, vcpu->arch.pio_data, size * count); 6826 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data); 6827 vcpu->arch.pio.count = 0; 6828 } 6829 6830 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, 6831 unsigned short port, void *val, unsigned int count) 6832 { 6833 if (vcpu->arch.pio.count) { 6834 /* Complete previous iteration. */ 6835 } else { 6836 int r = __emulator_pio_in(vcpu, size, port, count); 6837 if (!r) 6838 return r; 6839 6840 /* Results already available, fall through. */ 6841 } 6842 6843 WARN_ON(count != vcpu->arch.pio.count); 6844 complete_emulator_pio_in(vcpu, val); 6845 return 1; 6846 } 6847 6848 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 6849 int size, unsigned short port, void *val, 6850 unsigned int count) 6851 { 6852 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); 6853 6854 } 6855 6856 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, 6857 unsigned short port, const void *val, 6858 unsigned int count) 6859 { 6860 int ret; 6861 6862 memcpy(vcpu->arch.pio_data, val, size * count); 6863 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 6864 ret = emulator_pio_in_out(vcpu, size, port, count, false); 6865 if (ret) 6866 vcpu->arch.pio.count = 0; 6867 6868 return ret; 6869 } 6870 6871 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 6872 int size, unsigned short port, 6873 const void *val, unsigned int count) 6874 { 6875 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); 6876 } 6877 6878 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 6879 { 6880 return static_call(kvm_x86_get_segment_base)(vcpu, seg); 6881 } 6882 6883 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 6884 { 6885 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 6886 } 6887 6888 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 6889 { 6890 if (!need_emulate_wbinvd(vcpu)) 6891 return X86EMUL_CONTINUE; 6892 6893 if (static_call(kvm_x86_has_wbinvd_exit)()) { 6894 int cpu = get_cpu(); 6895 6896 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 6897 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, 6898 wbinvd_ipi, NULL, 1); 6899 put_cpu(); 6900 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 6901 } else 6902 wbinvd(); 6903 return X86EMUL_CONTINUE; 6904 } 6905 6906 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 6907 { 6908 kvm_emulate_wbinvd_noskip(vcpu); 6909 return kvm_skip_emulated_instruction(vcpu); 6910 } 6911 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 6912 6913 6914 6915 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 6916 { 6917 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 6918 } 6919 6920 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 6921 unsigned long *dest) 6922 { 6923 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 6924 } 6925 6926 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 6927 unsigned long value) 6928 { 6929 6930 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 6931 } 6932 6933 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 6934 { 6935 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 6936 } 6937 6938 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 6939 { 6940 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6941 unsigned long value; 6942 6943 switch (cr) { 6944 case 0: 6945 value = kvm_read_cr0(vcpu); 6946 break; 6947 case 2: 6948 value = vcpu->arch.cr2; 6949 break; 6950 case 3: 6951 value = kvm_read_cr3(vcpu); 6952 break; 6953 case 4: 6954 value = kvm_read_cr4(vcpu); 6955 break; 6956 case 8: 6957 value = kvm_get_cr8(vcpu); 6958 break; 6959 default: 6960 kvm_err("%s: unexpected cr %u\n", __func__, cr); 6961 return 0; 6962 } 6963 6964 return value; 6965 } 6966 6967 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 6968 { 6969 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6970 int res = 0; 6971 6972 switch (cr) { 6973 case 0: 6974 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 6975 break; 6976 case 2: 6977 vcpu->arch.cr2 = val; 6978 break; 6979 case 3: 6980 res = kvm_set_cr3(vcpu, val); 6981 break; 6982 case 4: 6983 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 6984 break; 6985 case 8: 6986 res = kvm_set_cr8(vcpu, val); 6987 break; 6988 default: 6989 kvm_err("%s: unexpected cr %u\n", __func__, cr); 6990 res = -1; 6991 } 6992 6993 return res; 6994 } 6995 6996 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 6997 { 6998 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); 6999 } 7000 7001 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7002 { 7003 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); 7004 } 7005 7006 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7007 { 7008 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); 7009 } 7010 7011 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7012 { 7013 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); 7014 } 7015 7016 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7017 { 7018 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); 7019 } 7020 7021 static unsigned long emulator_get_cached_segment_base( 7022 struct x86_emulate_ctxt *ctxt, int seg) 7023 { 7024 return get_segment_base(emul_to_vcpu(ctxt), seg); 7025 } 7026 7027 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 7028 struct desc_struct *desc, u32 *base3, 7029 int seg) 7030 { 7031 struct kvm_segment var; 7032 7033 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 7034 *selector = var.selector; 7035 7036 if (var.unusable) { 7037 memset(desc, 0, sizeof(*desc)); 7038 if (base3) 7039 *base3 = 0; 7040 return false; 7041 } 7042 7043 if (var.g) 7044 var.limit >>= 12; 7045 set_desc_limit(desc, var.limit); 7046 set_desc_base(desc, (unsigned long)var.base); 7047 #ifdef CONFIG_X86_64 7048 if (base3) 7049 *base3 = var.base >> 32; 7050 #endif 7051 desc->type = var.type; 7052 desc->s = var.s; 7053 desc->dpl = var.dpl; 7054 desc->p = var.present; 7055 desc->avl = var.avl; 7056 desc->l = var.l; 7057 desc->d = var.db; 7058 desc->g = var.g; 7059 7060 return true; 7061 } 7062 7063 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 7064 struct desc_struct *desc, u32 base3, 7065 int seg) 7066 { 7067 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7068 struct kvm_segment var; 7069 7070 var.selector = selector; 7071 var.base = get_desc_base(desc); 7072 #ifdef CONFIG_X86_64 7073 var.base |= ((u64)base3) << 32; 7074 #endif 7075 var.limit = get_desc_limit(desc); 7076 if (desc->g) 7077 var.limit = (var.limit << 12) | 0xfff; 7078 var.type = desc->type; 7079 var.dpl = desc->dpl; 7080 var.db = desc->d; 7081 var.s = desc->s; 7082 var.l = desc->l; 7083 var.g = desc->g; 7084 var.avl = desc->avl; 7085 var.present = desc->p; 7086 var.unusable = !var.present; 7087 var.padding = 0; 7088 7089 kvm_set_segment(vcpu, &var, seg); 7090 return; 7091 } 7092 7093 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 7094 u32 msr_index, u64 *pdata) 7095 { 7096 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7097 int r; 7098 7099 r = kvm_get_msr(vcpu, msr_index, pdata); 7100 7101 if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) { 7102 /* Bounce to user space */ 7103 return X86EMUL_IO_NEEDED; 7104 } 7105 7106 return r; 7107 } 7108 7109 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 7110 u32 msr_index, u64 data) 7111 { 7112 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7113 int r; 7114 7115 r = kvm_set_msr(vcpu, msr_index, data); 7116 7117 if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) { 7118 /* Bounce to user space */ 7119 return X86EMUL_IO_NEEDED; 7120 } 7121 7122 return r; 7123 } 7124 7125 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 7126 { 7127 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7128 7129 return vcpu->arch.smbase; 7130 } 7131 7132 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 7133 { 7134 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7135 7136 vcpu->arch.smbase = smbase; 7137 } 7138 7139 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 7140 u32 pmc) 7141 { 7142 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); 7143 } 7144 7145 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 7146 u32 pmc, u64 *pdata) 7147 { 7148 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 7149 } 7150 7151 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 7152 { 7153 emul_to_vcpu(ctxt)->arch.halt_request = 1; 7154 } 7155 7156 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 7157 struct x86_instruction_info *info, 7158 enum x86_intercept_stage stage) 7159 { 7160 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, 7161 &ctxt->exception); 7162 } 7163 7164 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 7165 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, 7166 bool exact_only) 7167 { 7168 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); 7169 } 7170 7171 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) 7172 { 7173 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); 7174 } 7175 7176 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) 7177 { 7178 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); 7179 } 7180 7181 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) 7182 { 7183 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); 7184 } 7185 7186 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 7187 { 7188 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); 7189 } 7190 7191 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 7192 { 7193 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); 7194 } 7195 7196 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 7197 { 7198 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); 7199 } 7200 7201 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 7202 { 7203 return emul_to_vcpu(ctxt)->arch.hflags; 7204 } 7205 7206 static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt) 7207 { 7208 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7209 7210 kvm_smm_changed(vcpu, false); 7211 } 7212 7213 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt, 7214 const char *smstate) 7215 { 7216 return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate); 7217 } 7218 7219 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) 7220 { 7221 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); 7222 } 7223 7224 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) 7225 { 7226 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); 7227 } 7228 7229 static const struct x86_emulate_ops emulate_ops = { 7230 .read_gpr = emulator_read_gpr, 7231 .write_gpr = emulator_write_gpr, 7232 .read_std = emulator_read_std, 7233 .write_std = emulator_write_std, 7234 .read_phys = kvm_read_guest_phys_system, 7235 .fetch = kvm_fetch_guest_virt, 7236 .read_emulated = emulator_read_emulated, 7237 .write_emulated = emulator_write_emulated, 7238 .cmpxchg_emulated = emulator_cmpxchg_emulated, 7239 .invlpg = emulator_invlpg, 7240 .pio_in_emulated = emulator_pio_in_emulated, 7241 .pio_out_emulated = emulator_pio_out_emulated, 7242 .get_segment = emulator_get_segment, 7243 .set_segment = emulator_set_segment, 7244 .get_cached_segment_base = emulator_get_cached_segment_base, 7245 .get_gdt = emulator_get_gdt, 7246 .get_idt = emulator_get_idt, 7247 .set_gdt = emulator_set_gdt, 7248 .set_idt = emulator_set_idt, 7249 .get_cr = emulator_get_cr, 7250 .set_cr = emulator_set_cr, 7251 .cpl = emulator_get_cpl, 7252 .get_dr = emulator_get_dr, 7253 .set_dr = emulator_set_dr, 7254 .get_smbase = emulator_get_smbase, 7255 .set_smbase = emulator_set_smbase, 7256 .set_msr = emulator_set_msr, 7257 .get_msr = emulator_get_msr, 7258 .check_pmc = emulator_check_pmc, 7259 .read_pmc = emulator_read_pmc, 7260 .halt = emulator_halt, 7261 .wbinvd = emulator_wbinvd, 7262 .fix_hypercall = emulator_fix_hypercall, 7263 .intercept = emulator_intercept, 7264 .get_cpuid = emulator_get_cpuid, 7265 .guest_has_long_mode = emulator_guest_has_long_mode, 7266 .guest_has_movbe = emulator_guest_has_movbe, 7267 .guest_has_fxsr = emulator_guest_has_fxsr, 7268 .set_nmi_mask = emulator_set_nmi_mask, 7269 .get_hflags = emulator_get_hflags, 7270 .exiting_smm = emulator_exiting_smm, 7271 .leave_smm = emulator_leave_smm, 7272 .triple_fault = emulator_triple_fault, 7273 .set_xcr = emulator_set_xcr, 7274 }; 7275 7276 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 7277 { 7278 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 7279 /* 7280 * an sti; sti; sequence only disable interrupts for the first 7281 * instruction. So, if the last instruction, be it emulated or 7282 * not, left the system with the INT_STI flag enabled, it 7283 * means that the last instruction is an sti. We should not 7284 * leave the flag on in this case. The same goes for mov ss 7285 */ 7286 if (int_shadow & mask) 7287 mask = 0; 7288 if (unlikely(int_shadow || mask)) { 7289 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); 7290 if (!mask) 7291 kvm_make_request(KVM_REQ_EVENT, vcpu); 7292 } 7293 } 7294 7295 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 7296 { 7297 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7298 if (ctxt->exception.vector == PF_VECTOR) 7299 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); 7300 7301 if (ctxt->exception.error_code_valid) 7302 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 7303 ctxt->exception.error_code); 7304 else 7305 kvm_queue_exception(vcpu, ctxt->exception.vector); 7306 return false; 7307 } 7308 7309 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) 7310 { 7311 struct x86_emulate_ctxt *ctxt; 7312 7313 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); 7314 if (!ctxt) { 7315 pr_err("kvm: failed to allocate vcpu's emulator\n"); 7316 return NULL; 7317 } 7318 7319 ctxt->vcpu = vcpu; 7320 ctxt->ops = &emulate_ops; 7321 vcpu->arch.emulate_ctxt = ctxt; 7322 7323 return ctxt; 7324 } 7325 7326 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 7327 { 7328 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7329 int cs_db, cs_l; 7330 7331 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 7332 7333 ctxt->gpa_available = false; 7334 ctxt->eflags = kvm_get_rflags(vcpu); 7335 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 7336 7337 ctxt->eip = kvm_rip_read(vcpu); 7338 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 7339 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 7340 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 7341 cs_db ? X86EMUL_MODE_PROT32 : 7342 X86EMUL_MODE_PROT16; 7343 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 7344 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 7345 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 7346 7347 ctxt->interruptibility = 0; 7348 ctxt->have_exception = false; 7349 ctxt->exception.vector = -1; 7350 ctxt->perm_ok = false; 7351 7352 init_decode_cache(ctxt); 7353 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 7354 } 7355 7356 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 7357 { 7358 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7359 int ret; 7360 7361 init_emulate_ctxt(vcpu); 7362 7363 ctxt->op_bytes = 2; 7364 ctxt->ad_bytes = 2; 7365 ctxt->_eip = ctxt->eip + inc_eip; 7366 ret = emulate_int_real(ctxt, irq); 7367 7368 if (ret != X86EMUL_CONTINUE) { 7369 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 7370 } else { 7371 ctxt->eip = ctxt->_eip; 7372 kvm_rip_write(vcpu, ctxt->eip); 7373 kvm_set_rflags(vcpu, ctxt->eflags); 7374 } 7375 } 7376 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 7377 7378 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu) 7379 { 7380 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7381 u32 insn_size = ctxt->fetch.end - ctxt->fetch.data; 7382 struct kvm_run *run = vcpu->run; 7383 7384 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 7385 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION; 7386 run->emulation_failure.ndata = 0; 7387 run->emulation_failure.flags = 0; 7388 7389 if (insn_size) { 7390 run->emulation_failure.ndata = 3; 7391 run->emulation_failure.flags |= 7392 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES; 7393 run->emulation_failure.insn_size = insn_size; 7394 memset(run->emulation_failure.insn_bytes, 0x90, 7395 sizeof(run->emulation_failure.insn_bytes)); 7396 memcpy(run->emulation_failure.insn_bytes, 7397 ctxt->fetch.data, insn_size); 7398 } 7399 } 7400 7401 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 7402 { 7403 struct kvm *kvm = vcpu->kvm; 7404 7405 ++vcpu->stat.insn_emulation_fail; 7406 trace_kvm_emulate_insn_failed(vcpu); 7407 7408 if (emulation_type & EMULTYPE_VMWARE_GP) { 7409 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 7410 return 1; 7411 } 7412 7413 if (kvm->arch.exit_on_emulation_error || 7414 (emulation_type & EMULTYPE_SKIP)) { 7415 prepare_emulation_failure_exit(vcpu); 7416 return 0; 7417 } 7418 7419 kvm_queue_exception(vcpu, UD_VECTOR); 7420 7421 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { 7422 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 7423 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 7424 vcpu->run->internal.ndata = 0; 7425 return 0; 7426 } 7427 7428 return 1; 7429 } 7430 7431 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 7432 bool write_fault_to_shadow_pgtable, 7433 int emulation_type) 7434 { 7435 gpa_t gpa = cr2_or_gpa; 7436 kvm_pfn_t pfn; 7437 7438 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7439 return false; 7440 7441 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7442 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7443 return false; 7444 7445 if (!vcpu->arch.mmu->direct_map) { 7446 /* 7447 * Write permission should be allowed since only 7448 * write access need to be emulated. 7449 */ 7450 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 7451 7452 /* 7453 * If the mapping is invalid in guest, let cpu retry 7454 * it to generate fault. 7455 */ 7456 if (gpa == UNMAPPED_GVA) 7457 return true; 7458 } 7459 7460 /* 7461 * Do not retry the unhandleable instruction if it faults on the 7462 * readonly host memory, otherwise it will goto a infinite loop: 7463 * retry instruction -> write #PF -> emulation fail -> retry 7464 * instruction -> ... 7465 */ 7466 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 7467 7468 /* 7469 * If the instruction failed on the error pfn, it can not be fixed, 7470 * report the error to userspace. 7471 */ 7472 if (is_error_noslot_pfn(pfn)) 7473 return false; 7474 7475 kvm_release_pfn_clean(pfn); 7476 7477 /* The instructions are well-emulated on direct mmu. */ 7478 if (vcpu->arch.mmu->direct_map) { 7479 unsigned int indirect_shadow_pages; 7480 7481 write_lock(&vcpu->kvm->mmu_lock); 7482 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 7483 write_unlock(&vcpu->kvm->mmu_lock); 7484 7485 if (indirect_shadow_pages) 7486 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7487 7488 return true; 7489 } 7490 7491 /* 7492 * if emulation was due to access to shadowed page table 7493 * and it failed try to unshadow page and re-enter the 7494 * guest to let CPU execute the instruction. 7495 */ 7496 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7497 7498 /* 7499 * If the access faults on its page table, it can not 7500 * be fixed by unprotecting shadow page and it should 7501 * be reported to userspace. 7502 */ 7503 return !write_fault_to_shadow_pgtable; 7504 } 7505 7506 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 7507 gpa_t cr2_or_gpa, int emulation_type) 7508 { 7509 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7510 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; 7511 7512 last_retry_eip = vcpu->arch.last_retry_eip; 7513 last_retry_addr = vcpu->arch.last_retry_addr; 7514 7515 /* 7516 * If the emulation is caused by #PF and it is non-page_table 7517 * writing instruction, it means the VM-EXIT is caused by shadow 7518 * page protected, we can zap the shadow page and retry this 7519 * instruction directly. 7520 * 7521 * Note: if the guest uses a non-page-table modifying instruction 7522 * on the PDE that points to the instruction, then we will unmap 7523 * the instruction and go to an infinite loop. So, we cache the 7524 * last retried eip and the last fault address, if we meet the eip 7525 * and the address again, we can break out of the potential infinite 7526 * loop. 7527 */ 7528 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 7529 7530 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7531 return false; 7532 7533 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7534 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7535 return false; 7536 7537 if (x86_page_table_writing_insn(ctxt)) 7538 return false; 7539 7540 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) 7541 return false; 7542 7543 vcpu->arch.last_retry_eip = ctxt->eip; 7544 vcpu->arch.last_retry_addr = cr2_or_gpa; 7545 7546 if (!vcpu->arch.mmu->direct_map) 7547 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 7548 7549 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7550 7551 return true; 7552 } 7553 7554 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 7555 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 7556 7557 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm) 7558 { 7559 trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm); 7560 7561 if (entering_smm) { 7562 vcpu->arch.hflags |= HF_SMM_MASK; 7563 } else { 7564 vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK); 7565 7566 /* Process a latched INIT or SMI, if any. */ 7567 kvm_make_request(KVM_REQ_EVENT, vcpu); 7568 7569 /* 7570 * Even if KVM_SET_SREGS2 loaded PDPTRs out of band, 7571 * on SMM exit we still need to reload them from 7572 * guest memory 7573 */ 7574 vcpu->arch.pdptrs_from_userspace = false; 7575 } 7576 7577 kvm_mmu_reset_context(vcpu); 7578 } 7579 7580 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 7581 unsigned long *db) 7582 { 7583 u32 dr6 = 0; 7584 int i; 7585 u32 enable, rwlen; 7586 7587 enable = dr7; 7588 rwlen = dr7 >> 16; 7589 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 7590 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 7591 dr6 |= (1 << i); 7592 return dr6; 7593 } 7594 7595 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) 7596 { 7597 struct kvm_run *kvm_run = vcpu->run; 7598 7599 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 7600 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; 7601 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); 7602 kvm_run->debug.arch.exception = DB_VECTOR; 7603 kvm_run->exit_reason = KVM_EXIT_DEBUG; 7604 return 0; 7605 } 7606 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 7607 return 1; 7608 } 7609 7610 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 7611 { 7612 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 7613 int r; 7614 7615 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); 7616 if (unlikely(!r)) 7617 return 0; 7618 7619 /* 7620 * rflags is the old, "raw" value of the flags. The new value has 7621 * not been saved yet. 7622 * 7623 * This is correct even for TF set by the guest, because "the 7624 * processor will not generate this exception after the instruction 7625 * that sets the TF flag". 7626 */ 7627 if (unlikely(rflags & X86_EFLAGS_TF)) 7628 r = kvm_vcpu_do_singlestep(vcpu); 7629 return r; 7630 } 7631 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 7632 7633 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 7634 { 7635 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 7636 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 7637 struct kvm_run *kvm_run = vcpu->run; 7638 unsigned long eip = kvm_get_linear_rip(vcpu); 7639 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 7640 vcpu->arch.guest_debug_dr7, 7641 vcpu->arch.eff_db); 7642 7643 if (dr6 != 0) { 7644 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; 7645 kvm_run->debug.arch.pc = eip; 7646 kvm_run->debug.arch.exception = DB_VECTOR; 7647 kvm_run->exit_reason = KVM_EXIT_DEBUG; 7648 *r = 0; 7649 return true; 7650 } 7651 } 7652 7653 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 7654 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 7655 unsigned long eip = kvm_get_linear_rip(vcpu); 7656 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 7657 vcpu->arch.dr7, 7658 vcpu->arch.db); 7659 7660 if (dr6 != 0) { 7661 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); 7662 *r = 1; 7663 return true; 7664 } 7665 } 7666 7667 return false; 7668 } 7669 7670 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 7671 { 7672 switch (ctxt->opcode_len) { 7673 case 1: 7674 switch (ctxt->b) { 7675 case 0xe4: /* IN */ 7676 case 0xe5: 7677 case 0xec: 7678 case 0xed: 7679 case 0xe6: /* OUT */ 7680 case 0xe7: 7681 case 0xee: 7682 case 0xef: 7683 case 0x6c: /* INS */ 7684 case 0x6d: 7685 case 0x6e: /* OUTS */ 7686 case 0x6f: 7687 return true; 7688 } 7689 break; 7690 case 2: 7691 switch (ctxt->b) { 7692 case 0x33: /* RDPMC */ 7693 return true; 7694 } 7695 break; 7696 } 7697 7698 return false; 7699 } 7700 7701 /* 7702 * Decode to be emulated instruction. Return EMULATION_OK if success. 7703 */ 7704 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 7705 void *insn, int insn_len) 7706 { 7707 int r = EMULATION_OK; 7708 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7709 7710 init_emulate_ctxt(vcpu); 7711 7712 /* 7713 * We will reenter on the same instruction since we do not set 7714 * complete_userspace_io. This does not handle watchpoints yet, 7715 * those would be handled in the emulate_ops. 7716 */ 7717 if (!(emulation_type & EMULTYPE_SKIP) && 7718 kvm_vcpu_check_breakpoint(vcpu, &r)) 7719 return r; 7720 7721 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); 7722 7723 trace_kvm_emulate_insn_start(vcpu); 7724 ++vcpu->stat.insn_emulation; 7725 7726 return r; 7727 } 7728 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); 7729 7730 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 7731 int emulation_type, void *insn, int insn_len) 7732 { 7733 int r; 7734 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7735 bool writeback = true; 7736 bool write_fault_to_spt; 7737 7738 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, insn, insn_len))) 7739 return 1; 7740 7741 vcpu->arch.l1tf_flush_l1d = true; 7742 7743 /* 7744 * Clear write_fault_to_shadow_pgtable here to ensure it is 7745 * never reused. 7746 */ 7747 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 7748 vcpu->arch.write_fault_to_shadow_pgtable = false; 7749 7750 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 7751 kvm_clear_exception_queue(vcpu); 7752 7753 r = x86_decode_emulated_instruction(vcpu, emulation_type, 7754 insn, insn_len); 7755 if (r != EMULATION_OK) { 7756 if ((emulation_type & EMULTYPE_TRAP_UD) || 7757 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { 7758 kvm_queue_exception(vcpu, UD_VECTOR); 7759 return 1; 7760 } 7761 if (reexecute_instruction(vcpu, cr2_or_gpa, 7762 write_fault_to_spt, 7763 emulation_type)) 7764 return 1; 7765 if (ctxt->have_exception) { 7766 /* 7767 * #UD should result in just EMULATION_FAILED, and trap-like 7768 * exception should not be encountered during decode. 7769 */ 7770 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || 7771 exception_type(ctxt->exception.vector) == EXCPT_TRAP); 7772 inject_emulated_exception(vcpu); 7773 return 1; 7774 } 7775 return handle_emulation_failure(vcpu, emulation_type); 7776 } 7777 } 7778 7779 if ((emulation_type & EMULTYPE_VMWARE_GP) && 7780 !is_vmware_backdoor_opcode(ctxt)) { 7781 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 7782 return 1; 7783 } 7784 7785 /* 7786 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks 7787 * for kvm_skip_emulated_instruction(). The caller is responsible for 7788 * updating interruptibility state and injecting single-step #DBs. 7789 */ 7790 if (emulation_type & EMULTYPE_SKIP) { 7791 kvm_rip_write(vcpu, ctxt->_eip); 7792 if (ctxt->eflags & X86_EFLAGS_RF) 7793 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 7794 return 1; 7795 } 7796 7797 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) 7798 return 1; 7799 7800 /* this is needed for vmware backdoor interface to work since it 7801 changes registers values during IO operation */ 7802 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 7803 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 7804 emulator_invalidate_register_cache(ctxt); 7805 } 7806 7807 restart: 7808 if (emulation_type & EMULTYPE_PF) { 7809 /* Save the faulting GPA (cr2) in the address field */ 7810 ctxt->exception.address = cr2_or_gpa; 7811 7812 /* With shadow page tables, cr2 contains a GVA or nGPA. */ 7813 if (vcpu->arch.mmu->direct_map) { 7814 ctxt->gpa_available = true; 7815 ctxt->gpa_val = cr2_or_gpa; 7816 } 7817 } else { 7818 /* Sanitize the address out of an abundance of paranoia. */ 7819 ctxt->exception.address = 0; 7820 } 7821 7822 r = x86_emulate_insn(ctxt); 7823 7824 if (r == EMULATION_INTERCEPTED) 7825 return 1; 7826 7827 if (r == EMULATION_FAILED) { 7828 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, 7829 emulation_type)) 7830 return 1; 7831 7832 return handle_emulation_failure(vcpu, emulation_type); 7833 } 7834 7835 if (ctxt->have_exception) { 7836 r = 1; 7837 if (inject_emulated_exception(vcpu)) 7838 return r; 7839 } else if (vcpu->arch.pio.count) { 7840 if (!vcpu->arch.pio.in) { 7841 /* FIXME: return into emulator if single-stepping. */ 7842 vcpu->arch.pio.count = 0; 7843 } else { 7844 writeback = false; 7845 vcpu->arch.complete_userspace_io = complete_emulated_pio; 7846 } 7847 r = 0; 7848 } else if (vcpu->mmio_needed) { 7849 ++vcpu->stat.mmio_exits; 7850 7851 if (!vcpu->mmio_is_write) 7852 writeback = false; 7853 r = 0; 7854 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 7855 } else if (r == EMULATION_RESTART) 7856 goto restart; 7857 else 7858 r = 1; 7859 7860 if (writeback) { 7861 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 7862 toggle_interruptibility(vcpu, ctxt->interruptibility); 7863 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7864 if (!ctxt->have_exception || 7865 exception_type(ctxt->exception.vector) == EXCPT_TRAP) { 7866 kvm_rip_write(vcpu, ctxt->eip); 7867 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 7868 r = kvm_vcpu_do_singlestep(vcpu); 7869 if (kvm_x86_ops.update_emulated_instruction) 7870 static_call(kvm_x86_update_emulated_instruction)(vcpu); 7871 __kvm_set_rflags(vcpu, ctxt->eflags); 7872 } 7873 7874 /* 7875 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 7876 * do nothing, and it will be requested again as soon as 7877 * the shadow expires. But we still need to check here, 7878 * because POPF has no interrupt shadow. 7879 */ 7880 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 7881 kvm_make_request(KVM_REQ_EVENT, vcpu); 7882 } else 7883 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 7884 7885 return r; 7886 } 7887 7888 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 7889 { 7890 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 7891 } 7892 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 7893 7894 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 7895 void *insn, int insn_len) 7896 { 7897 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 7898 } 7899 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 7900 7901 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 7902 { 7903 vcpu->arch.pio.count = 0; 7904 return 1; 7905 } 7906 7907 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 7908 { 7909 vcpu->arch.pio.count = 0; 7910 7911 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 7912 return 1; 7913 7914 return kvm_skip_emulated_instruction(vcpu); 7915 } 7916 7917 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 7918 unsigned short port) 7919 { 7920 unsigned long val = kvm_rax_read(vcpu); 7921 int ret = emulator_pio_out(vcpu, size, port, &val, 1); 7922 7923 if (ret) 7924 return ret; 7925 7926 /* 7927 * Workaround userspace that relies on old KVM behavior of %rip being 7928 * incremented prior to exiting to userspace to handle "OUT 0x7e". 7929 */ 7930 if (port == 0x7e && 7931 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 7932 vcpu->arch.complete_userspace_io = 7933 complete_fast_pio_out_port_0x7e; 7934 kvm_skip_emulated_instruction(vcpu); 7935 } else { 7936 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 7937 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 7938 } 7939 return 0; 7940 } 7941 7942 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 7943 { 7944 unsigned long val; 7945 7946 /* We should only ever be called with arch.pio.count equal to 1 */ 7947 BUG_ON(vcpu->arch.pio.count != 1); 7948 7949 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 7950 vcpu->arch.pio.count = 0; 7951 return 1; 7952 } 7953 7954 /* For size less than 4 we merge, else we zero extend */ 7955 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 7956 7957 /* 7958 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform 7959 * the copy and tracing 7960 */ 7961 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); 7962 kvm_rax_write(vcpu, val); 7963 7964 return kvm_skip_emulated_instruction(vcpu); 7965 } 7966 7967 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 7968 unsigned short port) 7969 { 7970 unsigned long val; 7971 int ret; 7972 7973 /* For size less than 4 we merge, else we zero extend */ 7974 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 7975 7976 ret = emulator_pio_in(vcpu, size, port, &val, 1); 7977 if (ret) { 7978 kvm_rax_write(vcpu, val); 7979 return ret; 7980 } 7981 7982 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 7983 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 7984 7985 return 0; 7986 } 7987 7988 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 7989 { 7990 int ret; 7991 7992 if (in) 7993 ret = kvm_fast_pio_in(vcpu, size, port); 7994 else 7995 ret = kvm_fast_pio_out(vcpu, size, port); 7996 return ret && kvm_skip_emulated_instruction(vcpu); 7997 } 7998 EXPORT_SYMBOL_GPL(kvm_fast_pio); 7999 8000 static int kvmclock_cpu_down_prep(unsigned int cpu) 8001 { 8002 __this_cpu_write(cpu_tsc_khz, 0); 8003 return 0; 8004 } 8005 8006 static void tsc_khz_changed(void *data) 8007 { 8008 struct cpufreq_freqs *freq = data; 8009 unsigned long khz = 0; 8010 8011 if (data) 8012 khz = freq->new; 8013 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 8014 khz = cpufreq_quick_get(raw_smp_processor_id()); 8015 if (!khz) 8016 khz = tsc_khz; 8017 __this_cpu_write(cpu_tsc_khz, khz); 8018 } 8019 8020 #ifdef CONFIG_X86_64 8021 static void kvm_hyperv_tsc_notifier(void) 8022 { 8023 struct kvm *kvm; 8024 struct kvm_vcpu *vcpu; 8025 int cpu; 8026 unsigned long flags; 8027 8028 mutex_lock(&kvm_lock); 8029 list_for_each_entry(kvm, &vm_list, vm_list) 8030 kvm_make_mclock_inprogress_request(kvm); 8031 8032 hyperv_stop_tsc_emulation(); 8033 8034 /* TSC frequency always matches when on Hyper-V */ 8035 for_each_present_cpu(cpu) 8036 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 8037 kvm_max_guest_tsc_khz = tsc_khz; 8038 8039 list_for_each_entry(kvm, &vm_list, vm_list) { 8040 struct kvm_arch *ka = &kvm->arch; 8041 8042 raw_spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 8043 pvclock_update_vm_gtod_copy(kvm); 8044 raw_spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 8045 8046 kvm_for_each_vcpu(cpu, vcpu, kvm) 8047 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 8048 8049 kvm_for_each_vcpu(cpu, vcpu, kvm) 8050 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 8051 } 8052 mutex_unlock(&kvm_lock); 8053 } 8054 #endif 8055 8056 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 8057 { 8058 struct kvm *kvm; 8059 struct kvm_vcpu *vcpu; 8060 int i, send_ipi = 0; 8061 8062 /* 8063 * We allow guests to temporarily run on slowing clocks, 8064 * provided we notify them after, or to run on accelerating 8065 * clocks, provided we notify them before. Thus time never 8066 * goes backwards. 8067 * 8068 * However, we have a problem. We can't atomically update 8069 * the frequency of a given CPU from this function; it is 8070 * merely a notifier, which can be called from any CPU. 8071 * Changing the TSC frequency at arbitrary points in time 8072 * requires a recomputation of local variables related to 8073 * the TSC for each VCPU. We must flag these local variables 8074 * to be updated and be sure the update takes place with the 8075 * new frequency before any guests proceed. 8076 * 8077 * Unfortunately, the combination of hotplug CPU and frequency 8078 * change creates an intractable locking scenario; the order 8079 * of when these callouts happen is undefined with respect to 8080 * CPU hotplug, and they can race with each other. As such, 8081 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 8082 * undefined; you can actually have a CPU frequency change take 8083 * place in between the computation of X and the setting of the 8084 * variable. To protect against this problem, all updates of 8085 * the per_cpu tsc_khz variable are done in an interrupt 8086 * protected IPI, and all callers wishing to update the value 8087 * must wait for a synchronous IPI to complete (which is trivial 8088 * if the caller is on the CPU already). This establishes the 8089 * necessary total order on variable updates. 8090 * 8091 * Note that because a guest time update may take place 8092 * anytime after the setting of the VCPU's request bit, the 8093 * correct TSC value must be set before the request. However, 8094 * to ensure the update actually makes it to any guest which 8095 * starts running in hardware virtualization between the set 8096 * and the acquisition of the spinlock, we must also ping the 8097 * CPU after setting the request bit. 8098 * 8099 */ 8100 8101 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 8102 8103 mutex_lock(&kvm_lock); 8104 list_for_each_entry(kvm, &vm_list, vm_list) { 8105 kvm_for_each_vcpu(i, vcpu, kvm) { 8106 if (vcpu->cpu != cpu) 8107 continue; 8108 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 8109 if (vcpu->cpu != raw_smp_processor_id()) 8110 send_ipi = 1; 8111 } 8112 } 8113 mutex_unlock(&kvm_lock); 8114 8115 if (freq->old < freq->new && send_ipi) { 8116 /* 8117 * We upscale the frequency. Must make the guest 8118 * doesn't see old kvmclock values while running with 8119 * the new frequency, otherwise we risk the guest sees 8120 * time go backwards. 8121 * 8122 * In case we update the frequency for another cpu 8123 * (which might be in guest context) send an interrupt 8124 * to kick the cpu out of guest context. Next time 8125 * guest context is entered kvmclock will be updated, 8126 * so the guest will not see stale values. 8127 */ 8128 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 8129 } 8130 } 8131 8132 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 8133 void *data) 8134 { 8135 struct cpufreq_freqs *freq = data; 8136 int cpu; 8137 8138 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 8139 return 0; 8140 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 8141 return 0; 8142 8143 for_each_cpu(cpu, freq->policy->cpus) 8144 __kvmclock_cpufreq_notifier(freq, cpu); 8145 8146 return 0; 8147 } 8148 8149 static struct notifier_block kvmclock_cpufreq_notifier_block = { 8150 .notifier_call = kvmclock_cpufreq_notifier 8151 }; 8152 8153 static int kvmclock_cpu_online(unsigned int cpu) 8154 { 8155 tsc_khz_changed(NULL); 8156 return 0; 8157 } 8158 8159 static void kvm_timer_init(void) 8160 { 8161 max_tsc_khz = tsc_khz; 8162 8163 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 8164 #ifdef CONFIG_CPU_FREQ 8165 struct cpufreq_policy *policy; 8166 int cpu; 8167 8168 cpu = get_cpu(); 8169 policy = cpufreq_cpu_get(cpu); 8170 if (policy) { 8171 if (policy->cpuinfo.max_freq) 8172 max_tsc_khz = policy->cpuinfo.max_freq; 8173 cpufreq_cpu_put(policy); 8174 } 8175 put_cpu(); 8176 #endif 8177 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 8178 CPUFREQ_TRANSITION_NOTIFIER); 8179 } 8180 8181 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 8182 kvmclock_cpu_online, kvmclock_cpu_down_prep); 8183 } 8184 8185 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 8186 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); 8187 8188 int kvm_is_in_guest(void) 8189 { 8190 return __this_cpu_read(current_vcpu) != NULL; 8191 } 8192 8193 static int kvm_is_user_mode(void) 8194 { 8195 int user_mode = 3; 8196 8197 if (__this_cpu_read(current_vcpu)) 8198 user_mode = static_call(kvm_x86_get_cpl)(__this_cpu_read(current_vcpu)); 8199 8200 return user_mode != 0; 8201 } 8202 8203 static unsigned long kvm_get_guest_ip(void) 8204 { 8205 unsigned long ip = 0; 8206 8207 if (__this_cpu_read(current_vcpu)) 8208 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 8209 8210 return ip; 8211 } 8212 8213 static void kvm_handle_intel_pt_intr(void) 8214 { 8215 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); 8216 8217 kvm_make_request(KVM_REQ_PMI, vcpu); 8218 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, 8219 (unsigned long *)&vcpu->arch.pmu.global_status); 8220 } 8221 8222 static struct perf_guest_info_callbacks kvm_guest_cbs = { 8223 .is_in_guest = kvm_is_in_guest, 8224 .is_user_mode = kvm_is_user_mode, 8225 .get_guest_ip = kvm_get_guest_ip, 8226 .handle_intel_pt_intr = kvm_handle_intel_pt_intr, 8227 }; 8228 8229 #ifdef CONFIG_X86_64 8230 static void pvclock_gtod_update_fn(struct work_struct *work) 8231 { 8232 struct kvm *kvm; 8233 8234 struct kvm_vcpu *vcpu; 8235 int i; 8236 8237 mutex_lock(&kvm_lock); 8238 list_for_each_entry(kvm, &vm_list, vm_list) 8239 kvm_for_each_vcpu(i, vcpu, kvm) 8240 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 8241 atomic_set(&kvm_guest_has_master_clock, 0); 8242 mutex_unlock(&kvm_lock); 8243 } 8244 8245 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 8246 8247 /* 8248 * Indirection to move queue_work() out of the tk_core.seq write held 8249 * region to prevent possible deadlocks against time accessors which 8250 * are invoked with work related locks held. 8251 */ 8252 static void pvclock_irq_work_fn(struct irq_work *w) 8253 { 8254 queue_work(system_long_wq, &pvclock_gtod_work); 8255 } 8256 8257 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); 8258 8259 /* 8260 * Notification about pvclock gtod data update. 8261 */ 8262 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 8263 void *priv) 8264 { 8265 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 8266 struct timekeeper *tk = priv; 8267 8268 update_pvclock_gtod(tk); 8269 8270 /* 8271 * Disable master clock if host does not trust, or does not use, 8272 * TSC based clocksource. Delegate queue_work() to irq_work as 8273 * this is invoked with tk_core.seq write held. 8274 */ 8275 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 8276 atomic_read(&kvm_guest_has_master_clock) != 0) 8277 irq_work_queue(&pvclock_irq_work); 8278 return 0; 8279 } 8280 8281 static struct notifier_block pvclock_gtod_notifier = { 8282 .notifier_call = pvclock_gtod_notify, 8283 }; 8284 #endif 8285 8286 int kvm_arch_init(void *opaque) 8287 { 8288 struct kvm_x86_init_ops *ops = opaque; 8289 int r; 8290 8291 if (kvm_x86_ops.hardware_enable) { 8292 printk(KERN_ERR "kvm: already loaded the other module\n"); 8293 r = -EEXIST; 8294 goto out; 8295 } 8296 8297 if (!ops->cpu_has_kvm_support()) { 8298 pr_err_ratelimited("kvm: no hardware support\n"); 8299 r = -EOPNOTSUPP; 8300 goto out; 8301 } 8302 if (ops->disabled_by_bios()) { 8303 pr_err_ratelimited("kvm: disabled by bios\n"); 8304 r = -EOPNOTSUPP; 8305 goto out; 8306 } 8307 8308 /* 8309 * KVM explicitly assumes that the guest has an FPU and 8310 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 8311 * vCPU's FPU state as a fxregs_state struct. 8312 */ 8313 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 8314 printk(KERN_ERR "kvm: inadequate fpu\n"); 8315 r = -EOPNOTSUPP; 8316 goto out; 8317 } 8318 8319 r = -ENOMEM; 8320 8321 x86_emulator_cache = kvm_alloc_emulator_cache(); 8322 if (!x86_emulator_cache) { 8323 pr_err("kvm: failed to allocate cache for x86 emulator\n"); 8324 goto out; 8325 } 8326 8327 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); 8328 if (!user_return_msrs) { 8329 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); 8330 goto out_free_x86_emulator_cache; 8331 } 8332 kvm_nr_uret_msrs = 0; 8333 8334 r = kvm_mmu_module_init(); 8335 if (r) 8336 goto out_free_percpu; 8337 8338 kvm_timer_init(); 8339 8340 perf_register_guest_info_callbacks(&kvm_guest_cbs); 8341 8342 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 8343 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 8344 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; 8345 } 8346 8347 if (pi_inject_timer == -1) 8348 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); 8349 #ifdef CONFIG_X86_64 8350 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 8351 8352 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8353 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 8354 #endif 8355 8356 return 0; 8357 8358 out_free_percpu: 8359 free_percpu(user_return_msrs); 8360 out_free_x86_emulator_cache: 8361 kmem_cache_destroy(x86_emulator_cache); 8362 out: 8363 return r; 8364 } 8365 8366 void kvm_arch_exit(void) 8367 { 8368 #ifdef CONFIG_X86_64 8369 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8370 clear_hv_tscchange_cb(); 8371 #endif 8372 kvm_lapic_exit(); 8373 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 8374 8375 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 8376 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 8377 CPUFREQ_TRANSITION_NOTIFIER); 8378 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 8379 #ifdef CONFIG_X86_64 8380 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 8381 irq_work_sync(&pvclock_irq_work); 8382 cancel_work_sync(&pvclock_gtod_work); 8383 #endif 8384 kvm_x86_ops.hardware_enable = NULL; 8385 kvm_mmu_module_exit(); 8386 free_percpu(user_return_msrs); 8387 kmem_cache_destroy(x86_emulator_cache); 8388 #ifdef CONFIG_KVM_XEN 8389 static_key_deferred_flush(&kvm_xen_enabled); 8390 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); 8391 #endif 8392 } 8393 8394 static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason) 8395 { 8396 ++vcpu->stat.halt_exits; 8397 if (lapic_in_kernel(vcpu)) { 8398 vcpu->arch.mp_state = state; 8399 return 1; 8400 } else { 8401 vcpu->run->exit_reason = reason; 8402 return 0; 8403 } 8404 } 8405 8406 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 8407 { 8408 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); 8409 } 8410 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 8411 8412 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 8413 { 8414 int ret = kvm_skip_emulated_instruction(vcpu); 8415 /* 8416 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 8417 * KVM_EXIT_DEBUG here. 8418 */ 8419 return kvm_vcpu_halt(vcpu) && ret; 8420 } 8421 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 8422 8423 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) 8424 { 8425 int ret = kvm_skip_emulated_instruction(vcpu); 8426 8427 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret; 8428 } 8429 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); 8430 8431 #ifdef CONFIG_X86_64 8432 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 8433 unsigned long clock_type) 8434 { 8435 struct kvm_clock_pairing clock_pairing; 8436 struct timespec64 ts; 8437 u64 cycle; 8438 int ret; 8439 8440 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 8441 return -KVM_EOPNOTSUPP; 8442 8443 if (!kvm_get_walltime_and_clockread(&ts, &cycle)) 8444 return -KVM_EOPNOTSUPP; 8445 8446 clock_pairing.sec = ts.tv_sec; 8447 clock_pairing.nsec = ts.tv_nsec; 8448 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 8449 clock_pairing.flags = 0; 8450 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 8451 8452 ret = 0; 8453 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 8454 sizeof(struct kvm_clock_pairing))) 8455 ret = -KVM_EFAULT; 8456 8457 return ret; 8458 } 8459 #endif 8460 8461 /* 8462 * kvm_pv_kick_cpu_op: Kick a vcpu. 8463 * 8464 * @apicid - apicid of vcpu to be kicked. 8465 */ 8466 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 8467 { 8468 struct kvm_lapic_irq lapic_irq; 8469 8470 lapic_irq.shorthand = APIC_DEST_NOSHORT; 8471 lapic_irq.dest_mode = APIC_DEST_PHYSICAL; 8472 lapic_irq.level = 0; 8473 lapic_irq.dest_id = apicid; 8474 lapic_irq.msi_redir_hint = false; 8475 8476 lapic_irq.delivery_mode = APIC_DM_REMRD; 8477 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 8478 } 8479 8480 bool kvm_apicv_activated(struct kvm *kvm) 8481 { 8482 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); 8483 } 8484 EXPORT_SYMBOL_GPL(kvm_apicv_activated); 8485 8486 static void kvm_apicv_init(struct kvm *kvm) 8487 { 8488 mutex_init(&kvm->arch.apicv_update_lock); 8489 8490 if (enable_apicv) 8491 clear_bit(APICV_INHIBIT_REASON_DISABLE, 8492 &kvm->arch.apicv_inhibit_reasons); 8493 else 8494 set_bit(APICV_INHIBIT_REASON_DISABLE, 8495 &kvm->arch.apicv_inhibit_reasons); 8496 } 8497 8498 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) 8499 { 8500 struct kvm_vcpu *target = NULL; 8501 struct kvm_apic_map *map; 8502 8503 vcpu->stat.directed_yield_attempted++; 8504 8505 if (single_task_running()) 8506 goto no_yield; 8507 8508 rcu_read_lock(); 8509 map = rcu_dereference(vcpu->kvm->arch.apic_map); 8510 8511 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 8512 target = map->phys_map[dest_id]->vcpu; 8513 8514 rcu_read_unlock(); 8515 8516 if (!target || !READ_ONCE(target->ready)) 8517 goto no_yield; 8518 8519 /* Ignore requests to yield to self */ 8520 if (vcpu == target) 8521 goto no_yield; 8522 8523 if (kvm_vcpu_yield_to(target) <= 0) 8524 goto no_yield; 8525 8526 vcpu->stat.directed_yield_successful++; 8527 8528 no_yield: 8529 return; 8530 } 8531 8532 static int complete_hypercall_exit(struct kvm_vcpu *vcpu) 8533 { 8534 u64 ret = vcpu->run->hypercall.ret; 8535 8536 if (!is_64_bit_mode(vcpu)) 8537 ret = (u32)ret; 8538 kvm_rax_write(vcpu, ret); 8539 ++vcpu->stat.hypercalls; 8540 return kvm_skip_emulated_instruction(vcpu); 8541 } 8542 8543 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 8544 { 8545 unsigned long nr, a0, a1, a2, a3, ret; 8546 int op_64_bit; 8547 8548 if (kvm_xen_hypercall_enabled(vcpu->kvm)) 8549 return kvm_xen_hypercall(vcpu); 8550 8551 if (kvm_hv_hypercall_enabled(vcpu)) 8552 return kvm_hv_hypercall(vcpu); 8553 8554 nr = kvm_rax_read(vcpu); 8555 a0 = kvm_rbx_read(vcpu); 8556 a1 = kvm_rcx_read(vcpu); 8557 a2 = kvm_rdx_read(vcpu); 8558 a3 = kvm_rsi_read(vcpu); 8559 8560 trace_kvm_hypercall(nr, a0, a1, a2, a3); 8561 8562 op_64_bit = is_64_bit_mode(vcpu); 8563 if (!op_64_bit) { 8564 nr &= 0xFFFFFFFF; 8565 a0 &= 0xFFFFFFFF; 8566 a1 &= 0xFFFFFFFF; 8567 a2 &= 0xFFFFFFFF; 8568 a3 &= 0xFFFFFFFF; 8569 } 8570 8571 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { 8572 ret = -KVM_EPERM; 8573 goto out; 8574 } 8575 8576 ret = -KVM_ENOSYS; 8577 8578 switch (nr) { 8579 case KVM_HC_VAPIC_POLL_IRQ: 8580 ret = 0; 8581 break; 8582 case KVM_HC_KICK_CPU: 8583 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) 8584 break; 8585 8586 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 8587 kvm_sched_yield(vcpu, a1); 8588 ret = 0; 8589 break; 8590 #ifdef CONFIG_X86_64 8591 case KVM_HC_CLOCK_PAIRING: 8592 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 8593 break; 8594 #endif 8595 case KVM_HC_SEND_IPI: 8596 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) 8597 break; 8598 8599 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 8600 break; 8601 case KVM_HC_SCHED_YIELD: 8602 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) 8603 break; 8604 8605 kvm_sched_yield(vcpu, a0); 8606 ret = 0; 8607 break; 8608 case KVM_HC_MAP_GPA_RANGE: { 8609 u64 gpa = a0, npages = a1, attrs = a2; 8610 8611 ret = -KVM_ENOSYS; 8612 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE))) 8613 break; 8614 8615 if (!PAGE_ALIGNED(gpa) || !npages || 8616 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) { 8617 ret = -KVM_EINVAL; 8618 break; 8619 } 8620 8621 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL; 8622 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE; 8623 vcpu->run->hypercall.args[0] = gpa; 8624 vcpu->run->hypercall.args[1] = npages; 8625 vcpu->run->hypercall.args[2] = attrs; 8626 vcpu->run->hypercall.longmode = op_64_bit; 8627 vcpu->arch.complete_userspace_io = complete_hypercall_exit; 8628 return 0; 8629 } 8630 default: 8631 ret = -KVM_ENOSYS; 8632 break; 8633 } 8634 out: 8635 if (!op_64_bit) 8636 ret = (u32)ret; 8637 kvm_rax_write(vcpu, ret); 8638 8639 ++vcpu->stat.hypercalls; 8640 return kvm_skip_emulated_instruction(vcpu); 8641 } 8642 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 8643 8644 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 8645 { 8646 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8647 char instruction[3]; 8648 unsigned long rip = kvm_rip_read(vcpu); 8649 8650 static_call(kvm_x86_patch_hypercall)(vcpu, instruction); 8651 8652 return emulator_write_emulated(ctxt, rip, instruction, 3, 8653 &ctxt->exception); 8654 } 8655 8656 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 8657 { 8658 return vcpu->run->request_interrupt_window && 8659 likely(!pic_in_kernel(vcpu->kvm)); 8660 } 8661 8662 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 8663 { 8664 struct kvm_run *kvm_run = vcpu->run; 8665 8666 /* 8667 * if_flag is obsolete and useless, so do not bother 8668 * setting it for SEV-ES guests. Userspace can just 8669 * use kvm_run->ready_for_interrupt_injection. 8670 */ 8671 kvm_run->if_flag = !vcpu->arch.guest_state_protected 8672 && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 8673 8674 kvm_run->cr8 = kvm_get_cr8(vcpu); 8675 kvm_run->apic_base = kvm_get_apic_base(vcpu); 8676 8677 /* 8678 * The call to kvm_ready_for_interrupt_injection() may end up in 8679 * kvm_xen_has_interrupt() which may require the srcu lock to be 8680 * held, to protect against changes in the vcpu_info address. 8681 */ 8682 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 8683 kvm_run->ready_for_interrupt_injection = 8684 pic_in_kernel(vcpu->kvm) || 8685 kvm_vcpu_ready_for_interrupt_injection(vcpu); 8686 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 8687 8688 if (is_smm(vcpu)) 8689 kvm_run->flags |= KVM_RUN_X86_SMM; 8690 } 8691 8692 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 8693 { 8694 int max_irr, tpr; 8695 8696 if (!kvm_x86_ops.update_cr8_intercept) 8697 return; 8698 8699 if (!lapic_in_kernel(vcpu)) 8700 return; 8701 8702 if (vcpu->arch.apicv_active) 8703 return; 8704 8705 if (!vcpu->arch.apic->vapic_addr) 8706 max_irr = kvm_lapic_find_highest_irr(vcpu); 8707 else 8708 max_irr = -1; 8709 8710 if (max_irr != -1) 8711 max_irr >>= 4; 8712 8713 tpr = kvm_lapic_get_cr8(vcpu); 8714 8715 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); 8716 } 8717 8718 8719 int kvm_check_nested_events(struct kvm_vcpu *vcpu) 8720 { 8721 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 8722 kvm_x86_ops.nested_ops->triple_fault(vcpu); 8723 return 1; 8724 } 8725 8726 return kvm_x86_ops.nested_ops->check_events(vcpu); 8727 } 8728 8729 static void kvm_inject_exception(struct kvm_vcpu *vcpu) 8730 { 8731 if (vcpu->arch.exception.error_code && !is_protmode(vcpu)) 8732 vcpu->arch.exception.error_code = false; 8733 static_call(kvm_x86_queue_exception)(vcpu); 8734 } 8735 8736 static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) 8737 { 8738 int r; 8739 bool can_inject = true; 8740 8741 /* try to reinject previous events if any */ 8742 8743 if (vcpu->arch.exception.injected) { 8744 kvm_inject_exception(vcpu); 8745 can_inject = false; 8746 } 8747 /* 8748 * Do not inject an NMI or interrupt if there is a pending 8749 * exception. Exceptions and interrupts are recognized at 8750 * instruction boundaries, i.e. the start of an instruction. 8751 * Trap-like exceptions, e.g. #DB, have higher priority than 8752 * NMIs and interrupts, i.e. traps are recognized before an 8753 * NMI/interrupt that's pending on the same instruction. 8754 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 8755 * priority, but are only generated (pended) during instruction 8756 * execution, i.e. a pending fault-like exception means the 8757 * fault occurred on the *previous* instruction and must be 8758 * serviced prior to recognizing any new events in order to 8759 * fully complete the previous instruction. 8760 */ 8761 else if (!vcpu->arch.exception.pending) { 8762 if (vcpu->arch.nmi_injected) { 8763 static_call(kvm_x86_set_nmi)(vcpu); 8764 can_inject = false; 8765 } else if (vcpu->arch.interrupt.injected) { 8766 static_call(kvm_x86_set_irq)(vcpu); 8767 can_inject = false; 8768 } 8769 } 8770 8771 WARN_ON_ONCE(vcpu->arch.exception.injected && 8772 vcpu->arch.exception.pending); 8773 8774 /* 8775 * Call check_nested_events() even if we reinjected a previous event 8776 * in order for caller to determine if it should require immediate-exit 8777 * from L2 to L1 due to pending L1 events which require exit 8778 * from L2 to L1. 8779 */ 8780 if (is_guest_mode(vcpu)) { 8781 r = kvm_check_nested_events(vcpu); 8782 if (r < 0) 8783 goto out; 8784 } 8785 8786 /* try to inject new event if pending */ 8787 if (vcpu->arch.exception.pending) { 8788 trace_kvm_inj_exception(vcpu->arch.exception.nr, 8789 vcpu->arch.exception.has_error_code, 8790 vcpu->arch.exception.error_code); 8791 8792 vcpu->arch.exception.pending = false; 8793 vcpu->arch.exception.injected = true; 8794 8795 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 8796 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 8797 X86_EFLAGS_RF); 8798 8799 if (vcpu->arch.exception.nr == DB_VECTOR) { 8800 kvm_deliver_exception_payload(vcpu); 8801 if (vcpu->arch.dr7 & DR7_GD) { 8802 vcpu->arch.dr7 &= ~DR7_GD; 8803 kvm_update_dr7(vcpu); 8804 } 8805 } 8806 8807 kvm_inject_exception(vcpu); 8808 can_inject = false; 8809 } 8810 8811 /* Don't inject interrupts if the user asked to avoid doing so */ 8812 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) 8813 return 0; 8814 8815 /* 8816 * Finally, inject interrupt events. If an event cannot be injected 8817 * due to architectural conditions (e.g. IF=0) a window-open exit 8818 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending 8819 * and can architecturally be injected, but we cannot do it right now: 8820 * an interrupt could have arrived just now and we have to inject it 8821 * as a vmexit, or there could already an event in the queue, which is 8822 * indicated by can_inject. In that case we request an immediate exit 8823 * in order to make progress and get back here for another iteration. 8824 * The kvm_x86_ops hooks communicate this by returning -EBUSY. 8825 */ 8826 if (vcpu->arch.smi_pending) { 8827 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; 8828 if (r < 0) 8829 goto out; 8830 if (r) { 8831 vcpu->arch.smi_pending = false; 8832 ++vcpu->arch.smi_count; 8833 enter_smm(vcpu); 8834 can_inject = false; 8835 } else 8836 static_call(kvm_x86_enable_smi_window)(vcpu); 8837 } 8838 8839 if (vcpu->arch.nmi_pending) { 8840 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; 8841 if (r < 0) 8842 goto out; 8843 if (r) { 8844 --vcpu->arch.nmi_pending; 8845 vcpu->arch.nmi_injected = true; 8846 static_call(kvm_x86_set_nmi)(vcpu); 8847 can_inject = false; 8848 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); 8849 } 8850 if (vcpu->arch.nmi_pending) 8851 static_call(kvm_x86_enable_nmi_window)(vcpu); 8852 } 8853 8854 if (kvm_cpu_has_injectable_intr(vcpu)) { 8855 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; 8856 if (r < 0) 8857 goto out; 8858 if (r) { 8859 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); 8860 static_call(kvm_x86_set_irq)(vcpu); 8861 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); 8862 } 8863 if (kvm_cpu_has_injectable_intr(vcpu)) 8864 static_call(kvm_x86_enable_irq_window)(vcpu); 8865 } 8866 8867 if (is_guest_mode(vcpu) && 8868 kvm_x86_ops.nested_ops->hv_timer_pending && 8869 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 8870 *req_immediate_exit = true; 8871 8872 WARN_ON(vcpu->arch.exception.pending); 8873 return 0; 8874 8875 out: 8876 if (r == -EBUSY) { 8877 *req_immediate_exit = true; 8878 r = 0; 8879 } 8880 return r; 8881 } 8882 8883 static void process_nmi(struct kvm_vcpu *vcpu) 8884 { 8885 unsigned limit = 2; 8886 8887 /* 8888 * x86 is limited to one NMI running, and one NMI pending after it. 8889 * If an NMI is already in progress, limit further NMIs to just one. 8890 * Otherwise, allow two (and we'll inject the first one immediately). 8891 */ 8892 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) 8893 limit = 1; 8894 8895 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 8896 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 8897 kvm_make_request(KVM_REQ_EVENT, vcpu); 8898 } 8899 8900 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 8901 { 8902 u32 flags = 0; 8903 flags |= seg->g << 23; 8904 flags |= seg->db << 22; 8905 flags |= seg->l << 21; 8906 flags |= seg->avl << 20; 8907 flags |= seg->present << 15; 8908 flags |= seg->dpl << 13; 8909 flags |= seg->s << 12; 8910 flags |= seg->type << 8; 8911 return flags; 8912 } 8913 8914 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 8915 { 8916 struct kvm_segment seg; 8917 int offset; 8918 8919 kvm_get_segment(vcpu, &seg, n); 8920 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 8921 8922 if (n < 3) 8923 offset = 0x7f84 + n * 12; 8924 else 8925 offset = 0x7f2c + (n - 3) * 12; 8926 8927 put_smstate(u32, buf, offset + 8, seg.base); 8928 put_smstate(u32, buf, offset + 4, seg.limit); 8929 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 8930 } 8931 8932 #ifdef CONFIG_X86_64 8933 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 8934 { 8935 struct kvm_segment seg; 8936 int offset; 8937 u16 flags; 8938 8939 kvm_get_segment(vcpu, &seg, n); 8940 offset = 0x7e00 + n * 16; 8941 8942 flags = enter_smm_get_segment_flags(&seg) >> 8; 8943 put_smstate(u16, buf, offset, seg.selector); 8944 put_smstate(u16, buf, offset + 2, flags); 8945 put_smstate(u32, buf, offset + 4, seg.limit); 8946 put_smstate(u64, buf, offset + 8, seg.base); 8947 } 8948 #endif 8949 8950 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 8951 { 8952 struct desc_ptr dt; 8953 struct kvm_segment seg; 8954 unsigned long val; 8955 int i; 8956 8957 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 8958 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 8959 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 8960 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 8961 8962 for (i = 0; i < 8; i++) 8963 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i)); 8964 8965 kvm_get_dr(vcpu, 6, &val); 8966 put_smstate(u32, buf, 0x7fcc, (u32)val); 8967 kvm_get_dr(vcpu, 7, &val); 8968 put_smstate(u32, buf, 0x7fc8, (u32)val); 8969 8970 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 8971 put_smstate(u32, buf, 0x7fc4, seg.selector); 8972 put_smstate(u32, buf, 0x7f64, seg.base); 8973 put_smstate(u32, buf, 0x7f60, seg.limit); 8974 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 8975 8976 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 8977 put_smstate(u32, buf, 0x7fc0, seg.selector); 8978 put_smstate(u32, buf, 0x7f80, seg.base); 8979 put_smstate(u32, buf, 0x7f7c, seg.limit); 8980 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 8981 8982 static_call(kvm_x86_get_gdt)(vcpu, &dt); 8983 put_smstate(u32, buf, 0x7f74, dt.address); 8984 put_smstate(u32, buf, 0x7f70, dt.size); 8985 8986 static_call(kvm_x86_get_idt)(vcpu, &dt); 8987 put_smstate(u32, buf, 0x7f58, dt.address); 8988 put_smstate(u32, buf, 0x7f54, dt.size); 8989 8990 for (i = 0; i < 6; i++) 8991 enter_smm_save_seg_32(vcpu, buf, i); 8992 8993 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 8994 8995 /* revision id */ 8996 put_smstate(u32, buf, 0x7efc, 0x00020000); 8997 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 8998 } 8999 9000 #ifdef CONFIG_X86_64 9001 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 9002 { 9003 struct desc_ptr dt; 9004 struct kvm_segment seg; 9005 unsigned long val; 9006 int i; 9007 9008 for (i = 0; i < 16; i++) 9009 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i)); 9010 9011 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 9012 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 9013 9014 kvm_get_dr(vcpu, 6, &val); 9015 put_smstate(u64, buf, 0x7f68, val); 9016 kvm_get_dr(vcpu, 7, &val); 9017 put_smstate(u64, buf, 0x7f60, val); 9018 9019 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 9020 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 9021 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 9022 9023 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 9024 9025 /* revision id */ 9026 put_smstate(u32, buf, 0x7efc, 0x00020064); 9027 9028 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 9029 9030 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 9031 put_smstate(u16, buf, 0x7e90, seg.selector); 9032 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 9033 put_smstate(u32, buf, 0x7e94, seg.limit); 9034 put_smstate(u64, buf, 0x7e98, seg.base); 9035 9036 static_call(kvm_x86_get_idt)(vcpu, &dt); 9037 put_smstate(u32, buf, 0x7e84, dt.size); 9038 put_smstate(u64, buf, 0x7e88, dt.address); 9039 9040 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 9041 put_smstate(u16, buf, 0x7e70, seg.selector); 9042 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 9043 put_smstate(u32, buf, 0x7e74, seg.limit); 9044 put_smstate(u64, buf, 0x7e78, seg.base); 9045 9046 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9047 put_smstate(u32, buf, 0x7e64, dt.size); 9048 put_smstate(u64, buf, 0x7e68, dt.address); 9049 9050 for (i = 0; i < 6; i++) 9051 enter_smm_save_seg_64(vcpu, buf, i); 9052 } 9053 #endif 9054 9055 static void enter_smm(struct kvm_vcpu *vcpu) 9056 { 9057 struct kvm_segment cs, ds; 9058 struct desc_ptr dt; 9059 unsigned long cr0; 9060 char buf[512]; 9061 9062 memset(buf, 0, 512); 9063 #ifdef CONFIG_X86_64 9064 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 9065 enter_smm_save_state_64(vcpu, buf); 9066 else 9067 #endif 9068 enter_smm_save_state_32(vcpu, buf); 9069 9070 /* 9071 * Give enter_smm() a chance to make ISA-specific changes to the vCPU 9072 * state (e.g. leave guest mode) after we've saved the state into the 9073 * SMM state-save area. 9074 */ 9075 static_call(kvm_x86_enter_smm)(vcpu, buf); 9076 9077 kvm_smm_changed(vcpu, true); 9078 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 9079 9080 if (static_call(kvm_x86_get_nmi_mask)(vcpu)) 9081 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 9082 else 9083 static_call(kvm_x86_set_nmi_mask)(vcpu, true); 9084 9085 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 9086 kvm_rip_write(vcpu, 0x8000); 9087 9088 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 9089 static_call(kvm_x86_set_cr0)(vcpu, cr0); 9090 vcpu->arch.cr0 = cr0; 9091 9092 static_call(kvm_x86_set_cr4)(vcpu, 0); 9093 9094 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 9095 dt.address = dt.size = 0; 9096 static_call(kvm_x86_set_idt)(vcpu, &dt); 9097 9098 kvm_set_dr(vcpu, 7, DR7_FIXED_1); 9099 9100 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 9101 cs.base = vcpu->arch.smbase; 9102 9103 ds.selector = 0; 9104 ds.base = 0; 9105 9106 cs.limit = ds.limit = 0xffffffff; 9107 cs.type = ds.type = 0x3; 9108 cs.dpl = ds.dpl = 0; 9109 cs.db = ds.db = 0; 9110 cs.s = ds.s = 1; 9111 cs.l = ds.l = 0; 9112 cs.g = ds.g = 1; 9113 cs.avl = ds.avl = 0; 9114 cs.present = ds.present = 1; 9115 cs.unusable = ds.unusable = 0; 9116 cs.padding = ds.padding = 0; 9117 9118 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 9119 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 9120 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 9121 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 9122 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 9123 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 9124 9125 #ifdef CONFIG_X86_64 9126 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 9127 static_call(kvm_x86_set_efer)(vcpu, 0); 9128 #endif 9129 9130 kvm_update_cpuid_runtime(vcpu); 9131 kvm_mmu_reset_context(vcpu); 9132 } 9133 9134 static void process_smi(struct kvm_vcpu *vcpu) 9135 { 9136 vcpu->arch.smi_pending = true; 9137 kvm_make_request(KVM_REQ_EVENT, vcpu); 9138 } 9139 9140 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 9141 unsigned long *vcpu_bitmap) 9142 { 9143 cpumask_var_t cpus; 9144 9145 zalloc_cpumask_var(&cpus, GFP_ATOMIC); 9146 9147 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, 9148 NULL, vcpu_bitmap, cpus); 9149 9150 free_cpumask_var(cpus); 9151 } 9152 9153 void kvm_make_scan_ioapic_request(struct kvm *kvm) 9154 { 9155 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 9156 } 9157 9158 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 9159 { 9160 bool activate; 9161 9162 if (!lapic_in_kernel(vcpu)) 9163 return; 9164 9165 mutex_lock(&vcpu->kvm->arch.apicv_update_lock); 9166 9167 activate = kvm_apicv_activated(vcpu->kvm); 9168 if (vcpu->arch.apicv_active == activate) 9169 goto out; 9170 9171 vcpu->arch.apicv_active = activate; 9172 kvm_apic_update_apicv(vcpu); 9173 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); 9174 9175 /* 9176 * When APICv gets disabled, we may still have injected interrupts 9177 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was 9178 * still active when the interrupt got accepted. Make sure 9179 * inject_pending_event() is called to check for that. 9180 */ 9181 if (!vcpu->arch.apicv_active) 9182 kvm_make_request(KVM_REQ_EVENT, vcpu); 9183 9184 out: 9185 mutex_unlock(&vcpu->kvm->arch.apicv_update_lock); 9186 } 9187 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); 9188 9189 void __kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) 9190 { 9191 unsigned long old, new; 9192 9193 if (!kvm_x86_ops.check_apicv_inhibit_reasons || 9194 !static_call(kvm_x86_check_apicv_inhibit_reasons)(bit)) 9195 return; 9196 9197 old = new = kvm->arch.apicv_inhibit_reasons; 9198 9199 if (activate) 9200 __clear_bit(bit, &new); 9201 else 9202 __set_bit(bit, &new); 9203 9204 if (!!old != !!new) { 9205 trace_kvm_apicv_update_request(activate, bit); 9206 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); 9207 kvm->arch.apicv_inhibit_reasons = new; 9208 if (new) { 9209 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE); 9210 kvm_zap_gfn_range(kvm, gfn, gfn+1); 9211 } 9212 } else 9213 kvm->arch.apicv_inhibit_reasons = new; 9214 } 9215 EXPORT_SYMBOL_GPL(__kvm_request_apicv_update); 9216 9217 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) 9218 { 9219 mutex_lock(&kvm->arch.apicv_update_lock); 9220 __kvm_request_apicv_update(kvm, activate, bit); 9221 mutex_unlock(&kvm->arch.apicv_update_lock); 9222 } 9223 EXPORT_SYMBOL_GPL(kvm_request_apicv_update); 9224 9225 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 9226 { 9227 if (!kvm_apic_present(vcpu)) 9228 return; 9229 9230 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 9231 9232 if (irqchip_split(vcpu->kvm)) 9233 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 9234 else { 9235 if (vcpu->arch.apicv_active) 9236 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 9237 if (ioapic_in_kernel(vcpu->kvm)) 9238 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 9239 } 9240 9241 if (is_guest_mode(vcpu)) 9242 vcpu->arch.load_eoi_exitmap_pending = true; 9243 else 9244 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 9245 } 9246 9247 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 9248 { 9249 u64 eoi_exit_bitmap[4]; 9250 9251 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 9252 return; 9253 9254 if (to_hv_vcpu(vcpu)) 9255 bitmap_or((ulong *)eoi_exit_bitmap, 9256 vcpu->arch.ioapic_handled_vectors, 9257 to_hv_synic(vcpu)->vec_bitmap, 256); 9258 9259 static_call(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); 9260 } 9261 9262 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 9263 unsigned long start, unsigned long end) 9264 { 9265 unsigned long apic_address; 9266 9267 /* 9268 * The physical address of apic access page is stored in the VMCS. 9269 * Update it when it becomes invalid. 9270 */ 9271 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 9272 if (start <= apic_address && apic_address < end) 9273 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 9274 } 9275 9276 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 9277 { 9278 if (!lapic_in_kernel(vcpu)) 9279 return; 9280 9281 if (!kvm_x86_ops.set_apic_access_page_addr) 9282 return; 9283 9284 static_call(kvm_x86_set_apic_access_page_addr)(vcpu); 9285 } 9286 9287 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 9288 { 9289 smp_send_reschedule(vcpu->cpu); 9290 } 9291 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 9292 9293 /* 9294 * Returns 1 to let vcpu_run() continue the guest execution loop without 9295 * exiting to the userspace. Otherwise, the value will be returned to the 9296 * userspace. 9297 */ 9298 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 9299 { 9300 int r; 9301 bool req_int_win = 9302 dm_request_for_irq_injection(vcpu) && 9303 kvm_cpu_accept_dm_intr(vcpu); 9304 fastpath_t exit_fastpath; 9305 9306 bool req_immediate_exit = false; 9307 9308 /* Forbid vmenter if vcpu dirty ring is soft-full */ 9309 if (unlikely(vcpu->kvm->dirty_ring_size && 9310 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { 9311 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; 9312 trace_kvm_dirty_ring_exit(vcpu); 9313 r = 0; 9314 goto out; 9315 } 9316 9317 if (kvm_request_pending(vcpu)) { 9318 if (kvm_check_request(KVM_REQ_VM_BUGGED, vcpu)) { 9319 r = -EIO; 9320 goto out; 9321 } 9322 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { 9323 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { 9324 r = 0; 9325 goto out; 9326 } 9327 } 9328 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 9329 kvm_mmu_unload(vcpu); 9330 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 9331 __kvm_migrate_timers(vcpu); 9332 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 9333 kvm_gen_update_masterclock(vcpu->kvm); 9334 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 9335 kvm_gen_kvmclock_update(vcpu); 9336 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 9337 r = kvm_guest_time_update(vcpu); 9338 if (unlikely(r)) 9339 goto out; 9340 } 9341 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 9342 kvm_mmu_sync_roots(vcpu); 9343 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) 9344 kvm_mmu_load_pgd(vcpu); 9345 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { 9346 kvm_vcpu_flush_tlb_all(vcpu); 9347 9348 /* Flushing all ASIDs flushes the current ASID... */ 9349 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 9350 } 9351 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) 9352 kvm_vcpu_flush_tlb_current(vcpu); 9353 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu)) 9354 kvm_vcpu_flush_tlb_guest(vcpu); 9355 9356 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 9357 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 9358 r = 0; 9359 goto out; 9360 } 9361 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 9362 if (is_guest_mode(vcpu)) { 9363 kvm_x86_ops.nested_ops->triple_fault(vcpu); 9364 } else { 9365 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 9366 vcpu->mmio_needed = 0; 9367 r = 0; 9368 goto out; 9369 } 9370 } 9371 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 9372 /* Page is swapped out. Do synthetic halt */ 9373 vcpu->arch.apf.halted = true; 9374 r = 1; 9375 goto out; 9376 } 9377 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 9378 record_steal_time(vcpu); 9379 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 9380 process_smi(vcpu); 9381 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 9382 process_nmi(vcpu); 9383 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 9384 kvm_pmu_handle_event(vcpu); 9385 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 9386 kvm_pmu_deliver_pmi(vcpu); 9387 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 9388 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 9389 if (test_bit(vcpu->arch.pending_ioapic_eoi, 9390 vcpu->arch.ioapic_handled_vectors)) { 9391 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 9392 vcpu->run->eoi.vector = 9393 vcpu->arch.pending_ioapic_eoi; 9394 r = 0; 9395 goto out; 9396 } 9397 } 9398 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 9399 vcpu_scan_ioapic(vcpu); 9400 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 9401 vcpu_load_eoi_exitmap(vcpu); 9402 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 9403 kvm_vcpu_reload_apic_access_page(vcpu); 9404 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 9405 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 9406 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 9407 r = 0; 9408 goto out; 9409 } 9410 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 9411 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 9412 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 9413 r = 0; 9414 goto out; 9415 } 9416 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 9417 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); 9418 9419 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 9420 vcpu->run->hyperv = hv_vcpu->exit; 9421 r = 0; 9422 goto out; 9423 } 9424 9425 /* 9426 * KVM_REQ_HV_STIMER has to be processed after 9427 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 9428 * depend on the guest clock being up-to-date 9429 */ 9430 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 9431 kvm_hv_process_stimers(vcpu); 9432 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 9433 kvm_vcpu_update_apicv(vcpu); 9434 if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) 9435 kvm_check_async_pf_completion(vcpu); 9436 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) 9437 static_call(kvm_x86_msr_filter_changed)(vcpu); 9438 9439 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) 9440 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); 9441 } 9442 9443 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || 9444 kvm_xen_has_interrupt(vcpu)) { 9445 ++vcpu->stat.req_event; 9446 r = kvm_apic_accept_events(vcpu); 9447 if (r < 0) { 9448 r = 0; 9449 goto out; 9450 } 9451 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 9452 r = 1; 9453 goto out; 9454 } 9455 9456 r = inject_pending_event(vcpu, &req_immediate_exit); 9457 if (r < 0) { 9458 r = 0; 9459 goto out; 9460 } 9461 if (req_int_win) 9462 static_call(kvm_x86_enable_irq_window)(vcpu); 9463 9464 if (kvm_lapic_enabled(vcpu)) { 9465 update_cr8_intercept(vcpu); 9466 kvm_lapic_sync_to_vapic(vcpu); 9467 } 9468 } 9469 9470 r = kvm_mmu_reload(vcpu); 9471 if (unlikely(r)) { 9472 goto cancel_injection; 9473 } 9474 9475 preempt_disable(); 9476 9477 static_call(kvm_x86_prepare_guest_switch)(vcpu); 9478 9479 /* 9480 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 9481 * IPI are then delayed after guest entry, which ensures that they 9482 * result in virtual interrupt delivery. 9483 */ 9484 local_irq_disable(); 9485 vcpu->mode = IN_GUEST_MODE; 9486 9487 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 9488 9489 /* 9490 * 1) We should set ->mode before checking ->requests. Please see 9491 * the comment in kvm_vcpu_exiting_guest_mode(). 9492 * 9493 * 2) For APICv, we should set ->mode before checking PID.ON. This 9494 * pairs with the memory barrier implicit in pi_test_and_set_on 9495 * (see vmx_deliver_posted_interrupt). 9496 * 9497 * 3) This also orders the write to mode from any reads to the page 9498 * tables done while the VCPU is running. Please see the comment 9499 * in kvm_flush_remote_tlbs. 9500 */ 9501 smp_mb__after_srcu_read_unlock(); 9502 9503 /* 9504 * This handles the case where a posted interrupt was 9505 * notified with kvm_vcpu_kick. 9506 */ 9507 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) 9508 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 9509 9510 if (kvm_vcpu_exit_request(vcpu)) { 9511 vcpu->mode = OUTSIDE_GUEST_MODE; 9512 smp_wmb(); 9513 local_irq_enable(); 9514 preempt_enable(); 9515 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9516 r = 1; 9517 goto cancel_injection; 9518 } 9519 9520 if (req_immediate_exit) { 9521 kvm_make_request(KVM_REQ_EVENT, vcpu); 9522 static_call(kvm_x86_request_immediate_exit)(vcpu); 9523 } 9524 9525 fpregs_assert_state_consistent(); 9526 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 9527 switch_fpu_return(); 9528 9529 if (unlikely(vcpu->arch.switch_db_regs)) { 9530 set_debugreg(0, 7); 9531 set_debugreg(vcpu->arch.eff_db[0], 0); 9532 set_debugreg(vcpu->arch.eff_db[1], 1); 9533 set_debugreg(vcpu->arch.eff_db[2], 2); 9534 set_debugreg(vcpu->arch.eff_db[3], 3); 9535 } else if (unlikely(hw_breakpoint_active())) { 9536 set_debugreg(0, 7); 9537 } 9538 9539 for (;;) { 9540 exit_fastpath = static_call(kvm_x86_run)(vcpu); 9541 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) 9542 break; 9543 9544 if (vcpu->arch.apicv_active) 9545 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 9546 9547 if (unlikely(kvm_vcpu_exit_request(vcpu))) { 9548 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; 9549 break; 9550 } 9551 } 9552 9553 /* 9554 * Do this here before restoring debug registers on the host. And 9555 * since we do this before handling the vmexit, a DR access vmexit 9556 * can (a) read the correct value of the debug registers, (b) set 9557 * KVM_DEBUGREG_WONT_EXIT again. 9558 */ 9559 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 9560 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 9561 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); 9562 kvm_update_dr0123(vcpu); 9563 kvm_update_dr7(vcpu); 9564 } 9565 9566 /* 9567 * If the guest has used debug registers, at least dr7 9568 * will be disabled while returning to the host. 9569 * If we don't have active breakpoints in the host, we don't 9570 * care about the messed up debug address registers. But if 9571 * we have some of them active, restore the old state. 9572 */ 9573 if (hw_breakpoint_active()) 9574 hw_breakpoint_restore(); 9575 9576 vcpu->arch.last_vmentry_cpu = vcpu->cpu; 9577 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 9578 9579 vcpu->mode = OUTSIDE_GUEST_MODE; 9580 smp_wmb(); 9581 9582 static_call(kvm_x86_handle_exit_irqoff)(vcpu); 9583 9584 /* 9585 * Consume any pending interrupts, including the possible source of 9586 * VM-Exit on SVM and any ticks that occur between VM-Exit and now. 9587 * An instruction is required after local_irq_enable() to fully unblock 9588 * interrupts on processors that implement an interrupt shadow, the 9589 * stat.exits increment will do nicely. 9590 */ 9591 kvm_before_interrupt(vcpu); 9592 local_irq_enable(); 9593 ++vcpu->stat.exits; 9594 local_irq_disable(); 9595 kvm_after_interrupt(vcpu); 9596 9597 /* 9598 * Wait until after servicing IRQs to account guest time so that any 9599 * ticks that occurred while running the guest are properly accounted 9600 * to the guest. Waiting until IRQs are enabled degrades the accuracy 9601 * of accounting via context tracking, but the loss of accuracy is 9602 * acceptable for all known use cases. 9603 */ 9604 vtime_account_guest_exit(); 9605 9606 if (lapic_in_kernel(vcpu)) { 9607 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; 9608 if (delta != S64_MIN) { 9609 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); 9610 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; 9611 } 9612 } 9613 9614 local_irq_enable(); 9615 preempt_enable(); 9616 9617 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9618 9619 /* 9620 * Profile KVM exit RIPs: 9621 */ 9622 if (unlikely(prof_on == KVM_PROFILING)) { 9623 unsigned long rip = kvm_rip_read(vcpu); 9624 profile_hit(KVM_PROFILING, (void *)rip); 9625 } 9626 9627 if (unlikely(vcpu->arch.tsc_always_catchup)) 9628 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 9629 9630 if (vcpu->arch.apic_attention) 9631 kvm_lapic_sync_from_vapic(vcpu); 9632 9633 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); 9634 return r; 9635 9636 cancel_injection: 9637 if (req_immediate_exit) 9638 kvm_make_request(KVM_REQ_EVENT, vcpu); 9639 static_call(kvm_x86_cancel_injection)(vcpu); 9640 if (unlikely(vcpu->arch.apic_attention)) 9641 kvm_lapic_sync_from_vapic(vcpu); 9642 out: 9643 return r; 9644 } 9645 9646 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 9647 { 9648 if (!kvm_arch_vcpu_runnable(vcpu) && 9649 (!kvm_x86_ops.pre_block || static_call(kvm_x86_pre_block)(vcpu) == 0)) { 9650 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9651 kvm_vcpu_block(vcpu); 9652 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9653 9654 if (kvm_x86_ops.post_block) 9655 static_call(kvm_x86_post_block)(vcpu); 9656 9657 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 9658 return 1; 9659 } 9660 9661 if (kvm_apic_accept_events(vcpu) < 0) 9662 return 0; 9663 switch(vcpu->arch.mp_state) { 9664 case KVM_MP_STATE_HALTED: 9665 case KVM_MP_STATE_AP_RESET_HOLD: 9666 vcpu->arch.pv.pv_unhalted = false; 9667 vcpu->arch.mp_state = 9668 KVM_MP_STATE_RUNNABLE; 9669 fallthrough; 9670 case KVM_MP_STATE_RUNNABLE: 9671 vcpu->arch.apf.halted = false; 9672 break; 9673 case KVM_MP_STATE_INIT_RECEIVED: 9674 break; 9675 default: 9676 return -EINTR; 9677 } 9678 return 1; 9679 } 9680 9681 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 9682 { 9683 if (is_guest_mode(vcpu)) 9684 kvm_check_nested_events(vcpu); 9685 9686 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 9687 !vcpu->arch.apf.halted); 9688 } 9689 9690 static int vcpu_run(struct kvm_vcpu *vcpu) 9691 { 9692 int r; 9693 struct kvm *kvm = vcpu->kvm; 9694 9695 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9696 vcpu->arch.l1tf_flush_l1d = true; 9697 9698 for (;;) { 9699 if (kvm_vcpu_running(vcpu)) { 9700 r = vcpu_enter_guest(vcpu); 9701 } else { 9702 r = vcpu_block(kvm, vcpu); 9703 } 9704 9705 if (r <= 0) 9706 break; 9707 9708 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); 9709 if (kvm_cpu_has_pending_timer(vcpu)) 9710 kvm_inject_pending_timer_irqs(vcpu); 9711 9712 if (dm_request_for_irq_injection(vcpu) && 9713 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 9714 r = 0; 9715 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 9716 ++vcpu->stat.request_irq_exits; 9717 break; 9718 } 9719 9720 if (__xfer_to_guest_mode_work_pending()) { 9721 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9722 r = xfer_to_guest_mode_handle_work(vcpu); 9723 if (r) 9724 return r; 9725 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9726 } 9727 } 9728 9729 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9730 9731 return r; 9732 } 9733 9734 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 9735 { 9736 int r; 9737 9738 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9739 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 9740 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 9741 return r; 9742 } 9743 9744 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 9745 { 9746 BUG_ON(!vcpu->arch.pio.count); 9747 9748 return complete_emulated_io(vcpu); 9749 } 9750 9751 /* 9752 * Implements the following, as a state machine: 9753 * 9754 * read: 9755 * for each fragment 9756 * for each mmio piece in the fragment 9757 * write gpa, len 9758 * exit 9759 * copy data 9760 * execute insn 9761 * 9762 * write: 9763 * for each fragment 9764 * for each mmio piece in the fragment 9765 * write gpa, len 9766 * copy data 9767 * exit 9768 */ 9769 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 9770 { 9771 struct kvm_run *run = vcpu->run; 9772 struct kvm_mmio_fragment *frag; 9773 unsigned len; 9774 9775 BUG_ON(!vcpu->mmio_needed); 9776 9777 /* Complete previous fragment */ 9778 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 9779 len = min(8u, frag->len); 9780 if (!vcpu->mmio_is_write) 9781 memcpy(frag->data, run->mmio.data, len); 9782 9783 if (frag->len <= 8) { 9784 /* Switch to the next fragment. */ 9785 frag++; 9786 vcpu->mmio_cur_fragment++; 9787 } else { 9788 /* Go forward to the next mmio piece. */ 9789 frag->data += len; 9790 frag->gpa += len; 9791 frag->len -= len; 9792 } 9793 9794 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 9795 vcpu->mmio_needed = 0; 9796 9797 /* FIXME: return into emulator if single-stepping. */ 9798 if (vcpu->mmio_is_write) 9799 return 1; 9800 vcpu->mmio_read_completed = 1; 9801 return complete_emulated_io(vcpu); 9802 } 9803 9804 run->exit_reason = KVM_EXIT_MMIO; 9805 run->mmio.phys_addr = frag->gpa; 9806 if (vcpu->mmio_is_write) 9807 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 9808 run->mmio.len = min(8u, frag->len); 9809 run->mmio.is_write = vcpu->mmio_is_write; 9810 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 9811 return 0; 9812 } 9813 9814 /* Swap (qemu) user FPU context for the guest FPU context. */ 9815 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 9816 { 9817 /* 9818 * Exclude PKRU from restore as restored separately in 9819 * kvm_x86_ops.run(). 9820 */ 9821 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true); 9822 trace_kvm_fpu(1); 9823 } 9824 9825 /* When vcpu_run ends, restore user space FPU context. */ 9826 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 9827 { 9828 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false); 9829 ++vcpu->stat.fpu_reload; 9830 trace_kvm_fpu(0); 9831 } 9832 9833 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 9834 { 9835 struct kvm_run *kvm_run = vcpu->run; 9836 int r; 9837 9838 vcpu_load(vcpu); 9839 kvm_sigset_activate(vcpu); 9840 kvm_run->flags = 0; 9841 kvm_load_guest_fpu(vcpu); 9842 9843 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 9844 if (kvm_run->immediate_exit) { 9845 r = -EINTR; 9846 goto out; 9847 } 9848 kvm_vcpu_block(vcpu); 9849 if (kvm_apic_accept_events(vcpu) < 0) { 9850 r = 0; 9851 goto out; 9852 } 9853 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 9854 r = -EAGAIN; 9855 if (signal_pending(current)) { 9856 r = -EINTR; 9857 kvm_run->exit_reason = KVM_EXIT_INTR; 9858 ++vcpu->stat.signal_exits; 9859 } 9860 goto out; 9861 } 9862 9863 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) || 9864 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) { 9865 r = -EINVAL; 9866 goto out; 9867 } 9868 9869 if (kvm_run->kvm_dirty_regs) { 9870 r = sync_regs(vcpu); 9871 if (r != 0) 9872 goto out; 9873 } 9874 9875 /* re-sync apic's tpr */ 9876 if (!lapic_in_kernel(vcpu)) { 9877 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 9878 r = -EINVAL; 9879 goto out; 9880 } 9881 } 9882 9883 if (unlikely(vcpu->arch.complete_userspace_io)) { 9884 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 9885 vcpu->arch.complete_userspace_io = NULL; 9886 r = cui(vcpu); 9887 if (r <= 0) 9888 goto out; 9889 } else 9890 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 9891 9892 if (kvm_run->immediate_exit) 9893 r = -EINTR; 9894 else 9895 r = vcpu_run(vcpu); 9896 9897 out: 9898 kvm_put_guest_fpu(vcpu); 9899 if (kvm_run->kvm_valid_regs) 9900 store_regs(vcpu); 9901 post_kvm_run_save(vcpu); 9902 kvm_sigset_deactivate(vcpu); 9903 9904 vcpu_put(vcpu); 9905 return r; 9906 } 9907 9908 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9909 { 9910 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 9911 /* 9912 * We are here if userspace calls get_regs() in the middle of 9913 * instruction emulation. Registers state needs to be copied 9914 * back from emulation context to vcpu. Userspace shouldn't do 9915 * that usually, but some bad designed PV devices (vmware 9916 * backdoor interface) need this to work 9917 */ 9918 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); 9919 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 9920 } 9921 regs->rax = kvm_rax_read(vcpu); 9922 regs->rbx = kvm_rbx_read(vcpu); 9923 regs->rcx = kvm_rcx_read(vcpu); 9924 regs->rdx = kvm_rdx_read(vcpu); 9925 regs->rsi = kvm_rsi_read(vcpu); 9926 regs->rdi = kvm_rdi_read(vcpu); 9927 regs->rsp = kvm_rsp_read(vcpu); 9928 regs->rbp = kvm_rbp_read(vcpu); 9929 #ifdef CONFIG_X86_64 9930 regs->r8 = kvm_r8_read(vcpu); 9931 regs->r9 = kvm_r9_read(vcpu); 9932 regs->r10 = kvm_r10_read(vcpu); 9933 regs->r11 = kvm_r11_read(vcpu); 9934 regs->r12 = kvm_r12_read(vcpu); 9935 regs->r13 = kvm_r13_read(vcpu); 9936 regs->r14 = kvm_r14_read(vcpu); 9937 regs->r15 = kvm_r15_read(vcpu); 9938 #endif 9939 9940 regs->rip = kvm_rip_read(vcpu); 9941 regs->rflags = kvm_get_rflags(vcpu); 9942 } 9943 9944 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9945 { 9946 vcpu_load(vcpu); 9947 __get_regs(vcpu, regs); 9948 vcpu_put(vcpu); 9949 return 0; 9950 } 9951 9952 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9953 { 9954 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 9955 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 9956 9957 kvm_rax_write(vcpu, regs->rax); 9958 kvm_rbx_write(vcpu, regs->rbx); 9959 kvm_rcx_write(vcpu, regs->rcx); 9960 kvm_rdx_write(vcpu, regs->rdx); 9961 kvm_rsi_write(vcpu, regs->rsi); 9962 kvm_rdi_write(vcpu, regs->rdi); 9963 kvm_rsp_write(vcpu, regs->rsp); 9964 kvm_rbp_write(vcpu, regs->rbp); 9965 #ifdef CONFIG_X86_64 9966 kvm_r8_write(vcpu, regs->r8); 9967 kvm_r9_write(vcpu, regs->r9); 9968 kvm_r10_write(vcpu, regs->r10); 9969 kvm_r11_write(vcpu, regs->r11); 9970 kvm_r12_write(vcpu, regs->r12); 9971 kvm_r13_write(vcpu, regs->r13); 9972 kvm_r14_write(vcpu, regs->r14); 9973 kvm_r15_write(vcpu, regs->r15); 9974 #endif 9975 9976 kvm_rip_write(vcpu, regs->rip); 9977 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 9978 9979 vcpu->arch.exception.pending = false; 9980 9981 kvm_make_request(KVM_REQ_EVENT, vcpu); 9982 } 9983 9984 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9985 { 9986 vcpu_load(vcpu); 9987 __set_regs(vcpu, regs); 9988 vcpu_put(vcpu); 9989 return 0; 9990 } 9991 9992 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 9993 { 9994 struct kvm_segment cs; 9995 9996 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 9997 *db = cs.db; 9998 *l = cs.l; 9999 } 10000 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 10001 10002 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10003 { 10004 struct desc_ptr dt; 10005 10006 if (vcpu->arch.guest_state_protected) 10007 goto skip_protected_regs; 10008 10009 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 10010 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 10011 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 10012 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 10013 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 10014 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 10015 10016 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 10017 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 10018 10019 static_call(kvm_x86_get_idt)(vcpu, &dt); 10020 sregs->idt.limit = dt.size; 10021 sregs->idt.base = dt.address; 10022 static_call(kvm_x86_get_gdt)(vcpu, &dt); 10023 sregs->gdt.limit = dt.size; 10024 sregs->gdt.base = dt.address; 10025 10026 sregs->cr2 = vcpu->arch.cr2; 10027 sregs->cr3 = kvm_read_cr3(vcpu); 10028 10029 skip_protected_regs: 10030 sregs->cr0 = kvm_read_cr0(vcpu); 10031 sregs->cr4 = kvm_read_cr4(vcpu); 10032 sregs->cr8 = kvm_get_cr8(vcpu); 10033 sregs->efer = vcpu->arch.efer; 10034 sregs->apic_base = kvm_get_apic_base(vcpu); 10035 } 10036 10037 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10038 { 10039 __get_sregs_common(vcpu, sregs); 10040 10041 if (vcpu->arch.guest_state_protected) 10042 return; 10043 10044 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 10045 set_bit(vcpu->arch.interrupt.nr, 10046 (unsigned long *)sregs->interrupt_bitmap); 10047 } 10048 10049 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 10050 { 10051 int i; 10052 10053 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2); 10054 10055 if (vcpu->arch.guest_state_protected) 10056 return; 10057 10058 if (is_pae_paging(vcpu)) { 10059 for (i = 0 ; i < 4 ; i++) 10060 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i); 10061 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; 10062 } 10063 } 10064 10065 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 10066 struct kvm_sregs *sregs) 10067 { 10068 vcpu_load(vcpu); 10069 __get_sregs(vcpu, sregs); 10070 vcpu_put(vcpu); 10071 return 0; 10072 } 10073 10074 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 10075 struct kvm_mp_state *mp_state) 10076 { 10077 int r; 10078 10079 vcpu_load(vcpu); 10080 if (kvm_mpx_supported()) 10081 kvm_load_guest_fpu(vcpu); 10082 10083 r = kvm_apic_accept_events(vcpu); 10084 if (r < 0) 10085 goto out; 10086 r = 0; 10087 10088 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || 10089 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && 10090 vcpu->arch.pv.pv_unhalted) 10091 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 10092 else 10093 mp_state->mp_state = vcpu->arch.mp_state; 10094 10095 out: 10096 if (kvm_mpx_supported()) 10097 kvm_put_guest_fpu(vcpu); 10098 vcpu_put(vcpu); 10099 return r; 10100 } 10101 10102 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 10103 struct kvm_mp_state *mp_state) 10104 { 10105 int ret = -EINVAL; 10106 10107 vcpu_load(vcpu); 10108 10109 if (!lapic_in_kernel(vcpu) && 10110 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 10111 goto out; 10112 10113 /* 10114 * KVM_MP_STATE_INIT_RECEIVED means the processor is in 10115 * INIT state; latched init should be reported using 10116 * KVM_SET_VCPU_EVENTS, so reject it here. 10117 */ 10118 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && 10119 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 10120 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 10121 goto out; 10122 10123 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 10124 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 10125 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 10126 } else 10127 vcpu->arch.mp_state = mp_state->mp_state; 10128 kvm_make_request(KVM_REQ_EVENT, vcpu); 10129 10130 ret = 0; 10131 out: 10132 vcpu_put(vcpu); 10133 return ret; 10134 } 10135 10136 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 10137 int reason, bool has_error_code, u32 error_code) 10138 { 10139 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 10140 int ret; 10141 10142 init_emulate_ctxt(vcpu); 10143 10144 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 10145 has_error_code, error_code); 10146 if (ret) { 10147 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 10148 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 10149 vcpu->run->internal.ndata = 0; 10150 return 0; 10151 } 10152 10153 kvm_rip_write(vcpu, ctxt->eip); 10154 kvm_set_rflags(vcpu, ctxt->eflags); 10155 return 1; 10156 } 10157 EXPORT_SYMBOL_GPL(kvm_task_switch); 10158 10159 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10160 { 10161 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 10162 /* 10163 * When EFER.LME and CR0.PG are set, the processor is in 10164 * 64-bit mode (though maybe in a 32-bit code segment). 10165 * CR4.PAE and EFER.LMA must be set. 10166 */ 10167 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) 10168 return false; 10169 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) 10170 return false; 10171 } else { 10172 /* 10173 * Not in 64-bit mode: EFER.LMA is clear and the code 10174 * segment cannot be 64-bit. 10175 */ 10176 if (sregs->efer & EFER_LMA || sregs->cs.l) 10177 return false; 10178 } 10179 10180 return kvm_is_valid_cr4(vcpu, sregs->cr4); 10181 } 10182 10183 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs, 10184 int *mmu_reset_needed, bool update_pdptrs) 10185 { 10186 struct msr_data apic_base_msr; 10187 int idx; 10188 struct desc_ptr dt; 10189 10190 if (!kvm_is_valid_sregs(vcpu, sregs)) 10191 return -EINVAL; 10192 10193 apic_base_msr.data = sregs->apic_base; 10194 apic_base_msr.host_initiated = true; 10195 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 10196 return -EINVAL; 10197 10198 if (vcpu->arch.guest_state_protected) 10199 return 0; 10200 10201 dt.size = sregs->idt.limit; 10202 dt.address = sregs->idt.base; 10203 static_call(kvm_x86_set_idt)(vcpu, &dt); 10204 dt.size = sregs->gdt.limit; 10205 dt.address = sregs->gdt.base; 10206 static_call(kvm_x86_set_gdt)(vcpu, &dt); 10207 10208 vcpu->arch.cr2 = sregs->cr2; 10209 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 10210 vcpu->arch.cr3 = sregs->cr3; 10211 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 10212 10213 kvm_set_cr8(vcpu, sregs->cr8); 10214 10215 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 10216 static_call(kvm_x86_set_efer)(vcpu, sregs->efer); 10217 10218 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 10219 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); 10220 vcpu->arch.cr0 = sregs->cr0; 10221 10222 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 10223 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); 10224 10225 if (update_pdptrs) { 10226 idx = srcu_read_lock(&vcpu->kvm->srcu); 10227 if (is_pae_paging(vcpu)) { 10228 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 10229 *mmu_reset_needed = 1; 10230 } 10231 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10232 } 10233 10234 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 10235 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 10236 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 10237 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 10238 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 10239 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 10240 10241 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 10242 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 10243 10244 update_cr8_intercept(vcpu); 10245 10246 /* Older userspace won't unhalt the vcpu on reset. */ 10247 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 10248 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 10249 !is_protmode(vcpu)) 10250 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 10251 10252 return 0; 10253 } 10254 10255 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10256 { 10257 int pending_vec, max_bits; 10258 int mmu_reset_needed = 0; 10259 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true); 10260 10261 if (ret) 10262 return ret; 10263 10264 if (mmu_reset_needed) 10265 kvm_mmu_reset_context(vcpu); 10266 10267 max_bits = KVM_NR_INTERRUPTS; 10268 pending_vec = find_first_bit( 10269 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 10270 10271 if (pending_vec < max_bits) { 10272 kvm_queue_interrupt(vcpu, pending_vec, false); 10273 pr_debug("Set back pending irq %d\n", pending_vec); 10274 kvm_make_request(KVM_REQ_EVENT, vcpu); 10275 } 10276 return 0; 10277 } 10278 10279 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 10280 { 10281 int mmu_reset_needed = 0; 10282 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; 10283 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) && 10284 !(sregs2->efer & EFER_LMA); 10285 int i, ret; 10286 10287 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID) 10288 return -EINVAL; 10289 10290 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected)) 10291 return -EINVAL; 10292 10293 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2, 10294 &mmu_reset_needed, !valid_pdptrs); 10295 if (ret) 10296 return ret; 10297 10298 if (valid_pdptrs) { 10299 for (i = 0; i < 4 ; i++) 10300 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]); 10301 10302 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 10303 mmu_reset_needed = 1; 10304 vcpu->arch.pdptrs_from_userspace = true; 10305 } 10306 if (mmu_reset_needed) 10307 kvm_mmu_reset_context(vcpu); 10308 return 0; 10309 } 10310 10311 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 10312 struct kvm_sregs *sregs) 10313 { 10314 int ret; 10315 10316 vcpu_load(vcpu); 10317 ret = __set_sregs(vcpu, sregs); 10318 vcpu_put(vcpu); 10319 return ret; 10320 } 10321 10322 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 10323 struct kvm_guest_debug *dbg) 10324 { 10325 unsigned long rflags; 10326 int i, r; 10327 10328 if (vcpu->arch.guest_state_protected) 10329 return -EINVAL; 10330 10331 vcpu_load(vcpu); 10332 10333 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 10334 r = -EBUSY; 10335 if (vcpu->arch.exception.pending) 10336 goto out; 10337 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 10338 kvm_queue_exception(vcpu, DB_VECTOR); 10339 else 10340 kvm_queue_exception(vcpu, BP_VECTOR); 10341 } 10342 10343 /* 10344 * Read rflags as long as potentially injected trace flags are still 10345 * filtered out. 10346 */ 10347 rflags = kvm_get_rflags(vcpu); 10348 10349 vcpu->guest_debug = dbg->control; 10350 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 10351 vcpu->guest_debug = 0; 10352 10353 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 10354 for (i = 0; i < KVM_NR_DB_REGS; ++i) 10355 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 10356 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 10357 } else { 10358 for (i = 0; i < KVM_NR_DB_REGS; i++) 10359 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 10360 } 10361 kvm_update_dr7(vcpu); 10362 10363 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 10364 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); 10365 10366 /* 10367 * Trigger an rflags update that will inject or remove the trace 10368 * flags. 10369 */ 10370 kvm_set_rflags(vcpu, rflags); 10371 10372 static_call(kvm_x86_update_exception_bitmap)(vcpu); 10373 10374 r = 0; 10375 10376 out: 10377 vcpu_put(vcpu); 10378 return r; 10379 } 10380 10381 /* 10382 * Translate a guest virtual address to a guest physical address. 10383 */ 10384 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 10385 struct kvm_translation *tr) 10386 { 10387 unsigned long vaddr = tr->linear_address; 10388 gpa_t gpa; 10389 int idx; 10390 10391 vcpu_load(vcpu); 10392 10393 idx = srcu_read_lock(&vcpu->kvm->srcu); 10394 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 10395 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10396 tr->physical_address = gpa; 10397 tr->valid = gpa != UNMAPPED_GVA; 10398 tr->writeable = 1; 10399 tr->usermode = 0; 10400 10401 vcpu_put(vcpu); 10402 return 0; 10403 } 10404 10405 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 10406 { 10407 struct fxregs_state *fxsave; 10408 10409 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 10410 return 0; 10411 10412 vcpu_load(vcpu); 10413 10414 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 10415 memcpy(fpu->fpr, fxsave->st_space, 128); 10416 fpu->fcw = fxsave->cwd; 10417 fpu->fsw = fxsave->swd; 10418 fpu->ftwx = fxsave->twd; 10419 fpu->last_opcode = fxsave->fop; 10420 fpu->last_ip = fxsave->rip; 10421 fpu->last_dp = fxsave->rdp; 10422 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 10423 10424 vcpu_put(vcpu); 10425 return 0; 10426 } 10427 10428 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 10429 { 10430 struct fxregs_state *fxsave; 10431 10432 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 10433 return 0; 10434 10435 vcpu_load(vcpu); 10436 10437 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 10438 10439 memcpy(fxsave->st_space, fpu->fpr, 128); 10440 fxsave->cwd = fpu->fcw; 10441 fxsave->swd = fpu->fsw; 10442 fxsave->twd = fpu->ftwx; 10443 fxsave->fop = fpu->last_opcode; 10444 fxsave->rip = fpu->last_ip; 10445 fxsave->rdp = fpu->last_dp; 10446 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 10447 10448 vcpu_put(vcpu); 10449 return 0; 10450 } 10451 10452 static void store_regs(struct kvm_vcpu *vcpu) 10453 { 10454 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 10455 10456 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 10457 __get_regs(vcpu, &vcpu->run->s.regs.regs); 10458 10459 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 10460 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 10461 10462 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 10463 kvm_vcpu_ioctl_x86_get_vcpu_events( 10464 vcpu, &vcpu->run->s.regs.events); 10465 } 10466 10467 static int sync_regs(struct kvm_vcpu *vcpu) 10468 { 10469 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 10470 __set_regs(vcpu, &vcpu->run->s.regs.regs); 10471 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 10472 } 10473 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 10474 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 10475 return -EINVAL; 10476 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 10477 } 10478 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 10479 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 10480 vcpu, &vcpu->run->s.regs.events)) 10481 return -EINVAL; 10482 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 10483 } 10484 10485 return 0; 10486 } 10487 10488 static void fx_init(struct kvm_vcpu *vcpu) 10489 { 10490 /* 10491 * Ensure guest xcr0 is valid for loading 10492 */ 10493 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 10494 10495 vcpu->arch.cr0 |= X86_CR0_ET; 10496 } 10497 10498 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 10499 { 10500 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 10501 pr_warn_once("kvm: SMP vm created on host with unstable TSC; " 10502 "guest TSC will not be reliable\n"); 10503 10504 return 0; 10505 } 10506 10507 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 10508 { 10509 struct page *page; 10510 int r; 10511 10512 vcpu->arch.last_vmentry_cpu = -1; 10513 vcpu->arch.regs_avail = ~0; 10514 vcpu->arch.regs_dirty = ~0; 10515 10516 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 10517 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 10518 else 10519 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 10520 10521 r = kvm_mmu_create(vcpu); 10522 if (r < 0) 10523 return r; 10524 10525 if (irqchip_in_kernel(vcpu->kvm)) { 10526 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 10527 if (r < 0) 10528 goto fail_mmu_destroy; 10529 if (kvm_apicv_activated(vcpu->kvm)) 10530 vcpu->arch.apicv_active = true; 10531 } else 10532 static_branch_inc(&kvm_has_noapic_vcpu); 10533 10534 r = -ENOMEM; 10535 10536 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 10537 if (!page) 10538 goto fail_free_lapic; 10539 vcpu->arch.pio_data = page_address(page); 10540 10541 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 10542 GFP_KERNEL_ACCOUNT); 10543 if (!vcpu->arch.mce_banks) 10544 goto fail_free_pio_data; 10545 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 10546 10547 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 10548 GFP_KERNEL_ACCOUNT)) 10549 goto fail_free_mce_banks; 10550 10551 if (!alloc_emulate_ctxt(vcpu)) 10552 goto free_wbinvd_dirty_mask; 10553 10554 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) { 10555 pr_err("kvm: failed to allocate vcpu's fpu\n"); 10556 goto free_emulate_ctxt; 10557 } 10558 10559 fx_init(vcpu); 10560 10561 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 10562 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 10563 10564 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 10565 10566 kvm_async_pf_hash_reset(vcpu); 10567 kvm_pmu_init(vcpu); 10568 10569 vcpu->arch.pending_external_vector = -1; 10570 vcpu->arch.preempted_in_kernel = false; 10571 10572 #if IS_ENABLED(CONFIG_HYPERV) 10573 vcpu->arch.hv_root_tdp = INVALID_PAGE; 10574 #endif 10575 10576 r = static_call(kvm_x86_vcpu_create)(vcpu); 10577 if (r) 10578 goto free_guest_fpu; 10579 10580 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 10581 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 10582 kvm_vcpu_mtrr_init(vcpu); 10583 vcpu_load(vcpu); 10584 kvm_set_tsc_khz(vcpu, max_tsc_khz); 10585 kvm_vcpu_reset(vcpu, false); 10586 kvm_init_mmu(vcpu); 10587 vcpu_put(vcpu); 10588 return 0; 10589 10590 free_guest_fpu: 10591 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 10592 free_emulate_ctxt: 10593 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 10594 free_wbinvd_dirty_mask: 10595 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 10596 fail_free_mce_banks: 10597 kfree(vcpu->arch.mce_banks); 10598 fail_free_pio_data: 10599 free_page((unsigned long)vcpu->arch.pio_data); 10600 fail_free_lapic: 10601 kvm_free_lapic(vcpu); 10602 fail_mmu_destroy: 10603 kvm_mmu_destroy(vcpu); 10604 return r; 10605 } 10606 10607 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 10608 { 10609 struct kvm *kvm = vcpu->kvm; 10610 10611 if (mutex_lock_killable(&vcpu->mutex)) 10612 return; 10613 vcpu_load(vcpu); 10614 kvm_synchronize_tsc(vcpu, 0); 10615 vcpu_put(vcpu); 10616 10617 /* poll control enabled by default */ 10618 vcpu->arch.msr_kvm_poll_control = 1; 10619 10620 mutex_unlock(&vcpu->mutex); 10621 10622 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) 10623 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 10624 KVMCLOCK_SYNC_PERIOD); 10625 } 10626 10627 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 10628 { 10629 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; 10630 int idx; 10631 10632 kvm_release_pfn(cache->pfn, cache->dirty, cache); 10633 10634 kvmclock_reset(vcpu); 10635 10636 static_call(kvm_x86_vcpu_free)(vcpu); 10637 10638 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 10639 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 10640 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 10641 10642 kvm_hv_vcpu_uninit(vcpu); 10643 kvm_pmu_destroy(vcpu); 10644 kfree(vcpu->arch.mce_banks); 10645 kvm_free_lapic(vcpu); 10646 idx = srcu_read_lock(&vcpu->kvm->srcu); 10647 kvm_mmu_destroy(vcpu); 10648 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10649 free_page((unsigned long)vcpu->arch.pio_data); 10650 kvfree(vcpu->arch.cpuid_entries); 10651 if (!lapic_in_kernel(vcpu)) 10652 static_branch_dec(&kvm_has_noapic_vcpu); 10653 } 10654 10655 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 10656 { 10657 unsigned long old_cr0 = kvm_read_cr0(vcpu); 10658 unsigned long new_cr0; 10659 u32 eax, dummy; 10660 10661 kvm_lapic_reset(vcpu, init_event); 10662 10663 vcpu->arch.hflags = 0; 10664 10665 vcpu->arch.smi_pending = 0; 10666 vcpu->arch.smi_count = 0; 10667 atomic_set(&vcpu->arch.nmi_queued, 0); 10668 vcpu->arch.nmi_pending = 0; 10669 vcpu->arch.nmi_injected = false; 10670 kvm_clear_interrupt_queue(vcpu); 10671 kvm_clear_exception_queue(vcpu); 10672 10673 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 10674 kvm_update_dr0123(vcpu); 10675 vcpu->arch.dr6 = DR6_ACTIVE_LOW; 10676 vcpu->arch.dr7 = DR7_FIXED_1; 10677 kvm_update_dr7(vcpu); 10678 10679 vcpu->arch.cr2 = 0; 10680 10681 kvm_make_request(KVM_REQ_EVENT, vcpu); 10682 vcpu->arch.apf.msr_en_val = 0; 10683 vcpu->arch.apf.msr_int_val = 0; 10684 vcpu->arch.st.msr_val = 0; 10685 10686 kvmclock_reset(vcpu); 10687 10688 kvm_clear_async_pf_completion_queue(vcpu); 10689 kvm_async_pf_hash_reset(vcpu); 10690 vcpu->arch.apf.halted = false; 10691 10692 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) { 10693 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate; 10694 10695 /* 10696 * To avoid have the INIT path from kvm_apic_has_events() that be 10697 * called with loaded FPU and does not let userspace fix the state. 10698 */ 10699 if (init_event) 10700 kvm_put_guest_fpu(vcpu); 10701 10702 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS); 10703 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR); 10704 10705 if (init_event) 10706 kvm_load_guest_fpu(vcpu); 10707 } 10708 10709 if (!init_event) { 10710 kvm_pmu_reset(vcpu); 10711 vcpu->arch.smbase = 0x30000; 10712 10713 vcpu->arch.msr_misc_features_enables = 0; 10714 10715 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 10716 } 10717 10718 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 10719 vcpu->arch.regs_avail = ~0; 10720 vcpu->arch.regs_dirty = ~0; 10721 10722 /* 10723 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon) 10724 * if no CPUID match is found. Note, it's impossible to get a match at 10725 * RESET since KVM emulates RESET before exposing the vCPU to userspace, 10726 * i.e. it'simpossible for kvm_cpuid() to find a valid entry on RESET. 10727 * But, go through the motions in case that's ever remedied. 10728 */ 10729 eax = 1; 10730 if (!kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true)) 10731 eax = 0x600; 10732 kvm_rdx_write(vcpu, eax); 10733 10734 vcpu->arch.ia32_xss = 0; 10735 10736 static_call(kvm_x86_vcpu_reset)(vcpu, init_event); 10737 10738 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 10739 kvm_rip_write(vcpu, 0xfff0); 10740 10741 vcpu->arch.cr3 = 0; 10742 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 10743 10744 /* 10745 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions 10746 * of Intel's SDM list CD/NW as being set on INIT, but they contradict 10747 * (or qualify) that with a footnote stating that CD/NW are preserved. 10748 */ 10749 new_cr0 = X86_CR0_ET; 10750 if (init_event) 10751 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD)); 10752 else 10753 new_cr0 |= X86_CR0_NW | X86_CR0_CD; 10754 10755 static_call(kvm_x86_set_cr0)(vcpu, new_cr0); 10756 static_call(kvm_x86_set_cr4)(vcpu, 0); 10757 static_call(kvm_x86_set_efer)(vcpu, 0); 10758 static_call(kvm_x86_update_exception_bitmap)(vcpu); 10759 10760 /* 10761 * Reset the MMU context if paging was enabled prior to INIT (which is 10762 * implied if CR0.PG=1 as CR0 will be '0' prior to RESET). Unlike the 10763 * standard CR0/CR4/EFER modification paths, only CR0.PG needs to be 10764 * checked because it is unconditionally cleared on INIT and all other 10765 * paging related bits are ignored if paging is disabled, i.e. CR0.WP, 10766 * CR4, and EFER changes are all irrelevant if CR0.PG was '0'. 10767 */ 10768 if (old_cr0 & X86_CR0_PG) 10769 kvm_mmu_reset_context(vcpu); 10770 10771 /* 10772 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's 10773 * APM states the TLBs are untouched by INIT, but it also states that 10774 * the TLBs are flushed on "External initialization of the processor." 10775 * Flush the guest TLB regardless of vendor, there is no meaningful 10776 * benefit in relying on the guest to flush the TLB immediately after 10777 * INIT. A spurious TLB flush is benign and likely negligible from a 10778 * performance perspective. 10779 */ 10780 if (init_event) 10781 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 10782 } 10783 EXPORT_SYMBOL_GPL(kvm_vcpu_reset); 10784 10785 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 10786 { 10787 struct kvm_segment cs; 10788 10789 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 10790 cs.selector = vector << 8; 10791 cs.base = vector << 12; 10792 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 10793 kvm_rip_write(vcpu, 0); 10794 } 10795 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); 10796 10797 int kvm_arch_hardware_enable(void) 10798 { 10799 struct kvm *kvm; 10800 struct kvm_vcpu *vcpu; 10801 int i; 10802 int ret; 10803 u64 local_tsc; 10804 u64 max_tsc = 0; 10805 bool stable, backwards_tsc = false; 10806 10807 kvm_user_return_msr_cpu_online(); 10808 ret = static_call(kvm_x86_hardware_enable)(); 10809 if (ret != 0) 10810 return ret; 10811 10812 local_tsc = rdtsc(); 10813 stable = !kvm_check_tsc_unstable(); 10814 list_for_each_entry(kvm, &vm_list, vm_list) { 10815 kvm_for_each_vcpu(i, vcpu, kvm) { 10816 if (!stable && vcpu->cpu == smp_processor_id()) 10817 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 10818 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 10819 backwards_tsc = true; 10820 if (vcpu->arch.last_host_tsc > max_tsc) 10821 max_tsc = vcpu->arch.last_host_tsc; 10822 } 10823 } 10824 } 10825 10826 /* 10827 * Sometimes, even reliable TSCs go backwards. This happens on 10828 * platforms that reset TSC during suspend or hibernate actions, but 10829 * maintain synchronization. We must compensate. Fortunately, we can 10830 * detect that condition here, which happens early in CPU bringup, 10831 * before any KVM threads can be running. Unfortunately, we can't 10832 * bring the TSCs fully up to date with real time, as we aren't yet far 10833 * enough into CPU bringup that we know how much real time has actually 10834 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot 10835 * variables that haven't been updated yet. 10836 * 10837 * So we simply find the maximum observed TSC above, then record the 10838 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 10839 * the adjustment will be applied. Note that we accumulate 10840 * adjustments, in case multiple suspend cycles happen before some VCPU 10841 * gets a chance to run again. In the event that no KVM threads get a 10842 * chance to run, we will miss the entire elapsed period, as we'll have 10843 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 10844 * loose cycle time. This isn't too big a deal, since the loss will be 10845 * uniform across all VCPUs (not to mention the scenario is extremely 10846 * unlikely). It is possible that a second hibernate recovery happens 10847 * much faster than a first, causing the observed TSC here to be 10848 * smaller; this would require additional padding adjustment, which is 10849 * why we set last_host_tsc to the local tsc observed here. 10850 * 10851 * N.B. - this code below runs only on platforms with reliable TSC, 10852 * as that is the only way backwards_tsc is set above. Also note 10853 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 10854 * have the same delta_cyc adjustment applied if backwards_tsc 10855 * is detected. Note further, this adjustment is only done once, 10856 * as we reset last_host_tsc on all VCPUs to stop this from being 10857 * called multiple times (one for each physical CPU bringup). 10858 * 10859 * Platforms with unreliable TSCs don't have to deal with this, they 10860 * will be compensated by the logic in vcpu_load, which sets the TSC to 10861 * catchup mode. This will catchup all VCPUs to real time, but cannot 10862 * guarantee that they stay in perfect synchronization. 10863 */ 10864 if (backwards_tsc) { 10865 u64 delta_cyc = max_tsc - local_tsc; 10866 list_for_each_entry(kvm, &vm_list, vm_list) { 10867 kvm->arch.backwards_tsc_observed = true; 10868 kvm_for_each_vcpu(i, vcpu, kvm) { 10869 vcpu->arch.tsc_offset_adjustment += delta_cyc; 10870 vcpu->arch.last_host_tsc = local_tsc; 10871 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 10872 } 10873 10874 /* 10875 * We have to disable TSC offset matching.. if you were 10876 * booting a VM while issuing an S4 host suspend.... 10877 * you may have some problem. Solving this issue is 10878 * left as an exercise to the reader. 10879 */ 10880 kvm->arch.last_tsc_nsec = 0; 10881 kvm->arch.last_tsc_write = 0; 10882 } 10883 10884 } 10885 return 0; 10886 } 10887 10888 void kvm_arch_hardware_disable(void) 10889 { 10890 static_call(kvm_x86_hardware_disable)(); 10891 drop_user_return_notifiers(); 10892 } 10893 10894 int kvm_arch_hardware_setup(void *opaque) 10895 { 10896 struct kvm_x86_init_ops *ops = opaque; 10897 int r; 10898 10899 rdmsrl_safe(MSR_EFER, &host_efer); 10900 10901 if (boot_cpu_has(X86_FEATURE_XSAVES)) 10902 rdmsrl(MSR_IA32_XSS, host_xss); 10903 10904 r = ops->hardware_setup(); 10905 if (r != 0) 10906 return r; 10907 10908 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); 10909 kvm_ops_static_call_update(); 10910 10911 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) 10912 supported_xss = 0; 10913 10914 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) 10915 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); 10916 #undef __kvm_cpu_cap_has 10917 10918 if (kvm_has_tsc_control) { 10919 /* 10920 * Make sure the user can only configure tsc_khz values that 10921 * fit into a signed integer. 10922 * A min value is not calculated because it will always 10923 * be 1 on all machines. 10924 */ 10925 u64 max = min(0x7fffffffULL, 10926 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 10927 kvm_max_guest_tsc_khz = max; 10928 10929 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 10930 } 10931 10932 kvm_init_msr_list(); 10933 return 0; 10934 } 10935 10936 void kvm_arch_hardware_unsetup(void) 10937 { 10938 static_call(kvm_x86_hardware_unsetup)(); 10939 } 10940 10941 int kvm_arch_check_processor_compat(void *opaque) 10942 { 10943 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 10944 struct kvm_x86_init_ops *ops = opaque; 10945 10946 WARN_ON(!irqs_disabled()); 10947 10948 if (__cr4_reserved_bits(cpu_has, c) != 10949 __cr4_reserved_bits(cpu_has, &boot_cpu_data)) 10950 return -EIO; 10951 10952 return ops->check_processor_compatibility(); 10953 } 10954 10955 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 10956 { 10957 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 10958 } 10959 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 10960 10961 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 10962 { 10963 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 10964 } 10965 10966 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); 10967 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); 10968 10969 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 10970 { 10971 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 10972 10973 vcpu->arch.l1tf_flush_l1d = true; 10974 if (pmu->version && unlikely(pmu->event_count)) { 10975 pmu->need_cleanup = true; 10976 kvm_make_request(KVM_REQ_PMU, vcpu); 10977 } 10978 static_call(kvm_x86_sched_in)(vcpu, cpu); 10979 } 10980 10981 void kvm_arch_free_vm(struct kvm *kvm) 10982 { 10983 kfree(to_kvm_hv(kvm)->hv_pa_pg); 10984 vfree(kvm); 10985 } 10986 10987 10988 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 10989 { 10990 int ret; 10991 10992 if (type) 10993 return -EINVAL; 10994 10995 ret = kvm_page_track_init(kvm); 10996 if (ret) 10997 return ret; 10998 10999 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 11000 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 11001 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 11002 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); 11003 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 11004 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 11005 11006 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 11007 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 11008 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 11009 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 11010 &kvm->arch.irq_sources_bitmap); 11011 11012 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 11013 mutex_init(&kvm->arch.apic_map_lock); 11014 raw_spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 11015 11016 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); 11017 pvclock_update_vm_gtod_copy(kvm); 11018 11019 kvm->arch.guest_can_read_msr_platform_info = true; 11020 11021 #if IS_ENABLED(CONFIG_HYPERV) 11022 spin_lock_init(&kvm->arch.hv_root_tdp_lock); 11023 kvm->arch.hv_root_tdp = INVALID_PAGE; 11024 #endif 11025 11026 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 11027 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 11028 11029 kvm_apicv_init(kvm); 11030 kvm_hv_init_vm(kvm); 11031 kvm_mmu_init_vm(kvm); 11032 kvm_xen_init_vm(kvm); 11033 11034 return static_call(kvm_x86_vm_init)(kvm); 11035 } 11036 11037 int kvm_arch_post_init_vm(struct kvm *kvm) 11038 { 11039 return kvm_mmu_post_init_vm(kvm); 11040 } 11041 11042 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 11043 { 11044 vcpu_load(vcpu); 11045 kvm_mmu_unload(vcpu); 11046 vcpu_put(vcpu); 11047 } 11048 11049 static void kvm_free_vcpus(struct kvm *kvm) 11050 { 11051 unsigned int i; 11052 struct kvm_vcpu *vcpu; 11053 11054 /* 11055 * Unpin any mmu pages first. 11056 */ 11057 kvm_for_each_vcpu(i, vcpu, kvm) { 11058 kvm_clear_async_pf_completion_queue(vcpu); 11059 kvm_unload_vcpu_mmu(vcpu); 11060 } 11061 kvm_for_each_vcpu(i, vcpu, kvm) 11062 kvm_vcpu_destroy(vcpu); 11063 11064 mutex_lock(&kvm->lock); 11065 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 11066 kvm->vcpus[i] = NULL; 11067 11068 atomic_set(&kvm->online_vcpus, 0); 11069 mutex_unlock(&kvm->lock); 11070 } 11071 11072 void kvm_arch_sync_events(struct kvm *kvm) 11073 { 11074 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 11075 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 11076 kvm_free_pit(kvm); 11077 } 11078 11079 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) 11080 11081 /** 11082 * __x86_set_memory_region: Setup KVM internal memory slot 11083 * 11084 * @kvm: the kvm pointer to the VM. 11085 * @id: the slot ID to setup. 11086 * @gpa: the GPA to install the slot (unused when @size == 0). 11087 * @size: the size of the slot. Set to zero to uninstall a slot. 11088 * 11089 * This function helps to setup a KVM internal memory slot. Specify 11090 * @size > 0 to install a new slot, while @size == 0 to uninstall a 11091 * slot. The return code can be one of the following: 11092 * 11093 * HVA: on success (uninstall will return a bogus HVA) 11094 * -errno: on error 11095 * 11096 * The caller should always use IS_ERR() to check the return value 11097 * before use. Note, the KVM internal memory slots are guaranteed to 11098 * remain valid and unchanged until the VM is destroyed, i.e., the 11099 * GPA->HVA translation will not change. However, the HVA is a user 11100 * address, i.e. its accessibility is not guaranteed, and must be 11101 * accessed via __copy_{to,from}_user(). 11102 */ 11103 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, 11104 u32 size) 11105 { 11106 int i, r; 11107 unsigned long hva, old_npages; 11108 struct kvm_memslots *slots = kvm_memslots(kvm); 11109 struct kvm_memory_slot *slot; 11110 11111 /* Called with kvm->slots_lock held. */ 11112 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 11113 return ERR_PTR_USR(-EINVAL); 11114 11115 slot = id_to_memslot(slots, id); 11116 if (size) { 11117 if (slot && slot->npages) 11118 return ERR_PTR_USR(-EEXIST); 11119 11120 /* 11121 * MAP_SHARED to prevent internal slot pages from being moved 11122 * by fork()/COW. 11123 */ 11124 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 11125 MAP_SHARED | MAP_ANONYMOUS, 0); 11126 if (IS_ERR((void *)hva)) 11127 return (void __user *)hva; 11128 } else { 11129 if (!slot || !slot->npages) 11130 return NULL; 11131 11132 old_npages = slot->npages; 11133 hva = slot->userspace_addr; 11134 } 11135 11136 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 11137 struct kvm_userspace_memory_region m; 11138 11139 m.slot = id | (i << 16); 11140 m.flags = 0; 11141 m.guest_phys_addr = gpa; 11142 m.userspace_addr = hva; 11143 m.memory_size = size; 11144 r = __kvm_set_memory_region(kvm, &m); 11145 if (r < 0) 11146 return ERR_PTR_USR(r); 11147 } 11148 11149 if (!size) 11150 vm_munmap(hva, old_npages * PAGE_SIZE); 11151 11152 return (void __user *)hva; 11153 } 11154 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 11155 11156 void kvm_arch_pre_destroy_vm(struct kvm *kvm) 11157 { 11158 kvm_mmu_pre_destroy_vm(kvm); 11159 } 11160 11161 void kvm_arch_destroy_vm(struct kvm *kvm) 11162 { 11163 if (current->mm == kvm->mm) { 11164 /* 11165 * Free memory regions allocated on behalf of userspace, 11166 * unless the the memory map has changed due to process exit 11167 * or fd copying. 11168 */ 11169 mutex_lock(&kvm->slots_lock); 11170 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 11171 0, 0); 11172 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 11173 0, 0); 11174 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 11175 mutex_unlock(&kvm->slots_lock); 11176 } 11177 static_call_cond(kvm_x86_vm_destroy)(kvm); 11178 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); 11179 kvm_pic_destroy(kvm); 11180 kvm_ioapic_destroy(kvm); 11181 kvm_free_vcpus(kvm); 11182 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 11183 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); 11184 kvm_mmu_uninit_vm(kvm); 11185 kvm_page_track_cleanup(kvm); 11186 kvm_xen_destroy_vm(kvm); 11187 kvm_hv_destroy_vm(kvm); 11188 } 11189 11190 static void memslot_rmap_free(struct kvm_memory_slot *slot) 11191 { 11192 int i; 11193 11194 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 11195 kvfree(slot->arch.rmap[i]); 11196 slot->arch.rmap[i] = NULL; 11197 } 11198 } 11199 11200 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) 11201 { 11202 int i; 11203 11204 memslot_rmap_free(slot); 11205 11206 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 11207 kvfree(slot->arch.lpage_info[i - 1]); 11208 slot->arch.lpage_info[i - 1] = NULL; 11209 } 11210 11211 kvm_page_track_free_memslot(slot); 11212 } 11213 11214 static int memslot_rmap_alloc(struct kvm_memory_slot *slot, 11215 unsigned long npages) 11216 { 11217 const int sz = sizeof(*slot->arch.rmap[0]); 11218 int i; 11219 11220 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 11221 int level = i + 1; 11222 int lpages = __kvm_mmu_slot_lpages(slot, npages, level); 11223 11224 if (slot->arch.rmap[i]) 11225 continue; 11226 11227 slot->arch.rmap[i] = kvcalloc(lpages, sz, GFP_KERNEL_ACCOUNT); 11228 if (!slot->arch.rmap[i]) { 11229 memslot_rmap_free(slot); 11230 return -ENOMEM; 11231 } 11232 } 11233 11234 return 0; 11235 } 11236 11237 int alloc_all_memslots_rmaps(struct kvm *kvm) 11238 { 11239 struct kvm_memslots *slots; 11240 struct kvm_memory_slot *slot; 11241 int r, i; 11242 11243 /* 11244 * Check if memslots alreday have rmaps early before acquiring 11245 * the slots_arch_lock below. 11246 */ 11247 if (kvm_memslots_have_rmaps(kvm)) 11248 return 0; 11249 11250 mutex_lock(&kvm->slots_arch_lock); 11251 11252 /* 11253 * Read memslots_have_rmaps again, under the slots arch lock, 11254 * before allocating the rmaps 11255 */ 11256 if (kvm_memslots_have_rmaps(kvm)) { 11257 mutex_unlock(&kvm->slots_arch_lock); 11258 return 0; 11259 } 11260 11261 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 11262 slots = __kvm_memslots(kvm, i); 11263 kvm_for_each_memslot(slot, slots) { 11264 r = memslot_rmap_alloc(slot, slot->npages); 11265 if (r) { 11266 mutex_unlock(&kvm->slots_arch_lock); 11267 return r; 11268 } 11269 } 11270 } 11271 11272 /* 11273 * Ensure that memslots_have_rmaps becomes true strictly after 11274 * all the rmap pointers are set. 11275 */ 11276 smp_store_release(&kvm->arch.memslots_have_rmaps, true); 11277 mutex_unlock(&kvm->slots_arch_lock); 11278 return 0; 11279 } 11280 11281 static int kvm_alloc_memslot_metadata(struct kvm *kvm, 11282 struct kvm_memory_slot *slot, 11283 unsigned long npages) 11284 { 11285 int i, r; 11286 11287 /* 11288 * Clear out the previous array pointers for the KVM_MR_MOVE case. The 11289 * old arrays will be freed by __kvm_set_memory_region() if installing 11290 * the new memslot is successful. 11291 */ 11292 memset(&slot->arch, 0, sizeof(slot->arch)); 11293 11294 if (kvm_memslots_have_rmaps(kvm)) { 11295 r = memslot_rmap_alloc(slot, npages); 11296 if (r) 11297 return r; 11298 } 11299 11300 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 11301 struct kvm_lpage_info *linfo; 11302 unsigned long ugfn; 11303 int lpages; 11304 int level = i + 1; 11305 11306 lpages = __kvm_mmu_slot_lpages(slot, npages, level); 11307 11308 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 11309 if (!linfo) 11310 goto out_free; 11311 11312 slot->arch.lpage_info[i - 1] = linfo; 11313 11314 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 11315 linfo[0].disallow_lpage = 1; 11316 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 11317 linfo[lpages - 1].disallow_lpage = 1; 11318 ugfn = slot->userspace_addr >> PAGE_SHIFT; 11319 /* 11320 * If the gfn and userspace address are not aligned wrt each 11321 * other, disable large page support for this slot. 11322 */ 11323 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { 11324 unsigned long j; 11325 11326 for (j = 0; j < lpages; ++j) 11327 linfo[j].disallow_lpage = 1; 11328 } 11329 } 11330 11331 if (kvm_page_track_create_memslot(slot, npages)) 11332 goto out_free; 11333 11334 return 0; 11335 11336 out_free: 11337 memslot_rmap_free(slot); 11338 11339 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 11340 kvfree(slot->arch.lpage_info[i - 1]); 11341 slot->arch.lpage_info[i - 1] = NULL; 11342 } 11343 return -ENOMEM; 11344 } 11345 11346 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 11347 { 11348 struct kvm_vcpu *vcpu; 11349 int i; 11350 11351 /* 11352 * memslots->generation has been incremented. 11353 * mmio generation may have reached its maximum value. 11354 */ 11355 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 11356 11357 /* Force re-initialization of steal_time cache */ 11358 kvm_for_each_vcpu(i, vcpu, kvm) 11359 kvm_vcpu_kick(vcpu); 11360 } 11361 11362 int kvm_arch_prepare_memory_region(struct kvm *kvm, 11363 struct kvm_memory_slot *memslot, 11364 const struct kvm_userspace_memory_region *mem, 11365 enum kvm_mr_change change) 11366 { 11367 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) 11368 return kvm_alloc_memslot_metadata(kvm, memslot, 11369 mem->memory_size >> PAGE_SHIFT); 11370 return 0; 11371 } 11372 11373 11374 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) 11375 { 11376 struct kvm_arch *ka = &kvm->arch; 11377 11378 if (!kvm_x86_ops.cpu_dirty_log_size) 11379 return; 11380 11381 if ((enable && ++ka->cpu_dirty_logging_count == 1) || 11382 (!enable && --ka->cpu_dirty_logging_count == 0)) 11383 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); 11384 11385 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); 11386 } 11387 11388 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 11389 struct kvm_memory_slot *old, 11390 const struct kvm_memory_slot *new, 11391 enum kvm_mr_change change) 11392 { 11393 bool log_dirty_pages = new->flags & KVM_MEM_LOG_DIRTY_PAGES; 11394 11395 /* 11396 * Update CPU dirty logging if dirty logging is being toggled. This 11397 * applies to all operations. 11398 */ 11399 if ((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES) 11400 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); 11401 11402 /* 11403 * Nothing more to do for RO slots (which can't be dirtied and can't be 11404 * made writable) or CREATE/MOVE/DELETE of a slot. 11405 * 11406 * For a memslot with dirty logging disabled: 11407 * CREATE: No dirty mappings will already exist. 11408 * MOVE/DELETE: The old mappings will already have been cleaned up by 11409 * kvm_arch_flush_shadow_memslot() 11410 * 11411 * For a memslot with dirty logging enabled: 11412 * CREATE: No shadow pages exist, thus nothing to write-protect 11413 * and no dirty bits to clear. 11414 * MOVE/DELETE: The old mappings will already have been cleaned up by 11415 * kvm_arch_flush_shadow_memslot(). 11416 */ 11417 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) 11418 return; 11419 11420 /* 11421 * READONLY and non-flags changes were filtered out above, and the only 11422 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty 11423 * logging isn't being toggled on or off. 11424 */ 11425 if (WARN_ON_ONCE(!((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES))) 11426 return; 11427 11428 if (!log_dirty_pages) { 11429 /* 11430 * Dirty logging tracks sptes in 4k granularity, meaning that 11431 * large sptes have to be split. If live migration succeeds, 11432 * the guest in the source machine will be destroyed and large 11433 * sptes will be created in the destination. However, if the 11434 * guest continues to run in the source machine (for example if 11435 * live migration fails), small sptes will remain around and 11436 * cause bad performance. 11437 * 11438 * Scan sptes if dirty logging has been stopped, dropping those 11439 * which can be collapsed into a single large-page spte. Later 11440 * page faults will create the large-page sptes. 11441 */ 11442 kvm_mmu_zap_collapsible_sptes(kvm, new); 11443 } else { 11444 /* 11445 * Initially-all-set does not require write protecting any page, 11446 * because they're all assumed to be dirty. 11447 */ 11448 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) 11449 return; 11450 11451 if (kvm_x86_ops.cpu_dirty_log_size) { 11452 kvm_mmu_slot_leaf_clear_dirty(kvm, new); 11453 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M); 11454 } else { 11455 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K); 11456 } 11457 } 11458 } 11459 11460 void kvm_arch_commit_memory_region(struct kvm *kvm, 11461 const struct kvm_userspace_memory_region *mem, 11462 struct kvm_memory_slot *old, 11463 const struct kvm_memory_slot *new, 11464 enum kvm_mr_change change) 11465 { 11466 if (!kvm->arch.n_requested_mmu_pages) 11467 kvm_mmu_change_mmu_pages(kvm, 11468 kvm_mmu_calculate_default_mmu_pages(kvm)); 11469 11470 kvm_mmu_slot_apply_flags(kvm, old, new, change); 11471 11472 /* Free the arrays associated with the old memslot. */ 11473 if (change == KVM_MR_MOVE) 11474 kvm_arch_free_memslot(kvm, old); 11475 } 11476 11477 void kvm_arch_flush_shadow_all(struct kvm *kvm) 11478 { 11479 kvm_mmu_zap_all(kvm); 11480 } 11481 11482 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 11483 struct kvm_memory_slot *slot) 11484 { 11485 kvm_page_track_flush_slot(kvm, slot); 11486 } 11487 11488 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 11489 { 11490 return (is_guest_mode(vcpu) && 11491 kvm_x86_ops.guest_apic_has_interrupt && 11492 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); 11493 } 11494 11495 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 11496 { 11497 if (!list_empty_careful(&vcpu->async_pf.done)) 11498 return true; 11499 11500 if (kvm_apic_has_events(vcpu)) 11501 return true; 11502 11503 if (vcpu->arch.pv.pv_unhalted) 11504 return true; 11505 11506 if (vcpu->arch.exception.pending) 11507 return true; 11508 11509 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 11510 (vcpu->arch.nmi_pending && 11511 static_call(kvm_x86_nmi_allowed)(vcpu, false))) 11512 return true; 11513 11514 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 11515 (vcpu->arch.smi_pending && 11516 static_call(kvm_x86_smi_allowed)(vcpu, false))) 11517 return true; 11518 11519 if (kvm_arch_interrupt_allowed(vcpu) && 11520 (kvm_cpu_has_interrupt(vcpu) || 11521 kvm_guest_apic_has_interrupt(vcpu))) 11522 return true; 11523 11524 if (kvm_hv_has_stimer_pending(vcpu)) 11525 return true; 11526 11527 if (is_guest_mode(vcpu) && 11528 kvm_x86_ops.nested_ops->hv_timer_pending && 11529 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 11530 return true; 11531 11532 return false; 11533 } 11534 11535 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 11536 { 11537 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 11538 } 11539 11540 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) 11541 { 11542 if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) 11543 return true; 11544 11545 return false; 11546 } 11547 11548 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) 11549 { 11550 if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) 11551 return true; 11552 11553 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 11554 kvm_test_request(KVM_REQ_SMI, vcpu) || 11555 kvm_test_request(KVM_REQ_EVENT, vcpu)) 11556 return true; 11557 11558 return kvm_arch_dy_has_pending_interrupt(vcpu); 11559 } 11560 11561 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 11562 { 11563 if (vcpu->arch.guest_state_protected) 11564 return true; 11565 11566 return vcpu->arch.preempted_in_kernel; 11567 } 11568 11569 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 11570 { 11571 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 11572 } 11573 11574 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 11575 { 11576 return static_call(kvm_x86_interrupt_allowed)(vcpu, false); 11577 } 11578 11579 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 11580 { 11581 /* Can't read the RIP when guest state is protected, just return 0 */ 11582 if (vcpu->arch.guest_state_protected) 11583 return 0; 11584 11585 if (is_64_bit_mode(vcpu)) 11586 return kvm_rip_read(vcpu); 11587 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 11588 kvm_rip_read(vcpu)); 11589 } 11590 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 11591 11592 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 11593 { 11594 return kvm_get_linear_rip(vcpu) == linear_rip; 11595 } 11596 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 11597 11598 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 11599 { 11600 unsigned long rflags; 11601 11602 rflags = static_call(kvm_x86_get_rflags)(vcpu); 11603 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 11604 rflags &= ~X86_EFLAGS_TF; 11605 return rflags; 11606 } 11607 EXPORT_SYMBOL_GPL(kvm_get_rflags); 11608 11609 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 11610 { 11611 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 11612 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 11613 rflags |= X86_EFLAGS_TF; 11614 static_call(kvm_x86_set_rflags)(vcpu, rflags); 11615 } 11616 11617 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 11618 { 11619 __kvm_set_rflags(vcpu, rflags); 11620 kvm_make_request(KVM_REQ_EVENT, vcpu); 11621 } 11622 EXPORT_SYMBOL_GPL(kvm_set_rflags); 11623 11624 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 11625 { 11626 int r; 11627 11628 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || 11629 work->wakeup_all) 11630 return; 11631 11632 r = kvm_mmu_reload(vcpu); 11633 if (unlikely(r)) 11634 return; 11635 11636 if (!vcpu->arch.mmu->direct_map && 11637 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) 11638 return; 11639 11640 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); 11641 } 11642 11643 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 11644 { 11645 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); 11646 11647 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 11648 } 11649 11650 static inline u32 kvm_async_pf_next_probe(u32 key) 11651 { 11652 return (key + 1) & (ASYNC_PF_PER_VCPU - 1); 11653 } 11654 11655 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11656 { 11657 u32 key = kvm_async_pf_hash_fn(gfn); 11658 11659 while (vcpu->arch.apf.gfns[key] != ~0) 11660 key = kvm_async_pf_next_probe(key); 11661 11662 vcpu->arch.apf.gfns[key] = gfn; 11663 } 11664 11665 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 11666 { 11667 int i; 11668 u32 key = kvm_async_pf_hash_fn(gfn); 11669 11670 for (i = 0; i < ASYNC_PF_PER_VCPU && 11671 (vcpu->arch.apf.gfns[key] != gfn && 11672 vcpu->arch.apf.gfns[key] != ~0); i++) 11673 key = kvm_async_pf_next_probe(key); 11674 11675 return key; 11676 } 11677 11678 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11679 { 11680 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 11681 } 11682 11683 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11684 { 11685 u32 i, j, k; 11686 11687 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 11688 11689 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) 11690 return; 11691 11692 while (true) { 11693 vcpu->arch.apf.gfns[i] = ~0; 11694 do { 11695 j = kvm_async_pf_next_probe(j); 11696 if (vcpu->arch.apf.gfns[j] == ~0) 11697 return; 11698 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 11699 /* 11700 * k lies cyclically in ]i,j] 11701 * | i.k.j | 11702 * |....j i.k.| or |.k..j i...| 11703 */ 11704 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 11705 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 11706 i = j; 11707 } 11708 } 11709 11710 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) 11711 { 11712 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; 11713 11714 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, 11715 sizeof(reason)); 11716 } 11717 11718 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) 11719 { 11720 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 11721 11722 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 11723 &token, offset, sizeof(token)); 11724 } 11725 11726 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) 11727 { 11728 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 11729 u32 val; 11730 11731 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 11732 &val, offset, sizeof(val))) 11733 return false; 11734 11735 return !val; 11736 } 11737 11738 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) 11739 { 11740 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) 11741 return false; 11742 11743 if (!kvm_pv_async_pf_enabled(vcpu) || 11744 (vcpu->arch.apf.send_user_only && static_call(kvm_x86_get_cpl)(vcpu) == 0)) 11745 return false; 11746 11747 return true; 11748 } 11749 11750 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) 11751 { 11752 if (unlikely(!lapic_in_kernel(vcpu) || 11753 kvm_event_needs_reinjection(vcpu) || 11754 vcpu->arch.exception.pending)) 11755 return false; 11756 11757 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) 11758 return false; 11759 11760 /* 11761 * If interrupts are off we cannot even use an artificial 11762 * halt state. 11763 */ 11764 return kvm_arch_interrupt_allowed(vcpu); 11765 } 11766 11767 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 11768 struct kvm_async_pf *work) 11769 { 11770 struct x86_exception fault; 11771 11772 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); 11773 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 11774 11775 if (kvm_can_deliver_async_pf(vcpu) && 11776 !apf_put_user_notpresent(vcpu)) { 11777 fault.vector = PF_VECTOR; 11778 fault.error_code_valid = true; 11779 fault.error_code = 0; 11780 fault.nested_page_fault = false; 11781 fault.address = work->arch.token; 11782 fault.async_page_fault = true; 11783 kvm_inject_page_fault(vcpu, &fault); 11784 return true; 11785 } else { 11786 /* 11787 * It is not possible to deliver a paravirtualized asynchronous 11788 * page fault, but putting the guest in an artificial halt state 11789 * can be beneficial nevertheless: if an interrupt arrives, we 11790 * can deliver it timely and perhaps the guest will schedule 11791 * another process. When the instruction that triggered a page 11792 * fault is retried, hopefully the page will be ready in the host. 11793 */ 11794 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 11795 return false; 11796 } 11797 } 11798 11799 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 11800 struct kvm_async_pf *work) 11801 { 11802 struct kvm_lapic_irq irq = { 11803 .delivery_mode = APIC_DM_FIXED, 11804 .vector = vcpu->arch.apf.vec 11805 }; 11806 11807 if (work->wakeup_all) 11808 work->arch.token = ~0; /* broadcast wakeup */ 11809 else 11810 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 11811 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); 11812 11813 if ((work->wakeup_all || work->notpresent_injected) && 11814 kvm_pv_async_pf_enabled(vcpu) && 11815 !apf_put_user_ready(vcpu, work->arch.token)) { 11816 vcpu->arch.apf.pageready_pending = true; 11817 kvm_apic_set_irq(vcpu, &irq, NULL); 11818 } 11819 11820 vcpu->arch.apf.halted = false; 11821 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 11822 } 11823 11824 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) 11825 { 11826 kvm_make_request(KVM_REQ_APF_READY, vcpu); 11827 if (!vcpu->arch.apf.pageready_pending) 11828 kvm_vcpu_kick(vcpu); 11829 } 11830 11831 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) 11832 { 11833 if (!kvm_pv_async_pf_enabled(vcpu)) 11834 return true; 11835 else 11836 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); 11837 } 11838 11839 void kvm_arch_start_assignment(struct kvm *kvm) 11840 { 11841 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) 11842 static_call_cond(kvm_x86_start_assignment)(kvm); 11843 } 11844 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 11845 11846 void kvm_arch_end_assignment(struct kvm *kvm) 11847 { 11848 atomic_dec(&kvm->arch.assigned_device_count); 11849 } 11850 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 11851 11852 bool kvm_arch_has_assigned_device(struct kvm *kvm) 11853 { 11854 return atomic_read(&kvm->arch.assigned_device_count); 11855 } 11856 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 11857 11858 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 11859 { 11860 atomic_inc(&kvm->arch.noncoherent_dma_count); 11861 } 11862 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 11863 11864 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 11865 { 11866 atomic_dec(&kvm->arch.noncoherent_dma_count); 11867 } 11868 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 11869 11870 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 11871 { 11872 return atomic_read(&kvm->arch.noncoherent_dma_count); 11873 } 11874 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 11875 11876 bool kvm_arch_has_irq_bypass(void) 11877 { 11878 return true; 11879 } 11880 11881 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 11882 struct irq_bypass_producer *prod) 11883 { 11884 struct kvm_kernel_irqfd *irqfd = 11885 container_of(cons, struct kvm_kernel_irqfd, consumer); 11886 int ret; 11887 11888 irqfd->producer = prod; 11889 kvm_arch_start_assignment(irqfd->kvm); 11890 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, 11891 prod->irq, irqfd->gsi, 1); 11892 11893 if (ret) 11894 kvm_arch_end_assignment(irqfd->kvm); 11895 11896 return ret; 11897 } 11898 11899 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 11900 struct irq_bypass_producer *prod) 11901 { 11902 int ret; 11903 struct kvm_kernel_irqfd *irqfd = 11904 container_of(cons, struct kvm_kernel_irqfd, consumer); 11905 11906 WARN_ON(irqfd->producer != prod); 11907 irqfd->producer = NULL; 11908 11909 /* 11910 * When producer of consumer is unregistered, we change back to 11911 * remapped mode, so we can re-use the current implementation 11912 * when the irq is masked/disabled or the consumer side (KVM 11913 * int this case doesn't want to receive the interrupts. 11914 */ 11915 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); 11916 if (ret) 11917 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 11918 " fails: %d\n", irqfd->consumer.token, ret); 11919 11920 kvm_arch_end_assignment(irqfd->kvm); 11921 } 11922 11923 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 11924 uint32_t guest_irq, bool set) 11925 { 11926 return static_call(kvm_x86_update_pi_irte)(kvm, host_irq, guest_irq, set); 11927 } 11928 11929 bool kvm_vector_hashing_enabled(void) 11930 { 11931 return vector_hashing; 11932 } 11933 11934 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) 11935 { 11936 return (vcpu->arch.msr_kvm_poll_control & 1) == 0; 11937 } 11938 EXPORT_SYMBOL_GPL(kvm_arch_no_poll); 11939 11940 11941 int kvm_spec_ctrl_test_value(u64 value) 11942 { 11943 /* 11944 * test that setting IA32_SPEC_CTRL to given value 11945 * is allowed by the host processor 11946 */ 11947 11948 u64 saved_value; 11949 unsigned long flags; 11950 int ret = 0; 11951 11952 local_irq_save(flags); 11953 11954 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) 11955 ret = 1; 11956 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) 11957 ret = 1; 11958 else 11959 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); 11960 11961 local_irq_restore(flags); 11962 11963 return ret; 11964 } 11965 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); 11966 11967 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) 11968 { 11969 struct x86_exception fault; 11970 u32 access = error_code & 11971 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); 11972 11973 if (!(error_code & PFERR_PRESENT_MASK) || 11974 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) { 11975 /* 11976 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page 11977 * tables probably do not match the TLB. Just proceed 11978 * with the error code that the processor gave. 11979 */ 11980 fault.vector = PF_VECTOR; 11981 fault.error_code_valid = true; 11982 fault.error_code = error_code; 11983 fault.nested_page_fault = false; 11984 fault.address = gva; 11985 } 11986 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); 11987 } 11988 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); 11989 11990 /* 11991 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns 11992 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value 11993 * indicates whether exit to userspace is needed. 11994 */ 11995 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 11996 struct x86_exception *e) 11997 { 11998 if (r == X86EMUL_PROPAGATE_FAULT) { 11999 kvm_inject_emulated_page_fault(vcpu, e); 12000 return 1; 12001 } 12002 12003 /* 12004 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED 12005 * while handling a VMX instruction KVM could've handled the request 12006 * correctly by exiting to userspace and performing I/O but there 12007 * doesn't seem to be a real use-case behind such requests, just return 12008 * KVM_EXIT_INTERNAL_ERROR for now. 12009 */ 12010 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 12011 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 12012 vcpu->run->internal.ndata = 0; 12013 12014 return 0; 12015 } 12016 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); 12017 12018 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) 12019 { 12020 bool pcid_enabled; 12021 struct x86_exception e; 12022 struct { 12023 u64 pcid; 12024 u64 gla; 12025 } operand; 12026 int r; 12027 12028 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 12029 if (r != X86EMUL_CONTINUE) 12030 return kvm_handle_memory_failure(vcpu, r, &e); 12031 12032 if (operand.pcid >> 12 != 0) { 12033 kvm_inject_gp(vcpu, 0); 12034 return 1; 12035 } 12036 12037 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 12038 12039 switch (type) { 12040 case INVPCID_TYPE_INDIV_ADDR: 12041 if ((!pcid_enabled && (operand.pcid != 0)) || 12042 is_noncanonical_address(operand.gla, vcpu)) { 12043 kvm_inject_gp(vcpu, 0); 12044 return 1; 12045 } 12046 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 12047 return kvm_skip_emulated_instruction(vcpu); 12048 12049 case INVPCID_TYPE_SINGLE_CTXT: 12050 if (!pcid_enabled && (operand.pcid != 0)) { 12051 kvm_inject_gp(vcpu, 0); 12052 return 1; 12053 } 12054 12055 kvm_invalidate_pcid(vcpu, operand.pcid); 12056 return kvm_skip_emulated_instruction(vcpu); 12057 12058 case INVPCID_TYPE_ALL_NON_GLOBAL: 12059 /* 12060 * Currently, KVM doesn't mark global entries in the shadow 12061 * page tables, so a non-global flush just degenerates to a 12062 * global flush. If needed, we could optimize this later by 12063 * keeping track of global entries in shadow page tables. 12064 */ 12065 12066 fallthrough; 12067 case INVPCID_TYPE_ALL_INCL_GLOBAL: 12068 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 12069 return kvm_skip_emulated_instruction(vcpu); 12070 12071 default: 12072 BUG(); /* We have already checked above that type <= 3 */ 12073 } 12074 } 12075 EXPORT_SYMBOL_GPL(kvm_handle_invpcid); 12076 12077 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) 12078 { 12079 struct kvm_run *run = vcpu->run; 12080 struct kvm_mmio_fragment *frag; 12081 unsigned int len; 12082 12083 BUG_ON(!vcpu->mmio_needed); 12084 12085 /* Complete previous fragment */ 12086 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 12087 len = min(8u, frag->len); 12088 if (!vcpu->mmio_is_write) 12089 memcpy(frag->data, run->mmio.data, len); 12090 12091 if (frag->len <= 8) { 12092 /* Switch to the next fragment. */ 12093 frag++; 12094 vcpu->mmio_cur_fragment++; 12095 } else { 12096 /* Go forward to the next mmio piece. */ 12097 frag->data += len; 12098 frag->gpa += len; 12099 frag->len -= len; 12100 } 12101 12102 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 12103 vcpu->mmio_needed = 0; 12104 12105 // VMG change, at this point, we're always done 12106 // RIP has already been advanced 12107 return 1; 12108 } 12109 12110 // More MMIO is needed 12111 run->mmio.phys_addr = frag->gpa; 12112 run->mmio.len = min(8u, frag->len); 12113 run->mmio.is_write = vcpu->mmio_is_write; 12114 if (run->mmio.is_write) 12115 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 12116 run->exit_reason = KVM_EXIT_MMIO; 12117 12118 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12119 12120 return 0; 12121 } 12122 12123 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 12124 void *data) 12125 { 12126 int handled; 12127 struct kvm_mmio_fragment *frag; 12128 12129 if (!data) 12130 return -EINVAL; 12131 12132 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); 12133 if (handled == bytes) 12134 return 1; 12135 12136 bytes -= handled; 12137 gpa += handled; 12138 data += handled; 12139 12140 /*TODO: Check if need to increment number of frags */ 12141 frag = vcpu->mmio_fragments; 12142 vcpu->mmio_nr_fragments = 1; 12143 frag->len = bytes; 12144 frag->gpa = gpa; 12145 frag->data = data; 12146 12147 vcpu->mmio_needed = 1; 12148 vcpu->mmio_cur_fragment = 0; 12149 12150 vcpu->run->mmio.phys_addr = gpa; 12151 vcpu->run->mmio.len = min(8u, frag->len); 12152 vcpu->run->mmio.is_write = 1; 12153 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 12154 vcpu->run->exit_reason = KVM_EXIT_MMIO; 12155 12156 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12157 12158 return 0; 12159 } 12160 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); 12161 12162 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 12163 void *data) 12164 { 12165 int handled; 12166 struct kvm_mmio_fragment *frag; 12167 12168 if (!data) 12169 return -EINVAL; 12170 12171 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); 12172 if (handled == bytes) 12173 return 1; 12174 12175 bytes -= handled; 12176 gpa += handled; 12177 data += handled; 12178 12179 /*TODO: Check if need to increment number of frags */ 12180 frag = vcpu->mmio_fragments; 12181 vcpu->mmio_nr_fragments = 1; 12182 frag->len = bytes; 12183 frag->gpa = gpa; 12184 frag->data = data; 12185 12186 vcpu->mmio_needed = 1; 12187 vcpu->mmio_cur_fragment = 0; 12188 12189 vcpu->run->mmio.phys_addr = gpa; 12190 vcpu->run->mmio.len = min(8u, frag->len); 12191 vcpu->run->mmio.is_write = 0; 12192 vcpu->run->exit_reason = KVM_EXIT_MMIO; 12193 12194 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12195 12196 return 0; 12197 } 12198 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); 12199 12200 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 12201 unsigned int port); 12202 12203 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu) 12204 { 12205 int size = vcpu->arch.pio.size; 12206 int port = vcpu->arch.pio.port; 12207 12208 vcpu->arch.pio.count = 0; 12209 if (vcpu->arch.sev_pio_count) 12210 return kvm_sev_es_outs(vcpu, size, port); 12211 return 1; 12212 } 12213 12214 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 12215 unsigned int port) 12216 { 12217 for (;;) { 12218 unsigned int count = 12219 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 12220 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count); 12221 12222 /* memcpy done already by emulator_pio_out. */ 12223 vcpu->arch.sev_pio_count -= count; 12224 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size; 12225 if (!ret) 12226 break; 12227 12228 /* Emulation done by the kernel. */ 12229 if (!vcpu->arch.sev_pio_count) 12230 return 1; 12231 } 12232 12233 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs; 12234 return 0; 12235 } 12236 12237 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 12238 unsigned int port); 12239 12240 static void advance_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 12241 { 12242 unsigned count = vcpu->arch.pio.count; 12243 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data); 12244 vcpu->arch.sev_pio_count -= count; 12245 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size; 12246 } 12247 12248 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 12249 { 12250 int size = vcpu->arch.pio.size; 12251 int port = vcpu->arch.pio.port; 12252 12253 advance_sev_es_emulated_ins(vcpu); 12254 if (vcpu->arch.sev_pio_count) 12255 return kvm_sev_es_ins(vcpu, size, port); 12256 return 1; 12257 } 12258 12259 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 12260 unsigned int port) 12261 { 12262 for (;;) { 12263 unsigned int count = 12264 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 12265 if (!__emulator_pio_in(vcpu, size, port, count)) 12266 break; 12267 12268 /* Emulation done by the kernel. */ 12269 advance_sev_es_emulated_ins(vcpu); 12270 if (!vcpu->arch.sev_pio_count) 12271 return 1; 12272 } 12273 12274 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; 12275 return 0; 12276 } 12277 12278 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 12279 unsigned int port, void *data, unsigned int count, 12280 int in) 12281 { 12282 vcpu->arch.sev_pio_data = data; 12283 vcpu->arch.sev_pio_count = count; 12284 return in ? kvm_sev_es_ins(vcpu, size, port) 12285 : kvm_sev_es_outs(vcpu, size, port); 12286 } 12287 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); 12288 12289 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); 12290 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 12291 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 12292 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 12293 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 12294 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 12295 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 12296 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 12297 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 12298 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 12299 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 12300 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); 12301 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 12302 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 12303 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 12304 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 12305 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); 12306 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 12307 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 12308 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 12309 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 12310 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); 12311 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); 12312 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); 12313 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); 12314 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); 12315 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); 12316