1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * derived from drivers/kvm/kvm_main.c 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright (C) 2008 Qumranet, Inc. 9 * Copyright IBM Corporation, 2008 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 11 * 12 * Authors: 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * Amit Shah <amit.shah@qumranet.com> 16 * Ben-Ami Yassour <benami@il.ibm.com> 17 */ 18 19 #include <linux/kvm_host.h> 20 #include "irq.h" 21 #include "mmu.h" 22 #include "i8254.h" 23 #include "tss.h" 24 #include "kvm_cache_regs.h" 25 #include "kvm_emulate.h" 26 #include "x86.h" 27 #include "cpuid.h" 28 #include "pmu.h" 29 #include "hyperv.h" 30 #include "lapic.h" 31 32 #include <linux/clocksource.h> 33 #include <linux/interrupt.h> 34 #include <linux/kvm.h> 35 #include <linux/fs.h> 36 #include <linux/vmalloc.h> 37 #include <linux/export.h> 38 #include <linux/moduleparam.h> 39 #include <linux/mman.h> 40 #include <linux/highmem.h> 41 #include <linux/iommu.h> 42 #include <linux/intel-iommu.h> 43 #include <linux/cpufreq.h> 44 #include <linux/user-return-notifier.h> 45 #include <linux/srcu.h> 46 #include <linux/slab.h> 47 #include <linux/perf_event.h> 48 #include <linux/uaccess.h> 49 #include <linux/hash.h> 50 #include <linux/pci.h> 51 #include <linux/timekeeper_internal.h> 52 #include <linux/pvclock_gtod.h> 53 #include <linux/kvm_irqfd.h> 54 #include <linux/irqbypass.h> 55 #include <linux/sched/stat.h> 56 #include <linux/sched/isolation.h> 57 #include <linux/mem_encrypt.h> 58 59 #include <trace/events/kvm.h> 60 61 #include <asm/debugreg.h> 62 #include <asm/msr.h> 63 #include <asm/desc.h> 64 #include <asm/mce.h> 65 #include <linux/kernel_stat.h> 66 #include <asm/fpu/internal.h> /* Ugh! */ 67 #include <asm/pvclock.h> 68 #include <asm/div64.h> 69 #include <asm/irq_remapping.h> 70 #include <asm/mshyperv.h> 71 #include <asm/hypervisor.h> 72 #include <asm/intel_pt.h> 73 #include <asm/emulate_prefix.h> 74 #include <clocksource/hyperv_timer.h> 75 76 #define CREATE_TRACE_POINTS 77 #include "trace.h" 78 79 #define MAX_IO_MSRS 256 80 #define KVM_MAX_MCE_BANKS 32 81 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 82 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 83 84 #define emul_to_vcpu(ctxt) \ 85 ((struct kvm_vcpu *)(ctxt)->vcpu) 86 87 /* EFER defaults: 88 * - enable syscall per default because its emulated by KVM 89 * - enable LME and LMA per default on 64 bit KVM 90 */ 91 #ifdef CONFIG_X86_64 92 static 93 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 94 #else 95 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 96 #endif 97 98 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; 99 100 #define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__ 101 #define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__ 102 103 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 104 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 105 106 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 107 static void process_nmi(struct kvm_vcpu *vcpu); 108 static void enter_smm(struct kvm_vcpu *vcpu); 109 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 110 static void store_regs(struct kvm_vcpu *vcpu); 111 static int sync_regs(struct kvm_vcpu *vcpu); 112 113 struct kvm_x86_ops kvm_x86_ops __read_mostly; 114 EXPORT_SYMBOL_GPL(kvm_x86_ops); 115 116 static bool __read_mostly ignore_msrs = 0; 117 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 118 119 static bool __read_mostly report_ignored_msrs = true; 120 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 121 122 unsigned int min_timer_period_us = 200; 123 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 124 125 static bool __read_mostly kvmclock_periodic_sync = true; 126 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 127 128 bool __read_mostly kvm_has_tsc_control; 129 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 130 u32 __read_mostly kvm_max_guest_tsc_khz; 131 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 132 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 133 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 134 u64 __read_mostly kvm_max_tsc_scaling_ratio; 135 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 136 u64 __read_mostly kvm_default_tsc_scaling_ratio; 137 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 138 139 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 140 static u32 __read_mostly tsc_tolerance_ppm = 250; 141 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 142 143 /* 144 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 145 * adaptive tuning starting from default advancment of 1000ns. '0' disables 146 * advancement entirely. Any other value is used as-is and disables adaptive 147 * tuning, i.e. allows priveleged userspace to set an exact advancement time. 148 */ 149 static int __read_mostly lapic_timer_advance_ns = -1; 150 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); 151 152 static bool __read_mostly vector_hashing = true; 153 module_param(vector_hashing, bool, S_IRUGO); 154 155 bool __read_mostly enable_vmware_backdoor = false; 156 module_param(enable_vmware_backdoor, bool, S_IRUGO); 157 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 158 159 static bool __read_mostly force_emulation_prefix = false; 160 module_param(force_emulation_prefix, bool, S_IRUGO); 161 162 int __read_mostly pi_inject_timer = -1; 163 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); 164 165 #define KVM_NR_SHARED_MSRS 16 166 167 struct kvm_shared_msrs_global { 168 int nr; 169 u32 msrs[KVM_NR_SHARED_MSRS]; 170 }; 171 172 struct kvm_shared_msrs { 173 struct user_return_notifier urn; 174 bool registered; 175 struct kvm_shared_msr_values { 176 u64 host; 177 u64 curr; 178 } values[KVM_NR_SHARED_MSRS]; 179 }; 180 181 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 182 static struct kvm_shared_msrs __percpu *shared_msrs; 183 184 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 185 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 186 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 187 | XFEATURE_MASK_PKRU) 188 189 u64 __read_mostly host_efer; 190 EXPORT_SYMBOL_GPL(host_efer); 191 192 static u64 __read_mostly host_xss; 193 u64 __read_mostly supported_xss; 194 EXPORT_SYMBOL_GPL(supported_xss); 195 196 struct kvm_stats_debugfs_item debugfs_entries[] = { 197 { "pf_fixed", VCPU_STAT(pf_fixed) }, 198 { "pf_guest", VCPU_STAT(pf_guest) }, 199 { "tlb_flush", VCPU_STAT(tlb_flush) }, 200 { "invlpg", VCPU_STAT(invlpg) }, 201 { "exits", VCPU_STAT(exits) }, 202 { "io_exits", VCPU_STAT(io_exits) }, 203 { "mmio_exits", VCPU_STAT(mmio_exits) }, 204 { "signal_exits", VCPU_STAT(signal_exits) }, 205 { "irq_window", VCPU_STAT(irq_window_exits) }, 206 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 207 { "halt_exits", VCPU_STAT(halt_exits) }, 208 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 209 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 210 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, 211 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 212 { "hypercalls", VCPU_STAT(hypercalls) }, 213 { "request_irq", VCPU_STAT(request_irq_exits) }, 214 { "irq_exits", VCPU_STAT(irq_exits) }, 215 { "host_state_reload", VCPU_STAT(host_state_reload) }, 216 { "fpu_reload", VCPU_STAT(fpu_reload) }, 217 { "insn_emulation", VCPU_STAT(insn_emulation) }, 218 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 219 { "irq_injections", VCPU_STAT(irq_injections) }, 220 { "nmi_injections", VCPU_STAT(nmi_injections) }, 221 { "req_event", VCPU_STAT(req_event) }, 222 { "l1d_flush", VCPU_STAT(l1d_flush) }, 223 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 224 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 225 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 226 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 227 { "mmu_flooded", VM_STAT(mmu_flooded) }, 228 { "mmu_recycled", VM_STAT(mmu_recycled) }, 229 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 230 { "mmu_unsync", VM_STAT(mmu_unsync) }, 231 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 232 { "largepages", VM_STAT(lpages, .mode = 0444) }, 233 { "nx_largepages_splitted", VM_STAT(nx_lpage_splits, .mode = 0444) }, 234 { "max_mmu_page_hash_collisions", 235 VM_STAT(max_mmu_page_hash_collisions) }, 236 { NULL } 237 }; 238 239 u64 __read_mostly host_xcr0; 240 u64 __read_mostly supported_xcr0; 241 EXPORT_SYMBOL_GPL(supported_xcr0); 242 243 struct kmem_cache *x86_fpu_cache; 244 EXPORT_SYMBOL_GPL(x86_fpu_cache); 245 246 static struct kmem_cache *x86_emulator_cache; 247 248 static struct kmem_cache *kvm_alloc_emulator_cache(void) 249 { 250 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); 251 unsigned int size = sizeof(struct x86_emulate_ctxt); 252 253 return kmem_cache_create_usercopy("x86_emulator", size, 254 __alignof__(struct x86_emulate_ctxt), 255 SLAB_ACCOUNT, useroffset, 256 size - useroffset, NULL); 257 } 258 259 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 260 261 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 262 { 263 int i; 264 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 265 vcpu->arch.apf.gfns[i] = ~0; 266 } 267 268 static void kvm_on_user_return(struct user_return_notifier *urn) 269 { 270 unsigned slot; 271 struct kvm_shared_msrs *locals 272 = container_of(urn, struct kvm_shared_msrs, urn); 273 struct kvm_shared_msr_values *values; 274 unsigned long flags; 275 276 /* 277 * Disabling irqs at this point since the following code could be 278 * interrupted and executed through kvm_arch_hardware_disable() 279 */ 280 local_irq_save(flags); 281 if (locals->registered) { 282 locals->registered = false; 283 user_return_notifier_unregister(urn); 284 } 285 local_irq_restore(flags); 286 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 287 values = &locals->values[slot]; 288 if (values->host != values->curr) { 289 wrmsrl(shared_msrs_global.msrs[slot], values->host); 290 values->curr = values->host; 291 } 292 } 293 } 294 295 void kvm_define_shared_msr(unsigned slot, u32 msr) 296 { 297 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 298 shared_msrs_global.msrs[slot] = msr; 299 if (slot >= shared_msrs_global.nr) 300 shared_msrs_global.nr = slot + 1; 301 } 302 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 303 304 static void kvm_shared_msr_cpu_online(void) 305 { 306 unsigned int cpu = smp_processor_id(); 307 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 308 u64 value; 309 int i; 310 311 for (i = 0; i < shared_msrs_global.nr; ++i) { 312 rdmsrl_safe(shared_msrs_global.msrs[i], &value); 313 smsr->values[i].host = value; 314 smsr->values[i].curr = value; 315 } 316 } 317 318 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 319 { 320 unsigned int cpu = smp_processor_id(); 321 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 322 int err; 323 324 value = (value & mask) | (smsr->values[slot].host & ~mask); 325 if (value == smsr->values[slot].curr) 326 return 0; 327 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 328 if (err) 329 return 1; 330 331 smsr->values[slot].curr = value; 332 if (!smsr->registered) { 333 smsr->urn.on_user_return = kvm_on_user_return; 334 user_return_notifier_register(&smsr->urn); 335 smsr->registered = true; 336 } 337 return 0; 338 } 339 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 340 341 static void drop_user_return_notifiers(void) 342 { 343 unsigned int cpu = smp_processor_id(); 344 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 345 346 if (smsr->registered) 347 kvm_on_user_return(&smsr->urn); 348 } 349 350 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 351 { 352 return vcpu->arch.apic_base; 353 } 354 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 355 356 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 357 { 358 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 359 } 360 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 361 362 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 363 { 364 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 365 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 366 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | 367 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 368 369 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 370 return 1; 371 if (!msr_info->host_initiated) { 372 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 373 return 1; 374 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 375 return 1; 376 } 377 378 kvm_lapic_set_base(vcpu, msr_info->data); 379 kvm_recalculate_apic_map(vcpu->kvm); 380 return 0; 381 } 382 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 383 384 asmlinkage __visible void kvm_spurious_fault(void) 385 { 386 /* Fault while not rebooting. We want the trace. */ 387 BUG_ON(!kvm_rebooting); 388 } 389 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 390 391 #define EXCPT_BENIGN 0 392 #define EXCPT_CONTRIBUTORY 1 393 #define EXCPT_PF 2 394 395 static int exception_class(int vector) 396 { 397 switch (vector) { 398 case PF_VECTOR: 399 return EXCPT_PF; 400 case DE_VECTOR: 401 case TS_VECTOR: 402 case NP_VECTOR: 403 case SS_VECTOR: 404 case GP_VECTOR: 405 return EXCPT_CONTRIBUTORY; 406 default: 407 break; 408 } 409 return EXCPT_BENIGN; 410 } 411 412 #define EXCPT_FAULT 0 413 #define EXCPT_TRAP 1 414 #define EXCPT_ABORT 2 415 #define EXCPT_INTERRUPT 3 416 417 static int exception_type(int vector) 418 { 419 unsigned int mask; 420 421 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 422 return EXCPT_INTERRUPT; 423 424 mask = 1 << vector; 425 426 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 427 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 428 return EXCPT_TRAP; 429 430 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 431 return EXCPT_ABORT; 432 433 /* Reserved exceptions will result in fault */ 434 return EXCPT_FAULT; 435 } 436 437 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 438 { 439 unsigned nr = vcpu->arch.exception.nr; 440 bool has_payload = vcpu->arch.exception.has_payload; 441 unsigned long payload = vcpu->arch.exception.payload; 442 443 if (!has_payload) 444 return; 445 446 switch (nr) { 447 case DB_VECTOR: 448 /* 449 * "Certain debug exceptions may clear bit 0-3. The 450 * remaining contents of the DR6 register are never 451 * cleared by the processor". 452 */ 453 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 454 /* 455 * DR6.RTM is set by all #DB exceptions that don't clear it. 456 */ 457 vcpu->arch.dr6 |= DR6_RTM; 458 vcpu->arch.dr6 |= payload; 459 /* 460 * Bit 16 should be set in the payload whenever the #DB 461 * exception should clear DR6.RTM. This makes the payload 462 * compatible with the pending debug exceptions under VMX. 463 * Though not currently documented in the SDM, this also 464 * makes the payload compatible with the exit qualification 465 * for #DB exceptions under VMX. 466 */ 467 vcpu->arch.dr6 ^= payload & DR6_RTM; 468 469 /* 470 * The #DB payload is defined as compatible with the 'pending 471 * debug exceptions' field under VMX, not DR6. While bit 12 is 472 * defined in the 'pending debug exceptions' field (enabled 473 * breakpoint), it is reserved and must be zero in DR6. 474 */ 475 vcpu->arch.dr6 &= ~BIT(12); 476 break; 477 case PF_VECTOR: 478 vcpu->arch.cr2 = payload; 479 break; 480 } 481 482 vcpu->arch.exception.has_payload = false; 483 vcpu->arch.exception.payload = 0; 484 } 485 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 486 487 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 488 unsigned nr, bool has_error, u32 error_code, 489 bool has_payload, unsigned long payload, bool reinject) 490 { 491 u32 prev_nr; 492 int class1, class2; 493 494 kvm_make_request(KVM_REQ_EVENT, vcpu); 495 496 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 497 queue: 498 if (has_error && !is_protmode(vcpu)) 499 has_error = false; 500 if (reinject) { 501 /* 502 * On vmentry, vcpu->arch.exception.pending is only 503 * true if an event injection was blocked by 504 * nested_run_pending. In that case, however, 505 * vcpu_enter_guest requests an immediate exit, 506 * and the guest shouldn't proceed far enough to 507 * need reinjection. 508 */ 509 WARN_ON_ONCE(vcpu->arch.exception.pending); 510 vcpu->arch.exception.injected = true; 511 if (WARN_ON_ONCE(has_payload)) { 512 /* 513 * A reinjected event has already 514 * delivered its payload. 515 */ 516 has_payload = false; 517 payload = 0; 518 } 519 } else { 520 vcpu->arch.exception.pending = true; 521 vcpu->arch.exception.injected = false; 522 } 523 vcpu->arch.exception.has_error_code = has_error; 524 vcpu->arch.exception.nr = nr; 525 vcpu->arch.exception.error_code = error_code; 526 vcpu->arch.exception.has_payload = has_payload; 527 vcpu->arch.exception.payload = payload; 528 if (!is_guest_mode(vcpu)) 529 kvm_deliver_exception_payload(vcpu); 530 return; 531 } 532 533 /* to check exception */ 534 prev_nr = vcpu->arch.exception.nr; 535 if (prev_nr == DF_VECTOR) { 536 /* triple fault -> shutdown */ 537 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 538 return; 539 } 540 class1 = exception_class(prev_nr); 541 class2 = exception_class(nr); 542 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 543 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 544 /* 545 * Generate double fault per SDM Table 5-5. Set 546 * exception.pending = true so that the double fault 547 * can trigger a nested vmexit. 548 */ 549 vcpu->arch.exception.pending = true; 550 vcpu->arch.exception.injected = false; 551 vcpu->arch.exception.has_error_code = true; 552 vcpu->arch.exception.nr = DF_VECTOR; 553 vcpu->arch.exception.error_code = 0; 554 vcpu->arch.exception.has_payload = false; 555 vcpu->arch.exception.payload = 0; 556 } else 557 /* replace previous exception with a new one in a hope 558 that instruction re-execution will regenerate lost 559 exception */ 560 goto queue; 561 } 562 563 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 564 { 565 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 566 } 567 EXPORT_SYMBOL_GPL(kvm_queue_exception); 568 569 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 570 { 571 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 572 } 573 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 574 575 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 576 unsigned long payload) 577 { 578 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 579 } 580 581 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 582 u32 error_code, unsigned long payload) 583 { 584 kvm_multiple_exception(vcpu, nr, true, error_code, 585 true, payload, false); 586 } 587 588 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 589 { 590 if (err) 591 kvm_inject_gp(vcpu, 0); 592 else 593 return kvm_skip_emulated_instruction(vcpu); 594 595 return 1; 596 } 597 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 598 599 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 600 { 601 ++vcpu->stat.pf_guest; 602 vcpu->arch.exception.nested_apf = 603 is_guest_mode(vcpu) && fault->async_page_fault; 604 if (vcpu->arch.exception.nested_apf) { 605 vcpu->arch.apf.nested_apf_token = fault->address; 606 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 607 } else { 608 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 609 fault->address); 610 } 611 } 612 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 613 614 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 615 { 616 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 617 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 618 else 619 vcpu->arch.mmu->inject_page_fault(vcpu, fault); 620 621 return fault->nested_page_fault; 622 } 623 624 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 625 { 626 atomic_inc(&vcpu->arch.nmi_queued); 627 kvm_make_request(KVM_REQ_NMI, vcpu); 628 } 629 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 630 631 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 632 { 633 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 634 } 635 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 636 637 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 638 { 639 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 640 } 641 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 642 643 /* 644 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 645 * a #GP and return false. 646 */ 647 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 648 { 649 if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl) 650 return true; 651 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 652 return false; 653 } 654 EXPORT_SYMBOL_GPL(kvm_require_cpl); 655 656 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 657 { 658 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 659 return true; 660 661 kvm_queue_exception(vcpu, UD_VECTOR); 662 return false; 663 } 664 EXPORT_SYMBOL_GPL(kvm_require_dr); 665 666 /* 667 * This function will be used to read from the physical memory of the currently 668 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 669 * can read from guest physical or from the guest's guest physical memory. 670 */ 671 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 672 gfn_t ngfn, void *data, int offset, int len, 673 u32 access) 674 { 675 struct x86_exception exception; 676 gfn_t real_gfn; 677 gpa_t ngpa; 678 679 ngpa = gfn_to_gpa(ngfn); 680 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 681 if (real_gfn == UNMAPPED_GVA) 682 return -EFAULT; 683 684 real_gfn = gpa_to_gfn(real_gfn); 685 686 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 687 } 688 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 689 690 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 691 void *data, int offset, int len, u32 access) 692 { 693 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 694 data, offset, len, access); 695 } 696 697 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) 698 { 699 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) | 700 rsvd_bits(1, 2); 701 } 702 703 /* 704 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. 705 */ 706 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 707 { 708 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 709 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 710 int i; 711 int ret; 712 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 713 714 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 715 offset * sizeof(u64), sizeof(pdpte), 716 PFERR_USER_MASK|PFERR_WRITE_MASK); 717 if (ret < 0) { 718 ret = 0; 719 goto out; 720 } 721 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 722 if ((pdpte[i] & PT_PRESENT_MASK) && 723 (pdpte[i] & pdptr_rsvd_bits(vcpu))) { 724 ret = 0; 725 goto out; 726 } 727 } 728 ret = 1; 729 730 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 731 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 732 733 out: 734 735 return ret; 736 } 737 EXPORT_SYMBOL_GPL(load_pdptrs); 738 739 bool pdptrs_changed(struct kvm_vcpu *vcpu) 740 { 741 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 742 int offset; 743 gfn_t gfn; 744 int r; 745 746 if (!is_pae_paging(vcpu)) 747 return false; 748 749 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR)) 750 return true; 751 752 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; 753 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); 754 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 755 PFERR_USER_MASK | PFERR_WRITE_MASK); 756 if (r < 0) 757 return true; 758 759 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 760 } 761 EXPORT_SYMBOL_GPL(pdptrs_changed); 762 763 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 764 { 765 unsigned long old_cr0 = kvm_read_cr0(vcpu); 766 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 767 768 cr0 |= X86_CR0_ET; 769 770 #ifdef CONFIG_X86_64 771 if (cr0 & 0xffffffff00000000UL) 772 return 1; 773 #endif 774 775 cr0 &= ~CR0_RESERVED_BITS; 776 777 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 778 return 1; 779 780 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 781 return 1; 782 783 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 784 #ifdef CONFIG_X86_64 785 if ((vcpu->arch.efer & EFER_LME)) { 786 int cs_db, cs_l; 787 788 if (!is_pae(vcpu)) 789 return 1; 790 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 791 if (cs_l) 792 return 1; 793 } else 794 #endif 795 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 796 kvm_read_cr3(vcpu))) 797 return 1; 798 } 799 800 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 801 return 1; 802 803 kvm_x86_ops.set_cr0(vcpu, cr0); 804 805 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 806 kvm_clear_async_pf_completion_queue(vcpu); 807 kvm_async_pf_hash_reset(vcpu); 808 } 809 810 if ((cr0 ^ old_cr0) & update_bits) 811 kvm_mmu_reset_context(vcpu); 812 813 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 814 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 815 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 816 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 817 818 return 0; 819 } 820 EXPORT_SYMBOL_GPL(kvm_set_cr0); 821 822 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 823 { 824 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 825 } 826 EXPORT_SYMBOL_GPL(kvm_lmsw); 827 828 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) 829 { 830 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 831 832 if (vcpu->arch.xcr0 != host_xcr0) 833 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 834 835 if (vcpu->arch.xsaves_enabled && 836 vcpu->arch.ia32_xss != host_xss) 837 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 838 } 839 } 840 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); 841 842 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) 843 { 844 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 845 846 if (vcpu->arch.xcr0 != host_xcr0) 847 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 848 849 if (vcpu->arch.xsaves_enabled && 850 vcpu->arch.ia32_xss != host_xss) 851 wrmsrl(MSR_IA32_XSS, host_xss); 852 } 853 854 } 855 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); 856 857 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 858 { 859 u64 xcr0 = xcr; 860 u64 old_xcr0 = vcpu->arch.xcr0; 861 u64 valid_bits; 862 863 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 864 if (index != XCR_XFEATURE_ENABLED_MASK) 865 return 1; 866 if (!(xcr0 & XFEATURE_MASK_FP)) 867 return 1; 868 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 869 return 1; 870 871 /* 872 * Do not allow the guest to set bits that we do not support 873 * saving. However, xcr0 bit 0 is always set, even if the 874 * emulated CPU does not support XSAVE (see fx_init). 875 */ 876 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 877 if (xcr0 & ~valid_bits) 878 return 1; 879 880 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 881 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 882 return 1; 883 884 if (xcr0 & XFEATURE_MASK_AVX512) { 885 if (!(xcr0 & XFEATURE_MASK_YMM)) 886 return 1; 887 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 888 return 1; 889 } 890 vcpu->arch.xcr0 = xcr0; 891 892 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 893 kvm_update_cpuid(vcpu); 894 return 0; 895 } 896 897 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 898 { 899 if (kvm_x86_ops.get_cpl(vcpu) != 0 || 900 __kvm_set_xcr(vcpu, index, xcr)) { 901 kvm_inject_gp(vcpu, 0); 902 return 1; 903 } 904 return 0; 905 } 906 EXPORT_SYMBOL_GPL(kvm_set_xcr); 907 908 #define __cr4_reserved_bits(__cpu_has, __c) \ 909 ({ \ 910 u64 __reserved_bits = CR4_RESERVED_BITS; \ 911 \ 912 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \ 913 __reserved_bits |= X86_CR4_OSXSAVE; \ 914 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \ 915 __reserved_bits |= X86_CR4_SMEP; \ 916 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \ 917 __reserved_bits |= X86_CR4_SMAP; \ 918 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \ 919 __reserved_bits |= X86_CR4_FSGSBASE; \ 920 if (!__cpu_has(__c, X86_FEATURE_PKU)) \ 921 __reserved_bits |= X86_CR4_PKE; \ 922 if (!__cpu_has(__c, X86_FEATURE_LA57)) \ 923 __reserved_bits |= X86_CR4_LA57; \ 924 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \ 925 __reserved_bits |= X86_CR4_UMIP; \ 926 __reserved_bits; \ 927 }) 928 929 static u64 kvm_host_cr4_reserved_bits(struct cpuinfo_x86 *c) 930 { 931 u64 reserved_bits = __cr4_reserved_bits(cpu_has, c); 932 933 if (kvm_cpu_cap_has(X86_FEATURE_LA57)) 934 reserved_bits &= ~X86_CR4_LA57; 935 936 if (kvm_cpu_cap_has(X86_FEATURE_UMIP)) 937 reserved_bits &= ~X86_CR4_UMIP; 938 939 return reserved_bits; 940 } 941 942 static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 943 { 944 if (cr4 & cr4_reserved_bits) 945 return -EINVAL; 946 947 if (cr4 & __cr4_reserved_bits(guest_cpuid_has, vcpu)) 948 return -EINVAL; 949 950 return 0; 951 } 952 953 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 954 { 955 unsigned long old_cr4 = kvm_read_cr4(vcpu); 956 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 957 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 958 959 if (kvm_valid_cr4(vcpu, cr4)) 960 return 1; 961 962 if (is_long_mode(vcpu)) { 963 if (!(cr4 & X86_CR4_PAE)) 964 return 1; 965 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 966 && ((cr4 ^ old_cr4) & pdptr_bits) 967 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 968 kvm_read_cr3(vcpu))) 969 return 1; 970 971 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 972 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 973 return 1; 974 975 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 976 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 977 return 1; 978 } 979 980 if (kvm_x86_ops.set_cr4(vcpu, cr4)) 981 return 1; 982 983 if (((cr4 ^ old_cr4) & pdptr_bits) || 984 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 985 kvm_mmu_reset_context(vcpu); 986 987 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 988 kvm_update_cpuid(vcpu); 989 990 return 0; 991 } 992 EXPORT_SYMBOL_GPL(kvm_set_cr4); 993 994 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 995 { 996 bool skip_tlb_flush = false; 997 #ifdef CONFIG_X86_64 998 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 999 1000 if (pcid_enabled) { 1001 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 1002 cr3 &= ~X86_CR3_PCID_NOFLUSH; 1003 } 1004 #endif 1005 1006 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 1007 if (!skip_tlb_flush) { 1008 kvm_mmu_sync_roots(vcpu); 1009 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 1010 } 1011 return 0; 1012 } 1013 1014 if (is_long_mode(vcpu) && 1015 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63))) 1016 return 1; 1017 else if (is_pae_paging(vcpu) && 1018 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 1019 return 1; 1020 1021 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush); 1022 vcpu->arch.cr3 = cr3; 1023 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 1024 1025 return 0; 1026 } 1027 EXPORT_SYMBOL_GPL(kvm_set_cr3); 1028 1029 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 1030 { 1031 if (cr8 & CR8_RESERVED_BITS) 1032 return 1; 1033 if (lapic_in_kernel(vcpu)) 1034 kvm_lapic_set_tpr(vcpu, cr8); 1035 else 1036 vcpu->arch.cr8 = cr8; 1037 return 0; 1038 } 1039 EXPORT_SYMBOL_GPL(kvm_set_cr8); 1040 1041 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 1042 { 1043 if (lapic_in_kernel(vcpu)) 1044 return kvm_lapic_get_cr8(vcpu); 1045 else 1046 return vcpu->arch.cr8; 1047 } 1048 EXPORT_SYMBOL_GPL(kvm_get_cr8); 1049 1050 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 1051 { 1052 int i; 1053 1054 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1055 for (i = 0; i < KVM_NR_DB_REGS; i++) 1056 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1057 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 1058 } 1059 } 1060 1061 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 1062 { 1063 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1064 kvm_x86_ops.set_dr6(vcpu, vcpu->arch.dr6); 1065 } 1066 1067 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 1068 { 1069 unsigned long dr7; 1070 1071 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1072 dr7 = vcpu->arch.guest_debug_dr7; 1073 else 1074 dr7 = vcpu->arch.dr7; 1075 kvm_x86_ops.set_dr7(vcpu, dr7); 1076 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1077 if (dr7 & DR7_BP_EN_MASK) 1078 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1079 } 1080 1081 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1082 { 1083 u64 fixed = DR6_FIXED_1; 1084 1085 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1086 fixed |= DR6_RTM; 1087 return fixed; 1088 } 1089 1090 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1091 { 1092 size_t size = ARRAY_SIZE(vcpu->arch.db); 1093 1094 switch (dr) { 1095 case 0 ... 3: 1096 vcpu->arch.db[array_index_nospec(dr, size)] = val; 1097 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1098 vcpu->arch.eff_db[dr] = val; 1099 break; 1100 case 4: 1101 /* fall through */ 1102 case 6: 1103 if (val & 0xffffffff00000000ULL) 1104 return -1; /* #GP */ 1105 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1106 kvm_update_dr6(vcpu); 1107 break; 1108 case 5: 1109 /* fall through */ 1110 default: /* 7 */ 1111 if (!kvm_dr7_valid(val)) 1112 return -1; /* #GP */ 1113 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1114 kvm_update_dr7(vcpu); 1115 break; 1116 } 1117 1118 return 0; 1119 } 1120 1121 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1122 { 1123 if (__kvm_set_dr(vcpu, dr, val)) { 1124 kvm_inject_gp(vcpu, 0); 1125 return 1; 1126 } 1127 return 0; 1128 } 1129 EXPORT_SYMBOL_GPL(kvm_set_dr); 1130 1131 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1132 { 1133 size_t size = ARRAY_SIZE(vcpu->arch.db); 1134 1135 switch (dr) { 1136 case 0 ... 3: 1137 *val = vcpu->arch.db[array_index_nospec(dr, size)]; 1138 break; 1139 case 4: 1140 /* fall through */ 1141 case 6: 1142 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1143 *val = vcpu->arch.dr6; 1144 else 1145 *val = kvm_x86_ops.get_dr6(vcpu); 1146 break; 1147 case 5: 1148 /* fall through */ 1149 default: /* 7 */ 1150 *val = vcpu->arch.dr7; 1151 break; 1152 } 1153 return 0; 1154 } 1155 EXPORT_SYMBOL_GPL(kvm_get_dr); 1156 1157 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 1158 { 1159 u32 ecx = kvm_rcx_read(vcpu); 1160 u64 data; 1161 int err; 1162 1163 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 1164 if (err) 1165 return err; 1166 kvm_rax_write(vcpu, (u32)data); 1167 kvm_rdx_write(vcpu, data >> 32); 1168 return err; 1169 } 1170 EXPORT_SYMBOL_GPL(kvm_rdpmc); 1171 1172 /* 1173 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1174 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1175 * 1176 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) 1177 * extract the supported MSRs from the related const lists. 1178 * msrs_to_save is selected from the msrs_to_save_all to reflect the 1179 * capabilities of the host cpu. This capabilities test skips MSRs that are 1180 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs 1181 * may depend on host virtualization features rather than host cpu features. 1182 */ 1183 1184 static const u32 msrs_to_save_all[] = { 1185 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1186 MSR_STAR, 1187 #ifdef CONFIG_X86_64 1188 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1189 #endif 1190 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1191 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1192 MSR_IA32_SPEC_CTRL, 1193 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1194 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1195 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1196 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1197 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1198 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1199 MSR_IA32_UMWAIT_CONTROL, 1200 1201 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, 1202 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, 1203 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, 1204 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 1205 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, 1206 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, 1207 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, 1208 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, 1209 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, 1210 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, 1211 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, 1212 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, 1213 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, 1214 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, 1215 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, 1216 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, 1217 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, 1218 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, 1219 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, 1220 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, 1221 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, 1222 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, 1223 }; 1224 1225 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; 1226 static unsigned num_msrs_to_save; 1227 1228 static const u32 emulated_msrs_all[] = { 1229 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1230 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1231 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1232 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1233 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1234 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1235 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1236 HV_X64_MSR_RESET, 1237 HV_X64_MSR_VP_INDEX, 1238 HV_X64_MSR_VP_RUNTIME, 1239 HV_X64_MSR_SCONTROL, 1240 HV_X64_MSR_STIMER0_CONFIG, 1241 HV_X64_MSR_VP_ASSIST_PAGE, 1242 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1243 HV_X64_MSR_TSC_EMULATION_STATUS, 1244 1245 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1246 MSR_KVM_PV_EOI_EN, 1247 1248 MSR_IA32_TSC_ADJUST, 1249 MSR_IA32_TSCDEADLINE, 1250 MSR_IA32_ARCH_CAPABILITIES, 1251 MSR_IA32_MISC_ENABLE, 1252 MSR_IA32_MCG_STATUS, 1253 MSR_IA32_MCG_CTL, 1254 MSR_IA32_MCG_EXT_CTL, 1255 MSR_IA32_SMBASE, 1256 MSR_SMI_COUNT, 1257 MSR_PLATFORM_INFO, 1258 MSR_MISC_FEATURES_ENABLES, 1259 MSR_AMD64_VIRT_SPEC_CTRL, 1260 MSR_IA32_POWER_CTL, 1261 MSR_IA32_UCODE_REV, 1262 1263 /* 1264 * The following list leaves out MSRs whose values are determined 1265 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. 1266 * We always support the "true" VMX control MSRs, even if the host 1267 * processor does not, so I am putting these registers here rather 1268 * than in msrs_to_save_all. 1269 */ 1270 MSR_IA32_VMX_BASIC, 1271 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1272 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1273 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1274 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1275 MSR_IA32_VMX_MISC, 1276 MSR_IA32_VMX_CR0_FIXED0, 1277 MSR_IA32_VMX_CR4_FIXED0, 1278 MSR_IA32_VMX_VMCS_ENUM, 1279 MSR_IA32_VMX_PROCBASED_CTLS2, 1280 MSR_IA32_VMX_EPT_VPID_CAP, 1281 MSR_IA32_VMX_VMFUNC, 1282 1283 MSR_K7_HWCR, 1284 MSR_KVM_POLL_CONTROL, 1285 }; 1286 1287 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; 1288 static unsigned num_emulated_msrs; 1289 1290 /* 1291 * List of msr numbers which are used to expose MSR-based features that 1292 * can be used by a hypervisor to validate requested CPU features. 1293 */ 1294 static const u32 msr_based_features_all[] = { 1295 MSR_IA32_VMX_BASIC, 1296 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1297 MSR_IA32_VMX_PINBASED_CTLS, 1298 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1299 MSR_IA32_VMX_PROCBASED_CTLS, 1300 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1301 MSR_IA32_VMX_EXIT_CTLS, 1302 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1303 MSR_IA32_VMX_ENTRY_CTLS, 1304 MSR_IA32_VMX_MISC, 1305 MSR_IA32_VMX_CR0_FIXED0, 1306 MSR_IA32_VMX_CR0_FIXED1, 1307 MSR_IA32_VMX_CR4_FIXED0, 1308 MSR_IA32_VMX_CR4_FIXED1, 1309 MSR_IA32_VMX_VMCS_ENUM, 1310 MSR_IA32_VMX_PROCBASED_CTLS2, 1311 MSR_IA32_VMX_EPT_VPID_CAP, 1312 MSR_IA32_VMX_VMFUNC, 1313 1314 MSR_F10H_DECFG, 1315 MSR_IA32_UCODE_REV, 1316 MSR_IA32_ARCH_CAPABILITIES, 1317 }; 1318 1319 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; 1320 static unsigned int num_msr_based_features; 1321 1322 static u64 kvm_get_arch_capabilities(void) 1323 { 1324 u64 data = 0; 1325 1326 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1327 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); 1328 1329 /* 1330 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that 1331 * the nested hypervisor runs with NX huge pages. If it is not, 1332 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other 1333 * L1 guests, so it need not worry about its own (L2) guests. 1334 */ 1335 data |= ARCH_CAP_PSCHANGE_MC_NO; 1336 1337 /* 1338 * If we're doing cache flushes (either "always" or "cond") 1339 * we will do one whenever the guest does a vmlaunch/vmresume. 1340 * If an outer hypervisor is doing the cache flush for us 1341 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1342 * capability to the guest too, and if EPT is disabled we're not 1343 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1344 * require a nested hypervisor to do a flush of its own. 1345 */ 1346 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1347 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1348 1349 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) 1350 data |= ARCH_CAP_RDCL_NO; 1351 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1352 data |= ARCH_CAP_SSB_NO; 1353 if (!boot_cpu_has_bug(X86_BUG_MDS)) 1354 data |= ARCH_CAP_MDS_NO; 1355 1356 /* 1357 * On TAA affected systems: 1358 * - nothing to do if TSX is disabled on the host. 1359 * - we emulate TSX_CTRL if present on the host. 1360 * This lets the guest use VERW to clear CPU buffers. 1361 */ 1362 if (!boot_cpu_has(X86_FEATURE_RTM)) 1363 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR); 1364 else if (!boot_cpu_has_bug(X86_BUG_TAA)) 1365 data |= ARCH_CAP_TAA_NO; 1366 1367 return data; 1368 } 1369 1370 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1371 { 1372 switch (msr->index) { 1373 case MSR_IA32_ARCH_CAPABILITIES: 1374 msr->data = kvm_get_arch_capabilities(); 1375 break; 1376 case MSR_IA32_UCODE_REV: 1377 rdmsrl_safe(msr->index, &msr->data); 1378 break; 1379 default: 1380 if (kvm_x86_ops.get_msr_feature(msr)) 1381 return 1; 1382 } 1383 return 0; 1384 } 1385 1386 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1387 { 1388 struct kvm_msr_entry msr; 1389 int r; 1390 1391 msr.index = index; 1392 r = kvm_get_msr_feature(&msr); 1393 if (r) 1394 return r; 1395 1396 *data = msr.data; 1397 1398 return 0; 1399 } 1400 1401 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1402 { 1403 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1404 return false; 1405 1406 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1407 return false; 1408 1409 if (efer & (EFER_LME | EFER_LMA) && 1410 !guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1411 return false; 1412 1413 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) 1414 return false; 1415 1416 return true; 1417 1418 } 1419 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1420 { 1421 if (efer & efer_reserved_bits) 1422 return false; 1423 1424 return __kvm_valid_efer(vcpu, efer); 1425 } 1426 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1427 1428 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1429 { 1430 u64 old_efer = vcpu->arch.efer; 1431 u64 efer = msr_info->data; 1432 1433 if (efer & efer_reserved_bits) 1434 return 1; 1435 1436 if (!msr_info->host_initiated) { 1437 if (!__kvm_valid_efer(vcpu, efer)) 1438 return 1; 1439 1440 if (is_paging(vcpu) && 1441 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1442 return 1; 1443 } 1444 1445 efer &= ~EFER_LMA; 1446 efer |= vcpu->arch.efer & EFER_LMA; 1447 1448 kvm_x86_ops.set_efer(vcpu, efer); 1449 1450 /* Update reserved bits */ 1451 if ((efer ^ old_efer) & EFER_NX) 1452 kvm_mmu_reset_context(vcpu); 1453 1454 return 0; 1455 } 1456 1457 void kvm_enable_efer_bits(u64 mask) 1458 { 1459 efer_reserved_bits &= ~mask; 1460 } 1461 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1462 1463 /* 1464 * Write @data into the MSR specified by @index. Select MSR specific fault 1465 * checks are bypassed if @host_initiated is %true. 1466 * Returns 0 on success, non-0 otherwise. 1467 * Assumes vcpu_load() was already called. 1468 */ 1469 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, 1470 bool host_initiated) 1471 { 1472 struct msr_data msr; 1473 1474 switch (index) { 1475 case MSR_FS_BASE: 1476 case MSR_GS_BASE: 1477 case MSR_KERNEL_GS_BASE: 1478 case MSR_CSTAR: 1479 case MSR_LSTAR: 1480 if (is_noncanonical_address(data, vcpu)) 1481 return 1; 1482 break; 1483 case MSR_IA32_SYSENTER_EIP: 1484 case MSR_IA32_SYSENTER_ESP: 1485 /* 1486 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1487 * non-canonical address is written on Intel but not on 1488 * AMD (which ignores the top 32-bits, because it does 1489 * not implement 64-bit SYSENTER). 1490 * 1491 * 64-bit code should hence be able to write a non-canonical 1492 * value on AMD. Making the address canonical ensures that 1493 * vmentry does not fail on Intel after writing a non-canonical 1494 * value, and that something deterministic happens if the guest 1495 * invokes 64-bit SYSENTER. 1496 */ 1497 data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); 1498 } 1499 1500 msr.data = data; 1501 msr.index = index; 1502 msr.host_initiated = host_initiated; 1503 1504 return kvm_x86_ops.set_msr(vcpu, &msr); 1505 } 1506 1507 /* 1508 * Read the MSR specified by @index into @data. Select MSR specific fault 1509 * checks are bypassed if @host_initiated is %true. 1510 * Returns 0 on success, non-0 otherwise. 1511 * Assumes vcpu_load() was already called. 1512 */ 1513 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1514 bool host_initiated) 1515 { 1516 struct msr_data msr; 1517 int ret; 1518 1519 msr.index = index; 1520 msr.host_initiated = host_initiated; 1521 1522 ret = kvm_x86_ops.get_msr(vcpu, &msr); 1523 if (!ret) 1524 *data = msr.data; 1525 return ret; 1526 } 1527 1528 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1529 { 1530 return __kvm_get_msr(vcpu, index, data, false); 1531 } 1532 EXPORT_SYMBOL_GPL(kvm_get_msr); 1533 1534 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) 1535 { 1536 return __kvm_set_msr(vcpu, index, data, false); 1537 } 1538 EXPORT_SYMBOL_GPL(kvm_set_msr); 1539 1540 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) 1541 { 1542 u32 ecx = kvm_rcx_read(vcpu); 1543 u64 data; 1544 1545 if (kvm_get_msr(vcpu, ecx, &data)) { 1546 trace_kvm_msr_read_ex(ecx); 1547 kvm_inject_gp(vcpu, 0); 1548 return 1; 1549 } 1550 1551 trace_kvm_msr_read(ecx, data); 1552 1553 kvm_rax_write(vcpu, data & -1u); 1554 kvm_rdx_write(vcpu, (data >> 32) & -1u); 1555 return kvm_skip_emulated_instruction(vcpu); 1556 } 1557 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); 1558 1559 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) 1560 { 1561 u32 ecx = kvm_rcx_read(vcpu); 1562 u64 data = kvm_read_edx_eax(vcpu); 1563 1564 if (kvm_set_msr(vcpu, ecx, data)) { 1565 trace_kvm_msr_write_ex(ecx, data); 1566 kvm_inject_gp(vcpu, 0); 1567 return 1; 1568 } 1569 1570 trace_kvm_msr_write(ecx, data); 1571 return kvm_skip_emulated_instruction(vcpu); 1572 } 1573 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); 1574 1575 /* 1576 * The fast path for frequent and performance sensitive wrmsr emulation, 1577 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces 1578 * the latency of virtual IPI by avoiding the expensive bits of transitioning 1579 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the 1580 * other cases which must be called after interrupts are enabled on the host. 1581 */ 1582 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) 1583 { 1584 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) 1585 return 1; 1586 1587 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && 1588 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && 1589 ((data & APIC_MODE_MASK) == APIC_DM_FIXED)) { 1590 1591 data &= ~(1 << 12); 1592 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); 1593 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); 1594 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); 1595 trace_kvm_apic_write(APIC_ICR, (u32)data); 1596 return 0; 1597 } 1598 1599 return 1; 1600 } 1601 1602 enum exit_fastpath_completion handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) 1603 { 1604 u32 msr = kvm_rcx_read(vcpu); 1605 u64 data; 1606 int ret = 0; 1607 1608 switch (msr) { 1609 case APIC_BASE_MSR + (APIC_ICR >> 4): 1610 data = kvm_read_edx_eax(vcpu); 1611 ret = handle_fastpath_set_x2apic_icr_irqoff(vcpu, data); 1612 break; 1613 default: 1614 return EXIT_FASTPATH_NONE; 1615 } 1616 1617 if (!ret) { 1618 trace_kvm_msr_write(msr, data); 1619 return EXIT_FASTPATH_SKIP_EMUL_INS; 1620 } 1621 1622 return EXIT_FASTPATH_NONE; 1623 } 1624 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); 1625 1626 /* 1627 * Adapt set_msr() to msr_io()'s calling convention 1628 */ 1629 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1630 { 1631 return __kvm_get_msr(vcpu, index, data, true); 1632 } 1633 1634 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1635 { 1636 return __kvm_set_msr(vcpu, index, *data, true); 1637 } 1638 1639 #ifdef CONFIG_X86_64 1640 struct pvclock_clock { 1641 int vclock_mode; 1642 u64 cycle_last; 1643 u64 mask; 1644 u32 mult; 1645 u32 shift; 1646 u64 base_cycles; 1647 u64 offset; 1648 }; 1649 1650 struct pvclock_gtod_data { 1651 seqcount_t seq; 1652 1653 struct pvclock_clock clock; /* extract of a clocksource struct */ 1654 struct pvclock_clock raw_clock; /* extract of a clocksource struct */ 1655 1656 ktime_t offs_boot; 1657 u64 wall_time_sec; 1658 }; 1659 1660 static struct pvclock_gtod_data pvclock_gtod_data; 1661 1662 static void update_pvclock_gtod(struct timekeeper *tk) 1663 { 1664 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1665 1666 write_seqcount_begin(&vdata->seq); 1667 1668 /* copy pvclock gtod data */ 1669 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; 1670 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1671 vdata->clock.mask = tk->tkr_mono.mask; 1672 vdata->clock.mult = tk->tkr_mono.mult; 1673 vdata->clock.shift = tk->tkr_mono.shift; 1674 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 1675 vdata->clock.offset = tk->tkr_mono.base; 1676 1677 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; 1678 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; 1679 vdata->raw_clock.mask = tk->tkr_raw.mask; 1680 vdata->raw_clock.mult = tk->tkr_raw.mult; 1681 vdata->raw_clock.shift = tk->tkr_raw.shift; 1682 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; 1683 vdata->raw_clock.offset = tk->tkr_raw.base; 1684 1685 vdata->wall_time_sec = tk->xtime_sec; 1686 1687 vdata->offs_boot = tk->offs_boot; 1688 1689 write_seqcount_end(&vdata->seq); 1690 } 1691 1692 static s64 get_kvmclock_base_ns(void) 1693 { 1694 /* Count up from boot time, but with the frequency of the raw clock. */ 1695 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); 1696 } 1697 #else 1698 static s64 get_kvmclock_base_ns(void) 1699 { 1700 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ 1701 return ktime_get_boottime_ns(); 1702 } 1703 #endif 1704 1705 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1706 { 1707 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1708 kvm_vcpu_kick(vcpu); 1709 } 1710 1711 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1712 { 1713 int version; 1714 int r; 1715 struct pvclock_wall_clock wc; 1716 u64 wall_nsec; 1717 1718 if (!wall_clock) 1719 return; 1720 1721 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1722 if (r) 1723 return; 1724 1725 if (version & 1) 1726 ++version; /* first time write, random junk */ 1727 1728 ++version; 1729 1730 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1731 return; 1732 1733 /* 1734 * The guest calculates current wall clock time by adding 1735 * system time (updated by kvm_guest_time_update below) to the 1736 * wall clock specified here. We do the reverse here. 1737 */ 1738 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); 1739 1740 wc.nsec = do_div(wall_nsec, 1000000000); 1741 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ 1742 wc.version = version; 1743 1744 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1745 1746 version++; 1747 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1748 } 1749 1750 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1751 { 1752 do_shl32_div32(dividend, divisor); 1753 return dividend; 1754 } 1755 1756 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 1757 s8 *pshift, u32 *pmultiplier) 1758 { 1759 uint64_t scaled64; 1760 int32_t shift = 0; 1761 uint64_t tps64; 1762 uint32_t tps32; 1763 1764 tps64 = base_hz; 1765 scaled64 = scaled_hz; 1766 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1767 tps64 >>= 1; 1768 shift--; 1769 } 1770 1771 tps32 = (uint32_t)tps64; 1772 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1773 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1774 scaled64 >>= 1; 1775 else 1776 tps32 <<= 1; 1777 shift++; 1778 } 1779 1780 *pshift = shift; 1781 *pmultiplier = div_frac(scaled64, tps32); 1782 } 1783 1784 #ifdef CONFIG_X86_64 1785 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1786 #endif 1787 1788 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1789 static unsigned long max_tsc_khz; 1790 1791 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1792 { 1793 u64 v = (u64)khz * (1000000 + ppm); 1794 do_div(v, 1000000); 1795 return v; 1796 } 1797 1798 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 1799 { 1800 u64 ratio; 1801 1802 /* Guest TSC same frequency as host TSC? */ 1803 if (!scale) { 1804 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1805 return 0; 1806 } 1807 1808 /* TSC scaling supported? */ 1809 if (!kvm_has_tsc_control) { 1810 if (user_tsc_khz > tsc_khz) { 1811 vcpu->arch.tsc_catchup = 1; 1812 vcpu->arch.tsc_always_catchup = 1; 1813 return 0; 1814 } else { 1815 pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); 1816 return -1; 1817 } 1818 } 1819 1820 /* TSC scaling required - calculate ratio */ 1821 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 1822 user_tsc_khz, tsc_khz); 1823 1824 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 1825 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 1826 user_tsc_khz); 1827 return -1; 1828 } 1829 1830 vcpu->arch.tsc_scaling_ratio = ratio; 1831 return 0; 1832 } 1833 1834 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 1835 { 1836 u32 thresh_lo, thresh_hi; 1837 int use_scaling = 0; 1838 1839 /* tsc_khz can be zero if TSC calibration fails */ 1840 if (user_tsc_khz == 0) { 1841 /* set tsc_scaling_ratio to a safe value */ 1842 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1843 return -1; 1844 } 1845 1846 /* Compute a scale to convert nanoseconds in TSC cycles */ 1847 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 1848 &vcpu->arch.virtual_tsc_shift, 1849 &vcpu->arch.virtual_tsc_mult); 1850 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 1851 1852 /* 1853 * Compute the variation in TSC rate which is acceptable 1854 * within the range of tolerance and decide if the 1855 * rate being applied is within that bounds of the hardware 1856 * rate. If so, no scaling or compensation need be done. 1857 */ 1858 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1859 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1860 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 1861 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 1862 use_scaling = 1; 1863 } 1864 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 1865 } 1866 1867 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1868 { 1869 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1870 vcpu->arch.virtual_tsc_mult, 1871 vcpu->arch.virtual_tsc_shift); 1872 tsc += vcpu->arch.this_tsc_write; 1873 return tsc; 1874 } 1875 1876 static inline int gtod_is_based_on_tsc(int mode) 1877 { 1878 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; 1879 } 1880 1881 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1882 { 1883 #ifdef CONFIG_X86_64 1884 bool vcpus_matched; 1885 struct kvm_arch *ka = &vcpu->kvm->arch; 1886 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1887 1888 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1889 atomic_read(&vcpu->kvm->online_vcpus)); 1890 1891 /* 1892 * Once the masterclock is enabled, always perform request in 1893 * order to update it. 1894 * 1895 * In order to enable masterclock, the host clocksource must be TSC 1896 * and the vcpus need to have matched TSCs. When that happens, 1897 * perform request to enable masterclock. 1898 */ 1899 if (ka->use_master_clock || 1900 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 1901 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1902 1903 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1904 atomic_read(&vcpu->kvm->online_vcpus), 1905 ka->use_master_clock, gtod->clock.vclock_mode); 1906 #endif 1907 } 1908 1909 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1910 { 1911 u64 curr_offset = kvm_x86_ops.read_l1_tsc_offset(vcpu); 1912 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1913 } 1914 1915 /* 1916 * Multiply tsc by a fixed point number represented by ratio. 1917 * 1918 * The most significant 64-N bits (mult) of ratio represent the 1919 * integral part of the fixed point number; the remaining N bits 1920 * (frac) represent the fractional part, ie. ratio represents a fixed 1921 * point number (mult + frac * 2^(-N)). 1922 * 1923 * N equals to kvm_tsc_scaling_ratio_frac_bits. 1924 */ 1925 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 1926 { 1927 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 1928 } 1929 1930 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 1931 { 1932 u64 _tsc = tsc; 1933 u64 ratio = vcpu->arch.tsc_scaling_ratio; 1934 1935 if (ratio != kvm_default_tsc_scaling_ratio) 1936 _tsc = __scale_tsc(ratio, tsc); 1937 1938 return _tsc; 1939 } 1940 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 1941 1942 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 1943 { 1944 u64 tsc; 1945 1946 tsc = kvm_scale_tsc(vcpu, rdtsc()); 1947 1948 return target_tsc - tsc; 1949 } 1950 1951 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 1952 { 1953 u64 tsc_offset = kvm_x86_ops.read_l1_tsc_offset(vcpu); 1954 1955 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc); 1956 } 1957 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 1958 1959 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1960 { 1961 vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset); 1962 } 1963 1964 static inline bool kvm_check_tsc_unstable(void) 1965 { 1966 #ifdef CONFIG_X86_64 1967 /* 1968 * TSC is marked unstable when we're running on Hyper-V, 1969 * 'TSC page' clocksource is good. 1970 */ 1971 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) 1972 return false; 1973 #endif 1974 return check_tsc_unstable(); 1975 } 1976 1977 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1978 { 1979 struct kvm *kvm = vcpu->kvm; 1980 u64 offset, ns, elapsed; 1981 unsigned long flags; 1982 bool matched; 1983 bool already_matched; 1984 u64 data = msr->data; 1985 bool synchronizing = false; 1986 1987 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1988 offset = kvm_compute_tsc_offset(vcpu, data); 1989 ns = get_kvmclock_base_ns(); 1990 elapsed = ns - kvm->arch.last_tsc_nsec; 1991 1992 if (vcpu->arch.virtual_tsc_khz) { 1993 if (data == 0 && msr->host_initiated) { 1994 /* 1995 * detection of vcpu initialization -- need to sync 1996 * with other vCPUs. This particularly helps to keep 1997 * kvm_clock stable after CPU hotplug 1998 */ 1999 synchronizing = true; 2000 } else { 2001 u64 tsc_exp = kvm->arch.last_tsc_write + 2002 nsec_to_cycles(vcpu, elapsed); 2003 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 2004 /* 2005 * Special case: TSC write with a small delta (1 second) 2006 * of virtual cycle time against real time is 2007 * interpreted as an attempt to synchronize the CPU. 2008 */ 2009 synchronizing = data < tsc_exp + tsc_hz && 2010 data + tsc_hz > tsc_exp; 2011 } 2012 } 2013 2014 /* 2015 * For a reliable TSC, we can match TSC offsets, and for an unstable 2016 * TSC, we add elapsed time in this computation. We could let the 2017 * compensation code attempt to catch up if we fall behind, but 2018 * it's better to try to match offsets from the beginning. 2019 */ 2020 if (synchronizing && 2021 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 2022 if (!kvm_check_tsc_unstable()) { 2023 offset = kvm->arch.cur_tsc_offset; 2024 } else { 2025 u64 delta = nsec_to_cycles(vcpu, elapsed); 2026 data += delta; 2027 offset = kvm_compute_tsc_offset(vcpu, data); 2028 } 2029 matched = true; 2030 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 2031 } else { 2032 /* 2033 * We split periods of matched TSC writes into generations. 2034 * For each generation, we track the original measured 2035 * nanosecond time, offset, and write, so if TSCs are in 2036 * sync, we can match exact offset, and if not, we can match 2037 * exact software computation in compute_guest_tsc() 2038 * 2039 * These values are tracked in kvm->arch.cur_xxx variables. 2040 */ 2041 kvm->arch.cur_tsc_generation++; 2042 kvm->arch.cur_tsc_nsec = ns; 2043 kvm->arch.cur_tsc_write = data; 2044 kvm->arch.cur_tsc_offset = offset; 2045 matched = false; 2046 } 2047 2048 /* 2049 * We also track th most recent recorded KHZ, write and time to 2050 * allow the matching interval to be extended at each write. 2051 */ 2052 kvm->arch.last_tsc_nsec = ns; 2053 kvm->arch.last_tsc_write = data; 2054 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 2055 2056 vcpu->arch.last_guest_tsc = data; 2057 2058 /* Keep track of which generation this VCPU has synchronized to */ 2059 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 2060 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 2061 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 2062 2063 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) 2064 update_ia32_tsc_adjust_msr(vcpu, offset); 2065 2066 kvm_vcpu_write_tsc_offset(vcpu, offset); 2067 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 2068 2069 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 2070 if (!matched) { 2071 kvm->arch.nr_vcpus_matched_tsc = 0; 2072 } else if (!already_matched) { 2073 kvm->arch.nr_vcpus_matched_tsc++; 2074 } 2075 2076 kvm_track_tsc_matching(vcpu); 2077 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 2078 } 2079 2080 EXPORT_SYMBOL_GPL(kvm_write_tsc); 2081 2082 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 2083 s64 adjustment) 2084 { 2085 u64 tsc_offset = kvm_x86_ops.read_l1_tsc_offset(vcpu); 2086 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 2087 } 2088 2089 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 2090 { 2091 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 2092 WARN_ON(adjustment < 0); 2093 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 2094 adjust_tsc_offset_guest(vcpu, adjustment); 2095 } 2096 2097 #ifdef CONFIG_X86_64 2098 2099 static u64 read_tsc(void) 2100 { 2101 u64 ret = (u64)rdtsc_ordered(); 2102 u64 last = pvclock_gtod_data.clock.cycle_last; 2103 2104 if (likely(ret >= last)) 2105 return ret; 2106 2107 /* 2108 * GCC likes to generate cmov here, but this branch is extremely 2109 * predictable (it's just a function of time and the likely is 2110 * very likely) and there's a data dependence, so force GCC 2111 * to generate a branch instead. I don't barrier() because 2112 * we don't actually need a barrier, and if this function 2113 * ever gets inlined it will generate worse code. 2114 */ 2115 asm volatile (""); 2116 return last; 2117 } 2118 2119 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, 2120 int *mode) 2121 { 2122 long v; 2123 u64 tsc_pg_val; 2124 2125 switch (clock->vclock_mode) { 2126 case VDSO_CLOCKMODE_HVCLOCK: 2127 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 2128 tsc_timestamp); 2129 if (tsc_pg_val != U64_MAX) { 2130 /* TSC page valid */ 2131 *mode = VDSO_CLOCKMODE_HVCLOCK; 2132 v = (tsc_pg_val - clock->cycle_last) & 2133 clock->mask; 2134 } else { 2135 /* TSC page invalid */ 2136 *mode = VDSO_CLOCKMODE_NONE; 2137 } 2138 break; 2139 case VDSO_CLOCKMODE_TSC: 2140 *mode = VDSO_CLOCKMODE_TSC; 2141 *tsc_timestamp = read_tsc(); 2142 v = (*tsc_timestamp - clock->cycle_last) & 2143 clock->mask; 2144 break; 2145 default: 2146 *mode = VDSO_CLOCKMODE_NONE; 2147 } 2148 2149 if (*mode == VDSO_CLOCKMODE_NONE) 2150 *tsc_timestamp = v = 0; 2151 2152 return v * clock->mult; 2153 } 2154 2155 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) 2156 { 2157 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2158 unsigned long seq; 2159 int mode; 2160 u64 ns; 2161 2162 do { 2163 seq = read_seqcount_begin(>od->seq); 2164 ns = gtod->raw_clock.base_cycles; 2165 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); 2166 ns >>= gtod->raw_clock.shift; 2167 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); 2168 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2169 *t = ns; 2170 2171 return mode; 2172 } 2173 2174 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 2175 { 2176 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2177 unsigned long seq; 2178 int mode; 2179 u64 ns; 2180 2181 do { 2182 seq = read_seqcount_begin(>od->seq); 2183 ts->tv_sec = gtod->wall_time_sec; 2184 ns = gtod->clock.base_cycles; 2185 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2186 ns >>= gtod->clock.shift; 2187 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2188 2189 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 2190 ts->tv_nsec = ns; 2191 2192 return mode; 2193 } 2194 2195 /* returns true if host is using TSC based clocksource */ 2196 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2197 { 2198 /* checked again under seqlock below */ 2199 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2200 return false; 2201 2202 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, 2203 tsc_timestamp)); 2204 } 2205 2206 /* returns true if host is using TSC based clocksource */ 2207 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 2208 u64 *tsc_timestamp) 2209 { 2210 /* checked again under seqlock below */ 2211 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2212 return false; 2213 2214 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 2215 } 2216 #endif 2217 2218 /* 2219 * 2220 * Assuming a stable TSC across physical CPUS, and a stable TSC 2221 * across virtual CPUs, the following condition is possible. 2222 * Each numbered line represents an event visible to both 2223 * CPUs at the next numbered event. 2224 * 2225 * "timespecX" represents host monotonic time. "tscX" represents 2226 * RDTSC value. 2227 * 2228 * VCPU0 on CPU0 | VCPU1 on CPU1 2229 * 2230 * 1. read timespec0,tsc0 2231 * 2. | timespec1 = timespec0 + N 2232 * | tsc1 = tsc0 + M 2233 * 3. transition to guest | transition to guest 2234 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 2235 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 2236 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 2237 * 2238 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 2239 * 2240 * - ret0 < ret1 2241 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 2242 * ... 2243 * - 0 < N - M => M < N 2244 * 2245 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 2246 * always the case (the difference between two distinct xtime instances 2247 * might be smaller then the difference between corresponding TSC reads, 2248 * when updating guest vcpus pvclock areas). 2249 * 2250 * To avoid that problem, do not allow visibility of distinct 2251 * system_timestamp/tsc_timestamp values simultaneously: use a master 2252 * copy of host monotonic time values. Update that master copy 2253 * in lockstep. 2254 * 2255 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2256 * 2257 */ 2258 2259 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2260 { 2261 #ifdef CONFIG_X86_64 2262 struct kvm_arch *ka = &kvm->arch; 2263 int vclock_mode; 2264 bool host_tsc_clocksource, vcpus_matched; 2265 2266 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2267 atomic_read(&kvm->online_vcpus)); 2268 2269 /* 2270 * If the host uses TSC clock, then passthrough TSC as stable 2271 * to the guest. 2272 */ 2273 host_tsc_clocksource = kvm_get_time_and_clockread( 2274 &ka->master_kernel_ns, 2275 &ka->master_cycle_now); 2276 2277 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2278 && !ka->backwards_tsc_observed 2279 && !ka->boot_vcpu_runs_old_kvmclock; 2280 2281 if (ka->use_master_clock) 2282 atomic_set(&kvm_guest_has_master_clock, 1); 2283 2284 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2285 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2286 vcpus_matched); 2287 #endif 2288 } 2289 2290 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2291 { 2292 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2293 } 2294 2295 static void kvm_gen_update_masterclock(struct kvm *kvm) 2296 { 2297 #ifdef CONFIG_X86_64 2298 int i; 2299 struct kvm_vcpu *vcpu; 2300 struct kvm_arch *ka = &kvm->arch; 2301 2302 spin_lock(&ka->pvclock_gtod_sync_lock); 2303 kvm_make_mclock_inprogress_request(kvm); 2304 /* no guest entries from this point */ 2305 pvclock_update_vm_gtod_copy(kvm); 2306 2307 kvm_for_each_vcpu(i, vcpu, kvm) 2308 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2309 2310 /* guest entries allowed */ 2311 kvm_for_each_vcpu(i, vcpu, kvm) 2312 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2313 2314 spin_unlock(&ka->pvclock_gtod_sync_lock); 2315 #endif 2316 } 2317 2318 u64 get_kvmclock_ns(struct kvm *kvm) 2319 { 2320 struct kvm_arch *ka = &kvm->arch; 2321 struct pvclock_vcpu_time_info hv_clock; 2322 u64 ret; 2323 2324 spin_lock(&ka->pvclock_gtod_sync_lock); 2325 if (!ka->use_master_clock) { 2326 spin_unlock(&ka->pvclock_gtod_sync_lock); 2327 return get_kvmclock_base_ns() + ka->kvmclock_offset; 2328 } 2329 2330 hv_clock.tsc_timestamp = ka->master_cycle_now; 2331 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2332 spin_unlock(&ka->pvclock_gtod_sync_lock); 2333 2334 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2335 get_cpu(); 2336 2337 if (__this_cpu_read(cpu_tsc_khz)) { 2338 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2339 &hv_clock.tsc_shift, 2340 &hv_clock.tsc_to_system_mul); 2341 ret = __pvclock_read_cycles(&hv_clock, rdtsc()); 2342 } else 2343 ret = get_kvmclock_base_ns() + ka->kvmclock_offset; 2344 2345 put_cpu(); 2346 2347 return ret; 2348 } 2349 2350 static void kvm_setup_pvclock_page(struct kvm_vcpu *v) 2351 { 2352 struct kvm_vcpu_arch *vcpu = &v->arch; 2353 struct pvclock_vcpu_time_info guest_hv_clock; 2354 2355 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 2356 &guest_hv_clock, sizeof(guest_hv_clock)))) 2357 return; 2358 2359 /* This VCPU is paused, but it's legal for a guest to read another 2360 * VCPU's kvmclock, so we really have to follow the specification where 2361 * it says that version is odd if data is being modified, and even after 2362 * it is consistent. 2363 * 2364 * Version field updates must be kept separate. This is because 2365 * kvm_write_guest_cached might use a "rep movs" instruction, and 2366 * writes within a string instruction are weakly ordered. So there 2367 * are three writes overall. 2368 * 2369 * As a small optimization, only write the version field in the first 2370 * and third write. The vcpu->pv_time cache is still valid, because the 2371 * version field is the first in the struct. 2372 */ 2373 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 2374 2375 if (guest_hv_clock.version & 1) 2376 ++guest_hv_clock.version; /* first time write, random junk */ 2377 2378 vcpu->hv_clock.version = guest_hv_clock.version + 1; 2379 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2380 &vcpu->hv_clock, 2381 sizeof(vcpu->hv_clock.version)); 2382 2383 smp_wmb(); 2384 2385 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 2386 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 2387 2388 if (vcpu->pvclock_set_guest_stopped_request) { 2389 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 2390 vcpu->pvclock_set_guest_stopped_request = false; 2391 } 2392 2393 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 2394 2395 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2396 &vcpu->hv_clock, 2397 sizeof(vcpu->hv_clock)); 2398 2399 smp_wmb(); 2400 2401 vcpu->hv_clock.version++; 2402 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 2403 &vcpu->hv_clock, 2404 sizeof(vcpu->hv_clock.version)); 2405 } 2406 2407 static int kvm_guest_time_update(struct kvm_vcpu *v) 2408 { 2409 unsigned long flags, tgt_tsc_khz; 2410 struct kvm_vcpu_arch *vcpu = &v->arch; 2411 struct kvm_arch *ka = &v->kvm->arch; 2412 s64 kernel_ns; 2413 u64 tsc_timestamp, host_tsc; 2414 u8 pvclock_flags; 2415 bool use_master_clock; 2416 2417 kernel_ns = 0; 2418 host_tsc = 0; 2419 2420 /* 2421 * If the host uses TSC clock, then passthrough TSC as stable 2422 * to the guest. 2423 */ 2424 spin_lock(&ka->pvclock_gtod_sync_lock); 2425 use_master_clock = ka->use_master_clock; 2426 if (use_master_clock) { 2427 host_tsc = ka->master_cycle_now; 2428 kernel_ns = ka->master_kernel_ns; 2429 } 2430 spin_unlock(&ka->pvclock_gtod_sync_lock); 2431 2432 /* Keep irq disabled to prevent changes to the clock */ 2433 local_irq_save(flags); 2434 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 2435 if (unlikely(tgt_tsc_khz == 0)) { 2436 local_irq_restore(flags); 2437 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2438 return 1; 2439 } 2440 if (!use_master_clock) { 2441 host_tsc = rdtsc(); 2442 kernel_ns = get_kvmclock_base_ns(); 2443 } 2444 2445 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 2446 2447 /* 2448 * We may have to catch up the TSC to match elapsed wall clock 2449 * time for two reasons, even if kvmclock is used. 2450 * 1) CPU could have been running below the maximum TSC rate 2451 * 2) Broken TSC compensation resets the base at each VCPU 2452 * entry to avoid unknown leaps of TSC even when running 2453 * again on the same CPU. This may cause apparent elapsed 2454 * time to disappear, and the guest to stand still or run 2455 * very slowly. 2456 */ 2457 if (vcpu->tsc_catchup) { 2458 u64 tsc = compute_guest_tsc(v, kernel_ns); 2459 if (tsc > tsc_timestamp) { 2460 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 2461 tsc_timestamp = tsc; 2462 } 2463 } 2464 2465 local_irq_restore(flags); 2466 2467 /* With all the info we got, fill in the values */ 2468 2469 if (kvm_has_tsc_control) 2470 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 2471 2472 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 2473 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 2474 &vcpu->hv_clock.tsc_shift, 2475 &vcpu->hv_clock.tsc_to_system_mul); 2476 vcpu->hw_tsc_khz = tgt_tsc_khz; 2477 } 2478 2479 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 2480 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 2481 vcpu->last_guest_tsc = tsc_timestamp; 2482 2483 /* If the host uses TSC clocksource, then it is stable */ 2484 pvclock_flags = 0; 2485 if (use_master_clock) 2486 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 2487 2488 vcpu->hv_clock.flags = pvclock_flags; 2489 2490 if (vcpu->pv_time_enabled) 2491 kvm_setup_pvclock_page(v); 2492 if (v == kvm_get_vcpu(v->kvm, 0)) 2493 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 2494 return 0; 2495 } 2496 2497 /* 2498 * kvmclock updates which are isolated to a given vcpu, such as 2499 * vcpu->cpu migration, should not allow system_timestamp from 2500 * the rest of the vcpus to remain static. Otherwise ntp frequency 2501 * correction applies to one vcpu's system_timestamp but not 2502 * the others. 2503 * 2504 * So in those cases, request a kvmclock update for all vcpus. 2505 * We need to rate-limit these requests though, as they can 2506 * considerably slow guests that have a large number of vcpus. 2507 * The time for a remote vcpu to update its kvmclock is bound 2508 * by the delay we use to rate-limit the updates. 2509 */ 2510 2511 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 2512 2513 static void kvmclock_update_fn(struct work_struct *work) 2514 { 2515 int i; 2516 struct delayed_work *dwork = to_delayed_work(work); 2517 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2518 kvmclock_update_work); 2519 struct kvm *kvm = container_of(ka, struct kvm, arch); 2520 struct kvm_vcpu *vcpu; 2521 2522 kvm_for_each_vcpu(i, vcpu, kvm) { 2523 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2524 kvm_vcpu_kick(vcpu); 2525 } 2526 } 2527 2528 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 2529 { 2530 struct kvm *kvm = v->kvm; 2531 2532 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2533 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 2534 KVMCLOCK_UPDATE_DELAY); 2535 } 2536 2537 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 2538 2539 static void kvmclock_sync_fn(struct work_struct *work) 2540 { 2541 struct delayed_work *dwork = to_delayed_work(work); 2542 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2543 kvmclock_sync_work); 2544 struct kvm *kvm = container_of(ka, struct kvm, arch); 2545 2546 if (!kvmclock_periodic_sync) 2547 return; 2548 2549 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 2550 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 2551 KVMCLOCK_SYNC_PERIOD); 2552 } 2553 2554 /* 2555 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 2556 */ 2557 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 2558 { 2559 /* McStatusWrEn enabled? */ 2560 if (guest_cpuid_is_amd_or_hygon(vcpu)) 2561 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 2562 2563 return false; 2564 } 2565 2566 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2567 { 2568 u64 mcg_cap = vcpu->arch.mcg_cap; 2569 unsigned bank_num = mcg_cap & 0xff; 2570 u32 msr = msr_info->index; 2571 u64 data = msr_info->data; 2572 2573 switch (msr) { 2574 case MSR_IA32_MCG_STATUS: 2575 vcpu->arch.mcg_status = data; 2576 break; 2577 case MSR_IA32_MCG_CTL: 2578 if (!(mcg_cap & MCG_CTL_P) && 2579 (data || !msr_info->host_initiated)) 2580 return 1; 2581 if (data != 0 && data != ~(u64)0) 2582 return 1; 2583 vcpu->arch.mcg_ctl = data; 2584 break; 2585 default: 2586 if (msr >= MSR_IA32_MC0_CTL && 2587 msr < MSR_IA32_MCx_CTL(bank_num)) { 2588 u32 offset = array_index_nospec( 2589 msr - MSR_IA32_MC0_CTL, 2590 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 2591 2592 /* only 0 or all 1s can be written to IA32_MCi_CTL 2593 * some Linux kernels though clear bit 10 in bank 4 to 2594 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 2595 * this to avoid an uncatched #GP in the guest 2596 */ 2597 if ((offset & 0x3) == 0 && 2598 data != 0 && (data | (1 << 10)) != ~(u64)0) 2599 return -1; 2600 2601 /* MCi_STATUS */ 2602 if (!msr_info->host_initiated && 2603 (offset & 0x3) == 1 && data != 0) { 2604 if (!can_set_mci_status(vcpu)) 2605 return -1; 2606 } 2607 2608 vcpu->arch.mce_banks[offset] = data; 2609 break; 2610 } 2611 return 1; 2612 } 2613 return 0; 2614 } 2615 2616 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 2617 { 2618 struct kvm *kvm = vcpu->kvm; 2619 int lm = is_long_mode(vcpu); 2620 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 2621 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 2622 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 2623 : kvm->arch.xen_hvm_config.blob_size_32; 2624 u32 page_num = data & ~PAGE_MASK; 2625 u64 page_addr = data & PAGE_MASK; 2626 u8 *page; 2627 int r; 2628 2629 r = -E2BIG; 2630 if (page_num >= blob_size) 2631 goto out; 2632 r = -ENOMEM; 2633 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 2634 if (IS_ERR(page)) { 2635 r = PTR_ERR(page); 2636 goto out; 2637 } 2638 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 2639 goto out_free; 2640 r = 0; 2641 out_free: 2642 kfree(page); 2643 out: 2644 return r; 2645 } 2646 2647 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2648 { 2649 gpa_t gpa = data & ~0x3f; 2650 2651 /* Bits 3:5 are reserved, Should be zero */ 2652 if (data & 0x38) 2653 return 1; 2654 2655 vcpu->arch.apf.msr_val = data; 2656 2657 if (!(data & KVM_ASYNC_PF_ENABLED)) { 2658 kvm_clear_async_pf_completion_queue(vcpu); 2659 kvm_async_pf_hash_reset(vcpu); 2660 return 0; 2661 } 2662 2663 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2664 sizeof(u32))) 2665 return 1; 2666 2667 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2668 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 2669 kvm_async_pf_wakeup_all(vcpu); 2670 return 0; 2671 } 2672 2673 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2674 { 2675 vcpu->arch.pv_time_enabled = false; 2676 vcpu->arch.time = 0; 2677 } 2678 2679 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) 2680 { 2681 ++vcpu->stat.tlb_flush; 2682 kvm_x86_ops.tlb_flush(vcpu, invalidate_gpa); 2683 } 2684 2685 static void record_steal_time(struct kvm_vcpu *vcpu) 2686 { 2687 struct kvm_host_map map; 2688 struct kvm_steal_time *st; 2689 2690 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2691 return; 2692 2693 /* -EAGAIN is returned in atomic context so we can just return. */ 2694 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, 2695 &map, &vcpu->arch.st.cache, false)) 2696 return; 2697 2698 st = map.hva + 2699 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 2700 2701 /* 2702 * Doing a TLB flush here, on the guest's behalf, can avoid 2703 * expensive IPIs. 2704 */ 2705 trace_kvm_pv_tlb_flush(vcpu->vcpu_id, 2706 st->preempted & KVM_VCPU_FLUSH_TLB); 2707 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB) 2708 kvm_vcpu_flush_tlb(vcpu, false); 2709 2710 vcpu->arch.st.preempted = 0; 2711 2712 if (st->version & 1) 2713 st->version += 1; /* first time write, random junk */ 2714 2715 st->version += 1; 2716 2717 smp_wmb(); 2718 2719 st->steal += current->sched_info.run_delay - 2720 vcpu->arch.st.last_steal; 2721 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2722 2723 smp_wmb(); 2724 2725 st->version += 1; 2726 2727 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); 2728 } 2729 2730 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2731 { 2732 bool pr = false; 2733 u32 msr = msr_info->index; 2734 u64 data = msr_info->data; 2735 2736 switch (msr) { 2737 case MSR_AMD64_NB_CFG: 2738 case MSR_IA32_UCODE_WRITE: 2739 case MSR_VM_HSAVE_PA: 2740 case MSR_AMD64_PATCH_LOADER: 2741 case MSR_AMD64_BU_CFG2: 2742 case MSR_AMD64_DC_CFG: 2743 case MSR_F15H_EX_CFG: 2744 break; 2745 2746 case MSR_IA32_UCODE_REV: 2747 if (msr_info->host_initiated) 2748 vcpu->arch.microcode_version = data; 2749 break; 2750 case MSR_IA32_ARCH_CAPABILITIES: 2751 if (!msr_info->host_initiated) 2752 return 1; 2753 vcpu->arch.arch_capabilities = data; 2754 break; 2755 case MSR_EFER: 2756 return set_efer(vcpu, msr_info); 2757 case MSR_K7_HWCR: 2758 data &= ~(u64)0x40; /* ignore flush filter disable */ 2759 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2760 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2761 2762 /* Handle McStatusWrEn */ 2763 if (data == BIT_ULL(18)) { 2764 vcpu->arch.msr_hwcr = data; 2765 } else if (data != 0) { 2766 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2767 data); 2768 return 1; 2769 } 2770 break; 2771 case MSR_FAM10H_MMIO_CONF_BASE: 2772 if (data != 0) { 2773 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2774 "0x%llx\n", data); 2775 return 1; 2776 } 2777 break; 2778 case MSR_IA32_DEBUGCTLMSR: 2779 if (!data) { 2780 /* We support the non-activated case already */ 2781 break; 2782 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2783 /* Values other than LBR and BTF are vendor-specific, 2784 thus reserved and should throw a #GP */ 2785 return 1; 2786 } 2787 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2788 __func__, data); 2789 break; 2790 case 0x200 ... 0x2ff: 2791 return kvm_mtrr_set_msr(vcpu, msr, data); 2792 case MSR_IA32_APICBASE: 2793 return kvm_set_apic_base(vcpu, msr_info); 2794 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2795 return kvm_x2apic_msr_write(vcpu, msr, data); 2796 case MSR_IA32_TSCDEADLINE: 2797 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2798 break; 2799 case MSR_IA32_TSC_ADJUST: 2800 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 2801 if (!msr_info->host_initiated) { 2802 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2803 adjust_tsc_offset_guest(vcpu, adj); 2804 } 2805 vcpu->arch.ia32_tsc_adjust_msr = data; 2806 } 2807 break; 2808 case MSR_IA32_MISC_ENABLE: 2809 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && 2810 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { 2811 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) 2812 return 1; 2813 vcpu->arch.ia32_misc_enable_msr = data; 2814 kvm_update_cpuid(vcpu); 2815 } else { 2816 vcpu->arch.ia32_misc_enable_msr = data; 2817 } 2818 break; 2819 case MSR_IA32_SMBASE: 2820 if (!msr_info->host_initiated) 2821 return 1; 2822 vcpu->arch.smbase = data; 2823 break; 2824 case MSR_IA32_POWER_CTL: 2825 vcpu->arch.msr_ia32_power_ctl = data; 2826 break; 2827 case MSR_IA32_TSC: 2828 kvm_write_tsc(vcpu, msr_info); 2829 break; 2830 case MSR_IA32_XSS: 2831 if (!msr_info->host_initiated && 2832 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 2833 return 1; 2834 /* 2835 * KVM supports exposing PT to the guest, but does not support 2836 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than 2837 * XSAVES/XRSTORS to save/restore PT MSRs. 2838 */ 2839 if (data & ~supported_xss) 2840 return 1; 2841 vcpu->arch.ia32_xss = data; 2842 break; 2843 case MSR_SMI_COUNT: 2844 if (!msr_info->host_initiated) 2845 return 1; 2846 vcpu->arch.smi_count = data; 2847 break; 2848 case MSR_KVM_WALL_CLOCK_NEW: 2849 case MSR_KVM_WALL_CLOCK: 2850 vcpu->kvm->arch.wall_clock = data; 2851 kvm_write_wall_clock(vcpu->kvm, data); 2852 break; 2853 case MSR_KVM_SYSTEM_TIME_NEW: 2854 case MSR_KVM_SYSTEM_TIME: { 2855 struct kvm_arch *ka = &vcpu->kvm->arch; 2856 2857 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2858 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2859 2860 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2861 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2862 2863 ka->boot_vcpu_runs_old_kvmclock = tmp; 2864 } 2865 2866 vcpu->arch.time = data; 2867 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2868 2869 /* we verify if the enable bit is set... */ 2870 vcpu->arch.pv_time_enabled = false; 2871 if (!(data & 1)) 2872 break; 2873 2874 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, 2875 &vcpu->arch.pv_time, data & ~1ULL, 2876 sizeof(struct pvclock_vcpu_time_info))) 2877 vcpu->arch.pv_time_enabled = true; 2878 2879 break; 2880 } 2881 case MSR_KVM_ASYNC_PF_EN: 2882 if (kvm_pv_enable_async_pf(vcpu, data)) 2883 return 1; 2884 break; 2885 case MSR_KVM_STEAL_TIME: 2886 2887 if (unlikely(!sched_info_on())) 2888 return 1; 2889 2890 if (data & KVM_STEAL_RESERVED_MASK) 2891 return 1; 2892 2893 vcpu->arch.st.msr_val = data; 2894 2895 if (!(data & KVM_MSR_ENABLED)) 2896 break; 2897 2898 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2899 2900 break; 2901 case MSR_KVM_PV_EOI_EN: 2902 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) 2903 return 1; 2904 break; 2905 2906 case MSR_KVM_POLL_CONTROL: 2907 /* only enable bit supported */ 2908 if (data & (-1ULL << 1)) 2909 return 1; 2910 2911 vcpu->arch.msr_kvm_poll_control = data; 2912 break; 2913 2914 case MSR_IA32_MCG_CTL: 2915 case MSR_IA32_MCG_STATUS: 2916 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2917 return set_msr_mce(vcpu, msr_info); 2918 2919 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2920 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2921 pr = true; /* fall through */ 2922 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2923 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2924 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2925 return kvm_pmu_set_msr(vcpu, msr_info); 2926 2927 if (pr || data != 0) 2928 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2929 "0x%x data 0x%llx\n", msr, data); 2930 break; 2931 case MSR_K7_CLK_CTL: 2932 /* 2933 * Ignore all writes to this no longer documented MSR. 2934 * Writes are only relevant for old K7 processors, 2935 * all pre-dating SVM, but a recommended workaround from 2936 * AMD for these chips. It is possible to specify the 2937 * affected processor models on the command line, hence 2938 * the need to ignore the workaround. 2939 */ 2940 break; 2941 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2942 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2943 case HV_X64_MSR_CRASH_CTL: 2944 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2945 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 2946 case HV_X64_MSR_TSC_EMULATION_CONTROL: 2947 case HV_X64_MSR_TSC_EMULATION_STATUS: 2948 return kvm_hv_set_msr_common(vcpu, msr, data, 2949 msr_info->host_initiated); 2950 case MSR_IA32_BBL_CR_CTL3: 2951 /* Drop writes to this legacy MSR -- see rdmsr 2952 * counterpart for further detail. 2953 */ 2954 if (report_ignored_msrs) 2955 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 2956 msr, data); 2957 break; 2958 case MSR_AMD64_OSVW_ID_LENGTH: 2959 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2960 return 1; 2961 vcpu->arch.osvw.length = data; 2962 break; 2963 case MSR_AMD64_OSVW_STATUS: 2964 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2965 return 1; 2966 vcpu->arch.osvw.status = data; 2967 break; 2968 case MSR_PLATFORM_INFO: 2969 if (!msr_info->host_initiated || 2970 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 2971 cpuid_fault_enabled(vcpu))) 2972 return 1; 2973 vcpu->arch.msr_platform_info = data; 2974 break; 2975 case MSR_MISC_FEATURES_ENABLES: 2976 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 2977 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 2978 !supports_cpuid_fault(vcpu))) 2979 return 1; 2980 vcpu->arch.msr_misc_features_enables = data; 2981 break; 2982 default: 2983 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2984 return xen_hvm_config(vcpu, data); 2985 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2986 return kvm_pmu_set_msr(vcpu, msr_info); 2987 if (!ignore_msrs) { 2988 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n", 2989 msr, data); 2990 return 1; 2991 } else { 2992 if (report_ignored_msrs) 2993 vcpu_unimpl(vcpu, 2994 "ignored wrmsr: 0x%x data 0x%llx\n", 2995 msr, data); 2996 break; 2997 } 2998 } 2999 return 0; 3000 } 3001 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 3002 3003 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 3004 { 3005 u64 data; 3006 u64 mcg_cap = vcpu->arch.mcg_cap; 3007 unsigned bank_num = mcg_cap & 0xff; 3008 3009 switch (msr) { 3010 case MSR_IA32_P5_MC_ADDR: 3011 case MSR_IA32_P5_MC_TYPE: 3012 data = 0; 3013 break; 3014 case MSR_IA32_MCG_CAP: 3015 data = vcpu->arch.mcg_cap; 3016 break; 3017 case MSR_IA32_MCG_CTL: 3018 if (!(mcg_cap & MCG_CTL_P) && !host) 3019 return 1; 3020 data = vcpu->arch.mcg_ctl; 3021 break; 3022 case MSR_IA32_MCG_STATUS: 3023 data = vcpu->arch.mcg_status; 3024 break; 3025 default: 3026 if (msr >= MSR_IA32_MC0_CTL && 3027 msr < MSR_IA32_MCx_CTL(bank_num)) { 3028 u32 offset = array_index_nospec( 3029 msr - MSR_IA32_MC0_CTL, 3030 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3031 3032 data = vcpu->arch.mce_banks[offset]; 3033 break; 3034 } 3035 return 1; 3036 } 3037 *pdata = data; 3038 return 0; 3039 } 3040 3041 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3042 { 3043 switch (msr_info->index) { 3044 case MSR_IA32_PLATFORM_ID: 3045 case MSR_IA32_EBL_CR_POWERON: 3046 case MSR_IA32_DEBUGCTLMSR: 3047 case MSR_IA32_LASTBRANCHFROMIP: 3048 case MSR_IA32_LASTBRANCHTOIP: 3049 case MSR_IA32_LASTINTFROMIP: 3050 case MSR_IA32_LASTINTTOIP: 3051 case MSR_K8_SYSCFG: 3052 case MSR_K8_TSEG_ADDR: 3053 case MSR_K8_TSEG_MASK: 3054 case MSR_VM_HSAVE_PA: 3055 case MSR_K8_INT_PENDING_MSG: 3056 case MSR_AMD64_NB_CFG: 3057 case MSR_FAM10H_MMIO_CONF_BASE: 3058 case MSR_AMD64_BU_CFG2: 3059 case MSR_IA32_PERF_CTL: 3060 case MSR_AMD64_DC_CFG: 3061 case MSR_F15H_EX_CFG: 3062 msr_info->data = 0; 3063 break; 3064 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3065 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3066 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3067 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3068 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3069 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3070 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 3071 msr_info->data = 0; 3072 break; 3073 case MSR_IA32_UCODE_REV: 3074 msr_info->data = vcpu->arch.microcode_version; 3075 break; 3076 case MSR_IA32_ARCH_CAPABILITIES: 3077 if (!msr_info->host_initiated && 3078 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 3079 return 1; 3080 msr_info->data = vcpu->arch.arch_capabilities; 3081 break; 3082 case MSR_IA32_POWER_CTL: 3083 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 3084 break; 3085 case MSR_IA32_TSC: 3086 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset; 3087 break; 3088 case MSR_MTRRcap: 3089 case 0x200 ... 0x2ff: 3090 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 3091 case 0xcd: /* fsb frequency */ 3092 msr_info->data = 3; 3093 break; 3094 /* 3095 * MSR_EBC_FREQUENCY_ID 3096 * Conservative value valid for even the basic CPU models. 3097 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 3098 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 3099 * and 266MHz for model 3, or 4. Set Core Clock 3100 * Frequency to System Bus Frequency Ratio to 1 (bits 3101 * 31:24) even though these are only valid for CPU 3102 * models > 2, however guests may end up dividing or 3103 * multiplying by zero otherwise. 3104 */ 3105 case MSR_EBC_FREQUENCY_ID: 3106 msr_info->data = 1 << 24; 3107 break; 3108 case MSR_IA32_APICBASE: 3109 msr_info->data = kvm_get_apic_base(vcpu); 3110 break; 3111 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 3112 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 3113 case MSR_IA32_TSCDEADLINE: 3114 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 3115 break; 3116 case MSR_IA32_TSC_ADJUST: 3117 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 3118 break; 3119 case MSR_IA32_MISC_ENABLE: 3120 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 3121 break; 3122 case MSR_IA32_SMBASE: 3123 if (!msr_info->host_initiated) 3124 return 1; 3125 msr_info->data = vcpu->arch.smbase; 3126 break; 3127 case MSR_SMI_COUNT: 3128 msr_info->data = vcpu->arch.smi_count; 3129 break; 3130 case MSR_IA32_PERF_STATUS: 3131 /* TSC increment by tick */ 3132 msr_info->data = 1000ULL; 3133 /* CPU multiplier */ 3134 msr_info->data |= (((uint64_t)4ULL) << 40); 3135 break; 3136 case MSR_EFER: 3137 msr_info->data = vcpu->arch.efer; 3138 break; 3139 case MSR_KVM_WALL_CLOCK: 3140 case MSR_KVM_WALL_CLOCK_NEW: 3141 msr_info->data = vcpu->kvm->arch.wall_clock; 3142 break; 3143 case MSR_KVM_SYSTEM_TIME: 3144 case MSR_KVM_SYSTEM_TIME_NEW: 3145 msr_info->data = vcpu->arch.time; 3146 break; 3147 case MSR_KVM_ASYNC_PF_EN: 3148 msr_info->data = vcpu->arch.apf.msr_val; 3149 break; 3150 case MSR_KVM_STEAL_TIME: 3151 msr_info->data = vcpu->arch.st.msr_val; 3152 break; 3153 case MSR_KVM_PV_EOI_EN: 3154 msr_info->data = vcpu->arch.pv_eoi.msr_val; 3155 break; 3156 case MSR_KVM_POLL_CONTROL: 3157 msr_info->data = vcpu->arch.msr_kvm_poll_control; 3158 break; 3159 case MSR_IA32_P5_MC_ADDR: 3160 case MSR_IA32_P5_MC_TYPE: 3161 case MSR_IA32_MCG_CAP: 3162 case MSR_IA32_MCG_CTL: 3163 case MSR_IA32_MCG_STATUS: 3164 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3165 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 3166 msr_info->host_initiated); 3167 case MSR_IA32_XSS: 3168 if (!msr_info->host_initiated && 3169 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3170 return 1; 3171 msr_info->data = vcpu->arch.ia32_xss; 3172 break; 3173 case MSR_K7_CLK_CTL: 3174 /* 3175 * Provide expected ramp-up count for K7. All other 3176 * are set to zero, indicating minimum divisors for 3177 * every field. 3178 * 3179 * This prevents guest kernels on AMD host with CPU 3180 * type 6, model 8 and higher from exploding due to 3181 * the rdmsr failing. 3182 */ 3183 msr_info->data = 0x20000000; 3184 break; 3185 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3186 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3187 case HV_X64_MSR_CRASH_CTL: 3188 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3189 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3190 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3191 case HV_X64_MSR_TSC_EMULATION_STATUS: 3192 return kvm_hv_get_msr_common(vcpu, 3193 msr_info->index, &msr_info->data, 3194 msr_info->host_initiated); 3195 case MSR_IA32_BBL_CR_CTL3: 3196 /* This legacy MSR exists but isn't fully documented in current 3197 * silicon. It is however accessed by winxp in very narrow 3198 * scenarios where it sets bit #19, itself documented as 3199 * a "reserved" bit. Best effort attempt to source coherent 3200 * read data here should the balance of the register be 3201 * interpreted by the guest: 3202 * 3203 * L2 cache control register 3: 64GB range, 256KB size, 3204 * enabled, latency 0x1, configured 3205 */ 3206 msr_info->data = 0xbe702111; 3207 break; 3208 case MSR_AMD64_OSVW_ID_LENGTH: 3209 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3210 return 1; 3211 msr_info->data = vcpu->arch.osvw.length; 3212 break; 3213 case MSR_AMD64_OSVW_STATUS: 3214 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3215 return 1; 3216 msr_info->data = vcpu->arch.osvw.status; 3217 break; 3218 case MSR_PLATFORM_INFO: 3219 if (!msr_info->host_initiated && 3220 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 3221 return 1; 3222 msr_info->data = vcpu->arch.msr_platform_info; 3223 break; 3224 case MSR_MISC_FEATURES_ENABLES: 3225 msr_info->data = vcpu->arch.msr_misc_features_enables; 3226 break; 3227 case MSR_K7_HWCR: 3228 msr_info->data = vcpu->arch.msr_hwcr; 3229 break; 3230 default: 3231 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3232 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 3233 if (!ignore_msrs) { 3234 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n", 3235 msr_info->index); 3236 return 1; 3237 } else { 3238 if (report_ignored_msrs) 3239 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", 3240 msr_info->index); 3241 msr_info->data = 0; 3242 } 3243 break; 3244 } 3245 return 0; 3246 } 3247 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 3248 3249 /* 3250 * Read or write a bunch of msrs. All parameters are kernel addresses. 3251 * 3252 * @return number of msrs set successfully. 3253 */ 3254 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 3255 struct kvm_msr_entry *entries, 3256 int (*do_msr)(struct kvm_vcpu *vcpu, 3257 unsigned index, u64 *data)) 3258 { 3259 int i; 3260 3261 for (i = 0; i < msrs->nmsrs; ++i) 3262 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 3263 break; 3264 3265 return i; 3266 } 3267 3268 /* 3269 * Read or write a bunch of msrs. Parameters are user addresses. 3270 * 3271 * @return number of msrs set successfully. 3272 */ 3273 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 3274 int (*do_msr)(struct kvm_vcpu *vcpu, 3275 unsigned index, u64 *data), 3276 int writeback) 3277 { 3278 struct kvm_msrs msrs; 3279 struct kvm_msr_entry *entries; 3280 int r, n; 3281 unsigned size; 3282 3283 r = -EFAULT; 3284 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 3285 goto out; 3286 3287 r = -E2BIG; 3288 if (msrs.nmsrs >= MAX_IO_MSRS) 3289 goto out; 3290 3291 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 3292 entries = memdup_user(user_msrs->entries, size); 3293 if (IS_ERR(entries)) { 3294 r = PTR_ERR(entries); 3295 goto out; 3296 } 3297 3298 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 3299 if (r < 0) 3300 goto out_free; 3301 3302 r = -EFAULT; 3303 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 3304 goto out_free; 3305 3306 r = n; 3307 3308 out_free: 3309 kfree(entries); 3310 out: 3311 return r; 3312 } 3313 3314 static inline bool kvm_can_mwait_in_guest(void) 3315 { 3316 return boot_cpu_has(X86_FEATURE_MWAIT) && 3317 !boot_cpu_has_bug(X86_BUG_MONITOR) && 3318 boot_cpu_has(X86_FEATURE_ARAT); 3319 } 3320 3321 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 3322 { 3323 int r = 0; 3324 3325 switch (ext) { 3326 case KVM_CAP_IRQCHIP: 3327 case KVM_CAP_HLT: 3328 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 3329 case KVM_CAP_SET_TSS_ADDR: 3330 case KVM_CAP_EXT_CPUID: 3331 case KVM_CAP_EXT_EMUL_CPUID: 3332 case KVM_CAP_CLOCKSOURCE: 3333 case KVM_CAP_PIT: 3334 case KVM_CAP_NOP_IO_DELAY: 3335 case KVM_CAP_MP_STATE: 3336 case KVM_CAP_SYNC_MMU: 3337 case KVM_CAP_USER_NMI: 3338 case KVM_CAP_REINJECT_CONTROL: 3339 case KVM_CAP_IRQ_INJECT_STATUS: 3340 case KVM_CAP_IOEVENTFD: 3341 case KVM_CAP_IOEVENTFD_NO_LENGTH: 3342 case KVM_CAP_PIT2: 3343 case KVM_CAP_PIT_STATE2: 3344 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 3345 case KVM_CAP_XEN_HVM: 3346 case KVM_CAP_VCPU_EVENTS: 3347 case KVM_CAP_HYPERV: 3348 case KVM_CAP_HYPERV_VAPIC: 3349 case KVM_CAP_HYPERV_SPIN: 3350 case KVM_CAP_HYPERV_SYNIC: 3351 case KVM_CAP_HYPERV_SYNIC2: 3352 case KVM_CAP_HYPERV_VP_INDEX: 3353 case KVM_CAP_HYPERV_EVENTFD: 3354 case KVM_CAP_HYPERV_TLBFLUSH: 3355 case KVM_CAP_HYPERV_SEND_IPI: 3356 case KVM_CAP_HYPERV_CPUID: 3357 case KVM_CAP_PCI_SEGMENT: 3358 case KVM_CAP_DEBUGREGS: 3359 case KVM_CAP_X86_ROBUST_SINGLESTEP: 3360 case KVM_CAP_XSAVE: 3361 case KVM_CAP_ASYNC_PF: 3362 case KVM_CAP_GET_TSC_KHZ: 3363 case KVM_CAP_KVMCLOCK_CTRL: 3364 case KVM_CAP_READONLY_MEM: 3365 case KVM_CAP_HYPERV_TIME: 3366 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 3367 case KVM_CAP_TSC_DEADLINE_TIMER: 3368 case KVM_CAP_DISABLE_QUIRKS: 3369 case KVM_CAP_SET_BOOT_CPU_ID: 3370 case KVM_CAP_SPLIT_IRQCHIP: 3371 case KVM_CAP_IMMEDIATE_EXIT: 3372 case KVM_CAP_PMU_EVENT_FILTER: 3373 case KVM_CAP_GET_MSR_FEATURES: 3374 case KVM_CAP_MSR_PLATFORM_INFO: 3375 case KVM_CAP_EXCEPTION_PAYLOAD: 3376 r = 1; 3377 break; 3378 case KVM_CAP_SYNC_REGS: 3379 r = KVM_SYNC_X86_VALID_FIELDS; 3380 break; 3381 case KVM_CAP_ADJUST_CLOCK: 3382 r = KVM_CLOCK_TSC_STABLE; 3383 break; 3384 case KVM_CAP_X86_DISABLE_EXITS: 3385 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | 3386 KVM_X86_DISABLE_EXITS_CSTATE; 3387 if(kvm_can_mwait_in_guest()) 3388 r |= KVM_X86_DISABLE_EXITS_MWAIT; 3389 break; 3390 case KVM_CAP_X86_SMM: 3391 /* SMBASE is usually relocated above 1M on modern chipsets, 3392 * and SMM handlers might indeed rely on 4G segment limits, 3393 * so do not report SMM to be available if real mode is 3394 * emulated via vm86 mode. Still, do not go to great lengths 3395 * to avoid userspace's usage of the feature, because it is a 3396 * fringe case that is not enabled except via specific settings 3397 * of the module parameters. 3398 */ 3399 r = kvm_x86_ops.has_emulated_msr(MSR_IA32_SMBASE); 3400 break; 3401 case KVM_CAP_VAPIC: 3402 r = !kvm_x86_ops.cpu_has_accelerated_tpr(); 3403 break; 3404 case KVM_CAP_NR_VCPUS: 3405 r = KVM_SOFT_MAX_VCPUS; 3406 break; 3407 case KVM_CAP_MAX_VCPUS: 3408 r = KVM_MAX_VCPUS; 3409 break; 3410 case KVM_CAP_MAX_VCPU_ID: 3411 r = KVM_MAX_VCPU_ID; 3412 break; 3413 case KVM_CAP_PV_MMU: /* obsolete */ 3414 r = 0; 3415 break; 3416 case KVM_CAP_MCE: 3417 r = KVM_MAX_MCE_BANKS; 3418 break; 3419 case KVM_CAP_XCRS: 3420 r = boot_cpu_has(X86_FEATURE_XSAVE); 3421 break; 3422 case KVM_CAP_TSC_CONTROL: 3423 r = kvm_has_tsc_control; 3424 break; 3425 case KVM_CAP_X2APIC_API: 3426 r = KVM_X2APIC_API_VALID_FLAGS; 3427 break; 3428 case KVM_CAP_NESTED_STATE: 3429 r = kvm_x86_ops.get_nested_state ? 3430 kvm_x86_ops.get_nested_state(NULL, NULL, 0) : 0; 3431 break; 3432 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 3433 r = kvm_x86_ops.enable_direct_tlbflush != NULL; 3434 break; 3435 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 3436 r = kvm_x86_ops.nested_enable_evmcs != NULL; 3437 break; 3438 default: 3439 break; 3440 } 3441 return r; 3442 3443 } 3444 3445 long kvm_arch_dev_ioctl(struct file *filp, 3446 unsigned int ioctl, unsigned long arg) 3447 { 3448 void __user *argp = (void __user *)arg; 3449 long r; 3450 3451 switch (ioctl) { 3452 case KVM_GET_MSR_INDEX_LIST: { 3453 struct kvm_msr_list __user *user_msr_list = argp; 3454 struct kvm_msr_list msr_list; 3455 unsigned n; 3456 3457 r = -EFAULT; 3458 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3459 goto out; 3460 n = msr_list.nmsrs; 3461 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 3462 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3463 goto out; 3464 r = -E2BIG; 3465 if (n < msr_list.nmsrs) 3466 goto out; 3467 r = -EFAULT; 3468 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 3469 num_msrs_to_save * sizeof(u32))) 3470 goto out; 3471 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 3472 &emulated_msrs, 3473 num_emulated_msrs * sizeof(u32))) 3474 goto out; 3475 r = 0; 3476 break; 3477 } 3478 case KVM_GET_SUPPORTED_CPUID: 3479 case KVM_GET_EMULATED_CPUID: { 3480 struct kvm_cpuid2 __user *cpuid_arg = argp; 3481 struct kvm_cpuid2 cpuid; 3482 3483 r = -EFAULT; 3484 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3485 goto out; 3486 3487 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 3488 ioctl); 3489 if (r) 3490 goto out; 3491 3492 r = -EFAULT; 3493 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 3494 goto out; 3495 r = 0; 3496 break; 3497 } 3498 case KVM_X86_GET_MCE_CAP_SUPPORTED: 3499 r = -EFAULT; 3500 if (copy_to_user(argp, &kvm_mce_cap_supported, 3501 sizeof(kvm_mce_cap_supported))) 3502 goto out; 3503 r = 0; 3504 break; 3505 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 3506 struct kvm_msr_list __user *user_msr_list = argp; 3507 struct kvm_msr_list msr_list; 3508 unsigned int n; 3509 3510 r = -EFAULT; 3511 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3512 goto out; 3513 n = msr_list.nmsrs; 3514 msr_list.nmsrs = num_msr_based_features; 3515 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3516 goto out; 3517 r = -E2BIG; 3518 if (n < msr_list.nmsrs) 3519 goto out; 3520 r = -EFAULT; 3521 if (copy_to_user(user_msr_list->indices, &msr_based_features, 3522 num_msr_based_features * sizeof(u32))) 3523 goto out; 3524 r = 0; 3525 break; 3526 } 3527 case KVM_GET_MSRS: 3528 r = msr_io(NULL, argp, do_get_msr_feature, 1); 3529 break; 3530 default: 3531 r = -EINVAL; 3532 break; 3533 } 3534 out: 3535 return r; 3536 } 3537 3538 static void wbinvd_ipi(void *garbage) 3539 { 3540 wbinvd(); 3541 } 3542 3543 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 3544 { 3545 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 3546 } 3547 3548 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 3549 { 3550 /* Address WBINVD may be executed by guest */ 3551 if (need_emulate_wbinvd(vcpu)) { 3552 if (kvm_x86_ops.has_wbinvd_exit()) 3553 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 3554 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 3555 smp_call_function_single(vcpu->cpu, 3556 wbinvd_ipi, NULL, 1); 3557 } 3558 3559 kvm_x86_ops.vcpu_load(vcpu, cpu); 3560 3561 /* Apply any externally detected TSC adjustments (due to suspend) */ 3562 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 3563 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 3564 vcpu->arch.tsc_offset_adjustment = 0; 3565 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3566 } 3567 3568 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 3569 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 3570 rdtsc() - vcpu->arch.last_host_tsc; 3571 if (tsc_delta < 0) 3572 mark_tsc_unstable("KVM discovered backwards TSC"); 3573 3574 if (kvm_check_tsc_unstable()) { 3575 u64 offset = kvm_compute_tsc_offset(vcpu, 3576 vcpu->arch.last_guest_tsc); 3577 kvm_vcpu_write_tsc_offset(vcpu, offset); 3578 vcpu->arch.tsc_catchup = 1; 3579 } 3580 3581 if (kvm_lapic_hv_timer_in_use(vcpu)) 3582 kvm_lapic_restart_hv_timer(vcpu); 3583 3584 /* 3585 * On a host with synchronized TSC, there is no need to update 3586 * kvmclock on vcpu->cpu migration 3587 */ 3588 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 3589 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 3590 if (vcpu->cpu != cpu) 3591 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 3592 vcpu->cpu = cpu; 3593 } 3594 3595 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3596 } 3597 3598 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 3599 { 3600 struct kvm_host_map map; 3601 struct kvm_steal_time *st; 3602 3603 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3604 return; 3605 3606 if (vcpu->arch.st.preempted) 3607 return; 3608 3609 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, 3610 &vcpu->arch.st.cache, true)) 3611 return; 3612 3613 st = map.hva + 3614 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 3615 3616 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 3617 3618 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); 3619 } 3620 3621 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 3622 { 3623 int idx; 3624 3625 if (vcpu->preempted) 3626 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu); 3627 3628 /* 3629 * Disable page faults because we're in atomic context here. 3630 * kvm_write_guest_offset_cached() would call might_fault() 3631 * that relies on pagefault_disable() to tell if there's a 3632 * bug. NOTE: the write to guest memory may not go through if 3633 * during postcopy live migration or if there's heavy guest 3634 * paging. 3635 */ 3636 pagefault_disable(); 3637 /* 3638 * kvm_memslots() will be called by 3639 * kvm_write_guest_offset_cached() so take the srcu lock. 3640 */ 3641 idx = srcu_read_lock(&vcpu->kvm->srcu); 3642 kvm_steal_time_set_preempted(vcpu); 3643 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3644 pagefault_enable(); 3645 kvm_x86_ops.vcpu_put(vcpu); 3646 vcpu->arch.last_host_tsc = rdtsc(); 3647 /* 3648 * If userspace has set any breakpoints or watchpoints, dr6 is restored 3649 * on every vmexit, but if not, we might have a stale dr6 from the 3650 * guest. do_debug expects dr6 to be cleared after it runs, do the same. 3651 */ 3652 set_debugreg(0, 6); 3653 } 3654 3655 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 3656 struct kvm_lapic_state *s) 3657 { 3658 if (vcpu->arch.apicv_active) 3659 kvm_x86_ops.sync_pir_to_irr(vcpu); 3660 3661 return kvm_apic_get_state(vcpu, s); 3662 } 3663 3664 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 3665 struct kvm_lapic_state *s) 3666 { 3667 int r; 3668 3669 r = kvm_apic_set_state(vcpu, s); 3670 if (r) 3671 return r; 3672 update_cr8_intercept(vcpu); 3673 3674 return 0; 3675 } 3676 3677 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 3678 { 3679 return (!lapic_in_kernel(vcpu) || 3680 kvm_apic_accept_pic_intr(vcpu)); 3681 } 3682 3683 /* 3684 * if userspace requested an interrupt window, check that the 3685 * interrupt window is open. 3686 * 3687 * No need to exit to userspace if we already have an interrupt queued. 3688 */ 3689 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 3690 { 3691 return kvm_arch_interrupt_allowed(vcpu) && 3692 !kvm_cpu_has_interrupt(vcpu) && 3693 !kvm_event_needs_reinjection(vcpu) && 3694 kvm_cpu_accept_dm_intr(vcpu); 3695 } 3696 3697 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 3698 struct kvm_interrupt *irq) 3699 { 3700 if (irq->irq >= KVM_NR_INTERRUPTS) 3701 return -EINVAL; 3702 3703 if (!irqchip_in_kernel(vcpu->kvm)) { 3704 kvm_queue_interrupt(vcpu, irq->irq, false); 3705 kvm_make_request(KVM_REQ_EVENT, vcpu); 3706 return 0; 3707 } 3708 3709 /* 3710 * With in-kernel LAPIC, we only use this to inject EXTINT, so 3711 * fail for in-kernel 8259. 3712 */ 3713 if (pic_in_kernel(vcpu->kvm)) 3714 return -ENXIO; 3715 3716 if (vcpu->arch.pending_external_vector != -1) 3717 return -EEXIST; 3718 3719 vcpu->arch.pending_external_vector = irq->irq; 3720 kvm_make_request(KVM_REQ_EVENT, vcpu); 3721 return 0; 3722 } 3723 3724 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 3725 { 3726 kvm_inject_nmi(vcpu); 3727 3728 return 0; 3729 } 3730 3731 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 3732 { 3733 kvm_make_request(KVM_REQ_SMI, vcpu); 3734 3735 return 0; 3736 } 3737 3738 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 3739 struct kvm_tpr_access_ctl *tac) 3740 { 3741 if (tac->flags) 3742 return -EINVAL; 3743 vcpu->arch.tpr_access_reporting = !!tac->enabled; 3744 return 0; 3745 } 3746 3747 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 3748 u64 mcg_cap) 3749 { 3750 int r; 3751 unsigned bank_num = mcg_cap & 0xff, bank; 3752 3753 r = -EINVAL; 3754 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 3755 goto out; 3756 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 3757 goto out; 3758 r = 0; 3759 vcpu->arch.mcg_cap = mcg_cap; 3760 /* Init IA32_MCG_CTL to all 1s */ 3761 if (mcg_cap & MCG_CTL_P) 3762 vcpu->arch.mcg_ctl = ~(u64)0; 3763 /* Init IA32_MCi_CTL to all 1s */ 3764 for (bank = 0; bank < bank_num; bank++) 3765 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 3766 3767 kvm_x86_ops.setup_mce(vcpu); 3768 out: 3769 return r; 3770 } 3771 3772 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 3773 struct kvm_x86_mce *mce) 3774 { 3775 u64 mcg_cap = vcpu->arch.mcg_cap; 3776 unsigned bank_num = mcg_cap & 0xff; 3777 u64 *banks = vcpu->arch.mce_banks; 3778 3779 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 3780 return -EINVAL; 3781 /* 3782 * if IA32_MCG_CTL is not all 1s, the uncorrected error 3783 * reporting is disabled 3784 */ 3785 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 3786 vcpu->arch.mcg_ctl != ~(u64)0) 3787 return 0; 3788 banks += 4 * mce->bank; 3789 /* 3790 * if IA32_MCi_CTL is not all 1s, the uncorrected error 3791 * reporting is disabled for the bank 3792 */ 3793 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 3794 return 0; 3795 if (mce->status & MCI_STATUS_UC) { 3796 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 3797 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 3798 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 3799 return 0; 3800 } 3801 if (banks[1] & MCI_STATUS_VAL) 3802 mce->status |= MCI_STATUS_OVER; 3803 banks[2] = mce->addr; 3804 banks[3] = mce->misc; 3805 vcpu->arch.mcg_status = mce->mcg_status; 3806 banks[1] = mce->status; 3807 kvm_queue_exception(vcpu, MC_VECTOR); 3808 } else if (!(banks[1] & MCI_STATUS_VAL) 3809 || !(banks[1] & MCI_STATUS_UC)) { 3810 if (banks[1] & MCI_STATUS_VAL) 3811 mce->status |= MCI_STATUS_OVER; 3812 banks[2] = mce->addr; 3813 banks[3] = mce->misc; 3814 banks[1] = mce->status; 3815 } else 3816 banks[1] |= MCI_STATUS_OVER; 3817 return 0; 3818 } 3819 3820 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 3821 struct kvm_vcpu_events *events) 3822 { 3823 process_nmi(vcpu); 3824 3825 /* 3826 * In guest mode, payload delivery should be deferred, 3827 * so that the L1 hypervisor can intercept #PF before 3828 * CR2 is modified (or intercept #DB before DR6 is 3829 * modified under nVMX). Unless the per-VM capability, 3830 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of 3831 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we 3832 * opportunistically defer the exception payload, deliver it if the 3833 * capability hasn't been requested before processing a 3834 * KVM_GET_VCPU_EVENTS. 3835 */ 3836 if (!vcpu->kvm->arch.exception_payload_enabled && 3837 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) 3838 kvm_deliver_exception_payload(vcpu); 3839 3840 /* 3841 * The API doesn't provide the instruction length for software 3842 * exceptions, so don't report them. As long as the guest RIP 3843 * isn't advanced, we should expect to encounter the exception 3844 * again. 3845 */ 3846 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 3847 events->exception.injected = 0; 3848 events->exception.pending = 0; 3849 } else { 3850 events->exception.injected = vcpu->arch.exception.injected; 3851 events->exception.pending = vcpu->arch.exception.pending; 3852 /* 3853 * For ABI compatibility, deliberately conflate 3854 * pending and injected exceptions when 3855 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 3856 */ 3857 if (!vcpu->kvm->arch.exception_payload_enabled) 3858 events->exception.injected |= 3859 vcpu->arch.exception.pending; 3860 } 3861 events->exception.nr = vcpu->arch.exception.nr; 3862 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 3863 events->exception.error_code = vcpu->arch.exception.error_code; 3864 events->exception_has_payload = vcpu->arch.exception.has_payload; 3865 events->exception_payload = vcpu->arch.exception.payload; 3866 3867 events->interrupt.injected = 3868 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 3869 events->interrupt.nr = vcpu->arch.interrupt.nr; 3870 events->interrupt.soft = 0; 3871 events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu); 3872 3873 events->nmi.injected = vcpu->arch.nmi_injected; 3874 events->nmi.pending = vcpu->arch.nmi_pending != 0; 3875 events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu); 3876 events->nmi.pad = 0; 3877 3878 events->sipi_vector = 0; /* never valid when reporting to user space */ 3879 3880 events->smi.smm = is_smm(vcpu); 3881 events->smi.pending = vcpu->arch.smi_pending; 3882 events->smi.smm_inside_nmi = 3883 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 3884 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 3885 3886 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 3887 | KVM_VCPUEVENT_VALID_SHADOW 3888 | KVM_VCPUEVENT_VALID_SMM); 3889 if (vcpu->kvm->arch.exception_payload_enabled) 3890 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 3891 3892 memset(&events->reserved, 0, sizeof(events->reserved)); 3893 } 3894 3895 static void kvm_smm_changed(struct kvm_vcpu *vcpu); 3896 3897 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 3898 struct kvm_vcpu_events *events) 3899 { 3900 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 3901 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 3902 | KVM_VCPUEVENT_VALID_SHADOW 3903 | KVM_VCPUEVENT_VALID_SMM 3904 | KVM_VCPUEVENT_VALID_PAYLOAD)) 3905 return -EINVAL; 3906 3907 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 3908 if (!vcpu->kvm->arch.exception_payload_enabled) 3909 return -EINVAL; 3910 if (events->exception.pending) 3911 events->exception.injected = 0; 3912 else 3913 events->exception_has_payload = 0; 3914 } else { 3915 events->exception.pending = 0; 3916 events->exception_has_payload = 0; 3917 } 3918 3919 if ((events->exception.injected || events->exception.pending) && 3920 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 3921 return -EINVAL; 3922 3923 /* INITs are latched while in SMM */ 3924 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 3925 (events->smi.smm || events->smi.pending) && 3926 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 3927 return -EINVAL; 3928 3929 process_nmi(vcpu); 3930 vcpu->arch.exception.injected = events->exception.injected; 3931 vcpu->arch.exception.pending = events->exception.pending; 3932 vcpu->arch.exception.nr = events->exception.nr; 3933 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 3934 vcpu->arch.exception.error_code = events->exception.error_code; 3935 vcpu->arch.exception.has_payload = events->exception_has_payload; 3936 vcpu->arch.exception.payload = events->exception_payload; 3937 3938 vcpu->arch.interrupt.injected = events->interrupt.injected; 3939 vcpu->arch.interrupt.nr = events->interrupt.nr; 3940 vcpu->arch.interrupt.soft = events->interrupt.soft; 3941 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3942 kvm_x86_ops.set_interrupt_shadow(vcpu, 3943 events->interrupt.shadow); 3944 3945 vcpu->arch.nmi_injected = events->nmi.injected; 3946 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3947 vcpu->arch.nmi_pending = events->nmi.pending; 3948 kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked); 3949 3950 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3951 lapic_in_kernel(vcpu)) 3952 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3953 3954 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 3955 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { 3956 if (events->smi.smm) 3957 vcpu->arch.hflags |= HF_SMM_MASK; 3958 else 3959 vcpu->arch.hflags &= ~HF_SMM_MASK; 3960 kvm_smm_changed(vcpu); 3961 } 3962 3963 vcpu->arch.smi_pending = events->smi.pending; 3964 3965 if (events->smi.smm) { 3966 if (events->smi.smm_inside_nmi) 3967 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 3968 else 3969 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 3970 } 3971 3972 if (lapic_in_kernel(vcpu)) { 3973 if (events->smi.latched_init) 3974 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3975 else 3976 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3977 } 3978 } 3979 3980 kvm_make_request(KVM_REQ_EVENT, vcpu); 3981 3982 return 0; 3983 } 3984 3985 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3986 struct kvm_debugregs *dbgregs) 3987 { 3988 unsigned long val; 3989 3990 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3991 kvm_get_dr(vcpu, 6, &val); 3992 dbgregs->dr6 = val; 3993 dbgregs->dr7 = vcpu->arch.dr7; 3994 dbgregs->flags = 0; 3995 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3996 } 3997 3998 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3999 struct kvm_debugregs *dbgregs) 4000 { 4001 if (dbgregs->flags) 4002 return -EINVAL; 4003 4004 if (dbgregs->dr6 & ~0xffffffffull) 4005 return -EINVAL; 4006 if (dbgregs->dr7 & ~0xffffffffull) 4007 return -EINVAL; 4008 4009 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 4010 kvm_update_dr0123(vcpu); 4011 vcpu->arch.dr6 = dbgregs->dr6; 4012 kvm_update_dr6(vcpu); 4013 vcpu->arch.dr7 = dbgregs->dr7; 4014 kvm_update_dr7(vcpu); 4015 4016 return 0; 4017 } 4018 4019 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 4020 4021 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 4022 { 4023 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 4024 u64 xstate_bv = xsave->header.xfeatures; 4025 u64 valid; 4026 4027 /* 4028 * Copy legacy XSAVE area, to avoid complications with CPUID 4029 * leaves 0 and 1 in the loop below. 4030 */ 4031 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 4032 4033 /* Set XSTATE_BV */ 4034 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; 4035 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 4036 4037 /* 4038 * Copy each region from the possibly compacted offset to the 4039 * non-compacted offset. 4040 */ 4041 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 4042 while (valid) { 4043 u64 xfeature_mask = valid & -valid; 4044 int xfeature_nr = fls64(xfeature_mask) - 1; 4045 void *src = get_xsave_addr(xsave, xfeature_nr); 4046 4047 if (src) { 4048 u32 size, offset, ecx, edx; 4049 cpuid_count(XSTATE_CPUID, xfeature_nr, 4050 &size, &offset, &ecx, &edx); 4051 if (xfeature_nr == XFEATURE_PKRU) 4052 memcpy(dest + offset, &vcpu->arch.pkru, 4053 sizeof(vcpu->arch.pkru)); 4054 else 4055 memcpy(dest + offset, src, size); 4056 4057 } 4058 4059 valid -= xfeature_mask; 4060 } 4061 } 4062 4063 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 4064 { 4065 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 4066 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 4067 u64 valid; 4068 4069 /* 4070 * Copy legacy XSAVE area, to avoid complications with CPUID 4071 * leaves 0 and 1 in the loop below. 4072 */ 4073 memcpy(xsave, src, XSAVE_HDR_OFFSET); 4074 4075 /* Set XSTATE_BV and possibly XCOMP_BV. */ 4076 xsave->header.xfeatures = xstate_bv; 4077 if (boot_cpu_has(X86_FEATURE_XSAVES)) 4078 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 4079 4080 /* 4081 * Copy each region from the non-compacted offset to the 4082 * possibly compacted offset. 4083 */ 4084 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 4085 while (valid) { 4086 u64 xfeature_mask = valid & -valid; 4087 int xfeature_nr = fls64(xfeature_mask) - 1; 4088 void *dest = get_xsave_addr(xsave, xfeature_nr); 4089 4090 if (dest) { 4091 u32 size, offset, ecx, edx; 4092 cpuid_count(XSTATE_CPUID, xfeature_nr, 4093 &size, &offset, &ecx, &edx); 4094 if (xfeature_nr == XFEATURE_PKRU) 4095 memcpy(&vcpu->arch.pkru, src + offset, 4096 sizeof(vcpu->arch.pkru)); 4097 else 4098 memcpy(dest, src + offset, size); 4099 } 4100 4101 valid -= xfeature_mask; 4102 } 4103 } 4104 4105 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 4106 struct kvm_xsave *guest_xsave) 4107 { 4108 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 4109 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 4110 fill_xsave((u8 *) guest_xsave->region, vcpu); 4111 } else { 4112 memcpy(guest_xsave->region, 4113 &vcpu->arch.guest_fpu->state.fxsave, 4114 sizeof(struct fxregs_state)); 4115 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 4116 XFEATURE_MASK_FPSSE; 4117 } 4118 } 4119 4120 #define XSAVE_MXCSR_OFFSET 24 4121 4122 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 4123 struct kvm_xsave *guest_xsave) 4124 { 4125 u64 xstate_bv = 4126 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 4127 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; 4128 4129 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 4130 /* 4131 * Here we allow setting states that are not present in 4132 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 4133 * with old userspace. 4134 */ 4135 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask) 4136 return -EINVAL; 4137 load_xsave(vcpu, (u8 *)guest_xsave->region); 4138 } else { 4139 if (xstate_bv & ~XFEATURE_MASK_FPSSE || 4140 mxcsr & ~mxcsr_feature_mask) 4141 return -EINVAL; 4142 memcpy(&vcpu->arch.guest_fpu->state.fxsave, 4143 guest_xsave->region, sizeof(struct fxregs_state)); 4144 } 4145 return 0; 4146 } 4147 4148 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 4149 struct kvm_xcrs *guest_xcrs) 4150 { 4151 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 4152 guest_xcrs->nr_xcrs = 0; 4153 return; 4154 } 4155 4156 guest_xcrs->nr_xcrs = 1; 4157 guest_xcrs->flags = 0; 4158 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 4159 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 4160 } 4161 4162 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 4163 struct kvm_xcrs *guest_xcrs) 4164 { 4165 int i, r = 0; 4166 4167 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 4168 return -EINVAL; 4169 4170 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 4171 return -EINVAL; 4172 4173 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 4174 /* Only support XCR0 currently */ 4175 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 4176 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 4177 guest_xcrs->xcrs[i].value); 4178 break; 4179 } 4180 if (r) 4181 r = -EINVAL; 4182 return r; 4183 } 4184 4185 /* 4186 * kvm_set_guest_paused() indicates to the guest kernel that it has been 4187 * stopped by the hypervisor. This function will be called from the host only. 4188 * EINVAL is returned when the host attempts to set the flag for a guest that 4189 * does not support pv clocks. 4190 */ 4191 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 4192 { 4193 if (!vcpu->arch.pv_time_enabled) 4194 return -EINVAL; 4195 vcpu->arch.pvclock_set_guest_stopped_request = true; 4196 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4197 return 0; 4198 } 4199 4200 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 4201 struct kvm_enable_cap *cap) 4202 { 4203 int r; 4204 uint16_t vmcs_version; 4205 void __user *user_ptr; 4206 4207 if (cap->flags) 4208 return -EINVAL; 4209 4210 switch (cap->cap) { 4211 case KVM_CAP_HYPERV_SYNIC2: 4212 if (cap->args[0]) 4213 return -EINVAL; 4214 /* fall through */ 4215 4216 case KVM_CAP_HYPERV_SYNIC: 4217 if (!irqchip_in_kernel(vcpu->kvm)) 4218 return -EINVAL; 4219 return kvm_hv_activate_synic(vcpu, cap->cap == 4220 KVM_CAP_HYPERV_SYNIC2); 4221 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4222 if (!kvm_x86_ops.nested_enable_evmcs) 4223 return -ENOTTY; 4224 r = kvm_x86_ops.nested_enable_evmcs(vcpu, &vmcs_version); 4225 if (!r) { 4226 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 4227 if (copy_to_user(user_ptr, &vmcs_version, 4228 sizeof(vmcs_version))) 4229 r = -EFAULT; 4230 } 4231 return r; 4232 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4233 if (!kvm_x86_ops.enable_direct_tlbflush) 4234 return -ENOTTY; 4235 4236 return kvm_x86_ops.enable_direct_tlbflush(vcpu); 4237 4238 default: 4239 return -EINVAL; 4240 } 4241 } 4242 4243 long kvm_arch_vcpu_ioctl(struct file *filp, 4244 unsigned int ioctl, unsigned long arg) 4245 { 4246 struct kvm_vcpu *vcpu = filp->private_data; 4247 void __user *argp = (void __user *)arg; 4248 int r; 4249 union { 4250 struct kvm_lapic_state *lapic; 4251 struct kvm_xsave *xsave; 4252 struct kvm_xcrs *xcrs; 4253 void *buffer; 4254 } u; 4255 4256 vcpu_load(vcpu); 4257 4258 u.buffer = NULL; 4259 switch (ioctl) { 4260 case KVM_GET_LAPIC: { 4261 r = -EINVAL; 4262 if (!lapic_in_kernel(vcpu)) 4263 goto out; 4264 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 4265 GFP_KERNEL_ACCOUNT); 4266 4267 r = -ENOMEM; 4268 if (!u.lapic) 4269 goto out; 4270 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 4271 if (r) 4272 goto out; 4273 r = -EFAULT; 4274 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 4275 goto out; 4276 r = 0; 4277 break; 4278 } 4279 case KVM_SET_LAPIC: { 4280 r = -EINVAL; 4281 if (!lapic_in_kernel(vcpu)) 4282 goto out; 4283 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 4284 if (IS_ERR(u.lapic)) { 4285 r = PTR_ERR(u.lapic); 4286 goto out_nofree; 4287 } 4288 4289 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 4290 break; 4291 } 4292 case KVM_INTERRUPT: { 4293 struct kvm_interrupt irq; 4294 4295 r = -EFAULT; 4296 if (copy_from_user(&irq, argp, sizeof(irq))) 4297 goto out; 4298 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 4299 break; 4300 } 4301 case KVM_NMI: { 4302 r = kvm_vcpu_ioctl_nmi(vcpu); 4303 break; 4304 } 4305 case KVM_SMI: { 4306 r = kvm_vcpu_ioctl_smi(vcpu); 4307 break; 4308 } 4309 case KVM_SET_CPUID: { 4310 struct kvm_cpuid __user *cpuid_arg = argp; 4311 struct kvm_cpuid cpuid; 4312 4313 r = -EFAULT; 4314 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4315 goto out; 4316 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 4317 break; 4318 } 4319 case KVM_SET_CPUID2: { 4320 struct kvm_cpuid2 __user *cpuid_arg = argp; 4321 struct kvm_cpuid2 cpuid; 4322 4323 r = -EFAULT; 4324 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4325 goto out; 4326 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 4327 cpuid_arg->entries); 4328 break; 4329 } 4330 case KVM_GET_CPUID2: { 4331 struct kvm_cpuid2 __user *cpuid_arg = argp; 4332 struct kvm_cpuid2 cpuid; 4333 4334 r = -EFAULT; 4335 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4336 goto out; 4337 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 4338 cpuid_arg->entries); 4339 if (r) 4340 goto out; 4341 r = -EFAULT; 4342 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4343 goto out; 4344 r = 0; 4345 break; 4346 } 4347 case KVM_GET_MSRS: { 4348 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4349 r = msr_io(vcpu, argp, do_get_msr, 1); 4350 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4351 break; 4352 } 4353 case KVM_SET_MSRS: { 4354 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4355 r = msr_io(vcpu, argp, do_set_msr, 0); 4356 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4357 break; 4358 } 4359 case KVM_TPR_ACCESS_REPORTING: { 4360 struct kvm_tpr_access_ctl tac; 4361 4362 r = -EFAULT; 4363 if (copy_from_user(&tac, argp, sizeof(tac))) 4364 goto out; 4365 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 4366 if (r) 4367 goto out; 4368 r = -EFAULT; 4369 if (copy_to_user(argp, &tac, sizeof(tac))) 4370 goto out; 4371 r = 0; 4372 break; 4373 }; 4374 case KVM_SET_VAPIC_ADDR: { 4375 struct kvm_vapic_addr va; 4376 int idx; 4377 4378 r = -EINVAL; 4379 if (!lapic_in_kernel(vcpu)) 4380 goto out; 4381 r = -EFAULT; 4382 if (copy_from_user(&va, argp, sizeof(va))) 4383 goto out; 4384 idx = srcu_read_lock(&vcpu->kvm->srcu); 4385 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 4386 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4387 break; 4388 } 4389 case KVM_X86_SETUP_MCE: { 4390 u64 mcg_cap; 4391 4392 r = -EFAULT; 4393 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 4394 goto out; 4395 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 4396 break; 4397 } 4398 case KVM_X86_SET_MCE: { 4399 struct kvm_x86_mce mce; 4400 4401 r = -EFAULT; 4402 if (copy_from_user(&mce, argp, sizeof(mce))) 4403 goto out; 4404 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 4405 break; 4406 } 4407 case KVM_GET_VCPU_EVENTS: { 4408 struct kvm_vcpu_events events; 4409 4410 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 4411 4412 r = -EFAULT; 4413 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 4414 break; 4415 r = 0; 4416 break; 4417 } 4418 case KVM_SET_VCPU_EVENTS: { 4419 struct kvm_vcpu_events events; 4420 4421 r = -EFAULT; 4422 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 4423 break; 4424 4425 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 4426 break; 4427 } 4428 case KVM_GET_DEBUGREGS: { 4429 struct kvm_debugregs dbgregs; 4430 4431 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 4432 4433 r = -EFAULT; 4434 if (copy_to_user(argp, &dbgregs, 4435 sizeof(struct kvm_debugregs))) 4436 break; 4437 r = 0; 4438 break; 4439 } 4440 case KVM_SET_DEBUGREGS: { 4441 struct kvm_debugregs dbgregs; 4442 4443 r = -EFAULT; 4444 if (copy_from_user(&dbgregs, argp, 4445 sizeof(struct kvm_debugregs))) 4446 break; 4447 4448 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 4449 break; 4450 } 4451 case KVM_GET_XSAVE: { 4452 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 4453 r = -ENOMEM; 4454 if (!u.xsave) 4455 break; 4456 4457 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 4458 4459 r = -EFAULT; 4460 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 4461 break; 4462 r = 0; 4463 break; 4464 } 4465 case KVM_SET_XSAVE: { 4466 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 4467 if (IS_ERR(u.xsave)) { 4468 r = PTR_ERR(u.xsave); 4469 goto out_nofree; 4470 } 4471 4472 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 4473 break; 4474 } 4475 case KVM_GET_XCRS: { 4476 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 4477 r = -ENOMEM; 4478 if (!u.xcrs) 4479 break; 4480 4481 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 4482 4483 r = -EFAULT; 4484 if (copy_to_user(argp, u.xcrs, 4485 sizeof(struct kvm_xcrs))) 4486 break; 4487 r = 0; 4488 break; 4489 } 4490 case KVM_SET_XCRS: { 4491 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 4492 if (IS_ERR(u.xcrs)) { 4493 r = PTR_ERR(u.xcrs); 4494 goto out_nofree; 4495 } 4496 4497 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 4498 break; 4499 } 4500 case KVM_SET_TSC_KHZ: { 4501 u32 user_tsc_khz; 4502 4503 r = -EINVAL; 4504 user_tsc_khz = (u32)arg; 4505 4506 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 4507 goto out; 4508 4509 if (user_tsc_khz == 0) 4510 user_tsc_khz = tsc_khz; 4511 4512 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 4513 r = 0; 4514 4515 goto out; 4516 } 4517 case KVM_GET_TSC_KHZ: { 4518 r = vcpu->arch.virtual_tsc_khz; 4519 goto out; 4520 } 4521 case KVM_KVMCLOCK_CTRL: { 4522 r = kvm_set_guest_paused(vcpu); 4523 goto out; 4524 } 4525 case KVM_ENABLE_CAP: { 4526 struct kvm_enable_cap cap; 4527 4528 r = -EFAULT; 4529 if (copy_from_user(&cap, argp, sizeof(cap))) 4530 goto out; 4531 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 4532 break; 4533 } 4534 case KVM_GET_NESTED_STATE: { 4535 struct kvm_nested_state __user *user_kvm_nested_state = argp; 4536 u32 user_data_size; 4537 4538 r = -EINVAL; 4539 if (!kvm_x86_ops.get_nested_state) 4540 break; 4541 4542 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 4543 r = -EFAULT; 4544 if (get_user(user_data_size, &user_kvm_nested_state->size)) 4545 break; 4546 4547 r = kvm_x86_ops.get_nested_state(vcpu, user_kvm_nested_state, 4548 user_data_size); 4549 if (r < 0) 4550 break; 4551 4552 if (r > user_data_size) { 4553 if (put_user(r, &user_kvm_nested_state->size)) 4554 r = -EFAULT; 4555 else 4556 r = -E2BIG; 4557 break; 4558 } 4559 4560 r = 0; 4561 break; 4562 } 4563 case KVM_SET_NESTED_STATE: { 4564 struct kvm_nested_state __user *user_kvm_nested_state = argp; 4565 struct kvm_nested_state kvm_state; 4566 int idx; 4567 4568 r = -EINVAL; 4569 if (!kvm_x86_ops.set_nested_state) 4570 break; 4571 4572 r = -EFAULT; 4573 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 4574 break; 4575 4576 r = -EINVAL; 4577 if (kvm_state.size < sizeof(kvm_state)) 4578 break; 4579 4580 if (kvm_state.flags & 4581 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 4582 | KVM_STATE_NESTED_EVMCS)) 4583 break; 4584 4585 /* nested_run_pending implies guest_mode. */ 4586 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 4587 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 4588 break; 4589 4590 idx = srcu_read_lock(&vcpu->kvm->srcu); 4591 r = kvm_x86_ops.set_nested_state(vcpu, user_kvm_nested_state, &kvm_state); 4592 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4593 break; 4594 } 4595 case KVM_GET_SUPPORTED_HV_CPUID: { 4596 struct kvm_cpuid2 __user *cpuid_arg = argp; 4597 struct kvm_cpuid2 cpuid; 4598 4599 r = -EFAULT; 4600 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4601 goto out; 4602 4603 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid, 4604 cpuid_arg->entries); 4605 if (r) 4606 goto out; 4607 4608 r = -EFAULT; 4609 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4610 goto out; 4611 r = 0; 4612 break; 4613 } 4614 default: 4615 r = -EINVAL; 4616 } 4617 out: 4618 kfree(u.buffer); 4619 out_nofree: 4620 vcpu_put(vcpu); 4621 return r; 4622 } 4623 4624 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 4625 { 4626 return VM_FAULT_SIGBUS; 4627 } 4628 4629 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 4630 { 4631 int ret; 4632 4633 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 4634 return -EINVAL; 4635 ret = kvm_x86_ops.set_tss_addr(kvm, addr); 4636 return ret; 4637 } 4638 4639 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 4640 u64 ident_addr) 4641 { 4642 return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr); 4643 } 4644 4645 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 4646 unsigned long kvm_nr_mmu_pages) 4647 { 4648 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 4649 return -EINVAL; 4650 4651 mutex_lock(&kvm->slots_lock); 4652 4653 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 4654 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 4655 4656 mutex_unlock(&kvm->slots_lock); 4657 return 0; 4658 } 4659 4660 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 4661 { 4662 return kvm->arch.n_max_mmu_pages; 4663 } 4664 4665 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 4666 { 4667 struct kvm_pic *pic = kvm->arch.vpic; 4668 int r; 4669 4670 r = 0; 4671 switch (chip->chip_id) { 4672 case KVM_IRQCHIP_PIC_MASTER: 4673 memcpy(&chip->chip.pic, &pic->pics[0], 4674 sizeof(struct kvm_pic_state)); 4675 break; 4676 case KVM_IRQCHIP_PIC_SLAVE: 4677 memcpy(&chip->chip.pic, &pic->pics[1], 4678 sizeof(struct kvm_pic_state)); 4679 break; 4680 case KVM_IRQCHIP_IOAPIC: 4681 kvm_get_ioapic(kvm, &chip->chip.ioapic); 4682 break; 4683 default: 4684 r = -EINVAL; 4685 break; 4686 } 4687 return r; 4688 } 4689 4690 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 4691 { 4692 struct kvm_pic *pic = kvm->arch.vpic; 4693 int r; 4694 4695 r = 0; 4696 switch (chip->chip_id) { 4697 case KVM_IRQCHIP_PIC_MASTER: 4698 spin_lock(&pic->lock); 4699 memcpy(&pic->pics[0], &chip->chip.pic, 4700 sizeof(struct kvm_pic_state)); 4701 spin_unlock(&pic->lock); 4702 break; 4703 case KVM_IRQCHIP_PIC_SLAVE: 4704 spin_lock(&pic->lock); 4705 memcpy(&pic->pics[1], &chip->chip.pic, 4706 sizeof(struct kvm_pic_state)); 4707 spin_unlock(&pic->lock); 4708 break; 4709 case KVM_IRQCHIP_IOAPIC: 4710 kvm_set_ioapic(kvm, &chip->chip.ioapic); 4711 break; 4712 default: 4713 r = -EINVAL; 4714 break; 4715 } 4716 kvm_pic_update_irq(pic); 4717 return r; 4718 } 4719 4720 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 4721 { 4722 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 4723 4724 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 4725 4726 mutex_lock(&kps->lock); 4727 memcpy(ps, &kps->channels, sizeof(*ps)); 4728 mutex_unlock(&kps->lock); 4729 return 0; 4730 } 4731 4732 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 4733 { 4734 int i; 4735 struct kvm_pit *pit = kvm->arch.vpit; 4736 4737 mutex_lock(&pit->pit_state.lock); 4738 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 4739 for (i = 0; i < 3; i++) 4740 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 4741 mutex_unlock(&pit->pit_state.lock); 4742 return 0; 4743 } 4744 4745 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 4746 { 4747 mutex_lock(&kvm->arch.vpit->pit_state.lock); 4748 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 4749 sizeof(ps->channels)); 4750 ps->flags = kvm->arch.vpit->pit_state.flags; 4751 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 4752 memset(&ps->reserved, 0, sizeof(ps->reserved)); 4753 return 0; 4754 } 4755 4756 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 4757 { 4758 int start = 0; 4759 int i; 4760 u32 prev_legacy, cur_legacy; 4761 struct kvm_pit *pit = kvm->arch.vpit; 4762 4763 mutex_lock(&pit->pit_state.lock); 4764 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 4765 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 4766 if (!prev_legacy && cur_legacy) 4767 start = 1; 4768 memcpy(&pit->pit_state.channels, &ps->channels, 4769 sizeof(pit->pit_state.channels)); 4770 pit->pit_state.flags = ps->flags; 4771 for (i = 0; i < 3; i++) 4772 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 4773 start && i == 0); 4774 mutex_unlock(&pit->pit_state.lock); 4775 return 0; 4776 } 4777 4778 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 4779 struct kvm_reinject_control *control) 4780 { 4781 struct kvm_pit *pit = kvm->arch.vpit; 4782 4783 /* pit->pit_state.lock was overloaded to prevent userspace from getting 4784 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 4785 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 4786 */ 4787 mutex_lock(&pit->pit_state.lock); 4788 kvm_pit_set_reinject(pit, control->pit_reinject); 4789 mutex_unlock(&pit->pit_state.lock); 4790 4791 return 0; 4792 } 4793 4794 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 4795 { 4796 /* 4797 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 4798 */ 4799 if (kvm_x86_ops.flush_log_dirty) 4800 kvm_x86_ops.flush_log_dirty(kvm); 4801 } 4802 4803 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 4804 bool line_status) 4805 { 4806 if (!irqchip_in_kernel(kvm)) 4807 return -ENXIO; 4808 4809 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 4810 irq_event->irq, irq_event->level, 4811 line_status); 4812 return 0; 4813 } 4814 4815 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 4816 struct kvm_enable_cap *cap) 4817 { 4818 int r; 4819 4820 if (cap->flags) 4821 return -EINVAL; 4822 4823 switch (cap->cap) { 4824 case KVM_CAP_DISABLE_QUIRKS: 4825 kvm->arch.disabled_quirks = cap->args[0]; 4826 r = 0; 4827 break; 4828 case KVM_CAP_SPLIT_IRQCHIP: { 4829 mutex_lock(&kvm->lock); 4830 r = -EINVAL; 4831 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 4832 goto split_irqchip_unlock; 4833 r = -EEXIST; 4834 if (irqchip_in_kernel(kvm)) 4835 goto split_irqchip_unlock; 4836 if (kvm->created_vcpus) 4837 goto split_irqchip_unlock; 4838 r = kvm_setup_empty_irq_routing(kvm); 4839 if (r) 4840 goto split_irqchip_unlock; 4841 /* Pairs with irqchip_in_kernel. */ 4842 smp_wmb(); 4843 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 4844 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 4845 r = 0; 4846 split_irqchip_unlock: 4847 mutex_unlock(&kvm->lock); 4848 break; 4849 } 4850 case KVM_CAP_X2APIC_API: 4851 r = -EINVAL; 4852 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 4853 break; 4854 4855 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 4856 kvm->arch.x2apic_format = true; 4857 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 4858 kvm->arch.x2apic_broadcast_quirk_disabled = true; 4859 4860 r = 0; 4861 break; 4862 case KVM_CAP_X86_DISABLE_EXITS: 4863 r = -EINVAL; 4864 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 4865 break; 4866 4867 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 4868 kvm_can_mwait_in_guest()) 4869 kvm->arch.mwait_in_guest = true; 4870 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 4871 kvm->arch.hlt_in_guest = true; 4872 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 4873 kvm->arch.pause_in_guest = true; 4874 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) 4875 kvm->arch.cstate_in_guest = true; 4876 r = 0; 4877 break; 4878 case KVM_CAP_MSR_PLATFORM_INFO: 4879 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 4880 r = 0; 4881 break; 4882 case KVM_CAP_EXCEPTION_PAYLOAD: 4883 kvm->arch.exception_payload_enabled = cap->args[0]; 4884 r = 0; 4885 break; 4886 default: 4887 r = -EINVAL; 4888 break; 4889 } 4890 return r; 4891 } 4892 4893 long kvm_arch_vm_ioctl(struct file *filp, 4894 unsigned int ioctl, unsigned long arg) 4895 { 4896 struct kvm *kvm = filp->private_data; 4897 void __user *argp = (void __user *)arg; 4898 int r = -ENOTTY; 4899 /* 4900 * This union makes it completely explicit to gcc-3.x 4901 * that these two variables' stack usage should be 4902 * combined, not added together. 4903 */ 4904 union { 4905 struct kvm_pit_state ps; 4906 struct kvm_pit_state2 ps2; 4907 struct kvm_pit_config pit_config; 4908 } u; 4909 4910 switch (ioctl) { 4911 case KVM_SET_TSS_ADDR: 4912 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 4913 break; 4914 case KVM_SET_IDENTITY_MAP_ADDR: { 4915 u64 ident_addr; 4916 4917 mutex_lock(&kvm->lock); 4918 r = -EINVAL; 4919 if (kvm->created_vcpus) 4920 goto set_identity_unlock; 4921 r = -EFAULT; 4922 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 4923 goto set_identity_unlock; 4924 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 4925 set_identity_unlock: 4926 mutex_unlock(&kvm->lock); 4927 break; 4928 } 4929 case KVM_SET_NR_MMU_PAGES: 4930 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 4931 break; 4932 case KVM_GET_NR_MMU_PAGES: 4933 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 4934 break; 4935 case KVM_CREATE_IRQCHIP: { 4936 mutex_lock(&kvm->lock); 4937 4938 r = -EEXIST; 4939 if (irqchip_in_kernel(kvm)) 4940 goto create_irqchip_unlock; 4941 4942 r = -EINVAL; 4943 if (kvm->created_vcpus) 4944 goto create_irqchip_unlock; 4945 4946 r = kvm_pic_init(kvm); 4947 if (r) 4948 goto create_irqchip_unlock; 4949 4950 r = kvm_ioapic_init(kvm); 4951 if (r) { 4952 kvm_pic_destroy(kvm); 4953 goto create_irqchip_unlock; 4954 } 4955 4956 r = kvm_setup_default_irq_routing(kvm); 4957 if (r) { 4958 kvm_ioapic_destroy(kvm); 4959 kvm_pic_destroy(kvm); 4960 goto create_irqchip_unlock; 4961 } 4962 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 4963 smp_wmb(); 4964 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 4965 create_irqchip_unlock: 4966 mutex_unlock(&kvm->lock); 4967 break; 4968 } 4969 case KVM_CREATE_PIT: 4970 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 4971 goto create_pit; 4972 case KVM_CREATE_PIT2: 4973 r = -EFAULT; 4974 if (copy_from_user(&u.pit_config, argp, 4975 sizeof(struct kvm_pit_config))) 4976 goto out; 4977 create_pit: 4978 mutex_lock(&kvm->lock); 4979 r = -EEXIST; 4980 if (kvm->arch.vpit) 4981 goto create_pit_unlock; 4982 r = -ENOMEM; 4983 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 4984 if (kvm->arch.vpit) 4985 r = 0; 4986 create_pit_unlock: 4987 mutex_unlock(&kvm->lock); 4988 break; 4989 case KVM_GET_IRQCHIP: { 4990 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4991 struct kvm_irqchip *chip; 4992 4993 chip = memdup_user(argp, sizeof(*chip)); 4994 if (IS_ERR(chip)) { 4995 r = PTR_ERR(chip); 4996 goto out; 4997 } 4998 4999 r = -ENXIO; 5000 if (!irqchip_kernel(kvm)) 5001 goto get_irqchip_out; 5002 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 5003 if (r) 5004 goto get_irqchip_out; 5005 r = -EFAULT; 5006 if (copy_to_user(argp, chip, sizeof(*chip))) 5007 goto get_irqchip_out; 5008 r = 0; 5009 get_irqchip_out: 5010 kfree(chip); 5011 break; 5012 } 5013 case KVM_SET_IRQCHIP: { 5014 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 5015 struct kvm_irqchip *chip; 5016 5017 chip = memdup_user(argp, sizeof(*chip)); 5018 if (IS_ERR(chip)) { 5019 r = PTR_ERR(chip); 5020 goto out; 5021 } 5022 5023 r = -ENXIO; 5024 if (!irqchip_kernel(kvm)) 5025 goto set_irqchip_out; 5026 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 5027 set_irqchip_out: 5028 kfree(chip); 5029 break; 5030 } 5031 case KVM_GET_PIT: { 5032 r = -EFAULT; 5033 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 5034 goto out; 5035 r = -ENXIO; 5036 if (!kvm->arch.vpit) 5037 goto out; 5038 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 5039 if (r) 5040 goto out; 5041 r = -EFAULT; 5042 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 5043 goto out; 5044 r = 0; 5045 break; 5046 } 5047 case KVM_SET_PIT: { 5048 r = -EFAULT; 5049 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 5050 goto out; 5051 r = -ENXIO; 5052 if (!kvm->arch.vpit) 5053 goto out; 5054 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 5055 break; 5056 } 5057 case KVM_GET_PIT2: { 5058 r = -ENXIO; 5059 if (!kvm->arch.vpit) 5060 goto out; 5061 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 5062 if (r) 5063 goto out; 5064 r = -EFAULT; 5065 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 5066 goto out; 5067 r = 0; 5068 break; 5069 } 5070 case KVM_SET_PIT2: { 5071 r = -EFAULT; 5072 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 5073 goto out; 5074 r = -ENXIO; 5075 if (!kvm->arch.vpit) 5076 goto out; 5077 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 5078 break; 5079 } 5080 case KVM_REINJECT_CONTROL: { 5081 struct kvm_reinject_control control; 5082 r = -EFAULT; 5083 if (copy_from_user(&control, argp, sizeof(control))) 5084 goto out; 5085 r = -ENXIO; 5086 if (!kvm->arch.vpit) 5087 goto out; 5088 r = kvm_vm_ioctl_reinject(kvm, &control); 5089 break; 5090 } 5091 case KVM_SET_BOOT_CPU_ID: 5092 r = 0; 5093 mutex_lock(&kvm->lock); 5094 if (kvm->created_vcpus) 5095 r = -EBUSY; 5096 else 5097 kvm->arch.bsp_vcpu_id = arg; 5098 mutex_unlock(&kvm->lock); 5099 break; 5100 case KVM_XEN_HVM_CONFIG: { 5101 struct kvm_xen_hvm_config xhc; 5102 r = -EFAULT; 5103 if (copy_from_user(&xhc, argp, sizeof(xhc))) 5104 goto out; 5105 r = -EINVAL; 5106 if (xhc.flags) 5107 goto out; 5108 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); 5109 r = 0; 5110 break; 5111 } 5112 case KVM_SET_CLOCK: { 5113 struct kvm_clock_data user_ns; 5114 u64 now_ns; 5115 5116 r = -EFAULT; 5117 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 5118 goto out; 5119 5120 r = -EINVAL; 5121 if (user_ns.flags) 5122 goto out; 5123 5124 r = 0; 5125 /* 5126 * TODO: userspace has to take care of races with VCPU_RUN, so 5127 * kvm_gen_update_masterclock() can be cut down to locked 5128 * pvclock_update_vm_gtod_copy(). 5129 */ 5130 kvm_gen_update_masterclock(kvm); 5131 now_ns = get_kvmclock_ns(kvm); 5132 kvm->arch.kvmclock_offset += user_ns.clock - now_ns; 5133 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); 5134 break; 5135 } 5136 case KVM_GET_CLOCK: { 5137 struct kvm_clock_data user_ns; 5138 u64 now_ns; 5139 5140 now_ns = get_kvmclock_ns(kvm); 5141 user_ns.clock = now_ns; 5142 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 5143 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 5144 5145 r = -EFAULT; 5146 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 5147 goto out; 5148 r = 0; 5149 break; 5150 } 5151 case KVM_MEMORY_ENCRYPT_OP: { 5152 r = -ENOTTY; 5153 if (kvm_x86_ops.mem_enc_op) 5154 r = kvm_x86_ops.mem_enc_op(kvm, argp); 5155 break; 5156 } 5157 case KVM_MEMORY_ENCRYPT_REG_REGION: { 5158 struct kvm_enc_region region; 5159 5160 r = -EFAULT; 5161 if (copy_from_user(®ion, argp, sizeof(region))) 5162 goto out; 5163 5164 r = -ENOTTY; 5165 if (kvm_x86_ops.mem_enc_reg_region) 5166 r = kvm_x86_ops.mem_enc_reg_region(kvm, ®ion); 5167 break; 5168 } 5169 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 5170 struct kvm_enc_region region; 5171 5172 r = -EFAULT; 5173 if (copy_from_user(®ion, argp, sizeof(region))) 5174 goto out; 5175 5176 r = -ENOTTY; 5177 if (kvm_x86_ops.mem_enc_unreg_region) 5178 r = kvm_x86_ops.mem_enc_unreg_region(kvm, ®ion); 5179 break; 5180 } 5181 case KVM_HYPERV_EVENTFD: { 5182 struct kvm_hyperv_eventfd hvevfd; 5183 5184 r = -EFAULT; 5185 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 5186 goto out; 5187 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 5188 break; 5189 } 5190 case KVM_SET_PMU_EVENT_FILTER: 5191 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); 5192 break; 5193 default: 5194 r = -ENOTTY; 5195 } 5196 out: 5197 return r; 5198 } 5199 5200 static void kvm_init_msr_list(void) 5201 { 5202 struct x86_pmu_capability x86_pmu; 5203 u32 dummy[2]; 5204 unsigned i; 5205 5206 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, 5207 "Please update the fixed PMCs in msrs_to_saved_all[]"); 5208 5209 perf_get_x86_pmu_capability(&x86_pmu); 5210 5211 num_msrs_to_save = 0; 5212 num_emulated_msrs = 0; 5213 num_msr_based_features = 0; 5214 5215 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { 5216 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) 5217 continue; 5218 5219 /* 5220 * Even MSRs that are valid in the host may not be exposed 5221 * to the guests in some cases. 5222 */ 5223 switch (msrs_to_save_all[i]) { 5224 case MSR_IA32_BNDCFGS: 5225 if (!kvm_mpx_supported()) 5226 continue; 5227 break; 5228 case MSR_TSC_AUX: 5229 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) 5230 continue; 5231 break; 5232 case MSR_IA32_RTIT_CTL: 5233 case MSR_IA32_RTIT_STATUS: 5234 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) 5235 continue; 5236 break; 5237 case MSR_IA32_RTIT_CR3_MATCH: 5238 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 5239 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 5240 continue; 5241 break; 5242 case MSR_IA32_RTIT_OUTPUT_BASE: 5243 case MSR_IA32_RTIT_OUTPUT_MASK: 5244 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 5245 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 5246 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 5247 continue; 5248 break; 5249 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: { 5250 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 5251 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= 5252 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 5253 continue; 5254 break; 5255 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: 5256 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= 5257 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 5258 continue; 5259 break; 5260 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: 5261 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= 5262 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 5263 continue; 5264 } 5265 default: 5266 break; 5267 } 5268 5269 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; 5270 } 5271 5272 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { 5273 if (!kvm_x86_ops.has_emulated_msr(emulated_msrs_all[i])) 5274 continue; 5275 5276 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; 5277 } 5278 5279 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { 5280 struct kvm_msr_entry msr; 5281 5282 msr.index = msr_based_features_all[i]; 5283 if (kvm_get_msr_feature(&msr)) 5284 continue; 5285 5286 msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; 5287 } 5288 } 5289 5290 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 5291 const void *v) 5292 { 5293 int handled = 0; 5294 int n; 5295 5296 do { 5297 n = min(len, 8); 5298 if (!(lapic_in_kernel(vcpu) && 5299 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 5300 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 5301 break; 5302 handled += n; 5303 addr += n; 5304 len -= n; 5305 v += n; 5306 } while (len); 5307 5308 return handled; 5309 } 5310 5311 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 5312 { 5313 int handled = 0; 5314 int n; 5315 5316 do { 5317 n = min(len, 8); 5318 if (!(lapic_in_kernel(vcpu) && 5319 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 5320 addr, n, v)) 5321 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 5322 break; 5323 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 5324 handled += n; 5325 addr += n; 5326 len -= n; 5327 v += n; 5328 } while (len); 5329 5330 return handled; 5331 } 5332 5333 static void kvm_set_segment(struct kvm_vcpu *vcpu, 5334 struct kvm_segment *var, int seg) 5335 { 5336 kvm_x86_ops.set_segment(vcpu, var, seg); 5337 } 5338 5339 void kvm_get_segment(struct kvm_vcpu *vcpu, 5340 struct kvm_segment *var, int seg) 5341 { 5342 kvm_x86_ops.get_segment(vcpu, var, seg); 5343 } 5344 5345 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 5346 struct x86_exception *exception) 5347 { 5348 gpa_t t_gpa; 5349 5350 BUG_ON(!mmu_is_nested(vcpu)); 5351 5352 /* NPT walks are always user-walks */ 5353 access |= PFERR_USER_MASK; 5354 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); 5355 5356 return t_gpa; 5357 } 5358 5359 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 5360 struct x86_exception *exception) 5361 { 5362 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5363 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5364 } 5365 5366 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 5367 struct x86_exception *exception) 5368 { 5369 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5370 access |= PFERR_FETCH_MASK; 5371 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5372 } 5373 5374 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 5375 struct x86_exception *exception) 5376 { 5377 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5378 access |= PFERR_WRITE_MASK; 5379 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5380 } 5381 5382 /* uses this to access any guest's mapped memory without checking CPL */ 5383 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 5384 struct x86_exception *exception) 5385 { 5386 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 5387 } 5388 5389 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 5390 struct kvm_vcpu *vcpu, u32 access, 5391 struct x86_exception *exception) 5392 { 5393 void *data = val; 5394 int r = X86EMUL_CONTINUE; 5395 5396 while (bytes) { 5397 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 5398 exception); 5399 unsigned offset = addr & (PAGE_SIZE-1); 5400 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 5401 int ret; 5402 5403 if (gpa == UNMAPPED_GVA) 5404 return X86EMUL_PROPAGATE_FAULT; 5405 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 5406 offset, toread); 5407 if (ret < 0) { 5408 r = X86EMUL_IO_NEEDED; 5409 goto out; 5410 } 5411 5412 bytes -= toread; 5413 data += toread; 5414 addr += toread; 5415 } 5416 out: 5417 return r; 5418 } 5419 5420 /* used for instruction fetching */ 5421 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 5422 gva_t addr, void *val, unsigned int bytes, 5423 struct x86_exception *exception) 5424 { 5425 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5426 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5427 unsigned offset; 5428 int ret; 5429 5430 /* Inline kvm_read_guest_virt_helper for speed. */ 5431 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 5432 exception); 5433 if (unlikely(gpa == UNMAPPED_GVA)) 5434 return X86EMUL_PROPAGATE_FAULT; 5435 5436 offset = addr & (PAGE_SIZE-1); 5437 if (WARN_ON(offset + bytes > PAGE_SIZE)) 5438 bytes = (unsigned)PAGE_SIZE - offset; 5439 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 5440 offset, bytes); 5441 if (unlikely(ret < 0)) 5442 return X86EMUL_IO_NEEDED; 5443 5444 return X86EMUL_CONTINUE; 5445 } 5446 5447 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 5448 gva_t addr, void *val, unsigned int bytes, 5449 struct x86_exception *exception) 5450 { 5451 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 5452 5453 /* 5454 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 5455 * is returned, but our callers are not ready for that and they blindly 5456 * call kvm_inject_page_fault. Ensure that they at least do not leak 5457 * uninitialized kernel stack memory into cr2 and error code. 5458 */ 5459 memset(exception, 0, sizeof(*exception)); 5460 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 5461 exception); 5462 } 5463 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 5464 5465 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 5466 gva_t addr, void *val, unsigned int bytes, 5467 struct x86_exception *exception, bool system) 5468 { 5469 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5470 u32 access = 0; 5471 5472 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3) 5473 access |= PFERR_USER_MASK; 5474 5475 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 5476 } 5477 5478 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 5479 unsigned long addr, void *val, unsigned int bytes) 5480 { 5481 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5482 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 5483 5484 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 5485 } 5486 5487 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 5488 struct kvm_vcpu *vcpu, u32 access, 5489 struct x86_exception *exception) 5490 { 5491 void *data = val; 5492 int r = X86EMUL_CONTINUE; 5493 5494 while (bytes) { 5495 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 5496 access, 5497 exception); 5498 unsigned offset = addr & (PAGE_SIZE-1); 5499 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 5500 int ret; 5501 5502 if (gpa == UNMAPPED_GVA) 5503 return X86EMUL_PROPAGATE_FAULT; 5504 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 5505 if (ret < 0) { 5506 r = X86EMUL_IO_NEEDED; 5507 goto out; 5508 } 5509 5510 bytes -= towrite; 5511 data += towrite; 5512 addr += towrite; 5513 } 5514 out: 5515 return r; 5516 } 5517 5518 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 5519 unsigned int bytes, struct x86_exception *exception, 5520 bool system) 5521 { 5522 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5523 u32 access = PFERR_WRITE_MASK; 5524 5525 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3) 5526 access |= PFERR_USER_MASK; 5527 5528 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 5529 access, exception); 5530 } 5531 5532 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 5533 unsigned int bytes, struct x86_exception *exception) 5534 { 5535 /* kvm_write_guest_virt_system can pull in tons of pages. */ 5536 vcpu->arch.l1tf_flush_l1d = true; 5537 5538 /* 5539 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 5540 * is returned, but our callers are not ready for that and they blindly 5541 * call kvm_inject_page_fault. Ensure that they at least do not leak 5542 * uninitialized kernel stack memory into cr2 and error code. 5543 */ 5544 memset(exception, 0, sizeof(*exception)); 5545 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 5546 PFERR_WRITE_MASK, exception); 5547 } 5548 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 5549 5550 int handle_ud(struct kvm_vcpu *vcpu) 5551 { 5552 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; 5553 int emul_type = EMULTYPE_TRAP_UD; 5554 char sig[5]; /* ud2; .ascii "kvm" */ 5555 struct x86_exception e; 5556 5557 if (force_emulation_prefix && 5558 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 5559 sig, sizeof(sig), &e) == 0 && 5560 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { 5561 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 5562 emul_type = EMULTYPE_TRAP_UD_FORCED; 5563 } 5564 5565 return kvm_emulate_instruction(vcpu, emul_type); 5566 } 5567 EXPORT_SYMBOL_GPL(handle_ud); 5568 5569 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 5570 gpa_t gpa, bool write) 5571 { 5572 /* For APIC access vmexit */ 5573 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 5574 return 1; 5575 5576 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 5577 trace_vcpu_match_mmio(gva, gpa, write, true); 5578 return 1; 5579 } 5580 5581 return 0; 5582 } 5583 5584 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 5585 gpa_t *gpa, struct x86_exception *exception, 5586 bool write) 5587 { 5588 u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 5589 | (write ? PFERR_WRITE_MASK : 0); 5590 5591 /* 5592 * currently PKRU is only applied to ept enabled guest so 5593 * there is no pkey in EPT page table for L1 guest or EPT 5594 * shadow page table for L2 guest. 5595 */ 5596 if (vcpu_match_mmio_gva(vcpu, gva) 5597 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 5598 vcpu->arch.mmio_access, 0, access)) { 5599 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 5600 (gva & (PAGE_SIZE - 1)); 5601 trace_vcpu_match_mmio(gva, *gpa, write, false); 5602 return 1; 5603 } 5604 5605 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5606 5607 if (*gpa == UNMAPPED_GVA) 5608 return -1; 5609 5610 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 5611 } 5612 5613 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 5614 const void *val, int bytes) 5615 { 5616 int ret; 5617 5618 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 5619 if (ret < 0) 5620 return 0; 5621 kvm_page_track_write(vcpu, gpa, val, bytes); 5622 return 1; 5623 } 5624 5625 struct read_write_emulator_ops { 5626 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 5627 int bytes); 5628 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 5629 void *val, int bytes); 5630 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 5631 int bytes, void *val); 5632 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 5633 void *val, int bytes); 5634 bool write; 5635 }; 5636 5637 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 5638 { 5639 if (vcpu->mmio_read_completed) { 5640 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 5641 vcpu->mmio_fragments[0].gpa, val); 5642 vcpu->mmio_read_completed = 0; 5643 return 1; 5644 } 5645 5646 return 0; 5647 } 5648 5649 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 5650 void *val, int bytes) 5651 { 5652 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 5653 } 5654 5655 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 5656 void *val, int bytes) 5657 { 5658 return emulator_write_phys(vcpu, gpa, val, bytes); 5659 } 5660 5661 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 5662 { 5663 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 5664 return vcpu_mmio_write(vcpu, gpa, bytes, val); 5665 } 5666 5667 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 5668 void *val, int bytes) 5669 { 5670 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 5671 return X86EMUL_IO_NEEDED; 5672 } 5673 5674 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 5675 void *val, int bytes) 5676 { 5677 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 5678 5679 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 5680 return X86EMUL_CONTINUE; 5681 } 5682 5683 static const struct read_write_emulator_ops read_emultor = { 5684 .read_write_prepare = read_prepare, 5685 .read_write_emulate = read_emulate, 5686 .read_write_mmio = vcpu_mmio_read, 5687 .read_write_exit_mmio = read_exit_mmio, 5688 }; 5689 5690 static const struct read_write_emulator_ops write_emultor = { 5691 .read_write_emulate = write_emulate, 5692 .read_write_mmio = write_mmio, 5693 .read_write_exit_mmio = write_exit_mmio, 5694 .write = true, 5695 }; 5696 5697 static int emulator_read_write_onepage(unsigned long addr, void *val, 5698 unsigned int bytes, 5699 struct x86_exception *exception, 5700 struct kvm_vcpu *vcpu, 5701 const struct read_write_emulator_ops *ops) 5702 { 5703 gpa_t gpa; 5704 int handled, ret; 5705 bool write = ops->write; 5706 struct kvm_mmio_fragment *frag; 5707 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 5708 5709 /* 5710 * If the exit was due to a NPF we may already have a GPA. 5711 * If the GPA is present, use it to avoid the GVA to GPA table walk. 5712 * Note, this cannot be used on string operations since string 5713 * operation using rep will only have the initial GPA from the NPF 5714 * occurred. 5715 */ 5716 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && 5717 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { 5718 gpa = ctxt->gpa_val; 5719 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 5720 } else { 5721 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 5722 if (ret < 0) 5723 return X86EMUL_PROPAGATE_FAULT; 5724 } 5725 5726 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 5727 return X86EMUL_CONTINUE; 5728 5729 /* 5730 * Is this MMIO handled locally? 5731 */ 5732 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 5733 if (handled == bytes) 5734 return X86EMUL_CONTINUE; 5735 5736 gpa += handled; 5737 bytes -= handled; 5738 val += handled; 5739 5740 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 5741 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 5742 frag->gpa = gpa; 5743 frag->data = val; 5744 frag->len = bytes; 5745 return X86EMUL_CONTINUE; 5746 } 5747 5748 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 5749 unsigned long addr, 5750 void *val, unsigned int bytes, 5751 struct x86_exception *exception, 5752 const struct read_write_emulator_ops *ops) 5753 { 5754 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5755 gpa_t gpa; 5756 int rc; 5757 5758 if (ops->read_write_prepare && 5759 ops->read_write_prepare(vcpu, val, bytes)) 5760 return X86EMUL_CONTINUE; 5761 5762 vcpu->mmio_nr_fragments = 0; 5763 5764 /* Crossing a page boundary? */ 5765 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 5766 int now; 5767 5768 now = -addr & ~PAGE_MASK; 5769 rc = emulator_read_write_onepage(addr, val, now, exception, 5770 vcpu, ops); 5771 5772 if (rc != X86EMUL_CONTINUE) 5773 return rc; 5774 addr += now; 5775 if (ctxt->mode != X86EMUL_MODE_PROT64) 5776 addr = (u32)addr; 5777 val += now; 5778 bytes -= now; 5779 } 5780 5781 rc = emulator_read_write_onepage(addr, val, bytes, exception, 5782 vcpu, ops); 5783 if (rc != X86EMUL_CONTINUE) 5784 return rc; 5785 5786 if (!vcpu->mmio_nr_fragments) 5787 return rc; 5788 5789 gpa = vcpu->mmio_fragments[0].gpa; 5790 5791 vcpu->mmio_needed = 1; 5792 vcpu->mmio_cur_fragment = 0; 5793 5794 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 5795 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 5796 vcpu->run->exit_reason = KVM_EXIT_MMIO; 5797 vcpu->run->mmio.phys_addr = gpa; 5798 5799 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 5800 } 5801 5802 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 5803 unsigned long addr, 5804 void *val, 5805 unsigned int bytes, 5806 struct x86_exception *exception) 5807 { 5808 return emulator_read_write(ctxt, addr, val, bytes, 5809 exception, &read_emultor); 5810 } 5811 5812 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 5813 unsigned long addr, 5814 const void *val, 5815 unsigned int bytes, 5816 struct x86_exception *exception) 5817 { 5818 return emulator_read_write(ctxt, addr, (void *)val, bytes, 5819 exception, &write_emultor); 5820 } 5821 5822 #define CMPXCHG_TYPE(t, ptr, old, new) \ 5823 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 5824 5825 #ifdef CONFIG_X86_64 5826 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 5827 #else 5828 # define CMPXCHG64(ptr, old, new) \ 5829 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 5830 #endif 5831 5832 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 5833 unsigned long addr, 5834 const void *old, 5835 const void *new, 5836 unsigned int bytes, 5837 struct x86_exception *exception) 5838 { 5839 struct kvm_host_map map; 5840 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5841 gpa_t gpa; 5842 char *kaddr; 5843 bool exchanged; 5844 5845 /* guests cmpxchg8b have to be emulated atomically */ 5846 if (bytes > 8 || (bytes & (bytes - 1))) 5847 goto emul_write; 5848 5849 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 5850 5851 if (gpa == UNMAPPED_GVA || 5852 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 5853 goto emul_write; 5854 5855 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 5856 goto emul_write; 5857 5858 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) 5859 goto emul_write; 5860 5861 kaddr = map.hva + offset_in_page(gpa); 5862 5863 switch (bytes) { 5864 case 1: 5865 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 5866 break; 5867 case 2: 5868 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 5869 break; 5870 case 4: 5871 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 5872 break; 5873 case 8: 5874 exchanged = CMPXCHG64(kaddr, old, new); 5875 break; 5876 default: 5877 BUG(); 5878 } 5879 5880 kvm_vcpu_unmap(vcpu, &map, true); 5881 5882 if (!exchanged) 5883 return X86EMUL_CMPXCHG_FAILED; 5884 5885 kvm_page_track_write(vcpu, gpa, new, bytes); 5886 5887 return X86EMUL_CONTINUE; 5888 5889 emul_write: 5890 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 5891 5892 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 5893 } 5894 5895 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 5896 { 5897 int r = 0, i; 5898 5899 for (i = 0; i < vcpu->arch.pio.count; i++) { 5900 if (vcpu->arch.pio.in) 5901 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 5902 vcpu->arch.pio.size, pd); 5903 else 5904 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 5905 vcpu->arch.pio.port, vcpu->arch.pio.size, 5906 pd); 5907 if (r) 5908 break; 5909 pd += vcpu->arch.pio.size; 5910 } 5911 return r; 5912 } 5913 5914 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 5915 unsigned short port, void *val, 5916 unsigned int count, bool in) 5917 { 5918 vcpu->arch.pio.port = port; 5919 vcpu->arch.pio.in = in; 5920 vcpu->arch.pio.count = count; 5921 vcpu->arch.pio.size = size; 5922 5923 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 5924 vcpu->arch.pio.count = 0; 5925 return 1; 5926 } 5927 5928 vcpu->run->exit_reason = KVM_EXIT_IO; 5929 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 5930 vcpu->run->io.size = size; 5931 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 5932 vcpu->run->io.count = count; 5933 vcpu->run->io.port = port; 5934 5935 return 0; 5936 } 5937 5938 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, 5939 unsigned short port, void *val, unsigned int count) 5940 { 5941 int ret; 5942 5943 if (vcpu->arch.pio.count) 5944 goto data_avail; 5945 5946 memset(vcpu->arch.pio_data, 0, size * count); 5947 5948 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 5949 if (ret) { 5950 data_avail: 5951 memcpy(val, vcpu->arch.pio_data, size * count); 5952 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 5953 vcpu->arch.pio.count = 0; 5954 return 1; 5955 } 5956 5957 return 0; 5958 } 5959 5960 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 5961 int size, unsigned short port, void *val, 5962 unsigned int count) 5963 { 5964 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); 5965 5966 } 5967 5968 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, 5969 unsigned short port, const void *val, 5970 unsigned int count) 5971 { 5972 memcpy(vcpu->arch.pio_data, val, size * count); 5973 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 5974 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 5975 } 5976 5977 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 5978 int size, unsigned short port, 5979 const void *val, unsigned int count) 5980 { 5981 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); 5982 } 5983 5984 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 5985 { 5986 return kvm_x86_ops.get_segment_base(vcpu, seg); 5987 } 5988 5989 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 5990 { 5991 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 5992 } 5993 5994 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 5995 { 5996 if (!need_emulate_wbinvd(vcpu)) 5997 return X86EMUL_CONTINUE; 5998 5999 if (kvm_x86_ops.has_wbinvd_exit()) { 6000 int cpu = get_cpu(); 6001 6002 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 6003 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 6004 wbinvd_ipi, NULL, 1); 6005 put_cpu(); 6006 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 6007 } else 6008 wbinvd(); 6009 return X86EMUL_CONTINUE; 6010 } 6011 6012 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 6013 { 6014 kvm_emulate_wbinvd_noskip(vcpu); 6015 return kvm_skip_emulated_instruction(vcpu); 6016 } 6017 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 6018 6019 6020 6021 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 6022 { 6023 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 6024 } 6025 6026 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 6027 unsigned long *dest) 6028 { 6029 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 6030 } 6031 6032 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 6033 unsigned long value) 6034 { 6035 6036 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 6037 } 6038 6039 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 6040 { 6041 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 6042 } 6043 6044 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 6045 { 6046 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6047 unsigned long value; 6048 6049 switch (cr) { 6050 case 0: 6051 value = kvm_read_cr0(vcpu); 6052 break; 6053 case 2: 6054 value = vcpu->arch.cr2; 6055 break; 6056 case 3: 6057 value = kvm_read_cr3(vcpu); 6058 break; 6059 case 4: 6060 value = kvm_read_cr4(vcpu); 6061 break; 6062 case 8: 6063 value = kvm_get_cr8(vcpu); 6064 break; 6065 default: 6066 kvm_err("%s: unexpected cr %u\n", __func__, cr); 6067 return 0; 6068 } 6069 6070 return value; 6071 } 6072 6073 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 6074 { 6075 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6076 int res = 0; 6077 6078 switch (cr) { 6079 case 0: 6080 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 6081 break; 6082 case 2: 6083 vcpu->arch.cr2 = val; 6084 break; 6085 case 3: 6086 res = kvm_set_cr3(vcpu, val); 6087 break; 6088 case 4: 6089 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 6090 break; 6091 case 8: 6092 res = kvm_set_cr8(vcpu, val); 6093 break; 6094 default: 6095 kvm_err("%s: unexpected cr %u\n", __func__, cr); 6096 res = -1; 6097 } 6098 6099 return res; 6100 } 6101 6102 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 6103 { 6104 return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt)); 6105 } 6106 6107 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6108 { 6109 kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt); 6110 } 6111 6112 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6113 { 6114 kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt); 6115 } 6116 6117 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6118 { 6119 kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt); 6120 } 6121 6122 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6123 { 6124 kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt); 6125 } 6126 6127 static unsigned long emulator_get_cached_segment_base( 6128 struct x86_emulate_ctxt *ctxt, int seg) 6129 { 6130 return get_segment_base(emul_to_vcpu(ctxt), seg); 6131 } 6132 6133 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 6134 struct desc_struct *desc, u32 *base3, 6135 int seg) 6136 { 6137 struct kvm_segment var; 6138 6139 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 6140 *selector = var.selector; 6141 6142 if (var.unusable) { 6143 memset(desc, 0, sizeof(*desc)); 6144 if (base3) 6145 *base3 = 0; 6146 return false; 6147 } 6148 6149 if (var.g) 6150 var.limit >>= 12; 6151 set_desc_limit(desc, var.limit); 6152 set_desc_base(desc, (unsigned long)var.base); 6153 #ifdef CONFIG_X86_64 6154 if (base3) 6155 *base3 = var.base >> 32; 6156 #endif 6157 desc->type = var.type; 6158 desc->s = var.s; 6159 desc->dpl = var.dpl; 6160 desc->p = var.present; 6161 desc->avl = var.avl; 6162 desc->l = var.l; 6163 desc->d = var.db; 6164 desc->g = var.g; 6165 6166 return true; 6167 } 6168 6169 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 6170 struct desc_struct *desc, u32 base3, 6171 int seg) 6172 { 6173 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6174 struct kvm_segment var; 6175 6176 var.selector = selector; 6177 var.base = get_desc_base(desc); 6178 #ifdef CONFIG_X86_64 6179 var.base |= ((u64)base3) << 32; 6180 #endif 6181 var.limit = get_desc_limit(desc); 6182 if (desc->g) 6183 var.limit = (var.limit << 12) | 0xfff; 6184 var.type = desc->type; 6185 var.dpl = desc->dpl; 6186 var.db = desc->d; 6187 var.s = desc->s; 6188 var.l = desc->l; 6189 var.g = desc->g; 6190 var.avl = desc->avl; 6191 var.present = desc->p; 6192 var.unusable = !var.present; 6193 var.padding = 0; 6194 6195 kvm_set_segment(vcpu, &var, seg); 6196 return; 6197 } 6198 6199 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 6200 u32 msr_index, u64 *pdata) 6201 { 6202 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); 6203 } 6204 6205 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 6206 u32 msr_index, u64 data) 6207 { 6208 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data); 6209 } 6210 6211 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 6212 { 6213 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6214 6215 return vcpu->arch.smbase; 6216 } 6217 6218 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 6219 { 6220 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6221 6222 vcpu->arch.smbase = smbase; 6223 } 6224 6225 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 6226 u32 pmc) 6227 { 6228 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); 6229 } 6230 6231 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 6232 u32 pmc, u64 *pdata) 6233 { 6234 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 6235 } 6236 6237 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 6238 { 6239 emul_to_vcpu(ctxt)->arch.halt_request = 1; 6240 } 6241 6242 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 6243 struct x86_instruction_info *info, 6244 enum x86_intercept_stage stage) 6245 { 6246 return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage, 6247 &ctxt->exception); 6248 } 6249 6250 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 6251 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, 6252 bool exact_only) 6253 { 6254 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); 6255 } 6256 6257 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) 6258 { 6259 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); 6260 } 6261 6262 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) 6263 { 6264 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); 6265 } 6266 6267 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) 6268 { 6269 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); 6270 } 6271 6272 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 6273 { 6274 return kvm_register_read(emul_to_vcpu(ctxt), reg); 6275 } 6276 6277 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 6278 { 6279 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 6280 } 6281 6282 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 6283 { 6284 kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked); 6285 } 6286 6287 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 6288 { 6289 return emul_to_vcpu(ctxt)->arch.hflags; 6290 } 6291 6292 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) 6293 { 6294 emul_to_vcpu(ctxt)->arch.hflags = emul_flags; 6295 } 6296 6297 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, 6298 const char *smstate) 6299 { 6300 return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate); 6301 } 6302 6303 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) 6304 { 6305 kvm_smm_changed(emul_to_vcpu(ctxt)); 6306 } 6307 6308 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) 6309 { 6310 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); 6311 } 6312 6313 static const struct x86_emulate_ops emulate_ops = { 6314 .read_gpr = emulator_read_gpr, 6315 .write_gpr = emulator_write_gpr, 6316 .read_std = emulator_read_std, 6317 .write_std = emulator_write_std, 6318 .read_phys = kvm_read_guest_phys_system, 6319 .fetch = kvm_fetch_guest_virt, 6320 .read_emulated = emulator_read_emulated, 6321 .write_emulated = emulator_write_emulated, 6322 .cmpxchg_emulated = emulator_cmpxchg_emulated, 6323 .invlpg = emulator_invlpg, 6324 .pio_in_emulated = emulator_pio_in_emulated, 6325 .pio_out_emulated = emulator_pio_out_emulated, 6326 .get_segment = emulator_get_segment, 6327 .set_segment = emulator_set_segment, 6328 .get_cached_segment_base = emulator_get_cached_segment_base, 6329 .get_gdt = emulator_get_gdt, 6330 .get_idt = emulator_get_idt, 6331 .set_gdt = emulator_set_gdt, 6332 .set_idt = emulator_set_idt, 6333 .get_cr = emulator_get_cr, 6334 .set_cr = emulator_set_cr, 6335 .cpl = emulator_get_cpl, 6336 .get_dr = emulator_get_dr, 6337 .set_dr = emulator_set_dr, 6338 .get_smbase = emulator_get_smbase, 6339 .set_smbase = emulator_set_smbase, 6340 .set_msr = emulator_set_msr, 6341 .get_msr = emulator_get_msr, 6342 .check_pmc = emulator_check_pmc, 6343 .read_pmc = emulator_read_pmc, 6344 .halt = emulator_halt, 6345 .wbinvd = emulator_wbinvd, 6346 .fix_hypercall = emulator_fix_hypercall, 6347 .intercept = emulator_intercept, 6348 .get_cpuid = emulator_get_cpuid, 6349 .guest_has_long_mode = emulator_guest_has_long_mode, 6350 .guest_has_movbe = emulator_guest_has_movbe, 6351 .guest_has_fxsr = emulator_guest_has_fxsr, 6352 .set_nmi_mask = emulator_set_nmi_mask, 6353 .get_hflags = emulator_get_hflags, 6354 .set_hflags = emulator_set_hflags, 6355 .pre_leave_smm = emulator_pre_leave_smm, 6356 .post_leave_smm = emulator_post_leave_smm, 6357 .set_xcr = emulator_set_xcr, 6358 }; 6359 6360 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 6361 { 6362 u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu); 6363 /* 6364 * an sti; sti; sequence only disable interrupts for the first 6365 * instruction. So, if the last instruction, be it emulated or 6366 * not, left the system with the INT_STI flag enabled, it 6367 * means that the last instruction is an sti. We should not 6368 * leave the flag on in this case. The same goes for mov ss 6369 */ 6370 if (int_shadow & mask) 6371 mask = 0; 6372 if (unlikely(int_shadow || mask)) { 6373 kvm_x86_ops.set_interrupt_shadow(vcpu, mask); 6374 if (!mask) 6375 kvm_make_request(KVM_REQ_EVENT, vcpu); 6376 } 6377 } 6378 6379 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 6380 { 6381 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6382 if (ctxt->exception.vector == PF_VECTOR) 6383 return kvm_propagate_fault(vcpu, &ctxt->exception); 6384 6385 if (ctxt->exception.error_code_valid) 6386 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 6387 ctxt->exception.error_code); 6388 else 6389 kvm_queue_exception(vcpu, ctxt->exception.vector); 6390 return false; 6391 } 6392 6393 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) 6394 { 6395 struct x86_emulate_ctxt *ctxt; 6396 6397 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); 6398 if (!ctxt) { 6399 pr_err("kvm: failed to allocate vcpu's emulator\n"); 6400 return NULL; 6401 } 6402 6403 ctxt->vcpu = vcpu; 6404 ctxt->ops = &emulate_ops; 6405 vcpu->arch.emulate_ctxt = ctxt; 6406 6407 return ctxt; 6408 } 6409 6410 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 6411 { 6412 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6413 int cs_db, cs_l; 6414 6415 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 6416 6417 ctxt->gpa_available = false; 6418 ctxt->eflags = kvm_get_rflags(vcpu); 6419 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 6420 6421 ctxt->eip = kvm_rip_read(vcpu); 6422 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 6423 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 6424 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 6425 cs_db ? X86EMUL_MODE_PROT32 : 6426 X86EMUL_MODE_PROT16; 6427 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 6428 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 6429 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 6430 6431 init_decode_cache(ctxt); 6432 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 6433 } 6434 6435 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 6436 { 6437 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6438 int ret; 6439 6440 init_emulate_ctxt(vcpu); 6441 6442 ctxt->op_bytes = 2; 6443 ctxt->ad_bytes = 2; 6444 ctxt->_eip = ctxt->eip + inc_eip; 6445 ret = emulate_int_real(ctxt, irq); 6446 6447 if (ret != X86EMUL_CONTINUE) { 6448 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 6449 } else { 6450 ctxt->eip = ctxt->_eip; 6451 kvm_rip_write(vcpu, ctxt->eip); 6452 kvm_set_rflags(vcpu, ctxt->eflags); 6453 } 6454 } 6455 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 6456 6457 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 6458 { 6459 ++vcpu->stat.insn_emulation_fail; 6460 trace_kvm_emulate_insn_failed(vcpu); 6461 6462 if (emulation_type & EMULTYPE_VMWARE_GP) { 6463 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 6464 return 1; 6465 } 6466 6467 if (emulation_type & EMULTYPE_SKIP) { 6468 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 6469 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 6470 vcpu->run->internal.ndata = 0; 6471 return 0; 6472 } 6473 6474 kvm_queue_exception(vcpu, UD_VECTOR); 6475 6476 if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) { 6477 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 6478 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 6479 vcpu->run->internal.ndata = 0; 6480 return 0; 6481 } 6482 6483 return 1; 6484 } 6485 6486 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 6487 bool write_fault_to_shadow_pgtable, 6488 int emulation_type) 6489 { 6490 gpa_t gpa = cr2_or_gpa; 6491 kvm_pfn_t pfn; 6492 6493 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 6494 return false; 6495 6496 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 6497 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 6498 return false; 6499 6500 if (!vcpu->arch.mmu->direct_map) { 6501 /* 6502 * Write permission should be allowed since only 6503 * write access need to be emulated. 6504 */ 6505 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 6506 6507 /* 6508 * If the mapping is invalid in guest, let cpu retry 6509 * it to generate fault. 6510 */ 6511 if (gpa == UNMAPPED_GVA) 6512 return true; 6513 } 6514 6515 /* 6516 * Do not retry the unhandleable instruction if it faults on the 6517 * readonly host memory, otherwise it will goto a infinite loop: 6518 * retry instruction -> write #PF -> emulation fail -> retry 6519 * instruction -> ... 6520 */ 6521 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 6522 6523 /* 6524 * If the instruction failed on the error pfn, it can not be fixed, 6525 * report the error to userspace. 6526 */ 6527 if (is_error_noslot_pfn(pfn)) 6528 return false; 6529 6530 kvm_release_pfn_clean(pfn); 6531 6532 /* The instructions are well-emulated on direct mmu. */ 6533 if (vcpu->arch.mmu->direct_map) { 6534 unsigned int indirect_shadow_pages; 6535 6536 spin_lock(&vcpu->kvm->mmu_lock); 6537 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 6538 spin_unlock(&vcpu->kvm->mmu_lock); 6539 6540 if (indirect_shadow_pages) 6541 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 6542 6543 return true; 6544 } 6545 6546 /* 6547 * if emulation was due to access to shadowed page table 6548 * and it failed try to unshadow page and re-enter the 6549 * guest to let CPU execute the instruction. 6550 */ 6551 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 6552 6553 /* 6554 * If the access faults on its page table, it can not 6555 * be fixed by unprotecting shadow page and it should 6556 * be reported to userspace. 6557 */ 6558 return !write_fault_to_shadow_pgtable; 6559 } 6560 6561 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 6562 gpa_t cr2_or_gpa, int emulation_type) 6563 { 6564 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6565 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; 6566 6567 last_retry_eip = vcpu->arch.last_retry_eip; 6568 last_retry_addr = vcpu->arch.last_retry_addr; 6569 6570 /* 6571 * If the emulation is caused by #PF and it is non-page_table 6572 * writing instruction, it means the VM-EXIT is caused by shadow 6573 * page protected, we can zap the shadow page and retry this 6574 * instruction directly. 6575 * 6576 * Note: if the guest uses a non-page-table modifying instruction 6577 * on the PDE that points to the instruction, then we will unmap 6578 * the instruction and go to an infinite loop. So, we cache the 6579 * last retried eip and the last fault address, if we meet the eip 6580 * and the address again, we can break out of the potential infinite 6581 * loop. 6582 */ 6583 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 6584 6585 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 6586 return false; 6587 6588 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 6589 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 6590 return false; 6591 6592 if (x86_page_table_writing_insn(ctxt)) 6593 return false; 6594 6595 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) 6596 return false; 6597 6598 vcpu->arch.last_retry_eip = ctxt->eip; 6599 vcpu->arch.last_retry_addr = cr2_or_gpa; 6600 6601 if (!vcpu->arch.mmu->direct_map) 6602 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 6603 6604 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 6605 6606 return true; 6607 } 6608 6609 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 6610 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 6611 6612 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 6613 { 6614 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 6615 /* This is a good place to trace that we are exiting SMM. */ 6616 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 6617 6618 /* Process a latched INIT or SMI, if any. */ 6619 kvm_make_request(KVM_REQ_EVENT, vcpu); 6620 } 6621 6622 kvm_mmu_reset_context(vcpu); 6623 } 6624 6625 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 6626 unsigned long *db) 6627 { 6628 u32 dr6 = 0; 6629 int i; 6630 u32 enable, rwlen; 6631 6632 enable = dr7; 6633 rwlen = dr7 >> 16; 6634 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 6635 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 6636 dr6 |= (1 << i); 6637 return dr6; 6638 } 6639 6640 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) 6641 { 6642 struct kvm_run *kvm_run = vcpu->run; 6643 6644 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 6645 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; 6646 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 6647 kvm_run->debug.arch.exception = DB_VECTOR; 6648 kvm_run->exit_reason = KVM_EXIT_DEBUG; 6649 return 0; 6650 } 6651 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 6652 return 1; 6653 } 6654 6655 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 6656 { 6657 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu); 6658 int r; 6659 6660 r = kvm_x86_ops.skip_emulated_instruction(vcpu); 6661 if (unlikely(!r)) 6662 return 0; 6663 6664 /* 6665 * rflags is the old, "raw" value of the flags. The new value has 6666 * not been saved yet. 6667 * 6668 * This is correct even for TF set by the guest, because "the 6669 * processor will not generate this exception after the instruction 6670 * that sets the TF flag". 6671 */ 6672 if (unlikely(rflags & X86_EFLAGS_TF)) 6673 r = kvm_vcpu_do_singlestep(vcpu); 6674 return r; 6675 } 6676 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 6677 6678 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 6679 { 6680 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 6681 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 6682 struct kvm_run *kvm_run = vcpu->run; 6683 unsigned long eip = kvm_get_linear_rip(vcpu); 6684 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 6685 vcpu->arch.guest_debug_dr7, 6686 vcpu->arch.eff_db); 6687 6688 if (dr6 != 0) { 6689 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 6690 kvm_run->debug.arch.pc = eip; 6691 kvm_run->debug.arch.exception = DB_VECTOR; 6692 kvm_run->exit_reason = KVM_EXIT_DEBUG; 6693 *r = 0; 6694 return true; 6695 } 6696 } 6697 6698 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 6699 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 6700 unsigned long eip = kvm_get_linear_rip(vcpu); 6701 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 6702 vcpu->arch.dr7, 6703 vcpu->arch.db); 6704 6705 if (dr6 != 0) { 6706 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 6707 vcpu->arch.dr6 |= dr6 | DR6_RTM; 6708 kvm_queue_exception(vcpu, DB_VECTOR); 6709 *r = 1; 6710 return true; 6711 } 6712 } 6713 6714 return false; 6715 } 6716 6717 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 6718 { 6719 switch (ctxt->opcode_len) { 6720 case 1: 6721 switch (ctxt->b) { 6722 case 0xe4: /* IN */ 6723 case 0xe5: 6724 case 0xec: 6725 case 0xed: 6726 case 0xe6: /* OUT */ 6727 case 0xe7: 6728 case 0xee: 6729 case 0xef: 6730 case 0x6c: /* INS */ 6731 case 0x6d: 6732 case 0x6e: /* OUTS */ 6733 case 0x6f: 6734 return true; 6735 } 6736 break; 6737 case 2: 6738 switch (ctxt->b) { 6739 case 0x33: /* RDPMC */ 6740 return true; 6741 } 6742 break; 6743 } 6744 6745 return false; 6746 } 6747 6748 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 6749 int emulation_type, void *insn, int insn_len) 6750 { 6751 int r; 6752 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6753 bool writeback = true; 6754 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 6755 6756 vcpu->arch.l1tf_flush_l1d = true; 6757 6758 /* 6759 * Clear write_fault_to_shadow_pgtable here to ensure it is 6760 * never reused. 6761 */ 6762 vcpu->arch.write_fault_to_shadow_pgtable = false; 6763 kvm_clear_exception_queue(vcpu); 6764 6765 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 6766 init_emulate_ctxt(vcpu); 6767 6768 /* 6769 * We will reenter on the same instruction since 6770 * we do not set complete_userspace_io. This does not 6771 * handle watchpoints yet, those would be handled in 6772 * the emulate_ops. 6773 */ 6774 if (!(emulation_type & EMULTYPE_SKIP) && 6775 kvm_vcpu_check_breakpoint(vcpu, &r)) 6776 return r; 6777 6778 ctxt->interruptibility = 0; 6779 ctxt->have_exception = false; 6780 ctxt->exception.vector = -1; 6781 ctxt->perm_ok = false; 6782 6783 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 6784 6785 r = x86_decode_insn(ctxt, insn, insn_len); 6786 6787 trace_kvm_emulate_insn_start(vcpu); 6788 ++vcpu->stat.insn_emulation; 6789 if (r != EMULATION_OK) { 6790 if ((emulation_type & EMULTYPE_TRAP_UD) || 6791 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { 6792 kvm_queue_exception(vcpu, UD_VECTOR); 6793 return 1; 6794 } 6795 if (reexecute_instruction(vcpu, cr2_or_gpa, 6796 write_fault_to_spt, 6797 emulation_type)) 6798 return 1; 6799 if (ctxt->have_exception) { 6800 /* 6801 * #UD should result in just EMULATION_FAILED, and trap-like 6802 * exception should not be encountered during decode. 6803 */ 6804 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || 6805 exception_type(ctxt->exception.vector) == EXCPT_TRAP); 6806 inject_emulated_exception(vcpu); 6807 return 1; 6808 } 6809 return handle_emulation_failure(vcpu, emulation_type); 6810 } 6811 } 6812 6813 if ((emulation_type & EMULTYPE_VMWARE_GP) && 6814 !is_vmware_backdoor_opcode(ctxt)) { 6815 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 6816 return 1; 6817 } 6818 6819 /* 6820 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks 6821 * for kvm_skip_emulated_instruction(). The caller is responsible for 6822 * updating interruptibility state and injecting single-step #DBs. 6823 */ 6824 if (emulation_type & EMULTYPE_SKIP) { 6825 kvm_rip_write(vcpu, ctxt->_eip); 6826 if (ctxt->eflags & X86_EFLAGS_RF) 6827 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 6828 return 1; 6829 } 6830 6831 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) 6832 return 1; 6833 6834 /* this is needed for vmware backdoor interface to work since it 6835 changes registers values during IO operation */ 6836 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 6837 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 6838 emulator_invalidate_register_cache(ctxt); 6839 } 6840 6841 restart: 6842 if (emulation_type & EMULTYPE_PF) { 6843 /* Save the faulting GPA (cr2) in the address field */ 6844 ctxt->exception.address = cr2_or_gpa; 6845 6846 /* With shadow page tables, cr2 contains a GVA or nGPA. */ 6847 if (vcpu->arch.mmu->direct_map) { 6848 ctxt->gpa_available = true; 6849 ctxt->gpa_val = cr2_or_gpa; 6850 } 6851 } else { 6852 /* Sanitize the address out of an abundance of paranoia. */ 6853 ctxt->exception.address = 0; 6854 } 6855 6856 r = x86_emulate_insn(ctxt); 6857 6858 if (r == EMULATION_INTERCEPTED) 6859 return 1; 6860 6861 if (r == EMULATION_FAILED) { 6862 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, 6863 emulation_type)) 6864 return 1; 6865 6866 return handle_emulation_failure(vcpu, emulation_type); 6867 } 6868 6869 if (ctxt->have_exception) { 6870 r = 1; 6871 if (inject_emulated_exception(vcpu)) 6872 return r; 6873 } else if (vcpu->arch.pio.count) { 6874 if (!vcpu->arch.pio.in) { 6875 /* FIXME: return into emulator if single-stepping. */ 6876 vcpu->arch.pio.count = 0; 6877 } else { 6878 writeback = false; 6879 vcpu->arch.complete_userspace_io = complete_emulated_pio; 6880 } 6881 r = 0; 6882 } else if (vcpu->mmio_needed) { 6883 ++vcpu->stat.mmio_exits; 6884 6885 if (!vcpu->mmio_is_write) 6886 writeback = false; 6887 r = 0; 6888 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6889 } else if (r == EMULATION_RESTART) 6890 goto restart; 6891 else 6892 r = 1; 6893 6894 if (writeback) { 6895 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu); 6896 toggle_interruptibility(vcpu, ctxt->interruptibility); 6897 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6898 if (!ctxt->have_exception || 6899 exception_type(ctxt->exception.vector) == EXCPT_TRAP) { 6900 kvm_rip_write(vcpu, ctxt->eip); 6901 if (r && ctxt->tf) 6902 r = kvm_vcpu_do_singlestep(vcpu); 6903 if (kvm_x86_ops.update_emulated_instruction) 6904 kvm_x86_ops.update_emulated_instruction(vcpu); 6905 __kvm_set_rflags(vcpu, ctxt->eflags); 6906 } 6907 6908 /* 6909 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 6910 * do nothing, and it will be requested again as soon as 6911 * the shadow expires. But we still need to check here, 6912 * because POPF has no interrupt shadow. 6913 */ 6914 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 6915 kvm_make_request(KVM_REQ_EVENT, vcpu); 6916 } else 6917 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 6918 6919 return r; 6920 } 6921 6922 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 6923 { 6924 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 6925 } 6926 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 6927 6928 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 6929 void *insn, int insn_len) 6930 { 6931 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 6932 } 6933 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 6934 6935 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 6936 { 6937 vcpu->arch.pio.count = 0; 6938 return 1; 6939 } 6940 6941 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 6942 { 6943 vcpu->arch.pio.count = 0; 6944 6945 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 6946 return 1; 6947 6948 return kvm_skip_emulated_instruction(vcpu); 6949 } 6950 6951 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 6952 unsigned short port) 6953 { 6954 unsigned long val = kvm_rax_read(vcpu); 6955 int ret = emulator_pio_out(vcpu, size, port, &val, 1); 6956 6957 if (ret) 6958 return ret; 6959 6960 /* 6961 * Workaround userspace that relies on old KVM behavior of %rip being 6962 * incremented prior to exiting to userspace to handle "OUT 0x7e". 6963 */ 6964 if (port == 0x7e && 6965 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 6966 vcpu->arch.complete_userspace_io = 6967 complete_fast_pio_out_port_0x7e; 6968 kvm_skip_emulated_instruction(vcpu); 6969 } else { 6970 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 6971 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 6972 } 6973 return 0; 6974 } 6975 6976 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 6977 { 6978 unsigned long val; 6979 6980 /* We should only ever be called with arch.pio.count equal to 1 */ 6981 BUG_ON(vcpu->arch.pio.count != 1); 6982 6983 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 6984 vcpu->arch.pio.count = 0; 6985 return 1; 6986 } 6987 6988 /* For size less than 4 we merge, else we zero extend */ 6989 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 6990 6991 /* 6992 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform 6993 * the copy and tracing 6994 */ 6995 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); 6996 kvm_rax_write(vcpu, val); 6997 6998 return kvm_skip_emulated_instruction(vcpu); 6999 } 7000 7001 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 7002 unsigned short port) 7003 { 7004 unsigned long val; 7005 int ret; 7006 7007 /* For size less than 4 we merge, else we zero extend */ 7008 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 7009 7010 ret = emulator_pio_in(vcpu, size, port, &val, 1); 7011 if (ret) { 7012 kvm_rax_write(vcpu, val); 7013 return ret; 7014 } 7015 7016 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 7017 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 7018 7019 return 0; 7020 } 7021 7022 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 7023 { 7024 int ret; 7025 7026 if (in) 7027 ret = kvm_fast_pio_in(vcpu, size, port); 7028 else 7029 ret = kvm_fast_pio_out(vcpu, size, port); 7030 return ret && kvm_skip_emulated_instruction(vcpu); 7031 } 7032 EXPORT_SYMBOL_GPL(kvm_fast_pio); 7033 7034 static int kvmclock_cpu_down_prep(unsigned int cpu) 7035 { 7036 __this_cpu_write(cpu_tsc_khz, 0); 7037 return 0; 7038 } 7039 7040 static void tsc_khz_changed(void *data) 7041 { 7042 struct cpufreq_freqs *freq = data; 7043 unsigned long khz = 0; 7044 7045 if (data) 7046 khz = freq->new; 7047 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 7048 khz = cpufreq_quick_get(raw_smp_processor_id()); 7049 if (!khz) 7050 khz = tsc_khz; 7051 __this_cpu_write(cpu_tsc_khz, khz); 7052 } 7053 7054 #ifdef CONFIG_X86_64 7055 static void kvm_hyperv_tsc_notifier(void) 7056 { 7057 struct kvm *kvm; 7058 struct kvm_vcpu *vcpu; 7059 int cpu; 7060 7061 mutex_lock(&kvm_lock); 7062 list_for_each_entry(kvm, &vm_list, vm_list) 7063 kvm_make_mclock_inprogress_request(kvm); 7064 7065 hyperv_stop_tsc_emulation(); 7066 7067 /* TSC frequency always matches when on Hyper-V */ 7068 for_each_present_cpu(cpu) 7069 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 7070 kvm_max_guest_tsc_khz = tsc_khz; 7071 7072 list_for_each_entry(kvm, &vm_list, vm_list) { 7073 struct kvm_arch *ka = &kvm->arch; 7074 7075 spin_lock(&ka->pvclock_gtod_sync_lock); 7076 7077 pvclock_update_vm_gtod_copy(kvm); 7078 7079 kvm_for_each_vcpu(cpu, vcpu, kvm) 7080 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7081 7082 kvm_for_each_vcpu(cpu, vcpu, kvm) 7083 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 7084 7085 spin_unlock(&ka->pvclock_gtod_sync_lock); 7086 } 7087 mutex_unlock(&kvm_lock); 7088 } 7089 #endif 7090 7091 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 7092 { 7093 struct kvm *kvm; 7094 struct kvm_vcpu *vcpu; 7095 int i, send_ipi = 0; 7096 7097 /* 7098 * We allow guests to temporarily run on slowing clocks, 7099 * provided we notify them after, or to run on accelerating 7100 * clocks, provided we notify them before. Thus time never 7101 * goes backwards. 7102 * 7103 * However, we have a problem. We can't atomically update 7104 * the frequency of a given CPU from this function; it is 7105 * merely a notifier, which can be called from any CPU. 7106 * Changing the TSC frequency at arbitrary points in time 7107 * requires a recomputation of local variables related to 7108 * the TSC for each VCPU. We must flag these local variables 7109 * to be updated and be sure the update takes place with the 7110 * new frequency before any guests proceed. 7111 * 7112 * Unfortunately, the combination of hotplug CPU and frequency 7113 * change creates an intractable locking scenario; the order 7114 * of when these callouts happen is undefined with respect to 7115 * CPU hotplug, and they can race with each other. As such, 7116 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 7117 * undefined; you can actually have a CPU frequency change take 7118 * place in between the computation of X and the setting of the 7119 * variable. To protect against this problem, all updates of 7120 * the per_cpu tsc_khz variable are done in an interrupt 7121 * protected IPI, and all callers wishing to update the value 7122 * must wait for a synchronous IPI to complete (which is trivial 7123 * if the caller is on the CPU already). This establishes the 7124 * necessary total order on variable updates. 7125 * 7126 * Note that because a guest time update may take place 7127 * anytime after the setting of the VCPU's request bit, the 7128 * correct TSC value must be set before the request. However, 7129 * to ensure the update actually makes it to any guest which 7130 * starts running in hardware virtualization between the set 7131 * and the acquisition of the spinlock, we must also ping the 7132 * CPU after setting the request bit. 7133 * 7134 */ 7135 7136 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 7137 7138 mutex_lock(&kvm_lock); 7139 list_for_each_entry(kvm, &vm_list, vm_list) { 7140 kvm_for_each_vcpu(i, vcpu, kvm) { 7141 if (vcpu->cpu != cpu) 7142 continue; 7143 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7144 if (vcpu->cpu != raw_smp_processor_id()) 7145 send_ipi = 1; 7146 } 7147 } 7148 mutex_unlock(&kvm_lock); 7149 7150 if (freq->old < freq->new && send_ipi) { 7151 /* 7152 * We upscale the frequency. Must make the guest 7153 * doesn't see old kvmclock values while running with 7154 * the new frequency, otherwise we risk the guest sees 7155 * time go backwards. 7156 * 7157 * In case we update the frequency for another cpu 7158 * (which might be in guest context) send an interrupt 7159 * to kick the cpu out of guest context. Next time 7160 * guest context is entered kvmclock will be updated, 7161 * so the guest will not see stale values. 7162 */ 7163 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 7164 } 7165 } 7166 7167 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 7168 void *data) 7169 { 7170 struct cpufreq_freqs *freq = data; 7171 int cpu; 7172 7173 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 7174 return 0; 7175 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 7176 return 0; 7177 7178 for_each_cpu(cpu, freq->policy->cpus) 7179 __kvmclock_cpufreq_notifier(freq, cpu); 7180 7181 return 0; 7182 } 7183 7184 static struct notifier_block kvmclock_cpufreq_notifier_block = { 7185 .notifier_call = kvmclock_cpufreq_notifier 7186 }; 7187 7188 static int kvmclock_cpu_online(unsigned int cpu) 7189 { 7190 tsc_khz_changed(NULL); 7191 return 0; 7192 } 7193 7194 static void kvm_timer_init(void) 7195 { 7196 max_tsc_khz = tsc_khz; 7197 7198 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 7199 #ifdef CONFIG_CPU_FREQ 7200 struct cpufreq_policy *policy; 7201 int cpu; 7202 7203 cpu = get_cpu(); 7204 policy = cpufreq_cpu_get(cpu); 7205 if (policy) { 7206 if (policy->cpuinfo.max_freq) 7207 max_tsc_khz = policy->cpuinfo.max_freq; 7208 cpufreq_cpu_put(policy); 7209 } 7210 put_cpu(); 7211 #endif 7212 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 7213 CPUFREQ_TRANSITION_NOTIFIER); 7214 } 7215 7216 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 7217 kvmclock_cpu_online, kvmclock_cpu_down_prep); 7218 } 7219 7220 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 7221 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); 7222 7223 int kvm_is_in_guest(void) 7224 { 7225 return __this_cpu_read(current_vcpu) != NULL; 7226 } 7227 7228 static int kvm_is_user_mode(void) 7229 { 7230 int user_mode = 3; 7231 7232 if (__this_cpu_read(current_vcpu)) 7233 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu)); 7234 7235 return user_mode != 0; 7236 } 7237 7238 static unsigned long kvm_get_guest_ip(void) 7239 { 7240 unsigned long ip = 0; 7241 7242 if (__this_cpu_read(current_vcpu)) 7243 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 7244 7245 return ip; 7246 } 7247 7248 static void kvm_handle_intel_pt_intr(void) 7249 { 7250 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); 7251 7252 kvm_make_request(KVM_REQ_PMI, vcpu); 7253 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, 7254 (unsigned long *)&vcpu->arch.pmu.global_status); 7255 } 7256 7257 static struct perf_guest_info_callbacks kvm_guest_cbs = { 7258 .is_in_guest = kvm_is_in_guest, 7259 .is_user_mode = kvm_is_user_mode, 7260 .get_guest_ip = kvm_get_guest_ip, 7261 .handle_intel_pt_intr = kvm_handle_intel_pt_intr, 7262 }; 7263 7264 #ifdef CONFIG_X86_64 7265 static void pvclock_gtod_update_fn(struct work_struct *work) 7266 { 7267 struct kvm *kvm; 7268 7269 struct kvm_vcpu *vcpu; 7270 int i; 7271 7272 mutex_lock(&kvm_lock); 7273 list_for_each_entry(kvm, &vm_list, vm_list) 7274 kvm_for_each_vcpu(i, vcpu, kvm) 7275 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7276 atomic_set(&kvm_guest_has_master_clock, 0); 7277 mutex_unlock(&kvm_lock); 7278 } 7279 7280 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 7281 7282 /* 7283 * Notification about pvclock gtod data update. 7284 */ 7285 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 7286 void *priv) 7287 { 7288 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 7289 struct timekeeper *tk = priv; 7290 7291 update_pvclock_gtod(tk); 7292 7293 /* disable master clock if host does not trust, or does not 7294 * use, TSC based clocksource. 7295 */ 7296 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 7297 atomic_read(&kvm_guest_has_master_clock) != 0) 7298 queue_work(system_long_wq, &pvclock_gtod_work); 7299 7300 return 0; 7301 } 7302 7303 static struct notifier_block pvclock_gtod_notifier = { 7304 .notifier_call = pvclock_gtod_notify, 7305 }; 7306 #endif 7307 7308 int kvm_arch_init(void *opaque) 7309 { 7310 struct kvm_x86_init_ops *ops = opaque; 7311 int r; 7312 7313 if (kvm_x86_ops.hardware_enable) { 7314 printk(KERN_ERR "kvm: already loaded the other module\n"); 7315 r = -EEXIST; 7316 goto out; 7317 } 7318 7319 if (!ops->cpu_has_kvm_support()) { 7320 pr_err_ratelimited("kvm: no hardware support\n"); 7321 r = -EOPNOTSUPP; 7322 goto out; 7323 } 7324 if (ops->disabled_by_bios()) { 7325 pr_err_ratelimited("kvm: disabled by bios\n"); 7326 r = -EOPNOTSUPP; 7327 goto out; 7328 } 7329 7330 /* 7331 * KVM explicitly assumes that the guest has an FPU and 7332 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 7333 * vCPU's FPU state as a fxregs_state struct. 7334 */ 7335 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 7336 printk(KERN_ERR "kvm: inadequate fpu\n"); 7337 r = -EOPNOTSUPP; 7338 goto out; 7339 } 7340 7341 r = -ENOMEM; 7342 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), 7343 __alignof__(struct fpu), SLAB_ACCOUNT, 7344 NULL); 7345 if (!x86_fpu_cache) { 7346 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); 7347 goto out; 7348 } 7349 7350 x86_emulator_cache = kvm_alloc_emulator_cache(); 7351 if (!x86_emulator_cache) { 7352 pr_err("kvm: failed to allocate cache for x86 emulator\n"); 7353 goto out_free_x86_fpu_cache; 7354 } 7355 7356 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 7357 if (!shared_msrs) { 7358 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 7359 goto out_free_x86_emulator_cache; 7360 } 7361 7362 r = kvm_mmu_module_init(); 7363 if (r) 7364 goto out_free_percpu; 7365 7366 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 7367 PT_DIRTY_MASK, PT64_NX_MASK, 0, 7368 PT_PRESENT_MASK, 0, sme_me_mask); 7369 kvm_timer_init(); 7370 7371 perf_register_guest_info_callbacks(&kvm_guest_cbs); 7372 7373 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 7374 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 7375 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; 7376 } 7377 7378 kvm_lapic_init(); 7379 if (pi_inject_timer == -1) 7380 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); 7381 #ifdef CONFIG_X86_64 7382 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 7383 7384 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 7385 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 7386 #endif 7387 7388 return 0; 7389 7390 out_free_percpu: 7391 free_percpu(shared_msrs); 7392 out_free_x86_emulator_cache: 7393 kmem_cache_destroy(x86_emulator_cache); 7394 out_free_x86_fpu_cache: 7395 kmem_cache_destroy(x86_fpu_cache); 7396 out: 7397 return r; 7398 } 7399 7400 void kvm_arch_exit(void) 7401 { 7402 #ifdef CONFIG_X86_64 7403 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 7404 clear_hv_tscchange_cb(); 7405 #endif 7406 kvm_lapic_exit(); 7407 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 7408 7409 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 7410 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 7411 CPUFREQ_TRANSITION_NOTIFIER); 7412 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 7413 #ifdef CONFIG_X86_64 7414 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 7415 #endif 7416 kvm_x86_ops.hardware_enable = NULL; 7417 kvm_mmu_module_exit(); 7418 free_percpu(shared_msrs); 7419 kmem_cache_destroy(x86_fpu_cache); 7420 } 7421 7422 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 7423 { 7424 ++vcpu->stat.halt_exits; 7425 if (lapic_in_kernel(vcpu)) { 7426 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 7427 return 1; 7428 } else { 7429 vcpu->run->exit_reason = KVM_EXIT_HLT; 7430 return 0; 7431 } 7432 } 7433 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 7434 7435 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 7436 { 7437 int ret = kvm_skip_emulated_instruction(vcpu); 7438 /* 7439 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 7440 * KVM_EXIT_DEBUG here. 7441 */ 7442 return kvm_vcpu_halt(vcpu) && ret; 7443 } 7444 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 7445 7446 #ifdef CONFIG_X86_64 7447 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 7448 unsigned long clock_type) 7449 { 7450 struct kvm_clock_pairing clock_pairing; 7451 struct timespec64 ts; 7452 u64 cycle; 7453 int ret; 7454 7455 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 7456 return -KVM_EOPNOTSUPP; 7457 7458 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) 7459 return -KVM_EOPNOTSUPP; 7460 7461 clock_pairing.sec = ts.tv_sec; 7462 clock_pairing.nsec = ts.tv_nsec; 7463 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 7464 clock_pairing.flags = 0; 7465 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 7466 7467 ret = 0; 7468 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 7469 sizeof(struct kvm_clock_pairing))) 7470 ret = -KVM_EFAULT; 7471 7472 return ret; 7473 } 7474 #endif 7475 7476 /* 7477 * kvm_pv_kick_cpu_op: Kick a vcpu. 7478 * 7479 * @apicid - apicid of vcpu to be kicked. 7480 */ 7481 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 7482 { 7483 struct kvm_lapic_irq lapic_irq; 7484 7485 lapic_irq.shorthand = APIC_DEST_NOSHORT; 7486 lapic_irq.dest_mode = APIC_DEST_PHYSICAL; 7487 lapic_irq.level = 0; 7488 lapic_irq.dest_id = apicid; 7489 lapic_irq.msi_redir_hint = false; 7490 7491 lapic_irq.delivery_mode = APIC_DM_REMRD; 7492 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 7493 } 7494 7495 bool kvm_apicv_activated(struct kvm *kvm) 7496 { 7497 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); 7498 } 7499 EXPORT_SYMBOL_GPL(kvm_apicv_activated); 7500 7501 void kvm_apicv_init(struct kvm *kvm, bool enable) 7502 { 7503 if (enable) 7504 clear_bit(APICV_INHIBIT_REASON_DISABLE, 7505 &kvm->arch.apicv_inhibit_reasons); 7506 else 7507 set_bit(APICV_INHIBIT_REASON_DISABLE, 7508 &kvm->arch.apicv_inhibit_reasons); 7509 } 7510 EXPORT_SYMBOL_GPL(kvm_apicv_init); 7511 7512 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id) 7513 { 7514 struct kvm_vcpu *target = NULL; 7515 struct kvm_apic_map *map; 7516 7517 rcu_read_lock(); 7518 map = rcu_dereference(kvm->arch.apic_map); 7519 7520 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 7521 target = map->phys_map[dest_id]->vcpu; 7522 7523 rcu_read_unlock(); 7524 7525 if (target && READ_ONCE(target->ready)) 7526 kvm_vcpu_yield_to(target); 7527 } 7528 7529 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 7530 { 7531 unsigned long nr, a0, a1, a2, a3, ret; 7532 int op_64_bit; 7533 7534 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 7535 return kvm_hv_hypercall(vcpu); 7536 7537 nr = kvm_rax_read(vcpu); 7538 a0 = kvm_rbx_read(vcpu); 7539 a1 = kvm_rcx_read(vcpu); 7540 a2 = kvm_rdx_read(vcpu); 7541 a3 = kvm_rsi_read(vcpu); 7542 7543 trace_kvm_hypercall(nr, a0, a1, a2, a3); 7544 7545 op_64_bit = is_64_bit_mode(vcpu); 7546 if (!op_64_bit) { 7547 nr &= 0xFFFFFFFF; 7548 a0 &= 0xFFFFFFFF; 7549 a1 &= 0xFFFFFFFF; 7550 a2 &= 0xFFFFFFFF; 7551 a3 &= 0xFFFFFFFF; 7552 } 7553 7554 if (kvm_x86_ops.get_cpl(vcpu) != 0) { 7555 ret = -KVM_EPERM; 7556 goto out; 7557 } 7558 7559 switch (nr) { 7560 case KVM_HC_VAPIC_POLL_IRQ: 7561 ret = 0; 7562 break; 7563 case KVM_HC_KICK_CPU: 7564 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 7565 kvm_sched_yield(vcpu->kvm, a1); 7566 ret = 0; 7567 break; 7568 #ifdef CONFIG_X86_64 7569 case KVM_HC_CLOCK_PAIRING: 7570 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 7571 break; 7572 #endif 7573 case KVM_HC_SEND_IPI: 7574 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 7575 break; 7576 case KVM_HC_SCHED_YIELD: 7577 kvm_sched_yield(vcpu->kvm, a0); 7578 ret = 0; 7579 break; 7580 default: 7581 ret = -KVM_ENOSYS; 7582 break; 7583 } 7584 out: 7585 if (!op_64_bit) 7586 ret = (u32)ret; 7587 kvm_rax_write(vcpu, ret); 7588 7589 ++vcpu->stat.hypercalls; 7590 return kvm_skip_emulated_instruction(vcpu); 7591 } 7592 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 7593 7594 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 7595 { 7596 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7597 char instruction[3]; 7598 unsigned long rip = kvm_rip_read(vcpu); 7599 7600 kvm_x86_ops.patch_hypercall(vcpu, instruction); 7601 7602 return emulator_write_emulated(ctxt, rip, instruction, 3, 7603 &ctxt->exception); 7604 } 7605 7606 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 7607 { 7608 return vcpu->run->request_interrupt_window && 7609 likely(!pic_in_kernel(vcpu->kvm)); 7610 } 7611 7612 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 7613 { 7614 struct kvm_run *kvm_run = vcpu->run; 7615 7616 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 7617 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 7618 kvm_run->cr8 = kvm_get_cr8(vcpu); 7619 kvm_run->apic_base = kvm_get_apic_base(vcpu); 7620 kvm_run->ready_for_interrupt_injection = 7621 pic_in_kernel(vcpu->kvm) || 7622 kvm_vcpu_ready_for_interrupt_injection(vcpu); 7623 } 7624 7625 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 7626 { 7627 int max_irr, tpr; 7628 7629 if (!kvm_x86_ops.update_cr8_intercept) 7630 return; 7631 7632 if (!lapic_in_kernel(vcpu)) 7633 return; 7634 7635 if (vcpu->arch.apicv_active) 7636 return; 7637 7638 if (!vcpu->arch.apic->vapic_addr) 7639 max_irr = kvm_lapic_find_highest_irr(vcpu); 7640 else 7641 max_irr = -1; 7642 7643 if (max_irr != -1) 7644 max_irr >>= 4; 7645 7646 tpr = kvm_lapic_get_cr8(vcpu); 7647 7648 kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr); 7649 } 7650 7651 static int inject_pending_event(struct kvm_vcpu *vcpu) 7652 { 7653 int r; 7654 7655 /* try to reinject previous events if any */ 7656 7657 if (vcpu->arch.exception.injected) 7658 kvm_x86_ops.queue_exception(vcpu); 7659 /* 7660 * Do not inject an NMI or interrupt if there is a pending 7661 * exception. Exceptions and interrupts are recognized at 7662 * instruction boundaries, i.e. the start of an instruction. 7663 * Trap-like exceptions, e.g. #DB, have higher priority than 7664 * NMIs and interrupts, i.e. traps are recognized before an 7665 * NMI/interrupt that's pending on the same instruction. 7666 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 7667 * priority, but are only generated (pended) during instruction 7668 * execution, i.e. a pending fault-like exception means the 7669 * fault occurred on the *previous* instruction and must be 7670 * serviced prior to recognizing any new events in order to 7671 * fully complete the previous instruction. 7672 */ 7673 else if (!vcpu->arch.exception.pending) { 7674 if (vcpu->arch.nmi_injected) 7675 kvm_x86_ops.set_nmi(vcpu); 7676 else if (vcpu->arch.interrupt.injected) 7677 kvm_x86_ops.set_irq(vcpu); 7678 } 7679 7680 /* 7681 * Call check_nested_events() even if we reinjected a previous event 7682 * in order for caller to determine if it should require immediate-exit 7683 * from L2 to L1 due to pending L1 events which require exit 7684 * from L2 to L1. 7685 */ 7686 if (is_guest_mode(vcpu) && kvm_x86_ops.check_nested_events) { 7687 r = kvm_x86_ops.check_nested_events(vcpu); 7688 if (r != 0) 7689 return r; 7690 } 7691 7692 /* try to inject new event if pending */ 7693 if (vcpu->arch.exception.pending) { 7694 trace_kvm_inj_exception(vcpu->arch.exception.nr, 7695 vcpu->arch.exception.has_error_code, 7696 vcpu->arch.exception.error_code); 7697 7698 WARN_ON_ONCE(vcpu->arch.exception.injected); 7699 vcpu->arch.exception.pending = false; 7700 vcpu->arch.exception.injected = true; 7701 7702 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 7703 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 7704 X86_EFLAGS_RF); 7705 7706 if (vcpu->arch.exception.nr == DB_VECTOR) { 7707 /* 7708 * This code assumes that nSVM doesn't use 7709 * check_nested_events(). If it does, the 7710 * DR6/DR7 changes should happen before L1 7711 * gets a #VMEXIT for an intercepted #DB in 7712 * L2. (Under VMX, on the other hand, the 7713 * DR6/DR7 changes should not happen in the 7714 * event of a VM-exit to L1 for an intercepted 7715 * #DB in L2.) 7716 */ 7717 kvm_deliver_exception_payload(vcpu); 7718 if (vcpu->arch.dr7 & DR7_GD) { 7719 vcpu->arch.dr7 &= ~DR7_GD; 7720 kvm_update_dr7(vcpu); 7721 } 7722 } 7723 7724 kvm_x86_ops.queue_exception(vcpu); 7725 } 7726 7727 /* Don't consider new event if we re-injected an event */ 7728 if (kvm_event_needs_reinjection(vcpu)) 7729 return 0; 7730 7731 if (vcpu->arch.smi_pending && !is_smm(vcpu) && 7732 kvm_x86_ops.smi_allowed(vcpu)) { 7733 vcpu->arch.smi_pending = false; 7734 ++vcpu->arch.smi_count; 7735 enter_smm(vcpu); 7736 } else if (vcpu->arch.nmi_pending && kvm_x86_ops.nmi_allowed(vcpu)) { 7737 --vcpu->arch.nmi_pending; 7738 vcpu->arch.nmi_injected = true; 7739 kvm_x86_ops.set_nmi(vcpu); 7740 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 7741 /* 7742 * Because interrupts can be injected asynchronously, we are 7743 * calling check_nested_events again here to avoid a race condition. 7744 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 7745 * proposal and current concerns. Perhaps we should be setting 7746 * KVM_REQ_EVENT only on certain events and not unconditionally? 7747 */ 7748 if (is_guest_mode(vcpu) && kvm_x86_ops.check_nested_events) { 7749 r = kvm_x86_ops.check_nested_events(vcpu); 7750 if (r != 0) 7751 return r; 7752 } 7753 if (kvm_x86_ops.interrupt_allowed(vcpu)) { 7754 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 7755 false); 7756 kvm_x86_ops.set_irq(vcpu); 7757 } 7758 } 7759 7760 return 0; 7761 } 7762 7763 static void process_nmi(struct kvm_vcpu *vcpu) 7764 { 7765 unsigned limit = 2; 7766 7767 /* 7768 * x86 is limited to one NMI running, and one NMI pending after it. 7769 * If an NMI is already in progress, limit further NMIs to just one. 7770 * Otherwise, allow two (and we'll inject the first one immediately). 7771 */ 7772 if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 7773 limit = 1; 7774 7775 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 7776 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 7777 kvm_make_request(KVM_REQ_EVENT, vcpu); 7778 } 7779 7780 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 7781 { 7782 u32 flags = 0; 7783 flags |= seg->g << 23; 7784 flags |= seg->db << 22; 7785 flags |= seg->l << 21; 7786 flags |= seg->avl << 20; 7787 flags |= seg->present << 15; 7788 flags |= seg->dpl << 13; 7789 flags |= seg->s << 12; 7790 flags |= seg->type << 8; 7791 return flags; 7792 } 7793 7794 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 7795 { 7796 struct kvm_segment seg; 7797 int offset; 7798 7799 kvm_get_segment(vcpu, &seg, n); 7800 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 7801 7802 if (n < 3) 7803 offset = 0x7f84 + n * 12; 7804 else 7805 offset = 0x7f2c + (n - 3) * 12; 7806 7807 put_smstate(u32, buf, offset + 8, seg.base); 7808 put_smstate(u32, buf, offset + 4, seg.limit); 7809 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 7810 } 7811 7812 #ifdef CONFIG_X86_64 7813 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 7814 { 7815 struct kvm_segment seg; 7816 int offset; 7817 u16 flags; 7818 7819 kvm_get_segment(vcpu, &seg, n); 7820 offset = 0x7e00 + n * 16; 7821 7822 flags = enter_smm_get_segment_flags(&seg) >> 8; 7823 put_smstate(u16, buf, offset, seg.selector); 7824 put_smstate(u16, buf, offset + 2, flags); 7825 put_smstate(u32, buf, offset + 4, seg.limit); 7826 put_smstate(u64, buf, offset + 8, seg.base); 7827 } 7828 #endif 7829 7830 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 7831 { 7832 struct desc_ptr dt; 7833 struct kvm_segment seg; 7834 unsigned long val; 7835 int i; 7836 7837 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 7838 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 7839 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 7840 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 7841 7842 for (i = 0; i < 8; i++) 7843 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 7844 7845 kvm_get_dr(vcpu, 6, &val); 7846 put_smstate(u32, buf, 0x7fcc, (u32)val); 7847 kvm_get_dr(vcpu, 7, &val); 7848 put_smstate(u32, buf, 0x7fc8, (u32)val); 7849 7850 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 7851 put_smstate(u32, buf, 0x7fc4, seg.selector); 7852 put_smstate(u32, buf, 0x7f64, seg.base); 7853 put_smstate(u32, buf, 0x7f60, seg.limit); 7854 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 7855 7856 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 7857 put_smstate(u32, buf, 0x7fc0, seg.selector); 7858 put_smstate(u32, buf, 0x7f80, seg.base); 7859 put_smstate(u32, buf, 0x7f7c, seg.limit); 7860 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 7861 7862 kvm_x86_ops.get_gdt(vcpu, &dt); 7863 put_smstate(u32, buf, 0x7f74, dt.address); 7864 put_smstate(u32, buf, 0x7f70, dt.size); 7865 7866 kvm_x86_ops.get_idt(vcpu, &dt); 7867 put_smstate(u32, buf, 0x7f58, dt.address); 7868 put_smstate(u32, buf, 0x7f54, dt.size); 7869 7870 for (i = 0; i < 6; i++) 7871 enter_smm_save_seg_32(vcpu, buf, i); 7872 7873 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 7874 7875 /* revision id */ 7876 put_smstate(u32, buf, 0x7efc, 0x00020000); 7877 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 7878 } 7879 7880 #ifdef CONFIG_X86_64 7881 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 7882 { 7883 struct desc_ptr dt; 7884 struct kvm_segment seg; 7885 unsigned long val; 7886 int i; 7887 7888 for (i = 0; i < 16; i++) 7889 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 7890 7891 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 7892 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 7893 7894 kvm_get_dr(vcpu, 6, &val); 7895 put_smstate(u64, buf, 0x7f68, val); 7896 kvm_get_dr(vcpu, 7, &val); 7897 put_smstate(u64, buf, 0x7f60, val); 7898 7899 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 7900 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 7901 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 7902 7903 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 7904 7905 /* revision id */ 7906 put_smstate(u32, buf, 0x7efc, 0x00020064); 7907 7908 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 7909 7910 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 7911 put_smstate(u16, buf, 0x7e90, seg.selector); 7912 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 7913 put_smstate(u32, buf, 0x7e94, seg.limit); 7914 put_smstate(u64, buf, 0x7e98, seg.base); 7915 7916 kvm_x86_ops.get_idt(vcpu, &dt); 7917 put_smstate(u32, buf, 0x7e84, dt.size); 7918 put_smstate(u64, buf, 0x7e88, dt.address); 7919 7920 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 7921 put_smstate(u16, buf, 0x7e70, seg.selector); 7922 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 7923 put_smstate(u32, buf, 0x7e74, seg.limit); 7924 put_smstate(u64, buf, 0x7e78, seg.base); 7925 7926 kvm_x86_ops.get_gdt(vcpu, &dt); 7927 put_smstate(u32, buf, 0x7e64, dt.size); 7928 put_smstate(u64, buf, 0x7e68, dt.address); 7929 7930 for (i = 0; i < 6; i++) 7931 enter_smm_save_seg_64(vcpu, buf, i); 7932 } 7933 #endif 7934 7935 static void enter_smm(struct kvm_vcpu *vcpu) 7936 { 7937 struct kvm_segment cs, ds; 7938 struct desc_ptr dt; 7939 char buf[512]; 7940 u32 cr0; 7941 7942 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 7943 memset(buf, 0, 512); 7944 #ifdef CONFIG_X86_64 7945 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 7946 enter_smm_save_state_64(vcpu, buf); 7947 else 7948 #endif 7949 enter_smm_save_state_32(vcpu, buf); 7950 7951 /* 7952 * Give pre_enter_smm() a chance to make ISA-specific changes to the 7953 * vCPU state (e.g. leave guest mode) after we've saved the state into 7954 * the SMM state-save area. 7955 */ 7956 kvm_x86_ops.pre_enter_smm(vcpu, buf); 7957 7958 vcpu->arch.hflags |= HF_SMM_MASK; 7959 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 7960 7961 if (kvm_x86_ops.get_nmi_mask(vcpu)) 7962 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 7963 else 7964 kvm_x86_ops.set_nmi_mask(vcpu, true); 7965 7966 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 7967 kvm_rip_write(vcpu, 0x8000); 7968 7969 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 7970 kvm_x86_ops.set_cr0(vcpu, cr0); 7971 vcpu->arch.cr0 = cr0; 7972 7973 kvm_x86_ops.set_cr4(vcpu, 0); 7974 7975 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 7976 dt.address = dt.size = 0; 7977 kvm_x86_ops.set_idt(vcpu, &dt); 7978 7979 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 7980 7981 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 7982 cs.base = vcpu->arch.smbase; 7983 7984 ds.selector = 0; 7985 ds.base = 0; 7986 7987 cs.limit = ds.limit = 0xffffffff; 7988 cs.type = ds.type = 0x3; 7989 cs.dpl = ds.dpl = 0; 7990 cs.db = ds.db = 0; 7991 cs.s = ds.s = 1; 7992 cs.l = ds.l = 0; 7993 cs.g = ds.g = 1; 7994 cs.avl = ds.avl = 0; 7995 cs.present = ds.present = 1; 7996 cs.unusable = ds.unusable = 0; 7997 cs.padding = ds.padding = 0; 7998 7999 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 8000 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 8001 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 8002 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 8003 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 8004 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 8005 8006 #ifdef CONFIG_X86_64 8007 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 8008 kvm_x86_ops.set_efer(vcpu, 0); 8009 #endif 8010 8011 kvm_update_cpuid(vcpu); 8012 kvm_mmu_reset_context(vcpu); 8013 } 8014 8015 static void process_smi(struct kvm_vcpu *vcpu) 8016 { 8017 vcpu->arch.smi_pending = true; 8018 kvm_make_request(KVM_REQ_EVENT, vcpu); 8019 } 8020 8021 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 8022 unsigned long *vcpu_bitmap) 8023 { 8024 cpumask_var_t cpus; 8025 8026 zalloc_cpumask_var(&cpus, GFP_ATOMIC); 8027 8028 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, 8029 vcpu_bitmap, cpus); 8030 8031 free_cpumask_var(cpus); 8032 } 8033 8034 void kvm_make_scan_ioapic_request(struct kvm *kvm) 8035 { 8036 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 8037 } 8038 8039 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 8040 { 8041 if (!lapic_in_kernel(vcpu)) 8042 return; 8043 8044 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm); 8045 kvm_apic_update_apicv(vcpu); 8046 kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu); 8047 } 8048 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); 8049 8050 /* 8051 * NOTE: Do not hold any lock prior to calling this. 8052 * 8053 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be 8054 * locked, because it calls __x86_set_memory_region() which does 8055 * synchronize_srcu(&kvm->srcu). 8056 */ 8057 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) 8058 { 8059 unsigned long old, new, expected; 8060 8061 if (!kvm_x86_ops.check_apicv_inhibit_reasons || 8062 !kvm_x86_ops.check_apicv_inhibit_reasons(bit)) 8063 return; 8064 8065 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons); 8066 do { 8067 expected = new = old; 8068 if (activate) 8069 __clear_bit(bit, &new); 8070 else 8071 __set_bit(bit, &new); 8072 if (new == old) 8073 break; 8074 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new); 8075 } while (old != expected); 8076 8077 if (!!old == !!new) 8078 return; 8079 8080 trace_kvm_apicv_update_request(activate, bit); 8081 if (kvm_x86_ops.pre_update_apicv_exec_ctrl) 8082 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate); 8083 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); 8084 } 8085 EXPORT_SYMBOL_GPL(kvm_request_apicv_update); 8086 8087 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 8088 { 8089 if (!kvm_apic_present(vcpu)) 8090 return; 8091 8092 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 8093 8094 if (irqchip_split(vcpu->kvm)) 8095 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 8096 else { 8097 if (vcpu->arch.apicv_active) 8098 kvm_x86_ops.sync_pir_to_irr(vcpu); 8099 if (ioapic_in_kernel(vcpu->kvm)) 8100 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 8101 } 8102 8103 if (is_guest_mode(vcpu)) 8104 vcpu->arch.load_eoi_exitmap_pending = true; 8105 else 8106 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 8107 } 8108 8109 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 8110 { 8111 u64 eoi_exit_bitmap[4]; 8112 8113 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 8114 return; 8115 8116 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, 8117 vcpu_to_synic(vcpu)->vec_bitmap, 256); 8118 kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap); 8119 } 8120 8121 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 8122 unsigned long start, unsigned long end, 8123 bool blockable) 8124 { 8125 unsigned long apic_address; 8126 8127 /* 8128 * The physical address of apic access page is stored in the VMCS. 8129 * Update it when it becomes invalid. 8130 */ 8131 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 8132 if (start <= apic_address && apic_address < end) 8133 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 8134 8135 return 0; 8136 } 8137 8138 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 8139 { 8140 struct page *page = NULL; 8141 8142 if (!lapic_in_kernel(vcpu)) 8143 return; 8144 8145 if (!kvm_x86_ops.set_apic_access_page_addr) 8146 return; 8147 8148 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 8149 if (is_error_page(page)) 8150 return; 8151 kvm_x86_ops.set_apic_access_page_addr(vcpu, page_to_phys(page)); 8152 8153 /* 8154 * Do not pin apic access page in memory, the MMU notifier 8155 * will call us again if it is migrated or swapped out. 8156 */ 8157 put_page(page); 8158 } 8159 8160 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 8161 { 8162 smp_send_reschedule(vcpu->cpu); 8163 } 8164 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 8165 8166 /* 8167 * Returns 1 to let vcpu_run() continue the guest execution loop without 8168 * exiting to the userspace. Otherwise, the value will be returned to the 8169 * userspace. 8170 */ 8171 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 8172 { 8173 int r; 8174 bool req_int_win = 8175 dm_request_for_irq_injection(vcpu) && 8176 kvm_cpu_accept_dm_intr(vcpu); 8177 enum exit_fastpath_completion exit_fastpath = EXIT_FASTPATH_NONE; 8178 8179 bool req_immediate_exit = false; 8180 8181 if (kvm_request_pending(vcpu)) { 8182 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) { 8183 if (unlikely(!kvm_x86_ops.get_vmcs12_pages(vcpu))) { 8184 r = 0; 8185 goto out; 8186 } 8187 } 8188 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 8189 kvm_mmu_unload(vcpu); 8190 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 8191 __kvm_migrate_timers(vcpu); 8192 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 8193 kvm_gen_update_masterclock(vcpu->kvm); 8194 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 8195 kvm_gen_kvmclock_update(vcpu); 8196 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 8197 r = kvm_guest_time_update(vcpu); 8198 if (unlikely(r)) 8199 goto out; 8200 } 8201 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 8202 kvm_mmu_sync_roots(vcpu); 8203 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) 8204 kvm_mmu_load_pgd(vcpu); 8205 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 8206 kvm_vcpu_flush_tlb(vcpu, true); 8207 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 8208 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 8209 r = 0; 8210 goto out; 8211 } 8212 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 8213 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 8214 vcpu->mmio_needed = 0; 8215 r = 0; 8216 goto out; 8217 } 8218 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 8219 /* Page is swapped out. Do synthetic halt */ 8220 vcpu->arch.apf.halted = true; 8221 r = 1; 8222 goto out; 8223 } 8224 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 8225 record_steal_time(vcpu); 8226 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 8227 process_smi(vcpu); 8228 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 8229 process_nmi(vcpu); 8230 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 8231 kvm_pmu_handle_event(vcpu); 8232 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 8233 kvm_pmu_deliver_pmi(vcpu); 8234 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 8235 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 8236 if (test_bit(vcpu->arch.pending_ioapic_eoi, 8237 vcpu->arch.ioapic_handled_vectors)) { 8238 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 8239 vcpu->run->eoi.vector = 8240 vcpu->arch.pending_ioapic_eoi; 8241 r = 0; 8242 goto out; 8243 } 8244 } 8245 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 8246 vcpu_scan_ioapic(vcpu); 8247 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 8248 vcpu_load_eoi_exitmap(vcpu); 8249 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 8250 kvm_vcpu_reload_apic_access_page(vcpu); 8251 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 8252 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 8253 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 8254 r = 0; 8255 goto out; 8256 } 8257 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 8258 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 8259 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 8260 r = 0; 8261 goto out; 8262 } 8263 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 8264 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 8265 vcpu->run->hyperv = vcpu->arch.hyperv.exit; 8266 r = 0; 8267 goto out; 8268 } 8269 8270 /* 8271 * KVM_REQ_HV_STIMER has to be processed after 8272 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 8273 * depend on the guest clock being up-to-date 8274 */ 8275 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 8276 kvm_hv_process_stimers(vcpu); 8277 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 8278 kvm_vcpu_update_apicv(vcpu); 8279 } 8280 8281 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 8282 ++vcpu->stat.req_event; 8283 kvm_apic_accept_events(vcpu); 8284 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 8285 r = 1; 8286 goto out; 8287 } 8288 8289 if (inject_pending_event(vcpu) != 0) 8290 req_immediate_exit = true; 8291 else { 8292 /* Enable SMI/NMI/IRQ window open exits if needed. 8293 * 8294 * SMIs have three cases: 8295 * 1) They can be nested, and then there is nothing to 8296 * do here because RSM will cause a vmexit anyway. 8297 * 2) There is an ISA-specific reason why SMI cannot be 8298 * injected, and the moment when this changes can be 8299 * intercepted. 8300 * 3) Or the SMI can be pending because 8301 * inject_pending_event has completed the injection 8302 * of an IRQ or NMI from the previous vmexit, and 8303 * then we request an immediate exit to inject the 8304 * SMI. 8305 */ 8306 if (vcpu->arch.smi_pending && !is_smm(vcpu)) 8307 if (!kvm_x86_ops.enable_smi_window(vcpu)) 8308 req_immediate_exit = true; 8309 if (vcpu->arch.nmi_pending) 8310 kvm_x86_ops.enable_nmi_window(vcpu); 8311 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 8312 kvm_x86_ops.enable_irq_window(vcpu); 8313 WARN_ON(vcpu->arch.exception.pending); 8314 } 8315 8316 if (kvm_lapic_enabled(vcpu)) { 8317 update_cr8_intercept(vcpu); 8318 kvm_lapic_sync_to_vapic(vcpu); 8319 } 8320 } 8321 8322 r = kvm_mmu_reload(vcpu); 8323 if (unlikely(r)) { 8324 goto cancel_injection; 8325 } 8326 8327 preempt_disable(); 8328 8329 kvm_x86_ops.prepare_guest_switch(vcpu); 8330 8331 /* 8332 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 8333 * IPI are then delayed after guest entry, which ensures that they 8334 * result in virtual interrupt delivery. 8335 */ 8336 local_irq_disable(); 8337 vcpu->mode = IN_GUEST_MODE; 8338 8339 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 8340 8341 /* 8342 * 1) We should set ->mode before checking ->requests. Please see 8343 * the comment in kvm_vcpu_exiting_guest_mode(). 8344 * 8345 * 2) For APICv, we should set ->mode before checking PID.ON. This 8346 * pairs with the memory barrier implicit in pi_test_and_set_on 8347 * (see vmx_deliver_posted_interrupt). 8348 * 8349 * 3) This also orders the write to mode from any reads to the page 8350 * tables done while the VCPU is running. Please see the comment 8351 * in kvm_flush_remote_tlbs. 8352 */ 8353 smp_mb__after_srcu_read_unlock(); 8354 8355 /* 8356 * This handles the case where a posted interrupt was 8357 * notified with kvm_vcpu_kick. 8358 */ 8359 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) 8360 kvm_x86_ops.sync_pir_to_irr(vcpu); 8361 8362 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) 8363 || need_resched() || signal_pending(current)) { 8364 vcpu->mode = OUTSIDE_GUEST_MODE; 8365 smp_wmb(); 8366 local_irq_enable(); 8367 preempt_enable(); 8368 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 8369 r = 1; 8370 goto cancel_injection; 8371 } 8372 8373 if (req_immediate_exit) { 8374 kvm_make_request(KVM_REQ_EVENT, vcpu); 8375 kvm_x86_ops.request_immediate_exit(vcpu); 8376 } 8377 8378 trace_kvm_entry(vcpu->vcpu_id); 8379 guest_enter_irqoff(); 8380 8381 fpregs_assert_state_consistent(); 8382 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 8383 switch_fpu_return(); 8384 8385 if (unlikely(vcpu->arch.switch_db_regs)) { 8386 set_debugreg(0, 7); 8387 set_debugreg(vcpu->arch.eff_db[0], 0); 8388 set_debugreg(vcpu->arch.eff_db[1], 1); 8389 set_debugreg(vcpu->arch.eff_db[2], 2); 8390 set_debugreg(vcpu->arch.eff_db[3], 3); 8391 set_debugreg(vcpu->arch.dr6, 6); 8392 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 8393 } 8394 8395 kvm_x86_ops.run(vcpu); 8396 8397 /* 8398 * Do this here before restoring debug registers on the host. And 8399 * since we do this before handling the vmexit, a DR access vmexit 8400 * can (a) read the correct value of the debug registers, (b) set 8401 * KVM_DEBUGREG_WONT_EXIT again. 8402 */ 8403 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 8404 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 8405 kvm_x86_ops.sync_dirty_debug_regs(vcpu); 8406 kvm_update_dr0123(vcpu); 8407 kvm_update_dr6(vcpu); 8408 kvm_update_dr7(vcpu); 8409 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 8410 } 8411 8412 /* 8413 * If the guest has used debug registers, at least dr7 8414 * will be disabled while returning to the host. 8415 * If we don't have active breakpoints in the host, we don't 8416 * care about the messed up debug address registers. But if 8417 * we have some of them active, restore the old state. 8418 */ 8419 if (hw_breakpoint_active()) 8420 hw_breakpoint_restore(); 8421 8422 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 8423 8424 vcpu->mode = OUTSIDE_GUEST_MODE; 8425 smp_wmb(); 8426 8427 kvm_x86_ops.handle_exit_irqoff(vcpu, &exit_fastpath); 8428 8429 /* 8430 * Consume any pending interrupts, including the possible source of 8431 * VM-Exit on SVM and any ticks that occur between VM-Exit and now. 8432 * An instruction is required after local_irq_enable() to fully unblock 8433 * interrupts on processors that implement an interrupt shadow, the 8434 * stat.exits increment will do nicely. 8435 */ 8436 kvm_before_interrupt(vcpu); 8437 local_irq_enable(); 8438 ++vcpu->stat.exits; 8439 local_irq_disable(); 8440 kvm_after_interrupt(vcpu); 8441 8442 guest_exit_irqoff(); 8443 if (lapic_in_kernel(vcpu)) { 8444 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; 8445 if (delta != S64_MIN) { 8446 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); 8447 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; 8448 } 8449 } 8450 8451 local_irq_enable(); 8452 preempt_enable(); 8453 8454 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 8455 8456 /* 8457 * Profile KVM exit RIPs: 8458 */ 8459 if (unlikely(prof_on == KVM_PROFILING)) { 8460 unsigned long rip = kvm_rip_read(vcpu); 8461 profile_hit(KVM_PROFILING, (void *)rip); 8462 } 8463 8464 if (unlikely(vcpu->arch.tsc_always_catchup)) 8465 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 8466 8467 if (vcpu->arch.apic_attention) 8468 kvm_lapic_sync_from_vapic(vcpu); 8469 8470 r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath); 8471 return r; 8472 8473 cancel_injection: 8474 kvm_x86_ops.cancel_injection(vcpu); 8475 if (unlikely(vcpu->arch.apic_attention)) 8476 kvm_lapic_sync_from_vapic(vcpu); 8477 out: 8478 return r; 8479 } 8480 8481 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 8482 { 8483 if (!kvm_arch_vcpu_runnable(vcpu) && 8484 (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) { 8485 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 8486 kvm_vcpu_block(vcpu); 8487 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 8488 8489 if (kvm_x86_ops.post_block) 8490 kvm_x86_ops.post_block(vcpu); 8491 8492 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 8493 return 1; 8494 } 8495 8496 kvm_apic_accept_events(vcpu); 8497 switch(vcpu->arch.mp_state) { 8498 case KVM_MP_STATE_HALTED: 8499 vcpu->arch.pv.pv_unhalted = false; 8500 vcpu->arch.mp_state = 8501 KVM_MP_STATE_RUNNABLE; 8502 /* fall through */ 8503 case KVM_MP_STATE_RUNNABLE: 8504 vcpu->arch.apf.halted = false; 8505 break; 8506 case KVM_MP_STATE_INIT_RECEIVED: 8507 break; 8508 default: 8509 return -EINTR; 8510 } 8511 return 1; 8512 } 8513 8514 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 8515 { 8516 if (is_guest_mode(vcpu) && kvm_x86_ops.check_nested_events) 8517 kvm_x86_ops.check_nested_events(vcpu); 8518 8519 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 8520 !vcpu->arch.apf.halted); 8521 } 8522 8523 static int vcpu_run(struct kvm_vcpu *vcpu) 8524 { 8525 int r; 8526 struct kvm *kvm = vcpu->kvm; 8527 8528 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 8529 vcpu->arch.l1tf_flush_l1d = true; 8530 8531 for (;;) { 8532 if (kvm_vcpu_running(vcpu)) { 8533 r = vcpu_enter_guest(vcpu); 8534 } else { 8535 r = vcpu_block(kvm, vcpu); 8536 } 8537 8538 if (r <= 0) 8539 break; 8540 8541 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); 8542 if (kvm_cpu_has_pending_timer(vcpu)) 8543 kvm_inject_pending_timer_irqs(vcpu); 8544 8545 if (dm_request_for_irq_injection(vcpu) && 8546 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 8547 r = 0; 8548 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 8549 ++vcpu->stat.request_irq_exits; 8550 break; 8551 } 8552 8553 kvm_check_async_pf_completion(vcpu); 8554 8555 if (signal_pending(current)) { 8556 r = -EINTR; 8557 vcpu->run->exit_reason = KVM_EXIT_INTR; 8558 ++vcpu->stat.signal_exits; 8559 break; 8560 } 8561 if (need_resched()) { 8562 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 8563 cond_resched(); 8564 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 8565 } 8566 } 8567 8568 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 8569 8570 return r; 8571 } 8572 8573 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 8574 { 8575 int r; 8576 8577 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 8578 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 8579 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 8580 return r; 8581 } 8582 8583 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 8584 { 8585 BUG_ON(!vcpu->arch.pio.count); 8586 8587 return complete_emulated_io(vcpu); 8588 } 8589 8590 /* 8591 * Implements the following, as a state machine: 8592 * 8593 * read: 8594 * for each fragment 8595 * for each mmio piece in the fragment 8596 * write gpa, len 8597 * exit 8598 * copy data 8599 * execute insn 8600 * 8601 * write: 8602 * for each fragment 8603 * for each mmio piece in the fragment 8604 * write gpa, len 8605 * copy data 8606 * exit 8607 */ 8608 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 8609 { 8610 struct kvm_run *run = vcpu->run; 8611 struct kvm_mmio_fragment *frag; 8612 unsigned len; 8613 8614 BUG_ON(!vcpu->mmio_needed); 8615 8616 /* Complete previous fragment */ 8617 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 8618 len = min(8u, frag->len); 8619 if (!vcpu->mmio_is_write) 8620 memcpy(frag->data, run->mmio.data, len); 8621 8622 if (frag->len <= 8) { 8623 /* Switch to the next fragment. */ 8624 frag++; 8625 vcpu->mmio_cur_fragment++; 8626 } else { 8627 /* Go forward to the next mmio piece. */ 8628 frag->data += len; 8629 frag->gpa += len; 8630 frag->len -= len; 8631 } 8632 8633 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 8634 vcpu->mmio_needed = 0; 8635 8636 /* FIXME: return into emulator if single-stepping. */ 8637 if (vcpu->mmio_is_write) 8638 return 1; 8639 vcpu->mmio_read_completed = 1; 8640 return complete_emulated_io(vcpu); 8641 } 8642 8643 run->exit_reason = KVM_EXIT_MMIO; 8644 run->mmio.phys_addr = frag->gpa; 8645 if (vcpu->mmio_is_write) 8646 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 8647 run->mmio.len = min(8u, frag->len); 8648 run->mmio.is_write = vcpu->mmio_is_write; 8649 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 8650 return 0; 8651 } 8652 8653 static void kvm_save_current_fpu(struct fpu *fpu) 8654 { 8655 /* 8656 * If the target FPU state is not resident in the CPU registers, just 8657 * memcpy() from current, else save CPU state directly to the target. 8658 */ 8659 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 8660 memcpy(&fpu->state, ¤t->thread.fpu.state, 8661 fpu_kernel_xstate_size); 8662 else 8663 copy_fpregs_to_fpstate(fpu); 8664 } 8665 8666 /* Swap (qemu) user FPU context for the guest FPU context. */ 8667 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 8668 { 8669 fpregs_lock(); 8670 8671 kvm_save_current_fpu(vcpu->arch.user_fpu); 8672 8673 /* PKRU is separately restored in kvm_x86_ops.run. */ 8674 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, 8675 ~XFEATURE_MASK_PKRU); 8676 8677 fpregs_mark_activate(); 8678 fpregs_unlock(); 8679 8680 trace_kvm_fpu(1); 8681 } 8682 8683 /* When vcpu_run ends, restore user space FPU context. */ 8684 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 8685 { 8686 fpregs_lock(); 8687 8688 kvm_save_current_fpu(vcpu->arch.guest_fpu); 8689 8690 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); 8691 8692 fpregs_mark_activate(); 8693 fpregs_unlock(); 8694 8695 ++vcpu->stat.fpu_reload; 8696 trace_kvm_fpu(0); 8697 } 8698 8699 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 8700 { 8701 int r; 8702 8703 vcpu_load(vcpu); 8704 kvm_sigset_activate(vcpu); 8705 kvm_load_guest_fpu(vcpu); 8706 8707 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 8708 if (kvm_run->immediate_exit) { 8709 r = -EINTR; 8710 goto out; 8711 } 8712 kvm_vcpu_block(vcpu); 8713 kvm_apic_accept_events(vcpu); 8714 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 8715 r = -EAGAIN; 8716 if (signal_pending(current)) { 8717 r = -EINTR; 8718 vcpu->run->exit_reason = KVM_EXIT_INTR; 8719 ++vcpu->stat.signal_exits; 8720 } 8721 goto out; 8722 } 8723 8724 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { 8725 r = -EINVAL; 8726 goto out; 8727 } 8728 8729 if (vcpu->run->kvm_dirty_regs) { 8730 r = sync_regs(vcpu); 8731 if (r != 0) 8732 goto out; 8733 } 8734 8735 /* re-sync apic's tpr */ 8736 if (!lapic_in_kernel(vcpu)) { 8737 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 8738 r = -EINVAL; 8739 goto out; 8740 } 8741 } 8742 8743 if (unlikely(vcpu->arch.complete_userspace_io)) { 8744 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 8745 vcpu->arch.complete_userspace_io = NULL; 8746 r = cui(vcpu); 8747 if (r <= 0) 8748 goto out; 8749 } else 8750 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 8751 8752 if (kvm_run->immediate_exit) 8753 r = -EINTR; 8754 else 8755 r = vcpu_run(vcpu); 8756 8757 out: 8758 kvm_put_guest_fpu(vcpu); 8759 if (vcpu->run->kvm_valid_regs) 8760 store_regs(vcpu); 8761 post_kvm_run_save(vcpu); 8762 kvm_sigset_deactivate(vcpu); 8763 8764 vcpu_put(vcpu); 8765 return r; 8766 } 8767 8768 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8769 { 8770 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 8771 /* 8772 * We are here if userspace calls get_regs() in the middle of 8773 * instruction emulation. Registers state needs to be copied 8774 * back from emulation context to vcpu. Userspace shouldn't do 8775 * that usually, but some bad designed PV devices (vmware 8776 * backdoor interface) need this to work 8777 */ 8778 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); 8779 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 8780 } 8781 regs->rax = kvm_rax_read(vcpu); 8782 regs->rbx = kvm_rbx_read(vcpu); 8783 regs->rcx = kvm_rcx_read(vcpu); 8784 regs->rdx = kvm_rdx_read(vcpu); 8785 regs->rsi = kvm_rsi_read(vcpu); 8786 regs->rdi = kvm_rdi_read(vcpu); 8787 regs->rsp = kvm_rsp_read(vcpu); 8788 regs->rbp = kvm_rbp_read(vcpu); 8789 #ifdef CONFIG_X86_64 8790 regs->r8 = kvm_r8_read(vcpu); 8791 regs->r9 = kvm_r9_read(vcpu); 8792 regs->r10 = kvm_r10_read(vcpu); 8793 regs->r11 = kvm_r11_read(vcpu); 8794 regs->r12 = kvm_r12_read(vcpu); 8795 regs->r13 = kvm_r13_read(vcpu); 8796 regs->r14 = kvm_r14_read(vcpu); 8797 regs->r15 = kvm_r15_read(vcpu); 8798 #endif 8799 8800 regs->rip = kvm_rip_read(vcpu); 8801 regs->rflags = kvm_get_rflags(vcpu); 8802 } 8803 8804 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8805 { 8806 vcpu_load(vcpu); 8807 __get_regs(vcpu, regs); 8808 vcpu_put(vcpu); 8809 return 0; 8810 } 8811 8812 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8813 { 8814 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 8815 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 8816 8817 kvm_rax_write(vcpu, regs->rax); 8818 kvm_rbx_write(vcpu, regs->rbx); 8819 kvm_rcx_write(vcpu, regs->rcx); 8820 kvm_rdx_write(vcpu, regs->rdx); 8821 kvm_rsi_write(vcpu, regs->rsi); 8822 kvm_rdi_write(vcpu, regs->rdi); 8823 kvm_rsp_write(vcpu, regs->rsp); 8824 kvm_rbp_write(vcpu, regs->rbp); 8825 #ifdef CONFIG_X86_64 8826 kvm_r8_write(vcpu, regs->r8); 8827 kvm_r9_write(vcpu, regs->r9); 8828 kvm_r10_write(vcpu, regs->r10); 8829 kvm_r11_write(vcpu, regs->r11); 8830 kvm_r12_write(vcpu, regs->r12); 8831 kvm_r13_write(vcpu, regs->r13); 8832 kvm_r14_write(vcpu, regs->r14); 8833 kvm_r15_write(vcpu, regs->r15); 8834 #endif 8835 8836 kvm_rip_write(vcpu, regs->rip); 8837 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 8838 8839 vcpu->arch.exception.pending = false; 8840 8841 kvm_make_request(KVM_REQ_EVENT, vcpu); 8842 } 8843 8844 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 8845 { 8846 vcpu_load(vcpu); 8847 __set_regs(vcpu, regs); 8848 vcpu_put(vcpu); 8849 return 0; 8850 } 8851 8852 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 8853 { 8854 struct kvm_segment cs; 8855 8856 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 8857 *db = cs.db; 8858 *l = cs.l; 8859 } 8860 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 8861 8862 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 8863 { 8864 struct desc_ptr dt; 8865 8866 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 8867 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 8868 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 8869 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 8870 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 8871 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 8872 8873 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 8874 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 8875 8876 kvm_x86_ops.get_idt(vcpu, &dt); 8877 sregs->idt.limit = dt.size; 8878 sregs->idt.base = dt.address; 8879 kvm_x86_ops.get_gdt(vcpu, &dt); 8880 sregs->gdt.limit = dt.size; 8881 sregs->gdt.base = dt.address; 8882 8883 sregs->cr0 = kvm_read_cr0(vcpu); 8884 sregs->cr2 = vcpu->arch.cr2; 8885 sregs->cr3 = kvm_read_cr3(vcpu); 8886 sregs->cr4 = kvm_read_cr4(vcpu); 8887 sregs->cr8 = kvm_get_cr8(vcpu); 8888 sregs->efer = vcpu->arch.efer; 8889 sregs->apic_base = kvm_get_apic_base(vcpu); 8890 8891 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); 8892 8893 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 8894 set_bit(vcpu->arch.interrupt.nr, 8895 (unsigned long *)sregs->interrupt_bitmap); 8896 } 8897 8898 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 8899 struct kvm_sregs *sregs) 8900 { 8901 vcpu_load(vcpu); 8902 __get_sregs(vcpu, sregs); 8903 vcpu_put(vcpu); 8904 return 0; 8905 } 8906 8907 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 8908 struct kvm_mp_state *mp_state) 8909 { 8910 vcpu_load(vcpu); 8911 if (kvm_mpx_supported()) 8912 kvm_load_guest_fpu(vcpu); 8913 8914 kvm_apic_accept_events(vcpu); 8915 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 8916 vcpu->arch.pv.pv_unhalted) 8917 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 8918 else 8919 mp_state->mp_state = vcpu->arch.mp_state; 8920 8921 if (kvm_mpx_supported()) 8922 kvm_put_guest_fpu(vcpu); 8923 vcpu_put(vcpu); 8924 return 0; 8925 } 8926 8927 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 8928 struct kvm_mp_state *mp_state) 8929 { 8930 int ret = -EINVAL; 8931 8932 vcpu_load(vcpu); 8933 8934 if (!lapic_in_kernel(vcpu) && 8935 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 8936 goto out; 8937 8938 /* 8939 * KVM_MP_STATE_INIT_RECEIVED means the processor is in 8940 * INIT state; latched init should be reported using 8941 * KVM_SET_VCPU_EVENTS, so reject it here. 8942 */ 8943 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && 8944 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 8945 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 8946 goto out; 8947 8948 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 8949 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 8950 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 8951 } else 8952 vcpu->arch.mp_state = mp_state->mp_state; 8953 kvm_make_request(KVM_REQ_EVENT, vcpu); 8954 8955 ret = 0; 8956 out: 8957 vcpu_put(vcpu); 8958 return ret; 8959 } 8960 8961 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 8962 int reason, bool has_error_code, u32 error_code) 8963 { 8964 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8965 int ret; 8966 8967 init_emulate_ctxt(vcpu); 8968 8969 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 8970 has_error_code, error_code); 8971 if (ret) { 8972 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 8973 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 8974 vcpu->run->internal.ndata = 0; 8975 return 0; 8976 } 8977 8978 kvm_rip_write(vcpu, ctxt->eip); 8979 kvm_set_rflags(vcpu, ctxt->eflags); 8980 return 1; 8981 } 8982 EXPORT_SYMBOL_GPL(kvm_task_switch); 8983 8984 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 8985 { 8986 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 8987 /* 8988 * When EFER.LME and CR0.PG are set, the processor is in 8989 * 64-bit mode (though maybe in a 32-bit code segment). 8990 * CR4.PAE and EFER.LMA must be set. 8991 */ 8992 if (!(sregs->cr4 & X86_CR4_PAE) 8993 || !(sregs->efer & EFER_LMA)) 8994 return -EINVAL; 8995 } else { 8996 /* 8997 * Not in 64-bit mode: EFER.LMA is clear and the code 8998 * segment cannot be 64-bit. 8999 */ 9000 if (sregs->efer & EFER_LMA || sregs->cs.l) 9001 return -EINVAL; 9002 } 9003 9004 return kvm_valid_cr4(vcpu, sregs->cr4); 9005 } 9006 9007 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 9008 { 9009 struct msr_data apic_base_msr; 9010 int mmu_reset_needed = 0; 9011 int cpuid_update_needed = 0; 9012 int pending_vec, max_bits, idx; 9013 struct desc_ptr dt; 9014 int ret = -EINVAL; 9015 9016 if (kvm_valid_sregs(vcpu, sregs)) 9017 goto out; 9018 9019 apic_base_msr.data = sregs->apic_base; 9020 apic_base_msr.host_initiated = true; 9021 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 9022 goto out; 9023 9024 dt.size = sregs->idt.limit; 9025 dt.address = sregs->idt.base; 9026 kvm_x86_ops.set_idt(vcpu, &dt); 9027 dt.size = sregs->gdt.limit; 9028 dt.address = sregs->gdt.base; 9029 kvm_x86_ops.set_gdt(vcpu, &dt); 9030 9031 vcpu->arch.cr2 = sregs->cr2; 9032 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 9033 vcpu->arch.cr3 = sregs->cr3; 9034 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 9035 9036 kvm_set_cr8(vcpu, sregs->cr8); 9037 9038 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 9039 kvm_x86_ops.set_efer(vcpu, sregs->efer); 9040 9041 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 9042 kvm_x86_ops.set_cr0(vcpu, sregs->cr0); 9043 vcpu->arch.cr0 = sregs->cr0; 9044 9045 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 9046 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) & 9047 (X86_CR4_OSXSAVE | X86_CR4_PKE)); 9048 kvm_x86_ops.set_cr4(vcpu, sregs->cr4); 9049 if (cpuid_update_needed) 9050 kvm_update_cpuid(vcpu); 9051 9052 idx = srcu_read_lock(&vcpu->kvm->srcu); 9053 if (is_pae_paging(vcpu)) { 9054 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 9055 mmu_reset_needed = 1; 9056 } 9057 srcu_read_unlock(&vcpu->kvm->srcu, idx); 9058 9059 if (mmu_reset_needed) 9060 kvm_mmu_reset_context(vcpu); 9061 9062 max_bits = KVM_NR_INTERRUPTS; 9063 pending_vec = find_first_bit( 9064 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 9065 if (pending_vec < max_bits) { 9066 kvm_queue_interrupt(vcpu, pending_vec, false); 9067 pr_debug("Set back pending irq %d\n", pending_vec); 9068 } 9069 9070 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 9071 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 9072 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 9073 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 9074 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 9075 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 9076 9077 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 9078 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 9079 9080 update_cr8_intercept(vcpu); 9081 9082 /* Older userspace won't unhalt the vcpu on reset. */ 9083 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 9084 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 9085 !is_protmode(vcpu)) 9086 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 9087 9088 kvm_make_request(KVM_REQ_EVENT, vcpu); 9089 9090 ret = 0; 9091 out: 9092 return ret; 9093 } 9094 9095 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 9096 struct kvm_sregs *sregs) 9097 { 9098 int ret; 9099 9100 vcpu_load(vcpu); 9101 ret = __set_sregs(vcpu, sregs); 9102 vcpu_put(vcpu); 9103 return ret; 9104 } 9105 9106 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 9107 struct kvm_guest_debug *dbg) 9108 { 9109 unsigned long rflags; 9110 int i, r; 9111 9112 vcpu_load(vcpu); 9113 9114 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 9115 r = -EBUSY; 9116 if (vcpu->arch.exception.pending) 9117 goto out; 9118 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 9119 kvm_queue_exception(vcpu, DB_VECTOR); 9120 else 9121 kvm_queue_exception(vcpu, BP_VECTOR); 9122 } 9123 9124 /* 9125 * Read rflags as long as potentially injected trace flags are still 9126 * filtered out. 9127 */ 9128 rflags = kvm_get_rflags(vcpu); 9129 9130 vcpu->guest_debug = dbg->control; 9131 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 9132 vcpu->guest_debug = 0; 9133 9134 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 9135 for (i = 0; i < KVM_NR_DB_REGS; ++i) 9136 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 9137 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 9138 } else { 9139 for (i = 0; i < KVM_NR_DB_REGS; i++) 9140 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 9141 } 9142 kvm_update_dr7(vcpu); 9143 9144 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 9145 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 9146 get_segment_base(vcpu, VCPU_SREG_CS); 9147 9148 /* 9149 * Trigger an rflags update that will inject or remove the trace 9150 * flags. 9151 */ 9152 kvm_set_rflags(vcpu, rflags); 9153 9154 kvm_x86_ops.update_bp_intercept(vcpu); 9155 9156 r = 0; 9157 9158 out: 9159 vcpu_put(vcpu); 9160 return r; 9161 } 9162 9163 /* 9164 * Translate a guest virtual address to a guest physical address. 9165 */ 9166 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 9167 struct kvm_translation *tr) 9168 { 9169 unsigned long vaddr = tr->linear_address; 9170 gpa_t gpa; 9171 int idx; 9172 9173 vcpu_load(vcpu); 9174 9175 idx = srcu_read_lock(&vcpu->kvm->srcu); 9176 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 9177 srcu_read_unlock(&vcpu->kvm->srcu, idx); 9178 tr->physical_address = gpa; 9179 tr->valid = gpa != UNMAPPED_GVA; 9180 tr->writeable = 1; 9181 tr->usermode = 0; 9182 9183 vcpu_put(vcpu); 9184 return 0; 9185 } 9186 9187 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 9188 { 9189 struct fxregs_state *fxsave; 9190 9191 vcpu_load(vcpu); 9192 9193 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 9194 memcpy(fpu->fpr, fxsave->st_space, 128); 9195 fpu->fcw = fxsave->cwd; 9196 fpu->fsw = fxsave->swd; 9197 fpu->ftwx = fxsave->twd; 9198 fpu->last_opcode = fxsave->fop; 9199 fpu->last_ip = fxsave->rip; 9200 fpu->last_dp = fxsave->rdp; 9201 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 9202 9203 vcpu_put(vcpu); 9204 return 0; 9205 } 9206 9207 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 9208 { 9209 struct fxregs_state *fxsave; 9210 9211 vcpu_load(vcpu); 9212 9213 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 9214 9215 memcpy(fxsave->st_space, fpu->fpr, 128); 9216 fxsave->cwd = fpu->fcw; 9217 fxsave->swd = fpu->fsw; 9218 fxsave->twd = fpu->ftwx; 9219 fxsave->fop = fpu->last_opcode; 9220 fxsave->rip = fpu->last_ip; 9221 fxsave->rdp = fpu->last_dp; 9222 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 9223 9224 vcpu_put(vcpu); 9225 return 0; 9226 } 9227 9228 static void store_regs(struct kvm_vcpu *vcpu) 9229 { 9230 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 9231 9232 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 9233 __get_regs(vcpu, &vcpu->run->s.regs.regs); 9234 9235 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 9236 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 9237 9238 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 9239 kvm_vcpu_ioctl_x86_get_vcpu_events( 9240 vcpu, &vcpu->run->s.regs.events); 9241 } 9242 9243 static int sync_regs(struct kvm_vcpu *vcpu) 9244 { 9245 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) 9246 return -EINVAL; 9247 9248 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 9249 __set_regs(vcpu, &vcpu->run->s.regs.regs); 9250 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 9251 } 9252 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 9253 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 9254 return -EINVAL; 9255 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 9256 } 9257 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 9258 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 9259 vcpu, &vcpu->run->s.regs.events)) 9260 return -EINVAL; 9261 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 9262 } 9263 9264 return 0; 9265 } 9266 9267 static void fx_init(struct kvm_vcpu *vcpu) 9268 { 9269 fpstate_init(&vcpu->arch.guest_fpu->state); 9270 if (boot_cpu_has(X86_FEATURE_XSAVES)) 9271 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = 9272 host_xcr0 | XSTATE_COMPACTION_ENABLED; 9273 9274 /* 9275 * Ensure guest xcr0 is valid for loading 9276 */ 9277 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 9278 9279 vcpu->arch.cr0 |= X86_CR0_ET; 9280 } 9281 9282 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 9283 { 9284 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 9285 pr_warn_once("kvm: SMP vm created on host with unstable TSC; " 9286 "guest TSC will not be reliable\n"); 9287 9288 return 0; 9289 } 9290 9291 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 9292 { 9293 struct page *page; 9294 int r; 9295 9296 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 9297 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 9298 else 9299 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 9300 9301 kvm_set_tsc_khz(vcpu, max_tsc_khz); 9302 9303 r = kvm_mmu_create(vcpu); 9304 if (r < 0) 9305 return r; 9306 9307 if (irqchip_in_kernel(vcpu->kvm)) { 9308 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 9309 if (r < 0) 9310 goto fail_mmu_destroy; 9311 if (kvm_apicv_activated(vcpu->kvm)) 9312 vcpu->arch.apicv_active = true; 9313 } else 9314 static_key_slow_inc(&kvm_no_apic_vcpu); 9315 9316 r = -ENOMEM; 9317 9318 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 9319 if (!page) 9320 goto fail_free_lapic; 9321 vcpu->arch.pio_data = page_address(page); 9322 9323 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 9324 GFP_KERNEL_ACCOUNT); 9325 if (!vcpu->arch.mce_banks) 9326 goto fail_free_pio_data; 9327 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 9328 9329 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 9330 GFP_KERNEL_ACCOUNT)) 9331 goto fail_free_mce_banks; 9332 9333 if (!alloc_emulate_ctxt(vcpu)) 9334 goto free_wbinvd_dirty_mask; 9335 9336 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, 9337 GFP_KERNEL_ACCOUNT); 9338 if (!vcpu->arch.user_fpu) { 9339 pr_err("kvm: failed to allocate userspace's fpu\n"); 9340 goto free_emulate_ctxt; 9341 } 9342 9343 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, 9344 GFP_KERNEL_ACCOUNT); 9345 if (!vcpu->arch.guest_fpu) { 9346 pr_err("kvm: failed to allocate vcpu's fpu\n"); 9347 goto free_user_fpu; 9348 } 9349 fx_init(vcpu); 9350 9351 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 9352 9353 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 9354 9355 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 9356 9357 kvm_async_pf_hash_reset(vcpu); 9358 kvm_pmu_init(vcpu); 9359 9360 vcpu->arch.pending_external_vector = -1; 9361 vcpu->arch.preempted_in_kernel = false; 9362 9363 kvm_hv_vcpu_init(vcpu); 9364 9365 r = kvm_x86_ops.vcpu_create(vcpu); 9366 if (r) 9367 goto free_guest_fpu; 9368 9369 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 9370 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 9371 kvm_vcpu_mtrr_init(vcpu); 9372 vcpu_load(vcpu); 9373 kvm_vcpu_reset(vcpu, false); 9374 kvm_init_mmu(vcpu, false); 9375 vcpu_put(vcpu); 9376 return 0; 9377 9378 free_guest_fpu: 9379 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); 9380 free_user_fpu: 9381 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); 9382 free_emulate_ctxt: 9383 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 9384 free_wbinvd_dirty_mask: 9385 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 9386 fail_free_mce_banks: 9387 kfree(vcpu->arch.mce_banks); 9388 fail_free_pio_data: 9389 free_page((unsigned long)vcpu->arch.pio_data); 9390 fail_free_lapic: 9391 kvm_free_lapic(vcpu); 9392 fail_mmu_destroy: 9393 kvm_mmu_destroy(vcpu); 9394 return r; 9395 } 9396 9397 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 9398 { 9399 struct msr_data msr; 9400 struct kvm *kvm = vcpu->kvm; 9401 9402 kvm_hv_vcpu_postcreate(vcpu); 9403 9404 if (mutex_lock_killable(&vcpu->mutex)) 9405 return; 9406 vcpu_load(vcpu); 9407 msr.data = 0x0; 9408 msr.index = MSR_IA32_TSC; 9409 msr.host_initiated = true; 9410 kvm_write_tsc(vcpu, &msr); 9411 vcpu_put(vcpu); 9412 9413 /* poll control enabled by default */ 9414 vcpu->arch.msr_kvm_poll_control = 1; 9415 9416 mutex_unlock(&vcpu->mutex); 9417 9418 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) 9419 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 9420 KVMCLOCK_SYNC_PERIOD); 9421 } 9422 9423 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 9424 { 9425 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; 9426 int idx; 9427 9428 kvm_release_pfn(cache->pfn, cache->dirty, cache); 9429 9430 kvmclock_reset(vcpu); 9431 9432 kvm_x86_ops.vcpu_free(vcpu); 9433 9434 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 9435 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 9436 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); 9437 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); 9438 9439 kvm_hv_vcpu_uninit(vcpu); 9440 kvm_pmu_destroy(vcpu); 9441 kfree(vcpu->arch.mce_banks); 9442 kvm_free_lapic(vcpu); 9443 idx = srcu_read_lock(&vcpu->kvm->srcu); 9444 kvm_mmu_destroy(vcpu); 9445 srcu_read_unlock(&vcpu->kvm->srcu, idx); 9446 free_page((unsigned long)vcpu->arch.pio_data); 9447 if (!lapic_in_kernel(vcpu)) 9448 static_key_slow_dec(&kvm_no_apic_vcpu); 9449 } 9450 9451 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 9452 { 9453 kvm_lapic_reset(vcpu, init_event); 9454 9455 vcpu->arch.hflags = 0; 9456 9457 vcpu->arch.smi_pending = 0; 9458 vcpu->arch.smi_count = 0; 9459 atomic_set(&vcpu->arch.nmi_queued, 0); 9460 vcpu->arch.nmi_pending = 0; 9461 vcpu->arch.nmi_injected = false; 9462 kvm_clear_interrupt_queue(vcpu); 9463 kvm_clear_exception_queue(vcpu); 9464 9465 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 9466 kvm_update_dr0123(vcpu); 9467 vcpu->arch.dr6 = DR6_INIT; 9468 kvm_update_dr6(vcpu); 9469 vcpu->arch.dr7 = DR7_FIXED_1; 9470 kvm_update_dr7(vcpu); 9471 9472 vcpu->arch.cr2 = 0; 9473 9474 kvm_make_request(KVM_REQ_EVENT, vcpu); 9475 vcpu->arch.apf.msr_val = 0; 9476 vcpu->arch.st.msr_val = 0; 9477 9478 kvmclock_reset(vcpu); 9479 9480 kvm_clear_async_pf_completion_queue(vcpu); 9481 kvm_async_pf_hash_reset(vcpu); 9482 vcpu->arch.apf.halted = false; 9483 9484 if (kvm_mpx_supported()) { 9485 void *mpx_state_buffer; 9486 9487 /* 9488 * To avoid have the INIT path from kvm_apic_has_events() that be 9489 * called with loaded FPU and does not let userspace fix the state. 9490 */ 9491 if (init_event) 9492 kvm_put_guest_fpu(vcpu); 9493 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 9494 XFEATURE_BNDREGS); 9495 if (mpx_state_buffer) 9496 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); 9497 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 9498 XFEATURE_BNDCSR); 9499 if (mpx_state_buffer) 9500 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); 9501 if (init_event) 9502 kvm_load_guest_fpu(vcpu); 9503 } 9504 9505 if (!init_event) { 9506 kvm_pmu_reset(vcpu); 9507 vcpu->arch.smbase = 0x30000; 9508 9509 vcpu->arch.msr_misc_features_enables = 0; 9510 9511 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 9512 } 9513 9514 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 9515 vcpu->arch.regs_avail = ~0; 9516 vcpu->arch.regs_dirty = ~0; 9517 9518 vcpu->arch.ia32_xss = 0; 9519 9520 kvm_x86_ops.vcpu_reset(vcpu, init_event); 9521 } 9522 9523 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 9524 { 9525 struct kvm_segment cs; 9526 9527 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 9528 cs.selector = vector << 8; 9529 cs.base = vector << 12; 9530 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 9531 kvm_rip_write(vcpu, 0); 9532 } 9533 9534 int kvm_arch_hardware_enable(void) 9535 { 9536 struct kvm *kvm; 9537 struct kvm_vcpu *vcpu; 9538 int i; 9539 int ret; 9540 u64 local_tsc; 9541 u64 max_tsc = 0; 9542 bool stable, backwards_tsc = false; 9543 9544 kvm_shared_msr_cpu_online(); 9545 ret = kvm_x86_ops.hardware_enable(); 9546 if (ret != 0) 9547 return ret; 9548 9549 local_tsc = rdtsc(); 9550 stable = !kvm_check_tsc_unstable(); 9551 list_for_each_entry(kvm, &vm_list, vm_list) { 9552 kvm_for_each_vcpu(i, vcpu, kvm) { 9553 if (!stable && vcpu->cpu == smp_processor_id()) 9554 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 9555 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 9556 backwards_tsc = true; 9557 if (vcpu->arch.last_host_tsc > max_tsc) 9558 max_tsc = vcpu->arch.last_host_tsc; 9559 } 9560 } 9561 } 9562 9563 /* 9564 * Sometimes, even reliable TSCs go backwards. This happens on 9565 * platforms that reset TSC during suspend or hibernate actions, but 9566 * maintain synchronization. We must compensate. Fortunately, we can 9567 * detect that condition here, which happens early in CPU bringup, 9568 * before any KVM threads can be running. Unfortunately, we can't 9569 * bring the TSCs fully up to date with real time, as we aren't yet far 9570 * enough into CPU bringup that we know how much real time has actually 9571 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot 9572 * variables that haven't been updated yet. 9573 * 9574 * So we simply find the maximum observed TSC above, then record the 9575 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 9576 * the adjustment will be applied. Note that we accumulate 9577 * adjustments, in case multiple suspend cycles happen before some VCPU 9578 * gets a chance to run again. In the event that no KVM threads get a 9579 * chance to run, we will miss the entire elapsed period, as we'll have 9580 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 9581 * loose cycle time. This isn't too big a deal, since the loss will be 9582 * uniform across all VCPUs (not to mention the scenario is extremely 9583 * unlikely). It is possible that a second hibernate recovery happens 9584 * much faster than a first, causing the observed TSC here to be 9585 * smaller; this would require additional padding adjustment, which is 9586 * why we set last_host_tsc to the local tsc observed here. 9587 * 9588 * N.B. - this code below runs only on platforms with reliable TSC, 9589 * as that is the only way backwards_tsc is set above. Also note 9590 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 9591 * have the same delta_cyc adjustment applied if backwards_tsc 9592 * is detected. Note further, this adjustment is only done once, 9593 * as we reset last_host_tsc on all VCPUs to stop this from being 9594 * called multiple times (one for each physical CPU bringup). 9595 * 9596 * Platforms with unreliable TSCs don't have to deal with this, they 9597 * will be compensated by the logic in vcpu_load, which sets the TSC to 9598 * catchup mode. This will catchup all VCPUs to real time, but cannot 9599 * guarantee that they stay in perfect synchronization. 9600 */ 9601 if (backwards_tsc) { 9602 u64 delta_cyc = max_tsc - local_tsc; 9603 list_for_each_entry(kvm, &vm_list, vm_list) { 9604 kvm->arch.backwards_tsc_observed = true; 9605 kvm_for_each_vcpu(i, vcpu, kvm) { 9606 vcpu->arch.tsc_offset_adjustment += delta_cyc; 9607 vcpu->arch.last_host_tsc = local_tsc; 9608 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 9609 } 9610 9611 /* 9612 * We have to disable TSC offset matching.. if you were 9613 * booting a VM while issuing an S4 host suspend.... 9614 * you may have some problem. Solving this issue is 9615 * left as an exercise to the reader. 9616 */ 9617 kvm->arch.last_tsc_nsec = 0; 9618 kvm->arch.last_tsc_write = 0; 9619 } 9620 9621 } 9622 return 0; 9623 } 9624 9625 void kvm_arch_hardware_disable(void) 9626 { 9627 kvm_x86_ops.hardware_disable(); 9628 drop_user_return_notifiers(); 9629 } 9630 9631 int kvm_arch_hardware_setup(void *opaque) 9632 { 9633 struct kvm_x86_init_ops *ops = opaque; 9634 int r; 9635 9636 rdmsrl_safe(MSR_EFER, &host_efer); 9637 9638 if (boot_cpu_has(X86_FEATURE_XSAVES)) 9639 rdmsrl(MSR_IA32_XSS, host_xss); 9640 9641 r = ops->hardware_setup(); 9642 if (r != 0) 9643 return r; 9644 9645 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); 9646 9647 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) 9648 supported_xss = 0; 9649 9650 cr4_reserved_bits = kvm_host_cr4_reserved_bits(&boot_cpu_data); 9651 9652 if (kvm_has_tsc_control) { 9653 /* 9654 * Make sure the user can only configure tsc_khz values that 9655 * fit into a signed integer. 9656 * A min value is not calculated because it will always 9657 * be 1 on all machines. 9658 */ 9659 u64 max = min(0x7fffffffULL, 9660 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 9661 kvm_max_guest_tsc_khz = max; 9662 9663 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 9664 } 9665 9666 kvm_init_msr_list(); 9667 return 0; 9668 } 9669 9670 void kvm_arch_hardware_unsetup(void) 9671 { 9672 kvm_x86_ops.hardware_unsetup(); 9673 } 9674 9675 int kvm_arch_check_processor_compat(void *opaque) 9676 { 9677 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 9678 struct kvm_x86_init_ops *ops = opaque; 9679 9680 WARN_ON(!irqs_disabled()); 9681 9682 if (kvm_host_cr4_reserved_bits(c) != cr4_reserved_bits) 9683 return -EIO; 9684 9685 return ops->check_processor_compatibility(); 9686 } 9687 9688 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 9689 { 9690 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 9691 } 9692 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 9693 9694 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 9695 { 9696 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 9697 } 9698 9699 struct static_key kvm_no_apic_vcpu __read_mostly; 9700 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); 9701 9702 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 9703 { 9704 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 9705 9706 vcpu->arch.l1tf_flush_l1d = true; 9707 if (pmu->version && unlikely(pmu->event_count)) { 9708 pmu->need_cleanup = true; 9709 kvm_make_request(KVM_REQ_PMU, vcpu); 9710 } 9711 kvm_x86_ops.sched_in(vcpu, cpu); 9712 } 9713 9714 void kvm_arch_free_vm(struct kvm *kvm) 9715 { 9716 kfree(kvm->arch.hyperv.hv_pa_pg); 9717 vfree(kvm); 9718 } 9719 9720 9721 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 9722 { 9723 if (type) 9724 return -EINVAL; 9725 9726 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 9727 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 9728 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 9729 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); 9730 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 9731 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 9732 9733 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 9734 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 9735 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 9736 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 9737 &kvm->arch.irq_sources_bitmap); 9738 9739 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 9740 mutex_init(&kvm->arch.apic_map_lock); 9741 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 9742 9743 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); 9744 pvclock_update_vm_gtod_copy(kvm); 9745 9746 kvm->arch.guest_can_read_msr_platform_info = true; 9747 9748 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 9749 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 9750 9751 kvm_hv_init_vm(kvm); 9752 kvm_page_track_init(kvm); 9753 kvm_mmu_init_vm(kvm); 9754 9755 return kvm_x86_ops.vm_init(kvm); 9756 } 9757 9758 int kvm_arch_post_init_vm(struct kvm *kvm) 9759 { 9760 return kvm_mmu_post_init_vm(kvm); 9761 } 9762 9763 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 9764 { 9765 vcpu_load(vcpu); 9766 kvm_mmu_unload(vcpu); 9767 vcpu_put(vcpu); 9768 } 9769 9770 static void kvm_free_vcpus(struct kvm *kvm) 9771 { 9772 unsigned int i; 9773 struct kvm_vcpu *vcpu; 9774 9775 /* 9776 * Unpin any mmu pages first. 9777 */ 9778 kvm_for_each_vcpu(i, vcpu, kvm) { 9779 kvm_clear_async_pf_completion_queue(vcpu); 9780 kvm_unload_vcpu_mmu(vcpu); 9781 } 9782 kvm_for_each_vcpu(i, vcpu, kvm) 9783 kvm_vcpu_destroy(vcpu); 9784 9785 mutex_lock(&kvm->lock); 9786 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 9787 kvm->vcpus[i] = NULL; 9788 9789 atomic_set(&kvm->online_vcpus, 0); 9790 mutex_unlock(&kvm->lock); 9791 } 9792 9793 void kvm_arch_sync_events(struct kvm *kvm) 9794 { 9795 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 9796 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 9797 kvm_free_pit(kvm); 9798 } 9799 9800 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 9801 { 9802 int i, r; 9803 unsigned long hva, uninitialized_var(old_npages); 9804 struct kvm_memslots *slots = kvm_memslots(kvm); 9805 struct kvm_memory_slot *slot; 9806 9807 /* Called with kvm->slots_lock held. */ 9808 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 9809 return -EINVAL; 9810 9811 slot = id_to_memslot(slots, id); 9812 if (size) { 9813 if (slot && slot->npages) 9814 return -EEXIST; 9815 9816 /* 9817 * MAP_SHARED to prevent internal slot pages from being moved 9818 * by fork()/COW. 9819 */ 9820 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 9821 MAP_SHARED | MAP_ANONYMOUS, 0); 9822 if (IS_ERR((void *)hva)) 9823 return PTR_ERR((void *)hva); 9824 } else { 9825 if (!slot || !slot->npages) 9826 return 0; 9827 9828 /* 9829 * Stuff a non-canonical value to catch use-after-delete. This 9830 * ends up being 0 on 32-bit KVM, but there's no better 9831 * alternative. 9832 */ 9833 hva = (unsigned long)(0xdeadull << 48); 9834 old_npages = slot->npages; 9835 } 9836 9837 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 9838 struct kvm_userspace_memory_region m; 9839 9840 m.slot = id | (i << 16); 9841 m.flags = 0; 9842 m.guest_phys_addr = gpa; 9843 m.userspace_addr = hva; 9844 m.memory_size = size; 9845 r = __kvm_set_memory_region(kvm, &m); 9846 if (r < 0) 9847 return r; 9848 } 9849 9850 if (!size) 9851 vm_munmap(hva, old_npages * PAGE_SIZE); 9852 9853 return 0; 9854 } 9855 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 9856 9857 void kvm_arch_pre_destroy_vm(struct kvm *kvm) 9858 { 9859 kvm_mmu_pre_destroy_vm(kvm); 9860 } 9861 9862 void kvm_arch_destroy_vm(struct kvm *kvm) 9863 { 9864 if (current->mm == kvm->mm) { 9865 /* 9866 * Free memory regions allocated on behalf of userspace, 9867 * unless the the memory map has changed due to process exit 9868 * or fd copying. 9869 */ 9870 mutex_lock(&kvm->slots_lock); 9871 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 9872 0, 0); 9873 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 9874 0, 0); 9875 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 9876 mutex_unlock(&kvm->slots_lock); 9877 } 9878 if (kvm_x86_ops.vm_destroy) 9879 kvm_x86_ops.vm_destroy(kvm); 9880 kvm_pic_destroy(kvm); 9881 kvm_ioapic_destroy(kvm); 9882 kvm_free_vcpus(kvm); 9883 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 9884 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); 9885 kvm_mmu_uninit_vm(kvm); 9886 kvm_page_track_cleanup(kvm); 9887 kvm_hv_destroy_vm(kvm); 9888 } 9889 9890 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) 9891 { 9892 int i; 9893 9894 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 9895 kvfree(slot->arch.rmap[i]); 9896 slot->arch.rmap[i] = NULL; 9897 9898 if (i == 0) 9899 continue; 9900 9901 kvfree(slot->arch.lpage_info[i - 1]); 9902 slot->arch.lpage_info[i - 1] = NULL; 9903 } 9904 9905 kvm_page_track_free_memslot(slot); 9906 } 9907 9908 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot, 9909 unsigned long npages) 9910 { 9911 int i; 9912 9913 /* 9914 * Clear out the previous array pointers for the KVM_MR_MOVE case. The 9915 * old arrays will be freed by __kvm_set_memory_region() if installing 9916 * the new memslot is successful. 9917 */ 9918 memset(&slot->arch, 0, sizeof(slot->arch)); 9919 9920 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 9921 struct kvm_lpage_info *linfo; 9922 unsigned long ugfn; 9923 int lpages; 9924 int level = i + 1; 9925 9926 lpages = gfn_to_index(slot->base_gfn + npages - 1, 9927 slot->base_gfn, level) + 1; 9928 9929 slot->arch.rmap[i] = 9930 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), 9931 GFP_KERNEL_ACCOUNT); 9932 if (!slot->arch.rmap[i]) 9933 goto out_free; 9934 if (i == 0) 9935 continue; 9936 9937 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 9938 if (!linfo) 9939 goto out_free; 9940 9941 slot->arch.lpage_info[i - 1] = linfo; 9942 9943 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 9944 linfo[0].disallow_lpage = 1; 9945 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 9946 linfo[lpages - 1].disallow_lpage = 1; 9947 ugfn = slot->userspace_addr >> PAGE_SHIFT; 9948 /* 9949 * If the gfn and userspace address are not aligned wrt each 9950 * other, disable large page support for this slot. 9951 */ 9952 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { 9953 unsigned long j; 9954 9955 for (j = 0; j < lpages; ++j) 9956 linfo[j].disallow_lpage = 1; 9957 } 9958 } 9959 9960 if (kvm_page_track_create_memslot(slot, npages)) 9961 goto out_free; 9962 9963 return 0; 9964 9965 out_free: 9966 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 9967 kvfree(slot->arch.rmap[i]); 9968 slot->arch.rmap[i] = NULL; 9969 if (i == 0) 9970 continue; 9971 9972 kvfree(slot->arch.lpage_info[i - 1]); 9973 slot->arch.lpage_info[i - 1] = NULL; 9974 } 9975 return -ENOMEM; 9976 } 9977 9978 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 9979 { 9980 struct kvm_vcpu *vcpu; 9981 int i; 9982 9983 /* 9984 * memslots->generation has been incremented. 9985 * mmio generation may have reached its maximum value. 9986 */ 9987 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 9988 9989 /* Force re-initialization of steal_time cache */ 9990 kvm_for_each_vcpu(i, vcpu, kvm) 9991 kvm_vcpu_kick(vcpu); 9992 } 9993 9994 int kvm_arch_prepare_memory_region(struct kvm *kvm, 9995 struct kvm_memory_slot *memslot, 9996 const struct kvm_userspace_memory_region *mem, 9997 enum kvm_mr_change change) 9998 { 9999 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) 10000 return kvm_alloc_memslot_metadata(memslot, 10001 mem->memory_size >> PAGE_SHIFT); 10002 return 0; 10003 } 10004 10005 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 10006 struct kvm_memory_slot *new) 10007 { 10008 /* Still write protect RO slot */ 10009 if (new->flags & KVM_MEM_READONLY) { 10010 kvm_mmu_slot_remove_write_access(kvm, new, PT_PAGE_TABLE_LEVEL); 10011 return; 10012 } 10013 10014 /* 10015 * Call kvm_x86_ops dirty logging hooks when they are valid. 10016 * 10017 * kvm_x86_ops.slot_disable_log_dirty is called when: 10018 * 10019 * - KVM_MR_CREATE with dirty logging is disabled 10020 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 10021 * 10022 * The reason is, in case of PML, we need to set D-bit for any slots 10023 * with dirty logging disabled in order to eliminate unnecessary GPA 10024 * logging in PML buffer (and potential PML buffer full VMEXIT). This 10025 * guarantees leaving PML enabled during guest's lifetime won't have 10026 * any additional overhead from PML when guest is running with dirty 10027 * logging disabled for memory slots. 10028 * 10029 * kvm_x86_ops.slot_enable_log_dirty is called when switching new slot 10030 * to dirty logging mode. 10031 * 10032 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 10033 * 10034 * In case of write protect: 10035 * 10036 * Write protect all pages for dirty logging. 10037 * 10038 * All the sptes including the large sptes which point to this 10039 * slot are set to readonly. We can not create any new large 10040 * spte on this slot until the end of the logging. 10041 * 10042 * See the comments in fast_page_fault(). 10043 */ 10044 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 10045 if (kvm_x86_ops.slot_enable_log_dirty) { 10046 kvm_x86_ops.slot_enable_log_dirty(kvm, new); 10047 } else { 10048 int level = 10049 kvm_dirty_log_manual_protect_and_init_set(kvm) ? 10050 PT_DIRECTORY_LEVEL : PT_PAGE_TABLE_LEVEL; 10051 10052 /* 10053 * If we're with initial-all-set, we don't need 10054 * to write protect any small page because 10055 * they're reported as dirty already. However 10056 * we still need to write-protect huge pages 10057 * so that the page split can happen lazily on 10058 * the first write to the huge page. 10059 */ 10060 kvm_mmu_slot_remove_write_access(kvm, new, level); 10061 } 10062 } else { 10063 if (kvm_x86_ops.slot_disable_log_dirty) 10064 kvm_x86_ops.slot_disable_log_dirty(kvm, new); 10065 } 10066 } 10067 10068 void kvm_arch_commit_memory_region(struct kvm *kvm, 10069 const struct kvm_userspace_memory_region *mem, 10070 struct kvm_memory_slot *old, 10071 const struct kvm_memory_slot *new, 10072 enum kvm_mr_change change) 10073 { 10074 if (!kvm->arch.n_requested_mmu_pages) 10075 kvm_mmu_change_mmu_pages(kvm, 10076 kvm_mmu_calculate_default_mmu_pages(kvm)); 10077 10078 /* 10079 * Dirty logging tracks sptes in 4k granularity, meaning that large 10080 * sptes have to be split. If live migration is successful, the guest 10081 * in the source machine will be destroyed and large sptes will be 10082 * created in the destination. However, if the guest continues to run 10083 * in the source machine (for example if live migration fails), small 10084 * sptes will remain around and cause bad performance. 10085 * 10086 * Scan sptes if dirty logging has been stopped, dropping those 10087 * which can be collapsed into a single large-page spte. Later 10088 * page faults will create the large-page sptes. 10089 * 10090 * There is no need to do this in any of the following cases: 10091 * CREATE: No dirty mappings will already exist. 10092 * MOVE/DELETE: The old mappings will already have been cleaned up by 10093 * kvm_arch_flush_shadow_memslot() 10094 */ 10095 if (change == KVM_MR_FLAGS_ONLY && 10096 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 10097 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 10098 kvm_mmu_zap_collapsible_sptes(kvm, new); 10099 10100 /* 10101 * Set up write protection and/or dirty logging for the new slot. 10102 * 10103 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 10104 * been zapped so no dirty logging staff is needed for old slot. For 10105 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 10106 * new and it's also covered when dealing with the new slot. 10107 * 10108 * FIXME: const-ify all uses of struct kvm_memory_slot. 10109 */ 10110 if (change != KVM_MR_DELETE) 10111 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 10112 10113 /* Free the arrays associated with the old memslot. */ 10114 if (change == KVM_MR_MOVE) 10115 kvm_arch_free_memslot(kvm, old); 10116 } 10117 10118 void kvm_arch_flush_shadow_all(struct kvm *kvm) 10119 { 10120 kvm_mmu_zap_all(kvm); 10121 } 10122 10123 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 10124 struct kvm_memory_slot *slot) 10125 { 10126 kvm_page_track_flush_slot(kvm, slot); 10127 } 10128 10129 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 10130 { 10131 return (is_guest_mode(vcpu) && 10132 kvm_x86_ops.guest_apic_has_interrupt && 10133 kvm_x86_ops.guest_apic_has_interrupt(vcpu)); 10134 } 10135 10136 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 10137 { 10138 if (!list_empty_careful(&vcpu->async_pf.done)) 10139 return true; 10140 10141 if (kvm_apic_has_events(vcpu)) 10142 return true; 10143 10144 if (vcpu->arch.pv.pv_unhalted) 10145 return true; 10146 10147 if (vcpu->arch.exception.pending) 10148 return true; 10149 10150 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 10151 (vcpu->arch.nmi_pending && 10152 kvm_x86_ops.nmi_allowed(vcpu))) 10153 return true; 10154 10155 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 10156 (vcpu->arch.smi_pending && !is_smm(vcpu))) 10157 return true; 10158 10159 if (kvm_arch_interrupt_allowed(vcpu) && 10160 (kvm_cpu_has_interrupt(vcpu) || 10161 kvm_guest_apic_has_interrupt(vcpu))) 10162 return true; 10163 10164 if (kvm_hv_has_stimer_pending(vcpu)) 10165 return true; 10166 10167 return false; 10168 } 10169 10170 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 10171 { 10172 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 10173 } 10174 10175 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) 10176 { 10177 if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) 10178 return true; 10179 10180 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 10181 kvm_test_request(KVM_REQ_SMI, vcpu) || 10182 kvm_test_request(KVM_REQ_EVENT, vcpu)) 10183 return true; 10184 10185 if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu)) 10186 return true; 10187 10188 return false; 10189 } 10190 10191 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 10192 { 10193 return vcpu->arch.preempted_in_kernel; 10194 } 10195 10196 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 10197 { 10198 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 10199 } 10200 10201 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 10202 { 10203 return kvm_x86_ops.interrupt_allowed(vcpu); 10204 } 10205 10206 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 10207 { 10208 if (is_64_bit_mode(vcpu)) 10209 return kvm_rip_read(vcpu); 10210 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 10211 kvm_rip_read(vcpu)); 10212 } 10213 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 10214 10215 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 10216 { 10217 return kvm_get_linear_rip(vcpu) == linear_rip; 10218 } 10219 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 10220 10221 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 10222 { 10223 unsigned long rflags; 10224 10225 rflags = kvm_x86_ops.get_rflags(vcpu); 10226 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 10227 rflags &= ~X86_EFLAGS_TF; 10228 return rflags; 10229 } 10230 EXPORT_SYMBOL_GPL(kvm_get_rflags); 10231 10232 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 10233 { 10234 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 10235 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 10236 rflags |= X86_EFLAGS_TF; 10237 kvm_x86_ops.set_rflags(vcpu, rflags); 10238 } 10239 10240 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 10241 { 10242 __kvm_set_rflags(vcpu, rflags); 10243 kvm_make_request(KVM_REQ_EVENT, vcpu); 10244 } 10245 EXPORT_SYMBOL_GPL(kvm_set_rflags); 10246 10247 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 10248 { 10249 int r; 10250 10251 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || 10252 work->wakeup_all) 10253 return; 10254 10255 r = kvm_mmu_reload(vcpu); 10256 if (unlikely(r)) 10257 return; 10258 10259 if (!vcpu->arch.mmu->direct_map && 10260 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) 10261 return; 10262 10263 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); 10264 } 10265 10266 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 10267 { 10268 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 10269 } 10270 10271 static inline u32 kvm_async_pf_next_probe(u32 key) 10272 { 10273 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 10274 } 10275 10276 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 10277 { 10278 u32 key = kvm_async_pf_hash_fn(gfn); 10279 10280 while (vcpu->arch.apf.gfns[key] != ~0) 10281 key = kvm_async_pf_next_probe(key); 10282 10283 vcpu->arch.apf.gfns[key] = gfn; 10284 } 10285 10286 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 10287 { 10288 int i; 10289 u32 key = kvm_async_pf_hash_fn(gfn); 10290 10291 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 10292 (vcpu->arch.apf.gfns[key] != gfn && 10293 vcpu->arch.apf.gfns[key] != ~0); i++) 10294 key = kvm_async_pf_next_probe(key); 10295 10296 return key; 10297 } 10298 10299 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 10300 { 10301 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 10302 } 10303 10304 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 10305 { 10306 u32 i, j, k; 10307 10308 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 10309 while (true) { 10310 vcpu->arch.apf.gfns[i] = ~0; 10311 do { 10312 j = kvm_async_pf_next_probe(j); 10313 if (vcpu->arch.apf.gfns[j] == ~0) 10314 return; 10315 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 10316 /* 10317 * k lies cyclically in ]i,j] 10318 * | i.k.j | 10319 * |....j i.k.| or |.k..j i...| 10320 */ 10321 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 10322 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 10323 i = j; 10324 } 10325 } 10326 10327 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 10328 { 10329 10330 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 10331 sizeof(val)); 10332 } 10333 10334 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val) 10335 { 10336 10337 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val, 10338 sizeof(u32)); 10339 } 10340 10341 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) 10342 { 10343 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) 10344 return false; 10345 10346 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 10347 (vcpu->arch.apf.send_user_only && 10348 kvm_x86_ops.get_cpl(vcpu) == 0)) 10349 return false; 10350 10351 return true; 10352 } 10353 10354 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) 10355 { 10356 if (unlikely(!lapic_in_kernel(vcpu) || 10357 kvm_event_needs_reinjection(vcpu) || 10358 vcpu->arch.exception.pending)) 10359 return false; 10360 10361 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) 10362 return false; 10363 10364 /* 10365 * If interrupts are off we cannot even use an artificial 10366 * halt state. 10367 */ 10368 return kvm_x86_ops.interrupt_allowed(vcpu); 10369 } 10370 10371 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 10372 struct kvm_async_pf *work) 10373 { 10374 struct x86_exception fault; 10375 10376 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); 10377 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 10378 10379 if (kvm_can_deliver_async_pf(vcpu) && 10380 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 10381 fault.vector = PF_VECTOR; 10382 fault.error_code_valid = true; 10383 fault.error_code = 0; 10384 fault.nested_page_fault = false; 10385 fault.address = work->arch.token; 10386 fault.async_page_fault = true; 10387 kvm_inject_page_fault(vcpu, &fault); 10388 } else { 10389 /* 10390 * It is not possible to deliver a paravirtualized asynchronous 10391 * page fault, but putting the guest in an artificial halt state 10392 * can be beneficial nevertheless: if an interrupt arrives, we 10393 * can deliver it timely and perhaps the guest will schedule 10394 * another process. When the instruction that triggered a page 10395 * fault is retried, hopefully the page will be ready in the host. 10396 */ 10397 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 10398 } 10399 } 10400 10401 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 10402 struct kvm_async_pf *work) 10403 { 10404 struct x86_exception fault; 10405 u32 val; 10406 10407 if (work->wakeup_all) 10408 work->arch.token = ~0; /* broadcast wakeup */ 10409 else 10410 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 10411 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); 10412 10413 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED && 10414 !apf_get_user(vcpu, &val)) { 10415 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT && 10416 vcpu->arch.exception.pending && 10417 vcpu->arch.exception.nr == PF_VECTOR && 10418 !apf_put_user(vcpu, 0)) { 10419 vcpu->arch.exception.injected = false; 10420 vcpu->arch.exception.pending = false; 10421 vcpu->arch.exception.nr = 0; 10422 vcpu->arch.exception.has_error_code = false; 10423 vcpu->arch.exception.error_code = 0; 10424 vcpu->arch.exception.has_payload = false; 10425 vcpu->arch.exception.payload = 0; 10426 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 10427 fault.vector = PF_VECTOR; 10428 fault.error_code_valid = true; 10429 fault.error_code = 0; 10430 fault.nested_page_fault = false; 10431 fault.address = work->arch.token; 10432 fault.async_page_fault = true; 10433 kvm_inject_page_fault(vcpu, &fault); 10434 } 10435 } 10436 vcpu->arch.apf.halted = false; 10437 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 10438 } 10439 10440 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 10441 { 10442 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 10443 return true; 10444 else 10445 return kvm_can_do_async_pf(vcpu); 10446 } 10447 10448 void kvm_arch_start_assignment(struct kvm *kvm) 10449 { 10450 atomic_inc(&kvm->arch.assigned_device_count); 10451 } 10452 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 10453 10454 void kvm_arch_end_assignment(struct kvm *kvm) 10455 { 10456 atomic_dec(&kvm->arch.assigned_device_count); 10457 } 10458 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 10459 10460 bool kvm_arch_has_assigned_device(struct kvm *kvm) 10461 { 10462 return atomic_read(&kvm->arch.assigned_device_count); 10463 } 10464 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 10465 10466 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 10467 { 10468 atomic_inc(&kvm->arch.noncoherent_dma_count); 10469 } 10470 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 10471 10472 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 10473 { 10474 atomic_dec(&kvm->arch.noncoherent_dma_count); 10475 } 10476 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 10477 10478 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 10479 { 10480 return atomic_read(&kvm->arch.noncoherent_dma_count); 10481 } 10482 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 10483 10484 bool kvm_arch_has_irq_bypass(void) 10485 { 10486 return true; 10487 } 10488 10489 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 10490 struct irq_bypass_producer *prod) 10491 { 10492 struct kvm_kernel_irqfd *irqfd = 10493 container_of(cons, struct kvm_kernel_irqfd, consumer); 10494 10495 irqfd->producer = prod; 10496 10497 return kvm_x86_ops.update_pi_irte(irqfd->kvm, 10498 prod->irq, irqfd->gsi, 1); 10499 } 10500 10501 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 10502 struct irq_bypass_producer *prod) 10503 { 10504 int ret; 10505 struct kvm_kernel_irqfd *irqfd = 10506 container_of(cons, struct kvm_kernel_irqfd, consumer); 10507 10508 WARN_ON(irqfd->producer != prod); 10509 irqfd->producer = NULL; 10510 10511 /* 10512 * When producer of consumer is unregistered, we change back to 10513 * remapped mode, so we can re-use the current implementation 10514 * when the irq is masked/disabled or the consumer side (KVM 10515 * int this case doesn't want to receive the interrupts. 10516 */ 10517 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 10518 if (ret) 10519 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 10520 " fails: %d\n", irqfd->consumer.token, ret); 10521 } 10522 10523 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 10524 uint32_t guest_irq, bool set) 10525 { 10526 return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set); 10527 } 10528 10529 bool kvm_vector_hashing_enabled(void) 10530 { 10531 return vector_hashing; 10532 } 10533 10534 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) 10535 { 10536 return (vcpu->arch.msr_kvm_poll_control & 1) == 0; 10537 } 10538 EXPORT_SYMBOL_GPL(kvm_arch_no_poll); 10539 10540 u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu) 10541 { 10542 uint64_t bits = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD; 10543 10544 /* The STIBP bit doesn't fault even if it's not advertised */ 10545 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) && 10546 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS)) 10547 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP); 10548 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL) && 10549 !boot_cpu_has(X86_FEATURE_AMD_IBRS)) 10550 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP); 10551 10552 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL_SSBD) && 10553 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD)) 10554 bits &= ~SPEC_CTRL_SSBD; 10555 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && 10556 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 10557 bits &= ~SPEC_CTRL_SSBD; 10558 10559 return bits; 10560 } 10561 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits); 10562 10563 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 10564 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 10565 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 10566 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 10567 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 10568 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 10569 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 10570 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 10571 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 10572 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 10573 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); 10574 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 10575 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 10576 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 10577 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 10578 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); 10579 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 10580 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 10581 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 10582 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 10583 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); 10584 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); 10585