1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * derived from drivers/kvm/kvm_main.c 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright (C) 2008 Qumranet, Inc. 9 * Copyright IBM Corporation, 2008 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 11 * 12 * Authors: 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * Amit Shah <amit.shah@qumranet.com> 16 * Ben-Ami Yassour <benami@il.ibm.com> 17 */ 18 19 #include <linux/kvm_host.h> 20 #include "irq.h" 21 #include "ioapic.h" 22 #include "mmu.h" 23 #include "i8254.h" 24 #include "tss.h" 25 #include "kvm_cache_regs.h" 26 #include "kvm_emulate.h" 27 #include "x86.h" 28 #include "cpuid.h" 29 #include "pmu.h" 30 #include "hyperv.h" 31 #include "lapic.h" 32 #include "xen.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/export.h> 40 #include <linux/moduleparam.h> 41 #include <linux/mman.h> 42 #include <linux/highmem.h> 43 #include <linux/iommu.h> 44 #include <linux/intel-iommu.h> 45 #include <linux/cpufreq.h> 46 #include <linux/user-return-notifier.h> 47 #include <linux/srcu.h> 48 #include <linux/slab.h> 49 #include <linux/perf_event.h> 50 #include <linux/uaccess.h> 51 #include <linux/hash.h> 52 #include <linux/pci.h> 53 #include <linux/timekeeper_internal.h> 54 #include <linux/pvclock_gtod.h> 55 #include <linux/kvm_irqfd.h> 56 #include <linux/irqbypass.h> 57 #include <linux/sched/stat.h> 58 #include <linux/sched/isolation.h> 59 #include <linux/mem_encrypt.h> 60 #include <linux/entry-kvm.h> 61 62 #include <trace/events/kvm.h> 63 64 #include <asm/debugreg.h> 65 #include <asm/msr.h> 66 #include <asm/desc.h> 67 #include <asm/mce.h> 68 #include <linux/kernel_stat.h> 69 #include <asm/fpu/internal.h> /* Ugh! */ 70 #include <asm/pvclock.h> 71 #include <asm/div64.h> 72 #include <asm/irq_remapping.h> 73 #include <asm/mshyperv.h> 74 #include <asm/hypervisor.h> 75 #include <asm/tlbflush.h> 76 #include <asm/intel_pt.h> 77 #include <asm/emulate_prefix.h> 78 #include <clocksource/hyperv_timer.h> 79 80 #define CREATE_TRACE_POINTS 81 #include "trace.h" 82 83 #define MAX_IO_MSRS 256 84 #define KVM_MAX_MCE_BANKS 32 85 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 86 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 87 88 #define emul_to_vcpu(ctxt) \ 89 ((struct kvm_vcpu *)(ctxt)->vcpu) 90 91 /* EFER defaults: 92 * - enable syscall per default because its emulated by KVM 93 * - enable LME and LMA per default on 64 bit KVM 94 */ 95 #ifdef CONFIG_X86_64 96 static 97 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 98 #else 99 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 100 #endif 101 102 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; 103 104 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 105 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 106 107 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 108 static void process_nmi(struct kvm_vcpu *vcpu); 109 static void process_smi(struct kvm_vcpu *vcpu); 110 static void enter_smm(struct kvm_vcpu *vcpu); 111 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 112 static void store_regs(struct kvm_vcpu *vcpu); 113 static int sync_regs(struct kvm_vcpu *vcpu); 114 115 struct kvm_x86_ops kvm_x86_ops __read_mostly; 116 EXPORT_SYMBOL_GPL(kvm_x86_ops); 117 118 #define KVM_X86_OP(func) \ 119 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ 120 *(((struct kvm_x86_ops *)0)->func)); 121 #define KVM_X86_OP_NULL KVM_X86_OP 122 #include <asm/kvm-x86-ops.h> 123 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); 124 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); 125 EXPORT_STATIC_CALL_GPL(kvm_x86_tlb_flush_current); 126 127 static bool __read_mostly ignore_msrs = 0; 128 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 129 130 bool __read_mostly report_ignored_msrs = true; 131 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 132 EXPORT_SYMBOL_GPL(report_ignored_msrs); 133 134 unsigned int min_timer_period_us = 200; 135 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 136 137 static bool __read_mostly kvmclock_periodic_sync = true; 138 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 139 140 bool __read_mostly kvm_has_tsc_control; 141 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 142 u32 __read_mostly kvm_max_guest_tsc_khz; 143 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 144 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 145 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 146 u64 __read_mostly kvm_max_tsc_scaling_ratio; 147 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 148 u64 __read_mostly kvm_default_tsc_scaling_ratio; 149 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 150 bool __read_mostly kvm_has_bus_lock_exit; 151 EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit); 152 153 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 154 static u32 __read_mostly tsc_tolerance_ppm = 250; 155 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 156 157 /* 158 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 159 * adaptive tuning starting from default advancment of 1000ns. '0' disables 160 * advancement entirely. Any other value is used as-is and disables adaptive 161 * tuning, i.e. allows priveleged userspace to set an exact advancement time. 162 */ 163 static int __read_mostly lapic_timer_advance_ns = -1; 164 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); 165 166 static bool __read_mostly vector_hashing = true; 167 module_param(vector_hashing, bool, S_IRUGO); 168 169 bool __read_mostly enable_vmware_backdoor = false; 170 module_param(enable_vmware_backdoor, bool, S_IRUGO); 171 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 172 173 static bool __read_mostly force_emulation_prefix = false; 174 module_param(force_emulation_prefix, bool, S_IRUGO); 175 176 int __read_mostly pi_inject_timer = -1; 177 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); 178 179 /* 180 * Restoring the host value for MSRs that are only consumed when running in 181 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU 182 * returns to userspace, i.e. the kernel can run with the guest's value. 183 */ 184 #define KVM_MAX_NR_USER_RETURN_MSRS 16 185 186 struct kvm_user_return_msrs_global { 187 int nr; 188 u32 msrs[KVM_MAX_NR_USER_RETURN_MSRS]; 189 }; 190 191 struct kvm_user_return_msrs { 192 struct user_return_notifier urn; 193 bool registered; 194 struct kvm_user_return_msr_values { 195 u64 host; 196 u64 curr; 197 } values[KVM_MAX_NR_USER_RETURN_MSRS]; 198 }; 199 200 static struct kvm_user_return_msrs_global __read_mostly user_return_msrs_global; 201 static struct kvm_user_return_msrs __percpu *user_return_msrs; 202 203 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 204 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 205 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 206 | XFEATURE_MASK_PKRU) 207 208 u64 __read_mostly host_efer; 209 EXPORT_SYMBOL_GPL(host_efer); 210 211 bool __read_mostly allow_smaller_maxphyaddr = 0; 212 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); 213 214 u64 __read_mostly host_xss; 215 EXPORT_SYMBOL_GPL(host_xss); 216 u64 __read_mostly supported_xss; 217 EXPORT_SYMBOL_GPL(supported_xss); 218 219 struct kvm_stats_debugfs_item debugfs_entries[] = { 220 VCPU_STAT("pf_fixed", pf_fixed), 221 VCPU_STAT("pf_guest", pf_guest), 222 VCPU_STAT("tlb_flush", tlb_flush), 223 VCPU_STAT("invlpg", invlpg), 224 VCPU_STAT("exits", exits), 225 VCPU_STAT("io_exits", io_exits), 226 VCPU_STAT("mmio_exits", mmio_exits), 227 VCPU_STAT("signal_exits", signal_exits), 228 VCPU_STAT("irq_window", irq_window_exits), 229 VCPU_STAT("nmi_window", nmi_window_exits), 230 VCPU_STAT("halt_exits", halt_exits), 231 VCPU_STAT("halt_successful_poll", halt_successful_poll), 232 VCPU_STAT("halt_attempted_poll", halt_attempted_poll), 233 VCPU_STAT("halt_poll_invalid", halt_poll_invalid), 234 VCPU_STAT("halt_wakeup", halt_wakeup), 235 VCPU_STAT("hypercalls", hypercalls), 236 VCPU_STAT("request_irq", request_irq_exits), 237 VCPU_STAT("irq_exits", irq_exits), 238 VCPU_STAT("host_state_reload", host_state_reload), 239 VCPU_STAT("fpu_reload", fpu_reload), 240 VCPU_STAT("insn_emulation", insn_emulation), 241 VCPU_STAT("insn_emulation_fail", insn_emulation_fail), 242 VCPU_STAT("irq_injections", irq_injections), 243 VCPU_STAT("nmi_injections", nmi_injections), 244 VCPU_STAT("req_event", req_event), 245 VCPU_STAT("l1d_flush", l1d_flush), 246 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns), 247 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns), 248 VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped), 249 VM_STAT("mmu_pte_write", mmu_pte_write), 250 VM_STAT("mmu_pde_zapped", mmu_pde_zapped), 251 VM_STAT("mmu_flooded", mmu_flooded), 252 VM_STAT("mmu_recycled", mmu_recycled), 253 VM_STAT("mmu_cache_miss", mmu_cache_miss), 254 VM_STAT("mmu_unsync", mmu_unsync), 255 VM_STAT("remote_tlb_flush", remote_tlb_flush), 256 VM_STAT("largepages", lpages, .mode = 0444), 257 VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444), 258 VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions), 259 { NULL } 260 }; 261 262 u64 __read_mostly host_xcr0; 263 u64 __read_mostly supported_xcr0; 264 EXPORT_SYMBOL_GPL(supported_xcr0); 265 266 static struct kmem_cache *x86_fpu_cache; 267 268 static struct kmem_cache *x86_emulator_cache; 269 270 /* 271 * When called, it means the previous get/set msr reached an invalid msr. 272 * Return true if we want to ignore/silent this failed msr access. 273 */ 274 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) 275 { 276 const char *op = write ? "wrmsr" : "rdmsr"; 277 278 if (ignore_msrs) { 279 if (report_ignored_msrs) 280 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", 281 op, msr, data); 282 /* Mask the error */ 283 return true; 284 } else { 285 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", 286 op, msr, data); 287 return false; 288 } 289 } 290 291 static struct kmem_cache *kvm_alloc_emulator_cache(void) 292 { 293 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); 294 unsigned int size = sizeof(struct x86_emulate_ctxt); 295 296 return kmem_cache_create_usercopy("x86_emulator", size, 297 __alignof__(struct x86_emulate_ctxt), 298 SLAB_ACCOUNT, useroffset, 299 size - useroffset, NULL); 300 } 301 302 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 303 304 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 305 { 306 int i; 307 for (i = 0; i < ASYNC_PF_PER_VCPU; i++) 308 vcpu->arch.apf.gfns[i] = ~0; 309 } 310 311 static void kvm_on_user_return(struct user_return_notifier *urn) 312 { 313 unsigned slot; 314 struct kvm_user_return_msrs *msrs 315 = container_of(urn, struct kvm_user_return_msrs, urn); 316 struct kvm_user_return_msr_values *values; 317 unsigned long flags; 318 319 /* 320 * Disabling irqs at this point since the following code could be 321 * interrupted and executed through kvm_arch_hardware_disable() 322 */ 323 local_irq_save(flags); 324 if (msrs->registered) { 325 msrs->registered = false; 326 user_return_notifier_unregister(urn); 327 } 328 local_irq_restore(flags); 329 for (slot = 0; slot < user_return_msrs_global.nr; ++slot) { 330 values = &msrs->values[slot]; 331 if (values->host != values->curr) { 332 wrmsrl(user_return_msrs_global.msrs[slot], values->host); 333 values->curr = values->host; 334 } 335 } 336 } 337 338 void kvm_define_user_return_msr(unsigned slot, u32 msr) 339 { 340 BUG_ON(slot >= KVM_MAX_NR_USER_RETURN_MSRS); 341 user_return_msrs_global.msrs[slot] = msr; 342 if (slot >= user_return_msrs_global.nr) 343 user_return_msrs_global.nr = slot + 1; 344 } 345 EXPORT_SYMBOL_GPL(kvm_define_user_return_msr); 346 347 static void kvm_user_return_msr_cpu_online(void) 348 { 349 unsigned int cpu = smp_processor_id(); 350 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 351 u64 value; 352 int i; 353 354 for (i = 0; i < user_return_msrs_global.nr; ++i) { 355 rdmsrl_safe(user_return_msrs_global.msrs[i], &value); 356 msrs->values[i].host = value; 357 msrs->values[i].curr = value; 358 } 359 } 360 361 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) 362 { 363 unsigned int cpu = smp_processor_id(); 364 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 365 int err; 366 367 value = (value & mask) | (msrs->values[slot].host & ~mask); 368 if (value == msrs->values[slot].curr) 369 return 0; 370 err = wrmsrl_safe(user_return_msrs_global.msrs[slot], value); 371 if (err) 372 return 1; 373 374 msrs->values[slot].curr = value; 375 if (!msrs->registered) { 376 msrs->urn.on_user_return = kvm_on_user_return; 377 user_return_notifier_register(&msrs->urn); 378 msrs->registered = true; 379 } 380 return 0; 381 } 382 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); 383 384 static void drop_user_return_notifiers(void) 385 { 386 unsigned int cpu = smp_processor_id(); 387 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 388 389 if (msrs->registered) 390 kvm_on_user_return(&msrs->urn); 391 } 392 393 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 394 { 395 return vcpu->arch.apic_base; 396 } 397 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 398 399 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 400 { 401 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 402 } 403 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 404 405 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 406 { 407 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 408 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 409 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | 410 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 411 412 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 413 return 1; 414 if (!msr_info->host_initiated) { 415 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 416 return 1; 417 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 418 return 1; 419 } 420 421 kvm_lapic_set_base(vcpu, msr_info->data); 422 kvm_recalculate_apic_map(vcpu->kvm); 423 return 0; 424 } 425 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 426 427 asmlinkage __visible noinstr void kvm_spurious_fault(void) 428 { 429 /* Fault while not rebooting. We want the trace. */ 430 BUG_ON(!kvm_rebooting); 431 } 432 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 433 434 #define EXCPT_BENIGN 0 435 #define EXCPT_CONTRIBUTORY 1 436 #define EXCPT_PF 2 437 438 static int exception_class(int vector) 439 { 440 switch (vector) { 441 case PF_VECTOR: 442 return EXCPT_PF; 443 case DE_VECTOR: 444 case TS_VECTOR: 445 case NP_VECTOR: 446 case SS_VECTOR: 447 case GP_VECTOR: 448 return EXCPT_CONTRIBUTORY; 449 default: 450 break; 451 } 452 return EXCPT_BENIGN; 453 } 454 455 #define EXCPT_FAULT 0 456 #define EXCPT_TRAP 1 457 #define EXCPT_ABORT 2 458 #define EXCPT_INTERRUPT 3 459 460 static int exception_type(int vector) 461 { 462 unsigned int mask; 463 464 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 465 return EXCPT_INTERRUPT; 466 467 mask = 1 << vector; 468 469 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 470 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 471 return EXCPT_TRAP; 472 473 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 474 return EXCPT_ABORT; 475 476 /* Reserved exceptions will result in fault */ 477 return EXCPT_FAULT; 478 } 479 480 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 481 { 482 unsigned nr = vcpu->arch.exception.nr; 483 bool has_payload = vcpu->arch.exception.has_payload; 484 unsigned long payload = vcpu->arch.exception.payload; 485 486 if (!has_payload) 487 return; 488 489 switch (nr) { 490 case DB_VECTOR: 491 /* 492 * "Certain debug exceptions may clear bit 0-3. The 493 * remaining contents of the DR6 register are never 494 * cleared by the processor". 495 */ 496 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 497 /* 498 * In order to reflect the #DB exception payload in guest 499 * dr6, three components need to be considered: active low 500 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, 501 * DR6_BS and DR6_BT) 502 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. 503 * In the target guest dr6: 504 * FIXED_1 bits should always be set. 505 * Active low bits should be cleared if 1-setting in payload. 506 * Active high bits should be set if 1-setting in payload. 507 * 508 * Note, the payload is compatible with the pending debug 509 * exceptions/exit qualification under VMX, that active_low bits 510 * are active high in payload. 511 * So they need to be flipped for DR6. 512 */ 513 vcpu->arch.dr6 |= DR6_ACTIVE_LOW; 514 vcpu->arch.dr6 |= payload; 515 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; 516 517 /* 518 * The #DB payload is defined as compatible with the 'pending 519 * debug exceptions' field under VMX, not DR6. While bit 12 is 520 * defined in the 'pending debug exceptions' field (enabled 521 * breakpoint), it is reserved and must be zero in DR6. 522 */ 523 vcpu->arch.dr6 &= ~BIT(12); 524 break; 525 case PF_VECTOR: 526 vcpu->arch.cr2 = payload; 527 break; 528 } 529 530 vcpu->arch.exception.has_payload = false; 531 vcpu->arch.exception.payload = 0; 532 } 533 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 534 535 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 536 unsigned nr, bool has_error, u32 error_code, 537 bool has_payload, unsigned long payload, bool reinject) 538 { 539 u32 prev_nr; 540 int class1, class2; 541 542 kvm_make_request(KVM_REQ_EVENT, vcpu); 543 544 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 545 queue: 546 if (has_error && !is_protmode(vcpu)) 547 has_error = false; 548 if (reinject) { 549 /* 550 * On vmentry, vcpu->arch.exception.pending is only 551 * true if an event injection was blocked by 552 * nested_run_pending. In that case, however, 553 * vcpu_enter_guest requests an immediate exit, 554 * and the guest shouldn't proceed far enough to 555 * need reinjection. 556 */ 557 WARN_ON_ONCE(vcpu->arch.exception.pending); 558 vcpu->arch.exception.injected = true; 559 if (WARN_ON_ONCE(has_payload)) { 560 /* 561 * A reinjected event has already 562 * delivered its payload. 563 */ 564 has_payload = false; 565 payload = 0; 566 } 567 } else { 568 vcpu->arch.exception.pending = true; 569 vcpu->arch.exception.injected = false; 570 } 571 vcpu->arch.exception.has_error_code = has_error; 572 vcpu->arch.exception.nr = nr; 573 vcpu->arch.exception.error_code = error_code; 574 vcpu->arch.exception.has_payload = has_payload; 575 vcpu->arch.exception.payload = payload; 576 if (!is_guest_mode(vcpu)) 577 kvm_deliver_exception_payload(vcpu); 578 return; 579 } 580 581 /* to check exception */ 582 prev_nr = vcpu->arch.exception.nr; 583 if (prev_nr == DF_VECTOR) { 584 /* triple fault -> shutdown */ 585 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 586 return; 587 } 588 class1 = exception_class(prev_nr); 589 class2 = exception_class(nr); 590 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 591 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 592 /* 593 * Generate double fault per SDM Table 5-5. Set 594 * exception.pending = true so that the double fault 595 * can trigger a nested vmexit. 596 */ 597 vcpu->arch.exception.pending = true; 598 vcpu->arch.exception.injected = false; 599 vcpu->arch.exception.has_error_code = true; 600 vcpu->arch.exception.nr = DF_VECTOR; 601 vcpu->arch.exception.error_code = 0; 602 vcpu->arch.exception.has_payload = false; 603 vcpu->arch.exception.payload = 0; 604 } else 605 /* replace previous exception with a new one in a hope 606 that instruction re-execution will regenerate lost 607 exception */ 608 goto queue; 609 } 610 611 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 612 { 613 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 614 } 615 EXPORT_SYMBOL_GPL(kvm_queue_exception); 616 617 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 618 { 619 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 620 } 621 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 622 623 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 624 unsigned long payload) 625 { 626 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 627 } 628 EXPORT_SYMBOL_GPL(kvm_queue_exception_p); 629 630 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 631 u32 error_code, unsigned long payload) 632 { 633 kvm_multiple_exception(vcpu, nr, true, error_code, 634 true, payload, false); 635 } 636 637 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 638 { 639 if (err) 640 kvm_inject_gp(vcpu, 0); 641 else 642 return kvm_skip_emulated_instruction(vcpu); 643 644 return 1; 645 } 646 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 647 648 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 649 { 650 ++vcpu->stat.pf_guest; 651 vcpu->arch.exception.nested_apf = 652 is_guest_mode(vcpu) && fault->async_page_fault; 653 if (vcpu->arch.exception.nested_apf) { 654 vcpu->arch.apf.nested_apf_token = fault->address; 655 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 656 } else { 657 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 658 fault->address); 659 } 660 } 661 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 662 663 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 664 struct x86_exception *fault) 665 { 666 struct kvm_mmu *fault_mmu; 667 WARN_ON_ONCE(fault->vector != PF_VECTOR); 668 669 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : 670 vcpu->arch.walk_mmu; 671 672 /* 673 * Invalidate the TLB entry for the faulting address, if it exists, 674 * else the access will fault indefinitely (and to emulate hardware). 675 */ 676 if ((fault->error_code & PFERR_PRESENT_MASK) && 677 !(fault->error_code & PFERR_RSVD_MASK)) 678 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, 679 fault_mmu->root_hpa); 680 681 fault_mmu->inject_page_fault(vcpu, fault); 682 return fault->nested_page_fault; 683 } 684 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); 685 686 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 687 { 688 atomic_inc(&vcpu->arch.nmi_queued); 689 kvm_make_request(KVM_REQ_NMI, vcpu); 690 } 691 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 692 693 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 694 { 695 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 696 } 697 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 698 699 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 700 { 701 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 702 } 703 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 704 705 /* 706 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 707 * a #GP and return false. 708 */ 709 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 710 { 711 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) 712 return true; 713 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 714 return false; 715 } 716 EXPORT_SYMBOL_GPL(kvm_require_cpl); 717 718 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 719 { 720 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 721 return true; 722 723 kvm_queue_exception(vcpu, UD_VECTOR); 724 return false; 725 } 726 EXPORT_SYMBOL_GPL(kvm_require_dr); 727 728 /* 729 * This function will be used to read from the physical memory of the currently 730 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 731 * can read from guest physical or from the guest's guest physical memory. 732 */ 733 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 734 gfn_t ngfn, void *data, int offset, int len, 735 u32 access) 736 { 737 struct x86_exception exception; 738 gfn_t real_gfn; 739 gpa_t ngpa; 740 741 ngpa = gfn_to_gpa(ngfn); 742 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 743 if (real_gfn == UNMAPPED_GVA) 744 return -EFAULT; 745 746 real_gfn = gpa_to_gfn(real_gfn); 747 748 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 749 } 750 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 751 752 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 753 void *data, int offset, int len, u32 access) 754 { 755 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 756 data, offset, len, access); 757 } 758 759 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) 760 { 761 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); 762 } 763 764 /* 765 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. 766 */ 767 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 768 { 769 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 770 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 771 int i; 772 int ret; 773 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 774 775 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 776 offset * sizeof(u64), sizeof(pdpte), 777 PFERR_USER_MASK|PFERR_WRITE_MASK); 778 if (ret < 0) { 779 ret = 0; 780 goto out; 781 } 782 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 783 if ((pdpte[i] & PT_PRESENT_MASK) && 784 (pdpte[i] & pdptr_rsvd_bits(vcpu))) { 785 ret = 0; 786 goto out; 787 } 788 } 789 ret = 1; 790 791 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 792 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 793 794 out: 795 796 return ret; 797 } 798 EXPORT_SYMBOL_GPL(load_pdptrs); 799 800 bool pdptrs_changed(struct kvm_vcpu *vcpu) 801 { 802 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 803 int offset; 804 gfn_t gfn; 805 int r; 806 807 if (!is_pae_paging(vcpu)) 808 return false; 809 810 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR)) 811 return true; 812 813 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; 814 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); 815 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 816 PFERR_USER_MASK | PFERR_WRITE_MASK); 817 if (r < 0) 818 return true; 819 820 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 821 } 822 EXPORT_SYMBOL_GPL(pdptrs_changed); 823 824 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) 825 { 826 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 827 828 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 829 kvm_clear_async_pf_completion_queue(vcpu); 830 kvm_async_pf_hash_reset(vcpu); 831 } 832 833 if ((cr0 ^ old_cr0) & update_bits) 834 kvm_mmu_reset_context(vcpu); 835 836 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 837 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 838 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 839 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 840 } 841 EXPORT_SYMBOL_GPL(kvm_post_set_cr0); 842 843 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 844 { 845 unsigned long old_cr0 = kvm_read_cr0(vcpu); 846 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; 847 848 cr0 |= X86_CR0_ET; 849 850 #ifdef CONFIG_X86_64 851 if (cr0 & 0xffffffff00000000UL) 852 return 1; 853 #endif 854 855 cr0 &= ~CR0_RESERVED_BITS; 856 857 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 858 return 1; 859 860 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 861 return 1; 862 863 #ifdef CONFIG_X86_64 864 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && 865 (cr0 & X86_CR0_PG)) { 866 int cs_db, cs_l; 867 868 if (!is_pae(vcpu)) 869 return 1; 870 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 871 if (cs_l) 872 return 1; 873 } 874 #endif 875 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && 876 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && 877 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) 878 return 1; 879 880 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 881 return 1; 882 883 static_call(kvm_x86_set_cr0)(vcpu, cr0); 884 885 kvm_post_set_cr0(vcpu, old_cr0, cr0); 886 887 return 0; 888 } 889 EXPORT_SYMBOL_GPL(kvm_set_cr0); 890 891 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 892 { 893 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 894 } 895 EXPORT_SYMBOL_GPL(kvm_lmsw); 896 897 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) 898 { 899 if (vcpu->arch.guest_state_protected) 900 return; 901 902 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 903 904 if (vcpu->arch.xcr0 != host_xcr0) 905 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 906 907 if (vcpu->arch.xsaves_enabled && 908 vcpu->arch.ia32_xss != host_xss) 909 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 910 } 911 912 if (static_cpu_has(X86_FEATURE_PKU) && 913 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 914 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && 915 vcpu->arch.pkru != vcpu->arch.host_pkru) 916 __write_pkru(vcpu->arch.pkru); 917 } 918 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); 919 920 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) 921 { 922 if (vcpu->arch.guest_state_protected) 923 return; 924 925 if (static_cpu_has(X86_FEATURE_PKU) && 926 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 927 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { 928 vcpu->arch.pkru = rdpkru(); 929 if (vcpu->arch.pkru != vcpu->arch.host_pkru) 930 __write_pkru(vcpu->arch.host_pkru); 931 } 932 933 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 934 935 if (vcpu->arch.xcr0 != host_xcr0) 936 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 937 938 if (vcpu->arch.xsaves_enabled && 939 vcpu->arch.ia32_xss != host_xss) 940 wrmsrl(MSR_IA32_XSS, host_xss); 941 } 942 943 } 944 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); 945 946 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 947 { 948 u64 xcr0 = xcr; 949 u64 old_xcr0 = vcpu->arch.xcr0; 950 u64 valid_bits; 951 952 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 953 if (index != XCR_XFEATURE_ENABLED_MASK) 954 return 1; 955 if (!(xcr0 & XFEATURE_MASK_FP)) 956 return 1; 957 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 958 return 1; 959 960 /* 961 * Do not allow the guest to set bits that we do not support 962 * saving. However, xcr0 bit 0 is always set, even if the 963 * emulated CPU does not support XSAVE (see fx_init). 964 */ 965 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 966 if (xcr0 & ~valid_bits) 967 return 1; 968 969 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 970 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 971 return 1; 972 973 if (xcr0 & XFEATURE_MASK_AVX512) { 974 if (!(xcr0 & XFEATURE_MASK_YMM)) 975 return 1; 976 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 977 return 1; 978 } 979 vcpu->arch.xcr0 = xcr0; 980 981 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 982 kvm_update_cpuid_runtime(vcpu); 983 return 0; 984 } 985 986 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 987 { 988 if (static_call(kvm_x86_get_cpl)(vcpu) == 0) 989 return __kvm_set_xcr(vcpu, index, xcr); 990 991 return 1; 992 } 993 EXPORT_SYMBOL_GPL(kvm_set_xcr); 994 995 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 996 { 997 if (cr4 & cr4_reserved_bits) 998 return false; 999 1000 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) 1001 return false; 1002 1003 return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); 1004 } 1005 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); 1006 1007 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) 1008 { 1009 unsigned long mmu_role_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 1010 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 1011 1012 if (((cr4 ^ old_cr4) & mmu_role_bits) || 1013 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 1014 kvm_mmu_reset_context(vcpu); 1015 } 1016 EXPORT_SYMBOL_GPL(kvm_post_set_cr4); 1017 1018 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1019 { 1020 unsigned long old_cr4 = kvm_read_cr4(vcpu); 1021 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 1022 X86_CR4_SMEP; 1023 1024 if (!kvm_is_valid_cr4(vcpu, cr4)) 1025 return 1; 1026 1027 if (is_long_mode(vcpu)) { 1028 if (!(cr4 & X86_CR4_PAE)) 1029 return 1; 1030 if ((cr4 ^ old_cr4) & X86_CR4_LA57) 1031 return 1; 1032 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 1033 && ((cr4 ^ old_cr4) & pdptr_bits) 1034 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 1035 kvm_read_cr3(vcpu))) 1036 return 1; 1037 1038 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 1039 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 1040 return 1; 1041 1042 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 1043 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 1044 return 1; 1045 } 1046 1047 static_call(kvm_x86_set_cr4)(vcpu, cr4); 1048 1049 kvm_post_set_cr4(vcpu, old_cr4, cr4); 1050 1051 return 0; 1052 } 1053 EXPORT_SYMBOL_GPL(kvm_set_cr4); 1054 1055 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 1056 { 1057 bool skip_tlb_flush = false; 1058 #ifdef CONFIG_X86_64 1059 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 1060 1061 if (pcid_enabled) { 1062 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 1063 cr3 &= ~X86_CR3_PCID_NOFLUSH; 1064 } 1065 #endif 1066 1067 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 1068 if (!skip_tlb_flush) { 1069 kvm_mmu_sync_roots(vcpu); 1070 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1071 } 1072 return 0; 1073 } 1074 1075 if (is_long_mode(vcpu) && kvm_vcpu_is_illegal_gpa(vcpu, cr3)) 1076 return 1; 1077 else if (is_pae_paging(vcpu) && 1078 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 1079 return 1; 1080 1081 kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush); 1082 vcpu->arch.cr3 = cr3; 1083 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 1084 1085 return 0; 1086 } 1087 EXPORT_SYMBOL_GPL(kvm_set_cr3); 1088 1089 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 1090 { 1091 if (cr8 & CR8_RESERVED_BITS) 1092 return 1; 1093 if (lapic_in_kernel(vcpu)) 1094 kvm_lapic_set_tpr(vcpu, cr8); 1095 else 1096 vcpu->arch.cr8 = cr8; 1097 return 0; 1098 } 1099 EXPORT_SYMBOL_GPL(kvm_set_cr8); 1100 1101 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 1102 { 1103 if (lapic_in_kernel(vcpu)) 1104 return kvm_lapic_get_cr8(vcpu); 1105 else 1106 return vcpu->arch.cr8; 1107 } 1108 EXPORT_SYMBOL_GPL(kvm_get_cr8); 1109 1110 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 1111 { 1112 int i; 1113 1114 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1115 for (i = 0; i < KVM_NR_DB_REGS; i++) 1116 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1117 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 1118 } 1119 } 1120 1121 void kvm_update_dr7(struct kvm_vcpu *vcpu) 1122 { 1123 unsigned long dr7; 1124 1125 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1126 dr7 = vcpu->arch.guest_debug_dr7; 1127 else 1128 dr7 = vcpu->arch.dr7; 1129 static_call(kvm_x86_set_dr7)(vcpu, dr7); 1130 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1131 if (dr7 & DR7_BP_EN_MASK) 1132 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1133 } 1134 EXPORT_SYMBOL_GPL(kvm_update_dr7); 1135 1136 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1137 { 1138 u64 fixed = DR6_FIXED_1; 1139 1140 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1141 fixed |= DR6_RTM; 1142 return fixed; 1143 } 1144 1145 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1146 { 1147 size_t size = ARRAY_SIZE(vcpu->arch.db); 1148 1149 switch (dr) { 1150 case 0 ... 3: 1151 vcpu->arch.db[array_index_nospec(dr, size)] = val; 1152 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1153 vcpu->arch.eff_db[dr] = val; 1154 break; 1155 case 4: 1156 case 6: 1157 if (!kvm_dr6_valid(val)) 1158 return 1; /* #GP */ 1159 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1160 break; 1161 case 5: 1162 default: /* 7 */ 1163 if (!kvm_dr7_valid(val)) 1164 return 1; /* #GP */ 1165 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1166 kvm_update_dr7(vcpu); 1167 break; 1168 } 1169 1170 return 0; 1171 } 1172 EXPORT_SYMBOL_GPL(kvm_set_dr); 1173 1174 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1175 { 1176 size_t size = ARRAY_SIZE(vcpu->arch.db); 1177 1178 switch (dr) { 1179 case 0 ... 3: 1180 *val = vcpu->arch.db[array_index_nospec(dr, size)]; 1181 break; 1182 case 4: 1183 case 6: 1184 *val = vcpu->arch.dr6; 1185 break; 1186 case 5: 1187 default: /* 7 */ 1188 *val = vcpu->arch.dr7; 1189 break; 1190 } 1191 } 1192 EXPORT_SYMBOL_GPL(kvm_get_dr); 1193 1194 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 1195 { 1196 u32 ecx = kvm_rcx_read(vcpu); 1197 u64 data; 1198 int err; 1199 1200 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 1201 if (err) 1202 return err; 1203 kvm_rax_write(vcpu, (u32)data); 1204 kvm_rdx_write(vcpu, data >> 32); 1205 return err; 1206 } 1207 EXPORT_SYMBOL_GPL(kvm_rdpmc); 1208 1209 /* 1210 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1211 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1212 * 1213 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) 1214 * extract the supported MSRs from the related const lists. 1215 * msrs_to_save is selected from the msrs_to_save_all to reflect the 1216 * capabilities of the host cpu. This capabilities test skips MSRs that are 1217 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs 1218 * may depend on host virtualization features rather than host cpu features. 1219 */ 1220 1221 static const u32 msrs_to_save_all[] = { 1222 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1223 MSR_STAR, 1224 #ifdef CONFIG_X86_64 1225 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1226 #endif 1227 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1228 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1229 MSR_IA32_SPEC_CTRL, 1230 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1231 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1232 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1233 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1234 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1235 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1236 MSR_IA32_UMWAIT_CONTROL, 1237 1238 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, 1239 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, 1240 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, 1241 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 1242 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, 1243 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, 1244 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, 1245 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, 1246 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, 1247 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, 1248 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, 1249 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, 1250 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, 1251 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, 1252 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, 1253 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, 1254 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, 1255 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, 1256 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, 1257 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, 1258 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, 1259 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, 1260 }; 1261 1262 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; 1263 static unsigned num_msrs_to_save; 1264 1265 static const u32 emulated_msrs_all[] = { 1266 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1267 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1268 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1269 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1270 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1271 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1272 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1273 HV_X64_MSR_RESET, 1274 HV_X64_MSR_VP_INDEX, 1275 HV_X64_MSR_VP_RUNTIME, 1276 HV_X64_MSR_SCONTROL, 1277 HV_X64_MSR_STIMER0_CONFIG, 1278 HV_X64_MSR_VP_ASSIST_PAGE, 1279 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1280 HV_X64_MSR_TSC_EMULATION_STATUS, 1281 HV_X64_MSR_SYNDBG_OPTIONS, 1282 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, 1283 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, 1284 HV_X64_MSR_SYNDBG_PENDING_BUFFER, 1285 1286 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1287 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, 1288 1289 MSR_IA32_TSC_ADJUST, 1290 MSR_IA32_TSCDEADLINE, 1291 MSR_IA32_ARCH_CAPABILITIES, 1292 MSR_IA32_PERF_CAPABILITIES, 1293 MSR_IA32_MISC_ENABLE, 1294 MSR_IA32_MCG_STATUS, 1295 MSR_IA32_MCG_CTL, 1296 MSR_IA32_MCG_EXT_CTL, 1297 MSR_IA32_SMBASE, 1298 MSR_SMI_COUNT, 1299 MSR_PLATFORM_INFO, 1300 MSR_MISC_FEATURES_ENABLES, 1301 MSR_AMD64_VIRT_SPEC_CTRL, 1302 MSR_IA32_POWER_CTL, 1303 MSR_IA32_UCODE_REV, 1304 1305 /* 1306 * The following list leaves out MSRs whose values are determined 1307 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. 1308 * We always support the "true" VMX control MSRs, even if the host 1309 * processor does not, so I am putting these registers here rather 1310 * than in msrs_to_save_all. 1311 */ 1312 MSR_IA32_VMX_BASIC, 1313 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1314 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1315 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1316 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1317 MSR_IA32_VMX_MISC, 1318 MSR_IA32_VMX_CR0_FIXED0, 1319 MSR_IA32_VMX_CR4_FIXED0, 1320 MSR_IA32_VMX_VMCS_ENUM, 1321 MSR_IA32_VMX_PROCBASED_CTLS2, 1322 MSR_IA32_VMX_EPT_VPID_CAP, 1323 MSR_IA32_VMX_VMFUNC, 1324 1325 MSR_K7_HWCR, 1326 MSR_KVM_POLL_CONTROL, 1327 }; 1328 1329 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; 1330 static unsigned num_emulated_msrs; 1331 1332 /* 1333 * List of msr numbers which are used to expose MSR-based features that 1334 * can be used by a hypervisor to validate requested CPU features. 1335 */ 1336 static const u32 msr_based_features_all[] = { 1337 MSR_IA32_VMX_BASIC, 1338 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1339 MSR_IA32_VMX_PINBASED_CTLS, 1340 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1341 MSR_IA32_VMX_PROCBASED_CTLS, 1342 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1343 MSR_IA32_VMX_EXIT_CTLS, 1344 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1345 MSR_IA32_VMX_ENTRY_CTLS, 1346 MSR_IA32_VMX_MISC, 1347 MSR_IA32_VMX_CR0_FIXED0, 1348 MSR_IA32_VMX_CR0_FIXED1, 1349 MSR_IA32_VMX_CR4_FIXED0, 1350 MSR_IA32_VMX_CR4_FIXED1, 1351 MSR_IA32_VMX_VMCS_ENUM, 1352 MSR_IA32_VMX_PROCBASED_CTLS2, 1353 MSR_IA32_VMX_EPT_VPID_CAP, 1354 MSR_IA32_VMX_VMFUNC, 1355 1356 MSR_F10H_DECFG, 1357 MSR_IA32_UCODE_REV, 1358 MSR_IA32_ARCH_CAPABILITIES, 1359 MSR_IA32_PERF_CAPABILITIES, 1360 }; 1361 1362 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; 1363 static unsigned int num_msr_based_features; 1364 1365 static u64 kvm_get_arch_capabilities(void) 1366 { 1367 u64 data = 0; 1368 1369 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1370 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); 1371 1372 /* 1373 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that 1374 * the nested hypervisor runs with NX huge pages. If it is not, 1375 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other 1376 * L1 guests, so it need not worry about its own (L2) guests. 1377 */ 1378 data |= ARCH_CAP_PSCHANGE_MC_NO; 1379 1380 /* 1381 * If we're doing cache flushes (either "always" or "cond") 1382 * we will do one whenever the guest does a vmlaunch/vmresume. 1383 * If an outer hypervisor is doing the cache flush for us 1384 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1385 * capability to the guest too, and if EPT is disabled we're not 1386 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1387 * require a nested hypervisor to do a flush of its own. 1388 */ 1389 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1390 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1391 1392 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) 1393 data |= ARCH_CAP_RDCL_NO; 1394 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1395 data |= ARCH_CAP_SSB_NO; 1396 if (!boot_cpu_has_bug(X86_BUG_MDS)) 1397 data |= ARCH_CAP_MDS_NO; 1398 1399 if (!boot_cpu_has(X86_FEATURE_RTM)) { 1400 /* 1401 * If RTM=0 because the kernel has disabled TSX, the host might 1402 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 1403 * and therefore knows that there cannot be TAA) but keep 1404 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, 1405 * and we want to allow migrating those guests to tsx=off hosts. 1406 */ 1407 data &= ~ARCH_CAP_TAA_NO; 1408 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { 1409 data |= ARCH_CAP_TAA_NO; 1410 } else { 1411 /* 1412 * Nothing to do here; we emulate TSX_CTRL if present on the 1413 * host so the guest can choose between disabling TSX or 1414 * using VERW to clear CPU buffers. 1415 */ 1416 } 1417 1418 return data; 1419 } 1420 1421 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1422 { 1423 switch (msr->index) { 1424 case MSR_IA32_ARCH_CAPABILITIES: 1425 msr->data = kvm_get_arch_capabilities(); 1426 break; 1427 case MSR_IA32_UCODE_REV: 1428 rdmsrl_safe(msr->index, &msr->data); 1429 break; 1430 default: 1431 return static_call(kvm_x86_get_msr_feature)(msr); 1432 } 1433 return 0; 1434 } 1435 1436 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1437 { 1438 struct kvm_msr_entry msr; 1439 int r; 1440 1441 msr.index = index; 1442 r = kvm_get_msr_feature(&msr); 1443 1444 if (r == KVM_MSR_RET_INVALID) { 1445 /* Unconditionally clear the output for simplicity */ 1446 *data = 0; 1447 if (kvm_msr_ignored_check(index, 0, false)) 1448 r = 0; 1449 } 1450 1451 if (r) 1452 return r; 1453 1454 *data = msr.data; 1455 1456 return 0; 1457 } 1458 1459 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1460 { 1461 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1462 return false; 1463 1464 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1465 return false; 1466 1467 if (efer & (EFER_LME | EFER_LMA) && 1468 !guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1469 return false; 1470 1471 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) 1472 return false; 1473 1474 return true; 1475 1476 } 1477 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1478 { 1479 if (efer & efer_reserved_bits) 1480 return false; 1481 1482 return __kvm_valid_efer(vcpu, efer); 1483 } 1484 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1485 1486 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1487 { 1488 u64 old_efer = vcpu->arch.efer; 1489 u64 efer = msr_info->data; 1490 int r; 1491 1492 if (efer & efer_reserved_bits) 1493 return 1; 1494 1495 if (!msr_info->host_initiated) { 1496 if (!__kvm_valid_efer(vcpu, efer)) 1497 return 1; 1498 1499 if (is_paging(vcpu) && 1500 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1501 return 1; 1502 } 1503 1504 efer &= ~EFER_LMA; 1505 efer |= vcpu->arch.efer & EFER_LMA; 1506 1507 r = static_call(kvm_x86_set_efer)(vcpu, efer); 1508 if (r) { 1509 WARN_ON(r > 0); 1510 return r; 1511 } 1512 1513 /* Update reserved bits */ 1514 if ((efer ^ old_efer) & EFER_NX) 1515 kvm_mmu_reset_context(vcpu); 1516 1517 return 0; 1518 } 1519 1520 void kvm_enable_efer_bits(u64 mask) 1521 { 1522 efer_reserved_bits &= ~mask; 1523 } 1524 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1525 1526 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) 1527 { 1528 struct kvm_x86_msr_filter *msr_filter; 1529 struct msr_bitmap_range *ranges; 1530 struct kvm *kvm = vcpu->kvm; 1531 bool allowed; 1532 int idx; 1533 u32 i; 1534 1535 /* x2APIC MSRs do not support filtering. */ 1536 if (index >= 0x800 && index <= 0x8ff) 1537 return true; 1538 1539 idx = srcu_read_lock(&kvm->srcu); 1540 1541 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); 1542 if (!msr_filter) { 1543 allowed = true; 1544 goto out; 1545 } 1546 1547 allowed = msr_filter->default_allow; 1548 ranges = msr_filter->ranges; 1549 1550 for (i = 0; i < msr_filter->count; i++) { 1551 u32 start = ranges[i].base; 1552 u32 end = start + ranges[i].nmsrs; 1553 u32 flags = ranges[i].flags; 1554 unsigned long *bitmap = ranges[i].bitmap; 1555 1556 if ((index >= start) && (index < end) && (flags & type)) { 1557 allowed = !!test_bit(index - start, bitmap); 1558 break; 1559 } 1560 } 1561 1562 out: 1563 srcu_read_unlock(&kvm->srcu, idx); 1564 1565 return allowed; 1566 } 1567 EXPORT_SYMBOL_GPL(kvm_msr_allowed); 1568 1569 /* 1570 * Write @data into the MSR specified by @index. Select MSR specific fault 1571 * checks are bypassed if @host_initiated is %true. 1572 * Returns 0 on success, non-0 otherwise. 1573 * Assumes vcpu_load() was already called. 1574 */ 1575 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, 1576 bool host_initiated) 1577 { 1578 struct msr_data msr; 1579 1580 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) 1581 return KVM_MSR_RET_FILTERED; 1582 1583 switch (index) { 1584 case MSR_FS_BASE: 1585 case MSR_GS_BASE: 1586 case MSR_KERNEL_GS_BASE: 1587 case MSR_CSTAR: 1588 case MSR_LSTAR: 1589 if (is_noncanonical_address(data, vcpu)) 1590 return 1; 1591 break; 1592 case MSR_IA32_SYSENTER_EIP: 1593 case MSR_IA32_SYSENTER_ESP: 1594 /* 1595 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1596 * non-canonical address is written on Intel but not on 1597 * AMD (which ignores the top 32-bits, because it does 1598 * not implement 64-bit SYSENTER). 1599 * 1600 * 64-bit code should hence be able to write a non-canonical 1601 * value on AMD. Making the address canonical ensures that 1602 * vmentry does not fail on Intel after writing a non-canonical 1603 * value, and that something deterministic happens if the guest 1604 * invokes 64-bit SYSENTER. 1605 */ 1606 data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); 1607 } 1608 1609 msr.data = data; 1610 msr.index = index; 1611 msr.host_initiated = host_initiated; 1612 1613 return static_call(kvm_x86_set_msr)(vcpu, &msr); 1614 } 1615 1616 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, 1617 u32 index, u64 data, bool host_initiated) 1618 { 1619 int ret = __kvm_set_msr(vcpu, index, data, host_initiated); 1620 1621 if (ret == KVM_MSR_RET_INVALID) 1622 if (kvm_msr_ignored_check(index, data, true)) 1623 ret = 0; 1624 1625 return ret; 1626 } 1627 1628 /* 1629 * Read the MSR specified by @index into @data. Select MSR specific fault 1630 * checks are bypassed if @host_initiated is %true. 1631 * Returns 0 on success, non-0 otherwise. 1632 * Assumes vcpu_load() was already called. 1633 */ 1634 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1635 bool host_initiated) 1636 { 1637 struct msr_data msr; 1638 int ret; 1639 1640 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) 1641 return KVM_MSR_RET_FILTERED; 1642 1643 msr.index = index; 1644 msr.host_initiated = host_initiated; 1645 1646 ret = static_call(kvm_x86_get_msr)(vcpu, &msr); 1647 if (!ret) 1648 *data = msr.data; 1649 return ret; 1650 } 1651 1652 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, 1653 u32 index, u64 *data, bool host_initiated) 1654 { 1655 int ret = __kvm_get_msr(vcpu, index, data, host_initiated); 1656 1657 if (ret == KVM_MSR_RET_INVALID) { 1658 /* Unconditionally clear *data for simplicity */ 1659 *data = 0; 1660 if (kvm_msr_ignored_check(index, 0, false)) 1661 ret = 0; 1662 } 1663 1664 return ret; 1665 } 1666 1667 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1668 { 1669 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1670 } 1671 EXPORT_SYMBOL_GPL(kvm_get_msr); 1672 1673 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) 1674 { 1675 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1676 } 1677 EXPORT_SYMBOL_GPL(kvm_set_msr); 1678 1679 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) 1680 { 1681 int err = vcpu->run->msr.error; 1682 if (!err) { 1683 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); 1684 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); 1685 } 1686 1687 return static_call(kvm_x86_complete_emulated_msr)(vcpu, err); 1688 } 1689 1690 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu) 1691 { 1692 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); 1693 } 1694 1695 static u64 kvm_msr_reason(int r) 1696 { 1697 switch (r) { 1698 case KVM_MSR_RET_INVALID: 1699 return KVM_MSR_EXIT_REASON_UNKNOWN; 1700 case KVM_MSR_RET_FILTERED: 1701 return KVM_MSR_EXIT_REASON_FILTER; 1702 default: 1703 return KVM_MSR_EXIT_REASON_INVAL; 1704 } 1705 } 1706 1707 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, 1708 u32 exit_reason, u64 data, 1709 int (*completion)(struct kvm_vcpu *vcpu), 1710 int r) 1711 { 1712 u64 msr_reason = kvm_msr_reason(r); 1713 1714 /* Check if the user wanted to know about this MSR fault */ 1715 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) 1716 return 0; 1717 1718 vcpu->run->exit_reason = exit_reason; 1719 vcpu->run->msr.error = 0; 1720 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); 1721 vcpu->run->msr.reason = msr_reason; 1722 vcpu->run->msr.index = index; 1723 vcpu->run->msr.data = data; 1724 vcpu->arch.complete_userspace_io = completion; 1725 1726 return 1; 1727 } 1728 1729 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r) 1730 { 1731 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0, 1732 complete_emulated_rdmsr, r); 1733 } 1734 1735 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r) 1736 { 1737 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data, 1738 complete_emulated_wrmsr, r); 1739 } 1740 1741 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) 1742 { 1743 u32 ecx = kvm_rcx_read(vcpu); 1744 u64 data; 1745 int r; 1746 1747 r = kvm_get_msr(vcpu, ecx, &data); 1748 1749 /* MSR read failed? See if we should ask user space */ 1750 if (r && kvm_get_msr_user_space(vcpu, ecx, r)) { 1751 /* Bounce to user space */ 1752 return 0; 1753 } 1754 1755 if (!r) { 1756 trace_kvm_msr_read(ecx, data); 1757 1758 kvm_rax_write(vcpu, data & -1u); 1759 kvm_rdx_write(vcpu, (data >> 32) & -1u); 1760 } else { 1761 trace_kvm_msr_read_ex(ecx); 1762 } 1763 1764 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1765 } 1766 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); 1767 1768 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) 1769 { 1770 u32 ecx = kvm_rcx_read(vcpu); 1771 u64 data = kvm_read_edx_eax(vcpu); 1772 int r; 1773 1774 r = kvm_set_msr(vcpu, ecx, data); 1775 1776 /* MSR write failed? See if we should ask user space */ 1777 if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) 1778 /* Bounce to user space */ 1779 return 0; 1780 1781 /* Signal all other negative errors to userspace */ 1782 if (r < 0) 1783 return r; 1784 1785 if (!r) 1786 trace_kvm_msr_write(ecx, data); 1787 else 1788 trace_kvm_msr_write_ex(ecx, data); 1789 1790 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1791 } 1792 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); 1793 1794 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) 1795 { 1796 xfer_to_guest_mode_prepare(); 1797 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || 1798 xfer_to_guest_mode_work_pending(); 1799 } 1800 1801 /* 1802 * The fast path for frequent and performance sensitive wrmsr emulation, 1803 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces 1804 * the latency of virtual IPI by avoiding the expensive bits of transitioning 1805 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the 1806 * other cases which must be called after interrupts are enabled on the host. 1807 */ 1808 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) 1809 { 1810 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) 1811 return 1; 1812 1813 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && 1814 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && 1815 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && 1816 ((u32)(data >> 32) != X2APIC_BROADCAST)) { 1817 1818 data &= ~(1 << 12); 1819 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); 1820 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); 1821 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); 1822 trace_kvm_apic_write(APIC_ICR, (u32)data); 1823 return 0; 1824 } 1825 1826 return 1; 1827 } 1828 1829 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) 1830 { 1831 if (!kvm_can_use_hv_timer(vcpu)) 1832 return 1; 1833 1834 kvm_set_lapic_tscdeadline_msr(vcpu, data); 1835 return 0; 1836 } 1837 1838 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) 1839 { 1840 u32 msr = kvm_rcx_read(vcpu); 1841 u64 data; 1842 fastpath_t ret = EXIT_FASTPATH_NONE; 1843 1844 switch (msr) { 1845 case APIC_BASE_MSR + (APIC_ICR >> 4): 1846 data = kvm_read_edx_eax(vcpu); 1847 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { 1848 kvm_skip_emulated_instruction(vcpu); 1849 ret = EXIT_FASTPATH_EXIT_HANDLED; 1850 } 1851 break; 1852 case MSR_IA32_TSCDEADLINE: 1853 data = kvm_read_edx_eax(vcpu); 1854 if (!handle_fastpath_set_tscdeadline(vcpu, data)) { 1855 kvm_skip_emulated_instruction(vcpu); 1856 ret = EXIT_FASTPATH_REENTER_GUEST; 1857 } 1858 break; 1859 default: 1860 break; 1861 } 1862 1863 if (ret != EXIT_FASTPATH_NONE) 1864 trace_kvm_msr_write(msr, data); 1865 1866 return ret; 1867 } 1868 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); 1869 1870 /* 1871 * Adapt set_msr() to msr_io()'s calling convention 1872 */ 1873 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1874 { 1875 return kvm_get_msr_ignored_check(vcpu, index, data, true); 1876 } 1877 1878 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1879 { 1880 return kvm_set_msr_ignored_check(vcpu, index, *data, true); 1881 } 1882 1883 #ifdef CONFIG_X86_64 1884 struct pvclock_clock { 1885 int vclock_mode; 1886 u64 cycle_last; 1887 u64 mask; 1888 u32 mult; 1889 u32 shift; 1890 u64 base_cycles; 1891 u64 offset; 1892 }; 1893 1894 struct pvclock_gtod_data { 1895 seqcount_t seq; 1896 1897 struct pvclock_clock clock; /* extract of a clocksource struct */ 1898 struct pvclock_clock raw_clock; /* extract of a clocksource struct */ 1899 1900 ktime_t offs_boot; 1901 u64 wall_time_sec; 1902 }; 1903 1904 static struct pvclock_gtod_data pvclock_gtod_data; 1905 1906 static void update_pvclock_gtod(struct timekeeper *tk) 1907 { 1908 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1909 1910 write_seqcount_begin(&vdata->seq); 1911 1912 /* copy pvclock gtod data */ 1913 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; 1914 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1915 vdata->clock.mask = tk->tkr_mono.mask; 1916 vdata->clock.mult = tk->tkr_mono.mult; 1917 vdata->clock.shift = tk->tkr_mono.shift; 1918 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 1919 vdata->clock.offset = tk->tkr_mono.base; 1920 1921 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; 1922 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; 1923 vdata->raw_clock.mask = tk->tkr_raw.mask; 1924 vdata->raw_clock.mult = tk->tkr_raw.mult; 1925 vdata->raw_clock.shift = tk->tkr_raw.shift; 1926 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; 1927 vdata->raw_clock.offset = tk->tkr_raw.base; 1928 1929 vdata->wall_time_sec = tk->xtime_sec; 1930 1931 vdata->offs_boot = tk->offs_boot; 1932 1933 write_seqcount_end(&vdata->seq); 1934 } 1935 1936 static s64 get_kvmclock_base_ns(void) 1937 { 1938 /* Count up from boot time, but with the frequency of the raw clock. */ 1939 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); 1940 } 1941 #else 1942 static s64 get_kvmclock_base_ns(void) 1943 { 1944 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ 1945 return ktime_get_boottime_ns(); 1946 } 1947 #endif 1948 1949 void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) 1950 { 1951 int version; 1952 int r; 1953 struct pvclock_wall_clock wc; 1954 u32 wc_sec_hi; 1955 u64 wall_nsec; 1956 1957 if (!wall_clock) 1958 return; 1959 1960 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1961 if (r) 1962 return; 1963 1964 if (version & 1) 1965 ++version; /* first time write, random junk */ 1966 1967 ++version; 1968 1969 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1970 return; 1971 1972 /* 1973 * The guest calculates current wall clock time by adding 1974 * system time (updated by kvm_guest_time_update below) to the 1975 * wall clock specified here. We do the reverse here. 1976 */ 1977 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); 1978 1979 wc.nsec = do_div(wall_nsec, 1000000000); 1980 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ 1981 wc.version = version; 1982 1983 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1984 1985 if (sec_hi_ofs) { 1986 wc_sec_hi = wall_nsec >> 32; 1987 kvm_write_guest(kvm, wall_clock + sec_hi_ofs, 1988 &wc_sec_hi, sizeof(wc_sec_hi)); 1989 } 1990 1991 version++; 1992 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1993 } 1994 1995 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, 1996 bool old_msr, bool host_initiated) 1997 { 1998 struct kvm_arch *ka = &vcpu->kvm->arch; 1999 2000 if (vcpu->vcpu_id == 0 && !host_initiated) { 2001 if (ka->boot_vcpu_runs_old_kvmclock != old_msr) 2002 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2003 2004 ka->boot_vcpu_runs_old_kvmclock = old_msr; 2005 } 2006 2007 vcpu->arch.time = system_time; 2008 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2009 2010 /* we verify if the enable bit is set... */ 2011 vcpu->arch.pv_time_enabled = false; 2012 if (!(system_time & 1)) 2013 return; 2014 2015 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, 2016 &vcpu->arch.pv_time, system_time & ~1ULL, 2017 sizeof(struct pvclock_vcpu_time_info))) 2018 vcpu->arch.pv_time_enabled = true; 2019 2020 return; 2021 } 2022 2023 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 2024 { 2025 do_shl32_div32(dividend, divisor); 2026 return dividend; 2027 } 2028 2029 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 2030 s8 *pshift, u32 *pmultiplier) 2031 { 2032 uint64_t scaled64; 2033 int32_t shift = 0; 2034 uint64_t tps64; 2035 uint32_t tps32; 2036 2037 tps64 = base_hz; 2038 scaled64 = scaled_hz; 2039 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 2040 tps64 >>= 1; 2041 shift--; 2042 } 2043 2044 tps32 = (uint32_t)tps64; 2045 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 2046 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 2047 scaled64 >>= 1; 2048 else 2049 tps32 <<= 1; 2050 shift++; 2051 } 2052 2053 *pshift = shift; 2054 *pmultiplier = div_frac(scaled64, tps32); 2055 } 2056 2057 #ifdef CONFIG_X86_64 2058 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 2059 #endif 2060 2061 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 2062 static unsigned long max_tsc_khz; 2063 2064 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 2065 { 2066 u64 v = (u64)khz * (1000000 + ppm); 2067 do_div(v, 1000000); 2068 return v; 2069 } 2070 2071 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 2072 { 2073 u64 ratio; 2074 2075 /* Guest TSC same frequency as host TSC? */ 2076 if (!scale) { 2077 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 2078 return 0; 2079 } 2080 2081 /* TSC scaling supported? */ 2082 if (!kvm_has_tsc_control) { 2083 if (user_tsc_khz > tsc_khz) { 2084 vcpu->arch.tsc_catchup = 1; 2085 vcpu->arch.tsc_always_catchup = 1; 2086 return 0; 2087 } else { 2088 pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); 2089 return -1; 2090 } 2091 } 2092 2093 /* TSC scaling required - calculate ratio */ 2094 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 2095 user_tsc_khz, tsc_khz); 2096 2097 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 2098 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 2099 user_tsc_khz); 2100 return -1; 2101 } 2102 2103 vcpu->arch.tsc_scaling_ratio = ratio; 2104 return 0; 2105 } 2106 2107 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 2108 { 2109 u32 thresh_lo, thresh_hi; 2110 int use_scaling = 0; 2111 2112 /* tsc_khz can be zero if TSC calibration fails */ 2113 if (user_tsc_khz == 0) { 2114 /* set tsc_scaling_ratio to a safe value */ 2115 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 2116 return -1; 2117 } 2118 2119 /* Compute a scale to convert nanoseconds in TSC cycles */ 2120 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 2121 &vcpu->arch.virtual_tsc_shift, 2122 &vcpu->arch.virtual_tsc_mult); 2123 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 2124 2125 /* 2126 * Compute the variation in TSC rate which is acceptable 2127 * within the range of tolerance and decide if the 2128 * rate being applied is within that bounds of the hardware 2129 * rate. If so, no scaling or compensation need be done. 2130 */ 2131 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 2132 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 2133 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 2134 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 2135 use_scaling = 1; 2136 } 2137 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 2138 } 2139 2140 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 2141 { 2142 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 2143 vcpu->arch.virtual_tsc_mult, 2144 vcpu->arch.virtual_tsc_shift); 2145 tsc += vcpu->arch.this_tsc_write; 2146 return tsc; 2147 } 2148 2149 static inline int gtod_is_based_on_tsc(int mode) 2150 { 2151 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; 2152 } 2153 2154 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 2155 { 2156 #ifdef CONFIG_X86_64 2157 bool vcpus_matched; 2158 struct kvm_arch *ka = &vcpu->kvm->arch; 2159 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2160 2161 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2162 atomic_read(&vcpu->kvm->online_vcpus)); 2163 2164 /* 2165 * Once the masterclock is enabled, always perform request in 2166 * order to update it. 2167 * 2168 * In order to enable masterclock, the host clocksource must be TSC 2169 * and the vcpus need to have matched TSCs. When that happens, 2170 * perform request to enable masterclock. 2171 */ 2172 if (ka->use_master_clock || 2173 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 2174 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2175 2176 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 2177 atomic_read(&vcpu->kvm->online_vcpus), 2178 ka->use_master_clock, gtod->clock.vclock_mode); 2179 #endif 2180 } 2181 2182 /* 2183 * Multiply tsc by a fixed point number represented by ratio. 2184 * 2185 * The most significant 64-N bits (mult) of ratio represent the 2186 * integral part of the fixed point number; the remaining N bits 2187 * (frac) represent the fractional part, ie. ratio represents a fixed 2188 * point number (mult + frac * 2^(-N)). 2189 * 2190 * N equals to kvm_tsc_scaling_ratio_frac_bits. 2191 */ 2192 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 2193 { 2194 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 2195 } 2196 2197 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 2198 { 2199 u64 _tsc = tsc; 2200 u64 ratio = vcpu->arch.tsc_scaling_ratio; 2201 2202 if (ratio != kvm_default_tsc_scaling_ratio) 2203 _tsc = __scale_tsc(ratio, tsc); 2204 2205 return _tsc; 2206 } 2207 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 2208 2209 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 2210 { 2211 u64 tsc; 2212 2213 tsc = kvm_scale_tsc(vcpu, rdtsc()); 2214 2215 return target_tsc - tsc; 2216 } 2217 2218 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 2219 { 2220 return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc); 2221 } 2222 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 2223 2224 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 2225 { 2226 vcpu->arch.l1_tsc_offset = offset; 2227 vcpu->arch.tsc_offset = static_call(kvm_x86_write_l1_tsc_offset)(vcpu, offset); 2228 } 2229 2230 static inline bool kvm_check_tsc_unstable(void) 2231 { 2232 #ifdef CONFIG_X86_64 2233 /* 2234 * TSC is marked unstable when we're running on Hyper-V, 2235 * 'TSC page' clocksource is good. 2236 */ 2237 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) 2238 return false; 2239 #endif 2240 return check_tsc_unstable(); 2241 } 2242 2243 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) 2244 { 2245 struct kvm *kvm = vcpu->kvm; 2246 u64 offset, ns, elapsed; 2247 unsigned long flags; 2248 bool matched; 2249 bool already_matched; 2250 bool synchronizing = false; 2251 2252 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 2253 offset = kvm_compute_tsc_offset(vcpu, data); 2254 ns = get_kvmclock_base_ns(); 2255 elapsed = ns - kvm->arch.last_tsc_nsec; 2256 2257 if (vcpu->arch.virtual_tsc_khz) { 2258 if (data == 0) { 2259 /* 2260 * detection of vcpu initialization -- need to sync 2261 * with other vCPUs. This particularly helps to keep 2262 * kvm_clock stable after CPU hotplug 2263 */ 2264 synchronizing = true; 2265 } else { 2266 u64 tsc_exp = kvm->arch.last_tsc_write + 2267 nsec_to_cycles(vcpu, elapsed); 2268 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 2269 /* 2270 * Special case: TSC write with a small delta (1 second) 2271 * of virtual cycle time against real time is 2272 * interpreted as an attempt to synchronize the CPU. 2273 */ 2274 synchronizing = data < tsc_exp + tsc_hz && 2275 data + tsc_hz > tsc_exp; 2276 } 2277 } 2278 2279 /* 2280 * For a reliable TSC, we can match TSC offsets, and for an unstable 2281 * TSC, we add elapsed time in this computation. We could let the 2282 * compensation code attempt to catch up if we fall behind, but 2283 * it's better to try to match offsets from the beginning. 2284 */ 2285 if (synchronizing && 2286 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 2287 if (!kvm_check_tsc_unstable()) { 2288 offset = kvm->arch.cur_tsc_offset; 2289 } else { 2290 u64 delta = nsec_to_cycles(vcpu, elapsed); 2291 data += delta; 2292 offset = kvm_compute_tsc_offset(vcpu, data); 2293 } 2294 matched = true; 2295 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 2296 } else { 2297 /* 2298 * We split periods of matched TSC writes into generations. 2299 * For each generation, we track the original measured 2300 * nanosecond time, offset, and write, so if TSCs are in 2301 * sync, we can match exact offset, and if not, we can match 2302 * exact software computation in compute_guest_tsc() 2303 * 2304 * These values are tracked in kvm->arch.cur_xxx variables. 2305 */ 2306 kvm->arch.cur_tsc_generation++; 2307 kvm->arch.cur_tsc_nsec = ns; 2308 kvm->arch.cur_tsc_write = data; 2309 kvm->arch.cur_tsc_offset = offset; 2310 matched = false; 2311 } 2312 2313 /* 2314 * We also track th most recent recorded KHZ, write and time to 2315 * allow the matching interval to be extended at each write. 2316 */ 2317 kvm->arch.last_tsc_nsec = ns; 2318 kvm->arch.last_tsc_write = data; 2319 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 2320 2321 vcpu->arch.last_guest_tsc = data; 2322 2323 /* Keep track of which generation this VCPU has synchronized to */ 2324 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 2325 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 2326 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 2327 2328 kvm_vcpu_write_tsc_offset(vcpu, offset); 2329 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 2330 2331 spin_lock_irqsave(&kvm->arch.pvclock_gtod_sync_lock, flags); 2332 if (!matched) { 2333 kvm->arch.nr_vcpus_matched_tsc = 0; 2334 } else if (!already_matched) { 2335 kvm->arch.nr_vcpus_matched_tsc++; 2336 } 2337 2338 kvm_track_tsc_matching(vcpu); 2339 spin_unlock_irqrestore(&kvm->arch.pvclock_gtod_sync_lock, flags); 2340 } 2341 2342 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 2343 s64 adjustment) 2344 { 2345 u64 tsc_offset = vcpu->arch.l1_tsc_offset; 2346 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 2347 } 2348 2349 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 2350 { 2351 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 2352 WARN_ON(adjustment < 0); 2353 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 2354 adjust_tsc_offset_guest(vcpu, adjustment); 2355 } 2356 2357 #ifdef CONFIG_X86_64 2358 2359 static u64 read_tsc(void) 2360 { 2361 u64 ret = (u64)rdtsc_ordered(); 2362 u64 last = pvclock_gtod_data.clock.cycle_last; 2363 2364 if (likely(ret >= last)) 2365 return ret; 2366 2367 /* 2368 * GCC likes to generate cmov here, but this branch is extremely 2369 * predictable (it's just a function of time and the likely is 2370 * very likely) and there's a data dependence, so force GCC 2371 * to generate a branch instead. I don't barrier() because 2372 * we don't actually need a barrier, and if this function 2373 * ever gets inlined it will generate worse code. 2374 */ 2375 asm volatile (""); 2376 return last; 2377 } 2378 2379 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, 2380 int *mode) 2381 { 2382 long v; 2383 u64 tsc_pg_val; 2384 2385 switch (clock->vclock_mode) { 2386 case VDSO_CLOCKMODE_HVCLOCK: 2387 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 2388 tsc_timestamp); 2389 if (tsc_pg_val != U64_MAX) { 2390 /* TSC page valid */ 2391 *mode = VDSO_CLOCKMODE_HVCLOCK; 2392 v = (tsc_pg_val - clock->cycle_last) & 2393 clock->mask; 2394 } else { 2395 /* TSC page invalid */ 2396 *mode = VDSO_CLOCKMODE_NONE; 2397 } 2398 break; 2399 case VDSO_CLOCKMODE_TSC: 2400 *mode = VDSO_CLOCKMODE_TSC; 2401 *tsc_timestamp = read_tsc(); 2402 v = (*tsc_timestamp - clock->cycle_last) & 2403 clock->mask; 2404 break; 2405 default: 2406 *mode = VDSO_CLOCKMODE_NONE; 2407 } 2408 2409 if (*mode == VDSO_CLOCKMODE_NONE) 2410 *tsc_timestamp = v = 0; 2411 2412 return v * clock->mult; 2413 } 2414 2415 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) 2416 { 2417 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2418 unsigned long seq; 2419 int mode; 2420 u64 ns; 2421 2422 do { 2423 seq = read_seqcount_begin(>od->seq); 2424 ns = gtod->raw_clock.base_cycles; 2425 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); 2426 ns >>= gtod->raw_clock.shift; 2427 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); 2428 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2429 *t = ns; 2430 2431 return mode; 2432 } 2433 2434 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 2435 { 2436 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2437 unsigned long seq; 2438 int mode; 2439 u64 ns; 2440 2441 do { 2442 seq = read_seqcount_begin(>od->seq); 2443 ts->tv_sec = gtod->wall_time_sec; 2444 ns = gtod->clock.base_cycles; 2445 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2446 ns >>= gtod->clock.shift; 2447 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2448 2449 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 2450 ts->tv_nsec = ns; 2451 2452 return mode; 2453 } 2454 2455 /* returns true if host is using TSC based clocksource */ 2456 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2457 { 2458 /* checked again under seqlock below */ 2459 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2460 return false; 2461 2462 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, 2463 tsc_timestamp)); 2464 } 2465 2466 /* returns true if host is using TSC based clocksource */ 2467 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 2468 u64 *tsc_timestamp) 2469 { 2470 /* checked again under seqlock below */ 2471 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2472 return false; 2473 2474 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 2475 } 2476 #endif 2477 2478 /* 2479 * 2480 * Assuming a stable TSC across physical CPUS, and a stable TSC 2481 * across virtual CPUs, the following condition is possible. 2482 * Each numbered line represents an event visible to both 2483 * CPUs at the next numbered event. 2484 * 2485 * "timespecX" represents host monotonic time. "tscX" represents 2486 * RDTSC value. 2487 * 2488 * VCPU0 on CPU0 | VCPU1 on CPU1 2489 * 2490 * 1. read timespec0,tsc0 2491 * 2. | timespec1 = timespec0 + N 2492 * | tsc1 = tsc0 + M 2493 * 3. transition to guest | transition to guest 2494 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 2495 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 2496 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 2497 * 2498 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 2499 * 2500 * - ret0 < ret1 2501 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 2502 * ... 2503 * - 0 < N - M => M < N 2504 * 2505 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 2506 * always the case (the difference between two distinct xtime instances 2507 * might be smaller then the difference between corresponding TSC reads, 2508 * when updating guest vcpus pvclock areas). 2509 * 2510 * To avoid that problem, do not allow visibility of distinct 2511 * system_timestamp/tsc_timestamp values simultaneously: use a master 2512 * copy of host monotonic time values. Update that master copy 2513 * in lockstep. 2514 * 2515 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2516 * 2517 */ 2518 2519 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2520 { 2521 #ifdef CONFIG_X86_64 2522 struct kvm_arch *ka = &kvm->arch; 2523 int vclock_mode; 2524 bool host_tsc_clocksource, vcpus_matched; 2525 2526 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2527 atomic_read(&kvm->online_vcpus)); 2528 2529 /* 2530 * If the host uses TSC clock, then passthrough TSC as stable 2531 * to the guest. 2532 */ 2533 host_tsc_clocksource = kvm_get_time_and_clockread( 2534 &ka->master_kernel_ns, 2535 &ka->master_cycle_now); 2536 2537 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2538 && !ka->backwards_tsc_observed 2539 && !ka->boot_vcpu_runs_old_kvmclock; 2540 2541 if (ka->use_master_clock) 2542 atomic_set(&kvm_guest_has_master_clock, 1); 2543 2544 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2545 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2546 vcpus_matched); 2547 #endif 2548 } 2549 2550 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2551 { 2552 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2553 } 2554 2555 static void kvm_gen_update_masterclock(struct kvm *kvm) 2556 { 2557 #ifdef CONFIG_X86_64 2558 int i; 2559 struct kvm_vcpu *vcpu; 2560 struct kvm_arch *ka = &kvm->arch; 2561 unsigned long flags; 2562 2563 kvm_hv_invalidate_tsc_page(kvm); 2564 2565 kvm_make_mclock_inprogress_request(kvm); 2566 2567 /* no guest entries from this point */ 2568 spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 2569 pvclock_update_vm_gtod_copy(kvm); 2570 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2571 2572 kvm_for_each_vcpu(i, vcpu, kvm) 2573 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2574 2575 /* guest entries allowed */ 2576 kvm_for_each_vcpu(i, vcpu, kvm) 2577 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2578 #endif 2579 } 2580 2581 u64 get_kvmclock_ns(struct kvm *kvm) 2582 { 2583 struct kvm_arch *ka = &kvm->arch; 2584 struct pvclock_vcpu_time_info hv_clock; 2585 unsigned long flags; 2586 u64 ret; 2587 2588 spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 2589 if (!ka->use_master_clock) { 2590 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2591 return get_kvmclock_base_ns() + ka->kvmclock_offset; 2592 } 2593 2594 hv_clock.tsc_timestamp = ka->master_cycle_now; 2595 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2596 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2597 2598 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2599 get_cpu(); 2600 2601 if (__this_cpu_read(cpu_tsc_khz)) { 2602 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2603 &hv_clock.tsc_shift, 2604 &hv_clock.tsc_to_system_mul); 2605 ret = __pvclock_read_cycles(&hv_clock, rdtsc()); 2606 } else 2607 ret = get_kvmclock_base_ns() + ka->kvmclock_offset; 2608 2609 put_cpu(); 2610 2611 return ret; 2612 } 2613 2614 static void kvm_setup_pvclock_page(struct kvm_vcpu *v, 2615 struct gfn_to_hva_cache *cache, 2616 unsigned int offset) 2617 { 2618 struct kvm_vcpu_arch *vcpu = &v->arch; 2619 struct pvclock_vcpu_time_info guest_hv_clock; 2620 2621 if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache, 2622 &guest_hv_clock, offset, sizeof(guest_hv_clock)))) 2623 return; 2624 2625 /* This VCPU is paused, but it's legal for a guest to read another 2626 * VCPU's kvmclock, so we really have to follow the specification where 2627 * it says that version is odd if data is being modified, and even after 2628 * it is consistent. 2629 * 2630 * Version field updates must be kept separate. This is because 2631 * kvm_write_guest_cached might use a "rep movs" instruction, and 2632 * writes within a string instruction are weakly ordered. So there 2633 * are three writes overall. 2634 * 2635 * As a small optimization, only write the version field in the first 2636 * and third write. The vcpu->pv_time cache is still valid, because the 2637 * version field is the first in the struct. 2638 */ 2639 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 2640 2641 if (guest_hv_clock.version & 1) 2642 ++guest_hv_clock.version; /* first time write, random junk */ 2643 2644 vcpu->hv_clock.version = guest_hv_clock.version + 1; 2645 kvm_write_guest_offset_cached(v->kvm, cache, 2646 &vcpu->hv_clock, offset, 2647 sizeof(vcpu->hv_clock.version)); 2648 2649 smp_wmb(); 2650 2651 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 2652 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 2653 2654 if (vcpu->pvclock_set_guest_stopped_request) { 2655 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 2656 vcpu->pvclock_set_guest_stopped_request = false; 2657 } 2658 2659 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 2660 2661 kvm_write_guest_offset_cached(v->kvm, cache, 2662 &vcpu->hv_clock, offset, 2663 sizeof(vcpu->hv_clock)); 2664 2665 smp_wmb(); 2666 2667 vcpu->hv_clock.version++; 2668 kvm_write_guest_offset_cached(v->kvm, cache, 2669 &vcpu->hv_clock, offset, 2670 sizeof(vcpu->hv_clock.version)); 2671 } 2672 2673 static int kvm_guest_time_update(struct kvm_vcpu *v) 2674 { 2675 unsigned long flags, tgt_tsc_khz; 2676 struct kvm_vcpu_arch *vcpu = &v->arch; 2677 struct kvm_arch *ka = &v->kvm->arch; 2678 s64 kernel_ns; 2679 u64 tsc_timestamp, host_tsc; 2680 u8 pvclock_flags; 2681 bool use_master_clock; 2682 2683 kernel_ns = 0; 2684 host_tsc = 0; 2685 2686 /* 2687 * If the host uses TSC clock, then passthrough TSC as stable 2688 * to the guest. 2689 */ 2690 spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 2691 use_master_clock = ka->use_master_clock; 2692 if (use_master_clock) { 2693 host_tsc = ka->master_cycle_now; 2694 kernel_ns = ka->master_kernel_ns; 2695 } 2696 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 2697 2698 /* Keep irq disabled to prevent changes to the clock */ 2699 local_irq_save(flags); 2700 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 2701 if (unlikely(tgt_tsc_khz == 0)) { 2702 local_irq_restore(flags); 2703 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2704 return 1; 2705 } 2706 if (!use_master_clock) { 2707 host_tsc = rdtsc(); 2708 kernel_ns = get_kvmclock_base_ns(); 2709 } 2710 2711 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 2712 2713 /* 2714 * We may have to catch up the TSC to match elapsed wall clock 2715 * time for two reasons, even if kvmclock is used. 2716 * 1) CPU could have been running below the maximum TSC rate 2717 * 2) Broken TSC compensation resets the base at each VCPU 2718 * entry to avoid unknown leaps of TSC even when running 2719 * again on the same CPU. This may cause apparent elapsed 2720 * time to disappear, and the guest to stand still or run 2721 * very slowly. 2722 */ 2723 if (vcpu->tsc_catchup) { 2724 u64 tsc = compute_guest_tsc(v, kernel_ns); 2725 if (tsc > tsc_timestamp) { 2726 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 2727 tsc_timestamp = tsc; 2728 } 2729 } 2730 2731 local_irq_restore(flags); 2732 2733 /* With all the info we got, fill in the values */ 2734 2735 if (kvm_has_tsc_control) 2736 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 2737 2738 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 2739 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 2740 &vcpu->hv_clock.tsc_shift, 2741 &vcpu->hv_clock.tsc_to_system_mul); 2742 vcpu->hw_tsc_khz = tgt_tsc_khz; 2743 } 2744 2745 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 2746 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 2747 vcpu->last_guest_tsc = tsc_timestamp; 2748 2749 /* If the host uses TSC clocksource, then it is stable */ 2750 pvclock_flags = 0; 2751 if (use_master_clock) 2752 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 2753 2754 vcpu->hv_clock.flags = pvclock_flags; 2755 2756 if (vcpu->pv_time_enabled) 2757 kvm_setup_pvclock_page(v, &vcpu->pv_time, 0); 2758 if (vcpu->xen.vcpu_info_set) 2759 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache, 2760 offsetof(struct compat_vcpu_info, time)); 2761 if (vcpu->xen.vcpu_time_info_set) 2762 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0); 2763 if (v == kvm_get_vcpu(v->kvm, 0)) 2764 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 2765 return 0; 2766 } 2767 2768 /* 2769 * kvmclock updates which are isolated to a given vcpu, such as 2770 * vcpu->cpu migration, should not allow system_timestamp from 2771 * the rest of the vcpus to remain static. Otherwise ntp frequency 2772 * correction applies to one vcpu's system_timestamp but not 2773 * the others. 2774 * 2775 * So in those cases, request a kvmclock update for all vcpus. 2776 * We need to rate-limit these requests though, as they can 2777 * considerably slow guests that have a large number of vcpus. 2778 * The time for a remote vcpu to update its kvmclock is bound 2779 * by the delay we use to rate-limit the updates. 2780 */ 2781 2782 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 2783 2784 static void kvmclock_update_fn(struct work_struct *work) 2785 { 2786 int i; 2787 struct delayed_work *dwork = to_delayed_work(work); 2788 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2789 kvmclock_update_work); 2790 struct kvm *kvm = container_of(ka, struct kvm, arch); 2791 struct kvm_vcpu *vcpu; 2792 2793 kvm_for_each_vcpu(i, vcpu, kvm) { 2794 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2795 kvm_vcpu_kick(vcpu); 2796 } 2797 } 2798 2799 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 2800 { 2801 struct kvm *kvm = v->kvm; 2802 2803 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2804 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 2805 KVMCLOCK_UPDATE_DELAY); 2806 } 2807 2808 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 2809 2810 static void kvmclock_sync_fn(struct work_struct *work) 2811 { 2812 struct delayed_work *dwork = to_delayed_work(work); 2813 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2814 kvmclock_sync_work); 2815 struct kvm *kvm = container_of(ka, struct kvm, arch); 2816 2817 if (!kvmclock_periodic_sync) 2818 return; 2819 2820 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 2821 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 2822 KVMCLOCK_SYNC_PERIOD); 2823 } 2824 2825 /* 2826 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 2827 */ 2828 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 2829 { 2830 /* McStatusWrEn enabled? */ 2831 if (guest_cpuid_is_amd_or_hygon(vcpu)) 2832 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 2833 2834 return false; 2835 } 2836 2837 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2838 { 2839 u64 mcg_cap = vcpu->arch.mcg_cap; 2840 unsigned bank_num = mcg_cap & 0xff; 2841 u32 msr = msr_info->index; 2842 u64 data = msr_info->data; 2843 2844 switch (msr) { 2845 case MSR_IA32_MCG_STATUS: 2846 vcpu->arch.mcg_status = data; 2847 break; 2848 case MSR_IA32_MCG_CTL: 2849 if (!(mcg_cap & MCG_CTL_P) && 2850 (data || !msr_info->host_initiated)) 2851 return 1; 2852 if (data != 0 && data != ~(u64)0) 2853 return 1; 2854 vcpu->arch.mcg_ctl = data; 2855 break; 2856 default: 2857 if (msr >= MSR_IA32_MC0_CTL && 2858 msr < MSR_IA32_MCx_CTL(bank_num)) { 2859 u32 offset = array_index_nospec( 2860 msr - MSR_IA32_MC0_CTL, 2861 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 2862 2863 /* only 0 or all 1s can be written to IA32_MCi_CTL 2864 * some Linux kernels though clear bit 10 in bank 4 to 2865 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 2866 * this to avoid an uncatched #GP in the guest 2867 */ 2868 if ((offset & 0x3) == 0 && 2869 data != 0 && (data | (1 << 10)) != ~(u64)0) 2870 return -1; 2871 2872 /* MCi_STATUS */ 2873 if (!msr_info->host_initiated && 2874 (offset & 0x3) == 1 && data != 0) { 2875 if (!can_set_mci_status(vcpu)) 2876 return -1; 2877 } 2878 2879 vcpu->arch.mce_banks[offset] = data; 2880 break; 2881 } 2882 return 1; 2883 } 2884 return 0; 2885 } 2886 2887 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) 2888 { 2889 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; 2890 2891 return (vcpu->arch.apf.msr_en_val & mask) == mask; 2892 } 2893 2894 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2895 { 2896 gpa_t gpa = data & ~0x3f; 2897 2898 /* Bits 4:5 are reserved, Should be zero */ 2899 if (data & 0x30) 2900 return 1; 2901 2902 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && 2903 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) 2904 return 1; 2905 2906 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && 2907 (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) 2908 return 1; 2909 2910 if (!lapic_in_kernel(vcpu)) 2911 return data ? 1 : 0; 2912 2913 vcpu->arch.apf.msr_en_val = data; 2914 2915 if (!kvm_pv_async_pf_enabled(vcpu)) { 2916 kvm_clear_async_pf_completion_queue(vcpu); 2917 kvm_async_pf_hash_reset(vcpu); 2918 return 0; 2919 } 2920 2921 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2922 sizeof(u64))) 2923 return 1; 2924 2925 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2926 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 2927 2928 kvm_async_pf_wakeup_all(vcpu); 2929 2930 return 0; 2931 } 2932 2933 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) 2934 { 2935 /* Bits 8-63 are reserved */ 2936 if (data >> 8) 2937 return 1; 2938 2939 if (!lapic_in_kernel(vcpu)) 2940 return 1; 2941 2942 vcpu->arch.apf.msr_int_val = data; 2943 2944 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; 2945 2946 return 0; 2947 } 2948 2949 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2950 { 2951 vcpu->arch.pv_time_enabled = false; 2952 vcpu->arch.time = 0; 2953 } 2954 2955 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) 2956 { 2957 ++vcpu->stat.tlb_flush; 2958 static_call(kvm_x86_tlb_flush_all)(vcpu); 2959 } 2960 2961 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) 2962 { 2963 ++vcpu->stat.tlb_flush; 2964 static_call(kvm_x86_tlb_flush_guest)(vcpu); 2965 } 2966 2967 static void record_steal_time(struct kvm_vcpu *vcpu) 2968 { 2969 struct kvm_host_map map; 2970 struct kvm_steal_time *st; 2971 2972 if (kvm_xen_msr_enabled(vcpu->kvm)) { 2973 kvm_xen_runstate_set_running(vcpu); 2974 return; 2975 } 2976 2977 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2978 return; 2979 2980 /* -EAGAIN is returned in atomic context so we can just return. */ 2981 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, 2982 &map, &vcpu->arch.st.cache, false)) 2983 return; 2984 2985 st = map.hva + 2986 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 2987 2988 /* 2989 * Doing a TLB flush here, on the guest's behalf, can avoid 2990 * expensive IPIs. 2991 */ 2992 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { 2993 trace_kvm_pv_tlb_flush(vcpu->vcpu_id, 2994 st->preempted & KVM_VCPU_FLUSH_TLB); 2995 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB) 2996 kvm_vcpu_flush_tlb_guest(vcpu); 2997 } 2998 2999 vcpu->arch.st.preempted = 0; 3000 3001 if (st->version & 1) 3002 st->version += 1; /* first time write, random junk */ 3003 3004 st->version += 1; 3005 3006 smp_wmb(); 3007 3008 st->steal += current->sched_info.run_delay - 3009 vcpu->arch.st.last_steal; 3010 vcpu->arch.st.last_steal = current->sched_info.run_delay; 3011 3012 smp_wmb(); 3013 3014 st->version += 1; 3015 3016 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); 3017 } 3018 3019 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3020 { 3021 bool pr = false; 3022 u32 msr = msr_info->index; 3023 u64 data = msr_info->data; 3024 3025 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) 3026 return kvm_xen_write_hypercall_page(vcpu, data); 3027 3028 switch (msr) { 3029 case MSR_AMD64_NB_CFG: 3030 case MSR_IA32_UCODE_WRITE: 3031 case MSR_VM_HSAVE_PA: 3032 case MSR_AMD64_PATCH_LOADER: 3033 case MSR_AMD64_BU_CFG2: 3034 case MSR_AMD64_DC_CFG: 3035 case MSR_F15H_EX_CFG: 3036 break; 3037 3038 case MSR_IA32_UCODE_REV: 3039 if (msr_info->host_initiated) 3040 vcpu->arch.microcode_version = data; 3041 break; 3042 case MSR_IA32_ARCH_CAPABILITIES: 3043 if (!msr_info->host_initiated) 3044 return 1; 3045 vcpu->arch.arch_capabilities = data; 3046 break; 3047 case MSR_IA32_PERF_CAPABILITIES: { 3048 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; 3049 3050 if (!msr_info->host_initiated) 3051 return 1; 3052 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent)) 3053 return 1; 3054 if (data & ~msr_ent.data) 3055 return 1; 3056 3057 vcpu->arch.perf_capabilities = data; 3058 3059 return 0; 3060 } 3061 case MSR_EFER: 3062 return set_efer(vcpu, msr_info); 3063 case MSR_K7_HWCR: 3064 data &= ~(u64)0x40; /* ignore flush filter disable */ 3065 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 3066 data &= ~(u64)0x8; /* ignore TLB cache disable */ 3067 3068 /* Handle McStatusWrEn */ 3069 if (data == BIT_ULL(18)) { 3070 vcpu->arch.msr_hwcr = data; 3071 } else if (data != 0) { 3072 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 3073 data); 3074 return 1; 3075 } 3076 break; 3077 case MSR_FAM10H_MMIO_CONF_BASE: 3078 if (data != 0) { 3079 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 3080 "0x%llx\n", data); 3081 return 1; 3082 } 3083 break; 3084 case 0x200 ... 0x2ff: 3085 return kvm_mtrr_set_msr(vcpu, msr, data); 3086 case MSR_IA32_APICBASE: 3087 return kvm_set_apic_base(vcpu, msr_info); 3088 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3089 return kvm_x2apic_msr_write(vcpu, msr, data); 3090 case MSR_IA32_TSCDEADLINE: 3091 kvm_set_lapic_tscdeadline_msr(vcpu, data); 3092 break; 3093 case MSR_IA32_TSC_ADJUST: 3094 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 3095 if (!msr_info->host_initiated) { 3096 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 3097 adjust_tsc_offset_guest(vcpu, adj); 3098 } 3099 vcpu->arch.ia32_tsc_adjust_msr = data; 3100 } 3101 break; 3102 case MSR_IA32_MISC_ENABLE: 3103 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && 3104 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { 3105 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) 3106 return 1; 3107 vcpu->arch.ia32_misc_enable_msr = data; 3108 kvm_update_cpuid_runtime(vcpu); 3109 } else { 3110 vcpu->arch.ia32_misc_enable_msr = data; 3111 } 3112 break; 3113 case MSR_IA32_SMBASE: 3114 if (!msr_info->host_initiated) 3115 return 1; 3116 vcpu->arch.smbase = data; 3117 break; 3118 case MSR_IA32_POWER_CTL: 3119 vcpu->arch.msr_ia32_power_ctl = data; 3120 break; 3121 case MSR_IA32_TSC: 3122 if (msr_info->host_initiated) { 3123 kvm_synchronize_tsc(vcpu, data); 3124 } else { 3125 u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; 3126 adjust_tsc_offset_guest(vcpu, adj); 3127 vcpu->arch.ia32_tsc_adjust_msr += adj; 3128 } 3129 break; 3130 case MSR_IA32_XSS: 3131 if (!msr_info->host_initiated && 3132 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3133 return 1; 3134 /* 3135 * KVM supports exposing PT to the guest, but does not support 3136 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than 3137 * XSAVES/XRSTORS to save/restore PT MSRs. 3138 */ 3139 if (data & ~supported_xss) 3140 return 1; 3141 vcpu->arch.ia32_xss = data; 3142 break; 3143 case MSR_SMI_COUNT: 3144 if (!msr_info->host_initiated) 3145 return 1; 3146 vcpu->arch.smi_count = data; 3147 break; 3148 case MSR_KVM_WALL_CLOCK_NEW: 3149 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3150 return 1; 3151 3152 vcpu->kvm->arch.wall_clock = data; 3153 kvm_write_wall_clock(vcpu->kvm, data, 0); 3154 break; 3155 case MSR_KVM_WALL_CLOCK: 3156 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3157 return 1; 3158 3159 vcpu->kvm->arch.wall_clock = data; 3160 kvm_write_wall_clock(vcpu->kvm, data, 0); 3161 break; 3162 case MSR_KVM_SYSTEM_TIME_NEW: 3163 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3164 return 1; 3165 3166 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); 3167 break; 3168 case MSR_KVM_SYSTEM_TIME: 3169 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3170 return 1; 3171 3172 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); 3173 break; 3174 case MSR_KVM_ASYNC_PF_EN: 3175 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3176 return 1; 3177 3178 if (kvm_pv_enable_async_pf(vcpu, data)) 3179 return 1; 3180 break; 3181 case MSR_KVM_ASYNC_PF_INT: 3182 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3183 return 1; 3184 3185 if (kvm_pv_enable_async_pf_int(vcpu, data)) 3186 return 1; 3187 break; 3188 case MSR_KVM_ASYNC_PF_ACK: 3189 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3190 return 1; 3191 if (data & 0x1) { 3192 vcpu->arch.apf.pageready_pending = false; 3193 kvm_check_async_pf_completion(vcpu); 3194 } 3195 break; 3196 case MSR_KVM_STEAL_TIME: 3197 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3198 return 1; 3199 3200 if (unlikely(!sched_info_on())) 3201 return 1; 3202 3203 if (data & KVM_STEAL_RESERVED_MASK) 3204 return 1; 3205 3206 vcpu->arch.st.msr_val = data; 3207 3208 if (!(data & KVM_MSR_ENABLED)) 3209 break; 3210 3211 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3212 3213 break; 3214 case MSR_KVM_PV_EOI_EN: 3215 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3216 return 1; 3217 3218 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) 3219 return 1; 3220 break; 3221 3222 case MSR_KVM_POLL_CONTROL: 3223 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3224 return 1; 3225 3226 /* only enable bit supported */ 3227 if (data & (-1ULL << 1)) 3228 return 1; 3229 3230 vcpu->arch.msr_kvm_poll_control = data; 3231 break; 3232 3233 case MSR_IA32_MCG_CTL: 3234 case MSR_IA32_MCG_STATUS: 3235 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3236 return set_msr_mce(vcpu, msr_info); 3237 3238 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3239 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3240 pr = true; 3241 fallthrough; 3242 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3243 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3244 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3245 return kvm_pmu_set_msr(vcpu, msr_info); 3246 3247 if (pr || data != 0) 3248 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 3249 "0x%x data 0x%llx\n", msr, data); 3250 break; 3251 case MSR_K7_CLK_CTL: 3252 /* 3253 * Ignore all writes to this no longer documented MSR. 3254 * Writes are only relevant for old K7 processors, 3255 * all pre-dating SVM, but a recommended workaround from 3256 * AMD for these chips. It is possible to specify the 3257 * affected processor models on the command line, hence 3258 * the need to ignore the workaround. 3259 */ 3260 break; 3261 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3262 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3263 case HV_X64_MSR_SYNDBG_OPTIONS: 3264 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3265 case HV_X64_MSR_CRASH_CTL: 3266 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3267 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3268 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3269 case HV_X64_MSR_TSC_EMULATION_STATUS: 3270 return kvm_hv_set_msr_common(vcpu, msr, data, 3271 msr_info->host_initiated); 3272 case MSR_IA32_BBL_CR_CTL3: 3273 /* Drop writes to this legacy MSR -- see rdmsr 3274 * counterpart for further detail. 3275 */ 3276 if (report_ignored_msrs) 3277 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 3278 msr, data); 3279 break; 3280 case MSR_AMD64_OSVW_ID_LENGTH: 3281 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3282 return 1; 3283 vcpu->arch.osvw.length = data; 3284 break; 3285 case MSR_AMD64_OSVW_STATUS: 3286 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3287 return 1; 3288 vcpu->arch.osvw.status = data; 3289 break; 3290 case MSR_PLATFORM_INFO: 3291 if (!msr_info->host_initiated || 3292 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 3293 cpuid_fault_enabled(vcpu))) 3294 return 1; 3295 vcpu->arch.msr_platform_info = data; 3296 break; 3297 case MSR_MISC_FEATURES_ENABLES: 3298 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 3299 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3300 !supports_cpuid_fault(vcpu))) 3301 return 1; 3302 vcpu->arch.msr_misc_features_enables = data; 3303 break; 3304 default: 3305 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3306 return kvm_pmu_set_msr(vcpu, msr_info); 3307 return KVM_MSR_RET_INVALID; 3308 } 3309 return 0; 3310 } 3311 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 3312 3313 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 3314 { 3315 u64 data; 3316 u64 mcg_cap = vcpu->arch.mcg_cap; 3317 unsigned bank_num = mcg_cap & 0xff; 3318 3319 switch (msr) { 3320 case MSR_IA32_P5_MC_ADDR: 3321 case MSR_IA32_P5_MC_TYPE: 3322 data = 0; 3323 break; 3324 case MSR_IA32_MCG_CAP: 3325 data = vcpu->arch.mcg_cap; 3326 break; 3327 case MSR_IA32_MCG_CTL: 3328 if (!(mcg_cap & MCG_CTL_P) && !host) 3329 return 1; 3330 data = vcpu->arch.mcg_ctl; 3331 break; 3332 case MSR_IA32_MCG_STATUS: 3333 data = vcpu->arch.mcg_status; 3334 break; 3335 default: 3336 if (msr >= MSR_IA32_MC0_CTL && 3337 msr < MSR_IA32_MCx_CTL(bank_num)) { 3338 u32 offset = array_index_nospec( 3339 msr - MSR_IA32_MC0_CTL, 3340 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3341 3342 data = vcpu->arch.mce_banks[offset]; 3343 break; 3344 } 3345 return 1; 3346 } 3347 *pdata = data; 3348 return 0; 3349 } 3350 3351 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3352 { 3353 switch (msr_info->index) { 3354 case MSR_IA32_PLATFORM_ID: 3355 case MSR_IA32_EBL_CR_POWERON: 3356 case MSR_IA32_LASTBRANCHFROMIP: 3357 case MSR_IA32_LASTBRANCHTOIP: 3358 case MSR_IA32_LASTINTFROMIP: 3359 case MSR_IA32_LASTINTTOIP: 3360 case MSR_K8_SYSCFG: 3361 case MSR_K8_TSEG_ADDR: 3362 case MSR_K8_TSEG_MASK: 3363 case MSR_VM_HSAVE_PA: 3364 case MSR_K8_INT_PENDING_MSG: 3365 case MSR_AMD64_NB_CFG: 3366 case MSR_FAM10H_MMIO_CONF_BASE: 3367 case MSR_AMD64_BU_CFG2: 3368 case MSR_IA32_PERF_CTL: 3369 case MSR_AMD64_DC_CFG: 3370 case MSR_F15H_EX_CFG: 3371 /* 3372 * Intel Sandy Bridge CPUs must support the RAPL (running average power 3373 * limit) MSRs. Just return 0, as we do not want to expose the host 3374 * data here. Do not conditionalize this on CPUID, as KVM does not do 3375 * so for existing CPU-specific MSRs. 3376 */ 3377 case MSR_RAPL_POWER_UNIT: 3378 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ 3379 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ 3380 case MSR_PKG_ENERGY_STATUS: /* Total package */ 3381 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ 3382 msr_info->data = 0; 3383 break; 3384 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3385 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3386 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3387 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3388 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3389 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3390 return kvm_pmu_get_msr(vcpu, msr_info); 3391 msr_info->data = 0; 3392 break; 3393 case MSR_IA32_UCODE_REV: 3394 msr_info->data = vcpu->arch.microcode_version; 3395 break; 3396 case MSR_IA32_ARCH_CAPABILITIES: 3397 if (!msr_info->host_initiated && 3398 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 3399 return 1; 3400 msr_info->data = vcpu->arch.arch_capabilities; 3401 break; 3402 case MSR_IA32_PERF_CAPABILITIES: 3403 if (!msr_info->host_initiated && 3404 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) 3405 return 1; 3406 msr_info->data = vcpu->arch.perf_capabilities; 3407 break; 3408 case MSR_IA32_POWER_CTL: 3409 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 3410 break; 3411 case MSR_IA32_TSC: { 3412 /* 3413 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset 3414 * even when not intercepted. AMD manual doesn't explicitly 3415 * state this but appears to behave the same. 3416 * 3417 * On userspace reads and writes, however, we unconditionally 3418 * return L1's TSC value to ensure backwards-compatible 3419 * behavior for migration. 3420 */ 3421 u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset : 3422 vcpu->arch.tsc_offset; 3423 3424 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset; 3425 break; 3426 } 3427 case MSR_MTRRcap: 3428 case 0x200 ... 0x2ff: 3429 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 3430 case 0xcd: /* fsb frequency */ 3431 msr_info->data = 3; 3432 break; 3433 /* 3434 * MSR_EBC_FREQUENCY_ID 3435 * Conservative value valid for even the basic CPU models. 3436 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 3437 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 3438 * and 266MHz for model 3, or 4. Set Core Clock 3439 * Frequency to System Bus Frequency Ratio to 1 (bits 3440 * 31:24) even though these are only valid for CPU 3441 * models > 2, however guests may end up dividing or 3442 * multiplying by zero otherwise. 3443 */ 3444 case MSR_EBC_FREQUENCY_ID: 3445 msr_info->data = 1 << 24; 3446 break; 3447 case MSR_IA32_APICBASE: 3448 msr_info->data = kvm_get_apic_base(vcpu); 3449 break; 3450 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3451 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 3452 case MSR_IA32_TSCDEADLINE: 3453 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 3454 break; 3455 case MSR_IA32_TSC_ADJUST: 3456 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 3457 break; 3458 case MSR_IA32_MISC_ENABLE: 3459 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 3460 break; 3461 case MSR_IA32_SMBASE: 3462 if (!msr_info->host_initiated) 3463 return 1; 3464 msr_info->data = vcpu->arch.smbase; 3465 break; 3466 case MSR_SMI_COUNT: 3467 msr_info->data = vcpu->arch.smi_count; 3468 break; 3469 case MSR_IA32_PERF_STATUS: 3470 /* TSC increment by tick */ 3471 msr_info->data = 1000ULL; 3472 /* CPU multiplier */ 3473 msr_info->data |= (((uint64_t)4ULL) << 40); 3474 break; 3475 case MSR_EFER: 3476 msr_info->data = vcpu->arch.efer; 3477 break; 3478 case MSR_KVM_WALL_CLOCK: 3479 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3480 return 1; 3481 3482 msr_info->data = vcpu->kvm->arch.wall_clock; 3483 break; 3484 case MSR_KVM_WALL_CLOCK_NEW: 3485 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3486 return 1; 3487 3488 msr_info->data = vcpu->kvm->arch.wall_clock; 3489 break; 3490 case MSR_KVM_SYSTEM_TIME: 3491 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3492 return 1; 3493 3494 msr_info->data = vcpu->arch.time; 3495 break; 3496 case MSR_KVM_SYSTEM_TIME_NEW: 3497 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3498 return 1; 3499 3500 msr_info->data = vcpu->arch.time; 3501 break; 3502 case MSR_KVM_ASYNC_PF_EN: 3503 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3504 return 1; 3505 3506 msr_info->data = vcpu->arch.apf.msr_en_val; 3507 break; 3508 case MSR_KVM_ASYNC_PF_INT: 3509 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3510 return 1; 3511 3512 msr_info->data = vcpu->arch.apf.msr_int_val; 3513 break; 3514 case MSR_KVM_ASYNC_PF_ACK: 3515 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3516 return 1; 3517 3518 msr_info->data = 0; 3519 break; 3520 case MSR_KVM_STEAL_TIME: 3521 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3522 return 1; 3523 3524 msr_info->data = vcpu->arch.st.msr_val; 3525 break; 3526 case MSR_KVM_PV_EOI_EN: 3527 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3528 return 1; 3529 3530 msr_info->data = vcpu->arch.pv_eoi.msr_val; 3531 break; 3532 case MSR_KVM_POLL_CONTROL: 3533 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3534 return 1; 3535 3536 msr_info->data = vcpu->arch.msr_kvm_poll_control; 3537 break; 3538 case MSR_IA32_P5_MC_ADDR: 3539 case MSR_IA32_P5_MC_TYPE: 3540 case MSR_IA32_MCG_CAP: 3541 case MSR_IA32_MCG_CTL: 3542 case MSR_IA32_MCG_STATUS: 3543 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3544 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 3545 msr_info->host_initiated); 3546 case MSR_IA32_XSS: 3547 if (!msr_info->host_initiated && 3548 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3549 return 1; 3550 msr_info->data = vcpu->arch.ia32_xss; 3551 break; 3552 case MSR_K7_CLK_CTL: 3553 /* 3554 * Provide expected ramp-up count for K7. All other 3555 * are set to zero, indicating minimum divisors for 3556 * every field. 3557 * 3558 * This prevents guest kernels on AMD host with CPU 3559 * type 6, model 8 and higher from exploding due to 3560 * the rdmsr failing. 3561 */ 3562 msr_info->data = 0x20000000; 3563 break; 3564 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3565 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3566 case HV_X64_MSR_SYNDBG_OPTIONS: 3567 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3568 case HV_X64_MSR_CRASH_CTL: 3569 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3570 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3571 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3572 case HV_X64_MSR_TSC_EMULATION_STATUS: 3573 return kvm_hv_get_msr_common(vcpu, 3574 msr_info->index, &msr_info->data, 3575 msr_info->host_initiated); 3576 case MSR_IA32_BBL_CR_CTL3: 3577 /* This legacy MSR exists but isn't fully documented in current 3578 * silicon. It is however accessed by winxp in very narrow 3579 * scenarios where it sets bit #19, itself documented as 3580 * a "reserved" bit. Best effort attempt to source coherent 3581 * read data here should the balance of the register be 3582 * interpreted by the guest: 3583 * 3584 * L2 cache control register 3: 64GB range, 256KB size, 3585 * enabled, latency 0x1, configured 3586 */ 3587 msr_info->data = 0xbe702111; 3588 break; 3589 case MSR_AMD64_OSVW_ID_LENGTH: 3590 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3591 return 1; 3592 msr_info->data = vcpu->arch.osvw.length; 3593 break; 3594 case MSR_AMD64_OSVW_STATUS: 3595 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3596 return 1; 3597 msr_info->data = vcpu->arch.osvw.status; 3598 break; 3599 case MSR_PLATFORM_INFO: 3600 if (!msr_info->host_initiated && 3601 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 3602 return 1; 3603 msr_info->data = vcpu->arch.msr_platform_info; 3604 break; 3605 case MSR_MISC_FEATURES_ENABLES: 3606 msr_info->data = vcpu->arch.msr_misc_features_enables; 3607 break; 3608 case MSR_K7_HWCR: 3609 msr_info->data = vcpu->arch.msr_hwcr; 3610 break; 3611 default: 3612 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3613 return kvm_pmu_get_msr(vcpu, msr_info); 3614 return KVM_MSR_RET_INVALID; 3615 } 3616 return 0; 3617 } 3618 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 3619 3620 /* 3621 * Read or write a bunch of msrs. All parameters are kernel addresses. 3622 * 3623 * @return number of msrs set successfully. 3624 */ 3625 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 3626 struct kvm_msr_entry *entries, 3627 int (*do_msr)(struct kvm_vcpu *vcpu, 3628 unsigned index, u64 *data)) 3629 { 3630 int i; 3631 3632 for (i = 0; i < msrs->nmsrs; ++i) 3633 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 3634 break; 3635 3636 return i; 3637 } 3638 3639 /* 3640 * Read or write a bunch of msrs. Parameters are user addresses. 3641 * 3642 * @return number of msrs set successfully. 3643 */ 3644 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 3645 int (*do_msr)(struct kvm_vcpu *vcpu, 3646 unsigned index, u64 *data), 3647 int writeback) 3648 { 3649 struct kvm_msrs msrs; 3650 struct kvm_msr_entry *entries; 3651 int r, n; 3652 unsigned size; 3653 3654 r = -EFAULT; 3655 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 3656 goto out; 3657 3658 r = -E2BIG; 3659 if (msrs.nmsrs >= MAX_IO_MSRS) 3660 goto out; 3661 3662 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 3663 entries = memdup_user(user_msrs->entries, size); 3664 if (IS_ERR(entries)) { 3665 r = PTR_ERR(entries); 3666 goto out; 3667 } 3668 3669 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 3670 if (r < 0) 3671 goto out_free; 3672 3673 r = -EFAULT; 3674 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 3675 goto out_free; 3676 3677 r = n; 3678 3679 out_free: 3680 kfree(entries); 3681 out: 3682 return r; 3683 } 3684 3685 static inline bool kvm_can_mwait_in_guest(void) 3686 { 3687 return boot_cpu_has(X86_FEATURE_MWAIT) && 3688 !boot_cpu_has_bug(X86_BUG_MONITOR) && 3689 boot_cpu_has(X86_FEATURE_ARAT); 3690 } 3691 3692 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, 3693 struct kvm_cpuid2 __user *cpuid_arg) 3694 { 3695 struct kvm_cpuid2 cpuid; 3696 int r; 3697 3698 r = -EFAULT; 3699 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3700 return r; 3701 3702 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3703 if (r) 3704 return r; 3705 3706 r = -EFAULT; 3707 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 3708 return r; 3709 3710 return 0; 3711 } 3712 3713 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 3714 { 3715 int r = 0; 3716 3717 switch (ext) { 3718 case KVM_CAP_IRQCHIP: 3719 case KVM_CAP_HLT: 3720 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 3721 case KVM_CAP_SET_TSS_ADDR: 3722 case KVM_CAP_EXT_CPUID: 3723 case KVM_CAP_EXT_EMUL_CPUID: 3724 case KVM_CAP_CLOCKSOURCE: 3725 case KVM_CAP_PIT: 3726 case KVM_CAP_NOP_IO_DELAY: 3727 case KVM_CAP_MP_STATE: 3728 case KVM_CAP_SYNC_MMU: 3729 case KVM_CAP_USER_NMI: 3730 case KVM_CAP_REINJECT_CONTROL: 3731 case KVM_CAP_IRQ_INJECT_STATUS: 3732 case KVM_CAP_IOEVENTFD: 3733 case KVM_CAP_IOEVENTFD_NO_LENGTH: 3734 case KVM_CAP_PIT2: 3735 case KVM_CAP_PIT_STATE2: 3736 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 3737 case KVM_CAP_VCPU_EVENTS: 3738 case KVM_CAP_HYPERV: 3739 case KVM_CAP_HYPERV_VAPIC: 3740 case KVM_CAP_HYPERV_SPIN: 3741 case KVM_CAP_HYPERV_SYNIC: 3742 case KVM_CAP_HYPERV_SYNIC2: 3743 case KVM_CAP_HYPERV_VP_INDEX: 3744 case KVM_CAP_HYPERV_EVENTFD: 3745 case KVM_CAP_HYPERV_TLBFLUSH: 3746 case KVM_CAP_HYPERV_SEND_IPI: 3747 case KVM_CAP_HYPERV_CPUID: 3748 case KVM_CAP_SYS_HYPERV_CPUID: 3749 case KVM_CAP_PCI_SEGMENT: 3750 case KVM_CAP_DEBUGREGS: 3751 case KVM_CAP_X86_ROBUST_SINGLESTEP: 3752 case KVM_CAP_XSAVE: 3753 case KVM_CAP_ASYNC_PF: 3754 case KVM_CAP_ASYNC_PF_INT: 3755 case KVM_CAP_GET_TSC_KHZ: 3756 case KVM_CAP_KVMCLOCK_CTRL: 3757 case KVM_CAP_READONLY_MEM: 3758 case KVM_CAP_HYPERV_TIME: 3759 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 3760 case KVM_CAP_TSC_DEADLINE_TIMER: 3761 case KVM_CAP_DISABLE_QUIRKS: 3762 case KVM_CAP_SET_BOOT_CPU_ID: 3763 case KVM_CAP_SPLIT_IRQCHIP: 3764 case KVM_CAP_IMMEDIATE_EXIT: 3765 case KVM_CAP_PMU_EVENT_FILTER: 3766 case KVM_CAP_GET_MSR_FEATURES: 3767 case KVM_CAP_MSR_PLATFORM_INFO: 3768 case KVM_CAP_EXCEPTION_PAYLOAD: 3769 case KVM_CAP_SET_GUEST_DEBUG: 3770 case KVM_CAP_LAST_CPU: 3771 case KVM_CAP_X86_USER_SPACE_MSR: 3772 case KVM_CAP_X86_MSR_FILTER: 3773 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 3774 r = 1; 3775 break; 3776 #ifdef CONFIG_KVM_XEN 3777 case KVM_CAP_XEN_HVM: 3778 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | 3779 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | 3780 KVM_XEN_HVM_CONFIG_SHARED_INFO; 3781 if (sched_info_on()) 3782 r |= KVM_XEN_HVM_CONFIG_RUNSTATE; 3783 break; 3784 #endif 3785 case KVM_CAP_SYNC_REGS: 3786 r = KVM_SYNC_X86_VALID_FIELDS; 3787 break; 3788 case KVM_CAP_ADJUST_CLOCK: 3789 r = KVM_CLOCK_TSC_STABLE; 3790 break; 3791 case KVM_CAP_X86_DISABLE_EXITS: 3792 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | 3793 KVM_X86_DISABLE_EXITS_CSTATE; 3794 if(kvm_can_mwait_in_guest()) 3795 r |= KVM_X86_DISABLE_EXITS_MWAIT; 3796 break; 3797 case KVM_CAP_X86_SMM: 3798 /* SMBASE is usually relocated above 1M on modern chipsets, 3799 * and SMM handlers might indeed rely on 4G segment limits, 3800 * so do not report SMM to be available if real mode is 3801 * emulated via vm86 mode. Still, do not go to great lengths 3802 * to avoid userspace's usage of the feature, because it is a 3803 * fringe case that is not enabled except via specific settings 3804 * of the module parameters. 3805 */ 3806 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); 3807 break; 3808 case KVM_CAP_VAPIC: 3809 r = !static_call(kvm_x86_cpu_has_accelerated_tpr)(); 3810 break; 3811 case KVM_CAP_NR_VCPUS: 3812 r = KVM_SOFT_MAX_VCPUS; 3813 break; 3814 case KVM_CAP_MAX_VCPUS: 3815 r = KVM_MAX_VCPUS; 3816 break; 3817 case KVM_CAP_MAX_VCPU_ID: 3818 r = KVM_MAX_VCPU_ID; 3819 break; 3820 case KVM_CAP_PV_MMU: /* obsolete */ 3821 r = 0; 3822 break; 3823 case KVM_CAP_MCE: 3824 r = KVM_MAX_MCE_BANKS; 3825 break; 3826 case KVM_CAP_XCRS: 3827 r = boot_cpu_has(X86_FEATURE_XSAVE); 3828 break; 3829 case KVM_CAP_TSC_CONTROL: 3830 r = kvm_has_tsc_control; 3831 break; 3832 case KVM_CAP_X2APIC_API: 3833 r = KVM_X2APIC_API_VALID_FLAGS; 3834 break; 3835 case KVM_CAP_NESTED_STATE: 3836 r = kvm_x86_ops.nested_ops->get_state ? 3837 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; 3838 break; 3839 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 3840 r = kvm_x86_ops.enable_direct_tlbflush != NULL; 3841 break; 3842 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 3843 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; 3844 break; 3845 case KVM_CAP_SMALLER_MAXPHYADDR: 3846 r = (int) allow_smaller_maxphyaddr; 3847 break; 3848 case KVM_CAP_STEAL_TIME: 3849 r = sched_info_on(); 3850 break; 3851 case KVM_CAP_X86_BUS_LOCK_EXIT: 3852 if (kvm_has_bus_lock_exit) 3853 r = KVM_BUS_LOCK_DETECTION_OFF | 3854 KVM_BUS_LOCK_DETECTION_EXIT; 3855 else 3856 r = 0; 3857 break; 3858 default: 3859 break; 3860 } 3861 return r; 3862 3863 } 3864 3865 long kvm_arch_dev_ioctl(struct file *filp, 3866 unsigned int ioctl, unsigned long arg) 3867 { 3868 void __user *argp = (void __user *)arg; 3869 long r; 3870 3871 switch (ioctl) { 3872 case KVM_GET_MSR_INDEX_LIST: { 3873 struct kvm_msr_list __user *user_msr_list = argp; 3874 struct kvm_msr_list msr_list; 3875 unsigned n; 3876 3877 r = -EFAULT; 3878 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3879 goto out; 3880 n = msr_list.nmsrs; 3881 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 3882 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3883 goto out; 3884 r = -E2BIG; 3885 if (n < msr_list.nmsrs) 3886 goto out; 3887 r = -EFAULT; 3888 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 3889 num_msrs_to_save * sizeof(u32))) 3890 goto out; 3891 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 3892 &emulated_msrs, 3893 num_emulated_msrs * sizeof(u32))) 3894 goto out; 3895 r = 0; 3896 break; 3897 } 3898 case KVM_GET_SUPPORTED_CPUID: 3899 case KVM_GET_EMULATED_CPUID: { 3900 struct kvm_cpuid2 __user *cpuid_arg = argp; 3901 struct kvm_cpuid2 cpuid; 3902 3903 r = -EFAULT; 3904 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3905 goto out; 3906 3907 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 3908 ioctl); 3909 if (r) 3910 goto out; 3911 3912 r = -EFAULT; 3913 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 3914 goto out; 3915 r = 0; 3916 break; 3917 } 3918 case KVM_X86_GET_MCE_CAP_SUPPORTED: 3919 r = -EFAULT; 3920 if (copy_to_user(argp, &kvm_mce_cap_supported, 3921 sizeof(kvm_mce_cap_supported))) 3922 goto out; 3923 r = 0; 3924 break; 3925 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 3926 struct kvm_msr_list __user *user_msr_list = argp; 3927 struct kvm_msr_list msr_list; 3928 unsigned int n; 3929 3930 r = -EFAULT; 3931 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3932 goto out; 3933 n = msr_list.nmsrs; 3934 msr_list.nmsrs = num_msr_based_features; 3935 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3936 goto out; 3937 r = -E2BIG; 3938 if (n < msr_list.nmsrs) 3939 goto out; 3940 r = -EFAULT; 3941 if (copy_to_user(user_msr_list->indices, &msr_based_features, 3942 num_msr_based_features * sizeof(u32))) 3943 goto out; 3944 r = 0; 3945 break; 3946 } 3947 case KVM_GET_MSRS: 3948 r = msr_io(NULL, argp, do_get_msr_feature, 1); 3949 break; 3950 case KVM_GET_SUPPORTED_HV_CPUID: 3951 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); 3952 break; 3953 default: 3954 r = -EINVAL; 3955 break; 3956 } 3957 out: 3958 return r; 3959 } 3960 3961 static void wbinvd_ipi(void *garbage) 3962 { 3963 wbinvd(); 3964 } 3965 3966 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 3967 { 3968 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 3969 } 3970 3971 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 3972 { 3973 /* Address WBINVD may be executed by guest */ 3974 if (need_emulate_wbinvd(vcpu)) { 3975 if (static_call(kvm_x86_has_wbinvd_exit)()) 3976 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 3977 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 3978 smp_call_function_single(vcpu->cpu, 3979 wbinvd_ipi, NULL, 1); 3980 } 3981 3982 static_call(kvm_x86_vcpu_load)(vcpu, cpu); 3983 3984 /* Save host pkru register if supported */ 3985 vcpu->arch.host_pkru = read_pkru(); 3986 3987 /* Apply any externally detected TSC adjustments (due to suspend) */ 3988 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 3989 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 3990 vcpu->arch.tsc_offset_adjustment = 0; 3991 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3992 } 3993 3994 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 3995 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 3996 rdtsc() - vcpu->arch.last_host_tsc; 3997 if (tsc_delta < 0) 3998 mark_tsc_unstable("KVM discovered backwards TSC"); 3999 4000 if (kvm_check_tsc_unstable()) { 4001 u64 offset = kvm_compute_tsc_offset(vcpu, 4002 vcpu->arch.last_guest_tsc); 4003 kvm_vcpu_write_tsc_offset(vcpu, offset); 4004 vcpu->arch.tsc_catchup = 1; 4005 } 4006 4007 if (kvm_lapic_hv_timer_in_use(vcpu)) 4008 kvm_lapic_restart_hv_timer(vcpu); 4009 4010 /* 4011 * On a host with synchronized TSC, there is no need to update 4012 * kvmclock on vcpu->cpu migration 4013 */ 4014 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 4015 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 4016 if (vcpu->cpu != cpu) 4017 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 4018 vcpu->cpu = cpu; 4019 } 4020 4021 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 4022 } 4023 4024 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 4025 { 4026 struct kvm_host_map map; 4027 struct kvm_steal_time *st; 4028 int idx; 4029 4030 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 4031 return; 4032 4033 if (vcpu->arch.st.preempted) 4034 return; 4035 4036 /* 4037 * Take the srcu lock as memslots will be accessed to check the gfn 4038 * cache generation against the memslots generation. 4039 */ 4040 idx = srcu_read_lock(&vcpu->kvm->srcu); 4041 4042 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, 4043 &vcpu->arch.st.cache, true)) 4044 goto out; 4045 4046 st = map.hva + 4047 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 4048 4049 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 4050 4051 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); 4052 4053 out: 4054 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4055 } 4056 4057 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 4058 { 4059 if (vcpu->preempted && !vcpu->arch.guest_state_protected) 4060 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); 4061 4062 if (kvm_xen_msr_enabled(vcpu->kvm)) 4063 kvm_xen_runstate_set_preempted(vcpu); 4064 else 4065 kvm_steal_time_set_preempted(vcpu); 4066 4067 static_call(kvm_x86_vcpu_put)(vcpu); 4068 vcpu->arch.last_host_tsc = rdtsc(); 4069 /* 4070 * If userspace has set any breakpoints or watchpoints, dr6 is restored 4071 * on every vmexit, but if not, we might have a stale dr6 from the 4072 * guest. do_debug expects dr6 to be cleared after it runs, do the same. 4073 */ 4074 set_debugreg(0, 6); 4075 } 4076 4077 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 4078 struct kvm_lapic_state *s) 4079 { 4080 if (vcpu->arch.apicv_active) 4081 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 4082 4083 return kvm_apic_get_state(vcpu, s); 4084 } 4085 4086 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 4087 struct kvm_lapic_state *s) 4088 { 4089 int r; 4090 4091 r = kvm_apic_set_state(vcpu, s); 4092 if (r) 4093 return r; 4094 update_cr8_intercept(vcpu); 4095 4096 return 0; 4097 } 4098 4099 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 4100 { 4101 /* 4102 * We can accept userspace's request for interrupt injection 4103 * as long as we have a place to store the interrupt number. 4104 * The actual injection will happen when the CPU is able to 4105 * deliver the interrupt. 4106 */ 4107 if (kvm_cpu_has_extint(vcpu)) 4108 return false; 4109 4110 /* Acknowledging ExtINT does not happen if LINT0 is masked. */ 4111 return (!lapic_in_kernel(vcpu) || 4112 kvm_apic_accept_pic_intr(vcpu)); 4113 } 4114 4115 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 4116 { 4117 return kvm_arch_interrupt_allowed(vcpu) && 4118 kvm_cpu_accept_dm_intr(vcpu); 4119 } 4120 4121 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 4122 struct kvm_interrupt *irq) 4123 { 4124 if (irq->irq >= KVM_NR_INTERRUPTS) 4125 return -EINVAL; 4126 4127 if (!irqchip_in_kernel(vcpu->kvm)) { 4128 kvm_queue_interrupt(vcpu, irq->irq, false); 4129 kvm_make_request(KVM_REQ_EVENT, vcpu); 4130 return 0; 4131 } 4132 4133 /* 4134 * With in-kernel LAPIC, we only use this to inject EXTINT, so 4135 * fail for in-kernel 8259. 4136 */ 4137 if (pic_in_kernel(vcpu->kvm)) 4138 return -ENXIO; 4139 4140 if (vcpu->arch.pending_external_vector != -1) 4141 return -EEXIST; 4142 4143 vcpu->arch.pending_external_vector = irq->irq; 4144 kvm_make_request(KVM_REQ_EVENT, vcpu); 4145 return 0; 4146 } 4147 4148 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 4149 { 4150 kvm_inject_nmi(vcpu); 4151 4152 return 0; 4153 } 4154 4155 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 4156 { 4157 kvm_make_request(KVM_REQ_SMI, vcpu); 4158 4159 return 0; 4160 } 4161 4162 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 4163 struct kvm_tpr_access_ctl *tac) 4164 { 4165 if (tac->flags) 4166 return -EINVAL; 4167 vcpu->arch.tpr_access_reporting = !!tac->enabled; 4168 return 0; 4169 } 4170 4171 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 4172 u64 mcg_cap) 4173 { 4174 int r; 4175 unsigned bank_num = mcg_cap & 0xff, bank; 4176 4177 r = -EINVAL; 4178 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) 4179 goto out; 4180 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 4181 goto out; 4182 r = 0; 4183 vcpu->arch.mcg_cap = mcg_cap; 4184 /* Init IA32_MCG_CTL to all 1s */ 4185 if (mcg_cap & MCG_CTL_P) 4186 vcpu->arch.mcg_ctl = ~(u64)0; 4187 /* Init IA32_MCi_CTL to all 1s */ 4188 for (bank = 0; bank < bank_num; bank++) 4189 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 4190 4191 static_call(kvm_x86_setup_mce)(vcpu); 4192 out: 4193 return r; 4194 } 4195 4196 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 4197 struct kvm_x86_mce *mce) 4198 { 4199 u64 mcg_cap = vcpu->arch.mcg_cap; 4200 unsigned bank_num = mcg_cap & 0xff; 4201 u64 *banks = vcpu->arch.mce_banks; 4202 4203 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 4204 return -EINVAL; 4205 /* 4206 * if IA32_MCG_CTL is not all 1s, the uncorrected error 4207 * reporting is disabled 4208 */ 4209 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 4210 vcpu->arch.mcg_ctl != ~(u64)0) 4211 return 0; 4212 banks += 4 * mce->bank; 4213 /* 4214 * if IA32_MCi_CTL is not all 1s, the uncorrected error 4215 * reporting is disabled for the bank 4216 */ 4217 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 4218 return 0; 4219 if (mce->status & MCI_STATUS_UC) { 4220 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 4221 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 4222 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 4223 return 0; 4224 } 4225 if (banks[1] & MCI_STATUS_VAL) 4226 mce->status |= MCI_STATUS_OVER; 4227 banks[2] = mce->addr; 4228 banks[3] = mce->misc; 4229 vcpu->arch.mcg_status = mce->mcg_status; 4230 banks[1] = mce->status; 4231 kvm_queue_exception(vcpu, MC_VECTOR); 4232 } else if (!(banks[1] & MCI_STATUS_VAL) 4233 || !(banks[1] & MCI_STATUS_UC)) { 4234 if (banks[1] & MCI_STATUS_VAL) 4235 mce->status |= MCI_STATUS_OVER; 4236 banks[2] = mce->addr; 4237 banks[3] = mce->misc; 4238 banks[1] = mce->status; 4239 } else 4240 banks[1] |= MCI_STATUS_OVER; 4241 return 0; 4242 } 4243 4244 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 4245 struct kvm_vcpu_events *events) 4246 { 4247 process_nmi(vcpu); 4248 4249 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 4250 process_smi(vcpu); 4251 4252 /* 4253 * In guest mode, payload delivery should be deferred, 4254 * so that the L1 hypervisor can intercept #PF before 4255 * CR2 is modified (or intercept #DB before DR6 is 4256 * modified under nVMX). Unless the per-VM capability, 4257 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of 4258 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we 4259 * opportunistically defer the exception payload, deliver it if the 4260 * capability hasn't been requested before processing a 4261 * KVM_GET_VCPU_EVENTS. 4262 */ 4263 if (!vcpu->kvm->arch.exception_payload_enabled && 4264 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) 4265 kvm_deliver_exception_payload(vcpu); 4266 4267 /* 4268 * The API doesn't provide the instruction length for software 4269 * exceptions, so don't report them. As long as the guest RIP 4270 * isn't advanced, we should expect to encounter the exception 4271 * again. 4272 */ 4273 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 4274 events->exception.injected = 0; 4275 events->exception.pending = 0; 4276 } else { 4277 events->exception.injected = vcpu->arch.exception.injected; 4278 events->exception.pending = vcpu->arch.exception.pending; 4279 /* 4280 * For ABI compatibility, deliberately conflate 4281 * pending and injected exceptions when 4282 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 4283 */ 4284 if (!vcpu->kvm->arch.exception_payload_enabled) 4285 events->exception.injected |= 4286 vcpu->arch.exception.pending; 4287 } 4288 events->exception.nr = vcpu->arch.exception.nr; 4289 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 4290 events->exception.error_code = vcpu->arch.exception.error_code; 4291 events->exception_has_payload = vcpu->arch.exception.has_payload; 4292 events->exception_payload = vcpu->arch.exception.payload; 4293 4294 events->interrupt.injected = 4295 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 4296 events->interrupt.nr = vcpu->arch.interrupt.nr; 4297 events->interrupt.soft = 0; 4298 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 4299 4300 events->nmi.injected = vcpu->arch.nmi_injected; 4301 events->nmi.pending = vcpu->arch.nmi_pending != 0; 4302 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); 4303 events->nmi.pad = 0; 4304 4305 events->sipi_vector = 0; /* never valid when reporting to user space */ 4306 4307 events->smi.smm = is_smm(vcpu); 4308 events->smi.pending = vcpu->arch.smi_pending; 4309 events->smi.smm_inside_nmi = 4310 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 4311 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 4312 4313 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 4314 | KVM_VCPUEVENT_VALID_SHADOW 4315 | KVM_VCPUEVENT_VALID_SMM); 4316 if (vcpu->kvm->arch.exception_payload_enabled) 4317 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 4318 4319 memset(&events->reserved, 0, sizeof(events->reserved)); 4320 } 4321 4322 static void kvm_smm_changed(struct kvm_vcpu *vcpu); 4323 4324 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 4325 struct kvm_vcpu_events *events) 4326 { 4327 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 4328 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 4329 | KVM_VCPUEVENT_VALID_SHADOW 4330 | KVM_VCPUEVENT_VALID_SMM 4331 | KVM_VCPUEVENT_VALID_PAYLOAD)) 4332 return -EINVAL; 4333 4334 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 4335 if (!vcpu->kvm->arch.exception_payload_enabled) 4336 return -EINVAL; 4337 if (events->exception.pending) 4338 events->exception.injected = 0; 4339 else 4340 events->exception_has_payload = 0; 4341 } else { 4342 events->exception.pending = 0; 4343 events->exception_has_payload = 0; 4344 } 4345 4346 if ((events->exception.injected || events->exception.pending) && 4347 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 4348 return -EINVAL; 4349 4350 /* INITs are latched while in SMM */ 4351 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 4352 (events->smi.smm || events->smi.pending) && 4353 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 4354 return -EINVAL; 4355 4356 process_nmi(vcpu); 4357 vcpu->arch.exception.injected = events->exception.injected; 4358 vcpu->arch.exception.pending = events->exception.pending; 4359 vcpu->arch.exception.nr = events->exception.nr; 4360 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 4361 vcpu->arch.exception.error_code = events->exception.error_code; 4362 vcpu->arch.exception.has_payload = events->exception_has_payload; 4363 vcpu->arch.exception.payload = events->exception_payload; 4364 4365 vcpu->arch.interrupt.injected = events->interrupt.injected; 4366 vcpu->arch.interrupt.nr = events->interrupt.nr; 4367 vcpu->arch.interrupt.soft = events->interrupt.soft; 4368 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 4369 static_call(kvm_x86_set_interrupt_shadow)(vcpu, 4370 events->interrupt.shadow); 4371 4372 vcpu->arch.nmi_injected = events->nmi.injected; 4373 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 4374 vcpu->arch.nmi_pending = events->nmi.pending; 4375 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); 4376 4377 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 4378 lapic_in_kernel(vcpu)) 4379 vcpu->arch.apic->sipi_vector = events->sipi_vector; 4380 4381 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 4382 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { 4383 if (events->smi.smm) 4384 vcpu->arch.hflags |= HF_SMM_MASK; 4385 else 4386 vcpu->arch.hflags &= ~HF_SMM_MASK; 4387 kvm_smm_changed(vcpu); 4388 } 4389 4390 vcpu->arch.smi_pending = events->smi.pending; 4391 4392 if (events->smi.smm) { 4393 if (events->smi.smm_inside_nmi) 4394 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 4395 else 4396 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 4397 } 4398 4399 if (lapic_in_kernel(vcpu)) { 4400 if (events->smi.latched_init) 4401 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4402 else 4403 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4404 } 4405 } 4406 4407 kvm_make_request(KVM_REQ_EVENT, vcpu); 4408 4409 return 0; 4410 } 4411 4412 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 4413 struct kvm_debugregs *dbgregs) 4414 { 4415 unsigned long val; 4416 4417 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 4418 kvm_get_dr(vcpu, 6, &val); 4419 dbgregs->dr6 = val; 4420 dbgregs->dr7 = vcpu->arch.dr7; 4421 dbgregs->flags = 0; 4422 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 4423 } 4424 4425 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 4426 struct kvm_debugregs *dbgregs) 4427 { 4428 if (dbgregs->flags) 4429 return -EINVAL; 4430 4431 if (!kvm_dr6_valid(dbgregs->dr6)) 4432 return -EINVAL; 4433 if (!kvm_dr7_valid(dbgregs->dr7)) 4434 return -EINVAL; 4435 4436 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 4437 kvm_update_dr0123(vcpu); 4438 vcpu->arch.dr6 = dbgregs->dr6; 4439 vcpu->arch.dr7 = dbgregs->dr7; 4440 kvm_update_dr7(vcpu); 4441 4442 return 0; 4443 } 4444 4445 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 4446 4447 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 4448 { 4449 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 4450 u64 xstate_bv = xsave->header.xfeatures; 4451 u64 valid; 4452 4453 /* 4454 * Copy legacy XSAVE area, to avoid complications with CPUID 4455 * leaves 0 and 1 in the loop below. 4456 */ 4457 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 4458 4459 /* Set XSTATE_BV */ 4460 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; 4461 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 4462 4463 /* 4464 * Copy each region from the possibly compacted offset to the 4465 * non-compacted offset. 4466 */ 4467 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 4468 while (valid) { 4469 u64 xfeature_mask = valid & -valid; 4470 int xfeature_nr = fls64(xfeature_mask) - 1; 4471 void *src = get_xsave_addr(xsave, xfeature_nr); 4472 4473 if (src) { 4474 u32 size, offset, ecx, edx; 4475 cpuid_count(XSTATE_CPUID, xfeature_nr, 4476 &size, &offset, &ecx, &edx); 4477 if (xfeature_nr == XFEATURE_PKRU) 4478 memcpy(dest + offset, &vcpu->arch.pkru, 4479 sizeof(vcpu->arch.pkru)); 4480 else 4481 memcpy(dest + offset, src, size); 4482 4483 } 4484 4485 valid -= xfeature_mask; 4486 } 4487 } 4488 4489 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 4490 { 4491 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 4492 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 4493 u64 valid; 4494 4495 /* 4496 * Copy legacy XSAVE area, to avoid complications with CPUID 4497 * leaves 0 and 1 in the loop below. 4498 */ 4499 memcpy(xsave, src, XSAVE_HDR_OFFSET); 4500 4501 /* Set XSTATE_BV and possibly XCOMP_BV. */ 4502 xsave->header.xfeatures = xstate_bv; 4503 if (boot_cpu_has(X86_FEATURE_XSAVES)) 4504 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 4505 4506 /* 4507 * Copy each region from the non-compacted offset to the 4508 * possibly compacted offset. 4509 */ 4510 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 4511 while (valid) { 4512 u64 xfeature_mask = valid & -valid; 4513 int xfeature_nr = fls64(xfeature_mask) - 1; 4514 void *dest = get_xsave_addr(xsave, xfeature_nr); 4515 4516 if (dest) { 4517 u32 size, offset, ecx, edx; 4518 cpuid_count(XSTATE_CPUID, xfeature_nr, 4519 &size, &offset, &ecx, &edx); 4520 if (xfeature_nr == XFEATURE_PKRU) 4521 memcpy(&vcpu->arch.pkru, src + offset, 4522 sizeof(vcpu->arch.pkru)); 4523 else 4524 memcpy(dest, src + offset, size); 4525 } 4526 4527 valid -= xfeature_mask; 4528 } 4529 } 4530 4531 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 4532 struct kvm_xsave *guest_xsave) 4533 { 4534 if (!vcpu->arch.guest_fpu) 4535 return; 4536 4537 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 4538 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 4539 fill_xsave((u8 *) guest_xsave->region, vcpu); 4540 } else { 4541 memcpy(guest_xsave->region, 4542 &vcpu->arch.guest_fpu->state.fxsave, 4543 sizeof(struct fxregs_state)); 4544 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 4545 XFEATURE_MASK_FPSSE; 4546 } 4547 } 4548 4549 #define XSAVE_MXCSR_OFFSET 24 4550 4551 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 4552 struct kvm_xsave *guest_xsave) 4553 { 4554 u64 xstate_bv; 4555 u32 mxcsr; 4556 4557 if (!vcpu->arch.guest_fpu) 4558 return 0; 4559 4560 xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 4561 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; 4562 4563 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 4564 /* 4565 * Here we allow setting states that are not present in 4566 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 4567 * with old userspace. 4568 */ 4569 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask) 4570 return -EINVAL; 4571 load_xsave(vcpu, (u8 *)guest_xsave->region); 4572 } else { 4573 if (xstate_bv & ~XFEATURE_MASK_FPSSE || 4574 mxcsr & ~mxcsr_feature_mask) 4575 return -EINVAL; 4576 memcpy(&vcpu->arch.guest_fpu->state.fxsave, 4577 guest_xsave->region, sizeof(struct fxregs_state)); 4578 } 4579 return 0; 4580 } 4581 4582 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 4583 struct kvm_xcrs *guest_xcrs) 4584 { 4585 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 4586 guest_xcrs->nr_xcrs = 0; 4587 return; 4588 } 4589 4590 guest_xcrs->nr_xcrs = 1; 4591 guest_xcrs->flags = 0; 4592 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 4593 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 4594 } 4595 4596 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 4597 struct kvm_xcrs *guest_xcrs) 4598 { 4599 int i, r = 0; 4600 4601 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 4602 return -EINVAL; 4603 4604 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 4605 return -EINVAL; 4606 4607 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 4608 /* Only support XCR0 currently */ 4609 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 4610 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 4611 guest_xcrs->xcrs[i].value); 4612 break; 4613 } 4614 if (r) 4615 r = -EINVAL; 4616 return r; 4617 } 4618 4619 /* 4620 * kvm_set_guest_paused() indicates to the guest kernel that it has been 4621 * stopped by the hypervisor. This function will be called from the host only. 4622 * EINVAL is returned when the host attempts to set the flag for a guest that 4623 * does not support pv clocks. 4624 */ 4625 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 4626 { 4627 if (!vcpu->arch.pv_time_enabled) 4628 return -EINVAL; 4629 vcpu->arch.pvclock_set_guest_stopped_request = true; 4630 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4631 return 0; 4632 } 4633 4634 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 4635 struct kvm_enable_cap *cap) 4636 { 4637 int r; 4638 uint16_t vmcs_version; 4639 void __user *user_ptr; 4640 4641 if (cap->flags) 4642 return -EINVAL; 4643 4644 switch (cap->cap) { 4645 case KVM_CAP_HYPERV_SYNIC2: 4646 if (cap->args[0]) 4647 return -EINVAL; 4648 fallthrough; 4649 4650 case KVM_CAP_HYPERV_SYNIC: 4651 if (!irqchip_in_kernel(vcpu->kvm)) 4652 return -EINVAL; 4653 return kvm_hv_activate_synic(vcpu, cap->cap == 4654 KVM_CAP_HYPERV_SYNIC2); 4655 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4656 if (!kvm_x86_ops.nested_ops->enable_evmcs) 4657 return -ENOTTY; 4658 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); 4659 if (!r) { 4660 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 4661 if (copy_to_user(user_ptr, &vmcs_version, 4662 sizeof(vmcs_version))) 4663 r = -EFAULT; 4664 } 4665 return r; 4666 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4667 if (!kvm_x86_ops.enable_direct_tlbflush) 4668 return -ENOTTY; 4669 4670 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); 4671 4672 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 4673 vcpu->arch.pv_cpuid.enforce = cap->args[0]; 4674 if (vcpu->arch.pv_cpuid.enforce) 4675 kvm_update_pv_runtime(vcpu); 4676 4677 return 0; 4678 4679 default: 4680 return -EINVAL; 4681 } 4682 } 4683 4684 long kvm_arch_vcpu_ioctl(struct file *filp, 4685 unsigned int ioctl, unsigned long arg) 4686 { 4687 struct kvm_vcpu *vcpu = filp->private_data; 4688 void __user *argp = (void __user *)arg; 4689 int r; 4690 union { 4691 struct kvm_lapic_state *lapic; 4692 struct kvm_xsave *xsave; 4693 struct kvm_xcrs *xcrs; 4694 void *buffer; 4695 } u; 4696 4697 vcpu_load(vcpu); 4698 4699 u.buffer = NULL; 4700 switch (ioctl) { 4701 case KVM_GET_LAPIC: { 4702 r = -EINVAL; 4703 if (!lapic_in_kernel(vcpu)) 4704 goto out; 4705 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 4706 GFP_KERNEL_ACCOUNT); 4707 4708 r = -ENOMEM; 4709 if (!u.lapic) 4710 goto out; 4711 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 4712 if (r) 4713 goto out; 4714 r = -EFAULT; 4715 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 4716 goto out; 4717 r = 0; 4718 break; 4719 } 4720 case KVM_SET_LAPIC: { 4721 r = -EINVAL; 4722 if (!lapic_in_kernel(vcpu)) 4723 goto out; 4724 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 4725 if (IS_ERR(u.lapic)) { 4726 r = PTR_ERR(u.lapic); 4727 goto out_nofree; 4728 } 4729 4730 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 4731 break; 4732 } 4733 case KVM_INTERRUPT: { 4734 struct kvm_interrupt irq; 4735 4736 r = -EFAULT; 4737 if (copy_from_user(&irq, argp, sizeof(irq))) 4738 goto out; 4739 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 4740 break; 4741 } 4742 case KVM_NMI: { 4743 r = kvm_vcpu_ioctl_nmi(vcpu); 4744 break; 4745 } 4746 case KVM_SMI: { 4747 r = kvm_vcpu_ioctl_smi(vcpu); 4748 break; 4749 } 4750 case KVM_SET_CPUID: { 4751 struct kvm_cpuid __user *cpuid_arg = argp; 4752 struct kvm_cpuid cpuid; 4753 4754 r = -EFAULT; 4755 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4756 goto out; 4757 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 4758 break; 4759 } 4760 case KVM_SET_CPUID2: { 4761 struct kvm_cpuid2 __user *cpuid_arg = argp; 4762 struct kvm_cpuid2 cpuid; 4763 4764 r = -EFAULT; 4765 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4766 goto out; 4767 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 4768 cpuid_arg->entries); 4769 break; 4770 } 4771 case KVM_GET_CPUID2: { 4772 struct kvm_cpuid2 __user *cpuid_arg = argp; 4773 struct kvm_cpuid2 cpuid; 4774 4775 r = -EFAULT; 4776 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4777 goto out; 4778 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 4779 cpuid_arg->entries); 4780 if (r) 4781 goto out; 4782 r = -EFAULT; 4783 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4784 goto out; 4785 r = 0; 4786 break; 4787 } 4788 case KVM_GET_MSRS: { 4789 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4790 r = msr_io(vcpu, argp, do_get_msr, 1); 4791 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4792 break; 4793 } 4794 case KVM_SET_MSRS: { 4795 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4796 r = msr_io(vcpu, argp, do_set_msr, 0); 4797 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4798 break; 4799 } 4800 case KVM_TPR_ACCESS_REPORTING: { 4801 struct kvm_tpr_access_ctl tac; 4802 4803 r = -EFAULT; 4804 if (copy_from_user(&tac, argp, sizeof(tac))) 4805 goto out; 4806 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 4807 if (r) 4808 goto out; 4809 r = -EFAULT; 4810 if (copy_to_user(argp, &tac, sizeof(tac))) 4811 goto out; 4812 r = 0; 4813 break; 4814 }; 4815 case KVM_SET_VAPIC_ADDR: { 4816 struct kvm_vapic_addr va; 4817 int idx; 4818 4819 r = -EINVAL; 4820 if (!lapic_in_kernel(vcpu)) 4821 goto out; 4822 r = -EFAULT; 4823 if (copy_from_user(&va, argp, sizeof(va))) 4824 goto out; 4825 idx = srcu_read_lock(&vcpu->kvm->srcu); 4826 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 4827 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4828 break; 4829 } 4830 case KVM_X86_SETUP_MCE: { 4831 u64 mcg_cap; 4832 4833 r = -EFAULT; 4834 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 4835 goto out; 4836 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 4837 break; 4838 } 4839 case KVM_X86_SET_MCE: { 4840 struct kvm_x86_mce mce; 4841 4842 r = -EFAULT; 4843 if (copy_from_user(&mce, argp, sizeof(mce))) 4844 goto out; 4845 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 4846 break; 4847 } 4848 case KVM_GET_VCPU_EVENTS: { 4849 struct kvm_vcpu_events events; 4850 4851 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 4852 4853 r = -EFAULT; 4854 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 4855 break; 4856 r = 0; 4857 break; 4858 } 4859 case KVM_SET_VCPU_EVENTS: { 4860 struct kvm_vcpu_events events; 4861 4862 r = -EFAULT; 4863 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 4864 break; 4865 4866 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 4867 break; 4868 } 4869 case KVM_GET_DEBUGREGS: { 4870 struct kvm_debugregs dbgregs; 4871 4872 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 4873 4874 r = -EFAULT; 4875 if (copy_to_user(argp, &dbgregs, 4876 sizeof(struct kvm_debugregs))) 4877 break; 4878 r = 0; 4879 break; 4880 } 4881 case KVM_SET_DEBUGREGS: { 4882 struct kvm_debugregs dbgregs; 4883 4884 r = -EFAULT; 4885 if (copy_from_user(&dbgregs, argp, 4886 sizeof(struct kvm_debugregs))) 4887 break; 4888 4889 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 4890 break; 4891 } 4892 case KVM_GET_XSAVE: { 4893 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 4894 r = -ENOMEM; 4895 if (!u.xsave) 4896 break; 4897 4898 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 4899 4900 r = -EFAULT; 4901 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 4902 break; 4903 r = 0; 4904 break; 4905 } 4906 case KVM_SET_XSAVE: { 4907 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 4908 if (IS_ERR(u.xsave)) { 4909 r = PTR_ERR(u.xsave); 4910 goto out_nofree; 4911 } 4912 4913 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 4914 break; 4915 } 4916 case KVM_GET_XCRS: { 4917 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 4918 r = -ENOMEM; 4919 if (!u.xcrs) 4920 break; 4921 4922 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 4923 4924 r = -EFAULT; 4925 if (copy_to_user(argp, u.xcrs, 4926 sizeof(struct kvm_xcrs))) 4927 break; 4928 r = 0; 4929 break; 4930 } 4931 case KVM_SET_XCRS: { 4932 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 4933 if (IS_ERR(u.xcrs)) { 4934 r = PTR_ERR(u.xcrs); 4935 goto out_nofree; 4936 } 4937 4938 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 4939 break; 4940 } 4941 case KVM_SET_TSC_KHZ: { 4942 u32 user_tsc_khz; 4943 4944 r = -EINVAL; 4945 user_tsc_khz = (u32)arg; 4946 4947 if (kvm_has_tsc_control && 4948 user_tsc_khz >= kvm_max_guest_tsc_khz) 4949 goto out; 4950 4951 if (user_tsc_khz == 0) 4952 user_tsc_khz = tsc_khz; 4953 4954 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 4955 r = 0; 4956 4957 goto out; 4958 } 4959 case KVM_GET_TSC_KHZ: { 4960 r = vcpu->arch.virtual_tsc_khz; 4961 goto out; 4962 } 4963 case KVM_KVMCLOCK_CTRL: { 4964 r = kvm_set_guest_paused(vcpu); 4965 goto out; 4966 } 4967 case KVM_ENABLE_CAP: { 4968 struct kvm_enable_cap cap; 4969 4970 r = -EFAULT; 4971 if (copy_from_user(&cap, argp, sizeof(cap))) 4972 goto out; 4973 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 4974 break; 4975 } 4976 case KVM_GET_NESTED_STATE: { 4977 struct kvm_nested_state __user *user_kvm_nested_state = argp; 4978 u32 user_data_size; 4979 4980 r = -EINVAL; 4981 if (!kvm_x86_ops.nested_ops->get_state) 4982 break; 4983 4984 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 4985 r = -EFAULT; 4986 if (get_user(user_data_size, &user_kvm_nested_state->size)) 4987 break; 4988 4989 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, 4990 user_data_size); 4991 if (r < 0) 4992 break; 4993 4994 if (r > user_data_size) { 4995 if (put_user(r, &user_kvm_nested_state->size)) 4996 r = -EFAULT; 4997 else 4998 r = -E2BIG; 4999 break; 5000 } 5001 5002 r = 0; 5003 break; 5004 } 5005 case KVM_SET_NESTED_STATE: { 5006 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5007 struct kvm_nested_state kvm_state; 5008 int idx; 5009 5010 r = -EINVAL; 5011 if (!kvm_x86_ops.nested_ops->set_state) 5012 break; 5013 5014 r = -EFAULT; 5015 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 5016 break; 5017 5018 r = -EINVAL; 5019 if (kvm_state.size < sizeof(kvm_state)) 5020 break; 5021 5022 if (kvm_state.flags & 5023 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 5024 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING 5025 | KVM_STATE_NESTED_GIF_SET)) 5026 break; 5027 5028 /* nested_run_pending implies guest_mode. */ 5029 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 5030 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 5031 break; 5032 5033 idx = srcu_read_lock(&vcpu->kvm->srcu); 5034 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); 5035 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5036 break; 5037 } 5038 case KVM_GET_SUPPORTED_HV_CPUID: 5039 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); 5040 break; 5041 #ifdef CONFIG_KVM_XEN 5042 case KVM_XEN_VCPU_GET_ATTR: { 5043 struct kvm_xen_vcpu_attr xva; 5044 5045 r = -EFAULT; 5046 if (copy_from_user(&xva, argp, sizeof(xva))) 5047 goto out; 5048 r = kvm_xen_vcpu_get_attr(vcpu, &xva); 5049 if (!r && copy_to_user(argp, &xva, sizeof(xva))) 5050 r = -EFAULT; 5051 break; 5052 } 5053 case KVM_XEN_VCPU_SET_ATTR: { 5054 struct kvm_xen_vcpu_attr xva; 5055 5056 r = -EFAULT; 5057 if (copy_from_user(&xva, argp, sizeof(xva))) 5058 goto out; 5059 r = kvm_xen_vcpu_set_attr(vcpu, &xva); 5060 break; 5061 } 5062 #endif 5063 default: 5064 r = -EINVAL; 5065 } 5066 out: 5067 kfree(u.buffer); 5068 out_nofree: 5069 vcpu_put(vcpu); 5070 return r; 5071 } 5072 5073 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 5074 { 5075 return VM_FAULT_SIGBUS; 5076 } 5077 5078 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 5079 { 5080 int ret; 5081 5082 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 5083 return -EINVAL; 5084 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); 5085 return ret; 5086 } 5087 5088 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 5089 u64 ident_addr) 5090 { 5091 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); 5092 } 5093 5094 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 5095 unsigned long kvm_nr_mmu_pages) 5096 { 5097 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 5098 return -EINVAL; 5099 5100 mutex_lock(&kvm->slots_lock); 5101 5102 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 5103 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 5104 5105 mutex_unlock(&kvm->slots_lock); 5106 return 0; 5107 } 5108 5109 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 5110 { 5111 return kvm->arch.n_max_mmu_pages; 5112 } 5113 5114 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5115 { 5116 struct kvm_pic *pic = kvm->arch.vpic; 5117 int r; 5118 5119 r = 0; 5120 switch (chip->chip_id) { 5121 case KVM_IRQCHIP_PIC_MASTER: 5122 memcpy(&chip->chip.pic, &pic->pics[0], 5123 sizeof(struct kvm_pic_state)); 5124 break; 5125 case KVM_IRQCHIP_PIC_SLAVE: 5126 memcpy(&chip->chip.pic, &pic->pics[1], 5127 sizeof(struct kvm_pic_state)); 5128 break; 5129 case KVM_IRQCHIP_IOAPIC: 5130 kvm_get_ioapic(kvm, &chip->chip.ioapic); 5131 break; 5132 default: 5133 r = -EINVAL; 5134 break; 5135 } 5136 return r; 5137 } 5138 5139 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5140 { 5141 struct kvm_pic *pic = kvm->arch.vpic; 5142 int r; 5143 5144 r = 0; 5145 switch (chip->chip_id) { 5146 case KVM_IRQCHIP_PIC_MASTER: 5147 spin_lock(&pic->lock); 5148 memcpy(&pic->pics[0], &chip->chip.pic, 5149 sizeof(struct kvm_pic_state)); 5150 spin_unlock(&pic->lock); 5151 break; 5152 case KVM_IRQCHIP_PIC_SLAVE: 5153 spin_lock(&pic->lock); 5154 memcpy(&pic->pics[1], &chip->chip.pic, 5155 sizeof(struct kvm_pic_state)); 5156 spin_unlock(&pic->lock); 5157 break; 5158 case KVM_IRQCHIP_IOAPIC: 5159 kvm_set_ioapic(kvm, &chip->chip.ioapic); 5160 break; 5161 default: 5162 r = -EINVAL; 5163 break; 5164 } 5165 kvm_pic_update_irq(pic); 5166 return r; 5167 } 5168 5169 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5170 { 5171 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 5172 5173 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 5174 5175 mutex_lock(&kps->lock); 5176 memcpy(ps, &kps->channels, sizeof(*ps)); 5177 mutex_unlock(&kps->lock); 5178 return 0; 5179 } 5180 5181 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5182 { 5183 int i; 5184 struct kvm_pit *pit = kvm->arch.vpit; 5185 5186 mutex_lock(&pit->pit_state.lock); 5187 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 5188 for (i = 0; i < 3; i++) 5189 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 5190 mutex_unlock(&pit->pit_state.lock); 5191 return 0; 5192 } 5193 5194 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5195 { 5196 mutex_lock(&kvm->arch.vpit->pit_state.lock); 5197 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 5198 sizeof(ps->channels)); 5199 ps->flags = kvm->arch.vpit->pit_state.flags; 5200 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 5201 memset(&ps->reserved, 0, sizeof(ps->reserved)); 5202 return 0; 5203 } 5204 5205 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5206 { 5207 int start = 0; 5208 int i; 5209 u32 prev_legacy, cur_legacy; 5210 struct kvm_pit *pit = kvm->arch.vpit; 5211 5212 mutex_lock(&pit->pit_state.lock); 5213 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 5214 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 5215 if (!prev_legacy && cur_legacy) 5216 start = 1; 5217 memcpy(&pit->pit_state.channels, &ps->channels, 5218 sizeof(pit->pit_state.channels)); 5219 pit->pit_state.flags = ps->flags; 5220 for (i = 0; i < 3; i++) 5221 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 5222 start && i == 0); 5223 mutex_unlock(&pit->pit_state.lock); 5224 return 0; 5225 } 5226 5227 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 5228 struct kvm_reinject_control *control) 5229 { 5230 struct kvm_pit *pit = kvm->arch.vpit; 5231 5232 /* pit->pit_state.lock was overloaded to prevent userspace from getting 5233 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 5234 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 5235 */ 5236 mutex_lock(&pit->pit_state.lock); 5237 kvm_pit_set_reinject(pit, control->pit_reinject); 5238 mutex_unlock(&pit->pit_state.lock); 5239 5240 return 0; 5241 } 5242 5243 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 5244 { 5245 5246 /* 5247 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called 5248 * before reporting dirty_bitmap to userspace. KVM flushes the buffers 5249 * on all VM-Exits, thus we only need to kick running vCPUs to force a 5250 * VM-Exit. 5251 */ 5252 struct kvm_vcpu *vcpu; 5253 int i; 5254 5255 kvm_for_each_vcpu(i, vcpu, kvm) 5256 kvm_vcpu_kick(vcpu); 5257 } 5258 5259 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 5260 bool line_status) 5261 { 5262 if (!irqchip_in_kernel(kvm)) 5263 return -ENXIO; 5264 5265 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 5266 irq_event->irq, irq_event->level, 5267 line_status); 5268 return 0; 5269 } 5270 5271 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 5272 struct kvm_enable_cap *cap) 5273 { 5274 int r; 5275 5276 if (cap->flags) 5277 return -EINVAL; 5278 5279 switch (cap->cap) { 5280 case KVM_CAP_DISABLE_QUIRKS: 5281 kvm->arch.disabled_quirks = cap->args[0]; 5282 r = 0; 5283 break; 5284 case KVM_CAP_SPLIT_IRQCHIP: { 5285 mutex_lock(&kvm->lock); 5286 r = -EINVAL; 5287 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 5288 goto split_irqchip_unlock; 5289 r = -EEXIST; 5290 if (irqchip_in_kernel(kvm)) 5291 goto split_irqchip_unlock; 5292 if (kvm->created_vcpus) 5293 goto split_irqchip_unlock; 5294 r = kvm_setup_empty_irq_routing(kvm); 5295 if (r) 5296 goto split_irqchip_unlock; 5297 /* Pairs with irqchip_in_kernel. */ 5298 smp_wmb(); 5299 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 5300 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 5301 r = 0; 5302 split_irqchip_unlock: 5303 mutex_unlock(&kvm->lock); 5304 break; 5305 } 5306 case KVM_CAP_X2APIC_API: 5307 r = -EINVAL; 5308 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 5309 break; 5310 5311 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 5312 kvm->arch.x2apic_format = true; 5313 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 5314 kvm->arch.x2apic_broadcast_quirk_disabled = true; 5315 5316 r = 0; 5317 break; 5318 case KVM_CAP_X86_DISABLE_EXITS: 5319 r = -EINVAL; 5320 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 5321 break; 5322 5323 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 5324 kvm_can_mwait_in_guest()) 5325 kvm->arch.mwait_in_guest = true; 5326 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 5327 kvm->arch.hlt_in_guest = true; 5328 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 5329 kvm->arch.pause_in_guest = true; 5330 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) 5331 kvm->arch.cstate_in_guest = true; 5332 r = 0; 5333 break; 5334 case KVM_CAP_MSR_PLATFORM_INFO: 5335 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 5336 r = 0; 5337 break; 5338 case KVM_CAP_EXCEPTION_PAYLOAD: 5339 kvm->arch.exception_payload_enabled = cap->args[0]; 5340 r = 0; 5341 break; 5342 case KVM_CAP_X86_USER_SPACE_MSR: 5343 kvm->arch.user_space_msr_mask = cap->args[0]; 5344 r = 0; 5345 break; 5346 case KVM_CAP_X86_BUS_LOCK_EXIT: 5347 r = -EINVAL; 5348 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) 5349 break; 5350 5351 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && 5352 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) 5353 break; 5354 5355 if (kvm_has_bus_lock_exit && 5356 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) 5357 kvm->arch.bus_lock_detection_enabled = true; 5358 r = 0; 5359 break; 5360 default: 5361 r = -EINVAL; 5362 break; 5363 } 5364 return r; 5365 } 5366 5367 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) 5368 { 5369 struct kvm_x86_msr_filter *msr_filter; 5370 5371 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); 5372 if (!msr_filter) 5373 return NULL; 5374 5375 msr_filter->default_allow = default_allow; 5376 return msr_filter; 5377 } 5378 5379 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) 5380 { 5381 u32 i; 5382 5383 if (!msr_filter) 5384 return; 5385 5386 for (i = 0; i < msr_filter->count; i++) 5387 kfree(msr_filter->ranges[i].bitmap); 5388 5389 kfree(msr_filter); 5390 } 5391 5392 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, 5393 struct kvm_msr_filter_range *user_range) 5394 { 5395 struct msr_bitmap_range range; 5396 unsigned long *bitmap = NULL; 5397 size_t bitmap_size; 5398 int r; 5399 5400 if (!user_range->nmsrs) 5401 return 0; 5402 5403 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); 5404 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) 5405 return -EINVAL; 5406 5407 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); 5408 if (IS_ERR(bitmap)) 5409 return PTR_ERR(bitmap); 5410 5411 range = (struct msr_bitmap_range) { 5412 .flags = user_range->flags, 5413 .base = user_range->base, 5414 .nmsrs = user_range->nmsrs, 5415 .bitmap = bitmap, 5416 }; 5417 5418 if (range.flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) { 5419 r = -EINVAL; 5420 goto err; 5421 } 5422 5423 if (!range.flags) { 5424 r = -EINVAL; 5425 goto err; 5426 } 5427 5428 /* Everything ok, add this range identifier. */ 5429 msr_filter->ranges[msr_filter->count] = range; 5430 msr_filter->count++; 5431 5432 return 0; 5433 err: 5434 kfree(bitmap); 5435 return r; 5436 } 5437 5438 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) 5439 { 5440 struct kvm_msr_filter __user *user_msr_filter = argp; 5441 struct kvm_x86_msr_filter *new_filter, *old_filter; 5442 struct kvm_msr_filter filter; 5443 bool default_allow; 5444 bool empty = true; 5445 int r = 0; 5446 u32 i; 5447 5448 if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) 5449 return -EFAULT; 5450 5451 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) 5452 empty &= !filter.ranges[i].nmsrs; 5453 5454 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); 5455 if (empty && !default_allow) 5456 return -EINVAL; 5457 5458 new_filter = kvm_alloc_msr_filter(default_allow); 5459 if (!new_filter) 5460 return -ENOMEM; 5461 5462 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { 5463 r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); 5464 if (r) { 5465 kvm_free_msr_filter(new_filter); 5466 return r; 5467 } 5468 } 5469 5470 mutex_lock(&kvm->lock); 5471 5472 /* The per-VM filter is protected by kvm->lock... */ 5473 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1); 5474 5475 rcu_assign_pointer(kvm->arch.msr_filter, new_filter); 5476 synchronize_srcu(&kvm->srcu); 5477 5478 kvm_free_msr_filter(old_filter); 5479 5480 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); 5481 mutex_unlock(&kvm->lock); 5482 5483 return 0; 5484 } 5485 5486 long kvm_arch_vm_ioctl(struct file *filp, 5487 unsigned int ioctl, unsigned long arg) 5488 { 5489 struct kvm *kvm = filp->private_data; 5490 void __user *argp = (void __user *)arg; 5491 int r = -ENOTTY; 5492 /* 5493 * This union makes it completely explicit to gcc-3.x 5494 * that these two variables' stack usage should be 5495 * combined, not added together. 5496 */ 5497 union { 5498 struct kvm_pit_state ps; 5499 struct kvm_pit_state2 ps2; 5500 struct kvm_pit_config pit_config; 5501 } u; 5502 5503 switch (ioctl) { 5504 case KVM_SET_TSS_ADDR: 5505 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 5506 break; 5507 case KVM_SET_IDENTITY_MAP_ADDR: { 5508 u64 ident_addr; 5509 5510 mutex_lock(&kvm->lock); 5511 r = -EINVAL; 5512 if (kvm->created_vcpus) 5513 goto set_identity_unlock; 5514 r = -EFAULT; 5515 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 5516 goto set_identity_unlock; 5517 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 5518 set_identity_unlock: 5519 mutex_unlock(&kvm->lock); 5520 break; 5521 } 5522 case KVM_SET_NR_MMU_PAGES: 5523 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 5524 break; 5525 case KVM_GET_NR_MMU_PAGES: 5526 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 5527 break; 5528 case KVM_CREATE_IRQCHIP: { 5529 mutex_lock(&kvm->lock); 5530 5531 r = -EEXIST; 5532 if (irqchip_in_kernel(kvm)) 5533 goto create_irqchip_unlock; 5534 5535 r = -EINVAL; 5536 if (kvm->created_vcpus) 5537 goto create_irqchip_unlock; 5538 5539 r = kvm_pic_init(kvm); 5540 if (r) 5541 goto create_irqchip_unlock; 5542 5543 r = kvm_ioapic_init(kvm); 5544 if (r) { 5545 kvm_pic_destroy(kvm); 5546 goto create_irqchip_unlock; 5547 } 5548 5549 r = kvm_setup_default_irq_routing(kvm); 5550 if (r) { 5551 kvm_ioapic_destroy(kvm); 5552 kvm_pic_destroy(kvm); 5553 goto create_irqchip_unlock; 5554 } 5555 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 5556 smp_wmb(); 5557 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 5558 create_irqchip_unlock: 5559 mutex_unlock(&kvm->lock); 5560 break; 5561 } 5562 case KVM_CREATE_PIT: 5563 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 5564 goto create_pit; 5565 case KVM_CREATE_PIT2: 5566 r = -EFAULT; 5567 if (copy_from_user(&u.pit_config, argp, 5568 sizeof(struct kvm_pit_config))) 5569 goto out; 5570 create_pit: 5571 mutex_lock(&kvm->lock); 5572 r = -EEXIST; 5573 if (kvm->arch.vpit) 5574 goto create_pit_unlock; 5575 r = -ENOMEM; 5576 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 5577 if (kvm->arch.vpit) 5578 r = 0; 5579 create_pit_unlock: 5580 mutex_unlock(&kvm->lock); 5581 break; 5582 case KVM_GET_IRQCHIP: { 5583 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 5584 struct kvm_irqchip *chip; 5585 5586 chip = memdup_user(argp, sizeof(*chip)); 5587 if (IS_ERR(chip)) { 5588 r = PTR_ERR(chip); 5589 goto out; 5590 } 5591 5592 r = -ENXIO; 5593 if (!irqchip_kernel(kvm)) 5594 goto get_irqchip_out; 5595 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 5596 if (r) 5597 goto get_irqchip_out; 5598 r = -EFAULT; 5599 if (copy_to_user(argp, chip, sizeof(*chip))) 5600 goto get_irqchip_out; 5601 r = 0; 5602 get_irqchip_out: 5603 kfree(chip); 5604 break; 5605 } 5606 case KVM_SET_IRQCHIP: { 5607 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 5608 struct kvm_irqchip *chip; 5609 5610 chip = memdup_user(argp, sizeof(*chip)); 5611 if (IS_ERR(chip)) { 5612 r = PTR_ERR(chip); 5613 goto out; 5614 } 5615 5616 r = -ENXIO; 5617 if (!irqchip_kernel(kvm)) 5618 goto set_irqchip_out; 5619 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 5620 set_irqchip_out: 5621 kfree(chip); 5622 break; 5623 } 5624 case KVM_GET_PIT: { 5625 r = -EFAULT; 5626 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 5627 goto out; 5628 r = -ENXIO; 5629 if (!kvm->arch.vpit) 5630 goto out; 5631 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 5632 if (r) 5633 goto out; 5634 r = -EFAULT; 5635 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 5636 goto out; 5637 r = 0; 5638 break; 5639 } 5640 case KVM_SET_PIT: { 5641 r = -EFAULT; 5642 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 5643 goto out; 5644 mutex_lock(&kvm->lock); 5645 r = -ENXIO; 5646 if (!kvm->arch.vpit) 5647 goto set_pit_out; 5648 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 5649 set_pit_out: 5650 mutex_unlock(&kvm->lock); 5651 break; 5652 } 5653 case KVM_GET_PIT2: { 5654 r = -ENXIO; 5655 if (!kvm->arch.vpit) 5656 goto out; 5657 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 5658 if (r) 5659 goto out; 5660 r = -EFAULT; 5661 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 5662 goto out; 5663 r = 0; 5664 break; 5665 } 5666 case KVM_SET_PIT2: { 5667 r = -EFAULT; 5668 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 5669 goto out; 5670 mutex_lock(&kvm->lock); 5671 r = -ENXIO; 5672 if (!kvm->arch.vpit) 5673 goto set_pit2_out; 5674 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 5675 set_pit2_out: 5676 mutex_unlock(&kvm->lock); 5677 break; 5678 } 5679 case KVM_REINJECT_CONTROL: { 5680 struct kvm_reinject_control control; 5681 r = -EFAULT; 5682 if (copy_from_user(&control, argp, sizeof(control))) 5683 goto out; 5684 r = -ENXIO; 5685 if (!kvm->arch.vpit) 5686 goto out; 5687 r = kvm_vm_ioctl_reinject(kvm, &control); 5688 break; 5689 } 5690 case KVM_SET_BOOT_CPU_ID: 5691 r = 0; 5692 mutex_lock(&kvm->lock); 5693 if (kvm->created_vcpus) 5694 r = -EBUSY; 5695 else 5696 kvm->arch.bsp_vcpu_id = arg; 5697 mutex_unlock(&kvm->lock); 5698 break; 5699 #ifdef CONFIG_KVM_XEN 5700 case KVM_XEN_HVM_CONFIG: { 5701 struct kvm_xen_hvm_config xhc; 5702 r = -EFAULT; 5703 if (copy_from_user(&xhc, argp, sizeof(xhc))) 5704 goto out; 5705 r = kvm_xen_hvm_config(kvm, &xhc); 5706 break; 5707 } 5708 case KVM_XEN_HVM_GET_ATTR: { 5709 struct kvm_xen_hvm_attr xha; 5710 5711 r = -EFAULT; 5712 if (copy_from_user(&xha, argp, sizeof(xha))) 5713 goto out; 5714 r = kvm_xen_hvm_get_attr(kvm, &xha); 5715 if (!r && copy_to_user(argp, &xha, sizeof(xha))) 5716 r = -EFAULT; 5717 break; 5718 } 5719 case KVM_XEN_HVM_SET_ATTR: { 5720 struct kvm_xen_hvm_attr xha; 5721 5722 r = -EFAULT; 5723 if (copy_from_user(&xha, argp, sizeof(xha))) 5724 goto out; 5725 r = kvm_xen_hvm_set_attr(kvm, &xha); 5726 break; 5727 } 5728 #endif 5729 case KVM_SET_CLOCK: { 5730 struct kvm_arch *ka = &kvm->arch; 5731 struct kvm_clock_data user_ns; 5732 u64 now_ns; 5733 5734 r = -EFAULT; 5735 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 5736 goto out; 5737 5738 r = -EINVAL; 5739 if (user_ns.flags) 5740 goto out; 5741 5742 r = 0; 5743 /* 5744 * TODO: userspace has to take care of races with VCPU_RUN, so 5745 * kvm_gen_update_masterclock() can be cut down to locked 5746 * pvclock_update_vm_gtod_copy(). 5747 */ 5748 kvm_gen_update_masterclock(kvm); 5749 5750 /* 5751 * This pairs with kvm_guest_time_update(): when masterclock is 5752 * in use, we use master_kernel_ns + kvmclock_offset to set 5753 * unsigned 'system_time' so if we use get_kvmclock_ns() (which 5754 * is slightly ahead) here we risk going negative on unsigned 5755 * 'system_time' when 'user_ns.clock' is very small. 5756 */ 5757 spin_lock_irq(&ka->pvclock_gtod_sync_lock); 5758 if (kvm->arch.use_master_clock) 5759 now_ns = ka->master_kernel_ns; 5760 else 5761 now_ns = get_kvmclock_base_ns(); 5762 ka->kvmclock_offset = user_ns.clock - now_ns; 5763 spin_unlock_irq(&ka->pvclock_gtod_sync_lock); 5764 5765 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); 5766 break; 5767 } 5768 case KVM_GET_CLOCK: { 5769 struct kvm_clock_data user_ns; 5770 u64 now_ns; 5771 5772 now_ns = get_kvmclock_ns(kvm); 5773 user_ns.clock = now_ns; 5774 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 5775 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 5776 5777 r = -EFAULT; 5778 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 5779 goto out; 5780 r = 0; 5781 break; 5782 } 5783 case KVM_MEMORY_ENCRYPT_OP: { 5784 r = -ENOTTY; 5785 if (kvm_x86_ops.mem_enc_op) 5786 r = static_call(kvm_x86_mem_enc_op)(kvm, argp); 5787 break; 5788 } 5789 case KVM_MEMORY_ENCRYPT_REG_REGION: { 5790 struct kvm_enc_region region; 5791 5792 r = -EFAULT; 5793 if (copy_from_user(®ion, argp, sizeof(region))) 5794 goto out; 5795 5796 r = -ENOTTY; 5797 if (kvm_x86_ops.mem_enc_reg_region) 5798 r = static_call(kvm_x86_mem_enc_reg_region)(kvm, ®ion); 5799 break; 5800 } 5801 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 5802 struct kvm_enc_region region; 5803 5804 r = -EFAULT; 5805 if (copy_from_user(®ion, argp, sizeof(region))) 5806 goto out; 5807 5808 r = -ENOTTY; 5809 if (kvm_x86_ops.mem_enc_unreg_region) 5810 r = static_call(kvm_x86_mem_enc_unreg_region)(kvm, ®ion); 5811 break; 5812 } 5813 case KVM_HYPERV_EVENTFD: { 5814 struct kvm_hyperv_eventfd hvevfd; 5815 5816 r = -EFAULT; 5817 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 5818 goto out; 5819 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 5820 break; 5821 } 5822 case KVM_SET_PMU_EVENT_FILTER: 5823 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); 5824 break; 5825 case KVM_X86_SET_MSR_FILTER: 5826 r = kvm_vm_ioctl_set_msr_filter(kvm, argp); 5827 break; 5828 default: 5829 r = -ENOTTY; 5830 } 5831 out: 5832 return r; 5833 } 5834 5835 static void kvm_init_msr_list(void) 5836 { 5837 struct x86_pmu_capability x86_pmu; 5838 u32 dummy[2]; 5839 unsigned i; 5840 5841 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, 5842 "Please update the fixed PMCs in msrs_to_saved_all[]"); 5843 5844 perf_get_x86_pmu_capability(&x86_pmu); 5845 5846 num_msrs_to_save = 0; 5847 num_emulated_msrs = 0; 5848 num_msr_based_features = 0; 5849 5850 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { 5851 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) 5852 continue; 5853 5854 /* 5855 * Even MSRs that are valid in the host may not be exposed 5856 * to the guests in some cases. 5857 */ 5858 switch (msrs_to_save_all[i]) { 5859 case MSR_IA32_BNDCFGS: 5860 if (!kvm_mpx_supported()) 5861 continue; 5862 break; 5863 case MSR_TSC_AUX: 5864 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) 5865 continue; 5866 break; 5867 case MSR_IA32_UMWAIT_CONTROL: 5868 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) 5869 continue; 5870 break; 5871 case MSR_IA32_RTIT_CTL: 5872 case MSR_IA32_RTIT_STATUS: 5873 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) 5874 continue; 5875 break; 5876 case MSR_IA32_RTIT_CR3_MATCH: 5877 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 5878 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 5879 continue; 5880 break; 5881 case MSR_IA32_RTIT_OUTPUT_BASE: 5882 case MSR_IA32_RTIT_OUTPUT_MASK: 5883 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 5884 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 5885 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 5886 continue; 5887 break; 5888 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 5889 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 5890 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= 5891 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 5892 continue; 5893 break; 5894 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: 5895 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= 5896 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 5897 continue; 5898 break; 5899 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: 5900 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= 5901 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 5902 continue; 5903 break; 5904 default: 5905 break; 5906 } 5907 5908 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; 5909 } 5910 5911 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { 5912 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) 5913 continue; 5914 5915 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; 5916 } 5917 5918 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { 5919 struct kvm_msr_entry msr; 5920 5921 msr.index = msr_based_features_all[i]; 5922 if (kvm_get_msr_feature(&msr)) 5923 continue; 5924 5925 msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; 5926 } 5927 } 5928 5929 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 5930 const void *v) 5931 { 5932 int handled = 0; 5933 int n; 5934 5935 do { 5936 n = min(len, 8); 5937 if (!(lapic_in_kernel(vcpu) && 5938 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 5939 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 5940 break; 5941 handled += n; 5942 addr += n; 5943 len -= n; 5944 v += n; 5945 } while (len); 5946 5947 return handled; 5948 } 5949 5950 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 5951 { 5952 int handled = 0; 5953 int n; 5954 5955 do { 5956 n = min(len, 8); 5957 if (!(lapic_in_kernel(vcpu) && 5958 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 5959 addr, n, v)) 5960 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 5961 break; 5962 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 5963 handled += n; 5964 addr += n; 5965 len -= n; 5966 v += n; 5967 } while (len); 5968 5969 return handled; 5970 } 5971 5972 static void kvm_set_segment(struct kvm_vcpu *vcpu, 5973 struct kvm_segment *var, int seg) 5974 { 5975 static_call(kvm_x86_set_segment)(vcpu, var, seg); 5976 } 5977 5978 void kvm_get_segment(struct kvm_vcpu *vcpu, 5979 struct kvm_segment *var, int seg) 5980 { 5981 static_call(kvm_x86_get_segment)(vcpu, var, seg); 5982 } 5983 5984 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 5985 struct x86_exception *exception) 5986 { 5987 gpa_t t_gpa; 5988 5989 BUG_ON(!mmu_is_nested(vcpu)); 5990 5991 /* NPT walks are always user-walks */ 5992 access |= PFERR_USER_MASK; 5993 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); 5994 5995 return t_gpa; 5996 } 5997 5998 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 5999 struct x86_exception *exception) 6000 { 6001 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6002 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6003 } 6004 6005 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 6006 struct x86_exception *exception) 6007 { 6008 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6009 access |= PFERR_FETCH_MASK; 6010 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6011 } 6012 6013 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 6014 struct x86_exception *exception) 6015 { 6016 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6017 access |= PFERR_WRITE_MASK; 6018 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6019 } 6020 6021 /* uses this to access any guest's mapped memory without checking CPL */ 6022 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 6023 struct x86_exception *exception) 6024 { 6025 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 6026 } 6027 6028 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6029 struct kvm_vcpu *vcpu, u32 access, 6030 struct x86_exception *exception) 6031 { 6032 void *data = val; 6033 int r = X86EMUL_CONTINUE; 6034 6035 while (bytes) { 6036 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 6037 exception); 6038 unsigned offset = addr & (PAGE_SIZE-1); 6039 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 6040 int ret; 6041 6042 if (gpa == UNMAPPED_GVA) 6043 return X86EMUL_PROPAGATE_FAULT; 6044 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 6045 offset, toread); 6046 if (ret < 0) { 6047 r = X86EMUL_IO_NEEDED; 6048 goto out; 6049 } 6050 6051 bytes -= toread; 6052 data += toread; 6053 addr += toread; 6054 } 6055 out: 6056 return r; 6057 } 6058 6059 /* used for instruction fetching */ 6060 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 6061 gva_t addr, void *val, unsigned int bytes, 6062 struct x86_exception *exception) 6063 { 6064 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6065 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6066 unsigned offset; 6067 int ret; 6068 6069 /* Inline kvm_read_guest_virt_helper for speed. */ 6070 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 6071 exception); 6072 if (unlikely(gpa == UNMAPPED_GVA)) 6073 return X86EMUL_PROPAGATE_FAULT; 6074 6075 offset = addr & (PAGE_SIZE-1); 6076 if (WARN_ON(offset + bytes > PAGE_SIZE)) 6077 bytes = (unsigned)PAGE_SIZE - offset; 6078 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 6079 offset, bytes); 6080 if (unlikely(ret < 0)) 6081 return X86EMUL_IO_NEEDED; 6082 6083 return X86EMUL_CONTINUE; 6084 } 6085 6086 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 6087 gva_t addr, void *val, unsigned int bytes, 6088 struct x86_exception *exception) 6089 { 6090 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6091 6092 /* 6093 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 6094 * is returned, but our callers are not ready for that and they blindly 6095 * call kvm_inject_page_fault. Ensure that they at least do not leak 6096 * uninitialized kernel stack memory into cr2 and error code. 6097 */ 6098 memset(exception, 0, sizeof(*exception)); 6099 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 6100 exception); 6101 } 6102 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 6103 6104 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 6105 gva_t addr, void *val, unsigned int bytes, 6106 struct x86_exception *exception, bool system) 6107 { 6108 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6109 u32 access = 0; 6110 6111 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6112 access |= PFERR_USER_MASK; 6113 6114 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 6115 } 6116 6117 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 6118 unsigned long addr, void *val, unsigned int bytes) 6119 { 6120 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6121 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 6122 6123 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 6124 } 6125 6126 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6127 struct kvm_vcpu *vcpu, u32 access, 6128 struct x86_exception *exception) 6129 { 6130 void *data = val; 6131 int r = X86EMUL_CONTINUE; 6132 6133 while (bytes) { 6134 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 6135 access, 6136 exception); 6137 unsigned offset = addr & (PAGE_SIZE-1); 6138 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 6139 int ret; 6140 6141 if (gpa == UNMAPPED_GVA) 6142 return X86EMUL_PROPAGATE_FAULT; 6143 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 6144 if (ret < 0) { 6145 r = X86EMUL_IO_NEEDED; 6146 goto out; 6147 } 6148 6149 bytes -= towrite; 6150 data += towrite; 6151 addr += towrite; 6152 } 6153 out: 6154 return r; 6155 } 6156 6157 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 6158 unsigned int bytes, struct x86_exception *exception, 6159 bool system) 6160 { 6161 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6162 u32 access = PFERR_WRITE_MASK; 6163 6164 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6165 access |= PFERR_USER_MASK; 6166 6167 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6168 access, exception); 6169 } 6170 6171 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 6172 unsigned int bytes, struct x86_exception *exception) 6173 { 6174 /* kvm_write_guest_virt_system can pull in tons of pages. */ 6175 vcpu->arch.l1tf_flush_l1d = true; 6176 6177 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6178 PFERR_WRITE_MASK, exception); 6179 } 6180 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 6181 6182 int handle_ud(struct kvm_vcpu *vcpu) 6183 { 6184 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; 6185 int emul_type = EMULTYPE_TRAP_UD; 6186 char sig[5]; /* ud2; .ascii "kvm" */ 6187 struct x86_exception e; 6188 6189 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, NULL, 0))) 6190 return 1; 6191 6192 if (force_emulation_prefix && 6193 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 6194 sig, sizeof(sig), &e) == 0 && 6195 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { 6196 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 6197 emul_type = EMULTYPE_TRAP_UD_FORCED; 6198 } 6199 6200 return kvm_emulate_instruction(vcpu, emul_type); 6201 } 6202 EXPORT_SYMBOL_GPL(handle_ud); 6203 6204 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6205 gpa_t gpa, bool write) 6206 { 6207 /* For APIC access vmexit */ 6208 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 6209 return 1; 6210 6211 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 6212 trace_vcpu_match_mmio(gva, gpa, write, true); 6213 return 1; 6214 } 6215 6216 return 0; 6217 } 6218 6219 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6220 gpa_t *gpa, struct x86_exception *exception, 6221 bool write) 6222 { 6223 u32 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) 6224 | (write ? PFERR_WRITE_MASK : 0); 6225 6226 /* 6227 * currently PKRU is only applied to ept enabled guest so 6228 * there is no pkey in EPT page table for L1 guest or EPT 6229 * shadow page table for L2 guest. 6230 */ 6231 if (vcpu_match_mmio_gva(vcpu, gva) 6232 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 6233 vcpu->arch.mmio_access, 0, access)) { 6234 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 6235 (gva & (PAGE_SIZE - 1)); 6236 trace_vcpu_match_mmio(gva, *gpa, write, false); 6237 return 1; 6238 } 6239 6240 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6241 6242 if (*gpa == UNMAPPED_GVA) 6243 return -1; 6244 6245 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 6246 } 6247 6248 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 6249 const void *val, int bytes) 6250 { 6251 int ret; 6252 6253 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 6254 if (ret < 0) 6255 return 0; 6256 kvm_page_track_write(vcpu, gpa, val, bytes); 6257 return 1; 6258 } 6259 6260 struct read_write_emulator_ops { 6261 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 6262 int bytes); 6263 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 6264 void *val, int bytes); 6265 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6266 int bytes, void *val); 6267 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6268 void *val, int bytes); 6269 bool write; 6270 }; 6271 6272 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 6273 { 6274 if (vcpu->mmio_read_completed) { 6275 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 6276 vcpu->mmio_fragments[0].gpa, val); 6277 vcpu->mmio_read_completed = 0; 6278 return 1; 6279 } 6280 6281 return 0; 6282 } 6283 6284 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6285 void *val, int bytes) 6286 { 6287 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 6288 } 6289 6290 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6291 void *val, int bytes) 6292 { 6293 return emulator_write_phys(vcpu, gpa, val, bytes); 6294 } 6295 6296 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 6297 { 6298 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 6299 return vcpu_mmio_write(vcpu, gpa, bytes, val); 6300 } 6301 6302 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6303 void *val, int bytes) 6304 { 6305 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 6306 return X86EMUL_IO_NEEDED; 6307 } 6308 6309 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6310 void *val, int bytes) 6311 { 6312 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 6313 6314 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 6315 return X86EMUL_CONTINUE; 6316 } 6317 6318 static const struct read_write_emulator_ops read_emultor = { 6319 .read_write_prepare = read_prepare, 6320 .read_write_emulate = read_emulate, 6321 .read_write_mmio = vcpu_mmio_read, 6322 .read_write_exit_mmio = read_exit_mmio, 6323 }; 6324 6325 static const struct read_write_emulator_ops write_emultor = { 6326 .read_write_emulate = write_emulate, 6327 .read_write_mmio = write_mmio, 6328 .read_write_exit_mmio = write_exit_mmio, 6329 .write = true, 6330 }; 6331 6332 static int emulator_read_write_onepage(unsigned long addr, void *val, 6333 unsigned int bytes, 6334 struct x86_exception *exception, 6335 struct kvm_vcpu *vcpu, 6336 const struct read_write_emulator_ops *ops) 6337 { 6338 gpa_t gpa; 6339 int handled, ret; 6340 bool write = ops->write; 6341 struct kvm_mmio_fragment *frag; 6342 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6343 6344 /* 6345 * If the exit was due to a NPF we may already have a GPA. 6346 * If the GPA is present, use it to avoid the GVA to GPA table walk. 6347 * Note, this cannot be used on string operations since string 6348 * operation using rep will only have the initial GPA from the NPF 6349 * occurred. 6350 */ 6351 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && 6352 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { 6353 gpa = ctxt->gpa_val; 6354 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 6355 } else { 6356 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 6357 if (ret < 0) 6358 return X86EMUL_PROPAGATE_FAULT; 6359 } 6360 6361 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 6362 return X86EMUL_CONTINUE; 6363 6364 /* 6365 * Is this MMIO handled locally? 6366 */ 6367 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 6368 if (handled == bytes) 6369 return X86EMUL_CONTINUE; 6370 6371 gpa += handled; 6372 bytes -= handled; 6373 val += handled; 6374 6375 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 6376 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 6377 frag->gpa = gpa; 6378 frag->data = val; 6379 frag->len = bytes; 6380 return X86EMUL_CONTINUE; 6381 } 6382 6383 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 6384 unsigned long addr, 6385 void *val, unsigned int bytes, 6386 struct x86_exception *exception, 6387 const struct read_write_emulator_ops *ops) 6388 { 6389 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6390 gpa_t gpa; 6391 int rc; 6392 6393 if (ops->read_write_prepare && 6394 ops->read_write_prepare(vcpu, val, bytes)) 6395 return X86EMUL_CONTINUE; 6396 6397 vcpu->mmio_nr_fragments = 0; 6398 6399 /* Crossing a page boundary? */ 6400 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 6401 int now; 6402 6403 now = -addr & ~PAGE_MASK; 6404 rc = emulator_read_write_onepage(addr, val, now, exception, 6405 vcpu, ops); 6406 6407 if (rc != X86EMUL_CONTINUE) 6408 return rc; 6409 addr += now; 6410 if (ctxt->mode != X86EMUL_MODE_PROT64) 6411 addr = (u32)addr; 6412 val += now; 6413 bytes -= now; 6414 } 6415 6416 rc = emulator_read_write_onepage(addr, val, bytes, exception, 6417 vcpu, ops); 6418 if (rc != X86EMUL_CONTINUE) 6419 return rc; 6420 6421 if (!vcpu->mmio_nr_fragments) 6422 return rc; 6423 6424 gpa = vcpu->mmio_fragments[0].gpa; 6425 6426 vcpu->mmio_needed = 1; 6427 vcpu->mmio_cur_fragment = 0; 6428 6429 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 6430 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 6431 vcpu->run->exit_reason = KVM_EXIT_MMIO; 6432 vcpu->run->mmio.phys_addr = gpa; 6433 6434 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 6435 } 6436 6437 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 6438 unsigned long addr, 6439 void *val, 6440 unsigned int bytes, 6441 struct x86_exception *exception) 6442 { 6443 return emulator_read_write(ctxt, addr, val, bytes, 6444 exception, &read_emultor); 6445 } 6446 6447 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 6448 unsigned long addr, 6449 const void *val, 6450 unsigned int bytes, 6451 struct x86_exception *exception) 6452 { 6453 return emulator_read_write(ctxt, addr, (void *)val, bytes, 6454 exception, &write_emultor); 6455 } 6456 6457 #define CMPXCHG_TYPE(t, ptr, old, new) \ 6458 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 6459 6460 #ifdef CONFIG_X86_64 6461 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 6462 #else 6463 # define CMPXCHG64(ptr, old, new) \ 6464 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 6465 #endif 6466 6467 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 6468 unsigned long addr, 6469 const void *old, 6470 const void *new, 6471 unsigned int bytes, 6472 struct x86_exception *exception) 6473 { 6474 struct kvm_host_map map; 6475 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6476 u64 page_line_mask; 6477 gpa_t gpa; 6478 char *kaddr; 6479 bool exchanged; 6480 6481 /* guests cmpxchg8b have to be emulated atomically */ 6482 if (bytes > 8 || (bytes & (bytes - 1))) 6483 goto emul_write; 6484 6485 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 6486 6487 if (gpa == UNMAPPED_GVA || 6488 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 6489 goto emul_write; 6490 6491 /* 6492 * Emulate the atomic as a straight write to avoid #AC if SLD is 6493 * enabled in the host and the access splits a cache line. 6494 */ 6495 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 6496 page_line_mask = ~(cache_line_size() - 1); 6497 else 6498 page_line_mask = PAGE_MASK; 6499 6500 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) 6501 goto emul_write; 6502 6503 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) 6504 goto emul_write; 6505 6506 kaddr = map.hva + offset_in_page(gpa); 6507 6508 switch (bytes) { 6509 case 1: 6510 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 6511 break; 6512 case 2: 6513 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 6514 break; 6515 case 4: 6516 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 6517 break; 6518 case 8: 6519 exchanged = CMPXCHG64(kaddr, old, new); 6520 break; 6521 default: 6522 BUG(); 6523 } 6524 6525 kvm_vcpu_unmap(vcpu, &map, true); 6526 6527 if (!exchanged) 6528 return X86EMUL_CMPXCHG_FAILED; 6529 6530 kvm_page_track_write(vcpu, gpa, new, bytes); 6531 6532 return X86EMUL_CONTINUE; 6533 6534 emul_write: 6535 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 6536 6537 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 6538 } 6539 6540 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 6541 { 6542 int r = 0, i; 6543 6544 for (i = 0; i < vcpu->arch.pio.count; i++) { 6545 if (vcpu->arch.pio.in) 6546 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 6547 vcpu->arch.pio.size, pd); 6548 else 6549 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 6550 vcpu->arch.pio.port, vcpu->arch.pio.size, 6551 pd); 6552 if (r) 6553 break; 6554 pd += vcpu->arch.pio.size; 6555 } 6556 return r; 6557 } 6558 6559 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 6560 unsigned short port, void *val, 6561 unsigned int count, bool in) 6562 { 6563 vcpu->arch.pio.port = port; 6564 vcpu->arch.pio.in = in; 6565 vcpu->arch.pio.count = count; 6566 vcpu->arch.pio.size = size; 6567 6568 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 6569 vcpu->arch.pio.count = 0; 6570 return 1; 6571 } 6572 6573 vcpu->run->exit_reason = KVM_EXIT_IO; 6574 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 6575 vcpu->run->io.size = size; 6576 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 6577 vcpu->run->io.count = count; 6578 vcpu->run->io.port = port; 6579 6580 return 0; 6581 } 6582 6583 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, 6584 unsigned short port, void *val, unsigned int count) 6585 { 6586 int ret; 6587 6588 if (vcpu->arch.pio.count) 6589 goto data_avail; 6590 6591 memset(vcpu->arch.pio_data, 0, size * count); 6592 6593 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 6594 if (ret) { 6595 data_avail: 6596 memcpy(val, vcpu->arch.pio_data, size * count); 6597 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 6598 vcpu->arch.pio.count = 0; 6599 return 1; 6600 } 6601 6602 return 0; 6603 } 6604 6605 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 6606 int size, unsigned short port, void *val, 6607 unsigned int count) 6608 { 6609 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); 6610 6611 } 6612 6613 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, 6614 unsigned short port, const void *val, 6615 unsigned int count) 6616 { 6617 memcpy(vcpu->arch.pio_data, val, size * count); 6618 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 6619 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 6620 } 6621 6622 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 6623 int size, unsigned short port, 6624 const void *val, unsigned int count) 6625 { 6626 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); 6627 } 6628 6629 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 6630 { 6631 return static_call(kvm_x86_get_segment_base)(vcpu, seg); 6632 } 6633 6634 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 6635 { 6636 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 6637 } 6638 6639 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 6640 { 6641 if (!need_emulate_wbinvd(vcpu)) 6642 return X86EMUL_CONTINUE; 6643 6644 if (static_call(kvm_x86_has_wbinvd_exit)()) { 6645 int cpu = get_cpu(); 6646 6647 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 6648 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, 6649 wbinvd_ipi, NULL, 1); 6650 put_cpu(); 6651 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 6652 } else 6653 wbinvd(); 6654 return X86EMUL_CONTINUE; 6655 } 6656 6657 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 6658 { 6659 kvm_emulate_wbinvd_noskip(vcpu); 6660 return kvm_skip_emulated_instruction(vcpu); 6661 } 6662 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 6663 6664 6665 6666 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 6667 { 6668 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 6669 } 6670 6671 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 6672 unsigned long *dest) 6673 { 6674 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 6675 } 6676 6677 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 6678 unsigned long value) 6679 { 6680 6681 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 6682 } 6683 6684 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 6685 { 6686 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 6687 } 6688 6689 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 6690 { 6691 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6692 unsigned long value; 6693 6694 switch (cr) { 6695 case 0: 6696 value = kvm_read_cr0(vcpu); 6697 break; 6698 case 2: 6699 value = vcpu->arch.cr2; 6700 break; 6701 case 3: 6702 value = kvm_read_cr3(vcpu); 6703 break; 6704 case 4: 6705 value = kvm_read_cr4(vcpu); 6706 break; 6707 case 8: 6708 value = kvm_get_cr8(vcpu); 6709 break; 6710 default: 6711 kvm_err("%s: unexpected cr %u\n", __func__, cr); 6712 return 0; 6713 } 6714 6715 return value; 6716 } 6717 6718 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 6719 { 6720 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6721 int res = 0; 6722 6723 switch (cr) { 6724 case 0: 6725 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 6726 break; 6727 case 2: 6728 vcpu->arch.cr2 = val; 6729 break; 6730 case 3: 6731 res = kvm_set_cr3(vcpu, val); 6732 break; 6733 case 4: 6734 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 6735 break; 6736 case 8: 6737 res = kvm_set_cr8(vcpu, val); 6738 break; 6739 default: 6740 kvm_err("%s: unexpected cr %u\n", __func__, cr); 6741 res = -1; 6742 } 6743 6744 return res; 6745 } 6746 6747 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 6748 { 6749 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); 6750 } 6751 6752 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6753 { 6754 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); 6755 } 6756 6757 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6758 { 6759 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); 6760 } 6761 6762 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6763 { 6764 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); 6765 } 6766 6767 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6768 { 6769 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); 6770 } 6771 6772 static unsigned long emulator_get_cached_segment_base( 6773 struct x86_emulate_ctxt *ctxt, int seg) 6774 { 6775 return get_segment_base(emul_to_vcpu(ctxt), seg); 6776 } 6777 6778 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 6779 struct desc_struct *desc, u32 *base3, 6780 int seg) 6781 { 6782 struct kvm_segment var; 6783 6784 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 6785 *selector = var.selector; 6786 6787 if (var.unusable) { 6788 memset(desc, 0, sizeof(*desc)); 6789 if (base3) 6790 *base3 = 0; 6791 return false; 6792 } 6793 6794 if (var.g) 6795 var.limit >>= 12; 6796 set_desc_limit(desc, var.limit); 6797 set_desc_base(desc, (unsigned long)var.base); 6798 #ifdef CONFIG_X86_64 6799 if (base3) 6800 *base3 = var.base >> 32; 6801 #endif 6802 desc->type = var.type; 6803 desc->s = var.s; 6804 desc->dpl = var.dpl; 6805 desc->p = var.present; 6806 desc->avl = var.avl; 6807 desc->l = var.l; 6808 desc->d = var.db; 6809 desc->g = var.g; 6810 6811 return true; 6812 } 6813 6814 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 6815 struct desc_struct *desc, u32 base3, 6816 int seg) 6817 { 6818 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6819 struct kvm_segment var; 6820 6821 var.selector = selector; 6822 var.base = get_desc_base(desc); 6823 #ifdef CONFIG_X86_64 6824 var.base |= ((u64)base3) << 32; 6825 #endif 6826 var.limit = get_desc_limit(desc); 6827 if (desc->g) 6828 var.limit = (var.limit << 12) | 0xfff; 6829 var.type = desc->type; 6830 var.dpl = desc->dpl; 6831 var.db = desc->d; 6832 var.s = desc->s; 6833 var.l = desc->l; 6834 var.g = desc->g; 6835 var.avl = desc->avl; 6836 var.present = desc->p; 6837 var.unusable = !var.present; 6838 var.padding = 0; 6839 6840 kvm_set_segment(vcpu, &var, seg); 6841 return; 6842 } 6843 6844 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 6845 u32 msr_index, u64 *pdata) 6846 { 6847 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6848 int r; 6849 6850 r = kvm_get_msr(vcpu, msr_index, pdata); 6851 6852 if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) { 6853 /* Bounce to user space */ 6854 return X86EMUL_IO_NEEDED; 6855 } 6856 6857 return r; 6858 } 6859 6860 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 6861 u32 msr_index, u64 data) 6862 { 6863 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6864 int r; 6865 6866 r = kvm_set_msr(vcpu, msr_index, data); 6867 6868 if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) { 6869 /* Bounce to user space */ 6870 return X86EMUL_IO_NEEDED; 6871 } 6872 6873 return r; 6874 } 6875 6876 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 6877 { 6878 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6879 6880 return vcpu->arch.smbase; 6881 } 6882 6883 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 6884 { 6885 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6886 6887 vcpu->arch.smbase = smbase; 6888 } 6889 6890 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 6891 u32 pmc) 6892 { 6893 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); 6894 } 6895 6896 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 6897 u32 pmc, u64 *pdata) 6898 { 6899 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 6900 } 6901 6902 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 6903 { 6904 emul_to_vcpu(ctxt)->arch.halt_request = 1; 6905 } 6906 6907 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 6908 struct x86_instruction_info *info, 6909 enum x86_intercept_stage stage) 6910 { 6911 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, 6912 &ctxt->exception); 6913 } 6914 6915 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 6916 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, 6917 bool exact_only) 6918 { 6919 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); 6920 } 6921 6922 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) 6923 { 6924 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); 6925 } 6926 6927 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) 6928 { 6929 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); 6930 } 6931 6932 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) 6933 { 6934 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); 6935 } 6936 6937 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 6938 { 6939 return kvm_register_read(emul_to_vcpu(ctxt), reg); 6940 } 6941 6942 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 6943 { 6944 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 6945 } 6946 6947 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 6948 { 6949 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); 6950 } 6951 6952 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 6953 { 6954 return emul_to_vcpu(ctxt)->arch.hflags; 6955 } 6956 6957 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) 6958 { 6959 emul_to_vcpu(ctxt)->arch.hflags = emul_flags; 6960 } 6961 6962 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, 6963 const char *smstate) 6964 { 6965 return static_call(kvm_x86_pre_leave_smm)(emul_to_vcpu(ctxt), smstate); 6966 } 6967 6968 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) 6969 { 6970 kvm_smm_changed(emul_to_vcpu(ctxt)); 6971 } 6972 6973 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) 6974 { 6975 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); 6976 } 6977 6978 static const struct x86_emulate_ops emulate_ops = { 6979 .read_gpr = emulator_read_gpr, 6980 .write_gpr = emulator_write_gpr, 6981 .read_std = emulator_read_std, 6982 .write_std = emulator_write_std, 6983 .read_phys = kvm_read_guest_phys_system, 6984 .fetch = kvm_fetch_guest_virt, 6985 .read_emulated = emulator_read_emulated, 6986 .write_emulated = emulator_write_emulated, 6987 .cmpxchg_emulated = emulator_cmpxchg_emulated, 6988 .invlpg = emulator_invlpg, 6989 .pio_in_emulated = emulator_pio_in_emulated, 6990 .pio_out_emulated = emulator_pio_out_emulated, 6991 .get_segment = emulator_get_segment, 6992 .set_segment = emulator_set_segment, 6993 .get_cached_segment_base = emulator_get_cached_segment_base, 6994 .get_gdt = emulator_get_gdt, 6995 .get_idt = emulator_get_idt, 6996 .set_gdt = emulator_set_gdt, 6997 .set_idt = emulator_set_idt, 6998 .get_cr = emulator_get_cr, 6999 .set_cr = emulator_set_cr, 7000 .cpl = emulator_get_cpl, 7001 .get_dr = emulator_get_dr, 7002 .set_dr = emulator_set_dr, 7003 .get_smbase = emulator_get_smbase, 7004 .set_smbase = emulator_set_smbase, 7005 .set_msr = emulator_set_msr, 7006 .get_msr = emulator_get_msr, 7007 .check_pmc = emulator_check_pmc, 7008 .read_pmc = emulator_read_pmc, 7009 .halt = emulator_halt, 7010 .wbinvd = emulator_wbinvd, 7011 .fix_hypercall = emulator_fix_hypercall, 7012 .intercept = emulator_intercept, 7013 .get_cpuid = emulator_get_cpuid, 7014 .guest_has_long_mode = emulator_guest_has_long_mode, 7015 .guest_has_movbe = emulator_guest_has_movbe, 7016 .guest_has_fxsr = emulator_guest_has_fxsr, 7017 .set_nmi_mask = emulator_set_nmi_mask, 7018 .get_hflags = emulator_get_hflags, 7019 .set_hflags = emulator_set_hflags, 7020 .pre_leave_smm = emulator_pre_leave_smm, 7021 .post_leave_smm = emulator_post_leave_smm, 7022 .set_xcr = emulator_set_xcr, 7023 }; 7024 7025 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 7026 { 7027 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 7028 /* 7029 * an sti; sti; sequence only disable interrupts for the first 7030 * instruction. So, if the last instruction, be it emulated or 7031 * not, left the system with the INT_STI flag enabled, it 7032 * means that the last instruction is an sti. We should not 7033 * leave the flag on in this case. The same goes for mov ss 7034 */ 7035 if (int_shadow & mask) 7036 mask = 0; 7037 if (unlikely(int_shadow || mask)) { 7038 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); 7039 if (!mask) 7040 kvm_make_request(KVM_REQ_EVENT, vcpu); 7041 } 7042 } 7043 7044 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 7045 { 7046 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7047 if (ctxt->exception.vector == PF_VECTOR) 7048 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); 7049 7050 if (ctxt->exception.error_code_valid) 7051 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 7052 ctxt->exception.error_code); 7053 else 7054 kvm_queue_exception(vcpu, ctxt->exception.vector); 7055 return false; 7056 } 7057 7058 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) 7059 { 7060 struct x86_emulate_ctxt *ctxt; 7061 7062 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); 7063 if (!ctxt) { 7064 pr_err("kvm: failed to allocate vcpu's emulator\n"); 7065 return NULL; 7066 } 7067 7068 ctxt->vcpu = vcpu; 7069 ctxt->ops = &emulate_ops; 7070 vcpu->arch.emulate_ctxt = ctxt; 7071 7072 return ctxt; 7073 } 7074 7075 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 7076 { 7077 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7078 int cs_db, cs_l; 7079 7080 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 7081 7082 ctxt->gpa_available = false; 7083 ctxt->eflags = kvm_get_rflags(vcpu); 7084 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 7085 7086 ctxt->eip = kvm_rip_read(vcpu); 7087 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 7088 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 7089 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 7090 cs_db ? X86EMUL_MODE_PROT32 : 7091 X86EMUL_MODE_PROT16; 7092 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 7093 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 7094 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 7095 7096 init_decode_cache(ctxt); 7097 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 7098 } 7099 7100 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 7101 { 7102 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7103 int ret; 7104 7105 init_emulate_ctxt(vcpu); 7106 7107 ctxt->op_bytes = 2; 7108 ctxt->ad_bytes = 2; 7109 ctxt->_eip = ctxt->eip + inc_eip; 7110 ret = emulate_int_real(ctxt, irq); 7111 7112 if (ret != X86EMUL_CONTINUE) { 7113 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 7114 } else { 7115 ctxt->eip = ctxt->_eip; 7116 kvm_rip_write(vcpu, ctxt->eip); 7117 kvm_set_rflags(vcpu, ctxt->eflags); 7118 } 7119 } 7120 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 7121 7122 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 7123 { 7124 ++vcpu->stat.insn_emulation_fail; 7125 trace_kvm_emulate_insn_failed(vcpu); 7126 7127 if (emulation_type & EMULTYPE_VMWARE_GP) { 7128 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 7129 return 1; 7130 } 7131 7132 if (emulation_type & EMULTYPE_SKIP) { 7133 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 7134 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 7135 vcpu->run->internal.ndata = 0; 7136 return 0; 7137 } 7138 7139 kvm_queue_exception(vcpu, UD_VECTOR); 7140 7141 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { 7142 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 7143 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 7144 vcpu->run->internal.ndata = 0; 7145 return 0; 7146 } 7147 7148 return 1; 7149 } 7150 7151 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 7152 bool write_fault_to_shadow_pgtable, 7153 int emulation_type) 7154 { 7155 gpa_t gpa = cr2_or_gpa; 7156 kvm_pfn_t pfn; 7157 7158 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7159 return false; 7160 7161 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7162 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7163 return false; 7164 7165 if (!vcpu->arch.mmu->direct_map) { 7166 /* 7167 * Write permission should be allowed since only 7168 * write access need to be emulated. 7169 */ 7170 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 7171 7172 /* 7173 * If the mapping is invalid in guest, let cpu retry 7174 * it to generate fault. 7175 */ 7176 if (gpa == UNMAPPED_GVA) 7177 return true; 7178 } 7179 7180 /* 7181 * Do not retry the unhandleable instruction if it faults on the 7182 * readonly host memory, otherwise it will goto a infinite loop: 7183 * retry instruction -> write #PF -> emulation fail -> retry 7184 * instruction -> ... 7185 */ 7186 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 7187 7188 /* 7189 * If the instruction failed on the error pfn, it can not be fixed, 7190 * report the error to userspace. 7191 */ 7192 if (is_error_noslot_pfn(pfn)) 7193 return false; 7194 7195 kvm_release_pfn_clean(pfn); 7196 7197 /* The instructions are well-emulated on direct mmu. */ 7198 if (vcpu->arch.mmu->direct_map) { 7199 unsigned int indirect_shadow_pages; 7200 7201 write_lock(&vcpu->kvm->mmu_lock); 7202 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 7203 write_unlock(&vcpu->kvm->mmu_lock); 7204 7205 if (indirect_shadow_pages) 7206 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7207 7208 return true; 7209 } 7210 7211 /* 7212 * if emulation was due to access to shadowed page table 7213 * and it failed try to unshadow page and re-enter the 7214 * guest to let CPU execute the instruction. 7215 */ 7216 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7217 7218 /* 7219 * If the access faults on its page table, it can not 7220 * be fixed by unprotecting shadow page and it should 7221 * be reported to userspace. 7222 */ 7223 return !write_fault_to_shadow_pgtable; 7224 } 7225 7226 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 7227 gpa_t cr2_or_gpa, int emulation_type) 7228 { 7229 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7230 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; 7231 7232 last_retry_eip = vcpu->arch.last_retry_eip; 7233 last_retry_addr = vcpu->arch.last_retry_addr; 7234 7235 /* 7236 * If the emulation is caused by #PF and it is non-page_table 7237 * writing instruction, it means the VM-EXIT is caused by shadow 7238 * page protected, we can zap the shadow page and retry this 7239 * instruction directly. 7240 * 7241 * Note: if the guest uses a non-page-table modifying instruction 7242 * on the PDE that points to the instruction, then we will unmap 7243 * the instruction and go to an infinite loop. So, we cache the 7244 * last retried eip and the last fault address, if we meet the eip 7245 * and the address again, we can break out of the potential infinite 7246 * loop. 7247 */ 7248 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 7249 7250 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7251 return false; 7252 7253 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7254 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7255 return false; 7256 7257 if (x86_page_table_writing_insn(ctxt)) 7258 return false; 7259 7260 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) 7261 return false; 7262 7263 vcpu->arch.last_retry_eip = ctxt->eip; 7264 vcpu->arch.last_retry_addr = cr2_or_gpa; 7265 7266 if (!vcpu->arch.mmu->direct_map) 7267 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 7268 7269 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7270 7271 return true; 7272 } 7273 7274 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 7275 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 7276 7277 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 7278 { 7279 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 7280 /* This is a good place to trace that we are exiting SMM. */ 7281 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 7282 7283 /* Process a latched INIT or SMI, if any. */ 7284 kvm_make_request(KVM_REQ_EVENT, vcpu); 7285 } 7286 7287 kvm_mmu_reset_context(vcpu); 7288 } 7289 7290 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 7291 unsigned long *db) 7292 { 7293 u32 dr6 = 0; 7294 int i; 7295 u32 enable, rwlen; 7296 7297 enable = dr7; 7298 rwlen = dr7 >> 16; 7299 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 7300 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 7301 dr6 |= (1 << i); 7302 return dr6; 7303 } 7304 7305 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) 7306 { 7307 struct kvm_run *kvm_run = vcpu->run; 7308 7309 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 7310 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; 7311 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); 7312 kvm_run->debug.arch.exception = DB_VECTOR; 7313 kvm_run->exit_reason = KVM_EXIT_DEBUG; 7314 return 0; 7315 } 7316 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 7317 return 1; 7318 } 7319 7320 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 7321 { 7322 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 7323 int r; 7324 7325 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); 7326 if (unlikely(!r)) 7327 return 0; 7328 7329 /* 7330 * rflags is the old, "raw" value of the flags. The new value has 7331 * not been saved yet. 7332 * 7333 * This is correct even for TF set by the guest, because "the 7334 * processor will not generate this exception after the instruction 7335 * that sets the TF flag". 7336 */ 7337 if (unlikely(rflags & X86_EFLAGS_TF)) 7338 r = kvm_vcpu_do_singlestep(vcpu); 7339 return r; 7340 } 7341 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 7342 7343 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 7344 { 7345 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 7346 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 7347 struct kvm_run *kvm_run = vcpu->run; 7348 unsigned long eip = kvm_get_linear_rip(vcpu); 7349 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 7350 vcpu->arch.guest_debug_dr7, 7351 vcpu->arch.eff_db); 7352 7353 if (dr6 != 0) { 7354 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; 7355 kvm_run->debug.arch.pc = eip; 7356 kvm_run->debug.arch.exception = DB_VECTOR; 7357 kvm_run->exit_reason = KVM_EXIT_DEBUG; 7358 *r = 0; 7359 return true; 7360 } 7361 } 7362 7363 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 7364 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 7365 unsigned long eip = kvm_get_linear_rip(vcpu); 7366 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 7367 vcpu->arch.dr7, 7368 vcpu->arch.db); 7369 7370 if (dr6 != 0) { 7371 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); 7372 *r = 1; 7373 return true; 7374 } 7375 } 7376 7377 return false; 7378 } 7379 7380 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 7381 { 7382 switch (ctxt->opcode_len) { 7383 case 1: 7384 switch (ctxt->b) { 7385 case 0xe4: /* IN */ 7386 case 0xe5: 7387 case 0xec: 7388 case 0xed: 7389 case 0xe6: /* OUT */ 7390 case 0xe7: 7391 case 0xee: 7392 case 0xef: 7393 case 0x6c: /* INS */ 7394 case 0x6d: 7395 case 0x6e: /* OUTS */ 7396 case 0x6f: 7397 return true; 7398 } 7399 break; 7400 case 2: 7401 switch (ctxt->b) { 7402 case 0x33: /* RDPMC */ 7403 return true; 7404 } 7405 break; 7406 } 7407 7408 return false; 7409 } 7410 7411 /* 7412 * Decode to be emulated instruction. Return EMULATION_OK if success. 7413 */ 7414 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 7415 void *insn, int insn_len) 7416 { 7417 int r = EMULATION_OK; 7418 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7419 7420 init_emulate_ctxt(vcpu); 7421 7422 /* 7423 * We will reenter on the same instruction since we do not set 7424 * complete_userspace_io. This does not handle watchpoints yet, 7425 * those would be handled in the emulate_ops. 7426 */ 7427 if (!(emulation_type & EMULTYPE_SKIP) && 7428 kvm_vcpu_check_breakpoint(vcpu, &r)) 7429 return r; 7430 7431 ctxt->interruptibility = 0; 7432 ctxt->have_exception = false; 7433 ctxt->exception.vector = -1; 7434 ctxt->perm_ok = false; 7435 7436 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 7437 7438 r = x86_decode_insn(ctxt, insn, insn_len); 7439 7440 trace_kvm_emulate_insn_start(vcpu); 7441 ++vcpu->stat.insn_emulation; 7442 7443 return r; 7444 } 7445 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); 7446 7447 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 7448 int emulation_type, void *insn, int insn_len) 7449 { 7450 int r; 7451 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7452 bool writeback = true; 7453 bool write_fault_to_spt; 7454 7455 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, insn, insn_len))) 7456 return 1; 7457 7458 vcpu->arch.l1tf_flush_l1d = true; 7459 7460 /* 7461 * Clear write_fault_to_shadow_pgtable here to ensure it is 7462 * never reused. 7463 */ 7464 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 7465 vcpu->arch.write_fault_to_shadow_pgtable = false; 7466 7467 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 7468 kvm_clear_exception_queue(vcpu); 7469 7470 r = x86_decode_emulated_instruction(vcpu, emulation_type, 7471 insn, insn_len); 7472 if (r != EMULATION_OK) { 7473 if ((emulation_type & EMULTYPE_TRAP_UD) || 7474 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { 7475 kvm_queue_exception(vcpu, UD_VECTOR); 7476 return 1; 7477 } 7478 if (reexecute_instruction(vcpu, cr2_or_gpa, 7479 write_fault_to_spt, 7480 emulation_type)) 7481 return 1; 7482 if (ctxt->have_exception) { 7483 /* 7484 * #UD should result in just EMULATION_FAILED, and trap-like 7485 * exception should not be encountered during decode. 7486 */ 7487 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || 7488 exception_type(ctxt->exception.vector) == EXCPT_TRAP); 7489 inject_emulated_exception(vcpu); 7490 return 1; 7491 } 7492 return handle_emulation_failure(vcpu, emulation_type); 7493 } 7494 } 7495 7496 if ((emulation_type & EMULTYPE_VMWARE_GP) && 7497 !is_vmware_backdoor_opcode(ctxt)) { 7498 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 7499 return 1; 7500 } 7501 7502 /* 7503 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks 7504 * for kvm_skip_emulated_instruction(). The caller is responsible for 7505 * updating interruptibility state and injecting single-step #DBs. 7506 */ 7507 if (emulation_type & EMULTYPE_SKIP) { 7508 kvm_rip_write(vcpu, ctxt->_eip); 7509 if (ctxt->eflags & X86_EFLAGS_RF) 7510 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 7511 return 1; 7512 } 7513 7514 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) 7515 return 1; 7516 7517 /* this is needed for vmware backdoor interface to work since it 7518 changes registers values during IO operation */ 7519 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 7520 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 7521 emulator_invalidate_register_cache(ctxt); 7522 } 7523 7524 restart: 7525 if (emulation_type & EMULTYPE_PF) { 7526 /* Save the faulting GPA (cr2) in the address field */ 7527 ctxt->exception.address = cr2_or_gpa; 7528 7529 /* With shadow page tables, cr2 contains a GVA or nGPA. */ 7530 if (vcpu->arch.mmu->direct_map) { 7531 ctxt->gpa_available = true; 7532 ctxt->gpa_val = cr2_or_gpa; 7533 } 7534 } else { 7535 /* Sanitize the address out of an abundance of paranoia. */ 7536 ctxt->exception.address = 0; 7537 } 7538 7539 r = x86_emulate_insn(ctxt); 7540 7541 if (r == EMULATION_INTERCEPTED) 7542 return 1; 7543 7544 if (r == EMULATION_FAILED) { 7545 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, 7546 emulation_type)) 7547 return 1; 7548 7549 return handle_emulation_failure(vcpu, emulation_type); 7550 } 7551 7552 if (ctxt->have_exception) { 7553 r = 1; 7554 if (inject_emulated_exception(vcpu)) 7555 return r; 7556 } else if (vcpu->arch.pio.count) { 7557 if (!vcpu->arch.pio.in) { 7558 /* FIXME: return into emulator if single-stepping. */ 7559 vcpu->arch.pio.count = 0; 7560 } else { 7561 writeback = false; 7562 vcpu->arch.complete_userspace_io = complete_emulated_pio; 7563 } 7564 r = 0; 7565 } else if (vcpu->mmio_needed) { 7566 ++vcpu->stat.mmio_exits; 7567 7568 if (!vcpu->mmio_is_write) 7569 writeback = false; 7570 r = 0; 7571 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 7572 } else if (r == EMULATION_RESTART) 7573 goto restart; 7574 else 7575 r = 1; 7576 7577 if (writeback) { 7578 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 7579 toggle_interruptibility(vcpu, ctxt->interruptibility); 7580 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7581 if (!ctxt->have_exception || 7582 exception_type(ctxt->exception.vector) == EXCPT_TRAP) { 7583 kvm_rip_write(vcpu, ctxt->eip); 7584 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 7585 r = kvm_vcpu_do_singlestep(vcpu); 7586 if (kvm_x86_ops.update_emulated_instruction) 7587 static_call(kvm_x86_update_emulated_instruction)(vcpu); 7588 __kvm_set_rflags(vcpu, ctxt->eflags); 7589 } 7590 7591 /* 7592 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 7593 * do nothing, and it will be requested again as soon as 7594 * the shadow expires. But we still need to check here, 7595 * because POPF has no interrupt shadow. 7596 */ 7597 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 7598 kvm_make_request(KVM_REQ_EVENT, vcpu); 7599 } else 7600 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 7601 7602 return r; 7603 } 7604 7605 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 7606 { 7607 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 7608 } 7609 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 7610 7611 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 7612 void *insn, int insn_len) 7613 { 7614 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 7615 } 7616 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 7617 7618 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 7619 { 7620 vcpu->arch.pio.count = 0; 7621 return 1; 7622 } 7623 7624 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 7625 { 7626 vcpu->arch.pio.count = 0; 7627 7628 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 7629 return 1; 7630 7631 return kvm_skip_emulated_instruction(vcpu); 7632 } 7633 7634 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 7635 unsigned short port) 7636 { 7637 unsigned long val = kvm_rax_read(vcpu); 7638 int ret = emulator_pio_out(vcpu, size, port, &val, 1); 7639 7640 if (ret) 7641 return ret; 7642 7643 /* 7644 * Workaround userspace that relies on old KVM behavior of %rip being 7645 * incremented prior to exiting to userspace to handle "OUT 0x7e". 7646 */ 7647 if (port == 0x7e && 7648 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 7649 vcpu->arch.complete_userspace_io = 7650 complete_fast_pio_out_port_0x7e; 7651 kvm_skip_emulated_instruction(vcpu); 7652 } else { 7653 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 7654 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 7655 } 7656 return 0; 7657 } 7658 7659 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 7660 { 7661 unsigned long val; 7662 7663 /* We should only ever be called with arch.pio.count equal to 1 */ 7664 BUG_ON(vcpu->arch.pio.count != 1); 7665 7666 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 7667 vcpu->arch.pio.count = 0; 7668 return 1; 7669 } 7670 7671 /* For size less than 4 we merge, else we zero extend */ 7672 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 7673 7674 /* 7675 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform 7676 * the copy and tracing 7677 */ 7678 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); 7679 kvm_rax_write(vcpu, val); 7680 7681 return kvm_skip_emulated_instruction(vcpu); 7682 } 7683 7684 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 7685 unsigned short port) 7686 { 7687 unsigned long val; 7688 int ret; 7689 7690 /* For size less than 4 we merge, else we zero extend */ 7691 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 7692 7693 ret = emulator_pio_in(vcpu, size, port, &val, 1); 7694 if (ret) { 7695 kvm_rax_write(vcpu, val); 7696 return ret; 7697 } 7698 7699 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 7700 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 7701 7702 return 0; 7703 } 7704 7705 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 7706 { 7707 int ret; 7708 7709 if (in) 7710 ret = kvm_fast_pio_in(vcpu, size, port); 7711 else 7712 ret = kvm_fast_pio_out(vcpu, size, port); 7713 return ret && kvm_skip_emulated_instruction(vcpu); 7714 } 7715 EXPORT_SYMBOL_GPL(kvm_fast_pio); 7716 7717 static int kvmclock_cpu_down_prep(unsigned int cpu) 7718 { 7719 __this_cpu_write(cpu_tsc_khz, 0); 7720 return 0; 7721 } 7722 7723 static void tsc_khz_changed(void *data) 7724 { 7725 struct cpufreq_freqs *freq = data; 7726 unsigned long khz = 0; 7727 7728 if (data) 7729 khz = freq->new; 7730 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 7731 khz = cpufreq_quick_get(raw_smp_processor_id()); 7732 if (!khz) 7733 khz = tsc_khz; 7734 __this_cpu_write(cpu_tsc_khz, khz); 7735 } 7736 7737 #ifdef CONFIG_X86_64 7738 static void kvm_hyperv_tsc_notifier(void) 7739 { 7740 struct kvm *kvm; 7741 struct kvm_vcpu *vcpu; 7742 int cpu; 7743 unsigned long flags; 7744 7745 mutex_lock(&kvm_lock); 7746 list_for_each_entry(kvm, &vm_list, vm_list) 7747 kvm_make_mclock_inprogress_request(kvm); 7748 7749 hyperv_stop_tsc_emulation(); 7750 7751 /* TSC frequency always matches when on Hyper-V */ 7752 for_each_present_cpu(cpu) 7753 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 7754 kvm_max_guest_tsc_khz = tsc_khz; 7755 7756 list_for_each_entry(kvm, &vm_list, vm_list) { 7757 struct kvm_arch *ka = &kvm->arch; 7758 7759 spin_lock_irqsave(&ka->pvclock_gtod_sync_lock, flags); 7760 pvclock_update_vm_gtod_copy(kvm); 7761 spin_unlock_irqrestore(&ka->pvclock_gtod_sync_lock, flags); 7762 7763 kvm_for_each_vcpu(cpu, vcpu, kvm) 7764 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7765 7766 kvm_for_each_vcpu(cpu, vcpu, kvm) 7767 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 7768 } 7769 mutex_unlock(&kvm_lock); 7770 } 7771 #endif 7772 7773 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 7774 { 7775 struct kvm *kvm; 7776 struct kvm_vcpu *vcpu; 7777 int i, send_ipi = 0; 7778 7779 /* 7780 * We allow guests to temporarily run on slowing clocks, 7781 * provided we notify them after, or to run on accelerating 7782 * clocks, provided we notify them before. Thus time never 7783 * goes backwards. 7784 * 7785 * However, we have a problem. We can't atomically update 7786 * the frequency of a given CPU from this function; it is 7787 * merely a notifier, which can be called from any CPU. 7788 * Changing the TSC frequency at arbitrary points in time 7789 * requires a recomputation of local variables related to 7790 * the TSC for each VCPU. We must flag these local variables 7791 * to be updated and be sure the update takes place with the 7792 * new frequency before any guests proceed. 7793 * 7794 * Unfortunately, the combination of hotplug CPU and frequency 7795 * change creates an intractable locking scenario; the order 7796 * of when these callouts happen is undefined with respect to 7797 * CPU hotplug, and they can race with each other. As such, 7798 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 7799 * undefined; you can actually have a CPU frequency change take 7800 * place in between the computation of X and the setting of the 7801 * variable. To protect against this problem, all updates of 7802 * the per_cpu tsc_khz variable are done in an interrupt 7803 * protected IPI, and all callers wishing to update the value 7804 * must wait for a synchronous IPI to complete (which is trivial 7805 * if the caller is on the CPU already). This establishes the 7806 * necessary total order on variable updates. 7807 * 7808 * Note that because a guest time update may take place 7809 * anytime after the setting of the VCPU's request bit, the 7810 * correct TSC value must be set before the request. However, 7811 * to ensure the update actually makes it to any guest which 7812 * starts running in hardware virtualization between the set 7813 * and the acquisition of the spinlock, we must also ping the 7814 * CPU after setting the request bit. 7815 * 7816 */ 7817 7818 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 7819 7820 mutex_lock(&kvm_lock); 7821 list_for_each_entry(kvm, &vm_list, vm_list) { 7822 kvm_for_each_vcpu(i, vcpu, kvm) { 7823 if (vcpu->cpu != cpu) 7824 continue; 7825 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7826 if (vcpu->cpu != raw_smp_processor_id()) 7827 send_ipi = 1; 7828 } 7829 } 7830 mutex_unlock(&kvm_lock); 7831 7832 if (freq->old < freq->new && send_ipi) { 7833 /* 7834 * We upscale the frequency. Must make the guest 7835 * doesn't see old kvmclock values while running with 7836 * the new frequency, otherwise we risk the guest sees 7837 * time go backwards. 7838 * 7839 * In case we update the frequency for another cpu 7840 * (which might be in guest context) send an interrupt 7841 * to kick the cpu out of guest context. Next time 7842 * guest context is entered kvmclock will be updated, 7843 * so the guest will not see stale values. 7844 */ 7845 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 7846 } 7847 } 7848 7849 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 7850 void *data) 7851 { 7852 struct cpufreq_freqs *freq = data; 7853 int cpu; 7854 7855 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 7856 return 0; 7857 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 7858 return 0; 7859 7860 for_each_cpu(cpu, freq->policy->cpus) 7861 __kvmclock_cpufreq_notifier(freq, cpu); 7862 7863 return 0; 7864 } 7865 7866 static struct notifier_block kvmclock_cpufreq_notifier_block = { 7867 .notifier_call = kvmclock_cpufreq_notifier 7868 }; 7869 7870 static int kvmclock_cpu_online(unsigned int cpu) 7871 { 7872 tsc_khz_changed(NULL); 7873 return 0; 7874 } 7875 7876 static void kvm_timer_init(void) 7877 { 7878 max_tsc_khz = tsc_khz; 7879 7880 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 7881 #ifdef CONFIG_CPU_FREQ 7882 struct cpufreq_policy *policy; 7883 int cpu; 7884 7885 cpu = get_cpu(); 7886 policy = cpufreq_cpu_get(cpu); 7887 if (policy) { 7888 if (policy->cpuinfo.max_freq) 7889 max_tsc_khz = policy->cpuinfo.max_freq; 7890 cpufreq_cpu_put(policy); 7891 } 7892 put_cpu(); 7893 #endif 7894 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 7895 CPUFREQ_TRANSITION_NOTIFIER); 7896 } 7897 7898 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 7899 kvmclock_cpu_online, kvmclock_cpu_down_prep); 7900 } 7901 7902 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 7903 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); 7904 7905 int kvm_is_in_guest(void) 7906 { 7907 return __this_cpu_read(current_vcpu) != NULL; 7908 } 7909 7910 static int kvm_is_user_mode(void) 7911 { 7912 int user_mode = 3; 7913 7914 if (__this_cpu_read(current_vcpu)) 7915 user_mode = static_call(kvm_x86_get_cpl)(__this_cpu_read(current_vcpu)); 7916 7917 return user_mode != 0; 7918 } 7919 7920 static unsigned long kvm_get_guest_ip(void) 7921 { 7922 unsigned long ip = 0; 7923 7924 if (__this_cpu_read(current_vcpu)) 7925 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 7926 7927 return ip; 7928 } 7929 7930 static void kvm_handle_intel_pt_intr(void) 7931 { 7932 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); 7933 7934 kvm_make_request(KVM_REQ_PMI, vcpu); 7935 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, 7936 (unsigned long *)&vcpu->arch.pmu.global_status); 7937 } 7938 7939 static struct perf_guest_info_callbacks kvm_guest_cbs = { 7940 .is_in_guest = kvm_is_in_guest, 7941 .is_user_mode = kvm_is_user_mode, 7942 .get_guest_ip = kvm_get_guest_ip, 7943 .handle_intel_pt_intr = kvm_handle_intel_pt_intr, 7944 }; 7945 7946 #ifdef CONFIG_X86_64 7947 static void pvclock_gtod_update_fn(struct work_struct *work) 7948 { 7949 struct kvm *kvm; 7950 7951 struct kvm_vcpu *vcpu; 7952 int i; 7953 7954 mutex_lock(&kvm_lock); 7955 list_for_each_entry(kvm, &vm_list, vm_list) 7956 kvm_for_each_vcpu(i, vcpu, kvm) 7957 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7958 atomic_set(&kvm_guest_has_master_clock, 0); 7959 mutex_unlock(&kvm_lock); 7960 } 7961 7962 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 7963 7964 /* 7965 * Notification about pvclock gtod data update. 7966 */ 7967 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 7968 void *priv) 7969 { 7970 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 7971 struct timekeeper *tk = priv; 7972 7973 update_pvclock_gtod(tk); 7974 7975 /* disable master clock if host does not trust, or does not 7976 * use, TSC based clocksource. 7977 */ 7978 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 7979 atomic_read(&kvm_guest_has_master_clock) != 0) 7980 queue_work(system_long_wq, &pvclock_gtod_work); 7981 7982 return 0; 7983 } 7984 7985 static struct notifier_block pvclock_gtod_notifier = { 7986 .notifier_call = pvclock_gtod_notify, 7987 }; 7988 #endif 7989 7990 int kvm_arch_init(void *opaque) 7991 { 7992 struct kvm_x86_init_ops *ops = opaque; 7993 int r; 7994 7995 if (kvm_x86_ops.hardware_enable) { 7996 printk(KERN_ERR "kvm: already loaded the other module\n"); 7997 r = -EEXIST; 7998 goto out; 7999 } 8000 8001 if (!ops->cpu_has_kvm_support()) { 8002 pr_err_ratelimited("kvm: no hardware support\n"); 8003 r = -EOPNOTSUPP; 8004 goto out; 8005 } 8006 if (ops->disabled_by_bios()) { 8007 pr_err_ratelimited("kvm: disabled by bios\n"); 8008 r = -EOPNOTSUPP; 8009 goto out; 8010 } 8011 8012 /* 8013 * KVM explicitly assumes that the guest has an FPU and 8014 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 8015 * vCPU's FPU state as a fxregs_state struct. 8016 */ 8017 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 8018 printk(KERN_ERR "kvm: inadequate fpu\n"); 8019 r = -EOPNOTSUPP; 8020 goto out; 8021 } 8022 8023 r = -ENOMEM; 8024 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), 8025 __alignof__(struct fpu), SLAB_ACCOUNT, 8026 NULL); 8027 if (!x86_fpu_cache) { 8028 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); 8029 goto out; 8030 } 8031 8032 x86_emulator_cache = kvm_alloc_emulator_cache(); 8033 if (!x86_emulator_cache) { 8034 pr_err("kvm: failed to allocate cache for x86 emulator\n"); 8035 goto out_free_x86_fpu_cache; 8036 } 8037 8038 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); 8039 if (!user_return_msrs) { 8040 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); 8041 goto out_free_x86_emulator_cache; 8042 } 8043 8044 r = kvm_mmu_module_init(); 8045 if (r) 8046 goto out_free_percpu; 8047 8048 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 8049 PT_DIRTY_MASK, PT64_NX_MASK, 0, 8050 PT_PRESENT_MASK, 0, sme_me_mask); 8051 kvm_timer_init(); 8052 8053 perf_register_guest_info_callbacks(&kvm_guest_cbs); 8054 8055 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 8056 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 8057 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; 8058 } 8059 8060 if (pi_inject_timer == -1) 8061 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); 8062 #ifdef CONFIG_X86_64 8063 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 8064 8065 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8066 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 8067 #endif 8068 8069 return 0; 8070 8071 out_free_percpu: 8072 free_percpu(user_return_msrs); 8073 out_free_x86_emulator_cache: 8074 kmem_cache_destroy(x86_emulator_cache); 8075 out_free_x86_fpu_cache: 8076 kmem_cache_destroy(x86_fpu_cache); 8077 out: 8078 return r; 8079 } 8080 8081 void kvm_arch_exit(void) 8082 { 8083 #ifdef CONFIG_X86_64 8084 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8085 clear_hv_tscchange_cb(); 8086 #endif 8087 kvm_lapic_exit(); 8088 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 8089 8090 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 8091 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 8092 CPUFREQ_TRANSITION_NOTIFIER); 8093 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 8094 #ifdef CONFIG_X86_64 8095 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 8096 #endif 8097 kvm_x86_ops.hardware_enable = NULL; 8098 kvm_mmu_module_exit(); 8099 free_percpu(user_return_msrs); 8100 kmem_cache_destroy(x86_fpu_cache); 8101 #ifdef CONFIG_KVM_XEN 8102 static_key_deferred_flush(&kvm_xen_enabled); 8103 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); 8104 #endif 8105 } 8106 8107 static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason) 8108 { 8109 ++vcpu->stat.halt_exits; 8110 if (lapic_in_kernel(vcpu)) { 8111 vcpu->arch.mp_state = state; 8112 return 1; 8113 } else { 8114 vcpu->run->exit_reason = reason; 8115 return 0; 8116 } 8117 } 8118 8119 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 8120 { 8121 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); 8122 } 8123 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 8124 8125 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 8126 { 8127 int ret = kvm_skip_emulated_instruction(vcpu); 8128 /* 8129 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 8130 * KVM_EXIT_DEBUG here. 8131 */ 8132 return kvm_vcpu_halt(vcpu) && ret; 8133 } 8134 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 8135 8136 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) 8137 { 8138 int ret = kvm_skip_emulated_instruction(vcpu); 8139 8140 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret; 8141 } 8142 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); 8143 8144 #ifdef CONFIG_X86_64 8145 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 8146 unsigned long clock_type) 8147 { 8148 struct kvm_clock_pairing clock_pairing; 8149 struct timespec64 ts; 8150 u64 cycle; 8151 int ret; 8152 8153 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 8154 return -KVM_EOPNOTSUPP; 8155 8156 if (!kvm_get_walltime_and_clockread(&ts, &cycle)) 8157 return -KVM_EOPNOTSUPP; 8158 8159 clock_pairing.sec = ts.tv_sec; 8160 clock_pairing.nsec = ts.tv_nsec; 8161 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 8162 clock_pairing.flags = 0; 8163 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 8164 8165 ret = 0; 8166 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 8167 sizeof(struct kvm_clock_pairing))) 8168 ret = -KVM_EFAULT; 8169 8170 return ret; 8171 } 8172 #endif 8173 8174 /* 8175 * kvm_pv_kick_cpu_op: Kick a vcpu. 8176 * 8177 * @apicid - apicid of vcpu to be kicked. 8178 */ 8179 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 8180 { 8181 struct kvm_lapic_irq lapic_irq; 8182 8183 lapic_irq.shorthand = APIC_DEST_NOSHORT; 8184 lapic_irq.dest_mode = APIC_DEST_PHYSICAL; 8185 lapic_irq.level = 0; 8186 lapic_irq.dest_id = apicid; 8187 lapic_irq.msi_redir_hint = false; 8188 8189 lapic_irq.delivery_mode = APIC_DM_REMRD; 8190 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 8191 } 8192 8193 bool kvm_apicv_activated(struct kvm *kvm) 8194 { 8195 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); 8196 } 8197 EXPORT_SYMBOL_GPL(kvm_apicv_activated); 8198 8199 void kvm_apicv_init(struct kvm *kvm, bool enable) 8200 { 8201 if (enable) 8202 clear_bit(APICV_INHIBIT_REASON_DISABLE, 8203 &kvm->arch.apicv_inhibit_reasons); 8204 else 8205 set_bit(APICV_INHIBIT_REASON_DISABLE, 8206 &kvm->arch.apicv_inhibit_reasons); 8207 } 8208 EXPORT_SYMBOL_GPL(kvm_apicv_init); 8209 8210 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id) 8211 { 8212 struct kvm_vcpu *target = NULL; 8213 struct kvm_apic_map *map; 8214 8215 rcu_read_lock(); 8216 map = rcu_dereference(kvm->arch.apic_map); 8217 8218 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 8219 target = map->phys_map[dest_id]->vcpu; 8220 8221 rcu_read_unlock(); 8222 8223 if (target && READ_ONCE(target->ready)) 8224 kvm_vcpu_yield_to(target); 8225 } 8226 8227 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 8228 { 8229 unsigned long nr, a0, a1, a2, a3, ret; 8230 int op_64_bit; 8231 8232 if (kvm_xen_hypercall_enabled(vcpu->kvm)) 8233 return kvm_xen_hypercall(vcpu); 8234 8235 if (kvm_hv_hypercall_enabled(vcpu)) 8236 return kvm_hv_hypercall(vcpu); 8237 8238 nr = kvm_rax_read(vcpu); 8239 a0 = kvm_rbx_read(vcpu); 8240 a1 = kvm_rcx_read(vcpu); 8241 a2 = kvm_rdx_read(vcpu); 8242 a3 = kvm_rsi_read(vcpu); 8243 8244 trace_kvm_hypercall(nr, a0, a1, a2, a3); 8245 8246 op_64_bit = is_64_bit_mode(vcpu); 8247 if (!op_64_bit) { 8248 nr &= 0xFFFFFFFF; 8249 a0 &= 0xFFFFFFFF; 8250 a1 &= 0xFFFFFFFF; 8251 a2 &= 0xFFFFFFFF; 8252 a3 &= 0xFFFFFFFF; 8253 } 8254 8255 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { 8256 ret = -KVM_EPERM; 8257 goto out; 8258 } 8259 8260 ret = -KVM_ENOSYS; 8261 8262 switch (nr) { 8263 case KVM_HC_VAPIC_POLL_IRQ: 8264 ret = 0; 8265 break; 8266 case KVM_HC_KICK_CPU: 8267 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) 8268 break; 8269 8270 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 8271 kvm_sched_yield(vcpu->kvm, a1); 8272 ret = 0; 8273 break; 8274 #ifdef CONFIG_X86_64 8275 case KVM_HC_CLOCK_PAIRING: 8276 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 8277 break; 8278 #endif 8279 case KVM_HC_SEND_IPI: 8280 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) 8281 break; 8282 8283 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 8284 break; 8285 case KVM_HC_SCHED_YIELD: 8286 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) 8287 break; 8288 8289 kvm_sched_yield(vcpu->kvm, a0); 8290 ret = 0; 8291 break; 8292 default: 8293 ret = -KVM_ENOSYS; 8294 break; 8295 } 8296 out: 8297 if (!op_64_bit) 8298 ret = (u32)ret; 8299 kvm_rax_write(vcpu, ret); 8300 8301 ++vcpu->stat.hypercalls; 8302 return kvm_skip_emulated_instruction(vcpu); 8303 } 8304 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 8305 8306 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 8307 { 8308 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8309 char instruction[3]; 8310 unsigned long rip = kvm_rip_read(vcpu); 8311 8312 static_call(kvm_x86_patch_hypercall)(vcpu, instruction); 8313 8314 return emulator_write_emulated(ctxt, rip, instruction, 3, 8315 &ctxt->exception); 8316 } 8317 8318 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 8319 { 8320 return vcpu->run->request_interrupt_window && 8321 likely(!pic_in_kernel(vcpu->kvm)); 8322 } 8323 8324 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 8325 { 8326 struct kvm_run *kvm_run = vcpu->run; 8327 8328 /* 8329 * if_flag is obsolete and useless, so do not bother 8330 * setting it for SEV-ES guests. Userspace can just 8331 * use kvm_run->ready_for_interrupt_injection. 8332 */ 8333 kvm_run->if_flag = !vcpu->arch.guest_state_protected 8334 && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 8335 8336 kvm_run->cr8 = kvm_get_cr8(vcpu); 8337 kvm_run->apic_base = kvm_get_apic_base(vcpu); 8338 kvm_run->ready_for_interrupt_injection = 8339 pic_in_kernel(vcpu->kvm) || 8340 kvm_vcpu_ready_for_interrupt_injection(vcpu); 8341 8342 if (is_smm(vcpu)) 8343 kvm_run->flags |= KVM_RUN_X86_SMM; 8344 } 8345 8346 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 8347 { 8348 int max_irr, tpr; 8349 8350 if (!kvm_x86_ops.update_cr8_intercept) 8351 return; 8352 8353 if (!lapic_in_kernel(vcpu)) 8354 return; 8355 8356 if (vcpu->arch.apicv_active) 8357 return; 8358 8359 if (!vcpu->arch.apic->vapic_addr) 8360 max_irr = kvm_lapic_find_highest_irr(vcpu); 8361 else 8362 max_irr = -1; 8363 8364 if (max_irr != -1) 8365 max_irr >>= 4; 8366 8367 tpr = kvm_lapic_get_cr8(vcpu); 8368 8369 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); 8370 } 8371 8372 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) 8373 { 8374 int r; 8375 bool can_inject = true; 8376 8377 /* try to reinject previous events if any */ 8378 8379 if (vcpu->arch.exception.injected) { 8380 static_call(kvm_x86_queue_exception)(vcpu); 8381 can_inject = false; 8382 } 8383 /* 8384 * Do not inject an NMI or interrupt if there is a pending 8385 * exception. Exceptions and interrupts are recognized at 8386 * instruction boundaries, i.e. the start of an instruction. 8387 * Trap-like exceptions, e.g. #DB, have higher priority than 8388 * NMIs and interrupts, i.e. traps are recognized before an 8389 * NMI/interrupt that's pending on the same instruction. 8390 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 8391 * priority, but are only generated (pended) during instruction 8392 * execution, i.e. a pending fault-like exception means the 8393 * fault occurred on the *previous* instruction and must be 8394 * serviced prior to recognizing any new events in order to 8395 * fully complete the previous instruction. 8396 */ 8397 else if (!vcpu->arch.exception.pending) { 8398 if (vcpu->arch.nmi_injected) { 8399 static_call(kvm_x86_set_nmi)(vcpu); 8400 can_inject = false; 8401 } else if (vcpu->arch.interrupt.injected) { 8402 static_call(kvm_x86_set_irq)(vcpu); 8403 can_inject = false; 8404 } 8405 } 8406 8407 WARN_ON_ONCE(vcpu->arch.exception.injected && 8408 vcpu->arch.exception.pending); 8409 8410 /* 8411 * Call check_nested_events() even if we reinjected a previous event 8412 * in order for caller to determine if it should require immediate-exit 8413 * from L2 to L1 due to pending L1 events which require exit 8414 * from L2 to L1. 8415 */ 8416 if (is_guest_mode(vcpu)) { 8417 r = kvm_x86_ops.nested_ops->check_events(vcpu); 8418 if (r < 0) 8419 goto busy; 8420 } 8421 8422 /* try to inject new event if pending */ 8423 if (vcpu->arch.exception.pending) { 8424 trace_kvm_inj_exception(vcpu->arch.exception.nr, 8425 vcpu->arch.exception.has_error_code, 8426 vcpu->arch.exception.error_code); 8427 8428 vcpu->arch.exception.pending = false; 8429 vcpu->arch.exception.injected = true; 8430 8431 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 8432 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 8433 X86_EFLAGS_RF); 8434 8435 if (vcpu->arch.exception.nr == DB_VECTOR) { 8436 kvm_deliver_exception_payload(vcpu); 8437 if (vcpu->arch.dr7 & DR7_GD) { 8438 vcpu->arch.dr7 &= ~DR7_GD; 8439 kvm_update_dr7(vcpu); 8440 } 8441 } 8442 8443 static_call(kvm_x86_queue_exception)(vcpu); 8444 can_inject = false; 8445 } 8446 8447 /* 8448 * Finally, inject interrupt events. If an event cannot be injected 8449 * due to architectural conditions (e.g. IF=0) a window-open exit 8450 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending 8451 * and can architecturally be injected, but we cannot do it right now: 8452 * an interrupt could have arrived just now and we have to inject it 8453 * as a vmexit, or there could already an event in the queue, which is 8454 * indicated by can_inject. In that case we request an immediate exit 8455 * in order to make progress and get back here for another iteration. 8456 * The kvm_x86_ops hooks communicate this by returning -EBUSY. 8457 */ 8458 if (vcpu->arch.smi_pending) { 8459 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; 8460 if (r < 0) 8461 goto busy; 8462 if (r) { 8463 vcpu->arch.smi_pending = false; 8464 ++vcpu->arch.smi_count; 8465 enter_smm(vcpu); 8466 can_inject = false; 8467 } else 8468 static_call(kvm_x86_enable_smi_window)(vcpu); 8469 } 8470 8471 if (vcpu->arch.nmi_pending) { 8472 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; 8473 if (r < 0) 8474 goto busy; 8475 if (r) { 8476 --vcpu->arch.nmi_pending; 8477 vcpu->arch.nmi_injected = true; 8478 static_call(kvm_x86_set_nmi)(vcpu); 8479 can_inject = false; 8480 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); 8481 } 8482 if (vcpu->arch.nmi_pending) 8483 static_call(kvm_x86_enable_nmi_window)(vcpu); 8484 } 8485 8486 if (kvm_cpu_has_injectable_intr(vcpu)) { 8487 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; 8488 if (r < 0) 8489 goto busy; 8490 if (r) { 8491 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); 8492 static_call(kvm_x86_set_irq)(vcpu); 8493 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); 8494 } 8495 if (kvm_cpu_has_injectable_intr(vcpu)) 8496 static_call(kvm_x86_enable_irq_window)(vcpu); 8497 } 8498 8499 if (is_guest_mode(vcpu) && 8500 kvm_x86_ops.nested_ops->hv_timer_pending && 8501 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 8502 *req_immediate_exit = true; 8503 8504 WARN_ON(vcpu->arch.exception.pending); 8505 return; 8506 8507 busy: 8508 *req_immediate_exit = true; 8509 return; 8510 } 8511 8512 static void process_nmi(struct kvm_vcpu *vcpu) 8513 { 8514 unsigned limit = 2; 8515 8516 /* 8517 * x86 is limited to one NMI running, and one NMI pending after it. 8518 * If an NMI is already in progress, limit further NMIs to just one. 8519 * Otherwise, allow two (and we'll inject the first one immediately). 8520 */ 8521 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) 8522 limit = 1; 8523 8524 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 8525 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 8526 kvm_make_request(KVM_REQ_EVENT, vcpu); 8527 } 8528 8529 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 8530 { 8531 u32 flags = 0; 8532 flags |= seg->g << 23; 8533 flags |= seg->db << 22; 8534 flags |= seg->l << 21; 8535 flags |= seg->avl << 20; 8536 flags |= seg->present << 15; 8537 flags |= seg->dpl << 13; 8538 flags |= seg->s << 12; 8539 flags |= seg->type << 8; 8540 return flags; 8541 } 8542 8543 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 8544 { 8545 struct kvm_segment seg; 8546 int offset; 8547 8548 kvm_get_segment(vcpu, &seg, n); 8549 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 8550 8551 if (n < 3) 8552 offset = 0x7f84 + n * 12; 8553 else 8554 offset = 0x7f2c + (n - 3) * 12; 8555 8556 put_smstate(u32, buf, offset + 8, seg.base); 8557 put_smstate(u32, buf, offset + 4, seg.limit); 8558 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 8559 } 8560 8561 #ifdef CONFIG_X86_64 8562 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 8563 { 8564 struct kvm_segment seg; 8565 int offset; 8566 u16 flags; 8567 8568 kvm_get_segment(vcpu, &seg, n); 8569 offset = 0x7e00 + n * 16; 8570 8571 flags = enter_smm_get_segment_flags(&seg) >> 8; 8572 put_smstate(u16, buf, offset, seg.selector); 8573 put_smstate(u16, buf, offset + 2, flags); 8574 put_smstate(u32, buf, offset + 4, seg.limit); 8575 put_smstate(u64, buf, offset + 8, seg.base); 8576 } 8577 #endif 8578 8579 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 8580 { 8581 struct desc_ptr dt; 8582 struct kvm_segment seg; 8583 unsigned long val; 8584 int i; 8585 8586 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 8587 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 8588 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 8589 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 8590 8591 for (i = 0; i < 8; i++) 8592 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 8593 8594 kvm_get_dr(vcpu, 6, &val); 8595 put_smstate(u32, buf, 0x7fcc, (u32)val); 8596 kvm_get_dr(vcpu, 7, &val); 8597 put_smstate(u32, buf, 0x7fc8, (u32)val); 8598 8599 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 8600 put_smstate(u32, buf, 0x7fc4, seg.selector); 8601 put_smstate(u32, buf, 0x7f64, seg.base); 8602 put_smstate(u32, buf, 0x7f60, seg.limit); 8603 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 8604 8605 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 8606 put_smstate(u32, buf, 0x7fc0, seg.selector); 8607 put_smstate(u32, buf, 0x7f80, seg.base); 8608 put_smstate(u32, buf, 0x7f7c, seg.limit); 8609 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 8610 8611 static_call(kvm_x86_get_gdt)(vcpu, &dt); 8612 put_smstate(u32, buf, 0x7f74, dt.address); 8613 put_smstate(u32, buf, 0x7f70, dt.size); 8614 8615 static_call(kvm_x86_get_idt)(vcpu, &dt); 8616 put_smstate(u32, buf, 0x7f58, dt.address); 8617 put_smstate(u32, buf, 0x7f54, dt.size); 8618 8619 for (i = 0; i < 6; i++) 8620 enter_smm_save_seg_32(vcpu, buf, i); 8621 8622 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 8623 8624 /* revision id */ 8625 put_smstate(u32, buf, 0x7efc, 0x00020000); 8626 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 8627 } 8628 8629 #ifdef CONFIG_X86_64 8630 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 8631 { 8632 struct desc_ptr dt; 8633 struct kvm_segment seg; 8634 unsigned long val; 8635 int i; 8636 8637 for (i = 0; i < 16; i++) 8638 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 8639 8640 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 8641 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 8642 8643 kvm_get_dr(vcpu, 6, &val); 8644 put_smstate(u64, buf, 0x7f68, val); 8645 kvm_get_dr(vcpu, 7, &val); 8646 put_smstate(u64, buf, 0x7f60, val); 8647 8648 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 8649 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 8650 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 8651 8652 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 8653 8654 /* revision id */ 8655 put_smstate(u32, buf, 0x7efc, 0x00020064); 8656 8657 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 8658 8659 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 8660 put_smstate(u16, buf, 0x7e90, seg.selector); 8661 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 8662 put_smstate(u32, buf, 0x7e94, seg.limit); 8663 put_smstate(u64, buf, 0x7e98, seg.base); 8664 8665 static_call(kvm_x86_get_idt)(vcpu, &dt); 8666 put_smstate(u32, buf, 0x7e84, dt.size); 8667 put_smstate(u64, buf, 0x7e88, dt.address); 8668 8669 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 8670 put_smstate(u16, buf, 0x7e70, seg.selector); 8671 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 8672 put_smstate(u32, buf, 0x7e74, seg.limit); 8673 put_smstate(u64, buf, 0x7e78, seg.base); 8674 8675 static_call(kvm_x86_get_gdt)(vcpu, &dt); 8676 put_smstate(u32, buf, 0x7e64, dt.size); 8677 put_smstate(u64, buf, 0x7e68, dt.address); 8678 8679 for (i = 0; i < 6; i++) 8680 enter_smm_save_seg_64(vcpu, buf, i); 8681 } 8682 #endif 8683 8684 static void enter_smm(struct kvm_vcpu *vcpu) 8685 { 8686 struct kvm_segment cs, ds; 8687 struct desc_ptr dt; 8688 char buf[512]; 8689 u32 cr0; 8690 8691 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 8692 memset(buf, 0, 512); 8693 #ifdef CONFIG_X86_64 8694 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 8695 enter_smm_save_state_64(vcpu, buf); 8696 else 8697 #endif 8698 enter_smm_save_state_32(vcpu, buf); 8699 8700 /* 8701 * Give pre_enter_smm() a chance to make ISA-specific changes to the 8702 * vCPU state (e.g. leave guest mode) after we've saved the state into 8703 * the SMM state-save area. 8704 */ 8705 static_call(kvm_x86_pre_enter_smm)(vcpu, buf); 8706 8707 vcpu->arch.hflags |= HF_SMM_MASK; 8708 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 8709 8710 if (static_call(kvm_x86_get_nmi_mask)(vcpu)) 8711 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 8712 else 8713 static_call(kvm_x86_set_nmi_mask)(vcpu, true); 8714 8715 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 8716 kvm_rip_write(vcpu, 0x8000); 8717 8718 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 8719 static_call(kvm_x86_set_cr0)(vcpu, cr0); 8720 vcpu->arch.cr0 = cr0; 8721 8722 static_call(kvm_x86_set_cr4)(vcpu, 0); 8723 8724 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 8725 dt.address = dt.size = 0; 8726 static_call(kvm_x86_set_idt)(vcpu, &dt); 8727 8728 kvm_set_dr(vcpu, 7, DR7_FIXED_1); 8729 8730 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 8731 cs.base = vcpu->arch.smbase; 8732 8733 ds.selector = 0; 8734 ds.base = 0; 8735 8736 cs.limit = ds.limit = 0xffffffff; 8737 cs.type = ds.type = 0x3; 8738 cs.dpl = ds.dpl = 0; 8739 cs.db = ds.db = 0; 8740 cs.s = ds.s = 1; 8741 cs.l = ds.l = 0; 8742 cs.g = ds.g = 1; 8743 cs.avl = ds.avl = 0; 8744 cs.present = ds.present = 1; 8745 cs.unusable = ds.unusable = 0; 8746 cs.padding = ds.padding = 0; 8747 8748 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 8749 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 8750 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 8751 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 8752 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 8753 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 8754 8755 #ifdef CONFIG_X86_64 8756 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 8757 static_call(kvm_x86_set_efer)(vcpu, 0); 8758 #endif 8759 8760 kvm_update_cpuid_runtime(vcpu); 8761 kvm_mmu_reset_context(vcpu); 8762 } 8763 8764 static void process_smi(struct kvm_vcpu *vcpu) 8765 { 8766 vcpu->arch.smi_pending = true; 8767 kvm_make_request(KVM_REQ_EVENT, vcpu); 8768 } 8769 8770 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 8771 unsigned long *vcpu_bitmap) 8772 { 8773 cpumask_var_t cpus; 8774 8775 zalloc_cpumask_var(&cpus, GFP_ATOMIC); 8776 8777 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, 8778 NULL, vcpu_bitmap, cpus); 8779 8780 free_cpumask_var(cpus); 8781 } 8782 8783 void kvm_make_scan_ioapic_request(struct kvm *kvm) 8784 { 8785 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 8786 } 8787 8788 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 8789 { 8790 if (!lapic_in_kernel(vcpu)) 8791 return; 8792 8793 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm); 8794 kvm_apic_update_apicv(vcpu); 8795 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); 8796 } 8797 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); 8798 8799 /* 8800 * NOTE: Do not hold any lock prior to calling this. 8801 * 8802 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be 8803 * locked, because it calls __x86_set_memory_region() which does 8804 * synchronize_srcu(&kvm->srcu). 8805 */ 8806 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) 8807 { 8808 struct kvm_vcpu *except; 8809 unsigned long old, new, expected; 8810 8811 if (!kvm_x86_ops.check_apicv_inhibit_reasons || 8812 !static_call(kvm_x86_check_apicv_inhibit_reasons)(bit)) 8813 return; 8814 8815 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons); 8816 do { 8817 expected = new = old; 8818 if (activate) 8819 __clear_bit(bit, &new); 8820 else 8821 __set_bit(bit, &new); 8822 if (new == old) 8823 break; 8824 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new); 8825 } while (old != expected); 8826 8827 if (!!old == !!new) 8828 return; 8829 8830 trace_kvm_apicv_update_request(activate, bit); 8831 if (kvm_x86_ops.pre_update_apicv_exec_ctrl) 8832 static_call(kvm_x86_pre_update_apicv_exec_ctrl)(kvm, activate); 8833 8834 /* 8835 * Sending request to update APICV for all other vcpus, 8836 * while update the calling vcpu immediately instead of 8837 * waiting for another #VMEXIT to handle the request. 8838 */ 8839 except = kvm_get_running_vcpu(); 8840 kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE, 8841 except); 8842 if (except) 8843 kvm_vcpu_update_apicv(except); 8844 } 8845 EXPORT_SYMBOL_GPL(kvm_request_apicv_update); 8846 8847 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 8848 { 8849 if (!kvm_apic_present(vcpu)) 8850 return; 8851 8852 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 8853 8854 if (irqchip_split(vcpu->kvm)) 8855 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 8856 else { 8857 if (vcpu->arch.apicv_active) 8858 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 8859 if (ioapic_in_kernel(vcpu->kvm)) 8860 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 8861 } 8862 8863 if (is_guest_mode(vcpu)) 8864 vcpu->arch.load_eoi_exitmap_pending = true; 8865 else 8866 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 8867 } 8868 8869 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 8870 { 8871 u64 eoi_exit_bitmap[4]; 8872 8873 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 8874 return; 8875 8876 if (to_hv_vcpu(vcpu)) 8877 bitmap_or((ulong *)eoi_exit_bitmap, 8878 vcpu->arch.ioapic_handled_vectors, 8879 to_hv_synic(vcpu)->vec_bitmap, 256); 8880 8881 static_call(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); 8882 } 8883 8884 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 8885 unsigned long start, unsigned long end) 8886 { 8887 unsigned long apic_address; 8888 8889 /* 8890 * The physical address of apic access page is stored in the VMCS. 8891 * Update it when it becomes invalid. 8892 */ 8893 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 8894 if (start <= apic_address && apic_address < end) 8895 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 8896 } 8897 8898 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 8899 { 8900 if (!lapic_in_kernel(vcpu)) 8901 return; 8902 8903 if (!kvm_x86_ops.set_apic_access_page_addr) 8904 return; 8905 8906 static_call(kvm_x86_set_apic_access_page_addr)(vcpu); 8907 } 8908 8909 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 8910 { 8911 smp_send_reschedule(vcpu->cpu); 8912 } 8913 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 8914 8915 /* 8916 * Returns 1 to let vcpu_run() continue the guest execution loop without 8917 * exiting to the userspace. Otherwise, the value will be returned to the 8918 * userspace. 8919 */ 8920 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 8921 { 8922 int r; 8923 bool req_int_win = 8924 dm_request_for_irq_injection(vcpu) && 8925 kvm_cpu_accept_dm_intr(vcpu); 8926 fastpath_t exit_fastpath; 8927 8928 bool req_immediate_exit = false; 8929 8930 /* Forbid vmenter if vcpu dirty ring is soft-full */ 8931 if (unlikely(vcpu->kvm->dirty_ring_size && 8932 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { 8933 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; 8934 trace_kvm_dirty_ring_exit(vcpu); 8935 r = 0; 8936 goto out; 8937 } 8938 8939 if (kvm_request_pending(vcpu)) { 8940 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { 8941 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { 8942 r = 0; 8943 goto out; 8944 } 8945 } 8946 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 8947 kvm_mmu_unload(vcpu); 8948 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 8949 __kvm_migrate_timers(vcpu); 8950 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 8951 kvm_gen_update_masterclock(vcpu->kvm); 8952 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 8953 kvm_gen_kvmclock_update(vcpu); 8954 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 8955 r = kvm_guest_time_update(vcpu); 8956 if (unlikely(r)) 8957 goto out; 8958 } 8959 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 8960 kvm_mmu_sync_roots(vcpu); 8961 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) 8962 kvm_mmu_load_pgd(vcpu); 8963 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { 8964 kvm_vcpu_flush_tlb_all(vcpu); 8965 8966 /* Flushing all ASIDs flushes the current ASID... */ 8967 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 8968 } 8969 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) 8970 kvm_vcpu_flush_tlb_current(vcpu); 8971 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu)) 8972 kvm_vcpu_flush_tlb_guest(vcpu); 8973 8974 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 8975 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 8976 r = 0; 8977 goto out; 8978 } 8979 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 8980 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 8981 vcpu->mmio_needed = 0; 8982 r = 0; 8983 goto out; 8984 } 8985 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 8986 /* Page is swapped out. Do synthetic halt */ 8987 vcpu->arch.apf.halted = true; 8988 r = 1; 8989 goto out; 8990 } 8991 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 8992 record_steal_time(vcpu); 8993 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 8994 process_smi(vcpu); 8995 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 8996 process_nmi(vcpu); 8997 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 8998 kvm_pmu_handle_event(vcpu); 8999 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 9000 kvm_pmu_deliver_pmi(vcpu); 9001 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 9002 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 9003 if (test_bit(vcpu->arch.pending_ioapic_eoi, 9004 vcpu->arch.ioapic_handled_vectors)) { 9005 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 9006 vcpu->run->eoi.vector = 9007 vcpu->arch.pending_ioapic_eoi; 9008 r = 0; 9009 goto out; 9010 } 9011 } 9012 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 9013 vcpu_scan_ioapic(vcpu); 9014 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 9015 vcpu_load_eoi_exitmap(vcpu); 9016 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 9017 kvm_vcpu_reload_apic_access_page(vcpu); 9018 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 9019 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 9020 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 9021 r = 0; 9022 goto out; 9023 } 9024 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 9025 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 9026 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 9027 r = 0; 9028 goto out; 9029 } 9030 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 9031 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); 9032 9033 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 9034 vcpu->run->hyperv = hv_vcpu->exit; 9035 r = 0; 9036 goto out; 9037 } 9038 9039 /* 9040 * KVM_REQ_HV_STIMER has to be processed after 9041 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 9042 * depend on the guest clock being up-to-date 9043 */ 9044 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 9045 kvm_hv_process_stimers(vcpu); 9046 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 9047 kvm_vcpu_update_apicv(vcpu); 9048 if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) 9049 kvm_check_async_pf_completion(vcpu); 9050 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) 9051 static_call(kvm_x86_msr_filter_changed)(vcpu); 9052 9053 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) 9054 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); 9055 } 9056 9057 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || 9058 kvm_xen_has_interrupt(vcpu)) { 9059 ++vcpu->stat.req_event; 9060 kvm_apic_accept_events(vcpu); 9061 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 9062 r = 1; 9063 goto out; 9064 } 9065 9066 inject_pending_event(vcpu, &req_immediate_exit); 9067 if (req_int_win) 9068 static_call(kvm_x86_enable_irq_window)(vcpu); 9069 9070 if (kvm_lapic_enabled(vcpu)) { 9071 update_cr8_intercept(vcpu); 9072 kvm_lapic_sync_to_vapic(vcpu); 9073 } 9074 } 9075 9076 r = kvm_mmu_reload(vcpu); 9077 if (unlikely(r)) { 9078 goto cancel_injection; 9079 } 9080 9081 preempt_disable(); 9082 9083 static_call(kvm_x86_prepare_guest_switch)(vcpu); 9084 9085 /* 9086 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 9087 * IPI are then delayed after guest entry, which ensures that they 9088 * result in virtual interrupt delivery. 9089 */ 9090 local_irq_disable(); 9091 vcpu->mode = IN_GUEST_MODE; 9092 9093 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 9094 9095 /* 9096 * 1) We should set ->mode before checking ->requests. Please see 9097 * the comment in kvm_vcpu_exiting_guest_mode(). 9098 * 9099 * 2) For APICv, we should set ->mode before checking PID.ON. This 9100 * pairs with the memory barrier implicit in pi_test_and_set_on 9101 * (see vmx_deliver_posted_interrupt). 9102 * 9103 * 3) This also orders the write to mode from any reads to the page 9104 * tables done while the VCPU is running. Please see the comment 9105 * in kvm_flush_remote_tlbs. 9106 */ 9107 smp_mb__after_srcu_read_unlock(); 9108 9109 /* 9110 * This handles the case where a posted interrupt was 9111 * notified with kvm_vcpu_kick. 9112 */ 9113 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) 9114 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 9115 9116 if (kvm_vcpu_exit_request(vcpu)) { 9117 vcpu->mode = OUTSIDE_GUEST_MODE; 9118 smp_wmb(); 9119 local_irq_enable(); 9120 preempt_enable(); 9121 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9122 r = 1; 9123 goto cancel_injection; 9124 } 9125 9126 if (req_immediate_exit) { 9127 kvm_make_request(KVM_REQ_EVENT, vcpu); 9128 static_call(kvm_x86_request_immediate_exit)(vcpu); 9129 } 9130 9131 fpregs_assert_state_consistent(); 9132 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 9133 switch_fpu_return(); 9134 9135 if (unlikely(vcpu->arch.switch_db_regs)) { 9136 set_debugreg(0, 7); 9137 set_debugreg(vcpu->arch.eff_db[0], 0); 9138 set_debugreg(vcpu->arch.eff_db[1], 1); 9139 set_debugreg(vcpu->arch.eff_db[2], 2); 9140 set_debugreg(vcpu->arch.eff_db[3], 3); 9141 set_debugreg(vcpu->arch.dr6, 6); 9142 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 9143 } 9144 9145 for (;;) { 9146 exit_fastpath = static_call(kvm_x86_run)(vcpu); 9147 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) 9148 break; 9149 9150 if (unlikely(kvm_vcpu_exit_request(vcpu))) { 9151 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; 9152 break; 9153 } 9154 9155 if (vcpu->arch.apicv_active) 9156 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 9157 } 9158 9159 /* 9160 * Do this here before restoring debug registers on the host. And 9161 * since we do this before handling the vmexit, a DR access vmexit 9162 * can (a) read the correct value of the debug registers, (b) set 9163 * KVM_DEBUGREG_WONT_EXIT again. 9164 */ 9165 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 9166 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 9167 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); 9168 kvm_update_dr0123(vcpu); 9169 kvm_update_dr7(vcpu); 9170 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 9171 } 9172 9173 /* 9174 * If the guest has used debug registers, at least dr7 9175 * will be disabled while returning to the host. 9176 * If we don't have active breakpoints in the host, we don't 9177 * care about the messed up debug address registers. But if 9178 * we have some of them active, restore the old state. 9179 */ 9180 if (hw_breakpoint_active()) 9181 hw_breakpoint_restore(); 9182 9183 vcpu->arch.last_vmentry_cpu = vcpu->cpu; 9184 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 9185 9186 vcpu->mode = OUTSIDE_GUEST_MODE; 9187 smp_wmb(); 9188 9189 static_call(kvm_x86_handle_exit_irqoff)(vcpu); 9190 9191 /* 9192 * Consume any pending interrupts, including the possible source of 9193 * VM-Exit on SVM and any ticks that occur between VM-Exit and now. 9194 * An instruction is required after local_irq_enable() to fully unblock 9195 * interrupts on processors that implement an interrupt shadow, the 9196 * stat.exits increment will do nicely. 9197 */ 9198 kvm_before_interrupt(vcpu); 9199 local_irq_enable(); 9200 ++vcpu->stat.exits; 9201 local_irq_disable(); 9202 kvm_after_interrupt(vcpu); 9203 9204 if (lapic_in_kernel(vcpu)) { 9205 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; 9206 if (delta != S64_MIN) { 9207 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); 9208 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; 9209 } 9210 } 9211 9212 local_irq_enable(); 9213 preempt_enable(); 9214 9215 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9216 9217 /* 9218 * Profile KVM exit RIPs: 9219 */ 9220 if (unlikely(prof_on == KVM_PROFILING)) { 9221 unsigned long rip = kvm_rip_read(vcpu); 9222 profile_hit(KVM_PROFILING, (void *)rip); 9223 } 9224 9225 if (unlikely(vcpu->arch.tsc_always_catchup)) 9226 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 9227 9228 if (vcpu->arch.apic_attention) 9229 kvm_lapic_sync_from_vapic(vcpu); 9230 9231 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); 9232 return r; 9233 9234 cancel_injection: 9235 if (req_immediate_exit) 9236 kvm_make_request(KVM_REQ_EVENT, vcpu); 9237 static_call(kvm_x86_cancel_injection)(vcpu); 9238 if (unlikely(vcpu->arch.apic_attention)) 9239 kvm_lapic_sync_from_vapic(vcpu); 9240 out: 9241 return r; 9242 } 9243 9244 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 9245 { 9246 if (!kvm_arch_vcpu_runnable(vcpu) && 9247 (!kvm_x86_ops.pre_block || static_call(kvm_x86_pre_block)(vcpu) == 0)) { 9248 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9249 kvm_vcpu_block(vcpu); 9250 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9251 9252 if (kvm_x86_ops.post_block) 9253 static_call(kvm_x86_post_block)(vcpu); 9254 9255 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 9256 return 1; 9257 } 9258 9259 kvm_apic_accept_events(vcpu); 9260 switch(vcpu->arch.mp_state) { 9261 case KVM_MP_STATE_HALTED: 9262 case KVM_MP_STATE_AP_RESET_HOLD: 9263 vcpu->arch.pv.pv_unhalted = false; 9264 vcpu->arch.mp_state = 9265 KVM_MP_STATE_RUNNABLE; 9266 fallthrough; 9267 case KVM_MP_STATE_RUNNABLE: 9268 vcpu->arch.apf.halted = false; 9269 break; 9270 case KVM_MP_STATE_INIT_RECEIVED: 9271 break; 9272 default: 9273 return -EINTR; 9274 } 9275 return 1; 9276 } 9277 9278 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 9279 { 9280 if (is_guest_mode(vcpu)) 9281 kvm_x86_ops.nested_ops->check_events(vcpu); 9282 9283 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 9284 !vcpu->arch.apf.halted); 9285 } 9286 9287 static int vcpu_run(struct kvm_vcpu *vcpu) 9288 { 9289 int r; 9290 struct kvm *kvm = vcpu->kvm; 9291 9292 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9293 vcpu->arch.l1tf_flush_l1d = true; 9294 9295 for (;;) { 9296 if (kvm_vcpu_running(vcpu)) { 9297 r = vcpu_enter_guest(vcpu); 9298 } else { 9299 r = vcpu_block(kvm, vcpu); 9300 } 9301 9302 if (r <= 0) 9303 break; 9304 9305 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); 9306 if (kvm_cpu_has_pending_timer(vcpu)) 9307 kvm_inject_pending_timer_irqs(vcpu); 9308 9309 if (dm_request_for_irq_injection(vcpu) && 9310 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 9311 r = 0; 9312 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 9313 ++vcpu->stat.request_irq_exits; 9314 break; 9315 } 9316 9317 if (__xfer_to_guest_mode_work_pending()) { 9318 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9319 r = xfer_to_guest_mode_handle_work(vcpu); 9320 if (r) 9321 return r; 9322 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9323 } 9324 } 9325 9326 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9327 9328 return r; 9329 } 9330 9331 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 9332 { 9333 int r; 9334 9335 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9336 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 9337 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 9338 return r; 9339 } 9340 9341 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 9342 { 9343 BUG_ON(!vcpu->arch.pio.count); 9344 9345 return complete_emulated_io(vcpu); 9346 } 9347 9348 /* 9349 * Implements the following, as a state machine: 9350 * 9351 * read: 9352 * for each fragment 9353 * for each mmio piece in the fragment 9354 * write gpa, len 9355 * exit 9356 * copy data 9357 * execute insn 9358 * 9359 * write: 9360 * for each fragment 9361 * for each mmio piece in the fragment 9362 * write gpa, len 9363 * copy data 9364 * exit 9365 */ 9366 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 9367 { 9368 struct kvm_run *run = vcpu->run; 9369 struct kvm_mmio_fragment *frag; 9370 unsigned len; 9371 9372 BUG_ON(!vcpu->mmio_needed); 9373 9374 /* Complete previous fragment */ 9375 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 9376 len = min(8u, frag->len); 9377 if (!vcpu->mmio_is_write) 9378 memcpy(frag->data, run->mmio.data, len); 9379 9380 if (frag->len <= 8) { 9381 /* Switch to the next fragment. */ 9382 frag++; 9383 vcpu->mmio_cur_fragment++; 9384 } else { 9385 /* Go forward to the next mmio piece. */ 9386 frag->data += len; 9387 frag->gpa += len; 9388 frag->len -= len; 9389 } 9390 9391 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 9392 vcpu->mmio_needed = 0; 9393 9394 /* FIXME: return into emulator if single-stepping. */ 9395 if (vcpu->mmio_is_write) 9396 return 1; 9397 vcpu->mmio_read_completed = 1; 9398 return complete_emulated_io(vcpu); 9399 } 9400 9401 run->exit_reason = KVM_EXIT_MMIO; 9402 run->mmio.phys_addr = frag->gpa; 9403 if (vcpu->mmio_is_write) 9404 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 9405 run->mmio.len = min(8u, frag->len); 9406 run->mmio.is_write = vcpu->mmio_is_write; 9407 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 9408 return 0; 9409 } 9410 9411 static void kvm_save_current_fpu(struct fpu *fpu) 9412 { 9413 /* 9414 * If the target FPU state is not resident in the CPU registers, just 9415 * memcpy() from current, else save CPU state directly to the target. 9416 */ 9417 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 9418 memcpy(&fpu->state, ¤t->thread.fpu.state, 9419 fpu_kernel_xstate_size); 9420 else 9421 copy_fpregs_to_fpstate(fpu); 9422 } 9423 9424 /* Swap (qemu) user FPU context for the guest FPU context. */ 9425 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 9426 { 9427 fpregs_lock(); 9428 9429 kvm_save_current_fpu(vcpu->arch.user_fpu); 9430 9431 /* 9432 * Guests with protected state can't have it set by the hypervisor, 9433 * so skip trying to set it. 9434 */ 9435 if (vcpu->arch.guest_fpu) 9436 /* PKRU is separately restored in kvm_x86_ops.run. */ 9437 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, 9438 ~XFEATURE_MASK_PKRU); 9439 9440 fpregs_mark_activate(); 9441 fpregs_unlock(); 9442 9443 trace_kvm_fpu(1); 9444 } 9445 9446 /* When vcpu_run ends, restore user space FPU context. */ 9447 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 9448 { 9449 fpregs_lock(); 9450 9451 /* 9452 * Guests with protected state can't have it read by the hypervisor, 9453 * so skip trying to save it. 9454 */ 9455 if (vcpu->arch.guest_fpu) 9456 kvm_save_current_fpu(vcpu->arch.guest_fpu); 9457 9458 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); 9459 9460 fpregs_mark_activate(); 9461 fpregs_unlock(); 9462 9463 ++vcpu->stat.fpu_reload; 9464 trace_kvm_fpu(0); 9465 } 9466 9467 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 9468 { 9469 struct kvm_run *kvm_run = vcpu->run; 9470 int r; 9471 9472 vcpu_load(vcpu); 9473 kvm_sigset_activate(vcpu); 9474 kvm_run->flags = 0; 9475 kvm_load_guest_fpu(vcpu); 9476 9477 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 9478 if (kvm_run->immediate_exit) { 9479 r = -EINTR; 9480 goto out; 9481 } 9482 kvm_vcpu_block(vcpu); 9483 kvm_apic_accept_events(vcpu); 9484 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 9485 r = -EAGAIN; 9486 if (signal_pending(current)) { 9487 r = -EINTR; 9488 kvm_run->exit_reason = KVM_EXIT_INTR; 9489 ++vcpu->stat.signal_exits; 9490 } 9491 goto out; 9492 } 9493 9494 if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { 9495 r = -EINVAL; 9496 goto out; 9497 } 9498 9499 if (kvm_run->kvm_dirty_regs) { 9500 r = sync_regs(vcpu); 9501 if (r != 0) 9502 goto out; 9503 } 9504 9505 /* re-sync apic's tpr */ 9506 if (!lapic_in_kernel(vcpu)) { 9507 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 9508 r = -EINVAL; 9509 goto out; 9510 } 9511 } 9512 9513 if (unlikely(vcpu->arch.complete_userspace_io)) { 9514 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 9515 vcpu->arch.complete_userspace_io = NULL; 9516 r = cui(vcpu); 9517 if (r <= 0) 9518 goto out; 9519 } else 9520 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 9521 9522 if (kvm_run->immediate_exit) 9523 r = -EINTR; 9524 else 9525 r = vcpu_run(vcpu); 9526 9527 out: 9528 kvm_put_guest_fpu(vcpu); 9529 if (kvm_run->kvm_valid_regs) 9530 store_regs(vcpu); 9531 post_kvm_run_save(vcpu); 9532 kvm_sigset_deactivate(vcpu); 9533 9534 vcpu_put(vcpu); 9535 return r; 9536 } 9537 9538 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9539 { 9540 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 9541 /* 9542 * We are here if userspace calls get_regs() in the middle of 9543 * instruction emulation. Registers state needs to be copied 9544 * back from emulation context to vcpu. Userspace shouldn't do 9545 * that usually, but some bad designed PV devices (vmware 9546 * backdoor interface) need this to work 9547 */ 9548 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); 9549 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 9550 } 9551 regs->rax = kvm_rax_read(vcpu); 9552 regs->rbx = kvm_rbx_read(vcpu); 9553 regs->rcx = kvm_rcx_read(vcpu); 9554 regs->rdx = kvm_rdx_read(vcpu); 9555 regs->rsi = kvm_rsi_read(vcpu); 9556 regs->rdi = kvm_rdi_read(vcpu); 9557 regs->rsp = kvm_rsp_read(vcpu); 9558 regs->rbp = kvm_rbp_read(vcpu); 9559 #ifdef CONFIG_X86_64 9560 regs->r8 = kvm_r8_read(vcpu); 9561 regs->r9 = kvm_r9_read(vcpu); 9562 regs->r10 = kvm_r10_read(vcpu); 9563 regs->r11 = kvm_r11_read(vcpu); 9564 regs->r12 = kvm_r12_read(vcpu); 9565 regs->r13 = kvm_r13_read(vcpu); 9566 regs->r14 = kvm_r14_read(vcpu); 9567 regs->r15 = kvm_r15_read(vcpu); 9568 #endif 9569 9570 regs->rip = kvm_rip_read(vcpu); 9571 regs->rflags = kvm_get_rflags(vcpu); 9572 } 9573 9574 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9575 { 9576 vcpu_load(vcpu); 9577 __get_regs(vcpu, regs); 9578 vcpu_put(vcpu); 9579 return 0; 9580 } 9581 9582 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9583 { 9584 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 9585 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 9586 9587 kvm_rax_write(vcpu, regs->rax); 9588 kvm_rbx_write(vcpu, regs->rbx); 9589 kvm_rcx_write(vcpu, regs->rcx); 9590 kvm_rdx_write(vcpu, regs->rdx); 9591 kvm_rsi_write(vcpu, regs->rsi); 9592 kvm_rdi_write(vcpu, regs->rdi); 9593 kvm_rsp_write(vcpu, regs->rsp); 9594 kvm_rbp_write(vcpu, regs->rbp); 9595 #ifdef CONFIG_X86_64 9596 kvm_r8_write(vcpu, regs->r8); 9597 kvm_r9_write(vcpu, regs->r9); 9598 kvm_r10_write(vcpu, regs->r10); 9599 kvm_r11_write(vcpu, regs->r11); 9600 kvm_r12_write(vcpu, regs->r12); 9601 kvm_r13_write(vcpu, regs->r13); 9602 kvm_r14_write(vcpu, regs->r14); 9603 kvm_r15_write(vcpu, regs->r15); 9604 #endif 9605 9606 kvm_rip_write(vcpu, regs->rip); 9607 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 9608 9609 vcpu->arch.exception.pending = false; 9610 9611 kvm_make_request(KVM_REQ_EVENT, vcpu); 9612 } 9613 9614 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9615 { 9616 vcpu_load(vcpu); 9617 __set_regs(vcpu, regs); 9618 vcpu_put(vcpu); 9619 return 0; 9620 } 9621 9622 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 9623 { 9624 struct kvm_segment cs; 9625 9626 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 9627 *db = cs.db; 9628 *l = cs.l; 9629 } 9630 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 9631 9632 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 9633 { 9634 struct desc_ptr dt; 9635 9636 if (vcpu->arch.guest_state_protected) 9637 goto skip_protected_regs; 9638 9639 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 9640 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 9641 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 9642 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 9643 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 9644 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 9645 9646 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 9647 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 9648 9649 static_call(kvm_x86_get_idt)(vcpu, &dt); 9650 sregs->idt.limit = dt.size; 9651 sregs->idt.base = dt.address; 9652 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9653 sregs->gdt.limit = dt.size; 9654 sregs->gdt.base = dt.address; 9655 9656 sregs->cr2 = vcpu->arch.cr2; 9657 sregs->cr3 = kvm_read_cr3(vcpu); 9658 9659 skip_protected_regs: 9660 sregs->cr0 = kvm_read_cr0(vcpu); 9661 sregs->cr4 = kvm_read_cr4(vcpu); 9662 sregs->cr8 = kvm_get_cr8(vcpu); 9663 sregs->efer = vcpu->arch.efer; 9664 sregs->apic_base = kvm_get_apic_base(vcpu); 9665 9666 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); 9667 9668 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 9669 set_bit(vcpu->arch.interrupt.nr, 9670 (unsigned long *)sregs->interrupt_bitmap); 9671 } 9672 9673 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 9674 struct kvm_sregs *sregs) 9675 { 9676 vcpu_load(vcpu); 9677 __get_sregs(vcpu, sregs); 9678 vcpu_put(vcpu); 9679 return 0; 9680 } 9681 9682 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 9683 struct kvm_mp_state *mp_state) 9684 { 9685 vcpu_load(vcpu); 9686 if (kvm_mpx_supported()) 9687 kvm_load_guest_fpu(vcpu); 9688 9689 kvm_apic_accept_events(vcpu); 9690 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || 9691 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && 9692 vcpu->arch.pv.pv_unhalted) 9693 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 9694 else 9695 mp_state->mp_state = vcpu->arch.mp_state; 9696 9697 if (kvm_mpx_supported()) 9698 kvm_put_guest_fpu(vcpu); 9699 vcpu_put(vcpu); 9700 return 0; 9701 } 9702 9703 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 9704 struct kvm_mp_state *mp_state) 9705 { 9706 int ret = -EINVAL; 9707 9708 vcpu_load(vcpu); 9709 9710 if (!lapic_in_kernel(vcpu) && 9711 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 9712 goto out; 9713 9714 /* 9715 * KVM_MP_STATE_INIT_RECEIVED means the processor is in 9716 * INIT state; latched init should be reported using 9717 * KVM_SET_VCPU_EVENTS, so reject it here. 9718 */ 9719 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && 9720 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 9721 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 9722 goto out; 9723 9724 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 9725 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 9726 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 9727 } else 9728 vcpu->arch.mp_state = mp_state->mp_state; 9729 kvm_make_request(KVM_REQ_EVENT, vcpu); 9730 9731 ret = 0; 9732 out: 9733 vcpu_put(vcpu); 9734 return ret; 9735 } 9736 9737 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 9738 int reason, bool has_error_code, u32 error_code) 9739 { 9740 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 9741 int ret; 9742 9743 init_emulate_ctxt(vcpu); 9744 9745 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 9746 has_error_code, error_code); 9747 if (ret) { 9748 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 9749 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 9750 vcpu->run->internal.ndata = 0; 9751 return 0; 9752 } 9753 9754 kvm_rip_write(vcpu, ctxt->eip); 9755 kvm_set_rflags(vcpu, ctxt->eflags); 9756 return 1; 9757 } 9758 EXPORT_SYMBOL_GPL(kvm_task_switch); 9759 9760 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 9761 { 9762 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 9763 /* 9764 * When EFER.LME and CR0.PG are set, the processor is in 9765 * 64-bit mode (though maybe in a 32-bit code segment). 9766 * CR4.PAE and EFER.LMA must be set. 9767 */ 9768 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) 9769 return false; 9770 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) 9771 return false; 9772 } else { 9773 /* 9774 * Not in 64-bit mode: EFER.LMA is clear and the code 9775 * segment cannot be 64-bit. 9776 */ 9777 if (sregs->efer & EFER_LMA || sregs->cs.l) 9778 return false; 9779 } 9780 9781 return kvm_is_valid_cr4(vcpu, sregs->cr4); 9782 } 9783 9784 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 9785 { 9786 struct msr_data apic_base_msr; 9787 int mmu_reset_needed = 0; 9788 int pending_vec, max_bits, idx; 9789 struct desc_ptr dt; 9790 int ret = -EINVAL; 9791 9792 if (!kvm_is_valid_sregs(vcpu, sregs)) 9793 goto out; 9794 9795 apic_base_msr.data = sregs->apic_base; 9796 apic_base_msr.host_initiated = true; 9797 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 9798 goto out; 9799 9800 if (vcpu->arch.guest_state_protected) 9801 goto skip_protected_regs; 9802 9803 dt.size = sregs->idt.limit; 9804 dt.address = sregs->idt.base; 9805 static_call(kvm_x86_set_idt)(vcpu, &dt); 9806 dt.size = sregs->gdt.limit; 9807 dt.address = sregs->gdt.base; 9808 static_call(kvm_x86_set_gdt)(vcpu, &dt); 9809 9810 vcpu->arch.cr2 = sregs->cr2; 9811 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 9812 vcpu->arch.cr3 = sregs->cr3; 9813 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 9814 9815 kvm_set_cr8(vcpu, sregs->cr8); 9816 9817 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 9818 static_call(kvm_x86_set_efer)(vcpu, sregs->efer); 9819 9820 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 9821 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); 9822 vcpu->arch.cr0 = sregs->cr0; 9823 9824 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 9825 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); 9826 9827 idx = srcu_read_lock(&vcpu->kvm->srcu); 9828 if (is_pae_paging(vcpu)) { 9829 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 9830 mmu_reset_needed = 1; 9831 } 9832 srcu_read_unlock(&vcpu->kvm->srcu, idx); 9833 9834 if (mmu_reset_needed) 9835 kvm_mmu_reset_context(vcpu); 9836 9837 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 9838 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 9839 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 9840 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 9841 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 9842 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 9843 9844 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 9845 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 9846 9847 update_cr8_intercept(vcpu); 9848 9849 /* Older userspace won't unhalt the vcpu on reset. */ 9850 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 9851 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 9852 !is_protmode(vcpu)) 9853 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 9854 9855 skip_protected_regs: 9856 max_bits = KVM_NR_INTERRUPTS; 9857 pending_vec = find_first_bit( 9858 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 9859 if (pending_vec < max_bits) { 9860 kvm_queue_interrupt(vcpu, pending_vec, false); 9861 pr_debug("Set back pending irq %d\n", pending_vec); 9862 } 9863 9864 kvm_make_request(KVM_REQ_EVENT, vcpu); 9865 9866 ret = 0; 9867 out: 9868 return ret; 9869 } 9870 9871 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 9872 struct kvm_sregs *sregs) 9873 { 9874 int ret; 9875 9876 vcpu_load(vcpu); 9877 ret = __set_sregs(vcpu, sregs); 9878 vcpu_put(vcpu); 9879 return ret; 9880 } 9881 9882 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 9883 struct kvm_guest_debug *dbg) 9884 { 9885 unsigned long rflags; 9886 int i, r; 9887 9888 if (vcpu->arch.guest_state_protected) 9889 return -EINVAL; 9890 9891 vcpu_load(vcpu); 9892 9893 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 9894 r = -EBUSY; 9895 if (vcpu->arch.exception.pending) 9896 goto out; 9897 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 9898 kvm_queue_exception(vcpu, DB_VECTOR); 9899 else 9900 kvm_queue_exception(vcpu, BP_VECTOR); 9901 } 9902 9903 /* 9904 * Read rflags as long as potentially injected trace flags are still 9905 * filtered out. 9906 */ 9907 rflags = kvm_get_rflags(vcpu); 9908 9909 vcpu->guest_debug = dbg->control; 9910 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 9911 vcpu->guest_debug = 0; 9912 9913 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 9914 for (i = 0; i < KVM_NR_DB_REGS; ++i) 9915 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 9916 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 9917 } else { 9918 for (i = 0; i < KVM_NR_DB_REGS; i++) 9919 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 9920 } 9921 kvm_update_dr7(vcpu); 9922 9923 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 9924 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 9925 get_segment_base(vcpu, VCPU_SREG_CS); 9926 9927 /* 9928 * Trigger an rflags update that will inject or remove the trace 9929 * flags. 9930 */ 9931 kvm_set_rflags(vcpu, rflags); 9932 9933 static_call(kvm_x86_update_exception_bitmap)(vcpu); 9934 9935 r = 0; 9936 9937 out: 9938 vcpu_put(vcpu); 9939 return r; 9940 } 9941 9942 /* 9943 * Translate a guest virtual address to a guest physical address. 9944 */ 9945 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 9946 struct kvm_translation *tr) 9947 { 9948 unsigned long vaddr = tr->linear_address; 9949 gpa_t gpa; 9950 int idx; 9951 9952 vcpu_load(vcpu); 9953 9954 idx = srcu_read_lock(&vcpu->kvm->srcu); 9955 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 9956 srcu_read_unlock(&vcpu->kvm->srcu, idx); 9957 tr->physical_address = gpa; 9958 tr->valid = gpa != UNMAPPED_GVA; 9959 tr->writeable = 1; 9960 tr->usermode = 0; 9961 9962 vcpu_put(vcpu); 9963 return 0; 9964 } 9965 9966 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 9967 { 9968 struct fxregs_state *fxsave; 9969 9970 if (!vcpu->arch.guest_fpu) 9971 return 0; 9972 9973 vcpu_load(vcpu); 9974 9975 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 9976 memcpy(fpu->fpr, fxsave->st_space, 128); 9977 fpu->fcw = fxsave->cwd; 9978 fpu->fsw = fxsave->swd; 9979 fpu->ftwx = fxsave->twd; 9980 fpu->last_opcode = fxsave->fop; 9981 fpu->last_ip = fxsave->rip; 9982 fpu->last_dp = fxsave->rdp; 9983 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 9984 9985 vcpu_put(vcpu); 9986 return 0; 9987 } 9988 9989 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 9990 { 9991 struct fxregs_state *fxsave; 9992 9993 if (!vcpu->arch.guest_fpu) 9994 return 0; 9995 9996 vcpu_load(vcpu); 9997 9998 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 9999 10000 memcpy(fxsave->st_space, fpu->fpr, 128); 10001 fxsave->cwd = fpu->fcw; 10002 fxsave->swd = fpu->fsw; 10003 fxsave->twd = fpu->ftwx; 10004 fxsave->fop = fpu->last_opcode; 10005 fxsave->rip = fpu->last_ip; 10006 fxsave->rdp = fpu->last_dp; 10007 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 10008 10009 vcpu_put(vcpu); 10010 return 0; 10011 } 10012 10013 static void store_regs(struct kvm_vcpu *vcpu) 10014 { 10015 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 10016 10017 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 10018 __get_regs(vcpu, &vcpu->run->s.regs.regs); 10019 10020 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 10021 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 10022 10023 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 10024 kvm_vcpu_ioctl_x86_get_vcpu_events( 10025 vcpu, &vcpu->run->s.regs.events); 10026 } 10027 10028 static int sync_regs(struct kvm_vcpu *vcpu) 10029 { 10030 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) 10031 return -EINVAL; 10032 10033 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 10034 __set_regs(vcpu, &vcpu->run->s.regs.regs); 10035 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 10036 } 10037 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 10038 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 10039 return -EINVAL; 10040 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 10041 } 10042 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 10043 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 10044 vcpu, &vcpu->run->s.regs.events)) 10045 return -EINVAL; 10046 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 10047 } 10048 10049 return 0; 10050 } 10051 10052 static void fx_init(struct kvm_vcpu *vcpu) 10053 { 10054 if (!vcpu->arch.guest_fpu) 10055 return; 10056 10057 fpstate_init(&vcpu->arch.guest_fpu->state); 10058 if (boot_cpu_has(X86_FEATURE_XSAVES)) 10059 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = 10060 host_xcr0 | XSTATE_COMPACTION_ENABLED; 10061 10062 /* 10063 * Ensure guest xcr0 is valid for loading 10064 */ 10065 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 10066 10067 vcpu->arch.cr0 |= X86_CR0_ET; 10068 } 10069 10070 void kvm_free_guest_fpu(struct kvm_vcpu *vcpu) 10071 { 10072 if (vcpu->arch.guest_fpu) { 10073 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); 10074 vcpu->arch.guest_fpu = NULL; 10075 } 10076 } 10077 EXPORT_SYMBOL_GPL(kvm_free_guest_fpu); 10078 10079 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 10080 { 10081 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 10082 pr_warn_once("kvm: SMP vm created on host with unstable TSC; " 10083 "guest TSC will not be reliable\n"); 10084 10085 return 0; 10086 } 10087 10088 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 10089 { 10090 struct page *page; 10091 int r; 10092 10093 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 10094 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 10095 else 10096 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 10097 10098 kvm_set_tsc_khz(vcpu, max_tsc_khz); 10099 10100 r = kvm_mmu_create(vcpu); 10101 if (r < 0) 10102 return r; 10103 10104 if (irqchip_in_kernel(vcpu->kvm)) { 10105 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 10106 if (r < 0) 10107 goto fail_mmu_destroy; 10108 if (kvm_apicv_activated(vcpu->kvm)) 10109 vcpu->arch.apicv_active = true; 10110 } else 10111 static_branch_inc(&kvm_has_noapic_vcpu); 10112 10113 r = -ENOMEM; 10114 10115 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 10116 if (!page) 10117 goto fail_free_lapic; 10118 vcpu->arch.pio_data = page_address(page); 10119 10120 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 10121 GFP_KERNEL_ACCOUNT); 10122 if (!vcpu->arch.mce_banks) 10123 goto fail_free_pio_data; 10124 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 10125 10126 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 10127 GFP_KERNEL_ACCOUNT)) 10128 goto fail_free_mce_banks; 10129 10130 if (!alloc_emulate_ctxt(vcpu)) 10131 goto free_wbinvd_dirty_mask; 10132 10133 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, 10134 GFP_KERNEL_ACCOUNT); 10135 if (!vcpu->arch.user_fpu) { 10136 pr_err("kvm: failed to allocate userspace's fpu\n"); 10137 goto free_emulate_ctxt; 10138 } 10139 10140 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, 10141 GFP_KERNEL_ACCOUNT); 10142 if (!vcpu->arch.guest_fpu) { 10143 pr_err("kvm: failed to allocate vcpu's fpu\n"); 10144 goto free_user_fpu; 10145 } 10146 fx_init(vcpu); 10147 10148 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 10149 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 10150 10151 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 10152 10153 kvm_async_pf_hash_reset(vcpu); 10154 kvm_pmu_init(vcpu); 10155 10156 vcpu->arch.pending_external_vector = -1; 10157 vcpu->arch.preempted_in_kernel = false; 10158 10159 r = static_call(kvm_x86_vcpu_create)(vcpu); 10160 if (r) 10161 goto free_guest_fpu; 10162 10163 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 10164 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 10165 kvm_vcpu_mtrr_init(vcpu); 10166 vcpu_load(vcpu); 10167 kvm_vcpu_reset(vcpu, false); 10168 kvm_init_mmu(vcpu, false); 10169 vcpu_put(vcpu); 10170 return 0; 10171 10172 free_guest_fpu: 10173 kvm_free_guest_fpu(vcpu); 10174 free_user_fpu: 10175 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); 10176 free_emulate_ctxt: 10177 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 10178 free_wbinvd_dirty_mask: 10179 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 10180 fail_free_mce_banks: 10181 kfree(vcpu->arch.mce_banks); 10182 fail_free_pio_data: 10183 free_page((unsigned long)vcpu->arch.pio_data); 10184 fail_free_lapic: 10185 kvm_free_lapic(vcpu); 10186 fail_mmu_destroy: 10187 kvm_mmu_destroy(vcpu); 10188 return r; 10189 } 10190 10191 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 10192 { 10193 struct kvm *kvm = vcpu->kvm; 10194 10195 if (mutex_lock_killable(&vcpu->mutex)) 10196 return; 10197 vcpu_load(vcpu); 10198 kvm_synchronize_tsc(vcpu, 0); 10199 vcpu_put(vcpu); 10200 10201 /* poll control enabled by default */ 10202 vcpu->arch.msr_kvm_poll_control = 1; 10203 10204 mutex_unlock(&vcpu->mutex); 10205 10206 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) 10207 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 10208 KVMCLOCK_SYNC_PERIOD); 10209 } 10210 10211 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 10212 { 10213 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; 10214 int idx; 10215 10216 kvm_release_pfn(cache->pfn, cache->dirty, cache); 10217 10218 kvmclock_reset(vcpu); 10219 10220 static_call(kvm_x86_vcpu_free)(vcpu); 10221 10222 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 10223 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 10224 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); 10225 kvm_free_guest_fpu(vcpu); 10226 10227 kvm_hv_vcpu_uninit(vcpu); 10228 kvm_pmu_destroy(vcpu); 10229 kfree(vcpu->arch.mce_banks); 10230 kvm_free_lapic(vcpu); 10231 idx = srcu_read_lock(&vcpu->kvm->srcu); 10232 kvm_mmu_destroy(vcpu); 10233 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10234 free_page((unsigned long)vcpu->arch.pio_data); 10235 kvfree(vcpu->arch.cpuid_entries); 10236 if (!lapic_in_kernel(vcpu)) 10237 static_branch_dec(&kvm_has_noapic_vcpu); 10238 } 10239 10240 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 10241 { 10242 kvm_lapic_reset(vcpu, init_event); 10243 10244 vcpu->arch.hflags = 0; 10245 10246 vcpu->arch.smi_pending = 0; 10247 vcpu->arch.smi_count = 0; 10248 atomic_set(&vcpu->arch.nmi_queued, 0); 10249 vcpu->arch.nmi_pending = 0; 10250 vcpu->arch.nmi_injected = false; 10251 kvm_clear_interrupt_queue(vcpu); 10252 kvm_clear_exception_queue(vcpu); 10253 10254 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 10255 kvm_update_dr0123(vcpu); 10256 vcpu->arch.dr6 = DR6_ACTIVE_LOW; 10257 vcpu->arch.dr7 = DR7_FIXED_1; 10258 kvm_update_dr7(vcpu); 10259 10260 vcpu->arch.cr2 = 0; 10261 10262 kvm_make_request(KVM_REQ_EVENT, vcpu); 10263 vcpu->arch.apf.msr_en_val = 0; 10264 vcpu->arch.apf.msr_int_val = 0; 10265 vcpu->arch.st.msr_val = 0; 10266 10267 kvmclock_reset(vcpu); 10268 10269 kvm_clear_async_pf_completion_queue(vcpu); 10270 kvm_async_pf_hash_reset(vcpu); 10271 vcpu->arch.apf.halted = false; 10272 10273 if (vcpu->arch.guest_fpu && kvm_mpx_supported()) { 10274 void *mpx_state_buffer; 10275 10276 /* 10277 * To avoid have the INIT path from kvm_apic_has_events() that be 10278 * called with loaded FPU and does not let userspace fix the state. 10279 */ 10280 if (init_event) 10281 kvm_put_guest_fpu(vcpu); 10282 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 10283 XFEATURE_BNDREGS); 10284 if (mpx_state_buffer) 10285 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); 10286 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 10287 XFEATURE_BNDCSR); 10288 if (mpx_state_buffer) 10289 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); 10290 if (init_event) 10291 kvm_load_guest_fpu(vcpu); 10292 } 10293 10294 if (!init_event) { 10295 kvm_pmu_reset(vcpu); 10296 vcpu->arch.smbase = 0x30000; 10297 10298 vcpu->arch.msr_misc_features_enables = 0; 10299 10300 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 10301 } 10302 10303 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 10304 vcpu->arch.regs_avail = ~0; 10305 vcpu->arch.regs_dirty = ~0; 10306 10307 vcpu->arch.ia32_xss = 0; 10308 10309 static_call(kvm_x86_vcpu_reset)(vcpu, init_event); 10310 } 10311 10312 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 10313 { 10314 struct kvm_segment cs; 10315 10316 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 10317 cs.selector = vector << 8; 10318 cs.base = vector << 12; 10319 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 10320 kvm_rip_write(vcpu, 0); 10321 } 10322 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); 10323 10324 int kvm_arch_hardware_enable(void) 10325 { 10326 struct kvm *kvm; 10327 struct kvm_vcpu *vcpu; 10328 int i; 10329 int ret; 10330 u64 local_tsc; 10331 u64 max_tsc = 0; 10332 bool stable, backwards_tsc = false; 10333 10334 kvm_user_return_msr_cpu_online(); 10335 ret = static_call(kvm_x86_hardware_enable)(); 10336 if (ret != 0) 10337 return ret; 10338 10339 local_tsc = rdtsc(); 10340 stable = !kvm_check_tsc_unstable(); 10341 list_for_each_entry(kvm, &vm_list, vm_list) { 10342 kvm_for_each_vcpu(i, vcpu, kvm) { 10343 if (!stable && vcpu->cpu == smp_processor_id()) 10344 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 10345 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 10346 backwards_tsc = true; 10347 if (vcpu->arch.last_host_tsc > max_tsc) 10348 max_tsc = vcpu->arch.last_host_tsc; 10349 } 10350 } 10351 } 10352 10353 /* 10354 * Sometimes, even reliable TSCs go backwards. This happens on 10355 * platforms that reset TSC during suspend or hibernate actions, but 10356 * maintain synchronization. We must compensate. Fortunately, we can 10357 * detect that condition here, which happens early in CPU bringup, 10358 * before any KVM threads can be running. Unfortunately, we can't 10359 * bring the TSCs fully up to date with real time, as we aren't yet far 10360 * enough into CPU bringup that we know how much real time has actually 10361 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot 10362 * variables that haven't been updated yet. 10363 * 10364 * So we simply find the maximum observed TSC above, then record the 10365 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 10366 * the adjustment will be applied. Note that we accumulate 10367 * adjustments, in case multiple suspend cycles happen before some VCPU 10368 * gets a chance to run again. In the event that no KVM threads get a 10369 * chance to run, we will miss the entire elapsed period, as we'll have 10370 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 10371 * loose cycle time. This isn't too big a deal, since the loss will be 10372 * uniform across all VCPUs (not to mention the scenario is extremely 10373 * unlikely). It is possible that a second hibernate recovery happens 10374 * much faster than a first, causing the observed TSC here to be 10375 * smaller; this would require additional padding adjustment, which is 10376 * why we set last_host_tsc to the local tsc observed here. 10377 * 10378 * N.B. - this code below runs only on platforms with reliable TSC, 10379 * as that is the only way backwards_tsc is set above. Also note 10380 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 10381 * have the same delta_cyc adjustment applied if backwards_tsc 10382 * is detected. Note further, this adjustment is only done once, 10383 * as we reset last_host_tsc on all VCPUs to stop this from being 10384 * called multiple times (one for each physical CPU bringup). 10385 * 10386 * Platforms with unreliable TSCs don't have to deal with this, they 10387 * will be compensated by the logic in vcpu_load, which sets the TSC to 10388 * catchup mode. This will catchup all VCPUs to real time, but cannot 10389 * guarantee that they stay in perfect synchronization. 10390 */ 10391 if (backwards_tsc) { 10392 u64 delta_cyc = max_tsc - local_tsc; 10393 list_for_each_entry(kvm, &vm_list, vm_list) { 10394 kvm->arch.backwards_tsc_observed = true; 10395 kvm_for_each_vcpu(i, vcpu, kvm) { 10396 vcpu->arch.tsc_offset_adjustment += delta_cyc; 10397 vcpu->arch.last_host_tsc = local_tsc; 10398 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 10399 } 10400 10401 /* 10402 * We have to disable TSC offset matching.. if you were 10403 * booting a VM while issuing an S4 host suspend.... 10404 * you may have some problem. Solving this issue is 10405 * left as an exercise to the reader. 10406 */ 10407 kvm->arch.last_tsc_nsec = 0; 10408 kvm->arch.last_tsc_write = 0; 10409 } 10410 10411 } 10412 return 0; 10413 } 10414 10415 void kvm_arch_hardware_disable(void) 10416 { 10417 static_call(kvm_x86_hardware_disable)(); 10418 drop_user_return_notifiers(); 10419 } 10420 10421 int kvm_arch_hardware_setup(void *opaque) 10422 { 10423 struct kvm_x86_init_ops *ops = opaque; 10424 int r; 10425 10426 rdmsrl_safe(MSR_EFER, &host_efer); 10427 10428 if (boot_cpu_has(X86_FEATURE_XSAVES)) 10429 rdmsrl(MSR_IA32_XSS, host_xss); 10430 10431 r = ops->hardware_setup(); 10432 if (r != 0) 10433 return r; 10434 10435 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); 10436 kvm_ops_static_call_update(); 10437 10438 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) 10439 supported_xss = 0; 10440 10441 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) 10442 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); 10443 #undef __kvm_cpu_cap_has 10444 10445 if (kvm_has_tsc_control) { 10446 /* 10447 * Make sure the user can only configure tsc_khz values that 10448 * fit into a signed integer. 10449 * A min value is not calculated because it will always 10450 * be 1 on all machines. 10451 */ 10452 u64 max = min(0x7fffffffULL, 10453 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 10454 kvm_max_guest_tsc_khz = max; 10455 10456 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 10457 } 10458 10459 kvm_init_msr_list(); 10460 return 0; 10461 } 10462 10463 void kvm_arch_hardware_unsetup(void) 10464 { 10465 static_call(kvm_x86_hardware_unsetup)(); 10466 } 10467 10468 int kvm_arch_check_processor_compat(void *opaque) 10469 { 10470 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 10471 struct kvm_x86_init_ops *ops = opaque; 10472 10473 WARN_ON(!irqs_disabled()); 10474 10475 if (__cr4_reserved_bits(cpu_has, c) != 10476 __cr4_reserved_bits(cpu_has, &boot_cpu_data)) 10477 return -EIO; 10478 10479 return ops->check_processor_compatibility(); 10480 } 10481 10482 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 10483 { 10484 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 10485 } 10486 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 10487 10488 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 10489 { 10490 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 10491 } 10492 10493 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); 10494 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); 10495 10496 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 10497 { 10498 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 10499 10500 vcpu->arch.l1tf_flush_l1d = true; 10501 if (pmu->version && unlikely(pmu->event_count)) { 10502 pmu->need_cleanup = true; 10503 kvm_make_request(KVM_REQ_PMU, vcpu); 10504 } 10505 static_call(kvm_x86_sched_in)(vcpu, cpu); 10506 } 10507 10508 void kvm_arch_free_vm(struct kvm *kvm) 10509 { 10510 kfree(to_kvm_hv(kvm)->hv_pa_pg); 10511 vfree(kvm); 10512 } 10513 10514 10515 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 10516 { 10517 if (type) 10518 return -EINVAL; 10519 10520 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 10521 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 10522 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 10523 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); 10524 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 10525 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 10526 10527 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 10528 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 10529 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 10530 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 10531 &kvm->arch.irq_sources_bitmap); 10532 10533 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 10534 mutex_init(&kvm->arch.apic_map_lock); 10535 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 10536 10537 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); 10538 pvclock_update_vm_gtod_copy(kvm); 10539 10540 kvm->arch.guest_can_read_msr_platform_info = true; 10541 10542 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 10543 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 10544 10545 kvm_hv_init_vm(kvm); 10546 kvm_page_track_init(kvm); 10547 kvm_mmu_init_vm(kvm); 10548 10549 return static_call(kvm_x86_vm_init)(kvm); 10550 } 10551 10552 int kvm_arch_post_init_vm(struct kvm *kvm) 10553 { 10554 return kvm_mmu_post_init_vm(kvm); 10555 } 10556 10557 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 10558 { 10559 vcpu_load(vcpu); 10560 kvm_mmu_unload(vcpu); 10561 vcpu_put(vcpu); 10562 } 10563 10564 static void kvm_free_vcpus(struct kvm *kvm) 10565 { 10566 unsigned int i; 10567 struct kvm_vcpu *vcpu; 10568 10569 /* 10570 * Unpin any mmu pages first. 10571 */ 10572 kvm_for_each_vcpu(i, vcpu, kvm) { 10573 kvm_clear_async_pf_completion_queue(vcpu); 10574 kvm_unload_vcpu_mmu(vcpu); 10575 } 10576 kvm_for_each_vcpu(i, vcpu, kvm) 10577 kvm_vcpu_destroy(vcpu); 10578 10579 mutex_lock(&kvm->lock); 10580 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 10581 kvm->vcpus[i] = NULL; 10582 10583 atomic_set(&kvm->online_vcpus, 0); 10584 mutex_unlock(&kvm->lock); 10585 } 10586 10587 void kvm_arch_sync_events(struct kvm *kvm) 10588 { 10589 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 10590 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 10591 kvm_free_pit(kvm); 10592 } 10593 10594 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) 10595 10596 /** 10597 * __x86_set_memory_region: Setup KVM internal memory slot 10598 * 10599 * @kvm: the kvm pointer to the VM. 10600 * @id: the slot ID to setup. 10601 * @gpa: the GPA to install the slot (unused when @size == 0). 10602 * @size: the size of the slot. Set to zero to uninstall a slot. 10603 * 10604 * This function helps to setup a KVM internal memory slot. Specify 10605 * @size > 0 to install a new slot, while @size == 0 to uninstall a 10606 * slot. The return code can be one of the following: 10607 * 10608 * HVA: on success (uninstall will return a bogus HVA) 10609 * -errno: on error 10610 * 10611 * The caller should always use IS_ERR() to check the return value 10612 * before use. Note, the KVM internal memory slots are guaranteed to 10613 * remain valid and unchanged until the VM is destroyed, i.e., the 10614 * GPA->HVA translation will not change. However, the HVA is a user 10615 * address, i.e. its accessibility is not guaranteed, and must be 10616 * accessed via __copy_{to,from}_user(). 10617 */ 10618 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, 10619 u32 size) 10620 { 10621 int i, r; 10622 unsigned long hva, old_npages; 10623 struct kvm_memslots *slots = kvm_memslots(kvm); 10624 struct kvm_memory_slot *slot; 10625 10626 /* Called with kvm->slots_lock held. */ 10627 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 10628 return ERR_PTR_USR(-EINVAL); 10629 10630 slot = id_to_memslot(slots, id); 10631 if (size) { 10632 if (slot && slot->npages) 10633 return ERR_PTR_USR(-EEXIST); 10634 10635 /* 10636 * MAP_SHARED to prevent internal slot pages from being moved 10637 * by fork()/COW. 10638 */ 10639 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 10640 MAP_SHARED | MAP_ANONYMOUS, 0); 10641 if (IS_ERR((void *)hva)) 10642 return (void __user *)hva; 10643 } else { 10644 if (!slot || !slot->npages) 10645 return NULL; 10646 10647 old_npages = slot->npages; 10648 hva = slot->userspace_addr; 10649 } 10650 10651 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 10652 struct kvm_userspace_memory_region m; 10653 10654 m.slot = id | (i << 16); 10655 m.flags = 0; 10656 m.guest_phys_addr = gpa; 10657 m.userspace_addr = hva; 10658 m.memory_size = size; 10659 r = __kvm_set_memory_region(kvm, &m); 10660 if (r < 0) 10661 return ERR_PTR_USR(r); 10662 } 10663 10664 if (!size) 10665 vm_munmap(hva, old_npages * PAGE_SIZE); 10666 10667 return (void __user *)hva; 10668 } 10669 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 10670 10671 void kvm_arch_pre_destroy_vm(struct kvm *kvm) 10672 { 10673 kvm_mmu_pre_destroy_vm(kvm); 10674 } 10675 10676 void kvm_arch_destroy_vm(struct kvm *kvm) 10677 { 10678 if (current->mm == kvm->mm) { 10679 /* 10680 * Free memory regions allocated on behalf of userspace, 10681 * unless the the memory map has changed due to process exit 10682 * or fd copying. 10683 */ 10684 mutex_lock(&kvm->slots_lock); 10685 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 10686 0, 0); 10687 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 10688 0, 0); 10689 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 10690 mutex_unlock(&kvm->slots_lock); 10691 } 10692 static_call_cond(kvm_x86_vm_destroy)(kvm); 10693 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); 10694 kvm_pic_destroy(kvm); 10695 kvm_ioapic_destroy(kvm); 10696 kvm_free_vcpus(kvm); 10697 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 10698 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); 10699 kvm_mmu_uninit_vm(kvm); 10700 kvm_page_track_cleanup(kvm); 10701 kvm_xen_destroy_vm(kvm); 10702 kvm_hv_destroy_vm(kvm); 10703 } 10704 10705 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) 10706 { 10707 int i; 10708 10709 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 10710 kvfree(slot->arch.rmap[i]); 10711 slot->arch.rmap[i] = NULL; 10712 10713 if (i == 0) 10714 continue; 10715 10716 kvfree(slot->arch.lpage_info[i - 1]); 10717 slot->arch.lpage_info[i - 1] = NULL; 10718 } 10719 10720 kvm_page_track_free_memslot(slot); 10721 } 10722 10723 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot, 10724 unsigned long npages) 10725 { 10726 int i; 10727 10728 /* 10729 * Clear out the previous array pointers for the KVM_MR_MOVE case. The 10730 * old arrays will be freed by __kvm_set_memory_region() if installing 10731 * the new memslot is successful. 10732 */ 10733 memset(&slot->arch, 0, sizeof(slot->arch)); 10734 10735 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 10736 struct kvm_lpage_info *linfo; 10737 unsigned long ugfn; 10738 int lpages; 10739 int level = i + 1; 10740 10741 lpages = gfn_to_index(slot->base_gfn + npages - 1, 10742 slot->base_gfn, level) + 1; 10743 10744 slot->arch.rmap[i] = 10745 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), 10746 GFP_KERNEL_ACCOUNT); 10747 if (!slot->arch.rmap[i]) 10748 goto out_free; 10749 if (i == 0) 10750 continue; 10751 10752 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 10753 if (!linfo) 10754 goto out_free; 10755 10756 slot->arch.lpage_info[i - 1] = linfo; 10757 10758 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 10759 linfo[0].disallow_lpage = 1; 10760 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 10761 linfo[lpages - 1].disallow_lpage = 1; 10762 ugfn = slot->userspace_addr >> PAGE_SHIFT; 10763 /* 10764 * If the gfn and userspace address are not aligned wrt each 10765 * other, disable large page support for this slot. 10766 */ 10767 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { 10768 unsigned long j; 10769 10770 for (j = 0; j < lpages; ++j) 10771 linfo[j].disallow_lpage = 1; 10772 } 10773 } 10774 10775 if (kvm_page_track_create_memslot(slot, npages)) 10776 goto out_free; 10777 10778 return 0; 10779 10780 out_free: 10781 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 10782 kvfree(slot->arch.rmap[i]); 10783 slot->arch.rmap[i] = NULL; 10784 if (i == 0) 10785 continue; 10786 10787 kvfree(slot->arch.lpage_info[i - 1]); 10788 slot->arch.lpage_info[i - 1] = NULL; 10789 } 10790 return -ENOMEM; 10791 } 10792 10793 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 10794 { 10795 struct kvm_vcpu *vcpu; 10796 int i; 10797 10798 /* 10799 * memslots->generation has been incremented. 10800 * mmio generation may have reached its maximum value. 10801 */ 10802 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 10803 10804 /* Force re-initialization of steal_time cache */ 10805 kvm_for_each_vcpu(i, vcpu, kvm) 10806 kvm_vcpu_kick(vcpu); 10807 } 10808 10809 int kvm_arch_prepare_memory_region(struct kvm *kvm, 10810 struct kvm_memory_slot *memslot, 10811 const struct kvm_userspace_memory_region *mem, 10812 enum kvm_mr_change change) 10813 { 10814 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) 10815 return kvm_alloc_memslot_metadata(memslot, 10816 mem->memory_size >> PAGE_SHIFT); 10817 return 0; 10818 } 10819 10820 10821 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) 10822 { 10823 struct kvm_arch *ka = &kvm->arch; 10824 10825 if (!kvm_x86_ops.cpu_dirty_log_size) 10826 return; 10827 10828 if ((enable && ++ka->cpu_dirty_logging_count == 1) || 10829 (!enable && --ka->cpu_dirty_logging_count == 0)) 10830 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); 10831 10832 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); 10833 } 10834 10835 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 10836 struct kvm_memory_slot *old, 10837 struct kvm_memory_slot *new, 10838 enum kvm_mr_change change) 10839 { 10840 bool log_dirty_pages = new->flags & KVM_MEM_LOG_DIRTY_PAGES; 10841 10842 /* 10843 * Update CPU dirty logging if dirty logging is being toggled. This 10844 * applies to all operations. 10845 */ 10846 if ((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES) 10847 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); 10848 10849 /* 10850 * Nothing more to do for RO slots (which can't be dirtied and can't be 10851 * made writable) or CREATE/MOVE/DELETE of a slot. 10852 * 10853 * For a memslot with dirty logging disabled: 10854 * CREATE: No dirty mappings will already exist. 10855 * MOVE/DELETE: The old mappings will already have been cleaned up by 10856 * kvm_arch_flush_shadow_memslot() 10857 * 10858 * For a memslot with dirty logging enabled: 10859 * CREATE: No shadow pages exist, thus nothing to write-protect 10860 * and no dirty bits to clear. 10861 * MOVE/DELETE: The old mappings will already have been cleaned up by 10862 * kvm_arch_flush_shadow_memslot(). 10863 */ 10864 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) 10865 return; 10866 10867 /* 10868 * READONLY and non-flags changes were filtered out above, and the only 10869 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty 10870 * logging isn't being toggled on or off. 10871 */ 10872 if (WARN_ON_ONCE(!((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES))) 10873 return; 10874 10875 if (!log_dirty_pages) { 10876 /* 10877 * Dirty logging tracks sptes in 4k granularity, meaning that 10878 * large sptes have to be split. If live migration succeeds, 10879 * the guest in the source machine will be destroyed and large 10880 * sptes will be created in the destination. However, if the 10881 * guest continues to run in the source machine (for example if 10882 * live migration fails), small sptes will remain around and 10883 * cause bad performance. 10884 * 10885 * Scan sptes if dirty logging has been stopped, dropping those 10886 * which can be collapsed into a single large-page spte. Later 10887 * page faults will create the large-page sptes. 10888 */ 10889 kvm_mmu_zap_collapsible_sptes(kvm, new); 10890 } else { 10891 /* By default, write-protect everything to log writes. */ 10892 int level = PG_LEVEL_4K; 10893 10894 if (kvm_x86_ops.cpu_dirty_log_size) { 10895 /* 10896 * Clear all dirty bits, unless pages are treated as 10897 * dirty from the get-go. 10898 */ 10899 if (!kvm_dirty_log_manual_protect_and_init_set(kvm)) 10900 kvm_mmu_slot_leaf_clear_dirty(kvm, new); 10901 10902 /* 10903 * Write-protect large pages on write so that dirty 10904 * logging happens at 4k granularity. No need to 10905 * write-protect small SPTEs since write accesses are 10906 * logged by the CPU via dirty bits. 10907 */ 10908 level = PG_LEVEL_2M; 10909 } else if (kvm_dirty_log_manual_protect_and_init_set(kvm)) { 10910 /* 10911 * If we're with initial-all-set, we don't need 10912 * to write protect any small page because 10913 * they're reported as dirty already. However 10914 * we still need to write-protect huge pages 10915 * so that the page split can happen lazily on 10916 * the first write to the huge page. 10917 */ 10918 level = PG_LEVEL_2M; 10919 } 10920 kvm_mmu_slot_remove_write_access(kvm, new, level); 10921 } 10922 } 10923 10924 void kvm_arch_commit_memory_region(struct kvm *kvm, 10925 const struct kvm_userspace_memory_region *mem, 10926 struct kvm_memory_slot *old, 10927 const struct kvm_memory_slot *new, 10928 enum kvm_mr_change change) 10929 { 10930 if (!kvm->arch.n_requested_mmu_pages) 10931 kvm_mmu_change_mmu_pages(kvm, 10932 kvm_mmu_calculate_default_mmu_pages(kvm)); 10933 10934 /* 10935 * FIXME: const-ify all uses of struct kvm_memory_slot. 10936 */ 10937 kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change); 10938 10939 /* Free the arrays associated with the old memslot. */ 10940 if (change == KVM_MR_MOVE) 10941 kvm_arch_free_memslot(kvm, old); 10942 } 10943 10944 void kvm_arch_flush_shadow_all(struct kvm *kvm) 10945 { 10946 kvm_mmu_zap_all(kvm); 10947 } 10948 10949 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 10950 struct kvm_memory_slot *slot) 10951 { 10952 kvm_page_track_flush_slot(kvm, slot); 10953 } 10954 10955 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 10956 { 10957 return (is_guest_mode(vcpu) && 10958 kvm_x86_ops.guest_apic_has_interrupt && 10959 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); 10960 } 10961 10962 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 10963 { 10964 if (!list_empty_careful(&vcpu->async_pf.done)) 10965 return true; 10966 10967 if (kvm_apic_has_events(vcpu)) 10968 return true; 10969 10970 if (vcpu->arch.pv.pv_unhalted) 10971 return true; 10972 10973 if (vcpu->arch.exception.pending) 10974 return true; 10975 10976 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 10977 (vcpu->arch.nmi_pending && 10978 static_call(kvm_x86_nmi_allowed)(vcpu, false))) 10979 return true; 10980 10981 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 10982 (vcpu->arch.smi_pending && 10983 static_call(kvm_x86_smi_allowed)(vcpu, false))) 10984 return true; 10985 10986 if (kvm_arch_interrupt_allowed(vcpu) && 10987 (kvm_cpu_has_interrupt(vcpu) || 10988 kvm_guest_apic_has_interrupt(vcpu))) 10989 return true; 10990 10991 if (kvm_hv_has_stimer_pending(vcpu)) 10992 return true; 10993 10994 if (is_guest_mode(vcpu) && 10995 kvm_x86_ops.nested_ops->hv_timer_pending && 10996 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 10997 return true; 10998 10999 return false; 11000 } 11001 11002 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 11003 { 11004 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 11005 } 11006 11007 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) 11008 { 11009 if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) 11010 return true; 11011 11012 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 11013 kvm_test_request(KVM_REQ_SMI, vcpu) || 11014 kvm_test_request(KVM_REQ_EVENT, vcpu)) 11015 return true; 11016 11017 if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) 11018 return true; 11019 11020 return false; 11021 } 11022 11023 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 11024 { 11025 return vcpu->arch.preempted_in_kernel; 11026 } 11027 11028 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 11029 { 11030 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 11031 } 11032 11033 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 11034 { 11035 return static_call(kvm_x86_interrupt_allowed)(vcpu, false); 11036 } 11037 11038 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 11039 { 11040 /* Can't read the RIP when guest state is protected, just return 0 */ 11041 if (vcpu->arch.guest_state_protected) 11042 return 0; 11043 11044 if (is_64_bit_mode(vcpu)) 11045 return kvm_rip_read(vcpu); 11046 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 11047 kvm_rip_read(vcpu)); 11048 } 11049 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 11050 11051 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 11052 { 11053 return kvm_get_linear_rip(vcpu) == linear_rip; 11054 } 11055 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 11056 11057 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 11058 { 11059 unsigned long rflags; 11060 11061 rflags = static_call(kvm_x86_get_rflags)(vcpu); 11062 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 11063 rflags &= ~X86_EFLAGS_TF; 11064 return rflags; 11065 } 11066 EXPORT_SYMBOL_GPL(kvm_get_rflags); 11067 11068 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 11069 { 11070 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 11071 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 11072 rflags |= X86_EFLAGS_TF; 11073 static_call(kvm_x86_set_rflags)(vcpu, rflags); 11074 } 11075 11076 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 11077 { 11078 __kvm_set_rflags(vcpu, rflags); 11079 kvm_make_request(KVM_REQ_EVENT, vcpu); 11080 } 11081 EXPORT_SYMBOL_GPL(kvm_set_rflags); 11082 11083 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 11084 { 11085 int r; 11086 11087 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || 11088 work->wakeup_all) 11089 return; 11090 11091 r = kvm_mmu_reload(vcpu); 11092 if (unlikely(r)) 11093 return; 11094 11095 if (!vcpu->arch.mmu->direct_map && 11096 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) 11097 return; 11098 11099 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); 11100 } 11101 11102 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 11103 { 11104 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); 11105 11106 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 11107 } 11108 11109 static inline u32 kvm_async_pf_next_probe(u32 key) 11110 { 11111 return (key + 1) & (ASYNC_PF_PER_VCPU - 1); 11112 } 11113 11114 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11115 { 11116 u32 key = kvm_async_pf_hash_fn(gfn); 11117 11118 while (vcpu->arch.apf.gfns[key] != ~0) 11119 key = kvm_async_pf_next_probe(key); 11120 11121 vcpu->arch.apf.gfns[key] = gfn; 11122 } 11123 11124 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 11125 { 11126 int i; 11127 u32 key = kvm_async_pf_hash_fn(gfn); 11128 11129 for (i = 0; i < ASYNC_PF_PER_VCPU && 11130 (vcpu->arch.apf.gfns[key] != gfn && 11131 vcpu->arch.apf.gfns[key] != ~0); i++) 11132 key = kvm_async_pf_next_probe(key); 11133 11134 return key; 11135 } 11136 11137 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11138 { 11139 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 11140 } 11141 11142 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11143 { 11144 u32 i, j, k; 11145 11146 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 11147 11148 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) 11149 return; 11150 11151 while (true) { 11152 vcpu->arch.apf.gfns[i] = ~0; 11153 do { 11154 j = kvm_async_pf_next_probe(j); 11155 if (vcpu->arch.apf.gfns[j] == ~0) 11156 return; 11157 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 11158 /* 11159 * k lies cyclically in ]i,j] 11160 * | i.k.j | 11161 * |....j i.k.| or |.k..j i...| 11162 */ 11163 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 11164 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 11165 i = j; 11166 } 11167 } 11168 11169 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) 11170 { 11171 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; 11172 11173 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, 11174 sizeof(reason)); 11175 } 11176 11177 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) 11178 { 11179 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 11180 11181 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 11182 &token, offset, sizeof(token)); 11183 } 11184 11185 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) 11186 { 11187 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 11188 u32 val; 11189 11190 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 11191 &val, offset, sizeof(val))) 11192 return false; 11193 11194 return !val; 11195 } 11196 11197 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) 11198 { 11199 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) 11200 return false; 11201 11202 if (!kvm_pv_async_pf_enabled(vcpu) || 11203 (vcpu->arch.apf.send_user_only && static_call(kvm_x86_get_cpl)(vcpu) == 0)) 11204 return false; 11205 11206 return true; 11207 } 11208 11209 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) 11210 { 11211 if (unlikely(!lapic_in_kernel(vcpu) || 11212 kvm_event_needs_reinjection(vcpu) || 11213 vcpu->arch.exception.pending)) 11214 return false; 11215 11216 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) 11217 return false; 11218 11219 /* 11220 * If interrupts are off we cannot even use an artificial 11221 * halt state. 11222 */ 11223 return kvm_arch_interrupt_allowed(vcpu); 11224 } 11225 11226 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 11227 struct kvm_async_pf *work) 11228 { 11229 struct x86_exception fault; 11230 11231 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); 11232 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 11233 11234 if (kvm_can_deliver_async_pf(vcpu) && 11235 !apf_put_user_notpresent(vcpu)) { 11236 fault.vector = PF_VECTOR; 11237 fault.error_code_valid = true; 11238 fault.error_code = 0; 11239 fault.nested_page_fault = false; 11240 fault.address = work->arch.token; 11241 fault.async_page_fault = true; 11242 kvm_inject_page_fault(vcpu, &fault); 11243 return true; 11244 } else { 11245 /* 11246 * It is not possible to deliver a paravirtualized asynchronous 11247 * page fault, but putting the guest in an artificial halt state 11248 * can be beneficial nevertheless: if an interrupt arrives, we 11249 * can deliver it timely and perhaps the guest will schedule 11250 * another process. When the instruction that triggered a page 11251 * fault is retried, hopefully the page will be ready in the host. 11252 */ 11253 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 11254 return false; 11255 } 11256 } 11257 11258 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 11259 struct kvm_async_pf *work) 11260 { 11261 struct kvm_lapic_irq irq = { 11262 .delivery_mode = APIC_DM_FIXED, 11263 .vector = vcpu->arch.apf.vec 11264 }; 11265 11266 if (work->wakeup_all) 11267 work->arch.token = ~0; /* broadcast wakeup */ 11268 else 11269 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 11270 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); 11271 11272 if ((work->wakeup_all || work->notpresent_injected) && 11273 kvm_pv_async_pf_enabled(vcpu) && 11274 !apf_put_user_ready(vcpu, work->arch.token)) { 11275 vcpu->arch.apf.pageready_pending = true; 11276 kvm_apic_set_irq(vcpu, &irq, NULL); 11277 } 11278 11279 vcpu->arch.apf.halted = false; 11280 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 11281 } 11282 11283 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) 11284 { 11285 kvm_make_request(KVM_REQ_APF_READY, vcpu); 11286 if (!vcpu->arch.apf.pageready_pending) 11287 kvm_vcpu_kick(vcpu); 11288 } 11289 11290 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) 11291 { 11292 if (!kvm_pv_async_pf_enabled(vcpu)) 11293 return true; 11294 else 11295 return apf_pageready_slot_free(vcpu); 11296 } 11297 11298 void kvm_arch_start_assignment(struct kvm *kvm) 11299 { 11300 atomic_inc(&kvm->arch.assigned_device_count); 11301 } 11302 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 11303 11304 void kvm_arch_end_assignment(struct kvm *kvm) 11305 { 11306 atomic_dec(&kvm->arch.assigned_device_count); 11307 } 11308 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 11309 11310 bool kvm_arch_has_assigned_device(struct kvm *kvm) 11311 { 11312 return atomic_read(&kvm->arch.assigned_device_count); 11313 } 11314 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 11315 11316 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 11317 { 11318 atomic_inc(&kvm->arch.noncoherent_dma_count); 11319 } 11320 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 11321 11322 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 11323 { 11324 atomic_dec(&kvm->arch.noncoherent_dma_count); 11325 } 11326 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 11327 11328 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 11329 { 11330 return atomic_read(&kvm->arch.noncoherent_dma_count); 11331 } 11332 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 11333 11334 bool kvm_arch_has_irq_bypass(void) 11335 { 11336 return true; 11337 } 11338 11339 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 11340 struct irq_bypass_producer *prod) 11341 { 11342 struct kvm_kernel_irqfd *irqfd = 11343 container_of(cons, struct kvm_kernel_irqfd, consumer); 11344 int ret; 11345 11346 irqfd->producer = prod; 11347 kvm_arch_start_assignment(irqfd->kvm); 11348 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, 11349 prod->irq, irqfd->gsi, 1); 11350 11351 if (ret) 11352 kvm_arch_end_assignment(irqfd->kvm); 11353 11354 return ret; 11355 } 11356 11357 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 11358 struct irq_bypass_producer *prod) 11359 { 11360 int ret; 11361 struct kvm_kernel_irqfd *irqfd = 11362 container_of(cons, struct kvm_kernel_irqfd, consumer); 11363 11364 WARN_ON(irqfd->producer != prod); 11365 irqfd->producer = NULL; 11366 11367 /* 11368 * When producer of consumer is unregistered, we change back to 11369 * remapped mode, so we can re-use the current implementation 11370 * when the irq is masked/disabled or the consumer side (KVM 11371 * int this case doesn't want to receive the interrupts. 11372 */ 11373 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); 11374 if (ret) 11375 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 11376 " fails: %d\n", irqfd->consumer.token, ret); 11377 11378 kvm_arch_end_assignment(irqfd->kvm); 11379 } 11380 11381 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 11382 uint32_t guest_irq, bool set) 11383 { 11384 return static_call(kvm_x86_update_pi_irte)(kvm, host_irq, guest_irq, set); 11385 } 11386 11387 bool kvm_vector_hashing_enabled(void) 11388 { 11389 return vector_hashing; 11390 } 11391 11392 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) 11393 { 11394 return (vcpu->arch.msr_kvm_poll_control & 1) == 0; 11395 } 11396 EXPORT_SYMBOL_GPL(kvm_arch_no_poll); 11397 11398 11399 int kvm_spec_ctrl_test_value(u64 value) 11400 { 11401 /* 11402 * test that setting IA32_SPEC_CTRL to given value 11403 * is allowed by the host processor 11404 */ 11405 11406 u64 saved_value; 11407 unsigned long flags; 11408 int ret = 0; 11409 11410 local_irq_save(flags); 11411 11412 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) 11413 ret = 1; 11414 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) 11415 ret = 1; 11416 else 11417 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); 11418 11419 local_irq_restore(flags); 11420 11421 return ret; 11422 } 11423 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); 11424 11425 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) 11426 { 11427 struct x86_exception fault; 11428 u32 access = error_code & 11429 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); 11430 11431 if (!(error_code & PFERR_PRESENT_MASK) || 11432 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) { 11433 /* 11434 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page 11435 * tables probably do not match the TLB. Just proceed 11436 * with the error code that the processor gave. 11437 */ 11438 fault.vector = PF_VECTOR; 11439 fault.error_code_valid = true; 11440 fault.error_code = error_code; 11441 fault.nested_page_fault = false; 11442 fault.address = gva; 11443 } 11444 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); 11445 } 11446 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); 11447 11448 /* 11449 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns 11450 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value 11451 * indicates whether exit to userspace is needed. 11452 */ 11453 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 11454 struct x86_exception *e) 11455 { 11456 if (r == X86EMUL_PROPAGATE_FAULT) { 11457 kvm_inject_emulated_page_fault(vcpu, e); 11458 return 1; 11459 } 11460 11461 /* 11462 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED 11463 * while handling a VMX instruction KVM could've handled the request 11464 * correctly by exiting to userspace and performing I/O but there 11465 * doesn't seem to be a real use-case behind such requests, just return 11466 * KVM_EXIT_INTERNAL_ERROR for now. 11467 */ 11468 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 11469 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 11470 vcpu->run->internal.ndata = 0; 11471 11472 return 0; 11473 } 11474 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); 11475 11476 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) 11477 { 11478 bool pcid_enabled; 11479 struct x86_exception e; 11480 unsigned i; 11481 unsigned long roots_to_free = 0; 11482 struct { 11483 u64 pcid; 11484 u64 gla; 11485 } operand; 11486 int r; 11487 11488 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 11489 if (r != X86EMUL_CONTINUE) 11490 return kvm_handle_memory_failure(vcpu, r, &e); 11491 11492 if (operand.pcid >> 12 != 0) { 11493 kvm_inject_gp(vcpu, 0); 11494 return 1; 11495 } 11496 11497 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 11498 11499 switch (type) { 11500 case INVPCID_TYPE_INDIV_ADDR: 11501 if ((!pcid_enabled && (operand.pcid != 0)) || 11502 is_noncanonical_address(operand.gla, vcpu)) { 11503 kvm_inject_gp(vcpu, 0); 11504 return 1; 11505 } 11506 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 11507 return kvm_skip_emulated_instruction(vcpu); 11508 11509 case INVPCID_TYPE_SINGLE_CTXT: 11510 if (!pcid_enabled && (operand.pcid != 0)) { 11511 kvm_inject_gp(vcpu, 0); 11512 return 1; 11513 } 11514 11515 if (kvm_get_active_pcid(vcpu) == operand.pcid) { 11516 kvm_mmu_sync_roots(vcpu); 11517 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 11518 } 11519 11520 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 11521 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd) 11522 == operand.pcid) 11523 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 11524 11525 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); 11526 /* 11527 * If neither the current cr3 nor any of the prev_roots use the 11528 * given PCID, then nothing needs to be done here because a 11529 * resync will happen anyway before switching to any other CR3. 11530 */ 11531 11532 return kvm_skip_emulated_instruction(vcpu); 11533 11534 case INVPCID_TYPE_ALL_NON_GLOBAL: 11535 /* 11536 * Currently, KVM doesn't mark global entries in the shadow 11537 * page tables, so a non-global flush just degenerates to a 11538 * global flush. If needed, we could optimize this later by 11539 * keeping track of global entries in shadow page tables. 11540 */ 11541 11542 fallthrough; 11543 case INVPCID_TYPE_ALL_INCL_GLOBAL: 11544 kvm_mmu_unload(vcpu); 11545 return kvm_skip_emulated_instruction(vcpu); 11546 11547 default: 11548 BUG(); /* We have already checked above that type <= 3 */ 11549 } 11550 } 11551 EXPORT_SYMBOL_GPL(kvm_handle_invpcid); 11552 11553 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) 11554 { 11555 struct kvm_run *run = vcpu->run; 11556 struct kvm_mmio_fragment *frag; 11557 unsigned int len; 11558 11559 BUG_ON(!vcpu->mmio_needed); 11560 11561 /* Complete previous fragment */ 11562 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 11563 len = min(8u, frag->len); 11564 if (!vcpu->mmio_is_write) 11565 memcpy(frag->data, run->mmio.data, len); 11566 11567 if (frag->len <= 8) { 11568 /* Switch to the next fragment. */ 11569 frag++; 11570 vcpu->mmio_cur_fragment++; 11571 } else { 11572 /* Go forward to the next mmio piece. */ 11573 frag->data += len; 11574 frag->gpa += len; 11575 frag->len -= len; 11576 } 11577 11578 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 11579 vcpu->mmio_needed = 0; 11580 11581 // VMG change, at this point, we're always done 11582 // RIP has already been advanced 11583 return 1; 11584 } 11585 11586 // More MMIO is needed 11587 run->mmio.phys_addr = frag->gpa; 11588 run->mmio.len = min(8u, frag->len); 11589 run->mmio.is_write = vcpu->mmio_is_write; 11590 if (run->mmio.is_write) 11591 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 11592 run->exit_reason = KVM_EXIT_MMIO; 11593 11594 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 11595 11596 return 0; 11597 } 11598 11599 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 11600 void *data) 11601 { 11602 int handled; 11603 struct kvm_mmio_fragment *frag; 11604 11605 if (!data) 11606 return -EINVAL; 11607 11608 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); 11609 if (handled == bytes) 11610 return 1; 11611 11612 bytes -= handled; 11613 gpa += handled; 11614 data += handled; 11615 11616 /*TODO: Check if need to increment number of frags */ 11617 frag = vcpu->mmio_fragments; 11618 vcpu->mmio_nr_fragments = 1; 11619 frag->len = bytes; 11620 frag->gpa = gpa; 11621 frag->data = data; 11622 11623 vcpu->mmio_needed = 1; 11624 vcpu->mmio_cur_fragment = 0; 11625 11626 vcpu->run->mmio.phys_addr = gpa; 11627 vcpu->run->mmio.len = min(8u, frag->len); 11628 vcpu->run->mmio.is_write = 1; 11629 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 11630 vcpu->run->exit_reason = KVM_EXIT_MMIO; 11631 11632 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 11633 11634 return 0; 11635 } 11636 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); 11637 11638 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 11639 void *data) 11640 { 11641 int handled; 11642 struct kvm_mmio_fragment *frag; 11643 11644 if (!data) 11645 return -EINVAL; 11646 11647 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); 11648 if (handled == bytes) 11649 return 1; 11650 11651 bytes -= handled; 11652 gpa += handled; 11653 data += handled; 11654 11655 /*TODO: Check if need to increment number of frags */ 11656 frag = vcpu->mmio_fragments; 11657 vcpu->mmio_nr_fragments = 1; 11658 frag->len = bytes; 11659 frag->gpa = gpa; 11660 frag->data = data; 11661 11662 vcpu->mmio_needed = 1; 11663 vcpu->mmio_cur_fragment = 0; 11664 11665 vcpu->run->mmio.phys_addr = gpa; 11666 vcpu->run->mmio.len = min(8u, frag->len); 11667 vcpu->run->mmio.is_write = 0; 11668 vcpu->run->exit_reason = KVM_EXIT_MMIO; 11669 11670 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 11671 11672 return 0; 11673 } 11674 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); 11675 11676 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 11677 { 11678 memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data, 11679 vcpu->arch.pio.count * vcpu->arch.pio.size); 11680 vcpu->arch.pio.count = 0; 11681 11682 return 1; 11683 } 11684 11685 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 11686 unsigned int port, void *data, unsigned int count) 11687 { 11688 int ret; 11689 11690 ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port, 11691 data, count); 11692 if (ret) 11693 return ret; 11694 11695 vcpu->arch.pio.count = 0; 11696 11697 return 0; 11698 } 11699 11700 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 11701 unsigned int port, void *data, unsigned int count) 11702 { 11703 int ret; 11704 11705 ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port, 11706 data, count); 11707 if (ret) { 11708 vcpu->arch.pio.count = 0; 11709 } else { 11710 vcpu->arch.guest_ins_data = data; 11711 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; 11712 } 11713 11714 return 0; 11715 } 11716 11717 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 11718 unsigned int port, void *data, unsigned int count, 11719 int in) 11720 { 11721 return in ? kvm_sev_es_ins(vcpu, size, port, data, count) 11722 : kvm_sev_es_outs(vcpu, size, port, data, count); 11723 } 11724 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); 11725 11726 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); 11727 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 11728 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 11729 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 11730 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 11731 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 11732 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 11733 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 11734 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 11735 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 11736 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 11737 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); 11738 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 11739 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 11740 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 11741 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 11742 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); 11743 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 11744 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 11745 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 11746 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 11747 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); 11748 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); 11749 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); 11750 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); 11751 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); 11752 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); 11753