1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "assigned-dev.h" 31 32 #include <linux/clocksource.h> 33 #include <linux/interrupt.h> 34 #include <linux/kvm.h> 35 #include <linux/fs.h> 36 #include <linux/vmalloc.h> 37 #include <linux/module.h> 38 #include <linux/mman.h> 39 #include <linux/highmem.h> 40 #include <linux/iommu.h> 41 #include <linux/intel-iommu.h> 42 #include <linux/cpufreq.h> 43 #include <linux/user-return-notifier.h> 44 #include <linux/srcu.h> 45 #include <linux/slab.h> 46 #include <linux/perf_event.h> 47 #include <linux/uaccess.h> 48 #include <linux/hash.h> 49 #include <linux/pci.h> 50 #include <linux/timekeeper_internal.h> 51 #include <linux/pvclock_gtod.h> 52 #include <trace/events/kvm.h> 53 54 #define CREATE_TRACE_POINTS 55 #include "trace.h" 56 57 #include <asm/debugreg.h> 58 #include <asm/msr.h> 59 #include <asm/desc.h> 60 #include <asm/mtrr.h> 61 #include <asm/mce.h> 62 #include <asm/i387.h> 63 #include <asm/fpu-internal.h> /* Ugh! */ 64 #include <asm/xcr.h> 65 #include <asm/pvclock.h> 66 #include <asm/div64.h> 67 68 #define MAX_IO_MSRS 256 69 #define KVM_MAX_MCE_BANKS 32 70 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) 71 72 #define emul_to_vcpu(ctxt) \ 73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 74 75 /* EFER defaults: 76 * - enable syscall per default because its emulated by KVM 77 * - enable LME and LMA per default on 64 bit KVM 78 */ 79 #ifdef CONFIG_X86_64 80 static 81 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 82 #else 83 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 84 #endif 85 86 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 87 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 88 89 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 90 static void process_nmi(struct kvm_vcpu *vcpu); 91 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 92 93 struct kvm_x86_ops *kvm_x86_ops; 94 EXPORT_SYMBOL_GPL(kvm_x86_ops); 95 96 static bool ignore_msrs = 0; 97 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 98 99 unsigned int min_timer_period_us = 500; 100 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 101 102 bool kvm_has_tsc_control; 103 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 104 u32 kvm_max_guest_tsc_khz; 105 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 106 107 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 108 static u32 tsc_tolerance_ppm = 250; 109 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 110 111 /* lapic timer advance (tscdeadline mode only) in nanoseconds */ 112 unsigned int lapic_timer_advance_ns = 0; 113 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 114 115 static bool backwards_tsc_observed = false; 116 117 #define KVM_NR_SHARED_MSRS 16 118 119 struct kvm_shared_msrs_global { 120 int nr; 121 u32 msrs[KVM_NR_SHARED_MSRS]; 122 }; 123 124 struct kvm_shared_msrs { 125 struct user_return_notifier urn; 126 bool registered; 127 struct kvm_shared_msr_values { 128 u64 host; 129 u64 curr; 130 } values[KVM_NR_SHARED_MSRS]; 131 }; 132 133 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 134 static struct kvm_shared_msrs __percpu *shared_msrs; 135 136 struct kvm_stats_debugfs_item debugfs_entries[] = { 137 { "pf_fixed", VCPU_STAT(pf_fixed) }, 138 { "pf_guest", VCPU_STAT(pf_guest) }, 139 { "tlb_flush", VCPU_STAT(tlb_flush) }, 140 { "invlpg", VCPU_STAT(invlpg) }, 141 { "exits", VCPU_STAT(exits) }, 142 { "io_exits", VCPU_STAT(io_exits) }, 143 { "mmio_exits", VCPU_STAT(mmio_exits) }, 144 { "signal_exits", VCPU_STAT(signal_exits) }, 145 { "irq_window", VCPU_STAT(irq_window_exits) }, 146 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 147 { "halt_exits", VCPU_STAT(halt_exits) }, 148 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 149 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 150 { "hypercalls", VCPU_STAT(hypercalls) }, 151 { "request_irq", VCPU_STAT(request_irq_exits) }, 152 { "irq_exits", VCPU_STAT(irq_exits) }, 153 { "host_state_reload", VCPU_STAT(host_state_reload) }, 154 { "efer_reload", VCPU_STAT(efer_reload) }, 155 { "fpu_reload", VCPU_STAT(fpu_reload) }, 156 { "insn_emulation", VCPU_STAT(insn_emulation) }, 157 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 158 { "irq_injections", VCPU_STAT(irq_injections) }, 159 { "nmi_injections", VCPU_STAT(nmi_injections) }, 160 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 161 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 162 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 163 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 164 { "mmu_flooded", VM_STAT(mmu_flooded) }, 165 { "mmu_recycled", VM_STAT(mmu_recycled) }, 166 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 167 { "mmu_unsync", VM_STAT(mmu_unsync) }, 168 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 169 { "largepages", VM_STAT(lpages) }, 170 { NULL } 171 }; 172 173 u64 __read_mostly host_xcr0; 174 175 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 176 177 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 178 { 179 int i; 180 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 181 vcpu->arch.apf.gfns[i] = ~0; 182 } 183 184 static void kvm_on_user_return(struct user_return_notifier *urn) 185 { 186 unsigned slot; 187 struct kvm_shared_msrs *locals 188 = container_of(urn, struct kvm_shared_msrs, urn); 189 struct kvm_shared_msr_values *values; 190 191 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 192 values = &locals->values[slot]; 193 if (values->host != values->curr) { 194 wrmsrl(shared_msrs_global.msrs[slot], values->host); 195 values->curr = values->host; 196 } 197 } 198 locals->registered = false; 199 user_return_notifier_unregister(urn); 200 } 201 202 static void shared_msr_update(unsigned slot, u32 msr) 203 { 204 u64 value; 205 unsigned int cpu = smp_processor_id(); 206 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 207 208 /* only read, and nobody should modify it at this time, 209 * so don't need lock */ 210 if (slot >= shared_msrs_global.nr) { 211 printk(KERN_ERR "kvm: invalid MSR slot!"); 212 return; 213 } 214 rdmsrl_safe(msr, &value); 215 smsr->values[slot].host = value; 216 smsr->values[slot].curr = value; 217 } 218 219 void kvm_define_shared_msr(unsigned slot, u32 msr) 220 { 221 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 222 if (slot >= shared_msrs_global.nr) 223 shared_msrs_global.nr = slot + 1; 224 shared_msrs_global.msrs[slot] = msr; 225 /* we need ensured the shared_msr_global have been updated */ 226 smp_wmb(); 227 } 228 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 229 230 static void kvm_shared_msr_cpu_online(void) 231 { 232 unsigned i; 233 234 for (i = 0; i < shared_msrs_global.nr; ++i) 235 shared_msr_update(i, shared_msrs_global.msrs[i]); 236 } 237 238 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 239 { 240 unsigned int cpu = smp_processor_id(); 241 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 242 int err; 243 244 if (((value ^ smsr->values[slot].curr) & mask) == 0) 245 return 0; 246 smsr->values[slot].curr = value; 247 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 248 if (err) 249 return 1; 250 251 if (!smsr->registered) { 252 smsr->urn.on_user_return = kvm_on_user_return; 253 user_return_notifier_register(&smsr->urn); 254 smsr->registered = true; 255 } 256 return 0; 257 } 258 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 259 260 static void drop_user_return_notifiers(void) 261 { 262 unsigned int cpu = smp_processor_id(); 263 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 264 265 if (smsr->registered) 266 kvm_on_user_return(&smsr->urn); 267 } 268 269 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 270 { 271 return vcpu->arch.apic_base; 272 } 273 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 274 275 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 276 { 277 u64 old_state = vcpu->arch.apic_base & 278 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 279 u64 new_state = msr_info->data & 280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 281 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 282 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); 283 284 if (!msr_info->host_initiated && 285 ((msr_info->data & reserved_bits) != 0 || 286 new_state == X2APIC_ENABLE || 287 (new_state == MSR_IA32_APICBASE_ENABLE && 288 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 289 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 290 old_state == 0))) 291 return 1; 292 293 kvm_lapic_set_base(vcpu, msr_info->data); 294 return 0; 295 } 296 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 297 298 asmlinkage __visible void kvm_spurious_fault(void) 299 { 300 /* Fault while not rebooting. We want the trace. */ 301 BUG(); 302 } 303 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 304 305 #define EXCPT_BENIGN 0 306 #define EXCPT_CONTRIBUTORY 1 307 #define EXCPT_PF 2 308 309 static int exception_class(int vector) 310 { 311 switch (vector) { 312 case PF_VECTOR: 313 return EXCPT_PF; 314 case DE_VECTOR: 315 case TS_VECTOR: 316 case NP_VECTOR: 317 case SS_VECTOR: 318 case GP_VECTOR: 319 return EXCPT_CONTRIBUTORY; 320 default: 321 break; 322 } 323 return EXCPT_BENIGN; 324 } 325 326 #define EXCPT_FAULT 0 327 #define EXCPT_TRAP 1 328 #define EXCPT_ABORT 2 329 #define EXCPT_INTERRUPT 3 330 331 static int exception_type(int vector) 332 { 333 unsigned int mask; 334 335 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 336 return EXCPT_INTERRUPT; 337 338 mask = 1 << vector; 339 340 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 341 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 342 return EXCPT_TRAP; 343 344 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 345 return EXCPT_ABORT; 346 347 /* Reserved exceptions will result in fault */ 348 return EXCPT_FAULT; 349 } 350 351 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 352 unsigned nr, bool has_error, u32 error_code, 353 bool reinject) 354 { 355 u32 prev_nr; 356 int class1, class2; 357 358 kvm_make_request(KVM_REQ_EVENT, vcpu); 359 360 if (!vcpu->arch.exception.pending) { 361 queue: 362 if (has_error && !is_protmode(vcpu)) 363 has_error = false; 364 vcpu->arch.exception.pending = true; 365 vcpu->arch.exception.has_error_code = has_error; 366 vcpu->arch.exception.nr = nr; 367 vcpu->arch.exception.error_code = error_code; 368 vcpu->arch.exception.reinject = reinject; 369 return; 370 } 371 372 /* to check exception */ 373 prev_nr = vcpu->arch.exception.nr; 374 if (prev_nr == DF_VECTOR) { 375 /* triple fault -> shutdown */ 376 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 377 return; 378 } 379 class1 = exception_class(prev_nr); 380 class2 = exception_class(nr); 381 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 382 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 383 /* generate double fault per SDM Table 5-5 */ 384 vcpu->arch.exception.pending = true; 385 vcpu->arch.exception.has_error_code = true; 386 vcpu->arch.exception.nr = DF_VECTOR; 387 vcpu->arch.exception.error_code = 0; 388 } else 389 /* replace previous exception with a new one in a hope 390 that instruction re-execution will regenerate lost 391 exception */ 392 goto queue; 393 } 394 395 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 396 { 397 kvm_multiple_exception(vcpu, nr, false, 0, false); 398 } 399 EXPORT_SYMBOL_GPL(kvm_queue_exception); 400 401 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 402 { 403 kvm_multiple_exception(vcpu, nr, false, 0, true); 404 } 405 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 406 407 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 408 { 409 if (err) 410 kvm_inject_gp(vcpu, 0); 411 else 412 kvm_x86_ops->skip_emulated_instruction(vcpu); 413 } 414 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 415 416 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 417 { 418 ++vcpu->stat.pf_guest; 419 vcpu->arch.cr2 = fault->address; 420 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 421 } 422 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 423 424 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 425 { 426 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 427 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 428 else 429 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 430 431 return fault->nested_page_fault; 432 } 433 434 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 435 { 436 atomic_inc(&vcpu->arch.nmi_queued); 437 kvm_make_request(KVM_REQ_NMI, vcpu); 438 } 439 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 440 441 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 442 { 443 kvm_multiple_exception(vcpu, nr, true, error_code, false); 444 } 445 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 446 447 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 448 { 449 kvm_multiple_exception(vcpu, nr, true, error_code, true); 450 } 451 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 452 453 /* 454 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 455 * a #GP and return false. 456 */ 457 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 458 { 459 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 460 return true; 461 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 462 return false; 463 } 464 EXPORT_SYMBOL_GPL(kvm_require_cpl); 465 466 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 467 { 468 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 469 return true; 470 471 kvm_queue_exception(vcpu, UD_VECTOR); 472 return false; 473 } 474 EXPORT_SYMBOL_GPL(kvm_require_dr); 475 476 /* 477 * This function will be used to read from the physical memory of the currently 478 * running guest. The difference to kvm_read_guest_page is that this function 479 * can read from guest physical or from the guest's guest physical memory. 480 */ 481 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 482 gfn_t ngfn, void *data, int offset, int len, 483 u32 access) 484 { 485 struct x86_exception exception; 486 gfn_t real_gfn; 487 gpa_t ngpa; 488 489 ngpa = gfn_to_gpa(ngfn); 490 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 491 if (real_gfn == UNMAPPED_GVA) 492 return -EFAULT; 493 494 real_gfn = gpa_to_gfn(real_gfn); 495 496 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len); 497 } 498 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 499 500 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 501 void *data, int offset, int len, u32 access) 502 { 503 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 504 data, offset, len, access); 505 } 506 507 /* 508 * Load the pae pdptrs. Return true is they are all valid. 509 */ 510 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 511 { 512 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 513 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 514 int i; 515 int ret; 516 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 517 518 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 519 offset * sizeof(u64), sizeof(pdpte), 520 PFERR_USER_MASK|PFERR_WRITE_MASK); 521 if (ret < 0) { 522 ret = 0; 523 goto out; 524 } 525 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 526 if (is_present_gpte(pdpte[i]) && 527 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { 528 ret = 0; 529 goto out; 530 } 531 } 532 ret = 1; 533 534 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 535 __set_bit(VCPU_EXREG_PDPTR, 536 (unsigned long *)&vcpu->arch.regs_avail); 537 __set_bit(VCPU_EXREG_PDPTR, 538 (unsigned long *)&vcpu->arch.regs_dirty); 539 out: 540 541 return ret; 542 } 543 EXPORT_SYMBOL_GPL(load_pdptrs); 544 545 static bool pdptrs_changed(struct kvm_vcpu *vcpu) 546 { 547 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 548 bool changed = true; 549 int offset; 550 gfn_t gfn; 551 int r; 552 553 if (is_long_mode(vcpu) || !is_pae(vcpu)) 554 return false; 555 556 if (!test_bit(VCPU_EXREG_PDPTR, 557 (unsigned long *)&vcpu->arch.regs_avail)) 558 return true; 559 560 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; 561 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); 562 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 563 PFERR_USER_MASK | PFERR_WRITE_MASK); 564 if (r < 0) 565 goto out; 566 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 567 out: 568 569 return changed; 570 } 571 572 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 573 { 574 unsigned long old_cr0 = kvm_read_cr0(vcpu); 575 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP | 576 X86_CR0_CD | X86_CR0_NW; 577 578 cr0 |= X86_CR0_ET; 579 580 #ifdef CONFIG_X86_64 581 if (cr0 & 0xffffffff00000000UL) 582 return 1; 583 #endif 584 585 cr0 &= ~CR0_RESERVED_BITS; 586 587 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 588 return 1; 589 590 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 591 return 1; 592 593 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 594 #ifdef CONFIG_X86_64 595 if ((vcpu->arch.efer & EFER_LME)) { 596 int cs_db, cs_l; 597 598 if (!is_pae(vcpu)) 599 return 1; 600 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 601 if (cs_l) 602 return 1; 603 } else 604 #endif 605 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 606 kvm_read_cr3(vcpu))) 607 return 1; 608 } 609 610 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 611 return 1; 612 613 kvm_x86_ops->set_cr0(vcpu, cr0); 614 615 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 616 kvm_clear_async_pf_completion_queue(vcpu); 617 kvm_async_pf_hash_reset(vcpu); 618 } 619 620 if ((cr0 ^ old_cr0) & update_bits) 621 kvm_mmu_reset_context(vcpu); 622 return 0; 623 } 624 EXPORT_SYMBOL_GPL(kvm_set_cr0); 625 626 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 627 { 628 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 629 } 630 EXPORT_SYMBOL_GPL(kvm_lmsw); 631 632 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 633 { 634 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 635 !vcpu->guest_xcr0_loaded) { 636 /* kvm_set_xcr() also depends on this */ 637 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 638 vcpu->guest_xcr0_loaded = 1; 639 } 640 } 641 642 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 643 { 644 if (vcpu->guest_xcr0_loaded) { 645 if (vcpu->arch.xcr0 != host_xcr0) 646 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 647 vcpu->guest_xcr0_loaded = 0; 648 } 649 } 650 651 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 652 { 653 u64 xcr0 = xcr; 654 u64 old_xcr0 = vcpu->arch.xcr0; 655 u64 valid_bits; 656 657 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 658 if (index != XCR_XFEATURE_ENABLED_MASK) 659 return 1; 660 if (!(xcr0 & XSTATE_FP)) 661 return 1; 662 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) 663 return 1; 664 665 /* 666 * Do not allow the guest to set bits that we do not support 667 * saving. However, xcr0 bit 0 is always set, even if the 668 * emulated CPU does not support XSAVE (see fx_init). 669 */ 670 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP; 671 if (xcr0 & ~valid_bits) 672 return 1; 673 674 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR))) 675 return 1; 676 677 if (xcr0 & XSTATE_AVX512) { 678 if (!(xcr0 & XSTATE_YMM)) 679 return 1; 680 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512) 681 return 1; 682 } 683 kvm_put_guest_xcr0(vcpu); 684 vcpu->arch.xcr0 = xcr0; 685 686 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK) 687 kvm_update_cpuid(vcpu); 688 return 0; 689 } 690 691 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 692 { 693 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 694 __kvm_set_xcr(vcpu, index, xcr)) { 695 kvm_inject_gp(vcpu, 0); 696 return 1; 697 } 698 return 0; 699 } 700 EXPORT_SYMBOL_GPL(kvm_set_xcr); 701 702 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 703 { 704 unsigned long old_cr4 = kvm_read_cr4(vcpu); 705 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 706 X86_CR4_SMEP | X86_CR4_SMAP; 707 708 if (cr4 & CR4_RESERVED_BITS) 709 return 1; 710 711 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) 712 return 1; 713 714 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) 715 return 1; 716 717 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) 718 return 1; 719 720 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) 721 return 1; 722 723 if (is_long_mode(vcpu)) { 724 if (!(cr4 & X86_CR4_PAE)) 725 return 1; 726 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 727 && ((cr4 ^ old_cr4) & pdptr_bits) 728 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 729 kvm_read_cr3(vcpu))) 730 return 1; 731 732 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 733 if (!guest_cpuid_has_pcid(vcpu)) 734 return 1; 735 736 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 737 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 738 return 1; 739 } 740 741 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 742 return 1; 743 744 if (((cr4 ^ old_cr4) & pdptr_bits) || 745 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 746 kvm_mmu_reset_context(vcpu); 747 748 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) 749 kvm_update_cpuid(vcpu); 750 751 return 0; 752 } 753 EXPORT_SYMBOL_GPL(kvm_set_cr4); 754 755 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 756 { 757 #ifdef CONFIG_X86_64 758 cr3 &= ~CR3_PCID_INVD; 759 #endif 760 761 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 762 kvm_mmu_sync_roots(vcpu); 763 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 764 return 0; 765 } 766 767 if (is_long_mode(vcpu)) { 768 if (cr3 & CR3_L_MODE_RESERVED_BITS) 769 return 1; 770 } else if (is_pae(vcpu) && is_paging(vcpu) && 771 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 772 return 1; 773 774 vcpu->arch.cr3 = cr3; 775 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 776 kvm_mmu_new_cr3(vcpu); 777 return 0; 778 } 779 EXPORT_SYMBOL_GPL(kvm_set_cr3); 780 781 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 782 { 783 if (cr8 & CR8_RESERVED_BITS) 784 return 1; 785 if (irqchip_in_kernel(vcpu->kvm)) 786 kvm_lapic_set_tpr(vcpu, cr8); 787 else 788 vcpu->arch.cr8 = cr8; 789 return 0; 790 } 791 EXPORT_SYMBOL_GPL(kvm_set_cr8); 792 793 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 794 { 795 if (irqchip_in_kernel(vcpu->kvm)) 796 return kvm_lapic_get_cr8(vcpu); 797 else 798 return vcpu->arch.cr8; 799 } 800 EXPORT_SYMBOL_GPL(kvm_get_cr8); 801 802 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 803 { 804 int i; 805 806 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 807 for (i = 0; i < KVM_NR_DB_REGS; i++) 808 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 809 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 810 } 811 } 812 813 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 814 { 815 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 816 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 817 } 818 819 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 820 { 821 unsigned long dr7; 822 823 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 824 dr7 = vcpu->arch.guest_debug_dr7; 825 else 826 dr7 = vcpu->arch.dr7; 827 kvm_x86_ops->set_dr7(vcpu, dr7); 828 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 829 if (dr7 & DR7_BP_EN_MASK) 830 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 831 } 832 833 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 834 { 835 u64 fixed = DR6_FIXED_1; 836 837 if (!guest_cpuid_has_rtm(vcpu)) 838 fixed |= DR6_RTM; 839 return fixed; 840 } 841 842 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 843 { 844 switch (dr) { 845 case 0 ... 3: 846 vcpu->arch.db[dr] = val; 847 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 848 vcpu->arch.eff_db[dr] = val; 849 break; 850 case 4: 851 /* fall through */ 852 case 6: 853 if (val & 0xffffffff00000000ULL) 854 return -1; /* #GP */ 855 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 856 kvm_update_dr6(vcpu); 857 break; 858 case 5: 859 /* fall through */ 860 default: /* 7 */ 861 if (val & 0xffffffff00000000ULL) 862 return -1; /* #GP */ 863 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 864 kvm_update_dr7(vcpu); 865 break; 866 } 867 868 return 0; 869 } 870 871 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 872 { 873 if (__kvm_set_dr(vcpu, dr, val)) { 874 kvm_inject_gp(vcpu, 0); 875 return 1; 876 } 877 return 0; 878 } 879 EXPORT_SYMBOL_GPL(kvm_set_dr); 880 881 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 882 { 883 switch (dr) { 884 case 0 ... 3: 885 *val = vcpu->arch.db[dr]; 886 break; 887 case 4: 888 /* fall through */ 889 case 6: 890 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 891 *val = vcpu->arch.dr6; 892 else 893 *val = kvm_x86_ops->get_dr6(vcpu); 894 break; 895 case 5: 896 /* fall through */ 897 default: /* 7 */ 898 *val = vcpu->arch.dr7; 899 break; 900 } 901 return 0; 902 } 903 EXPORT_SYMBOL_GPL(kvm_get_dr); 904 905 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 906 { 907 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 908 u64 data; 909 int err; 910 911 err = kvm_pmu_read_pmc(vcpu, ecx, &data); 912 if (err) 913 return err; 914 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 915 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 916 return err; 917 } 918 EXPORT_SYMBOL_GPL(kvm_rdpmc); 919 920 /* 921 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 922 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 923 * 924 * This list is modified at module load time to reflect the 925 * capabilities of the host cpu. This capabilities test skips MSRs that are 926 * kvm-specific. Those are put in the beginning of the list. 927 */ 928 929 #define KVM_SAVE_MSRS_BEGIN 12 930 static u32 msrs_to_save[] = { 931 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 932 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 933 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 934 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 935 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 936 MSR_KVM_PV_EOI_EN, 937 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 938 MSR_STAR, 939 #ifdef CONFIG_X86_64 940 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 941 #endif 942 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 943 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS 944 }; 945 946 static unsigned num_msrs_to_save; 947 948 static const u32 emulated_msrs[] = { 949 MSR_IA32_TSC_ADJUST, 950 MSR_IA32_TSCDEADLINE, 951 MSR_IA32_MISC_ENABLE, 952 MSR_IA32_MCG_STATUS, 953 MSR_IA32_MCG_CTL, 954 }; 955 956 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 957 { 958 if (efer & efer_reserved_bits) 959 return false; 960 961 if (efer & EFER_FFXSR) { 962 struct kvm_cpuid_entry2 *feat; 963 964 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 965 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) 966 return false; 967 } 968 969 if (efer & EFER_SVME) { 970 struct kvm_cpuid_entry2 *feat; 971 972 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 973 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) 974 return false; 975 } 976 977 return true; 978 } 979 EXPORT_SYMBOL_GPL(kvm_valid_efer); 980 981 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 982 { 983 u64 old_efer = vcpu->arch.efer; 984 985 if (!kvm_valid_efer(vcpu, efer)) 986 return 1; 987 988 if (is_paging(vcpu) 989 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 990 return 1; 991 992 efer &= ~EFER_LMA; 993 efer |= vcpu->arch.efer & EFER_LMA; 994 995 kvm_x86_ops->set_efer(vcpu, efer); 996 997 /* Update reserved bits */ 998 if ((efer ^ old_efer) & EFER_NX) 999 kvm_mmu_reset_context(vcpu); 1000 1001 return 0; 1002 } 1003 1004 void kvm_enable_efer_bits(u64 mask) 1005 { 1006 efer_reserved_bits &= ~mask; 1007 } 1008 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1009 1010 /* 1011 * Writes msr value into into the appropriate "register". 1012 * Returns 0 on success, non-0 otherwise. 1013 * Assumes vcpu_load() was already called. 1014 */ 1015 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1016 { 1017 switch (msr->index) { 1018 case MSR_FS_BASE: 1019 case MSR_GS_BASE: 1020 case MSR_KERNEL_GS_BASE: 1021 case MSR_CSTAR: 1022 case MSR_LSTAR: 1023 if (is_noncanonical_address(msr->data)) 1024 return 1; 1025 break; 1026 case MSR_IA32_SYSENTER_EIP: 1027 case MSR_IA32_SYSENTER_ESP: 1028 /* 1029 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1030 * non-canonical address is written on Intel but not on 1031 * AMD (which ignores the top 32-bits, because it does 1032 * not implement 64-bit SYSENTER). 1033 * 1034 * 64-bit code should hence be able to write a non-canonical 1035 * value on AMD. Making the address canonical ensures that 1036 * vmentry does not fail on Intel after writing a non-canonical 1037 * value, and that something deterministic happens if the guest 1038 * invokes 64-bit SYSENTER. 1039 */ 1040 msr->data = get_canonical(msr->data); 1041 } 1042 return kvm_x86_ops->set_msr(vcpu, msr); 1043 } 1044 EXPORT_SYMBOL_GPL(kvm_set_msr); 1045 1046 /* 1047 * Adapt set_msr() to msr_io()'s calling convention 1048 */ 1049 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1050 { 1051 struct msr_data msr; 1052 1053 msr.data = *data; 1054 msr.index = index; 1055 msr.host_initiated = true; 1056 return kvm_set_msr(vcpu, &msr); 1057 } 1058 1059 #ifdef CONFIG_X86_64 1060 struct pvclock_gtod_data { 1061 seqcount_t seq; 1062 1063 struct { /* extract of a clocksource struct */ 1064 int vclock_mode; 1065 cycle_t cycle_last; 1066 cycle_t mask; 1067 u32 mult; 1068 u32 shift; 1069 } clock; 1070 1071 u64 boot_ns; 1072 u64 nsec_base; 1073 }; 1074 1075 static struct pvclock_gtod_data pvclock_gtod_data; 1076 1077 static void update_pvclock_gtod(struct timekeeper *tk) 1078 { 1079 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1080 u64 boot_ns; 1081 1082 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1083 1084 write_seqcount_begin(&vdata->seq); 1085 1086 /* copy pvclock gtod data */ 1087 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1088 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1089 vdata->clock.mask = tk->tkr_mono.mask; 1090 vdata->clock.mult = tk->tkr_mono.mult; 1091 vdata->clock.shift = tk->tkr_mono.shift; 1092 1093 vdata->boot_ns = boot_ns; 1094 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1095 1096 write_seqcount_end(&vdata->seq); 1097 } 1098 #endif 1099 1100 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1101 { 1102 /* 1103 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1104 * vcpu_enter_guest. This function is only called from 1105 * the physical CPU that is running vcpu. 1106 */ 1107 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1108 } 1109 1110 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1111 { 1112 int version; 1113 int r; 1114 struct pvclock_wall_clock wc; 1115 struct timespec boot; 1116 1117 if (!wall_clock) 1118 return; 1119 1120 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1121 if (r) 1122 return; 1123 1124 if (version & 1) 1125 ++version; /* first time write, random junk */ 1126 1127 ++version; 1128 1129 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1130 1131 /* 1132 * The guest calculates current wall clock time by adding 1133 * system time (updated by kvm_guest_time_update below) to the 1134 * wall clock specified here. guest system time equals host 1135 * system time for us, thus we must fill in host boot time here. 1136 */ 1137 getboottime(&boot); 1138 1139 if (kvm->arch.kvmclock_offset) { 1140 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); 1141 boot = timespec_sub(boot, ts); 1142 } 1143 wc.sec = boot.tv_sec; 1144 wc.nsec = boot.tv_nsec; 1145 wc.version = version; 1146 1147 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1148 1149 version++; 1150 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1151 } 1152 1153 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1154 { 1155 uint32_t quotient, remainder; 1156 1157 /* Don't try to replace with do_div(), this one calculates 1158 * "(dividend << 32) / divisor" */ 1159 __asm__ ( "divl %4" 1160 : "=a" (quotient), "=d" (remainder) 1161 : "0" (0), "1" (dividend), "r" (divisor) ); 1162 return quotient; 1163 } 1164 1165 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, 1166 s8 *pshift, u32 *pmultiplier) 1167 { 1168 uint64_t scaled64; 1169 int32_t shift = 0; 1170 uint64_t tps64; 1171 uint32_t tps32; 1172 1173 tps64 = base_khz * 1000LL; 1174 scaled64 = scaled_khz * 1000LL; 1175 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1176 tps64 >>= 1; 1177 shift--; 1178 } 1179 1180 tps32 = (uint32_t)tps64; 1181 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1182 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1183 scaled64 >>= 1; 1184 else 1185 tps32 <<= 1; 1186 shift++; 1187 } 1188 1189 *pshift = shift; 1190 *pmultiplier = div_frac(scaled64, tps32); 1191 1192 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", 1193 __func__, base_khz, scaled_khz, shift, *pmultiplier); 1194 } 1195 1196 static inline u64 get_kernel_ns(void) 1197 { 1198 return ktime_get_boot_ns(); 1199 } 1200 1201 #ifdef CONFIG_X86_64 1202 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1203 #endif 1204 1205 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1206 static unsigned long max_tsc_khz; 1207 1208 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) 1209 { 1210 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, 1211 vcpu->arch.virtual_tsc_shift); 1212 } 1213 1214 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1215 { 1216 u64 v = (u64)khz * (1000000 + ppm); 1217 do_div(v, 1000000); 1218 return v; 1219 } 1220 1221 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) 1222 { 1223 u32 thresh_lo, thresh_hi; 1224 int use_scaling = 0; 1225 1226 /* tsc_khz can be zero if TSC calibration fails */ 1227 if (this_tsc_khz == 0) 1228 return; 1229 1230 /* Compute a scale to convert nanoseconds in TSC cycles */ 1231 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, 1232 &vcpu->arch.virtual_tsc_shift, 1233 &vcpu->arch.virtual_tsc_mult); 1234 vcpu->arch.virtual_tsc_khz = this_tsc_khz; 1235 1236 /* 1237 * Compute the variation in TSC rate which is acceptable 1238 * within the range of tolerance and decide if the 1239 * rate being applied is within that bounds of the hardware 1240 * rate. If so, no scaling or compensation need be done. 1241 */ 1242 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1243 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1244 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { 1245 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); 1246 use_scaling = 1; 1247 } 1248 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling); 1249 } 1250 1251 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1252 { 1253 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1254 vcpu->arch.virtual_tsc_mult, 1255 vcpu->arch.virtual_tsc_shift); 1256 tsc += vcpu->arch.this_tsc_write; 1257 return tsc; 1258 } 1259 1260 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1261 { 1262 #ifdef CONFIG_X86_64 1263 bool vcpus_matched; 1264 struct kvm_arch *ka = &vcpu->kvm->arch; 1265 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1266 1267 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1268 atomic_read(&vcpu->kvm->online_vcpus)); 1269 1270 /* 1271 * Once the masterclock is enabled, always perform request in 1272 * order to update it. 1273 * 1274 * In order to enable masterclock, the host clocksource must be TSC 1275 * and the vcpus need to have matched TSCs. When that happens, 1276 * perform request to enable masterclock. 1277 */ 1278 if (ka->use_master_clock || 1279 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) 1280 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1281 1282 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1283 atomic_read(&vcpu->kvm->online_vcpus), 1284 ka->use_master_clock, gtod->clock.vclock_mode); 1285 #endif 1286 } 1287 1288 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1289 { 1290 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); 1291 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1292 } 1293 1294 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1295 { 1296 struct kvm *kvm = vcpu->kvm; 1297 u64 offset, ns, elapsed; 1298 unsigned long flags; 1299 s64 usdiff; 1300 bool matched; 1301 bool already_matched; 1302 u64 data = msr->data; 1303 1304 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1305 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); 1306 ns = get_kernel_ns(); 1307 elapsed = ns - kvm->arch.last_tsc_nsec; 1308 1309 if (vcpu->arch.virtual_tsc_khz) { 1310 int faulted = 0; 1311 1312 /* n.b - signed multiplication and division required */ 1313 usdiff = data - kvm->arch.last_tsc_write; 1314 #ifdef CONFIG_X86_64 1315 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; 1316 #else 1317 /* do_div() only does unsigned */ 1318 asm("1: idivl %[divisor]\n" 1319 "2: xor %%edx, %%edx\n" 1320 " movl $0, %[faulted]\n" 1321 "3:\n" 1322 ".section .fixup,\"ax\"\n" 1323 "4: movl $1, %[faulted]\n" 1324 " jmp 3b\n" 1325 ".previous\n" 1326 1327 _ASM_EXTABLE(1b, 4b) 1328 1329 : "=A"(usdiff), [faulted] "=r" (faulted) 1330 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); 1331 1332 #endif 1333 do_div(elapsed, 1000); 1334 usdiff -= elapsed; 1335 if (usdiff < 0) 1336 usdiff = -usdiff; 1337 1338 /* idivl overflow => difference is larger than USEC_PER_SEC */ 1339 if (faulted) 1340 usdiff = USEC_PER_SEC; 1341 } else 1342 usdiff = USEC_PER_SEC; /* disable TSC match window below */ 1343 1344 /* 1345 * Special case: TSC write with a small delta (1 second) of virtual 1346 * cycle time against real time is interpreted as an attempt to 1347 * synchronize the CPU. 1348 * 1349 * For a reliable TSC, we can match TSC offsets, and for an unstable 1350 * TSC, we add elapsed time in this computation. We could let the 1351 * compensation code attempt to catch up if we fall behind, but 1352 * it's better to try to match offsets from the beginning. 1353 */ 1354 if (usdiff < USEC_PER_SEC && 1355 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1356 if (!check_tsc_unstable()) { 1357 offset = kvm->arch.cur_tsc_offset; 1358 pr_debug("kvm: matched tsc offset for %llu\n", data); 1359 } else { 1360 u64 delta = nsec_to_cycles(vcpu, elapsed); 1361 data += delta; 1362 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); 1363 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1364 } 1365 matched = true; 1366 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1367 } else { 1368 /* 1369 * We split periods of matched TSC writes into generations. 1370 * For each generation, we track the original measured 1371 * nanosecond time, offset, and write, so if TSCs are in 1372 * sync, we can match exact offset, and if not, we can match 1373 * exact software computation in compute_guest_tsc() 1374 * 1375 * These values are tracked in kvm->arch.cur_xxx variables. 1376 */ 1377 kvm->arch.cur_tsc_generation++; 1378 kvm->arch.cur_tsc_nsec = ns; 1379 kvm->arch.cur_tsc_write = data; 1380 kvm->arch.cur_tsc_offset = offset; 1381 matched = false; 1382 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1383 kvm->arch.cur_tsc_generation, data); 1384 } 1385 1386 /* 1387 * We also track th most recent recorded KHZ, write and time to 1388 * allow the matching interval to be extended at each write. 1389 */ 1390 kvm->arch.last_tsc_nsec = ns; 1391 kvm->arch.last_tsc_write = data; 1392 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1393 1394 vcpu->arch.last_guest_tsc = data; 1395 1396 /* Keep track of which generation this VCPU has synchronized to */ 1397 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1398 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1399 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1400 1401 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) 1402 update_ia32_tsc_adjust_msr(vcpu, offset); 1403 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1404 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1405 1406 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1407 if (!matched) { 1408 kvm->arch.nr_vcpus_matched_tsc = 0; 1409 } else if (!already_matched) { 1410 kvm->arch.nr_vcpus_matched_tsc++; 1411 } 1412 1413 kvm_track_tsc_matching(vcpu); 1414 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1415 } 1416 1417 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1418 1419 #ifdef CONFIG_X86_64 1420 1421 static cycle_t read_tsc(void) 1422 { 1423 cycle_t ret; 1424 u64 last; 1425 1426 /* 1427 * Empirically, a fence (of type that depends on the CPU) 1428 * before rdtsc is enough to ensure that rdtsc is ordered 1429 * with respect to loads. The various CPU manuals are unclear 1430 * as to whether rdtsc can be reordered with later loads, 1431 * but no one has ever seen it happen. 1432 */ 1433 rdtsc_barrier(); 1434 ret = (cycle_t)vget_cycles(); 1435 1436 last = pvclock_gtod_data.clock.cycle_last; 1437 1438 if (likely(ret >= last)) 1439 return ret; 1440 1441 /* 1442 * GCC likes to generate cmov here, but this branch is extremely 1443 * predictable (it's just a funciton of time and the likely is 1444 * very likely) and there's a data dependence, so force GCC 1445 * to generate a branch instead. I don't barrier() because 1446 * we don't actually need a barrier, and if this function 1447 * ever gets inlined it will generate worse code. 1448 */ 1449 asm volatile (""); 1450 return last; 1451 } 1452 1453 static inline u64 vgettsc(cycle_t *cycle_now) 1454 { 1455 long v; 1456 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1457 1458 *cycle_now = read_tsc(); 1459 1460 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; 1461 return v * gtod->clock.mult; 1462 } 1463 1464 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now) 1465 { 1466 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1467 unsigned long seq; 1468 int mode; 1469 u64 ns; 1470 1471 do { 1472 seq = read_seqcount_begin(>od->seq); 1473 mode = gtod->clock.vclock_mode; 1474 ns = gtod->nsec_base; 1475 ns += vgettsc(cycle_now); 1476 ns >>= gtod->clock.shift; 1477 ns += gtod->boot_ns; 1478 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1479 *t = ns; 1480 1481 return mode; 1482 } 1483 1484 /* returns true if host is using tsc clocksource */ 1485 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) 1486 { 1487 /* checked again under seqlock below */ 1488 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) 1489 return false; 1490 1491 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; 1492 } 1493 #endif 1494 1495 /* 1496 * 1497 * Assuming a stable TSC across physical CPUS, and a stable TSC 1498 * across virtual CPUs, the following condition is possible. 1499 * Each numbered line represents an event visible to both 1500 * CPUs at the next numbered event. 1501 * 1502 * "timespecX" represents host monotonic time. "tscX" represents 1503 * RDTSC value. 1504 * 1505 * VCPU0 on CPU0 | VCPU1 on CPU1 1506 * 1507 * 1. read timespec0,tsc0 1508 * 2. | timespec1 = timespec0 + N 1509 * | tsc1 = tsc0 + M 1510 * 3. transition to guest | transition to guest 1511 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1512 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1513 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1514 * 1515 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1516 * 1517 * - ret0 < ret1 1518 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1519 * ... 1520 * - 0 < N - M => M < N 1521 * 1522 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1523 * always the case (the difference between two distinct xtime instances 1524 * might be smaller then the difference between corresponding TSC reads, 1525 * when updating guest vcpus pvclock areas). 1526 * 1527 * To avoid that problem, do not allow visibility of distinct 1528 * system_timestamp/tsc_timestamp values simultaneously: use a master 1529 * copy of host monotonic time values. Update that master copy 1530 * in lockstep. 1531 * 1532 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1533 * 1534 */ 1535 1536 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1537 { 1538 #ifdef CONFIG_X86_64 1539 struct kvm_arch *ka = &kvm->arch; 1540 int vclock_mode; 1541 bool host_tsc_clocksource, vcpus_matched; 1542 1543 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1544 atomic_read(&kvm->online_vcpus)); 1545 1546 /* 1547 * If the host uses TSC clock, then passthrough TSC as stable 1548 * to the guest. 1549 */ 1550 host_tsc_clocksource = kvm_get_time_and_clockread( 1551 &ka->master_kernel_ns, 1552 &ka->master_cycle_now); 1553 1554 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 1555 && !backwards_tsc_observed 1556 && !ka->boot_vcpu_runs_old_kvmclock; 1557 1558 if (ka->use_master_clock) 1559 atomic_set(&kvm_guest_has_master_clock, 1); 1560 1561 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1562 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1563 vcpus_matched); 1564 #endif 1565 } 1566 1567 static void kvm_gen_update_masterclock(struct kvm *kvm) 1568 { 1569 #ifdef CONFIG_X86_64 1570 int i; 1571 struct kvm_vcpu *vcpu; 1572 struct kvm_arch *ka = &kvm->arch; 1573 1574 spin_lock(&ka->pvclock_gtod_sync_lock); 1575 kvm_make_mclock_inprogress_request(kvm); 1576 /* no guest entries from this point */ 1577 pvclock_update_vm_gtod_copy(kvm); 1578 1579 kvm_for_each_vcpu(i, vcpu, kvm) 1580 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1581 1582 /* guest entries allowed */ 1583 kvm_for_each_vcpu(i, vcpu, kvm) 1584 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); 1585 1586 spin_unlock(&ka->pvclock_gtod_sync_lock); 1587 #endif 1588 } 1589 1590 static int kvm_guest_time_update(struct kvm_vcpu *v) 1591 { 1592 unsigned long flags, this_tsc_khz; 1593 struct kvm_vcpu_arch *vcpu = &v->arch; 1594 struct kvm_arch *ka = &v->kvm->arch; 1595 s64 kernel_ns; 1596 u64 tsc_timestamp, host_tsc; 1597 struct pvclock_vcpu_time_info guest_hv_clock; 1598 u8 pvclock_flags; 1599 bool use_master_clock; 1600 1601 kernel_ns = 0; 1602 host_tsc = 0; 1603 1604 /* 1605 * If the host uses TSC clock, then passthrough TSC as stable 1606 * to the guest. 1607 */ 1608 spin_lock(&ka->pvclock_gtod_sync_lock); 1609 use_master_clock = ka->use_master_clock; 1610 if (use_master_clock) { 1611 host_tsc = ka->master_cycle_now; 1612 kernel_ns = ka->master_kernel_ns; 1613 } 1614 spin_unlock(&ka->pvclock_gtod_sync_lock); 1615 1616 /* Keep irq disabled to prevent changes to the clock */ 1617 local_irq_save(flags); 1618 this_tsc_khz = __this_cpu_read(cpu_tsc_khz); 1619 if (unlikely(this_tsc_khz == 0)) { 1620 local_irq_restore(flags); 1621 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1622 return 1; 1623 } 1624 if (!use_master_clock) { 1625 host_tsc = native_read_tsc(); 1626 kernel_ns = get_kernel_ns(); 1627 } 1628 1629 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc); 1630 1631 /* 1632 * We may have to catch up the TSC to match elapsed wall clock 1633 * time for two reasons, even if kvmclock is used. 1634 * 1) CPU could have been running below the maximum TSC rate 1635 * 2) Broken TSC compensation resets the base at each VCPU 1636 * entry to avoid unknown leaps of TSC even when running 1637 * again on the same CPU. This may cause apparent elapsed 1638 * time to disappear, and the guest to stand still or run 1639 * very slowly. 1640 */ 1641 if (vcpu->tsc_catchup) { 1642 u64 tsc = compute_guest_tsc(v, kernel_ns); 1643 if (tsc > tsc_timestamp) { 1644 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 1645 tsc_timestamp = tsc; 1646 } 1647 } 1648 1649 local_irq_restore(flags); 1650 1651 if (!vcpu->pv_time_enabled) 1652 return 0; 1653 1654 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { 1655 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz, 1656 &vcpu->hv_clock.tsc_shift, 1657 &vcpu->hv_clock.tsc_to_system_mul); 1658 vcpu->hw_tsc_khz = this_tsc_khz; 1659 } 1660 1661 /* With all the info we got, fill in the values */ 1662 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 1663 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 1664 vcpu->last_guest_tsc = tsc_timestamp; 1665 1666 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1667 &guest_hv_clock, sizeof(guest_hv_clock)))) 1668 return 0; 1669 1670 /* This VCPU is paused, but it's legal for a guest to read another 1671 * VCPU's kvmclock, so we really have to follow the specification where 1672 * it says that version is odd if data is being modified, and even after 1673 * it is consistent. 1674 * 1675 * Version field updates must be kept separate. This is because 1676 * kvm_write_guest_cached might use a "rep movs" instruction, and 1677 * writes within a string instruction are weakly ordered. So there 1678 * are three writes overall. 1679 * 1680 * As a small optimization, only write the version field in the first 1681 * and third write. The vcpu->pv_time cache is still valid, because the 1682 * version field is the first in the struct. 1683 */ 1684 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 1685 1686 vcpu->hv_clock.version = guest_hv_clock.version + 1; 1687 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1688 &vcpu->hv_clock, 1689 sizeof(vcpu->hv_clock.version)); 1690 1691 smp_wmb(); 1692 1693 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1694 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1695 1696 if (vcpu->pvclock_set_guest_stopped_request) { 1697 pvclock_flags |= PVCLOCK_GUEST_STOPPED; 1698 vcpu->pvclock_set_guest_stopped_request = false; 1699 } 1700 1701 /* If the host uses TSC clocksource, then it is stable */ 1702 if (use_master_clock) 1703 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 1704 1705 vcpu->hv_clock.flags = pvclock_flags; 1706 1707 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 1708 1709 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1710 &vcpu->hv_clock, 1711 sizeof(vcpu->hv_clock)); 1712 1713 smp_wmb(); 1714 1715 vcpu->hv_clock.version++; 1716 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1717 &vcpu->hv_clock, 1718 sizeof(vcpu->hv_clock.version)); 1719 return 0; 1720 } 1721 1722 /* 1723 * kvmclock updates which are isolated to a given vcpu, such as 1724 * vcpu->cpu migration, should not allow system_timestamp from 1725 * the rest of the vcpus to remain static. Otherwise ntp frequency 1726 * correction applies to one vcpu's system_timestamp but not 1727 * the others. 1728 * 1729 * So in those cases, request a kvmclock update for all vcpus. 1730 * We need to rate-limit these requests though, as they can 1731 * considerably slow guests that have a large number of vcpus. 1732 * The time for a remote vcpu to update its kvmclock is bound 1733 * by the delay we use to rate-limit the updates. 1734 */ 1735 1736 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 1737 1738 static void kvmclock_update_fn(struct work_struct *work) 1739 { 1740 int i; 1741 struct delayed_work *dwork = to_delayed_work(work); 1742 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1743 kvmclock_update_work); 1744 struct kvm *kvm = container_of(ka, struct kvm, arch); 1745 struct kvm_vcpu *vcpu; 1746 1747 kvm_for_each_vcpu(i, vcpu, kvm) { 1748 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1749 kvm_vcpu_kick(vcpu); 1750 } 1751 } 1752 1753 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 1754 { 1755 struct kvm *kvm = v->kvm; 1756 1757 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1758 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 1759 KVMCLOCK_UPDATE_DELAY); 1760 } 1761 1762 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 1763 1764 static void kvmclock_sync_fn(struct work_struct *work) 1765 { 1766 struct delayed_work *dwork = to_delayed_work(work); 1767 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1768 kvmclock_sync_work); 1769 struct kvm *kvm = container_of(ka, struct kvm, arch); 1770 1771 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 1772 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 1773 KVMCLOCK_SYNC_PERIOD); 1774 } 1775 1776 static bool msr_mtrr_valid(unsigned msr) 1777 { 1778 switch (msr) { 1779 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: 1780 case MSR_MTRRfix64K_00000: 1781 case MSR_MTRRfix16K_80000: 1782 case MSR_MTRRfix16K_A0000: 1783 case MSR_MTRRfix4K_C0000: 1784 case MSR_MTRRfix4K_C8000: 1785 case MSR_MTRRfix4K_D0000: 1786 case MSR_MTRRfix4K_D8000: 1787 case MSR_MTRRfix4K_E0000: 1788 case MSR_MTRRfix4K_E8000: 1789 case MSR_MTRRfix4K_F0000: 1790 case MSR_MTRRfix4K_F8000: 1791 case MSR_MTRRdefType: 1792 case MSR_IA32_CR_PAT: 1793 return true; 1794 case 0x2f8: 1795 return true; 1796 } 1797 return false; 1798 } 1799 1800 static bool valid_pat_type(unsigned t) 1801 { 1802 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ 1803 } 1804 1805 static bool valid_mtrr_type(unsigned t) 1806 { 1807 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ 1808 } 1809 1810 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1811 { 1812 int i; 1813 u64 mask; 1814 1815 if (!msr_mtrr_valid(msr)) 1816 return false; 1817 1818 if (msr == MSR_IA32_CR_PAT) { 1819 for (i = 0; i < 8; i++) 1820 if (!valid_pat_type((data >> (i * 8)) & 0xff)) 1821 return false; 1822 return true; 1823 } else if (msr == MSR_MTRRdefType) { 1824 if (data & ~0xcff) 1825 return false; 1826 return valid_mtrr_type(data & 0xff); 1827 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { 1828 for (i = 0; i < 8 ; i++) 1829 if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) 1830 return false; 1831 return true; 1832 } 1833 1834 /* variable MTRRs */ 1835 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR)); 1836 1837 mask = (~0ULL) << cpuid_maxphyaddr(vcpu); 1838 if ((msr & 1) == 0) { 1839 /* MTRR base */ 1840 if (!valid_mtrr_type(data & 0xff)) 1841 return false; 1842 mask |= 0xf00; 1843 } else 1844 /* MTRR mask */ 1845 mask |= 0x7ff; 1846 if (data & mask) { 1847 kvm_inject_gp(vcpu, 0); 1848 return false; 1849 } 1850 1851 return true; 1852 } 1853 EXPORT_SYMBOL_GPL(kvm_mtrr_valid); 1854 1855 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1856 { 1857 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; 1858 1859 if (!kvm_mtrr_valid(vcpu, msr, data)) 1860 return 1; 1861 1862 if (msr == MSR_MTRRdefType) { 1863 vcpu->arch.mtrr_state.def_type = data; 1864 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; 1865 } else if (msr == MSR_MTRRfix64K_00000) 1866 p[0] = data; 1867 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) 1868 p[1 + msr - MSR_MTRRfix16K_80000] = data; 1869 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) 1870 p[3 + msr - MSR_MTRRfix4K_C0000] = data; 1871 else if (msr == MSR_IA32_CR_PAT) 1872 vcpu->arch.pat = data; 1873 else { /* Variable MTRRs */ 1874 int idx, is_mtrr_mask; 1875 u64 *pt; 1876 1877 idx = (msr - 0x200) / 2; 1878 is_mtrr_mask = msr - 0x200 - 2 * idx; 1879 if (!is_mtrr_mask) 1880 pt = 1881 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; 1882 else 1883 pt = 1884 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; 1885 *pt = data; 1886 } 1887 1888 kvm_mmu_reset_context(vcpu); 1889 return 0; 1890 } 1891 1892 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1893 { 1894 u64 mcg_cap = vcpu->arch.mcg_cap; 1895 unsigned bank_num = mcg_cap & 0xff; 1896 1897 switch (msr) { 1898 case MSR_IA32_MCG_STATUS: 1899 vcpu->arch.mcg_status = data; 1900 break; 1901 case MSR_IA32_MCG_CTL: 1902 if (!(mcg_cap & MCG_CTL_P)) 1903 return 1; 1904 if (data != 0 && data != ~(u64)0) 1905 return -1; 1906 vcpu->arch.mcg_ctl = data; 1907 break; 1908 default: 1909 if (msr >= MSR_IA32_MC0_CTL && 1910 msr < MSR_IA32_MCx_CTL(bank_num)) { 1911 u32 offset = msr - MSR_IA32_MC0_CTL; 1912 /* only 0 or all 1s can be written to IA32_MCi_CTL 1913 * some Linux kernels though clear bit 10 in bank 4 to 1914 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 1915 * this to avoid an uncatched #GP in the guest 1916 */ 1917 if ((offset & 0x3) == 0 && 1918 data != 0 && (data | (1 << 10)) != ~(u64)0) 1919 return -1; 1920 vcpu->arch.mce_banks[offset] = data; 1921 break; 1922 } 1923 return 1; 1924 } 1925 return 0; 1926 } 1927 1928 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 1929 { 1930 struct kvm *kvm = vcpu->kvm; 1931 int lm = is_long_mode(vcpu); 1932 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 1933 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 1934 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 1935 : kvm->arch.xen_hvm_config.blob_size_32; 1936 u32 page_num = data & ~PAGE_MASK; 1937 u64 page_addr = data & PAGE_MASK; 1938 u8 *page; 1939 int r; 1940 1941 r = -E2BIG; 1942 if (page_num >= blob_size) 1943 goto out; 1944 r = -ENOMEM; 1945 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 1946 if (IS_ERR(page)) { 1947 r = PTR_ERR(page); 1948 goto out; 1949 } 1950 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) 1951 goto out_free; 1952 r = 0; 1953 out_free: 1954 kfree(page); 1955 out: 1956 return r; 1957 } 1958 1959 static bool kvm_hv_hypercall_enabled(struct kvm *kvm) 1960 { 1961 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; 1962 } 1963 1964 static bool kvm_hv_msr_partition_wide(u32 msr) 1965 { 1966 bool r = false; 1967 switch (msr) { 1968 case HV_X64_MSR_GUEST_OS_ID: 1969 case HV_X64_MSR_HYPERCALL: 1970 case HV_X64_MSR_REFERENCE_TSC: 1971 case HV_X64_MSR_TIME_REF_COUNT: 1972 r = true; 1973 break; 1974 } 1975 1976 return r; 1977 } 1978 1979 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1980 { 1981 struct kvm *kvm = vcpu->kvm; 1982 1983 switch (msr) { 1984 case HV_X64_MSR_GUEST_OS_ID: 1985 kvm->arch.hv_guest_os_id = data; 1986 /* setting guest os id to zero disables hypercall page */ 1987 if (!kvm->arch.hv_guest_os_id) 1988 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; 1989 break; 1990 case HV_X64_MSR_HYPERCALL: { 1991 u64 gfn; 1992 unsigned long addr; 1993 u8 instructions[4]; 1994 1995 /* if guest os id is not set hypercall should remain disabled */ 1996 if (!kvm->arch.hv_guest_os_id) 1997 break; 1998 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { 1999 kvm->arch.hv_hypercall = data; 2000 break; 2001 } 2002 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; 2003 addr = gfn_to_hva(kvm, gfn); 2004 if (kvm_is_error_hva(addr)) 2005 return 1; 2006 kvm_x86_ops->patch_hypercall(vcpu, instructions); 2007 ((unsigned char *)instructions)[3] = 0xc3; /* ret */ 2008 if (__copy_to_user((void __user *)addr, instructions, 4)) 2009 return 1; 2010 kvm->arch.hv_hypercall = data; 2011 mark_page_dirty(kvm, gfn); 2012 break; 2013 } 2014 case HV_X64_MSR_REFERENCE_TSC: { 2015 u64 gfn; 2016 HV_REFERENCE_TSC_PAGE tsc_ref; 2017 memset(&tsc_ref, 0, sizeof(tsc_ref)); 2018 kvm->arch.hv_tsc_page = data; 2019 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE)) 2020 break; 2021 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT; 2022 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT, 2023 &tsc_ref, sizeof(tsc_ref))) 2024 return 1; 2025 mark_page_dirty(kvm, gfn); 2026 break; 2027 } 2028 default: 2029 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " 2030 "data 0x%llx\n", msr, data); 2031 return 1; 2032 } 2033 return 0; 2034 } 2035 2036 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) 2037 { 2038 switch (msr) { 2039 case HV_X64_MSR_APIC_ASSIST_PAGE: { 2040 u64 gfn; 2041 unsigned long addr; 2042 2043 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { 2044 vcpu->arch.hv_vapic = data; 2045 if (kvm_lapic_enable_pv_eoi(vcpu, 0)) 2046 return 1; 2047 break; 2048 } 2049 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT; 2050 addr = gfn_to_hva(vcpu->kvm, gfn); 2051 if (kvm_is_error_hva(addr)) 2052 return 1; 2053 if (__clear_user((void __user *)addr, PAGE_SIZE)) 2054 return 1; 2055 vcpu->arch.hv_vapic = data; 2056 mark_page_dirty(vcpu->kvm, gfn); 2057 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED)) 2058 return 1; 2059 break; 2060 } 2061 case HV_X64_MSR_EOI: 2062 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); 2063 case HV_X64_MSR_ICR: 2064 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); 2065 case HV_X64_MSR_TPR: 2066 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); 2067 default: 2068 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " 2069 "data 0x%llx\n", msr, data); 2070 return 1; 2071 } 2072 2073 return 0; 2074 } 2075 2076 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2077 { 2078 gpa_t gpa = data & ~0x3f; 2079 2080 /* Bits 2:5 are reserved, Should be zero */ 2081 if (data & 0x3c) 2082 return 1; 2083 2084 vcpu->arch.apf.msr_val = data; 2085 2086 if (!(data & KVM_ASYNC_PF_ENABLED)) { 2087 kvm_clear_async_pf_completion_queue(vcpu); 2088 kvm_async_pf_hash_reset(vcpu); 2089 return 0; 2090 } 2091 2092 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2093 sizeof(u32))) 2094 return 1; 2095 2096 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2097 kvm_async_pf_wakeup_all(vcpu); 2098 return 0; 2099 } 2100 2101 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2102 { 2103 vcpu->arch.pv_time_enabled = false; 2104 } 2105 2106 static void accumulate_steal_time(struct kvm_vcpu *vcpu) 2107 { 2108 u64 delta; 2109 2110 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2111 return; 2112 2113 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; 2114 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2115 vcpu->arch.st.accum_steal = delta; 2116 } 2117 2118 static void record_steal_time(struct kvm_vcpu *vcpu) 2119 { 2120 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2121 return; 2122 2123 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2124 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2125 return; 2126 2127 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; 2128 vcpu->arch.st.steal.version += 2; 2129 vcpu->arch.st.accum_steal = 0; 2130 2131 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2132 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2133 } 2134 2135 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2136 { 2137 bool pr = false; 2138 u32 msr = msr_info->index; 2139 u64 data = msr_info->data; 2140 2141 switch (msr) { 2142 case MSR_AMD64_NB_CFG: 2143 case MSR_IA32_UCODE_REV: 2144 case MSR_IA32_UCODE_WRITE: 2145 case MSR_VM_HSAVE_PA: 2146 case MSR_AMD64_PATCH_LOADER: 2147 case MSR_AMD64_BU_CFG2: 2148 break; 2149 2150 case MSR_EFER: 2151 return set_efer(vcpu, data); 2152 case MSR_K7_HWCR: 2153 data &= ~(u64)0x40; /* ignore flush filter disable */ 2154 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2155 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2156 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2157 if (data != 0) { 2158 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2159 data); 2160 return 1; 2161 } 2162 break; 2163 case MSR_FAM10H_MMIO_CONF_BASE: 2164 if (data != 0) { 2165 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2166 "0x%llx\n", data); 2167 return 1; 2168 } 2169 break; 2170 case MSR_IA32_DEBUGCTLMSR: 2171 if (!data) { 2172 /* We support the non-activated case already */ 2173 break; 2174 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2175 /* Values other than LBR and BTF are vendor-specific, 2176 thus reserved and should throw a #GP */ 2177 return 1; 2178 } 2179 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2180 __func__, data); 2181 break; 2182 case 0x200 ... 0x2ff: 2183 return set_msr_mtrr(vcpu, msr, data); 2184 case MSR_IA32_APICBASE: 2185 return kvm_set_apic_base(vcpu, msr_info); 2186 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2187 return kvm_x2apic_msr_write(vcpu, msr, data); 2188 case MSR_IA32_TSCDEADLINE: 2189 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2190 break; 2191 case MSR_IA32_TSC_ADJUST: 2192 if (guest_cpuid_has_tsc_adjust(vcpu)) { 2193 if (!msr_info->host_initiated) { 2194 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2195 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true); 2196 } 2197 vcpu->arch.ia32_tsc_adjust_msr = data; 2198 } 2199 break; 2200 case MSR_IA32_MISC_ENABLE: 2201 vcpu->arch.ia32_misc_enable_msr = data; 2202 break; 2203 case MSR_KVM_WALL_CLOCK_NEW: 2204 case MSR_KVM_WALL_CLOCK: 2205 vcpu->kvm->arch.wall_clock = data; 2206 kvm_write_wall_clock(vcpu->kvm, data); 2207 break; 2208 case MSR_KVM_SYSTEM_TIME_NEW: 2209 case MSR_KVM_SYSTEM_TIME: { 2210 u64 gpa_offset; 2211 struct kvm_arch *ka = &vcpu->kvm->arch; 2212 2213 kvmclock_reset(vcpu); 2214 2215 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2216 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2217 2218 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2219 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, 2220 &vcpu->requests); 2221 2222 ka->boot_vcpu_runs_old_kvmclock = tmp; 2223 } 2224 2225 vcpu->arch.time = data; 2226 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2227 2228 /* we verify if the enable bit is set... */ 2229 if (!(data & 1)) 2230 break; 2231 2232 gpa_offset = data & ~(PAGE_MASK | 1); 2233 2234 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2235 &vcpu->arch.pv_time, data & ~1ULL, 2236 sizeof(struct pvclock_vcpu_time_info))) 2237 vcpu->arch.pv_time_enabled = false; 2238 else 2239 vcpu->arch.pv_time_enabled = true; 2240 2241 break; 2242 } 2243 case MSR_KVM_ASYNC_PF_EN: 2244 if (kvm_pv_enable_async_pf(vcpu, data)) 2245 return 1; 2246 break; 2247 case MSR_KVM_STEAL_TIME: 2248 2249 if (unlikely(!sched_info_on())) 2250 return 1; 2251 2252 if (data & KVM_STEAL_RESERVED_MASK) 2253 return 1; 2254 2255 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2256 data & KVM_STEAL_VALID_BITS, 2257 sizeof(struct kvm_steal_time))) 2258 return 1; 2259 2260 vcpu->arch.st.msr_val = data; 2261 2262 if (!(data & KVM_MSR_ENABLED)) 2263 break; 2264 2265 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2266 2267 preempt_disable(); 2268 accumulate_steal_time(vcpu); 2269 preempt_enable(); 2270 2271 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2272 2273 break; 2274 case MSR_KVM_PV_EOI_EN: 2275 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2276 return 1; 2277 break; 2278 2279 case MSR_IA32_MCG_CTL: 2280 case MSR_IA32_MCG_STATUS: 2281 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2282 return set_msr_mce(vcpu, msr, data); 2283 2284 /* Performance counters are not protected by a CPUID bit, 2285 * so we should check all of them in the generic path for the sake of 2286 * cross vendor migration. 2287 * Writing a zero into the event select MSRs disables them, 2288 * which we perfectly emulate ;-). Any other value should be at least 2289 * reported, some guests depend on them. 2290 */ 2291 case MSR_K7_EVNTSEL0: 2292 case MSR_K7_EVNTSEL1: 2293 case MSR_K7_EVNTSEL2: 2294 case MSR_K7_EVNTSEL3: 2295 if (data != 0) 2296 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " 2297 "0x%x data 0x%llx\n", msr, data); 2298 break; 2299 /* at least RHEL 4 unconditionally writes to the perfctr registers, 2300 * so we ignore writes to make it happy. 2301 */ 2302 case MSR_K7_PERFCTR0: 2303 case MSR_K7_PERFCTR1: 2304 case MSR_K7_PERFCTR2: 2305 case MSR_K7_PERFCTR3: 2306 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " 2307 "0x%x data 0x%llx\n", msr, data); 2308 break; 2309 case MSR_P6_PERFCTR0: 2310 case MSR_P6_PERFCTR1: 2311 pr = true; 2312 case MSR_P6_EVNTSEL0: 2313 case MSR_P6_EVNTSEL1: 2314 if (kvm_pmu_msr(vcpu, msr)) 2315 return kvm_pmu_set_msr(vcpu, msr_info); 2316 2317 if (pr || data != 0) 2318 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2319 "0x%x data 0x%llx\n", msr, data); 2320 break; 2321 case MSR_K7_CLK_CTL: 2322 /* 2323 * Ignore all writes to this no longer documented MSR. 2324 * Writes are only relevant for old K7 processors, 2325 * all pre-dating SVM, but a recommended workaround from 2326 * AMD for these chips. It is possible to specify the 2327 * affected processor models on the command line, hence 2328 * the need to ignore the workaround. 2329 */ 2330 break; 2331 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2332 if (kvm_hv_msr_partition_wide(msr)) { 2333 int r; 2334 mutex_lock(&vcpu->kvm->lock); 2335 r = set_msr_hyperv_pw(vcpu, msr, data); 2336 mutex_unlock(&vcpu->kvm->lock); 2337 return r; 2338 } else 2339 return set_msr_hyperv(vcpu, msr, data); 2340 break; 2341 case MSR_IA32_BBL_CR_CTL3: 2342 /* Drop writes to this legacy MSR -- see rdmsr 2343 * counterpart for further detail. 2344 */ 2345 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); 2346 break; 2347 case MSR_AMD64_OSVW_ID_LENGTH: 2348 if (!guest_cpuid_has_osvw(vcpu)) 2349 return 1; 2350 vcpu->arch.osvw.length = data; 2351 break; 2352 case MSR_AMD64_OSVW_STATUS: 2353 if (!guest_cpuid_has_osvw(vcpu)) 2354 return 1; 2355 vcpu->arch.osvw.status = data; 2356 break; 2357 default: 2358 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2359 return xen_hvm_config(vcpu, data); 2360 if (kvm_pmu_msr(vcpu, msr)) 2361 return kvm_pmu_set_msr(vcpu, msr_info); 2362 if (!ignore_msrs) { 2363 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", 2364 msr, data); 2365 return 1; 2366 } else { 2367 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", 2368 msr, data); 2369 break; 2370 } 2371 } 2372 return 0; 2373 } 2374 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2375 2376 2377 /* 2378 * Reads an msr value (of 'msr_index') into 'pdata'. 2379 * Returns 0 on success, non-0 otherwise. 2380 * Assumes vcpu_load() was already called. 2381 */ 2382 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) 2383 { 2384 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); 2385 } 2386 EXPORT_SYMBOL_GPL(kvm_get_msr); 2387 2388 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2389 { 2390 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; 2391 2392 if (!msr_mtrr_valid(msr)) 2393 return 1; 2394 2395 if (msr == MSR_MTRRdefType) 2396 *pdata = vcpu->arch.mtrr_state.def_type + 2397 (vcpu->arch.mtrr_state.enabled << 10); 2398 else if (msr == MSR_MTRRfix64K_00000) 2399 *pdata = p[0]; 2400 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) 2401 *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; 2402 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) 2403 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; 2404 else if (msr == MSR_IA32_CR_PAT) 2405 *pdata = vcpu->arch.pat; 2406 else { /* Variable MTRRs */ 2407 int idx, is_mtrr_mask; 2408 u64 *pt; 2409 2410 idx = (msr - 0x200) / 2; 2411 is_mtrr_mask = msr - 0x200 - 2 * idx; 2412 if (!is_mtrr_mask) 2413 pt = 2414 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; 2415 else 2416 pt = 2417 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; 2418 *pdata = *pt; 2419 } 2420 2421 return 0; 2422 } 2423 2424 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2425 { 2426 u64 data; 2427 u64 mcg_cap = vcpu->arch.mcg_cap; 2428 unsigned bank_num = mcg_cap & 0xff; 2429 2430 switch (msr) { 2431 case MSR_IA32_P5_MC_ADDR: 2432 case MSR_IA32_P5_MC_TYPE: 2433 data = 0; 2434 break; 2435 case MSR_IA32_MCG_CAP: 2436 data = vcpu->arch.mcg_cap; 2437 break; 2438 case MSR_IA32_MCG_CTL: 2439 if (!(mcg_cap & MCG_CTL_P)) 2440 return 1; 2441 data = vcpu->arch.mcg_ctl; 2442 break; 2443 case MSR_IA32_MCG_STATUS: 2444 data = vcpu->arch.mcg_status; 2445 break; 2446 default: 2447 if (msr >= MSR_IA32_MC0_CTL && 2448 msr < MSR_IA32_MCx_CTL(bank_num)) { 2449 u32 offset = msr - MSR_IA32_MC0_CTL; 2450 data = vcpu->arch.mce_banks[offset]; 2451 break; 2452 } 2453 return 1; 2454 } 2455 *pdata = data; 2456 return 0; 2457 } 2458 2459 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2460 { 2461 u64 data = 0; 2462 struct kvm *kvm = vcpu->kvm; 2463 2464 switch (msr) { 2465 case HV_X64_MSR_GUEST_OS_ID: 2466 data = kvm->arch.hv_guest_os_id; 2467 break; 2468 case HV_X64_MSR_HYPERCALL: 2469 data = kvm->arch.hv_hypercall; 2470 break; 2471 case HV_X64_MSR_TIME_REF_COUNT: { 2472 data = 2473 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100); 2474 break; 2475 } 2476 case HV_X64_MSR_REFERENCE_TSC: 2477 data = kvm->arch.hv_tsc_page; 2478 break; 2479 default: 2480 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); 2481 return 1; 2482 } 2483 2484 *pdata = data; 2485 return 0; 2486 } 2487 2488 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2489 { 2490 u64 data = 0; 2491 2492 switch (msr) { 2493 case HV_X64_MSR_VP_INDEX: { 2494 int r; 2495 struct kvm_vcpu *v; 2496 kvm_for_each_vcpu(r, v, vcpu->kvm) { 2497 if (v == vcpu) { 2498 data = r; 2499 break; 2500 } 2501 } 2502 break; 2503 } 2504 case HV_X64_MSR_EOI: 2505 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); 2506 case HV_X64_MSR_ICR: 2507 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); 2508 case HV_X64_MSR_TPR: 2509 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); 2510 case HV_X64_MSR_APIC_ASSIST_PAGE: 2511 data = vcpu->arch.hv_vapic; 2512 break; 2513 default: 2514 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); 2515 return 1; 2516 } 2517 *pdata = data; 2518 return 0; 2519 } 2520 2521 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2522 { 2523 u64 data; 2524 2525 switch (msr) { 2526 case MSR_IA32_PLATFORM_ID: 2527 case MSR_IA32_EBL_CR_POWERON: 2528 case MSR_IA32_DEBUGCTLMSR: 2529 case MSR_IA32_LASTBRANCHFROMIP: 2530 case MSR_IA32_LASTBRANCHTOIP: 2531 case MSR_IA32_LASTINTFROMIP: 2532 case MSR_IA32_LASTINTTOIP: 2533 case MSR_K8_SYSCFG: 2534 case MSR_K7_HWCR: 2535 case MSR_VM_HSAVE_PA: 2536 case MSR_K7_EVNTSEL0: 2537 case MSR_K7_EVNTSEL1: 2538 case MSR_K7_EVNTSEL2: 2539 case MSR_K7_EVNTSEL3: 2540 case MSR_K7_PERFCTR0: 2541 case MSR_K7_PERFCTR1: 2542 case MSR_K7_PERFCTR2: 2543 case MSR_K7_PERFCTR3: 2544 case MSR_K8_INT_PENDING_MSG: 2545 case MSR_AMD64_NB_CFG: 2546 case MSR_FAM10H_MMIO_CONF_BASE: 2547 case MSR_AMD64_BU_CFG2: 2548 data = 0; 2549 break; 2550 case MSR_P6_PERFCTR0: 2551 case MSR_P6_PERFCTR1: 2552 case MSR_P6_EVNTSEL0: 2553 case MSR_P6_EVNTSEL1: 2554 if (kvm_pmu_msr(vcpu, msr)) 2555 return kvm_pmu_get_msr(vcpu, msr, pdata); 2556 data = 0; 2557 break; 2558 case MSR_IA32_UCODE_REV: 2559 data = 0x100000000ULL; 2560 break; 2561 case MSR_MTRRcap: 2562 data = 0x500 | KVM_NR_VAR_MTRR; 2563 break; 2564 case 0x200 ... 0x2ff: 2565 return get_msr_mtrr(vcpu, msr, pdata); 2566 case 0xcd: /* fsb frequency */ 2567 data = 3; 2568 break; 2569 /* 2570 * MSR_EBC_FREQUENCY_ID 2571 * Conservative value valid for even the basic CPU models. 2572 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2573 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2574 * and 266MHz for model 3, or 4. Set Core Clock 2575 * Frequency to System Bus Frequency Ratio to 1 (bits 2576 * 31:24) even though these are only valid for CPU 2577 * models > 2, however guests may end up dividing or 2578 * multiplying by zero otherwise. 2579 */ 2580 case MSR_EBC_FREQUENCY_ID: 2581 data = 1 << 24; 2582 break; 2583 case MSR_IA32_APICBASE: 2584 data = kvm_get_apic_base(vcpu); 2585 break; 2586 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2587 return kvm_x2apic_msr_read(vcpu, msr, pdata); 2588 break; 2589 case MSR_IA32_TSCDEADLINE: 2590 data = kvm_get_lapic_tscdeadline_msr(vcpu); 2591 break; 2592 case MSR_IA32_TSC_ADJUST: 2593 data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2594 break; 2595 case MSR_IA32_MISC_ENABLE: 2596 data = vcpu->arch.ia32_misc_enable_msr; 2597 break; 2598 case MSR_IA32_PERF_STATUS: 2599 /* TSC increment by tick */ 2600 data = 1000ULL; 2601 /* CPU multiplier */ 2602 data |= (((uint64_t)4ULL) << 40); 2603 break; 2604 case MSR_EFER: 2605 data = vcpu->arch.efer; 2606 break; 2607 case MSR_KVM_WALL_CLOCK: 2608 case MSR_KVM_WALL_CLOCK_NEW: 2609 data = vcpu->kvm->arch.wall_clock; 2610 break; 2611 case MSR_KVM_SYSTEM_TIME: 2612 case MSR_KVM_SYSTEM_TIME_NEW: 2613 data = vcpu->arch.time; 2614 break; 2615 case MSR_KVM_ASYNC_PF_EN: 2616 data = vcpu->arch.apf.msr_val; 2617 break; 2618 case MSR_KVM_STEAL_TIME: 2619 data = vcpu->arch.st.msr_val; 2620 break; 2621 case MSR_KVM_PV_EOI_EN: 2622 data = vcpu->arch.pv_eoi.msr_val; 2623 break; 2624 case MSR_IA32_P5_MC_ADDR: 2625 case MSR_IA32_P5_MC_TYPE: 2626 case MSR_IA32_MCG_CAP: 2627 case MSR_IA32_MCG_CTL: 2628 case MSR_IA32_MCG_STATUS: 2629 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2630 return get_msr_mce(vcpu, msr, pdata); 2631 case MSR_K7_CLK_CTL: 2632 /* 2633 * Provide expected ramp-up count for K7. All other 2634 * are set to zero, indicating minimum divisors for 2635 * every field. 2636 * 2637 * This prevents guest kernels on AMD host with CPU 2638 * type 6, model 8 and higher from exploding due to 2639 * the rdmsr failing. 2640 */ 2641 data = 0x20000000; 2642 break; 2643 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2644 if (kvm_hv_msr_partition_wide(msr)) { 2645 int r; 2646 mutex_lock(&vcpu->kvm->lock); 2647 r = get_msr_hyperv_pw(vcpu, msr, pdata); 2648 mutex_unlock(&vcpu->kvm->lock); 2649 return r; 2650 } else 2651 return get_msr_hyperv(vcpu, msr, pdata); 2652 break; 2653 case MSR_IA32_BBL_CR_CTL3: 2654 /* This legacy MSR exists but isn't fully documented in current 2655 * silicon. It is however accessed by winxp in very narrow 2656 * scenarios where it sets bit #19, itself documented as 2657 * a "reserved" bit. Best effort attempt to source coherent 2658 * read data here should the balance of the register be 2659 * interpreted by the guest: 2660 * 2661 * L2 cache control register 3: 64GB range, 256KB size, 2662 * enabled, latency 0x1, configured 2663 */ 2664 data = 0xbe702111; 2665 break; 2666 case MSR_AMD64_OSVW_ID_LENGTH: 2667 if (!guest_cpuid_has_osvw(vcpu)) 2668 return 1; 2669 data = vcpu->arch.osvw.length; 2670 break; 2671 case MSR_AMD64_OSVW_STATUS: 2672 if (!guest_cpuid_has_osvw(vcpu)) 2673 return 1; 2674 data = vcpu->arch.osvw.status; 2675 break; 2676 default: 2677 if (kvm_pmu_msr(vcpu, msr)) 2678 return kvm_pmu_get_msr(vcpu, msr, pdata); 2679 if (!ignore_msrs) { 2680 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); 2681 return 1; 2682 } else { 2683 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); 2684 data = 0; 2685 } 2686 break; 2687 } 2688 *pdata = data; 2689 return 0; 2690 } 2691 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2692 2693 /* 2694 * Read or write a bunch of msrs. All parameters are kernel addresses. 2695 * 2696 * @return number of msrs set successfully. 2697 */ 2698 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2699 struct kvm_msr_entry *entries, 2700 int (*do_msr)(struct kvm_vcpu *vcpu, 2701 unsigned index, u64 *data)) 2702 { 2703 int i, idx; 2704 2705 idx = srcu_read_lock(&vcpu->kvm->srcu); 2706 for (i = 0; i < msrs->nmsrs; ++i) 2707 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2708 break; 2709 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2710 2711 return i; 2712 } 2713 2714 /* 2715 * Read or write a bunch of msrs. Parameters are user addresses. 2716 * 2717 * @return number of msrs set successfully. 2718 */ 2719 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2720 int (*do_msr)(struct kvm_vcpu *vcpu, 2721 unsigned index, u64 *data), 2722 int writeback) 2723 { 2724 struct kvm_msrs msrs; 2725 struct kvm_msr_entry *entries; 2726 int r, n; 2727 unsigned size; 2728 2729 r = -EFAULT; 2730 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2731 goto out; 2732 2733 r = -E2BIG; 2734 if (msrs.nmsrs >= MAX_IO_MSRS) 2735 goto out; 2736 2737 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2738 entries = memdup_user(user_msrs->entries, size); 2739 if (IS_ERR(entries)) { 2740 r = PTR_ERR(entries); 2741 goto out; 2742 } 2743 2744 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2745 if (r < 0) 2746 goto out_free; 2747 2748 r = -EFAULT; 2749 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2750 goto out_free; 2751 2752 r = n; 2753 2754 out_free: 2755 kfree(entries); 2756 out: 2757 return r; 2758 } 2759 2760 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2761 { 2762 int r; 2763 2764 switch (ext) { 2765 case KVM_CAP_IRQCHIP: 2766 case KVM_CAP_HLT: 2767 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2768 case KVM_CAP_SET_TSS_ADDR: 2769 case KVM_CAP_EXT_CPUID: 2770 case KVM_CAP_EXT_EMUL_CPUID: 2771 case KVM_CAP_CLOCKSOURCE: 2772 case KVM_CAP_PIT: 2773 case KVM_CAP_NOP_IO_DELAY: 2774 case KVM_CAP_MP_STATE: 2775 case KVM_CAP_SYNC_MMU: 2776 case KVM_CAP_USER_NMI: 2777 case KVM_CAP_REINJECT_CONTROL: 2778 case KVM_CAP_IRQ_INJECT_STATUS: 2779 case KVM_CAP_IOEVENTFD: 2780 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2781 case KVM_CAP_PIT2: 2782 case KVM_CAP_PIT_STATE2: 2783 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2784 case KVM_CAP_XEN_HVM: 2785 case KVM_CAP_ADJUST_CLOCK: 2786 case KVM_CAP_VCPU_EVENTS: 2787 case KVM_CAP_HYPERV: 2788 case KVM_CAP_HYPERV_VAPIC: 2789 case KVM_CAP_HYPERV_SPIN: 2790 case KVM_CAP_PCI_SEGMENT: 2791 case KVM_CAP_DEBUGREGS: 2792 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2793 case KVM_CAP_XSAVE: 2794 case KVM_CAP_ASYNC_PF: 2795 case KVM_CAP_GET_TSC_KHZ: 2796 case KVM_CAP_KVMCLOCK_CTRL: 2797 case KVM_CAP_READONLY_MEM: 2798 case KVM_CAP_HYPERV_TIME: 2799 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2800 case KVM_CAP_TSC_DEADLINE_TIMER: 2801 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2802 case KVM_CAP_ASSIGN_DEV_IRQ: 2803 case KVM_CAP_PCI_2_3: 2804 #endif 2805 r = 1; 2806 break; 2807 case KVM_CAP_COALESCED_MMIO: 2808 r = KVM_COALESCED_MMIO_PAGE_OFFSET; 2809 break; 2810 case KVM_CAP_VAPIC: 2811 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2812 break; 2813 case KVM_CAP_NR_VCPUS: 2814 r = KVM_SOFT_MAX_VCPUS; 2815 break; 2816 case KVM_CAP_MAX_VCPUS: 2817 r = KVM_MAX_VCPUS; 2818 break; 2819 case KVM_CAP_NR_MEMSLOTS: 2820 r = KVM_USER_MEM_SLOTS; 2821 break; 2822 case KVM_CAP_PV_MMU: /* obsolete */ 2823 r = 0; 2824 break; 2825 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2826 case KVM_CAP_IOMMU: 2827 r = iommu_present(&pci_bus_type); 2828 break; 2829 #endif 2830 case KVM_CAP_MCE: 2831 r = KVM_MAX_MCE_BANKS; 2832 break; 2833 case KVM_CAP_XCRS: 2834 r = cpu_has_xsave; 2835 break; 2836 case KVM_CAP_TSC_CONTROL: 2837 r = kvm_has_tsc_control; 2838 break; 2839 default: 2840 r = 0; 2841 break; 2842 } 2843 return r; 2844 2845 } 2846 2847 long kvm_arch_dev_ioctl(struct file *filp, 2848 unsigned int ioctl, unsigned long arg) 2849 { 2850 void __user *argp = (void __user *)arg; 2851 long r; 2852 2853 switch (ioctl) { 2854 case KVM_GET_MSR_INDEX_LIST: { 2855 struct kvm_msr_list __user *user_msr_list = argp; 2856 struct kvm_msr_list msr_list; 2857 unsigned n; 2858 2859 r = -EFAULT; 2860 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2861 goto out; 2862 n = msr_list.nmsrs; 2863 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); 2864 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2865 goto out; 2866 r = -E2BIG; 2867 if (n < msr_list.nmsrs) 2868 goto out; 2869 r = -EFAULT; 2870 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2871 num_msrs_to_save * sizeof(u32))) 2872 goto out; 2873 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2874 &emulated_msrs, 2875 ARRAY_SIZE(emulated_msrs) * sizeof(u32))) 2876 goto out; 2877 r = 0; 2878 break; 2879 } 2880 case KVM_GET_SUPPORTED_CPUID: 2881 case KVM_GET_EMULATED_CPUID: { 2882 struct kvm_cpuid2 __user *cpuid_arg = argp; 2883 struct kvm_cpuid2 cpuid; 2884 2885 r = -EFAULT; 2886 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2887 goto out; 2888 2889 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2890 ioctl); 2891 if (r) 2892 goto out; 2893 2894 r = -EFAULT; 2895 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2896 goto out; 2897 r = 0; 2898 break; 2899 } 2900 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2901 u64 mce_cap; 2902 2903 mce_cap = KVM_MCE_CAP_SUPPORTED; 2904 r = -EFAULT; 2905 if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) 2906 goto out; 2907 r = 0; 2908 break; 2909 } 2910 default: 2911 r = -EINVAL; 2912 } 2913 out: 2914 return r; 2915 } 2916 2917 static void wbinvd_ipi(void *garbage) 2918 { 2919 wbinvd(); 2920 } 2921 2922 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 2923 { 2924 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 2925 } 2926 2927 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 2928 { 2929 /* Address WBINVD may be executed by guest */ 2930 if (need_emulate_wbinvd(vcpu)) { 2931 if (kvm_x86_ops->has_wbinvd_exit()) 2932 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 2933 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 2934 smp_call_function_single(vcpu->cpu, 2935 wbinvd_ipi, NULL, 1); 2936 } 2937 2938 kvm_x86_ops->vcpu_load(vcpu, cpu); 2939 2940 /* Apply any externally detected TSC adjustments (due to suspend) */ 2941 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 2942 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 2943 vcpu->arch.tsc_offset_adjustment = 0; 2944 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2945 } 2946 2947 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { 2948 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 2949 native_read_tsc() - vcpu->arch.last_host_tsc; 2950 if (tsc_delta < 0) 2951 mark_tsc_unstable("KVM discovered backwards TSC"); 2952 if (check_tsc_unstable()) { 2953 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu, 2954 vcpu->arch.last_guest_tsc); 2955 kvm_x86_ops->write_tsc_offset(vcpu, offset); 2956 vcpu->arch.tsc_catchup = 1; 2957 } 2958 /* 2959 * On a host with synchronized TSC, there is no need to update 2960 * kvmclock on vcpu->cpu migration 2961 */ 2962 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 2963 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2964 if (vcpu->cpu != cpu) 2965 kvm_migrate_timers(vcpu); 2966 vcpu->cpu = cpu; 2967 } 2968 2969 accumulate_steal_time(vcpu); 2970 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2971 } 2972 2973 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 2974 { 2975 kvm_x86_ops->vcpu_put(vcpu); 2976 kvm_put_guest_fpu(vcpu); 2977 vcpu->arch.last_host_tsc = native_read_tsc(); 2978 } 2979 2980 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 2981 struct kvm_lapic_state *s) 2982 { 2983 kvm_x86_ops->sync_pir_to_irr(vcpu); 2984 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); 2985 2986 return 0; 2987 } 2988 2989 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 2990 struct kvm_lapic_state *s) 2991 { 2992 kvm_apic_post_state_restore(vcpu, s); 2993 update_cr8_intercept(vcpu); 2994 2995 return 0; 2996 } 2997 2998 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 2999 struct kvm_interrupt *irq) 3000 { 3001 if (irq->irq >= KVM_NR_INTERRUPTS) 3002 return -EINVAL; 3003 if (irqchip_in_kernel(vcpu->kvm)) 3004 return -ENXIO; 3005 3006 kvm_queue_interrupt(vcpu, irq->irq, false); 3007 kvm_make_request(KVM_REQ_EVENT, vcpu); 3008 3009 return 0; 3010 } 3011 3012 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 3013 { 3014 kvm_inject_nmi(vcpu); 3015 3016 return 0; 3017 } 3018 3019 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 3020 struct kvm_tpr_access_ctl *tac) 3021 { 3022 if (tac->flags) 3023 return -EINVAL; 3024 vcpu->arch.tpr_access_reporting = !!tac->enabled; 3025 return 0; 3026 } 3027 3028 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 3029 u64 mcg_cap) 3030 { 3031 int r; 3032 unsigned bank_num = mcg_cap & 0xff, bank; 3033 3034 r = -EINVAL; 3035 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 3036 goto out; 3037 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) 3038 goto out; 3039 r = 0; 3040 vcpu->arch.mcg_cap = mcg_cap; 3041 /* Init IA32_MCG_CTL to all 1s */ 3042 if (mcg_cap & MCG_CTL_P) 3043 vcpu->arch.mcg_ctl = ~(u64)0; 3044 /* Init IA32_MCi_CTL to all 1s */ 3045 for (bank = 0; bank < bank_num; bank++) 3046 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 3047 out: 3048 return r; 3049 } 3050 3051 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 3052 struct kvm_x86_mce *mce) 3053 { 3054 u64 mcg_cap = vcpu->arch.mcg_cap; 3055 unsigned bank_num = mcg_cap & 0xff; 3056 u64 *banks = vcpu->arch.mce_banks; 3057 3058 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 3059 return -EINVAL; 3060 /* 3061 * if IA32_MCG_CTL is not all 1s, the uncorrected error 3062 * reporting is disabled 3063 */ 3064 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 3065 vcpu->arch.mcg_ctl != ~(u64)0) 3066 return 0; 3067 banks += 4 * mce->bank; 3068 /* 3069 * if IA32_MCi_CTL is not all 1s, the uncorrected error 3070 * reporting is disabled for the bank 3071 */ 3072 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 3073 return 0; 3074 if (mce->status & MCI_STATUS_UC) { 3075 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 3076 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 3077 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 3078 return 0; 3079 } 3080 if (banks[1] & MCI_STATUS_VAL) 3081 mce->status |= MCI_STATUS_OVER; 3082 banks[2] = mce->addr; 3083 banks[3] = mce->misc; 3084 vcpu->arch.mcg_status = mce->mcg_status; 3085 banks[1] = mce->status; 3086 kvm_queue_exception(vcpu, MC_VECTOR); 3087 } else if (!(banks[1] & MCI_STATUS_VAL) 3088 || !(banks[1] & MCI_STATUS_UC)) { 3089 if (banks[1] & MCI_STATUS_VAL) 3090 mce->status |= MCI_STATUS_OVER; 3091 banks[2] = mce->addr; 3092 banks[3] = mce->misc; 3093 banks[1] = mce->status; 3094 } else 3095 banks[1] |= MCI_STATUS_OVER; 3096 return 0; 3097 } 3098 3099 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 3100 struct kvm_vcpu_events *events) 3101 { 3102 process_nmi(vcpu); 3103 events->exception.injected = 3104 vcpu->arch.exception.pending && 3105 !kvm_exception_is_soft(vcpu->arch.exception.nr); 3106 events->exception.nr = vcpu->arch.exception.nr; 3107 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 3108 events->exception.pad = 0; 3109 events->exception.error_code = vcpu->arch.exception.error_code; 3110 3111 events->interrupt.injected = 3112 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; 3113 events->interrupt.nr = vcpu->arch.interrupt.nr; 3114 events->interrupt.soft = 0; 3115 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 3116 3117 events->nmi.injected = vcpu->arch.nmi_injected; 3118 events->nmi.pending = vcpu->arch.nmi_pending != 0; 3119 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 3120 events->nmi.pad = 0; 3121 3122 events->sipi_vector = 0; /* never valid when reporting to user space */ 3123 3124 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 3125 | KVM_VCPUEVENT_VALID_SHADOW); 3126 memset(&events->reserved, 0, sizeof(events->reserved)); 3127 } 3128 3129 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 3130 struct kvm_vcpu_events *events) 3131 { 3132 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 3133 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 3134 | KVM_VCPUEVENT_VALID_SHADOW)) 3135 return -EINVAL; 3136 3137 process_nmi(vcpu); 3138 vcpu->arch.exception.pending = events->exception.injected; 3139 vcpu->arch.exception.nr = events->exception.nr; 3140 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 3141 vcpu->arch.exception.error_code = events->exception.error_code; 3142 3143 vcpu->arch.interrupt.pending = events->interrupt.injected; 3144 vcpu->arch.interrupt.nr = events->interrupt.nr; 3145 vcpu->arch.interrupt.soft = events->interrupt.soft; 3146 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3147 kvm_x86_ops->set_interrupt_shadow(vcpu, 3148 events->interrupt.shadow); 3149 3150 vcpu->arch.nmi_injected = events->nmi.injected; 3151 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3152 vcpu->arch.nmi_pending = events->nmi.pending; 3153 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 3154 3155 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3156 kvm_vcpu_has_lapic(vcpu)) 3157 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3158 3159 kvm_make_request(KVM_REQ_EVENT, vcpu); 3160 3161 return 0; 3162 } 3163 3164 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3165 struct kvm_debugregs *dbgregs) 3166 { 3167 unsigned long val; 3168 3169 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3170 kvm_get_dr(vcpu, 6, &val); 3171 dbgregs->dr6 = val; 3172 dbgregs->dr7 = vcpu->arch.dr7; 3173 dbgregs->flags = 0; 3174 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3175 } 3176 3177 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3178 struct kvm_debugregs *dbgregs) 3179 { 3180 if (dbgregs->flags) 3181 return -EINVAL; 3182 3183 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3184 kvm_update_dr0123(vcpu); 3185 vcpu->arch.dr6 = dbgregs->dr6; 3186 kvm_update_dr6(vcpu); 3187 vcpu->arch.dr7 = dbgregs->dr7; 3188 kvm_update_dr7(vcpu); 3189 3190 return 0; 3191 } 3192 3193 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3194 3195 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3196 { 3197 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave; 3198 u64 xstate_bv = xsave->xsave_hdr.xstate_bv; 3199 u64 valid; 3200 3201 /* 3202 * Copy legacy XSAVE area, to avoid complications with CPUID 3203 * leaves 0 and 1 in the loop below. 3204 */ 3205 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3206 3207 /* Set XSTATE_BV */ 3208 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3209 3210 /* 3211 * Copy each region from the possibly compacted offset to the 3212 * non-compacted offset. 3213 */ 3214 valid = xstate_bv & ~XSTATE_FPSSE; 3215 while (valid) { 3216 u64 feature = valid & -valid; 3217 int index = fls64(feature) - 1; 3218 void *src = get_xsave_addr(xsave, feature); 3219 3220 if (src) { 3221 u32 size, offset, ecx, edx; 3222 cpuid_count(XSTATE_CPUID, index, 3223 &size, &offset, &ecx, &edx); 3224 memcpy(dest + offset, src, size); 3225 } 3226 3227 valid -= feature; 3228 } 3229 } 3230 3231 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3232 { 3233 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave; 3234 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3235 u64 valid; 3236 3237 /* 3238 * Copy legacy XSAVE area, to avoid complications with CPUID 3239 * leaves 0 and 1 in the loop below. 3240 */ 3241 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3242 3243 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3244 xsave->xsave_hdr.xstate_bv = xstate_bv; 3245 if (cpu_has_xsaves) 3246 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3247 3248 /* 3249 * Copy each region from the non-compacted offset to the 3250 * possibly compacted offset. 3251 */ 3252 valid = xstate_bv & ~XSTATE_FPSSE; 3253 while (valid) { 3254 u64 feature = valid & -valid; 3255 int index = fls64(feature) - 1; 3256 void *dest = get_xsave_addr(xsave, feature); 3257 3258 if (dest) { 3259 u32 size, offset, ecx, edx; 3260 cpuid_count(XSTATE_CPUID, index, 3261 &size, &offset, &ecx, &edx); 3262 memcpy(dest, src + offset, size); 3263 } else 3264 WARN_ON_ONCE(1); 3265 3266 valid -= feature; 3267 } 3268 } 3269 3270 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3271 struct kvm_xsave *guest_xsave) 3272 { 3273 if (cpu_has_xsave) { 3274 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3275 fill_xsave((u8 *) guest_xsave->region, vcpu); 3276 } else { 3277 memcpy(guest_xsave->region, 3278 &vcpu->arch.guest_fpu.state->fxsave, 3279 sizeof(struct i387_fxsave_struct)); 3280 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3281 XSTATE_FPSSE; 3282 } 3283 } 3284 3285 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3286 struct kvm_xsave *guest_xsave) 3287 { 3288 u64 xstate_bv = 3289 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3290 3291 if (cpu_has_xsave) { 3292 /* 3293 * Here we allow setting states that are not present in 3294 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3295 * with old userspace. 3296 */ 3297 if (xstate_bv & ~kvm_supported_xcr0()) 3298 return -EINVAL; 3299 load_xsave(vcpu, (u8 *)guest_xsave->region); 3300 } else { 3301 if (xstate_bv & ~XSTATE_FPSSE) 3302 return -EINVAL; 3303 memcpy(&vcpu->arch.guest_fpu.state->fxsave, 3304 guest_xsave->region, sizeof(struct i387_fxsave_struct)); 3305 } 3306 return 0; 3307 } 3308 3309 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3310 struct kvm_xcrs *guest_xcrs) 3311 { 3312 if (!cpu_has_xsave) { 3313 guest_xcrs->nr_xcrs = 0; 3314 return; 3315 } 3316 3317 guest_xcrs->nr_xcrs = 1; 3318 guest_xcrs->flags = 0; 3319 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3320 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3321 } 3322 3323 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3324 struct kvm_xcrs *guest_xcrs) 3325 { 3326 int i, r = 0; 3327 3328 if (!cpu_has_xsave) 3329 return -EINVAL; 3330 3331 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3332 return -EINVAL; 3333 3334 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3335 /* Only support XCR0 currently */ 3336 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3337 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3338 guest_xcrs->xcrs[i].value); 3339 break; 3340 } 3341 if (r) 3342 r = -EINVAL; 3343 return r; 3344 } 3345 3346 /* 3347 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3348 * stopped by the hypervisor. This function will be called from the host only. 3349 * EINVAL is returned when the host attempts to set the flag for a guest that 3350 * does not support pv clocks. 3351 */ 3352 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3353 { 3354 if (!vcpu->arch.pv_time_enabled) 3355 return -EINVAL; 3356 vcpu->arch.pvclock_set_guest_stopped_request = true; 3357 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3358 return 0; 3359 } 3360 3361 long kvm_arch_vcpu_ioctl(struct file *filp, 3362 unsigned int ioctl, unsigned long arg) 3363 { 3364 struct kvm_vcpu *vcpu = filp->private_data; 3365 void __user *argp = (void __user *)arg; 3366 int r; 3367 union { 3368 struct kvm_lapic_state *lapic; 3369 struct kvm_xsave *xsave; 3370 struct kvm_xcrs *xcrs; 3371 void *buffer; 3372 } u; 3373 3374 u.buffer = NULL; 3375 switch (ioctl) { 3376 case KVM_GET_LAPIC: { 3377 r = -EINVAL; 3378 if (!vcpu->arch.apic) 3379 goto out; 3380 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3381 3382 r = -ENOMEM; 3383 if (!u.lapic) 3384 goto out; 3385 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3386 if (r) 3387 goto out; 3388 r = -EFAULT; 3389 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3390 goto out; 3391 r = 0; 3392 break; 3393 } 3394 case KVM_SET_LAPIC: { 3395 r = -EINVAL; 3396 if (!vcpu->arch.apic) 3397 goto out; 3398 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3399 if (IS_ERR(u.lapic)) 3400 return PTR_ERR(u.lapic); 3401 3402 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3403 break; 3404 } 3405 case KVM_INTERRUPT: { 3406 struct kvm_interrupt irq; 3407 3408 r = -EFAULT; 3409 if (copy_from_user(&irq, argp, sizeof irq)) 3410 goto out; 3411 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3412 break; 3413 } 3414 case KVM_NMI: { 3415 r = kvm_vcpu_ioctl_nmi(vcpu); 3416 break; 3417 } 3418 case KVM_SET_CPUID: { 3419 struct kvm_cpuid __user *cpuid_arg = argp; 3420 struct kvm_cpuid cpuid; 3421 3422 r = -EFAULT; 3423 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3424 goto out; 3425 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3426 break; 3427 } 3428 case KVM_SET_CPUID2: { 3429 struct kvm_cpuid2 __user *cpuid_arg = argp; 3430 struct kvm_cpuid2 cpuid; 3431 3432 r = -EFAULT; 3433 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3434 goto out; 3435 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3436 cpuid_arg->entries); 3437 break; 3438 } 3439 case KVM_GET_CPUID2: { 3440 struct kvm_cpuid2 __user *cpuid_arg = argp; 3441 struct kvm_cpuid2 cpuid; 3442 3443 r = -EFAULT; 3444 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3445 goto out; 3446 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3447 cpuid_arg->entries); 3448 if (r) 3449 goto out; 3450 r = -EFAULT; 3451 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3452 goto out; 3453 r = 0; 3454 break; 3455 } 3456 case KVM_GET_MSRS: 3457 r = msr_io(vcpu, argp, kvm_get_msr, 1); 3458 break; 3459 case KVM_SET_MSRS: 3460 r = msr_io(vcpu, argp, do_set_msr, 0); 3461 break; 3462 case KVM_TPR_ACCESS_REPORTING: { 3463 struct kvm_tpr_access_ctl tac; 3464 3465 r = -EFAULT; 3466 if (copy_from_user(&tac, argp, sizeof tac)) 3467 goto out; 3468 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3469 if (r) 3470 goto out; 3471 r = -EFAULT; 3472 if (copy_to_user(argp, &tac, sizeof tac)) 3473 goto out; 3474 r = 0; 3475 break; 3476 }; 3477 case KVM_SET_VAPIC_ADDR: { 3478 struct kvm_vapic_addr va; 3479 3480 r = -EINVAL; 3481 if (!irqchip_in_kernel(vcpu->kvm)) 3482 goto out; 3483 r = -EFAULT; 3484 if (copy_from_user(&va, argp, sizeof va)) 3485 goto out; 3486 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3487 break; 3488 } 3489 case KVM_X86_SETUP_MCE: { 3490 u64 mcg_cap; 3491 3492 r = -EFAULT; 3493 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3494 goto out; 3495 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3496 break; 3497 } 3498 case KVM_X86_SET_MCE: { 3499 struct kvm_x86_mce mce; 3500 3501 r = -EFAULT; 3502 if (copy_from_user(&mce, argp, sizeof mce)) 3503 goto out; 3504 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3505 break; 3506 } 3507 case KVM_GET_VCPU_EVENTS: { 3508 struct kvm_vcpu_events events; 3509 3510 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3511 3512 r = -EFAULT; 3513 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3514 break; 3515 r = 0; 3516 break; 3517 } 3518 case KVM_SET_VCPU_EVENTS: { 3519 struct kvm_vcpu_events events; 3520 3521 r = -EFAULT; 3522 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3523 break; 3524 3525 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3526 break; 3527 } 3528 case KVM_GET_DEBUGREGS: { 3529 struct kvm_debugregs dbgregs; 3530 3531 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3532 3533 r = -EFAULT; 3534 if (copy_to_user(argp, &dbgregs, 3535 sizeof(struct kvm_debugregs))) 3536 break; 3537 r = 0; 3538 break; 3539 } 3540 case KVM_SET_DEBUGREGS: { 3541 struct kvm_debugregs dbgregs; 3542 3543 r = -EFAULT; 3544 if (copy_from_user(&dbgregs, argp, 3545 sizeof(struct kvm_debugregs))) 3546 break; 3547 3548 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3549 break; 3550 } 3551 case KVM_GET_XSAVE: { 3552 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3553 r = -ENOMEM; 3554 if (!u.xsave) 3555 break; 3556 3557 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3558 3559 r = -EFAULT; 3560 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3561 break; 3562 r = 0; 3563 break; 3564 } 3565 case KVM_SET_XSAVE: { 3566 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3567 if (IS_ERR(u.xsave)) 3568 return PTR_ERR(u.xsave); 3569 3570 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3571 break; 3572 } 3573 case KVM_GET_XCRS: { 3574 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3575 r = -ENOMEM; 3576 if (!u.xcrs) 3577 break; 3578 3579 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3580 3581 r = -EFAULT; 3582 if (copy_to_user(argp, u.xcrs, 3583 sizeof(struct kvm_xcrs))) 3584 break; 3585 r = 0; 3586 break; 3587 } 3588 case KVM_SET_XCRS: { 3589 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3590 if (IS_ERR(u.xcrs)) 3591 return PTR_ERR(u.xcrs); 3592 3593 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3594 break; 3595 } 3596 case KVM_SET_TSC_KHZ: { 3597 u32 user_tsc_khz; 3598 3599 r = -EINVAL; 3600 user_tsc_khz = (u32)arg; 3601 3602 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3603 goto out; 3604 3605 if (user_tsc_khz == 0) 3606 user_tsc_khz = tsc_khz; 3607 3608 kvm_set_tsc_khz(vcpu, user_tsc_khz); 3609 3610 r = 0; 3611 goto out; 3612 } 3613 case KVM_GET_TSC_KHZ: { 3614 r = vcpu->arch.virtual_tsc_khz; 3615 goto out; 3616 } 3617 case KVM_KVMCLOCK_CTRL: { 3618 r = kvm_set_guest_paused(vcpu); 3619 goto out; 3620 } 3621 default: 3622 r = -EINVAL; 3623 } 3624 out: 3625 kfree(u.buffer); 3626 return r; 3627 } 3628 3629 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3630 { 3631 return VM_FAULT_SIGBUS; 3632 } 3633 3634 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3635 { 3636 int ret; 3637 3638 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3639 return -EINVAL; 3640 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3641 return ret; 3642 } 3643 3644 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3645 u64 ident_addr) 3646 { 3647 kvm->arch.ept_identity_map_addr = ident_addr; 3648 return 0; 3649 } 3650 3651 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3652 u32 kvm_nr_mmu_pages) 3653 { 3654 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3655 return -EINVAL; 3656 3657 mutex_lock(&kvm->slots_lock); 3658 3659 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3660 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3661 3662 mutex_unlock(&kvm->slots_lock); 3663 return 0; 3664 } 3665 3666 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 3667 { 3668 return kvm->arch.n_max_mmu_pages; 3669 } 3670 3671 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3672 { 3673 int r; 3674 3675 r = 0; 3676 switch (chip->chip_id) { 3677 case KVM_IRQCHIP_PIC_MASTER: 3678 memcpy(&chip->chip.pic, 3679 &pic_irqchip(kvm)->pics[0], 3680 sizeof(struct kvm_pic_state)); 3681 break; 3682 case KVM_IRQCHIP_PIC_SLAVE: 3683 memcpy(&chip->chip.pic, 3684 &pic_irqchip(kvm)->pics[1], 3685 sizeof(struct kvm_pic_state)); 3686 break; 3687 case KVM_IRQCHIP_IOAPIC: 3688 r = kvm_get_ioapic(kvm, &chip->chip.ioapic); 3689 break; 3690 default: 3691 r = -EINVAL; 3692 break; 3693 } 3694 return r; 3695 } 3696 3697 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3698 { 3699 int r; 3700 3701 r = 0; 3702 switch (chip->chip_id) { 3703 case KVM_IRQCHIP_PIC_MASTER: 3704 spin_lock(&pic_irqchip(kvm)->lock); 3705 memcpy(&pic_irqchip(kvm)->pics[0], 3706 &chip->chip.pic, 3707 sizeof(struct kvm_pic_state)); 3708 spin_unlock(&pic_irqchip(kvm)->lock); 3709 break; 3710 case KVM_IRQCHIP_PIC_SLAVE: 3711 spin_lock(&pic_irqchip(kvm)->lock); 3712 memcpy(&pic_irqchip(kvm)->pics[1], 3713 &chip->chip.pic, 3714 sizeof(struct kvm_pic_state)); 3715 spin_unlock(&pic_irqchip(kvm)->lock); 3716 break; 3717 case KVM_IRQCHIP_IOAPIC: 3718 r = kvm_set_ioapic(kvm, &chip->chip.ioapic); 3719 break; 3720 default: 3721 r = -EINVAL; 3722 break; 3723 } 3724 kvm_pic_update_irq(pic_irqchip(kvm)); 3725 return r; 3726 } 3727 3728 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3729 { 3730 int r = 0; 3731 3732 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3733 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); 3734 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3735 return r; 3736 } 3737 3738 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3739 { 3740 int r = 0; 3741 3742 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3743 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); 3744 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); 3745 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3746 return r; 3747 } 3748 3749 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3750 { 3751 int r = 0; 3752 3753 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3754 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 3755 sizeof(ps->channels)); 3756 ps->flags = kvm->arch.vpit->pit_state.flags; 3757 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3758 memset(&ps->reserved, 0, sizeof(ps->reserved)); 3759 return r; 3760 } 3761 3762 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3763 { 3764 int r = 0, start = 0; 3765 u32 prev_legacy, cur_legacy; 3766 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3767 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 3768 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 3769 if (!prev_legacy && cur_legacy) 3770 start = 1; 3771 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, 3772 sizeof(kvm->arch.vpit->pit_state.channels)); 3773 kvm->arch.vpit->pit_state.flags = ps->flags; 3774 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); 3775 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3776 return r; 3777 } 3778 3779 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 3780 struct kvm_reinject_control *control) 3781 { 3782 if (!kvm->arch.vpit) 3783 return -ENXIO; 3784 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3785 kvm->arch.vpit->pit_state.reinject = control->pit_reinject; 3786 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3787 return 0; 3788 } 3789 3790 /** 3791 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 3792 * @kvm: kvm instance 3793 * @log: slot id and address to which we copy the log 3794 * 3795 * Steps 1-4 below provide general overview of dirty page logging. See 3796 * kvm_get_dirty_log_protect() function description for additional details. 3797 * 3798 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 3799 * always flush the TLB (step 4) even if previous step failed and the dirty 3800 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 3801 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 3802 * writes will be marked dirty for next log read. 3803 * 3804 * 1. Take a snapshot of the bit and clear it if needed. 3805 * 2. Write protect the corresponding page. 3806 * 3. Copy the snapshot to the userspace. 3807 * 4. Flush TLB's if needed. 3808 */ 3809 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 3810 { 3811 bool is_dirty = false; 3812 int r; 3813 3814 mutex_lock(&kvm->slots_lock); 3815 3816 /* 3817 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 3818 */ 3819 if (kvm_x86_ops->flush_log_dirty) 3820 kvm_x86_ops->flush_log_dirty(kvm); 3821 3822 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 3823 3824 /* 3825 * All the TLBs can be flushed out of mmu lock, see the comments in 3826 * kvm_mmu_slot_remove_write_access(). 3827 */ 3828 lockdep_assert_held(&kvm->slots_lock); 3829 if (is_dirty) 3830 kvm_flush_remote_tlbs(kvm); 3831 3832 mutex_unlock(&kvm->slots_lock); 3833 return r; 3834 } 3835 3836 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 3837 bool line_status) 3838 { 3839 if (!irqchip_in_kernel(kvm)) 3840 return -ENXIO; 3841 3842 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 3843 irq_event->irq, irq_event->level, 3844 line_status); 3845 return 0; 3846 } 3847 3848 long kvm_arch_vm_ioctl(struct file *filp, 3849 unsigned int ioctl, unsigned long arg) 3850 { 3851 struct kvm *kvm = filp->private_data; 3852 void __user *argp = (void __user *)arg; 3853 int r = -ENOTTY; 3854 /* 3855 * This union makes it completely explicit to gcc-3.x 3856 * that these two variables' stack usage should be 3857 * combined, not added together. 3858 */ 3859 union { 3860 struct kvm_pit_state ps; 3861 struct kvm_pit_state2 ps2; 3862 struct kvm_pit_config pit_config; 3863 } u; 3864 3865 switch (ioctl) { 3866 case KVM_SET_TSS_ADDR: 3867 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 3868 break; 3869 case KVM_SET_IDENTITY_MAP_ADDR: { 3870 u64 ident_addr; 3871 3872 r = -EFAULT; 3873 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 3874 goto out; 3875 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 3876 break; 3877 } 3878 case KVM_SET_NR_MMU_PAGES: 3879 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 3880 break; 3881 case KVM_GET_NR_MMU_PAGES: 3882 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 3883 break; 3884 case KVM_CREATE_IRQCHIP: { 3885 struct kvm_pic *vpic; 3886 3887 mutex_lock(&kvm->lock); 3888 r = -EEXIST; 3889 if (kvm->arch.vpic) 3890 goto create_irqchip_unlock; 3891 r = -EINVAL; 3892 if (atomic_read(&kvm->online_vcpus)) 3893 goto create_irqchip_unlock; 3894 r = -ENOMEM; 3895 vpic = kvm_create_pic(kvm); 3896 if (vpic) { 3897 r = kvm_ioapic_init(kvm); 3898 if (r) { 3899 mutex_lock(&kvm->slots_lock); 3900 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, 3901 &vpic->dev_master); 3902 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, 3903 &vpic->dev_slave); 3904 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, 3905 &vpic->dev_eclr); 3906 mutex_unlock(&kvm->slots_lock); 3907 kfree(vpic); 3908 goto create_irqchip_unlock; 3909 } 3910 } else 3911 goto create_irqchip_unlock; 3912 smp_wmb(); 3913 kvm->arch.vpic = vpic; 3914 smp_wmb(); 3915 r = kvm_setup_default_irq_routing(kvm); 3916 if (r) { 3917 mutex_lock(&kvm->slots_lock); 3918 mutex_lock(&kvm->irq_lock); 3919 kvm_ioapic_destroy(kvm); 3920 kvm_destroy_pic(kvm); 3921 mutex_unlock(&kvm->irq_lock); 3922 mutex_unlock(&kvm->slots_lock); 3923 } 3924 create_irqchip_unlock: 3925 mutex_unlock(&kvm->lock); 3926 break; 3927 } 3928 case KVM_CREATE_PIT: 3929 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 3930 goto create_pit; 3931 case KVM_CREATE_PIT2: 3932 r = -EFAULT; 3933 if (copy_from_user(&u.pit_config, argp, 3934 sizeof(struct kvm_pit_config))) 3935 goto out; 3936 create_pit: 3937 mutex_lock(&kvm->slots_lock); 3938 r = -EEXIST; 3939 if (kvm->arch.vpit) 3940 goto create_pit_unlock; 3941 r = -ENOMEM; 3942 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 3943 if (kvm->arch.vpit) 3944 r = 0; 3945 create_pit_unlock: 3946 mutex_unlock(&kvm->slots_lock); 3947 break; 3948 case KVM_GET_IRQCHIP: { 3949 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3950 struct kvm_irqchip *chip; 3951 3952 chip = memdup_user(argp, sizeof(*chip)); 3953 if (IS_ERR(chip)) { 3954 r = PTR_ERR(chip); 3955 goto out; 3956 } 3957 3958 r = -ENXIO; 3959 if (!irqchip_in_kernel(kvm)) 3960 goto get_irqchip_out; 3961 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 3962 if (r) 3963 goto get_irqchip_out; 3964 r = -EFAULT; 3965 if (copy_to_user(argp, chip, sizeof *chip)) 3966 goto get_irqchip_out; 3967 r = 0; 3968 get_irqchip_out: 3969 kfree(chip); 3970 break; 3971 } 3972 case KVM_SET_IRQCHIP: { 3973 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3974 struct kvm_irqchip *chip; 3975 3976 chip = memdup_user(argp, sizeof(*chip)); 3977 if (IS_ERR(chip)) { 3978 r = PTR_ERR(chip); 3979 goto out; 3980 } 3981 3982 r = -ENXIO; 3983 if (!irqchip_in_kernel(kvm)) 3984 goto set_irqchip_out; 3985 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 3986 if (r) 3987 goto set_irqchip_out; 3988 r = 0; 3989 set_irqchip_out: 3990 kfree(chip); 3991 break; 3992 } 3993 case KVM_GET_PIT: { 3994 r = -EFAULT; 3995 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 3996 goto out; 3997 r = -ENXIO; 3998 if (!kvm->arch.vpit) 3999 goto out; 4000 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 4001 if (r) 4002 goto out; 4003 r = -EFAULT; 4004 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 4005 goto out; 4006 r = 0; 4007 break; 4008 } 4009 case KVM_SET_PIT: { 4010 r = -EFAULT; 4011 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 4012 goto out; 4013 r = -ENXIO; 4014 if (!kvm->arch.vpit) 4015 goto out; 4016 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 4017 break; 4018 } 4019 case KVM_GET_PIT2: { 4020 r = -ENXIO; 4021 if (!kvm->arch.vpit) 4022 goto out; 4023 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 4024 if (r) 4025 goto out; 4026 r = -EFAULT; 4027 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 4028 goto out; 4029 r = 0; 4030 break; 4031 } 4032 case KVM_SET_PIT2: { 4033 r = -EFAULT; 4034 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 4035 goto out; 4036 r = -ENXIO; 4037 if (!kvm->arch.vpit) 4038 goto out; 4039 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 4040 break; 4041 } 4042 case KVM_REINJECT_CONTROL: { 4043 struct kvm_reinject_control control; 4044 r = -EFAULT; 4045 if (copy_from_user(&control, argp, sizeof(control))) 4046 goto out; 4047 r = kvm_vm_ioctl_reinject(kvm, &control); 4048 break; 4049 } 4050 case KVM_XEN_HVM_CONFIG: { 4051 r = -EFAULT; 4052 if (copy_from_user(&kvm->arch.xen_hvm_config, argp, 4053 sizeof(struct kvm_xen_hvm_config))) 4054 goto out; 4055 r = -EINVAL; 4056 if (kvm->arch.xen_hvm_config.flags) 4057 goto out; 4058 r = 0; 4059 break; 4060 } 4061 case KVM_SET_CLOCK: { 4062 struct kvm_clock_data user_ns; 4063 u64 now_ns; 4064 s64 delta; 4065 4066 r = -EFAULT; 4067 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 4068 goto out; 4069 4070 r = -EINVAL; 4071 if (user_ns.flags) 4072 goto out; 4073 4074 r = 0; 4075 local_irq_disable(); 4076 now_ns = get_kernel_ns(); 4077 delta = user_ns.clock - now_ns; 4078 local_irq_enable(); 4079 kvm->arch.kvmclock_offset = delta; 4080 kvm_gen_update_masterclock(kvm); 4081 break; 4082 } 4083 case KVM_GET_CLOCK: { 4084 struct kvm_clock_data user_ns; 4085 u64 now_ns; 4086 4087 local_irq_disable(); 4088 now_ns = get_kernel_ns(); 4089 user_ns.clock = kvm->arch.kvmclock_offset + now_ns; 4090 local_irq_enable(); 4091 user_ns.flags = 0; 4092 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 4093 4094 r = -EFAULT; 4095 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 4096 goto out; 4097 r = 0; 4098 break; 4099 } 4100 4101 default: 4102 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg); 4103 } 4104 out: 4105 return r; 4106 } 4107 4108 static void kvm_init_msr_list(void) 4109 { 4110 u32 dummy[2]; 4111 unsigned i, j; 4112 4113 /* skip the first msrs in the list. KVM-specific */ 4114 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { 4115 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4116 continue; 4117 4118 /* 4119 * Even MSRs that are valid in the host may not be exposed 4120 * to the guests in some cases. We could work around this 4121 * in VMX with the generic MSR save/load machinery, but it 4122 * is not really worthwhile since it will really only 4123 * happen with nested virtualization. 4124 */ 4125 switch (msrs_to_save[i]) { 4126 case MSR_IA32_BNDCFGS: 4127 if (!kvm_x86_ops->mpx_supported()) 4128 continue; 4129 break; 4130 default: 4131 break; 4132 } 4133 4134 if (j < i) 4135 msrs_to_save[j] = msrs_to_save[i]; 4136 j++; 4137 } 4138 num_msrs_to_save = j; 4139 } 4140 4141 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 4142 const void *v) 4143 { 4144 int handled = 0; 4145 int n; 4146 4147 do { 4148 n = min(len, 8); 4149 if (!(vcpu->arch.apic && 4150 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 4151 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 4152 break; 4153 handled += n; 4154 addr += n; 4155 len -= n; 4156 v += n; 4157 } while (len); 4158 4159 return handled; 4160 } 4161 4162 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4163 { 4164 int handled = 0; 4165 int n; 4166 4167 do { 4168 n = min(len, 8); 4169 if (!(vcpu->arch.apic && 4170 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 4171 addr, n, v)) 4172 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 4173 break; 4174 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); 4175 handled += n; 4176 addr += n; 4177 len -= n; 4178 v += n; 4179 } while (len); 4180 4181 return handled; 4182 } 4183 4184 static void kvm_set_segment(struct kvm_vcpu *vcpu, 4185 struct kvm_segment *var, int seg) 4186 { 4187 kvm_x86_ops->set_segment(vcpu, var, seg); 4188 } 4189 4190 void kvm_get_segment(struct kvm_vcpu *vcpu, 4191 struct kvm_segment *var, int seg) 4192 { 4193 kvm_x86_ops->get_segment(vcpu, var, seg); 4194 } 4195 4196 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 4197 struct x86_exception *exception) 4198 { 4199 gpa_t t_gpa; 4200 4201 BUG_ON(!mmu_is_nested(vcpu)); 4202 4203 /* NPT walks are always user-walks */ 4204 access |= PFERR_USER_MASK; 4205 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); 4206 4207 return t_gpa; 4208 } 4209 4210 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 4211 struct x86_exception *exception) 4212 { 4213 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4214 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4215 } 4216 4217 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 4218 struct x86_exception *exception) 4219 { 4220 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4221 access |= PFERR_FETCH_MASK; 4222 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4223 } 4224 4225 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 4226 struct x86_exception *exception) 4227 { 4228 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4229 access |= PFERR_WRITE_MASK; 4230 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4231 } 4232 4233 /* uses this to access any guest's mapped memory without checking CPL */ 4234 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 4235 struct x86_exception *exception) 4236 { 4237 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 4238 } 4239 4240 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 4241 struct kvm_vcpu *vcpu, u32 access, 4242 struct x86_exception *exception) 4243 { 4244 void *data = val; 4245 int r = X86EMUL_CONTINUE; 4246 4247 while (bytes) { 4248 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 4249 exception); 4250 unsigned offset = addr & (PAGE_SIZE-1); 4251 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 4252 int ret; 4253 4254 if (gpa == UNMAPPED_GVA) 4255 return X86EMUL_PROPAGATE_FAULT; 4256 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data, 4257 offset, toread); 4258 if (ret < 0) { 4259 r = X86EMUL_IO_NEEDED; 4260 goto out; 4261 } 4262 4263 bytes -= toread; 4264 data += toread; 4265 addr += toread; 4266 } 4267 out: 4268 return r; 4269 } 4270 4271 /* used for instruction fetching */ 4272 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4273 gva_t addr, void *val, unsigned int bytes, 4274 struct x86_exception *exception) 4275 { 4276 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4277 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4278 unsigned offset; 4279 int ret; 4280 4281 /* Inline kvm_read_guest_virt_helper for speed. */ 4282 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 4283 exception); 4284 if (unlikely(gpa == UNMAPPED_GVA)) 4285 return X86EMUL_PROPAGATE_FAULT; 4286 4287 offset = addr & (PAGE_SIZE-1); 4288 if (WARN_ON(offset + bytes > PAGE_SIZE)) 4289 bytes = (unsigned)PAGE_SIZE - offset; 4290 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val, 4291 offset, bytes); 4292 if (unlikely(ret < 0)) 4293 return X86EMUL_IO_NEEDED; 4294 4295 return X86EMUL_CONTINUE; 4296 } 4297 4298 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4299 gva_t addr, void *val, unsigned int bytes, 4300 struct x86_exception *exception) 4301 { 4302 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4303 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4304 4305 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4306 exception); 4307 } 4308 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4309 4310 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4311 gva_t addr, void *val, unsigned int bytes, 4312 struct x86_exception *exception) 4313 { 4314 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4315 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4316 } 4317 4318 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4319 gva_t addr, void *val, 4320 unsigned int bytes, 4321 struct x86_exception *exception) 4322 { 4323 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4324 void *data = val; 4325 int r = X86EMUL_CONTINUE; 4326 4327 while (bytes) { 4328 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4329 PFERR_WRITE_MASK, 4330 exception); 4331 unsigned offset = addr & (PAGE_SIZE-1); 4332 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4333 int ret; 4334 4335 if (gpa == UNMAPPED_GVA) 4336 return X86EMUL_PROPAGATE_FAULT; 4337 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); 4338 if (ret < 0) { 4339 r = X86EMUL_IO_NEEDED; 4340 goto out; 4341 } 4342 4343 bytes -= towrite; 4344 data += towrite; 4345 addr += towrite; 4346 } 4347 out: 4348 return r; 4349 } 4350 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4351 4352 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4353 gpa_t *gpa, struct x86_exception *exception, 4354 bool write) 4355 { 4356 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4357 | (write ? PFERR_WRITE_MASK : 0); 4358 4359 if (vcpu_match_mmio_gva(vcpu, gva) 4360 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4361 vcpu->arch.access, access)) { 4362 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4363 (gva & (PAGE_SIZE - 1)); 4364 trace_vcpu_match_mmio(gva, *gpa, write, false); 4365 return 1; 4366 } 4367 4368 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4369 4370 if (*gpa == UNMAPPED_GVA) 4371 return -1; 4372 4373 /* For APIC access vmexit */ 4374 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4375 return 1; 4376 4377 if (vcpu_match_mmio_gpa(vcpu, *gpa)) { 4378 trace_vcpu_match_mmio(gva, *gpa, write, true); 4379 return 1; 4380 } 4381 4382 return 0; 4383 } 4384 4385 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4386 const void *val, int bytes) 4387 { 4388 int ret; 4389 4390 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); 4391 if (ret < 0) 4392 return 0; 4393 kvm_mmu_pte_write(vcpu, gpa, val, bytes); 4394 return 1; 4395 } 4396 4397 struct read_write_emulator_ops { 4398 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4399 int bytes); 4400 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4401 void *val, int bytes); 4402 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4403 int bytes, void *val); 4404 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4405 void *val, int bytes); 4406 bool write; 4407 }; 4408 4409 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4410 { 4411 if (vcpu->mmio_read_completed) { 4412 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4413 vcpu->mmio_fragments[0].gpa, *(u64 *)val); 4414 vcpu->mmio_read_completed = 0; 4415 return 1; 4416 } 4417 4418 return 0; 4419 } 4420 4421 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4422 void *val, int bytes) 4423 { 4424 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes); 4425 } 4426 4427 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4428 void *val, int bytes) 4429 { 4430 return emulator_write_phys(vcpu, gpa, val, bytes); 4431 } 4432 4433 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4434 { 4435 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); 4436 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4437 } 4438 4439 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4440 void *val, int bytes) 4441 { 4442 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); 4443 return X86EMUL_IO_NEEDED; 4444 } 4445 4446 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4447 void *val, int bytes) 4448 { 4449 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4450 4451 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4452 return X86EMUL_CONTINUE; 4453 } 4454 4455 static const struct read_write_emulator_ops read_emultor = { 4456 .read_write_prepare = read_prepare, 4457 .read_write_emulate = read_emulate, 4458 .read_write_mmio = vcpu_mmio_read, 4459 .read_write_exit_mmio = read_exit_mmio, 4460 }; 4461 4462 static const struct read_write_emulator_ops write_emultor = { 4463 .read_write_emulate = write_emulate, 4464 .read_write_mmio = write_mmio, 4465 .read_write_exit_mmio = write_exit_mmio, 4466 .write = true, 4467 }; 4468 4469 static int emulator_read_write_onepage(unsigned long addr, void *val, 4470 unsigned int bytes, 4471 struct x86_exception *exception, 4472 struct kvm_vcpu *vcpu, 4473 const struct read_write_emulator_ops *ops) 4474 { 4475 gpa_t gpa; 4476 int handled, ret; 4477 bool write = ops->write; 4478 struct kvm_mmio_fragment *frag; 4479 4480 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 4481 4482 if (ret < 0) 4483 return X86EMUL_PROPAGATE_FAULT; 4484 4485 /* For APIC access vmexit */ 4486 if (ret) 4487 goto mmio; 4488 4489 if (ops->read_write_emulate(vcpu, gpa, val, bytes)) 4490 return X86EMUL_CONTINUE; 4491 4492 mmio: 4493 /* 4494 * Is this MMIO handled locally? 4495 */ 4496 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 4497 if (handled == bytes) 4498 return X86EMUL_CONTINUE; 4499 4500 gpa += handled; 4501 bytes -= handled; 4502 val += handled; 4503 4504 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 4505 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 4506 frag->gpa = gpa; 4507 frag->data = val; 4508 frag->len = bytes; 4509 return X86EMUL_CONTINUE; 4510 } 4511 4512 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 4513 unsigned long addr, 4514 void *val, unsigned int bytes, 4515 struct x86_exception *exception, 4516 const struct read_write_emulator_ops *ops) 4517 { 4518 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4519 gpa_t gpa; 4520 int rc; 4521 4522 if (ops->read_write_prepare && 4523 ops->read_write_prepare(vcpu, val, bytes)) 4524 return X86EMUL_CONTINUE; 4525 4526 vcpu->mmio_nr_fragments = 0; 4527 4528 /* Crossing a page boundary? */ 4529 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 4530 int now; 4531 4532 now = -addr & ~PAGE_MASK; 4533 rc = emulator_read_write_onepage(addr, val, now, exception, 4534 vcpu, ops); 4535 4536 if (rc != X86EMUL_CONTINUE) 4537 return rc; 4538 addr += now; 4539 if (ctxt->mode != X86EMUL_MODE_PROT64) 4540 addr = (u32)addr; 4541 val += now; 4542 bytes -= now; 4543 } 4544 4545 rc = emulator_read_write_onepage(addr, val, bytes, exception, 4546 vcpu, ops); 4547 if (rc != X86EMUL_CONTINUE) 4548 return rc; 4549 4550 if (!vcpu->mmio_nr_fragments) 4551 return rc; 4552 4553 gpa = vcpu->mmio_fragments[0].gpa; 4554 4555 vcpu->mmio_needed = 1; 4556 vcpu->mmio_cur_fragment = 0; 4557 4558 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 4559 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 4560 vcpu->run->exit_reason = KVM_EXIT_MMIO; 4561 vcpu->run->mmio.phys_addr = gpa; 4562 4563 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 4564 } 4565 4566 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 4567 unsigned long addr, 4568 void *val, 4569 unsigned int bytes, 4570 struct x86_exception *exception) 4571 { 4572 return emulator_read_write(ctxt, addr, val, bytes, 4573 exception, &read_emultor); 4574 } 4575 4576 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 4577 unsigned long addr, 4578 const void *val, 4579 unsigned int bytes, 4580 struct x86_exception *exception) 4581 { 4582 return emulator_read_write(ctxt, addr, (void *)val, bytes, 4583 exception, &write_emultor); 4584 } 4585 4586 #define CMPXCHG_TYPE(t, ptr, old, new) \ 4587 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 4588 4589 #ifdef CONFIG_X86_64 4590 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 4591 #else 4592 # define CMPXCHG64(ptr, old, new) \ 4593 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 4594 #endif 4595 4596 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 4597 unsigned long addr, 4598 const void *old, 4599 const void *new, 4600 unsigned int bytes, 4601 struct x86_exception *exception) 4602 { 4603 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4604 gpa_t gpa; 4605 struct page *page; 4606 char *kaddr; 4607 bool exchanged; 4608 4609 /* guests cmpxchg8b have to be emulated atomically */ 4610 if (bytes > 8 || (bytes & (bytes - 1))) 4611 goto emul_write; 4612 4613 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 4614 4615 if (gpa == UNMAPPED_GVA || 4616 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4617 goto emul_write; 4618 4619 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 4620 goto emul_write; 4621 4622 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); 4623 if (is_error_page(page)) 4624 goto emul_write; 4625 4626 kaddr = kmap_atomic(page); 4627 kaddr += offset_in_page(gpa); 4628 switch (bytes) { 4629 case 1: 4630 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 4631 break; 4632 case 2: 4633 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 4634 break; 4635 case 4: 4636 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 4637 break; 4638 case 8: 4639 exchanged = CMPXCHG64(kaddr, old, new); 4640 break; 4641 default: 4642 BUG(); 4643 } 4644 kunmap_atomic(kaddr); 4645 kvm_release_page_dirty(page); 4646 4647 if (!exchanged) 4648 return X86EMUL_CMPXCHG_FAILED; 4649 4650 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT); 4651 kvm_mmu_pte_write(vcpu, gpa, new, bytes); 4652 4653 return X86EMUL_CONTINUE; 4654 4655 emul_write: 4656 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 4657 4658 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 4659 } 4660 4661 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 4662 { 4663 /* TODO: String I/O for in kernel device */ 4664 int r; 4665 4666 if (vcpu->arch.pio.in) 4667 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 4668 vcpu->arch.pio.size, pd); 4669 else 4670 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 4671 vcpu->arch.pio.port, vcpu->arch.pio.size, 4672 pd); 4673 return r; 4674 } 4675 4676 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 4677 unsigned short port, void *val, 4678 unsigned int count, bool in) 4679 { 4680 vcpu->arch.pio.port = port; 4681 vcpu->arch.pio.in = in; 4682 vcpu->arch.pio.count = count; 4683 vcpu->arch.pio.size = size; 4684 4685 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 4686 vcpu->arch.pio.count = 0; 4687 return 1; 4688 } 4689 4690 vcpu->run->exit_reason = KVM_EXIT_IO; 4691 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 4692 vcpu->run->io.size = size; 4693 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 4694 vcpu->run->io.count = count; 4695 vcpu->run->io.port = port; 4696 4697 return 0; 4698 } 4699 4700 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 4701 int size, unsigned short port, void *val, 4702 unsigned int count) 4703 { 4704 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4705 int ret; 4706 4707 if (vcpu->arch.pio.count) 4708 goto data_avail; 4709 4710 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 4711 if (ret) { 4712 data_avail: 4713 memcpy(val, vcpu->arch.pio_data, size * count); 4714 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 4715 vcpu->arch.pio.count = 0; 4716 return 1; 4717 } 4718 4719 return 0; 4720 } 4721 4722 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 4723 int size, unsigned short port, 4724 const void *val, unsigned int count) 4725 { 4726 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4727 4728 memcpy(vcpu->arch.pio_data, val, size * count); 4729 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 4730 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 4731 } 4732 4733 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 4734 { 4735 return kvm_x86_ops->get_segment_base(vcpu, seg); 4736 } 4737 4738 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 4739 { 4740 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 4741 } 4742 4743 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 4744 { 4745 if (!need_emulate_wbinvd(vcpu)) 4746 return X86EMUL_CONTINUE; 4747 4748 if (kvm_x86_ops->has_wbinvd_exit()) { 4749 int cpu = get_cpu(); 4750 4751 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4752 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 4753 wbinvd_ipi, NULL, 1); 4754 put_cpu(); 4755 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 4756 } else 4757 wbinvd(); 4758 return X86EMUL_CONTINUE; 4759 } 4760 4761 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 4762 { 4763 kvm_x86_ops->skip_emulated_instruction(vcpu); 4764 return kvm_emulate_wbinvd_noskip(vcpu); 4765 } 4766 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 4767 4768 4769 4770 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 4771 { 4772 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 4773 } 4774 4775 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 4776 unsigned long *dest) 4777 { 4778 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 4779 } 4780 4781 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 4782 unsigned long value) 4783 { 4784 4785 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 4786 } 4787 4788 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 4789 { 4790 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 4791 } 4792 4793 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 4794 { 4795 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4796 unsigned long value; 4797 4798 switch (cr) { 4799 case 0: 4800 value = kvm_read_cr0(vcpu); 4801 break; 4802 case 2: 4803 value = vcpu->arch.cr2; 4804 break; 4805 case 3: 4806 value = kvm_read_cr3(vcpu); 4807 break; 4808 case 4: 4809 value = kvm_read_cr4(vcpu); 4810 break; 4811 case 8: 4812 value = kvm_get_cr8(vcpu); 4813 break; 4814 default: 4815 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4816 return 0; 4817 } 4818 4819 return value; 4820 } 4821 4822 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 4823 { 4824 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4825 int res = 0; 4826 4827 switch (cr) { 4828 case 0: 4829 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 4830 break; 4831 case 2: 4832 vcpu->arch.cr2 = val; 4833 break; 4834 case 3: 4835 res = kvm_set_cr3(vcpu, val); 4836 break; 4837 case 4: 4838 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 4839 break; 4840 case 8: 4841 res = kvm_set_cr8(vcpu, val); 4842 break; 4843 default: 4844 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4845 res = -1; 4846 } 4847 4848 return res; 4849 } 4850 4851 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 4852 { 4853 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 4854 } 4855 4856 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4857 { 4858 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 4859 } 4860 4861 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4862 { 4863 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 4864 } 4865 4866 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4867 { 4868 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 4869 } 4870 4871 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4872 { 4873 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 4874 } 4875 4876 static unsigned long emulator_get_cached_segment_base( 4877 struct x86_emulate_ctxt *ctxt, int seg) 4878 { 4879 return get_segment_base(emul_to_vcpu(ctxt), seg); 4880 } 4881 4882 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 4883 struct desc_struct *desc, u32 *base3, 4884 int seg) 4885 { 4886 struct kvm_segment var; 4887 4888 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 4889 *selector = var.selector; 4890 4891 if (var.unusable) { 4892 memset(desc, 0, sizeof(*desc)); 4893 return false; 4894 } 4895 4896 if (var.g) 4897 var.limit >>= 12; 4898 set_desc_limit(desc, var.limit); 4899 set_desc_base(desc, (unsigned long)var.base); 4900 #ifdef CONFIG_X86_64 4901 if (base3) 4902 *base3 = var.base >> 32; 4903 #endif 4904 desc->type = var.type; 4905 desc->s = var.s; 4906 desc->dpl = var.dpl; 4907 desc->p = var.present; 4908 desc->avl = var.avl; 4909 desc->l = var.l; 4910 desc->d = var.db; 4911 desc->g = var.g; 4912 4913 return true; 4914 } 4915 4916 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 4917 struct desc_struct *desc, u32 base3, 4918 int seg) 4919 { 4920 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4921 struct kvm_segment var; 4922 4923 var.selector = selector; 4924 var.base = get_desc_base(desc); 4925 #ifdef CONFIG_X86_64 4926 var.base |= ((u64)base3) << 32; 4927 #endif 4928 var.limit = get_desc_limit(desc); 4929 if (desc->g) 4930 var.limit = (var.limit << 12) | 0xfff; 4931 var.type = desc->type; 4932 var.dpl = desc->dpl; 4933 var.db = desc->d; 4934 var.s = desc->s; 4935 var.l = desc->l; 4936 var.g = desc->g; 4937 var.avl = desc->avl; 4938 var.present = desc->p; 4939 var.unusable = !var.present; 4940 var.padding = 0; 4941 4942 kvm_set_segment(vcpu, &var, seg); 4943 return; 4944 } 4945 4946 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 4947 u32 msr_index, u64 *pdata) 4948 { 4949 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); 4950 } 4951 4952 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 4953 u32 msr_index, u64 data) 4954 { 4955 struct msr_data msr; 4956 4957 msr.data = data; 4958 msr.index = msr_index; 4959 msr.host_initiated = false; 4960 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 4961 } 4962 4963 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 4964 u32 pmc) 4965 { 4966 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc); 4967 } 4968 4969 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 4970 u32 pmc, u64 *pdata) 4971 { 4972 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata); 4973 } 4974 4975 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 4976 { 4977 emul_to_vcpu(ctxt)->arch.halt_request = 1; 4978 } 4979 4980 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) 4981 { 4982 preempt_disable(); 4983 kvm_load_guest_fpu(emul_to_vcpu(ctxt)); 4984 /* 4985 * CR0.TS may reference the host fpu state, not the guest fpu state, 4986 * so it may be clear at this point. 4987 */ 4988 clts(); 4989 } 4990 4991 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) 4992 { 4993 preempt_enable(); 4994 } 4995 4996 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 4997 struct x86_instruction_info *info, 4998 enum x86_intercept_stage stage) 4999 { 5000 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 5001 } 5002 5003 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 5004 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) 5005 { 5006 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); 5007 } 5008 5009 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 5010 { 5011 return kvm_register_read(emul_to_vcpu(ctxt), reg); 5012 } 5013 5014 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 5015 { 5016 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 5017 } 5018 5019 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 5020 { 5021 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 5022 } 5023 5024 static const struct x86_emulate_ops emulate_ops = { 5025 .read_gpr = emulator_read_gpr, 5026 .write_gpr = emulator_write_gpr, 5027 .read_std = kvm_read_guest_virt_system, 5028 .write_std = kvm_write_guest_virt_system, 5029 .fetch = kvm_fetch_guest_virt, 5030 .read_emulated = emulator_read_emulated, 5031 .write_emulated = emulator_write_emulated, 5032 .cmpxchg_emulated = emulator_cmpxchg_emulated, 5033 .invlpg = emulator_invlpg, 5034 .pio_in_emulated = emulator_pio_in_emulated, 5035 .pio_out_emulated = emulator_pio_out_emulated, 5036 .get_segment = emulator_get_segment, 5037 .set_segment = emulator_set_segment, 5038 .get_cached_segment_base = emulator_get_cached_segment_base, 5039 .get_gdt = emulator_get_gdt, 5040 .get_idt = emulator_get_idt, 5041 .set_gdt = emulator_set_gdt, 5042 .set_idt = emulator_set_idt, 5043 .get_cr = emulator_get_cr, 5044 .set_cr = emulator_set_cr, 5045 .cpl = emulator_get_cpl, 5046 .get_dr = emulator_get_dr, 5047 .set_dr = emulator_set_dr, 5048 .set_msr = emulator_set_msr, 5049 .get_msr = emulator_get_msr, 5050 .check_pmc = emulator_check_pmc, 5051 .read_pmc = emulator_read_pmc, 5052 .halt = emulator_halt, 5053 .wbinvd = emulator_wbinvd, 5054 .fix_hypercall = emulator_fix_hypercall, 5055 .get_fpu = emulator_get_fpu, 5056 .put_fpu = emulator_put_fpu, 5057 .intercept = emulator_intercept, 5058 .get_cpuid = emulator_get_cpuid, 5059 .set_nmi_mask = emulator_set_nmi_mask, 5060 }; 5061 5062 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 5063 { 5064 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 5065 /* 5066 * an sti; sti; sequence only disable interrupts for the first 5067 * instruction. So, if the last instruction, be it emulated or 5068 * not, left the system with the INT_STI flag enabled, it 5069 * means that the last instruction is an sti. We should not 5070 * leave the flag on in this case. The same goes for mov ss 5071 */ 5072 if (int_shadow & mask) 5073 mask = 0; 5074 if (unlikely(int_shadow || mask)) { 5075 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 5076 if (!mask) 5077 kvm_make_request(KVM_REQ_EVENT, vcpu); 5078 } 5079 } 5080 5081 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 5082 { 5083 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5084 if (ctxt->exception.vector == PF_VECTOR) 5085 return kvm_propagate_fault(vcpu, &ctxt->exception); 5086 5087 if (ctxt->exception.error_code_valid) 5088 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 5089 ctxt->exception.error_code); 5090 else 5091 kvm_queue_exception(vcpu, ctxt->exception.vector); 5092 return false; 5093 } 5094 5095 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 5096 { 5097 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5098 int cs_db, cs_l; 5099 5100 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 5101 5102 ctxt->eflags = kvm_get_rflags(vcpu); 5103 ctxt->eip = kvm_rip_read(vcpu); 5104 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 5105 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 5106 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 5107 cs_db ? X86EMUL_MODE_PROT32 : 5108 X86EMUL_MODE_PROT16; 5109 ctxt->guest_mode = is_guest_mode(vcpu); 5110 5111 init_decode_cache(ctxt); 5112 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5113 } 5114 5115 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 5116 { 5117 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5118 int ret; 5119 5120 init_emulate_ctxt(vcpu); 5121 5122 ctxt->op_bytes = 2; 5123 ctxt->ad_bytes = 2; 5124 ctxt->_eip = ctxt->eip + inc_eip; 5125 ret = emulate_int_real(ctxt, irq); 5126 5127 if (ret != X86EMUL_CONTINUE) 5128 return EMULATE_FAIL; 5129 5130 ctxt->eip = ctxt->_eip; 5131 kvm_rip_write(vcpu, ctxt->eip); 5132 kvm_set_rflags(vcpu, ctxt->eflags); 5133 5134 if (irq == NMI_VECTOR) 5135 vcpu->arch.nmi_pending = 0; 5136 else 5137 vcpu->arch.interrupt.pending = false; 5138 5139 return EMULATE_DONE; 5140 } 5141 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 5142 5143 static int handle_emulation_failure(struct kvm_vcpu *vcpu) 5144 { 5145 int r = EMULATE_DONE; 5146 5147 ++vcpu->stat.insn_emulation_fail; 5148 trace_kvm_emulate_insn_failed(vcpu); 5149 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 5150 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5151 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 5152 vcpu->run->internal.ndata = 0; 5153 r = EMULATE_FAIL; 5154 } 5155 kvm_queue_exception(vcpu, UD_VECTOR); 5156 5157 return r; 5158 } 5159 5160 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 5161 bool write_fault_to_shadow_pgtable, 5162 int emulation_type) 5163 { 5164 gpa_t gpa = cr2; 5165 pfn_t pfn; 5166 5167 if (emulation_type & EMULTYPE_NO_REEXECUTE) 5168 return false; 5169 5170 if (!vcpu->arch.mmu.direct_map) { 5171 /* 5172 * Write permission should be allowed since only 5173 * write access need to be emulated. 5174 */ 5175 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5176 5177 /* 5178 * If the mapping is invalid in guest, let cpu retry 5179 * it to generate fault. 5180 */ 5181 if (gpa == UNMAPPED_GVA) 5182 return true; 5183 } 5184 5185 /* 5186 * Do not retry the unhandleable instruction if it faults on the 5187 * readonly host memory, otherwise it will goto a infinite loop: 5188 * retry instruction -> write #PF -> emulation fail -> retry 5189 * instruction -> ... 5190 */ 5191 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 5192 5193 /* 5194 * If the instruction failed on the error pfn, it can not be fixed, 5195 * report the error to userspace. 5196 */ 5197 if (is_error_noslot_pfn(pfn)) 5198 return false; 5199 5200 kvm_release_pfn_clean(pfn); 5201 5202 /* The instructions are well-emulated on direct mmu. */ 5203 if (vcpu->arch.mmu.direct_map) { 5204 unsigned int indirect_shadow_pages; 5205 5206 spin_lock(&vcpu->kvm->mmu_lock); 5207 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 5208 spin_unlock(&vcpu->kvm->mmu_lock); 5209 5210 if (indirect_shadow_pages) 5211 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5212 5213 return true; 5214 } 5215 5216 /* 5217 * if emulation was due to access to shadowed page table 5218 * and it failed try to unshadow page and re-enter the 5219 * guest to let CPU execute the instruction. 5220 */ 5221 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5222 5223 /* 5224 * If the access faults on its page table, it can not 5225 * be fixed by unprotecting shadow page and it should 5226 * be reported to userspace. 5227 */ 5228 return !write_fault_to_shadow_pgtable; 5229 } 5230 5231 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5232 unsigned long cr2, int emulation_type) 5233 { 5234 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5235 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5236 5237 last_retry_eip = vcpu->arch.last_retry_eip; 5238 last_retry_addr = vcpu->arch.last_retry_addr; 5239 5240 /* 5241 * If the emulation is caused by #PF and it is non-page_table 5242 * writing instruction, it means the VM-EXIT is caused by shadow 5243 * page protected, we can zap the shadow page and retry this 5244 * instruction directly. 5245 * 5246 * Note: if the guest uses a non-page-table modifying instruction 5247 * on the PDE that points to the instruction, then we will unmap 5248 * the instruction and go to an infinite loop. So, we cache the 5249 * last retried eip and the last fault address, if we meet the eip 5250 * and the address again, we can break out of the potential infinite 5251 * loop. 5252 */ 5253 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5254 5255 if (!(emulation_type & EMULTYPE_RETRY)) 5256 return false; 5257 5258 if (x86_page_table_writing_insn(ctxt)) 5259 return false; 5260 5261 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5262 return false; 5263 5264 vcpu->arch.last_retry_eip = ctxt->eip; 5265 vcpu->arch.last_retry_addr = cr2; 5266 5267 if (!vcpu->arch.mmu.direct_map) 5268 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5269 5270 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5271 5272 return true; 5273 } 5274 5275 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5276 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5277 5278 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5279 unsigned long *db) 5280 { 5281 u32 dr6 = 0; 5282 int i; 5283 u32 enable, rwlen; 5284 5285 enable = dr7; 5286 rwlen = dr7 >> 16; 5287 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5288 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5289 dr6 |= (1 << i); 5290 return dr6; 5291 } 5292 5293 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) 5294 { 5295 struct kvm_run *kvm_run = vcpu->run; 5296 5297 /* 5298 * rflags is the old, "raw" value of the flags. The new value has 5299 * not been saved yet. 5300 * 5301 * This is correct even for TF set by the guest, because "the 5302 * processor will not generate this exception after the instruction 5303 * that sets the TF flag". 5304 */ 5305 if (unlikely(rflags & X86_EFLAGS_TF)) { 5306 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5307 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | 5308 DR6_RTM; 5309 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5310 kvm_run->debug.arch.exception = DB_VECTOR; 5311 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5312 *r = EMULATE_USER_EXIT; 5313 } else { 5314 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; 5315 /* 5316 * "Certain debug exceptions may clear bit 0-3. The 5317 * remaining contents of the DR6 register are never 5318 * cleared by the processor". 5319 */ 5320 vcpu->arch.dr6 &= ~15; 5321 vcpu->arch.dr6 |= DR6_BS | DR6_RTM; 5322 kvm_queue_exception(vcpu, DB_VECTOR); 5323 } 5324 } 5325 } 5326 5327 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5328 { 5329 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5330 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5331 struct kvm_run *kvm_run = vcpu->run; 5332 unsigned long eip = kvm_get_linear_rip(vcpu); 5333 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5334 vcpu->arch.guest_debug_dr7, 5335 vcpu->arch.eff_db); 5336 5337 if (dr6 != 0) { 5338 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 5339 kvm_run->debug.arch.pc = eip; 5340 kvm_run->debug.arch.exception = DB_VECTOR; 5341 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5342 *r = EMULATE_USER_EXIT; 5343 return true; 5344 } 5345 } 5346 5347 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 5348 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 5349 unsigned long eip = kvm_get_linear_rip(vcpu); 5350 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5351 vcpu->arch.dr7, 5352 vcpu->arch.db); 5353 5354 if (dr6 != 0) { 5355 vcpu->arch.dr6 &= ~15; 5356 vcpu->arch.dr6 |= dr6 | DR6_RTM; 5357 kvm_queue_exception(vcpu, DB_VECTOR); 5358 *r = EMULATE_DONE; 5359 return true; 5360 } 5361 } 5362 5363 return false; 5364 } 5365 5366 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 5367 unsigned long cr2, 5368 int emulation_type, 5369 void *insn, 5370 int insn_len) 5371 { 5372 int r; 5373 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5374 bool writeback = true; 5375 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 5376 5377 /* 5378 * Clear write_fault_to_shadow_pgtable here to ensure it is 5379 * never reused. 5380 */ 5381 vcpu->arch.write_fault_to_shadow_pgtable = false; 5382 kvm_clear_exception_queue(vcpu); 5383 5384 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 5385 init_emulate_ctxt(vcpu); 5386 5387 /* 5388 * We will reenter on the same instruction since 5389 * we do not set complete_userspace_io. This does not 5390 * handle watchpoints yet, those would be handled in 5391 * the emulate_ops. 5392 */ 5393 if (kvm_vcpu_check_breakpoint(vcpu, &r)) 5394 return r; 5395 5396 ctxt->interruptibility = 0; 5397 ctxt->have_exception = false; 5398 ctxt->exception.vector = -1; 5399 ctxt->perm_ok = false; 5400 5401 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 5402 5403 r = x86_decode_insn(ctxt, insn, insn_len); 5404 5405 trace_kvm_emulate_insn_start(vcpu); 5406 ++vcpu->stat.insn_emulation; 5407 if (r != EMULATION_OK) { 5408 if (emulation_type & EMULTYPE_TRAP_UD) 5409 return EMULATE_FAIL; 5410 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5411 emulation_type)) 5412 return EMULATE_DONE; 5413 if (emulation_type & EMULTYPE_SKIP) 5414 return EMULATE_FAIL; 5415 return handle_emulation_failure(vcpu); 5416 } 5417 } 5418 5419 if (emulation_type & EMULTYPE_SKIP) { 5420 kvm_rip_write(vcpu, ctxt->_eip); 5421 if (ctxt->eflags & X86_EFLAGS_RF) 5422 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 5423 return EMULATE_DONE; 5424 } 5425 5426 if (retry_instruction(ctxt, cr2, emulation_type)) 5427 return EMULATE_DONE; 5428 5429 /* this is needed for vmware backdoor interface to work since it 5430 changes registers values during IO operation */ 5431 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 5432 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5433 emulator_invalidate_register_cache(ctxt); 5434 } 5435 5436 restart: 5437 r = x86_emulate_insn(ctxt); 5438 5439 if (r == EMULATION_INTERCEPTED) 5440 return EMULATE_DONE; 5441 5442 if (r == EMULATION_FAILED) { 5443 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5444 emulation_type)) 5445 return EMULATE_DONE; 5446 5447 return handle_emulation_failure(vcpu); 5448 } 5449 5450 if (ctxt->have_exception) { 5451 r = EMULATE_DONE; 5452 if (inject_emulated_exception(vcpu)) 5453 return r; 5454 } else if (vcpu->arch.pio.count) { 5455 if (!vcpu->arch.pio.in) { 5456 /* FIXME: return into emulator if single-stepping. */ 5457 vcpu->arch.pio.count = 0; 5458 } else { 5459 writeback = false; 5460 vcpu->arch.complete_userspace_io = complete_emulated_pio; 5461 } 5462 r = EMULATE_USER_EXIT; 5463 } else if (vcpu->mmio_needed) { 5464 if (!vcpu->mmio_is_write) 5465 writeback = false; 5466 r = EMULATE_USER_EXIT; 5467 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 5468 } else if (r == EMULATION_RESTART) 5469 goto restart; 5470 else 5471 r = EMULATE_DONE; 5472 5473 if (writeback) { 5474 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5475 toggle_interruptibility(vcpu, ctxt->interruptibility); 5476 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 5477 kvm_rip_write(vcpu, ctxt->eip); 5478 if (r == EMULATE_DONE) 5479 kvm_vcpu_check_singlestep(vcpu, rflags, &r); 5480 if (!ctxt->have_exception || 5481 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 5482 __kvm_set_rflags(vcpu, ctxt->eflags); 5483 5484 /* 5485 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 5486 * do nothing, and it will be requested again as soon as 5487 * the shadow expires. But we still need to check here, 5488 * because POPF has no interrupt shadow. 5489 */ 5490 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 5491 kvm_make_request(KVM_REQ_EVENT, vcpu); 5492 } else 5493 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 5494 5495 return r; 5496 } 5497 EXPORT_SYMBOL_GPL(x86_emulate_instruction); 5498 5499 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) 5500 { 5501 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 5502 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 5503 size, port, &val, 1); 5504 /* do not return to emulator after return from userspace */ 5505 vcpu->arch.pio.count = 0; 5506 return ret; 5507 } 5508 EXPORT_SYMBOL_GPL(kvm_fast_pio_out); 5509 5510 static void tsc_bad(void *info) 5511 { 5512 __this_cpu_write(cpu_tsc_khz, 0); 5513 } 5514 5515 static void tsc_khz_changed(void *data) 5516 { 5517 struct cpufreq_freqs *freq = data; 5518 unsigned long khz = 0; 5519 5520 if (data) 5521 khz = freq->new; 5522 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5523 khz = cpufreq_quick_get(raw_smp_processor_id()); 5524 if (!khz) 5525 khz = tsc_khz; 5526 __this_cpu_write(cpu_tsc_khz, khz); 5527 } 5528 5529 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 5530 void *data) 5531 { 5532 struct cpufreq_freqs *freq = data; 5533 struct kvm *kvm; 5534 struct kvm_vcpu *vcpu; 5535 int i, send_ipi = 0; 5536 5537 /* 5538 * We allow guests to temporarily run on slowing clocks, 5539 * provided we notify them after, or to run on accelerating 5540 * clocks, provided we notify them before. Thus time never 5541 * goes backwards. 5542 * 5543 * However, we have a problem. We can't atomically update 5544 * the frequency of a given CPU from this function; it is 5545 * merely a notifier, which can be called from any CPU. 5546 * Changing the TSC frequency at arbitrary points in time 5547 * requires a recomputation of local variables related to 5548 * the TSC for each VCPU. We must flag these local variables 5549 * to be updated and be sure the update takes place with the 5550 * new frequency before any guests proceed. 5551 * 5552 * Unfortunately, the combination of hotplug CPU and frequency 5553 * change creates an intractable locking scenario; the order 5554 * of when these callouts happen is undefined with respect to 5555 * CPU hotplug, and they can race with each other. As such, 5556 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 5557 * undefined; you can actually have a CPU frequency change take 5558 * place in between the computation of X and the setting of the 5559 * variable. To protect against this problem, all updates of 5560 * the per_cpu tsc_khz variable are done in an interrupt 5561 * protected IPI, and all callers wishing to update the value 5562 * must wait for a synchronous IPI to complete (which is trivial 5563 * if the caller is on the CPU already). This establishes the 5564 * necessary total order on variable updates. 5565 * 5566 * Note that because a guest time update may take place 5567 * anytime after the setting of the VCPU's request bit, the 5568 * correct TSC value must be set before the request. However, 5569 * to ensure the update actually makes it to any guest which 5570 * starts running in hardware virtualization between the set 5571 * and the acquisition of the spinlock, we must also ping the 5572 * CPU after setting the request bit. 5573 * 5574 */ 5575 5576 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 5577 return 0; 5578 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 5579 return 0; 5580 5581 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5582 5583 spin_lock(&kvm_lock); 5584 list_for_each_entry(kvm, &vm_list, vm_list) { 5585 kvm_for_each_vcpu(i, vcpu, kvm) { 5586 if (vcpu->cpu != freq->cpu) 5587 continue; 5588 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5589 if (vcpu->cpu != smp_processor_id()) 5590 send_ipi = 1; 5591 } 5592 } 5593 spin_unlock(&kvm_lock); 5594 5595 if (freq->old < freq->new && send_ipi) { 5596 /* 5597 * We upscale the frequency. Must make the guest 5598 * doesn't see old kvmclock values while running with 5599 * the new frequency, otherwise we risk the guest sees 5600 * time go backwards. 5601 * 5602 * In case we update the frequency for another cpu 5603 * (which might be in guest context) send an interrupt 5604 * to kick the cpu out of guest context. Next time 5605 * guest context is entered kvmclock will be updated, 5606 * so the guest will not see stale values. 5607 */ 5608 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5609 } 5610 return 0; 5611 } 5612 5613 static struct notifier_block kvmclock_cpufreq_notifier_block = { 5614 .notifier_call = kvmclock_cpufreq_notifier 5615 }; 5616 5617 static int kvmclock_cpu_notifier(struct notifier_block *nfb, 5618 unsigned long action, void *hcpu) 5619 { 5620 unsigned int cpu = (unsigned long)hcpu; 5621 5622 switch (action) { 5623 case CPU_ONLINE: 5624 case CPU_DOWN_FAILED: 5625 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5626 break; 5627 case CPU_DOWN_PREPARE: 5628 smp_call_function_single(cpu, tsc_bad, NULL, 1); 5629 break; 5630 } 5631 return NOTIFY_OK; 5632 } 5633 5634 static struct notifier_block kvmclock_cpu_notifier_block = { 5635 .notifier_call = kvmclock_cpu_notifier, 5636 .priority = -INT_MAX 5637 }; 5638 5639 static void kvm_timer_init(void) 5640 { 5641 int cpu; 5642 5643 max_tsc_khz = tsc_khz; 5644 5645 cpu_notifier_register_begin(); 5646 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 5647 #ifdef CONFIG_CPU_FREQ 5648 struct cpufreq_policy policy; 5649 memset(&policy, 0, sizeof(policy)); 5650 cpu = get_cpu(); 5651 cpufreq_get_policy(&policy, cpu); 5652 if (policy.cpuinfo.max_freq) 5653 max_tsc_khz = policy.cpuinfo.max_freq; 5654 put_cpu(); 5655 #endif 5656 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 5657 CPUFREQ_TRANSITION_NOTIFIER); 5658 } 5659 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 5660 for_each_online_cpu(cpu) 5661 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5662 5663 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5664 cpu_notifier_register_done(); 5665 5666 } 5667 5668 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 5669 5670 int kvm_is_in_guest(void) 5671 { 5672 return __this_cpu_read(current_vcpu) != NULL; 5673 } 5674 5675 static int kvm_is_user_mode(void) 5676 { 5677 int user_mode = 3; 5678 5679 if (__this_cpu_read(current_vcpu)) 5680 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 5681 5682 return user_mode != 0; 5683 } 5684 5685 static unsigned long kvm_get_guest_ip(void) 5686 { 5687 unsigned long ip = 0; 5688 5689 if (__this_cpu_read(current_vcpu)) 5690 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 5691 5692 return ip; 5693 } 5694 5695 static struct perf_guest_info_callbacks kvm_guest_cbs = { 5696 .is_in_guest = kvm_is_in_guest, 5697 .is_user_mode = kvm_is_user_mode, 5698 .get_guest_ip = kvm_get_guest_ip, 5699 }; 5700 5701 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) 5702 { 5703 __this_cpu_write(current_vcpu, vcpu); 5704 } 5705 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); 5706 5707 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) 5708 { 5709 __this_cpu_write(current_vcpu, NULL); 5710 } 5711 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); 5712 5713 static void kvm_set_mmio_spte_mask(void) 5714 { 5715 u64 mask; 5716 int maxphyaddr = boot_cpu_data.x86_phys_bits; 5717 5718 /* 5719 * Set the reserved bits and the present bit of an paging-structure 5720 * entry to generate page fault with PFER.RSV = 1. 5721 */ 5722 /* Mask the reserved physical address bits. */ 5723 mask = rsvd_bits(maxphyaddr, 51); 5724 5725 /* Bit 62 is always reserved for 32bit host. */ 5726 mask |= 0x3ull << 62; 5727 5728 /* Set the present bit. */ 5729 mask |= 1ull; 5730 5731 #ifdef CONFIG_X86_64 5732 /* 5733 * If reserved bit is not supported, clear the present bit to disable 5734 * mmio page fault. 5735 */ 5736 if (maxphyaddr == 52) 5737 mask &= ~1ull; 5738 #endif 5739 5740 kvm_mmu_set_mmio_spte_mask(mask); 5741 } 5742 5743 #ifdef CONFIG_X86_64 5744 static void pvclock_gtod_update_fn(struct work_struct *work) 5745 { 5746 struct kvm *kvm; 5747 5748 struct kvm_vcpu *vcpu; 5749 int i; 5750 5751 spin_lock(&kvm_lock); 5752 list_for_each_entry(kvm, &vm_list, vm_list) 5753 kvm_for_each_vcpu(i, vcpu, kvm) 5754 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 5755 atomic_set(&kvm_guest_has_master_clock, 0); 5756 spin_unlock(&kvm_lock); 5757 } 5758 5759 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 5760 5761 /* 5762 * Notification about pvclock gtod data update. 5763 */ 5764 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 5765 void *priv) 5766 { 5767 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 5768 struct timekeeper *tk = priv; 5769 5770 update_pvclock_gtod(tk); 5771 5772 /* disable master clock if host does not trust, or does not 5773 * use, TSC clocksource 5774 */ 5775 if (gtod->clock.vclock_mode != VCLOCK_TSC && 5776 atomic_read(&kvm_guest_has_master_clock) != 0) 5777 queue_work(system_long_wq, &pvclock_gtod_work); 5778 5779 return 0; 5780 } 5781 5782 static struct notifier_block pvclock_gtod_notifier = { 5783 .notifier_call = pvclock_gtod_notify, 5784 }; 5785 #endif 5786 5787 int kvm_arch_init(void *opaque) 5788 { 5789 int r; 5790 struct kvm_x86_ops *ops = opaque; 5791 5792 if (kvm_x86_ops) { 5793 printk(KERN_ERR "kvm: already loaded the other module\n"); 5794 r = -EEXIST; 5795 goto out; 5796 } 5797 5798 if (!ops->cpu_has_kvm_support()) { 5799 printk(KERN_ERR "kvm: no hardware support\n"); 5800 r = -EOPNOTSUPP; 5801 goto out; 5802 } 5803 if (ops->disabled_by_bios()) { 5804 printk(KERN_ERR "kvm: disabled by bios\n"); 5805 r = -EOPNOTSUPP; 5806 goto out; 5807 } 5808 5809 r = -ENOMEM; 5810 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 5811 if (!shared_msrs) { 5812 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 5813 goto out; 5814 } 5815 5816 r = kvm_mmu_module_init(); 5817 if (r) 5818 goto out_free_percpu; 5819 5820 kvm_set_mmio_spte_mask(); 5821 5822 kvm_x86_ops = ops; 5823 5824 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 5825 PT_DIRTY_MASK, PT64_NX_MASK, 0); 5826 5827 kvm_timer_init(); 5828 5829 perf_register_guest_info_callbacks(&kvm_guest_cbs); 5830 5831 if (cpu_has_xsave) 5832 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 5833 5834 kvm_lapic_init(); 5835 #ifdef CONFIG_X86_64 5836 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 5837 #endif 5838 5839 return 0; 5840 5841 out_free_percpu: 5842 free_percpu(shared_msrs); 5843 out: 5844 return r; 5845 } 5846 5847 void kvm_arch_exit(void) 5848 { 5849 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 5850 5851 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5852 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 5853 CPUFREQ_TRANSITION_NOTIFIER); 5854 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5855 #ifdef CONFIG_X86_64 5856 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 5857 #endif 5858 kvm_x86_ops = NULL; 5859 kvm_mmu_module_exit(); 5860 free_percpu(shared_msrs); 5861 } 5862 5863 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 5864 { 5865 ++vcpu->stat.halt_exits; 5866 if (irqchip_in_kernel(vcpu->kvm)) { 5867 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 5868 return 1; 5869 } else { 5870 vcpu->run->exit_reason = KVM_EXIT_HLT; 5871 return 0; 5872 } 5873 } 5874 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 5875 5876 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 5877 { 5878 kvm_x86_ops->skip_emulated_instruction(vcpu); 5879 return kvm_vcpu_halt(vcpu); 5880 } 5881 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 5882 5883 int kvm_hv_hypercall(struct kvm_vcpu *vcpu) 5884 { 5885 u64 param, ingpa, outgpa, ret; 5886 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; 5887 bool fast, longmode; 5888 5889 /* 5890 * hypercall generates UD from non zero cpl and real mode 5891 * per HYPER-V spec 5892 */ 5893 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { 5894 kvm_queue_exception(vcpu, UD_VECTOR); 5895 return 0; 5896 } 5897 5898 longmode = is_64_bit_mode(vcpu); 5899 5900 if (!longmode) { 5901 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | 5902 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); 5903 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | 5904 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); 5905 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | 5906 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); 5907 } 5908 #ifdef CONFIG_X86_64 5909 else { 5910 param = kvm_register_read(vcpu, VCPU_REGS_RCX); 5911 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); 5912 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); 5913 } 5914 #endif 5915 5916 code = param & 0xffff; 5917 fast = (param >> 16) & 0x1; 5918 rep_cnt = (param >> 32) & 0xfff; 5919 rep_idx = (param >> 48) & 0xfff; 5920 5921 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); 5922 5923 switch (code) { 5924 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: 5925 kvm_vcpu_on_spin(vcpu); 5926 break; 5927 default: 5928 res = HV_STATUS_INVALID_HYPERCALL_CODE; 5929 break; 5930 } 5931 5932 ret = res | (((u64)rep_done & 0xfff) << 32); 5933 if (longmode) { 5934 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 5935 } else { 5936 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); 5937 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); 5938 } 5939 5940 return 1; 5941 } 5942 5943 /* 5944 * kvm_pv_kick_cpu_op: Kick a vcpu. 5945 * 5946 * @apicid - apicid of vcpu to be kicked. 5947 */ 5948 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 5949 { 5950 struct kvm_lapic_irq lapic_irq; 5951 5952 lapic_irq.shorthand = 0; 5953 lapic_irq.dest_mode = 0; 5954 lapic_irq.dest_id = apicid; 5955 5956 lapic_irq.delivery_mode = APIC_DM_REMRD; 5957 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 5958 } 5959 5960 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 5961 { 5962 unsigned long nr, a0, a1, a2, a3, ret; 5963 int op_64_bit, r = 1; 5964 5965 kvm_x86_ops->skip_emulated_instruction(vcpu); 5966 5967 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 5968 return kvm_hv_hypercall(vcpu); 5969 5970 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 5971 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 5972 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 5973 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 5974 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 5975 5976 trace_kvm_hypercall(nr, a0, a1, a2, a3); 5977 5978 op_64_bit = is_64_bit_mode(vcpu); 5979 if (!op_64_bit) { 5980 nr &= 0xFFFFFFFF; 5981 a0 &= 0xFFFFFFFF; 5982 a1 &= 0xFFFFFFFF; 5983 a2 &= 0xFFFFFFFF; 5984 a3 &= 0xFFFFFFFF; 5985 } 5986 5987 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 5988 ret = -KVM_EPERM; 5989 goto out; 5990 } 5991 5992 switch (nr) { 5993 case KVM_HC_VAPIC_POLL_IRQ: 5994 ret = 0; 5995 break; 5996 case KVM_HC_KICK_CPU: 5997 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 5998 ret = 0; 5999 break; 6000 default: 6001 ret = -KVM_ENOSYS; 6002 break; 6003 } 6004 out: 6005 if (!op_64_bit) 6006 ret = (u32)ret; 6007 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 6008 ++vcpu->stat.hypercalls; 6009 return r; 6010 } 6011 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 6012 6013 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 6014 { 6015 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6016 char instruction[3]; 6017 unsigned long rip = kvm_rip_read(vcpu); 6018 6019 kvm_x86_ops->patch_hypercall(vcpu, instruction); 6020 6021 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); 6022 } 6023 6024 /* 6025 * Check if userspace requested an interrupt window, and that the 6026 * interrupt window is open. 6027 * 6028 * No need to exit to userspace if we already have an interrupt queued. 6029 */ 6030 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 6031 { 6032 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && 6033 vcpu->run->request_interrupt_window && 6034 kvm_arch_interrupt_allowed(vcpu)); 6035 } 6036 6037 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 6038 { 6039 struct kvm_run *kvm_run = vcpu->run; 6040 6041 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 6042 kvm_run->cr8 = kvm_get_cr8(vcpu); 6043 kvm_run->apic_base = kvm_get_apic_base(vcpu); 6044 if (irqchip_in_kernel(vcpu->kvm)) 6045 kvm_run->ready_for_interrupt_injection = 1; 6046 else 6047 kvm_run->ready_for_interrupt_injection = 6048 kvm_arch_interrupt_allowed(vcpu) && 6049 !kvm_cpu_has_interrupt(vcpu) && 6050 !kvm_event_needs_reinjection(vcpu); 6051 } 6052 6053 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 6054 { 6055 int max_irr, tpr; 6056 6057 if (!kvm_x86_ops->update_cr8_intercept) 6058 return; 6059 6060 if (!vcpu->arch.apic) 6061 return; 6062 6063 if (!vcpu->arch.apic->vapic_addr) 6064 max_irr = kvm_lapic_find_highest_irr(vcpu); 6065 else 6066 max_irr = -1; 6067 6068 if (max_irr != -1) 6069 max_irr >>= 4; 6070 6071 tpr = kvm_lapic_get_cr8(vcpu); 6072 6073 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 6074 } 6075 6076 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 6077 { 6078 int r; 6079 6080 /* try to reinject previous events if any */ 6081 if (vcpu->arch.exception.pending) { 6082 trace_kvm_inj_exception(vcpu->arch.exception.nr, 6083 vcpu->arch.exception.has_error_code, 6084 vcpu->arch.exception.error_code); 6085 6086 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 6087 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 6088 X86_EFLAGS_RF); 6089 6090 if (vcpu->arch.exception.nr == DB_VECTOR && 6091 (vcpu->arch.dr7 & DR7_GD)) { 6092 vcpu->arch.dr7 &= ~DR7_GD; 6093 kvm_update_dr7(vcpu); 6094 } 6095 6096 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, 6097 vcpu->arch.exception.has_error_code, 6098 vcpu->arch.exception.error_code, 6099 vcpu->arch.exception.reinject); 6100 return 0; 6101 } 6102 6103 if (vcpu->arch.nmi_injected) { 6104 kvm_x86_ops->set_nmi(vcpu); 6105 return 0; 6106 } 6107 6108 if (vcpu->arch.interrupt.pending) { 6109 kvm_x86_ops->set_irq(vcpu); 6110 return 0; 6111 } 6112 6113 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6114 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6115 if (r != 0) 6116 return r; 6117 } 6118 6119 /* try to inject new event if pending */ 6120 if (vcpu->arch.nmi_pending) { 6121 if (kvm_x86_ops->nmi_allowed(vcpu)) { 6122 --vcpu->arch.nmi_pending; 6123 vcpu->arch.nmi_injected = true; 6124 kvm_x86_ops->set_nmi(vcpu); 6125 } 6126 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 6127 /* 6128 * Because interrupts can be injected asynchronously, we are 6129 * calling check_nested_events again here to avoid a race condition. 6130 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 6131 * proposal and current concerns. Perhaps we should be setting 6132 * KVM_REQ_EVENT only on certain events and not unconditionally? 6133 */ 6134 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6135 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6136 if (r != 0) 6137 return r; 6138 } 6139 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 6140 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 6141 false); 6142 kvm_x86_ops->set_irq(vcpu); 6143 } 6144 } 6145 return 0; 6146 } 6147 6148 static void process_nmi(struct kvm_vcpu *vcpu) 6149 { 6150 unsigned limit = 2; 6151 6152 /* 6153 * x86 is limited to one NMI running, and one NMI pending after it. 6154 * If an NMI is already in progress, limit further NMIs to just one. 6155 * Otherwise, allow two (and we'll inject the first one immediately). 6156 */ 6157 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 6158 limit = 1; 6159 6160 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 6161 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 6162 kvm_make_request(KVM_REQ_EVENT, vcpu); 6163 } 6164 6165 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 6166 { 6167 u64 eoi_exit_bitmap[4]; 6168 u32 tmr[8]; 6169 6170 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 6171 return; 6172 6173 memset(eoi_exit_bitmap, 0, 32); 6174 memset(tmr, 0, 32); 6175 6176 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr); 6177 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 6178 kvm_apic_update_tmr(vcpu, tmr); 6179 } 6180 6181 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) 6182 { 6183 ++vcpu->stat.tlb_flush; 6184 kvm_x86_ops->tlb_flush(vcpu); 6185 } 6186 6187 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 6188 { 6189 struct page *page = NULL; 6190 6191 if (!irqchip_in_kernel(vcpu->kvm)) 6192 return; 6193 6194 if (!kvm_x86_ops->set_apic_access_page_addr) 6195 return; 6196 6197 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 6198 if (is_error_page(page)) 6199 return; 6200 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 6201 6202 /* 6203 * Do not pin apic access page in memory, the MMU notifier 6204 * will call us again if it is migrated or swapped out. 6205 */ 6206 put_page(page); 6207 } 6208 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 6209 6210 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, 6211 unsigned long address) 6212 { 6213 /* 6214 * The physical address of apic access page is stored in the VMCS. 6215 * Update it when it becomes invalid. 6216 */ 6217 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT)) 6218 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 6219 } 6220 6221 /* 6222 * Returns 1 to let vcpu_run() continue the guest execution loop without 6223 * exiting to the userspace. Otherwise, the value will be returned to the 6224 * userspace. 6225 */ 6226 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 6227 { 6228 int r; 6229 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && 6230 vcpu->run->request_interrupt_window; 6231 bool req_immediate_exit = false; 6232 6233 if (vcpu->requests) { 6234 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 6235 kvm_mmu_unload(vcpu); 6236 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 6237 __kvm_migrate_timers(vcpu); 6238 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 6239 kvm_gen_update_masterclock(vcpu->kvm); 6240 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 6241 kvm_gen_kvmclock_update(vcpu); 6242 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 6243 r = kvm_guest_time_update(vcpu); 6244 if (unlikely(r)) 6245 goto out; 6246 } 6247 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 6248 kvm_mmu_sync_roots(vcpu); 6249 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 6250 kvm_vcpu_flush_tlb(vcpu); 6251 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 6252 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 6253 r = 0; 6254 goto out; 6255 } 6256 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 6257 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 6258 r = 0; 6259 goto out; 6260 } 6261 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { 6262 vcpu->fpu_active = 0; 6263 kvm_x86_ops->fpu_deactivate(vcpu); 6264 } 6265 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 6266 /* Page is swapped out. Do synthetic halt */ 6267 vcpu->arch.apf.halted = true; 6268 r = 1; 6269 goto out; 6270 } 6271 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 6272 record_steal_time(vcpu); 6273 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 6274 process_nmi(vcpu); 6275 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 6276 kvm_handle_pmu_event(vcpu); 6277 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 6278 kvm_deliver_pmi(vcpu); 6279 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 6280 vcpu_scan_ioapic(vcpu); 6281 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 6282 kvm_vcpu_reload_apic_access_page(vcpu); 6283 } 6284 6285 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 6286 kvm_apic_accept_events(vcpu); 6287 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 6288 r = 1; 6289 goto out; 6290 } 6291 6292 if (inject_pending_event(vcpu, req_int_win) != 0) 6293 req_immediate_exit = true; 6294 /* enable NMI/IRQ window open exits if needed */ 6295 else if (vcpu->arch.nmi_pending) 6296 kvm_x86_ops->enable_nmi_window(vcpu); 6297 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 6298 kvm_x86_ops->enable_irq_window(vcpu); 6299 6300 if (kvm_lapic_enabled(vcpu)) { 6301 /* 6302 * Update architecture specific hints for APIC 6303 * virtual interrupt delivery. 6304 */ 6305 if (kvm_x86_ops->hwapic_irr_update) 6306 kvm_x86_ops->hwapic_irr_update(vcpu, 6307 kvm_lapic_find_highest_irr(vcpu)); 6308 update_cr8_intercept(vcpu); 6309 kvm_lapic_sync_to_vapic(vcpu); 6310 } 6311 } 6312 6313 r = kvm_mmu_reload(vcpu); 6314 if (unlikely(r)) { 6315 goto cancel_injection; 6316 } 6317 6318 preempt_disable(); 6319 6320 kvm_x86_ops->prepare_guest_switch(vcpu); 6321 if (vcpu->fpu_active) 6322 kvm_load_guest_fpu(vcpu); 6323 kvm_load_guest_xcr0(vcpu); 6324 6325 vcpu->mode = IN_GUEST_MODE; 6326 6327 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6328 6329 /* We should set ->mode before check ->requests, 6330 * see the comment in make_all_cpus_request. 6331 */ 6332 smp_mb__after_srcu_read_unlock(); 6333 6334 local_irq_disable(); 6335 6336 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests 6337 || need_resched() || signal_pending(current)) { 6338 vcpu->mode = OUTSIDE_GUEST_MODE; 6339 smp_wmb(); 6340 local_irq_enable(); 6341 preempt_enable(); 6342 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6343 r = 1; 6344 goto cancel_injection; 6345 } 6346 6347 if (req_immediate_exit) 6348 smp_send_reschedule(vcpu->cpu); 6349 6350 kvm_guest_enter(); 6351 6352 if (unlikely(vcpu->arch.switch_db_regs)) { 6353 set_debugreg(0, 7); 6354 set_debugreg(vcpu->arch.eff_db[0], 0); 6355 set_debugreg(vcpu->arch.eff_db[1], 1); 6356 set_debugreg(vcpu->arch.eff_db[2], 2); 6357 set_debugreg(vcpu->arch.eff_db[3], 3); 6358 set_debugreg(vcpu->arch.dr6, 6); 6359 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 6360 } 6361 6362 trace_kvm_entry(vcpu->vcpu_id); 6363 wait_lapic_expire(vcpu); 6364 kvm_x86_ops->run(vcpu); 6365 6366 /* 6367 * Do this here before restoring debug registers on the host. And 6368 * since we do this before handling the vmexit, a DR access vmexit 6369 * can (a) read the correct value of the debug registers, (b) set 6370 * KVM_DEBUGREG_WONT_EXIT again. 6371 */ 6372 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 6373 int i; 6374 6375 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 6376 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 6377 for (i = 0; i < KVM_NR_DB_REGS; i++) 6378 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 6379 } 6380 6381 /* 6382 * If the guest has used debug registers, at least dr7 6383 * will be disabled while returning to the host. 6384 * If we don't have active breakpoints in the host, we don't 6385 * care about the messed up debug address registers. But if 6386 * we have some of them active, restore the old state. 6387 */ 6388 if (hw_breakpoint_active()) 6389 hw_breakpoint_restore(); 6390 6391 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, 6392 native_read_tsc()); 6393 6394 vcpu->mode = OUTSIDE_GUEST_MODE; 6395 smp_wmb(); 6396 6397 /* Interrupt is enabled by handle_external_intr() */ 6398 kvm_x86_ops->handle_external_intr(vcpu); 6399 6400 ++vcpu->stat.exits; 6401 6402 /* 6403 * We must have an instruction between local_irq_enable() and 6404 * kvm_guest_exit(), so the timer interrupt isn't delayed by 6405 * the interrupt shadow. The stat.exits increment will do nicely. 6406 * But we need to prevent reordering, hence this barrier(): 6407 */ 6408 barrier(); 6409 6410 kvm_guest_exit(); 6411 6412 preempt_enable(); 6413 6414 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6415 6416 /* 6417 * Profile KVM exit RIPs: 6418 */ 6419 if (unlikely(prof_on == KVM_PROFILING)) { 6420 unsigned long rip = kvm_rip_read(vcpu); 6421 profile_hit(KVM_PROFILING, (void *)rip); 6422 } 6423 6424 if (unlikely(vcpu->arch.tsc_always_catchup)) 6425 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6426 6427 if (vcpu->arch.apic_attention) 6428 kvm_lapic_sync_from_vapic(vcpu); 6429 6430 r = kvm_x86_ops->handle_exit(vcpu); 6431 return r; 6432 6433 cancel_injection: 6434 kvm_x86_ops->cancel_injection(vcpu); 6435 if (unlikely(vcpu->arch.apic_attention)) 6436 kvm_lapic_sync_from_vapic(vcpu); 6437 out: 6438 return r; 6439 } 6440 6441 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 6442 { 6443 if (!kvm_arch_vcpu_runnable(vcpu)) { 6444 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6445 kvm_vcpu_block(vcpu); 6446 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6447 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 6448 return 1; 6449 } 6450 6451 kvm_apic_accept_events(vcpu); 6452 switch(vcpu->arch.mp_state) { 6453 case KVM_MP_STATE_HALTED: 6454 vcpu->arch.pv.pv_unhalted = false; 6455 vcpu->arch.mp_state = 6456 KVM_MP_STATE_RUNNABLE; 6457 case KVM_MP_STATE_RUNNABLE: 6458 vcpu->arch.apf.halted = false; 6459 break; 6460 case KVM_MP_STATE_INIT_RECEIVED: 6461 break; 6462 default: 6463 return -EINTR; 6464 break; 6465 } 6466 return 1; 6467 } 6468 6469 static int vcpu_run(struct kvm_vcpu *vcpu) 6470 { 6471 int r; 6472 struct kvm *kvm = vcpu->kvm; 6473 6474 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6475 6476 for (;;) { 6477 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 6478 !vcpu->arch.apf.halted) 6479 r = vcpu_enter_guest(vcpu); 6480 else 6481 r = vcpu_block(kvm, vcpu); 6482 if (r <= 0) 6483 break; 6484 6485 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); 6486 if (kvm_cpu_has_pending_timer(vcpu)) 6487 kvm_inject_pending_timer_irqs(vcpu); 6488 6489 if (dm_request_for_irq_injection(vcpu)) { 6490 r = -EINTR; 6491 vcpu->run->exit_reason = KVM_EXIT_INTR; 6492 ++vcpu->stat.request_irq_exits; 6493 break; 6494 } 6495 6496 kvm_check_async_pf_completion(vcpu); 6497 6498 if (signal_pending(current)) { 6499 r = -EINTR; 6500 vcpu->run->exit_reason = KVM_EXIT_INTR; 6501 ++vcpu->stat.signal_exits; 6502 break; 6503 } 6504 if (need_resched()) { 6505 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6506 cond_resched(); 6507 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6508 } 6509 } 6510 6511 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6512 6513 return r; 6514 } 6515 6516 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 6517 { 6518 int r; 6519 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6520 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 6521 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6522 if (r != EMULATE_DONE) 6523 return 0; 6524 return 1; 6525 } 6526 6527 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 6528 { 6529 BUG_ON(!vcpu->arch.pio.count); 6530 6531 return complete_emulated_io(vcpu); 6532 } 6533 6534 /* 6535 * Implements the following, as a state machine: 6536 * 6537 * read: 6538 * for each fragment 6539 * for each mmio piece in the fragment 6540 * write gpa, len 6541 * exit 6542 * copy data 6543 * execute insn 6544 * 6545 * write: 6546 * for each fragment 6547 * for each mmio piece in the fragment 6548 * write gpa, len 6549 * copy data 6550 * exit 6551 */ 6552 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 6553 { 6554 struct kvm_run *run = vcpu->run; 6555 struct kvm_mmio_fragment *frag; 6556 unsigned len; 6557 6558 BUG_ON(!vcpu->mmio_needed); 6559 6560 /* Complete previous fragment */ 6561 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 6562 len = min(8u, frag->len); 6563 if (!vcpu->mmio_is_write) 6564 memcpy(frag->data, run->mmio.data, len); 6565 6566 if (frag->len <= 8) { 6567 /* Switch to the next fragment. */ 6568 frag++; 6569 vcpu->mmio_cur_fragment++; 6570 } else { 6571 /* Go forward to the next mmio piece. */ 6572 frag->data += len; 6573 frag->gpa += len; 6574 frag->len -= len; 6575 } 6576 6577 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 6578 vcpu->mmio_needed = 0; 6579 6580 /* FIXME: return into emulator if single-stepping. */ 6581 if (vcpu->mmio_is_write) 6582 return 1; 6583 vcpu->mmio_read_completed = 1; 6584 return complete_emulated_io(vcpu); 6585 } 6586 6587 run->exit_reason = KVM_EXIT_MMIO; 6588 run->mmio.phys_addr = frag->gpa; 6589 if (vcpu->mmio_is_write) 6590 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 6591 run->mmio.len = min(8u, frag->len); 6592 run->mmio.is_write = vcpu->mmio_is_write; 6593 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6594 return 0; 6595 } 6596 6597 6598 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 6599 { 6600 int r; 6601 sigset_t sigsaved; 6602 6603 if (!tsk_used_math(current) && init_fpu(current)) 6604 return -ENOMEM; 6605 6606 if (vcpu->sigset_active) 6607 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); 6608 6609 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 6610 kvm_vcpu_block(vcpu); 6611 kvm_apic_accept_events(vcpu); 6612 clear_bit(KVM_REQ_UNHALT, &vcpu->requests); 6613 r = -EAGAIN; 6614 goto out; 6615 } 6616 6617 /* re-sync apic's tpr */ 6618 if (!irqchip_in_kernel(vcpu->kvm)) { 6619 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 6620 r = -EINVAL; 6621 goto out; 6622 } 6623 } 6624 6625 if (unlikely(vcpu->arch.complete_userspace_io)) { 6626 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 6627 vcpu->arch.complete_userspace_io = NULL; 6628 r = cui(vcpu); 6629 if (r <= 0) 6630 goto out; 6631 } else 6632 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 6633 6634 r = vcpu_run(vcpu); 6635 6636 out: 6637 post_kvm_run_save(vcpu); 6638 if (vcpu->sigset_active) 6639 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 6640 6641 return r; 6642 } 6643 6644 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6645 { 6646 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 6647 /* 6648 * We are here if userspace calls get_regs() in the middle of 6649 * instruction emulation. Registers state needs to be copied 6650 * back from emulation context to vcpu. Userspace shouldn't do 6651 * that usually, but some bad designed PV devices (vmware 6652 * backdoor interface) need this to work 6653 */ 6654 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 6655 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6656 } 6657 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 6658 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 6659 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 6660 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 6661 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 6662 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 6663 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 6664 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 6665 #ifdef CONFIG_X86_64 6666 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 6667 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 6668 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 6669 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 6670 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 6671 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 6672 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 6673 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 6674 #endif 6675 6676 regs->rip = kvm_rip_read(vcpu); 6677 regs->rflags = kvm_get_rflags(vcpu); 6678 6679 return 0; 6680 } 6681 6682 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6683 { 6684 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 6685 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6686 6687 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 6688 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 6689 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 6690 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 6691 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 6692 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 6693 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 6694 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 6695 #ifdef CONFIG_X86_64 6696 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 6697 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 6698 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 6699 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 6700 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 6701 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 6702 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 6703 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 6704 #endif 6705 6706 kvm_rip_write(vcpu, regs->rip); 6707 kvm_set_rflags(vcpu, regs->rflags); 6708 6709 vcpu->arch.exception.pending = false; 6710 6711 kvm_make_request(KVM_REQ_EVENT, vcpu); 6712 6713 return 0; 6714 } 6715 6716 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 6717 { 6718 struct kvm_segment cs; 6719 6720 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 6721 *db = cs.db; 6722 *l = cs.l; 6723 } 6724 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 6725 6726 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 6727 struct kvm_sregs *sregs) 6728 { 6729 struct desc_ptr dt; 6730 6731 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 6732 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 6733 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 6734 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 6735 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 6736 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 6737 6738 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 6739 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 6740 6741 kvm_x86_ops->get_idt(vcpu, &dt); 6742 sregs->idt.limit = dt.size; 6743 sregs->idt.base = dt.address; 6744 kvm_x86_ops->get_gdt(vcpu, &dt); 6745 sregs->gdt.limit = dt.size; 6746 sregs->gdt.base = dt.address; 6747 6748 sregs->cr0 = kvm_read_cr0(vcpu); 6749 sregs->cr2 = vcpu->arch.cr2; 6750 sregs->cr3 = kvm_read_cr3(vcpu); 6751 sregs->cr4 = kvm_read_cr4(vcpu); 6752 sregs->cr8 = kvm_get_cr8(vcpu); 6753 sregs->efer = vcpu->arch.efer; 6754 sregs->apic_base = kvm_get_apic_base(vcpu); 6755 6756 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 6757 6758 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) 6759 set_bit(vcpu->arch.interrupt.nr, 6760 (unsigned long *)sregs->interrupt_bitmap); 6761 6762 return 0; 6763 } 6764 6765 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 6766 struct kvm_mp_state *mp_state) 6767 { 6768 kvm_apic_accept_events(vcpu); 6769 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 6770 vcpu->arch.pv.pv_unhalted) 6771 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 6772 else 6773 mp_state->mp_state = vcpu->arch.mp_state; 6774 6775 return 0; 6776 } 6777 6778 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 6779 struct kvm_mp_state *mp_state) 6780 { 6781 if (!kvm_vcpu_has_lapic(vcpu) && 6782 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 6783 return -EINVAL; 6784 6785 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 6786 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 6787 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 6788 } else 6789 vcpu->arch.mp_state = mp_state->mp_state; 6790 kvm_make_request(KVM_REQ_EVENT, vcpu); 6791 return 0; 6792 } 6793 6794 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 6795 int reason, bool has_error_code, u32 error_code) 6796 { 6797 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6798 int ret; 6799 6800 init_emulate_ctxt(vcpu); 6801 6802 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 6803 has_error_code, error_code); 6804 6805 if (ret) 6806 return EMULATE_FAIL; 6807 6808 kvm_rip_write(vcpu, ctxt->eip); 6809 kvm_set_rflags(vcpu, ctxt->eflags); 6810 kvm_make_request(KVM_REQ_EVENT, vcpu); 6811 return EMULATE_DONE; 6812 } 6813 EXPORT_SYMBOL_GPL(kvm_task_switch); 6814 6815 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 6816 struct kvm_sregs *sregs) 6817 { 6818 struct msr_data apic_base_msr; 6819 int mmu_reset_needed = 0; 6820 int pending_vec, max_bits, idx; 6821 struct desc_ptr dt; 6822 6823 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) 6824 return -EINVAL; 6825 6826 dt.size = sregs->idt.limit; 6827 dt.address = sregs->idt.base; 6828 kvm_x86_ops->set_idt(vcpu, &dt); 6829 dt.size = sregs->gdt.limit; 6830 dt.address = sregs->gdt.base; 6831 kvm_x86_ops->set_gdt(vcpu, &dt); 6832 6833 vcpu->arch.cr2 = sregs->cr2; 6834 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 6835 vcpu->arch.cr3 = sregs->cr3; 6836 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 6837 6838 kvm_set_cr8(vcpu, sregs->cr8); 6839 6840 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 6841 kvm_x86_ops->set_efer(vcpu, sregs->efer); 6842 apic_base_msr.data = sregs->apic_base; 6843 apic_base_msr.host_initiated = true; 6844 kvm_set_apic_base(vcpu, &apic_base_msr); 6845 6846 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 6847 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 6848 vcpu->arch.cr0 = sregs->cr0; 6849 6850 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 6851 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 6852 if (sregs->cr4 & X86_CR4_OSXSAVE) 6853 kvm_update_cpuid(vcpu); 6854 6855 idx = srcu_read_lock(&vcpu->kvm->srcu); 6856 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 6857 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 6858 mmu_reset_needed = 1; 6859 } 6860 srcu_read_unlock(&vcpu->kvm->srcu, idx); 6861 6862 if (mmu_reset_needed) 6863 kvm_mmu_reset_context(vcpu); 6864 6865 max_bits = KVM_NR_INTERRUPTS; 6866 pending_vec = find_first_bit( 6867 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 6868 if (pending_vec < max_bits) { 6869 kvm_queue_interrupt(vcpu, pending_vec, false); 6870 pr_debug("Set back pending irq %d\n", pending_vec); 6871 } 6872 6873 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 6874 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 6875 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 6876 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 6877 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 6878 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 6879 6880 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 6881 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 6882 6883 update_cr8_intercept(vcpu); 6884 6885 /* Older userspace won't unhalt the vcpu on reset. */ 6886 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 6887 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 6888 !is_protmode(vcpu)) 6889 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 6890 6891 kvm_make_request(KVM_REQ_EVENT, vcpu); 6892 6893 return 0; 6894 } 6895 6896 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 6897 struct kvm_guest_debug *dbg) 6898 { 6899 unsigned long rflags; 6900 int i, r; 6901 6902 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 6903 r = -EBUSY; 6904 if (vcpu->arch.exception.pending) 6905 goto out; 6906 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 6907 kvm_queue_exception(vcpu, DB_VECTOR); 6908 else 6909 kvm_queue_exception(vcpu, BP_VECTOR); 6910 } 6911 6912 /* 6913 * Read rflags as long as potentially injected trace flags are still 6914 * filtered out. 6915 */ 6916 rflags = kvm_get_rflags(vcpu); 6917 6918 vcpu->guest_debug = dbg->control; 6919 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 6920 vcpu->guest_debug = 0; 6921 6922 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 6923 for (i = 0; i < KVM_NR_DB_REGS; ++i) 6924 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 6925 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 6926 } else { 6927 for (i = 0; i < KVM_NR_DB_REGS; i++) 6928 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 6929 } 6930 kvm_update_dr7(vcpu); 6931 6932 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6933 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 6934 get_segment_base(vcpu, VCPU_SREG_CS); 6935 6936 /* 6937 * Trigger an rflags update that will inject or remove the trace 6938 * flags. 6939 */ 6940 kvm_set_rflags(vcpu, rflags); 6941 6942 kvm_x86_ops->update_db_bp_intercept(vcpu); 6943 6944 r = 0; 6945 6946 out: 6947 6948 return r; 6949 } 6950 6951 /* 6952 * Translate a guest virtual address to a guest physical address. 6953 */ 6954 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 6955 struct kvm_translation *tr) 6956 { 6957 unsigned long vaddr = tr->linear_address; 6958 gpa_t gpa; 6959 int idx; 6960 6961 idx = srcu_read_lock(&vcpu->kvm->srcu); 6962 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 6963 srcu_read_unlock(&vcpu->kvm->srcu, idx); 6964 tr->physical_address = gpa; 6965 tr->valid = gpa != UNMAPPED_GVA; 6966 tr->writeable = 1; 6967 tr->usermode = 0; 6968 6969 return 0; 6970 } 6971 6972 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 6973 { 6974 struct i387_fxsave_struct *fxsave = 6975 &vcpu->arch.guest_fpu.state->fxsave; 6976 6977 memcpy(fpu->fpr, fxsave->st_space, 128); 6978 fpu->fcw = fxsave->cwd; 6979 fpu->fsw = fxsave->swd; 6980 fpu->ftwx = fxsave->twd; 6981 fpu->last_opcode = fxsave->fop; 6982 fpu->last_ip = fxsave->rip; 6983 fpu->last_dp = fxsave->rdp; 6984 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 6985 6986 return 0; 6987 } 6988 6989 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 6990 { 6991 struct i387_fxsave_struct *fxsave = 6992 &vcpu->arch.guest_fpu.state->fxsave; 6993 6994 memcpy(fxsave->st_space, fpu->fpr, 128); 6995 fxsave->cwd = fpu->fcw; 6996 fxsave->swd = fpu->fsw; 6997 fxsave->twd = fpu->ftwx; 6998 fxsave->fop = fpu->last_opcode; 6999 fxsave->rip = fpu->last_ip; 7000 fxsave->rdp = fpu->last_dp; 7001 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 7002 7003 return 0; 7004 } 7005 7006 int fx_init(struct kvm_vcpu *vcpu) 7007 { 7008 int err; 7009 7010 err = fpu_alloc(&vcpu->arch.guest_fpu); 7011 if (err) 7012 return err; 7013 7014 fpu_finit(&vcpu->arch.guest_fpu); 7015 if (cpu_has_xsaves) 7016 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv = 7017 host_xcr0 | XSTATE_COMPACTION_ENABLED; 7018 7019 /* 7020 * Ensure guest xcr0 is valid for loading 7021 */ 7022 vcpu->arch.xcr0 = XSTATE_FP; 7023 7024 vcpu->arch.cr0 |= X86_CR0_ET; 7025 7026 return 0; 7027 } 7028 EXPORT_SYMBOL_GPL(fx_init); 7029 7030 static void fx_free(struct kvm_vcpu *vcpu) 7031 { 7032 fpu_free(&vcpu->arch.guest_fpu); 7033 } 7034 7035 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 7036 { 7037 if (vcpu->guest_fpu_loaded) 7038 return; 7039 7040 /* 7041 * Restore all possible states in the guest, 7042 * and assume host would use all available bits. 7043 * Guest xcr0 would be loaded later. 7044 */ 7045 kvm_put_guest_xcr0(vcpu); 7046 vcpu->guest_fpu_loaded = 1; 7047 __kernel_fpu_begin(); 7048 fpu_restore_checking(&vcpu->arch.guest_fpu); 7049 trace_kvm_fpu(1); 7050 } 7051 7052 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 7053 { 7054 kvm_put_guest_xcr0(vcpu); 7055 7056 if (!vcpu->guest_fpu_loaded) 7057 return; 7058 7059 vcpu->guest_fpu_loaded = 0; 7060 fpu_save_init(&vcpu->arch.guest_fpu); 7061 __kernel_fpu_end(); 7062 ++vcpu->stat.fpu_reload; 7063 if (!vcpu->arch.eager_fpu) 7064 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); 7065 7066 trace_kvm_fpu(0); 7067 } 7068 7069 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 7070 { 7071 kvmclock_reset(vcpu); 7072 7073 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 7074 fx_free(vcpu); 7075 kvm_x86_ops->vcpu_free(vcpu); 7076 } 7077 7078 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 7079 unsigned int id) 7080 { 7081 struct kvm_vcpu *vcpu; 7082 7083 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 7084 printk_once(KERN_WARNING 7085 "kvm: SMP vm created on host with unstable TSC; " 7086 "guest TSC will not be reliable\n"); 7087 7088 vcpu = kvm_x86_ops->vcpu_create(kvm, id); 7089 7090 /* 7091 * Activate fpu unconditionally in case the guest needs eager FPU. It will be 7092 * deactivated soon if it doesn't. 7093 */ 7094 kvm_x86_ops->fpu_activate(vcpu); 7095 return vcpu; 7096 } 7097 7098 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 7099 { 7100 int r; 7101 7102 vcpu->arch.mtrr_state.have_fixed = 1; 7103 r = vcpu_load(vcpu); 7104 if (r) 7105 return r; 7106 kvm_vcpu_reset(vcpu); 7107 kvm_mmu_setup(vcpu); 7108 vcpu_put(vcpu); 7109 7110 return r; 7111 } 7112 7113 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 7114 { 7115 struct msr_data msr; 7116 struct kvm *kvm = vcpu->kvm; 7117 7118 if (vcpu_load(vcpu)) 7119 return; 7120 msr.data = 0x0; 7121 msr.index = MSR_IA32_TSC; 7122 msr.host_initiated = true; 7123 kvm_write_tsc(vcpu, &msr); 7124 vcpu_put(vcpu); 7125 7126 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 7127 KVMCLOCK_SYNC_PERIOD); 7128 } 7129 7130 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 7131 { 7132 int r; 7133 vcpu->arch.apf.msr_val = 0; 7134 7135 r = vcpu_load(vcpu); 7136 BUG_ON(r); 7137 kvm_mmu_unload(vcpu); 7138 vcpu_put(vcpu); 7139 7140 fx_free(vcpu); 7141 kvm_x86_ops->vcpu_free(vcpu); 7142 } 7143 7144 void kvm_vcpu_reset(struct kvm_vcpu *vcpu) 7145 { 7146 atomic_set(&vcpu->arch.nmi_queued, 0); 7147 vcpu->arch.nmi_pending = 0; 7148 vcpu->arch.nmi_injected = false; 7149 kvm_clear_interrupt_queue(vcpu); 7150 kvm_clear_exception_queue(vcpu); 7151 7152 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 7153 kvm_update_dr0123(vcpu); 7154 vcpu->arch.dr6 = DR6_INIT; 7155 kvm_update_dr6(vcpu); 7156 vcpu->arch.dr7 = DR7_FIXED_1; 7157 kvm_update_dr7(vcpu); 7158 7159 vcpu->arch.cr2 = 0; 7160 7161 kvm_make_request(KVM_REQ_EVENT, vcpu); 7162 vcpu->arch.apf.msr_val = 0; 7163 vcpu->arch.st.msr_val = 0; 7164 7165 kvmclock_reset(vcpu); 7166 7167 kvm_clear_async_pf_completion_queue(vcpu); 7168 kvm_async_pf_hash_reset(vcpu); 7169 vcpu->arch.apf.halted = false; 7170 7171 kvm_pmu_reset(vcpu); 7172 7173 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 7174 vcpu->arch.regs_avail = ~0; 7175 vcpu->arch.regs_dirty = ~0; 7176 7177 kvm_x86_ops->vcpu_reset(vcpu); 7178 } 7179 7180 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 7181 { 7182 struct kvm_segment cs; 7183 7184 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7185 cs.selector = vector << 8; 7186 cs.base = vector << 12; 7187 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7188 kvm_rip_write(vcpu, 0); 7189 } 7190 7191 int kvm_arch_hardware_enable(void) 7192 { 7193 struct kvm *kvm; 7194 struct kvm_vcpu *vcpu; 7195 int i; 7196 int ret; 7197 u64 local_tsc; 7198 u64 max_tsc = 0; 7199 bool stable, backwards_tsc = false; 7200 7201 kvm_shared_msr_cpu_online(); 7202 ret = kvm_x86_ops->hardware_enable(); 7203 if (ret != 0) 7204 return ret; 7205 7206 local_tsc = native_read_tsc(); 7207 stable = !check_tsc_unstable(); 7208 list_for_each_entry(kvm, &vm_list, vm_list) { 7209 kvm_for_each_vcpu(i, vcpu, kvm) { 7210 if (!stable && vcpu->cpu == smp_processor_id()) 7211 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7212 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 7213 backwards_tsc = true; 7214 if (vcpu->arch.last_host_tsc > max_tsc) 7215 max_tsc = vcpu->arch.last_host_tsc; 7216 } 7217 } 7218 } 7219 7220 /* 7221 * Sometimes, even reliable TSCs go backwards. This happens on 7222 * platforms that reset TSC during suspend or hibernate actions, but 7223 * maintain synchronization. We must compensate. Fortunately, we can 7224 * detect that condition here, which happens early in CPU bringup, 7225 * before any KVM threads can be running. Unfortunately, we can't 7226 * bring the TSCs fully up to date with real time, as we aren't yet far 7227 * enough into CPU bringup that we know how much real time has actually 7228 * elapsed; our helper function, get_kernel_ns() will be using boot 7229 * variables that haven't been updated yet. 7230 * 7231 * So we simply find the maximum observed TSC above, then record the 7232 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 7233 * the adjustment will be applied. Note that we accumulate 7234 * adjustments, in case multiple suspend cycles happen before some VCPU 7235 * gets a chance to run again. In the event that no KVM threads get a 7236 * chance to run, we will miss the entire elapsed period, as we'll have 7237 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 7238 * loose cycle time. This isn't too big a deal, since the loss will be 7239 * uniform across all VCPUs (not to mention the scenario is extremely 7240 * unlikely). It is possible that a second hibernate recovery happens 7241 * much faster than a first, causing the observed TSC here to be 7242 * smaller; this would require additional padding adjustment, which is 7243 * why we set last_host_tsc to the local tsc observed here. 7244 * 7245 * N.B. - this code below runs only on platforms with reliable TSC, 7246 * as that is the only way backwards_tsc is set above. Also note 7247 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 7248 * have the same delta_cyc adjustment applied if backwards_tsc 7249 * is detected. Note further, this adjustment is only done once, 7250 * as we reset last_host_tsc on all VCPUs to stop this from being 7251 * called multiple times (one for each physical CPU bringup). 7252 * 7253 * Platforms with unreliable TSCs don't have to deal with this, they 7254 * will be compensated by the logic in vcpu_load, which sets the TSC to 7255 * catchup mode. This will catchup all VCPUs to real time, but cannot 7256 * guarantee that they stay in perfect synchronization. 7257 */ 7258 if (backwards_tsc) { 7259 u64 delta_cyc = max_tsc - local_tsc; 7260 backwards_tsc_observed = true; 7261 list_for_each_entry(kvm, &vm_list, vm_list) { 7262 kvm_for_each_vcpu(i, vcpu, kvm) { 7263 vcpu->arch.tsc_offset_adjustment += delta_cyc; 7264 vcpu->arch.last_host_tsc = local_tsc; 7265 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7266 } 7267 7268 /* 7269 * We have to disable TSC offset matching.. if you were 7270 * booting a VM while issuing an S4 host suspend.... 7271 * you may have some problem. Solving this issue is 7272 * left as an exercise to the reader. 7273 */ 7274 kvm->arch.last_tsc_nsec = 0; 7275 kvm->arch.last_tsc_write = 0; 7276 } 7277 7278 } 7279 return 0; 7280 } 7281 7282 void kvm_arch_hardware_disable(void) 7283 { 7284 kvm_x86_ops->hardware_disable(); 7285 drop_user_return_notifiers(); 7286 } 7287 7288 int kvm_arch_hardware_setup(void) 7289 { 7290 int r; 7291 7292 r = kvm_x86_ops->hardware_setup(); 7293 if (r != 0) 7294 return r; 7295 7296 kvm_init_msr_list(); 7297 return 0; 7298 } 7299 7300 void kvm_arch_hardware_unsetup(void) 7301 { 7302 kvm_x86_ops->hardware_unsetup(); 7303 } 7304 7305 void kvm_arch_check_processor_compat(void *rtn) 7306 { 7307 kvm_x86_ops->check_processor_compatibility(rtn); 7308 } 7309 7310 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) 7311 { 7312 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL); 7313 } 7314 7315 struct static_key kvm_no_apic_vcpu __read_mostly; 7316 7317 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 7318 { 7319 struct page *page; 7320 struct kvm *kvm; 7321 int r; 7322 7323 BUG_ON(vcpu->kvm == NULL); 7324 kvm = vcpu->kvm; 7325 7326 vcpu->arch.pv.pv_unhalted = false; 7327 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 7328 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 7329 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7330 else 7331 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 7332 7333 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 7334 if (!page) { 7335 r = -ENOMEM; 7336 goto fail; 7337 } 7338 vcpu->arch.pio_data = page_address(page); 7339 7340 kvm_set_tsc_khz(vcpu, max_tsc_khz); 7341 7342 r = kvm_mmu_create(vcpu); 7343 if (r < 0) 7344 goto fail_free_pio_data; 7345 7346 if (irqchip_in_kernel(kvm)) { 7347 r = kvm_create_lapic(vcpu); 7348 if (r < 0) 7349 goto fail_mmu_destroy; 7350 } else 7351 static_key_slow_inc(&kvm_no_apic_vcpu); 7352 7353 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 7354 GFP_KERNEL); 7355 if (!vcpu->arch.mce_banks) { 7356 r = -ENOMEM; 7357 goto fail_free_lapic; 7358 } 7359 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 7360 7361 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 7362 r = -ENOMEM; 7363 goto fail_free_mce_banks; 7364 } 7365 7366 r = fx_init(vcpu); 7367 if (r) 7368 goto fail_free_wbinvd_dirty_mask; 7369 7370 vcpu->arch.ia32_tsc_adjust_msr = 0x0; 7371 vcpu->arch.pv_time_enabled = false; 7372 7373 vcpu->arch.guest_supported_xcr0 = 0; 7374 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 7375 7376 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 7377 7378 kvm_async_pf_hash_reset(vcpu); 7379 kvm_pmu_init(vcpu); 7380 7381 return 0; 7382 fail_free_wbinvd_dirty_mask: 7383 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 7384 fail_free_mce_banks: 7385 kfree(vcpu->arch.mce_banks); 7386 fail_free_lapic: 7387 kvm_free_lapic(vcpu); 7388 fail_mmu_destroy: 7389 kvm_mmu_destroy(vcpu); 7390 fail_free_pio_data: 7391 free_page((unsigned long)vcpu->arch.pio_data); 7392 fail: 7393 return r; 7394 } 7395 7396 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 7397 { 7398 int idx; 7399 7400 kvm_pmu_destroy(vcpu); 7401 kfree(vcpu->arch.mce_banks); 7402 kvm_free_lapic(vcpu); 7403 idx = srcu_read_lock(&vcpu->kvm->srcu); 7404 kvm_mmu_destroy(vcpu); 7405 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7406 free_page((unsigned long)vcpu->arch.pio_data); 7407 if (!irqchip_in_kernel(vcpu->kvm)) 7408 static_key_slow_dec(&kvm_no_apic_vcpu); 7409 } 7410 7411 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 7412 { 7413 kvm_x86_ops->sched_in(vcpu, cpu); 7414 } 7415 7416 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 7417 { 7418 if (type) 7419 return -EINVAL; 7420 7421 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 7422 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 7423 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 7424 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 7425 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 7426 7427 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 7428 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 7429 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 7430 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 7431 &kvm->arch.irq_sources_bitmap); 7432 7433 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 7434 mutex_init(&kvm->arch.apic_map_lock); 7435 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 7436 7437 pvclock_update_vm_gtod_copy(kvm); 7438 7439 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 7440 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 7441 7442 return 0; 7443 } 7444 7445 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 7446 { 7447 int r; 7448 r = vcpu_load(vcpu); 7449 BUG_ON(r); 7450 kvm_mmu_unload(vcpu); 7451 vcpu_put(vcpu); 7452 } 7453 7454 static void kvm_free_vcpus(struct kvm *kvm) 7455 { 7456 unsigned int i; 7457 struct kvm_vcpu *vcpu; 7458 7459 /* 7460 * Unpin any mmu pages first. 7461 */ 7462 kvm_for_each_vcpu(i, vcpu, kvm) { 7463 kvm_clear_async_pf_completion_queue(vcpu); 7464 kvm_unload_vcpu_mmu(vcpu); 7465 } 7466 kvm_for_each_vcpu(i, vcpu, kvm) 7467 kvm_arch_vcpu_free(vcpu); 7468 7469 mutex_lock(&kvm->lock); 7470 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 7471 kvm->vcpus[i] = NULL; 7472 7473 atomic_set(&kvm->online_vcpus, 0); 7474 mutex_unlock(&kvm->lock); 7475 } 7476 7477 void kvm_arch_sync_events(struct kvm *kvm) 7478 { 7479 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 7480 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 7481 kvm_free_all_assigned_devices(kvm); 7482 kvm_free_pit(kvm); 7483 } 7484 7485 void kvm_arch_destroy_vm(struct kvm *kvm) 7486 { 7487 if (current->mm == kvm->mm) { 7488 /* 7489 * Free memory regions allocated on behalf of userspace, 7490 * unless the the memory map has changed due to process exit 7491 * or fd copying. 7492 */ 7493 struct kvm_userspace_memory_region mem; 7494 memset(&mem, 0, sizeof(mem)); 7495 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; 7496 kvm_set_memory_region(kvm, &mem); 7497 7498 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; 7499 kvm_set_memory_region(kvm, &mem); 7500 7501 mem.slot = TSS_PRIVATE_MEMSLOT; 7502 kvm_set_memory_region(kvm, &mem); 7503 } 7504 kvm_iommu_unmap_guest(kvm); 7505 kfree(kvm->arch.vpic); 7506 kfree(kvm->arch.vioapic); 7507 kvm_free_vcpus(kvm); 7508 kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 7509 } 7510 7511 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 7512 struct kvm_memory_slot *dont) 7513 { 7514 int i; 7515 7516 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7517 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 7518 kvfree(free->arch.rmap[i]); 7519 free->arch.rmap[i] = NULL; 7520 } 7521 if (i == 0) 7522 continue; 7523 7524 if (!dont || free->arch.lpage_info[i - 1] != 7525 dont->arch.lpage_info[i - 1]) { 7526 kvfree(free->arch.lpage_info[i - 1]); 7527 free->arch.lpage_info[i - 1] = NULL; 7528 } 7529 } 7530 } 7531 7532 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 7533 unsigned long npages) 7534 { 7535 int i; 7536 7537 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7538 unsigned long ugfn; 7539 int lpages; 7540 int level = i + 1; 7541 7542 lpages = gfn_to_index(slot->base_gfn + npages - 1, 7543 slot->base_gfn, level) + 1; 7544 7545 slot->arch.rmap[i] = 7546 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); 7547 if (!slot->arch.rmap[i]) 7548 goto out_free; 7549 if (i == 0) 7550 continue; 7551 7552 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages * 7553 sizeof(*slot->arch.lpage_info[i - 1])); 7554 if (!slot->arch.lpage_info[i - 1]) 7555 goto out_free; 7556 7557 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 7558 slot->arch.lpage_info[i - 1][0].write_count = 1; 7559 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 7560 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1; 7561 ugfn = slot->userspace_addr >> PAGE_SHIFT; 7562 /* 7563 * If the gfn and userspace address are not aligned wrt each 7564 * other, or if explicitly asked to, disable large page 7565 * support for this slot 7566 */ 7567 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 7568 !kvm_largepages_enabled()) { 7569 unsigned long j; 7570 7571 for (j = 0; j < lpages; ++j) 7572 slot->arch.lpage_info[i - 1][j].write_count = 1; 7573 } 7574 } 7575 7576 return 0; 7577 7578 out_free: 7579 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7580 kvfree(slot->arch.rmap[i]); 7581 slot->arch.rmap[i] = NULL; 7582 if (i == 0) 7583 continue; 7584 7585 kvfree(slot->arch.lpage_info[i - 1]); 7586 slot->arch.lpage_info[i - 1] = NULL; 7587 } 7588 return -ENOMEM; 7589 } 7590 7591 void kvm_arch_memslots_updated(struct kvm *kvm) 7592 { 7593 /* 7594 * memslots->generation has been incremented. 7595 * mmio generation may have reached its maximum value. 7596 */ 7597 kvm_mmu_invalidate_mmio_sptes(kvm); 7598 } 7599 7600 int kvm_arch_prepare_memory_region(struct kvm *kvm, 7601 struct kvm_memory_slot *memslot, 7602 struct kvm_userspace_memory_region *mem, 7603 enum kvm_mr_change change) 7604 { 7605 /* 7606 * Only private memory slots need to be mapped here since 7607 * KVM_SET_MEMORY_REGION ioctl is no longer supported. 7608 */ 7609 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) { 7610 unsigned long userspace_addr; 7611 7612 /* 7613 * MAP_SHARED to prevent internal slot pages from being moved 7614 * by fork()/COW. 7615 */ 7616 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE, 7617 PROT_READ | PROT_WRITE, 7618 MAP_SHARED | MAP_ANONYMOUS, 0); 7619 7620 if (IS_ERR((void *)userspace_addr)) 7621 return PTR_ERR((void *)userspace_addr); 7622 7623 memslot->userspace_addr = userspace_addr; 7624 } 7625 7626 return 0; 7627 } 7628 7629 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 7630 struct kvm_memory_slot *new) 7631 { 7632 /* Still write protect RO slot */ 7633 if (new->flags & KVM_MEM_READONLY) { 7634 kvm_mmu_slot_remove_write_access(kvm, new); 7635 return; 7636 } 7637 7638 /* 7639 * Call kvm_x86_ops dirty logging hooks when they are valid. 7640 * 7641 * kvm_x86_ops->slot_disable_log_dirty is called when: 7642 * 7643 * - KVM_MR_CREATE with dirty logging is disabled 7644 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 7645 * 7646 * The reason is, in case of PML, we need to set D-bit for any slots 7647 * with dirty logging disabled in order to eliminate unnecessary GPA 7648 * logging in PML buffer (and potential PML buffer full VMEXT). This 7649 * guarantees leaving PML enabled during guest's lifetime won't have 7650 * any additonal overhead from PML when guest is running with dirty 7651 * logging disabled for memory slots. 7652 * 7653 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 7654 * to dirty logging mode. 7655 * 7656 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 7657 * 7658 * In case of write protect: 7659 * 7660 * Write protect all pages for dirty logging. 7661 * 7662 * All the sptes including the large sptes which point to this 7663 * slot are set to readonly. We can not create any new large 7664 * spte on this slot until the end of the logging. 7665 * 7666 * See the comments in fast_page_fault(). 7667 */ 7668 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 7669 if (kvm_x86_ops->slot_enable_log_dirty) 7670 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 7671 else 7672 kvm_mmu_slot_remove_write_access(kvm, new); 7673 } else { 7674 if (kvm_x86_ops->slot_disable_log_dirty) 7675 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 7676 } 7677 } 7678 7679 void kvm_arch_commit_memory_region(struct kvm *kvm, 7680 struct kvm_userspace_memory_region *mem, 7681 const struct kvm_memory_slot *old, 7682 enum kvm_mr_change change) 7683 { 7684 struct kvm_memory_slot *new; 7685 int nr_mmu_pages = 0; 7686 7687 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) { 7688 int ret; 7689 7690 ret = vm_munmap(old->userspace_addr, 7691 old->npages * PAGE_SIZE); 7692 if (ret < 0) 7693 printk(KERN_WARNING 7694 "kvm_vm_ioctl_set_memory_region: " 7695 "failed to munmap memory\n"); 7696 } 7697 7698 if (!kvm->arch.n_requested_mmu_pages) 7699 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 7700 7701 if (nr_mmu_pages) 7702 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 7703 7704 /* It's OK to get 'new' slot here as it has already been installed */ 7705 new = id_to_memslot(kvm->memslots, mem->slot); 7706 7707 /* 7708 * Dirty logging tracks sptes in 4k granularity, meaning that large 7709 * sptes have to be split. If live migration is successful, the guest 7710 * in the source machine will be destroyed and large sptes will be 7711 * created in the destination. However, if the guest continues to run 7712 * in the source machine (for example if live migration fails), small 7713 * sptes will remain around and cause bad performance. 7714 * 7715 * Scan sptes if dirty logging has been stopped, dropping those 7716 * which can be collapsed into a single large-page spte. Later 7717 * page faults will create the large-page sptes. 7718 */ 7719 if ((change != KVM_MR_DELETE) && 7720 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 7721 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 7722 kvm_mmu_zap_collapsible_sptes(kvm, new); 7723 7724 /* 7725 * Set up write protection and/or dirty logging for the new slot. 7726 * 7727 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 7728 * been zapped so no dirty logging staff is needed for old slot. For 7729 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 7730 * new and it's also covered when dealing with the new slot. 7731 */ 7732 if (change != KVM_MR_DELETE) 7733 kvm_mmu_slot_apply_flags(kvm, new); 7734 } 7735 7736 void kvm_arch_flush_shadow_all(struct kvm *kvm) 7737 { 7738 kvm_mmu_invalidate_zap_all_pages(kvm); 7739 } 7740 7741 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 7742 struct kvm_memory_slot *slot) 7743 { 7744 kvm_mmu_invalidate_zap_all_pages(kvm); 7745 } 7746 7747 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 7748 { 7749 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 7750 kvm_x86_ops->check_nested_events(vcpu, false); 7751 7752 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 7753 !vcpu->arch.apf.halted) 7754 || !list_empty_careful(&vcpu->async_pf.done) 7755 || kvm_apic_has_events(vcpu) 7756 || vcpu->arch.pv.pv_unhalted 7757 || atomic_read(&vcpu->arch.nmi_queued) || 7758 (kvm_arch_interrupt_allowed(vcpu) && 7759 kvm_cpu_has_interrupt(vcpu)); 7760 } 7761 7762 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 7763 { 7764 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 7765 } 7766 7767 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 7768 { 7769 return kvm_x86_ops->interrupt_allowed(vcpu); 7770 } 7771 7772 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 7773 { 7774 if (is_64_bit_mode(vcpu)) 7775 return kvm_rip_read(vcpu); 7776 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 7777 kvm_rip_read(vcpu)); 7778 } 7779 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 7780 7781 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 7782 { 7783 return kvm_get_linear_rip(vcpu) == linear_rip; 7784 } 7785 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 7786 7787 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 7788 { 7789 unsigned long rflags; 7790 7791 rflags = kvm_x86_ops->get_rflags(vcpu); 7792 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 7793 rflags &= ~X86_EFLAGS_TF; 7794 return rflags; 7795 } 7796 EXPORT_SYMBOL_GPL(kvm_get_rflags); 7797 7798 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 7799 { 7800 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 7801 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 7802 rflags |= X86_EFLAGS_TF; 7803 kvm_x86_ops->set_rflags(vcpu, rflags); 7804 } 7805 7806 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 7807 { 7808 __kvm_set_rflags(vcpu, rflags); 7809 kvm_make_request(KVM_REQ_EVENT, vcpu); 7810 } 7811 EXPORT_SYMBOL_GPL(kvm_set_rflags); 7812 7813 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 7814 { 7815 int r; 7816 7817 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 7818 work->wakeup_all) 7819 return; 7820 7821 r = kvm_mmu_reload(vcpu); 7822 if (unlikely(r)) 7823 return; 7824 7825 if (!vcpu->arch.mmu.direct_map && 7826 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 7827 return; 7828 7829 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 7830 } 7831 7832 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 7833 { 7834 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 7835 } 7836 7837 static inline u32 kvm_async_pf_next_probe(u32 key) 7838 { 7839 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 7840 } 7841 7842 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7843 { 7844 u32 key = kvm_async_pf_hash_fn(gfn); 7845 7846 while (vcpu->arch.apf.gfns[key] != ~0) 7847 key = kvm_async_pf_next_probe(key); 7848 7849 vcpu->arch.apf.gfns[key] = gfn; 7850 } 7851 7852 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 7853 { 7854 int i; 7855 u32 key = kvm_async_pf_hash_fn(gfn); 7856 7857 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 7858 (vcpu->arch.apf.gfns[key] != gfn && 7859 vcpu->arch.apf.gfns[key] != ~0); i++) 7860 key = kvm_async_pf_next_probe(key); 7861 7862 return key; 7863 } 7864 7865 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7866 { 7867 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 7868 } 7869 7870 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7871 { 7872 u32 i, j, k; 7873 7874 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 7875 while (true) { 7876 vcpu->arch.apf.gfns[i] = ~0; 7877 do { 7878 j = kvm_async_pf_next_probe(j); 7879 if (vcpu->arch.apf.gfns[j] == ~0) 7880 return; 7881 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 7882 /* 7883 * k lies cyclically in ]i,j] 7884 * | i.k.j | 7885 * |....j i.k.| or |.k..j i...| 7886 */ 7887 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 7888 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 7889 i = j; 7890 } 7891 } 7892 7893 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 7894 { 7895 7896 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 7897 sizeof(val)); 7898 } 7899 7900 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 7901 struct kvm_async_pf *work) 7902 { 7903 struct x86_exception fault; 7904 7905 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 7906 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 7907 7908 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 7909 (vcpu->arch.apf.send_user_only && 7910 kvm_x86_ops->get_cpl(vcpu) == 0)) 7911 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 7912 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 7913 fault.vector = PF_VECTOR; 7914 fault.error_code_valid = true; 7915 fault.error_code = 0; 7916 fault.nested_page_fault = false; 7917 fault.address = work->arch.token; 7918 kvm_inject_page_fault(vcpu, &fault); 7919 } 7920 } 7921 7922 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 7923 struct kvm_async_pf *work) 7924 { 7925 struct x86_exception fault; 7926 7927 trace_kvm_async_pf_ready(work->arch.token, work->gva); 7928 if (work->wakeup_all) 7929 work->arch.token = ~0; /* broadcast wakeup */ 7930 else 7931 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 7932 7933 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && 7934 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 7935 fault.vector = PF_VECTOR; 7936 fault.error_code_valid = true; 7937 fault.error_code = 0; 7938 fault.nested_page_fault = false; 7939 fault.address = work->arch.token; 7940 kvm_inject_page_fault(vcpu, &fault); 7941 } 7942 vcpu->arch.apf.halted = false; 7943 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7944 } 7945 7946 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 7947 { 7948 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 7949 return true; 7950 else 7951 return !kvm_event_needs_reinjection(vcpu) && 7952 kvm_x86_ops->interrupt_allowed(vcpu); 7953 } 7954 7955 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 7956 { 7957 atomic_inc(&kvm->arch.noncoherent_dma_count); 7958 } 7959 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 7960 7961 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 7962 { 7963 atomic_dec(&kvm->arch.noncoherent_dma_count); 7964 } 7965 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 7966 7967 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 7968 { 7969 return atomic_read(&kvm->arch.noncoherent_dma_count); 7970 } 7971 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 7972 7973 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 7974 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 7975 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 7976 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 7977 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 7978 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 7979 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 7980 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 7981 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 7982 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 7983 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 7984 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 7985 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 7986 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 7987 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 7988