1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "assigned-dev.h" 31 32 #include <linux/clocksource.h> 33 #include <linux/interrupt.h> 34 #include <linux/kvm.h> 35 #include <linux/fs.h> 36 #include <linux/vmalloc.h> 37 #include <linux/module.h> 38 #include <linux/mman.h> 39 #include <linux/highmem.h> 40 #include <linux/iommu.h> 41 #include <linux/intel-iommu.h> 42 #include <linux/cpufreq.h> 43 #include <linux/user-return-notifier.h> 44 #include <linux/srcu.h> 45 #include <linux/slab.h> 46 #include <linux/perf_event.h> 47 #include <linux/uaccess.h> 48 #include <linux/hash.h> 49 #include <linux/pci.h> 50 #include <linux/timekeeper_internal.h> 51 #include <linux/pvclock_gtod.h> 52 #include <trace/events/kvm.h> 53 54 #define CREATE_TRACE_POINTS 55 #include "trace.h" 56 57 #include <asm/debugreg.h> 58 #include <asm/msr.h> 59 #include <asm/desc.h> 60 #include <asm/mtrr.h> 61 #include <asm/mce.h> 62 #include <asm/i387.h> 63 #include <asm/fpu-internal.h> /* Ugh! */ 64 #include <asm/xcr.h> 65 #include <asm/pvclock.h> 66 #include <asm/div64.h> 67 68 #define MAX_IO_MSRS 256 69 #define KVM_MAX_MCE_BANKS 32 70 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) 71 72 #define emul_to_vcpu(ctxt) \ 73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 74 75 /* EFER defaults: 76 * - enable syscall per default because its emulated by KVM 77 * - enable LME and LMA per default on 64 bit KVM 78 */ 79 #ifdef CONFIG_X86_64 80 static 81 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 82 #else 83 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 84 #endif 85 86 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 87 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 88 89 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 90 static void process_nmi(struct kvm_vcpu *vcpu); 91 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 92 93 struct kvm_x86_ops *kvm_x86_ops; 94 EXPORT_SYMBOL_GPL(kvm_x86_ops); 95 96 static bool ignore_msrs = 0; 97 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 98 99 unsigned int min_timer_period_us = 500; 100 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 101 102 bool kvm_has_tsc_control; 103 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 104 u32 kvm_max_guest_tsc_khz; 105 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 106 107 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 108 static u32 tsc_tolerance_ppm = 250; 109 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 110 111 /* lapic timer advance (tscdeadline mode only) in nanoseconds */ 112 unsigned int lapic_timer_advance_ns = 0; 113 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 114 115 static bool backwards_tsc_observed = false; 116 117 #define KVM_NR_SHARED_MSRS 16 118 119 struct kvm_shared_msrs_global { 120 int nr; 121 u32 msrs[KVM_NR_SHARED_MSRS]; 122 }; 123 124 struct kvm_shared_msrs { 125 struct user_return_notifier urn; 126 bool registered; 127 struct kvm_shared_msr_values { 128 u64 host; 129 u64 curr; 130 } values[KVM_NR_SHARED_MSRS]; 131 }; 132 133 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 134 static struct kvm_shared_msrs __percpu *shared_msrs; 135 136 struct kvm_stats_debugfs_item debugfs_entries[] = { 137 { "pf_fixed", VCPU_STAT(pf_fixed) }, 138 { "pf_guest", VCPU_STAT(pf_guest) }, 139 { "tlb_flush", VCPU_STAT(tlb_flush) }, 140 { "invlpg", VCPU_STAT(invlpg) }, 141 { "exits", VCPU_STAT(exits) }, 142 { "io_exits", VCPU_STAT(io_exits) }, 143 { "mmio_exits", VCPU_STAT(mmio_exits) }, 144 { "signal_exits", VCPU_STAT(signal_exits) }, 145 { "irq_window", VCPU_STAT(irq_window_exits) }, 146 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 147 { "halt_exits", VCPU_STAT(halt_exits) }, 148 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 149 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 150 { "hypercalls", VCPU_STAT(hypercalls) }, 151 { "request_irq", VCPU_STAT(request_irq_exits) }, 152 { "irq_exits", VCPU_STAT(irq_exits) }, 153 { "host_state_reload", VCPU_STAT(host_state_reload) }, 154 { "efer_reload", VCPU_STAT(efer_reload) }, 155 { "fpu_reload", VCPU_STAT(fpu_reload) }, 156 { "insn_emulation", VCPU_STAT(insn_emulation) }, 157 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 158 { "irq_injections", VCPU_STAT(irq_injections) }, 159 { "nmi_injections", VCPU_STAT(nmi_injections) }, 160 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 161 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 162 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 163 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 164 { "mmu_flooded", VM_STAT(mmu_flooded) }, 165 { "mmu_recycled", VM_STAT(mmu_recycled) }, 166 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 167 { "mmu_unsync", VM_STAT(mmu_unsync) }, 168 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 169 { "largepages", VM_STAT(lpages) }, 170 { NULL } 171 }; 172 173 u64 __read_mostly host_xcr0; 174 175 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 176 177 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 178 { 179 int i; 180 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 181 vcpu->arch.apf.gfns[i] = ~0; 182 } 183 184 static void kvm_on_user_return(struct user_return_notifier *urn) 185 { 186 unsigned slot; 187 struct kvm_shared_msrs *locals 188 = container_of(urn, struct kvm_shared_msrs, urn); 189 struct kvm_shared_msr_values *values; 190 191 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 192 values = &locals->values[slot]; 193 if (values->host != values->curr) { 194 wrmsrl(shared_msrs_global.msrs[slot], values->host); 195 values->curr = values->host; 196 } 197 } 198 locals->registered = false; 199 user_return_notifier_unregister(urn); 200 } 201 202 static void shared_msr_update(unsigned slot, u32 msr) 203 { 204 u64 value; 205 unsigned int cpu = smp_processor_id(); 206 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 207 208 /* only read, and nobody should modify it at this time, 209 * so don't need lock */ 210 if (slot >= shared_msrs_global.nr) { 211 printk(KERN_ERR "kvm: invalid MSR slot!"); 212 return; 213 } 214 rdmsrl_safe(msr, &value); 215 smsr->values[slot].host = value; 216 smsr->values[slot].curr = value; 217 } 218 219 void kvm_define_shared_msr(unsigned slot, u32 msr) 220 { 221 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 222 if (slot >= shared_msrs_global.nr) 223 shared_msrs_global.nr = slot + 1; 224 shared_msrs_global.msrs[slot] = msr; 225 /* we need ensured the shared_msr_global have been updated */ 226 smp_wmb(); 227 } 228 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 229 230 static void kvm_shared_msr_cpu_online(void) 231 { 232 unsigned i; 233 234 for (i = 0; i < shared_msrs_global.nr; ++i) 235 shared_msr_update(i, shared_msrs_global.msrs[i]); 236 } 237 238 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 239 { 240 unsigned int cpu = smp_processor_id(); 241 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 242 int err; 243 244 if (((value ^ smsr->values[slot].curr) & mask) == 0) 245 return 0; 246 smsr->values[slot].curr = value; 247 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 248 if (err) 249 return 1; 250 251 if (!smsr->registered) { 252 smsr->urn.on_user_return = kvm_on_user_return; 253 user_return_notifier_register(&smsr->urn); 254 smsr->registered = true; 255 } 256 return 0; 257 } 258 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 259 260 static void drop_user_return_notifiers(void) 261 { 262 unsigned int cpu = smp_processor_id(); 263 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 264 265 if (smsr->registered) 266 kvm_on_user_return(&smsr->urn); 267 } 268 269 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 270 { 271 return vcpu->arch.apic_base; 272 } 273 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 274 275 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 276 { 277 u64 old_state = vcpu->arch.apic_base & 278 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 279 u64 new_state = msr_info->data & 280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 281 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 282 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); 283 284 if (!msr_info->host_initiated && 285 ((msr_info->data & reserved_bits) != 0 || 286 new_state == X2APIC_ENABLE || 287 (new_state == MSR_IA32_APICBASE_ENABLE && 288 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 289 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 290 old_state == 0))) 291 return 1; 292 293 kvm_lapic_set_base(vcpu, msr_info->data); 294 return 0; 295 } 296 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 297 298 asmlinkage __visible void kvm_spurious_fault(void) 299 { 300 /* Fault while not rebooting. We want the trace. */ 301 BUG(); 302 } 303 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 304 305 #define EXCPT_BENIGN 0 306 #define EXCPT_CONTRIBUTORY 1 307 #define EXCPT_PF 2 308 309 static int exception_class(int vector) 310 { 311 switch (vector) { 312 case PF_VECTOR: 313 return EXCPT_PF; 314 case DE_VECTOR: 315 case TS_VECTOR: 316 case NP_VECTOR: 317 case SS_VECTOR: 318 case GP_VECTOR: 319 return EXCPT_CONTRIBUTORY; 320 default: 321 break; 322 } 323 return EXCPT_BENIGN; 324 } 325 326 #define EXCPT_FAULT 0 327 #define EXCPT_TRAP 1 328 #define EXCPT_ABORT 2 329 #define EXCPT_INTERRUPT 3 330 331 static int exception_type(int vector) 332 { 333 unsigned int mask; 334 335 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 336 return EXCPT_INTERRUPT; 337 338 mask = 1 << vector; 339 340 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 341 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 342 return EXCPT_TRAP; 343 344 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 345 return EXCPT_ABORT; 346 347 /* Reserved exceptions will result in fault */ 348 return EXCPT_FAULT; 349 } 350 351 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 352 unsigned nr, bool has_error, u32 error_code, 353 bool reinject) 354 { 355 u32 prev_nr; 356 int class1, class2; 357 358 kvm_make_request(KVM_REQ_EVENT, vcpu); 359 360 if (!vcpu->arch.exception.pending) { 361 queue: 362 if (has_error && !is_protmode(vcpu)) 363 has_error = false; 364 vcpu->arch.exception.pending = true; 365 vcpu->arch.exception.has_error_code = has_error; 366 vcpu->arch.exception.nr = nr; 367 vcpu->arch.exception.error_code = error_code; 368 vcpu->arch.exception.reinject = reinject; 369 return; 370 } 371 372 /* to check exception */ 373 prev_nr = vcpu->arch.exception.nr; 374 if (prev_nr == DF_VECTOR) { 375 /* triple fault -> shutdown */ 376 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 377 return; 378 } 379 class1 = exception_class(prev_nr); 380 class2 = exception_class(nr); 381 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 382 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 383 /* generate double fault per SDM Table 5-5 */ 384 vcpu->arch.exception.pending = true; 385 vcpu->arch.exception.has_error_code = true; 386 vcpu->arch.exception.nr = DF_VECTOR; 387 vcpu->arch.exception.error_code = 0; 388 } else 389 /* replace previous exception with a new one in a hope 390 that instruction re-execution will regenerate lost 391 exception */ 392 goto queue; 393 } 394 395 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 396 { 397 kvm_multiple_exception(vcpu, nr, false, 0, false); 398 } 399 EXPORT_SYMBOL_GPL(kvm_queue_exception); 400 401 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 402 { 403 kvm_multiple_exception(vcpu, nr, false, 0, true); 404 } 405 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 406 407 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 408 { 409 if (err) 410 kvm_inject_gp(vcpu, 0); 411 else 412 kvm_x86_ops->skip_emulated_instruction(vcpu); 413 } 414 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 415 416 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 417 { 418 ++vcpu->stat.pf_guest; 419 vcpu->arch.cr2 = fault->address; 420 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 421 } 422 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 423 424 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 425 { 426 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 427 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 428 else 429 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 430 431 return fault->nested_page_fault; 432 } 433 434 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 435 { 436 atomic_inc(&vcpu->arch.nmi_queued); 437 kvm_make_request(KVM_REQ_NMI, vcpu); 438 } 439 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 440 441 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 442 { 443 kvm_multiple_exception(vcpu, nr, true, error_code, false); 444 } 445 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 446 447 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 448 { 449 kvm_multiple_exception(vcpu, nr, true, error_code, true); 450 } 451 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 452 453 /* 454 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 455 * a #GP and return false. 456 */ 457 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 458 { 459 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 460 return true; 461 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 462 return false; 463 } 464 EXPORT_SYMBOL_GPL(kvm_require_cpl); 465 466 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 467 { 468 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 469 return true; 470 471 kvm_queue_exception(vcpu, UD_VECTOR); 472 return false; 473 } 474 EXPORT_SYMBOL_GPL(kvm_require_dr); 475 476 /* 477 * This function will be used to read from the physical memory of the currently 478 * running guest. The difference to kvm_read_guest_page is that this function 479 * can read from guest physical or from the guest's guest physical memory. 480 */ 481 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 482 gfn_t ngfn, void *data, int offset, int len, 483 u32 access) 484 { 485 struct x86_exception exception; 486 gfn_t real_gfn; 487 gpa_t ngpa; 488 489 ngpa = gfn_to_gpa(ngfn); 490 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 491 if (real_gfn == UNMAPPED_GVA) 492 return -EFAULT; 493 494 real_gfn = gpa_to_gfn(real_gfn); 495 496 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len); 497 } 498 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 499 500 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 501 void *data, int offset, int len, u32 access) 502 { 503 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 504 data, offset, len, access); 505 } 506 507 /* 508 * Load the pae pdptrs. Return true is they are all valid. 509 */ 510 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 511 { 512 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 513 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 514 int i; 515 int ret; 516 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 517 518 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 519 offset * sizeof(u64), sizeof(pdpte), 520 PFERR_USER_MASK|PFERR_WRITE_MASK); 521 if (ret < 0) { 522 ret = 0; 523 goto out; 524 } 525 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 526 if (is_present_gpte(pdpte[i]) && 527 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { 528 ret = 0; 529 goto out; 530 } 531 } 532 ret = 1; 533 534 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 535 __set_bit(VCPU_EXREG_PDPTR, 536 (unsigned long *)&vcpu->arch.regs_avail); 537 __set_bit(VCPU_EXREG_PDPTR, 538 (unsigned long *)&vcpu->arch.regs_dirty); 539 out: 540 541 return ret; 542 } 543 EXPORT_SYMBOL_GPL(load_pdptrs); 544 545 static bool pdptrs_changed(struct kvm_vcpu *vcpu) 546 { 547 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 548 bool changed = true; 549 int offset; 550 gfn_t gfn; 551 int r; 552 553 if (is_long_mode(vcpu) || !is_pae(vcpu)) 554 return false; 555 556 if (!test_bit(VCPU_EXREG_PDPTR, 557 (unsigned long *)&vcpu->arch.regs_avail)) 558 return true; 559 560 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; 561 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); 562 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 563 PFERR_USER_MASK | PFERR_WRITE_MASK); 564 if (r < 0) 565 goto out; 566 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 567 out: 568 569 return changed; 570 } 571 572 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 573 { 574 unsigned long old_cr0 = kvm_read_cr0(vcpu); 575 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP | 576 X86_CR0_CD | X86_CR0_NW; 577 578 cr0 |= X86_CR0_ET; 579 580 #ifdef CONFIG_X86_64 581 if (cr0 & 0xffffffff00000000UL) 582 return 1; 583 #endif 584 585 cr0 &= ~CR0_RESERVED_BITS; 586 587 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 588 return 1; 589 590 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 591 return 1; 592 593 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 594 #ifdef CONFIG_X86_64 595 if ((vcpu->arch.efer & EFER_LME)) { 596 int cs_db, cs_l; 597 598 if (!is_pae(vcpu)) 599 return 1; 600 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 601 if (cs_l) 602 return 1; 603 } else 604 #endif 605 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 606 kvm_read_cr3(vcpu))) 607 return 1; 608 } 609 610 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 611 return 1; 612 613 kvm_x86_ops->set_cr0(vcpu, cr0); 614 615 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 616 kvm_clear_async_pf_completion_queue(vcpu); 617 kvm_async_pf_hash_reset(vcpu); 618 } 619 620 if ((cr0 ^ old_cr0) & update_bits) 621 kvm_mmu_reset_context(vcpu); 622 return 0; 623 } 624 EXPORT_SYMBOL_GPL(kvm_set_cr0); 625 626 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 627 { 628 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 629 } 630 EXPORT_SYMBOL_GPL(kvm_lmsw); 631 632 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 633 { 634 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 635 !vcpu->guest_xcr0_loaded) { 636 /* kvm_set_xcr() also depends on this */ 637 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 638 vcpu->guest_xcr0_loaded = 1; 639 } 640 } 641 642 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 643 { 644 if (vcpu->guest_xcr0_loaded) { 645 if (vcpu->arch.xcr0 != host_xcr0) 646 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 647 vcpu->guest_xcr0_loaded = 0; 648 } 649 } 650 651 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 652 { 653 u64 xcr0 = xcr; 654 u64 old_xcr0 = vcpu->arch.xcr0; 655 u64 valid_bits; 656 657 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 658 if (index != XCR_XFEATURE_ENABLED_MASK) 659 return 1; 660 if (!(xcr0 & XSTATE_FP)) 661 return 1; 662 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) 663 return 1; 664 665 /* 666 * Do not allow the guest to set bits that we do not support 667 * saving. However, xcr0 bit 0 is always set, even if the 668 * emulated CPU does not support XSAVE (see fx_init). 669 */ 670 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP; 671 if (xcr0 & ~valid_bits) 672 return 1; 673 674 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR))) 675 return 1; 676 677 if (xcr0 & XSTATE_AVX512) { 678 if (!(xcr0 & XSTATE_YMM)) 679 return 1; 680 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512) 681 return 1; 682 } 683 kvm_put_guest_xcr0(vcpu); 684 vcpu->arch.xcr0 = xcr0; 685 686 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK) 687 kvm_update_cpuid(vcpu); 688 return 0; 689 } 690 691 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 692 { 693 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 694 __kvm_set_xcr(vcpu, index, xcr)) { 695 kvm_inject_gp(vcpu, 0); 696 return 1; 697 } 698 return 0; 699 } 700 EXPORT_SYMBOL_GPL(kvm_set_xcr); 701 702 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 703 { 704 unsigned long old_cr4 = kvm_read_cr4(vcpu); 705 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | 706 X86_CR4_PAE | X86_CR4_SMEP; 707 if (cr4 & CR4_RESERVED_BITS) 708 return 1; 709 710 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) 711 return 1; 712 713 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) 714 return 1; 715 716 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) 717 return 1; 718 719 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) 720 return 1; 721 722 if (is_long_mode(vcpu)) { 723 if (!(cr4 & X86_CR4_PAE)) 724 return 1; 725 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 726 && ((cr4 ^ old_cr4) & pdptr_bits) 727 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 728 kvm_read_cr3(vcpu))) 729 return 1; 730 731 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 732 if (!guest_cpuid_has_pcid(vcpu)) 733 return 1; 734 735 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 736 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 737 return 1; 738 } 739 740 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 741 return 1; 742 743 if (((cr4 ^ old_cr4) & pdptr_bits) || 744 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 745 kvm_mmu_reset_context(vcpu); 746 747 if ((cr4 ^ old_cr4) & X86_CR4_SMAP) 748 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false); 749 750 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) 751 kvm_update_cpuid(vcpu); 752 753 return 0; 754 } 755 EXPORT_SYMBOL_GPL(kvm_set_cr4); 756 757 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 758 { 759 #ifdef CONFIG_X86_64 760 cr3 &= ~CR3_PCID_INVD; 761 #endif 762 763 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 764 kvm_mmu_sync_roots(vcpu); 765 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 766 return 0; 767 } 768 769 if (is_long_mode(vcpu)) { 770 if (cr3 & CR3_L_MODE_RESERVED_BITS) 771 return 1; 772 } else if (is_pae(vcpu) && is_paging(vcpu) && 773 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 774 return 1; 775 776 vcpu->arch.cr3 = cr3; 777 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 778 kvm_mmu_new_cr3(vcpu); 779 return 0; 780 } 781 EXPORT_SYMBOL_GPL(kvm_set_cr3); 782 783 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 784 { 785 if (cr8 & CR8_RESERVED_BITS) 786 return 1; 787 if (irqchip_in_kernel(vcpu->kvm)) 788 kvm_lapic_set_tpr(vcpu, cr8); 789 else 790 vcpu->arch.cr8 = cr8; 791 return 0; 792 } 793 EXPORT_SYMBOL_GPL(kvm_set_cr8); 794 795 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 796 { 797 if (irqchip_in_kernel(vcpu->kvm)) 798 return kvm_lapic_get_cr8(vcpu); 799 else 800 return vcpu->arch.cr8; 801 } 802 EXPORT_SYMBOL_GPL(kvm_get_cr8); 803 804 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 805 { 806 int i; 807 808 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 809 for (i = 0; i < KVM_NR_DB_REGS; i++) 810 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 811 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 812 } 813 } 814 815 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 816 { 817 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 818 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 819 } 820 821 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 822 { 823 unsigned long dr7; 824 825 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 826 dr7 = vcpu->arch.guest_debug_dr7; 827 else 828 dr7 = vcpu->arch.dr7; 829 kvm_x86_ops->set_dr7(vcpu, dr7); 830 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 831 if (dr7 & DR7_BP_EN_MASK) 832 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 833 } 834 835 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 836 { 837 u64 fixed = DR6_FIXED_1; 838 839 if (!guest_cpuid_has_rtm(vcpu)) 840 fixed |= DR6_RTM; 841 return fixed; 842 } 843 844 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 845 { 846 switch (dr) { 847 case 0 ... 3: 848 vcpu->arch.db[dr] = val; 849 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 850 vcpu->arch.eff_db[dr] = val; 851 break; 852 case 4: 853 /* fall through */ 854 case 6: 855 if (val & 0xffffffff00000000ULL) 856 return -1; /* #GP */ 857 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 858 kvm_update_dr6(vcpu); 859 break; 860 case 5: 861 /* fall through */ 862 default: /* 7 */ 863 if (val & 0xffffffff00000000ULL) 864 return -1; /* #GP */ 865 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 866 kvm_update_dr7(vcpu); 867 break; 868 } 869 870 return 0; 871 } 872 873 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 874 { 875 if (__kvm_set_dr(vcpu, dr, val)) { 876 kvm_inject_gp(vcpu, 0); 877 return 1; 878 } 879 return 0; 880 } 881 EXPORT_SYMBOL_GPL(kvm_set_dr); 882 883 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 884 { 885 switch (dr) { 886 case 0 ... 3: 887 *val = vcpu->arch.db[dr]; 888 break; 889 case 4: 890 /* fall through */ 891 case 6: 892 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 893 *val = vcpu->arch.dr6; 894 else 895 *val = kvm_x86_ops->get_dr6(vcpu); 896 break; 897 case 5: 898 /* fall through */ 899 default: /* 7 */ 900 *val = vcpu->arch.dr7; 901 break; 902 } 903 return 0; 904 } 905 EXPORT_SYMBOL_GPL(kvm_get_dr); 906 907 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 908 { 909 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 910 u64 data; 911 int err; 912 913 err = kvm_pmu_read_pmc(vcpu, ecx, &data); 914 if (err) 915 return err; 916 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 917 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 918 return err; 919 } 920 EXPORT_SYMBOL_GPL(kvm_rdpmc); 921 922 /* 923 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 924 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 925 * 926 * This list is modified at module load time to reflect the 927 * capabilities of the host cpu. This capabilities test skips MSRs that are 928 * kvm-specific. Those are put in the beginning of the list. 929 */ 930 931 #define KVM_SAVE_MSRS_BEGIN 12 932 static u32 msrs_to_save[] = { 933 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 934 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 935 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 936 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 937 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 938 MSR_KVM_PV_EOI_EN, 939 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 940 MSR_STAR, 941 #ifdef CONFIG_X86_64 942 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 943 #endif 944 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 945 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS 946 }; 947 948 static unsigned num_msrs_to_save; 949 950 static const u32 emulated_msrs[] = { 951 MSR_IA32_TSC_ADJUST, 952 MSR_IA32_TSCDEADLINE, 953 MSR_IA32_MISC_ENABLE, 954 MSR_IA32_MCG_STATUS, 955 MSR_IA32_MCG_CTL, 956 }; 957 958 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 959 { 960 if (efer & efer_reserved_bits) 961 return false; 962 963 if (efer & EFER_FFXSR) { 964 struct kvm_cpuid_entry2 *feat; 965 966 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 967 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) 968 return false; 969 } 970 971 if (efer & EFER_SVME) { 972 struct kvm_cpuid_entry2 *feat; 973 974 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 975 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) 976 return false; 977 } 978 979 return true; 980 } 981 EXPORT_SYMBOL_GPL(kvm_valid_efer); 982 983 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 984 { 985 u64 old_efer = vcpu->arch.efer; 986 987 if (!kvm_valid_efer(vcpu, efer)) 988 return 1; 989 990 if (is_paging(vcpu) 991 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 992 return 1; 993 994 efer &= ~EFER_LMA; 995 efer |= vcpu->arch.efer & EFER_LMA; 996 997 kvm_x86_ops->set_efer(vcpu, efer); 998 999 /* Update reserved bits */ 1000 if ((efer ^ old_efer) & EFER_NX) 1001 kvm_mmu_reset_context(vcpu); 1002 1003 return 0; 1004 } 1005 1006 void kvm_enable_efer_bits(u64 mask) 1007 { 1008 efer_reserved_bits &= ~mask; 1009 } 1010 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1011 1012 /* 1013 * Writes msr value into into the appropriate "register". 1014 * Returns 0 on success, non-0 otherwise. 1015 * Assumes vcpu_load() was already called. 1016 */ 1017 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1018 { 1019 switch (msr->index) { 1020 case MSR_FS_BASE: 1021 case MSR_GS_BASE: 1022 case MSR_KERNEL_GS_BASE: 1023 case MSR_CSTAR: 1024 case MSR_LSTAR: 1025 if (is_noncanonical_address(msr->data)) 1026 return 1; 1027 break; 1028 case MSR_IA32_SYSENTER_EIP: 1029 case MSR_IA32_SYSENTER_ESP: 1030 /* 1031 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1032 * non-canonical address is written on Intel but not on 1033 * AMD (which ignores the top 32-bits, because it does 1034 * not implement 64-bit SYSENTER). 1035 * 1036 * 64-bit code should hence be able to write a non-canonical 1037 * value on AMD. Making the address canonical ensures that 1038 * vmentry does not fail on Intel after writing a non-canonical 1039 * value, and that something deterministic happens if the guest 1040 * invokes 64-bit SYSENTER. 1041 */ 1042 msr->data = get_canonical(msr->data); 1043 } 1044 return kvm_x86_ops->set_msr(vcpu, msr); 1045 } 1046 EXPORT_SYMBOL_GPL(kvm_set_msr); 1047 1048 /* 1049 * Adapt set_msr() to msr_io()'s calling convention 1050 */ 1051 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1052 { 1053 struct msr_data msr; 1054 1055 msr.data = *data; 1056 msr.index = index; 1057 msr.host_initiated = true; 1058 return kvm_set_msr(vcpu, &msr); 1059 } 1060 1061 #ifdef CONFIG_X86_64 1062 struct pvclock_gtod_data { 1063 seqcount_t seq; 1064 1065 struct { /* extract of a clocksource struct */ 1066 int vclock_mode; 1067 cycle_t cycle_last; 1068 cycle_t mask; 1069 u32 mult; 1070 u32 shift; 1071 } clock; 1072 1073 u64 boot_ns; 1074 u64 nsec_base; 1075 }; 1076 1077 static struct pvclock_gtod_data pvclock_gtod_data; 1078 1079 static void update_pvclock_gtod(struct timekeeper *tk) 1080 { 1081 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1082 u64 boot_ns; 1083 1084 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1085 1086 write_seqcount_begin(&vdata->seq); 1087 1088 /* copy pvclock gtod data */ 1089 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1090 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1091 vdata->clock.mask = tk->tkr_mono.mask; 1092 vdata->clock.mult = tk->tkr_mono.mult; 1093 vdata->clock.shift = tk->tkr_mono.shift; 1094 1095 vdata->boot_ns = boot_ns; 1096 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1097 1098 write_seqcount_end(&vdata->seq); 1099 } 1100 #endif 1101 1102 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1103 { 1104 /* 1105 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1106 * vcpu_enter_guest. This function is only called from 1107 * the physical CPU that is running vcpu. 1108 */ 1109 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1110 } 1111 1112 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1113 { 1114 int version; 1115 int r; 1116 struct pvclock_wall_clock wc; 1117 struct timespec boot; 1118 1119 if (!wall_clock) 1120 return; 1121 1122 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1123 if (r) 1124 return; 1125 1126 if (version & 1) 1127 ++version; /* first time write, random junk */ 1128 1129 ++version; 1130 1131 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1132 1133 /* 1134 * The guest calculates current wall clock time by adding 1135 * system time (updated by kvm_guest_time_update below) to the 1136 * wall clock specified here. guest system time equals host 1137 * system time for us, thus we must fill in host boot time here. 1138 */ 1139 getboottime(&boot); 1140 1141 if (kvm->arch.kvmclock_offset) { 1142 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); 1143 boot = timespec_sub(boot, ts); 1144 } 1145 wc.sec = boot.tv_sec; 1146 wc.nsec = boot.tv_nsec; 1147 wc.version = version; 1148 1149 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1150 1151 version++; 1152 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1153 } 1154 1155 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1156 { 1157 uint32_t quotient, remainder; 1158 1159 /* Don't try to replace with do_div(), this one calculates 1160 * "(dividend << 32) / divisor" */ 1161 __asm__ ( "divl %4" 1162 : "=a" (quotient), "=d" (remainder) 1163 : "0" (0), "1" (dividend), "r" (divisor) ); 1164 return quotient; 1165 } 1166 1167 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, 1168 s8 *pshift, u32 *pmultiplier) 1169 { 1170 uint64_t scaled64; 1171 int32_t shift = 0; 1172 uint64_t tps64; 1173 uint32_t tps32; 1174 1175 tps64 = base_khz * 1000LL; 1176 scaled64 = scaled_khz * 1000LL; 1177 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1178 tps64 >>= 1; 1179 shift--; 1180 } 1181 1182 tps32 = (uint32_t)tps64; 1183 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1184 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1185 scaled64 >>= 1; 1186 else 1187 tps32 <<= 1; 1188 shift++; 1189 } 1190 1191 *pshift = shift; 1192 *pmultiplier = div_frac(scaled64, tps32); 1193 1194 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", 1195 __func__, base_khz, scaled_khz, shift, *pmultiplier); 1196 } 1197 1198 static inline u64 get_kernel_ns(void) 1199 { 1200 return ktime_get_boot_ns(); 1201 } 1202 1203 #ifdef CONFIG_X86_64 1204 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1205 #endif 1206 1207 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1208 static unsigned long max_tsc_khz; 1209 1210 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) 1211 { 1212 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, 1213 vcpu->arch.virtual_tsc_shift); 1214 } 1215 1216 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1217 { 1218 u64 v = (u64)khz * (1000000 + ppm); 1219 do_div(v, 1000000); 1220 return v; 1221 } 1222 1223 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) 1224 { 1225 u32 thresh_lo, thresh_hi; 1226 int use_scaling = 0; 1227 1228 /* tsc_khz can be zero if TSC calibration fails */ 1229 if (this_tsc_khz == 0) 1230 return; 1231 1232 /* Compute a scale to convert nanoseconds in TSC cycles */ 1233 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, 1234 &vcpu->arch.virtual_tsc_shift, 1235 &vcpu->arch.virtual_tsc_mult); 1236 vcpu->arch.virtual_tsc_khz = this_tsc_khz; 1237 1238 /* 1239 * Compute the variation in TSC rate which is acceptable 1240 * within the range of tolerance and decide if the 1241 * rate being applied is within that bounds of the hardware 1242 * rate. If so, no scaling or compensation need be done. 1243 */ 1244 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1245 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1246 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { 1247 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); 1248 use_scaling = 1; 1249 } 1250 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling); 1251 } 1252 1253 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1254 { 1255 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1256 vcpu->arch.virtual_tsc_mult, 1257 vcpu->arch.virtual_tsc_shift); 1258 tsc += vcpu->arch.this_tsc_write; 1259 return tsc; 1260 } 1261 1262 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1263 { 1264 #ifdef CONFIG_X86_64 1265 bool vcpus_matched; 1266 struct kvm_arch *ka = &vcpu->kvm->arch; 1267 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1268 1269 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1270 atomic_read(&vcpu->kvm->online_vcpus)); 1271 1272 /* 1273 * Once the masterclock is enabled, always perform request in 1274 * order to update it. 1275 * 1276 * In order to enable masterclock, the host clocksource must be TSC 1277 * and the vcpus need to have matched TSCs. When that happens, 1278 * perform request to enable masterclock. 1279 */ 1280 if (ka->use_master_clock || 1281 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) 1282 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1283 1284 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1285 atomic_read(&vcpu->kvm->online_vcpus), 1286 ka->use_master_clock, gtod->clock.vclock_mode); 1287 #endif 1288 } 1289 1290 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1291 { 1292 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); 1293 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1294 } 1295 1296 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1297 { 1298 struct kvm *kvm = vcpu->kvm; 1299 u64 offset, ns, elapsed; 1300 unsigned long flags; 1301 s64 usdiff; 1302 bool matched; 1303 bool already_matched; 1304 u64 data = msr->data; 1305 1306 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1307 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); 1308 ns = get_kernel_ns(); 1309 elapsed = ns - kvm->arch.last_tsc_nsec; 1310 1311 if (vcpu->arch.virtual_tsc_khz) { 1312 int faulted = 0; 1313 1314 /* n.b - signed multiplication and division required */ 1315 usdiff = data - kvm->arch.last_tsc_write; 1316 #ifdef CONFIG_X86_64 1317 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; 1318 #else 1319 /* do_div() only does unsigned */ 1320 asm("1: idivl %[divisor]\n" 1321 "2: xor %%edx, %%edx\n" 1322 " movl $0, %[faulted]\n" 1323 "3:\n" 1324 ".section .fixup,\"ax\"\n" 1325 "4: movl $1, %[faulted]\n" 1326 " jmp 3b\n" 1327 ".previous\n" 1328 1329 _ASM_EXTABLE(1b, 4b) 1330 1331 : "=A"(usdiff), [faulted] "=r" (faulted) 1332 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); 1333 1334 #endif 1335 do_div(elapsed, 1000); 1336 usdiff -= elapsed; 1337 if (usdiff < 0) 1338 usdiff = -usdiff; 1339 1340 /* idivl overflow => difference is larger than USEC_PER_SEC */ 1341 if (faulted) 1342 usdiff = USEC_PER_SEC; 1343 } else 1344 usdiff = USEC_PER_SEC; /* disable TSC match window below */ 1345 1346 /* 1347 * Special case: TSC write with a small delta (1 second) of virtual 1348 * cycle time against real time is interpreted as an attempt to 1349 * synchronize the CPU. 1350 * 1351 * For a reliable TSC, we can match TSC offsets, and for an unstable 1352 * TSC, we add elapsed time in this computation. We could let the 1353 * compensation code attempt to catch up if we fall behind, but 1354 * it's better to try to match offsets from the beginning. 1355 */ 1356 if (usdiff < USEC_PER_SEC && 1357 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1358 if (!check_tsc_unstable()) { 1359 offset = kvm->arch.cur_tsc_offset; 1360 pr_debug("kvm: matched tsc offset for %llu\n", data); 1361 } else { 1362 u64 delta = nsec_to_cycles(vcpu, elapsed); 1363 data += delta; 1364 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); 1365 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1366 } 1367 matched = true; 1368 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1369 } else { 1370 /* 1371 * We split periods of matched TSC writes into generations. 1372 * For each generation, we track the original measured 1373 * nanosecond time, offset, and write, so if TSCs are in 1374 * sync, we can match exact offset, and if not, we can match 1375 * exact software computation in compute_guest_tsc() 1376 * 1377 * These values are tracked in kvm->arch.cur_xxx variables. 1378 */ 1379 kvm->arch.cur_tsc_generation++; 1380 kvm->arch.cur_tsc_nsec = ns; 1381 kvm->arch.cur_tsc_write = data; 1382 kvm->arch.cur_tsc_offset = offset; 1383 matched = false; 1384 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1385 kvm->arch.cur_tsc_generation, data); 1386 } 1387 1388 /* 1389 * We also track th most recent recorded KHZ, write and time to 1390 * allow the matching interval to be extended at each write. 1391 */ 1392 kvm->arch.last_tsc_nsec = ns; 1393 kvm->arch.last_tsc_write = data; 1394 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1395 1396 vcpu->arch.last_guest_tsc = data; 1397 1398 /* Keep track of which generation this VCPU has synchronized to */ 1399 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1400 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1401 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1402 1403 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) 1404 update_ia32_tsc_adjust_msr(vcpu, offset); 1405 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1406 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1407 1408 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1409 if (!matched) { 1410 kvm->arch.nr_vcpus_matched_tsc = 0; 1411 } else if (!already_matched) { 1412 kvm->arch.nr_vcpus_matched_tsc++; 1413 } 1414 1415 kvm_track_tsc_matching(vcpu); 1416 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1417 } 1418 1419 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1420 1421 #ifdef CONFIG_X86_64 1422 1423 static cycle_t read_tsc(void) 1424 { 1425 cycle_t ret; 1426 u64 last; 1427 1428 /* 1429 * Empirically, a fence (of type that depends on the CPU) 1430 * before rdtsc is enough to ensure that rdtsc is ordered 1431 * with respect to loads. The various CPU manuals are unclear 1432 * as to whether rdtsc can be reordered with later loads, 1433 * but no one has ever seen it happen. 1434 */ 1435 rdtsc_barrier(); 1436 ret = (cycle_t)vget_cycles(); 1437 1438 last = pvclock_gtod_data.clock.cycle_last; 1439 1440 if (likely(ret >= last)) 1441 return ret; 1442 1443 /* 1444 * GCC likes to generate cmov here, but this branch is extremely 1445 * predictable (it's just a funciton of time and the likely is 1446 * very likely) and there's a data dependence, so force GCC 1447 * to generate a branch instead. I don't barrier() because 1448 * we don't actually need a barrier, and if this function 1449 * ever gets inlined it will generate worse code. 1450 */ 1451 asm volatile (""); 1452 return last; 1453 } 1454 1455 static inline u64 vgettsc(cycle_t *cycle_now) 1456 { 1457 long v; 1458 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1459 1460 *cycle_now = read_tsc(); 1461 1462 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; 1463 return v * gtod->clock.mult; 1464 } 1465 1466 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now) 1467 { 1468 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1469 unsigned long seq; 1470 int mode; 1471 u64 ns; 1472 1473 do { 1474 seq = read_seqcount_begin(>od->seq); 1475 mode = gtod->clock.vclock_mode; 1476 ns = gtod->nsec_base; 1477 ns += vgettsc(cycle_now); 1478 ns >>= gtod->clock.shift; 1479 ns += gtod->boot_ns; 1480 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1481 *t = ns; 1482 1483 return mode; 1484 } 1485 1486 /* returns true if host is using tsc clocksource */ 1487 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) 1488 { 1489 /* checked again under seqlock below */ 1490 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) 1491 return false; 1492 1493 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; 1494 } 1495 #endif 1496 1497 /* 1498 * 1499 * Assuming a stable TSC across physical CPUS, and a stable TSC 1500 * across virtual CPUs, the following condition is possible. 1501 * Each numbered line represents an event visible to both 1502 * CPUs at the next numbered event. 1503 * 1504 * "timespecX" represents host monotonic time. "tscX" represents 1505 * RDTSC value. 1506 * 1507 * VCPU0 on CPU0 | VCPU1 on CPU1 1508 * 1509 * 1. read timespec0,tsc0 1510 * 2. | timespec1 = timespec0 + N 1511 * | tsc1 = tsc0 + M 1512 * 3. transition to guest | transition to guest 1513 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1514 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1515 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1516 * 1517 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1518 * 1519 * - ret0 < ret1 1520 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1521 * ... 1522 * - 0 < N - M => M < N 1523 * 1524 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1525 * always the case (the difference between two distinct xtime instances 1526 * might be smaller then the difference between corresponding TSC reads, 1527 * when updating guest vcpus pvclock areas). 1528 * 1529 * To avoid that problem, do not allow visibility of distinct 1530 * system_timestamp/tsc_timestamp values simultaneously: use a master 1531 * copy of host monotonic time values. Update that master copy 1532 * in lockstep. 1533 * 1534 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1535 * 1536 */ 1537 1538 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1539 { 1540 #ifdef CONFIG_X86_64 1541 struct kvm_arch *ka = &kvm->arch; 1542 int vclock_mode; 1543 bool host_tsc_clocksource, vcpus_matched; 1544 1545 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1546 atomic_read(&kvm->online_vcpus)); 1547 1548 /* 1549 * If the host uses TSC clock, then passthrough TSC as stable 1550 * to the guest. 1551 */ 1552 host_tsc_clocksource = kvm_get_time_and_clockread( 1553 &ka->master_kernel_ns, 1554 &ka->master_cycle_now); 1555 1556 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 1557 && !backwards_tsc_observed 1558 && !ka->boot_vcpu_runs_old_kvmclock; 1559 1560 if (ka->use_master_clock) 1561 atomic_set(&kvm_guest_has_master_clock, 1); 1562 1563 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1564 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1565 vcpus_matched); 1566 #endif 1567 } 1568 1569 static void kvm_gen_update_masterclock(struct kvm *kvm) 1570 { 1571 #ifdef CONFIG_X86_64 1572 int i; 1573 struct kvm_vcpu *vcpu; 1574 struct kvm_arch *ka = &kvm->arch; 1575 1576 spin_lock(&ka->pvclock_gtod_sync_lock); 1577 kvm_make_mclock_inprogress_request(kvm); 1578 /* no guest entries from this point */ 1579 pvclock_update_vm_gtod_copy(kvm); 1580 1581 kvm_for_each_vcpu(i, vcpu, kvm) 1582 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1583 1584 /* guest entries allowed */ 1585 kvm_for_each_vcpu(i, vcpu, kvm) 1586 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); 1587 1588 spin_unlock(&ka->pvclock_gtod_sync_lock); 1589 #endif 1590 } 1591 1592 static int kvm_guest_time_update(struct kvm_vcpu *v) 1593 { 1594 unsigned long flags, this_tsc_khz; 1595 struct kvm_vcpu_arch *vcpu = &v->arch; 1596 struct kvm_arch *ka = &v->kvm->arch; 1597 s64 kernel_ns; 1598 u64 tsc_timestamp, host_tsc; 1599 struct pvclock_vcpu_time_info guest_hv_clock; 1600 u8 pvclock_flags; 1601 bool use_master_clock; 1602 1603 kernel_ns = 0; 1604 host_tsc = 0; 1605 1606 /* 1607 * If the host uses TSC clock, then passthrough TSC as stable 1608 * to the guest. 1609 */ 1610 spin_lock(&ka->pvclock_gtod_sync_lock); 1611 use_master_clock = ka->use_master_clock; 1612 if (use_master_clock) { 1613 host_tsc = ka->master_cycle_now; 1614 kernel_ns = ka->master_kernel_ns; 1615 } 1616 spin_unlock(&ka->pvclock_gtod_sync_lock); 1617 1618 /* Keep irq disabled to prevent changes to the clock */ 1619 local_irq_save(flags); 1620 this_tsc_khz = __this_cpu_read(cpu_tsc_khz); 1621 if (unlikely(this_tsc_khz == 0)) { 1622 local_irq_restore(flags); 1623 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1624 return 1; 1625 } 1626 if (!use_master_clock) { 1627 host_tsc = native_read_tsc(); 1628 kernel_ns = get_kernel_ns(); 1629 } 1630 1631 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc); 1632 1633 /* 1634 * We may have to catch up the TSC to match elapsed wall clock 1635 * time for two reasons, even if kvmclock is used. 1636 * 1) CPU could have been running below the maximum TSC rate 1637 * 2) Broken TSC compensation resets the base at each VCPU 1638 * entry to avoid unknown leaps of TSC even when running 1639 * again on the same CPU. This may cause apparent elapsed 1640 * time to disappear, and the guest to stand still or run 1641 * very slowly. 1642 */ 1643 if (vcpu->tsc_catchup) { 1644 u64 tsc = compute_guest_tsc(v, kernel_ns); 1645 if (tsc > tsc_timestamp) { 1646 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 1647 tsc_timestamp = tsc; 1648 } 1649 } 1650 1651 local_irq_restore(flags); 1652 1653 if (!vcpu->pv_time_enabled) 1654 return 0; 1655 1656 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { 1657 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz, 1658 &vcpu->hv_clock.tsc_shift, 1659 &vcpu->hv_clock.tsc_to_system_mul); 1660 vcpu->hw_tsc_khz = this_tsc_khz; 1661 } 1662 1663 /* With all the info we got, fill in the values */ 1664 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 1665 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 1666 vcpu->last_guest_tsc = tsc_timestamp; 1667 1668 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1669 &guest_hv_clock, sizeof(guest_hv_clock)))) 1670 return 0; 1671 1672 /* This VCPU is paused, but it's legal for a guest to read another 1673 * VCPU's kvmclock, so we really have to follow the specification where 1674 * it says that version is odd if data is being modified, and even after 1675 * it is consistent. 1676 * 1677 * Version field updates must be kept separate. This is because 1678 * kvm_write_guest_cached might use a "rep movs" instruction, and 1679 * writes within a string instruction are weakly ordered. So there 1680 * are three writes overall. 1681 * 1682 * As a small optimization, only write the version field in the first 1683 * and third write. The vcpu->pv_time cache is still valid, because the 1684 * version field is the first in the struct. 1685 */ 1686 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 1687 1688 vcpu->hv_clock.version = guest_hv_clock.version + 1; 1689 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1690 &vcpu->hv_clock, 1691 sizeof(vcpu->hv_clock.version)); 1692 1693 smp_wmb(); 1694 1695 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1696 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1697 1698 if (vcpu->pvclock_set_guest_stopped_request) { 1699 pvclock_flags |= PVCLOCK_GUEST_STOPPED; 1700 vcpu->pvclock_set_guest_stopped_request = false; 1701 } 1702 1703 /* If the host uses TSC clocksource, then it is stable */ 1704 if (use_master_clock) 1705 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 1706 1707 vcpu->hv_clock.flags = pvclock_flags; 1708 1709 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 1710 1711 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1712 &vcpu->hv_clock, 1713 sizeof(vcpu->hv_clock)); 1714 1715 smp_wmb(); 1716 1717 vcpu->hv_clock.version++; 1718 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1719 &vcpu->hv_clock, 1720 sizeof(vcpu->hv_clock.version)); 1721 return 0; 1722 } 1723 1724 /* 1725 * kvmclock updates which are isolated to a given vcpu, such as 1726 * vcpu->cpu migration, should not allow system_timestamp from 1727 * the rest of the vcpus to remain static. Otherwise ntp frequency 1728 * correction applies to one vcpu's system_timestamp but not 1729 * the others. 1730 * 1731 * So in those cases, request a kvmclock update for all vcpus. 1732 * We need to rate-limit these requests though, as they can 1733 * considerably slow guests that have a large number of vcpus. 1734 * The time for a remote vcpu to update its kvmclock is bound 1735 * by the delay we use to rate-limit the updates. 1736 */ 1737 1738 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 1739 1740 static void kvmclock_update_fn(struct work_struct *work) 1741 { 1742 int i; 1743 struct delayed_work *dwork = to_delayed_work(work); 1744 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1745 kvmclock_update_work); 1746 struct kvm *kvm = container_of(ka, struct kvm, arch); 1747 struct kvm_vcpu *vcpu; 1748 1749 kvm_for_each_vcpu(i, vcpu, kvm) { 1750 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1751 kvm_vcpu_kick(vcpu); 1752 } 1753 } 1754 1755 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 1756 { 1757 struct kvm *kvm = v->kvm; 1758 1759 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1760 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 1761 KVMCLOCK_UPDATE_DELAY); 1762 } 1763 1764 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 1765 1766 static void kvmclock_sync_fn(struct work_struct *work) 1767 { 1768 struct delayed_work *dwork = to_delayed_work(work); 1769 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1770 kvmclock_sync_work); 1771 struct kvm *kvm = container_of(ka, struct kvm, arch); 1772 1773 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 1774 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 1775 KVMCLOCK_SYNC_PERIOD); 1776 } 1777 1778 static bool msr_mtrr_valid(unsigned msr) 1779 { 1780 switch (msr) { 1781 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: 1782 case MSR_MTRRfix64K_00000: 1783 case MSR_MTRRfix16K_80000: 1784 case MSR_MTRRfix16K_A0000: 1785 case MSR_MTRRfix4K_C0000: 1786 case MSR_MTRRfix4K_C8000: 1787 case MSR_MTRRfix4K_D0000: 1788 case MSR_MTRRfix4K_D8000: 1789 case MSR_MTRRfix4K_E0000: 1790 case MSR_MTRRfix4K_E8000: 1791 case MSR_MTRRfix4K_F0000: 1792 case MSR_MTRRfix4K_F8000: 1793 case MSR_MTRRdefType: 1794 case MSR_IA32_CR_PAT: 1795 return true; 1796 case 0x2f8: 1797 return true; 1798 } 1799 return false; 1800 } 1801 1802 static bool valid_pat_type(unsigned t) 1803 { 1804 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ 1805 } 1806 1807 static bool valid_mtrr_type(unsigned t) 1808 { 1809 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ 1810 } 1811 1812 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1813 { 1814 int i; 1815 u64 mask; 1816 1817 if (!msr_mtrr_valid(msr)) 1818 return false; 1819 1820 if (msr == MSR_IA32_CR_PAT) { 1821 for (i = 0; i < 8; i++) 1822 if (!valid_pat_type((data >> (i * 8)) & 0xff)) 1823 return false; 1824 return true; 1825 } else if (msr == MSR_MTRRdefType) { 1826 if (data & ~0xcff) 1827 return false; 1828 return valid_mtrr_type(data & 0xff); 1829 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { 1830 for (i = 0; i < 8 ; i++) 1831 if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) 1832 return false; 1833 return true; 1834 } 1835 1836 /* variable MTRRs */ 1837 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR)); 1838 1839 mask = (~0ULL) << cpuid_maxphyaddr(vcpu); 1840 if ((msr & 1) == 0) { 1841 /* MTRR base */ 1842 if (!valid_mtrr_type(data & 0xff)) 1843 return false; 1844 mask |= 0xf00; 1845 } else 1846 /* MTRR mask */ 1847 mask |= 0x7ff; 1848 if (data & mask) { 1849 kvm_inject_gp(vcpu, 0); 1850 return false; 1851 } 1852 1853 return true; 1854 } 1855 EXPORT_SYMBOL_GPL(kvm_mtrr_valid); 1856 1857 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1858 { 1859 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; 1860 1861 if (!kvm_mtrr_valid(vcpu, msr, data)) 1862 return 1; 1863 1864 if (msr == MSR_MTRRdefType) { 1865 vcpu->arch.mtrr_state.def_type = data; 1866 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; 1867 } else if (msr == MSR_MTRRfix64K_00000) 1868 p[0] = data; 1869 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) 1870 p[1 + msr - MSR_MTRRfix16K_80000] = data; 1871 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) 1872 p[3 + msr - MSR_MTRRfix4K_C0000] = data; 1873 else if (msr == MSR_IA32_CR_PAT) 1874 vcpu->arch.pat = data; 1875 else { /* Variable MTRRs */ 1876 int idx, is_mtrr_mask; 1877 u64 *pt; 1878 1879 idx = (msr - 0x200) / 2; 1880 is_mtrr_mask = msr - 0x200 - 2 * idx; 1881 if (!is_mtrr_mask) 1882 pt = 1883 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; 1884 else 1885 pt = 1886 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; 1887 *pt = data; 1888 } 1889 1890 kvm_mmu_reset_context(vcpu); 1891 return 0; 1892 } 1893 1894 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1895 { 1896 u64 mcg_cap = vcpu->arch.mcg_cap; 1897 unsigned bank_num = mcg_cap & 0xff; 1898 1899 switch (msr) { 1900 case MSR_IA32_MCG_STATUS: 1901 vcpu->arch.mcg_status = data; 1902 break; 1903 case MSR_IA32_MCG_CTL: 1904 if (!(mcg_cap & MCG_CTL_P)) 1905 return 1; 1906 if (data != 0 && data != ~(u64)0) 1907 return -1; 1908 vcpu->arch.mcg_ctl = data; 1909 break; 1910 default: 1911 if (msr >= MSR_IA32_MC0_CTL && 1912 msr < MSR_IA32_MCx_CTL(bank_num)) { 1913 u32 offset = msr - MSR_IA32_MC0_CTL; 1914 /* only 0 or all 1s can be written to IA32_MCi_CTL 1915 * some Linux kernels though clear bit 10 in bank 4 to 1916 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 1917 * this to avoid an uncatched #GP in the guest 1918 */ 1919 if ((offset & 0x3) == 0 && 1920 data != 0 && (data | (1 << 10)) != ~(u64)0) 1921 return -1; 1922 vcpu->arch.mce_banks[offset] = data; 1923 break; 1924 } 1925 return 1; 1926 } 1927 return 0; 1928 } 1929 1930 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 1931 { 1932 struct kvm *kvm = vcpu->kvm; 1933 int lm = is_long_mode(vcpu); 1934 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 1935 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 1936 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 1937 : kvm->arch.xen_hvm_config.blob_size_32; 1938 u32 page_num = data & ~PAGE_MASK; 1939 u64 page_addr = data & PAGE_MASK; 1940 u8 *page; 1941 int r; 1942 1943 r = -E2BIG; 1944 if (page_num >= blob_size) 1945 goto out; 1946 r = -ENOMEM; 1947 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 1948 if (IS_ERR(page)) { 1949 r = PTR_ERR(page); 1950 goto out; 1951 } 1952 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) 1953 goto out_free; 1954 r = 0; 1955 out_free: 1956 kfree(page); 1957 out: 1958 return r; 1959 } 1960 1961 static bool kvm_hv_hypercall_enabled(struct kvm *kvm) 1962 { 1963 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; 1964 } 1965 1966 static bool kvm_hv_msr_partition_wide(u32 msr) 1967 { 1968 bool r = false; 1969 switch (msr) { 1970 case HV_X64_MSR_GUEST_OS_ID: 1971 case HV_X64_MSR_HYPERCALL: 1972 case HV_X64_MSR_REFERENCE_TSC: 1973 case HV_X64_MSR_TIME_REF_COUNT: 1974 r = true; 1975 break; 1976 } 1977 1978 return r; 1979 } 1980 1981 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1982 { 1983 struct kvm *kvm = vcpu->kvm; 1984 1985 switch (msr) { 1986 case HV_X64_MSR_GUEST_OS_ID: 1987 kvm->arch.hv_guest_os_id = data; 1988 /* setting guest os id to zero disables hypercall page */ 1989 if (!kvm->arch.hv_guest_os_id) 1990 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; 1991 break; 1992 case HV_X64_MSR_HYPERCALL: { 1993 u64 gfn; 1994 unsigned long addr; 1995 u8 instructions[4]; 1996 1997 /* if guest os id is not set hypercall should remain disabled */ 1998 if (!kvm->arch.hv_guest_os_id) 1999 break; 2000 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { 2001 kvm->arch.hv_hypercall = data; 2002 break; 2003 } 2004 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; 2005 addr = gfn_to_hva(kvm, gfn); 2006 if (kvm_is_error_hva(addr)) 2007 return 1; 2008 kvm_x86_ops->patch_hypercall(vcpu, instructions); 2009 ((unsigned char *)instructions)[3] = 0xc3; /* ret */ 2010 if (__copy_to_user((void __user *)addr, instructions, 4)) 2011 return 1; 2012 kvm->arch.hv_hypercall = data; 2013 mark_page_dirty(kvm, gfn); 2014 break; 2015 } 2016 case HV_X64_MSR_REFERENCE_TSC: { 2017 u64 gfn; 2018 HV_REFERENCE_TSC_PAGE tsc_ref; 2019 memset(&tsc_ref, 0, sizeof(tsc_ref)); 2020 kvm->arch.hv_tsc_page = data; 2021 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE)) 2022 break; 2023 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT; 2024 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT, 2025 &tsc_ref, sizeof(tsc_ref))) 2026 return 1; 2027 mark_page_dirty(kvm, gfn); 2028 break; 2029 } 2030 default: 2031 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " 2032 "data 0x%llx\n", msr, data); 2033 return 1; 2034 } 2035 return 0; 2036 } 2037 2038 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) 2039 { 2040 switch (msr) { 2041 case HV_X64_MSR_APIC_ASSIST_PAGE: { 2042 u64 gfn; 2043 unsigned long addr; 2044 2045 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { 2046 vcpu->arch.hv_vapic = data; 2047 if (kvm_lapic_enable_pv_eoi(vcpu, 0)) 2048 return 1; 2049 break; 2050 } 2051 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT; 2052 addr = gfn_to_hva(vcpu->kvm, gfn); 2053 if (kvm_is_error_hva(addr)) 2054 return 1; 2055 if (__clear_user((void __user *)addr, PAGE_SIZE)) 2056 return 1; 2057 vcpu->arch.hv_vapic = data; 2058 mark_page_dirty(vcpu->kvm, gfn); 2059 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED)) 2060 return 1; 2061 break; 2062 } 2063 case HV_X64_MSR_EOI: 2064 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); 2065 case HV_X64_MSR_ICR: 2066 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); 2067 case HV_X64_MSR_TPR: 2068 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); 2069 default: 2070 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " 2071 "data 0x%llx\n", msr, data); 2072 return 1; 2073 } 2074 2075 return 0; 2076 } 2077 2078 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2079 { 2080 gpa_t gpa = data & ~0x3f; 2081 2082 /* Bits 2:5 are reserved, Should be zero */ 2083 if (data & 0x3c) 2084 return 1; 2085 2086 vcpu->arch.apf.msr_val = data; 2087 2088 if (!(data & KVM_ASYNC_PF_ENABLED)) { 2089 kvm_clear_async_pf_completion_queue(vcpu); 2090 kvm_async_pf_hash_reset(vcpu); 2091 return 0; 2092 } 2093 2094 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2095 sizeof(u32))) 2096 return 1; 2097 2098 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2099 kvm_async_pf_wakeup_all(vcpu); 2100 return 0; 2101 } 2102 2103 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2104 { 2105 vcpu->arch.pv_time_enabled = false; 2106 } 2107 2108 static void accumulate_steal_time(struct kvm_vcpu *vcpu) 2109 { 2110 u64 delta; 2111 2112 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2113 return; 2114 2115 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; 2116 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2117 vcpu->arch.st.accum_steal = delta; 2118 } 2119 2120 static void record_steal_time(struct kvm_vcpu *vcpu) 2121 { 2122 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2123 return; 2124 2125 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2126 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2127 return; 2128 2129 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; 2130 vcpu->arch.st.steal.version += 2; 2131 vcpu->arch.st.accum_steal = 0; 2132 2133 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2134 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2135 } 2136 2137 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2138 { 2139 bool pr = false; 2140 u32 msr = msr_info->index; 2141 u64 data = msr_info->data; 2142 2143 switch (msr) { 2144 case MSR_AMD64_NB_CFG: 2145 case MSR_IA32_UCODE_REV: 2146 case MSR_IA32_UCODE_WRITE: 2147 case MSR_VM_HSAVE_PA: 2148 case MSR_AMD64_PATCH_LOADER: 2149 case MSR_AMD64_BU_CFG2: 2150 break; 2151 2152 case MSR_EFER: 2153 return set_efer(vcpu, data); 2154 case MSR_K7_HWCR: 2155 data &= ~(u64)0x40; /* ignore flush filter disable */ 2156 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2157 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2158 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2159 if (data != 0) { 2160 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2161 data); 2162 return 1; 2163 } 2164 break; 2165 case MSR_FAM10H_MMIO_CONF_BASE: 2166 if (data != 0) { 2167 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2168 "0x%llx\n", data); 2169 return 1; 2170 } 2171 break; 2172 case MSR_IA32_DEBUGCTLMSR: 2173 if (!data) { 2174 /* We support the non-activated case already */ 2175 break; 2176 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2177 /* Values other than LBR and BTF are vendor-specific, 2178 thus reserved and should throw a #GP */ 2179 return 1; 2180 } 2181 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2182 __func__, data); 2183 break; 2184 case 0x200 ... 0x2ff: 2185 return set_msr_mtrr(vcpu, msr, data); 2186 case MSR_IA32_APICBASE: 2187 return kvm_set_apic_base(vcpu, msr_info); 2188 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2189 return kvm_x2apic_msr_write(vcpu, msr, data); 2190 case MSR_IA32_TSCDEADLINE: 2191 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2192 break; 2193 case MSR_IA32_TSC_ADJUST: 2194 if (guest_cpuid_has_tsc_adjust(vcpu)) { 2195 if (!msr_info->host_initiated) { 2196 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2197 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true); 2198 } 2199 vcpu->arch.ia32_tsc_adjust_msr = data; 2200 } 2201 break; 2202 case MSR_IA32_MISC_ENABLE: 2203 vcpu->arch.ia32_misc_enable_msr = data; 2204 break; 2205 case MSR_KVM_WALL_CLOCK_NEW: 2206 case MSR_KVM_WALL_CLOCK: 2207 vcpu->kvm->arch.wall_clock = data; 2208 kvm_write_wall_clock(vcpu->kvm, data); 2209 break; 2210 case MSR_KVM_SYSTEM_TIME_NEW: 2211 case MSR_KVM_SYSTEM_TIME: { 2212 u64 gpa_offset; 2213 struct kvm_arch *ka = &vcpu->kvm->arch; 2214 2215 kvmclock_reset(vcpu); 2216 2217 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2218 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2219 2220 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2221 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, 2222 &vcpu->requests); 2223 2224 ka->boot_vcpu_runs_old_kvmclock = tmp; 2225 } 2226 2227 vcpu->arch.time = data; 2228 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2229 2230 /* we verify if the enable bit is set... */ 2231 if (!(data & 1)) 2232 break; 2233 2234 gpa_offset = data & ~(PAGE_MASK | 1); 2235 2236 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2237 &vcpu->arch.pv_time, data & ~1ULL, 2238 sizeof(struct pvclock_vcpu_time_info))) 2239 vcpu->arch.pv_time_enabled = false; 2240 else 2241 vcpu->arch.pv_time_enabled = true; 2242 2243 break; 2244 } 2245 case MSR_KVM_ASYNC_PF_EN: 2246 if (kvm_pv_enable_async_pf(vcpu, data)) 2247 return 1; 2248 break; 2249 case MSR_KVM_STEAL_TIME: 2250 2251 if (unlikely(!sched_info_on())) 2252 return 1; 2253 2254 if (data & KVM_STEAL_RESERVED_MASK) 2255 return 1; 2256 2257 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2258 data & KVM_STEAL_VALID_BITS, 2259 sizeof(struct kvm_steal_time))) 2260 return 1; 2261 2262 vcpu->arch.st.msr_val = data; 2263 2264 if (!(data & KVM_MSR_ENABLED)) 2265 break; 2266 2267 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2268 2269 preempt_disable(); 2270 accumulate_steal_time(vcpu); 2271 preempt_enable(); 2272 2273 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2274 2275 break; 2276 case MSR_KVM_PV_EOI_EN: 2277 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2278 return 1; 2279 break; 2280 2281 case MSR_IA32_MCG_CTL: 2282 case MSR_IA32_MCG_STATUS: 2283 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2284 return set_msr_mce(vcpu, msr, data); 2285 2286 /* Performance counters are not protected by a CPUID bit, 2287 * so we should check all of them in the generic path for the sake of 2288 * cross vendor migration. 2289 * Writing a zero into the event select MSRs disables them, 2290 * which we perfectly emulate ;-). Any other value should be at least 2291 * reported, some guests depend on them. 2292 */ 2293 case MSR_K7_EVNTSEL0: 2294 case MSR_K7_EVNTSEL1: 2295 case MSR_K7_EVNTSEL2: 2296 case MSR_K7_EVNTSEL3: 2297 if (data != 0) 2298 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " 2299 "0x%x data 0x%llx\n", msr, data); 2300 break; 2301 /* at least RHEL 4 unconditionally writes to the perfctr registers, 2302 * so we ignore writes to make it happy. 2303 */ 2304 case MSR_K7_PERFCTR0: 2305 case MSR_K7_PERFCTR1: 2306 case MSR_K7_PERFCTR2: 2307 case MSR_K7_PERFCTR3: 2308 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " 2309 "0x%x data 0x%llx\n", msr, data); 2310 break; 2311 case MSR_P6_PERFCTR0: 2312 case MSR_P6_PERFCTR1: 2313 pr = true; 2314 case MSR_P6_EVNTSEL0: 2315 case MSR_P6_EVNTSEL1: 2316 if (kvm_pmu_msr(vcpu, msr)) 2317 return kvm_pmu_set_msr(vcpu, msr_info); 2318 2319 if (pr || data != 0) 2320 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2321 "0x%x data 0x%llx\n", msr, data); 2322 break; 2323 case MSR_K7_CLK_CTL: 2324 /* 2325 * Ignore all writes to this no longer documented MSR. 2326 * Writes are only relevant for old K7 processors, 2327 * all pre-dating SVM, but a recommended workaround from 2328 * AMD for these chips. It is possible to specify the 2329 * affected processor models on the command line, hence 2330 * the need to ignore the workaround. 2331 */ 2332 break; 2333 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2334 if (kvm_hv_msr_partition_wide(msr)) { 2335 int r; 2336 mutex_lock(&vcpu->kvm->lock); 2337 r = set_msr_hyperv_pw(vcpu, msr, data); 2338 mutex_unlock(&vcpu->kvm->lock); 2339 return r; 2340 } else 2341 return set_msr_hyperv(vcpu, msr, data); 2342 break; 2343 case MSR_IA32_BBL_CR_CTL3: 2344 /* Drop writes to this legacy MSR -- see rdmsr 2345 * counterpart for further detail. 2346 */ 2347 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); 2348 break; 2349 case MSR_AMD64_OSVW_ID_LENGTH: 2350 if (!guest_cpuid_has_osvw(vcpu)) 2351 return 1; 2352 vcpu->arch.osvw.length = data; 2353 break; 2354 case MSR_AMD64_OSVW_STATUS: 2355 if (!guest_cpuid_has_osvw(vcpu)) 2356 return 1; 2357 vcpu->arch.osvw.status = data; 2358 break; 2359 default: 2360 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2361 return xen_hvm_config(vcpu, data); 2362 if (kvm_pmu_msr(vcpu, msr)) 2363 return kvm_pmu_set_msr(vcpu, msr_info); 2364 if (!ignore_msrs) { 2365 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", 2366 msr, data); 2367 return 1; 2368 } else { 2369 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", 2370 msr, data); 2371 break; 2372 } 2373 } 2374 return 0; 2375 } 2376 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2377 2378 2379 /* 2380 * Reads an msr value (of 'msr_index') into 'pdata'. 2381 * Returns 0 on success, non-0 otherwise. 2382 * Assumes vcpu_load() was already called. 2383 */ 2384 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) 2385 { 2386 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); 2387 } 2388 EXPORT_SYMBOL_GPL(kvm_get_msr); 2389 2390 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2391 { 2392 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; 2393 2394 if (!msr_mtrr_valid(msr)) 2395 return 1; 2396 2397 if (msr == MSR_MTRRdefType) 2398 *pdata = vcpu->arch.mtrr_state.def_type + 2399 (vcpu->arch.mtrr_state.enabled << 10); 2400 else if (msr == MSR_MTRRfix64K_00000) 2401 *pdata = p[0]; 2402 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) 2403 *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; 2404 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) 2405 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; 2406 else if (msr == MSR_IA32_CR_PAT) 2407 *pdata = vcpu->arch.pat; 2408 else { /* Variable MTRRs */ 2409 int idx, is_mtrr_mask; 2410 u64 *pt; 2411 2412 idx = (msr - 0x200) / 2; 2413 is_mtrr_mask = msr - 0x200 - 2 * idx; 2414 if (!is_mtrr_mask) 2415 pt = 2416 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; 2417 else 2418 pt = 2419 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; 2420 *pdata = *pt; 2421 } 2422 2423 return 0; 2424 } 2425 2426 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2427 { 2428 u64 data; 2429 u64 mcg_cap = vcpu->arch.mcg_cap; 2430 unsigned bank_num = mcg_cap & 0xff; 2431 2432 switch (msr) { 2433 case MSR_IA32_P5_MC_ADDR: 2434 case MSR_IA32_P5_MC_TYPE: 2435 data = 0; 2436 break; 2437 case MSR_IA32_MCG_CAP: 2438 data = vcpu->arch.mcg_cap; 2439 break; 2440 case MSR_IA32_MCG_CTL: 2441 if (!(mcg_cap & MCG_CTL_P)) 2442 return 1; 2443 data = vcpu->arch.mcg_ctl; 2444 break; 2445 case MSR_IA32_MCG_STATUS: 2446 data = vcpu->arch.mcg_status; 2447 break; 2448 default: 2449 if (msr >= MSR_IA32_MC0_CTL && 2450 msr < MSR_IA32_MCx_CTL(bank_num)) { 2451 u32 offset = msr - MSR_IA32_MC0_CTL; 2452 data = vcpu->arch.mce_banks[offset]; 2453 break; 2454 } 2455 return 1; 2456 } 2457 *pdata = data; 2458 return 0; 2459 } 2460 2461 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2462 { 2463 u64 data = 0; 2464 struct kvm *kvm = vcpu->kvm; 2465 2466 switch (msr) { 2467 case HV_X64_MSR_GUEST_OS_ID: 2468 data = kvm->arch.hv_guest_os_id; 2469 break; 2470 case HV_X64_MSR_HYPERCALL: 2471 data = kvm->arch.hv_hypercall; 2472 break; 2473 case HV_X64_MSR_TIME_REF_COUNT: { 2474 data = 2475 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100); 2476 break; 2477 } 2478 case HV_X64_MSR_REFERENCE_TSC: 2479 data = kvm->arch.hv_tsc_page; 2480 break; 2481 default: 2482 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); 2483 return 1; 2484 } 2485 2486 *pdata = data; 2487 return 0; 2488 } 2489 2490 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2491 { 2492 u64 data = 0; 2493 2494 switch (msr) { 2495 case HV_X64_MSR_VP_INDEX: { 2496 int r; 2497 struct kvm_vcpu *v; 2498 kvm_for_each_vcpu(r, v, vcpu->kvm) { 2499 if (v == vcpu) { 2500 data = r; 2501 break; 2502 } 2503 } 2504 break; 2505 } 2506 case HV_X64_MSR_EOI: 2507 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); 2508 case HV_X64_MSR_ICR: 2509 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); 2510 case HV_X64_MSR_TPR: 2511 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); 2512 case HV_X64_MSR_APIC_ASSIST_PAGE: 2513 data = vcpu->arch.hv_vapic; 2514 break; 2515 default: 2516 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); 2517 return 1; 2518 } 2519 *pdata = data; 2520 return 0; 2521 } 2522 2523 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2524 { 2525 u64 data; 2526 2527 switch (msr) { 2528 case MSR_IA32_PLATFORM_ID: 2529 case MSR_IA32_EBL_CR_POWERON: 2530 case MSR_IA32_DEBUGCTLMSR: 2531 case MSR_IA32_LASTBRANCHFROMIP: 2532 case MSR_IA32_LASTBRANCHTOIP: 2533 case MSR_IA32_LASTINTFROMIP: 2534 case MSR_IA32_LASTINTTOIP: 2535 case MSR_K8_SYSCFG: 2536 case MSR_K7_HWCR: 2537 case MSR_VM_HSAVE_PA: 2538 case MSR_K7_EVNTSEL0: 2539 case MSR_K7_EVNTSEL1: 2540 case MSR_K7_EVNTSEL2: 2541 case MSR_K7_EVNTSEL3: 2542 case MSR_K7_PERFCTR0: 2543 case MSR_K7_PERFCTR1: 2544 case MSR_K7_PERFCTR2: 2545 case MSR_K7_PERFCTR3: 2546 case MSR_K8_INT_PENDING_MSG: 2547 case MSR_AMD64_NB_CFG: 2548 case MSR_FAM10H_MMIO_CONF_BASE: 2549 case MSR_AMD64_BU_CFG2: 2550 data = 0; 2551 break; 2552 case MSR_P6_PERFCTR0: 2553 case MSR_P6_PERFCTR1: 2554 case MSR_P6_EVNTSEL0: 2555 case MSR_P6_EVNTSEL1: 2556 if (kvm_pmu_msr(vcpu, msr)) 2557 return kvm_pmu_get_msr(vcpu, msr, pdata); 2558 data = 0; 2559 break; 2560 case MSR_IA32_UCODE_REV: 2561 data = 0x100000000ULL; 2562 break; 2563 case MSR_MTRRcap: 2564 data = 0x500 | KVM_NR_VAR_MTRR; 2565 break; 2566 case 0x200 ... 0x2ff: 2567 return get_msr_mtrr(vcpu, msr, pdata); 2568 case 0xcd: /* fsb frequency */ 2569 data = 3; 2570 break; 2571 /* 2572 * MSR_EBC_FREQUENCY_ID 2573 * Conservative value valid for even the basic CPU models. 2574 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2575 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2576 * and 266MHz for model 3, or 4. Set Core Clock 2577 * Frequency to System Bus Frequency Ratio to 1 (bits 2578 * 31:24) even though these are only valid for CPU 2579 * models > 2, however guests may end up dividing or 2580 * multiplying by zero otherwise. 2581 */ 2582 case MSR_EBC_FREQUENCY_ID: 2583 data = 1 << 24; 2584 break; 2585 case MSR_IA32_APICBASE: 2586 data = kvm_get_apic_base(vcpu); 2587 break; 2588 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2589 return kvm_x2apic_msr_read(vcpu, msr, pdata); 2590 break; 2591 case MSR_IA32_TSCDEADLINE: 2592 data = kvm_get_lapic_tscdeadline_msr(vcpu); 2593 break; 2594 case MSR_IA32_TSC_ADJUST: 2595 data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2596 break; 2597 case MSR_IA32_MISC_ENABLE: 2598 data = vcpu->arch.ia32_misc_enable_msr; 2599 break; 2600 case MSR_IA32_PERF_STATUS: 2601 /* TSC increment by tick */ 2602 data = 1000ULL; 2603 /* CPU multiplier */ 2604 data |= (((uint64_t)4ULL) << 40); 2605 break; 2606 case MSR_EFER: 2607 data = vcpu->arch.efer; 2608 break; 2609 case MSR_KVM_WALL_CLOCK: 2610 case MSR_KVM_WALL_CLOCK_NEW: 2611 data = vcpu->kvm->arch.wall_clock; 2612 break; 2613 case MSR_KVM_SYSTEM_TIME: 2614 case MSR_KVM_SYSTEM_TIME_NEW: 2615 data = vcpu->arch.time; 2616 break; 2617 case MSR_KVM_ASYNC_PF_EN: 2618 data = vcpu->arch.apf.msr_val; 2619 break; 2620 case MSR_KVM_STEAL_TIME: 2621 data = vcpu->arch.st.msr_val; 2622 break; 2623 case MSR_KVM_PV_EOI_EN: 2624 data = vcpu->arch.pv_eoi.msr_val; 2625 break; 2626 case MSR_IA32_P5_MC_ADDR: 2627 case MSR_IA32_P5_MC_TYPE: 2628 case MSR_IA32_MCG_CAP: 2629 case MSR_IA32_MCG_CTL: 2630 case MSR_IA32_MCG_STATUS: 2631 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2632 return get_msr_mce(vcpu, msr, pdata); 2633 case MSR_K7_CLK_CTL: 2634 /* 2635 * Provide expected ramp-up count for K7. All other 2636 * are set to zero, indicating minimum divisors for 2637 * every field. 2638 * 2639 * This prevents guest kernels on AMD host with CPU 2640 * type 6, model 8 and higher from exploding due to 2641 * the rdmsr failing. 2642 */ 2643 data = 0x20000000; 2644 break; 2645 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2646 if (kvm_hv_msr_partition_wide(msr)) { 2647 int r; 2648 mutex_lock(&vcpu->kvm->lock); 2649 r = get_msr_hyperv_pw(vcpu, msr, pdata); 2650 mutex_unlock(&vcpu->kvm->lock); 2651 return r; 2652 } else 2653 return get_msr_hyperv(vcpu, msr, pdata); 2654 break; 2655 case MSR_IA32_BBL_CR_CTL3: 2656 /* This legacy MSR exists but isn't fully documented in current 2657 * silicon. It is however accessed by winxp in very narrow 2658 * scenarios where it sets bit #19, itself documented as 2659 * a "reserved" bit. Best effort attempt to source coherent 2660 * read data here should the balance of the register be 2661 * interpreted by the guest: 2662 * 2663 * L2 cache control register 3: 64GB range, 256KB size, 2664 * enabled, latency 0x1, configured 2665 */ 2666 data = 0xbe702111; 2667 break; 2668 case MSR_AMD64_OSVW_ID_LENGTH: 2669 if (!guest_cpuid_has_osvw(vcpu)) 2670 return 1; 2671 data = vcpu->arch.osvw.length; 2672 break; 2673 case MSR_AMD64_OSVW_STATUS: 2674 if (!guest_cpuid_has_osvw(vcpu)) 2675 return 1; 2676 data = vcpu->arch.osvw.status; 2677 break; 2678 default: 2679 if (kvm_pmu_msr(vcpu, msr)) 2680 return kvm_pmu_get_msr(vcpu, msr, pdata); 2681 if (!ignore_msrs) { 2682 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); 2683 return 1; 2684 } else { 2685 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); 2686 data = 0; 2687 } 2688 break; 2689 } 2690 *pdata = data; 2691 return 0; 2692 } 2693 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2694 2695 /* 2696 * Read or write a bunch of msrs. All parameters are kernel addresses. 2697 * 2698 * @return number of msrs set successfully. 2699 */ 2700 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2701 struct kvm_msr_entry *entries, 2702 int (*do_msr)(struct kvm_vcpu *vcpu, 2703 unsigned index, u64 *data)) 2704 { 2705 int i, idx; 2706 2707 idx = srcu_read_lock(&vcpu->kvm->srcu); 2708 for (i = 0; i < msrs->nmsrs; ++i) 2709 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2710 break; 2711 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2712 2713 return i; 2714 } 2715 2716 /* 2717 * Read or write a bunch of msrs. Parameters are user addresses. 2718 * 2719 * @return number of msrs set successfully. 2720 */ 2721 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2722 int (*do_msr)(struct kvm_vcpu *vcpu, 2723 unsigned index, u64 *data), 2724 int writeback) 2725 { 2726 struct kvm_msrs msrs; 2727 struct kvm_msr_entry *entries; 2728 int r, n; 2729 unsigned size; 2730 2731 r = -EFAULT; 2732 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2733 goto out; 2734 2735 r = -E2BIG; 2736 if (msrs.nmsrs >= MAX_IO_MSRS) 2737 goto out; 2738 2739 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2740 entries = memdup_user(user_msrs->entries, size); 2741 if (IS_ERR(entries)) { 2742 r = PTR_ERR(entries); 2743 goto out; 2744 } 2745 2746 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2747 if (r < 0) 2748 goto out_free; 2749 2750 r = -EFAULT; 2751 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2752 goto out_free; 2753 2754 r = n; 2755 2756 out_free: 2757 kfree(entries); 2758 out: 2759 return r; 2760 } 2761 2762 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2763 { 2764 int r; 2765 2766 switch (ext) { 2767 case KVM_CAP_IRQCHIP: 2768 case KVM_CAP_HLT: 2769 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2770 case KVM_CAP_SET_TSS_ADDR: 2771 case KVM_CAP_EXT_CPUID: 2772 case KVM_CAP_EXT_EMUL_CPUID: 2773 case KVM_CAP_CLOCKSOURCE: 2774 case KVM_CAP_PIT: 2775 case KVM_CAP_NOP_IO_DELAY: 2776 case KVM_CAP_MP_STATE: 2777 case KVM_CAP_SYNC_MMU: 2778 case KVM_CAP_USER_NMI: 2779 case KVM_CAP_REINJECT_CONTROL: 2780 case KVM_CAP_IRQ_INJECT_STATUS: 2781 case KVM_CAP_IOEVENTFD: 2782 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2783 case KVM_CAP_PIT2: 2784 case KVM_CAP_PIT_STATE2: 2785 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2786 case KVM_CAP_XEN_HVM: 2787 case KVM_CAP_ADJUST_CLOCK: 2788 case KVM_CAP_VCPU_EVENTS: 2789 case KVM_CAP_HYPERV: 2790 case KVM_CAP_HYPERV_VAPIC: 2791 case KVM_CAP_HYPERV_SPIN: 2792 case KVM_CAP_PCI_SEGMENT: 2793 case KVM_CAP_DEBUGREGS: 2794 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2795 case KVM_CAP_XSAVE: 2796 case KVM_CAP_ASYNC_PF: 2797 case KVM_CAP_GET_TSC_KHZ: 2798 case KVM_CAP_KVMCLOCK_CTRL: 2799 case KVM_CAP_READONLY_MEM: 2800 case KVM_CAP_HYPERV_TIME: 2801 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2802 case KVM_CAP_TSC_DEADLINE_TIMER: 2803 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2804 case KVM_CAP_ASSIGN_DEV_IRQ: 2805 case KVM_CAP_PCI_2_3: 2806 #endif 2807 r = 1; 2808 break; 2809 case KVM_CAP_COALESCED_MMIO: 2810 r = KVM_COALESCED_MMIO_PAGE_OFFSET; 2811 break; 2812 case KVM_CAP_VAPIC: 2813 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2814 break; 2815 case KVM_CAP_NR_VCPUS: 2816 r = KVM_SOFT_MAX_VCPUS; 2817 break; 2818 case KVM_CAP_MAX_VCPUS: 2819 r = KVM_MAX_VCPUS; 2820 break; 2821 case KVM_CAP_NR_MEMSLOTS: 2822 r = KVM_USER_MEM_SLOTS; 2823 break; 2824 case KVM_CAP_PV_MMU: /* obsolete */ 2825 r = 0; 2826 break; 2827 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2828 case KVM_CAP_IOMMU: 2829 r = iommu_present(&pci_bus_type); 2830 break; 2831 #endif 2832 case KVM_CAP_MCE: 2833 r = KVM_MAX_MCE_BANKS; 2834 break; 2835 case KVM_CAP_XCRS: 2836 r = cpu_has_xsave; 2837 break; 2838 case KVM_CAP_TSC_CONTROL: 2839 r = kvm_has_tsc_control; 2840 break; 2841 default: 2842 r = 0; 2843 break; 2844 } 2845 return r; 2846 2847 } 2848 2849 long kvm_arch_dev_ioctl(struct file *filp, 2850 unsigned int ioctl, unsigned long arg) 2851 { 2852 void __user *argp = (void __user *)arg; 2853 long r; 2854 2855 switch (ioctl) { 2856 case KVM_GET_MSR_INDEX_LIST: { 2857 struct kvm_msr_list __user *user_msr_list = argp; 2858 struct kvm_msr_list msr_list; 2859 unsigned n; 2860 2861 r = -EFAULT; 2862 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2863 goto out; 2864 n = msr_list.nmsrs; 2865 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); 2866 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2867 goto out; 2868 r = -E2BIG; 2869 if (n < msr_list.nmsrs) 2870 goto out; 2871 r = -EFAULT; 2872 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2873 num_msrs_to_save * sizeof(u32))) 2874 goto out; 2875 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2876 &emulated_msrs, 2877 ARRAY_SIZE(emulated_msrs) * sizeof(u32))) 2878 goto out; 2879 r = 0; 2880 break; 2881 } 2882 case KVM_GET_SUPPORTED_CPUID: 2883 case KVM_GET_EMULATED_CPUID: { 2884 struct kvm_cpuid2 __user *cpuid_arg = argp; 2885 struct kvm_cpuid2 cpuid; 2886 2887 r = -EFAULT; 2888 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2889 goto out; 2890 2891 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2892 ioctl); 2893 if (r) 2894 goto out; 2895 2896 r = -EFAULT; 2897 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2898 goto out; 2899 r = 0; 2900 break; 2901 } 2902 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2903 u64 mce_cap; 2904 2905 mce_cap = KVM_MCE_CAP_SUPPORTED; 2906 r = -EFAULT; 2907 if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) 2908 goto out; 2909 r = 0; 2910 break; 2911 } 2912 default: 2913 r = -EINVAL; 2914 } 2915 out: 2916 return r; 2917 } 2918 2919 static void wbinvd_ipi(void *garbage) 2920 { 2921 wbinvd(); 2922 } 2923 2924 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 2925 { 2926 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 2927 } 2928 2929 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 2930 { 2931 /* Address WBINVD may be executed by guest */ 2932 if (need_emulate_wbinvd(vcpu)) { 2933 if (kvm_x86_ops->has_wbinvd_exit()) 2934 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 2935 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 2936 smp_call_function_single(vcpu->cpu, 2937 wbinvd_ipi, NULL, 1); 2938 } 2939 2940 kvm_x86_ops->vcpu_load(vcpu, cpu); 2941 2942 /* Apply any externally detected TSC adjustments (due to suspend) */ 2943 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 2944 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 2945 vcpu->arch.tsc_offset_adjustment = 0; 2946 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2947 } 2948 2949 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { 2950 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 2951 native_read_tsc() - vcpu->arch.last_host_tsc; 2952 if (tsc_delta < 0) 2953 mark_tsc_unstable("KVM discovered backwards TSC"); 2954 if (check_tsc_unstable()) { 2955 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu, 2956 vcpu->arch.last_guest_tsc); 2957 kvm_x86_ops->write_tsc_offset(vcpu, offset); 2958 vcpu->arch.tsc_catchup = 1; 2959 } 2960 /* 2961 * On a host with synchronized TSC, there is no need to update 2962 * kvmclock on vcpu->cpu migration 2963 */ 2964 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 2965 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2966 if (vcpu->cpu != cpu) 2967 kvm_migrate_timers(vcpu); 2968 vcpu->cpu = cpu; 2969 } 2970 2971 accumulate_steal_time(vcpu); 2972 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2973 } 2974 2975 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 2976 { 2977 kvm_x86_ops->vcpu_put(vcpu); 2978 kvm_put_guest_fpu(vcpu); 2979 vcpu->arch.last_host_tsc = native_read_tsc(); 2980 } 2981 2982 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 2983 struct kvm_lapic_state *s) 2984 { 2985 kvm_x86_ops->sync_pir_to_irr(vcpu); 2986 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); 2987 2988 return 0; 2989 } 2990 2991 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 2992 struct kvm_lapic_state *s) 2993 { 2994 kvm_apic_post_state_restore(vcpu, s); 2995 update_cr8_intercept(vcpu); 2996 2997 return 0; 2998 } 2999 3000 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 3001 struct kvm_interrupt *irq) 3002 { 3003 if (irq->irq >= KVM_NR_INTERRUPTS) 3004 return -EINVAL; 3005 if (irqchip_in_kernel(vcpu->kvm)) 3006 return -ENXIO; 3007 3008 kvm_queue_interrupt(vcpu, irq->irq, false); 3009 kvm_make_request(KVM_REQ_EVENT, vcpu); 3010 3011 return 0; 3012 } 3013 3014 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 3015 { 3016 kvm_inject_nmi(vcpu); 3017 3018 return 0; 3019 } 3020 3021 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 3022 struct kvm_tpr_access_ctl *tac) 3023 { 3024 if (tac->flags) 3025 return -EINVAL; 3026 vcpu->arch.tpr_access_reporting = !!tac->enabled; 3027 return 0; 3028 } 3029 3030 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 3031 u64 mcg_cap) 3032 { 3033 int r; 3034 unsigned bank_num = mcg_cap & 0xff, bank; 3035 3036 r = -EINVAL; 3037 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 3038 goto out; 3039 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) 3040 goto out; 3041 r = 0; 3042 vcpu->arch.mcg_cap = mcg_cap; 3043 /* Init IA32_MCG_CTL to all 1s */ 3044 if (mcg_cap & MCG_CTL_P) 3045 vcpu->arch.mcg_ctl = ~(u64)0; 3046 /* Init IA32_MCi_CTL to all 1s */ 3047 for (bank = 0; bank < bank_num; bank++) 3048 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 3049 out: 3050 return r; 3051 } 3052 3053 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 3054 struct kvm_x86_mce *mce) 3055 { 3056 u64 mcg_cap = vcpu->arch.mcg_cap; 3057 unsigned bank_num = mcg_cap & 0xff; 3058 u64 *banks = vcpu->arch.mce_banks; 3059 3060 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 3061 return -EINVAL; 3062 /* 3063 * if IA32_MCG_CTL is not all 1s, the uncorrected error 3064 * reporting is disabled 3065 */ 3066 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 3067 vcpu->arch.mcg_ctl != ~(u64)0) 3068 return 0; 3069 banks += 4 * mce->bank; 3070 /* 3071 * if IA32_MCi_CTL is not all 1s, the uncorrected error 3072 * reporting is disabled for the bank 3073 */ 3074 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 3075 return 0; 3076 if (mce->status & MCI_STATUS_UC) { 3077 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 3078 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 3079 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 3080 return 0; 3081 } 3082 if (banks[1] & MCI_STATUS_VAL) 3083 mce->status |= MCI_STATUS_OVER; 3084 banks[2] = mce->addr; 3085 banks[3] = mce->misc; 3086 vcpu->arch.mcg_status = mce->mcg_status; 3087 banks[1] = mce->status; 3088 kvm_queue_exception(vcpu, MC_VECTOR); 3089 } else if (!(banks[1] & MCI_STATUS_VAL) 3090 || !(banks[1] & MCI_STATUS_UC)) { 3091 if (banks[1] & MCI_STATUS_VAL) 3092 mce->status |= MCI_STATUS_OVER; 3093 banks[2] = mce->addr; 3094 banks[3] = mce->misc; 3095 banks[1] = mce->status; 3096 } else 3097 banks[1] |= MCI_STATUS_OVER; 3098 return 0; 3099 } 3100 3101 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 3102 struct kvm_vcpu_events *events) 3103 { 3104 process_nmi(vcpu); 3105 events->exception.injected = 3106 vcpu->arch.exception.pending && 3107 !kvm_exception_is_soft(vcpu->arch.exception.nr); 3108 events->exception.nr = vcpu->arch.exception.nr; 3109 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 3110 events->exception.pad = 0; 3111 events->exception.error_code = vcpu->arch.exception.error_code; 3112 3113 events->interrupt.injected = 3114 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; 3115 events->interrupt.nr = vcpu->arch.interrupt.nr; 3116 events->interrupt.soft = 0; 3117 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 3118 3119 events->nmi.injected = vcpu->arch.nmi_injected; 3120 events->nmi.pending = vcpu->arch.nmi_pending != 0; 3121 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 3122 events->nmi.pad = 0; 3123 3124 events->sipi_vector = 0; /* never valid when reporting to user space */ 3125 3126 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 3127 | KVM_VCPUEVENT_VALID_SHADOW); 3128 memset(&events->reserved, 0, sizeof(events->reserved)); 3129 } 3130 3131 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 3132 struct kvm_vcpu_events *events) 3133 { 3134 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 3135 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 3136 | KVM_VCPUEVENT_VALID_SHADOW)) 3137 return -EINVAL; 3138 3139 process_nmi(vcpu); 3140 vcpu->arch.exception.pending = events->exception.injected; 3141 vcpu->arch.exception.nr = events->exception.nr; 3142 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 3143 vcpu->arch.exception.error_code = events->exception.error_code; 3144 3145 vcpu->arch.interrupt.pending = events->interrupt.injected; 3146 vcpu->arch.interrupt.nr = events->interrupt.nr; 3147 vcpu->arch.interrupt.soft = events->interrupt.soft; 3148 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3149 kvm_x86_ops->set_interrupt_shadow(vcpu, 3150 events->interrupt.shadow); 3151 3152 vcpu->arch.nmi_injected = events->nmi.injected; 3153 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3154 vcpu->arch.nmi_pending = events->nmi.pending; 3155 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 3156 3157 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3158 kvm_vcpu_has_lapic(vcpu)) 3159 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3160 3161 kvm_make_request(KVM_REQ_EVENT, vcpu); 3162 3163 return 0; 3164 } 3165 3166 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3167 struct kvm_debugregs *dbgregs) 3168 { 3169 unsigned long val; 3170 3171 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3172 kvm_get_dr(vcpu, 6, &val); 3173 dbgregs->dr6 = val; 3174 dbgregs->dr7 = vcpu->arch.dr7; 3175 dbgregs->flags = 0; 3176 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3177 } 3178 3179 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3180 struct kvm_debugregs *dbgregs) 3181 { 3182 if (dbgregs->flags) 3183 return -EINVAL; 3184 3185 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3186 kvm_update_dr0123(vcpu); 3187 vcpu->arch.dr6 = dbgregs->dr6; 3188 kvm_update_dr6(vcpu); 3189 vcpu->arch.dr7 = dbgregs->dr7; 3190 kvm_update_dr7(vcpu); 3191 3192 return 0; 3193 } 3194 3195 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3196 3197 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3198 { 3199 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave; 3200 u64 xstate_bv = xsave->xsave_hdr.xstate_bv; 3201 u64 valid; 3202 3203 /* 3204 * Copy legacy XSAVE area, to avoid complications with CPUID 3205 * leaves 0 and 1 in the loop below. 3206 */ 3207 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3208 3209 /* Set XSTATE_BV */ 3210 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3211 3212 /* 3213 * Copy each region from the possibly compacted offset to the 3214 * non-compacted offset. 3215 */ 3216 valid = xstate_bv & ~XSTATE_FPSSE; 3217 while (valid) { 3218 u64 feature = valid & -valid; 3219 int index = fls64(feature) - 1; 3220 void *src = get_xsave_addr(xsave, feature); 3221 3222 if (src) { 3223 u32 size, offset, ecx, edx; 3224 cpuid_count(XSTATE_CPUID, index, 3225 &size, &offset, &ecx, &edx); 3226 memcpy(dest + offset, src, size); 3227 } 3228 3229 valid -= feature; 3230 } 3231 } 3232 3233 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3234 { 3235 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave; 3236 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3237 u64 valid; 3238 3239 /* 3240 * Copy legacy XSAVE area, to avoid complications with CPUID 3241 * leaves 0 and 1 in the loop below. 3242 */ 3243 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3244 3245 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3246 xsave->xsave_hdr.xstate_bv = xstate_bv; 3247 if (cpu_has_xsaves) 3248 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3249 3250 /* 3251 * Copy each region from the non-compacted offset to the 3252 * possibly compacted offset. 3253 */ 3254 valid = xstate_bv & ~XSTATE_FPSSE; 3255 while (valid) { 3256 u64 feature = valid & -valid; 3257 int index = fls64(feature) - 1; 3258 void *dest = get_xsave_addr(xsave, feature); 3259 3260 if (dest) { 3261 u32 size, offset, ecx, edx; 3262 cpuid_count(XSTATE_CPUID, index, 3263 &size, &offset, &ecx, &edx); 3264 memcpy(dest, src + offset, size); 3265 } else 3266 WARN_ON_ONCE(1); 3267 3268 valid -= feature; 3269 } 3270 } 3271 3272 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3273 struct kvm_xsave *guest_xsave) 3274 { 3275 if (cpu_has_xsave) { 3276 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3277 fill_xsave((u8 *) guest_xsave->region, vcpu); 3278 } else { 3279 memcpy(guest_xsave->region, 3280 &vcpu->arch.guest_fpu.state->fxsave, 3281 sizeof(struct i387_fxsave_struct)); 3282 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3283 XSTATE_FPSSE; 3284 } 3285 } 3286 3287 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3288 struct kvm_xsave *guest_xsave) 3289 { 3290 u64 xstate_bv = 3291 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3292 3293 if (cpu_has_xsave) { 3294 /* 3295 * Here we allow setting states that are not present in 3296 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3297 * with old userspace. 3298 */ 3299 if (xstate_bv & ~kvm_supported_xcr0()) 3300 return -EINVAL; 3301 load_xsave(vcpu, (u8 *)guest_xsave->region); 3302 } else { 3303 if (xstate_bv & ~XSTATE_FPSSE) 3304 return -EINVAL; 3305 memcpy(&vcpu->arch.guest_fpu.state->fxsave, 3306 guest_xsave->region, sizeof(struct i387_fxsave_struct)); 3307 } 3308 return 0; 3309 } 3310 3311 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3312 struct kvm_xcrs *guest_xcrs) 3313 { 3314 if (!cpu_has_xsave) { 3315 guest_xcrs->nr_xcrs = 0; 3316 return; 3317 } 3318 3319 guest_xcrs->nr_xcrs = 1; 3320 guest_xcrs->flags = 0; 3321 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3322 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3323 } 3324 3325 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3326 struct kvm_xcrs *guest_xcrs) 3327 { 3328 int i, r = 0; 3329 3330 if (!cpu_has_xsave) 3331 return -EINVAL; 3332 3333 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3334 return -EINVAL; 3335 3336 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3337 /* Only support XCR0 currently */ 3338 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3339 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3340 guest_xcrs->xcrs[i].value); 3341 break; 3342 } 3343 if (r) 3344 r = -EINVAL; 3345 return r; 3346 } 3347 3348 /* 3349 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3350 * stopped by the hypervisor. This function will be called from the host only. 3351 * EINVAL is returned when the host attempts to set the flag for a guest that 3352 * does not support pv clocks. 3353 */ 3354 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3355 { 3356 if (!vcpu->arch.pv_time_enabled) 3357 return -EINVAL; 3358 vcpu->arch.pvclock_set_guest_stopped_request = true; 3359 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3360 return 0; 3361 } 3362 3363 long kvm_arch_vcpu_ioctl(struct file *filp, 3364 unsigned int ioctl, unsigned long arg) 3365 { 3366 struct kvm_vcpu *vcpu = filp->private_data; 3367 void __user *argp = (void __user *)arg; 3368 int r; 3369 union { 3370 struct kvm_lapic_state *lapic; 3371 struct kvm_xsave *xsave; 3372 struct kvm_xcrs *xcrs; 3373 void *buffer; 3374 } u; 3375 3376 u.buffer = NULL; 3377 switch (ioctl) { 3378 case KVM_GET_LAPIC: { 3379 r = -EINVAL; 3380 if (!vcpu->arch.apic) 3381 goto out; 3382 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3383 3384 r = -ENOMEM; 3385 if (!u.lapic) 3386 goto out; 3387 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3388 if (r) 3389 goto out; 3390 r = -EFAULT; 3391 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3392 goto out; 3393 r = 0; 3394 break; 3395 } 3396 case KVM_SET_LAPIC: { 3397 r = -EINVAL; 3398 if (!vcpu->arch.apic) 3399 goto out; 3400 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3401 if (IS_ERR(u.lapic)) 3402 return PTR_ERR(u.lapic); 3403 3404 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3405 break; 3406 } 3407 case KVM_INTERRUPT: { 3408 struct kvm_interrupt irq; 3409 3410 r = -EFAULT; 3411 if (copy_from_user(&irq, argp, sizeof irq)) 3412 goto out; 3413 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3414 break; 3415 } 3416 case KVM_NMI: { 3417 r = kvm_vcpu_ioctl_nmi(vcpu); 3418 break; 3419 } 3420 case KVM_SET_CPUID: { 3421 struct kvm_cpuid __user *cpuid_arg = argp; 3422 struct kvm_cpuid cpuid; 3423 3424 r = -EFAULT; 3425 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3426 goto out; 3427 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3428 break; 3429 } 3430 case KVM_SET_CPUID2: { 3431 struct kvm_cpuid2 __user *cpuid_arg = argp; 3432 struct kvm_cpuid2 cpuid; 3433 3434 r = -EFAULT; 3435 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3436 goto out; 3437 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3438 cpuid_arg->entries); 3439 break; 3440 } 3441 case KVM_GET_CPUID2: { 3442 struct kvm_cpuid2 __user *cpuid_arg = argp; 3443 struct kvm_cpuid2 cpuid; 3444 3445 r = -EFAULT; 3446 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3447 goto out; 3448 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3449 cpuid_arg->entries); 3450 if (r) 3451 goto out; 3452 r = -EFAULT; 3453 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3454 goto out; 3455 r = 0; 3456 break; 3457 } 3458 case KVM_GET_MSRS: 3459 r = msr_io(vcpu, argp, kvm_get_msr, 1); 3460 break; 3461 case KVM_SET_MSRS: 3462 r = msr_io(vcpu, argp, do_set_msr, 0); 3463 break; 3464 case KVM_TPR_ACCESS_REPORTING: { 3465 struct kvm_tpr_access_ctl tac; 3466 3467 r = -EFAULT; 3468 if (copy_from_user(&tac, argp, sizeof tac)) 3469 goto out; 3470 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3471 if (r) 3472 goto out; 3473 r = -EFAULT; 3474 if (copy_to_user(argp, &tac, sizeof tac)) 3475 goto out; 3476 r = 0; 3477 break; 3478 }; 3479 case KVM_SET_VAPIC_ADDR: { 3480 struct kvm_vapic_addr va; 3481 3482 r = -EINVAL; 3483 if (!irqchip_in_kernel(vcpu->kvm)) 3484 goto out; 3485 r = -EFAULT; 3486 if (copy_from_user(&va, argp, sizeof va)) 3487 goto out; 3488 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3489 break; 3490 } 3491 case KVM_X86_SETUP_MCE: { 3492 u64 mcg_cap; 3493 3494 r = -EFAULT; 3495 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3496 goto out; 3497 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3498 break; 3499 } 3500 case KVM_X86_SET_MCE: { 3501 struct kvm_x86_mce mce; 3502 3503 r = -EFAULT; 3504 if (copy_from_user(&mce, argp, sizeof mce)) 3505 goto out; 3506 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3507 break; 3508 } 3509 case KVM_GET_VCPU_EVENTS: { 3510 struct kvm_vcpu_events events; 3511 3512 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3513 3514 r = -EFAULT; 3515 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3516 break; 3517 r = 0; 3518 break; 3519 } 3520 case KVM_SET_VCPU_EVENTS: { 3521 struct kvm_vcpu_events events; 3522 3523 r = -EFAULT; 3524 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3525 break; 3526 3527 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3528 break; 3529 } 3530 case KVM_GET_DEBUGREGS: { 3531 struct kvm_debugregs dbgregs; 3532 3533 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3534 3535 r = -EFAULT; 3536 if (copy_to_user(argp, &dbgregs, 3537 sizeof(struct kvm_debugregs))) 3538 break; 3539 r = 0; 3540 break; 3541 } 3542 case KVM_SET_DEBUGREGS: { 3543 struct kvm_debugregs dbgregs; 3544 3545 r = -EFAULT; 3546 if (copy_from_user(&dbgregs, argp, 3547 sizeof(struct kvm_debugregs))) 3548 break; 3549 3550 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3551 break; 3552 } 3553 case KVM_GET_XSAVE: { 3554 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3555 r = -ENOMEM; 3556 if (!u.xsave) 3557 break; 3558 3559 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3560 3561 r = -EFAULT; 3562 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3563 break; 3564 r = 0; 3565 break; 3566 } 3567 case KVM_SET_XSAVE: { 3568 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3569 if (IS_ERR(u.xsave)) 3570 return PTR_ERR(u.xsave); 3571 3572 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3573 break; 3574 } 3575 case KVM_GET_XCRS: { 3576 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3577 r = -ENOMEM; 3578 if (!u.xcrs) 3579 break; 3580 3581 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3582 3583 r = -EFAULT; 3584 if (copy_to_user(argp, u.xcrs, 3585 sizeof(struct kvm_xcrs))) 3586 break; 3587 r = 0; 3588 break; 3589 } 3590 case KVM_SET_XCRS: { 3591 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3592 if (IS_ERR(u.xcrs)) 3593 return PTR_ERR(u.xcrs); 3594 3595 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3596 break; 3597 } 3598 case KVM_SET_TSC_KHZ: { 3599 u32 user_tsc_khz; 3600 3601 r = -EINVAL; 3602 user_tsc_khz = (u32)arg; 3603 3604 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3605 goto out; 3606 3607 if (user_tsc_khz == 0) 3608 user_tsc_khz = tsc_khz; 3609 3610 kvm_set_tsc_khz(vcpu, user_tsc_khz); 3611 3612 r = 0; 3613 goto out; 3614 } 3615 case KVM_GET_TSC_KHZ: { 3616 r = vcpu->arch.virtual_tsc_khz; 3617 goto out; 3618 } 3619 case KVM_KVMCLOCK_CTRL: { 3620 r = kvm_set_guest_paused(vcpu); 3621 goto out; 3622 } 3623 default: 3624 r = -EINVAL; 3625 } 3626 out: 3627 kfree(u.buffer); 3628 return r; 3629 } 3630 3631 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3632 { 3633 return VM_FAULT_SIGBUS; 3634 } 3635 3636 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3637 { 3638 int ret; 3639 3640 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3641 return -EINVAL; 3642 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3643 return ret; 3644 } 3645 3646 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3647 u64 ident_addr) 3648 { 3649 kvm->arch.ept_identity_map_addr = ident_addr; 3650 return 0; 3651 } 3652 3653 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3654 u32 kvm_nr_mmu_pages) 3655 { 3656 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3657 return -EINVAL; 3658 3659 mutex_lock(&kvm->slots_lock); 3660 3661 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3662 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3663 3664 mutex_unlock(&kvm->slots_lock); 3665 return 0; 3666 } 3667 3668 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 3669 { 3670 return kvm->arch.n_max_mmu_pages; 3671 } 3672 3673 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3674 { 3675 int r; 3676 3677 r = 0; 3678 switch (chip->chip_id) { 3679 case KVM_IRQCHIP_PIC_MASTER: 3680 memcpy(&chip->chip.pic, 3681 &pic_irqchip(kvm)->pics[0], 3682 sizeof(struct kvm_pic_state)); 3683 break; 3684 case KVM_IRQCHIP_PIC_SLAVE: 3685 memcpy(&chip->chip.pic, 3686 &pic_irqchip(kvm)->pics[1], 3687 sizeof(struct kvm_pic_state)); 3688 break; 3689 case KVM_IRQCHIP_IOAPIC: 3690 r = kvm_get_ioapic(kvm, &chip->chip.ioapic); 3691 break; 3692 default: 3693 r = -EINVAL; 3694 break; 3695 } 3696 return r; 3697 } 3698 3699 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3700 { 3701 int r; 3702 3703 r = 0; 3704 switch (chip->chip_id) { 3705 case KVM_IRQCHIP_PIC_MASTER: 3706 spin_lock(&pic_irqchip(kvm)->lock); 3707 memcpy(&pic_irqchip(kvm)->pics[0], 3708 &chip->chip.pic, 3709 sizeof(struct kvm_pic_state)); 3710 spin_unlock(&pic_irqchip(kvm)->lock); 3711 break; 3712 case KVM_IRQCHIP_PIC_SLAVE: 3713 spin_lock(&pic_irqchip(kvm)->lock); 3714 memcpy(&pic_irqchip(kvm)->pics[1], 3715 &chip->chip.pic, 3716 sizeof(struct kvm_pic_state)); 3717 spin_unlock(&pic_irqchip(kvm)->lock); 3718 break; 3719 case KVM_IRQCHIP_IOAPIC: 3720 r = kvm_set_ioapic(kvm, &chip->chip.ioapic); 3721 break; 3722 default: 3723 r = -EINVAL; 3724 break; 3725 } 3726 kvm_pic_update_irq(pic_irqchip(kvm)); 3727 return r; 3728 } 3729 3730 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3731 { 3732 int r = 0; 3733 3734 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3735 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); 3736 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3737 return r; 3738 } 3739 3740 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3741 { 3742 int r = 0; 3743 3744 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3745 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); 3746 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); 3747 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3748 return r; 3749 } 3750 3751 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3752 { 3753 int r = 0; 3754 3755 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3756 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 3757 sizeof(ps->channels)); 3758 ps->flags = kvm->arch.vpit->pit_state.flags; 3759 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3760 memset(&ps->reserved, 0, sizeof(ps->reserved)); 3761 return r; 3762 } 3763 3764 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3765 { 3766 int r = 0, start = 0; 3767 u32 prev_legacy, cur_legacy; 3768 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3769 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 3770 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 3771 if (!prev_legacy && cur_legacy) 3772 start = 1; 3773 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, 3774 sizeof(kvm->arch.vpit->pit_state.channels)); 3775 kvm->arch.vpit->pit_state.flags = ps->flags; 3776 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); 3777 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3778 return r; 3779 } 3780 3781 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 3782 struct kvm_reinject_control *control) 3783 { 3784 if (!kvm->arch.vpit) 3785 return -ENXIO; 3786 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3787 kvm->arch.vpit->pit_state.reinject = control->pit_reinject; 3788 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3789 return 0; 3790 } 3791 3792 /** 3793 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 3794 * @kvm: kvm instance 3795 * @log: slot id and address to which we copy the log 3796 * 3797 * Steps 1-4 below provide general overview of dirty page logging. See 3798 * kvm_get_dirty_log_protect() function description for additional details. 3799 * 3800 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 3801 * always flush the TLB (step 4) even if previous step failed and the dirty 3802 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 3803 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 3804 * writes will be marked dirty for next log read. 3805 * 3806 * 1. Take a snapshot of the bit and clear it if needed. 3807 * 2. Write protect the corresponding page. 3808 * 3. Copy the snapshot to the userspace. 3809 * 4. Flush TLB's if needed. 3810 */ 3811 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 3812 { 3813 bool is_dirty = false; 3814 int r; 3815 3816 mutex_lock(&kvm->slots_lock); 3817 3818 /* 3819 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 3820 */ 3821 if (kvm_x86_ops->flush_log_dirty) 3822 kvm_x86_ops->flush_log_dirty(kvm); 3823 3824 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 3825 3826 /* 3827 * All the TLBs can be flushed out of mmu lock, see the comments in 3828 * kvm_mmu_slot_remove_write_access(). 3829 */ 3830 lockdep_assert_held(&kvm->slots_lock); 3831 if (is_dirty) 3832 kvm_flush_remote_tlbs(kvm); 3833 3834 mutex_unlock(&kvm->slots_lock); 3835 return r; 3836 } 3837 3838 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 3839 bool line_status) 3840 { 3841 if (!irqchip_in_kernel(kvm)) 3842 return -ENXIO; 3843 3844 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 3845 irq_event->irq, irq_event->level, 3846 line_status); 3847 return 0; 3848 } 3849 3850 long kvm_arch_vm_ioctl(struct file *filp, 3851 unsigned int ioctl, unsigned long arg) 3852 { 3853 struct kvm *kvm = filp->private_data; 3854 void __user *argp = (void __user *)arg; 3855 int r = -ENOTTY; 3856 /* 3857 * This union makes it completely explicit to gcc-3.x 3858 * that these two variables' stack usage should be 3859 * combined, not added together. 3860 */ 3861 union { 3862 struct kvm_pit_state ps; 3863 struct kvm_pit_state2 ps2; 3864 struct kvm_pit_config pit_config; 3865 } u; 3866 3867 switch (ioctl) { 3868 case KVM_SET_TSS_ADDR: 3869 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 3870 break; 3871 case KVM_SET_IDENTITY_MAP_ADDR: { 3872 u64 ident_addr; 3873 3874 r = -EFAULT; 3875 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 3876 goto out; 3877 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 3878 break; 3879 } 3880 case KVM_SET_NR_MMU_PAGES: 3881 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 3882 break; 3883 case KVM_GET_NR_MMU_PAGES: 3884 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 3885 break; 3886 case KVM_CREATE_IRQCHIP: { 3887 struct kvm_pic *vpic; 3888 3889 mutex_lock(&kvm->lock); 3890 r = -EEXIST; 3891 if (kvm->arch.vpic) 3892 goto create_irqchip_unlock; 3893 r = -EINVAL; 3894 if (atomic_read(&kvm->online_vcpus)) 3895 goto create_irqchip_unlock; 3896 r = -ENOMEM; 3897 vpic = kvm_create_pic(kvm); 3898 if (vpic) { 3899 r = kvm_ioapic_init(kvm); 3900 if (r) { 3901 mutex_lock(&kvm->slots_lock); 3902 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, 3903 &vpic->dev_master); 3904 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, 3905 &vpic->dev_slave); 3906 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, 3907 &vpic->dev_eclr); 3908 mutex_unlock(&kvm->slots_lock); 3909 kfree(vpic); 3910 goto create_irqchip_unlock; 3911 } 3912 } else 3913 goto create_irqchip_unlock; 3914 smp_wmb(); 3915 kvm->arch.vpic = vpic; 3916 smp_wmb(); 3917 r = kvm_setup_default_irq_routing(kvm); 3918 if (r) { 3919 mutex_lock(&kvm->slots_lock); 3920 mutex_lock(&kvm->irq_lock); 3921 kvm_ioapic_destroy(kvm); 3922 kvm_destroy_pic(kvm); 3923 mutex_unlock(&kvm->irq_lock); 3924 mutex_unlock(&kvm->slots_lock); 3925 } 3926 create_irqchip_unlock: 3927 mutex_unlock(&kvm->lock); 3928 break; 3929 } 3930 case KVM_CREATE_PIT: 3931 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 3932 goto create_pit; 3933 case KVM_CREATE_PIT2: 3934 r = -EFAULT; 3935 if (copy_from_user(&u.pit_config, argp, 3936 sizeof(struct kvm_pit_config))) 3937 goto out; 3938 create_pit: 3939 mutex_lock(&kvm->slots_lock); 3940 r = -EEXIST; 3941 if (kvm->arch.vpit) 3942 goto create_pit_unlock; 3943 r = -ENOMEM; 3944 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 3945 if (kvm->arch.vpit) 3946 r = 0; 3947 create_pit_unlock: 3948 mutex_unlock(&kvm->slots_lock); 3949 break; 3950 case KVM_GET_IRQCHIP: { 3951 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3952 struct kvm_irqchip *chip; 3953 3954 chip = memdup_user(argp, sizeof(*chip)); 3955 if (IS_ERR(chip)) { 3956 r = PTR_ERR(chip); 3957 goto out; 3958 } 3959 3960 r = -ENXIO; 3961 if (!irqchip_in_kernel(kvm)) 3962 goto get_irqchip_out; 3963 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 3964 if (r) 3965 goto get_irqchip_out; 3966 r = -EFAULT; 3967 if (copy_to_user(argp, chip, sizeof *chip)) 3968 goto get_irqchip_out; 3969 r = 0; 3970 get_irqchip_out: 3971 kfree(chip); 3972 break; 3973 } 3974 case KVM_SET_IRQCHIP: { 3975 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3976 struct kvm_irqchip *chip; 3977 3978 chip = memdup_user(argp, sizeof(*chip)); 3979 if (IS_ERR(chip)) { 3980 r = PTR_ERR(chip); 3981 goto out; 3982 } 3983 3984 r = -ENXIO; 3985 if (!irqchip_in_kernel(kvm)) 3986 goto set_irqchip_out; 3987 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 3988 if (r) 3989 goto set_irqchip_out; 3990 r = 0; 3991 set_irqchip_out: 3992 kfree(chip); 3993 break; 3994 } 3995 case KVM_GET_PIT: { 3996 r = -EFAULT; 3997 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 3998 goto out; 3999 r = -ENXIO; 4000 if (!kvm->arch.vpit) 4001 goto out; 4002 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 4003 if (r) 4004 goto out; 4005 r = -EFAULT; 4006 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 4007 goto out; 4008 r = 0; 4009 break; 4010 } 4011 case KVM_SET_PIT: { 4012 r = -EFAULT; 4013 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 4014 goto out; 4015 r = -ENXIO; 4016 if (!kvm->arch.vpit) 4017 goto out; 4018 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 4019 break; 4020 } 4021 case KVM_GET_PIT2: { 4022 r = -ENXIO; 4023 if (!kvm->arch.vpit) 4024 goto out; 4025 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 4026 if (r) 4027 goto out; 4028 r = -EFAULT; 4029 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 4030 goto out; 4031 r = 0; 4032 break; 4033 } 4034 case KVM_SET_PIT2: { 4035 r = -EFAULT; 4036 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 4037 goto out; 4038 r = -ENXIO; 4039 if (!kvm->arch.vpit) 4040 goto out; 4041 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 4042 break; 4043 } 4044 case KVM_REINJECT_CONTROL: { 4045 struct kvm_reinject_control control; 4046 r = -EFAULT; 4047 if (copy_from_user(&control, argp, sizeof(control))) 4048 goto out; 4049 r = kvm_vm_ioctl_reinject(kvm, &control); 4050 break; 4051 } 4052 case KVM_XEN_HVM_CONFIG: { 4053 r = -EFAULT; 4054 if (copy_from_user(&kvm->arch.xen_hvm_config, argp, 4055 sizeof(struct kvm_xen_hvm_config))) 4056 goto out; 4057 r = -EINVAL; 4058 if (kvm->arch.xen_hvm_config.flags) 4059 goto out; 4060 r = 0; 4061 break; 4062 } 4063 case KVM_SET_CLOCK: { 4064 struct kvm_clock_data user_ns; 4065 u64 now_ns; 4066 s64 delta; 4067 4068 r = -EFAULT; 4069 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 4070 goto out; 4071 4072 r = -EINVAL; 4073 if (user_ns.flags) 4074 goto out; 4075 4076 r = 0; 4077 local_irq_disable(); 4078 now_ns = get_kernel_ns(); 4079 delta = user_ns.clock - now_ns; 4080 local_irq_enable(); 4081 kvm->arch.kvmclock_offset = delta; 4082 kvm_gen_update_masterclock(kvm); 4083 break; 4084 } 4085 case KVM_GET_CLOCK: { 4086 struct kvm_clock_data user_ns; 4087 u64 now_ns; 4088 4089 local_irq_disable(); 4090 now_ns = get_kernel_ns(); 4091 user_ns.clock = kvm->arch.kvmclock_offset + now_ns; 4092 local_irq_enable(); 4093 user_ns.flags = 0; 4094 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 4095 4096 r = -EFAULT; 4097 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 4098 goto out; 4099 r = 0; 4100 break; 4101 } 4102 4103 default: 4104 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg); 4105 } 4106 out: 4107 return r; 4108 } 4109 4110 static void kvm_init_msr_list(void) 4111 { 4112 u32 dummy[2]; 4113 unsigned i, j; 4114 4115 /* skip the first msrs in the list. KVM-specific */ 4116 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { 4117 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4118 continue; 4119 4120 /* 4121 * Even MSRs that are valid in the host may not be exposed 4122 * to the guests in some cases. We could work around this 4123 * in VMX with the generic MSR save/load machinery, but it 4124 * is not really worthwhile since it will really only 4125 * happen with nested virtualization. 4126 */ 4127 switch (msrs_to_save[i]) { 4128 case MSR_IA32_BNDCFGS: 4129 if (!kvm_x86_ops->mpx_supported()) 4130 continue; 4131 break; 4132 default: 4133 break; 4134 } 4135 4136 if (j < i) 4137 msrs_to_save[j] = msrs_to_save[i]; 4138 j++; 4139 } 4140 num_msrs_to_save = j; 4141 } 4142 4143 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 4144 const void *v) 4145 { 4146 int handled = 0; 4147 int n; 4148 4149 do { 4150 n = min(len, 8); 4151 if (!(vcpu->arch.apic && 4152 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 4153 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 4154 break; 4155 handled += n; 4156 addr += n; 4157 len -= n; 4158 v += n; 4159 } while (len); 4160 4161 return handled; 4162 } 4163 4164 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4165 { 4166 int handled = 0; 4167 int n; 4168 4169 do { 4170 n = min(len, 8); 4171 if (!(vcpu->arch.apic && 4172 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 4173 addr, n, v)) 4174 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 4175 break; 4176 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); 4177 handled += n; 4178 addr += n; 4179 len -= n; 4180 v += n; 4181 } while (len); 4182 4183 return handled; 4184 } 4185 4186 static void kvm_set_segment(struct kvm_vcpu *vcpu, 4187 struct kvm_segment *var, int seg) 4188 { 4189 kvm_x86_ops->set_segment(vcpu, var, seg); 4190 } 4191 4192 void kvm_get_segment(struct kvm_vcpu *vcpu, 4193 struct kvm_segment *var, int seg) 4194 { 4195 kvm_x86_ops->get_segment(vcpu, var, seg); 4196 } 4197 4198 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 4199 struct x86_exception *exception) 4200 { 4201 gpa_t t_gpa; 4202 4203 BUG_ON(!mmu_is_nested(vcpu)); 4204 4205 /* NPT walks are always user-walks */ 4206 access |= PFERR_USER_MASK; 4207 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); 4208 4209 return t_gpa; 4210 } 4211 4212 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 4213 struct x86_exception *exception) 4214 { 4215 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4216 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4217 } 4218 4219 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 4220 struct x86_exception *exception) 4221 { 4222 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4223 access |= PFERR_FETCH_MASK; 4224 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4225 } 4226 4227 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 4228 struct x86_exception *exception) 4229 { 4230 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4231 access |= PFERR_WRITE_MASK; 4232 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4233 } 4234 4235 /* uses this to access any guest's mapped memory without checking CPL */ 4236 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 4237 struct x86_exception *exception) 4238 { 4239 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 4240 } 4241 4242 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 4243 struct kvm_vcpu *vcpu, u32 access, 4244 struct x86_exception *exception) 4245 { 4246 void *data = val; 4247 int r = X86EMUL_CONTINUE; 4248 4249 while (bytes) { 4250 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 4251 exception); 4252 unsigned offset = addr & (PAGE_SIZE-1); 4253 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 4254 int ret; 4255 4256 if (gpa == UNMAPPED_GVA) 4257 return X86EMUL_PROPAGATE_FAULT; 4258 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data, 4259 offset, toread); 4260 if (ret < 0) { 4261 r = X86EMUL_IO_NEEDED; 4262 goto out; 4263 } 4264 4265 bytes -= toread; 4266 data += toread; 4267 addr += toread; 4268 } 4269 out: 4270 return r; 4271 } 4272 4273 /* used for instruction fetching */ 4274 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4275 gva_t addr, void *val, unsigned int bytes, 4276 struct x86_exception *exception) 4277 { 4278 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4279 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4280 unsigned offset; 4281 int ret; 4282 4283 /* Inline kvm_read_guest_virt_helper for speed. */ 4284 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 4285 exception); 4286 if (unlikely(gpa == UNMAPPED_GVA)) 4287 return X86EMUL_PROPAGATE_FAULT; 4288 4289 offset = addr & (PAGE_SIZE-1); 4290 if (WARN_ON(offset + bytes > PAGE_SIZE)) 4291 bytes = (unsigned)PAGE_SIZE - offset; 4292 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val, 4293 offset, bytes); 4294 if (unlikely(ret < 0)) 4295 return X86EMUL_IO_NEEDED; 4296 4297 return X86EMUL_CONTINUE; 4298 } 4299 4300 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4301 gva_t addr, void *val, unsigned int bytes, 4302 struct x86_exception *exception) 4303 { 4304 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4305 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4306 4307 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4308 exception); 4309 } 4310 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4311 4312 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4313 gva_t addr, void *val, unsigned int bytes, 4314 struct x86_exception *exception) 4315 { 4316 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4317 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4318 } 4319 4320 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4321 gva_t addr, void *val, 4322 unsigned int bytes, 4323 struct x86_exception *exception) 4324 { 4325 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4326 void *data = val; 4327 int r = X86EMUL_CONTINUE; 4328 4329 while (bytes) { 4330 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4331 PFERR_WRITE_MASK, 4332 exception); 4333 unsigned offset = addr & (PAGE_SIZE-1); 4334 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4335 int ret; 4336 4337 if (gpa == UNMAPPED_GVA) 4338 return X86EMUL_PROPAGATE_FAULT; 4339 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); 4340 if (ret < 0) { 4341 r = X86EMUL_IO_NEEDED; 4342 goto out; 4343 } 4344 4345 bytes -= towrite; 4346 data += towrite; 4347 addr += towrite; 4348 } 4349 out: 4350 return r; 4351 } 4352 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4353 4354 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4355 gpa_t *gpa, struct x86_exception *exception, 4356 bool write) 4357 { 4358 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4359 | (write ? PFERR_WRITE_MASK : 0); 4360 4361 if (vcpu_match_mmio_gva(vcpu, gva) 4362 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4363 vcpu->arch.access, access)) { 4364 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4365 (gva & (PAGE_SIZE - 1)); 4366 trace_vcpu_match_mmio(gva, *gpa, write, false); 4367 return 1; 4368 } 4369 4370 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4371 4372 if (*gpa == UNMAPPED_GVA) 4373 return -1; 4374 4375 /* For APIC access vmexit */ 4376 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4377 return 1; 4378 4379 if (vcpu_match_mmio_gpa(vcpu, *gpa)) { 4380 trace_vcpu_match_mmio(gva, *gpa, write, true); 4381 return 1; 4382 } 4383 4384 return 0; 4385 } 4386 4387 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4388 const void *val, int bytes) 4389 { 4390 int ret; 4391 4392 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); 4393 if (ret < 0) 4394 return 0; 4395 kvm_mmu_pte_write(vcpu, gpa, val, bytes); 4396 return 1; 4397 } 4398 4399 struct read_write_emulator_ops { 4400 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4401 int bytes); 4402 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4403 void *val, int bytes); 4404 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4405 int bytes, void *val); 4406 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4407 void *val, int bytes); 4408 bool write; 4409 }; 4410 4411 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4412 { 4413 if (vcpu->mmio_read_completed) { 4414 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4415 vcpu->mmio_fragments[0].gpa, *(u64 *)val); 4416 vcpu->mmio_read_completed = 0; 4417 return 1; 4418 } 4419 4420 return 0; 4421 } 4422 4423 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4424 void *val, int bytes) 4425 { 4426 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes); 4427 } 4428 4429 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4430 void *val, int bytes) 4431 { 4432 return emulator_write_phys(vcpu, gpa, val, bytes); 4433 } 4434 4435 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4436 { 4437 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); 4438 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4439 } 4440 4441 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4442 void *val, int bytes) 4443 { 4444 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); 4445 return X86EMUL_IO_NEEDED; 4446 } 4447 4448 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4449 void *val, int bytes) 4450 { 4451 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4452 4453 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4454 return X86EMUL_CONTINUE; 4455 } 4456 4457 static const struct read_write_emulator_ops read_emultor = { 4458 .read_write_prepare = read_prepare, 4459 .read_write_emulate = read_emulate, 4460 .read_write_mmio = vcpu_mmio_read, 4461 .read_write_exit_mmio = read_exit_mmio, 4462 }; 4463 4464 static const struct read_write_emulator_ops write_emultor = { 4465 .read_write_emulate = write_emulate, 4466 .read_write_mmio = write_mmio, 4467 .read_write_exit_mmio = write_exit_mmio, 4468 .write = true, 4469 }; 4470 4471 static int emulator_read_write_onepage(unsigned long addr, void *val, 4472 unsigned int bytes, 4473 struct x86_exception *exception, 4474 struct kvm_vcpu *vcpu, 4475 const struct read_write_emulator_ops *ops) 4476 { 4477 gpa_t gpa; 4478 int handled, ret; 4479 bool write = ops->write; 4480 struct kvm_mmio_fragment *frag; 4481 4482 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 4483 4484 if (ret < 0) 4485 return X86EMUL_PROPAGATE_FAULT; 4486 4487 /* For APIC access vmexit */ 4488 if (ret) 4489 goto mmio; 4490 4491 if (ops->read_write_emulate(vcpu, gpa, val, bytes)) 4492 return X86EMUL_CONTINUE; 4493 4494 mmio: 4495 /* 4496 * Is this MMIO handled locally? 4497 */ 4498 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 4499 if (handled == bytes) 4500 return X86EMUL_CONTINUE; 4501 4502 gpa += handled; 4503 bytes -= handled; 4504 val += handled; 4505 4506 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 4507 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 4508 frag->gpa = gpa; 4509 frag->data = val; 4510 frag->len = bytes; 4511 return X86EMUL_CONTINUE; 4512 } 4513 4514 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 4515 unsigned long addr, 4516 void *val, unsigned int bytes, 4517 struct x86_exception *exception, 4518 const struct read_write_emulator_ops *ops) 4519 { 4520 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4521 gpa_t gpa; 4522 int rc; 4523 4524 if (ops->read_write_prepare && 4525 ops->read_write_prepare(vcpu, val, bytes)) 4526 return X86EMUL_CONTINUE; 4527 4528 vcpu->mmio_nr_fragments = 0; 4529 4530 /* Crossing a page boundary? */ 4531 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 4532 int now; 4533 4534 now = -addr & ~PAGE_MASK; 4535 rc = emulator_read_write_onepage(addr, val, now, exception, 4536 vcpu, ops); 4537 4538 if (rc != X86EMUL_CONTINUE) 4539 return rc; 4540 addr += now; 4541 if (ctxt->mode != X86EMUL_MODE_PROT64) 4542 addr = (u32)addr; 4543 val += now; 4544 bytes -= now; 4545 } 4546 4547 rc = emulator_read_write_onepage(addr, val, bytes, exception, 4548 vcpu, ops); 4549 if (rc != X86EMUL_CONTINUE) 4550 return rc; 4551 4552 if (!vcpu->mmio_nr_fragments) 4553 return rc; 4554 4555 gpa = vcpu->mmio_fragments[0].gpa; 4556 4557 vcpu->mmio_needed = 1; 4558 vcpu->mmio_cur_fragment = 0; 4559 4560 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 4561 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 4562 vcpu->run->exit_reason = KVM_EXIT_MMIO; 4563 vcpu->run->mmio.phys_addr = gpa; 4564 4565 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 4566 } 4567 4568 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 4569 unsigned long addr, 4570 void *val, 4571 unsigned int bytes, 4572 struct x86_exception *exception) 4573 { 4574 return emulator_read_write(ctxt, addr, val, bytes, 4575 exception, &read_emultor); 4576 } 4577 4578 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 4579 unsigned long addr, 4580 const void *val, 4581 unsigned int bytes, 4582 struct x86_exception *exception) 4583 { 4584 return emulator_read_write(ctxt, addr, (void *)val, bytes, 4585 exception, &write_emultor); 4586 } 4587 4588 #define CMPXCHG_TYPE(t, ptr, old, new) \ 4589 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 4590 4591 #ifdef CONFIG_X86_64 4592 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 4593 #else 4594 # define CMPXCHG64(ptr, old, new) \ 4595 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 4596 #endif 4597 4598 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 4599 unsigned long addr, 4600 const void *old, 4601 const void *new, 4602 unsigned int bytes, 4603 struct x86_exception *exception) 4604 { 4605 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4606 gpa_t gpa; 4607 struct page *page; 4608 char *kaddr; 4609 bool exchanged; 4610 4611 /* guests cmpxchg8b have to be emulated atomically */ 4612 if (bytes > 8 || (bytes & (bytes - 1))) 4613 goto emul_write; 4614 4615 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 4616 4617 if (gpa == UNMAPPED_GVA || 4618 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4619 goto emul_write; 4620 4621 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 4622 goto emul_write; 4623 4624 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); 4625 if (is_error_page(page)) 4626 goto emul_write; 4627 4628 kaddr = kmap_atomic(page); 4629 kaddr += offset_in_page(gpa); 4630 switch (bytes) { 4631 case 1: 4632 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 4633 break; 4634 case 2: 4635 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 4636 break; 4637 case 4: 4638 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 4639 break; 4640 case 8: 4641 exchanged = CMPXCHG64(kaddr, old, new); 4642 break; 4643 default: 4644 BUG(); 4645 } 4646 kunmap_atomic(kaddr); 4647 kvm_release_page_dirty(page); 4648 4649 if (!exchanged) 4650 return X86EMUL_CMPXCHG_FAILED; 4651 4652 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT); 4653 kvm_mmu_pte_write(vcpu, gpa, new, bytes); 4654 4655 return X86EMUL_CONTINUE; 4656 4657 emul_write: 4658 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 4659 4660 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 4661 } 4662 4663 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 4664 { 4665 /* TODO: String I/O for in kernel device */ 4666 int r; 4667 4668 if (vcpu->arch.pio.in) 4669 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 4670 vcpu->arch.pio.size, pd); 4671 else 4672 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 4673 vcpu->arch.pio.port, vcpu->arch.pio.size, 4674 pd); 4675 return r; 4676 } 4677 4678 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 4679 unsigned short port, void *val, 4680 unsigned int count, bool in) 4681 { 4682 vcpu->arch.pio.port = port; 4683 vcpu->arch.pio.in = in; 4684 vcpu->arch.pio.count = count; 4685 vcpu->arch.pio.size = size; 4686 4687 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 4688 vcpu->arch.pio.count = 0; 4689 return 1; 4690 } 4691 4692 vcpu->run->exit_reason = KVM_EXIT_IO; 4693 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 4694 vcpu->run->io.size = size; 4695 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 4696 vcpu->run->io.count = count; 4697 vcpu->run->io.port = port; 4698 4699 return 0; 4700 } 4701 4702 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 4703 int size, unsigned short port, void *val, 4704 unsigned int count) 4705 { 4706 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4707 int ret; 4708 4709 if (vcpu->arch.pio.count) 4710 goto data_avail; 4711 4712 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 4713 if (ret) { 4714 data_avail: 4715 memcpy(val, vcpu->arch.pio_data, size * count); 4716 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 4717 vcpu->arch.pio.count = 0; 4718 return 1; 4719 } 4720 4721 return 0; 4722 } 4723 4724 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 4725 int size, unsigned short port, 4726 const void *val, unsigned int count) 4727 { 4728 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4729 4730 memcpy(vcpu->arch.pio_data, val, size * count); 4731 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 4732 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 4733 } 4734 4735 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 4736 { 4737 return kvm_x86_ops->get_segment_base(vcpu, seg); 4738 } 4739 4740 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 4741 { 4742 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 4743 } 4744 4745 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 4746 { 4747 if (!need_emulate_wbinvd(vcpu)) 4748 return X86EMUL_CONTINUE; 4749 4750 if (kvm_x86_ops->has_wbinvd_exit()) { 4751 int cpu = get_cpu(); 4752 4753 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4754 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 4755 wbinvd_ipi, NULL, 1); 4756 put_cpu(); 4757 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 4758 } else 4759 wbinvd(); 4760 return X86EMUL_CONTINUE; 4761 } 4762 4763 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 4764 { 4765 kvm_x86_ops->skip_emulated_instruction(vcpu); 4766 return kvm_emulate_wbinvd_noskip(vcpu); 4767 } 4768 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 4769 4770 4771 4772 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 4773 { 4774 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 4775 } 4776 4777 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 4778 unsigned long *dest) 4779 { 4780 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 4781 } 4782 4783 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 4784 unsigned long value) 4785 { 4786 4787 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 4788 } 4789 4790 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 4791 { 4792 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 4793 } 4794 4795 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 4796 { 4797 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4798 unsigned long value; 4799 4800 switch (cr) { 4801 case 0: 4802 value = kvm_read_cr0(vcpu); 4803 break; 4804 case 2: 4805 value = vcpu->arch.cr2; 4806 break; 4807 case 3: 4808 value = kvm_read_cr3(vcpu); 4809 break; 4810 case 4: 4811 value = kvm_read_cr4(vcpu); 4812 break; 4813 case 8: 4814 value = kvm_get_cr8(vcpu); 4815 break; 4816 default: 4817 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4818 return 0; 4819 } 4820 4821 return value; 4822 } 4823 4824 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 4825 { 4826 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4827 int res = 0; 4828 4829 switch (cr) { 4830 case 0: 4831 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 4832 break; 4833 case 2: 4834 vcpu->arch.cr2 = val; 4835 break; 4836 case 3: 4837 res = kvm_set_cr3(vcpu, val); 4838 break; 4839 case 4: 4840 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 4841 break; 4842 case 8: 4843 res = kvm_set_cr8(vcpu, val); 4844 break; 4845 default: 4846 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4847 res = -1; 4848 } 4849 4850 return res; 4851 } 4852 4853 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 4854 { 4855 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 4856 } 4857 4858 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4859 { 4860 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 4861 } 4862 4863 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4864 { 4865 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 4866 } 4867 4868 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4869 { 4870 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 4871 } 4872 4873 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4874 { 4875 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 4876 } 4877 4878 static unsigned long emulator_get_cached_segment_base( 4879 struct x86_emulate_ctxt *ctxt, int seg) 4880 { 4881 return get_segment_base(emul_to_vcpu(ctxt), seg); 4882 } 4883 4884 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 4885 struct desc_struct *desc, u32 *base3, 4886 int seg) 4887 { 4888 struct kvm_segment var; 4889 4890 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 4891 *selector = var.selector; 4892 4893 if (var.unusable) { 4894 memset(desc, 0, sizeof(*desc)); 4895 return false; 4896 } 4897 4898 if (var.g) 4899 var.limit >>= 12; 4900 set_desc_limit(desc, var.limit); 4901 set_desc_base(desc, (unsigned long)var.base); 4902 #ifdef CONFIG_X86_64 4903 if (base3) 4904 *base3 = var.base >> 32; 4905 #endif 4906 desc->type = var.type; 4907 desc->s = var.s; 4908 desc->dpl = var.dpl; 4909 desc->p = var.present; 4910 desc->avl = var.avl; 4911 desc->l = var.l; 4912 desc->d = var.db; 4913 desc->g = var.g; 4914 4915 return true; 4916 } 4917 4918 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 4919 struct desc_struct *desc, u32 base3, 4920 int seg) 4921 { 4922 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4923 struct kvm_segment var; 4924 4925 var.selector = selector; 4926 var.base = get_desc_base(desc); 4927 #ifdef CONFIG_X86_64 4928 var.base |= ((u64)base3) << 32; 4929 #endif 4930 var.limit = get_desc_limit(desc); 4931 if (desc->g) 4932 var.limit = (var.limit << 12) | 0xfff; 4933 var.type = desc->type; 4934 var.dpl = desc->dpl; 4935 var.db = desc->d; 4936 var.s = desc->s; 4937 var.l = desc->l; 4938 var.g = desc->g; 4939 var.avl = desc->avl; 4940 var.present = desc->p; 4941 var.unusable = !var.present; 4942 var.padding = 0; 4943 4944 kvm_set_segment(vcpu, &var, seg); 4945 return; 4946 } 4947 4948 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 4949 u32 msr_index, u64 *pdata) 4950 { 4951 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); 4952 } 4953 4954 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 4955 u32 msr_index, u64 data) 4956 { 4957 struct msr_data msr; 4958 4959 msr.data = data; 4960 msr.index = msr_index; 4961 msr.host_initiated = false; 4962 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 4963 } 4964 4965 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 4966 u32 pmc) 4967 { 4968 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc); 4969 } 4970 4971 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 4972 u32 pmc, u64 *pdata) 4973 { 4974 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata); 4975 } 4976 4977 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 4978 { 4979 emul_to_vcpu(ctxt)->arch.halt_request = 1; 4980 } 4981 4982 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) 4983 { 4984 preempt_disable(); 4985 kvm_load_guest_fpu(emul_to_vcpu(ctxt)); 4986 /* 4987 * CR0.TS may reference the host fpu state, not the guest fpu state, 4988 * so it may be clear at this point. 4989 */ 4990 clts(); 4991 } 4992 4993 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) 4994 { 4995 preempt_enable(); 4996 } 4997 4998 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 4999 struct x86_instruction_info *info, 5000 enum x86_intercept_stage stage) 5001 { 5002 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 5003 } 5004 5005 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 5006 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) 5007 { 5008 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); 5009 } 5010 5011 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 5012 { 5013 return kvm_register_read(emul_to_vcpu(ctxt), reg); 5014 } 5015 5016 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 5017 { 5018 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 5019 } 5020 5021 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 5022 { 5023 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 5024 } 5025 5026 static const struct x86_emulate_ops emulate_ops = { 5027 .read_gpr = emulator_read_gpr, 5028 .write_gpr = emulator_write_gpr, 5029 .read_std = kvm_read_guest_virt_system, 5030 .write_std = kvm_write_guest_virt_system, 5031 .fetch = kvm_fetch_guest_virt, 5032 .read_emulated = emulator_read_emulated, 5033 .write_emulated = emulator_write_emulated, 5034 .cmpxchg_emulated = emulator_cmpxchg_emulated, 5035 .invlpg = emulator_invlpg, 5036 .pio_in_emulated = emulator_pio_in_emulated, 5037 .pio_out_emulated = emulator_pio_out_emulated, 5038 .get_segment = emulator_get_segment, 5039 .set_segment = emulator_set_segment, 5040 .get_cached_segment_base = emulator_get_cached_segment_base, 5041 .get_gdt = emulator_get_gdt, 5042 .get_idt = emulator_get_idt, 5043 .set_gdt = emulator_set_gdt, 5044 .set_idt = emulator_set_idt, 5045 .get_cr = emulator_get_cr, 5046 .set_cr = emulator_set_cr, 5047 .cpl = emulator_get_cpl, 5048 .get_dr = emulator_get_dr, 5049 .set_dr = emulator_set_dr, 5050 .set_msr = emulator_set_msr, 5051 .get_msr = emulator_get_msr, 5052 .check_pmc = emulator_check_pmc, 5053 .read_pmc = emulator_read_pmc, 5054 .halt = emulator_halt, 5055 .wbinvd = emulator_wbinvd, 5056 .fix_hypercall = emulator_fix_hypercall, 5057 .get_fpu = emulator_get_fpu, 5058 .put_fpu = emulator_put_fpu, 5059 .intercept = emulator_intercept, 5060 .get_cpuid = emulator_get_cpuid, 5061 .set_nmi_mask = emulator_set_nmi_mask, 5062 }; 5063 5064 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 5065 { 5066 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 5067 /* 5068 * an sti; sti; sequence only disable interrupts for the first 5069 * instruction. So, if the last instruction, be it emulated or 5070 * not, left the system with the INT_STI flag enabled, it 5071 * means that the last instruction is an sti. We should not 5072 * leave the flag on in this case. The same goes for mov ss 5073 */ 5074 if (int_shadow & mask) 5075 mask = 0; 5076 if (unlikely(int_shadow || mask)) { 5077 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 5078 if (!mask) 5079 kvm_make_request(KVM_REQ_EVENT, vcpu); 5080 } 5081 } 5082 5083 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 5084 { 5085 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5086 if (ctxt->exception.vector == PF_VECTOR) 5087 return kvm_propagate_fault(vcpu, &ctxt->exception); 5088 5089 if (ctxt->exception.error_code_valid) 5090 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 5091 ctxt->exception.error_code); 5092 else 5093 kvm_queue_exception(vcpu, ctxt->exception.vector); 5094 return false; 5095 } 5096 5097 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 5098 { 5099 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5100 int cs_db, cs_l; 5101 5102 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 5103 5104 ctxt->eflags = kvm_get_rflags(vcpu); 5105 ctxt->eip = kvm_rip_read(vcpu); 5106 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 5107 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 5108 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 5109 cs_db ? X86EMUL_MODE_PROT32 : 5110 X86EMUL_MODE_PROT16; 5111 ctxt->guest_mode = is_guest_mode(vcpu); 5112 5113 init_decode_cache(ctxt); 5114 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5115 } 5116 5117 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 5118 { 5119 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5120 int ret; 5121 5122 init_emulate_ctxt(vcpu); 5123 5124 ctxt->op_bytes = 2; 5125 ctxt->ad_bytes = 2; 5126 ctxt->_eip = ctxt->eip + inc_eip; 5127 ret = emulate_int_real(ctxt, irq); 5128 5129 if (ret != X86EMUL_CONTINUE) 5130 return EMULATE_FAIL; 5131 5132 ctxt->eip = ctxt->_eip; 5133 kvm_rip_write(vcpu, ctxt->eip); 5134 kvm_set_rflags(vcpu, ctxt->eflags); 5135 5136 if (irq == NMI_VECTOR) 5137 vcpu->arch.nmi_pending = 0; 5138 else 5139 vcpu->arch.interrupt.pending = false; 5140 5141 return EMULATE_DONE; 5142 } 5143 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 5144 5145 static int handle_emulation_failure(struct kvm_vcpu *vcpu) 5146 { 5147 int r = EMULATE_DONE; 5148 5149 ++vcpu->stat.insn_emulation_fail; 5150 trace_kvm_emulate_insn_failed(vcpu); 5151 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 5152 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5153 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 5154 vcpu->run->internal.ndata = 0; 5155 r = EMULATE_FAIL; 5156 } 5157 kvm_queue_exception(vcpu, UD_VECTOR); 5158 5159 return r; 5160 } 5161 5162 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 5163 bool write_fault_to_shadow_pgtable, 5164 int emulation_type) 5165 { 5166 gpa_t gpa = cr2; 5167 pfn_t pfn; 5168 5169 if (emulation_type & EMULTYPE_NO_REEXECUTE) 5170 return false; 5171 5172 if (!vcpu->arch.mmu.direct_map) { 5173 /* 5174 * Write permission should be allowed since only 5175 * write access need to be emulated. 5176 */ 5177 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5178 5179 /* 5180 * If the mapping is invalid in guest, let cpu retry 5181 * it to generate fault. 5182 */ 5183 if (gpa == UNMAPPED_GVA) 5184 return true; 5185 } 5186 5187 /* 5188 * Do not retry the unhandleable instruction if it faults on the 5189 * readonly host memory, otherwise it will goto a infinite loop: 5190 * retry instruction -> write #PF -> emulation fail -> retry 5191 * instruction -> ... 5192 */ 5193 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 5194 5195 /* 5196 * If the instruction failed on the error pfn, it can not be fixed, 5197 * report the error to userspace. 5198 */ 5199 if (is_error_noslot_pfn(pfn)) 5200 return false; 5201 5202 kvm_release_pfn_clean(pfn); 5203 5204 /* The instructions are well-emulated on direct mmu. */ 5205 if (vcpu->arch.mmu.direct_map) { 5206 unsigned int indirect_shadow_pages; 5207 5208 spin_lock(&vcpu->kvm->mmu_lock); 5209 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 5210 spin_unlock(&vcpu->kvm->mmu_lock); 5211 5212 if (indirect_shadow_pages) 5213 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5214 5215 return true; 5216 } 5217 5218 /* 5219 * if emulation was due to access to shadowed page table 5220 * and it failed try to unshadow page and re-enter the 5221 * guest to let CPU execute the instruction. 5222 */ 5223 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5224 5225 /* 5226 * If the access faults on its page table, it can not 5227 * be fixed by unprotecting shadow page and it should 5228 * be reported to userspace. 5229 */ 5230 return !write_fault_to_shadow_pgtable; 5231 } 5232 5233 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5234 unsigned long cr2, int emulation_type) 5235 { 5236 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5237 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5238 5239 last_retry_eip = vcpu->arch.last_retry_eip; 5240 last_retry_addr = vcpu->arch.last_retry_addr; 5241 5242 /* 5243 * If the emulation is caused by #PF and it is non-page_table 5244 * writing instruction, it means the VM-EXIT is caused by shadow 5245 * page protected, we can zap the shadow page and retry this 5246 * instruction directly. 5247 * 5248 * Note: if the guest uses a non-page-table modifying instruction 5249 * on the PDE that points to the instruction, then we will unmap 5250 * the instruction and go to an infinite loop. So, we cache the 5251 * last retried eip and the last fault address, if we meet the eip 5252 * and the address again, we can break out of the potential infinite 5253 * loop. 5254 */ 5255 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5256 5257 if (!(emulation_type & EMULTYPE_RETRY)) 5258 return false; 5259 5260 if (x86_page_table_writing_insn(ctxt)) 5261 return false; 5262 5263 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5264 return false; 5265 5266 vcpu->arch.last_retry_eip = ctxt->eip; 5267 vcpu->arch.last_retry_addr = cr2; 5268 5269 if (!vcpu->arch.mmu.direct_map) 5270 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5271 5272 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5273 5274 return true; 5275 } 5276 5277 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5278 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5279 5280 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5281 unsigned long *db) 5282 { 5283 u32 dr6 = 0; 5284 int i; 5285 u32 enable, rwlen; 5286 5287 enable = dr7; 5288 rwlen = dr7 >> 16; 5289 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5290 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5291 dr6 |= (1 << i); 5292 return dr6; 5293 } 5294 5295 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) 5296 { 5297 struct kvm_run *kvm_run = vcpu->run; 5298 5299 /* 5300 * rflags is the old, "raw" value of the flags. The new value has 5301 * not been saved yet. 5302 * 5303 * This is correct even for TF set by the guest, because "the 5304 * processor will not generate this exception after the instruction 5305 * that sets the TF flag". 5306 */ 5307 if (unlikely(rflags & X86_EFLAGS_TF)) { 5308 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5309 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | 5310 DR6_RTM; 5311 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5312 kvm_run->debug.arch.exception = DB_VECTOR; 5313 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5314 *r = EMULATE_USER_EXIT; 5315 } else { 5316 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; 5317 /* 5318 * "Certain debug exceptions may clear bit 0-3. The 5319 * remaining contents of the DR6 register are never 5320 * cleared by the processor". 5321 */ 5322 vcpu->arch.dr6 &= ~15; 5323 vcpu->arch.dr6 |= DR6_BS | DR6_RTM; 5324 kvm_queue_exception(vcpu, DB_VECTOR); 5325 } 5326 } 5327 } 5328 5329 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5330 { 5331 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5332 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5333 struct kvm_run *kvm_run = vcpu->run; 5334 unsigned long eip = kvm_get_linear_rip(vcpu); 5335 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5336 vcpu->arch.guest_debug_dr7, 5337 vcpu->arch.eff_db); 5338 5339 if (dr6 != 0) { 5340 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 5341 kvm_run->debug.arch.pc = eip; 5342 kvm_run->debug.arch.exception = DB_VECTOR; 5343 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5344 *r = EMULATE_USER_EXIT; 5345 return true; 5346 } 5347 } 5348 5349 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 5350 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 5351 unsigned long eip = kvm_get_linear_rip(vcpu); 5352 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5353 vcpu->arch.dr7, 5354 vcpu->arch.db); 5355 5356 if (dr6 != 0) { 5357 vcpu->arch.dr6 &= ~15; 5358 vcpu->arch.dr6 |= dr6 | DR6_RTM; 5359 kvm_queue_exception(vcpu, DB_VECTOR); 5360 *r = EMULATE_DONE; 5361 return true; 5362 } 5363 } 5364 5365 return false; 5366 } 5367 5368 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 5369 unsigned long cr2, 5370 int emulation_type, 5371 void *insn, 5372 int insn_len) 5373 { 5374 int r; 5375 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5376 bool writeback = true; 5377 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 5378 5379 /* 5380 * Clear write_fault_to_shadow_pgtable here to ensure it is 5381 * never reused. 5382 */ 5383 vcpu->arch.write_fault_to_shadow_pgtable = false; 5384 kvm_clear_exception_queue(vcpu); 5385 5386 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 5387 init_emulate_ctxt(vcpu); 5388 5389 /* 5390 * We will reenter on the same instruction since 5391 * we do not set complete_userspace_io. This does not 5392 * handle watchpoints yet, those would be handled in 5393 * the emulate_ops. 5394 */ 5395 if (kvm_vcpu_check_breakpoint(vcpu, &r)) 5396 return r; 5397 5398 ctxt->interruptibility = 0; 5399 ctxt->have_exception = false; 5400 ctxt->exception.vector = -1; 5401 ctxt->perm_ok = false; 5402 5403 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 5404 5405 r = x86_decode_insn(ctxt, insn, insn_len); 5406 5407 trace_kvm_emulate_insn_start(vcpu); 5408 ++vcpu->stat.insn_emulation; 5409 if (r != EMULATION_OK) { 5410 if (emulation_type & EMULTYPE_TRAP_UD) 5411 return EMULATE_FAIL; 5412 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5413 emulation_type)) 5414 return EMULATE_DONE; 5415 if (emulation_type & EMULTYPE_SKIP) 5416 return EMULATE_FAIL; 5417 return handle_emulation_failure(vcpu); 5418 } 5419 } 5420 5421 if (emulation_type & EMULTYPE_SKIP) { 5422 kvm_rip_write(vcpu, ctxt->_eip); 5423 if (ctxt->eflags & X86_EFLAGS_RF) 5424 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 5425 return EMULATE_DONE; 5426 } 5427 5428 if (retry_instruction(ctxt, cr2, emulation_type)) 5429 return EMULATE_DONE; 5430 5431 /* this is needed for vmware backdoor interface to work since it 5432 changes registers values during IO operation */ 5433 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 5434 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5435 emulator_invalidate_register_cache(ctxt); 5436 } 5437 5438 restart: 5439 r = x86_emulate_insn(ctxt); 5440 5441 if (r == EMULATION_INTERCEPTED) 5442 return EMULATE_DONE; 5443 5444 if (r == EMULATION_FAILED) { 5445 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5446 emulation_type)) 5447 return EMULATE_DONE; 5448 5449 return handle_emulation_failure(vcpu); 5450 } 5451 5452 if (ctxt->have_exception) { 5453 r = EMULATE_DONE; 5454 if (inject_emulated_exception(vcpu)) 5455 return r; 5456 } else if (vcpu->arch.pio.count) { 5457 if (!vcpu->arch.pio.in) { 5458 /* FIXME: return into emulator if single-stepping. */ 5459 vcpu->arch.pio.count = 0; 5460 } else { 5461 writeback = false; 5462 vcpu->arch.complete_userspace_io = complete_emulated_pio; 5463 } 5464 r = EMULATE_USER_EXIT; 5465 } else if (vcpu->mmio_needed) { 5466 if (!vcpu->mmio_is_write) 5467 writeback = false; 5468 r = EMULATE_USER_EXIT; 5469 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 5470 } else if (r == EMULATION_RESTART) 5471 goto restart; 5472 else 5473 r = EMULATE_DONE; 5474 5475 if (writeback) { 5476 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5477 toggle_interruptibility(vcpu, ctxt->interruptibility); 5478 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 5479 kvm_rip_write(vcpu, ctxt->eip); 5480 if (r == EMULATE_DONE) 5481 kvm_vcpu_check_singlestep(vcpu, rflags, &r); 5482 if (!ctxt->have_exception || 5483 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 5484 __kvm_set_rflags(vcpu, ctxt->eflags); 5485 5486 /* 5487 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 5488 * do nothing, and it will be requested again as soon as 5489 * the shadow expires. But we still need to check here, 5490 * because POPF has no interrupt shadow. 5491 */ 5492 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 5493 kvm_make_request(KVM_REQ_EVENT, vcpu); 5494 } else 5495 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 5496 5497 return r; 5498 } 5499 EXPORT_SYMBOL_GPL(x86_emulate_instruction); 5500 5501 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) 5502 { 5503 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 5504 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 5505 size, port, &val, 1); 5506 /* do not return to emulator after return from userspace */ 5507 vcpu->arch.pio.count = 0; 5508 return ret; 5509 } 5510 EXPORT_SYMBOL_GPL(kvm_fast_pio_out); 5511 5512 static void tsc_bad(void *info) 5513 { 5514 __this_cpu_write(cpu_tsc_khz, 0); 5515 } 5516 5517 static void tsc_khz_changed(void *data) 5518 { 5519 struct cpufreq_freqs *freq = data; 5520 unsigned long khz = 0; 5521 5522 if (data) 5523 khz = freq->new; 5524 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5525 khz = cpufreq_quick_get(raw_smp_processor_id()); 5526 if (!khz) 5527 khz = tsc_khz; 5528 __this_cpu_write(cpu_tsc_khz, khz); 5529 } 5530 5531 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 5532 void *data) 5533 { 5534 struct cpufreq_freqs *freq = data; 5535 struct kvm *kvm; 5536 struct kvm_vcpu *vcpu; 5537 int i, send_ipi = 0; 5538 5539 /* 5540 * We allow guests to temporarily run on slowing clocks, 5541 * provided we notify them after, or to run on accelerating 5542 * clocks, provided we notify them before. Thus time never 5543 * goes backwards. 5544 * 5545 * However, we have a problem. We can't atomically update 5546 * the frequency of a given CPU from this function; it is 5547 * merely a notifier, which can be called from any CPU. 5548 * Changing the TSC frequency at arbitrary points in time 5549 * requires a recomputation of local variables related to 5550 * the TSC for each VCPU. We must flag these local variables 5551 * to be updated and be sure the update takes place with the 5552 * new frequency before any guests proceed. 5553 * 5554 * Unfortunately, the combination of hotplug CPU and frequency 5555 * change creates an intractable locking scenario; the order 5556 * of when these callouts happen is undefined with respect to 5557 * CPU hotplug, and they can race with each other. As such, 5558 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 5559 * undefined; you can actually have a CPU frequency change take 5560 * place in between the computation of X and the setting of the 5561 * variable. To protect against this problem, all updates of 5562 * the per_cpu tsc_khz variable are done in an interrupt 5563 * protected IPI, and all callers wishing to update the value 5564 * must wait for a synchronous IPI to complete (which is trivial 5565 * if the caller is on the CPU already). This establishes the 5566 * necessary total order on variable updates. 5567 * 5568 * Note that because a guest time update may take place 5569 * anytime after the setting of the VCPU's request bit, the 5570 * correct TSC value must be set before the request. However, 5571 * to ensure the update actually makes it to any guest which 5572 * starts running in hardware virtualization between the set 5573 * and the acquisition of the spinlock, we must also ping the 5574 * CPU after setting the request bit. 5575 * 5576 */ 5577 5578 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 5579 return 0; 5580 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 5581 return 0; 5582 5583 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5584 5585 spin_lock(&kvm_lock); 5586 list_for_each_entry(kvm, &vm_list, vm_list) { 5587 kvm_for_each_vcpu(i, vcpu, kvm) { 5588 if (vcpu->cpu != freq->cpu) 5589 continue; 5590 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5591 if (vcpu->cpu != smp_processor_id()) 5592 send_ipi = 1; 5593 } 5594 } 5595 spin_unlock(&kvm_lock); 5596 5597 if (freq->old < freq->new && send_ipi) { 5598 /* 5599 * We upscale the frequency. Must make the guest 5600 * doesn't see old kvmclock values while running with 5601 * the new frequency, otherwise we risk the guest sees 5602 * time go backwards. 5603 * 5604 * In case we update the frequency for another cpu 5605 * (which might be in guest context) send an interrupt 5606 * to kick the cpu out of guest context. Next time 5607 * guest context is entered kvmclock will be updated, 5608 * so the guest will not see stale values. 5609 */ 5610 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5611 } 5612 return 0; 5613 } 5614 5615 static struct notifier_block kvmclock_cpufreq_notifier_block = { 5616 .notifier_call = kvmclock_cpufreq_notifier 5617 }; 5618 5619 static int kvmclock_cpu_notifier(struct notifier_block *nfb, 5620 unsigned long action, void *hcpu) 5621 { 5622 unsigned int cpu = (unsigned long)hcpu; 5623 5624 switch (action) { 5625 case CPU_ONLINE: 5626 case CPU_DOWN_FAILED: 5627 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5628 break; 5629 case CPU_DOWN_PREPARE: 5630 smp_call_function_single(cpu, tsc_bad, NULL, 1); 5631 break; 5632 } 5633 return NOTIFY_OK; 5634 } 5635 5636 static struct notifier_block kvmclock_cpu_notifier_block = { 5637 .notifier_call = kvmclock_cpu_notifier, 5638 .priority = -INT_MAX 5639 }; 5640 5641 static void kvm_timer_init(void) 5642 { 5643 int cpu; 5644 5645 max_tsc_khz = tsc_khz; 5646 5647 cpu_notifier_register_begin(); 5648 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 5649 #ifdef CONFIG_CPU_FREQ 5650 struct cpufreq_policy policy; 5651 memset(&policy, 0, sizeof(policy)); 5652 cpu = get_cpu(); 5653 cpufreq_get_policy(&policy, cpu); 5654 if (policy.cpuinfo.max_freq) 5655 max_tsc_khz = policy.cpuinfo.max_freq; 5656 put_cpu(); 5657 #endif 5658 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 5659 CPUFREQ_TRANSITION_NOTIFIER); 5660 } 5661 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 5662 for_each_online_cpu(cpu) 5663 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5664 5665 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5666 cpu_notifier_register_done(); 5667 5668 } 5669 5670 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 5671 5672 int kvm_is_in_guest(void) 5673 { 5674 return __this_cpu_read(current_vcpu) != NULL; 5675 } 5676 5677 static int kvm_is_user_mode(void) 5678 { 5679 int user_mode = 3; 5680 5681 if (__this_cpu_read(current_vcpu)) 5682 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 5683 5684 return user_mode != 0; 5685 } 5686 5687 static unsigned long kvm_get_guest_ip(void) 5688 { 5689 unsigned long ip = 0; 5690 5691 if (__this_cpu_read(current_vcpu)) 5692 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 5693 5694 return ip; 5695 } 5696 5697 static struct perf_guest_info_callbacks kvm_guest_cbs = { 5698 .is_in_guest = kvm_is_in_guest, 5699 .is_user_mode = kvm_is_user_mode, 5700 .get_guest_ip = kvm_get_guest_ip, 5701 }; 5702 5703 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) 5704 { 5705 __this_cpu_write(current_vcpu, vcpu); 5706 } 5707 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); 5708 5709 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) 5710 { 5711 __this_cpu_write(current_vcpu, NULL); 5712 } 5713 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); 5714 5715 static void kvm_set_mmio_spte_mask(void) 5716 { 5717 u64 mask; 5718 int maxphyaddr = boot_cpu_data.x86_phys_bits; 5719 5720 /* 5721 * Set the reserved bits and the present bit of an paging-structure 5722 * entry to generate page fault with PFER.RSV = 1. 5723 */ 5724 /* Mask the reserved physical address bits. */ 5725 mask = rsvd_bits(maxphyaddr, 51); 5726 5727 /* Bit 62 is always reserved for 32bit host. */ 5728 mask |= 0x3ull << 62; 5729 5730 /* Set the present bit. */ 5731 mask |= 1ull; 5732 5733 #ifdef CONFIG_X86_64 5734 /* 5735 * If reserved bit is not supported, clear the present bit to disable 5736 * mmio page fault. 5737 */ 5738 if (maxphyaddr == 52) 5739 mask &= ~1ull; 5740 #endif 5741 5742 kvm_mmu_set_mmio_spte_mask(mask); 5743 } 5744 5745 #ifdef CONFIG_X86_64 5746 static void pvclock_gtod_update_fn(struct work_struct *work) 5747 { 5748 struct kvm *kvm; 5749 5750 struct kvm_vcpu *vcpu; 5751 int i; 5752 5753 spin_lock(&kvm_lock); 5754 list_for_each_entry(kvm, &vm_list, vm_list) 5755 kvm_for_each_vcpu(i, vcpu, kvm) 5756 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 5757 atomic_set(&kvm_guest_has_master_clock, 0); 5758 spin_unlock(&kvm_lock); 5759 } 5760 5761 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 5762 5763 /* 5764 * Notification about pvclock gtod data update. 5765 */ 5766 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 5767 void *priv) 5768 { 5769 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 5770 struct timekeeper *tk = priv; 5771 5772 update_pvclock_gtod(tk); 5773 5774 /* disable master clock if host does not trust, or does not 5775 * use, TSC clocksource 5776 */ 5777 if (gtod->clock.vclock_mode != VCLOCK_TSC && 5778 atomic_read(&kvm_guest_has_master_clock) != 0) 5779 queue_work(system_long_wq, &pvclock_gtod_work); 5780 5781 return 0; 5782 } 5783 5784 static struct notifier_block pvclock_gtod_notifier = { 5785 .notifier_call = pvclock_gtod_notify, 5786 }; 5787 #endif 5788 5789 int kvm_arch_init(void *opaque) 5790 { 5791 int r; 5792 struct kvm_x86_ops *ops = opaque; 5793 5794 if (kvm_x86_ops) { 5795 printk(KERN_ERR "kvm: already loaded the other module\n"); 5796 r = -EEXIST; 5797 goto out; 5798 } 5799 5800 if (!ops->cpu_has_kvm_support()) { 5801 printk(KERN_ERR "kvm: no hardware support\n"); 5802 r = -EOPNOTSUPP; 5803 goto out; 5804 } 5805 if (ops->disabled_by_bios()) { 5806 printk(KERN_ERR "kvm: disabled by bios\n"); 5807 r = -EOPNOTSUPP; 5808 goto out; 5809 } 5810 5811 r = -ENOMEM; 5812 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 5813 if (!shared_msrs) { 5814 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 5815 goto out; 5816 } 5817 5818 r = kvm_mmu_module_init(); 5819 if (r) 5820 goto out_free_percpu; 5821 5822 kvm_set_mmio_spte_mask(); 5823 5824 kvm_x86_ops = ops; 5825 5826 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 5827 PT_DIRTY_MASK, PT64_NX_MASK, 0); 5828 5829 kvm_timer_init(); 5830 5831 perf_register_guest_info_callbacks(&kvm_guest_cbs); 5832 5833 if (cpu_has_xsave) 5834 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 5835 5836 kvm_lapic_init(); 5837 #ifdef CONFIG_X86_64 5838 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 5839 #endif 5840 5841 return 0; 5842 5843 out_free_percpu: 5844 free_percpu(shared_msrs); 5845 out: 5846 return r; 5847 } 5848 5849 void kvm_arch_exit(void) 5850 { 5851 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 5852 5853 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5854 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 5855 CPUFREQ_TRANSITION_NOTIFIER); 5856 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5857 #ifdef CONFIG_X86_64 5858 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 5859 #endif 5860 kvm_x86_ops = NULL; 5861 kvm_mmu_module_exit(); 5862 free_percpu(shared_msrs); 5863 } 5864 5865 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 5866 { 5867 ++vcpu->stat.halt_exits; 5868 if (irqchip_in_kernel(vcpu->kvm)) { 5869 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 5870 return 1; 5871 } else { 5872 vcpu->run->exit_reason = KVM_EXIT_HLT; 5873 return 0; 5874 } 5875 } 5876 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 5877 5878 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 5879 { 5880 kvm_x86_ops->skip_emulated_instruction(vcpu); 5881 return kvm_vcpu_halt(vcpu); 5882 } 5883 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 5884 5885 int kvm_hv_hypercall(struct kvm_vcpu *vcpu) 5886 { 5887 u64 param, ingpa, outgpa, ret; 5888 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; 5889 bool fast, longmode; 5890 5891 /* 5892 * hypercall generates UD from non zero cpl and real mode 5893 * per HYPER-V spec 5894 */ 5895 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { 5896 kvm_queue_exception(vcpu, UD_VECTOR); 5897 return 0; 5898 } 5899 5900 longmode = is_64_bit_mode(vcpu); 5901 5902 if (!longmode) { 5903 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | 5904 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); 5905 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | 5906 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); 5907 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | 5908 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); 5909 } 5910 #ifdef CONFIG_X86_64 5911 else { 5912 param = kvm_register_read(vcpu, VCPU_REGS_RCX); 5913 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); 5914 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); 5915 } 5916 #endif 5917 5918 code = param & 0xffff; 5919 fast = (param >> 16) & 0x1; 5920 rep_cnt = (param >> 32) & 0xfff; 5921 rep_idx = (param >> 48) & 0xfff; 5922 5923 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); 5924 5925 switch (code) { 5926 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: 5927 kvm_vcpu_on_spin(vcpu); 5928 break; 5929 default: 5930 res = HV_STATUS_INVALID_HYPERCALL_CODE; 5931 break; 5932 } 5933 5934 ret = res | (((u64)rep_done & 0xfff) << 32); 5935 if (longmode) { 5936 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 5937 } else { 5938 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); 5939 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); 5940 } 5941 5942 return 1; 5943 } 5944 5945 /* 5946 * kvm_pv_kick_cpu_op: Kick a vcpu. 5947 * 5948 * @apicid - apicid of vcpu to be kicked. 5949 */ 5950 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 5951 { 5952 struct kvm_lapic_irq lapic_irq; 5953 5954 lapic_irq.shorthand = 0; 5955 lapic_irq.dest_mode = 0; 5956 lapic_irq.dest_id = apicid; 5957 5958 lapic_irq.delivery_mode = APIC_DM_REMRD; 5959 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 5960 } 5961 5962 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 5963 { 5964 unsigned long nr, a0, a1, a2, a3, ret; 5965 int op_64_bit, r = 1; 5966 5967 kvm_x86_ops->skip_emulated_instruction(vcpu); 5968 5969 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 5970 return kvm_hv_hypercall(vcpu); 5971 5972 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 5973 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 5974 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 5975 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 5976 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 5977 5978 trace_kvm_hypercall(nr, a0, a1, a2, a3); 5979 5980 op_64_bit = is_64_bit_mode(vcpu); 5981 if (!op_64_bit) { 5982 nr &= 0xFFFFFFFF; 5983 a0 &= 0xFFFFFFFF; 5984 a1 &= 0xFFFFFFFF; 5985 a2 &= 0xFFFFFFFF; 5986 a3 &= 0xFFFFFFFF; 5987 } 5988 5989 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 5990 ret = -KVM_EPERM; 5991 goto out; 5992 } 5993 5994 switch (nr) { 5995 case KVM_HC_VAPIC_POLL_IRQ: 5996 ret = 0; 5997 break; 5998 case KVM_HC_KICK_CPU: 5999 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 6000 ret = 0; 6001 break; 6002 default: 6003 ret = -KVM_ENOSYS; 6004 break; 6005 } 6006 out: 6007 if (!op_64_bit) 6008 ret = (u32)ret; 6009 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 6010 ++vcpu->stat.hypercalls; 6011 return r; 6012 } 6013 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 6014 6015 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 6016 { 6017 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6018 char instruction[3]; 6019 unsigned long rip = kvm_rip_read(vcpu); 6020 6021 kvm_x86_ops->patch_hypercall(vcpu, instruction); 6022 6023 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); 6024 } 6025 6026 /* 6027 * Check if userspace requested an interrupt window, and that the 6028 * interrupt window is open. 6029 * 6030 * No need to exit to userspace if we already have an interrupt queued. 6031 */ 6032 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 6033 { 6034 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && 6035 vcpu->run->request_interrupt_window && 6036 kvm_arch_interrupt_allowed(vcpu)); 6037 } 6038 6039 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 6040 { 6041 struct kvm_run *kvm_run = vcpu->run; 6042 6043 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 6044 kvm_run->cr8 = kvm_get_cr8(vcpu); 6045 kvm_run->apic_base = kvm_get_apic_base(vcpu); 6046 if (irqchip_in_kernel(vcpu->kvm)) 6047 kvm_run->ready_for_interrupt_injection = 1; 6048 else 6049 kvm_run->ready_for_interrupt_injection = 6050 kvm_arch_interrupt_allowed(vcpu) && 6051 !kvm_cpu_has_interrupt(vcpu) && 6052 !kvm_event_needs_reinjection(vcpu); 6053 } 6054 6055 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 6056 { 6057 int max_irr, tpr; 6058 6059 if (!kvm_x86_ops->update_cr8_intercept) 6060 return; 6061 6062 if (!vcpu->arch.apic) 6063 return; 6064 6065 if (!vcpu->arch.apic->vapic_addr) 6066 max_irr = kvm_lapic_find_highest_irr(vcpu); 6067 else 6068 max_irr = -1; 6069 6070 if (max_irr != -1) 6071 max_irr >>= 4; 6072 6073 tpr = kvm_lapic_get_cr8(vcpu); 6074 6075 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 6076 } 6077 6078 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 6079 { 6080 int r; 6081 6082 /* try to reinject previous events if any */ 6083 if (vcpu->arch.exception.pending) { 6084 trace_kvm_inj_exception(vcpu->arch.exception.nr, 6085 vcpu->arch.exception.has_error_code, 6086 vcpu->arch.exception.error_code); 6087 6088 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 6089 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 6090 X86_EFLAGS_RF); 6091 6092 if (vcpu->arch.exception.nr == DB_VECTOR && 6093 (vcpu->arch.dr7 & DR7_GD)) { 6094 vcpu->arch.dr7 &= ~DR7_GD; 6095 kvm_update_dr7(vcpu); 6096 } 6097 6098 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, 6099 vcpu->arch.exception.has_error_code, 6100 vcpu->arch.exception.error_code, 6101 vcpu->arch.exception.reinject); 6102 return 0; 6103 } 6104 6105 if (vcpu->arch.nmi_injected) { 6106 kvm_x86_ops->set_nmi(vcpu); 6107 return 0; 6108 } 6109 6110 if (vcpu->arch.interrupt.pending) { 6111 kvm_x86_ops->set_irq(vcpu); 6112 return 0; 6113 } 6114 6115 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6116 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6117 if (r != 0) 6118 return r; 6119 } 6120 6121 /* try to inject new event if pending */ 6122 if (vcpu->arch.nmi_pending) { 6123 if (kvm_x86_ops->nmi_allowed(vcpu)) { 6124 --vcpu->arch.nmi_pending; 6125 vcpu->arch.nmi_injected = true; 6126 kvm_x86_ops->set_nmi(vcpu); 6127 } 6128 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 6129 /* 6130 * Because interrupts can be injected asynchronously, we are 6131 * calling check_nested_events again here to avoid a race condition. 6132 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 6133 * proposal and current concerns. Perhaps we should be setting 6134 * KVM_REQ_EVENT only on certain events and not unconditionally? 6135 */ 6136 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6137 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6138 if (r != 0) 6139 return r; 6140 } 6141 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 6142 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 6143 false); 6144 kvm_x86_ops->set_irq(vcpu); 6145 } 6146 } 6147 return 0; 6148 } 6149 6150 static void process_nmi(struct kvm_vcpu *vcpu) 6151 { 6152 unsigned limit = 2; 6153 6154 /* 6155 * x86 is limited to one NMI running, and one NMI pending after it. 6156 * If an NMI is already in progress, limit further NMIs to just one. 6157 * Otherwise, allow two (and we'll inject the first one immediately). 6158 */ 6159 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 6160 limit = 1; 6161 6162 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 6163 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 6164 kvm_make_request(KVM_REQ_EVENT, vcpu); 6165 } 6166 6167 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 6168 { 6169 u64 eoi_exit_bitmap[4]; 6170 u32 tmr[8]; 6171 6172 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 6173 return; 6174 6175 memset(eoi_exit_bitmap, 0, 32); 6176 memset(tmr, 0, 32); 6177 6178 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr); 6179 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 6180 kvm_apic_update_tmr(vcpu, tmr); 6181 } 6182 6183 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) 6184 { 6185 ++vcpu->stat.tlb_flush; 6186 kvm_x86_ops->tlb_flush(vcpu); 6187 } 6188 6189 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 6190 { 6191 struct page *page = NULL; 6192 6193 if (!irqchip_in_kernel(vcpu->kvm)) 6194 return; 6195 6196 if (!kvm_x86_ops->set_apic_access_page_addr) 6197 return; 6198 6199 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 6200 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 6201 6202 /* 6203 * Do not pin apic access page in memory, the MMU notifier 6204 * will call us again if it is migrated or swapped out. 6205 */ 6206 put_page(page); 6207 } 6208 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 6209 6210 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, 6211 unsigned long address) 6212 { 6213 /* 6214 * The physical address of apic access page is stored in the VMCS. 6215 * Update it when it becomes invalid. 6216 */ 6217 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT)) 6218 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 6219 } 6220 6221 /* 6222 * Returns 1 to let vcpu_run() continue the guest execution loop without 6223 * exiting to the userspace. Otherwise, the value will be returned to the 6224 * userspace. 6225 */ 6226 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 6227 { 6228 int r; 6229 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && 6230 vcpu->run->request_interrupt_window; 6231 bool req_immediate_exit = false; 6232 6233 if (vcpu->requests) { 6234 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 6235 kvm_mmu_unload(vcpu); 6236 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 6237 __kvm_migrate_timers(vcpu); 6238 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 6239 kvm_gen_update_masterclock(vcpu->kvm); 6240 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 6241 kvm_gen_kvmclock_update(vcpu); 6242 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 6243 r = kvm_guest_time_update(vcpu); 6244 if (unlikely(r)) 6245 goto out; 6246 } 6247 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 6248 kvm_mmu_sync_roots(vcpu); 6249 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 6250 kvm_vcpu_flush_tlb(vcpu); 6251 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 6252 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 6253 r = 0; 6254 goto out; 6255 } 6256 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 6257 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 6258 r = 0; 6259 goto out; 6260 } 6261 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { 6262 vcpu->fpu_active = 0; 6263 kvm_x86_ops->fpu_deactivate(vcpu); 6264 } 6265 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 6266 /* Page is swapped out. Do synthetic halt */ 6267 vcpu->arch.apf.halted = true; 6268 r = 1; 6269 goto out; 6270 } 6271 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 6272 record_steal_time(vcpu); 6273 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 6274 process_nmi(vcpu); 6275 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 6276 kvm_handle_pmu_event(vcpu); 6277 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 6278 kvm_deliver_pmi(vcpu); 6279 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 6280 vcpu_scan_ioapic(vcpu); 6281 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 6282 kvm_vcpu_reload_apic_access_page(vcpu); 6283 } 6284 6285 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 6286 kvm_apic_accept_events(vcpu); 6287 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 6288 r = 1; 6289 goto out; 6290 } 6291 6292 if (inject_pending_event(vcpu, req_int_win) != 0) 6293 req_immediate_exit = true; 6294 /* enable NMI/IRQ window open exits if needed */ 6295 else if (vcpu->arch.nmi_pending) 6296 kvm_x86_ops->enable_nmi_window(vcpu); 6297 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 6298 kvm_x86_ops->enable_irq_window(vcpu); 6299 6300 if (kvm_lapic_enabled(vcpu)) { 6301 /* 6302 * Update architecture specific hints for APIC 6303 * virtual interrupt delivery. 6304 */ 6305 if (kvm_x86_ops->hwapic_irr_update) 6306 kvm_x86_ops->hwapic_irr_update(vcpu, 6307 kvm_lapic_find_highest_irr(vcpu)); 6308 update_cr8_intercept(vcpu); 6309 kvm_lapic_sync_to_vapic(vcpu); 6310 } 6311 } 6312 6313 r = kvm_mmu_reload(vcpu); 6314 if (unlikely(r)) { 6315 goto cancel_injection; 6316 } 6317 6318 preempt_disable(); 6319 6320 kvm_x86_ops->prepare_guest_switch(vcpu); 6321 if (vcpu->fpu_active) 6322 kvm_load_guest_fpu(vcpu); 6323 kvm_load_guest_xcr0(vcpu); 6324 6325 vcpu->mode = IN_GUEST_MODE; 6326 6327 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6328 6329 /* We should set ->mode before check ->requests, 6330 * see the comment in make_all_cpus_request. 6331 */ 6332 smp_mb__after_srcu_read_unlock(); 6333 6334 local_irq_disable(); 6335 6336 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests 6337 || need_resched() || signal_pending(current)) { 6338 vcpu->mode = OUTSIDE_GUEST_MODE; 6339 smp_wmb(); 6340 local_irq_enable(); 6341 preempt_enable(); 6342 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6343 r = 1; 6344 goto cancel_injection; 6345 } 6346 6347 if (req_immediate_exit) 6348 smp_send_reschedule(vcpu->cpu); 6349 6350 kvm_guest_enter(); 6351 6352 if (unlikely(vcpu->arch.switch_db_regs)) { 6353 set_debugreg(0, 7); 6354 set_debugreg(vcpu->arch.eff_db[0], 0); 6355 set_debugreg(vcpu->arch.eff_db[1], 1); 6356 set_debugreg(vcpu->arch.eff_db[2], 2); 6357 set_debugreg(vcpu->arch.eff_db[3], 3); 6358 set_debugreg(vcpu->arch.dr6, 6); 6359 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 6360 } 6361 6362 trace_kvm_entry(vcpu->vcpu_id); 6363 wait_lapic_expire(vcpu); 6364 kvm_x86_ops->run(vcpu); 6365 6366 /* 6367 * Do this here before restoring debug registers on the host. And 6368 * since we do this before handling the vmexit, a DR access vmexit 6369 * can (a) read the correct value of the debug registers, (b) set 6370 * KVM_DEBUGREG_WONT_EXIT again. 6371 */ 6372 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 6373 int i; 6374 6375 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 6376 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 6377 for (i = 0; i < KVM_NR_DB_REGS; i++) 6378 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 6379 } 6380 6381 /* 6382 * If the guest has used debug registers, at least dr7 6383 * will be disabled while returning to the host. 6384 * If we don't have active breakpoints in the host, we don't 6385 * care about the messed up debug address registers. But if 6386 * we have some of them active, restore the old state. 6387 */ 6388 if (hw_breakpoint_active()) 6389 hw_breakpoint_restore(); 6390 6391 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, 6392 native_read_tsc()); 6393 6394 vcpu->mode = OUTSIDE_GUEST_MODE; 6395 smp_wmb(); 6396 6397 /* Interrupt is enabled by handle_external_intr() */ 6398 kvm_x86_ops->handle_external_intr(vcpu); 6399 6400 ++vcpu->stat.exits; 6401 6402 /* 6403 * We must have an instruction between local_irq_enable() and 6404 * kvm_guest_exit(), so the timer interrupt isn't delayed by 6405 * the interrupt shadow. The stat.exits increment will do nicely. 6406 * But we need to prevent reordering, hence this barrier(): 6407 */ 6408 barrier(); 6409 6410 kvm_guest_exit(); 6411 6412 preempt_enable(); 6413 6414 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6415 6416 /* 6417 * Profile KVM exit RIPs: 6418 */ 6419 if (unlikely(prof_on == KVM_PROFILING)) { 6420 unsigned long rip = kvm_rip_read(vcpu); 6421 profile_hit(KVM_PROFILING, (void *)rip); 6422 } 6423 6424 if (unlikely(vcpu->arch.tsc_always_catchup)) 6425 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6426 6427 if (vcpu->arch.apic_attention) 6428 kvm_lapic_sync_from_vapic(vcpu); 6429 6430 r = kvm_x86_ops->handle_exit(vcpu); 6431 return r; 6432 6433 cancel_injection: 6434 kvm_x86_ops->cancel_injection(vcpu); 6435 if (unlikely(vcpu->arch.apic_attention)) 6436 kvm_lapic_sync_from_vapic(vcpu); 6437 out: 6438 return r; 6439 } 6440 6441 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 6442 { 6443 if (!kvm_arch_vcpu_runnable(vcpu)) { 6444 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6445 kvm_vcpu_block(vcpu); 6446 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6447 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 6448 return 1; 6449 } 6450 6451 kvm_apic_accept_events(vcpu); 6452 switch(vcpu->arch.mp_state) { 6453 case KVM_MP_STATE_HALTED: 6454 vcpu->arch.pv.pv_unhalted = false; 6455 vcpu->arch.mp_state = 6456 KVM_MP_STATE_RUNNABLE; 6457 case KVM_MP_STATE_RUNNABLE: 6458 vcpu->arch.apf.halted = false; 6459 break; 6460 case KVM_MP_STATE_INIT_RECEIVED: 6461 break; 6462 default: 6463 return -EINTR; 6464 break; 6465 } 6466 return 1; 6467 } 6468 6469 static int vcpu_run(struct kvm_vcpu *vcpu) 6470 { 6471 int r; 6472 struct kvm *kvm = vcpu->kvm; 6473 6474 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6475 6476 for (;;) { 6477 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 6478 !vcpu->arch.apf.halted) 6479 r = vcpu_enter_guest(vcpu); 6480 else 6481 r = vcpu_block(kvm, vcpu); 6482 if (r <= 0) 6483 break; 6484 6485 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); 6486 if (kvm_cpu_has_pending_timer(vcpu)) 6487 kvm_inject_pending_timer_irqs(vcpu); 6488 6489 if (dm_request_for_irq_injection(vcpu)) { 6490 r = -EINTR; 6491 vcpu->run->exit_reason = KVM_EXIT_INTR; 6492 ++vcpu->stat.request_irq_exits; 6493 break; 6494 } 6495 6496 kvm_check_async_pf_completion(vcpu); 6497 6498 if (signal_pending(current)) { 6499 r = -EINTR; 6500 vcpu->run->exit_reason = KVM_EXIT_INTR; 6501 ++vcpu->stat.signal_exits; 6502 break; 6503 } 6504 if (need_resched()) { 6505 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6506 cond_resched(); 6507 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6508 } 6509 } 6510 6511 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6512 6513 return r; 6514 } 6515 6516 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 6517 { 6518 int r; 6519 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6520 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 6521 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6522 if (r != EMULATE_DONE) 6523 return 0; 6524 return 1; 6525 } 6526 6527 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 6528 { 6529 BUG_ON(!vcpu->arch.pio.count); 6530 6531 return complete_emulated_io(vcpu); 6532 } 6533 6534 /* 6535 * Implements the following, as a state machine: 6536 * 6537 * read: 6538 * for each fragment 6539 * for each mmio piece in the fragment 6540 * write gpa, len 6541 * exit 6542 * copy data 6543 * execute insn 6544 * 6545 * write: 6546 * for each fragment 6547 * for each mmio piece in the fragment 6548 * write gpa, len 6549 * copy data 6550 * exit 6551 */ 6552 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 6553 { 6554 struct kvm_run *run = vcpu->run; 6555 struct kvm_mmio_fragment *frag; 6556 unsigned len; 6557 6558 BUG_ON(!vcpu->mmio_needed); 6559 6560 /* Complete previous fragment */ 6561 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 6562 len = min(8u, frag->len); 6563 if (!vcpu->mmio_is_write) 6564 memcpy(frag->data, run->mmio.data, len); 6565 6566 if (frag->len <= 8) { 6567 /* Switch to the next fragment. */ 6568 frag++; 6569 vcpu->mmio_cur_fragment++; 6570 } else { 6571 /* Go forward to the next mmio piece. */ 6572 frag->data += len; 6573 frag->gpa += len; 6574 frag->len -= len; 6575 } 6576 6577 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 6578 vcpu->mmio_needed = 0; 6579 6580 /* FIXME: return into emulator if single-stepping. */ 6581 if (vcpu->mmio_is_write) 6582 return 1; 6583 vcpu->mmio_read_completed = 1; 6584 return complete_emulated_io(vcpu); 6585 } 6586 6587 run->exit_reason = KVM_EXIT_MMIO; 6588 run->mmio.phys_addr = frag->gpa; 6589 if (vcpu->mmio_is_write) 6590 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 6591 run->mmio.len = min(8u, frag->len); 6592 run->mmio.is_write = vcpu->mmio_is_write; 6593 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6594 return 0; 6595 } 6596 6597 6598 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 6599 { 6600 int r; 6601 sigset_t sigsaved; 6602 6603 if (!tsk_used_math(current) && init_fpu(current)) 6604 return -ENOMEM; 6605 6606 if (vcpu->sigset_active) 6607 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); 6608 6609 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 6610 kvm_vcpu_block(vcpu); 6611 kvm_apic_accept_events(vcpu); 6612 clear_bit(KVM_REQ_UNHALT, &vcpu->requests); 6613 r = -EAGAIN; 6614 goto out; 6615 } 6616 6617 /* re-sync apic's tpr */ 6618 if (!irqchip_in_kernel(vcpu->kvm)) { 6619 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 6620 r = -EINVAL; 6621 goto out; 6622 } 6623 } 6624 6625 if (unlikely(vcpu->arch.complete_userspace_io)) { 6626 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 6627 vcpu->arch.complete_userspace_io = NULL; 6628 r = cui(vcpu); 6629 if (r <= 0) 6630 goto out; 6631 } else 6632 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 6633 6634 r = vcpu_run(vcpu); 6635 6636 out: 6637 post_kvm_run_save(vcpu); 6638 if (vcpu->sigset_active) 6639 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 6640 6641 return r; 6642 } 6643 6644 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6645 { 6646 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 6647 /* 6648 * We are here if userspace calls get_regs() in the middle of 6649 * instruction emulation. Registers state needs to be copied 6650 * back from emulation context to vcpu. Userspace shouldn't do 6651 * that usually, but some bad designed PV devices (vmware 6652 * backdoor interface) need this to work 6653 */ 6654 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 6655 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6656 } 6657 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 6658 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 6659 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 6660 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 6661 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 6662 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 6663 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 6664 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 6665 #ifdef CONFIG_X86_64 6666 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 6667 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 6668 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 6669 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 6670 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 6671 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 6672 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 6673 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 6674 #endif 6675 6676 regs->rip = kvm_rip_read(vcpu); 6677 regs->rflags = kvm_get_rflags(vcpu); 6678 6679 return 0; 6680 } 6681 6682 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6683 { 6684 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 6685 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6686 6687 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 6688 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 6689 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 6690 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 6691 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 6692 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 6693 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 6694 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 6695 #ifdef CONFIG_X86_64 6696 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 6697 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 6698 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 6699 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 6700 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 6701 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 6702 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 6703 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 6704 #endif 6705 6706 kvm_rip_write(vcpu, regs->rip); 6707 kvm_set_rflags(vcpu, regs->rflags); 6708 6709 vcpu->arch.exception.pending = false; 6710 6711 kvm_make_request(KVM_REQ_EVENT, vcpu); 6712 6713 return 0; 6714 } 6715 6716 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 6717 { 6718 struct kvm_segment cs; 6719 6720 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 6721 *db = cs.db; 6722 *l = cs.l; 6723 } 6724 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 6725 6726 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 6727 struct kvm_sregs *sregs) 6728 { 6729 struct desc_ptr dt; 6730 6731 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 6732 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 6733 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 6734 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 6735 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 6736 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 6737 6738 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 6739 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 6740 6741 kvm_x86_ops->get_idt(vcpu, &dt); 6742 sregs->idt.limit = dt.size; 6743 sregs->idt.base = dt.address; 6744 kvm_x86_ops->get_gdt(vcpu, &dt); 6745 sregs->gdt.limit = dt.size; 6746 sregs->gdt.base = dt.address; 6747 6748 sregs->cr0 = kvm_read_cr0(vcpu); 6749 sregs->cr2 = vcpu->arch.cr2; 6750 sregs->cr3 = kvm_read_cr3(vcpu); 6751 sregs->cr4 = kvm_read_cr4(vcpu); 6752 sregs->cr8 = kvm_get_cr8(vcpu); 6753 sregs->efer = vcpu->arch.efer; 6754 sregs->apic_base = kvm_get_apic_base(vcpu); 6755 6756 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 6757 6758 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) 6759 set_bit(vcpu->arch.interrupt.nr, 6760 (unsigned long *)sregs->interrupt_bitmap); 6761 6762 return 0; 6763 } 6764 6765 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 6766 struct kvm_mp_state *mp_state) 6767 { 6768 kvm_apic_accept_events(vcpu); 6769 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 6770 vcpu->arch.pv.pv_unhalted) 6771 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 6772 else 6773 mp_state->mp_state = vcpu->arch.mp_state; 6774 6775 return 0; 6776 } 6777 6778 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 6779 struct kvm_mp_state *mp_state) 6780 { 6781 if (!kvm_vcpu_has_lapic(vcpu) && 6782 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 6783 return -EINVAL; 6784 6785 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 6786 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 6787 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 6788 } else 6789 vcpu->arch.mp_state = mp_state->mp_state; 6790 kvm_make_request(KVM_REQ_EVENT, vcpu); 6791 return 0; 6792 } 6793 6794 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 6795 int reason, bool has_error_code, u32 error_code) 6796 { 6797 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6798 int ret; 6799 6800 init_emulate_ctxt(vcpu); 6801 6802 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 6803 has_error_code, error_code); 6804 6805 if (ret) 6806 return EMULATE_FAIL; 6807 6808 kvm_rip_write(vcpu, ctxt->eip); 6809 kvm_set_rflags(vcpu, ctxt->eflags); 6810 kvm_make_request(KVM_REQ_EVENT, vcpu); 6811 return EMULATE_DONE; 6812 } 6813 EXPORT_SYMBOL_GPL(kvm_task_switch); 6814 6815 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 6816 struct kvm_sregs *sregs) 6817 { 6818 struct msr_data apic_base_msr; 6819 int mmu_reset_needed = 0; 6820 int pending_vec, max_bits, idx; 6821 struct desc_ptr dt; 6822 6823 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) 6824 return -EINVAL; 6825 6826 dt.size = sregs->idt.limit; 6827 dt.address = sregs->idt.base; 6828 kvm_x86_ops->set_idt(vcpu, &dt); 6829 dt.size = sregs->gdt.limit; 6830 dt.address = sregs->gdt.base; 6831 kvm_x86_ops->set_gdt(vcpu, &dt); 6832 6833 vcpu->arch.cr2 = sregs->cr2; 6834 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 6835 vcpu->arch.cr3 = sregs->cr3; 6836 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 6837 6838 kvm_set_cr8(vcpu, sregs->cr8); 6839 6840 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 6841 kvm_x86_ops->set_efer(vcpu, sregs->efer); 6842 apic_base_msr.data = sregs->apic_base; 6843 apic_base_msr.host_initiated = true; 6844 kvm_set_apic_base(vcpu, &apic_base_msr); 6845 6846 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 6847 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 6848 vcpu->arch.cr0 = sregs->cr0; 6849 6850 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 6851 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 6852 if (sregs->cr4 & X86_CR4_OSXSAVE) 6853 kvm_update_cpuid(vcpu); 6854 6855 idx = srcu_read_lock(&vcpu->kvm->srcu); 6856 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 6857 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 6858 mmu_reset_needed = 1; 6859 } 6860 srcu_read_unlock(&vcpu->kvm->srcu, idx); 6861 6862 if (mmu_reset_needed) 6863 kvm_mmu_reset_context(vcpu); 6864 6865 max_bits = KVM_NR_INTERRUPTS; 6866 pending_vec = find_first_bit( 6867 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 6868 if (pending_vec < max_bits) { 6869 kvm_queue_interrupt(vcpu, pending_vec, false); 6870 pr_debug("Set back pending irq %d\n", pending_vec); 6871 } 6872 6873 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 6874 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 6875 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 6876 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 6877 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 6878 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 6879 6880 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 6881 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 6882 6883 update_cr8_intercept(vcpu); 6884 6885 /* Older userspace won't unhalt the vcpu on reset. */ 6886 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 6887 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 6888 !is_protmode(vcpu)) 6889 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 6890 6891 kvm_make_request(KVM_REQ_EVENT, vcpu); 6892 6893 return 0; 6894 } 6895 6896 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 6897 struct kvm_guest_debug *dbg) 6898 { 6899 unsigned long rflags; 6900 int i, r; 6901 6902 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 6903 r = -EBUSY; 6904 if (vcpu->arch.exception.pending) 6905 goto out; 6906 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 6907 kvm_queue_exception(vcpu, DB_VECTOR); 6908 else 6909 kvm_queue_exception(vcpu, BP_VECTOR); 6910 } 6911 6912 /* 6913 * Read rflags as long as potentially injected trace flags are still 6914 * filtered out. 6915 */ 6916 rflags = kvm_get_rflags(vcpu); 6917 6918 vcpu->guest_debug = dbg->control; 6919 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 6920 vcpu->guest_debug = 0; 6921 6922 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 6923 for (i = 0; i < KVM_NR_DB_REGS; ++i) 6924 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 6925 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 6926 } else { 6927 for (i = 0; i < KVM_NR_DB_REGS; i++) 6928 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 6929 } 6930 kvm_update_dr7(vcpu); 6931 6932 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6933 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 6934 get_segment_base(vcpu, VCPU_SREG_CS); 6935 6936 /* 6937 * Trigger an rflags update that will inject or remove the trace 6938 * flags. 6939 */ 6940 kvm_set_rflags(vcpu, rflags); 6941 6942 kvm_x86_ops->update_db_bp_intercept(vcpu); 6943 6944 r = 0; 6945 6946 out: 6947 6948 return r; 6949 } 6950 6951 /* 6952 * Translate a guest virtual address to a guest physical address. 6953 */ 6954 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 6955 struct kvm_translation *tr) 6956 { 6957 unsigned long vaddr = tr->linear_address; 6958 gpa_t gpa; 6959 int idx; 6960 6961 idx = srcu_read_lock(&vcpu->kvm->srcu); 6962 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 6963 srcu_read_unlock(&vcpu->kvm->srcu, idx); 6964 tr->physical_address = gpa; 6965 tr->valid = gpa != UNMAPPED_GVA; 6966 tr->writeable = 1; 6967 tr->usermode = 0; 6968 6969 return 0; 6970 } 6971 6972 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 6973 { 6974 struct i387_fxsave_struct *fxsave = 6975 &vcpu->arch.guest_fpu.state->fxsave; 6976 6977 memcpy(fpu->fpr, fxsave->st_space, 128); 6978 fpu->fcw = fxsave->cwd; 6979 fpu->fsw = fxsave->swd; 6980 fpu->ftwx = fxsave->twd; 6981 fpu->last_opcode = fxsave->fop; 6982 fpu->last_ip = fxsave->rip; 6983 fpu->last_dp = fxsave->rdp; 6984 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 6985 6986 return 0; 6987 } 6988 6989 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 6990 { 6991 struct i387_fxsave_struct *fxsave = 6992 &vcpu->arch.guest_fpu.state->fxsave; 6993 6994 memcpy(fxsave->st_space, fpu->fpr, 128); 6995 fxsave->cwd = fpu->fcw; 6996 fxsave->swd = fpu->fsw; 6997 fxsave->twd = fpu->ftwx; 6998 fxsave->fop = fpu->last_opcode; 6999 fxsave->rip = fpu->last_ip; 7000 fxsave->rdp = fpu->last_dp; 7001 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 7002 7003 return 0; 7004 } 7005 7006 int fx_init(struct kvm_vcpu *vcpu) 7007 { 7008 int err; 7009 7010 err = fpu_alloc(&vcpu->arch.guest_fpu); 7011 if (err) 7012 return err; 7013 7014 fpu_finit(&vcpu->arch.guest_fpu); 7015 if (cpu_has_xsaves) 7016 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv = 7017 host_xcr0 | XSTATE_COMPACTION_ENABLED; 7018 7019 /* 7020 * Ensure guest xcr0 is valid for loading 7021 */ 7022 vcpu->arch.xcr0 = XSTATE_FP; 7023 7024 vcpu->arch.cr0 |= X86_CR0_ET; 7025 7026 return 0; 7027 } 7028 EXPORT_SYMBOL_GPL(fx_init); 7029 7030 static void fx_free(struct kvm_vcpu *vcpu) 7031 { 7032 fpu_free(&vcpu->arch.guest_fpu); 7033 } 7034 7035 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 7036 { 7037 if (vcpu->guest_fpu_loaded) 7038 return; 7039 7040 /* 7041 * Restore all possible states in the guest, 7042 * and assume host would use all available bits. 7043 * Guest xcr0 would be loaded later. 7044 */ 7045 kvm_put_guest_xcr0(vcpu); 7046 vcpu->guest_fpu_loaded = 1; 7047 __kernel_fpu_begin(); 7048 fpu_restore_checking(&vcpu->arch.guest_fpu); 7049 trace_kvm_fpu(1); 7050 } 7051 7052 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 7053 { 7054 kvm_put_guest_xcr0(vcpu); 7055 7056 if (!vcpu->guest_fpu_loaded) 7057 return; 7058 7059 vcpu->guest_fpu_loaded = 0; 7060 fpu_save_init(&vcpu->arch.guest_fpu); 7061 __kernel_fpu_end(); 7062 ++vcpu->stat.fpu_reload; 7063 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); 7064 trace_kvm_fpu(0); 7065 } 7066 7067 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 7068 { 7069 kvmclock_reset(vcpu); 7070 7071 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 7072 fx_free(vcpu); 7073 kvm_x86_ops->vcpu_free(vcpu); 7074 } 7075 7076 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 7077 unsigned int id) 7078 { 7079 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 7080 printk_once(KERN_WARNING 7081 "kvm: SMP vm created on host with unstable TSC; " 7082 "guest TSC will not be reliable\n"); 7083 return kvm_x86_ops->vcpu_create(kvm, id); 7084 } 7085 7086 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 7087 { 7088 int r; 7089 7090 vcpu->arch.mtrr_state.have_fixed = 1; 7091 r = vcpu_load(vcpu); 7092 if (r) 7093 return r; 7094 kvm_vcpu_reset(vcpu); 7095 kvm_mmu_setup(vcpu); 7096 vcpu_put(vcpu); 7097 7098 return r; 7099 } 7100 7101 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 7102 { 7103 struct msr_data msr; 7104 struct kvm *kvm = vcpu->kvm; 7105 7106 if (vcpu_load(vcpu)) 7107 return; 7108 msr.data = 0x0; 7109 msr.index = MSR_IA32_TSC; 7110 msr.host_initiated = true; 7111 kvm_write_tsc(vcpu, &msr); 7112 vcpu_put(vcpu); 7113 7114 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 7115 KVMCLOCK_SYNC_PERIOD); 7116 } 7117 7118 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 7119 { 7120 int r; 7121 vcpu->arch.apf.msr_val = 0; 7122 7123 r = vcpu_load(vcpu); 7124 BUG_ON(r); 7125 kvm_mmu_unload(vcpu); 7126 vcpu_put(vcpu); 7127 7128 fx_free(vcpu); 7129 kvm_x86_ops->vcpu_free(vcpu); 7130 } 7131 7132 void kvm_vcpu_reset(struct kvm_vcpu *vcpu) 7133 { 7134 atomic_set(&vcpu->arch.nmi_queued, 0); 7135 vcpu->arch.nmi_pending = 0; 7136 vcpu->arch.nmi_injected = false; 7137 kvm_clear_interrupt_queue(vcpu); 7138 kvm_clear_exception_queue(vcpu); 7139 7140 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 7141 kvm_update_dr0123(vcpu); 7142 vcpu->arch.dr6 = DR6_INIT; 7143 kvm_update_dr6(vcpu); 7144 vcpu->arch.dr7 = DR7_FIXED_1; 7145 kvm_update_dr7(vcpu); 7146 7147 vcpu->arch.cr2 = 0; 7148 7149 kvm_make_request(KVM_REQ_EVENT, vcpu); 7150 vcpu->arch.apf.msr_val = 0; 7151 vcpu->arch.st.msr_val = 0; 7152 7153 kvmclock_reset(vcpu); 7154 7155 kvm_clear_async_pf_completion_queue(vcpu); 7156 kvm_async_pf_hash_reset(vcpu); 7157 vcpu->arch.apf.halted = false; 7158 7159 kvm_pmu_reset(vcpu); 7160 7161 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 7162 vcpu->arch.regs_avail = ~0; 7163 vcpu->arch.regs_dirty = ~0; 7164 7165 kvm_x86_ops->vcpu_reset(vcpu); 7166 } 7167 7168 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 7169 { 7170 struct kvm_segment cs; 7171 7172 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7173 cs.selector = vector << 8; 7174 cs.base = vector << 12; 7175 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7176 kvm_rip_write(vcpu, 0); 7177 } 7178 7179 int kvm_arch_hardware_enable(void) 7180 { 7181 struct kvm *kvm; 7182 struct kvm_vcpu *vcpu; 7183 int i; 7184 int ret; 7185 u64 local_tsc; 7186 u64 max_tsc = 0; 7187 bool stable, backwards_tsc = false; 7188 7189 kvm_shared_msr_cpu_online(); 7190 ret = kvm_x86_ops->hardware_enable(); 7191 if (ret != 0) 7192 return ret; 7193 7194 local_tsc = native_read_tsc(); 7195 stable = !check_tsc_unstable(); 7196 list_for_each_entry(kvm, &vm_list, vm_list) { 7197 kvm_for_each_vcpu(i, vcpu, kvm) { 7198 if (!stable && vcpu->cpu == smp_processor_id()) 7199 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7200 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 7201 backwards_tsc = true; 7202 if (vcpu->arch.last_host_tsc > max_tsc) 7203 max_tsc = vcpu->arch.last_host_tsc; 7204 } 7205 } 7206 } 7207 7208 /* 7209 * Sometimes, even reliable TSCs go backwards. This happens on 7210 * platforms that reset TSC during suspend or hibernate actions, but 7211 * maintain synchronization. We must compensate. Fortunately, we can 7212 * detect that condition here, which happens early in CPU bringup, 7213 * before any KVM threads can be running. Unfortunately, we can't 7214 * bring the TSCs fully up to date with real time, as we aren't yet far 7215 * enough into CPU bringup that we know how much real time has actually 7216 * elapsed; our helper function, get_kernel_ns() will be using boot 7217 * variables that haven't been updated yet. 7218 * 7219 * So we simply find the maximum observed TSC above, then record the 7220 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 7221 * the adjustment will be applied. Note that we accumulate 7222 * adjustments, in case multiple suspend cycles happen before some VCPU 7223 * gets a chance to run again. In the event that no KVM threads get a 7224 * chance to run, we will miss the entire elapsed period, as we'll have 7225 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 7226 * loose cycle time. This isn't too big a deal, since the loss will be 7227 * uniform across all VCPUs (not to mention the scenario is extremely 7228 * unlikely). It is possible that a second hibernate recovery happens 7229 * much faster than a first, causing the observed TSC here to be 7230 * smaller; this would require additional padding adjustment, which is 7231 * why we set last_host_tsc to the local tsc observed here. 7232 * 7233 * N.B. - this code below runs only on platforms with reliable TSC, 7234 * as that is the only way backwards_tsc is set above. Also note 7235 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 7236 * have the same delta_cyc adjustment applied if backwards_tsc 7237 * is detected. Note further, this adjustment is only done once, 7238 * as we reset last_host_tsc on all VCPUs to stop this from being 7239 * called multiple times (one for each physical CPU bringup). 7240 * 7241 * Platforms with unreliable TSCs don't have to deal with this, they 7242 * will be compensated by the logic in vcpu_load, which sets the TSC to 7243 * catchup mode. This will catchup all VCPUs to real time, but cannot 7244 * guarantee that they stay in perfect synchronization. 7245 */ 7246 if (backwards_tsc) { 7247 u64 delta_cyc = max_tsc - local_tsc; 7248 backwards_tsc_observed = true; 7249 list_for_each_entry(kvm, &vm_list, vm_list) { 7250 kvm_for_each_vcpu(i, vcpu, kvm) { 7251 vcpu->arch.tsc_offset_adjustment += delta_cyc; 7252 vcpu->arch.last_host_tsc = local_tsc; 7253 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7254 } 7255 7256 /* 7257 * We have to disable TSC offset matching.. if you were 7258 * booting a VM while issuing an S4 host suspend.... 7259 * you may have some problem. Solving this issue is 7260 * left as an exercise to the reader. 7261 */ 7262 kvm->arch.last_tsc_nsec = 0; 7263 kvm->arch.last_tsc_write = 0; 7264 } 7265 7266 } 7267 return 0; 7268 } 7269 7270 void kvm_arch_hardware_disable(void) 7271 { 7272 kvm_x86_ops->hardware_disable(); 7273 drop_user_return_notifiers(); 7274 } 7275 7276 int kvm_arch_hardware_setup(void) 7277 { 7278 int r; 7279 7280 r = kvm_x86_ops->hardware_setup(); 7281 if (r != 0) 7282 return r; 7283 7284 kvm_init_msr_list(); 7285 return 0; 7286 } 7287 7288 void kvm_arch_hardware_unsetup(void) 7289 { 7290 kvm_x86_ops->hardware_unsetup(); 7291 } 7292 7293 void kvm_arch_check_processor_compat(void *rtn) 7294 { 7295 kvm_x86_ops->check_processor_compatibility(rtn); 7296 } 7297 7298 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) 7299 { 7300 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL); 7301 } 7302 7303 struct static_key kvm_no_apic_vcpu __read_mostly; 7304 7305 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 7306 { 7307 struct page *page; 7308 struct kvm *kvm; 7309 int r; 7310 7311 BUG_ON(vcpu->kvm == NULL); 7312 kvm = vcpu->kvm; 7313 7314 vcpu->arch.pv.pv_unhalted = false; 7315 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 7316 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 7317 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7318 else 7319 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 7320 7321 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 7322 if (!page) { 7323 r = -ENOMEM; 7324 goto fail; 7325 } 7326 vcpu->arch.pio_data = page_address(page); 7327 7328 kvm_set_tsc_khz(vcpu, max_tsc_khz); 7329 7330 r = kvm_mmu_create(vcpu); 7331 if (r < 0) 7332 goto fail_free_pio_data; 7333 7334 if (irqchip_in_kernel(kvm)) { 7335 r = kvm_create_lapic(vcpu); 7336 if (r < 0) 7337 goto fail_mmu_destroy; 7338 } else 7339 static_key_slow_inc(&kvm_no_apic_vcpu); 7340 7341 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 7342 GFP_KERNEL); 7343 if (!vcpu->arch.mce_banks) { 7344 r = -ENOMEM; 7345 goto fail_free_lapic; 7346 } 7347 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 7348 7349 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 7350 r = -ENOMEM; 7351 goto fail_free_mce_banks; 7352 } 7353 7354 r = fx_init(vcpu); 7355 if (r) 7356 goto fail_free_wbinvd_dirty_mask; 7357 7358 vcpu->arch.ia32_tsc_adjust_msr = 0x0; 7359 vcpu->arch.pv_time_enabled = false; 7360 7361 vcpu->arch.guest_supported_xcr0 = 0; 7362 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 7363 7364 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 7365 7366 kvm_async_pf_hash_reset(vcpu); 7367 kvm_pmu_init(vcpu); 7368 7369 return 0; 7370 fail_free_wbinvd_dirty_mask: 7371 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 7372 fail_free_mce_banks: 7373 kfree(vcpu->arch.mce_banks); 7374 fail_free_lapic: 7375 kvm_free_lapic(vcpu); 7376 fail_mmu_destroy: 7377 kvm_mmu_destroy(vcpu); 7378 fail_free_pio_data: 7379 free_page((unsigned long)vcpu->arch.pio_data); 7380 fail: 7381 return r; 7382 } 7383 7384 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 7385 { 7386 int idx; 7387 7388 kvm_pmu_destroy(vcpu); 7389 kfree(vcpu->arch.mce_banks); 7390 kvm_free_lapic(vcpu); 7391 idx = srcu_read_lock(&vcpu->kvm->srcu); 7392 kvm_mmu_destroy(vcpu); 7393 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7394 free_page((unsigned long)vcpu->arch.pio_data); 7395 if (!irqchip_in_kernel(vcpu->kvm)) 7396 static_key_slow_dec(&kvm_no_apic_vcpu); 7397 } 7398 7399 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 7400 { 7401 kvm_x86_ops->sched_in(vcpu, cpu); 7402 } 7403 7404 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 7405 { 7406 if (type) 7407 return -EINVAL; 7408 7409 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 7410 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 7411 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 7412 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 7413 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 7414 7415 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 7416 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 7417 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 7418 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 7419 &kvm->arch.irq_sources_bitmap); 7420 7421 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 7422 mutex_init(&kvm->arch.apic_map_lock); 7423 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 7424 7425 pvclock_update_vm_gtod_copy(kvm); 7426 7427 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 7428 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 7429 7430 return 0; 7431 } 7432 7433 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 7434 { 7435 int r; 7436 r = vcpu_load(vcpu); 7437 BUG_ON(r); 7438 kvm_mmu_unload(vcpu); 7439 vcpu_put(vcpu); 7440 } 7441 7442 static void kvm_free_vcpus(struct kvm *kvm) 7443 { 7444 unsigned int i; 7445 struct kvm_vcpu *vcpu; 7446 7447 /* 7448 * Unpin any mmu pages first. 7449 */ 7450 kvm_for_each_vcpu(i, vcpu, kvm) { 7451 kvm_clear_async_pf_completion_queue(vcpu); 7452 kvm_unload_vcpu_mmu(vcpu); 7453 } 7454 kvm_for_each_vcpu(i, vcpu, kvm) 7455 kvm_arch_vcpu_free(vcpu); 7456 7457 mutex_lock(&kvm->lock); 7458 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 7459 kvm->vcpus[i] = NULL; 7460 7461 atomic_set(&kvm->online_vcpus, 0); 7462 mutex_unlock(&kvm->lock); 7463 } 7464 7465 void kvm_arch_sync_events(struct kvm *kvm) 7466 { 7467 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 7468 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 7469 kvm_free_all_assigned_devices(kvm); 7470 kvm_free_pit(kvm); 7471 } 7472 7473 void kvm_arch_destroy_vm(struct kvm *kvm) 7474 { 7475 if (current->mm == kvm->mm) { 7476 /* 7477 * Free memory regions allocated on behalf of userspace, 7478 * unless the the memory map has changed due to process exit 7479 * or fd copying. 7480 */ 7481 struct kvm_userspace_memory_region mem; 7482 memset(&mem, 0, sizeof(mem)); 7483 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; 7484 kvm_set_memory_region(kvm, &mem); 7485 7486 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; 7487 kvm_set_memory_region(kvm, &mem); 7488 7489 mem.slot = TSS_PRIVATE_MEMSLOT; 7490 kvm_set_memory_region(kvm, &mem); 7491 } 7492 kvm_iommu_unmap_guest(kvm); 7493 kfree(kvm->arch.vpic); 7494 kfree(kvm->arch.vioapic); 7495 kvm_free_vcpus(kvm); 7496 kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 7497 } 7498 7499 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 7500 struct kvm_memory_slot *dont) 7501 { 7502 int i; 7503 7504 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7505 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 7506 kvfree(free->arch.rmap[i]); 7507 free->arch.rmap[i] = NULL; 7508 } 7509 if (i == 0) 7510 continue; 7511 7512 if (!dont || free->arch.lpage_info[i - 1] != 7513 dont->arch.lpage_info[i - 1]) { 7514 kvfree(free->arch.lpage_info[i - 1]); 7515 free->arch.lpage_info[i - 1] = NULL; 7516 } 7517 } 7518 } 7519 7520 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 7521 unsigned long npages) 7522 { 7523 int i; 7524 7525 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7526 unsigned long ugfn; 7527 int lpages; 7528 int level = i + 1; 7529 7530 lpages = gfn_to_index(slot->base_gfn + npages - 1, 7531 slot->base_gfn, level) + 1; 7532 7533 slot->arch.rmap[i] = 7534 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); 7535 if (!slot->arch.rmap[i]) 7536 goto out_free; 7537 if (i == 0) 7538 continue; 7539 7540 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages * 7541 sizeof(*slot->arch.lpage_info[i - 1])); 7542 if (!slot->arch.lpage_info[i - 1]) 7543 goto out_free; 7544 7545 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 7546 slot->arch.lpage_info[i - 1][0].write_count = 1; 7547 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 7548 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1; 7549 ugfn = slot->userspace_addr >> PAGE_SHIFT; 7550 /* 7551 * If the gfn and userspace address are not aligned wrt each 7552 * other, or if explicitly asked to, disable large page 7553 * support for this slot 7554 */ 7555 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 7556 !kvm_largepages_enabled()) { 7557 unsigned long j; 7558 7559 for (j = 0; j < lpages; ++j) 7560 slot->arch.lpage_info[i - 1][j].write_count = 1; 7561 } 7562 } 7563 7564 return 0; 7565 7566 out_free: 7567 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7568 kvfree(slot->arch.rmap[i]); 7569 slot->arch.rmap[i] = NULL; 7570 if (i == 0) 7571 continue; 7572 7573 kvfree(slot->arch.lpage_info[i - 1]); 7574 slot->arch.lpage_info[i - 1] = NULL; 7575 } 7576 return -ENOMEM; 7577 } 7578 7579 void kvm_arch_memslots_updated(struct kvm *kvm) 7580 { 7581 /* 7582 * memslots->generation has been incremented. 7583 * mmio generation may have reached its maximum value. 7584 */ 7585 kvm_mmu_invalidate_mmio_sptes(kvm); 7586 } 7587 7588 int kvm_arch_prepare_memory_region(struct kvm *kvm, 7589 struct kvm_memory_slot *memslot, 7590 struct kvm_userspace_memory_region *mem, 7591 enum kvm_mr_change change) 7592 { 7593 /* 7594 * Only private memory slots need to be mapped here since 7595 * KVM_SET_MEMORY_REGION ioctl is no longer supported. 7596 */ 7597 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) { 7598 unsigned long userspace_addr; 7599 7600 /* 7601 * MAP_SHARED to prevent internal slot pages from being moved 7602 * by fork()/COW. 7603 */ 7604 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE, 7605 PROT_READ | PROT_WRITE, 7606 MAP_SHARED | MAP_ANONYMOUS, 0); 7607 7608 if (IS_ERR((void *)userspace_addr)) 7609 return PTR_ERR((void *)userspace_addr); 7610 7611 memslot->userspace_addr = userspace_addr; 7612 } 7613 7614 return 0; 7615 } 7616 7617 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 7618 struct kvm_memory_slot *new) 7619 { 7620 /* Still write protect RO slot */ 7621 if (new->flags & KVM_MEM_READONLY) { 7622 kvm_mmu_slot_remove_write_access(kvm, new); 7623 return; 7624 } 7625 7626 /* 7627 * Call kvm_x86_ops dirty logging hooks when they are valid. 7628 * 7629 * kvm_x86_ops->slot_disable_log_dirty is called when: 7630 * 7631 * - KVM_MR_CREATE with dirty logging is disabled 7632 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 7633 * 7634 * The reason is, in case of PML, we need to set D-bit for any slots 7635 * with dirty logging disabled in order to eliminate unnecessary GPA 7636 * logging in PML buffer (and potential PML buffer full VMEXT). This 7637 * guarantees leaving PML enabled during guest's lifetime won't have 7638 * any additonal overhead from PML when guest is running with dirty 7639 * logging disabled for memory slots. 7640 * 7641 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 7642 * to dirty logging mode. 7643 * 7644 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 7645 * 7646 * In case of write protect: 7647 * 7648 * Write protect all pages for dirty logging. 7649 * 7650 * All the sptes including the large sptes which point to this 7651 * slot are set to readonly. We can not create any new large 7652 * spte on this slot until the end of the logging. 7653 * 7654 * See the comments in fast_page_fault(). 7655 */ 7656 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 7657 if (kvm_x86_ops->slot_enable_log_dirty) 7658 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 7659 else 7660 kvm_mmu_slot_remove_write_access(kvm, new); 7661 } else { 7662 if (kvm_x86_ops->slot_disable_log_dirty) 7663 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 7664 } 7665 } 7666 7667 void kvm_arch_commit_memory_region(struct kvm *kvm, 7668 struct kvm_userspace_memory_region *mem, 7669 const struct kvm_memory_slot *old, 7670 enum kvm_mr_change change) 7671 { 7672 struct kvm_memory_slot *new; 7673 int nr_mmu_pages = 0; 7674 7675 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) { 7676 int ret; 7677 7678 ret = vm_munmap(old->userspace_addr, 7679 old->npages * PAGE_SIZE); 7680 if (ret < 0) 7681 printk(KERN_WARNING 7682 "kvm_vm_ioctl_set_memory_region: " 7683 "failed to munmap memory\n"); 7684 } 7685 7686 if (!kvm->arch.n_requested_mmu_pages) 7687 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 7688 7689 if (nr_mmu_pages) 7690 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 7691 7692 /* It's OK to get 'new' slot here as it has already been installed */ 7693 new = id_to_memslot(kvm->memslots, mem->slot); 7694 7695 /* 7696 * Dirty logging tracks sptes in 4k granularity, meaning that large 7697 * sptes have to be split. If live migration is successful, the guest 7698 * in the source machine will be destroyed and large sptes will be 7699 * created in the destination. However, if the guest continues to run 7700 * in the source machine (for example if live migration fails), small 7701 * sptes will remain around and cause bad performance. 7702 * 7703 * Scan sptes if dirty logging has been stopped, dropping those 7704 * which can be collapsed into a single large-page spte. Later 7705 * page faults will create the large-page sptes. 7706 */ 7707 if ((change != KVM_MR_DELETE) && 7708 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 7709 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 7710 kvm_mmu_zap_collapsible_sptes(kvm, new); 7711 7712 /* 7713 * Set up write protection and/or dirty logging for the new slot. 7714 * 7715 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 7716 * been zapped so no dirty logging staff is needed for old slot. For 7717 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 7718 * new and it's also covered when dealing with the new slot. 7719 */ 7720 if (change != KVM_MR_DELETE) 7721 kvm_mmu_slot_apply_flags(kvm, new); 7722 } 7723 7724 void kvm_arch_flush_shadow_all(struct kvm *kvm) 7725 { 7726 kvm_mmu_invalidate_zap_all_pages(kvm); 7727 } 7728 7729 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 7730 struct kvm_memory_slot *slot) 7731 { 7732 kvm_mmu_invalidate_zap_all_pages(kvm); 7733 } 7734 7735 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 7736 { 7737 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 7738 kvm_x86_ops->check_nested_events(vcpu, false); 7739 7740 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 7741 !vcpu->arch.apf.halted) 7742 || !list_empty_careful(&vcpu->async_pf.done) 7743 || kvm_apic_has_events(vcpu) 7744 || vcpu->arch.pv.pv_unhalted 7745 || atomic_read(&vcpu->arch.nmi_queued) || 7746 (kvm_arch_interrupt_allowed(vcpu) && 7747 kvm_cpu_has_interrupt(vcpu)); 7748 } 7749 7750 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 7751 { 7752 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 7753 } 7754 7755 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 7756 { 7757 return kvm_x86_ops->interrupt_allowed(vcpu); 7758 } 7759 7760 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 7761 { 7762 if (is_64_bit_mode(vcpu)) 7763 return kvm_rip_read(vcpu); 7764 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 7765 kvm_rip_read(vcpu)); 7766 } 7767 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 7768 7769 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 7770 { 7771 return kvm_get_linear_rip(vcpu) == linear_rip; 7772 } 7773 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 7774 7775 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 7776 { 7777 unsigned long rflags; 7778 7779 rflags = kvm_x86_ops->get_rflags(vcpu); 7780 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 7781 rflags &= ~X86_EFLAGS_TF; 7782 return rflags; 7783 } 7784 EXPORT_SYMBOL_GPL(kvm_get_rflags); 7785 7786 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 7787 { 7788 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 7789 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 7790 rflags |= X86_EFLAGS_TF; 7791 kvm_x86_ops->set_rflags(vcpu, rflags); 7792 } 7793 7794 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 7795 { 7796 __kvm_set_rflags(vcpu, rflags); 7797 kvm_make_request(KVM_REQ_EVENT, vcpu); 7798 } 7799 EXPORT_SYMBOL_GPL(kvm_set_rflags); 7800 7801 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 7802 { 7803 int r; 7804 7805 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 7806 work->wakeup_all) 7807 return; 7808 7809 r = kvm_mmu_reload(vcpu); 7810 if (unlikely(r)) 7811 return; 7812 7813 if (!vcpu->arch.mmu.direct_map && 7814 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 7815 return; 7816 7817 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 7818 } 7819 7820 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 7821 { 7822 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 7823 } 7824 7825 static inline u32 kvm_async_pf_next_probe(u32 key) 7826 { 7827 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 7828 } 7829 7830 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7831 { 7832 u32 key = kvm_async_pf_hash_fn(gfn); 7833 7834 while (vcpu->arch.apf.gfns[key] != ~0) 7835 key = kvm_async_pf_next_probe(key); 7836 7837 vcpu->arch.apf.gfns[key] = gfn; 7838 } 7839 7840 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 7841 { 7842 int i; 7843 u32 key = kvm_async_pf_hash_fn(gfn); 7844 7845 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 7846 (vcpu->arch.apf.gfns[key] != gfn && 7847 vcpu->arch.apf.gfns[key] != ~0); i++) 7848 key = kvm_async_pf_next_probe(key); 7849 7850 return key; 7851 } 7852 7853 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7854 { 7855 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 7856 } 7857 7858 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7859 { 7860 u32 i, j, k; 7861 7862 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 7863 while (true) { 7864 vcpu->arch.apf.gfns[i] = ~0; 7865 do { 7866 j = kvm_async_pf_next_probe(j); 7867 if (vcpu->arch.apf.gfns[j] == ~0) 7868 return; 7869 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 7870 /* 7871 * k lies cyclically in ]i,j] 7872 * | i.k.j | 7873 * |....j i.k.| or |.k..j i...| 7874 */ 7875 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 7876 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 7877 i = j; 7878 } 7879 } 7880 7881 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 7882 { 7883 7884 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 7885 sizeof(val)); 7886 } 7887 7888 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 7889 struct kvm_async_pf *work) 7890 { 7891 struct x86_exception fault; 7892 7893 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 7894 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 7895 7896 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 7897 (vcpu->arch.apf.send_user_only && 7898 kvm_x86_ops->get_cpl(vcpu) == 0)) 7899 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 7900 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 7901 fault.vector = PF_VECTOR; 7902 fault.error_code_valid = true; 7903 fault.error_code = 0; 7904 fault.nested_page_fault = false; 7905 fault.address = work->arch.token; 7906 kvm_inject_page_fault(vcpu, &fault); 7907 } 7908 } 7909 7910 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 7911 struct kvm_async_pf *work) 7912 { 7913 struct x86_exception fault; 7914 7915 trace_kvm_async_pf_ready(work->arch.token, work->gva); 7916 if (work->wakeup_all) 7917 work->arch.token = ~0; /* broadcast wakeup */ 7918 else 7919 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 7920 7921 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && 7922 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 7923 fault.vector = PF_VECTOR; 7924 fault.error_code_valid = true; 7925 fault.error_code = 0; 7926 fault.nested_page_fault = false; 7927 fault.address = work->arch.token; 7928 kvm_inject_page_fault(vcpu, &fault); 7929 } 7930 vcpu->arch.apf.halted = false; 7931 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7932 } 7933 7934 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 7935 { 7936 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 7937 return true; 7938 else 7939 return !kvm_event_needs_reinjection(vcpu) && 7940 kvm_x86_ops->interrupt_allowed(vcpu); 7941 } 7942 7943 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 7944 { 7945 atomic_inc(&kvm->arch.noncoherent_dma_count); 7946 } 7947 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 7948 7949 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 7950 { 7951 atomic_dec(&kvm->arch.noncoherent_dma_count); 7952 } 7953 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 7954 7955 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 7956 { 7957 return atomic_read(&kvm->arch.noncoherent_dma_count); 7958 } 7959 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 7960 7961 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 7962 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 7963 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 7964 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 7965 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 7966 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 7967 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 7968 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 7969 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 7970 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 7971 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 7972 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 7973 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 7974 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 7975 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 7976