1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "assigned-dev.h" 31 32 #include <linux/clocksource.h> 33 #include <linux/interrupt.h> 34 #include <linux/kvm.h> 35 #include <linux/fs.h> 36 #include <linux/vmalloc.h> 37 #include <linux/module.h> 38 #include <linux/mman.h> 39 #include <linux/highmem.h> 40 #include <linux/iommu.h> 41 #include <linux/intel-iommu.h> 42 #include <linux/cpufreq.h> 43 #include <linux/user-return-notifier.h> 44 #include <linux/srcu.h> 45 #include <linux/slab.h> 46 #include <linux/perf_event.h> 47 #include <linux/uaccess.h> 48 #include <linux/hash.h> 49 #include <linux/pci.h> 50 #include <linux/timekeeper_internal.h> 51 #include <linux/pvclock_gtod.h> 52 #include <trace/events/kvm.h> 53 54 #define CREATE_TRACE_POINTS 55 #include "trace.h" 56 57 #include <asm/debugreg.h> 58 #include <asm/msr.h> 59 #include <asm/desc.h> 60 #include <asm/mtrr.h> 61 #include <asm/mce.h> 62 #include <asm/i387.h> 63 #include <asm/fpu-internal.h> /* Ugh! */ 64 #include <asm/xcr.h> 65 #include <asm/pvclock.h> 66 #include <asm/div64.h> 67 68 #define MAX_IO_MSRS 256 69 #define KVM_MAX_MCE_BANKS 32 70 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) 71 72 #define emul_to_vcpu(ctxt) \ 73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 74 75 /* EFER defaults: 76 * - enable syscall per default because its emulated by KVM 77 * - enable LME and LMA per default on 64 bit KVM 78 */ 79 #ifdef CONFIG_X86_64 80 static 81 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 82 #else 83 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 84 #endif 85 86 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 87 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 88 89 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 90 static void process_nmi(struct kvm_vcpu *vcpu); 91 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 92 93 struct kvm_x86_ops *kvm_x86_ops; 94 EXPORT_SYMBOL_GPL(kvm_x86_ops); 95 96 static bool ignore_msrs = 0; 97 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 98 99 unsigned int min_timer_period_us = 500; 100 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 101 102 bool kvm_has_tsc_control; 103 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 104 u32 kvm_max_guest_tsc_khz; 105 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 106 107 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 108 static u32 tsc_tolerance_ppm = 250; 109 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 110 111 /* lapic timer advance (tscdeadline mode only) in nanoseconds */ 112 unsigned int lapic_timer_advance_ns = 0; 113 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 114 115 static bool backwards_tsc_observed = false; 116 117 #define KVM_NR_SHARED_MSRS 16 118 119 struct kvm_shared_msrs_global { 120 int nr; 121 u32 msrs[KVM_NR_SHARED_MSRS]; 122 }; 123 124 struct kvm_shared_msrs { 125 struct user_return_notifier urn; 126 bool registered; 127 struct kvm_shared_msr_values { 128 u64 host; 129 u64 curr; 130 } values[KVM_NR_SHARED_MSRS]; 131 }; 132 133 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 134 static struct kvm_shared_msrs __percpu *shared_msrs; 135 136 struct kvm_stats_debugfs_item debugfs_entries[] = { 137 { "pf_fixed", VCPU_STAT(pf_fixed) }, 138 { "pf_guest", VCPU_STAT(pf_guest) }, 139 { "tlb_flush", VCPU_STAT(tlb_flush) }, 140 { "invlpg", VCPU_STAT(invlpg) }, 141 { "exits", VCPU_STAT(exits) }, 142 { "io_exits", VCPU_STAT(io_exits) }, 143 { "mmio_exits", VCPU_STAT(mmio_exits) }, 144 { "signal_exits", VCPU_STAT(signal_exits) }, 145 { "irq_window", VCPU_STAT(irq_window_exits) }, 146 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 147 { "halt_exits", VCPU_STAT(halt_exits) }, 148 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 149 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 150 { "hypercalls", VCPU_STAT(hypercalls) }, 151 { "request_irq", VCPU_STAT(request_irq_exits) }, 152 { "irq_exits", VCPU_STAT(irq_exits) }, 153 { "host_state_reload", VCPU_STAT(host_state_reload) }, 154 { "efer_reload", VCPU_STAT(efer_reload) }, 155 { "fpu_reload", VCPU_STAT(fpu_reload) }, 156 { "insn_emulation", VCPU_STAT(insn_emulation) }, 157 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 158 { "irq_injections", VCPU_STAT(irq_injections) }, 159 { "nmi_injections", VCPU_STAT(nmi_injections) }, 160 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 161 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 162 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 163 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 164 { "mmu_flooded", VM_STAT(mmu_flooded) }, 165 { "mmu_recycled", VM_STAT(mmu_recycled) }, 166 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 167 { "mmu_unsync", VM_STAT(mmu_unsync) }, 168 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 169 { "largepages", VM_STAT(lpages) }, 170 { NULL } 171 }; 172 173 u64 __read_mostly host_xcr0; 174 175 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 176 177 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 178 { 179 int i; 180 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 181 vcpu->arch.apf.gfns[i] = ~0; 182 } 183 184 static void kvm_on_user_return(struct user_return_notifier *urn) 185 { 186 unsigned slot; 187 struct kvm_shared_msrs *locals 188 = container_of(urn, struct kvm_shared_msrs, urn); 189 struct kvm_shared_msr_values *values; 190 191 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 192 values = &locals->values[slot]; 193 if (values->host != values->curr) { 194 wrmsrl(shared_msrs_global.msrs[slot], values->host); 195 values->curr = values->host; 196 } 197 } 198 locals->registered = false; 199 user_return_notifier_unregister(urn); 200 } 201 202 static void shared_msr_update(unsigned slot, u32 msr) 203 { 204 u64 value; 205 unsigned int cpu = smp_processor_id(); 206 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 207 208 /* only read, and nobody should modify it at this time, 209 * so don't need lock */ 210 if (slot >= shared_msrs_global.nr) { 211 printk(KERN_ERR "kvm: invalid MSR slot!"); 212 return; 213 } 214 rdmsrl_safe(msr, &value); 215 smsr->values[slot].host = value; 216 smsr->values[slot].curr = value; 217 } 218 219 void kvm_define_shared_msr(unsigned slot, u32 msr) 220 { 221 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 222 if (slot >= shared_msrs_global.nr) 223 shared_msrs_global.nr = slot + 1; 224 shared_msrs_global.msrs[slot] = msr; 225 /* we need ensured the shared_msr_global have been updated */ 226 smp_wmb(); 227 } 228 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 229 230 static void kvm_shared_msr_cpu_online(void) 231 { 232 unsigned i; 233 234 for (i = 0; i < shared_msrs_global.nr; ++i) 235 shared_msr_update(i, shared_msrs_global.msrs[i]); 236 } 237 238 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 239 { 240 unsigned int cpu = smp_processor_id(); 241 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 242 int err; 243 244 if (((value ^ smsr->values[slot].curr) & mask) == 0) 245 return 0; 246 smsr->values[slot].curr = value; 247 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 248 if (err) 249 return 1; 250 251 if (!smsr->registered) { 252 smsr->urn.on_user_return = kvm_on_user_return; 253 user_return_notifier_register(&smsr->urn); 254 smsr->registered = true; 255 } 256 return 0; 257 } 258 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 259 260 static void drop_user_return_notifiers(void) 261 { 262 unsigned int cpu = smp_processor_id(); 263 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 264 265 if (smsr->registered) 266 kvm_on_user_return(&smsr->urn); 267 } 268 269 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 270 { 271 return vcpu->arch.apic_base; 272 } 273 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 274 275 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 276 { 277 u64 old_state = vcpu->arch.apic_base & 278 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 279 u64 new_state = msr_info->data & 280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 281 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 282 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); 283 284 if (!msr_info->host_initiated && 285 ((msr_info->data & reserved_bits) != 0 || 286 new_state == X2APIC_ENABLE || 287 (new_state == MSR_IA32_APICBASE_ENABLE && 288 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 289 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 290 old_state == 0))) 291 return 1; 292 293 kvm_lapic_set_base(vcpu, msr_info->data); 294 return 0; 295 } 296 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 297 298 asmlinkage __visible void kvm_spurious_fault(void) 299 { 300 /* Fault while not rebooting. We want the trace. */ 301 BUG(); 302 } 303 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 304 305 #define EXCPT_BENIGN 0 306 #define EXCPT_CONTRIBUTORY 1 307 #define EXCPT_PF 2 308 309 static int exception_class(int vector) 310 { 311 switch (vector) { 312 case PF_VECTOR: 313 return EXCPT_PF; 314 case DE_VECTOR: 315 case TS_VECTOR: 316 case NP_VECTOR: 317 case SS_VECTOR: 318 case GP_VECTOR: 319 return EXCPT_CONTRIBUTORY; 320 default: 321 break; 322 } 323 return EXCPT_BENIGN; 324 } 325 326 #define EXCPT_FAULT 0 327 #define EXCPT_TRAP 1 328 #define EXCPT_ABORT 2 329 #define EXCPT_INTERRUPT 3 330 331 static int exception_type(int vector) 332 { 333 unsigned int mask; 334 335 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 336 return EXCPT_INTERRUPT; 337 338 mask = 1 << vector; 339 340 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 341 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 342 return EXCPT_TRAP; 343 344 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 345 return EXCPT_ABORT; 346 347 /* Reserved exceptions will result in fault */ 348 return EXCPT_FAULT; 349 } 350 351 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 352 unsigned nr, bool has_error, u32 error_code, 353 bool reinject) 354 { 355 u32 prev_nr; 356 int class1, class2; 357 358 kvm_make_request(KVM_REQ_EVENT, vcpu); 359 360 if (!vcpu->arch.exception.pending) { 361 queue: 362 if (has_error && !is_protmode(vcpu)) 363 has_error = false; 364 vcpu->arch.exception.pending = true; 365 vcpu->arch.exception.has_error_code = has_error; 366 vcpu->arch.exception.nr = nr; 367 vcpu->arch.exception.error_code = error_code; 368 vcpu->arch.exception.reinject = reinject; 369 return; 370 } 371 372 /* to check exception */ 373 prev_nr = vcpu->arch.exception.nr; 374 if (prev_nr == DF_VECTOR) { 375 /* triple fault -> shutdown */ 376 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 377 return; 378 } 379 class1 = exception_class(prev_nr); 380 class2 = exception_class(nr); 381 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 382 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 383 /* generate double fault per SDM Table 5-5 */ 384 vcpu->arch.exception.pending = true; 385 vcpu->arch.exception.has_error_code = true; 386 vcpu->arch.exception.nr = DF_VECTOR; 387 vcpu->arch.exception.error_code = 0; 388 } else 389 /* replace previous exception with a new one in a hope 390 that instruction re-execution will regenerate lost 391 exception */ 392 goto queue; 393 } 394 395 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 396 { 397 kvm_multiple_exception(vcpu, nr, false, 0, false); 398 } 399 EXPORT_SYMBOL_GPL(kvm_queue_exception); 400 401 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 402 { 403 kvm_multiple_exception(vcpu, nr, false, 0, true); 404 } 405 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 406 407 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 408 { 409 if (err) 410 kvm_inject_gp(vcpu, 0); 411 else 412 kvm_x86_ops->skip_emulated_instruction(vcpu); 413 } 414 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 415 416 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 417 { 418 ++vcpu->stat.pf_guest; 419 vcpu->arch.cr2 = fault->address; 420 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 421 } 422 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 423 424 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 425 { 426 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 427 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 428 else 429 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 430 431 return fault->nested_page_fault; 432 } 433 434 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 435 { 436 atomic_inc(&vcpu->arch.nmi_queued); 437 kvm_make_request(KVM_REQ_NMI, vcpu); 438 } 439 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 440 441 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 442 { 443 kvm_multiple_exception(vcpu, nr, true, error_code, false); 444 } 445 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 446 447 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 448 { 449 kvm_multiple_exception(vcpu, nr, true, error_code, true); 450 } 451 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 452 453 /* 454 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 455 * a #GP and return false. 456 */ 457 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 458 { 459 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 460 return true; 461 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 462 return false; 463 } 464 EXPORT_SYMBOL_GPL(kvm_require_cpl); 465 466 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 467 { 468 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 469 return true; 470 471 kvm_queue_exception(vcpu, UD_VECTOR); 472 return false; 473 } 474 EXPORT_SYMBOL_GPL(kvm_require_dr); 475 476 /* 477 * This function will be used to read from the physical memory of the currently 478 * running guest. The difference to kvm_read_guest_page is that this function 479 * can read from guest physical or from the guest's guest physical memory. 480 */ 481 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 482 gfn_t ngfn, void *data, int offset, int len, 483 u32 access) 484 { 485 struct x86_exception exception; 486 gfn_t real_gfn; 487 gpa_t ngpa; 488 489 ngpa = gfn_to_gpa(ngfn); 490 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 491 if (real_gfn == UNMAPPED_GVA) 492 return -EFAULT; 493 494 real_gfn = gpa_to_gfn(real_gfn); 495 496 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len); 497 } 498 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 499 500 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 501 void *data, int offset, int len, u32 access) 502 { 503 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 504 data, offset, len, access); 505 } 506 507 /* 508 * Load the pae pdptrs. Return true is they are all valid. 509 */ 510 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 511 { 512 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 513 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 514 int i; 515 int ret; 516 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 517 518 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 519 offset * sizeof(u64), sizeof(pdpte), 520 PFERR_USER_MASK|PFERR_WRITE_MASK); 521 if (ret < 0) { 522 ret = 0; 523 goto out; 524 } 525 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 526 if (is_present_gpte(pdpte[i]) && 527 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { 528 ret = 0; 529 goto out; 530 } 531 } 532 ret = 1; 533 534 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 535 __set_bit(VCPU_EXREG_PDPTR, 536 (unsigned long *)&vcpu->arch.regs_avail); 537 __set_bit(VCPU_EXREG_PDPTR, 538 (unsigned long *)&vcpu->arch.regs_dirty); 539 out: 540 541 return ret; 542 } 543 EXPORT_SYMBOL_GPL(load_pdptrs); 544 545 static bool pdptrs_changed(struct kvm_vcpu *vcpu) 546 { 547 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 548 bool changed = true; 549 int offset; 550 gfn_t gfn; 551 int r; 552 553 if (is_long_mode(vcpu) || !is_pae(vcpu)) 554 return false; 555 556 if (!test_bit(VCPU_EXREG_PDPTR, 557 (unsigned long *)&vcpu->arch.regs_avail)) 558 return true; 559 560 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; 561 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); 562 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 563 PFERR_USER_MASK | PFERR_WRITE_MASK); 564 if (r < 0) 565 goto out; 566 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 567 out: 568 569 return changed; 570 } 571 572 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 573 { 574 unsigned long old_cr0 = kvm_read_cr0(vcpu); 575 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP | 576 X86_CR0_CD | X86_CR0_NW; 577 578 cr0 |= X86_CR0_ET; 579 580 #ifdef CONFIG_X86_64 581 if (cr0 & 0xffffffff00000000UL) 582 return 1; 583 #endif 584 585 cr0 &= ~CR0_RESERVED_BITS; 586 587 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 588 return 1; 589 590 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 591 return 1; 592 593 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 594 #ifdef CONFIG_X86_64 595 if ((vcpu->arch.efer & EFER_LME)) { 596 int cs_db, cs_l; 597 598 if (!is_pae(vcpu)) 599 return 1; 600 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 601 if (cs_l) 602 return 1; 603 } else 604 #endif 605 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 606 kvm_read_cr3(vcpu))) 607 return 1; 608 } 609 610 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 611 return 1; 612 613 kvm_x86_ops->set_cr0(vcpu, cr0); 614 615 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 616 kvm_clear_async_pf_completion_queue(vcpu); 617 kvm_async_pf_hash_reset(vcpu); 618 } 619 620 if ((cr0 ^ old_cr0) & update_bits) 621 kvm_mmu_reset_context(vcpu); 622 return 0; 623 } 624 EXPORT_SYMBOL_GPL(kvm_set_cr0); 625 626 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 627 { 628 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 629 } 630 EXPORT_SYMBOL_GPL(kvm_lmsw); 631 632 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 633 { 634 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 635 !vcpu->guest_xcr0_loaded) { 636 /* kvm_set_xcr() also depends on this */ 637 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 638 vcpu->guest_xcr0_loaded = 1; 639 } 640 } 641 642 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 643 { 644 if (vcpu->guest_xcr0_loaded) { 645 if (vcpu->arch.xcr0 != host_xcr0) 646 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 647 vcpu->guest_xcr0_loaded = 0; 648 } 649 } 650 651 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 652 { 653 u64 xcr0 = xcr; 654 u64 old_xcr0 = vcpu->arch.xcr0; 655 u64 valid_bits; 656 657 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 658 if (index != XCR_XFEATURE_ENABLED_MASK) 659 return 1; 660 if (!(xcr0 & XSTATE_FP)) 661 return 1; 662 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) 663 return 1; 664 665 /* 666 * Do not allow the guest to set bits that we do not support 667 * saving. However, xcr0 bit 0 is always set, even if the 668 * emulated CPU does not support XSAVE (see fx_init). 669 */ 670 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP; 671 if (xcr0 & ~valid_bits) 672 return 1; 673 674 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR))) 675 return 1; 676 677 if (xcr0 & XSTATE_AVX512) { 678 if (!(xcr0 & XSTATE_YMM)) 679 return 1; 680 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512) 681 return 1; 682 } 683 kvm_put_guest_xcr0(vcpu); 684 vcpu->arch.xcr0 = xcr0; 685 686 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK) 687 kvm_update_cpuid(vcpu); 688 return 0; 689 } 690 691 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 692 { 693 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 694 __kvm_set_xcr(vcpu, index, xcr)) { 695 kvm_inject_gp(vcpu, 0); 696 return 1; 697 } 698 return 0; 699 } 700 EXPORT_SYMBOL_GPL(kvm_set_xcr); 701 702 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 703 { 704 unsigned long old_cr4 = kvm_read_cr4(vcpu); 705 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | 706 X86_CR4_PAE | X86_CR4_SMEP; 707 if (cr4 & CR4_RESERVED_BITS) 708 return 1; 709 710 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) 711 return 1; 712 713 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) 714 return 1; 715 716 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) 717 return 1; 718 719 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) 720 return 1; 721 722 if (is_long_mode(vcpu)) { 723 if (!(cr4 & X86_CR4_PAE)) 724 return 1; 725 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 726 && ((cr4 ^ old_cr4) & pdptr_bits) 727 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 728 kvm_read_cr3(vcpu))) 729 return 1; 730 731 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 732 if (!guest_cpuid_has_pcid(vcpu)) 733 return 1; 734 735 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 736 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 737 return 1; 738 } 739 740 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 741 return 1; 742 743 if (((cr4 ^ old_cr4) & pdptr_bits) || 744 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 745 kvm_mmu_reset_context(vcpu); 746 747 if ((cr4 ^ old_cr4) & X86_CR4_SMAP) 748 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false); 749 750 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) 751 kvm_update_cpuid(vcpu); 752 753 return 0; 754 } 755 EXPORT_SYMBOL_GPL(kvm_set_cr4); 756 757 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 758 { 759 #ifdef CONFIG_X86_64 760 cr3 &= ~CR3_PCID_INVD; 761 #endif 762 763 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 764 kvm_mmu_sync_roots(vcpu); 765 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 766 return 0; 767 } 768 769 if (is_long_mode(vcpu)) { 770 if (cr3 & CR3_L_MODE_RESERVED_BITS) 771 return 1; 772 } else if (is_pae(vcpu) && is_paging(vcpu) && 773 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 774 return 1; 775 776 vcpu->arch.cr3 = cr3; 777 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 778 kvm_mmu_new_cr3(vcpu); 779 return 0; 780 } 781 EXPORT_SYMBOL_GPL(kvm_set_cr3); 782 783 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 784 { 785 if (cr8 & CR8_RESERVED_BITS) 786 return 1; 787 if (irqchip_in_kernel(vcpu->kvm)) 788 kvm_lapic_set_tpr(vcpu, cr8); 789 else 790 vcpu->arch.cr8 = cr8; 791 return 0; 792 } 793 EXPORT_SYMBOL_GPL(kvm_set_cr8); 794 795 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 796 { 797 if (irqchip_in_kernel(vcpu->kvm)) 798 return kvm_lapic_get_cr8(vcpu); 799 else 800 return vcpu->arch.cr8; 801 } 802 EXPORT_SYMBOL_GPL(kvm_get_cr8); 803 804 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 805 { 806 int i; 807 808 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 809 for (i = 0; i < KVM_NR_DB_REGS; i++) 810 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 811 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 812 } 813 } 814 815 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 816 { 817 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 818 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 819 } 820 821 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 822 { 823 unsigned long dr7; 824 825 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 826 dr7 = vcpu->arch.guest_debug_dr7; 827 else 828 dr7 = vcpu->arch.dr7; 829 kvm_x86_ops->set_dr7(vcpu, dr7); 830 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 831 if (dr7 & DR7_BP_EN_MASK) 832 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 833 } 834 835 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 836 { 837 u64 fixed = DR6_FIXED_1; 838 839 if (!guest_cpuid_has_rtm(vcpu)) 840 fixed |= DR6_RTM; 841 return fixed; 842 } 843 844 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 845 { 846 switch (dr) { 847 case 0 ... 3: 848 vcpu->arch.db[dr] = val; 849 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 850 vcpu->arch.eff_db[dr] = val; 851 break; 852 case 4: 853 /* fall through */ 854 case 6: 855 if (val & 0xffffffff00000000ULL) 856 return -1; /* #GP */ 857 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 858 kvm_update_dr6(vcpu); 859 break; 860 case 5: 861 /* fall through */ 862 default: /* 7 */ 863 if (val & 0xffffffff00000000ULL) 864 return -1; /* #GP */ 865 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 866 kvm_update_dr7(vcpu); 867 break; 868 } 869 870 return 0; 871 } 872 873 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 874 { 875 if (__kvm_set_dr(vcpu, dr, val)) { 876 kvm_inject_gp(vcpu, 0); 877 return 1; 878 } 879 return 0; 880 } 881 EXPORT_SYMBOL_GPL(kvm_set_dr); 882 883 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 884 { 885 switch (dr) { 886 case 0 ... 3: 887 *val = vcpu->arch.db[dr]; 888 break; 889 case 4: 890 /* fall through */ 891 case 6: 892 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 893 *val = vcpu->arch.dr6; 894 else 895 *val = kvm_x86_ops->get_dr6(vcpu); 896 break; 897 case 5: 898 /* fall through */ 899 default: /* 7 */ 900 *val = vcpu->arch.dr7; 901 break; 902 } 903 return 0; 904 } 905 EXPORT_SYMBOL_GPL(kvm_get_dr); 906 907 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 908 { 909 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 910 u64 data; 911 int err; 912 913 err = kvm_pmu_read_pmc(vcpu, ecx, &data); 914 if (err) 915 return err; 916 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 917 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 918 return err; 919 } 920 EXPORT_SYMBOL_GPL(kvm_rdpmc); 921 922 /* 923 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 924 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 925 * 926 * This list is modified at module load time to reflect the 927 * capabilities of the host cpu. This capabilities test skips MSRs that are 928 * kvm-specific. Those are put in the beginning of the list. 929 */ 930 931 #define KVM_SAVE_MSRS_BEGIN 12 932 static u32 msrs_to_save[] = { 933 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 934 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 935 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 936 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 937 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 938 MSR_KVM_PV_EOI_EN, 939 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 940 MSR_STAR, 941 #ifdef CONFIG_X86_64 942 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 943 #endif 944 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 945 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS 946 }; 947 948 static unsigned num_msrs_to_save; 949 950 static const u32 emulated_msrs[] = { 951 MSR_IA32_TSC_ADJUST, 952 MSR_IA32_TSCDEADLINE, 953 MSR_IA32_MISC_ENABLE, 954 MSR_IA32_MCG_STATUS, 955 MSR_IA32_MCG_CTL, 956 }; 957 958 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 959 { 960 if (efer & efer_reserved_bits) 961 return false; 962 963 if (efer & EFER_FFXSR) { 964 struct kvm_cpuid_entry2 *feat; 965 966 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 967 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) 968 return false; 969 } 970 971 if (efer & EFER_SVME) { 972 struct kvm_cpuid_entry2 *feat; 973 974 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 975 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) 976 return false; 977 } 978 979 return true; 980 } 981 EXPORT_SYMBOL_GPL(kvm_valid_efer); 982 983 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 984 { 985 u64 old_efer = vcpu->arch.efer; 986 987 if (!kvm_valid_efer(vcpu, efer)) 988 return 1; 989 990 if (is_paging(vcpu) 991 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 992 return 1; 993 994 efer &= ~EFER_LMA; 995 efer |= vcpu->arch.efer & EFER_LMA; 996 997 kvm_x86_ops->set_efer(vcpu, efer); 998 999 /* Update reserved bits */ 1000 if ((efer ^ old_efer) & EFER_NX) 1001 kvm_mmu_reset_context(vcpu); 1002 1003 return 0; 1004 } 1005 1006 void kvm_enable_efer_bits(u64 mask) 1007 { 1008 efer_reserved_bits &= ~mask; 1009 } 1010 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1011 1012 /* 1013 * Writes msr value into into the appropriate "register". 1014 * Returns 0 on success, non-0 otherwise. 1015 * Assumes vcpu_load() was already called. 1016 */ 1017 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1018 { 1019 switch (msr->index) { 1020 case MSR_FS_BASE: 1021 case MSR_GS_BASE: 1022 case MSR_KERNEL_GS_BASE: 1023 case MSR_CSTAR: 1024 case MSR_LSTAR: 1025 if (is_noncanonical_address(msr->data)) 1026 return 1; 1027 break; 1028 case MSR_IA32_SYSENTER_EIP: 1029 case MSR_IA32_SYSENTER_ESP: 1030 /* 1031 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1032 * non-canonical address is written on Intel but not on 1033 * AMD (which ignores the top 32-bits, because it does 1034 * not implement 64-bit SYSENTER). 1035 * 1036 * 64-bit code should hence be able to write a non-canonical 1037 * value on AMD. Making the address canonical ensures that 1038 * vmentry does not fail on Intel after writing a non-canonical 1039 * value, and that something deterministic happens if the guest 1040 * invokes 64-bit SYSENTER. 1041 */ 1042 msr->data = get_canonical(msr->data); 1043 } 1044 return kvm_x86_ops->set_msr(vcpu, msr); 1045 } 1046 EXPORT_SYMBOL_GPL(kvm_set_msr); 1047 1048 /* 1049 * Adapt set_msr() to msr_io()'s calling convention 1050 */ 1051 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1052 { 1053 struct msr_data msr; 1054 1055 msr.data = *data; 1056 msr.index = index; 1057 msr.host_initiated = true; 1058 return kvm_set_msr(vcpu, &msr); 1059 } 1060 1061 #ifdef CONFIG_X86_64 1062 struct pvclock_gtod_data { 1063 seqcount_t seq; 1064 1065 struct { /* extract of a clocksource struct */ 1066 int vclock_mode; 1067 cycle_t cycle_last; 1068 cycle_t mask; 1069 u32 mult; 1070 u32 shift; 1071 } clock; 1072 1073 u64 boot_ns; 1074 u64 nsec_base; 1075 }; 1076 1077 static struct pvclock_gtod_data pvclock_gtod_data; 1078 1079 static void update_pvclock_gtod(struct timekeeper *tk) 1080 { 1081 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1082 u64 boot_ns; 1083 1084 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1085 1086 write_seqcount_begin(&vdata->seq); 1087 1088 /* copy pvclock gtod data */ 1089 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1090 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1091 vdata->clock.mask = tk->tkr_mono.mask; 1092 vdata->clock.mult = tk->tkr_mono.mult; 1093 vdata->clock.shift = tk->tkr_mono.shift; 1094 1095 vdata->boot_ns = boot_ns; 1096 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1097 1098 write_seqcount_end(&vdata->seq); 1099 } 1100 #endif 1101 1102 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1103 { 1104 /* 1105 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1106 * vcpu_enter_guest. This function is only called from 1107 * the physical CPU that is running vcpu. 1108 */ 1109 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1110 } 1111 1112 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1113 { 1114 int version; 1115 int r; 1116 struct pvclock_wall_clock wc; 1117 struct timespec boot; 1118 1119 if (!wall_clock) 1120 return; 1121 1122 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1123 if (r) 1124 return; 1125 1126 if (version & 1) 1127 ++version; /* first time write, random junk */ 1128 1129 ++version; 1130 1131 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1132 1133 /* 1134 * The guest calculates current wall clock time by adding 1135 * system time (updated by kvm_guest_time_update below) to the 1136 * wall clock specified here. guest system time equals host 1137 * system time for us, thus we must fill in host boot time here. 1138 */ 1139 getboottime(&boot); 1140 1141 if (kvm->arch.kvmclock_offset) { 1142 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); 1143 boot = timespec_sub(boot, ts); 1144 } 1145 wc.sec = boot.tv_sec; 1146 wc.nsec = boot.tv_nsec; 1147 wc.version = version; 1148 1149 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1150 1151 version++; 1152 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1153 } 1154 1155 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1156 { 1157 uint32_t quotient, remainder; 1158 1159 /* Don't try to replace with do_div(), this one calculates 1160 * "(dividend << 32) / divisor" */ 1161 __asm__ ( "divl %4" 1162 : "=a" (quotient), "=d" (remainder) 1163 : "0" (0), "1" (dividend), "r" (divisor) ); 1164 return quotient; 1165 } 1166 1167 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, 1168 s8 *pshift, u32 *pmultiplier) 1169 { 1170 uint64_t scaled64; 1171 int32_t shift = 0; 1172 uint64_t tps64; 1173 uint32_t tps32; 1174 1175 tps64 = base_khz * 1000LL; 1176 scaled64 = scaled_khz * 1000LL; 1177 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1178 tps64 >>= 1; 1179 shift--; 1180 } 1181 1182 tps32 = (uint32_t)tps64; 1183 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1184 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1185 scaled64 >>= 1; 1186 else 1187 tps32 <<= 1; 1188 shift++; 1189 } 1190 1191 *pshift = shift; 1192 *pmultiplier = div_frac(scaled64, tps32); 1193 1194 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", 1195 __func__, base_khz, scaled_khz, shift, *pmultiplier); 1196 } 1197 1198 static inline u64 get_kernel_ns(void) 1199 { 1200 return ktime_get_boot_ns(); 1201 } 1202 1203 #ifdef CONFIG_X86_64 1204 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1205 #endif 1206 1207 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1208 static unsigned long max_tsc_khz; 1209 1210 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) 1211 { 1212 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, 1213 vcpu->arch.virtual_tsc_shift); 1214 } 1215 1216 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1217 { 1218 u64 v = (u64)khz * (1000000 + ppm); 1219 do_div(v, 1000000); 1220 return v; 1221 } 1222 1223 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) 1224 { 1225 u32 thresh_lo, thresh_hi; 1226 int use_scaling = 0; 1227 1228 /* tsc_khz can be zero if TSC calibration fails */ 1229 if (this_tsc_khz == 0) 1230 return; 1231 1232 /* Compute a scale to convert nanoseconds in TSC cycles */ 1233 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, 1234 &vcpu->arch.virtual_tsc_shift, 1235 &vcpu->arch.virtual_tsc_mult); 1236 vcpu->arch.virtual_tsc_khz = this_tsc_khz; 1237 1238 /* 1239 * Compute the variation in TSC rate which is acceptable 1240 * within the range of tolerance and decide if the 1241 * rate being applied is within that bounds of the hardware 1242 * rate. If so, no scaling or compensation need be done. 1243 */ 1244 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1245 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1246 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { 1247 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); 1248 use_scaling = 1; 1249 } 1250 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling); 1251 } 1252 1253 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1254 { 1255 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1256 vcpu->arch.virtual_tsc_mult, 1257 vcpu->arch.virtual_tsc_shift); 1258 tsc += vcpu->arch.this_tsc_write; 1259 return tsc; 1260 } 1261 1262 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1263 { 1264 #ifdef CONFIG_X86_64 1265 bool vcpus_matched; 1266 struct kvm_arch *ka = &vcpu->kvm->arch; 1267 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1268 1269 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1270 atomic_read(&vcpu->kvm->online_vcpus)); 1271 1272 /* 1273 * Once the masterclock is enabled, always perform request in 1274 * order to update it. 1275 * 1276 * In order to enable masterclock, the host clocksource must be TSC 1277 * and the vcpus need to have matched TSCs. When that happens, 1278 * perform request to enable masterclock. 1279 */ 1280 if (ka->use_master_clock || 1281 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) 1282 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1283 1284 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1285 atomic_read(&vcpu->kvm->online_vcpus), 1286 ka->use_master_clock, gtod->clock.vclock_mode); 1287 #endif 1288 } 1289 1290 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1291 { 1292 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); 1293 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1294 } 1295 1296 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1297 { 1298 struct kvm *kvm = vcpu->kvm; 1299 u64 offset, ns, elapsed; 1300 unsigned long flags; 1301 s64 usdiff; 1302 bool matched; 1303 bool already_matched; 1304 u64 data = msr->data; 1305 1306 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1307 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); 1308 ns = get_kernel_ns(); 1309 elapsed = ns - kvm->arch.last_tsc_nsec; 1310 1311 if (vcpu->arch.virtual_tsc_khz) { 1312 int faulted = 0; 1313 1314 /* n.b - signed multiplication and division required */ 1315 usdiff = data - kvm->arch.last_tsc_write; 1316 #ifdef CONFIG_X86_64 1317 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; 1318 #else 1319 /* do_div() only does unsigned */ 1320 asm("1: idivl %[divisor]\n" 1321 "2: xor %%edx, %%edx\n" 1322 " movl $0, %[faulted]\n" 1323 "3:\n" 1324 ".section .fixup,\"ax\"\n" 1325 "4: movl $1, %[faulted]\n" 1326 " jmp 3b\n" 1327 ".previous\n" 1328 1329 _ASM_EXTABLE(1b, 4b) 1330 1331 : "=A"(usdiff), [faulted] "=r" (faulted) 1332 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); 1333 1334 #endif 1335 do_div(elapsed, 1000); 1336 usdiff -= elapsed; 1337 if (usdiff < 0) 1338 usdiff = -usdiff; 1339 1340 /* idivl overflow => difference is larger than USEC_PER_SEC */ 1341 if (faulted) 1342 usdiff = USEC_PER_SEC; 1343 } else 1344 usdiff = USEC_PER_SEC; /* disable TSC match window below */ 1345 1346 /* 1347 * Special case: TSC write with a small delta (1 second) of virtual 1348 * cycle time against real time is interpreted as an attempt to 1349 * synchronize the CPU. 1350 * 1351 * For a reliable TSC, we can match TSC offsets, and for an unstable 1352 * TSC, we add elapsed time in this computation. We could let the 1353 * compensation code attempt to catch up if we fall behind, but 1354 * it's better to try to match offsets from the beginning. 1355 */ 1356 if (usdiff < USEC_PER_SEC && 1357 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1358 if (!check_tsc_unstable()) { 1359 offset = kvm->arch.cur_tsc_offset; 1360 pr_debug("kvm: matched tsc offset for %llu\n", data); 1361 } else { 1362 u64 delta = nsec_to_cycles(vcpu, elapsed); 1363 data += delta; 1364 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); 1365 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1366 } 1367 matched = true; 1368 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1369 } else { 1370 /* 1371 * We split periods of matched TSC writes into generations. 1372 * For each generation, we track the original measured 1373 * nanosecond time, offset, and write, so if TSCs are in 1374 * sync, we can match exact offset, and if not, we can match 1375 * exact software computation in compute_guest_tsc() 1376 * 1377 * These values are tracked in kvm->arch.cur_xxx variables. 1378 */ 1379 kvm->arch.cur_tsc_generation++; 1380 kvm->arch.cur_tsc_nsec = ns; 1381 kvm->arch.cur_tsc_write = data; 1382 kvm->arch.cur_tsc_offset = offset; 1383 matched = false; 1384 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1385 kvm->arch.cur_tsc_generation, data); 1386 } 1387 1388 /* 1389 * We also track th most recent recorded KHZ, write and time to 1390 * allow the matching interval to be extended at each write. 1391 */ 1392 kvm->arch.last_tsc_nsec = ns; 1393 kvm->arch.last_tsc_write = data; 1394 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1395 1396 vcpu->arch.last_guest_tsc = data; 1397 1398 /* Keep track of which generation this VCPU has synchronized to */ 1399 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1400 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1401 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1402 1403 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) 1404 update_ia32_tsc_adjust_msr(vcpu, offset); 1405 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1406 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1407 1408 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1409 if (!matched) { 1410 kvm->arch.nr_vcpus_matched_tsc = 0; 1411 } else if (!already_matched) { 1412 kvm->arch.nr_vcpus_matched_tsc++; 1413 } 1414 1415 kvm_track_tsc_matching(vcpu); 1416 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1417 } 1418 1419 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1420 1421 #ifdef CONFIG_X86_64 1422 1423 static cycle_t read_tsc(void) 1424 { 1425 cycle_t ret; 1426 u64 last; 1427 1428 /* 1429 * Empirically, a fence (of type that depends on the CPU) 1430 * before rdtsc is enough to ensure that rdtsc is ordered 1431 * with respect to loads. The various CPU manuals are unclear 1432 * as to whether rdtsc can be reordered with later loads, 1433 * but no one has ever seen it happen. 1434 */ 1435 rdtsc_barrier(); 1436 ret = (cycle_t)vget_cycles(); 1437 1438 last = pvclock_gtod_data.clock.cycle_last; 1439 1440 if (likely(ret >= last)) 1441 return ret; 1442 1443 /* 1444 * GCC likes to generate cmov here, but this branch is extremely 1445 * predictable (it's just a funciton of time and the likely is 1446 * very likely) and there's a data dependence, so force GCC 1447 * to generate a branch instead. I don't barrier() because 1448 * we don't actually need a barrier, and if this function 1449 * ever gets inlined it will generate worse code. 1450 */ 1451 asm volatile (""); 1452 return last; 1453 } 1454 1455 static inline u64 vgettsc(cycle_t *cycle_now) 1456 { 1457 long v; 1458 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1459 1460 *cycle_now = read_tsc(); 1461 1462 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; 1463 return v * gtod->clock.mult; 1464 } 1465 1466 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now) 1467 { 1468 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1469 unsigned long seq; 1470 int mode; 1471 u64 ns; 1472 1473 do { 1474 seq = read_seqcount_begin(>od->seq); 1475 mode = gtod->clock.vclock_mode; 1476 ns = gtod->nsec_base; 1477 ns += vgettsc(cycle_now); 1478 ns >>= gtod->clock.shift; 1479 ns += gtod->boot_ns; 1480 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1481 *t = ns; 1482 1483 return mode; 1484 } 1485 1486 /* returns true if host is using tsc clocksource */ 1487 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) 1488 { 1489 /* checked again under seqlock below */ 1490 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) 1491 return false; 1492 1493 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; 1494 } 1495 #endif 1496 1497 /* 1498 * 1499 * Assuming a stable TSC across physical CPUS, and a stable TSC 1500 * across virtual CPUs, the following condition is possible. 1501 * Each numbered line represents an event visible to both 1502 * CPUs at the next numbered event. 1503 * 1504 * "timespecX" represents host monotonic time. "tscX" represents 1505 * RDTSC value. 1506 * 1507 * VCPU0 on CPU0 | VCPU1 on CPU1 1508 * 1509 * 1. read timespec0,tsc0 1510 * 2. | timespec1 = timespec0 + N 1511 * | tsc1 = tsc0 + M 1512 * 3. transition to guest | transition to guest 1513 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1514 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1515 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1516 * 1517 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1518 * 1519 * - ret0 < ret1 1520 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1521 * ... 1522 * - 0 < N - M => M < N 1523 * 1524 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1525 * always the case (the difference between two distinct xtime instances 1526 * might be smaller then the difference between corresponding TSC reads, 1527 * when updating guest vcpus pvclock areas). 1528 * 1529 * To avoid that problem, do not allow visibility of distinct 1530 * system_timestamp/tsc_timestamp values simultaneously: use a master 1531 * copy of host monotonic time values. Update that master copy 1532 * in lockstep. 1533 * 1534 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1535 * 1536 */ 1537 1538 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1539 { 1540 #ifdef CONFIG_X86_64 1541 struct kvm_arch *ka = &kvm->arch; 1542 int vclock_mode; 1543 bool host_tsc_clocksource, vcpus_matched; 1544 1545 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1546 atomic_read(&kvm->online_vcpus)); 1547 1548 /* 1549 * If the host uses TSC clock, then passthrough TSC as stable 1550 * to the guest. 1551 */ 1552 host_tsc_clocksource = kvm_get_time_and_clockread( 1553 &ka->master_kernel_ns, 1554 &ka->master_cycle_now); 1555 1556 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 1557 && !backwards_tsc_observed 1558 && !ka->boot_vcpu_runs_old_kvmclock; 1559 1560 if (ka->use_master_clock) 1561 atomic_set(&kvm_guest_has_master_clock, 1); 1562 1563 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1564 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1565 vcpus_matched); 1566 #endif 1567 } 1568 1569 static void kvm_gen_update_masterclock(struct kvm *kvm) 1570 { 1571 #ifdef CONFIG_X86_64 1572 int i; 1573 struct kvm_vcpu *vcpu; 1574 struct kvm_arch *ka = &kvm->arch; 1575 1576 spin_lock(&ka->pvclock_gtod_sync_lock); 1577 kvm_make_mclock_inprogress_request(kvm); 1578 /* no guest entries from this point */ 1579 pvclock_update_vm_gtod_copy(kvm); 1580 1581 kvm_for_each_vcpu(i, vcpu, kvm) 1582 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1583 1584 /* guest entries allowed */ 1585 kvm_for_each_vcpu(i, vcpu, kvm) 1586 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); 1587 1588 spin_unlock(&ka->pvclock_gtod_sync_lock); 1589 #endif 1590 } 1591 1592 static int kvm_guest_time_update(struct kvm_vcpu *v) 1593 { 1594 unsigned long flags, this_tsc_khz; 1595 struct kvm_vcpu_arch *vcpu = &v->arch; 1596 struct kvm_arch *ka = &v->kvm->arch; 1597 s64 kernel_ns; 1598 u64 tsc_timestamp, host_tsc; 1599 struct pvclock_vcpu_time_info guest_hv_clock; 1600 u8 pvclock_flags; 1601 bool use_master_clock; 1602 1603 kernel_ns = 0; 1604 host_tsc = 0; 1605 1606 /* 1607 * If the host uses TSC clock, then passthrough TSC as stable 1608 * to the guest. 1609 */ 1610 spin_lock(&ka->pvclock_gtod_sync_lock); 1611 use_master_clock = ka->use_master_clock; 1612 if (use_master_clock) { 1613 host_tsc = ka->master_cycle_now; 1614 kernel_ns = ka->master_kernel_ns; 1615 } 1616 spin_unlock(&ka->pvclock_gtod_sync_lock); 1617 1618 /* Keep irq disabled to prevent changes to the clock */ 1619 local_irq_save(flags); 1620 this_tsc_khz = __this_cpu_read(cpu_tsc_khz); 1621 if (unlikely(this_tsc_khz == 0)) { 1622 local_irq_restore(flags); 1623 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1624 return 1; 1625 } 1626 if (!use_master_clock) { 1627 host_tsc = native_read_tsc(); 1628 kernel_ns = get_kernel_ns(); 1629 } 1630 1631 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc); 1632 1633 /* 1634 * We may have to catch up the TSC to match elapsed wall clock 1635 * time for two reasons, even if kvmclock is used. 1636 * 1) CPU could have been running below the maximum TSC rate 1637 * 2) Broken TSC compensation resets the base at each VCPU 1638 * entry to avoid unknown leaps of TSC even when running 1639 * again on the same CPU. This may cause apparent elapsed 1640 * time to disappear, and the guest to stand still or run 1641 * very slowly. 1642 */ 1643 if (vcpu->tsc_catchup) { 1644 u64 tsc = compute_guest_tsc(v, kernel_ns); 1645 if (tsc > tsc_timestamp) { 1646 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 1647 tsc_timestamp = tsc; 1648 } 1649 } 1650 1651 local_irq_restore(flags); 1652 1653 if (!vcpu->pv_time_enabled) 1654 return 0; 1655 1656 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { 1657 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz, 1658 &vcpu->hv_clock.tsc_shift, 1659 &vcpu->hv_clock.tsc_to_system_mul); 1660 vcpu->hw_tsc_khz = this_tsc_khz; 1661 } 1662 1663 /* With all the info we got, fill in the values */ 1664 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 1665 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 1666 vcpu->last_guest_tsc = tsc_timestamp; 1667 1668 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1669 &guest_hv_clock, sizeof(guest_hv_clock)))) 1670 return 0; 1671 1672 /* 1673 * The interface expects us to write an even number signaling that the 1674 * update is finished. Since the guest won't see the intermediate 1675 * state, we just increase by 2 at the end. 1676 */ 1677 vcpu->hv_clock.version = guest_hv_clock.version + 2; 1678 1679 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1680 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1681 1682 if (vcpu->pvclock_set_guest_stopped_request) { 1683 pvclock_flags |= PVCLOCK_GUEST_STOPPED; 1684 vcpu->pvclock_set_guest_stopped_request = false; 1685 } 1686 1687 /* If the host uses TSC clocksource, then it is stable */ 1688 if (use_master_clock) 1689 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 1690 1691 vcpu->hv_clock.flags = pvclock_flags; 1692 1693 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 1694 1695 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1696 &vcpu->hv_clock, 1697 sizeof(vcpu->hv_clock)); 1698 return 0; 1699 } 1700 1701 /* 1702 * kvmclock updates which are isolated to a given vcpu, such as 1703 * vcpu->cpu migration, should not allow system_timestamp from 1704 * the rest of the vcpus to remain static. Otherwise ntp frequency 1705 * correction applies to one vcpu's system_timestamp but not 1706 * the others. 1707 * 1708 * So in those cases, request a kvmclock update for all vcpus. 1709 * We need to rate-limit these requests though, as they can 1710 * considerably slow guests that have a large number of vcpus. 1711 * The time for a remote vcpu to update its kvmclock is bound 1712 * by the delay we use to rate-limit the updates. 1713 */ 1714 1715 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 1716 1717 static void kvmclock_update_fn(struct work_struct *work) 1718 { 1719 int i; 1720 struct delayed_work *dwork = to_delayed_work(work); 1721 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1722 kvmclock_update_work); 1723 struct kvm *kvm = container_of(ka, struct kvm, arch); 1724 struct kvm_vcpu *vcpu; 1725 1726 kvm_for_each_vcpu(i, vcpu, kvm) { 1727 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1728 kvm_vcpu_kick(vcpu); 1729 } 1730 } 1731 1732 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 1733 { 1734 struct kvm *kvm = v->kvm; 1735 1736 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1737 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 1738 KVMCLOCK_UPDATE_DELAY); 1739 } 1740 1741 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 1742 1743 static void kvmclock_sync_fn(struct work_struct *work) 1744 { 1745 struct delayed_work *dwork = to_delayed_work(work); 1746 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1747 kvmclock_sync_work); 1748 struct kvm *kvm = container_of(ka, struct kvm, arch); 1749 1750 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 1751 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 1752 KVMCLOCK_SYNC_PERIOD); 1753 } 1754 1755 static bool msr_mtrr_valid(unsigned msr) 1756 { 1757 switch (msr) { 1758 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: 1759 case MSR_MTRRfix64K_00000: 1760 case MSR_MTRRfix16K_80000: 1761 case MSR_MTRRfix16K_A0000: 1762 case MSR_MTRRfix4K_C0000: 1763 case MSR_MTRRfix4K_C8000: 1764 case MSR_MTRRfix4K_D0000: 1765 case MSR_MTRRfix4K_D8000: 1766 case MSR_MTRRfix4K_E0000: 1767 case MSR_MTRRfix4K_E8000: 1768 case MSR_MTRRfix4K_F0000: 1769 case MSR_MTRRfix4K_F8000: 1770 case MSR_MTRRdefType: 1771 case MSR_IA32_CR_PAT: 1772 return true; 1773 case 0x2f8: 1774 return true; 1775 } 1776 return false; 1777 } 1778 1779 static bool valid_pat_type(unsigned t) 1780 { 1781 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ 1782 } 1783 1784 static bool valid_mtrr_type(unsigned t) 1785 { 1786 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ 1787 } 1788 1789 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1790 { 1791 int i; 1792 u64 mask; 1793 1794 if (!msr_mtrr_valid(msr)) 1795 return false; 1796 1797 if (msr == MSR_IA32_CR_PAT) { 1798 for (i = 0; i < 8; i++) 1799 if (!valid_pat_type((data >> (i * 8)) & 0xff)) 1800 return false; 1801 return true; 1802 } else if (msr == MSR_MTRRdefType) { 1803 if (data & ~0xcff) 1804 return false; 1805 return valid_mtrr_type(data & 0xff); 1806 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { 1807 for (i = 0; i < 8 ; i++) 1808 if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) 1809 return false; 1810 return true; 1811 } 1812 1813 /* variable MTRRs */ 1814 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR)); 1815 1816 mask = (~0ULL) << cpuid_maxphyaddr(vcpu); 1817 if ((msr & 1) == 0) { 1818 /* MTRR base */ 1819 if (!valid_mtrr_type(data & 0xff)) 1820 return false; 1821 mask |= 0xf00; 1822 } else 1823 /* MTRR mask */ 1824 mask |= 0x7ff; 1825 if (data & mask) { 1826 kvm_inject_gp(vcpu, 0); 1827 return false; 1828 } 1829 1830 return true; 1831 } 1832 EXPORT_SYMBOL_GPL(kvm_mtrr_valid); 1833 1834 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1835 { 1836 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; 1837 1838 if (!kvm_mtrr_valid(vcpu, msr, data)) 1839 return 1; 1840 1841 if (msr == MSR_MTRRdefType) { 1842 vcpu->arch.mtrr_state.def_type = data; 1843 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; 1844 } else if (msr == MSR_MTRRfix64K_00000) 1845 p[0] = data; 1846 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) 1847 p[1 + msr - MSR_MTRRfix16K_80000] = data; 1848 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) 1849 p[3 + msr - MSR_MTRRfix4K_C0000] = data; 1850 else if (msr == MSR_IA32_CR_PAT) 1851 vcpu->arch.pat = data; 1852 else { /* Variable MTRRs */ 1853 int idx, is_mtrr_mask; 1854 u64 *pt; 1855 1856 idx = (msr - 0x200) / 2; 1857 is_mtrr_mask = msr - 0x200 - 2 * idx; 1858 if (!is_mtrr_mask) 1859 pt = 1860 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; 1861 else 1862 pt = 1863 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; 1864 *pt = data; 1865 } 1866 1867 kvm_mmu_reset_context(vcpu); 1868 return 0; 1869 } 1870 1871 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1872 { 1873 u64 mcg_cap = vcpu->arch.mcg_cap; 1874 unsigned bank_num = mcg_cap & 0xff; 1875 1876 switch (msr) { 1877 case MSR_IA32_MCG_STATUS: 1878 vcpu->arch.mcg_status = data; 1879 break; 1880 case MSR_IA32_MCG_CTL: 1881 if (!(mcg_cap & MCG_CTL_P)) 1882 return 1; 1883 if (data != 0 && data != ~(u64)0) 1884 return -1; 1885 vcpu->arch.mcg_ctl = data; 1886 break; 1887 default: 1888 if (msr >= MSR_IA32_MC0_CTL && 1889 msr < MSR_IA32_MCx_CTL(bank_num)) { 1890 u32 offset = msr - MSR_IA32_MC0_CTL; 1891 /* only 0 or all 1s can be written to IA32_MCi_CTL 1892 * some Linux kernels though clear bit 10 in bank 4 to 1893 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 1894 * this to avoid an uncatched #GP in the guest 1895 */ 1896 if ((offset & 0x3) == 0 && 1897 data != 0 && (data | (1 << 10)) != ~(u64)0) 1898 return -1; 1899 vcpu->arch.mce_banks[offset] = data; 1900 break; 1901 } 1902 return 1; 1903 } 1904 return 0; 1905 } 1906 1907 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 1908 { 1909 struct kvm *kvm = vcpu->kvm; 1910 int lm = is_long_mode(vcpu); 1911 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 1912 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 1913 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 1914 : kvm->arch.xen_hvm_config.blob_size_32; 1915 u32 page_num = data & ~PAGE_MASK; 1916 u64 page_addr = data & PAGE_MASK; 1917 u8 *page; 1918 int r; 1919 1920 r = -E2BIG; 1921 if (page_num >= blob_size) 1922 goto out; 1923 r = -ENOMEM; 1924 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 1925 if (IS_ERR(page)) { 1926 r = PTR_ERR(page); 1927 goto out; 1928 } 1929 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) 1930 goto out_free; 1931 r = 0; 1932 out_free: 1933 kfree(page); 1934 out: 1935 return r; 1936 } 1937 1938 static bool kvm_hv_hypercall_enabled(struct kvm *kvm) 1939 { 1940 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; 1941 } 1942 1943 static bool kvm_hv_msr_partition_wide(u32 msr) 1944 { 1945 bool r = false; 1946 switch (msr) { 1947 case HV_X64_MSR_GUEST_OS_ID: 1948 case HV_X64_MSR_HYPERCALL: 1949 case HV_X64_MSR_REFERENCE_TSC: 1950 case HV_X64_MSR_TIME_REF_COUNT: 1951 r = true; 1952 break; 1953 } 1954 1955 return r; 1956 } 1957 1958 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1959 { 1960 struct kvm *kvm = vcpu->kvm; 1961 1962 switch (msr) { 1963 case HV_X64_MSR_GUEST_OS_ID: 1964 kvm->arch.hv_guest_os_id = data; 1965 /* setting guest os id to zero disables hypercall page */ 1966 if (!kvm->arch.hv_guest_os_id) 1967 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; 1968 break; 1969 case HV_X64_MSR_HYPERCALL: { 1970 u64 gfn; 1971 unsigned long addr; 1972 u8 instructions[4]; 1973 1974 /* if guest os id is not set hypercall should remain disabled */ 1975 if (!kvm->arch.hv_guest_os_id) 1976 break; 1977 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { 1978 kvm->arch.hv_hypercall = data; 1979 break; 1980 } 1981 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; 1982 addr = gfn_to_hva(kvm, gfn); 1983 if (kvm_is_error_hva(addr)) 1984 return 1; 1985 kvm_x86_ops->patch_hypercall(vcpu, instructions); 1986 ((unsigned char *)instructions)[3] = 0xc3; /* ret */ 1987 if (__copy_to_user((void __user *)addr, instructions, 4)) 1988 return 1; 1989 kvm->arch.hv_hypercall = data; 1990 mark_page_dirty(kvm, gfn); 1991 break; 1992 } 1993 case HV_X64_MSR_REFERENCE_TSC: { 1994 u64 gfn; 1995 HV_REFERENCE_TSC_PAGE tsc_ref; 1996 memset(&tsc_ref, 0, sizeof(tsc_ref)); 1997 kvm->arch.hv_tsc_page = data; 1998 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE)) 1999 break; 2000 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT; 2001 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT, 2002 &tsc_ref, sizeof(tsc_ref))) 2003 return 1; 2004 mark_page_dirty(kvm, gfn); 2005 break; 2006 } 2007 default: 2008 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " 2009 "data 0x%llx\n", msr, data); 2010 return 1; 2011 } 2012 return 0; 2013 } 2014 2015 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) 2016 { 2017 switch (msr) { 2018 case HV_X64_MSR_APIC_ASSIST_PAGE: { 2019 u64 gfn; 2020 unsigned long addr; 2021 2022 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { 2023 vcpu->arch.hv_vapic = data; 2024 if (kvm_lapic_enable_pv_eoi(vcpu, 0)) 2025 return 1; 2026 break; 2027 } 2028 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT; 2029 addr = gfn_to_hva(vcpu->kvm, gfn); 2030 if (kvm_is_error_hva(addr)) 2031 return 1; 2032 if (__clear_user((void __user *)addr, PAGE_SIZE)) 2033 return 1; 2034 vcpu->arch.hv_vapic = data; 2035 mark_page_dirty(vcpu->kvm, gfn); 2036 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED)) 2037 return 1; 2038 break; 2039 } 2040 case HV_X64_MSR_EOI: 2041 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); 2042 case HV_X64_MSR_ICR: 2043 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); 2044 case HV_X64_MSR_TPR: 2045 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); 2046 default: 2047 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " 2048 "data 0x%llx\n", msr, data); 2049 return 1; 2050 } 2051 2052 return 0; 2053 } 2054 2055 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2056 { 2057 gpa_t gpa = data & ~0x3f; 2058 2059 /* Bits 2:5 are reserved, Should be zero */ 2060 if (data & 0x3c) 2061 return 1; 2062 2063 vcpu->arch.apf.msr_val = data; 2064 2065 if (!(data & KVM_ASYNC_PF_ENABLED)) { 2066 kvm_clear_async_pf_completion_queue(vcpu); 2067 kvm_async_pf_hash_reset(vcpu); 2068 return 0; 2069 } 2070 2071 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2072 sizeof(u32))) 2073 return 1; 2074 2075 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2076 kvm_async_pf_wakeup_all(vcpu); 2077 return 0; 2078 } 2079 2080 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2081 { 2082 vcpu->arch.pv_time_enabled = false; 2083 } 2084 2085 static void accumulate_steal_time(struct kvm_vcpu *vcpu) 2086 { 2087 u64 delta; 2088 2089 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2090 return; 2091 2092 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; 2093 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2094 vcpu->arch.st.accum_steal = delta; 2095 } 2096 2097 static void record_steal_time(struct kvm_vcpu *vcpu) 2098 { 2099 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2100 return; 2101 2102 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2103 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2104 return; 2105 2106 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; 2107 vcpu->arch.st.steal.version += 2; 2108 vcpu->arch.st.accum_steal = 0; 2109 2110 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2111 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2112 } 2113 2114 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2115 { 2116 bool pr = false; 2117 u32 msr = msr_info->index; 2118 u64 data = msr_info->data; 2119 2120 switch (msr) { 2121 case MSR_AMD64_NB_CFG: 2122 case MSR_IA32_UCODE_REV: 2123 case MSR_IA32_UCODE_WRITE: 2124 case MSR_VM_HSAVE_PA: 2125 case MSR_AMD64_PATCH_LOADER: 2126 case MSR_AMD64_BU_CFG2: 2127 break; 2128 2129 case MSR_EFER: 2130 return set_efer(vcpu, data); 2131 case MSR_K7_HWCR: 2132 data &= ~(u64)0x40; /* ignore flush filter disable */ 2133 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2134 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2135 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2136 if (data != 0) { 2137 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2138 data); 2139 return 1; 2140 } 2141 break; 2142 case MSR_FAM10H_MMIO_CONF_BASE: 2143 if (data != 0) { 2144 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2145 "0x%llx\n", data); 2146 return 1; 2147 } 2148 break; 2149 case MSR_IA32_DEBUGCTLMSR: 2150 if (!data) { 2151 /* We support the non-activated case already */ 2152 break; 2153 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2154 /* Values other than LBR and BTF are vendor-specific, 2155 thus reserved and should throw a #GP */ 2156 return 1; 2157 } 2158 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2159 __func__, data); 2160 break; 2161 case 0x200 ... 0x2ff: 2162 return set_msr_mtrr(vcpu, msr, data); 2163 case MSR_IA32_APICBASE: 2164 return kvm_set_apic_base(vcpu, msr_info); 2165 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2166 return kvm_x2apic_msr_write(vcpu, msr, data); 2167 case MSR_IA32_TSCDEADLINE: 2168 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2169 break; 2170 case MSR_IA32_TSC_ADJUST: 2171 if (guest_cpuid_has_tsc_adjust(vcpu)) { 2172 if (!msr_info->host_initiated) { 2173 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2174 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true); 2175 } 2176 vcpu->arch.ia32_tsc_adjust_msr = data; 2177 } 2178 break; 2179 case MSR_IA32_MISC_ENABLE: 2180 vcpu->arch.ia32_misc_enable_msr = data; 2181 break; 2182 case MSR_KVM_WALL_CLOCK_NEW: 2183 case MSR_KVM_WALL_CLOCK: 2184 vcpu->kvm->arch.wall_clock = data; 2185 kvm_write_wall_clock(vcpu->kvm, data); 2186 break; 2187 case MSR_KVM_SYSTEM_TIME_NEW: 2188 case MSR_KVM_SYSTEM_TIME: { 2189 u64 gpa_offset; 2190 struct kvm_arch *ka = &vcpu->kvm->arch; 2191 2192 kvmclock_reset(vcpu); 2193 2194 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2195 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2196 2197 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2198 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, 2199 &vcpu->requests); 2200 2201 ka->boot_vcpu_runs_old_kvmclock = tmp; 2202 } 2203 2204 vcpu->arch.time = data; 2205 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2206 2207 /* we verify if the enable bit is set... */ 2208 if (!(data & 1)) 2209 break; 2210 2211 gpa_offset = data & ~(PAGE_MASK | 1); 2212 2213 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2214 &vcpu->arch.pv_time, data & ~1ULL, 2215 sizeof(struct pvclock_vcpu_time_info))) 2216 vcpu->arch.pv_time_enabled = false; 2217 else 2218 vcpu->arch.pv_time_enabled = true; 2219 2220 break; 2221 } 2222 case MSR_KVM_ASYNC_PF_EN: 2223 if (kvm_pv_enable_async_pf(vcpu, data)) 2224 return 1; 2225 break; 2226 case MSR_KVM_STEAL_TIME: 2227 2228 if (unlikely(!sched_info_on())) 2229 return 1; 2230 2231 if (data & KVM_STEAL_RESERVED_MASK) 2232 return 1; 2233 2234 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2235 data & KVM_STEAL_VALID_BITS, 2236 sizeof(struct kvm_steal_time))) 2237 return 1; 2238 2239 vcpu->arch.st.msr_val = data; 2240 2241 if (!(data & KVM_MSR_ENABLED)) 2242 break; 2243 2244 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2245 2246 preempt_disable(); 2247 accumulate_steal_time(vcpu); 2248 preempt_enable(); 2249 2250 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2251 2252 break; 2253 case MSR_KVM_PV_EOI_EN: 2254 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2255 return 1; 2256 break; 2257 2258 case MSR_IA32_MCG_CTL: 2259 case MSR_IA32_MCG_STATUS: 2260 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2261 return set_msr_mce(vcpu, msr, data); 2262 2263 /* Performance counters are not protected by a CPUID bit, 2264 * so we should check all of them in the generic path for the sake of 2265 * cross vendor migration. 2266 * Writing a zero into the event select MSRs disables them, 2267 * which we perfectly emulate ;-). Any other value should be at least 2268 * reported, some guests depend on them. 2269 */ 2270 case MSR_K7_EVNTSEL0: 2271 case MSR_K7_EVNTSEL1: 2272 case MSR_K7_EVNTSEL2: 2273 case MSR_K7_EVNTSEL3: 2274 if (data != 0) 2275 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " 2276 "0x%x data 0x%llx\n", msr, data); 2277 break; 2278 /* at least RHEL 4 unconditionally writes to the perfctr registers, 2279 * so we ignore writes to make it happy. 2280 */ 2281 case MSR_K7_PERFCTR0: 2282 case MSR_K7_PERFCTR1: 2283 case MSR_K7_PERFCTR2: 2284 case MSR_K7_PERFCTR3: 2285 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " 2286 "0x%x data 0x%llx\n", msr, data); 2287 break; 2288 case MSR_P6_PERFCTR0: 2289 case MSR_P6_PERFCTR1: 2290 pr = true; 2291 case MSR_P6_EVNTSEL0: 2292 case MSR_P6_EVNTSEL1: 2293 if (kvm_pmu_msr(vcpu, msr)) 2294 return kvm_pmu_set_msr(vcpu, msr_info); 2295 2296 if (pr || data != 0) 2297 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2298 "0x%x data 0x%llx\n", msr, data); 2299 break; 2300 case MSR_K7_CLK_CTL: 2301 /* 2302 * Ignore all writes to this no longer documented MSR. 2303 * Writes are only relevant for old K7 processors, 2304 * all pre-dating SVM, but a recommended workaround from 2305 * AMD for these chips. It is possible to specify the 2306 * affected processor models on the command line, hence 2307 * the need to ignore the workaround. 2308 */ 2309 break; 2310 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2311 if (kvm_hv_msr_partition_wide(msr)) { 2312 int r; 2313 mutex_lock(&vcpu->kvm->lock); 2314 r = set_msr_hyperv_pw(vcpu, msr, data); 2315 mutex_unlock(&vcpu->kvm->lock); 2316 return r; 2317 } else 2318 return set_msr_hyperv(vcpu, msr, data); 2319 break; 2320 case MSR_IA32_BBL_CR_CTL3: 2321 /* Drop writes to this legacy MSR -- see rdmsr 2322 * counterpart for further detail. 2323 */ 2324 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); 2325 break; 2326 case MSR_AMD64_OSVW_ID_LENGTH: 2327 if (!guest_cpuid_has_osvw(vcpu)) 2328 return 1; 2329 vcpu->arch.osvw.length = data; 2330 break; 2331 case MSR_AMD64_OSVW_STATUS: 2332 if (!guest_cpuid_has_osvw(vcpu)) 2333 return 1; 2334 vcpu->arch.osvw.status = data; 2335 break; 2336 default: 2337 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2338 return xen_hvm_config(vcpu, data); 2339 if (kvm_pmu_msr(vcpu, msr)) 2340 return kvm_pmu_set_msr(vcpu, msr_info); 2341 if (!ignore_msrs) { 2342 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", 2343 msr, data); 2344 return 1; 2345 } else { 2346 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", 2347 msr, data); 2348 break; 2349 } 2350 } 2351 return 0; 2352 } 2353 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2354 2355 2356 /* 2357 * Reads an msr value (of 'msr_index') into 'pdata'. 2358 * Returns 0 on success, non-0 otherwise. 2359 * Assumes vcpu_load() was already called. 2360 */ 2361 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) 2362 { 2363 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); 2364 } 2365 EXPORT_SYMBOL_GPL(kvm_get_msr); 2366 2367 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2368 { 2369 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; 2370 2371 if (!msr_mtrr_valid(msr)) 2372 return 1; 2373 2374 if (msr == MSR_MTRRdefType) 2375 *pdata = vcpu->arch.mtrr_state.def_type + 2376 (vcpu->arch.mtrr_state.enabled << 10); 2377 else if (msr == MSR_MTRRfix64K_00000) 2378 *pdata = p[0]; 2379 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) 2380 *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; 2381 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) 2382 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; 2383 else if (msr == MSR_IA32_CR_PAT) 2384 *pdata = vcpu->arch.pat; 2385 else { /* Variable MTRRs */ 2386 int idx, is_mtrr_mask; 2387 u64 *pt; 2388 2389 idx = (msr - 0x200) / 2; 2390 is_mtrr_mask = msr - 0x200 - 2 * idx; 2391 if (!is_mtrr_mask) 2392 pt = 2393 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; 2394 else 2395 pt = 2396 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; 2397 *pdata = *pt; 2398 } 2399 2400 return 0; 2401 } 2402 2403 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2404 { 2405 u64 data; 2406 u64 mcg_cap = vcpu->arch.mcg_cap; 2407 unsigned bank_num = mcg_cap & 0xff; 2408 2409 switch (msr) { 2410 case MSR_IA32_P5_MC_ADDR: 2411 case MSR_IA32_P5_MC_TYPE: 2412 data = 0; 2413 break; 2414 case MSR_IA32_MCG_CAP: 2415 data = vcpu->arch.mcg_cap; 2416 break; 2417 case MSR_IA32_MCG_CTL: 2418 if (!(mcg_cap & MCG_CTL_P)) 2419 return 1; 2420 data = vcpu->arch.mcg_ctl; 2421 break; 2422 case MSR_IA32_MCG_STATUS: 2423 data = vcpu->arch.mcg_status; 2424 break; 2425 default: 2426 if (msr >= MSR_IA32_MC0_CTL && 2427 msr < MSR_IA32_MCx_CTL(bank_num)) { 2428 u32 offset = msr - MSR_IA32_MC0_CTL; 2429 data = vcpu->arch.mce_banks[offset]; 2430 break; 2431 } 2432 return 1; 2433 } 2434 *pdata = data; 2435 return 0; 2436 } 2437 2438 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2439 { 2440 u64 data = 0; 2441 struct kvm *kvm = vcpu->kvm; 2442 2443 switch (msr) { 2444 case HV_X64_MSR_GUEST_OS_ID: 2445 data = kvm->arch.hv_guest_os_id; 2446 break; 2447 case HV_X64_MSR_HYPERCALL: 2448 data = kvm->arch.hv_hypercall; 2449 break; 2450 case HV_X64_MSR_TIME_REF_COUNT: { 2451 data = 2452 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100); 2453 break; 2454 } 2455 case HV_X64_MSR_REFERENCE_TSC: 2456 data = kvm->arch.hv_tsc_page; 2457 break; 2458 default: 2459 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); 2460 return 1; 2461 } 2462 2463 *pdata = data; 2464 return 0; 2465 } 2466 2467 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2468 { 2469 u64 data = 0; 2470 2471 switch (msr) { 2472 case HV_X64_MSR_VP_INDEX: { 2473 int r; 2474 struct kvm_vcpu *v; 2475 kvm_for_each_vcpu(r, v, vcpu->kvm) { 2476 if (v == vcpu) { 2477 data = r; 2478 break; 2479 } 2480 } 2481 break; 2482 } 2483 case HV_X64_MSR_EOI: 2484 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); 2485 case HV_X64_MSR_ICR: 2486 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); 2487 case HV_X64_MSR_TPR: 2488 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); 2489 case HV_X64_MSR_APIC_ASSIST_PAGE: 2490 data = vcpu->arch.hv_vapic; 2491 break; 2492 default: 2493 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); 2494 return 1; 2495 } 2496 *pdata = data; 2497 return 0; 2498 } 2499 2500 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2501 { 2502 u64 data; 2503 2504 switch (msr) { 2505 case MSR_IA32_PLATFORM_ID: 2506 case MSR_IA32_EBL_CR_POWERON: 2507 case MSR_IA32_DEBUGCTLMSR: 2508 case MSR_IA32_LASTBRANCHFROMIP: 2509 case MSR_IA32_LASTBRANCHTOIP: 2510 case MSR_IA32_LASTINTFROMIP: 2511 case MSR_IA32_LASTINTTOIP: 2512 case MSR_K8_SYSCFG: 2513 case MSR_K7_HWCR: 2514 case MSR_VM_HSAVE_PA: 2515 case MSR_K7_EVNTSEL0: 2516 case MSR_K7_EVNTSEL1: 2517 case MSR_K7_EVNTSEL2: 2518 case MSR_K7_EVNTSEL3: 2519 case MSR_K7_PERFCTR0: 2520 case MSR_K7_PERFCTR1: 2521 case MSR_K7_PERFCTR2: 2522 case MSR_K7_PERFCTR3: 2523 case MSR_K8_INT_PENDING_MSG: 2524 case MSR_AMD64_NB_CFG: 2525 case MSR_FAM10H_MMIO_CONF_BASE: 2526 case MSR_AMD64_BU_CFG2: 2527 data = 0; 2528 break; 2529 case MSR_P6_PERFCTR0: 2530 case MSR_P6_PERFCTR1: 2531 case MSR_P6_EVNTSEL0: 2532 case MSR_P6_EVNTSEL1: 2533 if (kvm_pmu_msr(vcpu, msr)) 2534 return kvm_pmu_get_msr(vcpu, msr, pdata); 2535 data = 0; 2536 break; 2537 case MSR_IA32_UCODE_REV: 2538 data = 0x100000000ULL; 2539 break; 2540 case MSR_MTRRcap: 2541 data = 0x500 | KVM_NR_VAR_MTRR; 2542 break; 2543 case 0x200 ... 0x2ff: 2544 return get_msr_mtrr(vcpu, msr, pdata); 2545 case 0xcd: /* fsb frequency */ 2546 data = 3; 2547 break; 2548 /* 2549 * MSR_EBC_FREQUENCY_ID 2550 * Conservative value valid for even the basic CPU models. 2551 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2552 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2553 * and 266MHz for model 3, or 4. Set Core Clock 2554 * Frequency to System Bus Frequency Ratio to 1 (bits 2555 * 31:24) even though these are only valid for CPU 2556 * models > 2, however guests may end up dividing or 2557 * multiplying by zero otherwise. 2558 */ 2559 case MSR_EBC_FREQUENCY_ID: 2560 data = 1 << 24; 2561 break; 2562 case MSR_IA32_APICBASE: 2563 data = kvm_get_apic_base(vcpu); 2564 break; 2565 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2566 return kvm_x2apic_msr_read(vcpu, msr, pdata); 2567 break; 2568 case MSR_IA32_TSCDEADLINE: 2569 data = kvm_get_lapic_tscdeadline_msr(vcpu); 2570 break; 2571 case MSR_IA32_TSC_ADJUST: 2572 data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2573 break; 2574 case MSR_IA32_MISC_ENABLE: 2575 data = vcpu->arch.ia32_misc_enable_msr; 2576 break; 2577 case MSR_IA32_PERF_STATUS: 2578 /* TSC increment by tick */ 2579 data = 1000ULL; 2580 /* CPU multiplier */ 2581 data |= (((uint64_t)4ULL) << 40); 2582 break; 2583 case MSR_EFER: 2584 data = vcpu->arch.efer; 2585 break; 2586 case MSR_KVM_WALL_CLOCK: 2587 case MSR_KVM_WALL_CLOCK_NEW: 2588 data = vcpu->kvm->arch.wall_clock; 2589 break; 2590 case MSR_KVM_SYSTEM_TIME: 2591 case MSR_KVM_SYSTEM_TIME_NEW: 2592 data = vcpu->arch.time; 2593 break; 2594 case MSR_KVM_ASYNC_PF_EN: 2595 data = vcpu->arch.apf.msr_val; 2596 break; 2597 case MSR_KVM_STEAL_TIME: 2598 data = vcpu->arch.st.msr_val; 2599 break; 2600 case MSR_KVM_PV_EOI_EN: 2601 data = vcpu->arch.pv_eoi.msr_val; 2602 break; 2603 case MSR_IA32_P5_MC_ADDR: 2604 case MSR_IA32_P5_MC_TYPE: 2605 case MSR_IA32_MCG_CAP: 2606 case MSR_IA32_MCG_CTL: 2607 case MSR_IA32_MCG_STATUS: 2608 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2609 return get_msr_mce(vcpu, msr, pdata); 2610 case MSR_K7_CLK_CTL: 2611 /* 2612 * Provide expected ramp-up count for K7. All other 2613 * are set to zero, indicating minimum divisors for 2614 * every field. 2615 * 2616 * This prevents guest kernels on AMD host with CPU 2617 * type 6, model 8 and higher from exploding due to 2618 * the rdmsr failing. 2619 */ 2620 data = 0x20000000; 2621 break; 2622 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2623 if (kvm_hv_msr_partition_wide(msr)) { 2624 int r; 2625 mutex_lock(&vcpu->kvm->lock); 2626 r = get_msr_hyperv_pw(vcpu, msr, pdata); 2627 mutex_unlock(&vcpu->kvm->lock); 2628 return r; 2629 } else 2630 return get_msr_hyperv(vcpu, msr, pdata); 2631 break; 2632 case MSR_IA32_BBL_CR_CTL3: 2633 /* This legacy MSR exists but isn't fully documented in current 2634 * silicon. It is however accessed by winxp in very narrow 2635 * scenarios where it sets bit #19, itself documented as 2636 * a "reserved" bit. Best effort attempt to source coherent 2637 * read data here should the balance of the register be 2638 * interpreted by the guest: 2639 * 2640 * L2 cache control register 3: 64GB range, 256KB size, 2641 * enabled, latency 0x1, configured 2642 */ 2643 data = 0xbe702111; 2644 break; 2645 case MSR_AMD64_OSVW_ID_LENGTH: 2646 if (!guest_cpuid_has_osvw(vcpu)) 2647 return 1; 2648 data = vcpu->arch.osvw.length; 2649 break; 2650 case MSR_AMD64_OSVW_STATUS: 2651 if (!guest_cpuid_has_osvw(vcpu)) 2652 return 1; 2653 data = vcpu->arch.osvw.status; 2654 break; 2655 default: 2656 if (kvm_pmu_msr(vcpu, msr)) 2657 return kvm_pmu_get_msr(vcpu, msr, pdata); 2658 if (!ignore_msrs) { 2659 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); 2660 return 1; 2661 } else { 2662 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); 2663 data = 0; 2664 } 2665 break; 2666 } 2667 *pdata = data; 2668 return 0; 2669 } 2670 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2671 2672 /* 2673 * Read or write a bunch of msrs. All parameters are kernel addresses. 2674 * 2675 * @return number of msrs set successfully. 2676 */ 2677 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2678 struct kvm_msr_entry *entries, 2679 int (*do_msr)(struct kvm_vcpu *vcpu, 2680 unsigned index, u64 *data)) 2681 { 2682 int i, idx; 2683 2684 idx = srcu_read_lock(&vcpu->kvm->srcu); 2685 for (i = 0; i < msrs->nmsrs; ++i) 2686 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2687 break; 2688 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2689 2690 return i; 2691 } 2692 2693 /* 2694 * Read or write a bunch of msrs. Parameters are user addresses. 2695 * 2696 * @return number of msrs set successfully. 2697 */ 2698 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2699 int (*do_msr)(struct kvm_vcpu *vcpu, 2700 unsigned index, u64 *data), 2701 int writeback) 2702 { 2703 struct kvm_msrs msrs; 2704 struct kvm_msr_entry *entries; 2705 int r, n; 2706 unsigned size; 2707 2708 r = -EFAULT; 2709 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2710 goto out; 2711 2712 r = -E2BIG; 2713 if (msrs.nmsrs >= MAX_IO_MSRS) 2714 goto out; 2715 2716 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2717 entries = memdup_user(user_msrs->entries, size); 2718 if (IS_ERR(entries)) { 2719 r = PTR_ERR(entries); 2720 goto out; 2721 } 2722 2723 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2724 if (r < 0) 2725 goto out_free; 2726 2727 r = -EFAULT; 2728 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2729 goto out_free; 2730 2731 r = n; 2732 2733 out_free: 2734 kfree(entries); 2735 out: 2736 return r; 2737 } 2738 2739 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2740 { 2741 int r; 2742 2743 switch (ext) { 2744 case KVM_CAP_IRQCHIP: 2745 case KVM_CAP_HLT: 2746 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2747 case KVM_CAP_SET_TSS_ADDR: 2748 case KVM_CAP_EXT_CPUID: 2749 case KVM_CAP_EXT_EMUL_CPUID: 2750 case KVM_CAP_CLOCKSOURCE: 2751 case KVM_CAP_PIT: 2752 case KVM_CAP_NOP_IO_DELAY: 2753 case KVM_CAP_MP_STATE: 2754 case KVM_CAP_SYNC_MMU: 2755 case KVM_CAP_USER_NMI: 2756 case KVM_CAP_REINJECT_CONTROL: 2757 case KVM_CAP_IRQ_INJECT_STATUS: 2758 case KVM_CAP_IOEVENTFD: 2759 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2760 case KVM_CAP_PIT2: 2761 case KVM_CAP_PIT_STATE2: 2762 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2763 case KVM_CAP_XEN_HVM: 2764 case KVM_CAP_ADJUST_CLOCK: 2765 case KVM_CAP_VCPU_EVENTS: 2766 case KVM_CAP_HYPERV: 2767 case KVM_CAP_HYPERV_VAPIC: 2768 case KVM_CAP_HYPERV_SPIN: 2769 case KVM_CAP_PCI_SEGMENT: 2770 case KVM_CAP_DEBUGREGS: 2771 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2772 case KVM_CAP_XSAVE: 2773 case KVM_CAP_ASYNC_PF: 2774 case KVM_CAP_GET_TSC_KHZ: 2775 case KVM_CAP_KVMCLOCK_CTRL: 2776 case KVM_CAP_READONLY_MEM: 2777 case KVM_CAP_HYPERV_TIME: 2778 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2779 case KVM_CAP_TSC_DEADLINE_TIMER: 2780 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2781 case KVM_CAP_ASSIGN_DEV_IRQ: 2782 case KVM_CAP_PCI_2_3: 2783 #endif 2784 r = 1; 2785 break; 2786 case KVM_CAP_COALESCED_MMIO: 2787 r = KVM_COALESCED_MMIO_PAGE_OFFSET; 2788 break; 2789 case KVM_CAP_VAPIC: 2790 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2791 break; 2792 case KVM_CAP_NR_VCPUS: 2793 r = KVM_SOFT_MAX_VCPUS; 2794 break; 2795 case KVM_CAP_MAX_VCPUS: 2796 r = KVM_MAX_VCPUS; 2797 break; 2798 case KVM_CAP_NR_MEMSLOTS: 2799 r = KVM_USER_MEM_SLOTS; 2800 break; 2801 case KVM_CAP_PV_MMU: /* obsolete */ 2802 r = 0; 2803 break; 2804 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2805 case KVM_CAP_IOMMU: 2806 r = iommu_present(&pci_bus_type); 2807 break; 2808 #endif 2809 case KVM_CAP_MCE: 2810 r = KVM_MAX_MCE_BANKS; 2811 break; 2812 case KVM_CAP_XCRS: 2813 r = cpu_has_xsave; 2814 break; 2815 case KVM_CAP_TSC_CONTROL: 2816 r = kvm_has_tsc_control; 2817 break; 2818 default: 2819 r = 0; 2820 break; 2821 } 2822 return r; 2823 2824 } 2825 2826 long kvm_arch_dev_ioctl(struct file *filp, 2827 unsigned int ioctl, unsigned long arg) 2828 { 2829 void __user *argp = (void __user *)arg; 2830 long r; 2831 2832 switch (ioctl) { 2833 case KVM_GET_MSR_INDEX_LIST: { 2834 struct kvm_msr_list __user *user_msr_list = argp; 2835 struct kvm_msr_list msr_list; 2836 unsigned n; 2837 2838 r = -EFAULT; 2839 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2840 goto out; 2841 n = msr_list.nmsrs; 2842 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); 2843 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2844 goto out; 2845 r = -E2BIG; 2846 if (n < msr_list.nmsrs) 2847 goto out; 2848 r = -EFAULT; 2849 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2850 num_msrs_to_save * sizeof(u32))) 2851 goto out; 2852 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2853 &emulated_msrs, 2854 ARRAY_SIZE(emulated_msrs) * sizeof(u32))) 2855 goto out; 2856 r = 0; 2857 break; 2858 } 2859 case KVM_GET_SUPPORTED_CPUID: 2860 case KVM_GET_EMULATED_CPUID: { 2861 struct kvm_cpuid2 __user *cpuid_arg = argp; 2862 struct kvm_cpuid2 cpuid; 2863 2864 r = -EFAULT; 2865 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2866 goto out; 2867 2868 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2869 ioctl); 2870 if (r) 2871 goto out; 2872 2873 r = -EFAULT; 2874 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2875 goto out; 2876 r = 0; 2877 break; 2878 } 2879 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2880 u64 mce_cap; 2881 2882 mce_cap = KVM_MCE_CAP_SUPPORTED; 2883 r = -EFAULT; 2884 if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) 2885 goto out; 2886 r = 0; 2887 break; 2888 } 2889 default: 2890 r = -EINVAL; 2891 } 2892 out: 2893 return r; 2894 } 2895 2896 static void wbinvd_ipi(void *garbage) 2897 { 2898 wbinvd(); 2899 } 2900 2901 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 2902 { 2903 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 2904 } 2905 2906 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 2907 { 2908 /* Address WBINVD may be executed by guest */ 2909 if (need_emulate_wbinvd(vcpu)) { 2910 if (kvm_x86_ops->has_wbinvd_exit()) 2911 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 2912 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 2913 smp_call_function_single(vcpu->cpu, 2914 wbinvd_ipi, NULL, 1); 2915 } 2916 2917 kvm_x86_ops->vcpu_load(vcpu, cpu); 2918 2919 /* Apply any externally detected TSC adjustments (due to suspend) */ 2920 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 2921 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 2922 vcpu->arch.tsc_offset_adjustment = 0; 2923 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2924 } 2925 2926 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { 2927 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 2928 native_read_tsc() - vcpu->arch.last_host_tsc; 2929 if (tsc_delta < 0) 2930 mark_tsc_unstable("KVM discovered backwards TSC"); 2931 if (check_tsc_unstable()) { 2932 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu, 2933 vcpu->arch.last_guest_tsc); 2934 kvm_x86_ops->write_tsc_offset(vcpu, offset); 2935 vcpu->arch.tsc_catchup = 1; 2936 } 2937 /* 2938 * On a host with synchronized TSC, there is no need to update 2939 * kvmclock on vcpu->cpu migration 2940 */ 2941 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 2942 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2943 if (vcpu->cpu != cpu) 2944 kvm_migrate_timers(vcpu); 2945 vcpu->cpu = cpu; 2946 } 2947 2948 accumulate_steal_time(vcpu); 2949 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2950 } 2951 2952 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 2953 { 2954 kvm_x86_ops->vcpu_put(vcpu); 2955 kvm_put_guest_fpu(vcpu); 2956 vcpu->arch.last_host_tsc = native_read_tsc(); 2957 } 2958 2959 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 2960 struct kvm_lapic_state *s) 2961 { 2962 kvm_x86_ops->sync_pir_to_irr(vcpu); 2963 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); 2964 2965 return 0; 2966 } 2967 2968 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 2969 struct kvm_lapic_state *s) 2970 { 2971 kvm_apic_post_state_restore(vcpu, s); 2972 update_cr8_intercept(vcpu); 2973 2974 return 0; 2975 } 2976 2977 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 2978 struct kvm_interrupt *irq) 2979 { 2980 if (irq->irq >= KVM_NR_INTERRUPTS) 2981 return -EINVAL; 2982 if (irqchip_in_kernel(vcpu->kvm)) 2983 return -ENXIO; 2984 2985 kvm_queue_interrupt(vcpu, irq->irq, false); 2986 kvm_make_request(KVM_REQ_EVENT, vcpu); 2987 2988 return 0; 2989 } 2990 2991 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 2992 { 2993 kvm_inject_nmi(vcpu); 2994 2995 return 0; 2996 } 2997 2998 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 2999 struct kvm_tpr_access_ctl *tac) 3000 { 3001 if (tac->flags) 3002 return -EINVAL; 3003 vcpu->arch.tpr_access_reporting = !!tac->enabled; 3004 return 0; 3005 } 3006 3007 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 3008 u64 mcg_cap) 3009 { 3010 int r; 3011 unsigned bank_num = mcg_cap & 0xff, bank; 3012 3013 r = -EINVAL; 3014 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 3015 goto out; 3016 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) 3017 goto out; 3018 r = 0; 3019 vcpu->arch.mcg_cap = mcg_cap; 3020 /* Init IA32_MCG_CTL to all 1s */ 3021 if (mcg_cap & MCG_CTL_P) 3022 vcpu->arch.mcg_ctl = ~(u64)0; 3023 /* Init IA32_MCi_CTL to all 1s */ 3024 for (bank = 0; bank < bank_num; bank++) 3025 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 3026 out: 3027 return r; 3028 } 3029 3030 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 3031 struct kvm_x86_mce *mce) 3032 { 3033 u64 mcg_cap = vcpu->arch.mcg_cap; 3034 unsigned bank_num = mcg_cap & 0xff; 3035 u64 *banks = vcpu->arch.mce_banks; 3036 3037 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 3038 return -EINVAL; 3039 /* 3040 * if IA32_MCG_CTL is not all 1s, the uncorrected error 3041 * reporting is disabled 3042 */ 3043 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 3044 vcpu->arch.mcg_ctl != ~(u64)0) 3045 return 0; 3046 banks += 4 * mce->bank; 3047 /* 3048 * if IA32_MCi_CTL is not all 1s, the uncorrected error 3049 * reporting is disabled for the bank 3050 */ 3051 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 3052 return 0; 3053 if (mce->status & MCI_STATUS_UC) { 3054 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 3055 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 3056 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 3057 return 0; 3058 } 3059 if (banks[1] & MCI_STATUS_VAL) 3060 mce->status |= MCI_STATUS_OVER; 3061 banks[2] = mce->addr; 3062 banks[3] = mce->misc; 3063 vcpu->arch.mcg_status = mce->mcg_status; 3064 banks[1] = mce->status; 3065 kvm_queue_exception(vcpu, MC_VECTOR); 3066 } else if (!(banks[1] & MCI_STATUS_VAL) 3067 || !(banks[1] & MCI_STATUS_UC)) { 3068 if (banks[1] & MCI_STATUS_VAL) 3069 mce->status |= MCI_STATUS_OVER; 3070 banks[2] = mce->addr; 3071 banks[3] = mce->misc; 3072 banks[1] = mce->status; 3073 } else 3074 banks[1] |= MCI_STATUS_OVER; 3075 return 0; 3076 } 3077 3078 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 3079 struct kvm_vcpu_events *events) 3080 { 3081 process_nmi(vcpu); 3082 events->exception.injected = 3083 vcpu->arch.exception.pending && 3084 !kvm_exception_is_soft(vcpu->arch.exception.nr); 3085 events->exception.nr = vcpu->arch.exception.nr; 3086 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 3087 events->exception.pad = 0; 3088 events->exception.error_code = vcpu->arch.exception.error_code; 3089 3090 events->interrupt.injected = 3091 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; 3092 events->interrupt.nr = vcpu->arch.interrupt.nr; 3093 events->interrupt.soft = 0; 3094 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 3095 3096 events->nmi.injected = vcpu->arch.nmi_injected; 3097 events->nmi.pending = vcpu->arch.nmi_pending != 0; 3098 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 3099 events->nmi.pad = 0; 3100 3101 events->sipi_vector = 0; /* never valid when reporting to user space */ 3102 3103 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 3104 | KVM_VCPUEVENT_VALID_SHADOW); 3105 memset(&events->reserved, 0, sizeof(events->reserved)); 3106 } 3107 3108 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 3109 struct kvm_vcpu_events *events) 3110 { 3111 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 3112 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 3113 | KVM_VCPUEVENT_VALID_SHADOW)) 3114 return -EINVAL; 3115 3116 process_nmi(vcpu); 3117 vcpu->arch.exception.pending = events->exception.injected; 3118 vcpu->arch.exception.nr = events->exception.nr; 3119 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 3120 vcpu->arch.exception.error_code = events->exception.error_code; 3121 3122 vcpu->arch.interrupt.pending = events->interrupt.injected; 3123 vcpu->arch.interrupt.nr = events->interrupt.nr; 3124 vcpu->arch.interrupt.soft = events->interrupt.soft; 3125 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3126 kvm_x86_ops->set_interrupt_shadow(vcpu, 3127 events->interrupt.shadow); 3128 3129 vcpu->arch.nmi_injected = events->nmi.injected; 3130 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3131 vcpu->arch.nmi_pending = events->nmi.pending; 3132 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 3133 3134 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3135 kvm_vcpu_has_lapic(vcpu)) 3136 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3137 3138 kvm_make_request(KVM_REQ_EVENT, vcpu); 3139 3140 return 0; 3141 } 3142 3143 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3144 struct kvm_debugregs *dbgregs) 3145 { 3146 unsigned long val; 3147 3148 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3149 kvm_get_dr(vcpu, 6, &val); 3150 dbgregs->dr6 = val; 3151 dbgregs->dr7 = vcpu->arch.dr7; 3152 dbgregs->flags = 0; 3153 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3154 } 3155 3156 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3157 struct kvm_debugregs *dbgregs) 3158 { 3159 if (dbgregs->flags) 3160 return -EINVAL; 3161 3162 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3163 kvm_update_dr0123(vcpu); 3164 vcpu->arch.dr6 = dbgregs->dr6; 3165 kvm_update_dr6(vcpu); 3166 vcpu->arch.dr7 = dbgregs->dr7; 3167 kvm_update_dr7(vcpu); 3168 3169 return 0; 3170 } 3171 3172 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3173 3174 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3175 { 3176 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave; 3177 u64 xstate_bv = xsave->xsave_hdr.xstate_bv; 3178 u64 valid; 3179 3180 /* 3181 * Copy legacy XSAVE area, to avoid complications with CPUID 3182 * leaves 0 and 1 in the loop below. 3183 */ 3184 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3185 3186 /* Set XSTATE_BV */ 3187 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3188 3189 /* 3190 * Copy each region from the possibly compacted offset to the 3191 * non-compacted offset. 3192 */ 3193 valid = xstate_bv & ~XSTATE_FPSSE; 3194 while (valid) { 3195 u64 feature = valid & -valid; 3196 int index = fls64(feature) - 1; 3197 void *src = get_xsave_addr(xsave, feature); 3198 3199 if (src) { 3200 u32 size, offset, ecx, edx; 3201 cpuid_count(XSTATE_CPUID, index, 3202 &size, &offset, &ecx, &edx); 3203 memcpy(dest + offset, src, size); 3204 } 3205 3206 valid -= feature; 3207 } 3208 } 3209 3210 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3211 { 3212 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave; 3213 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3214 u64 valid; 3215 3216 /* 3217 * Copy legacy XSAVE area, to avoid complications with CPUID 3218 * leaves 0 and 1 in the loop below. 3219 */ 3220 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3221 3222 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3223 xsave->xsave_hdr.xstate_bv = xstate_bv; 3224 if (cpu_has_xsaves) 3225 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3226 3227 /* 3228 * Copy each region from the non-compacted offset to the 3229 * possibly compacted offset. 3230 */ 3231 valid = xstate_bv & ~XSTATE_FPSSE; 3232 while (valid) { 3233 u64 feature = valid & -valid; 3234 int index = fls64(feature) - 1; 3235 void *dest = get_xsave_addr(xsave, feature); 3236 3237 if (dest) { 3238 u32 size, offset, ecx, edx; 3239 cpuid_count(XSTATE_CPUID, index, 3240 &size, &offset, &ecx, &edx); 3241 memcpy(dest, src + offset, size); 3242 } else 3243 WARN_ON_ONCE(1); 3244 3245 valid -= feature; 3246 } 3247 } 3248 3249 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3250 struct kvm_xsave *guest_xsave) 3251 { 3252 if (cpu_has_xsave) { 3253 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3254 fill_xsave((u8 *) guest_xsave->region, vcpu); 3255 } else { 3256 memcpy(guest_xsave->region, 3257 &vcpu->arch.guest_fpu.state->fxsave, 3258 sizeof(struct i387_fxsave_struct)); 3259 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3260 XSTATE_FPSSE; 3261 } 3262 } 3263 3264 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3265 struct kvm_xsave *guest_xsave) 3266 { 3267 u64 xstate_bv = 3268 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3269 3270 if (cpu_has_xsave) { 3271 /* 3272 * Here we allow setting states that are not present in 3273 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3274 * with old userspace. 3275 */ 3276 if (xstate_bv & ~kvm_supported_xcr0()) 3277 return -EINVAL; 3278 load_xsave(vcpu, (u8 *)guest_xsave->region); 3279 } else { 3280 if (xstate_bv & ~XSTATE_FPSSE) 3281 return -EINVAL; 3282 memcpy(&vcpu->arch.guest_fpu.state->fxsave, 3283 guest_xsave->region, sizeof(struct i387_fxsave_struct)); 3284 } 3285 return 0; 3286 } 3287 3288 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3289 struct kvm_xcrs *guest_xcrs) 3290 { 3291 if (!cpu_has_xsave) { 3292 guest_xcrs->nr_xcrs = 0; 3293 return; 3294 } 3295 3296 guest_xcrs->nr_xcrs = 1; 3297 guest_xcrs->flags = 0; 3298 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3299 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3300 } 3301 3302 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3303 struct kvm_xcrs *guest_xcrs) 3304 { 3305 int i, r = 0; 3306 3307 if (!cpu_has_xsave) 3308 return -EINVAL; 3309 3310 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3311 return -EINVAL; 3312 3313 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3314 /* Only support XCR0 currently */ 3315 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3316 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3317 guest_xcrs->xcrs[i].value); 3318 break; 3319 } 3320 if (r) 3321 r = -EINVAL; 3322 return r; 3323 } 3324 3325 /* 3326 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3327 * stopped by the hypervisor. This function will be called from the host only. 3328 * EINVAL is returned when the host attempts to set the flag for a guest that 3329 * does not support pv clocks. 3330 */ 3331 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3332 { 3333 if (!vcpu->arch.pv_time_enabled) 3334 return -EINVAL; 3335 vcpu->arch.pvclock_set_guest_stopped_request = true; 3336 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3337 return 0; 3338 } 3339 3340 long kvm_arch_vcpu_ioctl(struct file *filp, 3341 unsigned int ioctl, unsigned long arg) 3342 { 3343 struct kvm_vcpu *vcpu = filp->private_data; 3344 void __user *argp = (void __user *)arg; 3345 int r; 3346 union { 3347 struct kvm_lapic_state *lapic; 3348 struct kvm_xsave *xsave; 3349 struct kvm_xcrs *xcrs; 3350 void *buffer; 3351 } u; 3352 3353 u.buffer = NULL; 3354 switch (ioctl) { 3355 case KVM_GET_LAPIC: { 3356 r = -EINVAL; 3357 if (!vcpu->arch.apic) 3358 goto out; 3359 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3360 3361 r = -ENOMEM; 3362 if (!u.lapic) 3363 goto out; 3364 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3365 if (r) 3366 goto out; 3367 r = -EFAULT; 3368 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3369 goto out; 3370 r = 0; 3371 break; 3372 } 3373 case KVM_SET_LAPIC: { 3374 r = -EINVAL; 3375 if (!vcpu->arch.apic) 3376 goto out; 3377 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3378 if (IS_ERR(u.lapic)) 3379 return PTR_ERR(u.lapic); 3380 3381 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3382 break; 3383 } 3384 case KVM_INTERRUPT: { 3385 struct kvm_interrupt irq; 3386 3387 r = -EFAULT; 3388 if (copy_from_user(&irq, argp, sizeof irq)) 3389 goto out; 3390 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3391 break; 3392 } 3393 case KVM_NMI: { 3394 r = kvm_vcpu_ioctl_nmi(vcpu); 3395 break; 3396 } 3397 case KVM_SET_CPUID: { 3398 struct kvm_cpuid __user *cpuid_arg = argp; 3399 struct kvm_cpuid cpuid; 3400 3401 r = -EFAULT; 3402 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3403 goto out; 3404 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3405 break; 3406 } 3407 case KVM_SET_CPUID2: { 3408 struct kvm_cpuid2 __user *cpuid_arg = argp; 3409 struct kvm_cpuid2 cpuid; 3410 3411 r = -EFAULT; 3412 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3413 goto out; 3414 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3415 cpuid_arg->entries); 3416 break; 3417 } 3418 case KVM_GET_CPUID2: { 3419 struct kvm_cpuid2 __user *cpuid_arg = argp; 3420 struct kvm_cpuid2 cpuid; 3421 3422 r = -EFAULT; 3423 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3424 goto out; 3425 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3426 cpuid_arg->entries); 3427 if (r) 3428 goto out; 3429 r = -EFAULT; 3430 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3431 goto out; 3432 r = 0; 3433 break; 3434 } 3435 case KVM_GET_MSRS: 3436 r = msr_io(vcpu, argp, kvm_get_msr, 1); 3437 break; 3438 case KVM_SET_MSRS: 3439 r = msr_io(vcpu, argp, do_set_msr, 0); 3440 break; 3441 case KVM_TPR_ACCESS_REPORTING: { 3442 struct kvm_tpr_access_ctl tac; 3443 3444 r = -EFAULT; 3445 if (copy_from_user(&tac, argp, sizeof tac)) 3446 goto out; 3447 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3448 if (r) 3449 goto out; 3450 r = -EFAULT; 3451 if (copy_to_user(argp, &tac, sizeof tac)) 3452 goto out; 3453 r = 0; 3454 break; 3455 }; 3456 case KVM_SET_VAPIC_ADDR: { 3457 struct kvm_vapic_addr va; 3458 3459 r = -EINVAL; 3460 if (!irqchip_in_kernel(vcpu->kvm)) 3461 goto out; 3462 r = -EFAULT; 3463 if (copy_from_user(&va, argp, sizeof va)) 3464 goto out; 3465 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3466 break; 3467 } 3468 case KVM_X86_SETUP_MCE: { 3469 u64 mcg_cap; 3470 3471 r = -EFAULT; 3472 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3473 goto out; 3474 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3475 break; 3476 } 3477 case KVM_X86_SET_MCE: { 3478 struct kvm_x86_mce mce; 3479 3480 r = -EFAULT; 3481 if (copy_from_user(&mce, argp, sizeof mce)) 3482 goto out; 3483 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3484 break; 3485 } 3486 case KVM_GET_VCPU_EVENTS: { 3487 struct kvm_vcpu_events events; 3488 3489 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3490 3491 r = -EFAULT; 3492 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3493 break; 3494 r = 0; 3495 break; 3496 } 3497 case KVM_SET_VCPU_EVENTS: { 3498 struct kvm_vcpu_events events; 3499 3500 r = -EFAULT; 3501 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3502 break; 3503 3504 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3505 break; 3506 } 3507 case KVM_GET_DEBUGREGS: { 3508 struct kvm_debugregs dbgregs; 3509 3510 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3511 3512 r = -EFAULT; 3513 if (copy_to_user(argp, &dbgregs, 3514 sizeof(struct kvm_debugregs))) 3515 break; 3516 r = 0; 3517 break; 3518 } 3519 case KVM_SET_DEBUGREGS: { 3520 struct kvm_debugregs dbgregs; 3521 3522 r = -EFAULT; 3523 if (copy_from_user(&dbgregs, argp, 3524 sizeof(struct kvm_debugregs))) 3525 break; 3526 3527 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3528 break; 3529 } 3530 case KVM_GET_XSAVE: { 3531 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3532 r = -ENOMEM; 3533 if (!u.xsave) 3534 break; 3535 3536 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3537 3538 r = -EFAULT; 3539 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3540 break; 3541 r = 0; 3542 break; 3543 } 3544 case KVM_SET_XSAVE: { 3545 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3546 if (IS_ERR(u.xsave)) 3547 return PTR_ERR(u.xsave); 3548 3549 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3550 break; 3551 } 3552 case KVM_GET_XCRS: { 3553 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3554 r = -ENOMEM; 3555 if (!u.xcrs) 3556 break; 3557 3558 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3559 3560 r = -EFAULT; 3561 if (copy_to_user(argp, u.xcrs, 3562 sizeof(struct kvm_xcrs))) 3563 break; 3564 r = 0; 3565 break; 3566 } 3567 case KVM_SET_XCRS: { 3568 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3569 if (IS_ERR(u.xcrs)) 3570 return PTR_ERR(u.xcrs); 3571 3572 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3573 break; 3574 } 3575 case KVM_SET_TSC_KHZ: { 3576 u32 user_tsc_khz; 3577 3578 r = -EINVAL; 3579 user_tsc_khz = (u32)arg; 3580 3581 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3582 goto out; 3583 3584 if (user_tsc_khz == 0) 3585 user_tsc_khz = tsc_khz; 3586 3587 kvm_set_tsc_khz(vcpu, user_tsc_khz); 3588 3589 r = 0; 3590 goto out; 3591 } 3592 case KVM_GET_TSC_KHZ: { 3593 r = vcpu->arch.virtual_tsc_khz; 3594 goto out; 3595 } 3596 case KVM_KVMCLOCK_CTRL: { 3597 r = kvm_set_guest_paused(vcpu); 3598 goto out; 3599 } 3600 default: 3601 r = -EINVAL; 3602 } 3603 out: 3604 kfree(u.buffer); 3605 return r; 3606 } 3607 3608 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3609 { 3610 return VM_FAULT_SIGBUS; 3611 } 3612 3613 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3614 { 3615 int ret; 3616 3617 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3618 return -EINVAL; 3619 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3620 return ret; 3621 } 3622 3623 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3624 u64 ident_addr) 3625 { 3626 kvm->arch.ept_identity_map_addr = ident_addr; 3627 return 0; 3628 } 3629 3630 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3631 u32 kvm_nr_mmu_pages) 3632 { 3633 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3634 return -EINVAL; 3635 3636 mutex_lock(&kvm->slots_lock); 3637 3638 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3639 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3640 3641 mutex_unlock(&kvm->slots_lock); 3642 return 0; 3643 } 3644 3645 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 3646 { 3647 return kvm->arch.n_max_mmu_pages; 3648 } 3649 3650 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3651 { 3652 int r; 3653 3654 r = 0; 3655 switch (chip->chip_id) { 3656 case KVM_IRQCHIP_PIC_MASTER: 3657 memcpy(&chip->chip.pic, 3658 &pic_irqchip(kvm)->pics[0], 3659 sizeof(struct kvm_pic_state)); 3660 break; 3661 case KVM_IRQCHIP_PIC_SLAVE: 3662 memcpy(&chip->chip.pic, 3663 &pic_irqchip(kvm)->pics[1], 3664 sizeof(struct kvm_pic_state)); 3665 break; 3666 case KVM_IRQCHIP_IOAPIC: 3667 r = kvm_get_ioapic(kvm, &chip->chip.ioapic); 3668 break; 3669 default: 3670 r = -EINVAL; 3671 break; 3672 } 3673 return r; 3674 } 3675 3676 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3677 { 3678 int r; 3679 3680 r = 0; 3681 switch (chip->chip_id) { 3682 case KVM_IRQCHIP_PIC_MASTER: 3683 spin_lock(&pic_irqchip(kvm)->lock); 3684 memcpy(&pic_irqchip(kvm)->pics[0], 3685 &chip->chip.pic, 3686 sizeof(struct kvm_pic_state)); 3687 spin_unlock(&pic_irqchip(kvm)->lock); 3688 break; 3689 case KVM_IRQCHIP_PIC_SLAVE: 3690 spin_lock(&pic_irqchip(kvm)->lock); 3691 memcpy(&pic_irqchip(kvm)->pics[1], 3692 &chip->chip.pic, 3693 sizeof(struct kvm_pic_state)); 3694 spin_unlock(&pic_irqchip(kvm)->lock); 3695 break; 3696 case KVM_IRQCHIP_IOAPIC: 3697 r = kvm_set_ioapic(kvm, &chip->chip.ioapic); 3698 break; 3699 default: 3700 r = -EINVAL; 3701 break; 3702 } 3703 kvm_pic_update_irq(pic_irqchip(kvm)); 3704 return r; 3705 } 3706 3707 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3708 { 3709 int r = 0; 3710 3711 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3712 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); 3713 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3714 return r; 3715 } 3716 3717 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3718 { 3719 int r = 0; 3720 3721 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3722 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); 3723 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); 3724 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3725 return r; 3726 } 3727 3728 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3729 { 3730 int r = 0; 3731 3732 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3733 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 3734 sizeof(ps->channels)); 3735 ps->flags = kvm->arch.vpit->pit_state.flags; 3736 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3737 memset(&ps->reserved, 0, sizeof(ps->reserved)); 3738 return r; 3739 } 3740 3741 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3742 { 3743 int r = 0, start = 0; 3744 u32 prev_legacy, cur_legacy; 3745 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3746 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 3747 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 3748 if (!prev_legacy && cur_legacy) 3749 start = 1; 3750 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, 3751 sizeof(kvm->arch.vpit->pit_state.channels)); 3752 kvm->arch.vpit->pit_state.flags = ps->flags; 3753 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); 3754 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3755 return r; 3756 } 3757 3758 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 3759 struct kvm_reinject_control *control) 3760 { 3761 if (!kvm->arch.vpit) 3762 return -ENXIO; 3763 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3764 kvm->arch.vpit->pit_state.reinject = control->pit_reinject; 3765 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3766 return 0; 3767 } 3768 3769 /** 3770 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 3771 * @kvm: kvm instance 3772 * @log: slot id and address to which we copy the log 3773 * 3774 * Steps 1-4 below provide general overview of dirty page logging. See 3775 * kvm_get_dirty_log_protect() function description for additional details. 3776 * 3777 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 3778 * always flush the TLB (step 4) even if previous step failed and the dirty 3779 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 3780 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 3781 * writes will be marked dirty for next log read. 3782 * 3783 * 1. Take a snapshot of the bit and clear it if needed. 3784 * 2. Write protect the corresponding page. 3785 * 3. Copy the snapshot to the userspace. 3786 * 4. Flush TLB's if needed. 3787 */ 3788 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 3789 { 3790 bool is_dirty = false; 3791 int r; 3792 3793 mutex_lock(&kvm->slots_lock); 3794 3795 /* 3796 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 3797 */ 3798 if (kvm_x86_ops->flush_log_dirty) 3799 kvm_x86_ops->flush_log_dirty(kvm); 3800 3801 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 3802 3803 /* 3804 * All the TLBs can be flushed out of mmu lock, see the comments in 3805 * kvm_mmu_slot_remove_write_access(). 3806 */ 3807 lockdep_assert_held(&kvm->slots_lock); 3808 if (is_dirty) 3809 kvm_flush_remote_tlbs(kvm); 3810 3811 mutex_unlock(&kvm->slots_lock); 3812 return r; 3813 } 3814 3815 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 3816 bool line_status) 3817 { 3818 if (!irqchip_in_kernel(kvm)) 3819 return -ENXIO; 3820 3821 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 3822 irq_event->irq, irq_event->level, 3823 line_status); 3824 return 0; 3825 } 3826 3827 long kvm_arch_vm_ioctl(struct file *filp, 3828 unsigned int ioctl, unsigned long arg) 3829 { 3830 struct kvm *kvm = filp->private_data; 3831 void __user *argp = (void __user *)arg; 3832 int r = -ENOTTY; 3833 /* 3834 * This union makes it completely explicit to gcc-3.x 3835 * that these two variables' stack usage should be 3836 * combined, not added together. 3837 */ 3838 union { 3839 struct kvm_pit_state ps; 3840 struct kvm_pit_state2 ps2; 3841 struct kvm_pit_config pit_config; 3842 } u; 3843 3844 switch (ioctl) { 3845 case KVM_SET_TSS_ADDR: 3846 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 3847 break; 3848 case KVM_SET_IDENTITY_MAP_ADDR: { 3849 u64 ident_addr; 3850 3851 r = -EFAULT; 3852 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 3853 goto out; 3854 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 3855 break; 3856 } 3857 case KVM_SET_NR_MMU_PAGES: 3858 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 3859 break; 3860 case KVM_GET_NR_MMU_PAGES: 3861 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 3862 break; 3863 case KVM_CREATE_IRQCHIP: { 3864 struct kvm_pic *vpic; 3865 3866 mutex_lock(&kvm->lock); 3867 r = -EEXIST; 3868 if (kvm->arch.vpic) 3869 goto create_irqchip_unlock; 3870 r = -EINVAL; 3871 if (atomic_read(&kvm->online_vcpus)) 3872 goto create_irqchip_unlock; 3873 r = -ENOMEM; 3874 vpic = kvm_create_pic(kvm); 3875 if (vpic) { 3876 r = kvm_ioapic_init(kvm); 3877 if (r) { 3878 mutex_lock(&kvm->slots_lock); 3879 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, 3880 &vpic->dev_master); 3881 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, 3882 &vpic->dev_slave); 3883 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, 3884 &vpic->dev_eclr); 3885 mutex_unlock(&kvm->slots_lock); 3886 kfree(vpic); 3887 goto create_irqchip_unlock; 3888 } 3889 } else 3890 goto create_irqchip_unlock; 3891 smp_wmb(); 3892 kvm->arch.vpic = vpic; 3893 smp_wmb(); 3894 r = kvm_setup_default_irq_routing(kvm); 3895 if (r) { 3896 mutex_lock(&kvm->slots_lock); 3897 mutex_lock(&kvm->irq_lock); 3898 kvm_ioapic_destroy(kvm); 3899 kvm_destroy_pic(kvm); 3900 mutex_unlock(&kvm->irq_lock); 3901 mutex_unlock(&kvm->slots_lock); 3902 } 3903 create_irqchip_unlock: 3904 mutex_unlock(&kvm->lock); 3905 break; 3906 } 3907 case KVM_CREATE_PIT: 3908 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 3909 goto create_pit; 3910 case KVM_CREATE_PIT2: 3911 r = -EFAULT; 3912 if (copy_from_user(&u.pit_config, argp, 3913 sizeof(struct kvm_pit_config))) 3914 goto out; 3915 create_pit: 3916 mutex_lock(&kvm->slots_lock); 3917 r = -EEXIST; 3918 if (kvm->arch.vpit) 3919 goto create_pit_unlock; 3920 r = -ENOMEM; 3921 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 3922 if (kvm->arch.vpit) 3923 r = 0; 3924 create_pit_unlock: 3925 mutex_unlock(&kvm->slots_lock); 3926 break; 3927 case KVM_GET_IRQCHIP: { 3928 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3929 struct kvm_irqchip *chip; 3930 3931 chip = memdup_user(argp, sizeof(*chip)); 3932 if (IS_ERR(chip)) { 3933 r = PTR_ERR(chip); 3934 goto out; 3935 } 3936 3937 r = -ENXIO; 3938 if (!irqchip_in_kernel(kvm)) 3939 goto get_irqchip_out; 3940 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 3941 if (r) 3942 goto get_irqchip_out; 3943 r = -EFAULT; 3944 if (copy_to_user(argp, chip, sizeof *chip)) 3945 goto get_irqchip_out; 3946 r = 0; 3947 get_irqchip_out: 3948 kfree(chip); 3949 break; 3950 } 3951 case KVM_SET_IRQCHIP: { 3952 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3953 struct kvm_irqchip *chip; 3954 3955 chip = memdup_user(argp, sizeof(*chip)); 3956 if (IS_ERR(chip)) { 3957 r = PTR_ERR(chip); 3958 goto out; 3959 } 3960 3961 r = -ENXIO; 3962 if (!irqchip_in_kernel(kvm)) 3963 goto set_irqchip_out; 3964 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 3965 if (r) 3966 goto set_irqchip_out; 3967 r = 0; 3968 set_irqchip_out: 3969 kfree(chip); 3970 break; 3971 } 3972 case KVM_GET_PIT: { 3973 r = -EFAULT; 3974 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 3975 goto out; 3976 r = -ENXIO; 3977 if (!kvm->arch.vpit) 3978 goto out; 3979 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 3980 if (r) 3981 goto out; 3982 r = -EFAULT; 3983 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 3984 goto out; 3985 r = 0; 3986 break; 3987 } 3988 case KVM_SET_PIT: { 3989 r = -EFAULT; 3990 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 3991 goto out; 3992 r = -ENXIO; 3993 if (!kvm->arch.vpit) 3994 goto out; 3995 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 3996 break; 3997 } 3998 case KVM_GET_PIT2: { 3999 r = -ENXIO; 4000 if (!kvm->arch.vpit) 4001 goto out; 4002 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 4003 if (r) 4004 goto out; 4005 r = -EFAULT; 4006 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 4007 goto out; 4008 r = 0; 4009 break; 4010 } 4011 case KVM_SET_PIT2: { 4012 r = -EFAULT; 4013 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 4014 goto out; 4015 r = -ENXIO; 4016 if (!kvm->arch.vpit) 4017 goto out; 4018 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 4019 break; 4020 } 4021 case KVM_REINJECT_CONTROL: { 4022 struct kvm_reinject_control control; 4023 r = -EFAULT; 4024 if (copy_from_user(&control, argp, sizeof(control))) 4025 goto out; 4026 r = kvm_vm_ioctl_reinject(kvm, &control); 4027 break; 4028 } 4029 case KVM_XEN_HVM_CONFIG: { 4030 r = -EFAULT; 4031 if (copy_from_user(&kvm->arch.xen_hvm_config, argp, 4032 sizeof(struct kvm_xen_hvm_config))) 4033 goto out; 4034 r = -EINVAL; 4035 if (kvm->arch.xen_hvm_config.flags) 4036 goto out; 4037 r = 0; 4038 break; 4039 } 4040 case KVM_SET_CLOCK: { 4041 struct kvm_clock_data user_ns; 4042 u64 now_ns; 4043 s64 delta; 4044 4045 r = -EFAULT; 4046 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 4047 goto out; 4048 4049 r = -EINVAL; 4050 if (user_ns.flags) 4051 goto out; 4052 4053 r = 0; 4054 local_irq_disable(); 4055 now_ns = get_kernel_ns(); 4056 delta = user_ns.clock - now_ns; 4057 local_irq_enable(); 4058 kvm->arch.kvmclock_offset = delta; 4059 kvm_gen_update_masterclock(kvm); 4060 break; 4061 } 4062 case KVM_GET_CLOCK: { 4063 struct kvm_clock_data user_ns; 4064 u64 now_ns; 4065 4066 local_irq_disable(); 4067 now_ns = get_kernel_ns(); 4068 user_ns.clock = kvm->arch.kvmclock_offset + now_ns; 4069 local_irq_enable(); 4070 user_ns.flags = 0; 4071 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 4072 4073 r = -EFAULT; 4074 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 4075 goto out; 4076 r = 0; 4077 break; 4078 } 4079 4080 default: 4081 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg); 4082 } 4083 out: 4084 return r; 4085 } 4086 4087 static void kvm_init_msr_list(void) 4088 { 4089 u32 dummy[2]; 4090 unsigned i, j; 4091 4092 /* skip the first msrs in the list. KVM-specific */ 4093 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { 4094 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4095 continue; 4096 4097 /* 4098 * Even MSRs that are valid in the host may not be exposed 4099 * to the guests in some cases. We could work around this 4100 * in VMX with the generic MSR save/load machinery, but it 4101 * is not really worthwhile since it will really only 4102 * happen with nested virtualization. 4103 */ 4104 switch (msrs_to_save[i]) { 4105 case MSR_IA32_BNDCFGS: 4106 if (!kvm_x86_ops->mpx_supported()) 4107 continue; 4108 break; 4109 default: 4110 break; 4111 } 4112 4113 if (j < i) 4114 msrs_to_save[j] = msrs_to_save[i]; 4115 j++; 4116 } 4117 num_msrs_to_save = j; 4118 } 4119 4120 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 4121 const void *v) 4122 { 4123 int handled = 0; 4124 int n; 4125 4126 do { 4127 n = min(len, 8); 4128 if (!(vcpu->arch.apic && 4129 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 4130 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 4131 break; 4132 handled += n; 4133 addr += n; 4134 len -= n; 4135 v += n; 4136 } while (len); 4137 4138 return handled; 4139 } 4140 4141 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4142 { 4143 int handled = 0; 4144 int n; 4145 4146 do { 4147 n = min(len, 8); 4148 if (!(vcpu->arch.apic && 4149 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 4150 addr, n, v)) 4151 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 4152 break; 4153 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); 4154 handled += n; 4155 addr += n; 4156 len -= n; 4157 v += n; 4158 } while (len); 4159 4160 return handled; 4161 } 4162 4163 static void kvm_set_segment(struct kvm_vcpu *vcpu, 4164 struct kvm_segment *var, int seg) 4165 { 4166 kvm_x86_ops->set_segment(vcpu, var, seg); 4167 } 4168 4169 void kvm_get_segment(struct kvm_vcpu *vcpu, 4170 struct kvm_segment *var, int seg) 4171 { 4172 kvm_x86_ops->get_segment(vcpu, var, seg); 4173 } 4174 4175 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 4176 struct x86_exception *exception) 4177 { 4178 gpa_t t_gpa; 4179 4180 BUG_ON(!mmu_is_nested(vcpu)); 4181 4182 /* NPT walks are always user-walks */ 4183 access |= PFERR_USER_MASK; 4184 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); 4185 4186 return t_gpa; 4187 } 4188 4189 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 4190 struct x86_exception *exception) 4191 { 4192 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4193 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4194 } 4195 4196 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 4197 struct x86_exception *exception) 4198 { 4199 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4200 access |= PFERR_FETCH_MASK; 4201 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4202 } 4203 4204 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 4205 struct x86_exception *exception) 4206 { 4207 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4208 access |= PFERR_WRITE_MASK; 4209 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4210 } 4211 4212 /* uses this to access any guest's mapped memory without checking CPL */ 4213 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 4214 struct x86_exception *exception) 4215 { 4216 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 4217 } 4218 4219 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 4220 struct kvm_vcpu *vcpu, u32 access, 4221 struct x86_exception *exception) 4222 { 4223 void *data = val; 4224 int r = X86EMUL_CONTINUE; 4225 4226 while (bytes) { 4227 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 4228 exception); 4229 unsigned offset = addr & (PAGE_SIZE-1); 4230 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 4231 int ret; 4232 4233 if (gpa == UNMAPPED_GVA) 4234 return X86EMUL_PROPAGATE_FAULT; 4235 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data, 4236 offset, toread); 4237 if (ret < 0) { 4238 r = X86EMUL_IO_NEEDED; 4239 goto out; 4240 } 4241 4242 bytes -= toread; 4243 data += toread; 4244 addr += toread; 4245 } 4246 out: 4247 return r; 4248 } 4249 4250 /* used for instruction fetching */ 4251 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4252 gva_t addr, void *val, unsigned int bytes, 4253 struct x86_exception *exception) 4254 { 4255 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4256 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4257 unsigned offset; 4258 int ret; 4259 4260 /* Inline kvm_read_guest_virt_helper for speed. */ 4261 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 4262 exception); 4263 if (unlikely(gpa == UNMAPPED_GVA)) 4264 return X86EMUL_PROPAGATE_FAULT; 4265 4266 offset = addr & (PAGE_SIZE-1); 4267 if (WARN_ON(offset + bytes > PAGE_SIZE)) 4268 bytes = (unsigned)PAGE_SIZE - offset; 4269 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val, 4270 offset, bytes); 4271 if (unlikely(ret < 0)) 4272 return X86EMUL_IO_NEEDED; 4273 4274 return X86EMUL_CONTINUE; 4275 } 4276 4277 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4278 gva_t addr, void *val, unsigned int bytes, 4279 struct x86_exception *exception) 4280 { 4281 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4282 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4283 4284 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4285 exception); 4286 } 4287 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4288 4289 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4290 gva_t addr, void *val, unsigned int bytes, 4291 struct x86_exception *exception) 4292 { 4293 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4294 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4295 } 4296 4297 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4298 gva_t addr, void *val, 4299 unsigned int bytes, 4300 struct x86_exception *exception) 4301 { 4302 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4303 void *data = val; 4304 int r = X86EMUL_CONTINUE; 4305 4306 while (bytes) { 4307 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4308 PFERR_WRITE_MASK, 4309 exception); 4310 unsigned offset = addr & (PAGE_SIZE-1); 4311 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4312 int ret; 4313 4314 if (gpa == UNMAPPED_GVA) 4315 return X86EMUL_PROPAGATE_FAULT; 4316 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); 4317 if (ret < 0) { 4318 r = X86EMUL_IO_NEEDED; 4319 goto out; 4320 } 4321 4322 bytes -= towrite; 4323 data += towrite; 4324 addr += towrite; 4325 } 4326 out: 4327 return r; 4328 } 4329 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4330 4331 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4332 gpa_t *gpa, struct x86_exception *exception, 4333 bool write) 4334 { 4335 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4336 | (write ? PFERR_WRITE_MASK : 0); 4337 4338 if (vcpu_match_mmio_gva(vcpu, gva) 4339 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4340 vcpu->arch.access, access)) { 4341 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4342 (gva & (PAGE_SIZE - 1)); 4343 trace_vcpu_match_mmio(gva, *gpa, write, false); 4344 return 1; 4345 } 4346 4347 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4348 4349 if (*gpa == UNMAPPED_GVA) 4350 return -1; 4351 4352 /* For APIC access vmexit */ 4353 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4354 return 1; 4355 4356 if (vcpu_match_mmio_gpa(vcpu, *gpa)) { 4357 trace_vcpu_match_mmio(gva, *gpa, write, true); 4358 return 1; 4359 } 4360 4361 return 0; 4362 } 4363 4364 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4365 const void *val, int bytes) 4366 { 4367 int ret; 4368 4369 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); 4370 if (ret < 0) 4371 return 0; 4372 kvm_mmu_pte_write(vcpu, gpa, val, bytes); 4373 return 1; 4374 } 4375 4376 struct read_write_emulator_ops { 4377 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4378 int bytes); 4379 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4380 void *val, int bytes); 4381 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4382 int bytes, void *val); 4383 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4384 void *val, int bytes); 4385 bool write; 4386 }; 4387 4388 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4389 { 4390 if (vcpu->mmio_read_completed) { 4391 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4392 vcpu->mmio_fragments[0].gpa, *(u64 *)val); 4393 vcpu->mmio_read_completed = 0; 4394 return 1; 4395 } 4396 4397 return 0; 4398 } 4399 4400 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4401 void *val, int bytes) 4402 { 4403 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes); 4404 } 4405 4406 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4407 void *val, int bytes) 4408 { 4409 return emulator_write_phys(vcpu, gpa, val, bytes); 4410 } 4411 4412 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4413 { 4414 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); 4415 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4416 } 4417 4418 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4419 void *val, int bytes) 4420 { 4421 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); 4422 return X86EMUL_IO_NEEDED; 4423 } 4424 4425 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4426 void *val, int bytes) 4427 { 4428 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4429 4430 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4431 return X86EMUL_CONTINUE; 4432 } 4433 4434 static const struct read_write_emulator_ops read_emultor = { 4435 .read_write_prepare = read_prepare, 4436 .read_write_emulate = read_emulate, 4437 .read_write_mmio = vcpu_mmio_read, 4438 .read_write_exit_mmio = read_exit_mmio, 4439 }; 4440 4441 static const struct read_write_emulator_ops write_emultor = { 4442 .read_write_emulate = write_emulate, 4443 .read_write_mmio = write_mmio, 4444 .read_write_exit_mmio = write_exit_mmio, 4445 .write = true, 4446 }; 4447 4448 static int emulator_read_write_onepage(unsigned long addr, void *val, 4449 unsigned int bytes, 4450 struct x86_exception *exception, 4451 struct kvm_vcpu *vcpu, 4452 const struct read_write_emulator_ops *ops) 4453 { 4454 gpa_t gpa; 4455 int handled, ret; 4456 bool write = ops->write; 4457 struct kvm_mmio_fragment *frag; 4458 4459 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 4460 4461 if (ret < 0) 4462 return X86EMUL_PROPAGATE_FAULT; 4463 4464 /* For APIC access vmexit */ 4465 if (ret) 4466 goto mmio; 4467 4468 if (ops->read_write_emulate(vcpu, gpa, val, bytes)) 4469 return X86EMUL_CONTINUE; 4470 4471 mmio: 4472 /* 4473 * Is this MMIO handled locally? 4474 */ 4475 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 4476 if (handled == bytes) 4477 return X86EMUL_CONTINUE; 4478 4479 gpa += handled; 4480 bytes -= handled; 4481 val += handled; 4482 4483 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 4484 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 4485 frag->gpa = gpa; 4486 frag->data = val; 4487 frag->len = bytes; 4488 return X86EMUL_CONTINUE; 4489 } 4490 4491 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 4492 unsigned long addr, 4493 void *val, unsigned int bytes, 4494 struct x86_exception *exception, 4495 const struct read_write_emulator_ops *ops) 4496 { 4497 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4498 gpa_t gpa; 4499 int rc; 4500 4501 if (ops->read_write_prepare && 4502 ops->read_write_prepare(vcpu, val, bytes)) 4503 return X86EMUL_CONTINUE; 4504 4505 vcpu->mmio_nr_fragments = 0; 4506 4507 /* Crossing a page boundary? */ 4508 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 4509 int now; 4510 4511 now = -addr & ~PAGE_MASK; 4512 rc = emulator_read_write_onepage(addr, val, now, exception, 4513 vcpu, ops); 4514 4515 if (rc != X86EMUL_CONTINUE) 4516 return rc; 4517 addr += now; 4518 if (ctxt->mode != X86EMUL_MODE_PROT64) 4519 addr = (u32)addr; 4520 val += now; 4521 bytes -= now; 4522 } 4523 4524 rc = emulator_read_write_onepage(addr, val, bytes, exception, 4525 vcpu, ops); 4526 if (rc != X86EMUL_CONTINUE) 4527 return rc; 4528 4529 if (!vcpu->mmio_nr_fragments) 4530 return rc; 4531 4532 gpa = vcpu->mmio_fragments[0].gpa; 4533 4534 vcpu->mmio_needed = 1; 4535 vcpu->mmio_cur_fragment = 0; 4536 4537 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 4538 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 4539 vcpu->run->exit_reason = KVM_EXIT_MMIO; 4540 vcpu->run->mmio.phys_addr = gpa; 4541 4542 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 4543 } 4544 4545 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 4546 unsigned long addr, 4547 void *val, 4548 unsigned int bytes, 4549 struct x86_exception *exception) 4550 { 4551 return emulator_read_write(ctxt, addr, val, bytes, 4552 exception, &read_emultor); 4553 } 4554 4555 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 4556 unsigned long addr, 4557 const void *val, 4558 unsigned int bytes, 4559 struct x86_exception *exception) 4560 { 4561 return emulator_read_write(ctxt, addr, (void *)val, bytes, 4562 exception, &write_emultor); 4563 } 4564 4565 #define CMPXCHG_TYPE(t, ptr, old, new) \ 4566 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 4567 4568 #ifdef CONFIG_X86_64 4569 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 4570 #else 4571 # define CMPXCHG64(ptr, old, new) \ 4572 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 4573 #endif 4574 4575 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 4576 unsigned long addr, 4577 const void *old, 4578 const void *new, 4579 unsigned int bytes, 4580 struct x86_exception *exception) 4581 { 4582 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4583 gpa_t gpa; 4584 struct page *page; 4585 char *kaddr; 4586 bool exchanged; 4587 4588 /* guests cmpxchg8b have to be emulated atomically */ 4589 if (bytes > 8 || (bytes & (bytes - 1))) 4590 goto emul_write; 4591 4592 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 4593 4594 if (gpa == UNMAPPED_GVA || 4595 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4596 goto emul_write; 4597 4598 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 4599 goto emul_write; 4600 4601 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); 4602 if (is_error_page(page)) 4603 goto emul_write; 4604 4605 kaddr = kmap_atomic(page); 4606 kaddr += offset_in_page(gpa); 4607 switch (bytes) { 4608 case 1: 4609 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 4610 break; 4611 case 2: 4612 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 4613 break; 4614 case 4: 4615 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 4616 break; 4617 case 8: 4618 exchanged = CMPXCHG64(kaddr, old, new); 4619 break; 4620 default: 4621 BUG(); 4622 } 4623 kunmap_atomic(kaddr); 4624 kvm_release_page_dirty(page); 4625 4626 if (!exchanged) 4627 return X86EMUL_CMPXCHG_FAILED; 4628 4629 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT); 4630 kvm_mmu_pte_write(vcpu, gpa, new, bytes); 4631 4632 return X86EMUL_CONTINUE; 4633 4634 emul_write: 4635 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 4636 4637 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 4638 } 4639 4640 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 4641 { 4642 /* TODO: String I/O for in kernel device */ 4643 int r; 4644 4645 if (vcpu->arch.pio.in) 4646 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 4647 vcpu->arch.pio.size, pd); 4648 else 4649 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 4650 vcpu->arch.pio.port, vcpu->arch.pio.size, 4651 pd); 4652 return r; 4653 } 4654 4655 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 4656 unsigned short port, void *val, 4657 unsigned int count, bool in) 4658 { 4659 vcpu->arch.pio.port = port; 4660 vcpu->arch.pio.in = in; 4661 vcpu->arch.pio.count = count; 4662 vcpu->arch.pio.size = size; 4663 4664 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 4665 vcpu->arch.pio.count = 0; 4666 return 1; 4667 } 4668 4669 vcpu->run->exit_reason = KVM_EXIT_IO; 4670 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 4671 vcpu->run->io.size = size; 4672 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 4673 vcpu->run->io.count = count; 4674 vcpu->run->io.port = port; 4675 4676 return 0; 4677 } 4678 4679 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 4680 int size, unsigned short port, void *val, 4681 unsigned int count) 4682 { 4683 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4684 int ret; 4685 4686 if (vcpu->arch.pio.count) 4687 goto data_avail; 4688 4689 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 4690 if (ret) { 4691 data_avail: 4692 memcpy(val, vcpu->arch.pio_data, size * count); 4693 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 4694 vcpu->arch.pio.count = 0; 4695 return 1; 4696 } 4697 4698 return 0; 4699 } 4700 4701 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 4702 int size, unsigned short port, 4703 const void *val, unsigned int count) 4704 { 4705 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4706 4707 memcpy(vcpu->arch.pio_data, val, size * count); 4708 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 4709 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 4710 } 4711 4712 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 4713 { 4714 return kvm_x86_ops->get_segment_base(vcpu, seg); 4715 } 4716 4717 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 4718 { 4719 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 4720 } 4721 4722 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 4723 { 4724 if (!need_emulate_wbinvd(vcpu)) 4725 return X86EMUL_CONTINUE; 4726 4727 if (kvm_x86_ops->has_wbinvd_exit()) { 4728 int cpu = get_cpu(); 4729 4730 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4731 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 4732 wbinvd_ipi, NULL, 1); 4733 put_cpu(); 4734 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 4735 } else 4736 wbinvd(); 4737 return X86EMUL_CONTINUE; 4738 } 4739 4740 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 4741 { 4742 kvm_x86_ops->skip_emulated_instruction(vcpu); 4743 return kvm_emulate_wbinvd_noskip(vcpu); 4744 } 4745 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 4746 4747 4748 4749 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 4750 { 4751 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 4752 } 4753 4754 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 4755 unsigned long *dest) 4756 { 4757 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 4758 } 4759 4760 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 4761 unsigned long value) 4762 { 4763 4764 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 4765 } 4766 4767 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 4768 { 4769 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 4770 } 4771 4772 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 4773 { 4774 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4775 unsigned long value; 4776 4777 switch (cr) { 4778 case 0: 4779 value = kvm_read_cr0(vcpu); 4780 break; 4781 case 2: 4782 value = vcpu->arch.cr2; 4783 break; 4784 case 3: 4785 value = kvm_read_cr3(vcpu); 4786 break; 4787 case 4: 4788 value = kvm_read_cr4(vcpu); 4789 break; 4790 case 8: 4791 value = kvm_get_cr8(vcpu); 4792 break; 4793 default: 4794 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4795 return 0; 4796 } 4797 4798 return value; 4799 } 4800 4801 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 4802 { 4803 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4804 int res = 0; 4805 4806 switch (cr) { 4807 case 0: 4808 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 4809 break; 4810 case 2: 4811 vcpu->arch.cr2 = val; 4812 break; 4813 case 3: 4814 res = kvm_set_cr3(vcpu, val); 4815 break; 4816 case 4: 4817 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 4818 break; 4819 case 8: 4820 res = kvm_set_cr8(vcpu, val); 4821 break; 4822 default: 4823 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4824 res = -1; 4825 } 4826 4827 return res; 4828 } 4829 4830 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 4831 { 4832 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 4833 } 4834 4835 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4836 { 4837 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 4838 } 4839 4840 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4841 { 4842 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 4843 } 4844 4845 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4846 { 4847 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 4848 } 4849 4850 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4851 { 4852 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 4853 } 4854 4855 static unsigned long emulator_get_cached_segment_base( 4856 struct x86_emulate_ctxt *ctxt, int seg) 4857 { 4858 return get_segment_base(emul_to_vcpu(ctxt), seg); 4859 } 4860 4861 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 4862 struct desc_struct *desc, u32 *base3, 4863 int seg) 4864 { 4865 struct kvm_segment var; 4866 4867 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 4868 *selector = var.selector; 4869 4870 if (var.unusable) { 4871 memset(desc, 0, sizeof(*desc)); 4872 return false; 4873 } 4874 4875 if (var.g) 4876 var.limit >>= 12; 4877 set_desc_limit(desc, var.limit); 4878 set_desc_base(desc, (unsigned long)var.base); 4879 #ifdef CONFIG_X86_64 4880 if (base3) 4881 *base3 = var.base >> 32; 4882 #endif 4883 desc->type = var.type; 4884 desc->s = var.s; 4885 desc->dpl = var.dpl; 4886 desc->p = var.present; 4887 desc->avl = var.avl; 4888 desc->l = var.l; 4889 desc->d = var.db; 4890 desc->g = var.g; 4891 4892 return true; 4893 } 4894 4895 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 4896 struct desc_struct *desc, u32 base3, 4897 int seg) 4898 { 4899 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4900 struct kvm_segment var; 4901 4902 var.selector = selector; 4903 var.base = get_desc_base(desc); 4904 #ifdef CONFIG_X86_64 4905 var.base |= ((u64)base3) << 32; 4906 #endif 4907 var.limit = get_desc_limit(desc); 4908 if (desc->g) 4909 var.limit = (var.limit << 12) | 0xfff; 4910 var.type = desc->type; 4911 var.dpl = desc->dpl; 4912 var.db = desc->d; 4913 var.s = desc->s; 4914 var.l = desc->l; 4915 var.g = desc->g; 4916 var.avl = desc->avl; 4917 var.present = desc->p; 4918 var.unusable = !var.present; 4919 var.padding = 0; 4920 4921 kvm_set_segment(vcpu, &var, seg); 4922 return; 4923 } 4924 4925 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 4926 u32 msr_index, u64 *pdata) 4927 { 4928 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); 4929 } 4930 4931 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 4932 u32 msr_index, u64 data) 4933 { 4934 struct msr_data msr; 4935 4936 msr.data = data; 4937 msr.index = msr_index; 4938 msr.host_initiated = false; 4939 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 4940 } 4941 4942 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 4943 u32 pmc) 4944 { 4945 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc); 4946 } 4947 4948 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 4949 u32 pmc, u64 *pdata) 4950 { 4951 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata); 4952 } 4953 4954 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 4955 { 4956 emul_to_vcpu(ctxt)->arch.halt_request = 1; 4957 } 4958 4959 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) 4960 { 4961 preempt_disable(); 4962 kvm_load_guest_fpu(emul_to_vcpu(ctxt)); 4963 /* 4964 * CR0.TS may reference the host fpu state, not the guest fpu state, 4965 * so it may be clear at this point. 4966 */ 4967 clts(); 4968 } 4969 4970 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) 4971 { 4972 preempt_enable(); 4973 } 4974 4975 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 4976 struct x86_instruction_info *info, 4977 enum x86_intercept_stage stage) 4978 { 4979 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 4980 } 4981 4982 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 4983 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) 4984 { 4985 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); 4986 } 4987 4988 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 4989 { 4990 return kvm_register_read(emul_to_vcpu(ctxt), reg); 4991 } 4992 4993 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 4994 { 4995 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 4996 } 4997 4998 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 4999 { 5000 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 5001 } 5002 5003 static const struct x86_emulate_ops emulate_ops = { 5004 .read_gpr = emulator_read_gpr, 5005 .write_gpr = emulator_write_gpr, 5006 .read_std = kvm_read_guest_virt_system, 5007 .write_std = kvm_write_guest_virt_system, 5008 .fetch = kvm_fetch_guest_virt, 5009 .read_emulated = emulator_read_emulated, 5010 .write_emulated = emulator_write_emulated, 5011 .cmpxchg_emulated = emulator_cmpxchg_emulated, 5012 .invlpg = emulator_invlpg, 5013 .pio_in_emulated = emulator_pio_in_emulated, 5014 .pio_out_emulated = emulator_pio_out_emulated, 5015 .get_segment = emulator_get_segment, 5016 .set_segment = emulator_set_segment, 5017 .get_cached_segment_base = emulator_get_cached_segment_base, 5018 .get_gdt = emulator_get_gdt, 5019 .get_idt = emulator_get_idt, 5020 .set_gdt = emulator_set_gdt, 5021 .set_idt = emulator_set_idt, 5022 .get_cr = emulator_get_cr, 5023 .set_cr = emulator_set_cr, 5024 .cpl = emulator_get_cpl, 5025 .get_dr = emulator_get_dr, 5026 .set_dr = emulator_set_dr, 5027 .set_msr = emulator_set_msr, 5028 .get_msr = emulator_get_msr, 5029 .check_pmc = emulator_check_pmc, 5030 .read_pmc = emulator_read_pmc, 5031 .halt = emulator_halt, 5032 .wbinvd = emulator_wbinvd, 5033 .fix_hypercall = emulator_fix_hypercall, 5034 .get_fpu = emulator_get_fpu, 5035 .put_fpu = emulator_put_fpu, 5036 .intercept = emulator_intercept, 5037 .get_cpuid = emulator_get_cpuid, 5038 .set_nmi_mask = emulator_set_nmi_mask, 5039 }; 5040 5041 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 5042 { 5043 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 5044 /* 5045 * an sti; sti; sequence only disable interrupts for the first 5046 * instruction. So, if the last instruction, be it emulated or 5047 * not, left the system with the INT_STI flag enabled, it 5048 * means that the last instruction is an sti. We should not 5049 * leave the flag on in this case. The same goes for mov ss 5050 */ 5051 if (int_shadow & mask) 5052 mask = 0; 5053 if (unlikely(int_shadow || mask)) { 5054 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 5055 if (!mask) 5056 kvm_make_request(KVM_REQ_EVENT, vcpu); 5057 } 5058 } 5059 5060 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 5061 { 5062 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5063 if (ctxt->exception.vector == PF_VECTOR) 5064 return kvm_propagate_fault(vcpu, &ctxt->exception); 5065 5066 if (ctxt->exception.error_code_valid) 5067 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 5068 ctxt->exception.error_code); 5069 else 5070 kvm_queue_exception(vcpu, ctxt->exception.vector); 5071 return false; 5072 } 5073 5074 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 5075 { 5076 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5077 int cs_db, cs_l; 5078 5079 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 5080 5081 ctxt->eflags = kvm_get_rflags(vcpu); 5082 ctxt->eip = kvm_rip_read(vcpu); 5083 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 5084 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 5085 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 5086 cs_db ? X86EMUL_MODE_PROT32 : 5087 X86EMUL_MODE_PROT16; 5088 ctxt->guest_mode = is_guest_mode(vcpu); 5089 5090 init_decode_cache(ctxt); 5091 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5092 } 5093 5094 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 5095 { 5096 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5097 int ret; 5098 5099 init_emulate_ctxt(vcpu); 5100 5101 ctxt->op_bytes = 2; 5102 ctxt->ad_bytes = 2; 5103 ctxt->_eip = ctxt->eip + inc_eip; 5104 ret = emulate_int_real(ctxt, irq); 5105 5106 if (ret != X86EMUL_CONTINUE) 5107 return EMULATE_FAIL; 5108 5109 ctxt->eip = ctxt->_eip; 5110 kvm_rip_write(vcpu, ctxt->eip); 5111 kvm_set_rflags(vcpu, ctxt->eflags); 5112 5113 if (irq == NMI_VECTOR) 5114 vcpu->arch.nmi_pending = 0; 5115 else 5116 vcpu->arch.interrupt.pending = false; 5117 5118 return EMULATE_DONE; 5119 } 5120 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 5121 5122 static int handle_emulation_failure(struct kvm_vcpu *vcpu) 5123 { 5124 int r = EMULATE_DONE; 5125 5126 ++vcpu->stat.insn_emulation_fail; 5127 trace_kvm_emulate_insn_failed(vcpu); 5128 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 5129 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5130 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 5131 vcpu->run->internal.ndata = 0; 5132 r = EMULATE_FAIL; 5133 } 5134 kvm_queue_exception(vcpu, UD_VECTOR); 5135 5136 return r; 5137 } 5138 5139 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 5140 bool write_fault_to_shadow_pgtable, 5141 int emulation_type) 5142 { 5143 gpa_t gpa = cr2; 5144 pfn_t pfn; 5145 5146 if (emulation_type & EMULTYPE_NO_REEXECUTE) 5147 return false; 5148 5149 if (!vcpu->arch.mmu.direct_map) { 5150 /* 5151 * Write permission should be allowed since only 5152 * write access need to be emulated. 5153 */ 5154 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5155 5156 /* 5157 * If the mapping is invalid in guest, let cpu retry 5158 * it to generate fault. 5159 */ 5160 if (gpa == UNMAPPED_GVA) 5161 return true; 5162 } 5163 5164 /* 5165 * Do not retry the unhandleable instruction if it faults on the 5166 * readonly host memory, otherwise it will goto a infinite loop: 5167 * retry instruction -> write #PF -> emulation fail -> retry 5168 * instruction -> ... 5169 */ 5170 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 5171 5172 /* 5173 * If the instruction failed on the error pfn, it can not be fixed, 5174 * report the error to userspace. 5175 */ 5176 if (is_error_noslot_pfn(pfn)) 5177 return false; 5178 5179 kvm_release_pfn_clean(pfn); 5180 5181 /* The instructions are well-emulated on direct mmu. */ 5182 if (vcpu->arch.mmu.direct_map) { 5183 unsigned int indirect_shadow_pages; 5184 5185 spin_lock(&vcpu->kvm->mmu_lock); 5186 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 5187 spin_unlock(&vcpu->kvm->mmu_lock); 5188 5189 if (indirect_shadow_pages) 5190 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5191 5192 return true; 5193 } 5194 5195 /* 5196 * if emulation was due to access to shadowed page table 5197 * and it failed try to unshadow page and re-enter the 5198 * guest to let CPU execute the instruction. 5199 */ 5200 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5201 5202 /* 5203 * If the access faults on its page table, it can not 5204 * be fixed by unprotecting shadow page and it should 5205 * be reported to userspace. 5206 */ 5207 return !write_fault_to_shadow_pgtable; 5208 } 5209 5210 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5211 unsigned long cr2, int emulation_type) 5212 { 5213 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5214 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5215 5216 last_retry_eip = vcpu->arch.last_retry_eip; 5217 last_retry_addr = vcpu->arch.last_retry_addr; 5218 5219 /* 5220 * If the emulation is caused by #PF and it is non-page_table 5221 * writing instruction, it means the VM-EXIT is caused by shadow 5222 * page protected, we can zap the shadow page and retry this 5223 * instruction directly. 5224 * 5225 * Note: if the guest uses a non-page-table modifying instruction 5226 * on the PDE that points to the instruction, then we will unmap 5227 * the instruction and go to an infinite loop. So, we cache the 5228 * last retried eip and the last fault address, if we meet the eip 5229 * and the address again, we can break out of the potential infinite 5230 * loop. 5231 */ 5232 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5233 5234 if (!(emulation_type & EMULTYPE_RETRY)) 5235 return false; 5236 5237 if (x86_page_table_writing_insn(ctxt)) 5238 return false; 5239 5240 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5241 return false; 5242 5243 vcpu->arch.last_retry_eip = ctxt->eip; 5244 vcpu->arch.last_retry_addr = cr2; 5245 5246 if (!vcpu->arch.mmu.direct_map) 5247 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5248 5249 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5250 5251 return true; 5252 } 5253 5254 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5255 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5256 5257 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5258 unsigned long *db) 5259 { 5260 u32 dr6 = 0; 5261 int i; 5262 u32 enable, rwlen; 5263 5264 enable = dr7; 5265 rwlen = dr7 >> 16; 5266 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5267 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5268 dr6 |= (1 << i); 5269 return dr6; 5270 } 5271 5272 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) 5273 { 5274 struct kvm_run *kvm_run = vcpu->run; 5275 5276 /* 5277 * rflags is the old, "raw" value of the flags. The new value has 5278 * not been saved yet. 5279 * 5280 * This is correct even for TF set by the guest, because "the 5281 * processor will not generate this exception after the instruction 5282 * that sets the TF flag". 5283 */ 5284 if (unlikely(rflags & X86_EFLAGS_TF)) { 5285 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5286 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | 5287 DR6_RTM; 5288 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5289 kvm_run->debug.arch.exception = DB_VECTOR; 5290 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5291 *r = EMULATE_USER_EXIT; 5292 } else { 5293 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; 5294 /* 5295 * "Certain debug exceptions may clear bit 0-3. The 5296 * remaining contents of the DR6 register are never 5297 * cleared by the processor". 5298 */ 5299 vcpu->arch.dr6 &= ~15; 5300 vcpu->arch.dr6 |= DR6_BS | DR6_RTM; 5301 kvm_queue_exception(vcpu, DB_VECTOR); 5302 } 5303 } 5304 } 5305 5306 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5307 { 5308 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5309 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5310 struct kvm_run *kvm_run = vcpu->run; 5311 unsigned long eip = kvm_get_linear_rip(vcpu); 5312 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5313 vcpu->arch.guest_debug_dr7, 5314 vcpu->arch.eff_db); 5315 5316 if (dr6 != 0) { 5317 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 5318 kvm_run->debug.arch.pc = eip; 5319 kvm_run->debug.arch.exception = DB_VECTOR; 5320 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5321 *r = EMULATE_USER_EXIT; 5322 return true; 5323 } 5324 } 5325 5326 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 5327 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 5328 unsigned long eip = kvm_get_linear_rip(vcpu); 5329 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5330 vcpu->arch.dr7, 5331 vcpu->arch.db); 5332 5333 if (dr6 != 0) { 5334 vcpu->arch.dr6 &= ~15; 5335 vcpu->arch.dr6 |= dr6 | DR6_RTM; 5336 kvm_queue_exception(vcpu, DB_VECTOR); 5337 *r = EMULATE_DONE; 5338 return true; 5339 } 5340 } 5341 5342 return false; 5343 } 5344 5345 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 5346 unsigned long cr2, 5347 int emulation_type, 5348 void *insn, 5349 int insn_len) 5350 { 5351 int r; 5352 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5353 bool writeback = true; 5354 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 5355 5356 /* 5357 * Clear write_fault_to_shadow_pgtable here to ensure it is 5358 * never reused. 5359 */ 5360 vcpu->arch.write_fault_to_shadow_pgtable = false; 5361 kvm_clear_exception_queue(vcpu); 5362 5363 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 5364 init_emulate_ctxt(vcpu); 5365 5366 /* 5367 * We will reenter on the same instruction since 5368 * we do not set complete_userspace_io. This does not 5369 * handle watchpoints yet, those would be handled in 5370 * the emulate_ops. 5371 */ 5372 if (kvm_vcpu_check_breakpoint(vcpu, &r)) 5373 return r; 5374 5375 ctxt->interruptibility = 0; 5376 ctxt->have_exception = false; 5377 ctxt->exception.vector = -1; 5378 ctxt->perm_ok = false; 5379 5380 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 5381 5382 r = x86_decode_insn(ctxt, insn, insn_len); 5383 5384 trace_kvm_emulate_insn_start(vcpu); 5385 ++vcpu->stat.insn_emulation; 5386 if (r != EMULATION_OK) { 5387 if (emulation_type & EMULTYPE_TRAP_UD) 5388 return EMULATE_FAIL; 5389 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5390 emulation_type)) 5391 return EMULATE_DONE; 5392 if (emulation_type & EMULTYPE_SKIP) 5393 return EMULATE_FAIL; 5394 return handle_emulation_failure(vcpu); 5395 } 5396 } 5397 5398 if (emulation_type & EMULTYPE_SKIP) { 5399 kvm_rip_write(vcpu, ctxt->_eip); 5400 if (ctxt->eflags & X86_EFLAGS_RF) 5401 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 5402 return EMULATE_DONE; 5403 } 5404 5405 if (retry_instruction(ctxt, cr2, emulation_type)) 5406 return EMULATE_DONE; 5407 5408 /* this is needed for vmware backdoor interface to work since it 5409 changes registers values during IO operation */ 5410 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 5411 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5412 emulator_invalidate_register_cache(ctxt); 5413 } 5414 5415 restart: 5416 r = x86_emulate_insn(ctxt); 5417 5418 if (r == EMULATION_INTERCEPTED) 5419 return EMULATE_DONE; 5420 5421 if (r == EMULATION_FAILED) { 5422 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5423 emulation_type)) 5424 return EMULATE_DONE; 5425 5426 return handle_emulation_failure(vcpu); 5427 } 5428 5429 if (ctxt->have_exception) { 5430 r = EMULATE_DONE; 5431 if (inject_emulated_exception(vcpu)) 5432 return r; 5433 } else if (vcpu->arch.pio.count) { 5434 if (!vcpu->arch.pio.in) { 5435 /* FIXME: return into emulator if single-stepping. */ 5436 vcpu->arch.pio.count = 0; 5437 } else { 5438 writeback = false; 5439 vcpu->arch.complete_userspace_io = complete_emulated_pio; 5440 } 5441 r = EMULATE_USER_EXIT; 5442 } else if (vcpu->mmio_needed) { 5443 if (!vcpu->mmio_is_write) 5444 writeback = false; 5445 r = EMULATE_USER_EXIT; 5446 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 5447 } else if (r == EMULATION_RESTART) 5448 goto restart; 5449 else 5450 r = EMULATE_DONE; 5451 5452 if (writeback) { 5453 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5454 toggle_interruptibility(vcpu, ctxt->interruptibility); 5455 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 5456 kvm_rip_write(vcpu, ctxt->eip); 5457 if (r == EMULATE_DONE) 5458 kvm_vcpu_check_singlestep(vcpu, rflags, &r); 5459 if (!ctxt->have_exception || 5460 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 5461 __kvm_set_rflags(vcpu, ctxt->eflags); 5462 5463 /* 5464 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 5465 * do nothing, and it will be requested again as soon as 5466 * the shadow expires. But we still need to check here, 5467 * because POPF has no interrupt shadow. 5468 */ 5469 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 5470 kvm_make_request(KVM_REQ_EVENT, vcpu); 5471 } else 5472 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 5473 5474 return r; 5475 } 5476 EXPORT_SYMBOL_GPL(x86_emulate_instruction); 5477 5478 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) 5479 { 5480 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 5481 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 5482 size, port, &val, 1); 5483 /* do not return to emulator after return from userspace */ 5484 vcpu->arch.pio.count = 0; 5485 return ret; 5486 } 5487 EXPORT_SYMBOL_GPL(kvm_fast_pio_out); 5488 5489 static void tsc_bad(void *info) 5490 { 5491 __this_cpu_write(cpu_tsc_khz, 0); 5492 } 5493 5494 static void tsc_khz_changed(void *data) 5495 { 5496 struct cpufreq_freqs *freq = data; 5497 unsigned long khz = 0; 5498 5499 if (data) 5500 khz = freq->new; 5501 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5502 khz = cpufreq_quick_get(raw_smp_processor_id()); 5503 if (!khz) 5504 khz = tsc_khz; 5505 __this_cpu_write(cpu_tsc_khz, khz); 5506 } 5507 5508 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 5509 void *data) 5510 { 5511 struct cpufreq_freqs *freq = data; 5512 struct kvm *kvm; 5513 struct kvm_vcpu *vcpu; 5514 int i, send_ipi = 0; 5515 5516 /* 5517 * We allow guests to temporarily run on slowing clocks, 5518 * provided we notify them after, or to run on accelerating 5519 * clocks, provided we notify them before. Thus time never 5520 * goes backwards. 5521 * 5522 * However, we have a problem. We can't atomically update 5523 * the frequency of a given CPU from this function; it is 5524 * merely a notifier, which can be called from any CPU. 5525 * Changing the TSC frequency at arbitrary points in time 5526 * requires a recomputation of local variables related to 5527 * the TSC for each VCPU. We must flag these local variables 5528 * to be updated and be sure the update takes place with the 5529 * new frequency before any guests proceed. 5530 * 5531 * Unfortunately, the combination of hotplug CPU and frequency 5532 * change creates an intractable locking scenario; the order 5533 * of when these callouts happen is undefined with respect to 5534 * CPU hotplug, and they can race with each other. As such, 5535 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 5536 * undefined; you can actually have a CPU frequency change take 5537 * place in between the computation of X and the setting of the 5538 * variable. To protect against this problem, all updates of 5539 * the per_cpu tsc_khz variable are done in an interrupt 5540 * protected IPI, and all callers wishing to update the value 5541 * must wait for a synchronous IPI to complete (which is trivial 5542 * if the caller is on the CPU already). This establishes the 5543 * necessary total order on variable updates. 5544 * 5545 * Note that because a guest time update may take place 5546 * anytime after the setting of the VCPU's request bit, the 5547 * correct TSC value must be set before the request. However, 5548 * to ensure the update actually makes it to any guest which 5549 * starts running in hardware virtualization between the set 5550 * and the acquisition of the spinlock, we must also ping the 5551 * CPU after setting the request bit. 5552 * 5553 */ 5554 5555 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 5556 return 0; 5557 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 5558 return 0; 5559 5560 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5561 5562 spin_lock(&kvm_lock); 5563 list_for_each_entry(kvm, &vm_list, vm_list) { 5564 kvm_for_each_vcpu(i, vcpu, kvm) { 5565 if (vcpu->cpu != freq->cpu) 5566 continue; 5567 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5568 if (vcpu->cpu != smp_processor_id()) 5569 send_ipi = 1; 5570 } 5571 } 5572 spin_unlock(&kvm_lock); 5573 5574 if (freq->old < freq->new && send_ipi) { 5575 /* 5576 * We upscale the frequency. Must make the guest 5577 * doesn't see old kvmclock values while running with 5578 * the new frequency, otherwise we risk the guest sees 5579 * time go backwards. 5580 * 5581 * In case we update the frequency for another cpu 5582 * (which might be in guest context) send an interrupt 5583 * to kick the cpu out of guest context. Next time 5584 * guest context is entered kvmclock will be updated, 5585 * so the guest will not see stale values. 5586 */ 5587 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5588 } 5589 return 0; 5590 } 5591 5592 static struct notifier_block kvmclock_cpufreq_notifier_block = { 5593 .notifier_call = kvmclock_cpufreq_notifier 5594 }; 5595 5596 static int kvmclock_cpu_notifier(struct notifier_block *nfb, 5597 unsigned long action, void *hcpu) 5598 { 5599 unsigned int cpu = (unsigned long)hcpu; 5600 5601 switch (action) { 5602 case CPU_ONLINE: 5603 case CPU_DOWN_FAILED: 5604 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5605 break; 5606 case CPU_DOWN_PREPARE: 5607 smp_call_function_single(cpu, tsc_bad, NULL, 1); 5608 break; 5609 } 5610 return NOTIFY_OK; 5611 } 5612 5613 static struct notifier_block kvmclock_cpu_notifier_block = { 5614 .notifier_call = kvmclock_cpu_notifier, 5615 .priority = -INT_MAX 5616 }; 5617 5618 static void kvm_timer_init(void) 5619 { 5620 int cpu; 5621 5622 max_tsc_khz = tsc_khz; 5623 5624 cpu_notifier_register_begin(); 5625 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 5626 #ifdef CONFIG_CPU_FREQ 5627 struct cpufreq_policy policy; 5628 memset(&policy, 0, sizeof(policy)); 5629 cpu = get_cpu(); 5630 cpufreq_get_policy(&policy, cpu); 5631 if (policy.cpuinfo.max_freq) 5632 max_tsc_khz = policy.cpuinfo.max_freq; 5633 put_cpu(); 5634 #endif 5635 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 5636 CPUFREQ_TRANSITION_NOTIFIER); 5637 } 5638 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 5639 for_each_online_cpu(cpu) 5640 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5641 5642 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5643 cpu_notifier_register_done(); 5644 5645 } 5646 5647 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 5648 5649 int kvm_is_in_guest(void) 5650 { 5651 return __this_cpu_read(current_vcpu) != NULL; 5652 } 5653 5654 static int kvm_is_user_mode(void) 5655 { 5656 int user_mode = 3; 5657 5658 if (__this_cpu_read(current_vcpu)) 5659 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 5660 5661 return user_mode != 0; 5662 } 5663 5664 static unsigned long kvm_get_guest_ip(void) 5665 { 5666 unsigned long ip = 0; 5667 5668 if (__this_cpu_read(current_vcpu)) 5669 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 5670 5671 return ip; 5672 } 5673 5674 static struct perf_guest_info_callbacks kvm_guest_cbs = { 5675 .is_in_guest = kvm_is_in_guest, 5676 .is_user_mode = kvm_is_user_mode, 5677 .get_guest_ip = kvm_get_guest_ip, 5678 }; 5679 5680 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) 5681 { 5682 __this_cpu_write(current_vcpu, vcpu); 5683 } 5684 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); 5685 5686 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) 5687 { 5688 __this_cpu_write(current_vcpu, NULL); 5689 } 5690 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); 5691 5692 static void kvm_set_mmio_spte_mask(void) 5693 { 5694 u64 mask; 5695 int maxphyaddr = boot_cpu_data.x86_phys_bits; 5696 5697 /* 5698 * Set the reserved bits and the present bit of an paging-structure 5699 * entry to generate page fault with PFER.RSV = 1. 5700 */ 5701 /* Mask the reserved physical address bits. */ 5702 mask = rsvd_bits(maxphyaddr, 51); 5703 5704 /* Bit 62 is always reserved for 32bit host. */ 5705 mask |= 0x3ull << 62; 5706 5707 /* Set the present bit. */ 5708 mask |= 1ull; 5709 5710 #ifdef CONFIG_X86_64 5711 /* 5712 * If reserved bit is not supported, clear the present bit to disable 5713 * mmio page fault. 5714 */ 5715 if (maxphyaddr == 52) 5716 mask &= ~1ull; 5717 #endif 5718 5719 kvm_mmu_set_mmio_spte_mask(mask); 5720 } 5721 5722 #ifdef CONFIG_X86_64 5723 static void pvclock_gtod_update_fn(struct work_struct *work) 5724 { 5725 struct kvm *kvm; 5726 5727 struct kvm_vcpu *vcpu; 5728 int i; 5729 5730 spin_lock(&kvm_lock); 5731 list_for_each_entry(kvm, &vm_list, vm_list) 5732 kvm_for_each_vcpu(i, vcpu, kvm) 5733 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 5734 atomic_set(&kvm_guest_has_master_clock, 0); 5735 spin_unlock(&kvm_lock); 5736 } 5737 5738 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 5739 5740 /* 5741 * Notification about pvclock gtod data update. 5742 */ 5743 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 5744 void *priv) 5745 { 5746 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 5747 struct timekeeper *tk = priv; 5748 5749 update_pvclock_gtod(tk); 5750 5751 /* disable master clock if host does not trust, or does not 5752 * use, TSC clocksource 5753 */ 5754 if (gtod->clock.vclock_mode != VCLOCK_TSC && 5755 atomic_read(&kvm_guest_has_master_clock) != 0) 5756 queue_work(system_long_wq, &pvclock_gtod_work); 5757 5758 return 0; 5759 } 5760 5761 static struct notifier_block pvclock_gtod_notifier = { 5762 .notifier_call = pvclock_gtod_notify, 5763 }; 5764 #endif 5765 5766 int kvm_arch_init(void *opaque) 5767 { 5768 int r; 5769 struct kvm_x86_ops *ops = opaque; 5770 5771 if (kvm_x86_ops) { 5772 printk(KERN_ERR "kvm: already loaded the other module\n"); 5773 r = -EEXIST; 5774 goto out; 5775 } 5776 5777 if (!ops->cpu_has_kvm_support()) { 5778 printk(KERN_ERR "kvm: no hardware support\n"); 5779 r = -EOPNOTSUPP; 5780 goto out; 5781 } 5782 if (ops->disabled_by_bios()) { 5783 printk(KERN_ERR "kvm: disabled by bios\n"); 5784 r = -EOPNOTSUPP; 5785 goto out; 5786 } 5787 5788 r = -ENOMEM; 5789 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 5790 if (!shared_msrs) { 5791 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 5792 goto out; 5793 } 5794 5795 r = kvm_mmu_module_init(); 5796 if (r) 5797 goto out_free_percpu; 5798 5799 kvm_set_mmio_spte_mask(); 5800 5801 kvm_x86_ops = ops; 5802 5803 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 5804 PT_DIRTY_MASK, PT64_NX_MASK, 0); 5805 5806 kvm_timer_init(); 5807 5808 perf_register_guest_info_callbacks(&kvm_guest_cbs); 5809 5810 if (cpu_has_xsave) 5811 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 5812 5813 kvm_lapic_init(); 5814 #ifdef CONFIG_X86_64 5815 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 5816 #endif 5817 5818 return 0; 5819 5820 out_free_percpu: 5821 free_percpu(shared_msrs); 5822 out: 5823 return r; 5824 } 5825 5826 void kvm_arch_exit(void) 5827 { 5828 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 5829 5830 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5831 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 5832 CPUFREQ_TRANSITION_NOTIFIER); 5833 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5834 #ifdef CONFIG_X86_64 5835 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 5836 #endif 5837 kvm_x86_ops = NULL; 5838 kvm_mmu_module_exit(); 5839 free_percpu(shared_msrs); 5840 } 5841 5842 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 5843 { 5844 ++vcpu->stat.halt_exits; 5845 if (irqchip_in_kernel(vcpu->kvm)) { 5846 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 5847 return 1; 5848 } else { 5849 vcpu->run->exit_reason = KVM_EXIT_HLT; 5850 return 0; 5851 } 5852 } 5853 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 5854 5855 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 5856 { 5857 kvm_x86_ops->skip_emulated_instruction(vcpu); 5858 return kvm_vcpu_halt(vcpu); 5859 } 5860 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 5861 5862 int kvm_hv_hypercall(struct kvm_vcpu *vcpu) 5863 { 5864 u64 param, ingpa, outgpa, ret; 5865 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; 5866 bool fast, longmode; 5867 5868 /* 5869 * hypercall generates UD from non zero cpl and real mode 5870 * per HYPER-V spec 5871 */ 5872 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { 5873 kvm_queue_exception(vcpu, UD_VECTOR); 5874 return 0; 5875 } 5876 5877 longmode = is_64_bit_mode(vcpu); 5878 5879 if (!longmode) { 5880 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | 5881 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); 5882 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | 5883 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); 5884 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | 5885 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); 5886 } 5887 #ifdef CONFIG_X86_64 5888 else { 5889 param = kvm_register_read(vcpu, VCPU_REGS_RCX); 5890 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); 5891 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); 5892 } 5893 #endif 5894 5895 code = param & 0xffff; 5896 fast = (param >> 16) & 0x1; 5897 rep_cnt = (param >> 32) & 0xfff; 5898 rep_idx = (param >> 48) & 0xfff; 5899 5900 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); 5901 5902 switch (code) { 5903 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: 5904 kvm_vcpu_on_spin(vcpu); 5905 break; 5906 default: 5907 res = HV_STATUS_INVALID_HYPERCALL_CODE; 5908 break; 5909 } 5910 5911 ret = res | (((u64)rep_done & 0xfff) << 32); 5912 if (longmode) { 5913 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 5914 } else { 5915 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); 5916 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); 5917 } 5918 5919 return 1; 5920 } 5921 5922 /* 5923 * kvm_pv_kick_cpu_op: Kick a vcpu. 5924 * 5925 * @apicid - apicid of vcpu to be kicked. 5926 */ 5927 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 5928 { 5929 struct kvm_lapic_irq lapic_irq; 5930 5931 lapic_irq.shorthand = 0; 5932 lapic_irq.dest_mode = 0; 5933 lapic_irq.dest_id = apicid; 5934 5935 lapic_irq.delivery_mode = APIC_DM_REMRD; 5936 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 5937 } 5938 5939 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 5940 { 5941 unsigned long nr, a0, a1, a2, a3, ret; 5942 int op_64_bit, r = 1; 5943 5944 kvm_x86_ops->skip_emulated_instruction(vcpu); 5945 5946 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 5947 return kvm_hv_hypercall(vcpu); 5948 5949 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 5950 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 5951 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 5952 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 5953 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 5954 5955 trace_kvm_hypercall(nr, a0, a1, a2, a3); 5956 5957 op_64_bit = is_64_bit_mode(vcpu); 5958 if (!op_64_bit) { 5959 nr &= 0xFFFFFFFF; 5960 a0 &= 0xFFFFFFFF; 5961 a1 &= 0xFFFFFFFF; 5962 a2 &= 0xFFFFFFFF; 5963 a3 &= 0xFFFFFFFF; 5964 } 5965 5966 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 5967 ret = -KVM_EPERM; 5968 goto out; 5969 } 5970 5971 switch (nr) { 5972 case KVM_HC_VAPIC_POLL_IRQ: 5973 ret = 0; 5974 break; 5975 case KVM_HC_KICK_CPU: 5976 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 5977 ret = 0; 5978 break; 5979 default: 5980 ret = -KVM_ENOSYS; 5981 break; 5982 } 5983 out: 5984 if (!op_64_bit) 5985 ret = (u32)ret; 5986 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 5987 ++vcpu->stat.hypercalls; 5988 return r; 5989 } 5990 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 5991 5992 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 5993 { 5994 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5995 char instruction[3]; 5996 unsigned long rip = kvm_rip_read(vcpu); 5997 5998 kvm_x86_ops->patch_hypercall(vcpu, instruction); 5999 6000 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); 6001 } 6002 6003 /* 6004 * Check if userspace requested an interrupt window, and that the 6005 * interrupt window is open. 6006 * 6007 * No need to exit to userspace if we already have an interrupt queued. 6008 */ 6009 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 6010 { 6011 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && 6012 vcpu->run->request_interrupt_window && 6013 kvm_arch_interrupt_allowed(vcpu)); 6014 } 6015 6016 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 6017 { 6018 struct kvm_run *kvm_run = vcpu->run; 6019 6020 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 6021 kvm_run->cr8 = kvm_get_cr8(vcpu); 6022 kvm_run->apic_base = kvm_get_apic_base(vcpu); 6023 if (irqchip_in_kernel(vcpu->kvm)) 6024 kvm_run->ready_for_interrupt_injection = 1; 6025 else 6026 kvm_run->ready_for_interrupt_injection = 6027 kvm_arch_interrupt_allowed(vcpu) && 6028 !kvm_cpu_has_interrupt(vcpu) && 6029 !kvm_event_needs_reinjection(vcpu); 6030 } 6031 6032 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 6033 { 6034 int max_irr, tpr; 6035 6036 if (!kvm_x86_ops->update_cr8_intercept) 6037 return; 6038 6039 if (!vcpu->arch.apic) 6040 return; 6041 6042 if (!vcpu->arch.apic->vapic_addr) 6043 max_irr = kvm_lapic_find_highest_irr(vcpu); 6044 else 6045 max_irr = -1; 6046 6047 if (max_irr != -1) 6048 max_irr >>= 4; 6049 6050 tpr = kvm_lapic_get_cr8(vcpu); 6051 6052 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 6053 } 6054 6055 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 6056 { 6057 int r; 6058 6059 /* try to reinject previous events if any */ 6060 if (vcpu->arch.exception.pending) { 6061 trace_kvm_inj_exception(vcpu->arch.exception.nr, 6062 vcpu->arch.exception.has_error_code, 6063 vcpu->arch.exception.error_code); 6064 6065 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 6066 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 6067 X86_EFLAGS_RF); 6068 6069 if (vcpu->arch.exception.nr == DB_VECTOR && 6070 (vcpu->arch.dr7 & DR7_GD)) { 6071 vcpu->arch.dr7 &= ~DR7_GD; 6072 kvm_update_dr7(vcpu); 6073 } 6074 6075 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, 6076 vcpu->arch.exception.has_error_code, 6077 vcpu->arch.exception.error_code, 6078 vcpu->arch.exception.reinject); 6079 return 0; 6080 } 6081 6082 if (vcpu->arch.nmi_injected) { 6083 kvm_x86_ops->set_nmi(vcpu); 6084 return 0; 6085 } 6086 6087 if (vcpu->arch.interrupt.pending) { 6088 kvm_x86_ops->set_irq(vcpu); 6089 return 0; 6090 } 6091 6092 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6093 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6094 if (r != 0) 6095 return r; 6096 } 6097 6098 /* try to inject new event if pending */ 6099 if (vcpu->arch.nmi_pending) { 6100 if (kvm_x86_ops->nmi_allowed(vcpu)) { 6101 --vcpu->arch.nmi_pending; 6102 vcpu->arch.nmi_injected = true; 6103 kvm_x86_ops->set_nmi(vcpu); 6104 } 6105 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 6106 /* 6107 * Because interrupts can be injected asynchronously, we are 6108 * calling check_nested_events again here to avoid a race condition. 6109 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 6110 * proposal and current concerns. Perhaps we should be setting 6111 * KVM_REQ_EVENT only on certain events and not unconditionally? 6112 */ 6113 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6114 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6115 if (r != 0) 6116 return r; 6117 } 6118 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 6119 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 6120 false); 6121 kvm_x86_ops->set_irq(vcpu); 6122 } 6123 } 6124 return 0; 6125 } 6126 6127 static void process_nmi(struct kvm_vcpu *vcpu) 6128 { 6129 unsigned limit = 2; 6130 6131 /* 6132 * x86 is limited to one NMI running, and one NMI pending after it. 6133 * If an NMI is already in progress, limit further NMIs to just one. 6134 * Otherwise, allow two (and we'll inject the first one immediately). 6135 */ 6136 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 6137 limit = 1; 6138 6139 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 6140 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 6141 kvm_make_request(KVM_REQ_EVENT, vcpu); 6142 } 6143 6144 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 6145 { 6146 u64 eoi_exit_bitmap[4]; 6147 u32 tmr[8]; 6148 6149 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 6150 return; 6151 6152 memset(eoi_exit_bitmap, 0, 32); 6153 memset(tmr, 0, 32); 6154 6155 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr); 6156 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 6157 kvm_apic_update_tmr(vcpu, tmr); 6158 } 6159 6160 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) 6161 { 6162 ++vcpu->stat.tlb_flush; 6163 kvm_x86_ops->tlb_flush(vcpu); 6164 } 6165 6166 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 6167 { 6168 struct page *page = NULL; 6169 6170 if (!irqchip_in_kernel(vcpu->kvm)) 6171 return; 6172 6173 if (!kvm_x86_ops->set_apic_access_page_addr) 6174 return; 6175 6176 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 6177 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 6178 6179 /* 6180 * Do not pin apic access page in memory, the MMU notifier 6181 * will call us again if it is migrated or swapped out. 6182 */ 6183 put_page(page); 6184 } 6185 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 6186 6187 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, 6188 unsigned long address) 6189 { 6190 /* 6191 * The physical address of apic access page is stored in the VMCS. 6192 * Update it when it becomes invalid. 6193 */ 6194 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT)) 6195 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 6196 } 6197 6198 /* 6199 * Returns 1 to let vcpu_run() continue the guest execution loop without 6200 * exiting to the userspace. Otherwise, the value will be returned to the 6201 * userspace. 6202 */ 6203 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 6204 { 6205 int r; 6206 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && 6207 vcpu->run->request_interrupt_window; 6208 bool req_immediate_exit = false; 6209 6210 if (vcpu->requests) { 6211 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 6212 kvm_mmu_unload(vcpu); 6213 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 6214 __kvm_migrate_timers(vcpu); 6215 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 6216 kvm_gen_update_masterclock(vcpu->kvm); 6217 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 6218 kvm_gen_kvmclock_update(vcpu); 6219 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 6220 r = kvm_guest_time_update(vcpu); 6221 if (unlikely(r)) 6222 goto out; 6223 } 6224 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 6225 kvm_mmu_sync_roots(vcpu); 6226 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 6227 kvm_vcpu_flush_tlb(vcpu); 6228 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 6229 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 6230 r = 0; 6231 goto out; 6232 } 6233 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 6234 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 6235 r = 0; 6236 goto out; 6237 } 6238 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { 6239 vcpu->fpu_active = 0; 6240 kvm_x86_ops->fpu_deactivate(vcpu); 6241 } 6242 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 6243 /* Page is swapped out. Do synthetic halt */ 6244 vcpu->arch.apf.halted = true; 6245 r = 1; 6246 goto out; 6247 } 6248 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 6249 record_steal_time(vcpu); 6250 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 6251 process_nmi(vcpu); 6252 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 6253 kvm_handle_pmu_event(vcpu); 6254 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 6255 kvm_deliver_pmi(vcpu); 6256 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 6257 vcpu_scan_ioapic(vcpu); 6258 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 6259 kvm_vcpu_reload_apic_access_page(vcpu); 6260 } 6261 6262 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 6263 kvm_apic_accept_events(vcpu); 6264 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 6265 r = 1; 6266 goto out; 6267 } 6268 6269 if (inject_pending_event(vcpu, req_int_win) != 0) 6270 req_immediate_exit = true; 6271 /* enable NMI/IRQ window open exits if needed */ 6272 else if (vcpu->arch.nmi_pending) 6273 kvm_x86_ops->enable_nmi_window(vcpu); 6274 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 6275 kvm_x86_ops->enable_irq_window(vcpu); 6276 6277 if (kvm_lapic_enabled(vcpu)) { 6278 /* 6279 * Update architecture specific hints for APIC 6280 * virtual interrupt delivery. 6281 */ 6282 if (kvm_x86_ops->hwapic_irr_update) 6283 kvm_x86_ops->hwapic_irr_update(vcpu, 6284 kvm_lapic_find_highest_irr(vcpu)); 6285 update_cr8_intercept(vcpu); 6286 kvm_lapic_sync_to_vapic(vcpu); 6287 } 6288 } 6289 6290 r = kvm_mmu_reload(vcpu); 6291 if (unlikely(r)) { 6292 goto cancel_injection; 6293 } 6294 6295 preempt_disable(); 6296 6297 kvm_x86_ops->prepare_guest_switch(vcpu); 6298 if (vcpu->fpu_active) 6299 kvm_load_guest_fpu(vcpu); 6300 kvm_load_guest_xcr0(vcpu); 6301 6302 vcpu->mode = IN_GUEST_MODE; 6303 6304 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6305 6306 /* We should set ->mode before check ->requests, 6307 * see the comment in make_all_cpus_request. 6308 */ 6309 smp_mb__after_srcu_read_unlock(); 6310 6311 local_irq_disable(); 6312 6313 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests 6314 || need_resched() || signal_pending(current)) { 6315 vcpu->mode = OUTSIDE_GUEST_MODE; 6316 smp_wmb(); 6317 local_irq_enable(); 6318 preempt_enable(); 6319 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6320 r = 1; 6321 goto cancel_injection; 6322 } 6323 6324 if (req_immediate_exit) 6325 smp_send_reschedule(vcpu->cpu); 6326 6327 kvm_guest_enter(); 6328 6329 if (unlikely(vcpu->arch.switch_db_regs)) { 6330 set_debugreg(0, 7); 6331 set_debugreg(vcpu->arch.eff_db[0], 0); 6332 set_debugreg(vcpu->arch.eff_db[1], 1); 6333 set_debugreg(vcpu->arch.eff_db[2], 2); 6334 set_debugreg(vcpu->arch.eff_db[3], 3); 6335 set_debugreg(vcpu->arch.dr6, 6); 6336 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 6337 } 6338 6339 trace_kvm_entry(vcpu->vcpu_id); 6340 wait_lapic_expire(vcpu); 6341 kvm_x86_ops->run(vcpu); 6342 6343 /* 6344 * Do this here before restoring debug registers on the host. And 6345 * since we do this before handling the vmexit, a DR access vmexit 6346 * can (a) read the correct value of the debug registers, (b) set 6347 * KVM_DEBUGREG_WONT_EXIT again. 6348 */ 6349 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 6350 int i; 6351 6352 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 6353 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 6354 for (i = 0; i < KVM_NR_DB_REGS; i++) 6355 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 6356 } 6357 6358 /* 6359 * If the guest has used debug registers, at least dr7 6360 * will be disabled while returning to the host. 6361 * If we don't have active breakpoints in the host, we don't 6362 * care about the messed up debug address registers. But if 6363 * we have some of them active, restore the old state. 6364 */ 6365 if (hw_breakpoint_active()) 6366 hw_breakpoint_restore(); 6367 6368 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, 6369 native_read_tsc()); 6370 6371 vcpu->mode = OUTSIDE_GUEST_MODE; 6372 smp_wmb(); 6373 6374 /* Interrupt is enabled by handle_external_intr() */ 6375 kvm_x86_ops->handle_external_intr(vcpu); 6376 6377 ++vcpu->stat.exits; 6378 6379 /* 6380 * We must have an instruction between local_irq_enable() and 6381 * kvm_guest_exit(), so the timer interrupt isn't delayed by 6382 * the interrupt shadow. The stat.exits increment will do nicely. 6383 * But we need to prevent reordering, hence this barrier(): 6384 */ 6385 barrier(); 6386 6387 kvm_guest_exit(); 6388 6389 preempt_enable(); 6390 6391 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6392 6393 /* 6394 * Profile KVM exit RIPs: 6395 */ 6396 if (unlikely(prof_on == KVM_PROFILING)) { 6397 unsigned long rip = kvm_rip_read(vcpu); 6398 profile_hit(KVM_PROFILING, (void *)rip); 6399 } 6400 6401 if (unlikely(vcpu->arch.tsc_always_catchup)) 6402 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6403 6404 if (vcpu->arch.apic_attention) 6405 kvm_lapic_sync_from_vapic(vcpu); 6406 6407 r = kvm_x86_ops->handle_exit(vcpu); 6408 return r; 6409 6410 cancel_injection: 6411 kvm_x86_ops->cancel_injection(vcpu); 6412 if (unlikely(vcpu->arch.apic_attention)) 6413 kvm_lapic_sync_from_vapic(vcpu); 6414 out: 6415 return r; 6416 } 6417 6418 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 6419 { 6420 if (!kvm_arch_vcpu_runnable(vcpu)) { 6421 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6422 kvm_vcpu_block(vcpu); 6423 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6424 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 6425 return 1; 6426 } 6427 6428 kvm_apic_accept_events(vcpu); 6429 switch(vcpu->arch.mp_state) { 6430 case KVM_MP_STATE_HALTED: 6431 vcpu->arch.pv.pv_unhalted = false; 6432 vcpu->arch.mp_state = 6433 KVM_MP_STATE_RUNNABLE; 6434 case KVM_MP_STATE_RUNNABLE: 6435 vcpu->arch.apf.halted = false; 6436 break; 6437 case KVM_MP_STATE_INIT_RECEIVED: 6438 break; 6439 default: 6440 return -EINTR; 6441 break; 6442 } 6443 return 1; 6444 } 6445 6446 static int vcpu_run(struct kvm_vcpu *vcpu) 6447 { 6448 int r; 6449 struct kvm *kvm = vcpu->kvm; 6450 6451 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6452 6453 for (;;) { 6454 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 6455 !vcpu->arch.apf.halted) 6456 r = vcpu_enter_guest(vcpu); 6457 else 6458 r = vcpu_block(kvm, vcpu); 6459 if (r <= 0) 6460 break; 6461 6462 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); 6463 if (kvm_cpu_has_pending_timer(vcpu)) 6464 kvm_inject_pending_timer_irqs(vcpu); 6465 6466 if (dm_request_for_irq_injection(vcpu)) { 6467 r = -EINTR; 6468 vcpu->run->exit_reason = KVM_EXIT_INTR; 6469 ++vcpu->stat.request_irq_exits; 6470 break; 6471 } 6472 6473 kvm_check_async_pf_completion(vcpu); 6474 6475 if (signal_pending(current)) { 6476 r = -EINTR; 6477 vcpu->run->exit_reason = KVM_EXIT_INTR; 6478 ++vcpu->stat.signal_exits; 6479 break; 6480 } 6481 if (need_resched()) { 6482 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6483 cond_resched(); 6484 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6485 } 6486 } 6487 6488 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6489 6490 return r; 6491 } 6492 6493 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 6494 { 6495 int r; 6496 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6497 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 6498 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6499 if (r != EMULATE_DONE) 6500 return 0; 6501 return 1; 6502 } 6503 6504 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 6505 { 6506 BUG_ON(!vcpu->arch.pio.count); 6507 6508 return complete_emulated_io(vcpu); 6509 } 6510 6511 /* 6512 * Implements the following, as a state machine: 6513 * 6514 * read: 6515 * for each fragment 6516 * for each mmio piece in the fragment 6517 * write gpa, len 6518 * exit 6519 * copy data 6520 * execute insn 6521 * 6522 * write: 6523 * for each fragment 6524 * for each mmio piece in the fragment 6525 * write gpa, len 6526 * copy data 6527 * exit 6528 */ 6529 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 6530 { 6531 struct kvm_run *run = vcpu->run; 6532 struct kvm_mmio_fragment *frag; 6533 unsigned len; 6534 6535 BUG_ON(!vcpu->mmio_needed); 6536 6537 /* Complete previous fragment */ 6538 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 6539 len = min(8u, frag->len); 6540 if (!vcpu->mmio_is_write) 6541 memcpy(frag->data, run->mmio.data, len); 6542 6543 if (frag->len <= 8) { 6544 /* Switch to the next fragment. */ 6545 frag++; 6546 vcpu->mmio_cur_fragment++; 6547 } else { 6548 /* Go forward to the next mmio piece. */ 6549 frag->data += len; 6550 frag->gpa += len; 6551 frag->len -= len; 6552 } 6553 6554 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 6555 vcpu->mmio_needed = 0; 6556 6557 /* FIXME: return into emulator if single-stepping. */ 6558 if (vcpu->mmio_is_write) 6559 return 1; 6560 vcpu->mmio_read_completed = 1; 6561 return complete_emulated_io(vcpu); 6562 } 6563 6564 run->exit_reason = KVM_EXIT_MMIO; 6565 run->mmio.phys_addr = frag->gpa; 6566 if (vcpu->mmio_is_write) 6567 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 6568 run->mmio.len = min(8u, frag->len); 6569 run->mmio.is_write = vcpu->mmio_is_write; 6570 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6571 return 0; 6572 } 6573 6574 6575 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 6576 { 6577 int r; 6578 sigset_t sigsaved; 6579 6580 if (!tsk_used_math(current) && init_fpu(current)) 6581 return -ENOMEM; 6582 6583 if (vcpu->sigset_active) 6584 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); 6585 6586 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 6587 kvm_vcpu_block(vcpu); 6588 kvm_apic_accept_events(vcpu); 6589 clear_bit(KVM_REQ_UNHALT, &vcpu->requests); 6590 r = -EAGAIN; 6591 goto out; 6592 } 6593 6594 /* re-sync apic's tpr */ 6595 if (!irqchip_in_kernel(vcpu->kvm)) { 6596 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 6597 r = -EINVAL; 6598 goto out; 6599 } 6600 } 6601 6602 if (unlikely(vcpu->arch.complete_userspace_io)) { 6603 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 6604 vcpu->arch.complete_userspace_io = NULL; 6605 r = cui(vcpu); 6606 if (r <= 0) 6607 goto out; 6608 } else 6609 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 6610 6611 r = vcpu_run(vcpu); 6612 6613 out: 6614 post_kvm_run_save(vcpu); 6615 if (vcpu->sigset_active) 6616 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 6617 6618 return r; 6619 } 6620 6621 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6622 { 6623 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 6624 /* 6625 * We are here if userspace calls get_regs() in the middle of 6626 * instruction emulation. Registers state needs to be copied 6627 * back from emulation context to vcpu. Userspace shouldn't do 6628 * that usually, but some bad designed PV devices (vmware 6629 * backdoor interface) need this to work 6630 */ 6631 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 6632 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6633 } 6634 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 6635 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 6636 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 6637 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 6638 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 6639 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 6640 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 6641 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 6642 #ifdef CONFIG_X86_64 6643 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 6644 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 6645 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 6646 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 6647 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 6648 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 6649 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 6650 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 6651 #endif 6652 6653 regs->rip = kvm_rip_read(vcpu); 6654 regs->rflags = kvm_get_rflags(vcpu); 6655 6656 return 0; 6657 } 6658 6659 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6660 { 6661 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 6662 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6663 6664 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 6665 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 6666 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 6667 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 6668 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 6669 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 6670 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 6671 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 6672 #ifdef CONFIG_X86_64 6673 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 6674 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 6675 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 6676 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 6677 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 6678 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 6679 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 6680 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 6681 #endif 6682 6683 kvm_rip_write(vcpu, regs->rip); 6684 kvm_set_rflags(vcpu, regs->rflags); 6685 6686 vcpu->arch.exception.pending = false; 6687 6688 kvm_make_request(KVM_REQ_EVENT, vcpu); 6689 6690 return 0; 6691 } 6692 6693 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 6694 { 6695 struct kvm_segment cs; 6696 6697 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 6698 *db = cs.db; 6699 *l = cs.l; 6700 } 6701 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 6702 6703 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 6704 struct kvm_sregs *sregs) 6705 { 6706 struct desc_ptr dt; 6707 6708 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 6709 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 6710 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 6711 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 6712 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 6713 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 6714 6715 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 6716 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 6717 6718 kvm_x86_ops->get_idt(vcpu, &dt); 6719 sregs->idt.limit = dt.size; 6720 sregs->idt.base = dt.address; 6721 kvm_x86_ops->get_gdt(vcpu, &dt); 6722 sregs->gdt.limit = dt.size; 6723 sregs->gdt.base = dt.address; 6724 6725 sregs->cr0 = kvm_read_cr0(vcpu); 6726 sregs->cr2 = vcpu->arch.cr2; 6727 sregs->cr3 = kvm_read_cr3(vcpu); 6728 sregs->cr4 = kvm_read_cr4(vcpu); 6729 sregs->cr8 = kvm_get_cr8(vcpu); 6730 sregs->efer = vcpu->arch.efer; 6731 sregs->apic_base = kvm_get_apic_base(vcpu); 6732 6733 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 6734 6735 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) 6736 set_bit(vcpu->arch.interrupt.nr, 6737 (unsigned long *)sregs->interrupt_bitmap); 6738 6739 return 0; 6740 } 6741 6742 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 6743 struct kvm_mp_state *mp_state) 6744 { 6745 kvm_apic_accept_events(vcpu); 6746 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 6747 vcpu->arch.pv.pv_unhalted) 6748 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 6749 else 6750 mp_state->mp_state = vcpu->arch.mp_state; 6751 6752 return 0; 6753 } 6754 6755 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 6756 struct kvm_mp_state *mp_state) 6757 { 6758 if (!kvm_vcpu_has_lapic(vcpu) && 6759 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 6760 return -EINVAL; 6761 6762 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 6763 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 6764 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 6765 } else 6766 vcpu->arch.mp_state = mp_state->mp_state; 6767 kvm_make_request(KVM_REQ_EVENT, vcpu); 6768 return 0; 6769 } 6770 6771 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 6772 int reason, bool has_error_code, u32 error_code) 6773 { 6774 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6775 int ret; 6776 6777 init_emulate_ctxt(vcpu); 6778 6779 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 6780 has_error_code, error_code); 6781 6782 if (ret) 6783 return EMULATE_FAIL; 6784 6785 kvm_rip_write(vcpu, ctxt->eip); 6786 kvm_set_rflags(vcpu, ctxt->eflags); 6787 kvm_make_request(KVM_REQ_EVENT, vcpu); 6788 return EMULATE_DONE; 6789 } 6790 EXPORT_SYMBOL_GPL(kvm_task_switch); 6791 6792 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 6793 struct kvm_sregs *sregs) 6794 { 6795 struct msr_data apic_base_msr; 6796 int mmu_reset_needed = 0; 6797 int pending_vec, max_bits, idx; 6798 struct desc_ptr dt; 6799 6800 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) 6801 return -EINVAL; 6802 6803 dt.size = sregs->idt.limit; 6804 dt.address = sregs->idt.base; 6805 kvm_x86_ops->set_idt(vcpu, &dt); 6806 dt.size = sregs->gdt.limit; 6807 dt.address = sregs->gdt.base; 6808 kvm_x86_ops->set_gdt(vcpu, &dt); 6809 6810 vcpu->arch.cr2 = sregs->cr2; 6811 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 6812 vcpu->arch.cr3 = sregs->cr3; 6813 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 6814 6815 kvm_set_cr8(vcpu, sregs->cr8); 6816 6817 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 6818 kvm_x86_ops->set_efer(vcpu, sregs->efer); 6819 apic_base_msr.data = sregs->apic_base; 6820 apic_base_msr.host_initiated = true; 6821 kvm_set_apic_base(vcpu, &apic_base_msr); 6822 6823 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 6824 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 6825 vcpu->arch.cr0 = sregs->cr0; 6826 6827 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 6828 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 6829 if (sregs->cr4 & X86_CR4_OSXSAVE) 6830 kvm_update_cpuid(vcpu); 6831 6832 idx = srcu_read_lock(&vcpu->kvm->srcu); 6833 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 6834 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 6835 mmu_reset_needed = 1; 6836 } 6837 srcu_read_unlock(&vcpu->kvm->srcu, idx); 6838 6839 if (mmu_reset_needed) 6840 kvm_mmu_reset_context(vcpu); 6841 6842 max_bits = KVM_NR_INTERRUPTS; 6843 pending_vec = find_first_bit( 6844 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 6845 if (pending_vec < max_bits) { 6846 kvm_queue_interrupt(vcpu, pending_vec, false); 6847 pr_debug("Set back pending irq %d\n", pending_vec); 6848 } 6849 6850 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 6851 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 6852 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 6853 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 6854 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 6855 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 6856 6857 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 6858 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 6859 6860 update_cr8_intercept(vcpu); 6861 6862 /* Older userspace won't unhalt the vcpu on reset. */ 6863 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 6864 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 6865 !is_protmode(vcpu)) 6866 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 6867 6868 kvm_make_request(KVM_REQ_EVENT, vcpu); 6869 6870 return 0; 6871 } 6872 6873 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 6874 struct kvm_guest_debug *dbg) 6875 { 6876 unsigned long rflags; 6877 int i, r; 6878 6879 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 6880 r = -EBUSY; 6881 if (vcpu->arch.exception.pending) 6882 goto out; 6883 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 6884 kvm_queue_exception(vcpu, DB_VECTOR); 6885 else 6886 kvm_queue_exception(vcpu, BP_VECTOR); 6887 } 6888 6889 /* 6890 * Read rflags as long as potentially injected trace flags are still 6891 * filtered out. 6892 */ 6893 rflags = kvm_get_rflags(vcpu); 6894 6895 vcpu->guest_debug = dbg->control; 6896 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 6897 vcpu->guest_debug = 0; 6898 6899 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 6900 for (i = 0; i < KVM_NR_DB_REGS; ++i) 6901 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 6902 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 6903 } else { 6904 for (i = 0; i < KVM_NR_DB_REGS; i++) 6905 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 6906 } 6907 kvm_update_dr7(vcpu); 6908 6909 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6910 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 6911 get_segment_base(vcpu, VCPU_SREG_CS); 6912 6913 /* 6914 * Trigger an rflags update that will inject or remove the trace 6915 * flags. 6916 */ 6917 kvm_set_rflags(vcpu, rflags); 6918 6919 kvm_x86_ops->update_db_bp_intercept(vcpu); 6920 6921 r = 0; 6922 6923 out: 6924 6925 return r; 6926 } 6927 6928 /* 6929 * Translate a guest virtual address to a guest physical address. 6930 */ 6931 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 6932 struct kvm_translation *tr) 6933 { 6934 unsigned long vaddr = tr->linear_address; 6935 gpa_t gpa; 6936 int idx; 6937 6938 idx = srcu_read_lock(&vcpu->kvm->srcu); 6939 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 6940 srcu_read_unlock(&vcpu->kvm->srcu, idx); 6941 tr->physical_address = gpa; 6942 tr->valid = gpa != UNMAPPED_GVA; 6943 tr->writeable = 1; 6944 tr->usermode = 0; 6945 6946 return 0; 6947 } 6948 6949 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 6950 { 6951 struct i387_fxsave_struct *fxsave = 6952 &vcpu->arch.guest_fpu.state->fxsave; 6953 6954 memcpy(fpu->fpr, fxsave->st_space, 128); 6955 fpu->fcw = fxsave->cwd; 6956 fpu->fsw = fxsave->swd; 6957 fpu->ftwx = fxsave->twd; 6958 fpu->last_opcode = fxsave->fop; 6959 fpu->last_ip = fxsave->rip; 6960 fpu->last_dp = fxsave->rdp; 6961 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 6962 6963 return 0; 6964 } 6965 6966 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 6967 { 6968 struct i387_fxsave_struct *fxsave = 6969 &vcpu->arch.guest_fpu.state->fxsave; 6970 6971 memcpy(fxsave->st_space, fpu->fpr, 128); 6972 fxsave->cwd = fpu->fcw; 6973 fxsave->swd = fpu->fsw; 6974 fxsave->twd = fpu->ftwx; 6975 fxsave->fop = fpu->last_opcode; 6976 fxsave->rip = fpu->last_ip; 6977 fxsave->rdp = fpu->last_dp; 6978 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 6979 6980 return 0; 6981 } 6982 6983 int fx_init(struct kvm_vcpu *vcpu) 6984 { 6985 int err; 6986 6987 err = fpu_alloc(&vcpu->arch.guest_fpu); 6988 if (err) 6989 return err; 6990 6991 fpu_finit(&vcpu->arch.guest_fpu); 6992 if (cpu_has_xsaves) 6993 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv = 6994 host_xcr0 | XSTATE_COMPACTION_ENABLED; 6995 6996 /* 6997 * Ensure guest xcr0 is valid for loading 6998 */ 6999 vcpu->arch.xcr0 = XSTATE_FP; 7000 7001 vcpu->arch.cr0 |= X86_CR0_ET; 7002 7003 return 0; 7004 } 7005 EXPORT_SYMBOL_GPL(fx_init); 7006 7007 static void fx_free(struct kvm_vcpu *vcpu) 7008 { 7009 fpu_free(&vcpu->arch.guest_fpu); 7010 } 7011 7012 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 7013 { 7014 if (vcpu->guest_fpu_loaded) 7015 return; 7016 7017 /* 7018 * Restore all possible states in the guest, 7019 * and assume host would use all available bits. 7020 * Guest xcr0 would be loaded later. 7021 */ 7022 kvm_put_guest_xcr0(vcpu); 7023 vcpu->guest_fpu_loaded = 1; 7024 __kernel_fpu_begin(); 7025 fpu_restore_checking(&vcpu->arch.guest_fpu); 7026 trace_kvm_fpu(1); 7027 } 7028 7029 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 7030 { 7031 kvm_put_guest_xcr0(vcpu); 7032 7033 if (!vcpu->guest_fpu_loaded) 7034 return; 7035 7036 vcpu->guest_fpu_loaded = 0; 7037 fpu_save_init(&vcpu->arch.guest_fpu); 7038 __kernel_fpu_end(); 7039 ++vcpu->stat.fpu_reload; 7040 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); 7041 trace_kvm_fpu(0); 7042 } 7043 7044 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 7045 { 7046 kvmclock_reset(vcpu); 7047 7048 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 7049 fx_free(vcpu); 7050 kvm_x86_ops->vcpu_free(vcpu); 7051 } 7052 7053 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 7054 unsigned int id) 7055 { 7056 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 7057 printk_once(KERN_WARNING 7058 "kvm: SMP vm created on host with unstable TSC; " 7059 "guest TSC will not be reliable\n"); 7060 return kvm_x86_ops->vcpu_create(kvm, id); 7061 } 7062 7063 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 7064 { 7065 int r; 7066 7067 vcpu->arch.mtrr_state.have_fixed = 1; 7068 r = vcpu_load(vcpu); 7069 if (r) 7070 return r; 7071 kvm_vcpu_reset(vcpu); 7072 kvm_mmu_setup(vcpu); 7073 vcpu_put(vcpu); 7074 7075 return r; 7076 } 7077 7078 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 7079 { 7080 struct msr_data msr; 7081 struct kvm *kvm = vcpu->kvm; 7082 7083 if (vcpu_load(vcpu)) 7084 return; 7085 msr.data = 0x0; 7086 msr.index = MSR_IA32_TSC; 7087 msr.host_initiated = true; 7088 kvm_write_tsc(vcpu, &msr); 7089 vcpu_put(vcpu); 7090 7091 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 7092 KVMCLOCK_SYNC_PERIOD); 7093 } 7094 7095 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 7096 { 7097 int r; 7098 vcpu->arch.apf.msr_val = 0; 7099 7100 r = vcpu_load(vcpu); 7101 BUG_ON(r); 7102 kvm_mmu_unload(vcpu); 7103 vcpu_put(vcpu); 7104 7105 fx_free(vcpu); 7106 kvm_x86_ops->vcpu_free(vcpu); 7107 } 7108 7109 void kvm_vcpu_reset(struct kvm_vcpu *vcpu) 7110 { 7111 atomic_set(&vcpu->arch.nmi_queued, 0); 7112 vcpu->arch.nmi_pending = 0; 7113 vcpu->arch.nmi_injected = false; 7114 kvm_clear_interrupt_queue(vcpu); 7115 kvm_clear_exception_queue(vcpu); 7116 7117 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 7118 kvm_update_dr0123(vcpu); 7119 vcpu->arch.dr6 = DR6_INIT; 7120 kvm_update_dr6(vcpu); 7121 vcpu->arch.dr7 = DR7_FIXED_1; 7122 kvm_update_dr7(vcpu); 7123 7124 vcpu->arch.cr2 = 0; 7125 7126 kvm_make_request(KVM_REQ_EVENT, vcpu); 7127 vcpu->arch.apf.msr_val = 0; 7128 vcpu->arch.st.msr_val = 0; 7129 7130 kvmclock_reset(vcpu); 7131 7132 kvm_clear_async_pf_completion_queue(vcpu); 7133 kvm_async_pf_hash_reset(vcpu); 7134 vcpu->arch.apf.halted = false; 7135 7136 kvm_pmu_reset(vcpu); 7137 7138 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 7139 vcpu->arch.regs_avail = ~0; 7140 vcpu->arch.regs_dirty = ~0; 7141 7142 kvm_x86_ops->vcpu_reset(vcpu); 7143 } 7144 7145 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 7146 { 7147 struct kvm_segment cs; 7148 7149 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7150 cs.selector = vector << 8; 7151 cs.base = vector << 12; 7152 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7153 kvm_rip_write(vcpu, 0); 7154 } 7155 7156 int kvm_arch_hardware_enable(void) 7157 { 7158 struct kvm *kvm; 7159 struct kvm_vcpu *vcpu; 7160 int i; 7161 int ret; 7162 u64 local_tsc; 7163 u64 max_tsc = 0; 7164 bool stable, backwards_tsc = false; 7165 7166 kvm_shared_msr_cpu_online(); 7167 ret = kvm_x86_ops->hardware_enable(); 7168 if (ret != 0) 7169 return ret; 7170 7171 local_tsc = native_read_tsc(); 7172 stable = !check_tsc_unstable(); 7173 list_for_each_entry(kvm, &vm_list, vm_list) { 7174 kvm_for_each_vcpu(i, vcpu, kvm) { 7175 if (!stable && vcpu->cpu == smp_processor_id()) 7176 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7177 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 7178 backwards_tsc = true; 7179 if (vcpu->arch.last_host_tsc > max_tsc) 7180 max_tsc = vcpu->arch.last_host_tsc; 7181 } 7182 } 7183 } 7184 7185 /* 7186 * Sometimes, even reliable TSCs go backwards. This happens on 7187 * platforms that reset TSC during suspend or hibernate actions, but 7188 * maintain synchronization. We must compensate. Fortunately, we can 7189 * detect that condition here, which happens early in CPU bringup, 7190 * before any KVM threads can be running. Unfortunately, we can't 7191 * bring the TSCs fully up to date with real time, as we aren't yet far 7192 * enough into CPU bringup that we know how much real time has actually 7193 * elapsed; our helper function, get_kernel_ns() will be using boot 7194 * variables that haven't been updated yet. 7195 * 7196 * So we simply find the maximum observed TSC above, then record the 7197 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 7198 * the adjustment will be applied. Note that we accumulate 7199 * adjustments, in case multiple suspend cycles happen before some VCPU 7200 * gets a chance to run again. In the event that no KVM threads get a 7201 * chance to run, we will miss the entire elapsed period, as we'll have 7202 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 7203 * loose cycle time. This isn't too big a deal, since the loss will be 7204 * uniform across all VCPUs (not to mention the scenario is extremely 7205 * unlikely). It is possible that a second hibernate recovery happens 7206 * much faster than a first, causing the observed TSC here to be 7207 * smaller; this would require additional padding adjustment, which is 7208 * why we set last_host_tsc to the local tsc observed here. 7209 * 7210 * N.B. - this code below runs only on platforms with reliable TSC, 7211 * as that is the only way backwards_tsc is set above. Also note 7212 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 7213 * have the same delta_cyc adjustment applied if backwards_tsc 7214 * is detected. Note further, this adjustment is only done once, 7215 * as we reset last_host_tsc on all VCPUs to stop this from being 7216 * called multiple times (one for each physical CPU bringup). 7217 * 7218 * Platforms with unreliable TSCs don't have to deal with this, they 7219 * will be compensated by the logic in vcpu_load, which sets the TSC to 7220 * catchup mode. This will catchup all VCPUs to real time, but cannot 7221 * guarantee that they stay in perfect synchronization. 7222 */ 7223 if (backwards_tsc) { 7224 u64 delta_cyc = max_tsc - local_tsc; 7225 backwards_tsc_observed = true; 7226 list_for_each_entry(kvm, &vm_list, vm_list) { 7227 kvm_for_each_vcpu(i, vcpu, kvm) { 7228 vcpu->arch.tsc_offset_adjustment += delta_cyc; 7229 vcpu->arch.last_host_tsc = local_tsc; 7230 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7231 } 7232 7233 /* 7234 * We have to disable TSC offset matching.. if you were 7235 * booting a VM while issuing an S4 host suspend.... 7236 * you may have some problem. Solving this issue is 7237 * left as an exercise to the reader. 7238 */ 7239 kvm->arch.last_tsc_nsec = 0; 7240 kvm->arch.last_tsc_write = 0; 7241 } 7242 7243 } 7244 return 0; 7245 } 7246 7247 void kvm_arch_hardware_disable(void) 7248 { 7249 kvm_x86_ops->hardware_disable(); 7250 drop_user_return_notifiers(); 7251 } 7252 7253 int kvm_arch_hardware_setup(void) 7254 { 7255 int r; 7256 7257 r = kvm_x86_ops->hardware_setup(); 7258 if (r != 0) 7259 return r; 7260 7261 kvm_init_msr_list(); 7262 return 0; 7263 } 7264 7265 void kvm_arch_hardware_unsetup(void) 7266 { 7267 kvm_x86_ops->hardware_unsetup(); 7268 } 7269 7270 void kvm_arch_check_processor_compat(void *rtn) 7271 { 7272 kvm_x86_ops->check_processor_compatibility(rtn); 7273 } 7274 7275 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) 7276 { 7277 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL); 7278 } 7279 7280 struct static_key kvm_no_apic_vcpu __read_mostly; 7281 7282 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 7283 { 7284 struct page *page; 7285 struct kvm *kvm; 7286 int r; 7287 7288 BUG_ON(vcpu->kvm == NULL); 7289 kvm = vcpu->kvm; 7290 7291 vcpu->arch.pv.pv_unhalted = false; 7292 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 7293 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 7294 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7295 else 7296 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 7297 7298 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 7299 if (!page) { 7300 r = -ENOMEM; 7301 goto fail; 7302 } 7303 vcpu->arch.pio_data = page_address(page); 7304 7305 kvm_set_tsc_khz(vcpu, max_tsc_khz); 7306 7307 r = kvm_mmu_create(vcpu); 7308 if (r < 0) 7309 goto fail_free_pio_data; 7310 7311 if (irqchip_in_kernel(kvm)) { 7312 r = kvm_create_lapic(vcpu); 7313 if (r < 0) 7314 goto fail_mmu_destroy; 7315 } else 7316 static_key_slow_inc(&kvm_no_apic_vcpu); 7317 7318 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 7319 GFP_KERNEL); 7320 if (!vcpu->arch.mce_banks) { 7321 r = -ENOMEM; 7322 goto fail_free_lapic; 7323 } 7324 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 7325 7326 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 7327 r = -ENOMEM; 7328 goto fail_free_mce_banks; 7329 } 7330 7331 r = fx_init(vcpu); 7332 if (r) 7333 goto fail_free_wbinvd_dirty_mask; 7334 7335 vcpu->arch.ia32_tsc_adjust_msr = 0x0; 7336 vcpu->arch.pv_time_enabled = false; 7337 7338 vcpu->arch.guest_supported_xcr0 = 0; 7339 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 7340 7341 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 7342 7343 kvm_async_pf_hash_reset(vcpu); 7344 kvm_pmu_init(vcpu); 7345 7346 return 0; 7347 fail_free_wbinvd_dirty_mask: 7348 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 7349 fail_free_mce_banks: 7350 kfree(vcpu->arch.mce_banks); 7351 fail_free_lapic: 7352 kvm_free_lapic(vcpu); 7353 fail_mmu_destroy: 7354 kvm_mmu_destroy(vcpu); 7355 fail_free_pio_data: 7356 free_page((unsigned long)vcpu->arch.pio_data); 7357 fail: 7358 return r; 7359 } 7360 7361 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 7362 { 7363 int idx; 7364 7365 kvm_pmu_destroy(vcpu); 7366 kfree(vcpu->arch.mce_banks); 7367 kvm_free_lapic(vcpu); 7368 idx = srcu_read_lock(&vcpu->kvm->srcu); 7369 kvm_mmu_destroy(vcpu); 7370 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7371 free_page((unsigned long)vcpu->arch.pio_data); 7372 if (!irqchip_in_kernel(vcpu->kvm)) 7373 static_key_slow_dec(&kvm_no_apic_vcpu); 7374 } 7375 7376 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 7377 { 7378 kvm_x86_ops->sched_in(vcpu, cpu); 7379 } 7380 7381 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 7382 { 7383 if (type) 7384 return -EINVAL; 7385 7386 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 7387 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 7388 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 7389 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 7390 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 7391 7392 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 7393 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 7394 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 7395 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 7396 &kvm->arch.irq_sources_bitmap); 7397 7398 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 7399 mutex_init(&kvm->arch.apic_map_lock); 7400 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 7401 7402 pvclock_update_vm_gtod_copy(kvm); 7403 7404 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 7405 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 7406 7407 return 0; 7408 } 7409 7410 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 7411 { 7412 int r; 7413 r = vcpu_load(vcpu); 7414 BUG_ON(r); 7415 kvm_mmu_unload(vcpu); 7416 vcpu_put(vcpu); 7417 } 7418 7419 static void kvm_free_vcpus(struct kvm *kvm) 7420 { 7421 unsigned int i; 7422 struct kvm_vcpu *vcpu; 7423 7424 /* 7425 * Unpin any mmu pages first. 7426 */ 7427 kvm_for_each_vcpu(i, vcpu, kvm) { 7428 kvm_clear_async_pf_completion_queue(vcpu); 7429 kvm_unload_vcpu_mmu(vcpu); 7430 } 7431 kvm_for_each_vcpu(i, vcpu, kvm) 7432 kvm_arch_vcpu_free(vcpu); 7433 7434 mutex_lock(&kvm->lock); 7435 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 7436 kvm->vcpus[i] = NULL; 7437 7438 atomic_set(&kvm->online_vcpus, 0); 7439 mutex_unlock(&kvm->lock); 7440 } 7441 7442 void kvm_arch_sync_events(struct kvm *kvm) 7443 { 7444 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 7445 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 7446 kvm_free_all_assigned_devices(kvm); 7447 kvm_free_pit(kvm); 7448 } 7449 7450 void kvm_arch_destroy_vm(struct kvm *kvm) 7451 { 7452 if (current->mm == kvm->mm) { 7453 /* 7454 * Free memory regions allocated on behalf of userspace, 7455 * unless the the memory map has changed due to process exit 7456 * or fd copying. 7457 */ 7458 struct kvm_userspace_memory_region mem; 7459 memset(&mem, 0, sizeof(mem)); 7460 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; 7461 kvm_set_memory_region(kvm, &mem); 7462 7463 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; 7464 kvm_set_memory_region(kvm, &mem); 7465 7466 mem.slot = TSS_PRIVATE_MEMSLOT; 7467 kvm_set_memory_region(kvm, &mem); 7468 } 7469 kvm_iommu_unmap_guest(kvm); 7470 kfree(kvm->arch.vpic); 7471 kfree(kvm->arch.vioapic); 7472 kvm_free_vcpus(kvm); 7473 kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 7474 } 7475 7476 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 7477 struct kvm_memory_slot *dont) 7478 { 7479 int i; 7480 7481 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7482 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 7483 kvfree(free->arch.rmap[i]); 7484 free->arch.rmap[i] = NULL; 7485 } 7486 if (i == 0) 7487 continue; 7488 7489 if (!dont || free->arch.lpage_info[i - 1] != 7490 dont->arch.lpage_info[i - 1]) { 7491 kvfree(free->arch.lpage_info[i - 1]); 7492 free->arch.lpage_info[i - 1] = NULL; 7493 } 7494 } 7495 } 7496 7497 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 7498 unsigned long npages) 7499 { 7500 int i; 7501 7502 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7503 unsigned long ugfn; 7504 int lpages; 7505 int level = i + 1; 7506 7507 lpages = gfn_to_index(slot->base_gfn + npages - 1, 7508 slot->base_gfn, level) + 1; 7509 7510 slot->arch.rmap[i] = 7511 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); 7512 if (!slot->arch.rmap[i]) 7513 goto out_free; 7514 if (i == 0) 7515 continue; 7516 7517 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages * 7518 sizeof(*slot->arch.lpage_info[i - 1])); 7519 if (!slot->arch.lpage_info[i - 1]) 7520 goto out_free; 7521 7522 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 7523 slot->arch.lpage_info[i - 1][0].write_count = 1; 7524 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 7525 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1; 7526 ugfn = slot->userspace_addr >> PAGE_SHIFT; 7527 /* 7528 * If the gfn and userspace address are not aligned wrt each 7529 * other, or if explicitly asked to, disable large page 7530 * support for this slot 7531 */ 7532 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 7533 !kvm_largepages_enabled()) { 7534 unsigned long j; 7535 7536 for (j = 0; j < lpages; ++j) 7537 slot->arch.lpage_info[i - 1][j].write_count = 1; 7538 } 7539 } 7540 7541 return 0; 7542 7543 out_free: 7544 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7545 kvfree(slot->arch.rmap[i]); 7546 slot->arch.rmap[i] = NULL; 7547 if (i == 0) 7548 continue; 7549 7550 kvfree(slot->arch.lpage_info[i - 1]); 7551 slot->arch.lpage_info[i - 1] = NULL; 7552 } 7553 return -ENOMEM; 7554 } 7555 7556 void kvm_arch_memslots_updated(struct kvm *kvm) 7557 { 7558 /* 7559 * memslots->generation has been incremented. 7560 * mmio generation may have reached its maximum value. 7561 */ 7562 kvm_mmu_invalidate_mmio_sptes(kvm); 7563 } 7564 7565 int kvm_arch_prepare_memory_region(struct kvm *kvm, 7566 struct kvm_memory_slot *memslot, 7567 struct kvm_userspace_memory_region *mem, 7568 enum kvm_mr_change change) 7569 { 7570 /* 7571 * Only private memory slots need to be mapped here since 7572 * KVM_SET_MEMORY_REGION ioctl is no longer supported. 7573 */ 7574 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) { 7575 unsigned long userspace_addr; 7576 7577 /* 7578 * MAP_SHARED to prevent internal slot pages from being moved 7579 * by fork()/COW. 7580 */ 7581 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE, 7582 PROT_READ | PROT_WRITE, 7583 MAP_SHARED | MAP_ANONYMOUS, 0); 7584 7585 if (IS_ERR((void *)userspace_addr)) 7586 return PTR_ERR((void *)userspace_addr); 7587 7588 memslot->userspace_addr = userspace_addr; 7589 } 7590 7591 return 0; 7592 } 7593 7594 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 7595 struct kvm_memory_slot *new) 7596 { 7597 /* Still write protect RO slot */ 7598 if (new->flags & KVM_MEM_READONLY) { 7599 kvm_mmu_slot_remove_write_access(kvm, new); 7600 return; 7601 } 7602 7603 /* 7604 * Call kvm_x86_ops dirty logging hooks when they are valid. 7605 * 7606 * kvm_x86_ops->slot_disable_log_dirty is called when: 7607 * 7608 * - KVM_MR_CREATE with dirty logging is disabled 7609 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 7610 * 7611 * The reason is, in case of PML, we need to set D-bit for any slots 7612 * with dirty logging disabled in order to eliminate unnecessary GPA 7613 * logging in PML buffer (and potential PML buffer full VMEXT). This 7614 * guarantees leaving PML enabled during guest's lifetime won't have 7615 * any additonal overhead from PML when guest is running with dirty 7616 * logging disabled for memory slots. 7617 * 7618 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 7619 * to dirty logging mode. 7620 * 7621 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 7622 * 7623 * In case of write protect: 7624 * 7625 * Write protect all pages for dirty logging. 7626 * 7627 * All the sptes including the large sptes which point to this 7628 * slot are set to readonly. We can not create any new large 7629 * spte on this slot until the end of the logging. 7630 * 7631 * See the comments in fast_page_fault(). 7632 */ 7633 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 7634 if (kvm_x86_ops->slot_enable_log_dirty) 7635 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 7636 else 7637 kvm_mmu_slot_remove_write_access(kvm, new); 7638 } else { 7639 if (kvm_x86_ops->slot_disable_log_dirty) 7640 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 7641 } 7642 } 7643 7644 void kvm_arch_commit_memory_region(struct kvm *kvm, 7645 struct kvm_userspace_memory_region *mem, 7646 const struct kvm_memory_slot *old, 7647 enum kvm_mr_change change) 7648 { 7649 struct kvm_memory_slot *new; 7650 int nr_mmu_pages = 0; 7651 7652 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) { 7653 int ret; 7654 7655 ret = vm_munmap(old->userspace_addr, 7656 old->npages * PAGE_SIZE); 7657 if (ret < 0) 7658 printk(KERN_WARNING 7659 "kvm_vm_ioctl_set_memory_region: " 7660 "failed to munmap memory\n"); 7661 } 7662 7663 if (!kvm->arch.n_requested_mmu_pages) 7664 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 7665 7666 if (nr_mmu_pages) 7667 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 7668 7669 /* It's OK to get 'new' slot here as it has already been installed */ 7670 new = id_to_memslot(kvm->memslots, mem->slot); 7671 7672 /* 7673 * Dirty logging tracks sptes in 4k granularity, meaning that large 7674 * sptes have to be split. If live migration is successful, the guest 7675 * in the source machine will be destroyed and large sptes will be 7676 * created in the destination. However, if the guest continues to run 7677 * in the source machine (for example if live migration fails), small 7678 * sptes will remain around and cause bad performance. 7679 * 7680 * Scan sptes if dirty logging has been stopped, dropping those 7681 * which can be collapsed into a single large-page spte. Later 7682 * page faults will create the large-page sptes. 7683 */ 7684 if ((change != KVM_MR_DELETE) && 7685 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 7686 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 7687 kvm_mmu_zap_collapsible_sptes(kvm, new); 7688 7689 /* 7690 * Set up write protection and/or dirty logging for the new slot. 7691 * 7692 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 7693 * been zapped so no dirty logging staff is needed for old slot. For 7694 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 7695 * new and it's also covered when dealing with the new slot. 7696 */ 7697 if (change != KVM_MR_DELETE) 7698 kvm_mmu_slot_apply_flags(kvm, new); 7699 } 7700 7701 void kvm_arch_flush_shadow_all(struct kvm *kvm) 7702 { 7703 kvm_mmu_invalidate_zap_all_pages(kvm); 7704 } 7705 7706 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 7707 struct kvm_memory_slot *slot) 7708 { 7709 kvm_mmu_invalidate_zap_all_pages(kvm); 7710 } 7711 7712 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 7713 { 7714 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 7715 kvm_x86_ops->check_nested_events(vcpu, false); 7716 7717 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 7718 !vcpu->arch.apf.halted) 7719 || !list_empty_careful(&vcpu->async_pf.done) 7720 || kvm_apic_has_events(vcpu) 7721 || vcpu->arch.pv.pv_unhalted 7722 || atomic_read(&vcpu->arch.nmi_queued) || 7723 (kvm_arch_interrupt_allowed(vcpu) && 7724 kvm_cpu_has_interrupt(vcpu)); 7725 } 7726 7727 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 7728 { 7729 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 7730 } 7731 7732 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 7733 { 7734 return kvm_x86_ops->interrupt_allowed(vcpu); 7735 } 7736 7737 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 7738 { 7739 if (is_64_bit_mode(vcpu)) 7740 return kvm_rip_read(vcpu); 7741 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 7742 kvm_rip_read(vcpu)); 7743 } 7744 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 7745 7746 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 7747 { 7748 return kvm_get_linear_rip(vcpu) == linear_rip; 7749 } 7750 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 7751 7752 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 7753 { 7754 unsigned long rflags; 7755 7756 rflags = kvm_x86_ops->get_rflags(vcpu); 7757 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 7758 rflags &= ~X86_EFLAGS_TF; 7759 return rflags; 7760 } 7761 EXPORT_SYMBOL_GPL(kvm_get_rflags); 7762 7763 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 7764 { 7765 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 7766 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 7767 rflags |= X86_EFLAGS_TF; 7768 kvm_x86_ops->set_rflags(vcpu, rflags); 7769 } 7770 7771 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 7772 { 7773 __kvm_set_rflags(vcpu, rflags); 7774 kvm_make_request(KVM_REQ_EVENT, vcpu); 7775 } 7776 EXPORT_SYMBOL_GPL(kvm_set_rflags); 7777 7778 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 7779 { 7780 int r; 7781 7782 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 7783 work->wakeup_all) 7784 return; 7785 7786 r = kvm_mmu_reload(vcpu); 7787 if (unlikely(r)) 7788 return; 7789 7790 if (!vcpu->arch.mmu.direct_map && 7791 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 7792 return; 7793 7794 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 7795 } 7796 7797 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 7798 { 7799 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 7800 } 7801 7802 static inline u32 kvm_async_pf_next_probe(u32 key) 7803 { 7804 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 7805 } 7806 7807 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7808 { 7809 u32 key = kvm_async_pf_hash_fn(gfn); 7810 7811 while (vcpu->arch.apf.gfns[key] != ~0) 7812 key = kvm_async_pf_next_probe(key); 7813 7814 vcpu->arch.apf.gfns[key] = gfn; 7815 } 7816 7817 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 7818 { 7819 int i; 7820 u32 key = kvm_async_pf_hash_fn(gfn); 7821 7822 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 7823 (vcpu->arch.apf.gfns[key] != gfn && 7824 vcpu->arch.apf.gfns[key] != ~0); i++) 7825 key = kvm_async_pf_next_probe(key); 7826 7827 return key; 7828 } 7829 7830 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7831 { 7832 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 7833 } 7834 7835 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7836 { 7837 u32 i, j, k; 7838 7839 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 7840 while (true) { 7841 vcpu->arch.apf.gfns[i] = ~0; 7842 do { 7843 j = kvm_async_pf_next_probe(j); 7844 if (vcpu->arch.apf.gfns[j] == ~0) 7845 return; 7846 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 7847 /* 7848 * k lies cyclically in ]i,j] 7849 * | i.k.j | 7850 * |....j i.k.| or |.k..j i...| 7851 */ 7852 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 7853 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 7854 i = j; 7855 } 7856 } 7857 7858 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 7859 { 7860 7861 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 7862 sizeof(val)); 7863 } 7864 7865 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 7866 struct kvm_async_pf *work) 7867 { 7868 struct x86_exception fault; 7869 7870 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 7871 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 7872 7873 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 7874 (vcpu->arch.apf.send_user_only && 7875 kvm_x86_ops->get_cpl(vcpu) == 0)) 7876 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 7877 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 7878 fault.vector = PF_VECTOR; 7879 fault.error_code_valid = true; 7880 fault.error_code = 0; 7881 fault.nested_page_fault = false; 7882 fault.address = work->arch.token; 7883 kvm_inject_page_fault(vcpu, &fault); 7884 } 7885 } 7886 7887 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 7888 struct kvm_async_pf *work) 7889 { 7890 struct x86_exception fault; 7891 7892 trace_kvm_async_pf_ready(work->arch.token, work->gva); 7893 if (work->wakeup_all) 7894 work->arch.token = ~0; /* broadcast wakeup */ 7895 else 7896 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 7897 7898 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && 7899 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 7900 fault.vector = PF_VECTOR; 7901 fault.error_code_valid = true; 7902 fault.error_code = 0; 7903 fault.nested_page_fault = false; 7904 fault.address = work->arch.token; 7905 kvm_inject_page_fault(vcpu, &fault); 7906 } 7907 vcpu->arch.apf.halted = false; 7908 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7909 } 7910 7911 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 7912 { 7913 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 7914 return true; 7915 else 7916 return !kvm_event_needs_reinjection(vcpu) && 7917 kvm_x86_ops->interrupt_allowed(vcpu); 7918 } 7919 7920 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 7921 { 7922 atomic_inc(&kvm->arch.noncoherent_dma_count); 7923 } 7924 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 7925 7926 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 7927 { 7928 atomic_dec(&kvm->arch.noncoherent_dma_count); 7929 } 7930 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 7931 7932 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 7933 { 7934 return atomic_read(&kvm->arch.noncoherent_dma_count); 7935 } 7936 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 7937 7938 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 7939 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 7940 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 7941 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 7942 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 7943 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 7944 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 7945 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 7946 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 7947 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 7948 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 7949 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 7950 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 7951 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 7952 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 7953