1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * derived from drivers/kvm/kvm_main.c 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright (C) 2008 Qumranet, Inc. 9 * Copyright IBM Corporation, 2008 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 11 * 12 * Authors: 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * Amit Shah <amit.shah@qumranet.com> 16 * Ben-Ami Yassour <benami@il.ibm.com> 17 */ 18 19 #include <linux/kvm_host.h> 20 #include "irq.h" 21 #include "ioapic.h" 22 #include "mmu.h" 23 #include "i8254.h" 24 #include "tss.h" 25 #include "kvm_cache_regs.h" 26 #include "kvm_emulate.h" 27 #include "x86.h" 28 #include "cpuid.h" 29 #include "pmu.h" 30 #include "hyperv.h" 31 #include "lapic.h" 32 #include "xen.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/export.h> 40 #include <linux/moduleparam.h> 41 #include <linux/mman.h> 42 #include <linux/highmem.h> 43 #include <linux/iommu.h> 44 #include <linux/intel-iommu.h> 45 #include <linux/cpufreq.h> 46 #include <linux/user-return-notifier.h> 47 #include <linux/srcu.h> 48 #include <linux/slab.h> 49 #include <linux/perf_event.h> 50 #include <linux/uaccess.h> 51 #include <linux/hash.h> 52 #include <linux/pci.h> 53 #include <linux/timekeeper_internal.h> 54 #include <linux/pvclock_gtod.h> 55 #include <linux/kvm_irqfd.h> 56 #include <linux/irqbypass.h> 57 #include <linux/sched/stat.h> 58 #include <linux/sched/isolation.h> 59 #include <linux/mem_encrypt.h> 60 #include <linux/entry-kvm.h> 61 #include <linux/suspend.h> 62 63 #include <trace/events/kvm.h> 64 65 #include <asm/debugreg.h> 66 #include <asm/msr.h> 67 #include <asm/desc.h> 68 #include <asm/mce.h> 69 #include <asm/pkru.h> 70 #include <linux/kernel_stat.h> 71 #include <asm/fpu/api.h> 72 #include <asm/fpu/xcr.h> 73 #include <asm/fpu/xstate.h> 74 #include <asm/pvclock.h> 75 #include <asm/div64.h> 76 #include <asm/irq_remapping.h> 77 #include <asm/mshyperv.h> 78 #include <asm/hypervisor.h> 79 #include <asm/tlbflush.h> 80 #include <asm/intel_pt.h> 81 #include <asm/emulate_prefix.h> 82 #include <asm/sgx.h> 83 #include <clocksource/hyperv_timer.h> 84 85 #define CREATE_TRACE_POINTS 86 #include "trace.h" 87 88 #define MAX_IO_MSRS 256 89 #define KVM_MAX_MCE_BANKS 32 90 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 91 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 92 93 #define emul_to_vcpu(ctxt) \ 94 ((struct kvm_vcpu *)(ctxt)->vcpu) 95 96 /* EFER defaults: 97 * - enable syscall per default because its emulated by KVM 98 * - enable LME and LMA per default on 64 bit KVM 99 */ 100 #ifdef CONFIG_X86_64 101 static 102 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 103 #else 104 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 105 #endif 106 107 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; 108 109 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) 110 111 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 112 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 113 114 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 115 static void process_nmi(struct kvm_vcpu *vcpu); 116 static void process_smi(struct kvm_vcpu *vcpu); 117 static void enter_smm(struct kvm_vcpu *vcpu); 118 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 119 static void store_regs(struct kvm_vcpu *vcpu); 120 static int sync_regs(struct kvm_vcpu *vcpu); 121 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu); 122 123 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 124 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 125 126 struct kvm_x86_ops kvm_x86_ops __read_mostly; 127 EXPORT_SYMBOL_GPL(kvm_x86_ops); 128 129 #define KVM_X86_OP(func) \ 130 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ 131 *(((struct kvm_x86_ops *)0)->func)); 132 #define KVM_X86_OP_NULL KVM_X86_OP 133 #include <asm/kvm-x86-ops.h> 134 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); 135 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); 136 EXPORT_STATIC_CALL_GPL(kvm_x86_tlb_flush_current); 137 138 static bool __read_mostly ignore_msrs = 0; 139 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 140 141 bool __read_mostly report_ignored_msrs = true; 142 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 143 EXPORT_SYMBOL_GPL(report_ignored_msrs); 144 145 unsigned int min_timer_period_us = 200; 146 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 147 148 static bool __read_mostly kvmclock_periodic_sync = true; 149 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 150 151 bool __read_mostly kvm_has_tsc_control; 152 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 153 u32 __read_mostly kvm_max_guest_tsc_khz; 154 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 155 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 156 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 157 u64 __read_mostly kvm_max_tsc_scaling_ratio; 158 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 159 u64 __read_mostly kvm_default_tsc_scaling_ratio; 160 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 161 bool __read_mostly kvm_has_bus_lock_exit; 162 EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit); 163 164 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 165 static u32 __read_mostly tsc_tolerance_ppm = 250; 166 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 167 168 /* 169 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 170 * adaptive tuning starting from default advancement of 1000ns. '0' disables 171 * advancement entirely. Any other value is used as-is and disables adaptive 172 * tuning, i.e. allows privileged userspace to set an exact advancement time. 173 */ 174 static int __read_mostly lapic_timer_advance_ns = -1; 175 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); 176 177 static bool __read_mostly vector_hashing = true; 178 module_param(vector_hashing, bool, S_IRUGO); 179 180 bool __read_mostly enable_vmware_backdoor = false; 181 module_param(enable_vmware_backdoor, bool, S_IRUGO); 182 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 183 184 static bool __read_mostly force_emulation_prefix = false; 185 module_param(force_emulation_prefix, bool, S_IRUGO); 186 187 int __read_mostly pi_inject_timer = -1; 188 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); 189 190 /* 191 * Restoring the host value for MSRs that are only consumed when running in 192 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU 193 * returns to userspace, i.e. the kernel can run with the guest's value. 194 */ 195 #define KVM_MAX_NR_USER_RETURN_MSRS 16 196 197 struct kvm_user_return_msrs { 198 struct user_return_notifier urn; 199 bool registered; 200 struct kvm_user_return_msr_values { 201 u64 host; 202 u64 curr; 203 } values[KVM_MAX_NR_USER_RETURN_MSRS]; 204 }; 205 206 u32 __read_mostly kvm_nr_uret_msrs; 207 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); 208 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; 209 static struct kvm_user_return_msrs __percpu *user_return_msrs; 210 211 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 212 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 213 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 214 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE) 215 216 u64 __read_mostly host_efer; 217 EXPORT_SYMBOL_GPL(host_efer); 218 219 bool __read_mostly allow_smaller_maxphyaddr = 0; 220 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); 221 222 bool __read_mostly enable_apicv = true; 223 EXPORT_SYMBOL_GPL(enable_apicv); 224 225 u64 __read_mostly host_xss; 226 EXPORT_SYMBOL_GPL(host_xss); 227 u64 __read_mostly supported_xss; 228 EXPORT_SYMBOL_GPL(supported_xss); 229 230 const struct _kvm_stats_desc kvm_vm_stats_desc[] = { 231 KVM_GENERIC_VM_STATS(), 232 STATS_DESC_COUNTER(VM, mmu_shadow_zapped), 233 STATS_DESC_COUNTER(VM, mmu_pte_write), 234 STATS_DESC_COUNTER(VM, mmu_pde_zapped), 235 STATS_DESC_COUNTER(VM, mmu_flooded), 236 STATS_DESC_COUNTER(VM, mmu_recycled), 237 STATS_DESC_COUNTER(VM, mmu_cache_miss), 238 STATS_DESC_ICOUNTER(VM, mmu_unsync), 239 STATS_DESC_ICOUNTER(VM, pages_4k), 240 STATS_DESC_ICOUNTER(VM, pages_2m), 241 STATS_DESC_ICOUNTER(VM, pages_1g), 242 STATS_DESC_ICOUNTER(VM, nx_lpage_splits), 243 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size), 244 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions) 245 }; 246 247 const struct kvm_stats_header kvm_vm_stats_header = { 248 .name_size = KVM_STATS_NAME_SIZE, 249 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), 250 .id_offset = sizeof(struct kvm_stats_header), 251 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 252 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 253 sizeof(kvm_vm_stats_desc), 254 }; 255 256 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { 257 KVM_GENERIC_VCPU_STATS(), 258 STATS_DESC_COUNTER(VCPU, pf_fixed), 259 STATS_DESC_COUNTER(VCPU, pf_guest), 260 STATS_DESC_COUNTER(VCPU, tlb_flush), 261 STATS_DESC_COUNTER(VCPU, invlpg), 262 STATS_DESC_COUNTER(VCPU, exits), 263 STATS_DESC_COUNTER(VCPU, io_exits), 264 STATS_DESC_COUNTER(VCPU, mmio_exits), 265 STATS_DESC_COUNTER(VCPU, signal_exits), 266 STATS_DESC_COUNTER(VCPU, irq_window_exits), 267 STATS_DESC_COUNTER(VCPU, nmi_window_exits), 268 STATS_DESC_COUNTER(VCPU, l1d_flush), 269 STATS_DESC_COUNTER(VCPU, halt_exits), 270 STATS_DESC_COUNTER(VCPU, request_irq_exits), 271 STATS_DESC_COUNTER(VCPU, irq_exits), 272 STATS_DESC_COUNTER(VCPU, host_state_reload), 273 STATS_DESC_COUNTER(VCPU, fpu_reload), 274 STATS_DESC_COUNTER(VCPU, insn_emulation), 275 STATS_DESC_COUNTER(VCPU, insn_emulation_fail), 276 STATS_DESC_COUNTER(VCPU, hypercalls), 277 STATS_DESC_COUNTER(VCPU, irq_injections), 278 STATS_DESC_COUNTER(VCPU, nmi_injections), 279 STATS_DESC_COUNTER(VCPU, req_event), 280 STATS_DESC_COUNTER(VCPU, nested_run), 281 STATS_DESC_COUNTER(VCPU, directed_yield_attempted), 282 STATS_DESC_COUNTER(VCPU, directed_yield_successful), 283 STATS_DESC_ICOUNTER(VCPU, guest_mode) 284 }; 285 286 const struct kvm_stats_header kvm_vcpu_stats_header = { 287 .name_size = KVM_STATS_NAME_SIZE, 288 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), 289 .id_offset = sizeof(struct kvm_stats_header), 290 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 291 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 292 sizeof(kvm_vcpu_stats_desc), 293 }; 294 295 u64 __read_mostly host_xcr0; 296 u64 __read_mostly supported_xcr0; 297 EXPORT_SYMBOL_GPL(supported_xcr0); 298 299 static struct kmem_cache *x86_emulator_cache; 300 301 /* 302 * When called, it means the previous get/set msr reached an invalid msr. 303 * Return true if we want to ignore/silent this failed msr access. 304 */ 305 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) 306 { 307 const char *op = write ? "wrmsr" : "rdmsr"; 308 309 if (ignore_msrs) { 310 if (report_ignored_msrs) 311 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", 312 op, msr, data); 313 /* Mask the error */ 314 return true; 315 } else { 316 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", 317 op, msr, data); 318 return false; 319 } 320 } 321 322 static struct kmem_cache *kvm_alloc_emulator_cache(void) 323 { 324 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); 325 unsigned int size = sizeof(struct x86_emulate_ctxt); 326 327 return kmem_cache_create_usercopy("x86_emulator", size, 328 __alignof__(struct x86_emulate_ctxt), 329 SLAB_ACCOUNT, useroffset, 330 size - useroffset, NULL); 331 } 332 333 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 334 335 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 336 { 337 int i; 338 for (i = 0; i < ASYNC_PF_PER_VCPU; i++) 339 vcpu->arch.apf.gfns[i] = ~0; 340 } 341 342 static void kvm_on_user_return(struct user_return_notifier *urn) 343 { 344 unsigned slot; 345 struct kvm_user_return_msrs *msrs 346 = container_of(urn, struct kvm_user_return_msrs, urn); 347 struct kvm_user_return_msr_values *values; 348 unsigned long flags; 349 350 /* 351 * Disabling irqs at this point since the following code could be 352 * interrupted and executed through kvm_arch_hardware_disable() 353 */ 354 local_irq_save(flags); 355 if (msrs->registered) { 356 msrs->registered = false; 357 user_return_notifier_unregister(urn); 358 } 359 local_irq_restore(flags); 360 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { 361 values = &msrs->values[slot]; 362 if (values->host != values->curr) { 363 wrmsrl(kvm_uret_msrs_list[slot], values->host); 364 values->curr = values->host; 365 } 366 } 367 } 368 369 static int kvm_probe_user_return_msr(u32 msr) 370 { 371 u64 val; 372 int ret; 373 374 preempt_disable(); 375 ret = rdmsrl_safe(msr, &val); 376 if (ret) 377 goto out; 378 ret = wrmsrl_safe(msr, val); 379 out: 380 preempt_enable(); 381 return ret; 382 } 383 384 int kvm_add_user_return_msr(u32 msr) 385 { 386 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); 387 388 if (kvm_probe_user_return_msr(msr)) 389 return -1; 390 391 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; 392 return kvm_nr_uret_msrs++; 393 } 394 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); 395 396 int kvm_find_user_return_msr(u32 msr) 397 { 398 int i; 399 400 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 401 if (kvm_uret_msrs_list[i] == msr) 402 return i; 403 } 404 return -1; 405 } 406 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); 407 408 static void kvm_user_return_msr_cpu_online(void) 409 { 410 unsigned int cpu = smp_processor_id(); 411 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 412 u64 value; 413 int i; 414 415 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 416 rdmsrl_safe(kvm_uret_msrs_list[i], &value); 417 msrs->values[i].host = value; 418 msrs->values[i].curr = value; 419 } 420 } 421 422 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) 423 { 424 unsigned int cpu = smp_processor_id(); 425 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 426 int err; 427 428 value = (value & mask) | (msrs->values[slot].host & ~mask); 429 if (value == msrs->values[slot].curr) 430 return 0; 431 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); 432 if (err) 433 return 1; 434 435 msrs->values[slot].curr = value; 436 if (!msrs->registered) { 437 msrs->urn.on_user_return = kvm_on_user_return; 438 user_return_notifier_register(&msrs->urn); 439 msrs->registered = true; 440 } 441 return 0; 442 } 443 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); 444 445 static void drop_user_return_notifiers(void) 446 { 447 unsigned int cpu = smp_processor_id(); 448 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 449 450 if (msrs->registered) 451 kvm_on_user_return(&msrs->urn); 452 } 453 454 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 455 { 456 return vcpu->arch.apic_base; 457 } 458 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 459 460 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 461 { 462 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 463 } 464 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 465 466 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 467 { 468 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 469 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 470 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | 471 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 472 473 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 474 return 1; 475 if (!msr_info->host_initiated) { 476 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 477 return 1; 478 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 479 return 1; 480 } 481 482 kvm_lapic_set_base(vcpu, msr_info->data); 483 kvm_recalculate_apic_map(vcpu->kvm); 484 return 0; 485 } 486 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 487 488 /* 489 * Handle a fault on a hardware virtualization (VMX or SVM) instruction. 490 * 491 * Hardware virtualization extension instructions may fault if a reboot turns 492 * off virtualization while processes are running. Usually after catching the 493 * fault we just panic; during reboot instead the instruction is ignored. 494 */ 495 noinstr void kvm_spurious_fault(void) 496 { 497 /* Fault while not rebooting. We want the trace. */ 498 BUG_ON(!kvm_rebooting); 499 } 500 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 501 502 #define EXCPT_BENIGN 0 503 #define EXCPT_CONTRIBUTORY 1 504 #define EXCPT_PF 2 505 506 static int exception_class(int vector) 507 { 508 switch (vector) { 509 case PF_VECTOR: 510 return EXCPT_PF; 511 case DE_VECTOR: 512 case TS_VECTOR: 513 case NP_VECTOR: 514 case SS_VECTOR: 515 case GP_VECTOR: 516 return EXCPT_CONTRIBUTORY; 517 default: 518 break; 519 } 520 return EXCPT_BENIGN; 521 } 522 523 #define EXCPT_FAULT 0 524 #define EXCPT_TRAP 1 525 #define EXCPT_ABORT 2 526 #define EXCPT_INTERRUPT 3 527 528 static int exception_type(int vector) 529 { 530 unsigned int mask; 531 532 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 533 return EXCPT_INTERRUPT; 534 535 mask = 1 << vector; 536 537 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 538 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 539 return EXCPT_TRAP; 540 541 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 542 return EXCPT_ABORT; 543 544 /* Reserved exceptions will result in fault */ 545 return EXCPT_FAULT; 546 } 547 548 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 549 { 550 unsigned nr = vcpu->arch.exception.nr; 551 bool has_payload = vcpu->arch.exception.has_payload; 552 unsigned long payload = vcpu->arch.exception.payload; 553 554 if (!has_payload) 555 return; 556 557 switch (nr) { 558 case DB_VECTOR: 559 /* 560 * "Certain debug exceptions may clear bit 0-3. The 561 * remaining contents of the DR6 register are never 562 * cleared by the processor". 563 */ 564 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 565 /* 566 * In order to reflect the #DB exception payload in guest 567 * dr6, three components need to be considered: active low 568 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, 569 * DR6_BS and DR6_BT) 570 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. 571 * In the target guest dr6: 572 * FIXED_1 bits should always be set. 573 * Active low bits should be cleared if 1-setting in payload. 574 * Active high bits should be set if 1-setting in payload. 575 * 576 * Note, the payload is compatible with the pending debug 577 * exceptions/exit qualification under VMX, that active_low bits 578 * are active high in payload. 579 * So they need to be flipped for DR6. 580 */ 581 vcpu->arch.dr6 |= DR6_ACTIVE_LOW; 582 vcpu->arch.dr6 |= payload; 583 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; 584 585 /* 586 * The #DB payload is defined as compatible with the 'pending 587 * debug exceptions' field under VMX, not DR6. While bit 12 is 588 * defined in the 'pending debug exceptions' field (enabled 589 * breakpoint), it is reserved and must be zero in DR6. 590 */ 591 vcpu->arch.dr6 &= ~BIT(12); 592 break; 593 case PF_VECTOR: 594 vcpu->arch.cr2 = payload; 595 break; 596 } 597 598 vcpu->arch.exception.has_payload = false; 599 vcpu->arch.exception.payload = 0; 600 } 601 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 602 603 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 604 unsigned nr, bool has_error, u32 error_code, 605 bool has_payload, unsigned long payload, bool reinject) 606 { 607 u32 prev_nr; 608 int class1, class2; 609 610 kvm_make_request(KVM_REQ_EVENT, vcpu); 611 612 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 613 queue: 614 if (reinject) { 615 /* 616 * On vmentry, vcpu->arch.exception.pending is only 617 * true if an event injection was blocked by 618 * nested_run_pending. In that case, however, 619 * vcpu_enter_guest requests an immediate exit, 620 * and the guest shouldn't proceed far enough to 621 * need reinjection. 622 */ 623 WARN_ON_ONCE(vcpu->arch.exception.pending); 624 vcpu->arch.exception.injected = true; 625 if (WARN_ON_ONCE(has_payload)) { 626 /* 627 * A reinjected event has already 628 * delivered its payload. 629 */ 630 has_payload = false; 631 payload = 0; 632 } 633 } else { 634 vcpu->arch.exception.pending = true; 635 vcpu->arch.exception.injected = false; 636 } 637 vcpu->arch.exception.has_error_code = has_error; 638 vcpu->arch.exception.nr = nr; 639 vcpu->arch.exception.error_code = error_code; 640 vcpu->arch.exception.has_payload = has_payload; 641 vcpu->arch.exception.payload = payload; 642 if (!is_guest_mode(vcpu)) 643 kvm_deliver_exception_payload(vcpu); 644 return; 645 } 646 647 /* to check exception */ 648 prev_nr = vcpu->arch.exception.nr; 649 if (prev_nr == DF_VECTOR) { 650 /* triple fault -> shutdown */ 651 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 652 return; 653 } 654 class1 = exception_class(prev_nr); 655 class2 = exception_class(nr); 656 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 657 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 658 /* 659 * Generate double fault per SDM Table 5-5. Set 660 * exception.pending = true so that the double fault 661 * can trigger a nested vmexit. 662 */ 663 vcpu->arch.exception.pending = true; 664 vcpu->arch.exception.injected = false; 665 vcpu->arch.exception.has_error_code = true; 666 vcpu->arch.exception.nr = DF_VECTOR; 667 vcpu->arch.exception.error_code = 0; 668 vcpu->arch.exception.has_payload = false; 669 vcpu->arch.exception.payload = 0; 670 } else 671 /* replace previous exception with a new one in a hope 672 that instruction re-execution will regenerate lost 673 exception */ 674 goto queue; 675 } 676 677 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 678 { 679 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 680 } 681 EXPORT_SYMBOL_GPL(kvm_queue_exception); 682 683 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 684 { 685 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 686 } 687 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 688 689 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 690 unsigned long payload) 691 { 692 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 693 } 694 EXPORT_SYMBOL_GPL(kvm_queue_exception_p); 695 696 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 697 u32 error_code, unsigned long payload) 698 { 699 kvm_multiple_exception(vcpu, nr, true, error_code, 700 true, payload, false); 701 } 702 703 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 704 { 705 if (err) 706 kvm_inject_gp(vcpu, 0); 707 else 708 return kvm_skip_emulated_instruction(vcpu); 709 710 return 1; 711 } 712 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 713 714 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err) 715 { 716 if (err) { 717 kvm_inject_gp(vcpu, 0); 718 return 1; 719 } 720 721 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP | 722 EMULTYPE_COMPLETE_USER_EXIT); 723 } 724 725 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 726 { 727 ++vcpu->stat.pf_guest; 728 vcpu->arch.exception.nested_apf = 729 is_guest_mode(vcpu) && fault->async_page_fault; 730 if (vcpu->arch.exception.nested_apf) { 731 vcpu->arch.apf.nested_apf_token = fault->address; 732 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 733 } else { 734 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 735 fault->address); 736 } 737 } 738 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 739 740 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 741 struct x86_exception *fault) 742 { 743 struct kvm_mmu *fault_mmu; 744 WARN_ON_ONCE(fault->vector != PF_VECTOR); 745 746 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : 747 vcpu->arch.walk_mmu; 748 749 /* 750 * Invalidate the TLB entry for the faulting address, if it exists, 751 * else the access will fault indefinitely (and to emulate hardware). 752 */ 753 if ((fault->error_code & PFERR_PRESENT_MASK) && 754 !(fault->error_code & PFERR_RSVD_MASK)) 755 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, 756 fault_mmu->root_hpa); 757 758 fault_mmu->inject_page_fault(vcpu, fault); 759 return fault->nested_page_fault; 760 } 761 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); 762 763 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 764 { 765 atomic_inc(&vcpu->arch.nmi_queued); 766 kvm_make_request(KVM_REQ_NMI, vcpu); 767 } 768 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 769 770 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 771 { 772 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 773 } 774 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 775 776 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 777 { 778 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 779 } 780 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 781 782 /* 783 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 784 * a #GP and return false. 785 */ 786 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 787 { 788 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) 789 return true; 790 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 791 return false; 792 } 793 EXPORT_SYMBOL_GPL(kvm_require_cpl); 794 795 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 796 { 797 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 798 return true; 799 800 kvm_queue_exception(vcpu, UD_VECTOR); 801 return false; 802 } 803 EXPORT_SYMBOL_GPL(kvm_require_dr); 804 805 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) 806 { 807 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); 808 } 809 810 /* 811 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. 812 */ 813 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3) 814 { 815 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 816 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 817 gpa_t real_gpa; 818 int i; 819 int ret; 820 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 821 822 /* 823 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated 824 * to an L1 GPA. 825 */ 826 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn), 827 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL); 828 if (real_gpa == UNMAPPED_GVA) 829 return 0; 830 831 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */ 832 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte, 833 cr3 & GENMASK(11, 5), sizeof(pdpte)); 834 if (ret < 0) 835 return 0; 836 837 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 838 if ((pdpte[i] & PT_PRESENT_MASK) && 839 (pdpte[i] & pdptr_rsvd_bits(vcpu))) { 840 return 0; 841 } 842 } 843 844 /* 845 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled. 846 * Shadow page roots need to be reconstructed instead. 847 */ 848 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs))) 849 kvm_mmu_free_roots(vcpu, mmu, KVM_MMU_ROOT_CURRENT); 850 851 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 852 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 853 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); 854 vcpu->arch.pdptrs_from_userspace = false; 855 856 return 1; 857 } 858 EXPORT_SYMBOL_GPL(load_pdptrs); 859 860 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) 861 { 862 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 863 kvm_clear_async_pf_completion_queue(vcpu); 864 kvm_async_pf_hash_reset(vcpu); 865 } 866 867 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS) 868 kvm_mmu_reset_context(vcpu); 869 870 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 871 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 872 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 873 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 874 } 875 EXPORT_SYMBOL_GPL(kvm_post_set_cr0); 876 877 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 878 { 879 unsigned long old_cr0 = kvm_read_cr0(vcpu); 880 881 cr0 |= X86_CR0_ET; 882 883 #ifdef CONFIG_X86_64 884 if (cr0 & 0xffffffff00000000UL) 885 return 1; 886 #endif 887 888 cr0 &= ~CR0_RESERVED_BITS; 889 890 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 891 return 1; 892 893 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 894 return 1; 895 896 #ifdef CONFIG_X86_64 897 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && 898 (cr0 & X86_CR0_PG)) { 899 int cs_db, cs_l; 900 901 if (!is_pae(vcpu)) 902 return 1; 903 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 904 if (cs_l) 905 return 1; 906 } 907 #endif 908 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && 909 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) && 910 !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) 911 return 1; 912 913 if (!(cr0 & X86_CR0_PG) && 914 (is_64_bit_mode(vcpu) || kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))) 915 return 1; 916 917 static_call(kvm_x86_set_cr0)(vcpu, cr0); 918 919 kvm_post_set_cr0(vcpu, old_cr0, cr0); 920 921 return 0; 922 } 923 EXPORT_SYMBOL_GPL(kvm_set_cr0); 924 925 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 926 { 927 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 928 } 929 EXPORT_SYMBOL_GPL(kvm_lmsw); 930 931 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) 932 { 933 if (vcpu->arch.guest_state_protected) 934 return; 935 936 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 937 938 if (vcpu->arch.xcr0 != host_xcr0) 939 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 940 941 if (vcpu->arch.xsaves_enabled && 942 vcpu->arch.ia32_xss != host_xss) 943 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 944 } 945 946 if (static_cpu_has(X86_FEATURE_PKU) && 947 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 948 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && 949 vcpu->arch.pkru != vcpu->arch.host_pkru) 950 write_pkru(vcpu->arch.pkru); 951 } 952 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); 953 954 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) 955 { 956 if (vcpu->arch.guest_state_protected) 957 return; 958 959 if (static_cpu_has(X86_FEATURE_PKU) && 960 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 961 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { 962 vcpu->arch.pkru = rdpkru(); 963 if (vcpu->arch.pkru != vcpu->arch.host_pkru) 964 write_pkru(vcpu->arch.host_pkru); 965 } 966 967 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 968 969 if (vcpu->arch.xcr0 != host_xcr0) 970 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 971 972 if (vcpu->arch.xsaves_enabled && 973 vcpu->arch.ia32_xss != host_xss) 974 wrmsrl(MSR_IA32_XSS, host_xss); 975 } 976 977 } 978 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); 979 980 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 981 { 982 u64 xcr0 = xcr; 983 u64 old_xcr0 = vcpu->arch.xcr0; 984 u64 valid_bits; 985 986 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 987 if (index != XCR_XFEATURE_ENABLED_MASK) 988 return 1; 989 if (!(xcr0 & XFEATURE_MASK_FP)) 990 return 1; 991 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 992 return 1; 993 994 /* 995 * Do not allow the guest to set bits that we do not support 996 * saving. However, xcr0 bit 0 is always set, even if the 997 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()). 998 */ 999 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 1000 if (xcr0 & ~valid_bits) 1001 return 1; 1002 1003 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 1004 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 1005 return 1; 1006 1007 if (xcr0 & XFEATURE_MASK_AVX512) { 1008 if (!(xcr0 & XFEATURE_MASK_YMM)) 1009 return 1; 1010 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 1011 return 1; 1012 } 1013 1014 if ((xcr0 & XFEATURE_MASK_XTILE) && 1015 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE)) 1016 return 1; 1017 1018 vcpu->arch.xcr0 = xcr0; 1019 1020 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 1021 kvm_update_cpuid_runtime(vcpu); 1022 return 0; 1023 } 1024 1025 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) 1026 { 1027 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || 1028 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { 1029 kvm_inject_gp(vcpu, 0); 1030 return 1; 1031 } 1032 1033 return kvm_skip_emulated_instruction(vcpu); 1034 } 1035 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); 1036 1037 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1038 { 1039 if (cr4 & cr4_reserved_bits) 1040 return false; 1041 1042 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) 1043 return false; 1044 1045 return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); 1046 } 1047 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); 1048 1049 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) 1050 { 1051 /* 1052 * If any role bit is changed, the MMU needs to be reset. 1053 * 1054 * If CR4.PCIDE is changed 1 -> 0, the guest TLB must be flushed. 1055 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB 1056 * according to the SDM; however, stale prev_roots could be reused 1057 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we 1058 * free them all. KVM_REQ_MMU_RELOAD is fit for the both cases; it 1059 * is slow, but changing CR4.PCIDE is a rare case. 1060 * 1061 * If CR4.PGE is changed, the guest TLB must be flushed. 1062 * 1063 * Note: resetting MMU is a superset of KVM_REQ_MMU_RELOAD and 1064 * KVM_REQ_MMU_RELOAD is a superset of KVM_REQ_TLB_FLUSH_GUEST, hence 1065 * the usage of "else if". 1066 */ 1067 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) 1068 kvm_mmu_reset_context(vcpu); 1069 else if ((cr4 ^ old_cr4) & X86_CR4_PCIDE) 1070 kvm_make_request(KVM_REQ_MMU_RELOAD, vcpu); 1071 else if ((cr4 ^ old_cr4) & X86_CR4_PGE) 1072 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1073 } 1074 EXPORT_SYMBOL_GPL(kvm_post_set_cr4); 1075 1076 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1077 { 1078 unsigned long old_cr4 = kvm_read_cr4(vcpu); 1079 1080 if (!kvm_is_valid_cr4(vcpu, cr4)) 1081 return 1; 1082 1083 if (is_long_mode(vcpu)) { 1084 if (!(cr4 & X86_CR4_PAE)) 1085 return 1; 1086 if ((cr4 ^ old_cr4) & X86_CR4_LA57) 1087 return 1; 1088 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 1089 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS) 1090 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) 1091 return 1; 1092 1093 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 1094 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 1095 return 1; 1096 1097 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 1098 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 1099 return 1; 1100 } 1101 1102 static_call(kvm_x86_set_cr4)(vcpu, cr4); 1103 1104 kvm_post_set_cr4(vcpu, old_cr4, cr4); 1105 1106 return 0; 1107 } 1108 EXPORT_SYMBOL_GPL(kvm_set_cr4); 1109 1110 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) 1111 { 1112 struct kvm_mmu *mmu = vcpu->arch.mmu; 1113 unsigned long roots_to_free = 0; 1114 int i; 1115 1116 /* 1117 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but 1118 * this is reachable when running EPT=1 and unrestricted_guest=0, and 1119 * also via the emulator. KVM's TDP page tables are not in the scope of 1120 * the invalidation, but the guest's TLB entries need to be flushed as 1121 * the CPU may have cached entries in its TLB for the target PCID. 1122 */ 1123 if (unlikely(tdp_enabled)) { 1124 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1125 return; 1126 } 1127 1128 /* 1129 * If neither the current CR3 nor any of the prev_roots use the given 1130 * PCID, then nothing needs to be done here because a resync will 1131 * happen anyway before switching to any other CR3. 1132 */ 1133 if (kvm_get_active_pcid(vcpu) == pcid) { 1134 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); 1135 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1136 } 1137 1138 /* 1139 * If PCID is disabled, there is no need to free prev_roots even if the 1140 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB 1141 * with PCIDE=0. 1142 */ 1143 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 1144 return; 1145 1146 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 1147 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid) 1148 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 1149 1150 kvm_mmu_free_roots(vcpu, mmu, roots_to_free); 1151 } 1152 1153 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 1154 { 1155 bool skip_tlb_flush = false; 1156 unsigned long pcid = 0; 1157 #ifdef CONFIG_X86_64 1158 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 1159 1160 if (pcid_enabled) { 1161 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 1162 cr3 &= ~X86_CR3_PCID_NOFLUSH; 1163 pcid = cr3 & X86_CR3_PCID_MASK; 1164 } 1165 #endif 1166 1167 /* PDPTRs are always reloaded for PAE paging. */ 1168 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) 1169 goto handle_tlb_flush; 1170 1171 /* 1172 * Do not condition the GPA check on long mode, this helper is used to 1173 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that 1174 * the current vCPU mode is accurate. 1175 */ 1176 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) 1177 return 1; 1178 1179 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3)) 1180 return 1; 1181 1182 if (cr3 != kvm_read_cr3(vcpu)) 1183 kvm_mmu_new_pgd(vcpu, cr3); 1184 1185 vcpu->arch.cr3 = cr3; 1186 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 1187 /* Do not call post_set_cr3, we do not get here for confidential guests. */ 1188 1189 handle_tlb_flush: 1190 /* 1191 * A load of CR3 that flushes the TLB flushes only the current PCID, 1192 * even if PCID is disabled, in which case PCID=0 is flushed. It's a 1193 * moot point in the end because _disabling_ PCID will flush all PCIDs, 1194 * and it's impossible to use a non-zero PCID when PCID is disabled, 1195 * i.e. only PCID=0 can be relevant. 1196 */ 1197 if (!skip_tlb_flush) 1198 kvm_invalidate_pcid(vcpu, pcid); 1199 1200 return 0; 1201 } 1202 EXPORT_SYMBOL_GPL(kvm_set_cr3); 1203 1204 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 1205 { 1206 if (cr8 & CR8_RESERVED_BITS) 1207 return 1; 1208 if (lapic_in_kernel(vcpu)) 1209 kvm_lapic_set_tpr(vcpu, cr8); 1210 else 1211 vcpu->arch.cr8 = cr8; 1212 return 0; 1213 } 1214 EXPORT_SYMBOL_GPL(kvm_set_cr8); 1215 1216 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 1217 { 1218 if (lapic_in_kernel(vcpu)) 1219 return kvm_lapic_get_cr8(vcpu); 1220 else 1221 return vcpu->arch.cr8; 1222 } 1223 EXPORT_SYMBOL_GPL(kvm_get_cr8); 1224 1225 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 1226 { 1227 int i; 1228 1229 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1230 for (i = 0; i < KVM_NR_DB_REGS; i++) 1231 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1232 } 1233 } 1234 1235 void kvm_update_dr7(struct kvm_vcpu *vcpu) 1236 { 1237 unsigned long dr7; 1238 1239 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1240 dr7 = vcpu->arch.guest_debug_dr7; 1241 else 1242 dr7 = vcpu->arch.dr7; 1243 static_call(kvm_x86_set_dr7)(vcpu, dr7); 1244 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1245 if (dr7 & DR7_BP_EN_MASK) 1246 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1247 } 1248 EXPORT_SYMBOL_GPL(kvm_update_dr7); 1249 1250 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1251 { 1252 u64 fixed = DR6_FIXED_1; 1253 1254 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1255 fixed |= DR6_RTM; 1256 1257 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) 1258 fixed |= DR6_BUS_LOCK; 1259 return fixed; 1260 } 1261 1262 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1263 { 1264 size_t size = ARRAY_SIZE(vcpu->arch.db); 1265 1266 switch (dr) { 1267 case 0 ... 3: 1268 vcpu->arch.db[array_index_nospec(dr, size)] = val; 1269 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1270 vcpu->arch.eff_db[dr] = val; 1271 break; 1272 case 4: 1273 case 6: 1274 if (!kvm_dr6_valid(val)) 1275 return 1; /* #GP */ 1276 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1277 break; 1278 case 5: 1279 default: /* 7 */ 1280 if (!kvm_dr7_valid(val)) 1281 return 1; /* #GP */ 1282 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1283 kvm_update_dr7(vcpu); 1284 break; 1285 } 1286 1287 return 0; 1288 } 1289 EXPORT_SYMBOL_GPL(kvm_set_dr); 1290 1291 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1292 { 1293 size_t size = ARRAY_SIZE(vcpu->arch.db); 1294 1295 switch (dr) { 1296 case 0 ... 3: 1297 *val = vcpu->arch.db[array_index_nospec(dr, size)]; 1298 break; 1299 case 4: 1300 case 6: 1301 *val = vcpu->arch.dr6; 1302 break; 1303 case 5: 1304 default: /* 7 */ 1305 *val = vcpu->arch.dr7; 1306 break; 1307 } 1308 } 1309 EXPORT_SYMBOL_GPL(kvm_get_dr); 1310 1311 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) 1312 { 1313 u32 ecx = kvm_rcx_read(vcpu); 1314 u64 data; 1315 1316 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { 1317 kvm_inject_gp(vcpu, 0); 1318 return 1; 1319 } 1320 1321 kvm_rax_write(vcpu, (u32)data); 1322 kvm_rdx_write(vcpu, data >> 32); 1323 return kvm_skip_emulated_instruction(vcpu); 1324 } 1325 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); 1326 1327 /* 1328 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1329 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1330 * 1331 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) 1332 * extract the supported MSRs from the related const lists. 1333 * msrs_to_save is selected from the msrs_to_save_all to reflect the 1334 * capabilities of the host cpu. This capabilities test skips MSRs that are 1335 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs 1336 * may depend on host virtualization features rather than host cpu features. 1337 */ 1338 1339 static const u32 msrs_to_save_all[] = { 1340 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1341 MSR_STAR, 1342 #ifdef CONFIG_X86_64 1343 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1344 #endif 1345 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1346 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1347 MSR_IA32_SPEC_CTRL, 1348 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1349 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1350 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1351 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1352 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1353 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1354 MSR_IA32_UMWAIT_CONTROL, 1355 1356 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, 1357 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, 1358 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, 1359 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 1360 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, 1361 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, 1362 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, 1363 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, 1364 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, 1365 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, 1366 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, 1367 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, 1368 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, 1369 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, 1370 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, 1371 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, 1372 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, 1373 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, 1374 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, 1375 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, 1376 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, 1377 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, 1378 1379 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3, 1380 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3, 1381 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2, 1382 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, 1383 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, 1384 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, 1385 MSR_IA32_XFD, MSR_IA32_XFD_ERR, 1386 }; 1387 1388 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; 1389 static unsigned num_msrs_to_save; 1390 1391 static const u32 emulated_msrs_all[] = { 1392 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1393 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1394 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1395 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1396 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1397 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1398 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1399 HV_X64_MSR_RESET, 1400 HV_X64_MSR_VP_INDEX, 1401 HV_X64_MSR_VP_RUNTIME, 1402 HV_X64_MSR_SCONTROL, 1403 HV_X64_MSR_STIMER0_CONFIG, 1404 HV_X64_MSR_VP_ASSIST_PAGE, 1405 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1406 HV_X64_MSR_TSC_EMULATION_STATUS, 1407 HV_X64_MSR_SYNDBG_OPTIONS, 1408 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, 1409 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, 1410 HV_X64_MSR_SYNDBG_PENDING_BUFFER, 1411 1412 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1413 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, 1414 1415 MSR_IA32_TSC_ADJUST, 1416 MSR_IA32_TSC_DEADLINE, 1417 MSR_IA32_ARCH_CAPABILITIES, 1418 MSR_IA32_PERF_CAPABILITIES, 1419 MSR_IA32_MISC_ENABLE, 1420 MSR_IA32_MCG_STATUS, 1421 MSR_IA32_MCG_CTL, 1422 MSR_IA32_MCG_EXT_CTL, 1423 MSR_IA32_SMBASE, 1424 MSR_SMI_COUNT, 1425 MSR_PLATFORM_INFO, 1426 MSR_MISC_FEATURES_ENABLES, 1427 MSR_AMD64_VIRT_SPEC_CTRL, 1428 MSR_AMD64_TSC_RATIO, 1429 MSR_IA32_POWER_CTL, 1430 MSR_IA32_UCODE_REV, 1431 1432 /* 1433 * The following list leaves out MSRs whose values are determined 1434 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. 1435 * We always support the "true" VMX control MSRs, even if the host 1436 * processor does not, so I am putting these registers here rather 1437 * than in msrs_to_save_all. 1438 */ 1439 MSR_IA32_VMX_BASIC, 1440 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1441 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1442 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1443 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1444 MSR_IA32_VMX_MISC, 1445 MSR_IA32_VMX_CR0_FIXED0, 1446 MSR_IA32_VMX_CR4_FIXED0, 1447 MSR_IA32_VMX_VMCS_ENUM, 1448 MSR_IA32_VMX_PROCBASED_CTLS2, 1449 MSR_IA32_VMX_EPT_VPID_CAP, 1450 MSR_IA32_VMX_VMFUNC, 1451 1452 MSR_K7_HWCR, 1453 MSR_KVM_POLL_CONTROL, 1454 }; 1455 1456 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; 1457 static unsigned num_emulated_msrs; 1458 1459 /* 1460 * List of msr numbers which are used to expose MSR-based features that 1461 * can be used by a hypervisor to validate requested CPU features. 1462 */ 1463 static const u32 msr_based_features_all[] = { 1464 MSR_IA32_VMX_BASIC, 1465 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1466 MSR_IA32_VMX_PINBASED_CTLS, 1467 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1468 MSR_IA32_VMX_PROCBASED_CTLS, 1469 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1470 MSR_IA32_VMX_EXIT_CTLS, 1471 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1472 MSR_IA32_VMX_ENTRY_CTLS, 1473 MSR_IA32_VMX_MISC, 1474 MSR_IA32_VMX_CR0_FIXED0, 1475 MSR_IA32_VMX_CR0_FIXED1, 1476 MSR_IA32_VMX_CR4_FIXED0, 1477 MSR_IA32_VMX_CR4_FIXED1, 1478 MSR_IA32_VMX_VMCS_ENUM, 1479 MSR_IA32_VMX_PROCBASED_CTLS2, 1480 MSR_IA32_VMX_EPT_VPID_CAP, 1481 MSR_IA32_VMX_VMFUNC, 1482 1483 MSR_F10H_DECFG, 1484 MSR_IA32_UCODE_REV, 1485 MSR_IA32_ARCH_CAPABILITIES, 1486 MSR_IA32_PERF_CAPABILITIES, 1487 }; 1488 1489 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; 1490 static unsigned int num_msr_based_features; 1491 1492 static u64 kvm_get_arch_capabilities(void) 1493 { 1494 u64 data = 0; 1495 1496 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1497 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); 1498 1499 /* 1500 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that 1501 * the nested hypervisor runs with NX huge pages. If it is not, 1502 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other 1503 * L1 guests, so it need not worry about its own (L2) guests. 1504 */ 1505 data |= ARCH_CAP_PSCHANGE_MC_NO; 1506 1507 /* 1508 * If we're doing cache flushes (either "always" or "cond") 1509 * we will do one whenever the guest does a vmlaunch/vmresume. 1510 * If an outer hypervisor is doing the cache flush for us 1511 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1512 * capability to the guest too, and if EPT is disabled we're not 1513 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1514 * require a nested hypervisor to do a flush of its own. 1515 */ 1516 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1517 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1518 1519 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) 1520 data |= ARCH_CAP_RDCL_NO; 1521 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1522 data |= ARCH_CAP_SSB_NO; 1523 if (!boot_cpu_has_bug(X86_BUG_MDS)) 1524 data |= ARCH_CAP_MDS_NO; 1525 1526 if (!boot_cpu_has(X86_FEATURE_RTM)) { 1527 /* 1528 * If RTM=0 because the kernel has disabled TSX, the host might 1529 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 1530 * and therefore knows that there cannot be TAA) but keep 1531 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, 1532 * and we want to allow migrating those guests to tsx=off hosts. 1533 */ 1534 data &= ~ARCH_CAP_TAA_NO; 1535 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { 1536 data |= ARCH_CAP_TAA_NO; 1537 } else { 1538 /* 1539 * Nothing to do here; we emulate TSX_CTRL if present on the 1540 * host so the guest can choose between disabling TSX or 1541 * using VERW to clear CPU buffers. 1542 */ 1543 } 1544 1545 return data; 1546 } 1547 1548 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1549 { 1550 switch (msr->index) { 1551 case MSR_IA32_ARCH_CAPABILITIES: 1552 msr->data = kvm_get_arch_capabilities(); 1553 break; 1554 case MSR_IA32_UCODE_REV: 1555 rdmsrl_safe(msr->index, &msr->data); 1556 break; 1557 default: 1558 return static_call(kvm_x86_get_msr_feature)(msr); 1559 } 1560 return 0; 1561 } 1562 1563 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1564 { 1565 struct kvm_msr_entry msr; 1566 int r; 1567 1568 msr.index = index; 1569 r = kvm_get_msr_feature(&msr); 1570 1571 if (r == KVM_MSR_RET_INVALID) { 1572 /* Unconditionally clear the output for simplicity */ 1573 *data = 0; 1574 if (kvm_msr_ignored_check(index, 0, false)) 1575 r = 0; 1576 } 1577 1578 if (r) 1579 return r; 1580 1581 *data = msr.data; 1582 1583 return 0; 1584 } 1585 1586 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1587 { 1588 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1589 return false; 1590 1591 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1592 return false; 1593 1594 if (efer & (EFER_LME | EFER_LMA) && 1595 !guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1596 return false; 1597 1598 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) 1599 return false; 1600 1601 return true; 1602 1603 } 1604 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1605 { 1606 if (efer & efer_reserved_bits) 1607 return false; 1608 1609 return __kvm_valid_efer(vcpu, efer); 1610 } 1611 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1612 1613 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1614 { 1615 u64 old_efer = vcpu->arch.efer; 1616 u64 efer = msr_info->data; 1617 int r; 1618 1619 if (efer & efer_reserved_bits) 1620 return 1; 1621 1622 if (!msr_info->host_initiated) { 1623 if (!__kvm_valid_efer(vcpu, efer)) 1624 return 1; 1625 1626 if (is_paging(vcpu) && 1627 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1628 return 1; 1629 } 1630 1631 efer &= ~EFER_LMA; 1632 efer |= vcpu->arch.efer & EFER_LMA; 1633 1634 r = static_call(kvm_x86_set_efer)(vcpu, efer); 1635 if (r) { 1636 WARN_ON(r > 0); 1637 return r; 1638 } 1639 1640 /* Update reserved bits */ 1641 if ((efer ^ old_efer) & EFER_NX) 1642 kvm_mmu_reset_context(vcpu); 1643 1644 return 0; 1645 } 1646 1647 void kvm_enable_efer_bits(u64 mask) 1648 { 1649 efer_reserved_bits &= ~mask; 1650 } 1651 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1652 1653 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) 1654 { 1655 struct kvm_x86_msr_filter *msr_filter; 1656 struct msr_bitmap_range *ranges; 1657 struct kvm *kvm = vcpu->kvm; 1658 bool allowed; 1659 int idx; 1660 u32 i; 1661 1662 /* x2APIC MSRs do not support filtering. */ 1663 if (index >= 0x800 && index <= 0x8ff) 1664 return true; 1665 1666 idx = srcu_read_lock(&kvm->srcu); 1667 1668 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); 1669 if (!msr_filter) { 1670 allowed = true; 1671 goto out; 1672 } 1673 1674 allowed = msr_filter->default_allow; 1675 ranges = msr_filter->ranges; 1676 1677 for (i = 0; i < msr_filter->count; i++) { 1678 u32 start = ranges[i].base; 1679 u32 end = start + ranges[i].nmsrs; 1680 u32 flags = ranges[i].flags; 1681 unsigned long *bitmap = ranges[i].bitmap; 1682 1683 if ((index >= start) && (index < end) && (flags & type)) { 1684 allowed = !!test_bit(index - start, bitmap); 1685 break; 1686 } 1687 } 1688 1689 out: 1690 srcu_read_unlock(&kvm->srcu, idx); 1691 1692 return allowed; 1693 } 1694 EXPORT_SYMBOL_GPL(kvm_msr_allowed); 1695 1696 /* 1697 * Write @data into the MSR specified by @index. Select MSR specific fault 1698 * checks are bypassed if @host_initiated is %true. 1699 * Returns 0 on success, non-0 otherwise. 1700 * Assumes vcpu_load() was already called. 1701 */ 1702 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, 1703 bool host_initiated) 1704 { 1705 struct msr_data msr; 1706 1707 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) 1708 return KVM_MSR_RET_FILTERED; 1709 1710 switch (index) { 1711 case MSR_FS_BASE: 1712 case MSR_GS_BASE: 1713 case MSR_KERNEL_GS_BASE: 1714 case MSR_CSTAR: 1715 case MSR_LSTAR: 1716 if (is_noncanonical_address(data, vcpu)) 1717 return 1; 1718 break; 1719 case MSR_IA32_SYSENTER_EIP: 1720 case MSR_IA32_SYSENTER_ESP: 1721 /* 1722 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1723 * non-canonical address is written on Intel but not on 1724 * AMD (which ignores the top 32-bits, because it does 1725 * not implement 64-bit SYSENTER). 1726 * 1727 * 64-bit code should hence be able to write a non-canonical 1728 * value on AMD. Making the address canonical ensures that 1729 * vmentry does not fail on Intel after writing a non-canonical 1730 * value, and that something deterministic happens if the guest 1731 * invokes 64-bit SYSENTER. 1732 */ 1733 data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); 1734 break; 1735 case MSR_TSC_AUX: 1736 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1737 return 1; 1738 1739 if (!host_initiated && 1740 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1741 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1742 return 1; 1743 1744 /* 1745 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has 1746 * incomplete and conflicting architectural behavior. Current 1747 * AMD CPUs completely ignore bits 63:32, i.e. they aren't 1748 * reserved and always read as zeros. Enforce Intel's reserved 1749 * bits check if and only if the guest CPU is Intel, and clear 1750 * the bits in all other cases. This ensures cross-vendor 1751 * migration will provide consistent behavior for the guest. 1752 */ 1753 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) 1754 return 1; 1755 1756 data = (u32)data; 1757 break; 1758 } 1759 1760 msr.data = data; 1761 msr.index = index; 1762 msr.host_initiated = host_initiated; 1763 1764 return static_call(kvm_x86_set_msr)(vcpu, &msr); 1765 } 1766 1767 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, 1768 u32 index, u64 data, bool host_initiated) 1769 { 1770 int ret = __kvm_set_msr(vcpu, index, data, host_initiated); 1771 1772 if (ret == KVM_MSR_RET_INVALID) 1773 if (kvm_msr_ignored_check(index, data, true)) 1774 ret = 0; 1775 1776 return ret; 1777 } 1778 1779 /* 1780 * Read the MSR specified by @index into @data. Select MSR specific fault 1781 * checks are bypassed if @host_initiated is %true. 1782 * Returns 0 on success, non-0 otherwise. 1783 * Assumes vcpu_load() was already called. 1784 */ 1785 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1786 bool host_initiated) 1787 { 1788 struct msr_data msr; 1789 int ret; 1790 1791 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) 1792 return KVM_MSR_RET_FILTERED; 1793 1794 switch (index) { 1795 case MSR_TSC_AUX: 1796 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1797 return 1; 1798 1799 if (!host_initiated && 1800 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1801 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1802 return 1; 1803 break; 1804 } 1805 1806 msr.index = index; 1807 msr.host_initiated = host_initiated; 1808 1809 ret = static_call(kvm_x86_get_msr)(vcpu, &msr); 1810 if (!ret) 1811 *data = msr.data; 1812 return ret; 1813 } 1814 1815 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, 1816 u32 index, u64 *data, bool host_initiated) 1817 { 1818 int ret = __kvm_get_msr(vcpu, index, data, host_initiated); 1819 1820 if (ret == KVM_MSR_RET_INVALID) { 1821 /* Unconditionally clear *data for simplicity */ 1822 *data = 0; 1823 if (kvm_msr_ignored_check(index, 0, false)) 1824 ret = 0; 1825 } 1826 1827 return ret; 1828 } 1829 1830 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1831 { 1832 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1833 } 1834 EXPORT_SYMBOL_GPL(kvm_get_msr); 1835 1836 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) 1837 { 1838 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1839 } 1840 EXPORT_SYMBOL_GPL(kvm_set_msr); 1841 1842 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu) 1843 { 1844 if (!vcpu->run->msr.error) { 1845 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); 1846 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); 1847 } 1848 } 1849 1850 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu) 1851 { 1852 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error); 1853 } 1854 1855 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) 1856 { 1857 complete_userspace_rdmsr(vcpu); 1858 return complete_emulated_msr_access(vcpu); 1859 } 1860 1861 static int complete_fast_msr_access(struct kvm_vcpu *vcpu) 1862 { 1863 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); 1864 } 1865 1866 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu) 1867 { 1868 complete_userspace_rdmsr(vcpu); 1869 return complete_fast_msr_access(vcpu); 1870 } 1871 1872 static u64 kvm_msr_reason(int r) 1873 { 1874 switch (r) { 1875 case KVM_MSR_RET_INVALID: 1876 return KVM_MSR_EXIT_REASON_UNKNOWN; 1877 case KVM_MSR_RET_FILTERED: 1878 return KVM_MSR_EXIT_REASON_FILTER; 1879 default: 1880 return KVM_MSR_EXIT_REASON_INVAL; 1881 } 1882 } 1883 1884 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, 1885 u32 exit_reason, u64 data, 1886 int (*completion)(struct kvm_vcpu *vcpu), 1887 int r) 1888 { 1889 u64 msr_reason = kvm_msr_reason(r); 1890 1891 /* Check if the user wanted to know about this MSR fault */ 1892 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) 1893 return 0; 1894 1895 vcpu->run->exit_reason = exit_reason; 1896 vcpu->run->msr.error = 0; 1897 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); 1898 vcpu->run->msr.reason = msr_reason; 1899 vcpu->run->msr.index = index; 1900 vcpu->run->msr.data = data; 1901 vcpu->arch.complete_userspace_io = completion; 1902 1903 return 1; 1904 } 1905 1906 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) 1907 { 1908 u32 ecx = kvm_rcx_read(vcpu); 1909 u64 data; 1910 int r; 1911 1912 r = kvm_get_msr(vcpu, ecx, &data); 1913 1914 if (!r) { 1915 trace_kvm_msr_read(ecx, data); 1916 1917 kvm_rax_write(vcpu, data & -1u); 1918 kvm_rdx_write(vcpu, (data >> 32) & -1u); 1919 } else { 1920 /* MSR read failed? See if we should ask user space */ 1921 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0, 1922 complete_fast_rdmsr, r)) 1923 return 0; 1924 trace_kvm_msr_read_ex(ecx); 1925 } 1926 1927 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1928 } 1929 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); 1930 1931 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) 1932 { 1933 u32 ecx = kvm_rcx_read(vcpu); 1934 u64 data = kvm_read_edx_eax(vcpu); 1935 int r; 1936 1937 r = kvm_set_msr(vcpu, ecx, data); 1938 1939 if (!r) { 1940 trace_kvm_msr_write(ecx, data); 1941 } else { 1942 /* MSR write failed? See if we should ask user space */ 1943 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data, 1944 complete_fast_msr_access, r)) 1945 return 0; 1946 /* Signal all other negative errors to userspace */ 1947 if (r < 0) 1948 return r; 1949 trace_kvm_msr_write_ex(ecx, data); 1950 } 1951 1952 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1953 } 1954 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); 1955 1956 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) 1957 { 1958 return kvm_skip_emulated_instruction(vcpu); 1959 } 1960 EXPORT_SYMBOL_GPL(kvm_emulate_as_nop); 1961 1962 int kvm_emulate_invd(struct kvm_vcpu *vcpu) 1963 { 1964 /* Treat an INVD instruction as a NOP and just skip it. */ 1965 return kvm_emulate_as_nop(vcpu); 1966 } 1967 EXPORT_SYMBOL_GPL(kvm_emulate_invd); 1968 1969 int kvm_emulate_mwait(struct kvm_vcpu *vcpu) 1970 { 1971 pr_warn_once("kvm: MWAIT instruction emulated as NOP!\n"); 1972 return kvm_emulate_as_nop(vcpu); 1973 } 1974 EXPORT_SYMBOL_GPL(kvm_emulate_mwait); 1975 1976 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) 1977 { 1978 kvm_queue_exception(vcpu, UD_VECTOR); 1979 return 1; 1980 } 1981 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); 1982 1983 int kvm_emulate_monitor(struct kvm_vcpu *vcpu) 1984 { 1985 pr_warn_once("kvm: MONITOR instruction emulated as NOP!\n"); 1986 return kvm_emulate_as_nop(vcpu); 1987 } 1988 EXPORT_SYMBOL_GPL(kvm_emulate_monitor); 1989 1990 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) 1991 { 1992 xfer_to_guest_mode_prepare(); 1993 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || 1994 xfer_to_guest_mode_work_pending(); 1995 } 1996 1997 /* 1998 * The fast path for frequent and performance sensitive wrmsr emulation, 1999 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces 2000 * the latency of virtual IPI by avoiding the expensive bits of transitioning 2001 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the 2002 * other cases which must be called after interrupts are enabled on the host. 2003 */ 2004 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) 2005 { 2006 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) 2007 return 1; 2008 2009 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && 2010 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && 2011 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && 2012 ((u32)(data >> 32) != X2APIC_BROADCAST)) { 2013 2014 data &= ~(1 << 12); 2015 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); 2016 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); 2017 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); 2018 trace_kvm_apic_write(APIC_ICR, (u32)data); 2019 return 0; 2020 } 2021 2022 return 1; 2023 } 2024 2025 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) 2026 { 2027 if (!kvm_can_use_hv_timer(vcpu)) 2028 return 1; 2029 2030 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2031 return 0; 2032 } 2033 2034 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) 2035 { 2036 u32 msr = kvm_rcx_read(vcpu); 2037 u64 data; 2038 fastpath_t ret = EXIT_FASTPATH_NONE; 2039 2040 switch (msr) { 2041 case APIC_BASE_MSR + (APIC_ICR >> 4): 2042 data = kvm_read_edx_eax(vcpu); 2043 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { 2044 kvm_skip_emulated_instruction(vcpu); 2045 ret = EXIT_FASTPATH_EXIT_HANDLED; 2046 } 2047 break; 2048 case MSR_IA32_TSC_DEADLINE: 2049 data = kvm_read_edx_eax(vcpu); 2050 if (!handle_fastpath_set_tscdeadline(vcpu, data)) { 2051 kvm_skip_emulated_instruction(vcpu); 2052 ret = EXIT_FASTPATH_REENTER_GUEST; 2053 } 2054 break; 2055 default: 2056 break; 2057 } 2058 2059 if (ret != EXIT_FASTPATH_NONE) 2060 trace_kvm_msr_write(msr, data); 2061 2062 return ret; 2063 } 2064 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); 2065 2066 /* 2067 * Adapt set_msr() to msr_io()'s calling convention 2068 */ 2069 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2070 { 2071 return kvm_get_msr_ignored_check(vcpu, index, data, true); 2072 } 2073 2074 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2075 { 2076 return kvm_set_msr_ignored_check(vcpu, index, *data, true); 2077 } 2078 2079 #ifdef CONFIG_X86_64 2080 struct pvclock_clock { 2081 int vclock_mode; 2082 u64 cycle_last; 2083 u64 mask; 2084 u32 mult; 2085 u32 shift; 2086 u64 base_cycles; 2087 u64 offset; 2088 }; 2089 2090 struct pvclock_gtod_data { 2091 seqcount_t seq; 2092 2093 struct pvclock_clock clock; /* extract of a clocksource struct */ 2094 struct pvclock_clock raw_clock; /* extract of a clocksource struct */ 2095 2096 ktime_t offs_boot; 2097 u64 wall_time_sec; 2098 }; 2099 2100 static struct pvclock_gtod_data pvclock_gtod_data; 2101 2102 static void update_pvclock_gtod(struct timekeeper *tk) 2103 { 2104 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 2105 2106 write_seqcount_begin(&vdata->seq); 2107 2108 /* copy pvclock gtod data */ 2109 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; 2110 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 2111 vdata->clock.mask = tk->tkr_mono.mask; 2112 vdata->clock.mult = tk->tkr_mono.mult; 2113 vdata->clock.shift = tk->tkr_mono.shift; 2114 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 2115 vdata->clock.offset = tk->tkr_mono.base; 2116 2117 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; 2118 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; 2119 vdata->raw_clock.mask = tk->tkr_raw.mask; 2120 vdata->raw_clock.mult = tk->tkr_raw.mult; 2121 vdata->raw_clock.shift = tk->tkr_raw.shift; 2122 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; 2123 vdata->raw_clock.offset = tk->tkr_raw.base; 2124 2125 vdata->wall_time_sec = tk->xtime_sec; 2126 2127 vdata->offs_boot = tk->offs_boot; 2128 2129 write_seqcount_end(&vdata->seq); 2130 } 2131 2132 static s64 get_kvmclock_base_ns(void) 2133 { 2134 /* Count up from boot time, but with the frequency of the raw clock. */ 2135 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); 2136 } 2137 #else 2138 static s64 get_kvmclock_base_ns(void) 2139 { 2140 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ 2141 return ktime_get_boottime_ns(); 2142 } 2143 #endif 2144 2145 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) 2146 { 2147 int version; 2148 int r; 2149 struct pvclock_wall_clock wc; 2150 u32 wc_sec_hi; 2151 u64 wall_nsec; 2152 2153 if (!wall_clock) 2154 return; 2155 2156 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 2157 if (r) 2158 return; 2159 2160 if (version & 1) 2161 ++version; /* first time write, random junk */ 2162 2163 ++version; 2164 2165 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 2166 return; 2167 2168 /* 2169 * The guest calculates current wall clock time by adding 2170 * system time (updated by kvm_guest_time_update below) to the 2171 * wall clock specified here. We do the reverse here. 2172 */ 2173 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); 2174 2175 wc.nsec = do_div(wall_nsec, 1000000000); 2176 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ 2177 wc.version = version; 2178 2179 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 2180 2181 if (sec_hi_ofs) { 2182 wc_sec_hi = wall_nsec >> 32; 2183 kvm_write_guest(kvm, wall_clock + sec_hi_ofs, 2184 &wc_sec_hi, sizeof(wc_sec_hi)); 2185 } 2186 2187 version++; 2188 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 2189 } 2190 2191 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, 2192 bool old_msr, bool host_initiated) 2193 { 2194 struct kvm_arch *ka = &vcpu->kvm->arch; 2195 2196 if (vcpu->vcpu_id == 0 && !host_initiated) { 2197 if (ka->boot_vcpu_runs_old_kvmclock != old_msr) 2198 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2199 2200 ka->boot_vcpu_runs_old_kvmclock = old_msr; 2201 } 2202 2203 vcpu->arch.time = system_time; 2204 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2205 2206 /* we verify if the enable bit is set... */ 2207 vcpu->arch.pv_time_enabled = false; 2208 if (!(system_time & 1)) 2209 return; 2210 2211 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, 2212 &vcpu->arch.pv_time, system_time & ~1ULL, 2213 sizeof(struct pvclock_vcpu_time_info))) 2214 vcpu->arch.pv_time_enabled = true; 2215 2216 return; 2217 } 2218 2219 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 2220 { 2221 do_shl32_div32(dividend, divisor); 2222 return dividend; 2223 } 2224 2225 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 2226 s8 *pshift, u32 *pmultiplier) 2227 { 2228 uint64_t scaled64; 2229 int32_t shift = 0; 2230 uint64_t tps64; 2231 uint32_t tps32; 2232 2233 tps64 = base_hz; 2234 scaled64 = scaled_hz; 2235 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 2236 tps64 >>= 1; 2237 shift--; 2238 } 2239 2240 tps32 = (uint32_t)tps64; 2241 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 2242 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 2243 scaled64 >>= 1; 2244 else 2245 tps32 <<= 1; 2246 shift++; 2247 } 2248 2249 *pshift = shift; 2250 *pmultiplier = div_frac(scaled64, tps32); 2251 } 2252 2253 #ifdef CONFIG_X86_64 2254 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 2255 #endif 2256 2257 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 2258 static unsigned long max_tsc_khz; 2259 2260 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 2261 { 2262 u64 v = (u64)khz * (1000000 + ppm); 2263 do_div(v, 1000000); 2264 return v; 2265 } 2266 2267 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier); 2268 2269 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 2270 { 2271 u64 ratio; 2272 2273 /* Guest TSC same frequency as host TSC? */ 2274 if (!scale) { 2275 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); 2276 return 0; 2277 } 2278 2279 /* TSC scaling supported? */ 2280 if (!kvm_has_tsc_control) { 2281 if (user_tsc_khz > tsc_khz) { 2282 vcpu->arch.tsc_catchup = 1; 2283 vcpu->arch.tsc_always_catchup = 1; 2284 return 0; 2285 } else { 2286 pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); 2287 return -1; 2288 } 2289 } 2290 2291 /* TSC scaling required - calculate ratio */ 2292 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 2293 user_tsc_khz, tsc_khz); 2294 2295 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 2296 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 2297 user_tsc_khz); 2298 return -1; 2299 } 2300 2301 kvm_vcpu_write_tsc_multiplier(vcpu, ratio); 2302 return 0; 2303 } 2304 2305 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 2306 { 2307 u32 thresh_lo, thresh_hi; 2308 int use_scaling = 0; 2309 2310 /* tsc_khz can be zero if TSC calibration fails */ 2311 if (user_tsc_khz == 0) { 2312 /* set tsc_scaling_ratio to a safe value */ 2313 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio); 2314 return -1; 2315 } 2316 2317 /* Compute a scale to convert nanoseconds in TSC cycles */ 2318 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 2319 &vcpu->arch.virtual_tsc_shift, 2320 &vcpu->arch.virtual_tsc_mult); 2321 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 2322 2323 /* 2324 * Compute the variation in TSC rate which is acceptable 2325 * within the range of tolerance and decide if the 2326 * rate being applied is within that bounds of the hardware 2327 * rate. If so, no scaling or compensation need be done. 2328 */ 2329 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 2330 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 2331 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 2332 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 2333 use_scaling = 1; 2334 } 2335 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 2336 } 2337 2338 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 2339 { 2340 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 2341 vcpu->arch.virtual_tsc_mult, 2342 vcpu->arch.virtual_tsc_shift); 2343 tsc += vcpu->arch.this_tsc_write; 2344 return tsc; 2345 } 2346 2347 static inline int gtod_is_based_on_tsc(int mode) 2348 { 2349 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; 2350 } 2351 2352 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 2353 { 2354 #ifdef CONFIG_X86_64 2355 bool vcpus_matched; 2356 struct kvm_arch *ka = &vcpu->kvm->arch; 2357 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2358 2359 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2360 atomic_read(&vcpu->kvm->online_vcpus)); 2361 2362 /* 2363 * Once the masterclock is enabled, always perform request in 2364 * order to update it. 2365 * 2366 * In order to enable masterclock, the host clocksource must be TSC 2367 * and the vcpus need to have matched TSCs. When that happens, 2368 * perform request to enable masterclock. 2369 */ 2370 if (ka->use_master_clock || 2371 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 2372 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2373 2374 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 2375 atomic_read(&vcpu->kvm->online_vcpus), 2376 ka->use_master_clock, gtod->clock.vclock_mode); 2377 #endif 2378 } 2379 2380 /* 2381 * Multiply tsc by a fixed point number represented by ratio. 2382 * 2383 * The most significant 64-N bits (mult) of ratio represent the 2384 * integral part of the fixed point number; the remaining N bits 2385 * (frac) represent the fractional part, ie. ratio represents a fixed 2386 * point number (mult + frac * 2^(-N)). 2387 * 2388 * N equals to kvm_tsc_scaling_ratio_frac_bits. 2389 */ 2390 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 2391 { 2392 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 2393 } 2394 2395 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc, u64 ratio) 2396 { 2397 u64 _tsc = tsc; 2398 2399 if (ratio != kvm_default_tsc_scaling_ratio) 2400 _tsc = __scale_tsc(ratio, tsc); 2401 2402 return _tsc; 2403 } 2404 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 2405 2406 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 2407 { 2408 u64 tsc; 2409 2410 tsc = kvm_scale_tsc(vcpu, rdtsc(), vcpu->arch.l1_tsc_scaling_ratio); 2411 2412 return target_tsc - tsc; 2413 } 2414 2415 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 2416 { 2417 return vcpu->arch.l1_tsc_offset + 2418 kvm_scale_tsc(vcpu, host_tsc, vcpu->arch.l1_tsc_scaling_ratio); 2419 } 2420 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 2421 2422 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier) 2423 { 2424 u64 nested_offset; 2425 2426 if (l2_multiplier == kvm_default_tsc_scaling_ratio) 2427 nested_offset = l1_offset; 2428 else 2429 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier, 2430 kvm_tsc_scaling_ratio_frac_bits); 2431 2432 nested_offset += l2_offset; 2433 return nested_offset; 2434 } 2435 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset); 2436 2437 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier) 2438 { 2439 if (l2_multiplier != kvm_default_tsc_scaling_ratio) 2440 return mul_u64_u64_shr(l1_multiplier, l2_multiplier, 2441 kvm_tsc_scaling_ratio_frac_bits); 2442 2443 return l1_multiplier; 2444 } 2445 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier); 2446 2447 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset) 2448 { 2449 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 2450 vcpu->arch.l1_tsc_offset, 2451 l1_offset); 2452 2453 vcpu->arch.l1_tsc_offset = l1_offset; 2454 2455 /* 2456 * If we are here because L1 chose not to trap WRMSR to TSC then 2457 * according to the spec this should set L1's TSC (as opposed to 2458 * setting L1's offset for L2). 2459 */ 2460 if (is_guest_mode(vcpu)) 2461 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( 2462 l1_offset, 2463 static_call(kvm_x86_get_l2_tsc_offset)(vcpu), 2464 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2465 else 2466 vcpu->arch.tsc_offset = l1_offset; 2467 2468 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset); 2469 } 2470 2471 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier) 2472 { 2473 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier; 2474 2475 /* Userspace is changing the multiplier while L2 is active */ 2476 if (is_guest_mode(vcpu)) 2477 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( 2478 l1_multiplier, 2479 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2480 else 2481 vcpu->arch.tsc_scaling_ratio = l1_multiplier; 2482 2483 if (kvm_has_tsc_control) 2484 static_call(kvm_x86_write_tsc_multiplier)( 2485 vcpu, vcpu->arch.tsc_scaling_ratio); 2486 } 2487 2488 static inline bool kvm_check_tsc_unstable(void) 2489 { 2490 #ifdef CONFIG_X86_64 2491 /* 2492 * TSC is marked unstable when we're running on Hyper-V, 2493 * 'TSC page' clocksource is good. 2494 */ 2495 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) 2496 return false; 2497 #endif 2498 return check_tsc_unstable(); 2499 } 2500 2501 /* 2502 * Infers attempts to synchronize the guest's tsc from host writes. Sets the 2503 * offset for the vcpu and tracks the TSC matching generation that the vcpu 2504 * participates in. 2505 */ 2506 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc, 2507 u64 ns, bool matched) 2508 { 2509 struct kvm *kvm = vcpu->kvm; 2510 2511 lockdep_assert_held(&kvm->arch.tsc_write_lock); 2512 2513 /* 2514 * We also track th most recent recorded KHZ, write and time to 2515 * allow the matching interval to be extended at each write. 2516 */ 2517 kvm->arch.last_tsc_nsec = ns; 2518 kvm->arch.last_tsc_write = tsc; 2519 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 2520 kvm->arch.last_tsc_offset = offset; 2521 2522 vcpu->arch.last_guest_tsc = tsc; 2523 2524 kvm_vcpu_write_tsc_offset(vcpu, offset); 2525 2526 if (!matched) { 2527 /* 2528 * We split periods of matched TSC writes into generations. 2529 * For each generation, we track the original measured 2530 * nanosecond time, offset, and write, so if TSCs are in 2531 * sync, we can match exact offset, and if not, we can match 2532 * exact software computation in compute_guest_tsc() 2533 * 2534 * These values are tracked in kvm->arch.cur_xxx variables. 2535 */ 2536 kvm->arch.cur_tsc_generation++; 2537 kvm->arch.cur_tsc_nsec = ns; 2538 kvm->arch.cur_tsc_write = tsc; 2539 kvm->arch.cur_tsc_offset = offset; 2540 kvm->arch.nr_vcpus_matched_tsc = 0; 2541 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) { 2542 kvm->arch.nr_vcpus_matched_tsc++; 2543 } 2544 2545 /* Keep track of which generation this VCPU has synchronized to */ 2546 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 2547 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 2548 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 2549 2550 kvm_track_tsc_matching(vcpu); 2551 } 2552 2553 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) 2554 { 2555 struct kvm *kvm = vcpu->kvm; 2556 u64 offset, ns, elapsed; 2557 unsigned long flags; 2558 bool matched = false; 2559 bool synchronizing = false; 2560 2561 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 2562 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2563 ns = get_kvmclock_base_ns(); 2564 elapsed = ns - kvm->arch.last_tsc_nsec; 2565 2566 if (vcpu->arch.virtual_tsc_khz) { 2567 if (data == 0) { 2568 /* 2569 * detection of vcpu initialization -- need to sync 2570 * with other vCPUs. This particularly helps to keep 2571 * kvm_clock stable after CPU hotplug 2572 */ 2573 synchronizing = true; 2574 } else { 2575 u64 tsc_exp = kvm->arch.last_tsc_write + 2576 nsec_to_cycles(vcpu, elapsed); 2577 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 2578 /* 2579 * Special case: TSC write with a small delta (1 second) 2580 * of virtual cycle time against real time is 2581 * interpreted as an attempt to synchronize the CPU. 2582 */ 2583 synchronizing = data < tsc_exp + tsc_hz && 2584 data + tsc_hz > tsc_exp; 2585 } 2586 } 2587 2588 /* 2589 * For a reliable TSC, we can match TSC offsets, and for an unstable 2590 * TSC, we add elapsed time in this computation. We could let the 2591 * compensation code attempt to catch up if we fall behind, but 2592 * it's better to try to match offsets from the beginning. 2593 */ 2594 if (synchronizing && 2595 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 2596 if (!kvm_check_tsc_unstable()) { 2597 offset = kvm->arch.cur_tsc_offset; 2598 } else { 2599 u64 delta = nsec_to_cycles(vcpu, elapsed); 2600 data += delta; 2601 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2602 } 2603 matched = true; 2604 } 2605 2606 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched); 2607 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 2608 } 2609 2610 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 2611 s64 adjustment) 2612 { 2613 u64 tsc_offset = vcpu->arch.l1_tsc_offset; 2614 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 2615 } 2616 2617 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 2618 { 2619 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 2620 WARN_ON(adjustment < 0); 2621 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment, 2622 vcpu->arch.l1_tsc_scaling_ratio); 2623 adjust_tsc_offset_guest(vcpu, adjustment); 2624 } 2625 2626 #ifdef CONFIG_X86_64 2627 2628 static u64 read_tsc(void) 2629 { 2630 u64 ret = (u64)rdtsc_ordered(); 2631 u64 last = pvclock_gtod_data.clock.cycle_last; 2632 2633 if (likely(ret >= last)) 2634 return ret; 2635 2636 /* 2637 * GCC likes to generate cmov here, but this branch is extremely 2638 * predictable (it's just a function of time and the likely is 2639 * very likely) and there's a data dependence, so force GCC 2640 * to generate a branch instead. I don't barrier() because 2641 * we don't actually need a barrier, and if this function 2642 * ever gets inlined it will generate worse code. 2643 */ 2644 asm volatile (""); 2645 return last; 2646 } 2647 2648 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, 2649 int *mode) 2650 { 2651 long v; 2652 u64 tsc_pg_val; 2653 2654 switch (clock->vclock_mode) { 2655 case VDSO_CLOCKMODE_HVCLOCK: 2656 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 2657 tsc_timestamp); 2658 if (tsc_pg_val != U64_MAX) { 2659 /* TSC page valid */ 2660 *mode = VDSO_CLOCKMODE_HVCLOCK; 2661 v = (tsc_pg_val - clock->cycle_last) & 2662 clock->mask; 2663 } else { 2664 /* TSC page invalid */ 2665 *mode = VDSO_CLOCKMODE_NONE; 2666 } 2667 break; 2668 case VDSO_CLOCKMODE_TSC: 2669 *mode = VDSO_CLOCKMODE_TSC; 2670 *tsc_timestamp = read_tsc(); 2671 v = (*tsc_timestamp - clock->cycle_last) & 2672 clock->mask; 2673 break; 2674 default: 2675 *mode = VDSO_CLOCKMODE_NONE; 2676 } 2677 2678 if (*mode == VDSO_CLOCKMODE_NONE) 2679 *tsc_timestamp = v = 0; 2680 2681 return v * clock->mult; 2682 } 2683 2684 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) 2685 { 2686 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2687 unsigned long seq; 2688 int mode; 2689 u64 ns; 2690 2691 do { 2692 seq = read_seqcount_begin(>od->seq); 2693 ns = gtod->raw_clock.base_cycles; 2694 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); 2695 ns >>= gtod->raw_clock.shift; 2696 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); 2697 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2698 *t = ns; 2699 2700 return mode; 2701 } 2702 2703 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 2704 { 2705 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2706 unsigned long seq; 2707 int mode; 2708 u64 ns; 2709 2710 do { 2711 seq = read_seqcount_begin(>od->seq); 2712 ts->tv_sec = gtod->wall_time_sec; 2713 ns = gtod->clock.base_cycles; 2714 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2715 ns >>= gtod->clock.shift; 2716 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2717 2718 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 2719 ts->tv_nsec = ns; 2720 2721 return mode; 2722 } 2723 2724 /* returns true if host is using TSC based clocksource */ 2725 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2726 { 2727 /* checked again under seqlock below */ 2728 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2729 return false; 2730 2731 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, 2732 tsc_timestamp)); 2733 } 2734 2735 /* returns true if host is using TSC based clocksource */ 2736 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 2737 u64 *tsc_timestamp) 2738 { 2739 /* checked again under seqlock below */ 2740 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2741 return false; 2742 2743 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 2744 } 2745 #endif 2746 2747 /* 2748 * 2749 * Assuming a stable TSC across physical CPUS, and a stable TSC 2750 * across virtual CPUs, the following condition is possible. 2751 * Each numbered line represents an event visible to both 2752 * CPUs at the next numbered event. 2753 * 2754 * "timespecX" represents host monotonic time. "tscX" represents 2755 * RDTSC value. 2756 * 2757 * VCPU0 on CPU0 | VCPU1 on CPU1 2758 * 2759 * 1. read timespec0,tsc0 2760 * 2. | timespec1 = timespec0 + N 2761 * | tsc1 = tsc0 + M 2762 * 3. transition to guest | transition to guest 2763 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 2764 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 2765 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 2766 * 2767 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 2768 * 2769 * - ret0 < ret1 2770 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 2771 * ... 2772 * - 0 < N - M => M < N 2773 * 2774 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 2775 * always the case (the difference between two distinct xtime instances 2776 * might be smaller then the difference between corresponding TSC reads, 2777 * when updating guest vcpus pvclock areas). 2778 * 2779 * To avoid that problem, do not allow visibility of distinct 2780 * system_timestamp/tsc_timestamp values simultaneously: use a master 2781 * copy of host monotonic time values. Update that master copy 2782 * in lockstep. 2783 * 2784 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2785 * 2786 */ 2787 2788 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2789 { 2790 #ifdef CONFIG_X86_64 2791 struct kvm_arch *ka = &kvm->arch; 2792 int vclock_mode; 2793 bool host_tsc_clocksource, vcpus_matched; 2794 2795 lockdep_assert_held(&kvm->arch.tsc_write_lock); 2796 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2797 atomic_read(&kvm->online_vcpus)); 2798 2799 /* 2800 * If the host uses TSC clock, then passthrough TSC as stable 2801 * to the guest. 2802 */ 2803 host_tsc_clocksource = kvm_get_time_and_clockread( 2804 &ka->master_kernel_ns, 2805 &ka->master_cycle_now); 2806 2807 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2808 && !ka->backwards_tsc_observed 2809 && !ka->boot_vcpu_runs_old_kvmclock; 2810 2811 if (ka->use_master_clock) 2812 atomic_set(&kvm_guest_has_master_clock, 1); 2813 2814 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2815 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2816 vcpus_matched); 2817 #endif 2818 } 2819 2820 static void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2821 { 2822 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2823 } 2824 2825 static void __kvm_start_pvclock_update(struct kvm *kvm) 2826 { 2827 raw_spin_lock_irq(&kvm->arch.tsc_write_lock); 2828 write_seqcount_begin(&kvm->arch.pvclock_sc); 2829 } 2830 2831 static void kvm_start_pvclock_update(struct kvm *kvm) 2832 { 2833 kvm_make_mclock_inprogress_request(kvm); 2834 2835 /* no guest entries from this point */ 2836 __kvm_start_pvclock_update(kvm); 2837 } 2838 2839 static void kvm_end_pvclock_update(struct kvm *kvm) 2840 { 2841 struct kvm_arch *ka = &kvm->arch; 2842 struct kvm_vcpu *vcpu; 2843 unsigned long i; 2844 2845 write_seqcount_end(&ka->pvclock_sc); 2846 raw_spin_unlock_irq(&ka->tsc_write_lock); 2847 kvm_for_each_vcpu(i, vcpu, kvm) 2848 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2849 2850 /* guest entries allowed */ 2851 kvm_for_each_vcpu(i, vcpu, kvm) 2852 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2853 } 2854 2855 static void kvm_update_masterclock(struct kvm *kvm) 2856 { 2857 kvm_hv_invalidate_tsc_page(kvm); 2858 kvm_start_pvclock_update(kvm); 2859 pvclock_update_vm_gtod_copy(kvm); 2860 kvm_end_pvclock_update(kvm); 2861 } 2862 2863 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */ 2864 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) 2865 { 2866 struct kvm_arch *ka = &kvm->arch; 2867 struct pvclock_vcpu_time_info hv_clock; 2868 2869 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2870 get_cpu(); 2871 2872 data->flags = 0; 2873 if (ka->use_master_clock && __this_cpu_read(cpu_tsc_khz)) { 2874 #ifdef CONFIG_X86_64 2875 struct timespec64 ts; 2876 2877 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) { 2878 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec; 2879 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC; 2880 } else 2881 #endif 2882 data->host_tsc = rdtsc(); 2883 2884 data->flags |= KVM_CLOCK_TSC_STABLE; 2885 hv_clock.tsc_timestamp = ka->master_cycle_now; 2886 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2887 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2888 &hv_clock.tsc_shift, 2889 &hv_clock.tsc_to_system_mul); 2890 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc); 2891 } else { 2892 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset; 2893 } 2894 2895 put_cpu(); 2896 } 2897 2898 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) 2899 { 2900 struct kvm_arch *ka = &kvm->arch; 2901 unsigned seq; 2902 2903 do { 2904 seq = read_seqcount_begin(&ka->pvclock_sc); 2905 __get_kvmclock(kvm, data); 2906 } while (read_seqcount_retry(&ka->pvclock_sc, seq)); 2907 } 2908 2909 u64 get_kvmclock_ns(struct kvm *kvm) 2910 { 2911 struct kvm_clock_data data; 2912 2913 get_kvmclock(kvm, &data); 2914 return data.clock; 2915 } 2916 2917 static void kvm_setup_pvclock_page(struct kvm_vcpu *v, 2918 struct gfn_to_hva_cache *cache, 2919 unsigned int offset) 2920 { 2921 struct kvm_vcpu_arch *vcpu = &v->arch; 2922 struct pvclock_vcpu_time_info guest_hv_clock; 2923 2924 if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache, 2925 &guest_hv_clock, offset, sizeof(guest_hv_clock)))) 2926 return; 2927 2928 /* This VCPU is paused, but it's legal for a guest to read another 2929 * VCPU's kvmclock, so we really have to follow the specification where 2930 * it says that version is odd if data is being modified, and even after 2931 * it is consistent. 2932 * 2933 * Version field updates must be kept separate. This is because 2934 * kvm_write_guest_cached might use a "rep movs" instruction, and 2935 * writes within a string instruction are weakly ordered. So there 2936 * are three writes overall. 2937 * 2938 * As a small optimization, only write the version field in the first 2939 * and third write. The vcpu->pv_time cache is still valid, because the 2940 * version field is the first in the struct. 2941 */ 2942 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 2943 2944 if (guest_hv_clock.version & 1) 2945 ++guest_hv_clock.version; /* first time write, random junk */ 2946 2947 vcpu->hv_clock.version = guest_hv_clock.version + 1; 2948 kvm_write_guest_offset_cached(v->kvm, cache, 2949 &vcpu->hv_clock, offset, 2950 sizeof(vcpu->hv_clock.version)); 2951 2952 smp_wmb(); 2953 2954 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 2955 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 2956 2957 if (vcpu->pvclock_set_guest_stopped_request) { 2958 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 2959 vcpu->pvclock_set_guest_stopped_request = false; 2960 } 2961 2962 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 2963 2964 kvm_write_guest_offset_cached(v->kvm, cache, 2965 &vcpu->hv_clock, offset, 2966 sizeof(vcpu->hv_clock)); 2967 2968 smp_wmb(); 2969 2970 vcpu->hv_clock.version++; 2971 kvm_write_guest_offset_cached(v->kvm, cache, 2972 &vcpu->hv_clock, offset, 2973 sizeof(vcpu->hv_clock.version)); 2974 } 2975 2976 static int kvm_guest_time_update(struct kvm_vcpu *v) 2977 { 2978 unsigned long flags, tgt_tsc_khz; 2979 unsigned seq; 2980 struct kvm_vcpu_arch *vcpu = &v->arch; 2981 struct kvm_arch *ka = &v->kvm->arch; 2982 s64 kernel_ns; 2983 u64 tsc_timestamp, host_tsc; 2984 u8 pvclock_flags; 2985 bool use_master_clock; 2986 2987 kernel_ns = 0; 2988 host_tsc = 0; 2989 2990 /* 2991 * If the host uses TSC clock, then passthrough TSC as stable 2992 * to the guest. 2993 */ 2994 do { 2995 seq = read_seqcount_begin(&ka->pvclock_sc); 2996 use_master_clock = ka->use_master_clock; 2997 if (use_master_clock) { 2998 host_tsc = ka->master_cycle_now; 2999 kernel_ns = ka->master_kernel_ns; 3000 } 3001 } while (read_seqcount_retry(&ka->pvclock_sc, seq)); 3002 3003 /* Keep irq disabled to prevent changes to the clock */ 3004 local_irq_save(flags); 3005 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 3006 if (unlikely(tgt_tsc_khz == 0)) { 3007 local_irq_restore(flags); 3008 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 3009 return 1; 3010 } 3011 if (!use_master_clock) { 3012 host_tsc = rdtsc(); 3013 kernel_ns = get_kvmclock_base_ns(); 3014 } 3015 3016 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 3017 3018 /* 3019 * We may have to catch up the TSC to match elapsed wall clock 3020 * time for two reasons, even if kvmclock is used. 3021 * 1) CPU could have been running below the maximum TSC rate 3022 * 2) Broken TSC compensation resets the base at each VCPU 3023 * entry to avoid unknown leaps of TSC even when running 3024 * again on the same CPU. This may cause apparent elapsed 3025 * time to disappear, and the guest to stand still or run 3026 * very slowly. 3027 */ 3028 if (vcpu->tsc_catchup) { 3029 u64 tsc = compute_guest_tsc(v, kernel_ns); 3030 if (tsc > tsc_timestamp) { 3031 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 3032 tsc_timestamp = tsc; 3033 } 3034 } 3035 3036 local_irq_restore(flags); 3037 3038 /* With all the info we got, fill in the values */ 3039 3040 if (kvm_has_tsc_control) 3041 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz, 3042 v->arch.l1_tsc_scaling_ratio); 3043 3044 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 3045 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 3046 &vcpu->hv_clock.tsc_shift, 3047 &vcpu->hv_clock.tsc_to_system_mul); 3048 vcpu->hw_tsc_khz = tgt_tsc_khz; 3049 } 3050 3051 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 3052 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 3053 vcpu->last_guest_tsc = tsc_timestamp; 3054 3055 /* If the host uses TSC clocksource, then it is stable */ 3056 pvclock_flags = 0; 3057 if (use_master_clock) 3058 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 3059 3060 vcpu->hv_clock.flags = pvclock_flags; 3061 3062 if (vcpu->pv_time_enabled) 3063 kvm_setup_pvclock_page(v, &vcpu->pv_time, 0); 3064 if (vcpu->xen.vcpu_info_set) 3065 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache, 3066 offsetof(struct compat_vcpu_info, time)); 3067 if (vcpu->xen.vcpu_time_info_set) 3068 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0); 3069 if (!v->vcpu_idx) 3070 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 3071 return 0; 3072 } 3073 3074 /* 3075 * kvmclock updates which are isolated to a given vcpu, such as 3076 * vcpu->cpu migration, should not allow system_timestamp from 3077 * the rest of the vcpus to remain static. Otherwise ntp frequency 3078 * correction applies to one vcpu's system_timestamp but not 3079 * the others. 3080 * 3081 * So in those cases, request a kvmclock update for all vcpus. 3082 * We need to rate-limit these requests though, as they can 3083 * considerably slow guests that have a large number of vcpus. 3084 * The time for a remote vcpu to update its kvmclock is bound 3085 * by the delay we use to rate-limit the updates. 3086 */ 3087 3088 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 3089 3090 static void kvmclock_update_fn(struct work_struct *work) 3091 { 3092 unsigned long i; 3093 struct delayed_work *dwork = to_delayed_work(work); 3094 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3095 kvmclock_update_work); 3096 struct kvm *kvm = container_of(ka, struct kvm, arch); 3097 struct kvm_vcpu *vcpu; 3098 3099 kvm_for_each_vcpu(i, vcpu, kvm) { 3100 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3101 kvm_vcpu_kick(vcpu); 3102 } 3103 } 3104 3105 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 3106 { 3107 struct kvm *kvm = v->kvm; 3108 3109 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 3110 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 3111 KVMCLOCK_UPDATE_DELAY); 3112 } 3113 3114 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 3115 3116 static void kvmclock_sync_fn(struct work_struct *work) 3117 { 3118 struct delayed_work *dwork = to_delayed_work(work); 3119 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3120 kvmclock_sync_work); 3121 struct kvm *kvm = container_of(ka, struct kvm, arch); 3122 3123 if (!kvmclock_periodic_sync) 3124 return; 3125 3126 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 3127 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 3128 KVMCLOCK_SYNC_PERIOD); 3129 } 3130 3131 /* 3132 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 3133 */ 3134 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 3135 { 3136 /* McStatusWrEn enabled? */ 3137 if (guest_cpuid_is_amd_or_hygon(vcpu)) 3138 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 3139 3140 return false; 3141 } 3142 3143 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3144 { 3145 u64 mcg_cap = vcpu->arch.mcg_cap; 3146 unsigned bank_num = mcg_cap & 0xff; 3147 u32 msr = msr_info->index; 3148 u64 data = msr_info->data; 3149 3150 switch (msr) { 3151 case MSR_IA32_MCG_STATUS: 3152 vcpu->arch.mcg_status = data; 3153 break; 3154 case MSR_IA32_MCG_CTL: 3155 if (!(mcg_cap & MCG_CTL_P) && 3156 (data || !msr_info->host_initiated)) 3157 return 1; 3158 if (data != 0 && data != ~(u64)0) 3159 return 1; 3160 vcpu->arch.mcg_ctl = data; 3161 break; 3162 default: 3163 if (msr >= MSR_IA32_MC0_CTL && 3164 msr < MSR_IA32_MCx_CTL(bank_num)) { 3165 u32 offset = array_index_nospec( 3166 msr - MSR_IA32_MC0_CTL, 3167 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3168 3169 /* only 0 or all 1s can be written to IA32_MCi_CTL 3170 * some Linux kernels though clear bit 10 in bank 4 to 3171 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 3172 * this to avoid an uncatched #GP in the guest 3173 */ 3174 if ((offset & 0x3) == 0 && 3175 data != 0 && (data | (1 << 10)) != ~(u64)0) 3176 return -1; 3177 3178 /* MCi_STATUS */ 3179 if (!msr_info->host_initiated && 3180 (offset & 0x3) == 1 && data != 0) { 3181 if (!can_set_mci_status(vcpu)) 3182 return -1; 3183 } 3184 3185 vcpu->arch.mce_banks[offset] = data; 3186 break; 3187 } 3188 return 1; 3189 } 3190 return 0; 3191 } 3192 3193 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) 3194 { 3195 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; 3196 3197 return (vcpu->arch.apf.msr_en_val & mask) == mask; 3198 } 3199 3200 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 3201 { 3202 gpa_t gpa = data & ~0x3f; 3203 3204 /* Bits 4:5 are reserved, Should be zero */ 3205 if (data & 0x30) 3206 return 1; 3207 3208 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && 3209 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) 3210 return 1; 3211 3212 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && 3213 (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) 3214 return 1; 3215 3216 if (!lapic_in_kernel(vcpu)) 3217 return data ? 1 : 0; 3218 3219 vcpu->arch.apf.msr_en_val = data; 3220 3221 if (!kvm_pv_async_pf_enabled(vcpu)) { 3222 kvm_clear_async_pf_completion_queue(vcpu); 3223 kvm_async_pf_hash_reset(vcpu); 3224 return 0; 3225 } 3226 3227 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 3228 sizeof(u64))) 3229 return 1; 3230 3231 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 3232 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 3233 3234 kvm_async_pf_wakeup_all(vcpu); 3235 3236 return 0; 3237 } 3238 3239 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) 3240 { 3241 /* Bits 8-63 are reserved */ 3242 if (data >> 8) 3243 return 1; 3244 3245 if (!lapic_in_kernel(vcpu)) 3246 return 1; 3247 3248 vcpu->arch.apf.msr_int_val = data; 3249 3250 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; 3251 3252 return 0; 3253 } 3254 3255 static void kvmclock_reset(struct kvm_vcpu *vcpu) 3256 { 3257 vcpu->arch.pv_time_enabled = false; 3258 vcpu->arch.time = 0; 3259 } 3260 3261 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) 3262 { 3263 ++vcpu->stat.tlb_flush; 3264 static_call(kvm_x86_tlb_flush_all)(vcpu); 3265 } 3266 3267 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) 3268 { 3269 ++vcpu->stat.tlb_flush; 3270 3271 if (!tdp_enabled) { 3272 /* 3273 * A TLB flush on behalf of the guest is equivalent to 3274 * INVPCID(all), toggling CR4.PGE, etc., which requires 3275 * a forced sync of the shadow page tables. Ensure all the 3276 * roots are synced and the guest TLB in hardware is clean. 3277 */ 3278 kvm_mmu_sync_roots(vcpu); 3279 kvm_mmu_sync_prev_roots(vcpu); 3280 } 3281 3282 static_call(kvm_x86_tlb_flush_guest)(vcpu); 3283 } 3284 3285 3286 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu) 3287 { 3288 ++vcpu->stat.tlb_flush; 3289 static_call(kvm_x86_tlb_flush_current)(vcpu); 3290 } 3291 3292 /* 3293 * Service "local" TLB flush requests, which are specific to the current MMU 3294 * context. In addition to the generic event handling in vcpu_enter_guest(), 3295 * TLB flushes that are targeted at an MMU context also need to be serviced 3296 * prior before nested VM-Enter/VM-Exit. 3297 */ 3298 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu) 3299 { 3300 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) 3301 kvm_vcpu_flush_tlb_current(vcpu); 3302 3303 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu)) 3304 kvm_vcpu_flush_tlb_guest(vcpu); 3305 } 3306 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests); 3307 3308 static void record_steal_time(struct kvm_vcpu *vcpu) 3309 { 3310 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; 3311 struct kvm_steal_time __user *st; 3312 struct kvm_memslots *slots; 3313 u64 steal; 3314 u32 version; 3315 3316 if (kvm_xen_msr_enabled(vcpu->kvm)) { 3317 kvm_xen_runstate_set_running(vcpu); 3318 return; 3319 } 3320 3321 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3322 return; 3323 3324 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm)) 3325 return; 3326 3327 slots = kvm_memslots(vcpu->kvm); 3328 3329 if (unlikely(slots->generation != ghc->generation || 3330 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) { 3331 gfn_t gfn = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; 3332 3333 /* We rely on the fact that it fits in a single page. */ 3334 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS); 3335 3336 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gfn, sizeof(*st)) || 3337 kvm_is_error_hva(ghc->hva) || !ghc->memslot) 3338 return; 3339 } 3340 3341 st = (struct kvm_steal_time __user *)ghc->hva; 3342 /* 3343 * Doing a TLB flush here, on the guest's behalf, can avoid 3344 * expensive IPIs. 3345 */ 3346 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { 3347 u8 st_preempted = 0; 3348 int err = -EFAULT; 3349 3350 if (!user_access_begin(st, sizeof(*st))) 3351 return; 3352 3353 asm volatile("1: xchgb %0, %2\n" 3354 "xor %1, %1\n" 3355 "2:\n" 3356 _ASM_EXTABLE_UA(1b, 2b) 3357 : "+q" (st_preempted), 3358 "+&r" (err), 3359 "+m" (st->preempted)); 3360 if (err) 3361 goto out; 3362 3363 user_access_end(); 3364 3365 vcpu->arch.st.preempted = 0; 3366 3367 trace_kvm_pv_tlb_flush(vcpu->vcpu_id, 3368 st_preempted & KVM_VCPU_FLUSH_TLB); 3369 if (st_preempted & KVM_VCPU_FLUSH_TLB) 3370 kvm_vcpu_flush_tlb_guest(vcpu); 3371 3372 if (!user_access_begin(st, sizeof(*st))) 3373 goto dirty; 3374 } else { 3375 if (!user_access_begin(st, sizeof(*st))) 3376 return; 3377 3378 unsafe_put_user(0, &st->preempted, out); 3379 vcpu->arch.st.preempted = 0; 3380 } 3381 3382 unsafe_get_user(version, &st->version, out); 3383 if (version & 1) 3384 version += 1; /* first time write, random junk */ 3385 3386 version += 1; 3387 unsafe_put_user(version, &st->version, out); 3388 3389 smp_wmb(); 3390 3391 unsafe_get_user(steal, &st->steal, out); 3392 steal += current->sched_info.run_delay - 3393 vcpu->arch.st.last_steal; 3394 vcpu->arch.st.last_steal = current->sched_info.run_delay; 3395 unsafe_put_user(steal, &st->steal, out); 3396 3397 version += 1; 3398 unsafe_put_user(version, &st->version, out); 3399 3400 out: 3401 user_access_end(); 3402 dirty: 3403 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 3404 } 3405 3406 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3407 { 3408 bool pr = false; 3409 u32 msr = msr_info->index; 3410 u64 data = msr_info->data; 3411 3412 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) 3413 return kvm_xen_write_hypercall_page(vcpu, data); 3414 3415 switch (msr) { 3416 case MSR_AMD64_NB_CFG: 3417 case MSR_IA32_UCODE_WRITE: 3418 case MSR_VM_HSAVE_PA: 3419 case MSR_AMD64_PATCH_LOADER: 3420 case MSR_AMD64_BU_CFG2: 3421 case MSR_AMD64_DC_CFG: 3422 case MSR_F15H_EX_CFG: 3423 break; 3424 3425 case MSR_IA32_UCODE_REV: 3426 if (msr_info->host_initiated) 3427 vcpu->arch.microcode_version = data; 3428 break; 3429 case MSR_IA32_ARCH_CAPABILITIES: 3430 if (!msr_info->host_initiated) 3431 return 1; 3432 vcpu->arch.arch_capabilities = data; 3433 break; 3434 case MSR_IA32_PERF_CAPABILITIES: { 3435 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; 3436 3437 if (!msr_info->host_initiated) 3438 return 1; 3439 if (kvm_get_msr_feature(&msr_ent)) 3440 return 1; 3441 if (data & ~msr_ent.data) 3442 return 1; 3443 3444 vcpu->arch.perf_capabilities = data; 3445 3446 return 0; 3447 } 3448 case MSR_EFER: 3449 return set_efer(vcpu, msr_info); 3450 case MSR_K7_HWCR: 3451 data &= ~(u64)0x40; /* ignore flush filter disable */ 3452 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 3453 data &= ~(u64)0x8; /* ignore TLB cache disable */ 3454 3455 /* Handle McStatusWrEn */ 3456 if (data == BIT_ULL(18)) { 3457 vcpu->arch.msr_hwcr = data; 3458 } else if (data != 0) { 3459 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 3460 data); 3461 return 1; 3462 } 3463 break; 3464 case MSR_FAM10H_MMIO_CONF_BASE: 3465 if (data != 0) { 3466 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 3467 "0x%llx\n", data); 3468 return 1; 3469 } 3470 break; 3471 case 0x200 ... 0x2ff: 3472 return kvm_mtrr_set_msr(vcpu, msr, data); 3473 case MSR_IA32_APICBASE: 3474 return kvm_set_apic_base(vcpu, msr_info); 3475 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3476 return kvm_x2apic_msr_write(vcpu, msr, data); 3477 case MSR_IA32_TSC_DEADLINE: 3478 kvm_set_lapic_tscdeadline_msr(vcpu, data); 3479 break; 3480 case MSR_IA32_TSC_ADJUST: 3481 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 3482 if (!msr_info->host_initiated) { 3483 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 3484 adjust_tsc_offset_guest(vcpu, adj); 3485 /* Before back to guest, tsc_timestamp must be adjusted 3486 * as well, otherwise guest's percpu pvclock time could jump. 3487 */ 3488 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3489 } 3490 vcpu->arch.ia32_tsc_adjust_msr = data; 3491 } 3492 break; 3493 case MSR_IA32_MISC_ENABLE: 3494 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && 3495 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { 3496 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) 3497 return 1; 3498 vcpu->arch.ia32_misc_enable_msr = data; 3499 kvm_update_cpuid_runtime(vcpu); 3500 } else { 3501 vcpu->arch.ia32_misc_enable_msr = data; 3502 } 3503 break; 3504 case MSR_IA32_SMBASE: 3505 if (!msr_info->host_initiated) 3506 return 1; 3507 vcpu->arch.smbase = data; 3508 break; 3509 case MSR_IA32_POWER_CTL: 3510 vcpu->arch.msr_ia32_power_ctl = data; 3511 break; 3512 case MSR_IA32_TSC: 3513 if (msr_info->host_initiated) { 3514 kvm_synchronize_tsc(vcpu, data); 3515 } else { 3516 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; 3517 adjust_tsc_offset_guest(vcpu, adj); 3518 vcpu->arch.ia32_tsc_adjust_msr += adj; 3519 } 3520 break; 3521 case MSR_IA32_XSS: 3522 if (!msr_info->host_initiated && 3523 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3524 return 1; 3525 /* 3526 * KVM supports exposing PT to the guest, but does not support 3527 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than 3528 * XSAVES/XRSTORS to save/restore PT MSRs. 3529 */ 3530 if (data & ~supported_xss) 3531 return 1; 3532 vcpu->arch.ia32_xss = data; 3533 break; 3534 case MSR_SMI_COUNT: 3535 if (!msr_info->host_initiated) 3536 return 1; 3537 vcpu->arch.smi_count = data; 3538 break; 3539 case MSR_KVM_WALL_CLOCK_NEW: 3540 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3541 return 1; 3542 3543 vcpu->kvm->arch.wall_clock = data; 3544 kvm_write_wall_clock(vcpu->kvm, data, 0); 3545 break; 3546 case MSR_KVM_WALL_CLOCK: 3547 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3548 return 1; 3549 3550 vcpu->kvm->arch.wall_clock = data; 3551 kvm_write_wall_clock(vcpu->kvm, data, 0); 3552 break; 3553 case MSR_KVM_SYSTEM_TIME_NEW: 3554 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3555 return 1; 3556 3557 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); 3558 break; 3559 case MSR_KVM_SYSTEM_TIME: 3560 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3561 return 1; 3562 3563 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); 3564 break; 3565 case MSR_KVM_ASYNC_PF_EN: 3566 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3567 return 1; 3568 3569 if (kvm_pv_enable_async_pf(vcpu, data)) 3570 return 1; 3571 break; 3572 case MSR_KVM_ASYNC_PF_INT: 3573 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3574 return 1; 3575 3576 if (kvm_pv_enable_async_pf_int(vcpu, data)) 3577 return 1; 3578 break; 3579 case MSR_KVM_ASYNC_PF_ACK: 3580 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3581 return 1; 3582 if (data & 0x1) { 3583 vcpu->arch.apf.pageready_pending = false; 3584 kvm_check_async_pf_completion(vcpu); 3585 } 3586 break; 3587 case MSR_KVM_STEAL_TIME: 3588 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3589 return 1; 3590 3591 if (unlikely(!sched_info_on())) 3592 return 1; 3593 3594 if (data & KVM_STEAL_RESERVED_MASK) 3595 return 1; 3596 3597 vcpu->arch.st.msr_val = data; 3598 3599 if (!(data & KVM_MSR_ENABLED)) 3600 break; 3601 3602 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3603 3604 break; 3605 case MSR_KVM_PV_EOI_EN: 3606 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3607 return 1; 3608 3609 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8))) 3610 return 1; 3611 break; 3612 3613 case MSR_KVM_POLL_CONTROL: 3614 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3615 return 1; 3616 3617 /* only enable bit supported */ 3618 if (data & (-1ULL << 1)) 3619 return 1; 3620 3621 vcpu->arch.msr_kvm_poll_control = data; 3622 break; 3623 3624 case MSR_IA32_MCG_CTL: 3625 case MSR_IA32_MCG_STATUS: 3626 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3627 return set_msr_mce(vcpu, msr_info); 3628 3629 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3630 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3631 pr = true; 3632 fallthrough; 3633 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3634 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3635 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3636 return kvm_pmu_set_msr(vcpu, msr_info); 3637 3638 if (pr || data != 0) 3639 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 3640 "0x%x data 0x%llx\n", msr, data); 3641 break; 3642 case MSR_K7_CLK_CTL: 3643 /* 3644 * Ignore all writes to this no longer documented MSR. 3645 * Writes are only relevant for old K7 processors, 3646 * all pre-dating SVM, but a recommended workaround from 3647 * AMD for these chips. It is possible to specify the 3648 * affected processor models on the command line, hence 3649 * the need to ignore the workaround. 3650 */ 3651 break; 3652 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3653 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3654 case HV_X64_MSR_SYNDBG_OPTIONS: 3655 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3656 case HV_X64_MSR_CRASH_CTL: 3657 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3658 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3659 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3660 case HV_X64_MSR_TSC_EMULATION_STATUS: 3661 return kvm_hv_set_msr_common(vcpu, msr, data, 3662 msr_info->host_initiated); 3663 case MSR_IA32_BBL_CR_CTL3: 3664 /* Drop writes to this legacy MSR -- see rdmsr 3665 * counterpart for further detail. 3666 */ 3667 if (report_ignored_msrs) 3668 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 3669 msr, data); 3670 break; 3671 case MSR_AMD64_OSVW_ID_LENGTH: 3672 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3673 return 1; 3674 vcpu->arch.osvw.length = data; 3675 break; 3676 case MSR_AMD64_OSVW_STATUS: 3677 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3678 return 1; 3679 vcpu->arch.osvw.status = data; 3680 break; 3681 case MSR_PLATFORM_INFO: 3682 if (!msr_info->host_initiated || 3683 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 3684 cpuid_fault_enabled(vcpu))) 3685 return 1; 3686 vcpu->arch.msr_platform_info = data; 3687 break; 3688 case MSR_MISC_FEATURES_ENABLES: 3689 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 3690 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3691 !supports_cpuid_fault(vcpu))) 3692 return 1; 3693 vcpu->arch.msr_misc_features_enables = data; 3694 break; 3695 #ifdef CONFIG_X86_64 3696 case MSR_IA32_XFD: 3697 if (!msr_info->host_initiated && 3698 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 3699 return 1; 3700 3701 if (data & ~(XFEATURE_MASK_USER_DYNAMIC & 3702 vcpu->arch.guest_supported_xcr0)) 3703 return 1; 3704 3705 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data); 3706 break; 3707 case MSR_IA32_XFD_ERR: 3708 if (!msr_info->host_initiated && 3709 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 3710 return 1; 3711 3712 if (data & ~(XFEATURE_MASK_USER_DYNAMIC & 3713 vcpu->arch.guest_supported_xcr0)) 3714 return 1; 3715 3716 vcpu->arch.guest_fpu.xfd_err = data; 3717 break; 3718 #endif 3719 default: 3720 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3721 return kvm_pmu_set_msr(vcpu, msr_info); 3722 return KVM_MSR_RET_INVALID; 3723 } 3724 return 0; 3725 } 3726 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 3727 3728 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 3729 { 3730 u64 data; 3731 u64 mcg_cap = vcpu->arch.mcg_cap; 3732 unsigned bank_num = mcg_cap & 0xff; 3733 3734 switch (msr) { 3735 case MSR_IA32_P5_MC_ADDR: 3736 case MSR_IA32_P5_MC_TYPE: 3737 data = 0; 3738 break; 3739 case MSR_IA32_MCG_CAP: 3740 data = vcpu->arch.mcg_cap; 3741 break; 3742 case MSR_IA32_MCG_CTL: 3743 if (!(mcg_cap & MCG_CTL_P) && !host) 3744 return 1; 3745 data = vcpu->arch.mcg_ctl; 3746 break; 3747 case MSR_IA32_MCG_STATUS: 3748 data = vcpu->arch.mcg_status; 3749 break; 3750 default: 3751 if (msr >= MSR_IA32_MC0_CTL && 3752 msr < MSR_IA32_MCx_CTL(bank_num)) { 3753 u32 offset = array_index_nospec( 3754 msr - MSR_IA32_MC0_CTL, 3755 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3756 3757 data = vcpu->arch.mce_banks[offset]; 3758 break; 3759 } 3760 return 1; 3761 } 3762 *pdata = data; 3763 return 0; 3764 } 3765 3766 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3767 { 3768 switch (msr_info->index) { 3769 case MSR_IA32_PLATFORM_ID: 3770 case MSR_IA32_EBL_CR_POWERON: 3771 case MSR_IA32_LASTBRANCHFROMIP: 3772 case MSR_IA32_LASTBRANCHTOIP: 3773 case MSR_IA32_LASTINTFROMIP: 3774 case MSR_IA32_LASTINTTOIP: 3775 case MSR_AMD64_SYSCFG: 3776 case MSR_K8_TSEG_ADDR: 3777 case MSR_K8_TSEG_MASK: 3778 case MSR_VM_HSAVE_PA: 3779 case MSR_K8_INT_PENDING_MSG: 3780 case MSR_AMD64_NB_CFG: 3781 case MSR_FAM10H_MMIO_CONF_BASE: 3782 case MSR_AMD64_BU_CFG2: 3783 case MSR_IA32_PERF_CTL: 3784 case MSR_AMD64_DC_CFG: 3785 case MSR_F15H_EX_CFG: 3786 /* 3787 * Intel Sandy Bridge CPUs must support the RAPL (running average power 3788 * limit) MSRs. Just return 0, as we do not want to expose the host 3789 * data here. Do not conditionalize this on CPUID, as KVM does not do 3790 * so for existing CPU-specific MSRs. 3791 */ 3792 case MSR_RAPL_POWER_UNIT: 3793 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ 3794 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ 3795 case MSR_PKG_ENERGY_STATUS: /* Total package */ 3796 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ 3797 msr_info->data = 0; 3798 break; 3799 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3800 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3801 return kvm_pmu_get_msr(vcpu, msr_info); 3802 if (!msr_info->host_initiated) 3803 return 1; 3804 msr_info->data = 0; 3805 break; 3806 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3807 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3808 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3809 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3810 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3811 return kvm_pmu_get_msr(vcpu, msr_info); 3812 msr_info->data = 0; 3813 break; 3814 case MSR_IA32_UCODE_REV: 3815 msr_info->data = vcpu->arch.microcode_version; 3816 break; 3817 case MSR_IA32_ARCH_CAPABILITIES: 3818 if (!msr_info->host_initiated && 3819 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 3820 return 1; 3821 msr_info->data = vcpu->arch.arch_capabilities; 3822 break; 3823 case MSR_IA32_PERF_CAPABILITIES: 3824 if (!msr_info->host_initiated && 3825 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) 3826 return 1; 3827 msr_info->data = vcpu->arch.perf_capabilities; 3828 break; 3829 case MSR_IA32_POWER_CTL: 3830 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 3831 break; 3832 case MSR_IA32_TSC: { 3833 /* 3834 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset 3835 * even when not intercepted. AMD manual doesn't explicitly 3836 * state this but appears to behave the same. 3837 * 3838 * On userspace reads and writes, however, we unconditionally 3839 * return L1's TSC value to ensure backwards-compatible 3840 * behavior for migration. 3841 */ 3842 u64 offset, ratio; 3843 3844 if (msr_info->host_initiated) { 3845 offset = vcpu->arch.l1_tsc_offset; 3846 ratio = vcpu->arch.l1_tsc_scaling_ratio; 3847 } else { 3848 offset = vcpu->arch.tsc_offset; 3849 ratio = vcpu->arch.tsc_scaling_ratio; 3850 } 3851 3852 msr_info->data = kvm_scale_tsc(vcpu, rdtsc(), ratio) + offset; 3853 break; 3854 } 3855 case MSR_MTRRcap: 3856 case 0x200 ... 0x2ff: 3857 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 3858 case 0xcd: /* fsb frequency */ 3859 msr_info->data = 3; 3860 break; 3861 /* 3862 * MSR_EBC_FREQUENCY_ID 3863 * Conservative value valid for even the basic CPU models. 3864 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 3865 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 3866 * and 266MHz for model 3, or 4. Set Core Clock 3867 * Frequency to System Bus Frequency Ratio to 1 (bits 3868 * 31:24) even though these are only valid for CPU 3869 * models > 2, however guests may end up dividing or 3870 * multiplying by zero otherwise. 3871 */ 3872 case MSR_EBC_FREQUENCY_ID: 3873 msr_info->data = 1 << 24; 3874 break; 3875 case MSR_IA32_APICBASE: 3876 msr_info->data = kvm_get_apic_base(vcpu); 3877 break; 3878 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3879 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 3880 case MSR_IA32_TSC_DEADLINE: 3881 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 3882 break; 3883 case MSR_IA32_TSC_ADJUST: 3884 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 3885 break; 3886 case MSR_IA32_MISC_ENABLE: 3887 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 3888 break; 3889 case MSR_IA32_SMBASE: 3890 if (!msr_info->host_initiated) 3891 return 1; 3892 msr_info->data = vcpu->arch.smbase; 3893 break; 3894 case MSR_SMI_COUNT: 3895 msr_info->data = vcpu->arch.smi_count; 3896 break; 3897 case MSR_IA32_PERF_STATUS: 3898 /* TSC increment by tick */ 3899 msr_info->data = 1000ULL; 3900 /* CPU multiplier */ 3901 msr_info->data |= (((uint64_t)4ULL) << 40); 3902 break; 3903 case MSR_EFER: 3904 msr_info->data = vcpu->arch.efer; 3905 break; 3906 case MSR_KVM_WALL_CLOCK: 3907 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3908 return 1; 3909 3910 msr_info->data = vcpu->kvm->arch.wall_clock; 3911 break; 3912 case MSR_KVM_WALL_CLOCK_NEW: 3913 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3914 return 1; 3915 3916 msr_info->data = vcpu->kvm->arch.wall_clock; 3917 break; 3918 case MSR_KVM_SYSTEM_TIME: 3919 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3920 return 1; 3921 3922 msr_info->data = vcpu->arch.time; 3923 break; 3924 case MSR_KVM_SYSTEM_TIME_NEW: 3925 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3926 return 1; 3927 3928 msr_info->data = vcpu->arch.time; 3929 break; 3930 case MSR_KVM_ASYNC_PF_EN: 3931 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3932 return 1; 3933 3934 msr_info->data = vcpu->arch.apf.msr_en_val; 3935 break; 3936 case MSR_KVM_ASYNC_PF_INT: 3937 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3938 return 1; 3939 3940 msr_info->data = vcpu->arch.apf.msr_int_val; 3941 break; 3942 case MSR_KVM_ASYNC_PF_ACK: 3943 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3944 return 1; 3945 3946 msr_info->data = 0; 3947 break; 3948 case MSR_KVM_STEAL_TIME: 3949 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3950 return 1; 3951 3952 msr_info->data = vcpu->arch.st.msr_val; 3953 break; 3954 case MSR_KVM_PV_EOI_EN: 3955 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3956 return 1; 3957 3958 msr_info->data = vcpu->arch.pv_eoi.msr_val; 3959 break; 3960 case MSR_KVM_POLL_CONTROL: 3961 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3962 return 1; 3963 3964 msr_info->data = vcpu->arch.msr_kvm_poll_control; 3965 break; 3966 case MSR_IA32_P5_MC_ADDR: 3967 case MSR_IA32_P5_MC_TYPE: 3968 case MSR_IA32_MCG_CAP: 3969 case MSR_IA32_MCG_CTL: 3970 case MSR_IA32_MCG_STATUS: 3971 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3972 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 3973 msr_info->host_initiated); 3974 case MSR_IA32_XSS: 3975 if (!msr_info->host_initiated && 3976 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3977 return 1; 3978 msr_info->data = vcpu->arch.ia32_xss; 3979 break; 3980 case MSR_K7_CLK_CTL: 3981 /* 3982 * Provide expected ramp-up count for K7. All other 3983 * are set to zero, indicating minimum divisors for 3984 * every field. 3985 * 3986 * This prevents guest kernels on AMD host with CPU 3987 * type 6, model 8 and higher from exploding due to 3988 * the rdmsr failing. 3989 */ 3990 msr_info->data = 0x20000000; 3991 break; 3992 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3993 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3994 case HV_X64_MSR_SYNDBG_OPTIONS: 3995 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3996 case HV_X64_MSR_CRASH_CTL: 3997 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3998 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3999 case HV_X64_MSR_TSC_EMULATION_CONTROL: 4000 case HV_X64_MSR_TSC_EMULATION_STATUS: 4001 return kvm_hv_get_msr_common(vcpu, 4002 msr_info->index, &msr_info->data, 4003 msr_info->host_initiated); 4004 case MSR_IA32_BBL_CR_CTL3: 4005 /* This legacy MSR exists but isn't fully documented in current 4006 * silicon. It is however accessed by winxp in very narrow 4007 * scenarios where it sets bit #19, itself documented as 4008 * a "reserved" bit. Best effort attempt to source coherent 4009 * read data here should the balance of the register be 4010 * interpreted by the guest: 4011 * 4012 * L2 cache control register 3: 64GB range, 256KB size, 4013 * enabled, latency 0x1, configured 4014 */ 4015 msr_info->data = 0xbe702111; 4016 break; 4017 case MSR_AMD64_OSVW_ID_LENGTH: 4018 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 4019 return 1; 4020 msr_info->data = vcpu->arch.osvw.length; 4021 break; 4022 case MSR_AMD64_OSVW_STATUS: 4023 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 4024 return 1; 4025 msr_info->data = vcpu->arch.osvw.status; 4026 break; 4027 case MSR_PLATFORM_INFO: 4028 if (!msr_info->host_initiated && 4029 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 4030 return 1; 4031 msr_info->data = vcpu->arch.msr_platform_info; 4032 break; 4033 case MSR_MISC_FEATURES_ENABLES: 4034 msr_info->data = vcpu->arch.msr_misc_features_enables; 4035 break; 4036 case MSR_K7_HWCR: 4037 msr_info->data = vcpu->arch.msr_hwcr; 4038 break; 4039 #ifdef CONFIG_X86_64 4040 case MSR_IA32_XFD: 4041 if (!msr_info->host_initiated && 4042 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 4043 return 1; 4044 4045 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd; 4046 break; 4047 case MSR_IA32_XFD_ERR: 4048 if (!msr_info->host_initiated && 4049 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 4050 return 1; 4051 4052 msr_info->data = vcpu->arch.guest_fpu.xfd_err; 4053 break; 4054 #endif 4055 default: 4056 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 4057 return kvm_pmu_get_msr(vcpu, msr_info); 4058 return KVM_MSR_RET_INVALID; 4059 } 4060 return 0; 4061 } 4062 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 4063 4064 /* 4065 * Read or write a bunch of msrs. All parameters are kernel addresses. 4066 * 4067 * @return number of msrs set successfully. 4068 */ 4069 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 4070 struct kvm_msr_entry *entries, 4071 int (*do_msr)(struct kvm_vcpu *vcpu, 4072 unsigned index, u64 *data)) 4073 { 4074 int i; 4075 4076 for (i = 0; i < msrs->nmsrs; ++i) 4077 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 4078 break; 4079 4080 return i; 4081 } 4082 4083 /* 4084 * Read or write a bunch of msrs. Parameters are user addresses. 4085 * 4086 * @return number of msrs set successfully. 4087 */ 4088 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 4089 int (*do_msr)(struct kvm_vcpu *vcpu, 4090 unsigned index, u64 *data), 4091 int writeback) 4092 { 4093 struct kvm_msrs msrs; 4094 struct kvm_msr_entry *entries; 4095 int r, n; 4096 unsigned size; 4097 4098 r = -EFAULT; 4099 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 4100 goto out; 4101 4102 r = -E2BIG; 4103 if (msrs.nmsrs >= MAX_IO_MSRS) 4104 goto out; 4105 4106 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 4107 entries = memdup_user(user_msrs->entries, size); 4108 if (IS_ERR(entries)) { 4109 r = PTR_ERR(entries); 4110 goto out; 4111 } 4112 4113 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 4114 if (r < 0) 4115 goto out_free; 4116 4117 r = -EFAULT; 4118 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 4119 goto out_free; 4120 4121 r = n; 4122 4123 out_free: 4124 kfree(entries); 4125 out: 4126 return r; 4127 } 4128 4129 static inline bool kvm_can_mwait_in_guest(void) 4130 { 4131 return boot_cpu_has(X86_FEATURE_MWAIT) && 4132 !boot_cpu_has_bug(X86_BUG_MONITOR) && 4133 boot_cpu_has(X86_FEATURE_ARAT); 4134 } 4135 4136 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, 4137 struct kvm_cpuid2 __user *cpuid_arg) 4138 { 4139 struct kvm_cpuid2 cpuid; 4140 int r; 4141 4142 r = -EFAULT; 4143 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4144 return r; 4145 4146 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); 4147 if (r) 4148 return r; 4149 4150 r = -EFAULT; 4151 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4152 return r; 4153 4154 return 0; 4155 } 4156 4157 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 4158 { 4159 int r = 0; 4160 4161 switch (ext) { 4162 case KVM_CAP_IRQCHIP: 4163 case KVM_CAP_HLT: 4164 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 4165 case KVM_CAP_SET_TSS_ADDR: 4166 case KVM_CAP_EXT_CPUID: 4167 case KVM_CAP_EXT_EMUL_CPUID: 4168 case KVM_CAP_CLOCKSOURCE: 4169 case KVM_CAP_PIT: 4170 case KVM_CAP_NOP_IO_DELAY: 4171 case KVM_CAP_MP_STATE: 4172 case KVM_CAP_SYNC_MMU: 4173 case KVM_CAP_USER_NMI: 4174 case KVM_CAP_REINJECT_CONTROL: 4175 case KVM_CAP_IRQ_INJECT_STATUS: 4176 case KVM_CAP_IOEVENTFD: 4177 case KVM_CAP_IOEVENTFD_NO_LENGTH: 4178 case KVM_CAP_PIT2: 4179 case KVM_CAP_PIT_STATE2: 4180 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 4181 case KVM_CAP_VCPU_EVENTS: 4182 case KVM_CAP_HYPERV: 4183 case KVM_CAP_HYPERV_VAPIC: 4184 case KVM_CAP_HYPERV_SPIN: 4185 case KVM_CAP_HYPERV_SYNIC: 4186 case KVM_CAP_HYPERV_SYNIC2: 4187 case KVM_CAP_HYPERV_VP_INDEX: 4188 case KVM_CAP_HYPERV_EVENTFD: 4189 case KVM_CAP_HYPERV_TLBFLUSH: 4190 case KVM_CAP_HYPERV_SEND_IPI: 4191 case KVM_CAP_HYPERV_CPUID: 4192 case KVM_CAP_HYPERV_ENFORCE_CPUID: 4193 case KVM_CAP_SYS_HYPERV_CPUID: 4194 case KVM_CAP_PCI_SEGMENT: 4195 case KVM_CAP_DEBUGREGS: 4196 case KVM_CAP_X86_ROBUST_SINGLESTEP: 4197 case KVM_CAP_XSAVE: 4198 case KVM_CAP_ASYNC_PF: 4199 case KVM_CAP_ASYNC_PF_INT: 4200 case KVM_CAP_GET_TSC_KHZ: 4201 case KVM_CAP_KVMCLOCK_CTRL: 4202 case KVM_CAP_READONLY_MEM: 4203 case KVM_CAP_HYPERV_TIME: 4204 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 4205 case KVM_CAP_TSC_DEADLINE_TIMER: 4206 case KVM_CAP_DISABLE_QUIRKS: 4207 case KVM_CAP_SET_BOOT_CPU_ID: 4208 case KVM_CAP_SPLIT_IRQCHIP: 4209 case KVM_CAP_IMMEDIATE_EXIT: 4210 case KVM_CAP_PMU_EVENT_FILTER: 4211 case KVM_CAP_GET_MSR_FEATURES: 4212 case KVM_CAP_MSR_PLATFORM_INFO: 4213 case KVM_CAP_EXCEPTION_PAYLOAD: 4214 case KVM_CAP_SET_GUEST_DEBUG: 4215 case KVM_CAP_LAST_CPU: 4216 case KVM_CAP_X86_USER_SPACE_MSR: 4217 case KVM_CAP_X86_MSR_FILTER: 4218 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 4219 #ifdef CONFIG_X86_SGX_KVM 4220 case KVM_CAP_SGX_ATTRIBUTE: 4221 #endif 4222 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 4223 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: 4224 case KVM_CAP_SREGS2: 4225 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 4226 case KVM_CAP_VCPU_ATTRIBUTES: 4227 r = 1; 4228 break; 4229 case KVM_CAP_EXIT_HYPERCALL: 4230 r = KVM_EXIT_HYPERCALL_VALID_MASK; 4231 break; 4232 case KVM_CAP_SET_GUEST_DEBUG2: 4233 return KVM_GUESTDBG_VALID_MASK; 4234 #ifdef CONFIG_KVM_XEN 4235 case KVM_CAP_XEN_HVM: 4236 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | 4237 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | 4238 KVM_XEN_HVM_CONFIG_SHARED_INFO | 4239 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL; 4240 if (sched_info_on()) 4241 r |= KVM_XEN_HVM_CONFIG_RUNSTATE; 4242 break; 4243 #endif 4244 case KVM_CAP_SYNC_REGS: 4245 r = KVM_SYNC_X86_VALID_FIELDS; 4246 break; 4247 case KVM_CAP_ADJUST_CLOCK: 4248 r = KVM_CLOCK_VALID_FLAGS; 4249 break; 4250 case KVM_CAP_X86_DISABLE_EXITS: 4251 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | 4252 KVM_X86_DISABLE_EXITS_CSTATE; 4253 if(kvm_can_mwait_in_guest()) 4254 r |= KVM_X86_DISABLE_EXITS_MWAIT; 4255 break; 4256 case KVM_CAP_X86_SMM: 4257 /* SMBASE is usually relocated above 1M on modern chipsets, 4258 * and SMM handlers might indeed rely on 4G segment limits, 4259 * so do not report SMM to be available if real mode is 4260 * emulated via vm86 mode. Still, do not go to great lengths 4261 * to avoid userspace's usage of the feature, because it is a 4262 * fringe case that is not enabled except via specific settings 4263 * of the module parameters. 4264 */ 4265 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); 4266 break; 4267 case KVM_CAP_VAPIC: 4268 r = !static_call(kvm_x86_cpu_has_accelerated_tpr)(); 4269 break; 4270 case KVM_CAP_NR_VCPUS: 4271 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS); 4272 break; 4273 case KVM_CAP_MAX_VCPUS: 4274 r = KVM_MAX_VCPUS; 4275 break; 4276 case KVM_CAP_MAX_VCPU_ID: 4277 r = KVM_MAX_VCPU_IDS; 4278 break; 4279 case KVM_CAP_PV_MMU: /* obsolete */ 4280 r = 0; 4281 break; 4282 case KVM_CAP_MCE: 4283 r = KVM_MAX_MCE_BANKS; 4284 break; 4285 case KVM_CAP_XCRS: 4286 r = boot_cpu_has(X86_FEATURE_XSAVE); 4287 break; 4288 case KVM_CAP_TSC_CONTROL: 4289 r = kvm_has_tsc_control; 4290 break; 4291 case KVM_CAP_X2APIC_API: 4292 r = KVM_X2APIC_API_VALID_FLAGS; 4293 break; 4294 case KVM_CAP_NESTED_STATE: 4295 r = kvm_x86_ops.nested_ops->get_state ? 4296 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; 4297 break; 4298 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4299 r = kvm_x86_ops.enable_direct_tlbflush != NULL; 4300 break; 4301 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4302 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; 4303 break; 4304 case KVM_CAP_SMALLER_MAXPHYADDR: 4305 r = (int) allow_smaller_maxphyaddr; 4306 break; 4307 case KVM_CAP_STEAL_TIME: 4308 r = sched_info_on(); 4309 break; 4310 case KVM_CAP_X86_BUS_LOCK_EXIT: 4311 if (kvm_has_bus_lock_exit) 4312 r = KVM_BUS_LOCK_DETECTION_OFF | 4313 KVM_BUS_LOCK_DETECTION_EXIT; 4314 else 4315 r = 0; 4316 break; 4317 case KVM_CAP_XSAVE2: { 4318 u64 guest_perm = xstate_get_guest_group_perm(); 4319 4320 r = xstate_required_size(supported_xcr0 & guest_perm, false); 4321 if (r < sizeof(struct kvm_xsave)) 4322 r = sizeof(struct kvm_xsave); 4323 break; 4324 } 4325 default: 4326 break; 4327 } 4328 return r; 4329 4330 } 4331 4332 long kvm_arch_dev_ioctl(struct file *filp, 4333 unsigned int ioctl, unsigned long arg) 4334 { 4335 void __user *argp = (void __user *)arg; 4336 long r; 4337 4338 switch (ioctl) { 4339 case KVM_GET_MSR_INDEX_LIST: { 4340 struct kvm_msr_list __user *user_msr_list = argp; 4341 struct kvm_msr_list msr_list; 4342 unsigned n; 4343 4344 r = -EFAULT; 4345 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4346 goto out; 4347 n = msr_list.nmsrs; 4348 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 4349 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4350 goto out; 4351 r = -E2BIG; 4352 if (n < msr_list.nmsrs) 4353 goto out; 4354 r = -EFAULT; 4355 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 4356 num_msrs_to_save * sizeof(u32))) 4357 goto out; 4358 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 4359 &emulated_msrs, 4360 num_emulated_msrs * sizeof(u32))) 4361 goto out; 4362 r = 0; 4363 break; 4364 } 4365 case KVM_GET_SUPPORTED_CPUID: 4366 case KVM_GET_EMULATED_CPUID: { 4367 struct kvm_cpuid2 __user *cpuid_arg = argp; 4368 struct kvm_cpuid2 cpuid; 4369 4370 r = -EFAULT; 4371 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4372 goto out; 4373 4374 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 4375 ioctl); 4376 if (r) 4377 goto out; 4378 4379 r = -EFAULT; 4380 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4381 goto out; 4382 r = 0; 4383 break; 4384 } 4385 case KVM_X86_GET_MCE_CAP_SUPPORTED: 4386 r = -EFAULT; 4387 if (copy_to_user(argp, &kvm_mce_cap_supported, 4388 sizeof(kvm_mce_cap_supported))) 4389 goto out; 4390 r = 0; 4391 break; 4392 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 4393 struct kvm_msr_list __user *user_msr_list = argp; 4394 struct kvm_msr_list msr_list; 4395 unsigned int n; 4396 4397 r = -EFAULT; 4398 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4399 goto out; 4400 n = msr_list.nmsrs; 4401 msr_list.nmsrs = num_msr_based_features; 4402 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4403 goto out; 4404 r = -E2BIG; 4405 if (n < msr_list.nmsrs) 4406 goto out; 4407 r = -EFAULT; 4408 if (copy_to_user(user_msr_list->indices, &msr_based_features, 4409 num_msr_based_features * sizeof(u32))) 4410 goto out; 4411 r = 0; 4412 break; 4413 } 4414 case KVM_GET_MSRS: 4415 r = msr_io(NULL, argp, do_get_msr_feature, 1); 4416 break; 4417 case KVM_GET_SUPPORTED_HV_CPUID: 4418 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); 4419 break; 4420 default: 4421 r = -EINVAL; 4422 break; 4423 } 4424 out: 4425 return r; 4426 } 4427 4428 static void wbinvd_ipi(void *garbage) 4429 { 4430 wbinvd(); 4431 } 4432 4433 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 4434 { 4435 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 4436 } 4437 4438 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 4439 { 4440 /* Address WBINVD may be executed by guest */ 4441 if (need_emulate_wbinvd(vcpu)) { 4442 if (static_call(kvm_x86_has_wbinvd_exit)()) 4443 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4444 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 4445 smp_call_function_single(vcpu->cpu, 4446 wbinvd_ipi, NULL, 1); 4447 } 4448 4449 static_call(kvm_x86_vcpu_load)(vcpu, cpu); 4450 4451 /* Save host pkru register if supported */ 4452 vcpu->arch.host_pkru = read_pkru(); 4453 4454 /* Apply any externally detected TSC adjustments (due to suspend) */ 4455 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 4456 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 4457 vcpu->arch.tsc_offset_adjustment = 0; 4458 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4459 } 4460 4461 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 4462 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 4463 rdtsc() - vcpu->arch.last_host_tsc; 4464 if (tsc_delta < 0) 4465 mark_tsc_unstable("KVM discovered backwards TSC"); 4466 4467 if (kvm_check_tsc_unstable()) { 4468 u64 offset = kvm_compute_l1_tsc_offset(vcpu, 4469 vcpu->arch.last_guest_tsc); 4470 kvm_vcpu_write_tsc_offset(vcpu, offset); 4471 vcpu->arch.tsc_catchup = 1; 4472 } 4473 4474 if (kvm_lapic_hv_timer_in_use(vcpu)) 4475 kvm_lapic_restart_hv_timer(vcpu); 4476 4477 /* 4478 * On a host with synchronized TSC, there is no need to update 4479 * kvmclock on vcpu->cpu migration 4480 */ 4481 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 4482 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 4483 if (vcpu->cpu != cpu) 4484 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 4485 vcpu->cpu = cpu; 4486 } 4487 4488 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 4489 } 4490 4491 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 4492 { 4493 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; 4494 struct kvm_steal_time __user *st; 4495 struct kvm_memslots *slots; 4496 static const u8 preempted = KVM_VCPU_PREEMPTED; 4497 4498 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 4499 return; 4500 4501 if (vcpu->arch.st.preempted) 4502 return; 4503 4504 /* This happens on process exit */ 4505 if (unlikely(current->mm != vcpu->kvm->mm)) 4506 return; 4507 4508 slots = kvm_memslots(vcpu->kvm); 4509 4510 if (unlikely(slots->generation != ghc->generation || 4511 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) 4512 return; 4513 4514 st = (struct kvm_steal_time __user *)ghc->hva; 4515 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted)); 4516 4517 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted))) 4518 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 4519 4520 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 4521 } 4522 4523 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 4524 { 4525 int idx; 4526 4527 if (vcpu->preempted && !vcpu->arch.guest_state_protected) 4528 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); 4529 4530 /* 4531 * Take the srcu lock as memslots will be accessed to check the gfn 4532 * cache generation against the memslots generation. 4533 */ 4534 idx = srcu_read_lock(&vcpu->kvm->srcu); 4535 if (kvm_xen_msr_enabled(vcpu->kvm)) 4536 kvm_xen_runstate_set_preempted(vcpu); 4537 else 4538 kvm_steal_time_set_preempted(vcpu); 4539 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4540 4541 static_call(kvm_x86_vcpu_put)(vcpu); 4542 vcpu->arch.last_host_tsc = rdtsc(); 4543 } 4544 4545 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 4546 struct kvm_lapic_state *s) 4547 { 4548 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 4549 4550 return kvm_apic_get_state(vcpu, s); 4551 } 4552 4553 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 4554 struct kvm_lapic_state *s) 4555 { 4556 int r; 4557 4558 r = kvm_apic_set_state(vcpu, s); 4559 if (r) 4560 return r; 4561 update_cr8_intercept(vcpu); 4562 4563 return 0; 4564 } 4565 4566 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 4567 { 4568 /* 4569 * We can accept userspace's request for interrupt injection 4570 * as long as we have a place to store the interrupt number. 4571 * The actual injection will happen when the CPU is able to 4572 * deliver the interrupt. 4573 */ 4574 if (kvm_cpu_has_extint(vcpu)) 4575 return false; 4576 4577 /* Acknowledging ExtINT does not happen if LINT0 is masked. */ 4578 return (!lapic_in_kernel(vcpu) || 4579 kvm_apic_accept_pic_intr(vcpu)); 4580 } 4581 4582 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 4583 { 4584 /* 4585 * Do not cause an interrupt window exit if an exception 4586 * is pending or an event needs reinjection; userspace 4587 * might want to inject the interrupt manually using KVM_SET_REGS 4588 * or KVM_SET_SREGS. For that to work, we must be at an 4589 * instruction boundary and with no events half-injected. 4590 */ 4591 return (kvm_arch_interrupt_allowed(vcpu) && 4592 kvm_cpu_accept_dm_intr(vcpu) && 4593 !kvm_event_needs_reinjection(vcpu) && 4594 !vcpu->arch.exception.pending); 4595 } 4596 4597 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 4598 struct kvm_interrupt *irq) 4599 { 4600 if (irq->irq >= KVM_NR_INTERRUPTS) 4601 return -EINVAL; 4602 4603 if (!irqchip_in_kernel(vcpu->kvm)) { 4604 kvm_queue_interrupt(vcpu, irq->irq, false); 4605 kvm_make_request(KVM_REQ_EVENT, vcpu); 4606 return 0; 4607 } 4608 4609 /* 4610 * With in-kernel LAPIC, we only use this to inject EXTINT, so 4611 * fail for in-kernel 8259. 4612 */ 4613 if (pic_in_kernel(vcpu->kvm)) 4614 return -ENXIO; 4615 4616 if (vcpu->arch.pending_external_vector != -1) 4617 return -EEXIST; 4618 4619 vcpu->arch.pending_external_vector = irq->irq; 4620 kvm_make_request(KVM_REQ_EVENT, vcpu); 4621 return 0; 4622 } 4623 4624 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 4625 { 4626 kvm_inject_nmi(vcpu); 4627 4628 return 0; 4629 } 4630 4631 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 4632 { 4633 kvm_make_request(KVM_REQ_SMI, vcpu); 4634 4635 return 0; 4636 } 4637 4638 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 4639 struct kvm_tpr_access_ctl *tac) 4640 { 4641 if (tac->flags) 4642 return -EINVAL; 4643 vcpu->arch.tpr_access_reporting = !!tac->enabled; 4644 return 0; 4645 } 4646 4647 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 4648 u64 mcg_cap) 4649 { 4650 int r; 4651 unsigned bank_num = mcg_cap & 0xff, bank; 4652 4653 r = -EINVAL; 4654 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) 4655 goto out; 4656 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 4657 goto out; 4658 r = 0; 4659 vcpu->arch.mcg_cap = mcg_cap; 4660 /* Init IA32_MCG_CTL to all 1s */ 4661 if (mcg_cap & MCG_CTL_P) 4662 vcpu->arch.mcg_ctl = ~(u64)0; 4663 /* Init IA32_MCi_CTL to all 1s */ 4664 for (bank = 0; bank < bank_num; bank++) 4665 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 4666 4667 static_call(kvm_x86_setup_mce)(vcpu); 4668 out: 4669 return r; 4670 } 4671 4672 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 4673 struct kvm_x86_mce *mce) 4674 { 4675 u64 mcg_cap = vcpu->arch.mcg_cap; 4676 unsigned bank_num = mcg_cap & 0xff; 4677 u64 *banks = vcpu->arch.mce_banks; 4678 4679 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 4680 return -EINVAL; 4681 /* 4682 * if IA32_MCG_CTL is not all 1s, the uncorrected error 4683 * reporting is disabled 4684 */ 4685 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 4686 vcpu->arch.mcg_ctl != ~(u64)0) 4687 return 0; 4688 banks += 4 * mce->bank; 4689 /* 4690 * if IA32_MCi_CTL is not all 1s, the uncorrected error 4691 * reporting is disabled for the bank 4692 */ 4693 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 4694 return 0; 4695 if (mce->status & MCI_STATUS_UC) { 4696 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 4697 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 4698 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 4699 return 0; 4700 } 4701 if (banks[1] & MCI_STATUS_VAL) 4702 mce->status |= MCI_STATUS_OVER; 4703 banks[2] = mce->addr; 4704 banks[3] = mce->misc; 4705 vcpu->arch.mcg_status = mce->mcg_status; 4706 banks[1] = mce->status; 4707 kvm_queue_exception(vcpu, MC_VECTOR); 4708 } else if (!(banks[1] & MCI_STATUS_VAL) 4709 || !(banks[1] & MCI_STATUS_UC)) { 4710 if (banks[1] & MCI_STATUS_VAL) 4711 mce->status |= MCI_STATUS_OVER; 4712 banks[2] = mce->addr; 4713 banks[3] = mce->misc; 4714 banks[1] = mce->status; 4715 } else 4716 banks[1] |= MCI_STATUS_OVER; 4717 return 0; 4718 } 4719 4720 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 4721 struct kvm_vcpu_events *events) 4722 { 4723 process_nmi(vcpu); 4724 4725 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 4726 process_smi(vcpu); 4727 4728 /* 4729 * In guest mode, payload delivery should be deferred, 4730 * so that the L1 hypervisor can intercept #PF before 4731 * CR2 is modified (or intercept #DB before DR6 is 4732 * modified under nVMX). Unless the per-VM capability, 4733 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of 4734 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we 4735 * opportunistically defer the exception payload, deliver it if the 4736 * capability hasn't been requested before processing a 4737 * KVM_GET_VCPU_EVENTS. 4738 */ 4739 if (!vcpu->kvm->arch.exception_payload_enabled && 4740 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) 4741 kvm_deliver_exception_payload(vcpu); 4742 4743 /* 4744 * The API doesn't provide the instruction length for software 4745 * exceptions, so don't report them. As long as the guest RIP 4746 * isn't advanced, we should expect to encounter the exception 4747 * again. 4748 */ 4749 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 4750 events->exception.injected = 0; 4751 events->exception.pending = 0; 4752 } else { 4753 events->exception.injected = vcpu->arch.exception.injected; 4754 events->exception.pending = vcpu->arch.exception.pending; 4755 /* 4756 * For ABI compatibility, deliberately conflate 4757 * pending and injected exceptions when 4758 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 4759 */ 4760 if (!vcpu->kvm->arch.exception_payload_enabled) 4761 events->exception.injected |= 4762 vcpu->arch.exception.pending; 4763 } 4764 events->exception.nr = vcpu->arch.exception.nr; 4765 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 4766 events->exception.error_code = vcpu->arch.exception.error_code; 4767 events->exception_has_payload = vcpu->arch.exception.has_payload; 4768 events->exception_payload = vcpu->arch.exception.payload; 4769 4770 events->interrupt.injected = 4771 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 4772 events->interrupt.nr = vcpu->arch.interrupt.nr; 4773 events->interrupt.soft = 0; 4774 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 4775 4776 events->nmi.injected = vcpu->arch.nmi_injected; 4777 events->nmi.pending = vcpu->arch.nmi_pending != 0; 4778 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); 4779 events->nmi.pad = 0; 4780 4781 events->sipi_vector = 0; /* never valid when reporting to user space */ 4782 4783 events->smi.smm = is_smm(vcpu); 4784 events->smi.pending = vcpu->arch.smi_pending; 4785 events->smi.smm_inside_nmi = 4786 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 4787 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 4788 4789 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 4790 | KVM_VCPUEVENT_VALID_SHADOW 4791 | KVM_VCPUEVENT_VALID_SMM); 4792 if (vcpu->kvm->arch.exception_payload_enabled) 4793 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 4794 4795 memset(&events->reserved, 0, sizeof(events->reserved)); 4796 } 4797 4798 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm); 4799 4800 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 4801 struct kvm_vcpu_events *events) 4802 { 4803 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 4804 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 4805 | KVM_VCPUEVENT_VALID_SHADOW 4806 | KVM_VCPUEVENT_VALID_SMM 4807 | KVM_VCPUEVENT_VALID_PAYLOAD)) 4808 return -EINVAL; 4809 4810 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 4811 if (!vcpu->kvm->arch.exception_payload_enabled) 4812 return -EINVAL; 4813 if (events->exception.pending) 4814 events->exception.injected = 0; 4815 else 4816 events->exception_has_payload = 0; 4817 } else { 4818 events->exception.pending = 0; 4819 events->exception_has_payload = 0; 4820 } 4821 4822 if ((events->exception.injected || events->exception.pending) && 4823 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 4824 return -EINVAL; 4825 4826 /* INITs are latched while in SMM */ 4827 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 4828 (events->smi.smm || events->smi.pending) && 4829 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 4830 return -EINVAL; 4831 4832 process_nmi(vcpu); 4833 vcpu->arch.exception.injected = events->exception.injected; 4834 vcpu->arch.exception.pending = events->exception.pending; 4835 vcpu->arch.exception.nr = events->exception.nr; 4836 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 4837 vcpu->arch.exception.error_code = events->exception.error_code; 4838 vcpu->arch.exception.has_payload = events->exception_has_payload; 4839 vcpu->arch.exception.payload = events->exception_payload; 4840 4841 vcpu->arch.interrupt.injected = events->interrupt.injected; 4842 vcpu->arch.interrupt.nr = events->interrupt.nr; 4843 vcpu->arch.interrupt.soft = events->interrupt.soft; 4844 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 4845 static_call(kvm_x86_set_interrupt_shadow)(vcpu, 4846 events->interrupt.shadow); 4847 4848 vcpu->arch.nmi_injected = events->nmi.injected; 4849 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 4850 vcpu->arch.nmi_pending = events->nmi.pending; 4851 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); 4852 4853 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 4854 lapic_in_kernel(vcpu)) 4855 vcpu->arch.apic->sipi_vector = events->sipi_vector; 4856 4857 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 4858 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) 4859 kvm_smm_changed(vcpu, events->smi.smm); 4860 4861 vcpu->arch.smi_pending = events->smi.pending; 4862 4863 if (events->smi.smm) { 4864 if (events->smi.smm_inside_nmi) 4865 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 4866 else 4867 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 4868 } 4869 4870 if (lapic_in_kernel(vcpu)) { 4871 if (events->smi.latched_init) 4872 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4873 else 4874 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4875 } 4876 } 4877 4878 kvm_make_request(KVM_REQ_EVENT, vcpu); 4879 4880 return 0; 4881 } 4882 4883 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 4884 struct kvm_debugregs *dbgregs) 4885 { 4886 unsigned long val; 4887 4888 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 4889 kvm_get_dr(vcpu, 6, &val); 4890 dbgregs->dr6 = val; 4891 dbgregs->dr7 = vcpu->arch.dr7; 4892 dbgregs->flags = 0; 4893 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 4894 } 4895 4896 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 4897 struct kvm_debugregs *dbgregs) 4898 { 4899 if (dbgregs->flags) 4900 return -EINVAL; 4901 4902 if (!kvm_dr6_valid(dbgregs->dr6)) 4903 return -EINVAL; 4904 if (!kvm_dr7_valid(dbgregs->dr7)) 4905 return -EINVAL; 4906 4907 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 4908 kvm_update_dr0123(vcpu); 4909 vcpu->arch.dr6 = dbgregs->dr6; 4910 vcpu->arch.dr7 = dbgregs->dr7; 4911 kvm_update_dr7(vcpu); 4912 4913 return 0; 4914 } 4915 4916 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 4917 struct kvm_xsave *guest_xsave) 4918 { 4919 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 4920 return; 4921 4922 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, 4923 guest_xsave->region, 4924 sizeof(guest_xsave->region), 4925 vcpu->arch.pkru); 4926 } 4927 4928 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu, 4929 u8 *state, unsigned int size) 4930 { 4931 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 4932 return; 4933 4934 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, 4935 state, size, vcpu->arch.pkru); 4936 } 4937 4938 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 4939 struct kvm_xsave *guest_xsave) 4940 { 4941 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 4942 return 0; 4943 4944 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu, 4945 guest_xsave->region, 4946 supported_xcr0, &vcpu->arch.pkru); 4947 } 4948 4949 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 4950 struct kvm_xcrs *guest_xcrs) 4951 { 4952 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 4953 guest_xcrs->nr_xcrs = 0; 4954 return; 4955 } 4956 4957 guest_xcrs->nr_xcrs = 1; 4958 guest_xcrs->flags = 0; 4959 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 4960 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 4961 } 4962 4963 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 4964 struct kvm_xcrs *guest_xcrs) 4965 { 4966 int i, r = 0; 4967 4968 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 4969 return -EINVAL; 4970 4971 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 4972 return -EINVAL; 4973 4974 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 4975 /* Only support XCR0 currently */ 4976 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 4977 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 4978 guest_xcrs->xcrs[i].value); 4979 break; 4980 } 4981 if (r) 4982 r = -EINVAL; 4983 return r; 4984 } 4985 4986 /* 4987 * kvm_set_guest_paused() indicates to the guest kernel that it has been 4988 * stopped by the hypervisor. This function will be called from the host only. 4989 * EINVAL is returned when the host attempts to set the flag for a guest that 4990 * does not support pv clocks. 4991 */ 4992 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 4993 { 4994 if (!vcpu->arch.pv_time_enabled) 4995 return -EINVAL; 4996 vcpu->arch.pvclock_set_guest_stopped_request = true; 4997 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4998 return 0; 4999 } 5000 5001 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu, 5002 struct kvm_device_attr *attr) 5003 { 5004 int r; 5005 5006 switch (attr->attr) { 5007 case KVM_VCPU_TSC_OFFSET: 5008 r = 0; 5009 break; 5010 default: 5011 r = -ENXIO; 5012 } 5013 5014 return r; 5015 } 5016 5017 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu, 5018 struct kvm_device_attr *attr) 5019 { 5020 u64 __user *uaddr = (u64 __user *)(unsigned long)attr->addr; 5021 int r; 5022 5023 if ((u64)(unsigned long)uaddr != attr->addr) 5024 return -EFAULT; 5025 5026 switch (attr->attr) { 5027 case KVM_VCPU_TSC_OFFSET: 5028 r = -EFAULT; 5029 if (put_user(vcpu->arch.l1_tsc_offset, uaddr)) 5030 break; 5031 r = 0; 5032 break; 5033 default: 5034 r = -ENXIO; 5035 } 5036 5037 return r; 5038 } 5039 5040 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu, 5041 struct kvm_device_attr *attr) 5042 { 5043 u64 __user *uaddr = (u64 __user *)(unsigned long)attr->addr; 5044 struct kvm *kvm = vcpu->kvm; 5045 int r; 5046 5047 if ((u64)(unsigned long)uaddr != attr->addr) 5048 return -EFAULT; 5049 5050 switch (attr->attr) { 5051 case KVM_VCPU_TSC_OFFSET: { 5052 u64 offset, tsc, ns; 5053 unsigned long flags; 5054 bool matched; 5055 5056 r = -EFAULT; 5057 if (get_user(offset, uaddr)) 5058 break; 5059 5060 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 5061 5062 matched = (vcpu->arch.virtual_tsc_khz && 5063 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz && 5064 kvm->arch.last_tsc_offset == offset); 5065 5066 tsc = kvm_scale_tsc(vcpu, rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset; 5067 ns = get_kvmclock_base_ns(); 5068 5069 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched); 5070 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 5071 5072 r = 0; 5073 break; 5074 } 5075 default: 5076 r = -ENXIO; 5077 } 5078 5079 return r; 5080 } 5081 5082 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu, 5083 unsigned int ioctl, 5084 void __user *argp) 5085 { 5086 struct kvm_device_attr attr; 5087 int r; 5088 5089 if (copy_from_user(&attr, argp, sizeof(attr))) 5090 return -EFAULT; 5091 5092 if (attr.group != KVM_VCPU_TSC_CTRL) 5093 return -ENXIO; 5094 5095 switch (ioctl) { 5096 case KVM_HAS_DEVICE_ATTR: 5097 r = kvm_arch_tsc_has_attr(vcpu, &attr); 5098 break; 5099 case KVM_GET_DEVICE_ATTR: 5100 r = kvm_arch_tsc_get_attr(vcpu, &attr); 5101 break; 5102 case KVM_SET_DEVICE_ATTR: 5103 r = kvm_arch_tsc_set_attr(vcpu, &attr); 5104 break; 5105 } 5106 5107 return r; 5108 } 5109 5110 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 5111 struct kvm_enable_cap *cap) 5112 { 5113 int r; 5114 uint16_t vmcs_version; 5115 void __user *user_ptr; 5116 5117 if (cap->flags) 5118 return -EINVAL; 5119 5120 switch (cap->cap) { 5121 case KVM_CAP_HYPERV_SYNIC2: 5122 if (cap->args[0]) 5123 return -EINVAL; 5124 fallthrough; 5125 5126 case KVM_CAP_HYPERV_SYNIC: 5127 if (!irqchip_in_kernel(vcpu->kvm)) 5128 return -EINVAL; 5129 return kvm_hv_activate_synic(vcpu, cap->cap == 5130 KVM_CAP_HYPERV_SYNIC2); 5131 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 5132 if (!kvm_x86_ops.nested_ops->enable_evmcs) 5133 return -ENOTTY; 5134 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); 5135 if (!r) { 5136 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 5137 if (copy_to_user(user_ptr, &vmcs_version, 5138 sizeof(vmcs_version))) 5139 r = -EFAULT; 5140 } 5141 return r; 5142 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 5143 if (!kvm_x86_ops.enable_direct_tlbflush) 5144 return -ENOTTY; 5145 5146 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); 5147 5148 case KVM_CAP_HYPERV_ENFORCE_CPUID: 5149 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]); 5150 5151 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 5152 vcpu->arch.pv_cpuid.enforce = cap->args[0]; 5153 if (vcpu->arch.pv_cpuid.enforce) 5154 kvm_update_pv_runtime(vcpu); 5155 5156 return 0; 5157 default: 5158 return -EINVAL; 5159 } 5160 } 5161 5162 long kvm_arch_vcpu_ioctl(struct file *filp, 5163 unsigned int ioctl, unsigned long arg) 5164 { 5165 struct kvm_vcpu *vcpu = filp->private_data; 5166 void __user *argp = (void __user *)arg; 5167 int r; 5168 union { 5169 struct kvm_sregs2 *sregs2; 5170 struct kvm_lapic_state *lapic; 5171 struct kvm_xsave *xsave; 5172 struct kvm_xcrs *xcrs; 5173 void *buffer; 5174 } u; 5175 5176 vcpu_load(vcpu); 5177 5178 u.buffer = NULL; 5179 switch (ioctl) { 5180 case KVM_GET_LAPIC: { 5181 r = -EINVAL; 5182 if (!lapic_in_kernel(vcpu)) 5183 goto out; 5184 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 5185 GFP_KERNEL_ACCOUNT); 5186 5187 r = -ENOMEM; 5188 if (!u.lapic) 5189 goto out; 5190 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 5191 if (r) 5192 goto out; 5193 r = -EFAULT; 5194 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 5195 goto out; 5196 r = 0; 5197 break; 5198 } 5199 case KVM_SET_LAPIC: { 5200 r = -EINVAL; 5201 if (!lapic_in_kernel(vcpu)) 5202 goto out; 5203 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 5204 if (IS_ERR(u.lapic)) { 5205 r = PTR_ERR(u.lapic); 5206 goto out_nofree; 5207 } 5208 5209 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 5210 break; 5211 } 5212 case KVM_INTERRUPT: { 5213 struct kvm_interrupt irq; 5214 5215 r = -EFAULT; 5216 if (copy_from_user(&irq, argp, sizeof(irq))) 5217 goto out; 5218 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 5219 break; 5220 } 5221 case KVM_NMI: { 5222 r = kvm_vcpu_ioctl_nmi(vcpu); 5223 break; 5224 } 5225 case KVM_SMI: { 5226 r = kvm_vcpu_ioctl_smi(vcpu); 5227 break; 5228 } 5229 case KVM_SET_CPUID: { 5230 struct kvm_cpuid __user *cpuid_arg = argp; 5231 struct kvm_cpuid cpuid; 5232 5233 /* 5234 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as 5235 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't 5236 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page 5237 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with 5238 * the core vCPU model on the fly, so fail. 5239 */ 5240 r = -EINVAL; 5241 if (vcpu->arch.last_vmentry_cpu != -1) 5242 goto out; 5243 5244 r = -EFAULT; 5245 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5246 goto out; 5247 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 5248 break; 5249 } 5250 case KVM_SET_CPUID2: { 5251 struct kvm_cpuid2 __user *cpuid_arg = argp; 5252 struct kvm_cpuid2 cpuid; 5253 5254 /* 5255 * KVM_SET_CPUID{,2} after KVM_RUN is forbidded, see the comment in 5256 * KVM_SET_CPUID case above. 5257 */ 5258 r = -EINVAL; 5259 if (vcpu->arch.last_vmentry_cpu != -1) 5260 goto out; 5261 5262 r = -EFAULT; 5263 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5264 goto out; 5265 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 5266 cpuid_arg->entries); 5267 break; 5268 } 5269 case KVM_GET_CPUID2: { 5270 struct kvm_cpuid2 __user *cpuid_arg = argp; 5271 struct kvm_cpuid2 cpuid; 5272 5273 r = -EFAULT; 5274 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5275 goto out; 5276 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 5277 cpuid_arg->entries); 5278 if (r) 5279 goto out; 5280 r = -EFAULT; 5281 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 5282 goto out; 5283 r = 0; 5284 break; 5285 } 5286 case KVM_GET_MSRS: { 5287 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5288 r = msr_io(vcpu, argp, do_get_msr, 1); 5289 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5290 break; 5291 } 5292 case KVM_SET_MSRS: { 5293 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5294 r = msr_io(vcpu, argp, do_set_msr, 0); 5295 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5296 break; 5297 } 5298 case KVM_TPR_ACCESS_REPORTING: { 5299 struct kvm_tpr_access_ctl tac; 5300 5301 r = -EFAULT; 5302 if (copy_from_user(&tac, argp, sizeof(tac))) 5303 goto out; 5304 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 5305 if (r) 5306 goto out; 5307 r = -EFAULT; 5308 if (copy_to_user(argp, &tac, sizeof(tac))) 5309 goto out; 5310 r = 0; 5311 break; 5312 }; 5313 case KVM_SET_VAPIC_ADDR: { 5314 struct kvm_vapic_addr va; 5315 int idx; 5316 5317 r = -EINVAL; 5318 if (!lapic_in_kernel(vcpu)) 5319 goto out; 5320 r = -EFAULT; 5321 if (copy_from_user(&va, argp, sizeof(va))) 5322 goto out; 5323 idx = srcu_read_lock(&vcpu->kvm->srcu); 5324 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 5325 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5326 break; 5327 } 5328 case KVM_X86_SETUP_MCE: { 5329 u64 mcg_cap; 5330 5331 r = -EFAULT; 5332 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 5333 goto out; 5334 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 5335 break; 5336 } 5337 case KVM_X86_SET_MCE: { 5338 struct kvm_x86_mce mce; 5339 5340 r = -EFAULT; 5341 if (copy_from_user(&mce, argp, sizeof(mce))) 5342 goto out; 5343 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 5344 break; 5345 } 5346 case KVM_GET_VCPU_EVENTS: { 5347 struct kvm_vcpu_events events; 5348 5349 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 5350 5351 r = -EFAULT; 5352 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 5353 break; 5354 r = 0; 5355 break; 5356 } 5357 case KVM_SET_VCPU_EVENTS: { 5358 struct kvm_vcpu_events events; 5359 5360 r = -EFAULT; 5361 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 5362 break; 5363 5364 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 5365 break; 5366 } 5367 case KVM_GET_DEBUGREGS: { 5368 struct kvm_debugregs dbgregs; 5369 5370 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 5371 5372 r = -EFAULT; 5373 if (copy_to_user(argp, &dbgregs, 5374 sizeof(struct kvm_debugregs))) 5375 break; 5376 r = 0; 5377 break; 5378 } 5379 case KVM_SET_DEBUGREGS: { 5380 struct kvm_debugregs dbgregs; 5381 5382 r = -EFAULT; 5383 if (copy_from_user(&dbgregs, argp, 5384 sizeof(struct kvm_debugregs))) 5385 break; 5386 5387 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 5388 break; 5389 } 5390 case KVM_GET_XSAVE: { 5391 r = -EINVAL; 5392 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave)) 5393 break; 5394 5395 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 5396 r = -ENOMEM; 5397 if (!u.xsave) 5398 break; 5399 5400 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 5401 5402 r = -EFAULT; 5403 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 5404 break; 5405 r = 0; 5406 break; 5407 } 5408 case KVM_SET_XSAVE: { 5409 int size = vcpu->arch.guest_fpu.uabi_size; 5410 5411 u.xsave = memdup_user(argp, size); 5412 if (IS_ERR(u.xsave)) { 5413 r = PTR_ERR(u.xsave); 5414 goto out_nofree; 5415 } 5416 5417 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 5418 break; 5419 } 5420 5421 case KVM_GET_XSAVE2: { 5422 int size = vcpu->arch.guest_fpu.uabi_size; 5423 5424 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT); 5425 r = -ENOMEM; 5426 if (!u.xsave) 5427 break; 5428 5429 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size); 5430 5431 r = -EFAULT; 5432 if (copy_to_user(argp, u.xsave, size)) 5433 break; 5434 5435 r = 0; 5436 break; 5437 } 5438 5439 case KVM_GET_XCRS: { 5440 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 5441 r = -ENOMEM; 5442 if (!u.xcrs) 5443 break; 5444 5445 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 5446 5447 r = -EFAULT; 5448 if (copy_to_user(argp, u.xcrs, 5449 sizeof(struct kvm_xcrs))) 5450 break; 5451 r = 0; 5452 break; 5453 } 5454 case KVM_SET_XCRS: { 5455 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 5456 if (IS_ERR(u.xcrs)) { 5457 r = PTR_ERR(u.xcrs); 5458 goto out_nofree; 5459 } 5460 5461 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 5462 break; 5463 } 5464 case KVM_SET_TSC_KHZ: { 5465 u32 user_tsc_khz; 5466 5467 r = -EINVAL; 5468 user_tsc_khz = (u32)arg; 5469 5470 if (kvm_has_tsc_control && 5471 user_tsc_khz >= kvm_max_guest_tsc_khz) 5472 goto out; 5473 5474 if (user_tsc_khz == 0) 5475 user_tsc_khz = tsc_khz; 5476 5477 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 5478 r = 0; 5479 5480 goto out; 5481 } 5482 case KVM_GET_TSC_KHZ: { 5483 r = vcpu->arch.virtual_tsc_khz; 5484 goto out; 5485 } 5486 case KVM_KVMCLOCK_CTRL: { 5487 r = kvm_set_guest_paused(vcpu); 5488 goto out; 5489 } 5490 case KVM_ENABLE_CAP: { 5491 struct kvm_enable_cap cap; 5492 5493 r = -EFAULT; 5494 if (copy_from_user(&cap, argp, sizeof(cap))) 5495 goto out; 5496 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 5497 break; 5498 } 5499 case KVM_GET_NESTED_STATE: { 5500 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5501 u32 user_data_size; 5502 5503 r = -EINVAL; 5504 if (!kvm_x86_ops.nested_ops->get_state) 5505 break; 5506 5507 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 5508 r = -EFAULT; 5509 if (get_user(user_data_size, &user_kvm_nested_state->size)) 5510 break; 5511 5512 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, 5513 user_data_size); 5514 if (r < 0) 5515 break; 5516 5517 if (r > user_data_size) { 5518 if (put_user(r, &user_kvm_nested_state->size)) 5519 r = -EFAULT; 5520 else 5521 r = -E2BIG; 5522 break; 5523 } 5524 5525 r = 0; 5526 break; 5527 } 5528 case KVM_SET_NESTED_STATE: { 5529 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5530 struct kvm_nested_state kvm_state; 5531 int idx; 5532 5533 r = -EINVAL; 5534 if (!kvm_x86_ops.nested_ops->set_state) 5535 break; 5536 5537 r = -EFAULT; 5538 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 5539 break; 5540 5541 r = -EINVAL; 5542 if (kvm_state.size < sizeof(kvm_state)) 5543 break; 5544 5545 if (kvm_state.flags & 5546 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 5547 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING 5548 | KVM_STATE_NESTED_GIF_SET)) 5549 break; 5550 5551 /* nested_run_pending implies guest_mode. */ 5552 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 5553 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 5554 break; 5555 5556 idx = srcu_read_lock(&vcpu->kvm->srcu); 5557 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); 5558 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5559 break; 5560 } 5561 case KVM_GET_SUPPORTED_HV_CPUID: 5562 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); 5563 break; 5564 #ifdef CONFIG_KVM_XEN 5565 case KVM_XEN_VCPU_GET_ATTR: { 5566 struct kvm_xen_vcpu_attr xva; 5567 5568 r = -EFAULT; 5569 if (copy_from_user(&xva, argp, sizeof(xva))) 5570 goto out; 5571 r = kvm_xen_vcpu_get_attr(vcpu, &xva); 5572 if (!r && copy_to_user(argp, &xva, sizeof(xva))) 5573 r = -EFAULT; 5574 break; 5575 } 5576 case KVM_XEN_VCPU_SET_ATTR: { 5577 struct kvm_xen_vcpu_attr xva; 5578 5579 r = -EFAULT; 5580 if (copy_from_user(&xva, argp, sizeof(xva))) 5581 goto out; 5582 r = kvm_xen_vcpu_set_attr(vcpu, &xva); 5583 break; 5584 } 5585 #endif 5586 case KVM_GET_SREGS2: { 5587 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL); 5588 r = -ENOMEM; 5589 if (!u.sregs2) 5590 goto out; 5591 __get_sregs2(vcpu, u.sregs2); 5592 r = -EFAULT; 5593 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2))) 5594 goto out; 5595 r = 0; 5596 break; 5597 } 5598 case KVM_SET_SREGS2: { 5599 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2)); 5600 if (IS_ERR(u.sregs2)) { 5601 r = PTR_ERR(u.sregs2); 5602 u.sregs2 = NULL; 5603 goto out; 5604 } 5605 r = __set_sregs2(vcpu, u.sregs2); 5606 break; 5607 } 5608 case KVM_HAS_DEVICE_ATTR: 5609 case KVM_GET_DEVICE_ATTR: 5610 case KVM_SET_DEVICE_ATTR: 5611 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp); 5612 break; 5613 default: 5614 r = -EINVAL; 5615 } 5616 out: 5617 kfree(u.buffer); 5618 out_nofree: 5619 vcpu_put(vcpu); 5620 return r; 5621 } 5622 5623 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 5624 { 5625 return VM_FAULT_SIGBUS; 5626 } 5627 5628 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 5629 { 5630 int ret; 5631 5632 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 5633 return -EINVAL; 5634 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); 5635 return ret; 5636 } 5637 5638 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 5639 u64 ident_addr) 5640 { 5641 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); 5642 } 5643 5644 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 5645 unsigned long kvm_nr_mmu_pages) 5646 { 5647 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 5648 return -EINVAL; 5649 5650 mutex_lock(&kvm->slots_lock); 5651 5652 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 5653 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 5654 5655 mutex_unlock(&kvm->slots_lock); 5656 return 0; 5657 } 5658 5659 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 5660 { 5661 return kvm->arch.n_max_mmu_pages; 5662 } 5663 5664 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5665 { 5666 struct kvm_pic *pic = kvm->arch.vpic; 5667 int r; 5668 5669 r = 0; 5670 switch (chip->chip_id) { 5671 case KVM_IRQCHIP_PIC_MASTER: 5672 memcpy(&chip->chip.pic, &pic->pics[0], 5673 sizeof(struct kvm_pic_state)); 5674 break; 5675 case KVM_IRQCHIP_PIC_SLAVE: 5676 memcpy(&chip->chip.pic, &pic->pics[1], 5677 sizeof(struct kvm_pic_state)); 5678 break; 5679 case KVM_IRQCHIP_IOAPIC: 5680 kvm_get_ioapic(kvm, &chip->chip.ioapic); 5681 break; 5682 default: 5683 r = -EINVAL; 5684 break; 5685 } 5686 return r; 5687 } 5688 5689 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5690 { 5691 struct kvm_pic *pic = kvm->arch.vpic; 5692 int r; 5693 5694 r = 0; 5695 switch (chip->chip_id) { 5696 case KVM_IRQCHIP_PIC_MASTER: 5697 spin_lock(&pic->lock); 5698 memcpy(&pic->pics[0], &chip->chip.pic, 5699 sizeof(struct kvm_pic_state)); 5700 spin_unlock(&pic->lock); 5701 break; 5702 case KVM_IRQCHIP_PIC_SLAVE: 5703 spin_lock(&pic->lock); 5704 memcpy(&pic->pics[1], &chip->chip.pic, 5705 sizeof(struct kvm_pic_state)); 5706 spin_unlock(&pic->lock); 5707 break; 5708 case KVM_IRQCHIP_IOAPIC: 5709 kvm_set_ioapic(kvm, &chip->chip.ioapic); 5710 break; 5711 default: 5712 r = -EINVAL; 5713 break; 5714 } 5715 kvm_pic_update_irq(pic); 5716 return r; 5717 } 5718 5719 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5720 { 5721 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 5722 5723 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 5724 5725 mutex_lock(&kps->lock); 5726 memcpy(ps, &kps->channels, sizeof(*ps)); 5727 mutex_unlock(&kps->lock); 5728 return 0; 5729 } 5730 5731 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5732 { 5733 int i; 5734 struct kvm_pit *pit = kvm->arch.vpit; 5735 5736 mutex_lock(&pit->pit_state.lock); 5737 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 5738 for (i = 0; i < 3; i++) 5739 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 5740 mutex_unlock(&pit->pit_state.lock); 5741 return 0; 5742 } 5743 5744 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5745 { 5746 mutex_lock(&kvm->arch.vpit->pit_state.lock); 5747 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 5748 sizeof(ps->channels)); 5749 ps->flags = kvm->arch.vpit->pit_state.flags; 5750 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 5751 memset(&ps->reserved, 0, sizeof(ps->reserved)); 5752 return 0; 5753 } 5754 5755 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5756 { 5757 int start = 0; 5758 int i; 5759 u32 prev_legacy, cur_legacy; 5760 struct kvm_pit *pit = kvm->arch.vpit; 5761 5762 mutex_lock(&pit->pit_state.lock); 5763 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 5764 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 5765 if (!prev_legacy && cur_legacy) 5766 start = 1; 5767 memcpy(&pit->pit_state.channels, &ps->channels, 5768 sizeof(pit->pit_state.channels)); 5769 pit->pit_state.flags = ps->flags; 5770 for (i = 0; i < 3; i++) 5771 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 5772 start && i == 0); 5773 mutex_unlock(&pit->pit_state.lock); 5774 return 0; 5775 } 5776 5777 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 5778 struct kvm_reinject_control *control) 5779 { 5780 struct kvm_pit *pit = kvm->arch.vpit; 5781 5782 /* pit->pit_state.lock was overloaded to prevent userspace from getting 5783 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 5784 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 5785 */ 5786 mutex_lock(&pit->pit_state.lock); 5787 kvm_pit_set_reinject(pit, control->pit_reinject); 5788 mutex_unlock(&pit->pit_state.lock); 5789 5790 return 0; 5791 } 5792 5793 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 5794 { 5795 5796 /* 5797 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called 5798 * before reporting dirty_bitmap to userspace. KVM flushes the buffers 5799 * on all VM-Exits, thus we only need to kick running vCPUs to force a 5800 * VM-Exit. 5801 */ 5802 struct kvm_vcpu *vcpu; 5803 unsigned long i; 5804 5805 kvm_for_each_vcpu(i, vcpu, kvm) 5806 kvm_vcpu_kick(vcpu); 5807 } 5808 5809 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 5810 bool line_status) 5811 { 5812 if (!irqchip_in_kernel(kvm)) 5813 return -ENXIO; 5814 5815 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 5816 irq_event->irq, irq_event->level, 5817 line_status); 5818 return 0; 5819 } 5820 5821 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 5822 struct kvm_enable_cap *cap) 5823 { 5824 int r; 5825 5826 if (cap->flags) 5827 return -EINVAL; 5828 5829 switch (cap->cap) { 5830 case KVM_CAP_DISABLE_QUIRKS: 5831 kvm->arch.disabled_quirks = cap->args[0]; 5832 r = 0; 5833 break; 5834 case KVM_CAP_SPLIT_IRQCHIP: { 5835 mutex_lock(&kvm->lock); 5836 r = -EINVAL; 5837 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 5838 goto split_irqchip_unlock; 5839 r = -EEXIST; 5840 if (irqchip_in_kernel(kvm)) 5841 goto split_irqchip_unlock; 5842 if (kvm->created_vcpus) 5843 goto split_irqchip_unlock; 5844 r = kvm_setup_empty_irq_routing(kvm); 5845 if (r) 5846 goto split_irqchip_unlock; 5847 /* Pairs with irqchip_in_kernel. */ 5848 smp_wmb(); 5849 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 5850 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 5851 kvm_request_apicv_update(kvm, true, APICV_INHIBIT_REASON_ABSENT); 5852 r = 0; 5853 split_irqchip_unlock: 5854 mutex_unlock(&kvm->lock); 5855 break; 5856 } 5857 case KVM_CAP_X2APIC_API: 5858 r = -EINVAL; 5859 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 5860 break; 5861 5862 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 5863 kvm->arch.x2apic_format = true; 5864 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 5865 kvm->arch.x2apic_broadcast_quirk_disabled = true; 5866 5867 r = 0; 5868 break; 5869 case KVM_CAP_X86_DISABLE_EXITS: 5870 r = -EINVAL; 5871 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 5872 break; 5873 5874 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 5875 kvm_can_mwait_in_guest()) 5876 kvm->arch.mwait_in_guest = true; 5877 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 5878 kvm->arch.hlt_in_guest = true; 5879 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 5880 kvm->arch.pause_in_guest = true; 5881 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) 5882 kvm->arch.cstate_in_guest = true; 5883 r = 0; 5884 break; 5885 case KVM_CAP_MSR_PLATFORM_INFO: 5886 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 5887 r = 0; 5888 break; 5889 case KVM_CAP_EXCEPTION_PAYLOAD: 5890 kvm->arch.exception_payload_enabled = cap->args[0]; 5891 r = 0; 5892 break; 5893 case KVM_CAP_X86_USER_SPACE_MSR: 5894 kvm->arch.user_space_msr_mask = cap->args[0]; 5895 r = 0; 5896 break; 5897 case KVM_CAP_X86_BUS_LOCK_EXIT: 5898 r = -EINVAL; 5899 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) 5900 break; 5901 5902 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && 5903 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) 5904 break; 5905 5906 if (kvm_has_bus_lock_exit && 5907 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) 5908 kvm->arch.bus_lock_detection_enabled = true; 5909 r = 0; 5910 break; 5911 #ifdef CONFIG_X86_SGX_KVM 5912 case KVM_CAP_SGX_ATTRIBUTE: { 5913 unsigned long allowed_attributes = 0; 5914 5915 r = sgx_set_attribute(&allowed_attributes, cap->args[0]); 5916 if (r) 5917 break; 5918 5919 /* KVM only supports the PROVISIONKEY privileged attribute. */ 5920 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && 5921 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) 5922 kvm->arch.sgx_provisioning_allowed = true; 5923 else 5924 r = -EINVAL; 5925 break; 5926 } 5927 #endif 5928 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 5929 r = -EINVAL; 5930 if (kvm_x86_ops.vm_copy_enc_context_from) 5931 r = kvm_x86_ops.vm_copy_enc_context_from(kvm, cap->args[0]); 5932 return r; 5933 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: 5934 r = -EINVAL; 5935 if (kvm_x86_ops.vm_move_enc_context_from) 5936 r = kvm_x86_ops.vm_move_enc_context_from( 5937 kvm, cap->args[0]); 5938 return r; 5939 case KVM_CAP_EXIT_HYPERCALL: 5940 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) { 5941 r = -EINVAL; 5942 break; 5943 } 5944 kvm->arch.hypercall_exit_enabled = cap->args[0]; 5945 r = 0; 5946 break; 5947 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 5948 r = -EINVAL; 5949 if (cap->args[0] & ~1) 5950 break; 5951 kvm->arch.exit_on_emulation_error = cap->args[0]; 5952 r = 0; 5953 break; 5954 default: 5955 r = -EINVAL; 5956 break; 5957 } 5958 return r; 5959 } 5960 5961 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) 5962 { 5963 struct kvm_x86_msr_filter *msr_filter; 5964 5965 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); 5966 if (!msr_filter) 5967 return NULL; 5968 5969 msr_filter->default_allow = default_allow; 5970 return msr_filter; 5971 } 5972 5973 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) 5974 { 5975 u32 i; 5976 5977 if (!msr_filter) 5978 return; 5979 5980 for (i = 0; i < msr_filter->count; i++) 5981 kfree(msr_filter->ranges[i].bitmap); 5982 5983 kfree(msr_filter); 5984 } 5985 5986 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, 5987 struct kvm_msr_filter_range *user_range) 5988 { 5989 unsigned long *bitmap = NULL; 5990 size_t bitmap_size; 5991 5992 if (!user_range->nmsrs) 5993 return 0; 5994 5995 if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) 5996 return -EINVAL; 5997 5998 if (!user_range->flags) 5999 return -EINVAL; 6000 6001 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); 6002 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) 6003 return -EINVAL; 6004 6005 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); 6006 if (IS_ERR(bitmap)) 6007 return PTR_ERR(bitmap); 6008 6009 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { 6010 .flags = user_range->flags, 6011 .base = user_range->base, 6012 .nmsrs = user_range->nmsrs, 6013 .bitmap = bitmap, 6014 }; 6015 6016 msr_filter->count++; 6017 return 0; 6018 } 6019 6020 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) 6021 { 6022 struct kvm_msr_filter __user *user_msr_filter = argp; 6023 struct kvm_x86_msr_filter *new_filter, *old_filter; 6024 struct kvm_msr_filter filter; 6025 bool default_allow; 6026 bool empty = true; 6027 int r = 0; 6028 u32 i; 6029 6030 if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) 6031 return -EFAULT; 6032 6033 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) 6034 empty &= !filter.ranges[i].nmsrs; 6035 6036 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); 6037 if (empty && !default_allow) 6038 return -EINVAL; 6039 6040 new_filter = kvm_alloc_msr_filter(default_allow); 6041 if (!new_filter) 6042 return -ENOMEM; 6043 6044 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { 6045 r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); 6046 if (r) { 6047 kvm_free_msr_filter(new_filter); 6048 return r; 6049 } 6050 } 6051 6052 mutex_lock(&kvm->lock); 6053 6054 /* The per-VM filter is protected by kvm->lock... */ 6055 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1); 6056 6057 rcu_assign_pointer(kvm->arch.msr_filter, new_filter); 6058 synchronize_srcu(&kvm->srcu); 6059 6060 kvm_free_msr_filter(old_filter); 6061 6062 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); 6063 mutex_unlock(&kvm->lock); 6064 6065 return 0; 6066 } 6067 6068 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER 6069 static int kvm_arch_suspend_notifier(struct kvm *kvm) 6070 { 6071 struct kvm_vcpu *vcpu; 6072 unsigned long i; 6073 int ret = 0; 6074 6075 mutex_lock(&kvm->lock); 6076 kvm_for_each_vcpu(i, vcpu, kvm) { 6077 if (!vcpu->arch.pv_time_enabled) 6078 continue; 6079 6080 ret = kvm_set_guest_paused(vcpu); 6081 if (ret) { 6082 kvm_err("Failed to pause guest VCPU%d: %d\n", 6083 vcpu->vcpu_id, ret); 6084 break; 6085 } 6086 } 6087 mutex_unlock(&kvm->lock); 6088 6089 return ret ? NOTIFY_BAD : NOTIFY_DONE; 6090 } 6091 6092 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state) 6093 { 6094 switch (state) { 6095 case PM_HIBERNATION_PREPARE: 6096 case PM_SUSPEND_PREPARE: 6097 return kvm_arch_suspend_notifier(kvm); 6098 } 6099 6100 return NOTIFY_DONE; 6101 } 6102 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */ 6103 6104 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp) 6105 { 6106 struct kvm_clock_data data = { 0 }; 6107 6108 get_kvmclock(kvm, &data); 6109 if (copy_to_user(argp, &data, sizeof(data))) 6110 return -EFAULT; 6111 6112 return 0; 6113 } 6114 6115 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp) 6116 { 6117 struct kvm_arch *ka = &kvm->arch; 6118 struct kvm_clock_data data; 6119 u64 now_raw_ns; 6120 6121 if (copy_from_user(&data, argp, sizeof(data))) 6122 return -EFAULT; 6123 6124 /* 6125 * Only KVM_CLOCK_REALTIME is used, but allow passing the 6126 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK. 6127 */ 6128 if (data.flags & ~KVM_CLOCK_VALID_FLAGS) 6129 return -EINVAL; 6130 6131 kvm_hv_invalidate_tsc_page(kvm); 6132 kvm_start_pvclock_update(kvm); 6133 pvclock_update_vm_gtod_copy(kvm); 6134 6135 /* 6136 * This pairs with kvm_guest_time_update(): when masterclock is 6137 * in use, we use master_kernel_ns + kvmclock_offset to set 6138 * unsigned 'system_time' so if we use get_kvmclock_ns() (which 6139 * is slightly ahead) here we risk going negative on unsigned 6140 * 'system_time' when 'data.clock' is very small. 6141 */ 6142 if (data.flags & KVM_CLOCK_REALTIME) { 6143 u64 now_real_ns = ktime_get_real_ns(); 6144 6145 /* 6146 * Avoid stepping the kvmclock backwards. 6147 */ 6148 if (now_real_ns > data.realtime) 6149 data.clock += now_real_ns - data.realtime; 6150 } 6151 6152 if (ka->use_master_clock) 6153 now_raw_ns = ka->master_kernel_ns; 6154 else 6155 now_raw_ns = get_kvmclock_base_ns(); 6156 ka->kvmclock_offset = data.clock - now_raw_ns; 6157 kvm_end_pvclock_update(kvm); 6158 return 0; 6159 } 6160 6161 long kvm_arch_vm_ioctl(struct file *filp, 6162 unsigned int ioctl, unsigned long arg) 6163 { 6164 struct kvm *kvm = filp->private_data; 6165 void __user *argp = (void __user *)arg; 6166 int r = -ENOTTY; 6167 /* 6168 * This union makes it completely explicit to gcc-3.x 6169 * that these two variables' stack usage should be 6170 * combined, not added together. 6171 */ 6172 union { 6173 struct kvm_pit_state ps; 6174 struct kvm_pit_state2 ps2; 6175 struct kvm_pit_config pit_config; 6176 } u; 6177 6178 switch (ioctl) { 6179 case KVM_SET_TSS_ADDR: 6180 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 6181 break; 6182 case KVM_SET_IDENTITY_MAP_ADDR: { 6183 u64 ident_addr; 6184 6185 mutex_lock(&kvm->lock); 6186 r = -EINVAL; 6187 if (kvm->created_vcpus) 6188 goto set_identity_unlock; 6189 r = -EFAULT; 6190 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 6191 goto set_identity_unlock; 6192 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 6193 set_identity_unlock: 6194 mutex_unlock(&kvm->lock); 6195 break; 6196 } 6197 case KVM_SET_NR_MMU_PAGES: 6198 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 6199 break; 6200 case KVM_GET_NR_MMU_PAGES: 6201 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 6202 break; 6203 case KVM_CREATE_IRQCHIP: { 6204 mutex_lock(&kvm->lock); 6205 6206 r = -EEXIST; 6207 if (irqchip_in_kernel(kvm)) 6208 goto create_irqchip_unlock; 6209 6210 r = -EINVAL; 6211 if (kvm->created_vcpus) 6212 goto create_irqchip_unlock; 6213 6214 r = kvm_pic_init(kvm); 6215 if (r) 6216 goto create_irqchip_unlock; 6217 6218 r = kvm_ioapic_init(kvm); 6219 if (r) { 6220 kvm_pic_destroy(kvm); 6221 goto create_irqchip_unlock; 6222 } 6223 6224 r = kvm_setup_default_irq_routing(kvm); 6225 if (r) { 6226 kvm_ioapic_destroy(kvm); 6227 kvm_pic_destroy(kvm); 6228 goto create_irqchip_unlock; 6229 } 6230 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 6231 smp_wmb(); 6232 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 6233 kvm_request_apicv_update(kvm, true, APICV_INHIBIT_REASON_ABSENT); 6234 create_irqchip_unlock: 6235 mutex_unlock(&kvm->lock); 6236 break; 6237 } 6238 case KVM_CREATE_PIT: 6239 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 6240 goto create_pit; 6241 case KVM_CREATE_PIT2: 6242 r = -EFAULT; 6243 if (copy_from_user(&u.pit_config, argp, 6244 sizeof(struct kvm_pit_config))) 6245 goto out; 6246 create_pit: 6247 mutex_lock(&kvm->lock); 6248 r = -EEXIST; 6249 if (kvm->arch.vpit) 6250 goto create_pit_unlock; 6251 r = -ENOMEM; 6252 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 6253 if (kvm->arch.vpit) 6254 r = 0; 6255 create_pit_unlock: 6256 mutex_unlock(&kvm->lock); 6257 break; 6258 case KVM_GET_IRQCHIP: { 6259 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 6260 struct kvm_irqchip *chip; 6261 6262 chip = memdup_user(argp, sizeof(*chip)); 6263 if (IS_ERR(chip)) { 6264 r = PTR_ERR(chip); 6265 goto out; 6266 } 6267 6268 r = -ENXIO; 6269 if (!irqchip_kernel(kvm)) 6270 goto get_irqchip_out; 6271 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 6272 if (r) 6273 goto get_irqchip_out; 6274 r = -EFAULT; 6275 if (copy_to_user(argp, chip, sizeof(*chip))) 6276 goto get_irqchip_out; 6277 r = 0; 6278 get_irqchip_out: 6279 kfree(chip); 6280 break; 6281 } 6282 case KVM_SET_IRQCHIP: { 6283 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 6284 struct kvm_irqchip *chip; 6285 6286 chip = memdup_user(argp, sizeof(*chip)); 6287 if (IS_ERR(chip)) { 6288 r = PTR_ERR(chip); 6289 goto out; 6290 } 6291 6292 r = -ENXIO; 6293 if (!irqchip_kernel(kvm)) 6294 goto set_irqchip_out; 6295 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 6296 set_irqchip_out: 6297 kfree(chip); 6298 break; 6299 } 6300 case KVM_GET_PIT: { 6301 r = -EFAULT; 6302 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 6303 goto out; 6304 r = -ENXIO; 6305 if (!kvm->arch.vpit) 6306 goto out; 6307 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 6308 if (r) 6309 goto out; 6310 r = -EFAULT; 6311 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 6312 goto out; 6313 r = 0; 6314 break; 6315 } 6316 case KVM_SET_PIT: { 6317 r = -EFAULT; 6318 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 6319 goto out; 6320 mutex_lock(&kvm->lock); 6321 r = -ENXIO; 6322 if (!kvm->arch.vpit) 6323 goto set_pit_out; 6324 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 6325 set_pit_out: 6326 mutex_unlock(&kvm->lock); 6327 break; 6328 } 6329 case KVM_GET_PIT2: { 6330 r = -ENXIO; 6331 if (!kvm->arch.vpit) 6332 goto out; 6333 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 6334 if (r) 6335 goto out; 6336 r = -EFAULT; 6337 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 6338 goto out; 6339 r = 0; 6340 break; 6341 } 6342 case KVM_SET_PIT2: { 6343 r = -EFAULT; 6344 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 6345 goto out; 6346 mutex_lock(&kvm->lock); 6347 r = -ENXIO; 6348 if (!kvm->arch.vpit) 6349 goto set_pit2_out; 6350 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 6351 set_pit2_out: 6352 mutex_unlock(&kvm->lock); 6353 break; 6354 } 6355 case KVM_REINJECT_CONTROL: { 6356 struct kvm_reinject_control control; 6357 r = -EFAULT; 6358 if (copy_from_user(&control, argp, sizeof(control))) 6359 goto out; 6360 r = -ENXIO; 6361 if (!kvm->arch.vpit) 6362 goto out; 6363 r = kvm_vm_ioctl_reinject(kvm, &control); 6364 break; 6365 } 6366 case KVM_SET_BOOT_CPU_ID: 6367 r = 0; 6368 mutex_lock(&kvm->lock); 6369 if (kvm->created_vcpus) 6370 r = -EBUSY; 6371 else 6372 kvm->arch.bsp_vcpu_id = arg; 6373 mutex_unlock(&kvm->lock); 6374 break; 6375 #ifdef CONFIG_KVM_XEN 6376 case KVM_XEN_HVM_CONFIG: { 6377 struct kvm_xen_hvm_config xhc; 6378 r = -EFAULT; 6379 if (copy_from_user(&xhc, argp, sizeof(xhc))) 6380 goto out; 6381 r = kvm_xen_hvm_config(kvm, &xhc); 6382 break; 6383 } 6384 case KVM_XEN_HVM_GET_ATTR: { 6385 struct kvm_xen_hvm_attr xha; 6386 6387 r = -EFAULT; 6388 if (copy_from_user(&xha, argp, sizeof(xha))) 6389 goto out; 6390 r = kvm_xen_hvm_get_attr(kvm, &xha); 6391 if (!r && copy_to_user(argp, &xha, sizeof(xha))) 6392 r = -EFAULT; 6393 break; 6394 } 6395 case KVM_XEN_HVM_SET_ATTR: { 6396 struct kvm_xen_hvm_attr xha; 6397 6398 r = -EFAULT; 6399 if (copy_from_user(&xha, argp, sizeof(xha))) 6400 goto out; 6401 r = kvm_xen_hvm_set_attr(kvm, &xha); 6402 break; 6403 } 6404 #endif 6405 case KVM_SET_CLOCK: 6406 r = kvm_vm_ioctl_set_clock(kvm, argp); 6407 break; 6408 case KVM_GET_CLOCK: 6409 r = kvm_vm_ioctl_get_clock(kvm, argp); 6410 break; 6411 case KVM_MEMORY_ENCRYPT_OP: { 6412 r = -ENOTTY; 6413 if (kvm_x86_ops.mem_enc_op) 6414 r = static_call(kvm_x86_mem_enc_op)(kvm, argp); 6415 break; 6416 } 6417 case KVM_MEMORY_ENCRYPT_REG_REGION: { 6418 struct kvm_enc_region region; 6419 6420 r = -EFAULT; 6421 if (copy_from_user(®ion, argp, sizeof(region))) 6422 goto out; 6423 6424 r = -ENOTTY; 6425 if (kvm_x86_ops.mem_enc_reg_region) 6426 r = static_call(kvm_x86_mem_enc_reg_region)(kvm, ®ion); 6427 break; 6428 } 6429 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 6430 struct kvm_enc_region region; 6431 6432 r = -EFAULT; 6433 if (copy_from_user(®ion, argp, sizeof(region))) 6434 goto out; 6435 6436 r = -ENOTTY; 6437 if (kvm_x86_ops.mem_enc_unreg_region) 6438 r = static_call(kvm_x86_mem_enc_unreg_region)(kvm, ®ion); 6439 break; 6440 } 6441 case KVM_HYPERV_EVENTFD: { 6442 struct kvm_hyperv_eventfd hvevfd; 6443 6444 r = -EFAULT; 6445 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 6446 goto out; 6447 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 6448 break; 6449 } 6450 case KVM_SET_PMU_EVENT_FILTER: 6451 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); 6452 break; 6453 case KVM_X86_SET_MSR_FILTER: 6454 r = kvm_vm_ioctl_set_msr_filter(kvm, argp); 6455 break; 6456 default: 6457 r = -ENOTTY; 6458 } 6459 out: 6460 return r; 6461 } 6462 6463 static void kvm_init_msr_list(void) 6464 { 6465 struct x86_pmu_capability x86_pmu; 6466 u32 dummy[2]; 6467 unsigned i; 6468 6469 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, 6470 "Please update the fixed PMCs in msrs_to_saved_all[]"); 6471 6472 perf_get_x86_pmu_capability(&x86_pmu); 6473 6474 num_msrs_to_save = 0; 6475 num_emulated_msrs = 0; 6476 num_msr_based_features = 0; 6477 6478 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { 6479 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) 6480 continue; 6481 6482 /* 6483 * Even MSRs that are valid in the host may not be exposed 6484 * to the guests in some cases. 6485 */ 6486 switch (msrs_to_save_all[i]) { 6487 case MSR_IA32_BNDCFGS: 6488 if (!kvm_mpx_supported()) 6489 continue; 6490 break; 6491 case MSR_TSC_AUX: 6492 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && 6493 !kvm_cpu_cap_has(X86_FEATURE_RDPID)) 6494 continue; 6495 break; 6496 case MSR_IA32_UMWAIT_CONTROL: 6497 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) 6498 continue; 6499 break; 6500 case MSR_IA32_RTIT_CTL: 6501 case MSR_IA32_RTIT_STATUS: 6502 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) 6503 continue; 6504 break; 6505 case MSR_IA32_RTIT_CR3_MATCH: 6506 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6507 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 6508 continue; 6509 break; 6510 case MSR_IA32_RTIT_OUTPUT_BASE: 6511 case MSR_IA32_RTIT_OUTPUT_MASK: 6512 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6513 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 6514 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 6515 continue; 6516 break; 6517 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 6518 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 6519 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= 6520 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 6521 continue; 6522 break; 6523 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: 6524 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= 6525 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 6526 continue; 6527 break; 6528 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: 6529 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= 6530 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 6531 continue; 6532 break; 6533 case MSR_IA32_XFD: 6534 case MSR_IA32_XFD_ERR: 6535 if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) 6536 continue; 6537 break; 6538 default: 6539 break; 6540 } 6541 6542 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; 6543 } 6544 6545 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { 6546 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) 6547 continue; 6548 6549 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; 6550 } 6551 6552 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { 6553 struct kvm_msr_entry msr; 6554 6555 msr.index = msr_based_features_all[i]; 6556 if (kvm_get_msr_feature(&msr)) 6557 continue; 6558 6559 msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; 6560 } 6561 } 6562 6563 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 6564 const void *v) 6565 { 6566 int handled = 0; 6567 int n; 6568 6569 do { 6570 n = min(len, 8); 6571 if (!(lapic_in_kernel(vcpu) && 6572 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 6573 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 6574 break; 6575 handled += n; 6576 addr += n; 6577 len -= n; 6578 v += n; 6579 } while (len); 6580 6581 return handled; 6582 } 6583 6584 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 6585 { 6586 int handled = 0; 6587 int n; 6588 6589 do { 6590 n = min(len, 8); 6591 if (!(lapic_in_kernel(vcpu) && 6592 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 6593 addr, n, v)) 6594 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 6595 break; 6596 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 6597 handled += n; 6598 addr += n; 6599 len -= n; 6600 v += n; 6601 } while (len); 6602 6603 return handled; 6604 } 6605 6606 static void kvm_set_segment(struct kvm_vcpu *vcpu, 6607 struct kvm_segment *var, int seg) 6608 { 6609 static_call(kvm_x86_set_segment)(vcpu, var, seg); 6610 } 6611 6612 void kvm_get_segment(struct kvm_vcpu *vcpu, 6613 struct kvm_segment *var, int seg) 6614 { 6615 static_call(kvm_x86_get_segment)(vcpu, var, seg); 6616 } 6617 6618 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 6619 struct x86_exception *exception) 6620 { 6621 struct kvm_mmu *mmu = vcpu->arch.mmu; 6622 gpa_t t_gpa; 6623 6624 BUG_ON(!mmu_is_nested(vcpu)); 6625 6626 /* NPT walks are always user-walks */ 6627 access |= PFERR_USER_MASK; 6628 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception); 6629 6630 return t_gpa; 6631 } 6632 6633 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 6634 struct x86_exception *exception) 6635 { 6636 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6637 6638 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6639 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 6640 } 6641 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); 6642 6643 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 6644 struct x86_exception *exception) 6645 { 6646 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6647 6648 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6649 access |= PFERR_FETCH_MASK; 6650 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 6651 } 6652 6653 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 6654 struct x86_exception *exception) 6655 { 6656 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6657 6658 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6659 access |= PFERR_WRITE_MASK; 6660 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 6661 } 6662 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); 6663 6664 /* uses this to access any guest's mapped memory without checking CPL */ 6665 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 6666 struct x86_exception *exception) 6667 { 6668 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6669 6670 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception); 6671 } 6672 6673 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6674 struct kvm_vcpu *vcpu, u32 access, 6675 struct x86_exception *exception) 6676 { 6677 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6678 void *data = val; 6679 int r = X86EMUL_CONTINUE; 6680 6681 while (bytes) { 6682 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); 6683 unsigned offset = addr & (PAGE_SIZE-1); 6684 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 6685 int ret; 6686 6687 if (gpa == UNMAPPED_GVA) 6688 return X86EMUL_PROPAGATE_FAULT; 6689 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 6690 offset, toread); 6691 if (ret < 0) { 6692 r = X86EMUL_IO_NEEDED; 6693 goto out; 6694 } 6695 6696 bytes -= toread; 6697 data += toread; 6698 addr += toread; 6699 } 6700 out: 6701 return r; 6702 } 6703 6704 /* used for instruction fetching */ 6705 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 6706 gva_t addr, void *val, unsigned int bytes, 6707 struct x86_exception *exception) 6708 { 6709 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6710 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6711 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6712 unsigned offset; 6713 int ret; 6714 6715 /* Inline kvm_read_guest_virt_helper for speed. */ 6716 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK, 6717 exception); 6718 if (unlikely(gpa == UNMAPPED_GVA)) 6719 return X86EMUL_PROPAGATE_FAULT; 6720 6721 offset = addr & (PAGE_SIZE-1); 6722 if (WARN_ON(offset + bytes > PAGE_SIZE)) 6723 bytes = (unsigned)PAGE_SIZE - offset; 6724 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 6725 offset, bytes); 6726 if (unlikely(ret < 0)) 6727 return X86EMUL_IO_NEEDED; 6728 6729 return X86EMUL_CONTINUE; 6730 } 6731 6732 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 6733 gva_t addr, void *val, unsigned int bytes, 6734 struct x86_exception *exception) 6735 { 6736 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6737 6738 /* 6739 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 6740 * is returned, but our callers are not ready for that and they blindly 6741 * call kvm_inject_page_fault. Ensure that they at least do not leak 6742 * uninitialized kernel stack memory into cr2 and error code. 6743 */ 6744 memset(exception, 0, sizeof(*exception)); 6745 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 6746 exception); 6747 } 6748 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 6749 6750 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 6751 gva_t addr, void *val, unsigned int bytes, 6752 struct x86_exception *exception, bool system) 6753 { 6754 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6755 u32 access = 0; 6756 6757 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6758 access |= PFERR_USER_MASK; 6759 6760 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 6761 } 6762 6763 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 6764 unsigned long addr, void *val, unsigned int bytes) 6765 { 6766 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6767 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 6768 6769 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 6770 } 6771 6772 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6773 struct kvm_vcpu *vcpu, u32 access, 6774 struct x86_exception *exception) 6775 { 6776 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6777 void *data = val; 6778 int r = X86EMUL_CONTINUE; 6779 6780 while (bytes) { 6781 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); 6782 unsigned offset = addr & (PAGE_SIZE-1); 6783 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 6784 int ret; 6785 6786 if (gpa == UNMAPPED_GVA) 6787 return X86EMUL_PROPAGATE_FAULT; 6788 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 6789 if (ret < 0) { 6790 r = X86EMUL_IO_NEEDED; 6791 goto out; 6792 } 6793 6794 bytes -= towrite; 6795 data += towrite; 6796 addr += towrite; 6797 } 6798 out: 6799 return r; 6800 } 6801 6802 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 6803 unsigned int bytes, struct x86_exception *exception, 6804 bool system) 6805 { 6806 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6807 u32 access = PFERR_WRITE_MASK; 6808 6809 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6810 access |= PFERR_USER_MASK; 6811 6812 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6813 access, exception); 6814 } 6815 6816 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 6817 unsigned int bytes, struct x86_exception *exception) 6818 { 6819 /* kvm_write_guest_virt_system can pull in tons of pages. */ 6820 vcpu->arch.l1tf_flush_l1d = true; 6821 6822 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6823 PFERR_WRITE_MASK, exception); 6824 } 6825 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 6826 6827 int handle_ud(struct kvm_vcpu *vcpu) 6828 { 6829 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; 6830 int emul_type = EMULTYPE_TRAP_UD; 6831 char sig[5]; /* ud2; .ascii "kvm" */ 6832 struct x86_exception e; 6833 6834 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, NULL, 0))) 6835 return 1; 6836 6837 if (force_emulation_prefix && 6838 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 6839 sig, sizeof(sig), &e) == 0 && 6840 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { 6841 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 6842 emul_type = EMULTYPE_TRAP_UD_FORCED; 6843 } 6844 6845 return kvm_emulate_instruction(vcpu, emul_type); 6846 } 6847 EXPORT_SYMBOL_GPL(handle_ud); 6848 6849 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6850 gpa_t gpa, bool write) 6851 { 6852 /* For APIC access vmexit */ 6853 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 6854 return 1; 6855 6856 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 6857 trace_vcpu_match_mmio(gva, gpa, write, true); 6858 return 1; 6859 } 6860 6861 return 0; 6862 } 6863 6864 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6865 gpa_t *gpa, struct x86_exception *exception, 6866 bool write) 6867 { 6868 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 6869 u32 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) 6870 | (write ? PFERR_WRITE_MASK : 0); 6871 6872 /* 6873 * currently PKRU is only applied to ept enabled guest so 6874 * there is no pkey in EPT page table for L1 guest or EPT 6875 * shadow page table for L2 guest. 6876 */ 6877 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) || 6878 !permission_fault(vcpu, vcpu->arch.walk_mmu, 6879 vcpu->arch.mmio_access, 0, access))) { 6880 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 6881 (gva & (PAGE_SIZE - 1)); 6882 trace_vcpu_match_mmio(gva, *gpa, write, false); 6883 return 1; 6884 } 6885 6886 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 6887 6888 if (*gpa == UNMAPPED_GVA) 6889 return -1; 6890 6891 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 6892 } 6893 6894 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 6895 const void *val, int bytes) 6896 { 6897 int ret; 6898 6899 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 6900 if (ret < 0) 6901 return 0; 6902 kvm_page_track_write(vcpu, gpa, val, bytes); 6903 return 1; 6904 } 6905 6906 struct read_write_emulator_ops { 6907 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 6908 int bytes); 6909 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 6910 void *val, int bytes); 6911 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6912 int bytes, void *val); 6913 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6914 void *val, int bytes); 6915 bool write; 6916 }; 6917 6918 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 6919 { 6920 if (vcpu->mmio_read_completed) { 6921 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 6922 vcpu->mmio_fragments[0].gpa, val); 6923 vcpu->mmio_read_completed = 0; 6924 return 1; 6925 } 6926 6927 return 0; 6928 } 6929 6930 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6931 void *val, int bytes) 6932 { 6933 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 6934 } 6935 6936 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6937 void *val, int bytes) 6938 { 6939 return emulator_write_phys(vcpu, gpa, val, bytes); 6940 } 6941 6942 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 6943 { 6944 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 6945 return vcpu_mmio_write(vcpu, gpa, bytes, val); 6946 } 6947 6948 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6949 void *val, int bytes) 6950 { 6951 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 6952 return X86EMUL_IO_NEEDED; 6953 } 6954 6955 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6956 void *val, int bytes) 6957 { 6958 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 6959 6960 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 6961 return X86EMUL_CONTINUE; 6962 } 6963 6964 static const struct read_write_emulator_ops read_emultor = { 6965 .read_write_prepare = read_prepare, 6966 .read_write_emulate = read_emulate, 6967 .read_write_mmio = vcpu_mmio_read, 6968 .read_write_exit_mmio = read_exit_mmio, 6969 }; 6970 6971 static const struct read_write_emulator_ops write_emultor = { 6972 .read_write_emulate = write_emulate, 6973 .read_write_mmio = write_mmio, 6974 .read_write_exit_mmio = write_exit_mmio, 6975 .write = true, 6976 }; 6977 6978 static int emulator_read_write_onepage(unsigned long addr, void *val, 6979 unsigned int bytes, 6980 struct x86_exception *exception, 6981 struct kvm_vcpu *vcpu, 6982 const struct read_write_emulator_ops *ops) 6983 { 6984 gpa_t gpa; 6985 int handled, ret; 6986 bool write = ops->write; 6987 struct kvm_mmio_fragment *frag; 6988 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6989 6990 /* 6991 * If the exit was due to a NPF we may already have a GPA. 6992 * If the GPA is present, use it to avoid the GVA to GPA table walk. 6993 * Note, this cannot be used on string operations since string 6994 * operation using rep will only have the initial GPA from the NPF 6995 * occurred. 6996 */ 6997 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && 6998 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { 6999 gpa = ctxt->gpa_val; 7000 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 7001 } else { 7002 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 7003 if (ret < 0) 7004 return X86EMUL_PROPAGATE_FAULT; 7005 } 7006 7007 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 7008 return X86EMUL_CONTINUE; 7009 7010 /* 7011 * Is this MMIO handled locally? 7012 */ 7013 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 7014 if (handled == bytes) 7015 return X86EMUL_CONTINUE; 7016 7017 gpa += handled; 7018 bytes -= handled; 7019 val += handled; 7020 7021 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 7022 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 7023 frag->gpa = gpa; 7024 frag->data = val; 7025 frag->len = bytes; 7026 return X86EMUL_CONTINUE; 7027 } 7028 7029 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 7030 unsigned long addr, 7031 void *val, unsigned int bytes, 7032 struct x86_exception *exception, 7033 const struct read_write_emulator_ops *ops) 7034 { 7035 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7036 gpa_t gpa; 7037 int rc; 7038 7039 if (ops->read_write_prepare && 7040 ops->read_write_prepare(vcpu, val, bytes)) 7041 return X86EMUL_CONTINUE; 7042 7043 vcpu->mmio_nr_fragments = 0; 7044 7045 /* Crossing a page boundary? */ 7046 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 7047 int now; 7048 7049 now = -addr & ~PAGE_MASK; 7050 rc = emulator_read_write_onepage(addr, val, now, exception, 7051 vcpu, ops); 7052 7053 if (rc != X86EMUL_CONTINUE) 7054 return rc; 7055 addr += now; 7056 if (ctxt->mode != X86EMUL_MODE_PROT64) 7057 addr = (u32)addr; 7058 val += now; 7059 bytes -= now; 7060 } 7061 7062 rc = emulator_read_write_onepage(addr, val, bytes, exception, 7063 vcpu, ops); 7064 if (rc != X86EMUL_CONTINUE) 7065 return rc; 7066 7067 if (!vcpu->mmio_nr_fragments) 7068 return rc; 7069 7070 gpa = vcpu->mmio_fragments[0].gpa; 7071 7072 vcpu->mmio_needed = 1; 7073 vcpu->mmio_cur_fragment = 0; 7074 7075 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 7076 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 7077 vcpu->run->exit_reason = KVM_EXIT_MMIO; 7078 vcpu->run->mmio.phys_addr = gpa; 7079 7080 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 7081 } 7082 7083 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 7084 unsigned long addr, 7085 void *val, 7086 unsigned int bytes, 7087 struct x86_exception *exception) 7088 { 7089 return emulator_read_write(ctxt, addr, val, bytes, 7090 exception, &read_emultor); 7091 } 7092 7093 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 7094 unsigned long addr, 7095 const void *val, 7096 unsigned int bytes, 7097 struct x86_exception *exception) 7098 { 7099 return emulator_read_write(ctxt, addr, (void *)val, bytes, 7100 exception, &write_emultor); 7101 } 7102 7103 #define CMPXCHG_TYPE(t, ptr, old, new) \ 7104 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 7105 7106 #ifdef CONFIG_X86_64 7107 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 7108 #else 7109 # define CMPXCHG64(ptr, old, new) \ 7110 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 7111 #endif 7112 7113 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 7114 unsigned long addr, 7115 const void *old, 7116 const void *new, 7117 unsigned int bytes, 7118 struct x86_exception *exception) 7119 { 7120 struct kvm_host_map map; 7121 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7122 u64 page_line_mask; 7123 gpa_t gpa; 7124 char *kaddr; 7125 bool exchanged; 7126 7127 /* guests cmpxchg8b have to be emulated atomically */ 7128 if (bytes > 8 || (bytes & (bytes - 1))) 7129 goto emul_write; 7130 7131 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 7132 7133 if (gpa == UNMAPPED_GVA || 7134 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 7135 goto emul_write; 7136 7137 /* 7138 * Emulate the atomic as a straight write to avoid #AC if SLD is 7139 * enabled in the host and the access splits a cache line. 7140 */ 7141 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 7142 page_line_mask = ~(cache_line_size() - 1); 7143 else 7144 page_line_mask = PAGE_MASK; 7145 7146 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) 7147 goto emul_write; 7148 7149 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) 7150 goto emul_write; 7151 7152 kaddr = map.hva + offset_in_page(gpa); 7153 7154 switch (bytes) { 7155 case 1: 7156 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 7157 break; 7158 case 2: 7159 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 7160 break; 7161 case 4: 7162 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 7163 break; 7164 case 8: 7165 exchanged = CMPXCHG64(kaddr, old, new); 7166 break; 7167 default: 7168 BUG(); 7169 } 7170 7171 kvm_vcpu_unmap(vcpu, &map, true); 7172 7173 if (!exchanged) 7174 return X86EMUL_CMPXCHG_FAILED; 7175 7176 kvm_page_track_write(vcpu, gpa, new, bytes); 7177 7178 return X86EMUL_CONTINUE; 7179 7180 emul_write: 7181 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 7182 7183 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 7184 } 7185 7186 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 7187 { 7188 int r = 0, i; 7189 7190 for (i = 0; i < vcpu->arch.pio.count; i++) { 7191 if (vcpu->arch.pio.in) 7192 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 7193 vcpu->arch.pio.size, pd); 7194 else 7195 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 7196 vcpu->arch.pio.port, vcpu->arch.pio.size, 7197 pd); 7198 if (r) 7199 break; 7200 pd += vcpu->arch.pio.size; 7201 } 7202 return r; 7203 } 7204 7205 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 7206 unsigned short port, 7207 unsigned int count, bool in) 7208 { 7209 vcpu->arch.pio.port = port; 7210 vcpu->arch.pio.in = in; 7211 vcpu->arch.pio.count = count; 7212 vcpu->arch.pio.size = size; 7213 7214 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) 7215 return 1; 7216 7217 vcpu->run->exit_reason = KVM_EXIT_IO; 7218 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 7219 vcpu->run->io.size = size; 7220 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 7221 vcpu->run->io.count = count; 7222 vcpu->run->io.port = port; 7223 7224 return 0; 7225 } 7226 7227 static int __emulator_pio_in(struct kvm_vcpu *vcpu, int size, 7228 unsigned short port, unsigned int count) 7229 { 7230 WARN_ON(vcpu->arch.pio.count); 7231 memset(vcpu->arch.pio_data, 0, size * count); 7232 return emulator_pio_in_out(vcpu, size, port, count, true); 7233 } 7234 7235 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val) 7236 { 7237 int size = vcpu->arch.pio.size; 7238 unsigned count = vcpu->arch.pio.count; 7239 memcpy(val, vcpu->arch.pio_data, size * count); 7240 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data); 7241 vcpu->arch.pio.count = 0; 7242 } 7243 7244 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, 7245 unsigned short port, void *val, unsigned int count) 7246 { 7247 if (vcpu->arch.pio.count) { 7248 /* 7249 * Complete a previous iteration that required userspace I/O. 7250 * Note, @count isn't guaranteed to match pio.count as userspace 7251 * can modify ECX before rerunning the vCPU. Ignore any such 7252 * shenanigans as KVM doesn't support modifying the rep count, 7253 * and the emulator ensures @count doesn't overflow the buffer. 7254 */ 7255 } else { 7256 int r = __emulator_pio_in(vcpu, size, port, count); 7257 if (!r) 7258 return r; 7259 7260 /* Results already available, fall through. */ 7261 } 7262 7263 complete_emulator_pio_in(vcpu, val); 7264 return 1; 7265 } 7266 7267 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 7268 int size, unsigned short port, void *val, 7269 unsigned int count) 7270 { 7271 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); 7272 7273 } 7274 7275 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, 7276 unsigned short port, const void *val, 7277 unsigned int count) 7278 { 7279 int ret; 7280 7281 memcpy(vcpu->arch.pio_data, val, size * count); 7282 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 7283 ret = emulator_pio_in_out(vcpu, size, port, count, false); 7284 if (ret) 7285 vcpu->arch.pio.count = 0; 7286 7287 return ret; 7288 } 7289 7290 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 7291 int size, unsigned short port, 7292 const void *val, unsigned int count) 7293 { 7294 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); 7295 } 7296 7297 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 7298 { 7299 return static_call(kvm_x86_get_segment_base)(vcpu, seg); 7300 } 7301 7302 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 7303 { 7304 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 7305 } 7306 7307 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 7308 { 7309 if (!need_emulate_wbinvd(vcpu)) 7310 return X86EMUL_CONTINUE; 7311 7312 if (static_call(kvm_x86_has_wbinvd_exit)()) { 7313 int cpu = get_cpu(); 7314 7315 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 7316 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, 7317 wbinvd_ipi, NULL, 1); 7318 put_cpu(); 7319 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 7320 } else 7321 wbinvd(); 7322 return X86EMUL_CONTINUE; 7323 } 7324 7325 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 7326 { 7327 kvm_emulate_wbinvd_noskip(vcpu); 7328 return kvm_skip_emulated_instruction(vcpu); 7329 } 7330 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 7331 7332 7333 7334 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 7335 { 7336 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 7337 } 7338 7339 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 7340 unsigned long *dest) 7341 { 7342 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 7343 } 7344 7345 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 7346 unsigned long value) 7347 { 7348 7349 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 7350 } 7351 7352 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 7353 { 7354 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 7355 } 7356 7357 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 7358 { 7359 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7360 unsigned long value; 7361 7362 switch (cr) { 7363 case 0: 7364 value = kvm_read_cr0(vcpu); 7365 break; 7366 case 2: 7367 value = vcpu->arch.cr2; 7368 break; 7369 case 3: 7370 value = kvm_read_cr3(vcpu); 7371 break; 7372 case 4: 7373 value = kvm_read_cr4(vcpu); 7374 break; 7375 case 8: 7376 value = kvm_get_cr8(vcpu); 7377 break; 7378 default: 7379 kvm_err("%s: unexpected cr %u\n", __func__, cr); 7380 return 0; 7381 } 7382 7383 return value; 7384 } 7385 7386 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 7387 { 7388 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7389 int res = 0; 7390 7391 switch (cr) { 7392 case 0: 7393 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 7394 break; 7395 case 2: 7396 vcpu->arch.cr2 = val; 7397 break; 7398 case 3: 7399 res = kvm_set_cr3(vcpu, val); 7400 break; 7401 case 4: 7402 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 7403 break; 7404 case 8: 7405 res = kvm_set_cr8(vcpu, val); 7406 break; 7407 default: 7408 kvm_err("%s: unexpected cr %u\n", __func__, cr); 7409 res = -1; 7410 } 7411 7412 return res; 7413 } 7414 7415 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 7416 { 7417 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); 7418 } 7419 7420 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7421 { 7422 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); 7423 } 7424 7425 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7426 { 7427 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); 7428 } 7429 7430 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7431 { 7432 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); 7433 } 7434 7435 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 7436 { 7437 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); 7438 } 7439 7440 static unsigned long emulator_get_cached_segment_base( 7441 struct x86_emulate_ctxt *ctxt, int seg) 7442 { 7443 return get_segment_base(emul_to_vcpu(ctxt), seg); 7444 } 7445 7446 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 7447 struct desc_struct *desc, u32 *base3, 7448 int seg) 7449 { 7450 struct kvm_segment var; 7451 7452 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 7453 *selector = var.selector; 7454 7455 if (var.unusable) { 7456 memset(desc, 0, sizeof(*desc)); 7457 if (base3) 7458 *base3 = 0; 7459 return false; 7460 } 7461 7462 if (var.g) 7463 var.limit >>= 12; 7464 set_desc_limit(desc, var.limit); 7465 set_desc_base(desc, (unsigned long)var.base); 7466 #ifdef CONFIG_X86_64 7467 if (base3) 7468 *base3 = var.base >> 32; 7469 #endif 7470 desc->type = var.type; 7471 desc->s = var.s; 7472 desc->dpl = var.dpl; 7473 desc->p = var.present; 7474 desc->avl = var.avl; 7475 desc->l = var.l; 7476 desc->d = var.db; 7477 desc->g = var.g; 7478 7479 return true; 7480 } 7481 7482 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 7483 struct desc_struct *desc, u32 base3, 7484 int seg) 7485 { 7486 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7487 struct kvm_segment var; 7488 7489 var.selector = selector; 7490 var.base = get_desc_base(desc); 7491 #ifdef CONFIG_X86_64 7492 var.base |= ((u64)base3) << 32; 7493 #endif 7494 var.limit = get_desc_limit(desc); 7495 if (desc->g) 7496 var.limit = (var.limit << 12) | 0xfff; 7497 var.type = desc->type; 7498 var.dpl = desc->dpl; 7499 var.db = desc->d; 7500 var.s = desc->s; 7501 var.l = desc->l; 7502 var.g = desc->g; 7503 var.avl = desc->avl; 7504 var.present = desc->p; 7505 var.unusable = !var.present; 7506 var.padding = 0; 7507 7508 kvm_set_segment(vcpu, &var, seg); 7509 return; 7510 } 7511 7512 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 7513 u32 msr_index, u64 *pdata) 7514 { 7515 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7516 int r; 7517 7518 r = kvm_get_msr(vcpu, msr_index, pdata); 7519 7520 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0, 7521 complete_emulated_rdmsr, r)) { 7522 /* Bounce to user space */ 7523 return X86EMUL_IO_NEEDED; 7524 } 7525 7526 return r; 7527 } 7528 7529 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 7530 u32 msr_index, u64 data) 7531 { 7532 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7533 int r; 7534 7535 r = kvm_set_msr(vcpu, msr_index, data); 7536 7537 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data, 7538 complete_emulated_msr_access, r)) { 7539 /* Bounce to user space */ 7540 return X86EMUL_IO_NEEDED; 7541 } 7542 7543 return r; 7544 } 7545 7546 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 7547 { 7548 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7549 7550 return vcpu->arch.smbase; 7551 } 7552 7553 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 7554 { 7555 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7556 7557 vcpu->arch.smbase = smbase; 7558 } 7559 7560 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 7561 u32 pmc) 7562 { 7563 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc)) 7564 return 0; 7565 return -EINVAL; 7566 } 7567 7568 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 7569 u32 pmc, u64 *pdata) 7570 { 7571 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 7572 } 7573 7574 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 7575 { 7576 emul_to_vcpu(ctxt)->arch.halt_request = 1; 7577 } 7578 7579 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 7580 struct x86_instruction_info *info, 7581 enum x86_intercept_stage stage) 7582 { 7583 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, 7584 &ctxt->exception); 7585 } 7586 7587 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 7588 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, 7589 bool exact_only) 7590 { 7591 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); 7592 } 7593 7594 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) 7595 { 7596 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); 7597 } 7598 7599 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) 7600 { 7601 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); 7602 } 7603 7604 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) 7605 { 7606 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); 7607 } 7608 7609 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 7610 { 7611 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); 7612 } 7613 7614 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 7615 { 7616 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); 7617 } 7618 7619 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 7620 { 7621 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); 7622 } 7623 7624 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 7625 { 7626 return emul_to_vcpu(ctxt)->arch.hflags; 7627 } 7628 7629 static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt) 7630 { 7631 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7632 7633 kvm_smm_changed(vcpu, false); 7634 } 7635 7636 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt, 7637 const char *smstate) 7638 { 7639 return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate); 7640 } 7641 7642 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) 7643 { 7644 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); 7645 } 7646 7647 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) 7648 { 7649 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); 7650 } 7651 7652 static const struct x86_emulate_ops emulate_ops = { 7653 .read_gpr = emulator_read_gpr, 7654 .write_gpr = emulator_write_gpr, 7655 .read_std = emulator_read_std, 7656 .write_std = emulator_write_std, 7657 .read_phys = kvm_read_guest_phys_system, 7658 .fetch = kvm_fetch_guest_virt, 7659 .read_emulated = emulator_read_emulated, 7660 .write_emulated = emulator_write_emulated, 7661 .cmpxchg_emulated = emulator_cmpxchg_emulated, 7662 .invlpg = emulator_invlpg, 7663 .pio_in_emulated = emulator_pio_in_emulated, 7664 .pio_out_emulated = emulator_pio_out_emulated, 7665 .get_segment = emulator_get_segment, 7666 .set_segment = emulator_set_segment, 7667 .get_cached_segment_base = emulator_get_cached_segment_base, 7668 .get_gdt = emulator_get_gdt, 7669 .get_idt = emulator_get_idt, 7670 .set_gdt = emulator_set_gdt, 7671 .set_idt = emulator_set_idt, 7672 .get_cr = emulator_get_cr, 7673 .set_cr = emulator_set_cr, 7674 .cpl = emulator_get_cpl, 7675 .get_dr = emulator_get_dr, 7676 .set_dr = emulator_set_dr, 7677 .get_smbase = emulator_get_smbase, 7678 .set_smbase = emulator_set_smbase, 7679 .set_msr = emulator_set_msr, 7680 .get_msr = emulator_get_msr, 7681 .check_pmc = emulator_check_pmc, 7682 .read_pmc = emulator_read_pmc, 7683 .halt = emulator_halt, 7684 .wbinvd = emulator_wbinvd, 7685 .fix_hypercall = emulator_fix_hypercall, 7686 .intercept = emulator_intercept, 7687 .get_cpuid = emulator_get_cpuid, 7688 .guest_has_long_mode = emulator_guest_has_long_mode, 7689 .guest_has_movbe = emulator_guest_has_movbe, 7690 .guest_has_fxsr = emulator_guest_has_fxsr, 7691 .set_nmi_mask = emulator_set_nmi_mask, 7692 .get_hflags = emulator_get_hflags, 7693 .exiting_smm = emulator_exiting_smm, 7694 .leave_smm = emulator_leave_smm, 7695 .triple_fault = emulator_triple_fault, 7696 .set_xcr = emulator_set_xcr, 7697 }; 7698 7699 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 7700 { 7701 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 7702 /* 7703 * an sti; sti; sequence only disable interrupts for the first 7704 * instruction. So, if the last instruction, be it emulated or 7705 * not, left the system with the INT_STI flag enabled, it 7706 * means that the last instruction is an sti. We should not 7707 * leave the flag on in this case. The same goes for mov ss 7708 */ 7709 if (int_shadow & mask) 7710 mask = 0; 7711 if (unlikely(int_shadow || mask)) { 7712 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); 7713 if (!mask) 7714 kvm_make_request(KVM_REQ_EVENT, vcpu); 7715 } 7716 } 7717 7718 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 7719 { 7720 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7721 if (ctxt->exception.vector == PF_VECTOR) 7722 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); 7723 7724 if (ctxt->exception.error_code_valid) 7725 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 7726 ctxt->exception.error_code); 7727 else 7728 kvm_queue_exception(vcpu, ctxt->exception.vector); 7729 return false; 7730 } 7731 7732 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) 7733 { 7734 struct x86_emulate_ctxt *ctxt; 7735 7736 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); 7737 if (!ctxt) { 7738 pr_err("kvm: failed to allocate vcpu's emulator\n"); 7739 return NULL; 7740 } 7741 7742 ctxt->vcpu = vcpu; 7743 ctxt->ops = &emulate_ops; 7744 vcpu->arch.emulate_ctxt = ctxt; 7745 7746 return ctxt; 7747 } 7748 7749 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 7750 { 7751 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7752 int cs_db, cs_l; 7753 7754 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 7755 7756 ctxt->gpa_available = false; 7757 ctxt->eflags = kvm_get_rflags(vcpu); 7758 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 7759 7760 ctxt->eip = kvm_rip_read(vcpu); 7761 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 7762 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 7763 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 7764 cs_db ? X86EMUL_MODE_PROT32 : 7765 X86EMUL_MODE_PROT16; 7766 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 7767 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 7768 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 7769 7770 ctxt->interruptibility = 0; 7771 ctxt->have_exception = false; 7772 ctxt->exception.vector = -1; 7773 ctxt->perm_ok = false; 7774 7775 init_decode_cache(ctxt); 7776 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 7777 } 7778 7779 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 7780 { 7781 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7782 int ret; 7783 7784 init_emulate_ctxt(vcpu); 7785 7786 ctxt->op_bytes = 2; 7787 ctxt->ad_bytes = 2; 7788 ctxt->_eip = ctxt->eip + inc_eip; 7789 ret = emulate_int_real(ctxt, irq); 7790 7791 if (ret != X86EMUL_CONTINUE) { 7792 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 7793 } else { 7794 ctxt->eip = ctxt->_eip; 7795 kvm_rip_write(vcpu, ctxt->eip); 7796 kvm_set_rflags(vcpu, ctxt->eflags); 7797 } 7798 } 7799 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 7800 7801 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, 7802 u8 ndata, u8 *insn_bytes, u8 insn_size) 7803 { 7804 struct kvm_run *run = vcpu->run; 7805 u64 info[5]; 7806 u8 info_start; 7807 7808 /* 7809 * Zero the whole array used to retrieve the exit info, as casting to 7810 * u32 for select entries will leave some chunks uninitialized. 7811 */ 7812 memset(&info, 0, sizeof(info)); 7813 7814 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1], 7815 &info[2], (u32 *)&info[3], 7816 (u32 *)&info[4]); 7817 7818 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 7819 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION; 7820 7821 /* 7822 * There's currently space for 13 entries, but 5 are used for the exit 7823 * reason and info. Restrict to 4 to reduce the maintenance burden 7824 * when expanding kvm_run.emulation_failure in the future. 7825 */ 7826 if (WARN_ON_ONCE(ndata > 4)) 7827 ndata = 4; 7828 7829 /* Always include the flags as a 'data' entry. */ 7830 info_start = 1; 7831 run->emulation_failure.flags = 0; 7832 7833 if (insn_size) { 7834 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) + 7835 sizeof(run->emulation_failure.insn_bytes) != 16)); 7836 info_start += 2; 7837 run->emulation_failure.flags |= 7838 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES; 7839 run->emulation_failure.insn_size = insn_size; 7840 memset(run->emulation_failure.insn_bytes, 0x90, 7841 sizeof(run->emulation_failure.insn_bytes)); 7842 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size); 7843 } 7844 7845 memcpy(&run->internal.data[info_start], info, sizeof(info)); 7846 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data, 7847 ndata * sizeof(data[0])); 7848 7849 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata; 7850 } 7851 7852 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu) 7853 { 7854 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7855 7856 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data, 7857 ctxt->fetch.end - ctxt->fetch.data); 7858 } 7859 7860 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, 7861 u8 ndata) 7862 { 7863 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0); 7864 } 7865 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit); 7866 7867 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu) 7868 { 7869 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0); 7870 } 7871 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit); 7872 7873 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 7874 { 7875 struct kvm *kvm = vcpu->kvm; 7876 7877 ++vcpu->stat.insn_emulation_fail; 7878 trace_kvm_emulate_insn_failed(vcpu); 7879 7880 if (emulation_type & EMULTYPE_VMWARE_GP) { 7881 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 7882 return 1; 7883 } 7884 7885 if (kvm->arch.exit_on_emulation_error || 7886 (emulation_type & EMULTYPE_SKIP)) { 7887 prepare_emulation_ctxt_failure_exit(vcpu); 7888 return 0; 7889 } 7890 7891 kvm_queue_exception(vcpu, UD_VECTOR); 7892 7893 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { 7894 prepare_emulation_ctxt_failure_exit(vcpu); 7895 return 0; 7896 } 7897 7898 return 1; 7899 } 7900 7901 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 7902 bool write_fault_to_shadow_pgtable, 7903 int emulation_type) 7904 { 7905 gpa_t gpa = cr2_or_gpa; 7906 kvm_pfn_t pfn; 7907 7908 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7909 return false; 7910 7911 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7912 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7913 return false; 7914 7915 if (!vcpu->arch.mmu->direct_map) { 7916 /* 7917 * Write permission should be allowed since only 7918 * write access need to be emulated. 7919 */ 7920 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 7921 7922 /* 7923 * If the mapping is invalid in guest, let cpu retry 7924 * it to generate fault. 7925 */ 7926 if (gpa == UNMAPPED_GVA) 7927 return true; 7928 } 7929 7930 /* 7931 * Do not retry the unhandleable instruction if it faults on the 7932 * readonly host memory, otherwise it will goto a infinite loop: 7933 * retry instruction -> write #PF -> emulation fail -> retry 7934 * instruction -> ... 7935 */ 7936 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 7937 7938 /* 7939 * If the instruction failed on the error pfn, it can not be fixed, 7940 * report the error to userspace. 7941 */ 7942 if (is_error_noslot_pfn(pfn)) 7943 return false; 7944 7945 kvm_release_pfn_clean(pfn); 7946 7947 /* The instructions are well-emulated on direct mmu. */ 7948 if (vcpu->arch.mmu->direct_map) { 7949 unsigned int indirect_shadow_pages; 7950 7951 write_lock(&vcpu->kvm->mmu_lock); 7952 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 7953 write_unlock(&vcpu->kvm->mmu_lock); 7954 7955 if (indirect_shadow_pages) 7956 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7957 7958 return true; 7959 } 7960 7961 /* 7962 * if emulation was due to access to shadowed page table 7963 * and it failed try to unshadow page and re-enter the 7964 * guest to let CPU execute the instruction. 7965 */ 7966 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7967 7968 /* 7969 * If the access faults on its page table, it can not 7970 * be fixed by unprotecting shadow page and it should 7971 * be reported to userspace. 7972 */ 7973 return !write_fault_to_shadow_pgtable; 7974 } 7975 7976 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 7977 gpa_t cr2_or_gpa, int emulation_type) 7978 { 7979 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7980 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; 7981 7982 last_retry_eip = vcpu->arch.last_retry_eip; 7983 last_retry_addr = vcpu->arch.last_retry_addr; 7984 7985 /* 7986 * If the emulation is caused by #PF and it is non-page_table 7987 * writing instruction, it means the VM-EXIT is caused by shadow 7988 * page protected, we can zap the shadow page and retry this 7989 * instruction directly. 7990 * 7991 * Note: if the guest uses a non-page-table modifying instruction 7992 * on the PDE that points to the instruction, then we will unmap 7993 * the instruction and go to an infinite loop. So, we cache the 7994 * last retried eip and the last fault address, if we meet the eip 7995 * and the address again, we can break out of the potential infinite 7996 * loop. 7997 */ 7998 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 7999 8000 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 8001 return false; 8002 8003 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 8004 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 8005 return false; 8006 8007 if (x86_page_table_writing_insn(ctxt)) 8008 return false; 8009 8010 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) 8011 return false; 8012 8013 vcpu->arch.last_retry_eip = ctxt->eip; 8014 vcpu->arch.last_retry_addr = cr2_or_gpa; 8015 8016 if (!vcpu->arch.mmu->direct_map) 8017 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 8018 8019 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 8020 8021 return true; 8022 } 8023 8024 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 8025 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 8026 8027 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm) 8028 { 8029 trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm); 8030 8031 if (entering_smm) { 8032 vcpu->arch.hflags |= HF_SMM_MASK; 8033 } else { 8034 vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK); 8035 8036 /* Process a latched INIT or SMI, if any. */ 8037 kvm_make_request(KVM_REQ_EVENT, vcpu); 8038 8039 /* 8040 * Even if KVM_SET_SREGS2 loaded PDPTRs out of band, 8041 * on SMM exit we still need to reload them from 8042 * guest memory 8043 */ 8044 vcpu->arch.pdptrs_from_userspace = false; 8045 } 8046 8047 kvm_mmu_reset_context(vcpu); 8048 } 8049 8050 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 8051 unsigned long *db) 8052 { 8053 u32 dr6 = 0; 8054 int i; 8055 u32 enable, rwlen; 8056 8057 enable = dr7; 8058 rwlen = dr7 >> 16; 8059 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 8060 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 8061 dr6 |= (1 << i); 8062 return dr6; 8063 } 8064 8065 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) 8066 { 8067 struct kvm_run *kvm_run = vcpu->run; 8068 8069 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 8070 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; 8071 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); 8072 kvm_run->debug.arch.exception = DB_VECTOR; 8073 kvm_run->exit_reason = KVM_EXIT_DEBUG; 8074 return 0; 8075 } 8076 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 8077 return 1; 8078 } 8079 8080 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 8081 { 8082 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 8083 int r; 8084 8085 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); 8086 if (unlikely(!r)) 8087 return 0; 8088 8089 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS); 8090 8091 /* 8092 * rflags is the old, "raw" value of the flags. The new value has 8093 * not been saved yet. 8094 * 8095 * This is correct even for TF set by the guest, because "the 8096 * processor will not generate this exception after the instruction 8097 * that sets the TF flag". 8098 */ 8099 if (unlikely(rflags & X86_EFLAGS_TF)) 8100 r = kvm_vcpu_do_singlestep(vcpu); 8101 return r; 8102 } 8103 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 8104 8105 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 8106 { 8107 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 8108 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 8109 struct kvm_run *kvm_run = vcpu->run; 8110 unsigned long eip = kvm_get_linear_rip(vcpu); 8111 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 8112 vcpu->arch.guest_debug_dr7, 8113 vcpu->arch.eff_db); 8114 8115 if (dr6 != 0) { 8116 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; 8117 kvm_run->debug.arch.pc = eip; 8118 kvm_run->debug.arch.exception = DB_VECTOR; 8119 kvm_run->exit_reason = KVM_EXIT_DEBUG; 8120 *r = 0; 8121 return true; 8122 } 8123 } 8124 8125 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 8126 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 8127 unsigned long eip = kvm_get_linear_rip(vcpu); 8128 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 8129 vcpu->arch.dr7, 8130 vcpu->arch.db); 8131 8132 if (dr6 != 0) { 8133 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); 8134 *r = 1; 8135 return true; 8136 } 8137 } 8138 8139 return false; 8140 } 8141 8142 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 8143 { 8144 switch (ctxt->opcode_len) { 8145 case 1: 8146 switch (ctxt->b) { 8147 case 0xe4: /* IN */ 8148 case 0xe5: 8149 case 0xec: 8150 case 0xed: 8151 case 0xe6: /* OUT */ 8152 case 0xe7: 8153 case 0xee: 8154 case 0xef: 8155 case 0x6c: /* INS */ 8156 case 0x6d: 8157 case 0x6e: /* OUTS */ 8158 case 0x6f: 8159 return true; 8160 } 8161 break; 8162 case 2: 8163 switch (ctxt->b) { 8164 case 0x33: /* RDPMC */ 8165 return true; 8166 } 8167 break; 8168 } 8169 8170 return false; 8171 } 8172 8173 /* 8174 * Decode to be emulated instruction. Return EMULATION_OK if success. 8175 */ 8176 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 8177 void *insn, int insn_len) 8178 { 8179 int r = EMULATION_OK; 8180 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8181 8182 init_emulate_ctxt(vcpu); 8183 8184 /* 8185 * We will reenter on the same instruction since we do not set 8186 * complete_userspace_io. This does not handle watchpoints yet, 8187 * those would be handled in the emulate_ops. 8188 */ 8189 if (!(emulation_type & EMULTYPE_SKIP) && 8190 kvm_vcpu_check_breakpoint(vcpu, &r)) 8191 return r; 8192 8193 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); 8194 8195 trace_kvm_emulate_insn_start(vcpu); 8196 ++vcpu->stat.insn_emulation; 8197 8198 return r; 8199 } 8200 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); 8201 8202 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 8203 int emulation_type, void *insn, int insn_len) 8204 { 8205 int r; 8206 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8207 bool writeback = true; 8208 bool write_fault_to_spt; 8209 8210 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, insn, insn_len))) 8211 return 1; 8212 8213 vcpu->arch.l1tf_flush_l1d = true; 8214 8215 /* 8216 * Clear write_fault_to_shadow_pgtable here to ensure it is 8217 * never reused. 8218 */ 8219 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 8220 vcpu->arch.write_fault_to_shadow_pgtable = false; 8221 8222 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 8223 kvm_clear_exception_queue(vcpu); 8224 8225 r = x86_decode_emulated_instruction(vcpu, emulation_type, 8226 insn, insn_len); 8227 if (r != EMULATION_OK) { 8228 if ((emulation_type & EMULTYPE_TRAP_UD) || 8229 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { 8230 kvm_queue_exception(vcpu, UD_VECTOR); 8231 return 1; 8232 } 8233 if (reexecute_instruction(vcpu, cr2_or_gpa, 8234 write_fault_to_spt, 8235 emulation_type)) 8236 return 1; 8237 if (ctxt->have_exception) { 8238 /* 8239 * #UD should result in just EMULATION_FAILED, and trap-like 8240 * exception should not be encountered during decode. 8241 */ 8242 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || 8243 exception_type(ctxt->exception.vector) == EXCPT_TRAP); 8244 inject_emulated_exception(vcpu); 8245 return 1; 8246 } 8247 return handle_emulation_failure(vcpu, emulation_type); 8248 } 8249 } 8250 8251 if ((emulation_type & EMULTYPE_VMWARE_GP) && 8252 !is_vmware_backdoor_opcode(ctxt)) { 8253 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 8254 return 1; 8255 } 8256 8257 /* 8258 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for 8259 * use *only* by vendor callbacks for kvm_skip_emulated_instruction(). 8260 * The caller is responsible for updating interruptibility state and 8261 * injecting single-step #DBs. 8262 */ 8263 if (emulation_type & EMULTYPE_SKIP) { 8264 if (ctxt->mode != X86EMUL_MODE_PROT64) 8265 ctxt->eip = (u32)ctxt->_eip; 8266 else 8267 ctxt->eip = ctxt->_eip; 8268 8269 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) { 8270 r = 1; 8271 goto writeback; 8272 } 8273 8274 kvm_rip_write(vcpu, ctxt->eip); 8275 if (ctxt->eflags & X86_EFLAGS_RF) 8276 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 8277 return 1; 8278 } 8279 8280 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) 8281 return 1; 8282 8283 /* this is needed for vmware backdoor interface to work since it 8284 changes registers values during IO operation */ 8285 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 8286 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 8287 emulator_invalidate_register_cache(ctxt); 8288 } 8289 8290 restart: 8291 if (emulation_type & EMULTYPE_PF) { 8292 /* Save the faulting GPA (cr2) in the address field */ 8293 ctxt->exception.address = cr2_or_gpa; 8294 8295 /* With shadow page tables, cr2 contains a GVA or nGPA. */ 8296 if (vcpu->arch.mmu->direct_map) { 8297 ctxt->gpa_available = true; 8298 ctxt->gpa_val = cr2_or_gpa; 8299 } 8300 } else { 8301 /* Sanitize the address out of an abundance of paranoia. */ 8302 ctxt->exception.address = 0; 8303 } 8304 8305 r = x86_emulate_insn(ctxt); 8306 8307 if (r == EMULATION_INTERCEPTED) 8308 return 1; 8309 8310 if (r == EMULATION_FAILED) { 8311 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, 8312 emulation_type)) 8313 return 1; 8314 8315 return handle_emulation_failure(vcpu, emulation_type); 8316 } 8317 8318 if (ctxt->have_exception) { 8319 r = 1; 8320 if (inject_emulated_exception(vcpu)) 8321 return r; 8322 } else if (vcpu->arch.pio.count) { 8323 if (!vcpu->arch.pio.in) { 8324 /* FIXME: return into emulator if single-stepping. */ 8325 vcpu->arch.pio.count = 0; 8326 } else { 8327 writeback = false; 8328 vcpu->arch.complete_userspace_io = complete_emulated_pio; 8329 } 8330 r = 0; 8331 } else if (vcpu->mmio_needed) { 8332 ++vcpu->stat.mmio_exits; 8333 8334 if (!vcpu->mmio_is_write) 8335 writeback = false; 8336 r = 0; 8337 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 8338 } else if (vcpu->arch.complete_userspace_io) { 8339 writeback = false; 8340 r = 0; 8341 } else if (r == EMULATION_RESTART) 8342 goto restart; 8343 else 8344 r = 1; 8345 8346 writeback: 8347 if (writeback) { 8348 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 8349 toggle_interruptibility(vcpu, ctxt->interruptibility); 8350 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 8351 if (!ctxt->have_exception || 8352 exception_type(ctxt->exception.vector) == EXCPT_TRAP) { 8353 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS); 8354 if (ctxt->is_branch) 8355 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 8356 kvm_rip_write(vcpu, ctxt->eip); 8357 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 8358 r = kvm_vcpu_do_singlestep(vcpu); 8359 if (kvm_x86_ops.update_emulated_instruction) 8360 static_call(kvm_x86_update_emulated_instruction)(vcpu); 8361 __kvm_set_rflags(vcpu, ctxt->eflags); 8362 } 8363 8364 /* 8365 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 8366 * do nothing, and it will be requested again as soon as 8367 * the shadow expires. But we still need to check here, 8368 * because POPF has no interrupt shadow. 8369 */ 8370 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 8371 kvm_make_request(KVM_REQ_EVENT, vcpu); 8372 } else 8373 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 8374 8375 return r; 8376 } 8377 8378 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 8379 { 8380 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 8381 } 8382 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 8383 8384 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 8385 void *insn, int insn_len) 8386 { 8387 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 8388 } 8389 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 8390 8391 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 8392 { 8393 vcpu->arch.pio.count = 0; 8394 return 1; 8395 } 8396 8397 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 8398 { 8399 vcpu->arch.pio.count = 0; 8400 8401 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 8402 return 1; 8403 8404 return kvm_skip_emulated_instruction(vcpu); 8405 } 8406 8407 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 8408 unsigned short port) 8409 { 8410 unsigned long val = kvm_rax_read(vcpu); 8411 int ret = emulator_pio_out(vcpu, size, port, &val, 1); 8412 8413 if (ret) 8414 return ret; 8415 8416 /* 8417 * Workaround userspace that relies on old KVM behavior of %rip being 8418 * incremented prior to exiting to userspace to handle "OUT 0x7e". 8419 */ 8420 if (port == 0x7e && 8421 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 8422 vcpu->arch.complete_userspace_io = 8423 complete_fast_pio_out_port_0x7e; 8424 kvm_skip_emulated_instruction(vcpu); 8425 } else { 8426 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 8427 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 8428 } 8429 return 0; 8430 } 8431 8432 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 8433 { 8434 unsigned long val; 8435 8436 /* We should only ever be called with arch.pio.count equal to 1 */ 8437 BUG_ON(vcpu->arch.pio.count != 1); 8438 8439 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 8440 vcpu->arch.pio.count = 0; 8441 return 1; 8442 } 8443 8444 /* For size less than 4 we merge, else we zero extend */ 8445 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 8446 8447 /* 8448 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform 8449 * the copy and tracing 8450 */ 8451 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); 8452 kvm_rax_write(vcpu, val); 8453 8454 return kvm_skip_emulated_instruction(vcpu); 8455 } 8456 8457 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 8458 unsigned short port) 8459 { 8460 unsigned long val; 8461 int ret; 8462 8463 /* For size less than 4 we merge, else we zero extend */ 8464 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 8465 8466 ret = emulator_pio_in(vcpu, size, port, &val, 1); 8467 if (ret) { 8468 kvm_rax_write(vcpu, val); 8469 return ret; 8470 } 8471 8472 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 8473 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 8474 8475 return 0; 8476 } 8477 8478 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 8479 { 8480 int ret; 8481 8482 if (in) 8483 ret = kvm_fast_pio_in(vcpu, size, port); 8484 else 8485 ret = kvm_fast_pio_out(vcpu, size, port); 8486 return ret && kvm_skip_emulated_instruction(vcpu); 8487 } 8488 EXPORT_SYMBOL_GPL(kvm_fast_pio); 8489 8490 static int kvmclock_cpu_down_prep(unsigned int cpu) 8491 { 8492 __this_cpu_write(cpu_tsc_khz, 0); 8493 return 0; 8494 } 8495 8496 static void tsc_khz_changed(void *data) 8497 { 8498 struct cpufreq_freqs *freq = data; 8499 unsigned long khz = 0; 8500 8501 if (data) 8502 khz = freq->new; 8503 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 8504 khz = cpufreq_quick_get(raw_smp_processor_id()); 8505 if (!khz) 8506 khz = tsc_khz; 8507 __this_cpu_write(cpu_tsc_khz, khz); 8508 } 8509 8510 #ifdef CONFIG_X86_64 8511 static void kvm_hyperv_tsc_notifier(void) 8512 { 8513 struct kvm *kvm; 8514 int cpu; 8515 8516 mutex_lock(&kvm_lock); 8517 list_for_each_entry(kvm, &vm_list, vm_list) 8518 kvm_make_mclock_inprogress_request(kvm); 8519 8520 /* no guest entries from this point */ 8521 hyperv_stop_tsc_emulation(); 8522 8523 /* TSC frequency always matches when on Hyper-V */ 8524 for_each_present_cpu(cpu) 8525 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 8526 kvm_max_guest_tsc_khz = tsc_khz; 8527 8528 list_for_each_entry(kvm, &vm_list, vm_list) { 8529 __kvm_start_pvclock_update(kvm); 8530 pvclock_update_vm_gtod_copy(kvm); 8531 kvm_end_pvclock_update(kvm); 8532 } 8533 8534 mutex_unlock(&kvm_lock); 8535 } 8536 #endif 8537 8538 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 8539 { 8540 struct kvm *kvm; 8541 struct kvm_vcpu *vcpu; 8542 int send_ipi = 0; 8543 unsigned long i; 8544 8545 /* 8546 * We allow guests to temporarily run on slowing clocks, 8547 * provided we notify them after, or to run on accelerating 8548 * clocks, provided we notify them before. Thus time never 8549 * goes backwards. 8550 * 8551 * However, we have a problem. We can't atomically update 8552 * the frequency of a given CPU from this function; it is 8553 * merely a notifier, which can be called from any CPU. 8554 * Changing the TSC frequency at arbitrary points in time 8555 * requires a recomputation of local variables related to 8556 * the TSC for each VCPU. We must flag these local variables 8557 * to be updated and be sure the update takes place with the 8558 * new frequency before any guests proceed. 8559 * 8560 * Unfortunately, the combination of hotplug CPU and frequency 8561 * change creates an intractable locking scenario; the order 8562 * of when these callouts happen is undefined with respect to 8563 * CPU hotplug, and they can race with each other. As such, 8564 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 8565 * undefined; you can actually have a CPU frequency change take 8566 * place in between the computation of X and the setting of the 8567 * variable. To protect against this problem, all updates of 8568 * the per_cpu tsc_khz variable are done in an interrupt 8569 * protected IPI, and all callers wishing to update the value 8570 * must wait for a synchronous IPI to complete (which is trivial 8571 * if the caller is on the CPU already). This establishes the 8572 * necessary total order on variable updates. 8573 * 8574 * Note that because a guest time update may take place 8575 * anytime after the setting of the VCPU's request bit, the 8576 * correct TSC value must be set before the request. However, 8577 * to ensure the update actually makes it to any guest which 8578 * starts running in hardware virtualization between the set 8579 * and the acquisition of the spinlock, we must also ping the 8580 * CPU after setting the request bit. 8581 * 8582 */ 8583 8584 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 8585 8586 mutex_lock(&kvm_lock); 8587 list_for_each_entry(kvm, &vm_list, vm_list) { 8588 kvm_for_each_vcpu(i, vcpu, kvm) { 8589 if (vcpu->cpu != cpu) 8590 continue; 8591 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 8592 if (vcpu->cpu != raw_smp_processor_id()) 8593 send_ipi = 1; 8594 } 8595 } 8596 mutex_unlock(&kvm_lock); 8597 8598 if (freq->old < freq->new && send_ipi) { 8599 /* 8600 * We upscale the frequency. Must make the guest 8601 * doesn't see old kvmclock values while running with 8602 * the new frequency, otherwise we risk the guest sees 8603 * time go backwards. 8604 * 8605 * In case we update the frequency for another cpu 8606 * (which might be in guest context) send an interrupt 8607 * to kick the cpu out of guest context. Next time 8608 * guest context is entered kvmclock will be updated, 8609 * so the guest will not see stale values. 8610 */ 8611 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 8612 } 8613 } 8614 8615 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 8616 void *data) 8617 { 8618 struct cpufreq_freqs *freq = data; 8619 int cpu; 8620 8621 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 8622 return 0; 8623 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 8624 return 0; 8625 8626 for_each_cpu(cpu, freq->policy->cpus) 8627 __kvmclock_cpufreq_notifier(freq, cpu); 8628 8629 return 0; 8630 } 8631 8632 static struct notifier_block kvmclock_cpufreq_notifier_block = { 8633 .notifier_call = kvmclock_cpufreq_notifier 8634 }; 8635 8636 static int kvmclock_cpu_online(unsigned int cpu) 8637 { 8638 tsc_khz_changed(NULL); 8639 return 0; 8640 } 8641 8642 static void kvm_timer_init(void) 8643 { 8644 max_tsc_khz = tsc_khz; 8645 8646 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 8647 #ifdef CONFIG_CPU_FREQ 8648 struct cpufreq_policy *policy; 8649 int cpu; 8650 8651 cpu = get_cpu(); 8652 policy = cpufreq_cpu_get(cpu); 8653 if (policy) { 8654 if (policy->cpuinfo.max_freq) 8655 max_tsc_khz = policy->cpuinfo.max_freq; 8656 cpufreq_cpu_put(policy); 8657 } 8658 put_cpu(); 8659 #endif 8660 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 8661 CPUFREQ_TRANSITION_NOTIFIER); 8662 } 8663 8664 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 8665 kvmclock_cpu_online, kvmclock_cpu_down_prep); 8666 } 8667 8668 #ifdef CONFIG_X86_64 8669 static void pvclock_gtod_update_fn(struct work_struct *work) 8670 { 8671 struct kvm *kvm; 8672 struct kvm_vcpu *vcpu; 8673 unsigned long i; 8674 8675 mutex_lock(&kvm_lock); 8676 list_for_each_entry(kvm, &vm_list, vm_list) 8677 kvm_for_each_vcpu(i, vcpu, kvm) 8678 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 8679 atomic_set(&kvm_guest_has_master_clock, 0); 8680 mutex_unlock(&kvm_lock); 8681 } 8682 8683 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 8684 8685 /* 8686 * Indirection to move queue_work() out of the tk_core.seq write held 8687 * region to prevent possible deadlocks against time accessors which 8688 * are invoked with work related locks held. 8689 */ 8690 static void pvclock_irq_work_fn(struct irq_work *w) 8691 { 8692 queue_work(system_long_wq, &pvclock_gtod_work); 8693 } 8694 8695 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); 8696 8697 /* 8698 * Notification about pvclock gtod data update. 8699 */ 8700 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 8701 void *priv) 8702 { 8703 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 8704 struct timekeeper *tk = priv; 8705 8706 update_pvclock_gtod(tk); 8707 8708 /* 8709 * Disable master clock if host does not trust, or does not use, 8710 * TSC based clocksource. Delegate queue_work() to irq_work as 8711 * this is invoked with tk_core.seq write held. 8712 */ 8713 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 8714 atomic_read(&kvm_guest_has_master_clock) != 0) 8715 irq_work_queue(&pvclock_irq_work); 8716 return 0; 8717 } 8718 8719 static struct notifier_block pvclock_gtod_notifier = { 8720 .notifier_call = pvclock_gtod_notify, 8721 }; 8722 #endif 8723 8724 int kvm_arch_init(void *opaque) 8725 { 8726 struct kvm_x86_init_ops *ops = opaque; 8727 int r; 8728 8729 if (kvm_x86_ops.hardware_enable) { 8730 pr_err("kvm: already loaded vendor module '%s'\n", kvm_x86_ops.name); 8731 r = -EEXIST; 8732 goto out; 8733 } 8734 8735 if (!ops->cpu_has_kvm_support()) { 8736 pr_err_ratelimited("kvm: no hardware support for '%s'\n", 8737 ops->runtime_ops->name); 8738 r = -EOPNOTSUPP; 8739 goto out; 8740 } 8741 if (ops->disabled_by_bios()) { 8742 pr_err_ratelimited("kvm: support for '%s' disabled by bios\n", 8743 ops->runtime_ops->name); 8744 r = -EOPNOTSUPP; 8745 goto out; 8746 } 8747 8748 /* 8749 * KVM explicitly assumes that the guest has an FPU and 8750 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 8751 * vCPU's FPU state as a fxregs_state struct. 8752 */ 8753 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 8754 printk(KERN_ERR "kvm: inadequate fpu\n"); 8755 r = -EOPNOTSUPP; 8756 goto out; 8757 } 8758 8759 r = -ENOMEM; 8760 8761 x86_emulator_cache = kvm_alloc_emulator_cache(); 8762 if (!x86_emulator_cache) { 8763 pr_err("kvm: failed to allocate cache for x86 emulator\n"); 8764 goto out; 8765 } 8766 8767 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); 8768 if (!user_return_msrs) { 8769 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); 8770 goto out_free_x86_emulator_cache; 8771 } 8772 kvm_nr_uret_msrs = 0; 8773 8774 r = kvm_mmu_module_init(); 8775 if (r) 8776 goto out_free_percpu; 8777 8778 kvm_timer_init(); 8779 8780 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 8781 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 8782 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; 8783 } 8784 8785 if (pi_inject_timer == -1) 8786 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); 8787 #ifdef CONFIG_X86_64 8788 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 8789 8790 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8791 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 8792 #endif 8793 8794 return 0; 8795 8796 out_free_percpu: 8797 free_percpu(user_return_msrs); 8798 out_free_x86_emulator_cache: 8799 kmem_cache_destroy(x86_emulator_cache); 8800 out: 8801 return r; 8802 } 8803 8804 void kvm_arch_exit(void) 8805 { 8806 #ifdef CONFIG_X86_64 8807 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8808 clear_hv_tscchange_cb(); 8809 #endif 8810 kvm_lapic_exit(); 8811 8812 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 8813 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 8814 CPUFREQ_TRANSITION_NOTIFIER); 8815 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 8816 #ifdef CONFIG_X86_64 8817 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 8818 irq_work_sync(&pvclock_irq_work); 8819 cancel_work_sync(&pvclock_gtod_work); 8820 #endif 8821 kvm_x86_ops.hardware_enable = NULL; 8822 kvm_mmu_module_exit(); 8823 free_percpu(user_return_msrs); 8824 kmem_cache_destroy(x86_emulator_cache); 8825 #ifdef CONFIG_KVM_XEN 8826 static_key_deferred_flush(&kvm_xen_enabled); 8827 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); 8828 #endif 8829 } 8830 8831 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason) 8832 { 8833 /* 8834 * The vCPU has halted, e.g. executed HLT. Update the run state if the 8835 * local APIC is in-kernel, the run loop will detect the non-runnable 8836 * state and halt the vCPU. Exit to userspace if the local APIC is 8837 * managed by userspace, in which case userspace is responsible for 8838 * handling wake events. 8839 */ 8840 ++vcpu->stat.halt_exits; 8841 if (lapic_in_kernel(vcpu)) { 8842 vcpu->arch.mp_state = state; 8843 return 1; 8844 } else { 8845 vcpu->run->exit_reason = reason; 8846 return 0; 8847 } 8848 } 8849 8850 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu) 8851 { 8852 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); 8853 } 8854 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip); 8855 8856 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 8857 { 8858 int ret = kvm_skip_emulated_instruction(vcpu); 8859 /* 8860 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 8861 * KVM_EXIT_DEBUG here. 8862 */ 8863 return kvm_emulate_halt_noskip(vcpu) && ret; 8864 } 8865 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 8866 8867 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) 8868 { 8869 int ret = kvm_skip_emulated_instruction(vcpu); 8870 8871 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, 8872 KVM_EXIT_AP_RESET_HOLD) && ret; 8873 } 8874 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); 8875 8876 #ifdef CONFIG_X86_64 8877 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 8878 unsigned long clock_type) 8879 { 8880 struct kvm_clock_pairing clock_pairing; 8881 struct timespec64 ts; 8882 u64 cycle; 8883 int ret; 8884 8885 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 8886 return -KVM_EOPNOTSUPP; 8887 8888 if (!kvm_get_walltime_and_clockread(&ts, &cycle)) 8889 return -KVM_EOPNOTSUPP; 8890 8891 clock_pairing.sec = ts.tv_sec; 8892 clock_pairing.nsec = ts.tv_nsec; 8893 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 8894 clock_pairing.flags = 0; 8895 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 8896 8897 ret = 0; 8898 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 8899 sizeof(struct kvm_clock_pairing))) 8900 ret = -KVM_EFAULT; 8901 8902 return ret; 8903 } 8904 #endif 8905 8906 /* 8907 * kvm_pv_kick_cpu_op: Kick a vcpu. 8908 * 8909 * @apicid - apicid of vcpu to be kicked. 8910 */ 8911 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 8912 { 8913 struct kvm_lapic_irq lapic_irq; 8914 8915 lapic_irq.shorthand = APIC_DEST_NOSHORT; 8916 lapic_irq.dest_mode = APIC_DEST_PHYSICAL; 8917 lapic_irq.level = 0; 8918 lapic_irq.dest_id = apicid; 8919 lapic_irq.msi_redir_hint = false; 8920 8921 lapic_irq.delivery_mode = APIC_DM_REMRD; 8922 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 8923 } 8924 8925 bool kvm_apicv_activated(struct kvm *kvm) 8926 { 8927 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); 8928 } 8929 EXPORT_SYMBOL_GPL(kvm_apicv_activated); 8930 8931 static void kvm_apicv_init(struct kvm *kvm) 8932 { 8933 init_rwsem(&kvm->arch.apicv_update_lock); 8934 8935 set_bit(APICV_INHIBIT_REASON_ABSENT, 8936 &kvm->arch.apicv_inhibit_reasons); 8937 if (!enable_apicv) 8938 set_bit(APICV_INHIBIT_REASON_DISABLE, 8939 &kvm->arch.apicv_inhibit_reasons); 8940 } 8941 8942 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) 8943 { 8944 struct kvm_vcpu *target = NULL; 8945 struct kvm_apic_map *map; 8946 8947 vcpu->stat.directed_yield_attempted++; 8948 8949 if (single_task_running()) 8950 goto no_yield; 8951 8952 rcu_read_lock(); 8953 map = rcu_dereference(vcpu->kvm->arch.apic_map); 8954 8955 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 8956 target = map->phys_map[dest_id]->vcpu; 8957 8958 rcu_read_unlock(); 8959 8960 if (!target || !READ_ONCE(target->ready)) 8961 goto no_yield; 8962 8963 /* Ignore requests to yield to self */ 8964 if (vcpu == target) 8965 goto no_yield; 8966 8967 if (kvm_vcpu_yield_to(target) <= 0) 8968 goto no_yield; 8969 8970 vcpu->stat.directed_yield_successful++; 8971 8972 no_yield: 8973 return; 8974 } 8975 8976 static int complete_hypercall_exit(struct kvm_vcpu *vcpu) 8977 { 8978 u64 ret = vcpu->run->hypercall.ret; 8979 8980 if (!is_64_bit_mode(vcpu)) 8981 ret = (u32)ret; 8982 kvm_rax_write(vcpu, ret); 8983 ++vcpu->stat.hypercalls; 8984 return kvm_skip_emulated_instruction(vcpu); 8985 } 8986 8987 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 8988 { 8989 unsigned long nr, a0, a1, a2, a3, ret; 8990 int op_64_bit; 8991 8992 if (kvm_xen_hypercall_enabled(vcpu->kvm)) 8993 return kvm_xen_hypercall(vcpu); 8994 8995 if (kvm_hv_hypercall_enabled(vcpu)) 8996 return kvm_hv_hypercall(vcpu); 8997 8998 nr = kvm_rax_read(vcpu); 8999 a0 = kvm_rbx_read(vcpu); 9000 a1 = kvm_rcx_read(vcpu); 9001 a2 = kvm_rdx_read(vcpu); 9002 a3 = kvm_rsi_read(vcpu); 9003 9004 trace_kvm_hypercall(nr, a0, a1, a2, a3); 9005 9006 op_64_bit = is_64_bit_hypercall(vcpu); 9007 if (!op_64_bit) { 9008 nr &= 0xFFFFFFFF; 9009 a0 &= 0xFFFFFFFF; 9010 a1 &= 0xFFFFFFFF; 9011 a2 &= 0xFFFFFFFF; 9012 a3 &= 0xFFFFFFFF; 9013 } 9014 9015 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { 9016 ret = -KVM_EPERM; 9017 goto out; 9018 } 9019 9020 ret = -KVM_ENOSYS; 9021 9022 switch (nr) { 9023 case KVM_HC_VAPIC_POLL_IRQ: 9024 ret = 0; 9025 break; 9026 case KVM_HC_KICK_CPU: 9027 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) 9028 break; 9029 9030 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 9031 kvm_sched_yield(vcpu, a1); 9032 ret = 0; 9033 break; 9034 #ifdef CONFIG_X86_64 9035 case KVM_HC_CLOCK_PAIRING: 9036 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 9037 break; 9038 #endif 9039 case KVM_HC_SEND_IPI: 9040 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) 9041 break; 9042 9043 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 9044 break; 9045 case KVM_HC_SCHED_YIELD: 9046 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) 9047 break; 9048 9049 kvm_sched_yield(vcpu, a0); 9050 ret = 0; 9051 break; 9052 case KVM_HC_MAP_GPA_RANGE: { 9053 u64 gpa = a0, npages = a1, attrs = a2; 9054 9055 ret = -KVM_ENOSYS; 9056 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE))) 9057 break; 9058 9059 if (!PAGE_ALIGNED(gpa) || !npages || 9060 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) { 9061 ret = -KVM_EINVAL; 9062 break; 9063 } 9064 9065 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL; 9066 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE; 9067 vcpu->run->hypercall.args[0] = gpa; 9068 vcpu->run->hypercall.args[1] = npages; 9069 vcpu->run->hypercall.args[2] = attrs; 9070 vcpu->run->hypercall.longmode = op_64_bit; 9071 vcpu->arch.complete_userspace_io = complete_hypercall_exit; 9072 return 0; 9073 } 9074 default: 9075 ret = -KVM_ENOSYS; 9076 break; 9077 } 9078 out: 9079 if (!op_64_bit) 9080 ret = (u32)ret; 9081 kvm_rax_write(vcpu, ret); 9082 9083 ++vcpu->stat.hypercalls; 9084 return kvm_skip_emulated_instruction(vcpu); 9085 } 9086 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 9087 9088 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 9089 { 9090 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 9091 char instruction[3]; 9092 unsigned long rip = kvm_rip_read(vcpu); 9093 9094 static_call(kvm_x86_patch_hypercall)(vcpu, instruction); 9095 9096 return emulator_write_emulated(ctxt, rip, instruction, 3, 9097 &ctxt->exception); 9098 } 9099 9100 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 9101 { 9102 return vcpu->run->request_interrupt_window && 9103 likely(!pic_in_kernel(vcpu->kvm)); 9104 } 9105 9106 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 9107 { 9108 struct kvm_run *kvm_run = vcpu->run; 9109 9110 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu); 9111 kvm_run->cr8 = kvm_get_cr8(vcpu); 9112 kvm_run->apic_base = kvm_get_apic_base(vcpu); 9113 9114 /* 9115 * The call to kvm_ready_for_interrupt_injection() may end up in 9116 * kvm_xen_has_interrupt() which may require the srcu lock to be 9117 * held, to protect against changes in the vcpu_info address. 9118 */ 9119 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9120 kvm_run->ready_for_interrupt_injection = 9121 pic_in_kernel(vcpu->kvm) || 9122 kvm_vcpu_ready_for_interrupt_injection(vcpu); 9123 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 9124 9125 if (is_smm(vcpu)) 9126 kvm_run->flags |= KVM_RUN_X86_SMM; 9127 } 9128 9129 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 9130 { 9131 int max_irr, tpr; 9132 9133 if (!kvm_x86_ops.update_cr8_intercept) 9134 return; 9135 9136 if (!lapic_in_kernel(vcpu)) 9137 return; 9138 9139 if (vcpu->arch.apicv_active) 9140 return; 9141 9142 if (!vcpu->arch.apic->vapic_addr) 9143 max_irr = kvm_lapic_find_highest_irr(vcpu); 9144 else 9145 max_irr = -1; 9146 9147 if (max_irr != -1) 9148 max_irr >>= 4; 9149 9150 tpr = kvm_lapic_get_cr8(vcpu); 9151 9152 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); 9153 } 9154 9155 9156 int kvm_check_nested_events(struct kvm_vcpu *vcpu) 9157 { 9158 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 9159 kvm_x86_ops.nested_ops->triple_fault(vcpu); 9160 return 1; 9161 } 9162 9163 return kvm_x86_ops.nested_ops->check_events(vcpu); 9164 } 9165 9166 static void kvm_inject_exception(struct kvm_vcpu *vcpu) 9167 { 9168 if (vcpu->arch.exception.error_code && !is_protmode(vcpu)) 9169 vcpu->arch.exception.error_code = false; 9170 static_call(kvm_x86_queue_exception)(vcpu); 9171 } 9172 9173 static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) 9174 { 9175 int r; 9176 bool can_inject = true; 9177 9178 /* try to reinject previous events if any */ 9179 9180 if (vcpu->arch.exception.injected) { 9181 kvm_inject_exception(vcpu); 9182 can_inject = false; 9183 } 9184 /* 9185 * Do not inject an NMI or interrupt if there is a pending 9186 * exception. Exceptions and interrupts are recognized at 9187 * instruction boundaries, i.e. the start of an instruction. 9188 * Trap-like exceptions, e.g. #DB, have higher priority than 9189 * NMIs and interrupts, i.e. traps are recognized before an 9190 * NMI/interrupt that's pending on the same instruction. 9191 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 9192 * priority, but are only generated (pended) during instruction 9193 * execution, i.e. a pending fault-like exception means the 9194 * fault occurred on the *previous* instruction and must be 9195 * serviced prior to recognizing any new events in order to 9196 * fully complete the previous instruction. 9197 */ 9198 else if (!vcpu->arch.exception.pending) { 9199 if (vcpu->arch.nmi_injected) { 9200 static_call(kvm_x86_set_nmi)(vcpu); 9201 can_inject = false; 9202 } else if (vcpu->arch.interrupt.injected) { 9203 static_call(kvm_x86_set_irq)(vcpu); 9204 can_inject = false; 9205 } 9206 } 9207 9208 WARN_ON_ONCE(vcpu->arch.exception.injected && 9209 vcpu->arch.exception.pending); 9210 9211 /* 9212 * Call check_nested_events() even if we reinjected a previous event 9213 * in order for caller to determine if it should require immediate-exit 9214 * from L2 to L1 due to pending L1 events which require exit 9215 * from L2 to L1. 9216 */ 9217 if (is_guest_mode(vcpu)) { 9218 r = kvm_check_nested_events(vcpu); 9219 if (r < 0) 9220 goto out; 9221 } 9222 9223 /* try to inject new event if pending */ 9224 if (vcpu->arch.exception.pending) { 9225 trace_kvm_inj_exception(vcpu->arch.exception.nr, 9226 vcpu->arch.exception.has_error_code, 9227 vcpu->arch.exception.error_code); 9228 9229 vcpu->arch.exception.pending = false; 9230 vcpu->arch.exception.injected = true; 9231 9232 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 9233 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 9234 X86_EFLAGS_RF); 9235 9236 if (vcpu->arch.exception.nr == DB_VECTOR) { 9237 kvm_deliver_exception_payload(vcpu); 9238 if (vcpu->arch.dr7 & DR7_GD) { 9239 vcpu->arch.dr7 &= ~DR7_GD; 9240 kvm_update_dr7(vcpu); 9241 } 9242 } 9243 9244 kvm_inject_exception(vcpu); 9245 can_inject = false; 9246 } 9247 9248 /* Don't inject interrupts if the user asked to avoid doing so */ 9249 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) 9250 return 0; 9251 9252 /* 9253 * Finally, inject interrupt events. If an event cannot be injected 9254 * due to architectural conditions (e.g. IF=0) a window-open exit 9255 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending 9256 * and can architecturally be injected, but we cannot do it right now: 9257 * an interrupt could have arrived just now and we have to inject it 9258 * as a vmexit, or there could already an event in the queue, which is 9259 * indicated by can_inject. In that case we request an immediate exit 9260 * in order to make progress and get back here for another iteration. 9261 * The kvm_x86_ops hooks communicate this by returning -EBUSY. 9262 */ 9263 if (vcpu->arch.smi_pending) { 9264 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; 9265 if (r < 0) 9266 goto out; 9267 if (r) { 9268 vcpu->arch.smi_pending = false; 9269 ++vcpu->arch.smi_count; 9270 enter_smm(vcpu); 9271 can_inject = false; 9272 } else 9273 static_call(kvm_x86_enable_smi_window)(vcpu); 9274 } 9275 9276 if (vcpu->arch.nmi_pending) { 9277 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; 9278 if (r < 0) 9279 goto out; 9280 if (r) { 9281 --vcpu->arch.nmi_pending; 9282 vcpu->arch.nmi_injected = true; 9283 static_call(kvm_x86_set_nmi)(vcpu); 9284 can_inject = false; 9285 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); 9286 } 9287 if (vcpu->arch.nmi_pending) 9288 static_call(kvm_x86_enable_nmi_window)(vcpu); 9289 } 9290 9291 if (kvm_cpu_has_injectable_intr(vcpu)) { 9292 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; 9293 if (r < 0) 9294 goto out; 9295 if (r) { 9296 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); 9297 static_call(kvm_x86_set_irq)(vcpu); 9298 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); 9299 } 9300 if (kvm_cpu_has_injectable_intr(vcpu)) 9301 static_call(kvm_x86_enable_irq_window)(vcpu); 9302 } 9303 9304 if (is_guest_mode(vcpu) && 9305 kvm_x86_ops.nested_ops->hv_timer_pending && 9306 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 9307 *req_immediate_exit = true; 9308 9309 WARN_ON(vcpu->arch.exception.pending); 9310 return 0; 9311 9312 out: 9313 if (r == -EBUSY) { 9314 *req_immediate_exit = true; 9315 r = 0; 9316 } 9317 return r; 9318 } 9319 9320 static void process_nmi(struct kvm_vcpu *vcpu) 9321 { 9322 unsigned limit = 2; 9323 9324 /* 9325 * x86 is limited to one NMI running, and one NMI pending after it. 9326 * If an NMI is already in progress, limit further NMIs to just one. 9327 * Otherwise, allow two (and we'll inject the first one immediately). 9328 */ 9329 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) 9330 limit = 1; 9331 9332 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 9333 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 9334 kvm_make_request(KVM_REQ_EVENT, vcpu); 9335 } 9336 9337 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 9338 { 9339 u32 flags = 0; 9340 flags |= seg->g << 23; 9341 flags |= seg->db << 22; 9342 flags |= seg->l << 21; 9343 flags |= seg->avl << 20; 9344 flags |= seg->present << 15; 9345 flags |= seg->dpl << 13; 9346 flags |= seg->s << 12; 9347 flags |= seg->type << 8; 9348 return flags; 9349 } 9350 9351 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 9352 { 9353 struct kvm_segment seg; 9354 int offset; 9355 9356 kvm_get_segment(vcpu, &seg, n); 9357 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 9358 9359 if (n < 3) 9360 offset = 0x7f84 + n * 12; 9361 else 9362 offset = 0x7f2c + (n - 3) * 12; 9363 9364 put_smstate(u32, buf, offset + 8, seg.base); 9365 put_smstate(u32, buf, offset + 4, seg.limit); 9366 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 9367 } 9368 9369 #ifdef CONFIG_X86_64 9370 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 9371 { 9372 struct kvm_segment seg; 9373 int offset; 9374 u16 flags; 9375 9376 kvm_get_segment(vcpu, &seg, n); 9377 offset = 0x7e00 + n * 16; 9378 9379 flags = enter_smm_get_segment_flags(&seg) >> 8; 9380 put_smstate(u16, buf, offset, seg.selector); 9381 put_smstate(u16, buf, offset + 2, flags); 9382 put_smstate(u32, buf, offset + 4, seg.limit); 9383 put_smstate(u64, buf, offset + 8, seg.base); 9384 } 9385 #endif 9386 9387 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 9388 { 9389 struct desc_ptr dt; 9390 struct kvm_segment seg; 9391 unsigned long val; 9392 int i; 9393 9394 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 9395 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 9396 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 9397 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 9398 9399 for (i = 0; i < 8; i++) 9400 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i)); 9401 9402 kvm_get_dr(vcpu, 6, &val); 9403 put_smstate(u32, buf, 0x7fcc, (u32)val); 9404 kvm_get_dr(vcpu, 7, &val); 9405 put_smstate(u32, buf, 0x7fc8, (u32)val); 9406 9407 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 9408 put_smstate(u32, buf, 0x7fc4, seg.selector); 9409 put_smstate(u32, buf, 0x7f64, seg.base); 9410 put_smstate(u32, buf, 0x7f60, seg.limit); 9411 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 9412 9413 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 9414 put_smstate(u32, buf, 0x7fc0, seg.selector); 9415 put_smstate(u32, buf, 0x7f80, seg.base); 9416 put_smstate(u32, buf, 0x7f7c, seg.limit); 9417 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 9418 9419 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9420 put_smstate(u32, buf, 0x7f74, dt.address); 9421 put_smstate(u32, buf, 0x7f70, dt.size); 9422 9423 static_call(kvm_x86_get_idt)(vcpu, &dt); 9424 put_smstate(u32, buf, 0x7f58, dt.address); 9425 put_smstate(u32, buf, 0x7f54, dt.size); 9426 9427 for (i = 0; i < 6; i++) 9428 enter_smm_save_seg_32(vcpu, buf, i); 9429 9430 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 9431 9432 /* revision id */ 9433 put_smstate(u32, buf, 0x7efc, 0x00020000); 9434 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 9435 } 9436 9437 #ifdef CONFIG_X86_64 9438 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 9439 { 9440 struct desc_ptr dt; 9441 struct kvm_segment seg; 9442 unsigned long val; 9443 int i; 9444 9445 for (i = 0; i < 16; i++) 9446 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i)); 9447 9448 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 9449 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 9450 9451 kvm_get_dr(vcpu, 6, &val); 9452 put_smstate(u64, buf, 0x7f68, val); 9453 kvm_get_dr(vcpu, 7, &val); 9454 put_smstate(u64, buf, 0x7f60, val); 9455 9456 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 9457 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 9458 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 9459 9460 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 9461 9462 /* revision id */ 9463 put_smstate(u32, buf, 0x7efc, 0x00020064); 9464 9465 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 9466 9467 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 9468 put_smstate(u16, buf, 0x7e90, seg.selector); 9469 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 9470 put_smstate(u32, buf, 0x7e94, seg.limit); 9471 put_smstate(u64, buf, 0x7e98, seg.base); 9472 9473 static_call(kvm_x86_get_idt)(vcpu, &dt); 9474 put_smstate(u32, buf, 0x7e84, dt.size); 9475 put_smstate(u64, buf, 0x7e88, dt.address); 9476 9477 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 9478 put_smstate(u16, buf, 0x7e70, seg.selector); 9479 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 9480 put_smstate(u32, buf, 0x7e74, seg.limit); 9481 put_smstate(u64, buf, 0x7e78, seg.base); 9482 9483 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9484 put_smstate(u32, buf, 0x7e64, dt.size); 9485 put_smstate(u64, buf, 0x7e68, dt.address); 9486 9487 for (i = 0; i < 6; i++) 9488 enter_smm_save_seg_64(vcpu, buf, i); 9489 } 9490 #endif 9491 9492 static void enter_smm(struct kvm_vcpu *vcpu) 9493 { 9494 struct kvm_segment cs, ds; 9495 struct desc_ptr dt; 9496 unsigned long cr0; 9497 char buf[512]; 9498 9499 memset(buf, 0, 512); 9500 #ifdef CONFIG_X86_64 9501 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 9502 enter_smm_save_state_64(vcpu, buf); 9503 else 9504 #endif 9505 enter_smm_save_state_32(vcpu, buf); 9506 9507 /* 9508 * Give enter_smm() a chance to make ISA-specific changes to the vCPU 9509 * state (e.g. leave guest mode) after we've saved the state into the 9510 * SMM state-save area. 9511 */ 9512 static_call(kvm_x86_enter_smm)(vcpu, buf); 9513 9514 kvm_smm_changed(vcpu, true); 9515 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 9516 9517 if (static_call(kvm_x86_get_nmi_mask)(vcpu)) 9518 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 9519 else 9520 static_call(kvm_x86_set_nmi_mask)(vcpu, true); 9521 9522 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 9523 kvm_rip_write(vcpu, 0x8000); 9524 9525 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 9526 static_call(kvm_x86_set_cr0)(vcpu, cr0); 9527 vcpu->arch.cr0 = cr0; 9528 9529 static_call(kvm_x86_set_cr4)(vcpu, 0); 9530 9531 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 9532 dt.address = dt.size = 0; 9533 static_call(kvm_x86_set_idt)(vcpu, &dt); 9534 9535 kvm_set_dr(vcpu, 7, DR7_FIXED_1); 9536 9537 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 9538 cs.base = vcpu->arch.smbase; 9539 9540 ds.selector = 0; 9541 ds.base = 0; 9542 9543 cs.limit = ds.limit = 0xffffffff; 9544 cs.type = ds.type = 0x3; 9545 cs.dpl = ds.dpl = 0; 9546 cs.db = ds.db = 0; 9547 cs.s = ds.s = 1; 9548 cs.l = ds.l = 0; 9549 cs.g = ds.g = 1; 9550 cs.avl = ds.avl = 0; 9551 cs.present = ds.present = 1; 9552 cs.unusable = ds.unusable = 0; 9553 cs.padding = ds.padding = 0; 9554 9555 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 9556 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 9557 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 9558 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 9559 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 9560 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 9561 9562 #ifdef CONFIG_X86_64 9563 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 9564 static_call(kvm_x86_set_efer)(vcpu, 0); 9565 #endif 9566 9567 kvm_update_cpuid_runtime(vcpu); 9568 kvm_mmu_reset_context(vcpu); 9569 } 9570 9571 static void process_smi(struct kvm_vcpu *vcpu) 9572 { 9573 vcpu->arch.smi_pending = true; 9574 kvm_make_request(KVM_REQ_EVENT, vcpu); 9575 } 9576 9577 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 9578 unsigned long *vcpu_bitmap) 9579 { 9580 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap); 9581 } 9582 9583 void kvm_make_scan_ioapic_request(struct kvm *kvm) 9584 { 9585 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 9586 } 9587 9588 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 9589 { 9590 bool activate; 9591 9592 if (!lapic_in_kernel(vcpu)) 9593 return; 9594 9595 down_read(&vcpu->kvm->arch.apicv_update_lock); 9596 9597 activate = kvm_apicv_activated(vcpu->kvm); 9598 if (vcpu->arch.apicv_active == activate) 9599 goto out; 9600 9601 vcpu->arch.apicv_active = activate; 9602 kvm_apic_update_apicv(vcpu); 9603 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); 9604 9605 /* 9606 * When APICv gets disabled, we may still have injected interrupts 9607 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was 9608 * still active when the interrupt got accepted. Make sure 9609 * inject_pending_event() is called to check for that. 9610 */ 9611 if (!vcpu->arch.apicv_active) 9612 kvm_make_request(KVM_REQ_EVENT, vcpu); 9613 9614 out: 9615 up_read(&vcpu->kvm->arch.apicv_update_lock); 9616 } 9617 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); 9618 9619 void __kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) 9620 { 9621 unsigned long old, new; 9622 9623 lockdep_assert_held_write(&kvm->arch.apicv_update_lock); 9624 9625 if (!kvm_x86_ops.check_apicv_inhibit_reasons || 9626 !static_call(kvm_x86_check_apicv_inhibit_reasons)(bit)) 9627 return; 9628 9629 old = new = kvm->arch.apicv_inhibit_reasons; 9630 9631 if (activate) 9632 __clear_bit(bit, &new); 9633 else 9634 __set_bit(bit, &new); 9635 9636 if (!!old != !!new) { 9637 trace_kvm_apicv_update_request(activate, bit); 9638 /* 9639 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid 9640 * false positives in the sanity check WARN in svm_vcpu_run(). 9641 * This task will wait for all vCPUs to ack the kick IRQ before 9642 * updating apicv_inhibit_reasons, and all other vCPUs will 9643 * block on acquiring apicv_update_lock so that vCPUs can't 9644 * redo svm_vcpu_run() without seeing the new inhibit state. 9645 * 9646 * Note, holding apicv_update_lock and taking it in the read 9647 * side (handling the request) also prevents other vCPUs from 9648 * servicing the request with a stale apicv_inhibit_reasons. 9649 */ 9650 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); 9651 kvm->arch.apicv_inhibit_reasons = new; 9652 if (new) { 9653 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE); 9654 kvm_zap_gfn_range(kvm, gfn, gfn+1); 9655 } 9656 } else 9657 kvm->arch.apicv_inhibit_reasons = new; 9658 } 9659 EXPORT_SYMBOL_GPL(__kvm_request_apicv_update); 9660 9661 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) 9662 { 9663 down_write(&kvm->arch.apicv_update_lock); 9664 __kvm_request_apicv_update(kvm, activate, bit); 9665 up_write(&kvm->arch.apicv_update_lock); 9666 } 9667 EXPORT_SYMBOL_GPL(kvm_request_apicv_update); 9668 9669 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 9670 { 9671 if (!kvm_apic_present(vcpu)) 9672 return; 9673 9674 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 9675 9676 if (irqchip_split(vcpu->kvm)) 9677 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 9678 else { 9679 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 9680 if (ioapic_in_kernel(vcpu->kvm)) 9681 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 9682 } 9683 9684 if (is_guest_mode(vcpu)) 9685 vcpu->arch.load_eoi_exitmap_pending = true; 9686 else 9687 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 9688 } 9689 9690 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 9691 { 9692 u64 eoi_exit_bitmap[4]; 9693 9694 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 9695 return; 9696 9697 if (to_hv_vcpu(vcpu)) { 9698 bitmap_or((ulong *)eoi_exit_bitmap, 9699 vcpu->arch.ioapic_handled_vectors, 9700 to_hv_synic(vcpu)->vec_bitmap, 256); 9701 static_call(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); 9702 return; 9703 } 9704 9705 static_call(kvm_x86_load_eoi_exitmap)( 9706 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors); 9707 } 9708 9709 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 9710 unsigned long start, unsigned long end) 9711 { 9712 unsigned long apic_address; 9713 9714 /* 9715 * The physical address of apic access page is stored in the VMCS. 9716 * Update it when it becomes invalid. 9717 */ 9718 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 9719 if (start <= apic_address && apic_address < end) 9720 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 9721 } 9722 9723 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 9724 { 9725 if (!lapic_in_kernel(vcpu)) 9726 return; 9727 9728 if (!kvm_x86_ops.set_apic_access_page_addr) 9729 return; 9730 9731 static_call(kvm_x86_set_apic_access_page_addr)(vcpu); 9732 } 9733 9734 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 9735 { 9736 smp_send_reschedule(vcpu->cpu); 9737 } 9738 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 9739 9740 /* 9741 * Returns 1 to let vcpu_run() continue the guest execution loop without 9742 * exiting to the userspace. Otherwise, the value will be returned to the 9743 * userspace. 9744 */ 9745 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 9746 { 9747 int r; 9748 bool req_int_win = 9749 dm_request_for_irq_injection(vcpu) && 9750 kvm_cpu_accept_dm_intr(vcpu); 9751 fastpath_t exit_fastpath; 9752 9753 bool req_immediate_exit = false; 9754 9755 /* Forbid vmenter if vcpu dirty ring is soft-full */ 9756 if (unlikely(vcpu->kvm->dirty_ring_size && 9757 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { 9758 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; 9759 trace_kvm_dirty_ring_exit(vcpu); 9760 r = 0; 9761 goto out; 9762 } 9763 9764 if (kvm_request_pending(vcpu)) { 9765 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) { 9766 r = -EIO; 9767 goto out; 9768 } 9769 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { 9770 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { 9771 r = 0; 9772 goto out; 9773 } 9774 } 9775 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 9776 kvm_mmu_unload(vcpu); 9777 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 9778 __kvm_migrate_timers(vcpu); 9779 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 9780 kvm_update_masterclock(vcpu->kvm); 9781 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 9782 kvm_gen_kvmclock_update(vcpu); 9783 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 9784 r = kvm_guest_time_update(vcpu); 9785 if (unlikely(r)) 9786 goto out; 9787 } 9788 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 9789 kvm_mmu_sync_roots(vcpu); 9790 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) 9791 kvm_mmu_load_pgd(vcpu); 9792 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { 9793 kvm_vcpu_flush_tlb_all(vcpu); 9794 9795 /* Flushing all ASIDs flushes the current ASID... */ 9796 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 9797 } 9798 kvm_service_local_tlb_flush_requests(vcpu); 9799 9800 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 9801 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 9802 r = 0; 9803 goto out; 9804 } 9805 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 9806 if (is_guest_mode(vcpu)) { 9807 kvm_x86_ops.nested_ops->triple_fault(vcpu); 9808 } else { 9809 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 9810 vcpu->mmio_needed = 0; 9811 r = 0; 9812 goto out; 9813 } 9814 } 9815 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 9816 /* Page is swapped out. Do synthetic halt */ 9817 vcpu->arch.apf.halted = true; 9818 r = 1; 9819 goto out; 9820 } 9821 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 9822 record_steal_time(vcpu); 9823 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 9824 process_smi(vcpu); 9825 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 9826 process_nmi(vcpu); 9827 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 9828 kvm_pmu_handle_event(vcpu); 9829 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 9830 kvm_pmu_deliver_pmi(vcpu); 9831 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 9832 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 9833 if (test_bit(vcpu->arch.pending_ioapic_eoi, 9834 vcpu->arch.ioapic_handled_vectors)) { 9835 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 9836 vcpu->run->eoi.vector = 9837 vcpu->arch.pending_ioapic_eoi; 9838 r = 0; 9839 goto out; 9840 } 9841 } 9842 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 9843 vcpu_scan_ioapic(vcpu); 9844 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 9845 vcpu_load_eoi_exitmap(vcpu); 9846 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 9847 kvm_vcpu_reload_apic_access_page(vcpu); 9848 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 9849 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 9850 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 9851 r = 0; 9852 goto out; 9853 } 9854 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 9855 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 9856 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 9857 r = 0; 9858 goto out; 9859 } 9860 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 9861 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); 9862 9863 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 9864 vcpu->run->hyperv = hv_vcpu->exit; 9865 r = 0; 9866 goto out; 9867 } 9868 9869 /* 9870 * KVM_REQ_HV_STIMER has to be processed after 9871 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 9872 * depend on the guest clock being up-to-date 9873 */ 9874 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 9875 kvm_hv_process_stimers(vcpu); 9876 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 9877 kvm_vcpu_update_apicv(vcpu); 9878 if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) 9879 kvm_check_async_pf_completion(vcpu); 9880 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) 9881 static_call(kvm_x86_msr_filter_changed)(vcpu); 9882 9883 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) 9884 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); 9885 } 9886 9887 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || 9888 kvm_xen_has_interrupt(vcpu)) { 9889 ++vcpu->stat.req_event; 9890 r = kvm_apic_accept_events(vcpu); 9891 if (r < 0) { 9892 r = 0; 9893 goto out; 9894 } 9895 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 9896 r = 1; 9897 goto out; 9898 } 9899 9900 r = inject_pending_event(vcpu, &req_immediate_exit); 9901 if (r < 0) { 9902 r = 0; 9903 goto out; 9904 } 9905 if (req_int_win) 9906 static_call(kvm_x86_enable_irq_window)(vcpu); 9907 9908 if (kvm_lapic_enabled(vcpu)) { 9909 update_cr8_intercept(vcpu); 9910 kvm_lapic_sync_to_vapic(vcpu); 9911 } 9912 } 9913 9914 r = kvm_mmu_reload(vcpu); 9915 if (unlikely(r)) { 9916 goto cancel_injection; 9917 } 9918 9919 preempt_disable(); 9920 9921 static_call(kvm_x86_prepare_guest_switch)(vcpu); 9922 9923 /* 9924 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 9925 * IPI are then delayed after guest entry, which ensures that they 9926 * result in virtual interrupt delivery. 9927 */ 9928 local_irq_disable(); 9929 vcpu->mode = IN_GUEST_MODE; 9930 9931 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 9932 9933 /* 9934 * 1) We should set ->mode before checking ->requests. Please see 9935 * the comment in kvm_vcpu_exiting_guest_mode(). 9936 * 9937 * 2) For APICv, we should set ->mode before checking PID.ON. This 9938 * pairs with the memory barrier implicit in pi_test_and_set_on 9939 * (see vmx_deliver_posted_interrupt). 9940 * 9941 * 3) This also orders the write to mode from any reads to the page 9942 * tables done while the VCPU is running. Please see the comment 9943 * in kvm_flush_remote_tlbs. 9944 */ 9945 smp_mb__after_srcu_read_unlock(); 9946 9947 /* 9948 * This handles the case where a posted interrupt was 9949 * notified with kvm_vcpu_kick. Assigned devices can 9950 * use the POSTED_INTR_VECTOR even if APICv is disabled, 9951 * so do it even if APICv is disabled on this vCPU. 9952 */ 9953 if (kvm_lapic_enabled(vcpu)) 9954 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 9955 9956 if (kvm_vcpu_exit_request(vcpu)) { 9957 vcpu->mode = OUTSIDE_GUEST_MODE; 9958 smp_wmb(); 9959 local_irq_enable(); 9960 preempt_enable(); 9961 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9962 r = 1; 9963 goto cancel_injection; 9964 } 9965 9966 if (req_immediate_exit) { 9967 kvm_make_request(KVM_REQ_EVENT, vcpu); 9968 static_call(kvm_x86_request_immediate_exit)(vcpu); 9969 } 9970 9971 fpregs_assert_state_consistent(); 9972 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 9973 switch_fpu_return(); 9974 9975 if (vcpu->arch.guest_fpu.xfd_err) 9976 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err); 9977 9978 if (unlikely(vcpu->arch.switch_db_regs)) { 9979 set_debugreg(0, 7); 9980 set_debugreg(vcpu->arch.eff_db[0], 0); 9981 set_debugreg(vcpu->arch.eff_db[1], 1); 9982 set_debugreg(vcpu->arch.eff_db[2], 2); 9983 set_debugreg(vcpu->arch.eff_db[3], 3); 9984 } else if (unlikely(hw_breakpoint_active())) { 9985 set_debugreg(0, 7); 9986 } 9987 9988 for (;;) { 9989 /* 9990 * Assert that vCPU vs. VM APICv state is consistent. An APICv 9991 * update must kick and wait for all vCPUs before toggling the 9992 * per-VM state, and responsing vCPUs must wait for the update 9993 * to complete before servicing KVM_REQ_APICV_UPDATE. 9994 */ 9995 WARN_ON_ONCE(kvm_apicv_activated(vcpu->kvm) != kvm_vcpu_apicv_active(vcpu)); 9996 9997 exit_fastpath = static_call(kvm_x86_run)(vcpu); 9998 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) 9999 break; 10000 10001 if (kvm_lapic_enabled(vcpu)) 10002 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 10003 10004 if (unlikely(kvm_vcpu_exit_request(vcpu))) { 10005 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; 10006 break; 10007 } 10008 } 10009 10010 /* 10011 * Do this here before restoring debug registers on the host. And 10012 * since we do this before handling the vmexit, a DR access vmexit 10013 * can (a) read the correct value of the debug registers, (b) set 10014 * KVM_DEBUGREG_WONT_EXIT again. 10015 */ 10016 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 10017 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 10018 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); 10019 kvm_update_dr0123(vcpu); 10020 kvm_update_dr7(vcpu); 10021 } 10022 10023 /* 10024 * If the guest has used debug registers, at least dr7 10025 * will be disabled while returning to the host. 10026 * If we don't have active breakpoints in the host, we don't 10027 * care about the messed up debug address registers. But if 10028 * we have some of them active, restore the old state. 10029 */ 10030 if (hw_breakpoint_active()) 10031 hw_breakpoint_restore(); 10032 10033 vcpu->arch.last_vmentry_cpu = vcpu->cpu; 10034 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 10035 10036 vcpu->mode = OUTSIDE_GUEST_MODE; 10037 smp_wmb(); 10038 10039 /* 10040 * Sync xfd before calling handle_exit_irqoff() which may 10041 * rely on the fact that guest_fpu::xfd is up-to-date (e.g. 10042 * in #NM irqoff handler). 10043 */ 10044 if (vcpu->arch.xfd_no_write_intercept) 10045 fpu_sync_guest_vmexit_xfd_state(); 10046 10047 static_call(kvm_x86_handle_exit_irqoff)(vcpu); 10048 10049 if (vcpu->arch.guest_fpu.xfd_err) 10050 wrmsrl(MSR_IA32_XFD_ERR, 0); 10051 10052 /* 10053 * Consume any pending interrupts, including the possible source of 10054 * VM-Exit on SVM and any ticks that occur between VM-Exit and now. 10055 * An instruction is required after local_irq_enable() to fully unblock 10056 * interrupts on processors that implement an interrupt shadow, the 10057 * stat.exits increment will do nicely. 10058 */ 10059 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ); 10060 local_irq_enable(); 10061 ++vcpu->stat.exits; 10062 local_irq_disable(); 10063 kvm_after_interrupt(vcpu); 10064 10065 /* 10066 * Wait until after servicing IRQs to account guest time so that any 10067 * ticks that occurred while running the guest are properly accounted 10068 * to the guest. Waiting until IRQs are enabled degrades the accuracy 10069 * of accounting via context tracking, but the loss of accuracy is 10070 * acceptable for all known use cases. 10071 */ 10072 vtime_account_guest_exit(); 10073 10074 if (lapic_in_kernel(vcpu)) { 10075 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; 10076 if (delta != S64_MIN) { 10077 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); 10078 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; 10079 } 10080 } 10081 10082 local_irq_enable(); 10083 preempt_enable(); 10084 10085 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 10086 10087 /* 10088 * Profile KVM exit RIPs: 10089 */ 10090 if (unlikely(prof_on == KVM_PROFILING)) { 10091 unsigned long rip = kvm_rip_read(vcpu); 10092 profile_hit(KVM_PROFILING, (void *)rip); 10093 } 10094 10095 if (unlikely(vcpu->arch.tsc_always_catchup)) 10096 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 10097 10098 if (vcpu->arch.apic_attention) 10099 kvm_lapic_sync_from_vapic(vcpu); 10100 10101 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); 10102 return r; 10103 10104 cancel_injection: 10105 if (req_immediate_exit) 10106 kvm_make_request(KVM_REQ_EVENT, vcpu); 10107 static_call(kvm_x86_cancel_injection)(vcpu); 10108 if (unlikely(vcpu->arch.apic_attention)) 10109 kvm_lapic_sync_from_vapic(vcpu); 10110 out: 10111 return r; 10112 } 10113 10114 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 10115 { 10116 if (!kvm_arch_vcpu_runnable(vcpu) && 10117 (!kvm_x86_ops.pre_block || static_call(kvm_x86_pre_block)(vcpu) == 0)) { 10118 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 10119 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) 10120 kvm_vcpu_halt(vcpu); 10121 else 10122 kvm_vcpu_block(vcpu); 10123 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 10124 10125 if (kvm_x86_ops.post_block) 10126 static_call(kvm_x86_post_block)(vcpu); 10127 10128 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 10129 return 1; 10130 } 10131 10132 if (kvm_apic_accept_events(vcpu) < 0) 10133 return 0; 10134 switch(vcpu->arch.mp_state) { 10135 case KVM_MP_STATE_HALTED: 10136 case KVM_MP_STATE_AP_RESET_HOLD: 10137 vcpu->arch.pv.pv_unhalted = false; 10138 vcpu->arch.mp_state = 10139 KVM_MP_STATE_RUNNABLE; 10140 fallthrough; 10141 case KVM_MP_STATE_RUNNABLE: 10142 vcpu->arch.apf.halted = false; 10143 break; 10144 case KVM_MP_STATE_INIT_RECEIVED: 10145 break; 10146 default: 10147 return -EINTR; 10148 } 10149 return 1; 10150 } 10151 10152 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 10153 { 10154 if (is_guest_mode(vcpu)) 10155 kvm_check_nested_events(vcpu); 10156 10157 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 10158 !vcpu->arch.apf.halted); 10159 } 10160 10161 static int vcpu_run(struct kvm_vcpu *vcpu) 10162 { 10163 int r; 10164 struct kvm *kvm = vcpu->kvm; 10165 10166 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 10167 vcpu->arch.l1tf_flush_l1d = true; 10168 10169 for (;;) { 10170 if (kvm_vcpu_running(vcpu)) { 10171 r = vcpu_enter_guest(vcpu); 10172 } else { 10173 r = vcpu_block(kvm, vcpu); 10174 } 10175 10176 if (r <= 0) 10177 break; 10178 10179 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); 10180 if (kvm_cpu_has_pending_timer(vcpu)) 10181 kvm_inject_pending_timer_irqs(vcpu); 10182 10183 if (dm_request_for_irq_injection(vcpu) && 10184 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 10185 r = 0; 10186 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 10187 ++vcpu->stat.request_irq_exits; 10188 break; 10189 } 10190 10191 if (__xfer_to_guest_mode_work_pending()) { 10192 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 10193 r = xfer_to_guest_mode_handle_work(vcpu); 10194 if (r) 10195 return r; 10196 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 10197 } 10198 } 10199 10200 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 10201 10202 return r; 10203 } 10204 10205 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 10206 { 10207 int r; 10208 10209 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 10210 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 10211 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 10212 return r; 10213 } 10214 10215 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 10216 { 10217 BUG_ON(!vcpu->arch.pio.count); 10218 10219 return complete_emulated_io(vcpu); 10220 } 10221 10222 /* 10223 * Implements the following, as a state machine: 10224 * 10225 * read: 10226 * for each fragment 10227 * for each mmio piece in the fragment 10228 * write gpa, len 10229 * exit 10230 * copy data 10231 * execute insn 10232 * 10233 * write: 10234 * for each fragment 10235 * for each mmio piece in the fragment 10236 * write gpa, len 10237 * copy data 10238 * exit 10239 */ 10240 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 10241 { 10242 struct kvm_run *run = vcpu->run; 10243 struct kvm_mmio_fragment *frag; 10244 unsigned len; 10245 10246 BUG_ON(!vcpu->mmio_needed); 10247 10248 /* Complete previous fragment */ 10249 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 10250 len = min(8u, frag->len); 10251 if (!vcpu->mmio_is_write) 10252 memcpy(frag->data, run->mmio.data, len); 10253 10254 if (frag->len <= 8) { 10255 /* Switch to the next fragment. */ 10256 frag++; 10257 vcpu->mmio_cur_fragment++; 10258 } else { 10259 /* Go forward to the next mmio piece. */ 10260 frag->data += len; 10261 frag->gpa += len; 10262 frag->len -= len; 10263 } 10264 10265 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 10266 vcpu->mmio_needed = 0; 10267 10268 /* FIXME: return into emulator if single-stepping. */ 10269 if (vcpu->mmio_is_write) 10270 return 1; 10271 vcpu->mmio_read_completed = 1; 10272 return complete_emulated_io(vcpu); 10273 } 10274 10275 run->exit_reason = KVM_EXIT_MMIO; 10276 run->mmio.phys_addr = frag->gpa; 10277 if (vcpu->mmio_is_write) 10278 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 10279 run->mmio.len = min(8u, frag->len); 10280 run->mmio.is_write = vcpu->mmio_is_write; 10281 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 10282 return 0; 10283 } 10284 10285 /* Swap (qemu) user FPU context for the guest FPU context. */ 10286 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 10287 { 10288 /* 10289 * Exclude PKRU from restore as restored separately in 10290 * kvm_x86_ops.run(). 10291 */ 10292 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true); 10293 trace_kvm_fpu(1); 10294 } 10295 10296 /* When vcpu_run ends, restore user space FPU context. */ 10297 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 10298 { 10299 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false); 10300 ++vcpu->stat.fpu_reload; 10301 trace_kvm_fpu(0); 10302 } 10303 10304 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 10305 { 10306 struct kvm_run *kvm_run = vcpu->run; 10307 int r; 10308 10309 vcpu_load(vcpu); 10310 kvm_sigset_activate(vcpu); 10311 kvm_run->flags = 0; 10312 kvm_load_guest_fpu(vcpu); 10313 10314 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 10315 if (kvm_run->immediate_exit) { 10316 r = -EINTR; 10317 goto out; 10318 } 10319 kvm_vcpu_block(vcpu); 10320 if (kvm_apic_accept_events(vcpu) < 0) { 10321 r = 0; 10322 goto out; 10323 } 10324 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 10325 r = -EAGAIN; 10326 if (signal_pending(current)) { 10327 r = -EINTR; 10328 kvm_run->exit_reason = KVM_EXIT_INTR; 10329 ++vcpu->stat.signal_exits; 10330 } 10331 goto out; 10332 } 10333 10334 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) || 10335 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) { 10336 r = -EINVAL; 10337 goto out; 10338 } 10339 10340 if (kvm_run->kvm_dirty_regs) { 10341 r = sync_regs(vcpu); 10342 if (r != 0) 10343 goto out; 10344 } 10345 10346 /* re-sync apic's tpr */ 10347 if (!lapic_in_kernel(vcpu)) { 10348 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 10349 r = -EINVAL; 10350 goto out; 10351 } 10352 } 10353 10354 if (unlikely(vcpu->arch.complete_userspace_io)) { 10355 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 10356 vcpu->arch.complete_userspace_io = NULL; 10357 r = cui(vcpu); 10358 if (r <= 0) 10359 goto out; 10360 } else 10361 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 10362 10363 if (kvm_run->immediate_exit) 10364 r = -EINTR; 10365 else 10366 r = vcpu_run(vcpu); 10367 10368 out: 10369 kvm_put_guest_fpu(vcpu); 10370 if (kvm_run->kvm_valid_regs) 10371 store_regs(vcpu); 10372 post_kvm_run_save(vcpu); 10373 kvm_sigset_deactivate(vcpu); 10374 10375 vcpu_put(vcpu); 10376 return r; 10377 } 10378 10379 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10380 { 10381 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 10382 /* 10383 * We are here if userspace calls get_regs() in the middle of 10384 * instruction emulation. Registers state needs to be copied 10385 * back from emulation context to vcpu. Userspace shouldn't do 10386 * that usually, but some bad designed PV devices (vmware 10387 * backdoor interface) need this to work 10388 */ 10389 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); 10390 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 10391 } 10392 regs->rax = kvm_rax_read(vcpu); 10393 regs->rbx = kvm_rbx_read(vcpu); 10394 regs->rcx = kvm_rcx_read(vcpu); 10395 regs->rdx = kvm_rdx_read(vcpu); 10396 regs->rsi = kvm_rsi_read(vcpu); 10397 regs->rdi = kvm_rdi_read(vcpu); 10398 regs->rsp = kvm_rsp_read(vcpu); 10399 regs->rbp = kvm_rbp_read(vcpu); 10400 #ifdef CONFIG_X86_64 10401 regs->r8 = kvm_r8_read(vcpu); 10402 regs->r9 = kvm_r9_read(vcpu); 10403 regs->r10 = kvm_r10_read(vcpu); 10404 regs->r11 = kvm_r11_read(vcpu); 10405 regs->r12 = kvm_r12_read(vcpu); 10406 regs->r13 = kvm_r13_read(vcpu); 10407 regs->r14 = kvm_r14_read(vcpu); 10408 regs->r15 = kvm_r15_read(vcpu); 10409 #endif 10410 10411 regs->rip = kvm_rip_read(vcpu); 10412 regs->rflags = kvm_get_rflags(vcpu); 10413 } 10414 10415 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10416 { 10417 vcpu_load(vcpu); 10418 __get_regs(vcpu, regs); 10419 vcpu_put(vcpu); 10420 return 0; 10421 } 10422 10423 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10424 { 10425 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 10426 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 10427 10428 kvm_rax_write(vcpu, regs->rax); 10429 kvm_rbx_write(vcpu, regs->rbx); 10430 kvm_rcx_write(vcpu, regs->rcx); 10431 kvm_rdx_write(vcpu, regs->rdx); 10432 kvm_rsi_write(vcpu, regs->rsi); 10433 kvm_rdi_write(vcpu, regs->rdi); 10434 kvm_rsp_write(vcpu, regs->rsp); 10435 kvm_rbp_write(vcpu, regs->rbp); 10436 #ifdef CONFIG_X86_64 10437 kvm_r8_write(vcpu, regs->r8); 10438 kvm_r9_write(vcpu, regs->r9); 10439 kvm_r10_write(vcpu, regs->r10); 10440 kvm_r11_write(vcpu, regs->r11); 10441 kvm_r12_write(vcpu, regs->r12); 10442 kvm_r13_write(vcpu, regs->r13); 10443 kvm_r14_write(vcpu, regs->r14); 10444 kvm_r15_write(vcpu, regs->r15); 10445 #endif 10446 10447 kvm_rip_write(vcpu, regs->rip); 10448 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 10449 10450 vcpu->arch.exception.pending = false; 10451 10452 kvm_make_request(KVM_REQ_EVENT, vcpu); 10453 } 10454 10455 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 10456 { 10457 vcpu_load(vcpu); 10458 __set_regs(vcpu, regs); 10459 vcpu_put(vcpu); 10460 return 0; 10461 } 10462 10463 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 10464 { 10465 struct kvm_segment cs; 10466 10467 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 10468 *db = cs.db; 10469 *l = cs.l; 10470 } 10471 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 10472 10473 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10474 { 10475 struct desc_ptr dt; 10476 10477 if (vcpu->arch.guest_state_protected) 10478 goto skip_protected_regs; 10479 10480 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 10481 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 10482 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 10483 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 10484 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 10485 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 10486 10487 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 10488 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 10489 10490 static_call(kvm_x86_get_idt)(vcpu, &dt); 10491 sregs->idt.limit = dt.size; 10492 sregs->idt.base = dt.address; 10493 static_call(kvm_x86_get_gdt)(vcpu, &dt); 10494 sregs->gdt.limit = dt.size; 10495 sregs->gdt.base = dt.address; 10496 10497 sregs->cr2 = vcpu->arch.cr2; 10498 sregs->cr3 = kvm_read_cr3(vcpu); 10499 10500 skip_protected_regs: 10501 sregs->cr0 = kvm_read_cr0(vcpu); 10502 sregs->cr4 = kvm_read_cr4(vcpu); 10503 sregs->cr8 = kvm_get_cr8(vcpu); 10504 sregs->efer = vcpu->arch.efer; 10505 sregs->apic_base = kvm_get_apic_base(vcpu); 10506 } 10507 10508 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10509 { 10510 __get_sregs_common(vcpu, sregs); 10511 10512 if (vcpu->arch.guest_state_protected) 10513 return; 10514 10515 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 10516 set_bit(vcpu->arch.interrupt.nr, 10517 (unsigned long *)sregs->interrupt_bitmap); 10518 } 10519 10520 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 10521 { 10522 int i; 10523 10524 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2); 10525 10526 if (vcpu->arch.guest_state_protected) 10527 return; 10528 10529 if (is_pae_paging(vcpu)) { 10530 for (i = 0 ; i < 4 ; i++) 10531 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i); 10532 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; 10533 } 10534 } 10535 10536 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 10537 struct kvm_sregs *sregs) 10538 { 10539 vcpu_load(vcpu); 10540 __get_sregs(vcpu, sregs); 10541 vcpu_put(vcpu); 10542 return 0; 10543 } 10544 10545 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 10546 struct kvm_mp_state *mp_state) 10547 { 10548 int r; 10549 10550 vcpu_load(vcpu); 10551 if (kvm_mpx_supported()) 10552 kvm_load_guest_fpu(vcpu); 10553 10554 r = kvm_apic_accept_events(vcpu); 10555 if (r < 0) 10556 goto out; 10557 r = 0; 10558 10559 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || 10560 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && 10561 vcpu->arch.pv.pv_unhalted) 10562 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 10563 else 10564 mp_state->mp_state = vcpu->arch.mp_state; 10565 10566 out: 10567 if (kvm_mpx_supported()) 10568 kvm_put_guest_fpu(vcpu); 10569 vcpu_put(vcpu); 10570 return r; 10571 } 10572 10573 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 10574 struct kvm_mp_state *mp_state) 10575 { 10576 int ret = -EINVAL; 10577 10578 vcpu_load(vcpu); 10579 10580 if (!lapic_in_kernel(vcpu) && 10581 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 10582 goto out; 10583 10584 /* 10585 * KVM_MP_STATE_INIT_RECEIVED means the processor is in 10586 * INIT state; latched init should be reported using 10587 * KVM_SET_VCPU_EVENTS, so reject it here. 10588 */ 10589 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && 10590 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 10591 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 10592 goto out; 10593 10594 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 10595 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 10596 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 10597 } else 10598 vcpu->arch.mp_state = mp_state->mp_state; 10599 kvm_make_request(KVM_REQ_EVENT, vcpu); 10600 10601 ret = 0; 10602 out: 10603 vcpu_put(vcpu); 10604 return ret; 10605 } 10606 10607 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 10608 int reason, bool has_error_code, u32 error_code) 10609 { 10610 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 10611 int ret; 10612 10613 init_emulate_ctxt(vcpu); 10614 10615 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 10616 has_error_code, error_code); 10617 if (ret) { 10618 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 10619 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 10620 vcpu->run->internal.ndata = 0; 10621 return 0; 10622 } 10623 10624 kvm_rip_write(vcpu, ctxt->eip); 10625 kvm_set_rflags(vcpu, ctxt->eflags); 10626 return 1; 10627 } 10628 EXPORT_SYMBOL_GPL(kvm_task_switch); 10629 10630 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10631 { 10632 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 10633 /* 10634 * When EFER.LME and CR0.PG are set, the processor is in 10635 * 64-bit mode (though maybe in a 32-bit code segment). 10636 * CR4.PAE and EFER.LMA must be set. 10637 */ 10638 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) 10639 return false; 10640 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) 10641 return false; 10642 } else { 10643 /* 10644 * Not in 64-bit mode: EFER.LMA is clear and the code 10645 * segment cannot be 64-bit. 10646 */ 10647 if (sregs->efer & EFER_LMA || sregs->cs.l) 10648 return false; 10649 } 10650 10651 return kvm_is_valid_cr4(vcpu, sregs->cr4); 10652 } 10653 10654 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs, 10655 int *mmu_reset_needed, bool update_pdptrs) 10656 { 10657 struct msr_data apic_base_msr; 10658 int idx; 10659 struct desc_ptr dt; 10660 10661 if (!kvm_is_valid_sregs(vcpu, sregs)) 10662 return -EINVAL; 10663 10664 apic_base_msr.data = sregs->apic_base; 10665 apic_base_msr.host_initiated = true; 10666 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 10667 return -EINVAL; 10668 10669 if (vcpu->arch.guest_state_protected) 10670 return 0; 10671 10672 dt.size = sregs->idt.limit; 10673 dt.address = sregs->idt.base; 10674 static_call(kvm_x86_set_idt)(vcpu, &dt); 10675 dt.size = sregs->gdt.limit; 10676 dt.address = sregs->gdt.base; 10677 static_call(kvm_x86_set_gdt)(vcpu, &dt); 10678 10679 vcpu->arch.cr2 = sregs->cr2; 10680 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 10681 vcpu->arch.cr3 = sregs->cr3; 10682 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 10683 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3); 10684 10685 kvm_set_cr8(vcpu, sregs->cr8); 10686 10687 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 10688 static_call(kvm_x86_set_efer)(vcpu, sregs->efer); 10689 10690 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 10691 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); 10692 vcpu->arch.cr0 = sregs->cr0; 10693 10694 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 10695 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); 10696 10697 if (update_pdptrs) { 10698 idx = srcu_read_lock(&vcpu->kvm->srcu); 10699 if (is_pae_paging(vcpu)) { 10700 load_pdptrs(vcpu, kvm_read_cr3(vcpu)); 10701 *mmu_reset_needed = 1; 10702 } 10703 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10704 } 10705 10706 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 10707 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 10708 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 10709 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 10710 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 10711 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 10712 10713 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 10714 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 10715 10716 update_cr8_intercept(vcpu); 10717 10718 /* Older userspace won't unhalt the vcpu on reset. */ 10719 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 10720 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 10721 !is_protmode(vcpu)) 10722 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 10723 10724 return 0; 10725 } 10726 10727 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 10728 { 10729 int pending_vec, max_bits; 10730 int mmu_reset_needed = 0; 10731 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true); 10732 10733 if (ret) 10734 return ret; 10735 10736 if (mmu_reset_needed) 10737 kvm_mmu_reset_context(vcpu); 10738 10739 max_bits = KVM_NR_INTERRUPTS; 10740 pending_vec = find_first_bit( 10741 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 10742 10743 if (pending_vec < max_bits) { 10744 kvm_queue_interrupt(vcpu, pending_vec, false); 10745 pr_debug("Set back pending irq %d\n", pending_vec); 10746 kvm_make_request(KVM_REQ_EVENT, vcpu); 10747 } 10748 return 0; 10749 } 10750 10751 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 10752 { 10753 int mmu_reset_needed = 0; 10754 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; 10755 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) && 10756 !(sregs2->efer & EFER_LMA); 10757 int i, ret; 10758 10759 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID) 10760 return -EINVAL; 10761 10762 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected)) 10763 return -EINVAL; 10764 10765 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2, 10766 &mmu_reset_needed, !valid_pdptrs); 10767 if (ret) 10768 return ret; 10769 10770 if (valid_pdptrs) { 10771 for (i = 0; i < 4 ; i++) 10772 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]); 10773 10774 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 10775 mmu_reset_needed = 1; 10776 vcpu->arch.pdptrs_from_userspace = true; 10777 } 10778 if (mmu_reset_needed) 10779 kvm_mmu_reset_context(vcpu); 10780 return 0; 10781 } 10782 10783 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 10784 struct kvm_sregs *sregs) 10785 { 10786 int ret; 10787 10788 vcpu_load(vcpu); 10789 ret = __set_sregs(vcpu, sregs); 10790 vcpu_put(vcpu); 10791 return ret; 10792 } 10793 10794 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm) 10795 { 10796 bool inhibit = false; 10797 struct kvm_vcpu *vcpu; 10798 unsigned long i; 10799 10800 down_write(&kvm->arch.apicv_update_lock); 10801 10802 kvm_for_each_vcpu(i, vcpu, kvm) { 10803 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) { 10804 inhibit = true; 10805 break; 10806 } 10807 } 10808 __kvm_request_apicv_update(kvm, !inhibit, APICV_INHIBIT_REASON_BLOCKIRQ); 10809 up_write(&kvm->arch.apicv_update_lock); 10810 } 10811 10812 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 10813 struct kvm_guest_debug *dbg) 10814 { 10815 unsigned long rflags; 10816 int i, r; 10817 10818 if (vcpu->arch.guest_state_protected) 10819 return -EINVAL; 10820 10821 vcpu_load(vcpu); 10822 10823 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 10824 r = -EBUSY; 10825 if (vcpu->arch.exception.pending) 10826 goto out; 10827 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 10828 kvm_queue_exception(vcpu, DB_VECTOR); 10829 else 10830 kvm_queue_exception(vcpu, BP_VECTOR); 10831 } 10832 10833 /* 10834 * Read rflags as long as potentially injected trace flags are still 10835 * filtered out. 10836 */ 10837 rflags = kvm_get_rflags(vcpu); 10838 10839 vcpu->guest_debug = dbg->control; 10840 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 10841 vcpu->guest_debug = 0; 10842 10843 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 10844 for (i = 0; i < KVM_NR_DB_REGS; ++i) 10845 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 10846 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 10847 } else { 10848 for (i = 0; i < KVM_NR_DB_REGS; i++) 10849 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 10850 } 10851 kvm_update_dr7(vcpu); 10852 10853 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 10854 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); 10855 10856 /* 10857 * Trigger an rflags update that will inject or remove the trace 10858 * flags. 10859 */ 10860 kvm_set_rflags(vcpu, rflags); 10861 10862 static_call(kvm_x86_update_exception_bitmap)(vcpu); 10863 10864 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm); 10865 10866 r = 0; 10867 10868 out: 10869 vcpu_put(vcpu); 10870 return r; 10871 } 10872 10873 /* 10874 * Translate a guest virtual address to a guest physical address. 10875 */ 10876 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 10877 struct kvm_translation *tr) 10878 { 10879 unsigned long vaddr = tr->linear_address; 10880 gpa_t gpa; 10881 int idx; 10882 10883 vcpu_load(vcpu); 10884 10885 idx = srcu_read_lock(&vcpu->kvm->srcu); 10886 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 10887 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10888 tr->physical_address = gpa; 10889 tr->valid = gpa != UNMAPPED_GVA; 10890 tr->writeable = 1; 10891 tr->usermode = 0; 10892 10893 vcpu_put(vcpu); 10894 return 0; 10895 } 10896 10897 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 10898 { 10899 struct fxregs_state *fxsave; 10900 10901 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 10902 return 0; 10903 10904 vcpu_load(vcpu); 10905 10906 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 10907 memcpy(fpu->fpr, fxsave->st_space, 128); 10908 fpu->fcw = fxsave->cwd; 10909 fpu->fsw = fxsave->swd; 10910 fpu->ftwx = fxsave->twd; 10911 fpu->last_opcode = fxsave->fop; 10912 fpu->last_ip = fxsave->rip; 10913 fpu->last_dp = fxsave->rdp; 10914 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 10915 10916 vcpu_put(vcpu); 10917 return 0; 10918 } 10919 10920 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 10921 { 10922 struct fxregs_state *fxsave; 10923 10924 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 10925 return 0; 10926 10927 vcpu_load(vcpu); 10928 10929 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 10930 10931 memcpy(fxsave->st_space, fpu->fpr, 128); 10932 fxsave->cwd = fpu->fcw; 10933 fxsave->swd = fpu->fsw; 10934 fxsave->twd = fpu->ftwx; 10935 fxsave->fop = fpu->last_opcode; 10936 fxsave->rip = fpu->last_ip; 10937 fxsave->rdp = fpu->last_dp; 10938 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 10939 10940 vcpu_put(vcpu); 10941 return 0; 10942 } 10943 10944 static void store_regs(struct kvm_vcpu *vcpu) 10945 { 10946 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 10947 10948 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 10949 __get_regs(vcpu, &vcpu->run->s.regs.regs); 10950 10951 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 10952 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 10953 10954 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 10955 kvm_vcpu_ioctl_x86_get_vcpu_events( 10956 vcpu, &vcpu->run->s.regs.events); 10957 } 10958 10959 static int sync_regs(struct kvm_vcpu *vcpu) 10960 { 10961 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 10962 __set_regs(vcpu, &vcpu->run->s.regs.regs); 10963 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 10964 } 10965 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 10966 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 10967 return -EINVAL; 10968 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 10969 } 10970 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 10971 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 10972 vcpu, &vcpu->run->s.regs.events)) 10973 return -EINVAL; 10974 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 10975 } 10976 10977 return 0; 10978 } 10979 10980 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 10981 { 10982 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 10983 pr_warn_once("kvm: SMP vm created on host with unstable TSC; " 10984 "guest TSC will not be reliable\n"); 10985 10986 return 0; 10987 } 10988 10989 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 10990 { 10991 struct page *page; 10992 int r; 10993 10994 vcpu->arch.last_vmentry_cpu = -1; 10995 vcpu->arch.regs_avail = ~0; 10996 vcpu->arch.regs_dirty = ~0; 10997 10998 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 10999 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 11000 else 11001 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 11002 11003 r = kvm_mmu_create(vcpu); 11004 if (r < 0) 11005 return r; 11006 11007 if (irqchip_in_kernel(vcpu->kvm)) { 11008 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 11009 if (r < 0) 11010 goto fail_mmu_destroy; 11011 if (kvm_apicv_activated(vcpu->kvm)) 11012 vcpu->arch.apicv_active = true; 11013 } else 11014 static_branch_inc(&kvm_has_noapic_vcpu); 11015 11016 r = -ENOMEM; 11017 11018 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 11019 if (!page) 11020 goto fail_free_lapic; 11021 vcpu->arch.pio_data = page_address(page); 11022 11023 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 11024 GFP_KERNEL_ACCOUNT); 11025 if (!vcpu->arch.mce_banks) 11026 goto fail_free_pio_data; 11027 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 11028 11029 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 11030 GFP_KERNEL_ACCOUNT)) 11031 goto fail_free_mce_banks; 11032 11033 if (!alloc_emulate_ctxt(vcpu)) 11034 goto free_wbinvd_dirty_mask; 11035 11036 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) { 11037 pr_err("kvm: failed to allocate vcpu's fpu\n"); 11038 goto free_emulate_ctxt; 11039 } 11040 11041 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 11042 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 11043 11044 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 11045 11046 kvm_async_pf_hash_reset(vcpu); 11047 kvm_pmu_init(vcpu); 11048 11049 vcpu->arch.pending_external_vector = -1; 11050 vcpu->arch.preempted_in_kernel = false; 11051 11052 #if IS_ENABLED(CONFIG_HYPERV) 11053 vcpu->arch.hv_root_tdp = INVALID_PAGE; 11054 #endif 11055 11056 r = static_call(kvm_x86_vcpu_create)(vcpu); 11057 if (r) 11058 goto free_guest_fpu; 11059 11060 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 11061 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 11062 kvm_vcpu_mtrr_init(vcpu); 11063 vcpu_load(vcpu); 11064 kvm_set_tsc_khz(vcpu, max_tsc_khz); 11065 kvm_vcpu_reset(vcpu, false); 11066 kvm_init_mmu(vcpu); 11067 vcpu_put(vcpu); 11068 return 0; 11069 11070 free_guest_fpu: 11071 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 11072 free_emulate_ctxt: 11073 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 11074 free_wbinvd_dirty_mask: 11075 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 11076 fail_free_mce_banks: 11077 kfree(vcpu->arch.mce_banks); 11078 fail_free_pio_data: 11079 free_page((unsigned long)vcpu->arch.pio_data); 11080 fail_free_lapic: 11081 kvm_free_lapic(vcpu); 11082 fail_mmu_destroy: 11083 kvm_mmu_destroy(vcpu); 11084 return r; 11085 } 11086 11087 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 11088 { 11089 struct kvm *kvm = vcpu->kvm; 11090 11091 if (mutex_lock_killable(&vcpu->mutex)) 11092 return; 11093 vcpu_load(vcpu); 11094 kvm_synchronize_tsc(vcpu, 0); 11095 vcpu_put(vcpu); 11096 11097 /* poll control enabled by default */ 11098 vcpu->arch.msr_kvm_poll_control = 1; 11099 11100 mutex_unlock(&vcpu->mutex); 11101 11102 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) 11103 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 11104 KVMCLOCK_SYNC_PERIOD); 11105 } 11106 11107 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 11108 { 11109 int idx; 11110 11111 kvmclock_reset(vcpu); 11112 11113 static_call(kvm_x86_vcpu_free)(vcpu); 11114 11115 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 11116 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 11117 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 11118 11119 kvm_hv_vcpu_uninit(vcpu); 11120 kvm_pmu_destroy(vcpu); 11121 kfree(vcpu->arch.mce_banks); 11122 kvm_free_lapic(vcpu); 11123 idx = srcu_read_lock(&vcpu->kvm->srcu); 11124 kvm_mmu_destroy(vcpu); 11125 srcu_read_unlock(&vcpu->kvm->srcu, idx); 11126 free_page((unsigned long)vcpu->arch.pio_data); 11127 kvfree(vcpu->arch.cpuid_entries); 11128 if (!lapic_in_kernel(vcpu)) 11129 static_branch_dec(&kvm_has_noapic_vcpu); 11130 } 11131 11132 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 11133 { 11134 struct kvm_cpuid_entry2 *cpuid_0x1; 11135 unsigned long old_cr0 = kvm_read_cr0(vcpu); 11136 unsigned long new_cr0; 11137 11138 /* 11139 * Several of the "set" flows, e.g. ->set_cr0(), read other registers 11140 * to handle side effects. RESET emulation hits those flows and relies 11141 * on emulated/virtualized registers, including those that are loaded 11142 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel 11143 * to detect improper or missing initialization. 11144 */ 11145 WARN_ON_ONCE(!init_event && 11146 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu))); 11147 11148 kvm_lapic_reset(vcpu, init_event); 11149 11150 vcpu->arch.hflags = 0; 11151 11152 vcpu->arch.smi_pending = 0; 11153 vcpu->arch.smi_count = 0; 11154 atomic_set(&vcpu->arch.nmi_queued, 0); 11155 vcpu->arch.nmi_pending = 0; 11156 vcpu->arch.nmi_injected = false; 11157 kvm_clear_interrupt_queue(vcpu); 11158 kvm_clear_exception_queue(vcpu); 11159 11160 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 11161 kvm_update_dr0123(vcpu); 11162 vcpu->arch.dr6 = DR6_ACTIVE_LOW; 11163 vcpu->arch.dr7 = DR7_FIXED_1; 11164 kvm_update_dr7(vcpu); 11165 11166 vcpu->arch.cr2 = 0; 11167 11168 kvm_make_request(KVM_REQ_EVENT, vcpu); 11169 vcpu->arch.apf.msr_en_val = 0; 11170 vcpu->arch.apf.msr_int_val = 0; 11171 vcpu->arch.st.msr_val = 0; 11172 11173 kvmclock_reset(vcpu); 11174 11175 kvm_clear_async_pf_completion_queue(vcpu); 11176 kvm_async_pf_hash_reset(vcpu); 11177 vcpu->arch.apf.halted = false; 11178 11179 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) { 11180 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate; 11181 11182 /* 11183 * To avoid have the INIT path from kvm_apic_has_events() that be 11184 * called with loaded FPU and does not let userspace fix the state. 11185 */ 11186 if (init_event) 11187 kvm_put_guest_fpu(vcpu); 11188 11189 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS); 11190 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR); 11191 11192 if (init_event) 11193 kvm_load_guest_fpu(vcpu); 11194 } 11195 11196 if (!init_event) { 11197 kvm_pmu_reset(vcpu); 11198 vcpu->arch.smbase = 0x30000; 11199 11200 vcpu->arch.msr_misc_features_enables = 0; 11201 11202 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 11203 } 11204 11205 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */ 11206 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 11207 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP); 11208 11209 /* 11210 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon) 11211 * if no CPUID match is found. Note, it's impossible to get a match at 11212 * RESET since KVM emulates RESET before exposing the vCPU to userspace, 11213 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry 11214 * on RESET. But, go through the motions in case that's ever remedied. 11215 */ 11216 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1, 0); 11217 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600); 11218 11219 vcpu->arch.ia32_xss = 0; 11220 11221 static_call(kvm_x86_vcpu_reset)(vcpu, init_event); 11222 11223 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 11224 kvm_rip_write(vcpu, 0xfff0); 11225 11226 vcpu->arch.cr3 = 0; 11227 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 11228 11229 /* 11230 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions 11231 * of Intel's SDM list CD/NW as being set on INIT, but they contradict 11232 * (or qualify) that with a footnote stating that CD/NW are preserved. 11233 */ 11234 new_cr0 = X86_CR0_ET; 11235 if (init_event) 11236 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD)); 11237 else 11238 new_cr0 |= X86_CR0_NW | X86_CR0_CD; 11239 11240 static_call(kvm_x86_set_cr0)(vcpu, new_cr0); 11241 static_call(kvm_x86_set_cr4)(vcpu, 0); 11242 static_call(kvm_x86_set_efer)(vcpu, 0); 11243 static_call(kvm_x86_update_exception_bitmap)(vcpu); 11244 11245 /* 11246 * Reset the MMU context if paging was enabled prior to INIT (which is 11247 * implied if CR0.PG=1 as CR0 will be '0' prior to RESET). Unlike the 11248 * standard CR0/CR4/EFER modification paths, only CR0.PG needs to be 11249 * checked because it is unconditionally cleared on INIT and all other 11250 * paging related bits are ignored if paging is disabled, i.e. CR0.WP, 11251 * CR4, and EFER changes are all irrelevant if CR0.PG was '0'. 11252 */ 11253 if (old_cr0 & X86_CR0_PG) 11254 kvm_mmu_reset_context(vcpu); 11255 11256 /* 11257 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's 11258 * APM states the TLBs are untouched by INIT, but it also states that 11259 * the TLBs are flushed on "External initialization of the processor." 11260 * Flush the guest TLB regardless of vendor, there is no meaningful 11261 * benefit in relying on the guest to flush the TLB immediately after 11262 * INIT. A spurious TLB flush is benign and likely negligible from a 11263 * performance perspective. 11264 */ 11265 if (init_event) 11266 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 11267 } 11268 EXPORT_SYMBOL_GPL(kvm_vcpu_reset); 11269 11270 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 11271 { 11272 struct kvm_segment cs; 11273 11274 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 11275 cs.selector = vector << 8; 11276 cs.base = vector << 12; 11277 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 11278 kvm_rip_write(vcpu, 0); 11279 } 11280 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); 11281 11282 int kvm_arch_hardware_enable(void) 11283 { 11284 struct kvm *kvm; 11285 struct kvm_vcpu *vcpu; 11286 unsigned long i; 11287 int ret; 11288 u64 local_tsc; 11289 u64 max_tsc = 0; 11290 bool stable, backwards_tsc = false; 11291 11292 kvm_user_return_msr_cpu_online(); 11293 ret = static_call(kvm_x86_hardware_enable)(); 11294 if (ret != 0) 11295 return ret; 11296 11297 local_tsc = rdtsc(); 11298 stable = !kvm_check_tsc_unstable(); 11299 list_for_each_entry(kvm, &vm_list, vm_list) { 11300 kvm_for_each_vcpu(i, vcpu, kvm) { 11301 if (!stable && vcpu->cpu == smp_processor_id()) 11302 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 11303 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 11304 backwards_tsc = true; 11305 if (vcpu->arch.last_host_tsc > max_tsc) 11306 max_tsc = vcpu->arch.last_host_tsc; 11307 } 11308 } 11309 } 11310 11311 /* 11312 * Sometimes, even reliable TSCs go backwards. This happens on 11313 * platforms that reset TSC during suspend or hibernate actions, but 11314 * maintain synchronization. We must compensate. Fortunately, we can 11315 * detect that condition here, which happens early in CPU bringup, 11316 * before any KVM threads can be running. Unfortunately, we can't 11317 * bring the TSCs fully up to date with real time, as we aren't yet far 11318 * enough into CPU bringup that we know how much real time has actually 11319 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot 11320 * variables that haven't been updated yet. 11321 * 11322 * So we simply find the maximum observed TSC above, then record the 11323 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 11324 * the adjustment will be applied. Note that we accumulate 11325 * adjustments, in case multiple suspend cycles happen before some VCPU 11326 * gets a chance to run again. In the event that no KVM threads get a 11327 * chance to run, we will miss the entire elapsed period, as we'll have 11328 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 11329 * loose cycle time. This isn't too big a deal, since the loss will be 11330 * uniform across all VCPUs (not to mention the scenario is extremely 11331 * unlikely). It is possible that a second hibernate recovery happens 11332 * much faster than a first, causing the observed TSC here to be 11333 * smaller; this would require additional padding adjustment, which is 11334 * why we set last_host_tsc to the local tsc observed here. 11335 * 11336 * N.B. - this code below runs only on platforms with reliable TSC, 11337 * as that is the only way backwards_tsc is set above. Also note 11338 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 11339 * have the same delta_cyc adjustment applied if backwards_tsc 11340 * is detected. Note further, this adjustment is only done once, 11341 * as we reset last_host_tsc on all VCPUs to stop this from being 11342 * called multiple times (one for each physical CPU bringup). 11343 * 11344 * Platforms with unreliable TSCs don't have to deal with this, they 11345 * will be compensated by the logic in vcpu_load, which sets the TSC to 11346 * catchup mode. This will catchup all VCPUs to real time, but cannot 11347 * guarantee that they stay in perfect synchronization. 11348 */ 11349 if (backwards_tsc) { 11350 u64 delta_cyc = max_tsc - local_tsc; 11351 list_for_each_entry(kvm, &vm_list, vm_list) { 11352 kvm->arch.backwards_tsc_observed = true; 11353 kvm_for_each_vcpu(i, vcpu, kvm) { 11354 vcpu->arch.tsc_offset_adjustment += delta_cyc; 11355 vcpu->arch.last_host_tsc = local_tsc; 11356 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 11357 } 11358 11359 /* 11360 * We have to disable TSC offset matching.. if you were 11361 * booting a VM while issuing an S4 host suspend.... 11362 * you may have some problem. Solving this issue is 11363 * left as an exercise to the reader. 11364 */ 11365 kvm->arch.last_tsc_nsec = 0; 11366 kvm->arch.last_tsc_write = 0; 11367 } 11368 11369 } 11370 return 0; 11371 } 11372 11373 void kvm_arch_hardware_disable(void) 11374 { 11375 static_call(kvm_x86_hardware_disable)(); 11376 drop_user_return_notifiers(); 11377 } 11378 11379 int kvm_arch_hardware_setup(void *opaque) 11380 { 11381 struct kvm_x86_init_ops *ops = opaque; 11382 int r; 11383 11384 rdmsrl_safe(MSR_EFER, &host_efer); 11385 11386 if (boot_cpu_has(X86_FEATURE_XSAVES)) 11387 rdmsrl(MSR_IA32_XSS, host_xss); 11388 11389 r = ops->hardware_setup(); 11390 if (r != 0) 11391 return r; 11392 11393 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); 11394 kvm_ops_static_call_update(); 11395 11396 kvm_register_perf_callbacks(ops->handle_intel_pt_intr); 11397 11398 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) 11399 supported_xss = 0; 11400 11401 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) 11402 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); 11403 #undef __kvm_cpu_cap_has 11404 11405 if (kvm_has_tsc_control) { 11406 /* 11407 * Make sure the user can only configure tsc_khz values that 11408 * fit into a signed integer. 11409 * A min value is not calculated because it will always 11410 * be 1 on all machines. 11411 */ 11412 u64 max = min(0x7fffffffULL, 11413 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 11414 kvm_max_guest_tsc_khz = max; 11415 11416 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 11417 } 11418 11419 kvm_init_msr_list(); 11420 return 0; 11421 } 11422 11423 void kvm_arch_hardware_unsetup(void) 11424 { 11425 kvm_unregister_perf_callbacks(); 11426 11427 static_call(kvm_x86_hardware_unsetup)(); 11428 } 11429 11430 int kvm_arch_check_processor_compat(void *opaque) 11431 { 11432 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 11433 struct kvm_x86_init_ops *ops = opaque; 11434 11435 WARN_ON(!irqs_disabled()); 11436 11437 if (__cr4_reserved_bits(cpu_has, c) != 11438 __cr4_reserved_bits(cpu_has, &boot_cpu_data)) 11439 return -EIO; 11440 11441 return ops->check_processor_compatibility(); 11442 } 11443 11444 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 11445 { 11446 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 11447 } 11448 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 11449 11450 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 11451 { 11452 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 11453 } 11454 11455 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); 11456 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); 11457 11458 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 11459 { 11460 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 11461 11462 vcpu->arch.l1tf_flush_l1d = true; 11463 if (pmu->version && unlikely(pmu->event_count)) { 11464 pmu->need_cleanup = true; 11465 kvm_make_request(KVM_REQ_PMU, vcpu); 11466 } 11467 static_call(kvm_x86_sched_in)(vcpu, cpu); 11468 } 11469 11470 void kvm_arch_free_vm(struct kvm *kvm) 11471 { 11472 kfree(to_kvm_hv(kvm)->hv_pa_pg); 11473 __kvm_arch_free_vm(kvm); 11474 } 11475 11476 11477 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 11478 { 11479 int ret; 11480 unsigned long flags; 11481 11482 if (type) 11483 return -EINVAL; 11484 11485 ret = kvm_page_track_init(kvm); 11486 if (ret) 11487 return ret; 11488 11489 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 11490 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 11491 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 11492 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); 11493 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 11494 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 11495 11496 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 11497 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 11498 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 11499 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 11500 &kvm->arch.irq_sources_bitmap); 11501 11502 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 11503 mutex_init(&kvm->arch.apic_map_lock); 11504 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock); 11505 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); 11506 11507 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 11508 pvclock_update_vm_gtod_copy(kvm); 11509 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 11510 11511 kvm->arch.guest_can_read_msr_platform_info = true; 11512 11513 #if IS_ENABLED(CONFIG_HYPERV) 11514 spin_lock_init(&kvm->arch.hv_root_tdp_lock); 11515 kvm->arch.hv_root_tdp = INVALID_PAGE; 11516 #endif 11517 11518 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 11519 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 11520 11521 kvm_apicv_init(kvm); 11522 kvm_hv_init_vm(kvm); 11523 kvm_mmu_init_vm(kvm); 11524 kvm_xen_init_vm(kvm); 11525 11526 return static_call(kvm_x86_vm_init)(kvm); 11527 } 11528 11529 int kvm_arch_post_init_vm(struct kvm *kvm) 11530 { 11531 return kvm_mmu_post_init_vm(kvm); 11532 } 11533 11534 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 11535 { 11536 vcpu_load(vcpu); 11537 kvm_mmu_unload(vcpu); 11538 vcpu_put(vcpu); 11539 } 11540 11541 static void kvm_free_vcpus(struct kvm *kvm) 11542 { 11543 unsigned long i; 11544 struct kvm_vcpu *vcpu; 11545 11546 /* 11547 * Unpin any mmu pages first. 11548 */ 11549 kvm_for_each_vcpu(i, vcpu, kvm) { 11550 kvm_clear_async_pf_completion_queue(vcpu); 11551 kvm_unload_vcpu_mmu(vcpu); 11552 } 11553 11554 kvm_destroy_vcpus(kvm); 11555 } 11556 11557 void kvm_arch_sync_events(struct kvm *kvm) 11558 { 11559 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 11560 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 11561 kvm_free_pit(kvm); 11562 } 11563 11564 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) 11565 11566 /** 11567 * __x86_set_memory_region: Setup KVM internal memory slot 11568 * 11569 * @kvm: the kvm pointer to the VM. 11570 * @id: the slot ID to setup. 11571 * @gpa: the GPA to install the slot (unused when @size == 0). 11572 * @size: the size of the slot. Set to zero to uninstall a slot. 11573 * 11574 * This function helps to setup a KVM internal memory slot. Specify 11575 * @size > 0 to install a new slot, while @size == 0 to uninstall a 11576 * slot. The return code can be one of the following: 11577 * 11578 * HVA: on success (uninstall will return a bogus HVA) 11579 * -errno: on error 11580 * 11581 * The caller should always use IS_ERR() to check the return value 11582 * before use. Note, the KVM internal memory slots are guaranteed to 11583 * remain valid and unchanged until the VM is destroyed, i.e., the 11584 * GPA->HVA translation will not change. However, the HVA is a user 11585 * address, i.e. its accessibility is not guaranteed, and must be 11586 * accessed via __copy_{to,from}_user(). 11587 */ 11588 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, 11589 u32 size) 11590 { 11591 int i, r; 11592 unsigned long hva, old_npages; 11593 struct kvm_memslots *slots = kvm_memslots(kvm); 11594 struct kvm_memory_slot *slot; 11595 11596 /* Called with kvm->slots_lock held. */ 11597 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 11598 return ERR_PTR_USR(-EINVAL); 11599 11600 slot = id_to_memslot(slots, id); 11601 if (size) { 11602 if (slot && slot->npages) 11603 return ERR_PTR_USR(-EEXIST); 11604 11605 /* 11606 * MAP_SHARED to prevent internal slot pages from being moved 11607 * by fork()/COW. 11608 */ 11609 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 11610 MAP_SHARED | MAP_ANONYMOUS, 0); 11611 if (IS_ERR((void *)hva)) 11612 return (void __user *)hva; 11613 } else { 11614 if (!slot || !slot->npages) 11615 return NULL; 11616 11617 old_npages = slot->npages; 11618 hva = slot->userspace_addr; 11619 } 11620 11621 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 11622 struct kvm_userspace_memory_region m; 11623 11624 m.slot = id | (i << 16); 11625 m.flags = 0; 11626 m.guest_phys_addr = gpa; 11627 m.userspace_addr = hva; 11628 m.memory_size = size; 11629 r = __kvm_set_memory_region(kvm, &m); 11630 if (r < 0) 11631 return ERR_PTR_USR(r); 11632 } 11633 11634 if (!size) 11635 vm_munmap(hva, old_npages * PAGE_SIZE); 11636 11637 return (void __user *)hva; 11638 } 11639 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 11640 11641 void kvm_arch_pre_destroy_vm(struct kvm *kvm) 11642 { 11643 kvm_mmu_pre_destroy_vm(kvm); 11644 } 11645 11646 void kvm_arch_destroy_vm(struct kvm *kvm) 11647 { 11648 if (current->mm == kvm->mm) { 11649 /* 11650 * Free memory regions allocated on behalf of userspace, 11651 * unless the the memory map has changed due to process exit 11652 * or fd copying. 11653 */ 11654 mutex_lock(&kvm->slots_lock); 11655 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 11656 0, 0); 11657 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 11658 0, 0); 11659 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 11660 mutex_unlock(&kvm->slots_lock); 11661 } 11662 static_call_cond(kvm_x86_vm_destroy)(kvm); 11663 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); 11664 kvm_pic_destroy(kvm); 11665 kvm_ioapic_destroy(kvm); 11666 kvm_free_vcpus(kvm); 11667 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 11668 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); 11669 kvm_mmu_uninit_vm(kvm); 11670 kvm_page_track_cleanup(kvm); 11671 kvm_xen_destroy_vm(kvm); 11672 kvm_hv_destroy_vm(kvm); 11673 } 11674 11675 static void memslot_rmap_free(struct kvm_memory_slot *slot) 11676 { 11677 int i; 11678 11679 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 11680 kvfree(slot->arch.rmap[i]); 11681 slot->arch.rmap[i] = NULL; 11682 } 11683 } 11684 11685 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) 11686 { 11687 int i; 11688 11689 memslot_rmap_free(slot); 11690 11691 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 11692 kvfree(slot->arch.lpage_info[i - 1]); 11693 slot->arch.lpage_info[i - 1] = NULL; 11694 } 11695 11696 kvm_page_track_free_memslot(slot); 11697 } 11698 11699 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages) 11700 { 11701 const int sz = sizeof(*slot->arch.rmap[0]); 11702 int i; 11703 11704 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 11705 int level = i + 1; 11706 int lpages = __kvm_mmu_slot_lpages(slot, npages, level); 11707 11708 if (slot->arch.rmap[i]) 11709 continue; 11710 11711 slot->arch.rmap[i] = kvcalloc(lpages, sz, GFP_KERNEL_ACCOUNT); 11712 if (!slot->arch.rmap[i]) { 11713 memslot_rmap_free(slot); 11714 return -ENOMEM; 11715 } 11716 } 11717 11718 return 0; 11719 } 11720 11721 static int kvm_alloc_memslot_metadata(struct kvm *kvm, 11722 struct kvm_memory_slot *slot) 11723 { 11724 unsigned long npages = slot->npages; 11725 int i, r; 11726 11727 /* 11728 * Clear out the previous array pointers for the KVM_MR_MOVE case. The 11729 * old arrays will be freed by __kvm_set_memory_region() if installing 11730 * the new memslot is successful. 11731 */ 11732 memset(&slot->arch, 0, sizeof(slot->arch)); 11733 11734 if (kvm_memslots_have_rmaps(kvm)) { 11735 r = memslot_rmap_alloc(slot, npages); 11736 if (r) 11737 return r; 11738 } 11739 11740 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 11741 struct kvm_lpage_info *linfo; 11742 unsigned long ugfn; 11743 int lpages; 11744 int level = i + 1; 11745 11746 lpages = __kvm_mmu_slot_lpages(slot, npages, level); 11747 11748 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 11749 if (!linfo) 11750 goto out_free; 11751 11752 slot->arch.lpage_info[i - 1] = linfo; 11753 11754 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 11755 linfo[0].disallow_lpage = 1; 11756 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 11757 linfo[lpages - 1].disallow_lpage = 1; 11758 ugfn = slot->userspace_addr >> PAGE_SHIFT; 11759 /* 11760 * If the gfn and userspace address are not aligned wrt each 11761 * other, disable large page support for this slot. 11762 */ 11763 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { 11764 unsigned long j; 11765 11766 for (j = 0; j < lpages; ++j) 11767 linfo[j].disallow_lpage = 1; 11768 } 11769 } 11770 11771 if (kvm_page_track_create_memslot(kvm, slot, npages)) 11772 goto out_free; 11773 11774 return 0; 11775 11776 out_free: 11777 memslot_rmap_free(slot); 11778 11779 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 11780 kvfree(slot->arch.lpage_info[i - 1]); 11781 slot->arch.lpage_info[i - 1] = NULL; 11782 } 11783 return -ENOMEM; 11784 } 11785 11786 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 11787 { 11788 struct kvm_vcpu *vcpu; 11789 unsigned long i; 11790 11791 /* 11792 * memslots->generation has been incremented. 11793 * mmio generation may have reached its maximum value. 11794 */ 11795 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 11796 11797 /* Force re-initialization of steal_time cache */ 11798 kvm_for_each_vcpu(i, vcpu, kvm) 11799 kvm_vcpu_kick(vcpu); 11800 } 11801 11802 int kvm_arch_prepare_memory_region(struct kvm *kvm, 11803 const struct kvm_memory_slot *old, 11804 struct kvm_memory_slot *new, 11805 enum kvm_mr_change change) 11806 { 11807 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) 11808 return kvm_alloc_memslot_metadata(kvm, new); 11809 11810 if (change == KVM_MR_FLAGS_ONLY) 11811 memcpy(&new->arch, &old->arch, sizeof(old->arch)); 11812 else if (WARN_ON_ONCE(change != KVM_MR_DELETE)) 11813 return -EIO; 11814 11815 return 0; 11816 } 11817 11818 11819 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) 11820 { 11821 struct kvm_arch *ka = &kvm->arch; 11822 11823 if (!kvm_x86_ops.cpu_dirty_log_size) 11824 return; 11825 11826 if ((enable && ++ka->cpu_dirty_logging_count == 1) || 11827 (!enable && --ka->cpu_dirty_logging_count == 0)) 11828 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); 11829 11830 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); 11831 } 11832 11833 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 11834 struct kvm_memory_slot *old, 11835 const struct kvm_memory_slot *new, 11836 enum kvm_mr_change change) 11837 { 11838 u32 old_flags = old ? old->flags : 0; 11839 u32 new_flags = new ? new->flags : 0; 11840 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES; 11841 11842 /* 11843 * Update CPU dirty logging if dirty logging is being toggled. This 11844 * applies to all operations. 11845 */ 11846 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES) 11847 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); 11848 11849 /* 11850 * Nothing more to do for RO slots (which can't be dirtied and can't be 11851 * made writable) or CREATE/MOVE/DELETE of a slot. 11852 * 11853 * For a memslot with dirty logging disabled: 11854 * CREATE: No dirty mappings will already exist. 11855 * MOVE/DELETE: The old mappings will already have been cleaned up by 11856 * kvm_arch_flush_shadow_memslot() 11857 * 11858 * For a memslot with dirty logging enabled: 11859 * CREATE: No shadow pages exist, thus nothing to write-protect 11860 * and no dirty bits to clear. 11861 * MOVE/DELETE: The old mappings will already have been cleaned up by 11862 * kvm_arch_flush_shadow_memslot(). 11863 */ 11864 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY)) 11865 return; 11866 11867 /* 11868 * READONLY and non-flags changes were filtered out above, and the only 11869 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty 11870 * logging isn't being toggled on or off. 11871 */ 11872 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES))) 11873 return; 11874 11875 if (!log_dirty_pages) { 11876 /* 11877 * Dirty logging tracks sptes in 4k granularity, meaning that 11878 * large sptes have to be split. If live migration succeeds, 11879 * the guest in the source machine will be destroyed and large 11880 * sptes will be created in the destination. However, if the 11881 * guest continues to run in the source machine (for example if 11882 * live migration fails), small sptes will remain around and 11883 * cause bad performance. 11884 * 11885 * Scan sptes if dirty logging has been stopped, dropping those 11886 * which can be collapsed into a single large-page spte. Later 11887 * page faults will create the large-page sptes. 11888 */ 11889 kvm_mmu_zap_collapsible_sptes(kvm, new); 11890 } else { 11891 /* 11892 * Initially-all-set does not require write protecting any page, 11893 * because they're all assumed to be dirty. 11894 */ 11895 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) 11896 return; 11897 11898 if (kvm_x86_ops.cpu_dirty_log_size) { 11899 kvm_mmu_slot_leaf_clear_dirty(kvm, new); 11900 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M); 11901 } else { 11902 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K); 11903 } 11904 } 11905 } 11906 11907 void kvm_arch_commit_memory_region(struct kvm *kvm, 11908 struct kvm_memory_slot *old, 11909 const struct kvm_memory_slot *new, 11910 enum kvm_mr_change change) 11911 { 11912 if (!kvm->arch.n_requested_mmu_pages && 11913 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) { 11914 unsigned long nr_mmu_pages; 11915 11916 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO; 11917 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES); 11918 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 11919 } 11920 11921 kvm_mmu_slot_apply_flags(kvm, old, new, change); 11922 11923 /* Free the arrays associated with the old memslot. */ 11924 if (change == KVM_MR_MOVE) 11925 kvm_arch_free_memslot(kvm, old); 11926 } 11927 11928 void kvm_arch_flush_shadow_all(struct kvm *kvm) 11929 { 11930 kvm_mmu_zap_all(kvm); 11931 } 11932 11933 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 11934 struct kvm_memory_slot *slot) 11935 { 11936 kvm_page_track_flush_slot(kvm, slot); 11937 } 11938 11939 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 11940 { 11941 return (is_guest_mode(vcpu) && 11942 kvm_x86_ops.guest_apic_has_interrupt && 11943 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); 11944 } 11945 11946 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 11947 { 11948 if (!list_empty_careful(&vcpu->async_pf.done)) 11949 return true; 11950 11951 if (kvm_apic_has_events(vcpu)) 11952 return true; 11953 11954 if (vcpu->arch.pv.pv_unhalted) 11955 return true; 11956 11957 if (vcpu->arch.exception.pending) 11958 return true; 11959 11960 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 11961 (vcpu->arch.nmi_pending && 11962 static_call(kvm_x86_nmi_allowed)(vcpu, false))) 11963 return true; 11964 11965 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 11966 (vcpu->arch.smi_pending && 11967 static_call(kvm_x86_smi_allowed)(vcpu, false))) 11968 return true; 11969 11970 if (kvm_arch_interrupt_allowed(vcpu) && 11971 (kvm_cpu_has_interrupt(vcpu) || 11972 kvm_guest_apic_has_interrupt(vcpu))) 11973 return true; 11974 11975 if (kvm_hv_has_stimer_pending(vcpu)) 11976 return true; 11977 11978 if (is_guest_mode(vcpu) && 11979 kvm_x86_ops.nested_ops->hv_timer_pending && 11980 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 11981 return true; 11982 11983 return false; 11984 } 11985 11986 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 11987 { 11988 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 11989 } 11990 11991 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) 11992 { 11993 if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) 11994 return true; 11995 11996 return false; 11997 } 11998 11999 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) 12000 { 12001 if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) 12002 return true; 12003 12004 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 12005 kvm_test_request(KVM_REQ_SMI, vcpu) || 12006 kvm_test_request(KVM_REQ_EVENT, vcpu)) 12007 return true; 12008 12009 return kvm_arch_dy_has_pending_interrupt(vcpu); 12010 } 12011 12012 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 12013 { 12014 if (vcpu->arch.guest_state_protected) 12015 return true; 12016 12017 return vcpu->arch.preempted_in_kernel; 12018 } 12019 12020 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu) 12021 { 12022 return kvm_rip_read(vcpu); 12023 } 12024 12025 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 12026 { 12027 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 12028 } 12029 12030 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 12031 { 12032 return static_call(kvm_x86_interrupt_allowed)(vcpu, false); 12033 } 12034 12035 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 12036 { 12037 /* Can't read the RIP when guest state is protected, just return 0 */ 12038 if (vcpu->arch.guest_state_protected) 12039 return 0; 12040 12041 if (is_64_bit_mode(vcpu)) 12042 return kvm_rip_read(vcpu); 12043 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 12044 kvm_rip_read(vcpu)); 12045 } 12046 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 12047 12048 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 12049 { 12050 return kvm_get_linear_rip(vcpu) == linear_rip; 12051 } 12052 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 12053 12054 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 12055 { 12056 unsigned long rflags; 12057 12058 rflags = static_call(kvm_x86_get_rflags)(vcpu); 12059 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 12060 rflags &= ~X86_EFLAGS_TF; 12061 return rflags; 12062 } 12063 EXPORT_SYMBOL_GPL(kvm_get_rflags); 12064 12065 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 12066 { 12067 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 12068 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 12069 rflags |= X86_EFLAGS_TF; 12070 static_call(kvm_x86_set_rflags)(vcpu, rflags); 12071 } 12072 12073 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 12074 { 12075 __kvm_set_rflags(vcpu, rflags); 12076 kvm_make_request(KVM_REQ_EVENT, vcpu); 12077 } 12078 EXPORT_SYMBOL_GPL(kvm_set_rflags); 12079 12080 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 12081 { 12082 int r; 12083 12084 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || 12085 work->wakeup_all) 12086 return; 12087 12088 r = kvm_mmu_reload(vcpu); 12089 if (unlikely(r)) 12090 return; 12091 12092 if (!vcpu->arch.mmu->direct_map && 12093 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) 12094 return; 12095 12096 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); 12097 } 12098 12099 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 12100 { 12101 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); 12102 12103 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 12104 } 12105 12106 static inline u32 kvm_async_pf_next_probe(u32 key) 12107 { 12108 return (key + 1) & (ASYNC_PF_PER_VCPU - 1); 12109 } 12110 12111 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 12112 { 12113 u32 key = kvm_async_pf_hash_fn(gfn); 12114 12115 while (vcpu->arch.apf.gfns[key] != ~0) 12116 key = kvm_async_pf_next_probe(key); 12117 12118 vcpu->arch.apf.gfns[key] = gfn; 12119 } 12120 12121 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 12122 { 12123 int i; 12124 u32 key = kvm_async_pf_hash_fn(gfn); 12125 12126 for (i = 0; i < ASYNC_PF_PER_VCPU && 12127 (vcpu->arch.apf.gfns[key] != gfn && 12128 vcpu->arch.apf.gfns[key] != ~0); i++) 12129 key = kvm_async_pf_next_probe(key); 12130 12131 return key; 12132 } 12133 12134 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 12135 { 12136 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 12137 } 12138 12139 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 12140 { 12141 u32 i, j, k; 12142 12143 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 12144 12145 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) 12146 return; 12147 12148 while (true) { 12149 vcpu->arch.apf.gfns[i] = ~0; 12150 do { 12151 j = kvm_async_pf_next_probe(j); 12152 if (vcpu->arch.apf.gfns[j] == ~0) 12153 return; 12154 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 12155 /* 12156 * k lies cyclically in ]i,j] 12157 * | i.k.j | 12158 * |....j i.k.| or |.k..j i...| 12159 */ 12160 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 12161 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 12162 i = j; 12163 } 12164 } 12165 12166 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) 12167 { 12168 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; 12169 12170 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, 12171 sizeof(reason)); 12172 } 12173 12174 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) 12175 { 12176 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 12177 12178 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 12179 &token, offset, sizeof(token)); 12180 } 12181 12182 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) 12183 { 12184 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 12185 u32 val; 12186 12187 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 12188 &val, offset, sizeof(val))) 12189 return false; 12190 12191 return !val; 12192 } 12193 12194 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) 12195 { 12196 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) 12197 return false; 12198 12199 if (!kvm_pv_async_pf_enabled(vcpu) || 12200 (vcpu->arch.apf.send_user_only && static_call(kvm_x86_get_cpl)(vcpu) == 0)) 12201 return false; 12202 12203 return true; 12204 } 12205 12206 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) 12207 { 12208 if (unlikely(!lapic_in_kernel(vcpu) || 12209 kvm_event_needs_reinjection(vcpu) || 12210 vcpu->arch.exception.pending)) 12211 return false; 12212 12213 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) 12214 return false; 12215 12216 /* 12217 * If interrupts are off we cannot even use an artificial 12218 * halt state. 12219 */ 12220 return kvm_arch_interrupt_allowed(vcpu); 12221 } 12222 12223 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 12224 struct kvm_async_pf *work) 12225 { 12226 struct x86_exception fault; 12227 12228 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); 12229 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 12230 12231 if (kvm_can_deliver_async_pf(vcpu) && 12232 !apf_put_user_notpresent(vcpu)) { 12233 fault.vector = PF_VECTOR; 12234 fault.error_code_valid = true; 12235 fault.error_code = 0; 12236 fault.nested_page_fault = false; 12237 fault.address = work->arch.token; 12238 fault.async_page_fault = true; 12239 kvm_inject_page_fault(vcpu, &fault); 12240 return true; 12241 } else { 12242 /* 12243 * It is not possible to deliver a paravirtualized asynchronous 12244 * page fault, but putting the guest in an artificial halt state 12245 * can be beneficial nevertheless: if an interrupt arrives, we 12246 * can deliver it timely and perhaps the guest will schedule 12247 * another process. When the instruction that triggered a page 12248 * fault is retried, hopefully the page will be ready in the host. 12249 */ 12250 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 12251 return false; 12252 } 12253 } 12254 12255 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 12256 struct kvm_async_pf *work) 12257 { 12258 struct kvm_lapic_irq irq = { 12259 .delivery_mode = APIC_DM_FIXED, 12260 .vector = vcpu->arch.apf.vec 12261 }; 12262 12263 if (work->wakeup_all) 12264 work->arch.token = ~0; /* broadcast wakeup */ 12265 else 12266 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 12267 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); 12268 12269 if ((work->wakeup_all || work->notpresent_injected) && 12270 kvm_pv_async_pf_enabled(vcpu) && 12271 !apf_put_user_ready(vcpu, work->arch.token)) { 12272 vcpu->arch.apf.pageready_pending = true; 12273 kvm_apic_set_irq(vcpu, &irq, NULL); 12274 } 12275 12276 vcpu->arch.apf.halted = false; 12277 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 12278 } 12279 12280 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) 12281 { 12282 kvm_make_request(KVM_REQ_APF_READY, vcpu); 12283 if (!vcpu->arch.apf.pageready_pending) 12284 kvm_vcpu_kick(vcpu); 12285 } 12286 12287 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) 12288 { 12289 if (!kvm_pv_async_pf_enabled(vcpu)) 12290 return true; 12291 else 12292 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); 12293 } 12294 12295 void kvm_arch_start_assignment(struct kvm *kvm) 12296 { 12297 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) 12298 static_call_cond(kvm_x86_start_assignment)(kvm); 12299 } 12300 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 12301 12302 void kvm_arch_end_assignment(struct kvm *kvm) 12303 { 12304 atomic_dec(&kvm->arch.assigned_device_count); 12305 } 12306 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 12307 12308 bool kvm_arch_has_assigned_device(struct kvm *kvm) 12309 { 12310 return atomic_read(&kvm->arch.assigned_device_count); 12311 } 12312 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 12313 12314 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 12315 { 12316 atomic_inc(&kvm->arch.noncoherent_dma_count); 12317 } 12318 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 12319 12320 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 12321 { 12322 atomic_dec(&kvm->arch.noncoherent_dma_count); 12323 } 12324 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 12325 12326 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 12327 { 12328 return atomic_read(&kvm->arch.noncoherent_dma_count); 12329 } 12330 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 12331 12332 bool kvm_arch_has_irq_bypass(void) 12333 { 12334 return true; 12335 } 12336 12337 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 12338 struct irq_bypass_producer *prod) 12339 { 12340 struct kvm_kernel_irqfd *irqfd = 12341 container_of(cons, struct kvm_kernel_irqfd, consumer); 12342 int ret; 12343 12344 irqfd->producer = prod; 12345 kvm_arch_start_assignment(irqfd->kvm); 12346 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, 12347 prod->irq, irqfd->gsi, 1); 12348 12349 if (ret) 12350 kvm_arch_end_assignment(irqfd->kvm); 12351 12352 return ret; 12353 } 12354 12355 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 12356 struct irq_bypass_producer *prod) 12357 { 12358 int ret; 12359 struct kvm_kernel_irqfd *irqfd = 12360 container_of(cons, struct kvm_kernel_irqfd, consumer); 12361 12362 WARN_ON(irqfd->producer != prod); 12363 irqfd->producer = NULL; 12364 12365 /* 12366 * When producer of consumer is unregistered, we change back to 12367 * remapped mode, so we can re-use the current implementation 12368 * when the irq is masked/disabled or the consumer side (KVM 12369 * int this case doesn't want to receive the interrupts. 12370 */ 12371 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); 12372 if (ret) 12373 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 12374 " fails: %d\n", irqfd->consumer.token, ret); 12375 12376 kvm_arch_end_assignment(irqfd->kvm); 12377 } 12378 12379 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 12380 uint32_t guest_irq, bool set) 12381 { 12382 return static_call(kvm_x86_update_pi_irte)(kvm, host_irq, guest_irq, set); 12383 } 12384 12385 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old, 12386 struct kvm_kernel_irq_routing_entry *new) 12387 { 12388 if (new->type != KVM_IRQ_ROUTING_MSI) 12389 return true; 12390 12391 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi)); 12392 } 12393 12394 bool kvm_vector_hashing_enabled(void) 12395 { 12396 return vector_hashing; 12397 } 12398 12399 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) 12400 { 12401 return (vcpu->arch.msr_kvm_poll_control & 1) == 0; 12402 } 12403 EXPORT_SYMBOL_GPL(kvm_arch_no_poll); 12404 12405 12406 int kvm_spec_ctrl_test_value(u64 value) 12407 { 12408 /* 12409 * test that setting IA32_SPEC_CTRL to given value 12410 * is allowed by the host processor 12411 */ 12412 12413 u64 saved_value; 12414 unsigned long flags; 12415 int ret = 0; 12416 12417 local_irq_save(flags); 12418 12419 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) 12420 ret = 1; 12421 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) 12422 ret = 1; 12423 else 12424 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); 12425 12426 local_irq_restore(flags); 12427 12428 return ret; 12429 } 12430 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); 12431 12432 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) 12433 { 12434 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 12435 struct x86_exception fault; 12436 u32 access = error_code & 12437 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); 12438 12439 if (!(error_code & PFERR_PRESENT_MASK) || 12440 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != UNMAPPED_GVA) { 12441 /* 12442 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page 12443 * tables probably do not match the TLB. Just proceed 12444 * with the error code that the processor gave. 12445 */ 12446 fault.vector = PF_VECTOR; 12447 fault.error_code_valid = true; 12448 fault.error_code = error_code; 12449 fault.nested_page_fault = false; 12450 fault.address = gva; 12451 } 12452 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); 12453 } 12454 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); 12455 12456 /* 12457 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns 12458 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value 12459 * indicates whether exit to userspace is needed. 12460 */ 12461 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 12462 struct x86_exception *e) 12463 { 12464 if (r == X86EMUL_PROPAGATE_FAULT) { 12465 kvm_inject_emulated_page_fault(vcpu, e); 12466 return 1; 12467 } 12468 12469 /* 12470 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED 12471 * while handling a VMX instruction KVM could've handled the request 12472 * correctly by exiting to userspace and performing I/O but there 12473 * doesn't seem to be a real use-case behind such requests, just return 12474 * KVM_EXIT_INTERNAL_ERROR for now. 12475 */ 12476 kvm_prepare_emulation_failure_exit(vcpu); 12477 12478 return 0; 12479 } 12480 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); 12481 12482 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) 12483 { 12484 bool pcid_enabled; 12485 struct x86_exception e; 12486 struct { 12487 u64 pcid; 12488 u64 gla; 12489 } operand; 12490 int r; 12491 12492 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 12493 if (r != X86EMUL_CONTINUE) 12494 return kvm_handle_memory_failure(vcpu, r, &e); 12495 12496 if (operand.pcid >> 12 != 0) { 12497 kvm_inject_gp(vcpu, 0); 12498 return 1; 12499 } 12500 12501 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 12502 12503 switch (type) { 12504 case INVPCID_TYPE_INDIV_ADDR: 12505 if ((!pcid_enabled && (operand.pcid != 0)) || 12506 is_noncanonical_address(operand.gla, vcpu)) { 12507 kvm_inject_gp(vcpu, 0); 12508 return 1; 12509 } 12510 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 12511 return kvm_skip_emulated_instruction(vcpu); 12512 12513 case INVPCID_TYPE_SINGLE_CTXT: 12514 if (!pcid_enabled && (operand.pcid != 0)) { 12515 kvm_inject_gp(vcpu, 0); 12516 return 1; 12517 } 12518 12519 kvm_invalidate_pcid(vcpu, operand.pcid); 12520 return kvm_skip_emulated_instruction(vcpu); 12521 12522 case INVPCID_TYPE_ALL_NON_GLOBAL: 12523 /* 12524 * Currently, KVM doesn't mark global entries in the shadow 12525 * page tables, so a non-global flush just degenerates to a 12526 * global flush. If needed, we could optimize this later by 12527 * keeping track of global entries in shadow page tables. 12528 */ 12529 12530 fallthrough; 12531 case INVPCID_TYPE_ALL_INCL_GLOBAL: 12532 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 12533 return kvm_skip_emulated_instruction(vcpu); 12534 12535 default: 12536 kvm_inject_gp(vcpu, 0); 12537 return 1; 12538 } 12539 } 12540 EXPORT_SYMBOL_GPL(kvm_handle_invpcid); 12541 12542 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) 12543 { 12544 struct kvm_run *run = vcpu->run; 12545 struct kvm_mmio_fragment *frag; 12546 unsigned int len; 12547 12548 BUG_ON(!vcpu->mmio_needed); 12549 12550 /* Complete previous fragment */ 12551 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 12552 len = min(8u, frag->len); 12553 if (!vcpu->mmio_is_write) 12554 memcpy(frag->data, run->mmio.data, len); 12555 12556 if (frag->len <= 8) { 12557 /* Switch to the next fragment. */ 12558 frag++; 12559 vcpu->mmio_cur_fragment++; 12560 } else { 12561 /* Go forward to the next mmio piece. */ 12562 frag->data += len; 12563 frag->gpa += len; 12564 frag->len -= len; 12565 } 12566 12567 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 12568 vcpu->mmio_needed = 0; 12569 12570 // VMG change, at this point, we're always done 12571 // RIP has already been advanced 12572 return 1; 12573 } 12574 12575 // More MMIO is needed 12576 run->mmio.phys_addr = frag->gpa; 12577 run->mmio.len = min(8u, frag->len); 12578 run->mmio.is_write = vcpu->mmio_is_write; 12579 if (run->mmio.is_write) 12580 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 12581 run->exit_reason = KVM_EXIT_MMIO; 12582 12583 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12584 12585 return 0; 12586 } 12587 12588 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 12589 void *data) 12590 { 12591 int handled; 12592 struct kvm_mmio_fragment *frag; 12593 12594 if (!data) 12595 return -EINVAL; 12596 12597 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); 12598 if (handled == bytes) 12599 return 1; 12600 12601 bytes -= handled; 12602 gpa += handled; 12603 data += handled; 12604 12605 /*TODO: Check if need to increment number of frags */ 12606 frag = vcpu->mmio_fragments; 12607 vcpu->mmio_nr_fragments = 1; 12608 frag->len = bytes; 12609 frag->gpa = gpa; 12610 frag->data = data; 12611 12612 vcpu->mmio_needed = 1; 12613 vcpu->mmio_cur_fragment = 0; 12614 12615 vcpu->run->mmio.phys_addr = gpa; 12616 vcpu->run->mmio.len = min(8u, frag->len); 12617 vcpu->run->mmio.is_write = 1; 12618 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 12619 vcpu->run->exit_reason = KVM_EXIT_MMIO; 12620 12621 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12622 12623 return 0; 12624 } 12625 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); 12626 12627 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 12628 void *data) 12629 { 12630 int handled; 12631 struct kvm_mmio_fragment *frag; 12632 12633 if (!data) 12634 return -EINVAL; 12635 12636 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); 12637 if (handled == bytes) 12638 return 1; 12639 12640 bytes -= handled; 12641 gpa += handled; 12642 data += handled; 12643 12644 /*TODO: Check if need to increment number of frags */ 12645 frag = vcpu->mmio_fragments; 12646 vcpu->mmio_nr_fragments = 1; 12647 frag->len = bytes; 12648 frag->gpa = gpa; 12649 frag->data = data; 12650 12651 vcpu->mmio_needed = 1; 12652 vcpu->mmio_cur_fragment = 0; 12653 12654 vcpu->run->mmio.phys_addr = gpa; 12655 vcpu->run->mmio.len = min(8u, frag->len); 12656 vcpu->run->mmio.is_write = 0; 12657 vcpu->run->exit_reason = KVM_EXIT_MMIO; 12658 12659 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 12660 12661 return 0; 12662 } 12663 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); 12664 12665 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 12666 unsigned int port); 12667 12668 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu) 12669 { 12670 int size = vcpu->arch.pio.size; 12671 int port = vcpu->arch.pio.port; 12672 12673 vcpu->arch.pio.count = 0; 12674 if (vcpu->arch.sev_pio_count) 12675 return kvm_sev_es_outs(vcpu, size, port); 12676 return 1; 12677 } 12678 12679 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 12680 unsigned int port) 12681 { 12682 for (;;) { 12683 unsigned int count = 12684 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 12685 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count); 12686 12687 /* memcpy done already by emulator_pio_out. */ 12688 vcpu->arch.sev_pio_count -= count; 12689 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size; 12690 if (!ret) 12691 break; 12692 12693 /* Emulation done by the kernel. */ 12694 if (!vcpu->arch.sev_pio_count) 12695 return 1; 12696 } 12697 12698 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs; 12699 return 0; 12700 } 12701 12702 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 12703 unsigned int port); 12704 12705 static void advance_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 12706 { 12707 unsigned count = vcpu->arch.pio.count; 12708 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data); 12709 vcpu->arch.sev_pio_count -= count; 12710 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size; 12711 } 12712 12713 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 12714 { 12715 int size = vcpu->arch.pio.size; 12716 int port = vcpu->arch.pio.port; 12717 12718 advance_sev_es_emulated_ins(vcpu); 12719 if (vcpu->arch.sev_pio_count) 12720 return kvm_sev_es_ins(vcpu, size, port); 12721 return 1; 12722 } 12723 12724 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 12725 unsigned int port) 12726 { 12727 for (;;) { 12728 unsigned int count = 12729 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 12730 if (!__emulator_pio_in(vcpu, size, port, count)) 12731 break; 12732 12733 /* Emulation done by the kernel. */ 12734 advance_sev_es_emulated_ins(vcpu); 12735 if (!vcpu->arch.sev_pio_count) 12736 return 1; 12737 } 12738 12739 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; 12740 return 0; 12741 } 12742 12743 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 12744 unsigned int port, void *data, unsigned int count, 12745 int in) 12746 { 12747 vcpu->arch.sev_pio_data = data; 12748 vcpu->arch.sev_pio_count = count; 12749 return in ? kvm_sev_es_ins(vcpu, size, port) 12750 : kvm_sev_es_outs(vcpu, size, port); 12751 } 12752 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); 12753 12754 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); 12755 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 12756 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 12757 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 12758 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 12759 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 12760 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 12761 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 12762 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 12763 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 12764 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 12765 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); 12766 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 12767 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 12768 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 12769 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 12770 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); 12771 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 12772 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 12773 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 12774 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 12775 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); 12776 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); 12777 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq); 12778 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); 12779 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); 12780 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); 12781 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); 12782