1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * derived from drivers/kvm/kvm_main.c 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright (C) 2008 Qumranet, Inc. 9 * Copyright IBM Corporation, 2008 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 11 * 12 * Authors: 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * Amit Shah <amit.shah@qumranet.com> 16 * Ben-Ami Yassour <benami@il.ibm.com> 17 */ 18 19 #include <linux/kvm_host.h> 20 #include "irq.h" 21 #include "ioapic.h" 22 #include "mmu.h" 23 #include "i8254.h" 24 #include "tss.h" 25 #include "kvm_cache_regs.h" 26 #include "kvm_emulate.h" 27 #include "x86.h" 28 #include "cpuid.h" 29 #include "pmu.h" 30 #include "hyperv.h" 31 #include "lapic.h" 32 #include "xen.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/export.h> 40 #include <linux/moduleparam.h> 41 #include <linux/mman.h> 42 #include <linux/highmem.h> 43 #include <linux/iommu.h> 44 #include <linux/intel-iommu.h> 45 #include <linux/cpufreq.h> 46 #include <linux/user-return-notifier.h> 47 #include <linux/srcu.h> 48 #include <linux/slab.h> 49 #include <linux/perf_event.h> 50 #include <linux/uaccess.h> 51 #include <linux/hash.h> 52 #include <linux/pci.h> 53 #include <linux/timekeeper_internal.h> 54 #include <linux/pvclock_gtod.h> 55 #include <linux/kvm_irqfd.h> 56 #include <linux/irqbypass.h> 57 #include <linux/sched/stat.h> 58 #include <linux/sched/isolation.h> 59 #include <linux/mem_encrypt.h> 60 #include <linux/entry-kvm.h> 61 62 #include <trace/events/kvm.h> 63 64 #include <asm/debugreg.h> 65 #include <asm/msr.h> 66 #include <asm/desc.h> 67 #include <asm/mce.h> 68 #include <linux/kernel_stat.h> 69 #include <asm/fpu/internal.h> /* Ugh! */ 70 #include <asm/pvclock.h> 71 #include <asm/div64.h> 72 #include <asm/irq_remapping.h> 73 #include <asm/mshyperv.h> 74 #include <asm/hypervisor.h> 75 #include <asm/tlbflush.h> 76 #include <asm/intel_pt.h> 77 #include <asm/emulate_prefix.h> 78 #include <clocksource/hyperv_timer.h> 79 80 #define CREATE_TRACE_POINTS 81 #include "trace.h" 82 83 #define MAX_IO_MSRS 256 84 #define KVM_MAX_MCE_BANKS 32 85 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 86 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 87 88 #define emul_to_vcpu(ctxt) \ 89 ((struct kvm_vcpu *)(ctxt)->vcpu) 90 91 /* EFER defaults: 92 * - enable syscall per default because its emulated by KVM 93 * - enable LME and LMA per default on 64 bit KVM 94 */ 95 #ifdef CONFIG_X86_64 96 static 97 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 98 #else 99 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 100 #endif 101 102 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; 103 104 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 105 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 106 107 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 108 static void process_nmi(struct kvm_vcpu *vcpu); 109 static void process_smi(struct kvm_vcpu *vcpu); 110 static void enter_smm(struct kvm_vcpu *vcpu); 111 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 112 static void store_regs(struct kvm_vcpu *vcpu); 113 static int sync_regs(struct kvm_vcpu *vcpu); 114 115 struct kvm_x86_ops kvm_x86_ops __read_mostly; 116 EXPORT_SYMBOL_GPL(kvm_x86_ops); 117 118 #define KVM_X86_OP(func) \ 119 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ 120 *(((struct kvm_x86_ops *)0)->func)); 121 #define KVM_X86_OP_NULL KVM_X86_OP 122 #include <asm/kvm-x86-ops.h> 123 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); 124 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); 125 EXPORT_STATIC_CALL_GPL(kvm_x86_tlb_flush_current); 126 127 static bool __read_mostly ignore_msrs = 0; 128 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 129 130 bool __read_mostly report_ignored_msrs = true; 131 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 132 EXPORT_SYMBOL_GPL(report_ignored_msrs); 133 134 unsigned int min_timer_period_us = 200; 135 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 136 137 static bool __read_mostly kvmclock_periodic_sync = true; 138 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 139 140 bool __read_mostly kvm_has_tsc_control; 141 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 142 u32 __read_mostly kvm_max_guest_tsc_khz; 143 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 144 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 145 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 146 u64 __read_mostly kvm_max_tsc_scaling_ratio; 147 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 148 u64 __read_mostly kvm_default_tsc_scaling_ratio; 149 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 150 bool __read_mostly kvm_has_bus_lock_exit; 151 EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit); 152 153 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 154 static u32 __read_mostly tsc_tolerance_ppm = 250; 155 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 156 157 /* 158 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 159 * adaptive tuning starting from default advancment of 1000ns. '0' disables 160 * advancement entirely. Any other value is used as-is and disables adaptive 161 * tuning, i.e. allows priveleged userspace to set an exact advancement time. 162 */ 163 static int __read_mostly lapic_timer_advance_ns = -1; 164 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); 165 166 static bool __read_mostly vector_hashing = true; 167 module_param(vector_hashing, bool, S_IRUGO); 168 169 bool __read_mostly enable_vmware_backdoor = false; 170 module_param(enable_vmware_backdoor, bool, S_IRUGO); 171 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 172 173 static bool __read_mostly force_emulation_prefix = false; 174 module_param(force_emulation_prefix, bool, S_IRUGO); 175 176 int __read_mostly pi_inject_timer = -1; 177 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); 178 179 /* 180 * Restoring the host value for MSRs that are only consumed when running in 181 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU 182 * returns to userspace, i.e. the kernel can run with the guest's value. 183 */ 184 #define KVM_MAX_NR_USER_RETURN_MSRS 16 185 186 struct kvm_user_return_msrs_global { 187 int nr; 188 u32 msrs[KVM_MAX_NR_USER_RETURN_MSRS]; 189 }; 190 191 struct kvm_user_return_msrs { 192 struct user_return_notifier urn; 193 bool registered; 194 struct kvm_user_return_msr_values { 195 u64 host; 196 u64 curr; 197 } values[KVM_MAX_NR_USER_RETURN_MSRS]; 198 }; 199 200 static struct kvm_user_return_msrs_global __read_mostly user_return_msrs_global; 201 static struct kvm_user_return_msrs __percpu *user_return_msrs; 202 203 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 204 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 205 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 206 | XFEATURE_MASK_PKRU) 207 208 u64 __read_mostly host_efer; 209 EXPORT_SYMBOL_GPL(host_efer); 210 211 bool __read_mostly allow_smaller_maxphyaddr = 0; 212 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); 213 214 u64 __read_mostly host_xss; 215 EXPORT_SYMBOL_GPL(host_xss); 216 u64 __read_mostly supported_xss; 217 EXPORT_SYMBOL_GPL(supported_xss); 218 219 struct kvm_stats_debugfs_item debugfs_entries[] = { 220 VCPU_STAT("pf_fixed", pf_fixed), 221 VCPU_STAT("pf_guest", pf_guest), 222 VCPU_STAT("tlb_flush", tlb_flush), 223 VCPU_STAT("invlpg", invlpg), 224 VCPU_STAT("exits", exits), 225 VCPU_STAT("io_exits", io_exits), 226 VCPU_STAT("mmio_exits", mmio_exits), 227 VCPU_STAT("signal_exits", signal_exits), 228 VCPU_STAT("irq_window", irq_window_exits), 229 VCPU_STAT("nmi_window", nmi_window_exits), 230 VCPU_STAT("halt_exits", halt_exits), 231 VCPU_STAT("halt_successful_poll", halt_successful_poll), 232 VCPU_STAT("halt_attempted_poll", halt_attempted_poll), 233 VCPU_STAT("halt_poll_invalid", halt_poll_invalid), 234 VCPU_STAT("halt_wakeup", halt_wakeup), 235 VCPU_STAT("hypercalls", hypercalls), 236 VCPU_STAT("request_irq", request_irq_exits), 237 VCPU_STAT("irq_exits", irq_exits), 238 VCPU_STAT("host_state_reload", host_state_reload), 239 VCPU_STAT("fpu_reload", fpu_reload), 240 VCPU_STAT("insn_emulation", insn_emulation), 241 VCPU_STAT("insn_emulation_fail", insn_emulation_fail), 242 VCPU_STAT("irq_injections", irq_injections), 243 VCPU_STAT("nmi_injections", nmi_injections), 244 VCPU_STAT("req_event", req_event), 245 VCPU_STAT("l1d_flush", l1d_flush), 246 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns), 247 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns), 248 VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped), 249 VM_STAT("mmu_pte_write", mmu_pte_write), 250 VM_STAT("mmu_pde_zapped", mmu_pde_zapped), 251 VM_STAT("mmu_flooded", mmu_flooded), 252 VM_STAT("mmu_recycled", mmu_recycled), 253 VM_STAT("mmu_cache_miss", mmu_cache_miss), 254 VM_STAT("mmu_unsync", mmu_unsync), 255 VM_STAT("remote_tlb_flush", remote_tlb_flush), 256 VM_STAT("largepages", lpages, .mode = 0444), 257 VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444), 258 VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions), 259 { NULL } 260 }; 261 262 u64 __read_mostly host_xcr0; 263 u64 __read_mostly supported_xcr0; 264 EXPORT_SYMBOL_GPL(supported_xcr0); 265 266 static struct kmem_cache *x86_fpu_cache; 267 268 static struct kmem_cache *x86_emulator_cache; 269 270 /* 271 * When called, it means the previous get/set msr reached an invalid msr. 272 * Return true if we want to ignore/silent this failed msr access. 273 */ 274 static bool kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr, 275 u64 data, bool write) 276 { 277 const char *op = write ? "wrmsr" : "rdmsr"; 278 279 if (ignore_msrs) { 280 if (report_ignored_msrs) 281 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", 282 op, msr, data); 283 /* Mask the error */ 284 return true; 285 } else { 286 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", 287 op, msr, data); 288 return false; 289 } 290 } 291 292 static struct kmem_cache *kvm_alloc_emulator_cache(void) 293 { 294 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); 295 unsigned int size = sizeof(struct x86_emulate_ctxt); 296 297 return kmem_cache_create_usercopy("x86_emulator", size, 298 __alignof__(struct x86_emulate_ctxt), 299 SLAB_ACCOUNT, useroffset, 300 size - useroffset, NULL); 301 } 302 303 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 304 305 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 306 { 307 int i; 308 for (i = 0; i < ASYNC_PF_PER_VCPU; i++) 309 vcpu->arch.apf.gfns[i] = ~0; 310 } 311 312 static void kvm_on_user_return(struct user_return_notifier *urn) 313 { 314 unsigned slot; 315 struct kvm_user_return_msrs *msrs 316 = container_of(urn, struct kvm_user_return_msrs, urn); 317 struct kvm_user_return_msr_values *values; 318 unsigned long flags; 319 320 /* 321 * Disabling irqs at this point since the following code could be 322 * interrupted and executed through kvm_arch_hardware_disable() 323 */ 324 local_irq_save(flags); 325 if (msrs->registered) { 326 msrs->registered = false; 327 user_return_notifier_unregister(urn); 328 } 329 local_irq_restore(flags); 330 for (slot = 0; slot < user_return_msrs_global.nr; ++slot) { 331 values = &msrs->values[slot]; 332 if (values->host != values->curr) { 333 wrmsrl(user_return_msrs_global.msrs[slot], values->host); 334 values->curr = values->host; 335 } 336 } 337 } 338 339 void kvm_define_user_return_msr(unsigned slot, u32 msr) 340 { 341 BUG_ON(slot >= KVM_MAX_NR_USER_RETURN_MSRS); 342 user_return_msrs_global.msrs[slot] = msr; 343 if (slot >= user_return_msrs_global.nr) 344 user_return_msrs_global.nr = slot + 1; 345 } 346 EXPORT_SYMBOL_GPL(kvm_define_user_return_msr); 347 348 static void kvm_user_return_msr_cpu_online(void) 349 { 350 unsigned int cpu = smp_processor_id(); 351 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 352 u64 value; 353 int i; 354 355 for (i = 0; i < user_return_msrs_global.nr; ++i) { 356 rdmsrl_safe(user_return_msrs_global.msrs[i], &value); 357 msrs->values[i].host = value; 358 msrs->values[i].curr = value; 359 } 360 } 361 362 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) 363 { 364 unsigned int cpu = smp_processor_id(); 365 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 366 int err; 367 368 value = (value & mask) | (msrs->values[slot].host & ~mask); 369 if (value == msrs->values[slot].curr) 370 return 0; 371 err = wrmsrl_safe(user_return_msrs_global.msrs[slot], value); 372 if (err) 373 return 1; 374 375 msrs->values[slot].curr = value; 376 if (!msrs->registered) { 377 msrs->urn.on_user_return = kvm_on_user_return; 378 user_return_notifier_register(&msrs->urn); 379 msrs->registered = true; 380 } 381 return 0; 382 } 383 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); 384 385 static void drop_user_return_notifiers(void) 386 { 387 unsigned int cpu = smp_processor_id(); 388 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 389 390 if (msrs->registered) 391 kvm_on_user_return(&msrs->urn); 392 } 393 394 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 395 { 396 return vcpu->arch.apic_base; 397 } 398 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 399 400 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 401 { 402 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 403 } 404 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 405 406 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 407 { 408 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 409 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 410 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | 411 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 412 413 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 414 return 1; 415 if (!msr_info->host_initiated) { 416 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 417 return 1; 418 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 419 return 1; 420 } 421 422 kvm_lapic_set_base(vcpu, msr_info->data); 423 kvm_recalculate_apic_map(vcpu->kvm); 424 return 0; 425 } 426 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 427 428 asmlinkage __visible noinstr void kvm_spurious_fault(void) 429 { 430 /* Fault while not rebooting. We want the trace. */ 431 BUG_ON(!kvm_rebooting); 432 } 433 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 434 435 #define EXCPT_BENIGN 0 436 #define EXCPT_CONTRIBUTORY 1 437 #define EXCPT_PF 2 438 439 static int exception_class(int vector) 440 { 441 switch (vector) { 442 case PF_VECTOR: 443 return EXCPT_PF; 444 case DE_VECTOR: 445 case TS_VECTOR: 446 case NP_VECTOR: 447 case SS_VECTOR: 448 case GP_VECTOR: 449 return EXCPT_CONTRIBUTORY; 450 default: 451 break; 452 } 453 return EXCPT_BENIGN; 454 } 455 456 #define EXCPT_FAULT 0 457 #define EXCPT_TRAP 1 458 #define EXCPT_ABORT 2 459 #define EXCPT_INTERRUPT 3 460 461 static int exception_type(int vector) 462 { 463 unsigned int mask; 464 465 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 466 return EXCPT_INTERRUPT; 467 468 mask = 1 << vector; 469 470 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 471 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 472 return EXCPT_TRAP; 473 474 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 475 return EXCPT_ABORT; 476 477 /* Reserved exceptions will result in fault */ 478 return EXCPT_FAULT; 479 } 480 481 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) 482 { 483 unsigned nr = vcpu->arch.exception.nr; 484 bool has_payload = vcpu->arch.exception.has_payload; 485 unsigned long payload = vcpu->arch.exception.payload; 486 487 if (!has_payload) 488 return; 489 490 switch (nr) { 491 case DB_VECTOR: 492 /* 493 * "Certain debug exceptions may clear bit 0-3. The 494 * remaining contents of the DR6 register are never 495 * cleared by the processor". 496 */ 497 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 498 /* 499 * In order to reflect the #DB exception payload in guest 500 * dr6, three components need to be considered: active low 501 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, 502 * DR6_BS and DR6_BT) 503 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. 504 * In the target guest dr6: 505 * FIXED_1 bits should always be set. 506 * Active low bits should be cleared if 1-setting in payload. 507 * Active high bits should be set if 1-setting in payload. 508 * 509 * Note, the payload is compatible with the pending debug 510 * exceptions/exit qualification under VMX, that active_low bits 511 * are active high in payload. 512 * So they need to be flipped for DR6. 513 */ 514 vcpu->arch.dr6 |= DR6_ACTIVE_LOW; 515 vcpu->arch.dr6 |= payload; 516 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; 517 518 /* 519 * The #DB payload is defined as compatible with the 'pending 520 * debug exceptions' field under VMX, not DR6. While bit 12 is 521 * defined in the 'pending debug exceptions' field (enabled 522 * breakpoint), it is reserved and must be zero in DR6. 523 */ 524 vcpu->arch.dr6 &= ~BIT(12); 525 break; 526 case PF_VECTOR: 527 vcpu->arch.cr2 = payload; 528 break; 529 } 530 531 vcpu->arch.exception.has_payload = false; 532 vcpu->arch.exception.payload = 0; 533 } 534 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 535 536 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 537 unsigned nr, bool has_error, u32 error_code, 538 bool has_payload, unsigned long payload, bool reinject) 539 { 540 u32 prev_nr; 541 int class1, class2; 542 543 kvm_make_request(KVM_REQ_EVENT, vcpu); 544 545 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 546 queue: 547 if (has_error && !is_protmode(vcpu)) 548 has_error = false; 549 if (reinject) { 550 /* 551 * On vmentry, vcpu->arch.exception.pending is only 552 * true if an event injection was blocked by 553 * nested_run_pending. In that case, however, 554 * vcpu_enter_guest requests an immediate exit, 555 * and the guest shouldn't proceed far enough to 556 * need reinjection. 557 */ 558 WARN_ON_ONCE(vcpu->arch.exception.pending); 559 vcpu->arch.exception.injected = true; 560 if (WARN_ON_ONCE(has_payload)) { 561 /* 562 * A reinjected event has already 563 * delivered its payload. 564 */ 565 has_payload = false; 566 payload = 0; 567 } 568 } else { 569 vcpu->arch.exception.pending = true; 570 vcpu->arch.exception.injected = false; 571 } 572 vcpu->arch.exception.has_error_code = has_error; 573 vcpu->arch.exception.nr = nr; 574 vcpu->arch.exception.error_code = error_code; 575 vcpu->arch.exception.has_payload = has_payload; 576 vcpu->arch.exception.payload = payload; 577 if (!is_guest_mode(vcpu)) 578 kvm_deliver_exception_payload(vcpu); 579 return; 580 } 581 582 /* to check exception */ 583 prev_nr = vcpu->arch.exception.nr; 584 if (prev_nr == DF_VECTOR) { 585 /* triple fault -> shutdown */ 586 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 587 return; 588 } 589 class1 = exception_class(prev_nr); 590 class2 = exception_class(nr); 591 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 592 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 593 /* 594 * Generate double fault per SDM Table 5-5. Set 595 * exception.pending = true so that the double fault 596 * can trigger a nested vmexit. 597 */ 598 vcpu->arch.exception.pending = true; 599 vcpu->arch.exception.injected = false; 600 vcpu->arch.exception.has_error_code = true; 601 vcpu->arch.exception.nr = DF_VECTOR; 602 vcpu->arch.exception.error_code = 0; 603 vcpu->arch.exception.has_payload = false; 604 vcpu->arch.exception.payload = 0; 605 } else 606 /* replace previous exception with a new one in a hope 607 that instruction re-execution will regenerate lost 608 exception */ 609 goto queue; 610 } 611 612 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 613 { 614 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 615 } 616 EXPORT_SYMBOL_GPL(kvm_queue_exception); 617 618 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 619 { 620 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 621 } 622 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 623 624 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 625 unsigned long payload) 626 { 627 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 628 } 629 EXPORT_SYMBOL_GPL(kvm_queue_exception_p); 630 631 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 632 u32 error_code, unsigned long payload) 633 { 634 kvm_multiple_exception(vcpu, nr, true, error_code, 635 true, payload, false); 636 } 637 638 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 639 { 640 if (err) 641 kvm_inject_gp(vcpu, 0); 642 else 643 return kvm_skip_emulated_instruction(vcpu); 644 645 return 1; 646 } 647 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 648 649 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 650 { 651 ++vcpu->stat.pf_guest; 652 vcpu->arch.exception.nested_apf = 653 is_guest_mode(vcpu) && fault->async_page_fault; 654 if (vcpu->arch.exception.nested_apf) { 655 vcpu->arch.apf.nested_apf_token = fault->address; 656 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 657 } else { 658 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 659 fault->address); 660 } 661 } 662 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 663 664 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 665 struct x86_exception *fault) 666 { 667 struct kvm_mmu *fault_mmu; 668 WARN_ON_ONCE(fault->vector != PF_VECTOR); 669 670 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : 671 vcpu->arch.walk_mmu; 672 673 /* 674 * Invalidate the TLB entry for the faulting address, if it exists, 675 * else the access will fault indefinitely (and to emulate hardware). 676 */ 677 if ((fault->error_code & PFERR_PRESENT_MASK) && 678 !(fault->error_code & PFERR_RSVD_MASK)) 679 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, 680 fault_mmu->root_hpa); 681 682 fault_mmu->inject_page_fault(vcpu, fault); 683 return fault->nested_page_fault; 684 } 685 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); 686 687 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 688 { 689 atomic_inc(&vcpu->arch.nmi_queued); 690 kvm_make_request(KVM_REQ_NMI, vcpu); 691 } 692 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 693 694 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 695 { 696 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 697 } 698 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 699 700 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 701 { 702 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 703 } 704 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 705 706 /* 707 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 708 * a #GP and return false. 709 */ 710 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 711 { 712 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) 713 return true; 714 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 715 return false; 716 } 717 EXPORT_SYMBOL_GPL(kvm_require_cpl); 718 719 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 720 { 721 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 722 return true; 723 724 kvm_queue_exception(vcpu, UD_VECTOR); 725 return false; 726 } 727 EXPORT_SYMBOL_GPL(kvm_require_dr); 728 729 /* 730 * This function will be used to read from the physical memory of the currently 731 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 732 * can read from guest physical or from the guest's guest physical memory. 733 */ 734 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 735 gfn_t ngfn, void *data, int offset, int len, 736 u32 access) 737 { 738 struct x86_exception exception; 739 gfn_t real_gfn; 740 gpa_t ngpa; 741 742 ngpa = gfn_to_gpa(ngfn); 743 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 744 if (real_gfn == UNMAPPED_GVA) 745 return -EFAULT; 746 747 real_gfn = gpa_to_gfn(real_gfn); 748 749 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 750 } 751 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 752 753 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 754 void *data, int offset, int len, u32 access) 755 { 756 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 757 data, offset, len, access); 758 } 759 760 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) 761 { 762 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); 763 } 764 765 /* 766 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. 767 */ 768 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 769 { 770 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 771 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 772 int i; 773 int ret; 774 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 775 776 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 777 offset * sizeof(u64), sizeof(pdpte), 778 PFERR_USER_MASK|PFERR_WRITE_MASK); 779 if (ret < 0) { 780 ret = 0; 781 goto out; 782 } 783 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 784 if ((pdpte[i] & PT_PRESENT_MASK) && 785 (pdpte[i] & pdptr_rsvd_bits(vcpu))) { 786 ret = 0; 787 goto out; 788 } 789 } 790 ret = 1; 791 792 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 793 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 794 795 out: 796 797 return ret; 798 } 799 EXPORT_SYMBOL_GPL(load_pdptrs); 800 801 bool pdptrs_changed(struct kvm_vcpu *vcpu) 802 { 803 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 804 int offset; 805 gfn_t gfn; 806 int r; 807 808 if (!is_pae_paging(vcpu)) 809 return false; 810 811 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR)) 812 return true; 813 814 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; 815 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); 816 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 817 PFERR_USER_MASK | PFERR_WRITE_MASK); 818 if (r < 0) 819 return true; 820 821 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 822 } 823 EXPORT_SYMBOL_GPL(pdptrs_changed); 824 825 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) 826 { 827 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 828 829 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 830 kvm_clear_async_pf_completion_queue(vcpu); 831 kvm_async_pf_hash_reset(vcpu); 832 } 833 834 if ((cr0 ^ old_cr0) & update_bits) 835 kvm_mmu_reset_context(vcpu); 836 837 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 838 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 839 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 840 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 841 } 842 EXPORT_SYMBOL_GPL(kvm_post_set_cr0); 843 844 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 845 { 846 unsigned long old_cr0 = kvm_read_cr0(vcpu); 847 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG; 848 849 cr0 |= X86_CR0_ET; 850 851 #ifdef CONFIG_X86_64 852 if (cr0 & 0xffffffff00000000UL) 853 return 1; 854 #endif 855 856 cr0 &= ~CR0_RESERVED_BITS; 857 858 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 859 return 1; 860 861 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 862 return 1; 863 864 #ifdef CONFIG_X86_64 865 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && 866 (cr0 & X86_CR0_PG)) { 867 int cs_db, cs_l; 868 869 if (!is_pae(vcpu)) 870 return 1; 871 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 872 if (cs_l) 873 return 1; 874 } 875 #endif 876 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && 877 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) && 878 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu))) 879 return 1; 880 881 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 882 return 1; 883 884 static_call(kvm_x86_set_cr0)(vcpu, cr0); 885 886 kvm_post_set_cr0(vcpu, old_cr0, cr0); 887 888 return 0; 889 } 890 EXPORT_SYMBOL_GPL(kvm_set_cr0); 891 892 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 893 { 894 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 895 } 896 EXPORT_SYMBOL_GPL(kvm_lmsw); 897 898 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) 899 { 900 if (vcpu->arch.guest_state_protected) 901 return; 902 903 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 904 905 if (vcpu->arch.xcr0 != host_xcr0) 906 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 907 908 if (vcpu->arch.xsaves_enabled && 909 vcpu->arch.ia32_xss != host_xss) 910 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 911 } 912 913 if (static_cpu_has(X86_FEATURE_PKU) && 914 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 915 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) && 916 vcpu->arch.pkru != vcpu->arch.host_pkru) 917 __write_pkru(vcpu->arch.pkru); 918 } 919 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); 920 921 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) 922 { 923 if (vcpu->arch.guest_state_protected) 924 return; 925 926 if (static_cpu_has(X86_FEATURE_PKU) && 927 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || 928 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) { 929 vcpu->arch.pkru = rdpkru(); 930 if (vcpu->arch.pkru != vcpu->arch.host_pkru) 931 __write_pkru(vcpu->arch.host_pkru); 932 } 933 934 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { 935 936 if (vcpu->arch.xcr0 != host_xcr0) 937 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 938 939 if (vcpu->arch.xsaves_enabled && 940 vcpu->arch.ia32_xss != host_xss) 941 wrmsrl(MSR_IA32_XSS, host_xss); 942 } 943 944 } 945 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); 946 947 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 948 { 949 u64 xcr0 = xcr; 950 u64 old_xcr0 = vcpu->arch.xcr0; 951 u64 valid_bits; 952 953 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 954 if (index != XCR_XFEATURE_ENABLED_MASK) 955 return 1; 956 if (!(xcr0 & XFEATURE_MASK_FP)) 957 return 1; 958 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 959 return 1; 960 961 /* 962 * Do not allow the guest to set bits that we do not support 963 * saving. However, xcr0 bit 0 is always set, even if the 964 * emulated CPU does not support XSAVE (see fx_init). 965 */ 966 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 967 if (xcr0 & ~valid_bits) 968 return 1; 969 970 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 971 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 972 return 1; 973 974 if (xcr0 & XFEATURE_MASK_AVX512) { 975 if (!(xcr0 & XFEATURE_MASK_YMM)) 976 return 1; 977 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 978 return 1; 979 } 980 vcpu->arch.xcr0 = xcr0; 981 982 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 983 kvm_update_cpuid_runtime(vcpu); 984 return 0; 985 } 986 987 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 988 { 989 if (static_call(kvm_x86_get_cpl)(vcpu) == 0) 990 return __kvm_set_xcr(vcpu, index, xcr); 991 992 return 1; 993 } 994 EXPORT_SYMBOL_GPL(kvm_set_xcr); 995 996 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 997 { 998 if (cr4 & cr4_reserved_bits) 999 return false; 1000 1001 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) 1002 return false; 1003 1004 return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); 1005 } 1006 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4); 1007 1008 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) 1009 { 1010 unsigned long mmu_role_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 1011 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 1012 1013 if (((cr4 ^ old_cr4) & mmu_role_bits) || 1014 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 1015 kvm_mmu_reset_context(vcpu); 1016 } 1017 EXPORT_SYMBOL_GPL(kvm_post_set_cr4); 1018 1019 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1020 { 1021 unsigned long old_cr4 = kvm_read_cr4(vcpu); 1022 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 1023 X86_CR4_SMEP; 1024 1025 if (!kvm_is_valid_cr4(vcpu, cr4)) 1026 return 1; 1027 1028 if (is_long_mode(vcpu)) { 1029 if (!(cr4 & X86_CR4_PAE)) 1030 return 1; 1031 if ((cr4 ^ old_cr4) & X86_CR4_LA57) 1032 return 1; 1033 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 1034 && ((cr4 ^ old_cr4) & pdptr_bits) 1035 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 1036 kvm_read_cr3(vcpu))) 1037 return 1; 1038 1039 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 1040 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 1041 return 1; 1042 1043 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 1044 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 1045 return 1; 1046 } 1047 1048 static_call(kvm_x86_set_cr4)(vcpu, cr4); 1049 1050 kvm_post_set_cr4(vcpu, old_cr4, cr4); 1051 1052 return 0; 1053 } 1054 EXPORT_SYMBOL_GPL(kvm_set_cr4); 1055 1056 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 1057 { 1058 bool skip_tlb_flush = false; 1059 #ifdef CONFIG_X86_64 1060 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 1061 1062 if (pcid_enabled) { 1063 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 1064 cr3 &= ~X86_CR3_PCID_NOFLUSH; 1065 } 1066 #endif 1067 1068 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 1069 if (!skip_tlb_flush) { 1070 kvm_mmu_sync_roots(vcpu); 1071 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1072 } 1073 return 0; 1074 } 1075 1076 if (is_long_mode(vcpu) && kvm_vcpu_is_illegal_gpa(vcpu, cr3)) 1077 return 1; 1078 else if (is_pae_paging(vcpu) && 1079 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 1080 return 1; 1081 1082 kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush); 1083 vcpu->arch.cr3 = cr3; 1084 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 1085 1086 return 0; 1087 } 1088 EXPORT_SYMBOL_GPL(kvm_set_cr3); 1089 1090 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 1091 { 1092 if (cr8 & CR8_RESERVED_BITS) 1093 return 1; 1094 if (lapic_in_kernel(vcpu)) 1095 kvm_lapic_set_tpr(vcpu, cr8); 1096 else 1097 vcpu->arch.cr8 = cr8; 1098 return 0; 1099 } 1100 EXPORT_SYMBOL_GPL(kvm_set_cr8); 1101 1102 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 1103 { 1104 if (lapic_in_kernel(vcpu)) 1105 return kvm_lapic_get_cr8(vcpu); 1106 else 1107 return vcpu->arch.cr8; 1108 } 1109 EXPORT_SYMBOL_GPL(kvm_get_cr8); 1110 1111 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 1112 { 1113 int i; 1114 1115 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1116 for (i = 0; i < KVM_NR_DB_REGS; i++) 1117 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1118 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 1119 } 1120 } 1121 1122 void kvm_update_dr7(struct kvm_vcpu *vcpu) 1123 { 1124 unsigned long dr7; 1125 1126 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1127 dr7 = vcpu->arch.guest_debug_dr7; 1128 else 1129 dr7 = vcpu->arch.dr7; 1130 static_call(kvm_x86_set_dr7)(vcpu, dr7); 1131 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1132 if (dr7 & DR7_BP_EN_MASK) 1133 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1134 } 1135 EXPORT_SYMBOL_GPL(kvm_update_dr7); 1136 1137 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1138 { 1139 u64 fixed = DR6_FIXED_1; 1140 1141 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1142 fixed |= DR6_RTM; 1143 return fixed; 1144 } 1145 1146 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1147 { 1148 size_t size = ARRAY_SIZE(vcpu->arch.db); 1149 1150 switch (dr) { 1151 case 0 ... 3: 1152 vcpu->arch.db[array_index_nospec(dr, size)] = val; 1153 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1154 vcpu->arch.eff_db[dr] = val; 1155 break; 1156 case 4: 1157 case 6: 1158 if (!kvm_dr6_valid(val)) 1159 return 1; /* #GP */ 1160 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1161 break; 1162 case 5: 1163 default: /* 7 */ 1164 if (!kvm_dr7_valid(val)) 1165 return 1; /* #GP */ 1166 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1167 kvm_update_dr7(vcpu); 1168 break; 1169 } 1170 1171 return 0; 1172 } 1173 EXPORT_SYMBOL_GPL(kvm_set_dr); 1174 1175 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1176 { 1177 size_t size = ARRAY_SIZE(vcpu->arch.db); 1178 1179 switch (dr) { 1180 case 0 ... 3: 1181 *val = vcpu->arch.db[array_index_nospec(dr, size)]; 1182 break; 1183 case 4: 1184 case 6: 1185 *val = vcpu->arch.dr6; 1186 break; 1187 case 5: 1188 default: /* 7 */ 1189 *val = vcpu->arch.dr7; 1190 break; 1191 } 1192 } 1193 EXPORT_SYMBOL_GPL(kvm_get_dr); 1194 1195 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 1196 { 1197 u32 ecx = kvm_rcx_read(vcpu); 1198 u64 data; 1199 int err; 1200 1201 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 1202 if (err) 1203 return err; 1204 kvm_rax_write(vcpu, (u32)data); 1205 kvm_rdx_write(vcpu, data >> 32); 1206 return err; 1207 } 1208 EXPORT_SYMBOL_GPL(kvm_rdpmc); 1209 1210 /* 1211 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1212 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1213 * 1214 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) 1215 * extract the supported MSRs from the related const lists. 1216 * msrs_to_save is selected from the msrs_to_save_all to reflect the 1217 * capabilities of the host cpu. This capabilities test skips MSRs that are 1218 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs 1219 * may depend on host virtualization features rather than host cpu features. 1220 */ 1221 1222 static const u32 msrs_to_save_all[] = { 1223 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1224 MSR_STAR, 1225 #ifdef CONFIG_X86_64 1226 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1227 #endif 1228 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1229 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1230 MSR_IA32_SPEC_CTRL, 1231 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1232 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1233 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1234 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1235 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1236 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1237 MSR_IA32_UMWAIT_CONTROL, 1238 1239 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, 1240 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3, 1241 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, 1242 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 1243 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, 1244 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, 1245 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, 1246 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, 1247 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, 1248 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, 1249 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, 1250 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, 1251 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, 1252 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, 1253 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, 1254 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, 1255 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, 1256 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, 1257 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, 1258 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, 1259 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, 1260 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, 1261 }; 1262 1263 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; 1264 static unsigned num_msrs_to_save; 1265 1266 static const u32 emulated_msrs_all[] = { 1267 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1268 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1269 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1270 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1271 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1272 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1273 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1274 HV_X64_MSR_RESET, 1275 HV_X64_MSR_VP_INDEX, 1276 HV_X64_MSR_VP_RUNTIME, 1277 HV_X64_MSR_SCONTROL, 1278 HV_X64_MSR_STIMER0_CONFIG, 1279 HV_X64_MSR_VP_ASSIST_PAGE, 1280 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1281 HV_X64_MSR_TSC_EMULATION_STATUS, 1282 HV_X64_MSR_SYNDBG_OPTIONS, 1283 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, 1284 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, 1285 HV_X64_MSR_SYNDBG_PENDING_BUFFER, 1286 1287 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1288 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, 1289 1290 MSR_IA32_TSC_ADJUST, 1291 MSR_IA32_TSCDEADLINE, 1292 MSR_IA32_ARCH_CAPABILITIES, 1293 MSR_IA32_PERF_CAPABILITIES, 1294 MSR_IA32_MISC_ENABLE, 1295 MSR_IA32_MCG_STATUS, 1296 MSR_IA32_MCG_CTL, 1297 MSR_IA32_MCG_EXT_CTL, 1298 MSR_IA32_SMBASE, 1299 MSR_SMI_COUNT, 1300 MSR_PLATFORM_INFO, 1301 MSR_MISC_FEATURES_ENABLES, 1302 MSR_AMD64_VIRT_SPEC_CTRL, 1303 MSR_IA32_POWER_CTL, 1304 MSR_IA32_UCODE_REV, 1305 1306 /* 1307 * The following list leaves out MSRs whose values are determined 1308 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. 1309 * We always support the "true" VMX control MSRs, even if the host 1310 * processor does not, so I am putting these registers here rather 1311 * than in msrs_to_save_all. 1312 */ 1313 MSR_IA32_VMX_BASIC, 1314 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1315 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1316 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1317 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1318 MSR_IA32_VMX_MISC, 1319 MSR_IA32_VMX_CR0_FIXED0, 1320 MSR_IA32_VMX_CR4_FIXED0, 1321 MSR_IA32_VMX_VMCS_ENUM, 1322 MSR_IA32_VMX_PROCBASED_CTLS2, 1323 MSR_IA32_VMX_EPT_VPID_CAP, 1324 MSR_IA32_VMX_VMFUNC, 1325 1326 MSR_K7_HWCR, 1327 MSR_KVM_POLL_CONTROL, 1328 }; 1329 1330 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; 1331 static unsigned num_emulated_msrs; 1332 1333 /* 1334 * List of msr numbers which are used to expose MSR-based features that 1335 * can be used by a hypervisor to validate requested CPU features. 1336 */ 1337 static const u32 msr_based_features_all[] = { 1338 MSR_IA32_VMX_BASIC, 1339 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1340 MSR_IA32_VMX_PINBASED_CTLS, 1341 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1342 MSR_IA32_VMX_PROCBASED_CTLS, 1343 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1344 MSR_IA32_VMX_EXIT_CTLS, 1345 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1346 MSR_IA32_VMX_ENTRY_CTLS, 1347 MSR_IA32_VMX_MISC, 1348 MSR_IA32_VMX_CR0_FIXED0, 1349 MSR_IA32_VMX_CR0_FIXED1, 1350 MSR_IA32_VMX_CR4_FIXED0, 1351 MSR_IA32_VMX_CR4_FIXED1, 1352 MSR_IA32_VMX_VMCS_ENUM, 1353 MSR_IA32_VMX_PROCBASED_CTLS2, 1354 MSR_IA32_VMX_EPT_VPID_CAP, 1355 MSR_IA32_VMX_VMFUNC, 1356 1357 MSR_F10H_DECFG, 1358 MSR_IA32_UCODE_REV, 1359 MSR_IA32_ARCH_CAPABILITIES, 1360 MSR_IA32_PERF_CAPABILITIES, 1361 }; 1362 1363 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; 1364 static unsigned int num_msr_based_features; 1365 1366 static u64 kvm_get_arch_capabilities(void) 1367 { 1368 u64 data = 0; 1369 1370 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1371 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); 1372 1373 /* 1374 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that 1375 * the nested hypervisor runs with NX huge pages. If it is not, 1376 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other 1377 * L1 guests, so it need not worry about its own (L2) guests. 1378 */ 1379 data |= ARCH_CAP_PSCHANGE_MC_NO; 1380 1381 /* 1382 * If we're doing cache flushes (either "always" or "cond") 1383 * we will do one whenever the guest does a vmlaunch/vmresume. 1384 * If an outer hypervisor is doing the cache flush for us 1385 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that 1386 * capability to the guest too, and if EPT is disabled we're not 1387 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1388 * require a nested hypervisor to do a flush of its own. 1389 */ 1390 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1391 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1392 1393 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) 1394 data |= ARCH_CAP_RDCL_NO; 1395 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1396 data |= ARCH_CAP_SSB_NO; 1397 if (!boot_cpu_has_bug(X86_BUG_MDS)) 1398 data |= ARCH_CAP_MDS_NO; 1399 1400 if (!boot_cpu_has(X86_FEATURE_RTM)) { 1401 /* 1402 * If RTM=0 because the kernel has disabled TSX, the host might 1403 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 1404 * and therefore knows that there cannot be TAA) but keep 1405 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, 1406 * and we want to allow migrating those guests to tsx=off hosts. 1407 */ 1408 data &= ~ARCH_CAP_TAA_NO; 1409 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { 1410 data |= ARCH_CAP_TAA_NO; 1411 } else { 1412 /* 1413 * Nothing to do here; we emulate TSX_CTRL if present on the 1414 * host so the guest can choose between disabling TSX or 1415 * using VERW to clear CPU buffers. 1416 */ 1417 } 1418 1419 return data; 1420 } 1421 1422 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1423 { 1424 switch (msr->index) { 1425 case MSR_IA32_ARCH_CAPABILITIES: 1426 msr->data = kvm_get_arch_capabilities(); 1427 break; 1428 case MSR_IA32_UCODE_REV: 1429 rdmsrl_safe(msr->index, &msr->data); 1430 break; 1431 default: 1432 return static_call(kvm_x86_get_msr_feature)(msr); 1433 } 1434 return 0; 1435 } 1436 1437 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1438 { 1439 struct kvm_msr_entry msr; 1440 int r; 1441 1442 msr.index = index; 1443 r = kvm_get_msr_feature(&msr); 1444 1445 if (r == KVM_MSR_RET_INVALID) { 1446 /* Unconditionally clear the output for simplicity */ 1447 *data = 0; 1448 if (kvm_msr_ignored_check(vcpu, index, 0, false)) 1449 r = 0; 1450 } 1451 1452 if (r) 1453 return r; 1454 1455 *data = msr.data; 1456 1457 return 0; 1458 } 1459 1460 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1461 { 1462 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1463 return false; 1464 1465 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1466 return false; 1467 1468 if (efer & (EFER_LME | EFER_LMA) && 1469 !guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1470 return false; 1471 1472 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) 1473 return false; 1474 1475 return true; 1476 1477 } 1478 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1479 { 1480 if (efer & efer_reserved_bits) 1481 return false; 1482 1483 return __kvm_valid_efer(vcpu, efer); 1484 } 1485 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1486 1487 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1488 { 1489 u64 old_efer = vcpu->arch.efer; 1490 u64 efer = msr_info->data; 1491 int r; 1492 1493 if (efer & efer_reserved_bits) 1494 return 1; 1495 1496 if (!msr_info->host_initiated) { 1497 if (!__kvm_valid_efer(vcpu, efer)) 1498 return 1; 1499 1500 if (is_paging(vcpu) && 1501 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1502 return 1; 1503 } 1504 1505 efer &= ~EFER_LMA; 1506 efer |= vcpu->arch.efer & EFER_LMA; 1507 1508 r = static_call(kvm_x86_set_efer)(vcpu, efer); 1509 if (r) { 1510 WARN_ON(r > 0); 1511 return r; 1512 } 1513 1514 /* Update reserved bits */ 1515 if ((efer ^ old_efer) & EFER_NX) 1516 kvm_mmu_reset_context(vcpu); 1517 1518 return 0; 1519 } 1520 1521 void kvm_enable_efer_bits(u64 mask) 1522 { 1523 efer_reserved_bits &= ~mask; 1524 } 1525 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1526 1527 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) 1528 { 1529 struct kvm *kvm = vcpu->kvm; 1530 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges; 1531 u32 count = kvm->arch.msr_filter.count; 1532 u32 i; 1533 bool r = kvm->arch.msr_filter.default_allow; 1534 int idx; 1535 1536 /* MSR filtering not set up or x2APIC enabled, allow everything */ 1537 if (!count || (index >= 0x800 && index <= 0x8ff)) 1538 return true; 1539 1540 /* Prevent collision with set_msr_filter */ 1541 idx = srcu_read_lock(&kvm->srcu); 1542 1543 for (i = 0; i < count; i++) { 1544 u32 start = ranges[i].base; 1545 u32 end = start + ranges[i].nmsrs; 1546 u32 flags = ranges[i].flags; 1547 unsigned long *bitmap = ranges[i].bitmap; 1548 1549 if ((index >= start) && (index < end) && (flags & type)) { 1550 r = !!test_bit(index - start, bitmap); 1551 break; 1552 } 1553 } 1554 1555 srcu_read_unlock(&kvm->srcu, idx); 1556 1557 return r; 1558 } 1559 EXPORT_SYMBOL_GPL(kvm_msr_allowed); 1560 1561 /* 1562 * Write @data into the MSR specified by @index. Select MSR specific fault 1563 * checks are bypassed if @host_initiated is %true. 1564 * Returns 0 on success, non-0 otherwise. 1565 * Assumes vcpu_load() was already called. 1566 */ 1567 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, 1568 bool host_initiated) 1569 { 1570 struct msr_data msr; 1571 1572 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) 1573 return KVM_MSR_RET_FILTERED; 1574 1575 switch (index) { 1576 case MSR_FS_BASE: 1577 case MSR_GS_BASE: 1578 case MSR_KERNEL_GS_BASE: 1579 case MSR_CSTAR: 1580 case MSR_LSTAR: 1581 if (is_noncanonical_address(data, vcpu)) 1582 return 1; 1583 break; 1584 case MSR_IA32_SYSENTER_EIP: 1585 case MSR_IA32_SYSENTER_ESP: 1586 /* 1587 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1588 * non-canonical address is written on Intel but not on 1589 * AMD (which ignores the top 32-bits, because it does 1590 * not implement 64-bit SYSENTER). 1591 * 1592 * 64-bit code should hence be able to write a non-canonical 1593 * value on AMD. Making the address canonical ensures that 1594 * vmentry does not fail on Intel after writing a non-canonical 1595 * value, and that something deterministic happens if the guest 1596 * invokes 64-bit SYSENTER. 1597 */ 1598 data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); 1599 } 1600 1601 msr.data = data; 1602 msr.index = index; 1603 msr.host_initiated = host_initiated; 1604 1605 return static_call(kvm_x86_set_msr)(vcpu, &msr); 1606 } 1607 1608 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, 1609 u32 index, u64 data, bool host_initiated) 1610 { 1611 int ret = __kvm_set_msr(vcpu, index, data, host_initiated); 1612 1613 if (ret == KVM_MSR_RET_INVALID) 1614 if (kvm_msr_ignored_check(vcpu, index, data, true)) 1615 ret = 0; 1616 1617 return ret; 1618 } 1619 1620 /* 1621 * Read the MSR specified by @index into @data. Select MSR specific fault 1622 * checks are bypassed if @host_initiated is %true. 1623 * Returns 0 on success, non-0 otherwise. 1624 * Assumes vcpu_load() was already called. 1625 */ 1626 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1627 bool host_initiated) 1628 { 1629 struct msr_data msr; 1630 int ret; 1631 1632 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) 1633 return KVM_MSR_RET_FILTERED; 1634 1635 msr.index = index; 1636 msr.host_initiated = host_initiated; 1637 1638 ret = static_call(kvm_x86_get_msr)(vcpu, &msr); 1639 if (!ret) 1640 *data = msr.data; 1641 return ret; 1642 } 1643 1644 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, 1645 u32 index, u64 *data, bool host_initiated) 1646 { 1647 int ret = __kvm_get_msr(vcpu, index, data, host_initiated); 1648 1649 if (ret == KVM_MSR_RET_INVALID) { 1650 /* Unconditionally clear *data for simplicity */ 1651 *data = 0; 1652 if (kvm_msr_ignored_check(vcpu, index, 0, false)) 1653 ret = 0; 1654 } 1655 1656 return ret; 1657 } 1658 1659 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1660 { 1661 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1662 } 1663 EXPORT_SYMBOL_GPL(kvm_get_msr); 1664 1665 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) 1666 { 1667 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1668 } 1669 EXPORT_SYMBOL_GPL(kvm_set_msr); 1670 1671 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) 1672 { 1673 int err = vcpu->run->msr.error; 1674 if (!err) { 1675 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); 1676 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); 1677 } 1678 1679 return static_call(kvm_x86_complete_emulated_msr)(vcpu, err); 1680 } 1681 1682 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu) 1683 { 1684 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); 1685 } 1686 1687 static u64 kvm_msr_reason(int r) 1688 { 1689 switch (r) { 1690 case KVM_MSR_RET_INVALID: 1691 return KVM_MSR_EXIT_REASON_UNKNOWN; 1692 case KVM_MSR_RET_FILTERED: 1693 return KVM_MSR_EXIT_REASON_FILTER; 1694 default: 1695 return KVM_MSR_EXIT_REASON_INVAL; 1696 } 1697 } 1698 1699 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, 1700 u32 exit_reason, u64 data, 1701 int (*completion)(struct kvm_vcpu *vcpu), 1702 int r) 1703 { 1704 u64 msr_reason = kvm_msr_reason(r); 1705 1706 /* Check if the user wanted to know about this MSR fault */ 1707 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) 1708 return 0; 1709 1710 vcpu->run->exit_reason = exit_reason; 1711 vcpu->run->msr.error = 0; 1712 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); 1713 vcpu->run->msr.reason = msr_reason; 1714 vcpu->run->msr.index = index; 1715 vcpu->run->msr.data = data; 1716 vcpu->arch.complete_userspace_io = completion; 1717 1718 return 1; 1719 } 1720 1721 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r) 1722 { 1723 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0, 1724 complete_emulated_rdmsr, r); 1725 } 1726 1727 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r) 1728 { 1729 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data, 1730 complete_emulated_wrmsr, r); 1731 } 1732 1733 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) 1734 { 1735 u32 ecx = kvm_rcx_read(vcpu); 1736 u64 data; 1737 int r; 1738 1739 r = kvm_get_msr(vcpu, ecx, &data); 1740 1741 /* MSR read failed? See if we should ask user space */ 1742 if (r && kvm_get_msr_user_space(vcpu, ecx, r)) { 1743 /* Bounce to user space */ 1744 return 0; 1745 } 1746 1747 if (!r) { 1748 trace_kvm_msr_read(ecx, data); 1749 1750 kvm_rax_write(vcpu, data & -1u); 1751 kvm_rdx_write(vcpu, (data >> 32) & -1u); 1752 } else { 1753 trace_kvm_msr_read_ex(ecx); 1754 } 1755 1756 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1757 } 1758 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); 1759 1760 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) 1761 { 1762 u32 ecx = kvm_rcx_read(vcpu); 1763 u64 data = kvm_read_edx_eax(vcpu); 1764 int r; 1765 1766 r = kvm_set_msr(vcpu, ecx, data); 1767 1768 /* MSR write failed? See if we should ask user space */ 1769 if (r && kvm_set_msr_user_space(vcpu, ecx, data, r)) 1770 /* Bounce to user space */ 1771 return 0; 1772 1773 /* Signal all other negative errors to userspace */ 1774 if (r < 0) 1775 return r; 1776 1777 if (!r) 1778 trace_kvm_msr_write(ecx, data); 1779 else 1780 trace_kvm_msr_write_ex(ecx, data); 1781 1782 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 1783 } 1784 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); 1785 1786 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) 1787 { 1788 xfer_to_guest_mode_prepare(); 1789 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || 1790 xfer_to_guest_mode_work_pending(); 1791 } 1792 1793 /* 1794 * The fast path for frequent and performance sensitive wrmsr emulation, 1795 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces 1796 * the latency of virtual IPI by avoiding the expensive bits of transitioning 1797 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the 1798 * other cases which must be called after interrupts are enabled on the host. 1799 */ 1800 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) 1801 { 1802 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) 1803 return 1; 1804 1805 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && 1806 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && 1807 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && 1808 ((u32)(data >> 32) != X2APIC_BROADCAST)) { 1809 1810 data &= ~(1 << 12); 1811 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); 1812 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); 1813 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data); 1814 trace_kvm_apic_write(APIC_ICR, (u32)data); 1815 return 0; 1816 } 1817 1818 return 1; 1819 } 1820 1821 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) 1822 { 1823 if (!kvm_can_use_hv_timer(vcpu)) 1824 return 1; 1825 1826 kvm_set_lapic_tscdeadline_msr(vcpu, data); 1827 return 0; 1828 } 1829 1830 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) 1831 { 1832 u32 msr = kvm_rcx_read(vcpu); 1833 u64 data; 1834 fastpath_t ret = EXIT_FASTPATH_NONE; 1835 1836 switch (msr) { 1837 case APIC_BASE_MSR + (APIC_ICR >> 4): 1838 data = kvm_read_edx_eax(vcpu); 1839 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { 1840 kvm_skip_emulated_instruction(vcpu); 1841 ret = EXIT_FASTPATH_EXIT_HANDLED; 1842 } 1843 break; 1844 case MSR_IA32_TSCDEADLINE: 1845 data = kvm_read_edx_eax(vcpu); 1846 if (!handle_fastpath_set_tscdeadline(vcpu, data)) { 1847 kvm_skip_emulated_instruction(vcpu); 1848 ret = EXIT_FASTPATH_REENTER_GUEST; 1849 } 1850 break; 1851 default: 1852 break; 1853 } 1854 1855 if (ret != EXIT_FASTPATH_NONE) 1856 trace_kvm_msr_write(msr, data); 1857 1858 return ret; 1859 } 1860 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); 1861 1862 /* 1863 * Adapt set_msr() to msr_io()'s calling convention 1864 */ 1865 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1866 { 1867 return kvm_get_msr_ignored_check(vcpu, index, data, true); 1868 } 1869 1870 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1871 { 1872 return kvm_set_msr_ignored_check(vcpu, index, *data, true); 1873 } 1874 1875 #ifdef CONFIG_X86_64 1876 struct pvclock_clock { 1877 int vclock_mode; 1878 u64 cycle_last; 1879 u64 mask; 1880 u32 mult; 1881 u32 shift; 1882 u64 base_cycles; 1883 u64 offset; 1884 }; 1885 1886 struct pvclock_gtod_data { 1887 seqcount_t seq; 1888 1889 struct pvclock_clock clock; /* extract of a clocksource struct */ 1890 struct pvclock_clock raw_clock; /* extract of a clocksource struct */ 1891 1892 ktime_t offs_boot; 1893 u64 wall_time_sec; 1894 }; 1895 1896 static struct pvclock_gtod_data pvclock_gtod_data; 1897 1898 static void update_pvclock_gtod(struct timekeeper *tk) 1899 { 1900 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1901 1902 write_seqcount_begin(&vdata->seq); 1903 1904 /* copy pvclock gtod data */ 1905 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; 1906 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1907 vdata->clock.mask = tk->tkr_mono.mask; 1908 vdata->clock.mult = tk->tkr_mono.mult; 1909 vdata->clock.shift = tk->tkr_mono.shift; 1910 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 1911 vdata->clock.offset = tk->tkr_mono.base; 1912 1913 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; 1914 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; 1915 vdata->raw_clock.mask = tk->tkr_raw.mask; 1916 vdata->raw_clock.mult = tk->tkr_raw.mult; 1917 vdata->raw_clock.shift = tk->tkr_raw.shift; 1918 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; 1919 vdata->raw_clock.offset = tk->tkr_raw.base; 1920 1921 vdata->wall_time_sec = tk->xtime_sec; 1922 1923 vdata->offs_boot = tk->offs_boot; 1924 1925 write_seqcount_end(&vdata->seq); 1926 } 1927 1928 static s64 get_kvmclock_base_ns(void) 1929 { 1930 /* Count up from boot time, but with the frequency of the raw clock. */ 1931 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); 1932 } 1933 #else 1934 static s64 get_kvmclock_base_ns(void) 1935 { 1936 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ 1937 return ktime_get_boottime_ns(); 1938 } 1939 #endif 1940 1941 void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) 1942 { 1943 int version; 1944 int r; 1945 struct pvclock_wall_clock wc; 1946 u32 wc_sec_hi; 1947 u64 wall_nsec; 1948 1949 if (!wall_clock) 1950 return; 1951 1952 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1953 if (r) 1954 return; 1955 1956 if (version & 1) 1957 ++version; /* first time write, random junk */ 1958 1959 ++version; 1960 1961 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1962 return; 1963 1964 /* 1965 * The guest calculates current wall clock time by adding 1966 * system time (updated by kvm_guest_time_update below) to the 1967 * wall clock specified here. We do the reverse here. 1968 */ 1969 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); 1970 1971 wc.nsec = do_div(wall_nsec, 1000000000); 1972 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ 1973 wc.version = version; 1974 1975 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1976 1977 if (sec_hi_ofs) { 1978 wc_sec_hi = wall_nsec >> 32; 1979 kvm_write_guest(kvm, wall_clock + sec_hi_ofs, 1980 &wc_sec_hi, sizeof(wc_sec_hi)); 1981 } 1982 1983 version++; 1984 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1985 } 1986 1987 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, 1988 bool old_msr, bool host_initiated) 1989 { 1990 struct kvm_arch *ka = &vcpu->kvm->arch; 1991 1992 if (vcpu->vcpu_id == 0 && !host_initiated) { 1993 if (ka->boot_vcpu_runs_old_kvmclock != old_msr) 1994 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1995 1996 ka->boot_vcpu_runs_old_kvmclock = old_msr; 1997 } 1998 1999 vcpu->arch.time = system_time; 2000 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2001 2002 /* we verify if the enable bit is set... */ 2003 vcpu->arch.pv_time_enabled = false; 2004 if (!(system_time & 1)) 2005 return; 2006 2007 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm, 2008 &vcpu->arch.pv_time, system_time & ~1ULL, 2009 sizeof(struct pvclock_vcpu_time_info))) 2010 vcpu->arch.pv_time_enabled = true; 2011 2012 return; 2013 } 2014 2015 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 2016 { 2017 do_shl32_div32(dividend, divisor); 2018 return dividend; 2019 } 2020 2021 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 2022 s8 *pshift, u32 *pmultiplier) 2023 { 2024 uint64_t scaled64; 2025 int32_t shift = 0; 2026 uint64_t tps64; 2027 uint32_t tps32; 2028 2029 tps64 = base_hz; 2030 scaled64 = scaled_hz; 2031 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 2032 tps64 >>= 1; 2033 shift--; 2034 } 2035 2036 tps32 = (uint32_t)tps64; 2037 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 2038 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 2039 scaled64 >>= 1; 2040 else 2041 tps32 <<= 1; 2042 shift++; 2043 } 2044 2045 *pshift = shift; 2046 *pmultiplier = div_frac(scaled64, tps32); 2047 } 2048 2049 #ifdef CONFIG_X86_64 2050 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 2051 #endif 2052 2053 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 2054 static unsigned long max_tsc_khz; 2055 2056 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 2057 { 2058 u64 v = (u64)khz * (1000000 + ppm); 2059 do_div(v, 1000000); 2060 return v; 2061 } 2062 2063 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 2064 { 2065 u64 ratio; 2066 2067 /* Guest TSC same frequency as host TSC? */ 2068 if (!scale) { 2069 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 2070 return 0; 2071 } 2072 2073 /* TSC scaling supported? */ 2074 if (!kvm_has_tsc_control) { 2075 if (user_tsc_khz > tsc_khz) { 2076 vcpu->arch.tsc_catchup = 1; 2077 vcpu->arch.tsc_always_catchup = 1; 2078 return 0; 2079 } else { 2080 pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); 2081 return -1; 2082 } 2083 } 2084 2085 /* TSC scaling required - calculate ratio */ 2086 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 2087 user_tsc_khz, tsc_khz); 2088 2089 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 2090 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 2091 user_tsc_khz); 2092 return -1; 2093 } 2094 2095 vcpu->arch.tsc_scaling_ratio = ratio; 2096 return 0; 2097 } 2098 2099 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 2100 { 2101 u32 thresh_lo, thresh_hi; 2102 int use_scaling = 0; 2103 2104 /* tsc_khz can be zero if TSC calibration fails */ 2105 if (user_tsc_khz == 0) { 2106 /* set tsc_scaling_ratio to a safe value */ 2107 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 2108 return -1; 2109 } 2110 2111 /* Compute a scale to convert nanoseconds in TSC cycles */ 2112 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 2113 &vcpu->arch.virtual_tsc_shift, 2114 &vcpu->arch.virtual_tsc_mult); 2115 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 2116 2117 /* 2118 * Compute the variation in TSC rate which is acceptable 2119 * within the range of tolerance and decide if the 2120 * rate being applied is within that bounds of the hardware 2121 * rate. If so, no scaling or compensation need be done. 2122 */ 2123 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 2124 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 2125 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 2126 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 2127 use_scaling = 1; 2128 } 2129 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 2130 } 2131 2132 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 2133 { 2134 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 2135 vcpu->arch.virtual_tsc_mult, 2136 vcpu->arch.virtual_tsc_shift); 2137 tsc += vcpu->arch.this_tsc_write; 2138 return tsc; 2139 } 2140 2141 static inline int gtod_is_based_on_tsc(int mode) 2142 { 2143 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; 2144 } 2145 2146 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 2147 { 2148 #ifdef CONFIG_X86_64 2149 bool vcpus_matched; 2150 struct kvm_arch *ka = &vcpu->kvm->arch; 2151 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2152 2153 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2154 atomic_read(&vcpu->kvm->online_vcpus)); 2155 2156 /* 2157 * Once the masterclock is enabled, always perform request in 2158 * order to update it. 2159 * 2160 * In order to enable masterclock, the host clocksource must be TSC 2161 * and the vcpus need to have matched TSCs. When that happens, 2162 * perform request to enable masterclock. 2163 */ 2164 if (ka->use_master_clock || 2165 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 2166 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2167 2168 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 2169 atomic_read(&vcpu->kvm->online_vcpus), 2170 ka->use_master_clock, gtod->clock.vclock_mode); 2171 #endif 2172 } 2173 2174 /* 2175 * Multiply tsc by a fixed point number represented by ratio. 2176 * 2177 * The most significant 64-N bits (mult) of ratio represent the 2178 * integral part of the fixed point number; the remaining N bits 2179 * (frac) represent the fractional part, ie. ratio represents a fixed 2180 * point number (mult + frac * 2^(-N)). 2181 * 2182 * N equals to kvm_tsc_scaling_ratio_frac_bits. 2183 */ 2184 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 2185 { 2186 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 2187 } 2188 2189 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 2190 { 2191 u64 _tsc = tsc; 2192 u64 ratio = vcpu->arch.tsc_scaling_ratio; 2193 2194 if (ratio != kvm_default_tsc_scaling_ratio) 2195 _tsc = __scale_tsc(ratio, tsc); 2196 2197 return _tsc; 2198 } 2199 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 2200 2201 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 2202 { 2203 u64 tsc; 2204 2205 tsc = kvm_scale_tsc(vcpu, rdtsc()); 2206 2207 return target_tsc - tsc; 2208 } 2209 2210 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 2211 { 2212 return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc); 2213 } 2214 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 2215 2216 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 2217 { 2218 vcpu->arch.l1_tsc_offset = offset; 2219 vcpu->arch.tsc_offset = static_call(kvm_x86_write_l1_tsc_offset)(vcpu, offset); 2220 } 2221 2222 static inline bool kvm_check_tsc_unstable(void) 2223 { 2224 #ifdef CONFIG_X86_64 2225 /* 2226 * TSC is marked unstable when we're running on Hyper-V, 2227 * 'TSC page' clocksource is good. 2228 */ 2229 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) 2230 return false; 2231 #endif 2232 return check_tsc_unstable(); 2233 } 2234 2235 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) 2236 { 2237 struct kvm *kvm = vcpu->kvm; 2238 u64 offset, ns, elapsed; 2239 unsigned long flags; 2240 bool matched; 2241 bool already_matched; 2242 bool synchronizing = false; 2243 2244 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 2245 offset = kvm_compute_tsc_offset(vcpu, data); 2246 ns = get_kvmclock_base_ns(); 2247 elapsed = ns - kvm->arch.last_tsc_nsec; 2248 2249 if (vcpu->arch.virtual_tsc_khz) { 2250 if (data == 0) { 2251 /* 2252 * detection of vcpu initialization -- need to sync 2253 * with other vCPUs. This particularly helps to keep 2254 * kvm_clock stable after CPU hotplug 2255 */ 2256 synchronizing = true; 2257 } else { 2258 u64 tsc_exp = kvm->arch.last_tsc_write + 2259 nsec_to_cycles(vcpu, elapsed); 2260 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 2261 /* 2262 * Special case: TSC write with a small delta (1 second) 2263 * of virtual cycle time against real time is 2264 * interpreted as an attempt to synchronize the CPU. 2265 */ 2266 synchronizing = data < tsc_exp + tsc_hz && 2267 data + tsc_hz > tsc_exp; 2268 } 2269 } 2270 2271 /* 2272 * For a reliable TSC, we can match TSC offsets, and for an unstable 2273 * TSC, we add elapsed time in this computation. We could let the 2274 * compensation code attempt to catch up if we fall behind, but 2275 * it's better to try to match offsets from the beginning. 2276 */ 2277 if (synchronizing && 2278 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 2279 if (!kvm_check_tsc_unstable()) { 2280 offset = kvm->arch.cur_tsc_offset; 2281 } else { 2282 u64 delta = nsec_to_cycles(vcpu, elapsed); 2283 data += delta; 2284 offset = kvm_compute_tsc_offset(vcpu, data); 2285 } 2286 matched = true; 2287 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 2288 } else { 2289 /* 2290 * We split periods of matched TSC writes into generations. 2291 * For each generation, we track the original measured 2292 * nanosecond time, offset, and write, so if TSCs are in 2293 * sync, we can match exact offset, and if not, we can match 2294 * exact software computation in compute_guest_tsc() 2295 * 2296 * These values are tracked in kvm->arch.cur_xxx variables. 2297 */ 2298 kvm->arch.cur_tsc_generation++; 2299 kvm->arch.cur_tsc_nsec = ns; 2300 kvm->arch.cur_tsc_write = data; 2301 kvm->arch.cur_tsc_offset = offset; 2302 matched = false; 2303 } 2304 2305 /* 2306 * We also track th most recent recorded KHZ, write and time to 2307 * allow the matching interval to be extended at each write. 2308 */ 2309 kvm->arch.last_tsc_nsec = ns; 2310 kvm->arch.last_tsc_write = data; 2311 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 2312 2313 vcpu->arch.last_guest_tsc = data; 2314 2315 /* Keep track of which generation this VCPU has synchronized to */ 2316 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 2317 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 2318 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 2319 2320 kvm_vcpu_write_tsc_offset(vcpu, offset); 2321 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 2322 2323 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 2324 if (!matched) { 2325 kvm->arch.nr_vcpus_matched_tsc = 0; 2326 } else if (!already_matched) { 2327 kvm->arch.nr_vcpus_matched_tsc++; 2328 } 2329 2330 kvm_track_tsc_matching(vcpu); 2331 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 2332 } 2333 2334 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 2335 s64 adjustment) 2336 { 2337 u64 tsc_offset = vcpu->arch.l1_tsc_offset; 2338 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 2339 } 2340 2341 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 2342 { 2343 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 2344 WARN_ON(adjustment < 0); 2345 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 2346 adjust_tsc_offset_guest(vcpu, adjustment); 2347 } 2348 2349 #ifdef CONFIG_X86_64 2350 2351 static u64 read_tsc(void) 2352 { 2353 u64 ret = (u64)rdtsc_ordered(); 2354 u64 last = pvclock_gtod_data.clock.cycle_last; 2355 2356 if (likely(ret >= last)) 2357 return ret; 2358 2359 /* 2360 * GCC likes to generate cmov here, but this branch is extremely 2361 * predictable (it's just a function of time and the likely is 2362 * very likely) and there's a data dependence, so force GCC 2363 * to generate a branch instead. I don't barrier() because 2364 * we don't actually need a barrier, and if this function 2365 * ever gets inlined it will generate worse code. 2366 */ 2367 asm volatile (""); 2368 return last; 2369 } 2370 2371 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, 2372 int *mode) 2373 { 2374 long v; 2375 u64 tsc_pg_val; 2376 2377 switch (clock->vclock_mode) { 2378 case VDSO_CLOCKMODE_HVCLOCK: 2379 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 2380 tsc_timestamp); 2381 if (tsc_pg_val != U64_MAX) { 2382 /* TSC page valid */ 2383 *mode = VDSO_CLOCKMODE_HVCLOCK; 2384 v = (tsc_pg_val - clock->cycle_last) & 2385 clock->mask; 2386 } else { 2387 /* TSC page invalid */ 2388 *mode = VDSO_CLOCKMODE_NONE; 2389 } 2390 break; 2391 case VDSO_CLOCKMODE_TSC: 2392 *mode = VDSO_CLOCKMODE_TSC; 2393 *tsc_timestamp = read_tsc(); 2394 v = (*tsc_timestamp - clock->cycle_last) & 2395 clock->mask; 2396 break; 2397 default: 2398 *mode = VDSO_CLOCKMODE_NONE; 2399 } 2400 2401 if (*mode == VDSO_CLOCKMODE_NONE) 2402 *tsc_timestamp = v = 0; 2403 2404 return v * clock->mult; 2405 } 2406 2407 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) 2408 { 2409 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2410 unsigned long seq; 2411 int mode; 2412 u64 ns; 2413 2414 do { 2415 seq = read_seqcount_begin(>od->seq); 2416 ns = gtod->raw_clock.base_cycles; 2417 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); 2418 ns >>= gtod->raw_clock.shift; 2419 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); 2420 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2421 *t = ns; 2422 2423 return mode; 2424 } 2425 2426 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 2427 { 2428 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2429 unsigned long seq; 2430 int mode; 2431 u64 ns; 2432 2433 do { 2434 seq = read_seqcount_begin(>od->seq); 2435 ts->tv_sec = gtod->wall_time_sec; 2436 ns = gtod->clock.base_cycles; 2437 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2438 ns >>= gtod->clock.shift; 2439 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2440 2441 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 2442 ts->tv_nsec = ns; 2443 2444 return mode; 2445 } 2446 2447 /* returns true if host is using TSC based clocksource */ 2448 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2449 { 2450 /* checked again under seqlock below */ 2451 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2452 return false; 2453 2454 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, 2455 tsc_timestamp)); 2456 } 2457 2458 /* returns true if host is using TSC based clocksource */ 2459 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 2460 u64 *tsc_timestamp) 2461 { 2462 /* checked again under seqlock below */ 2463 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2464 return false; 2465 2466 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 2467 } 2468 #endif 2469 2470 /* 2471 * 2472 * Assuming a stable TSC across physical CPUS, and a stable TSC 2473 * across virtual CPUs, the following condition is possible. 2474 * Each numbered line represents an event visible to both 2475 * CPUs at the next numbered event. 2476 * 2477 * "timespecX" represents host monotonic time. "tscX" represents 2478 * RDTSC value. 2479 * 2480 * VCPU0 on CPU0 | VCPU1 on CPU1 2481 * 2482 * 1. read timespec0,tsc0 2483 * 2. | timespec1 = timespec0 + N 2484 * | tsc1 = tsc0 + M 2485 * 3. transition to guest | transition to guest 2486 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 2487 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 2488 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 2489 * 2490 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 2491 * 2492 * - ret0 < ret1 2493 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 2494 * ... 2495 * - 0 < N - M => M < N 2496 * 2497 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 2498 * always the case (the difference between two distinct xtime instances 2499 * might be smaller then the difference between corresponding TSC reads, 2500 * when updating guest vcpus pvclock areas). 2501 * 2502 * To avoid that problem, do not allow visibility of distinct 2503 * system_timestamp/tsc_timestamp values simultaneously: use a master 2504 * copy of host monotonic time values. Update that master copy 2505 * in lockstep. 2506 * 2507 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2508 * 2509 */ 2510 2511 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2512 { 2513 #ifdef CONFIG_X86_64 2514 struct kvm_arch *ka = &kvm->arch; 2515 int vclock_mode; 2516 bool host_tsc_clocksource, vcpus_matched; 2517 2518 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2519 atomic_read(&kvm->online_vcpus)); 2520 2521 /* 2522 * If the host uses TSC clock, then passthrough TSC as stable 2523 * to the guest. 2524 */ 2525 host_tsc_clocksource = kvm_get_time_and_clockread( 2526 &ka->master_kernel_ns, 2527 &ka->master_cycle_now); 2528 2529 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2530 && !ka->backwards_tsc_observed 2531 && !ka->boot_vcpu_runs_old_kvmclock; 2532 2533 if (ka->use_master_clock) 2534 atomic_set(&kvm_guest_has_master_clock, 1); 2535 2536 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2537 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2538 vcpus_matched); 2539 #endif 2540 } 2541 2542 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2543 { 2544 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2545 } 2546 2547 static void kvm_gen_update_masterclock(struct kvm *kvm) 2548 { 2549 #ifdef CONFIG_X86_64 2550 int i; 2551 struct kvm_vcpu *vcpu; 2552 struct kvm_arch *ka = &kvm->arch; 2553 2554 spin_lock(&ka->pvclock_gtod_sync_lock); 2555 kvm_make_mclock_inprogress_request(kvm); 2556 /* no guest entries from this point */ 2557 pvclock_update_vm_gtod_copy(kvm); 2558 2559 kvm_for_each_vcpu(i, vcpu, kvm) 2560 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2561 2562 /* guest entries allowed */ 2563 kvm_for_each_vcpu(i, vcpu, kvm) 2564 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 2565 2566 spin_unlock(&ka->pvclock_gtod_sync_lock); 2567 #endif 2568 } 2569 2570 u64 get_kvmclock_ns(struct kvm *kvm) 2571 { 2572 struct kvm_arch *ka = &kvm->arch; 2573 struct pvclock_vcpu_time_info hv_clock; 2574 u64 ret; 2575 2576 spin_lock(&ka->pvclock_gtod_sync_lock); 2577 if (!ka->use_master_clock) { 2578 spin_unlock(&ka->pvclock_gtod_sync_lock); 2579 return get_kvmclock_base_ns() + ka->kvmclock_offset; 2580 } 2581 2582 hv_clock.tsc_timestamp = ka->master_cycle_now; 2583 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 2584 spin_unlock(&ka->pvclock_gtod_sync_lock); 2585 2586 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 2587 get_cpu(); 2588 2589 if (__this_cpu_read(cpu_tsc_khz)) { 2590 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 2591 &hv_clock.tsc_shift, 2592 &hv_clock.tsc_to_system_mul); 2593 ret = __pvclock_read_cycles(&hv_clock, rdtsc()); 2594 } else 2595 ret = get_kvmclock_base_ns() + ka->kvmclock_offset; 2596 2597 put_cpu(); 2598 2599 return ret; 2600 } 2601 2602 static void kvm_setup_pvclock_page(struct kvm_vcpu *v, 2603 struct gfn_to_hva_cache *cache, 2604 unsigned int offset) 2605 { 2606 struct kvm_vcpu_arch *vcpu = &v->arch; 2607 struct pvclock_vcpu_time_info guest_hv_clock; 2608 2609 if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache, 2610 &guest_hv_clock, offset, sizeof(guest_hv_clock)))) 2611 return; 2612 2613 /* This VCPU is paused, but it's legal for a guest to read another 2614 * VCPU's kvmclock, so we really have to follow the specification where 2615 * it says that version is odd if data is being modified, and even after 2616 * it is consistent. 2617 * 2618 * Version field updates must be kept separate. This is because 2619 * kvm_write_guest_cached might use a "rep movs" instruction, and 2620 * writes within a string instruction are weakly ordered. So there 2621 * are three writes overall. 2622 * 2623 * As a small optimization, only write the version field in the first 2624 * and third write. The vcpu->pv_time cache is still valid, because the 2625 * version field is the first in the struct. 2626 */ 2627 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 2628 2629 if (guest_hv_clock.version & 1) 2630 ++guest_hv_clock.version; /* first time write, random junk */ 2631 2632 vcpu->hv_clock.version = guest_hv_clock.version + 1; 2633 kvm_write_guest_offset_cached(v->kvm, cache, 2634 &vcpu->hv_clock, offset, 2635 sizeof(vcpu->hv_clock.version)); 2636 2637 smp_wmb(); 2638 2639 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 2640 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 2641 2642 if (vcpu->pvclock_set_guest_stopped_request) { 2643 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 2644 vcpu->pvclock_set_guest_stopped_request = false; 2645 } 2646 2647 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 2648 2649 kvm_write_guest_offset_cached(v->kvm, cache, 2650 &vcpu->hv_clock, offset, 2651 sizeof(vcpu->hv_clock)); 2652 2653 smp_wmb(); 2654 2655 vcpu->hv_clock.version++; 2656 kvm_write_guest_offset_cached(v->kvm, cache, 2657 &vcpu->hv_clock, offset, 2658 sizeof(vcpu->hv_clock.version)); 2659 } 2660 2661 static int kvm_guest_time_update(struct kvm_vcpu *v) 2662 { 2663 unsigned long flags, tgt_tsc_khz; 2664 struct kvm_vcpu_arch *vcpu = &v->arch; 2665 struct kvm_arch *ka = &v->kvm->arch; 2666 s64 kernel_ns; 2667 u64 tsc_timestamp, host_tsc; 2668 u8 pvclock_flags; 2669 bool use_master_clock; 2670 2671 kernel_ns = 0; 2672 host_tsc = 0; 2673 2674 /* 2675 * If the host uses TSC clock, then passthrough TSC as stable 2676 * to the guest. 2677 */ 2678 spin_lock(&ka->pvclock_gtod_sync_lock); 2679 use_master_clock = ka->use_master_clock; 2680 if (use_master_clock) { 2681 host_tsc = ka->master_cycle_now; 2682 kernel_ns = ka->master_kernel_ns; 2683 } 2684 spin_unlock(&ka->pvclock_gtod_sync_lock); 2685 2686 /* Keep irq disabled to prevent changes to the clock */ 2687 local_irq_save(flags); 2688 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 2689 if (unlikely(tgt_tsc_khz == 0)) { 2690 local_irq_restore(flags); 2691 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2692 return 1; 2693 } 2694 if (!use_master_clock) { 2695 host_tsc = rdtsc(); 2696 kernel_ns = get_kvmclock_base_ns(); 2697 } 2698 2699 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 2700 2701 /* 2702 * We may have to catch up the TSC to match elapsed wall clock 2703 * time for two reasons, even if kvmclock is used. 2704 * 1) CPU could have been running below the maximum TSC rate 2705 * 2) Broken TSC compensation resets the base at each VCPU 2706 * entry to avoid unknown leaps of TSC even when running 2707 * again on the same CPU. This may cause apparent elapsed 2708 * time to disappear, and the guest to stand still or run 2709 * very slowly. 2710 */ 2711 if (vcpu->tsc_catchup) { 2712 u64 tsc = compute_guest_tsc(v, kernel_ns); 2713 if (tsc > tsc_timestamp) { 2714 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 2715 tsc_timestamp = tsc; 2716 } 2717 } 2718 2719 local_irq_restore(flags); 2720 2721 /* With all the info we got, fill in the values */ 2722 2723 if (kvm_has_tsc_control) 2724 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 2725 2726 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 2727 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 2728 &vcpu->hv_clock.tsc_shift, 2729 &vcpu->hv_clock.tsc_to_system_mul); 2730 vcpu->hw_tsc_khz = tgt_tsc_khz; 2731 } 2732 2733 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 2734 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 2735 vcpu->last_guest_tsc = tsc_timestamp; 2736 2737 /* If the host uses TSC clocksource, then it is stable */ 2738 pvclock_flags = 0; 2739 if (use_master_clock) 2740 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 2741 2742 vcpu->hv_clock.flags = pvclock_flags; 2743 2744 if (vcpu->pv_time_enabled) 2745 kvm_setup_pvclock_page(v, &vcpu->pv_time, 0); 2746 if (vcpu->xen.vcpu_info_set) 2747 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache, 2748 offsetof(struct compat_vcpu_info, time)); 2749 if (vcpu->xen.vcpu_time_info_set) 2750 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0); 2751 if (v == kvm_get_vcpu(v->kvm, 0)) 2752 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 2753 return 0; 2754 } 2755 2756 /* 2757 * kvmclock updates which are isolated to a given vcpu, such as 2758 * vcpu->cpu migration, should not allow system_timestamp from 2759 * the rest of the vcpus to remain static. Otherwise ntp frequency 2760 * correction applies to one vcpu's system_timestamp but not 2761 * the others. 2762 * 2763 * So in those cases, request a kvmclock update for all vcpus. 2764 * We need to rate-limit these requests though, as they can 2765 * considerably slow guests that have a large number of vcpus. 2766 * The time for a remote vcpu to update its kvmclock is bound 2767 * by the delay we use to rate-limit the updates. 2768 */ 2769 2770 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 2771 2772 static void kvmclock_update_fn(struct work_struct *work) 2773 { 2774 int i; 2775 struct delayed_work *dwork = to_delayed_work(work); 2776 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2777 kvmclock_update_work); 2778 struct kvm *kvm = container_of(ka, struct kvm, arch); 2779 struct kvm_vcpu *vcpu; 2780 2781 kvm_for_each_vcpu(i, vcpu, kvm) { 2782 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2783 kvm_vcpu_kick(vcpu); 2784 } 2785 } 2786 2787 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 2788 { 2789 struct kvm *kvm = v->kvm; 2790 2791 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2792 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 2793 KVMCLOCK_UPDATE_DELAY); 2794 } 2795 2796 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 2797 2798 static void kvmclock_sync_fn(struct work_struct *work) 2799 { 2800 struct delayed_work *dwork = to_delayed_work(work); 2801 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2802 kvmclock_sync_work); 2803 struct kvm *kvm = container_of(ka, struct kvm, arch); 2804 2805 if (!kvmclock_periodic_sync) 2806 return; 2807 2808 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 2809 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 2810 KVMCLOCK_SYNC_PERIOD); 2811 } 2812 2813 /* 2814 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 2815 */ 2816 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 2817 { 2818 /* McStatusWrEn enabled? */ 2819 if (guest_cpuid_is_amd_or_hygon(vcpu)) 2820 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 2821 2822 return false; 2823 } 2824 2825 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2826 { 2827 u64 mcg_cap = vcpu->arch.mcg_cap; 2828 unsigned bank_num = mcg_cap & 0xff; 2829 u32 msr = msr_info->index; 2830 u64 data = msr_info->data; 2831 2832 switch (msr) { 2833 case MSR_IA32_MCG_STATUS: 2834 vcpu->arch.mcg_status = data; 2835 break; 2836 case MSR_IA32_MCG_CTL: 2837 if (!(mcg_cap & MCG_CTL_P) && 2838 (data || !msr_info->host_initiated)) 2839 return 1; 2840 if (data != 0 && data != ~(u64)0) 2841 return 1; 2842 vcpu->arch.mcg_ctl = data; 2843 break; 2844 default: 2845 if (msr >= MSR_IA32_MC0_CTL && 2846 msr < MSR_IA32_MCx_CTL(bank_num)) { 2847 u32 offset = array_index_nospec( 2848 msr - MSR_IA32_MC0_CTL, 2849 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 2850 2851 /* only 0 or all 1s can be written to IA32_MCi_CTL 2852 * some Linux kernels though clear bit 10 in bank 4 to 2853 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 2854 * this to avoid an uncatched #GP in the guest 2855 */ 2856 if ((offset & 0x3) == 0 && 2857 data != 0 && (data | (1 << 10)) != ~(u64)0) 2858 return -1; 2859 2860 /* MCi_STATUS */ 2861 if (!msr_info->host_initiated && 2862 (offset & 0x3) == 1 && data != 0) { 2863 if (!can_set_mci_status(vcpu)) 2864 return -1; 2865 } 2866 2867 vcpu->arch.mce_banks[offset] = data; 2868 break; 2869 } 2870 return 1; 2871 } 2872 return 0; 2873 } 2874 2875 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) 2876 { 2877 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; 2878 2879 return (vcpu->arch.apf.msr_en_val & mask) == mask; 2880 } 2881 2882 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2883 { 2884 gpa_t gpa = data & ~0x3f; 2885 2886 /* Bits 4:5 are reserved, Should be zero */ 2887 if (data & 0x30) 2888 return 1; 2889 2890 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && 2891 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) 2892 return 1; 2893 2894 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && 2895 (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) 2896 return 1; 2897 2898 if (!lapic_in_kernel(vcpu)) 2899 return data ? 1 : 0; 2900 2901 vcpu->arch.apf.msr_en_val = data; 2902 2903 if (!kvm_pv_async_pf_enabled(vcpu)) { 2904 kvm_clear_async_pf_completion_queue(vcpu); 2905 kvm_async_pf_hash_reset(vcpu); 2906 return 0; 2907 } 2908 2909 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2910 sizeof(u64))) 2911 return 1; 2912 2913 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2914 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 2915 2916 kvm_async_pf_wakeup_all(vcpu); 2917 2918 return 0; 2919 } 2920 2921 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) 2922 { 2923 /* Bits 8-63 are reserved */ 2924 if (data >> 8) 2925 return 1; 2926 2927 if (!lapic_in_kernel(vcpu)) 2928 return 1; 2929 2930 vcpu->arch.apf.msr_int_val = data; 2931 2932 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; 2933 2934 return 0; 2935 } 2936 2937 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2938 { 2939 vcpu->arch.pv_time_enabled = false; 2940 vcpu->arch.time = 0; 2941 } 2942 2943 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) 2944 { 2945 ++vcpu->stat.tlb_flush; 2946 static_call(kvm_x86_tlb_flush_all)(vcpu); 2947 } 2948 2949 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) 2950 { 2951 ++vcpu->stat.tlb_flush; 2952 static_call(kvm_x86_tlb_flush_guest)(vcpu); 2953 } 2954 2955 static void record_steal_time(struct kvm_vcpu *vcpu) 2956 { 2957 struct kvm_host_map map; 2958 struct kvm_steal_time *st; 2959 2960 if (kvm_xen_msr_enabled(vcpu->kvm)) { 2961 kvm_xen_runstate_set_running(vcpu); 2962 return; 2963 } 2964 2965 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2966 return; 2967 2968 /* -EAGAIN is returned in atomic context so we can just return. */ 2969 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, 2970 &map, &vcpu->arch.st.cache, false)) 2971 return; 2972 2973 st = map.hva + 2974 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 2975 2976 /* 2977 * Doing a TLB flush here, on the guest's behalf, can avoid 2978 * expensive IPIs. 2979 */ 2980 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { 2981 trace_kvm_pv_tlb_flush(vcpu->vcpu_id, 2982 st->preempted & KVM_VCPU_FLUSH_TLB); 2983 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB) 2984 kvm_vcpu_flush_tlb_guest(vcpu); 2985 } 2986 2987 vcpu->arch.st.preempted = 0; 2988 2989 if (st->version & 1) 2990 st->version += 1; /* first time write, random junk */ 2991 2992 st->version += 1; 2993 2994 smp_wmb(); 2995 2996 st->steal += current->sched_info.run_delay - 2997 vcpu->arch.st.last_steal; 2998 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2999 3000 smp_wmb(); 3001 3002 st->version += 1; 3003 3004 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false); 3005 } 3006 3007 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3008 { 3009 bool pr = false; 3010 u32 msr = msr_info->index; 3011 u64 data = msr_info->data; 3012 3013 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) 3014 return kvm_xen_write_hypercall_page(vcpu, data); 3015 3016 switch (msr) { 3017 case MSR_AMD64_NB_CFG: 3018 case MSR_IA32_UCODE_WRITE: 3019 case MSR_VM_HSAVE_PA: 3020 case MSR_AMD64_PATCH_LOADER: 3021 case MSR_AMD64_BU_CFG2: 3022 case MSR_AMD64_DC_CFG: 3023 case MSR_F15H_EX_CFG: 3024 break; 3025 3026 case MSR_IA32_UCODE_REV: 3027 if (msr_info->host_initiated) 3028 vcpu->arch.microcode_version = data; 3029 break; 3030 case MSR_IA32_ARCH_CAPABILITIES: 3031 if (!msr_info->host_initiated) 3032 return 1; 3033 vcpu->arch.arch_capabilities = data; 3034 break; 3035 case MSR_IA32_PERF_CAPABILITIES: { 3036 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; 3037 3038 if (!msr_info->host_initiated) 3039 return 1; 3040 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent)) 3041 return 1; 3042 if (data & ~msr_ent.data) 3043 return 1; 3044 3045 vcpu->arch.perf_capabilities = data; 3046 3047 return 0; 3048 } 3049 case MSR_EFER: 3050 return set_efer(vcpu, msr_info); 3051 case MSR_K7_HWCR: 3052 data &= ~(u64)0x40; /* ignore flush filter disable */ 3053 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 3054 data &= ~(u64)0x8; /* ignore TLB cache disable */ 3055 3056 /* Handle McStatusWrEn */ 3057 if (data == BIT_ULL(18)) { 3058 vcpu->arch.msr_hwcr = data; 3059 } else if (data != 0) { 3060 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 3061 data); 3062 return 1; 3063 } 3064 break; 3065 case MSR_FAM10H_MMIO_CONF_BASE: 3066 if (data != 0) { 3067 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 3068 "0x%llx\n", data); 3069 return 1; 3070 } 3071 break; 3072 case 0x200 ... 0x2ff: 3073 return kvm_mtrr_set_msr(vcpu, msr, data); 3074 case MSR_IA32_APICBASE: 3075 return kvm_set_apic_base(vcpu, msr_info); 3076 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3077 return kvm_x2apic_msr_write(vcpu, msr, data); 3078 case MSR_IA32_TSCDEADLINE: 3079 kvm_set_lapic_tscdeadline_msr(vcpu, data); 3080 break; 3081 case MSR_IA32_TSC_ADJUST: 3082 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 3083 if (!msr_info->host_initiated) { 3084 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 3085 adjust_tsc_offset_guest(vcpu, adj); 3086 } 3087 vcpu->arch.ia32_tsc_adjust_msr = data; 3088 } 3089 break; 3090 case MSR_IA32_MISC_ENABLE: 3091 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && 3092 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { 3093 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) 3094 return 1; 3095 vcpu->arch.ia32_misc_enable_msr = data; 3096 kvm_update_cpuid_runtime(vcpu); 3097 } else { 3098 vcpu->arch.ia32_misc_enable_msr = data; 3099 } 3100 break; 3101 case MSR_IA32_SMBASE: 3102 if (!msr_info->host_initiated) 3103 return 1; 3104 vcpu->arch.smbase = data; 3105 break; 3106 case MSR_IA32_POWER_CTL: 3107 vcpu->arch.msr_ia32_power_ctl = data; 3108 break; 3109 case MSR_IA32_TSC: 3110 if (msr_info->host_initiated) { 3111 kvm_synchronize_tsc(vcpu, data); 3112 } else { 3113 u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; 3114 adjust_tsc_offset_guest(vcpu, adj); 3115 vcpu->arch.ia32_tsc_adjust_msr += adj; 3116 } 3117 break; 3118 case MSR_IA32_XSS: 3119 if (!msr_info->host_initiated && 3120 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3121 return 1; 3122 /* 3123 * KVM supports exposing PT to the guest, but does not support 3124 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than 3125 * XSAVES/XRSTORS to save/restore PT MSRs. 3126 */ 3127 if (data & ~supported_xss) 3128 return 1; 3129 vcpu->arch.ia32_xss = data; 3130 break; 3131 case MSR_SMI_COUNT: 3132 if (!msr_info->host_initiated) 3133 return 1; 3134 vcpu->arch.smi_count = data; 3135 break; 3136 case MSR_KVM_WALL_CLOCK_NEW: 3137 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3138 return 1; 3139 3140 vcpu->kvm->arch.wall_clock = data; 3141 kvm_write_wall_clock(vcpu->kvm, data, 0); 3142 break; 3143 case MSR_KVM_WALL_CLOCK: 3144 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3145 return 1; 3146 3147 vcpu->kvm->arch.wall_clock = data; 3148 kvm_write_wall_clock(vcpu->kvm, data, 0); 3149 break; 3150 case MSR_KVM_SYSTEM_TIME_NEW: 3151 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3152 return 1; 3153 3154 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); 3155 break; 3156 case MSR_KVM_SYSTEM_TIME: 3157 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3158 return 1; 3159 3160 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); 3161 break; 3162 case MSR_KVM_ASYNC_PF_EN: 3163 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3164 return 1; 3165 3166 if (kvm_pv_enable_async_pf(vcpu, data)) 3167 return 1; 3168 break; 3169 case MSR_KVM_ASYNC_PF_INT: 3170 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3171 return 1; 3172 3173 if (kvm_pv_enable_async_pf_int(vcpu, data)) 3174 return 1; 3175 break; 3176 case MSR_KVM_ASYNC_PF_ACK: 3177 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3178 return 1; 3179 if (data & 0x1) { 3180 vcpu->arch.apf.pageready_pending = false; 3181 kvm_check_async_pf_completion(vcpu); 3182 } 3183 break; 3184 case MSR_KVM_STEAL_TIME: 3185 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3186 return 1; 3187 3188 if (unlikely(!sched_info_on())) 3189 return 1; 3190 3191 if (data & KVM_STEAL_RESERVED_MASK) 3192 return 1; 3193 3194 vcpu->arch.st.msr_val = data; 3195 3196 if (!(data & KVM_MSR_ENABLED)) 3197 break; 3198 3199 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3200 3201 break; 3202 case MSR_KVM_PV_EOI_EN: 3203 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3204 return 1; 3205 3206 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8))) 3207 return 1; 3208 break; 3209 3210 case MSR_KVM_POLL_CONTROL: 3211 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3212 return 1; 3213 3214 /* only enable bit supported */ 3215 if (data & (-1ULL << 1)) 3216 return 1; 3217 3218 vcpu->arch.msr_kvm_poll_control = data; 3219 break; 3220 3221 case MSR_IA32_MCG_CTL: 3222 case MSR_IA32_MCG_STATUS: 3223 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3224 return set_msr_mce(vcpu, msr_info); 3225 3226 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3227 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3228 pr = true; 3229 fallthrough; 3230 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3231 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3232 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3233 return kvm_pmu_set_msr(vcpu, msr_info); 3234 3235 if (pr || data != 0) 3236 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 3237 "0x%x data 0x%llx\n", msr, data); 3238 break; 3239 case MSR_K7_CLK_CTL: 3240 /* 3241 * Ignore all writes to this no longer documented MSR. 3242 * Writes are only relevant for old K7 processors, 3243 * all pre-dating SVM, but a recommended workaround from 3244 * AMD for these chips. It is possible to specify the 3245 * affected processor models on the command line, hence 3246 * the need to ignore the workaround. 3247 */ 3248 break; 3249 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3250 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3251 case HV_X64_MSR_SYNDBG_OPTIONS: 3252 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3253 case HV_X64_MSR_CRASH_CTL: 3254 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3255 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3256 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3257 case HV_X64_MSR_TSC_EMULATION_STATUS: 3258 return kvm_hv_set_msr_common(vcpu, msr, data, 3259 msr_info->host_initiated); 3260 case MSR_IA32_BBL_CR_CTL3: 3261 /* Drop writes to this legacy MSR -- see rdmsr 3262 * counterpart for further detail. 3263 */ 3264 if (report_ignored_msrs) 3265 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 3266 msr, data); 3267 break; 3268 case MSR_AMD64_OSVW_ID_LENGTH: 3269 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3270 return 1; 3271 vcpu->arch.osvw.length = data; 3272 break; 3273 case MSR_AMD64_OSVW_STATUS: 3274 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3275 return 1; 3276 vcpu->arch.osvw.status = data; 3277 break; 3278 case MSR_PLATFORM_INFO: 3279 if (!msr_info->host_initiated || 3280 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 3281 cpuid_fault_enabled(vcpu))) 3282 return 1; 3283 vcpu->arch.msr_platform_info = data; 3284 break; 3285 case MSR_MISC_FEATURES_ENABLES: 3286 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 3287 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3288 !supports_cpuid_fault(vcpu))) 3289 return 1; 3290 vcpu->arch.msr_misc_features_enables = data; 3291 break; 3292 default: 3293 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3294 return kvm_pmu_set_msr(vcpu, msr_info); 3295 return KVM_MSR_RET_INVALID; 3296 } 3297 return 0; 3298 } 3299 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 3300 3301 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 3302 { 3303 u64 data; 3304 u64 mcg_cap = vcpu->arch.mcg_cap; 3305 unsigned bank_num = mcg_cap & 0xff; 3306 3307 switch (msr) { 3308 case MSR_IA32_P5_MC_ADDR: 3309 case MSR_IA32_P5_MC_TYPE: 3310 data = 0; 3311 break; 3312 case MSR_IA32_MCG_CAP: 3313 data = vcpu->arch.mcg_cap; 3314 break; 3315 case MSR_IA32_MCG_CTL: 3316 if (!(mcg_cap & MCG_CTL_P) && !host) 3317 return 1; 3318 data = vcpu->arch.mcg_ctl; 3319 break; 3320 case MSR_IA32_MCG_STATUS: 3321 data = vcpu->arch.mcg_status; 3322 break; 3323 default: 3324 if (msr >= MSR_IA32_MC0_CTL && 3325 msr < MSR_IA32_MCx_CTL(bank_num)) { 3326 u32 offset = array_index_nospec( 3327 msr - MSR_IA32_MC0_CTL, 3328 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); 3329 3330 data = vcpu->arch.mce_banks[offset]; 3331 break; 3332 } 3333 return 1; 3334 } 3335 *pdata = data; 3336 return 0; 3337 } 3338 3339 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3340 { 3341 switch (msr_info->index) { 3342 case MSR_IA32_PLATFORM_ID: 3343 case MSR_IA32_EBL_CR_POWERON: 3344 case MSR_IA32_LASTBRANCHFROMIP: 3345 case MSR_IA32_LASTBRANCHTOIP: 3346 case MSR_IA32_LASTINTFROMIP: 3347 case MSR_IA32_LASTINTTOIP: 3348 case MSR_K8_SYSCFG: 3349 case MSR_K8_TSEG_ADDR: 3350 case MSR_K8_TSEG_MASK: 3351 case MSR_VM_HSAVE_PA: 3352 case MSR_K8_INT_PENDING_MSG: 3353 case MSR_AMD64_NB_CFG: 3354 case MSR_FAM10H_MMIO_CONF_BASE: 3355 case MSR_AMD64_BU_CFG2: 3356 case MSR_IA32_PERF_CTL: 3357 case MSR_AMD64_DC_CFG: 3358 case MSR_F15H_EX_CFG: 3359 /* 3360 * Intel Sandy Bridge CPUs must support the RAPL (running average power 3361 * limit) MSRs. Just return 0, as we do not want to expose the host 3362 * data here. Do not conditionalize this on CPUID, as KVM does not do 3363 * so for existing CPU-specific MSRs. 3364 */ 3365 case MSR_RAPL_POWER_UNIT: 3366 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ 3367 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ 3368 case MSR_PKG_ENERGY_STATUS: /* Total package */ 3369 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ 3370 msr_info->data = 0; 3371 break; 3372 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3373 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3374 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3375 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3376 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3377 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3378 return kvm_pmu_get_msr(vcpu, msr_info); 3379 msr_info->data = 0; 3380 break; 3381 case MSR_IA32_UCODE_REV: 3382 msr_info->data = vcpu->arch.microcode_version; 3383 break; 3384 case MSR_IA32_ARCH_CAPABILITIES: 3385 if (!msr_info->host_initiated && 3386 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 3387 return 1; 3388 msr_info->data = vcpu->arch.arch_capabilities; 3389 break; 3390 case MSR_IA32_PERF_CAPABILITIES: 3391 if (!msr_info->host_initiated && 3392 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) 3393 return 1; 3394 msr_info->data = vcpu->arch.perf_capabilities; 3395 break; 3396 case MSR_IA32_POWER_CTL: 3397 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 3398 break; 3399 case MSR_IA32_TSC: { 3400 /* 3401 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset 3402 * even when not intercepted. AMD manual doesn't explicitly 3403 * state this but appears to behave the same. 3404 * 3405 * On userspace reads and writes, however, we unconditionally 3406 * return L1's TSC value to ensure backwards-compatible 3407 * behavior for migration. 3408 */ 3409 u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset : 3410 vcpu->arch.tsc_offset; 3411 3412 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset; 3413 break; 3414 } 3415 case MSR_MTRRcap: 3416 case 0x200 ... 0x2ff: 3417 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 3418 case 0xcd: /* fsb frequency */ 3419 msr_info->data = 3; 3420 break; 3421 /* 3422 * MSR_EBC_FREQUENCY_ID 3423 * Conservative value valid for even the basic CPU models. 3424 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 3425 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 3426 * and 266MHz for model 3, or 4. Set Core Clock 3427 * Frequency to System Bus Frequency Ratio to 1 (bits 3428 * 31:24) even though these are only valid for CPU 3429 * models > 2, however guests may end up dividing or 3430 * multiplying by zero otherwise. 3431 */ 3432 case MSR_EBC_FREQUENCY_ID: 3433 msr_info->data = 1 << 24; 3434 break; 3435 case MSR_IA32_APICBASE: 3436 msr_info->data = kvm_get_apic_base(vcpu); 3437 break; 3438 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3439 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 3440 case MSR_IA32_TSCDEADLINE: 3441 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 3442 break; 3443 case MSR_IA32_TSC_ADJUST: 3444 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 3445 break; 3446 case MSR_IA32_MISC_ENABLE: 3447 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 3448 break; 3449 case MSR_IA32_SMBASE: 3450 if (!msr_info->host_initiated) 3451 return 1; 3452 msr_info->data = vcpu->arch.smbase; 3453 break; 3454 case MSR_SMI_COUNT: 3455 msr_info->data = vcpu->arch.smi_count; 3456 break; 3457 case MSR_IA32_PERF_STATUS: 3458 /* TSC increment by tick */ 3459 msr_info->data = 1000ULL; 3460 /* CPU multiplier */ 3461 msr_info->data |= (((uint64_t)4ULL) << 40); 3462 break; 3463 case MSR_EFER: 3464 msr_info->data = vcpu->arch.efer; 3465 break; 3466 case MSR_KVM_WALL_CLOCK: 3467 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3468 return 1; 3469 3470 msr_info->data = vcpu->kvm->arch.wall_clock; 3471 break; 3472 case MSR_KVM_WALL_CLOCK_NEW: 3473 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3474 return 1; 3475 3476 msr_info->data = vcpu->kvm->arch.wall_clock; 3477 break; 3478 case MSR_KVM_SYSTEM_TIME: 3479 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3480 return 1; 3481 3482 msr_info->data = vcpu->arch.time; 3483 break; 3484 case MSR_KVM_SYSTEM_TIME_NEW: 3485 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3486 return 1; 3487 3488 msr_info->data = vcpu->arch.time; 3489 break; 3490 case MSR_KVM_ASYNC_PF_EN: 3491 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3492 return 1; 3493 3494 msr_info->data = vcpu->arch.apf.msr_en_val; 3495 break; 3496 case MSR_KVM_ASYNC_PF_INT: 3497 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3498 return 1; 3499 3500 msr_info->data = vcpu->arch.apf.msr_int_val; 3501 break; 3502 case MSR_KVM_ASYNC_PF_ACK: 3503 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3504 return 1; 3505 3506 msr_info->data = 0; 3507 break; 3508 case MSR_KVM_STEAL_TIME: 3509 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3510 return 1; 3511 3512 msr_info->data = vcpu->arch.st.msr_val; 3513 break; 3514 case MSR_KVM_PV_EOI_EN: 3515 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3516 return 1; 3517 3518 msr_info->data = vcpu->arch.pv_eoi.msr_val; 3519 break; 3520 case MSR_KVM_POLL_CONTROL: 3521 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3522 return 1; 3523 3524 msr_info->data = vcpu->arch.msr_kvm_poll_control; 3525 break; 3526 case MSR_IA32_P5_MC_ADDR: 3527 case MSR_IA32_P5_MC_TYPE: 3528 case MSR_IA32_MCG_CAP: 3529 case MSR_IA32_MCG_CTL: 3530 case MSR_IA32_MCG_STATUS: 3531 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3532 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 3533 msr_info->host_initiated); 3534 case MSR_IA32_XSS: 3535 if (!msr_info->host_initiated && 3536 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3537 return 1; 3538 msr_info->data = vcpu->arch.ia32_xss; 3539 break; 3540 case MSR_K7_CLK_CTL: 3541 /* 3542 * Provide expected ramp-up count for K7. All other 3543 * are set to zero, indicating minimum divisors for 3544 * every field. 3545 * 3546 * This prevents guest kernels on AMD host with CPU 3547 * type 6, model 8 and higher from exploding due to 3548 * the rdmsr failing. 3549 */ 3550 msr_info->data = 0x20000000; 3551 break; 3552 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3553 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3554 case HV_X64_MSR_SYNDBG_OPTIONS: 3555 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3556 case HV_X64_MSR_CRASH_CTL: 3557 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3558 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3559 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3560 case HV_X64_MSR_TSC_EMULATION_STATUS: 3561 return kvm_hv_get_msr_common(vcpu, 3562 msr_info->index, &msr_info->data, 3563 msr_info->host_initiated); 3564 case MSR_IA32_BBL_CR_CTL3: 3565 /* This legacy MSR exists but isn't fully documented in current 3566 * silicon. It is however accessed by winxp in very narrow 3567 * scenarios where it sets bit #19, itself documented as 3568 * a "reserved" bit. Best effort attempt to source coherent 3569 * read data here should the balance of the register be 3570 * interpreted by the guest: 3571 * 3572 * L2 cache control register 3: 64GB range, 256KB size, 3573 * enabled, latency 0x1, configured 3574 */ 3575 msr_info->data = 0xbe702111; 3576 break; 3577 case MSR_AMD64_OSVW_ID_LENGTH: 3578 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3579 return 1; 3580 msr_info->data = vcpu->arch.osvw.length; 3581 break; 3582 case MSR_AMD64_OSVW_STATUS: 3583 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3584 return 1; 3585 msr_info->data = vcpu->arch.osvw.status; 3586 break; 3587 case MSR_PLATFORM_INFO: 3588 if (!msr_info->host_initiated && 3589 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 3590 return 1; 3591 msr_info->data = vcpu->arch.msr_platform_info; 3592 break; 3593 case MSR_MISC_FEATURES_ENABLES: 3594 msr_info->data = vcpu->arch.msr_misc_features_enables; 3595 break; 3596 case MSR_K7_HWCR: 3597 msr_info->data = vcpu->arch.msr_hwcr; 3598 break; 3599 default: 3600 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3601 return kvm_pmu_get_msr(vcpu, msr_info); 3602 return KVM_MSR_RET_INVALID; 3603 } 3604 return 0; 3605 } 3606 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 3607 3608 /* 3609 * Read or write a bunch of msrs. All parameters are kernel addresses. 3610 * 3611 * @return number of msrs set successfully. 3612 */ 3613 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 3614 struct kvm_msr_entry *entries, 3615 int (*do_msr)(struct kvm_vcpu *vcpu, 3616 unsigned index, u64 *data)) 3617 { 3618 int i; 3619 3620 for (i = 0; i < msrs->nmsrs; ++i) 3621 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 3622 break; 3623 3624 return i; 3625 } 3626 3627 /* 3628 * Read or write a bunch of msrs. Parameters are user addresses. 3629 * 3630 * @return number of msrs set successfully. 3631 */ 3632 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 3633 int (*do_msr)(struct kvm_vcpu *vcpu, 3634 unsigned index, u64 *data), 3635 int writeback) 3636 { 3637 struct kvm_msrs msrs; 3638 struct kvm_msr_entry *entries; 3639 int r, n; 3640 unsigned size; 3641 3642 r = -EFAULT; 3643 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 3644 goto out; 3645 3646 r = -E2BIG; 3647 if (msrs.nmsrs >= MAX_IO_MSRS) 3648 goto out; 3649 3650 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 3651 entries = memdup_user(user_msrs->entries, size); 3652 if (IS_ERR(entries)) { 3653 r = PTR_ERR(entries); 3654 goto out; 3655 } 3656 3657 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 3658 if (r < 0) 3659 goto out_free; 3660 3661 r = -EFAULT; 3662 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 3663 goto out_free; 3664 3665 r = n; 3666 3667 out_free: 3668 kfree(entries); 3669 out: 3670 return r; 3671 } 3672 3673 static inline bool kvm_can_mwait_in_guest(void) 3674 { 3675 return boot_cpu_has(X86_FEATURE_MWAIT) && 3676 !boot_cpu_has_bug(X86_BUG_MONITOR) && 3677 boot_cpu_has(X86_FEATURE_ARAT); 3678 } 3679 3680 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, 3681 struct kvm_cpuid2 __user *cpuid_arg) 3682 { 3683 struct kvm_cpuid2 cpuid; 3684 int r; 3685 3686 r = -EFAULT; 3687 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3688 return r; 3689 3690 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3691 if (r) 3692 return r; 3693 3694 r = -EFAULT; 3695 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 3696 return r; 3697 3698 return 0; 3699 } 3700 3701 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 3702 { 3703 int r = 0; 3704 3705 switch (ext) { 3706 case KVM_CAP_IRQCHIP: 3707 case KVM_CAP_HLT: 3708 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 3709 case KVM_CAP_SET_TSS_ADDR: 3710 case KVM_CAP_EXT_CPUID: 3711 case KVM_CAP_EXT_EMUL_CPUID: 3712 case KVM_CAP_CLOCKSOURCE: 3713 case KVM_CAP_PIT: 3714 case KVM_CAP_NOP_IO_DELAY: 3715 case KVM_CAP_MP_STATE: 3716 case KVM_CAP_SYNC_MMU: 3717 case KVM_CAP_USER_NMI: 3718 case KVM_CAP_REINJECT_CONTROL: 3719 case KVM_CAP_IRQ_INJECT_STATUS: 3720 case KVM_CAP_IOEVENTFD: 3721 case KVM_CAP_IOEVENTFD_NO_LENGTH: 3722 case KVM_CAP_PIT2: 3723 case KVM_CAP_PIT_STATE2: 3724 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 3725 case KVM_CAP_VCPU_EVENTS: 3726 case KVM_CAP_HYPERV: 3727 case KVM_CAP_HYPERV_VAPIC: 3728 case KVM_CAP_HYPERV_SPIN: 3729 case KVM_CAP_HYPERV_SYNIC: 3730 case KVM_CAP_HYPERV_SYNIC2: 3731 case KVM_CAP_HYPERV_VP_INDEX: 3732 case KVM_CAP_HYPERV_EVENTFD: 3733 case KVM_CAP_HYPERV_TLBFLUSH: 3734 case KVM_CAP_HYPERV_SEND_IPI: 3735 case KVM_CAP_HYPERV_CPUID: 3736 case KVM_CAP_SYS_HYPERV_CPUID: 3737 case KVM_CAP_PCI_SEGMENT: 3738 case KVM_CAP_DEBUGREGS: 3739 case KVM_CAP_X86_ROBUST_SINGLESTEP: 3740 case KVM_CAP_XSAVE: 3741 case KVM_CAP_ASYNC_PF: 3742 case KVM_CAP_ASYNC_PF_INT: 3743 case KVM_CAP_GET_TSC_KHZ: 3744 case KVM_CAP_KVMCLOCK_CTRL: 3745 case KVM_CAP_READONLY_MEM: 3746 case KVM_CAP_HYPERV_TIME: 3747 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 3748 case KVM_CAP_TSC_DEADLINE_TIMER: 3749 case KVM_CAP_DISABLE_QUIRKS: 3750 case KVM_CAP_SET_BOOT_CPU_ID: 3751 case KVM_CAP_SPLIT_IRQCHIP: 3752 case KVM_CAP_IMMEDIATE_EXIT: 3753 case KVM_CAP_PMU_EVENT_FILTER: 3754 case KVM_CAP_GET_MSR_FEATURES: 3755 case KVM_CAP_MSR_PLATFORM_INFO: 3756 case KVM_CAP_EXCEPTION_PAYLOAD: 3757 case KVM_CAP_SET_GUEST_DEBUG: 3758 case KVM_CAP_LAST_CPU: 3759 case KVM_CAP_X86_USER_SPACE_MSR: 3760 case KVM_CAP_X86_MSR_FILTER: 3761 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 3762 r = 1; 3763 break; 3764 #ifdef CONFIG_KVM_XEN 3765 case KVM_CAP_XEN_HVM: 3766 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | 3767 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | 3768 KVM_XEN_HVM_CONFIG_SHARED_INFO; 3769 if (sched_info_on()) 3770 r |= KVM_XEN_HVM_CONFIG_RUNSTATE; 3771 break; 3772 #endif 3773 case KVM_CAP_SYNC_REGS: 3774 r = KVM_SYNC_X86_VALID_FIELDS; 3775 break; 3776 case KVM_CAP_ADJUST_CLOCK: 3777 r = KVM_CLOCK_TSC_STABLE; 3778 break; 3779 case KVM_CAP_X86_DISABLE_EXITS: 3780 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | 3781 KVM_X86_DISABLE_EXITS_CSTATE; 3782 if(kvm_can_mwait_in_guest()) 3783 r |= KVM_X86_DISABLE_EXITS_MWAIT; 3784 break; 3785 case KVM_CAP_X86_SMM: 3786 /* SMBASE is usually relocated above 1M on modern chipsets, 3787 * and SMM handlers might indeed rely on 4G segment limits, 3788 * so do not report SMM to be available if real mode is 3789 * emulated via vm86 mode. Still, do not go to great lengths 3790 * to avoid userspace's usage of the feature, because it is a 3791 * fringe case that is not enabled except via specific settings 3792 * of the module parameters. 3793 */ 3794 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); 3795 break; 3796 case KVM_CAP_VAPIC: 3797 r = !static_call(kvm_x86_cpu_has_accelerated_tpr)(); 3798 break; 3799 case KVM_CAP_NR_VCPUS: 3800 r = KVM_SOFT_MAX_VCPUS; 3801 break; 3802 case KVM_CAP_MAX_VCPUS: 3803 r = KVM_MAX_VCPUS; 3804 break; 3805 case KVM_CAP_MAX_VCPU_ID: 3806 r = KVM_MAX_VCPU_ID; 3807 break; 3808 case KVM_CAP_PV_MMU: /* obsolete */ 3809 r = 0; 3810 break; 3811 case KVM_CAP_MCE: 3812 r = KVM_MAX_MCE_BANKS; 3813 break; 3814 case KVM_CAP_XCRS: 3815 r = boot_cpu_has(X86_FEATURE_XSAVE); 3816 break; 3817 case KVM_CAP_TSC_CONTROL: 3818 r = kvm_has_tsc_control; 3819 break; 3820 case KVM_CAP_X2APIC_API: 3821 r = KVM_X2APIC_API_VALID_FLAGS; 3822 break; 3823 case KVM_CAP_NESTED_STATE: 3824 r = kvm_x86_ops.nested_ops->get_state ? 3825 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; 3826 break; 3827 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 3828 r = kvm_x86_ops.enable_direct_tlbflush != NULL; 3829 break; 3830 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 3831 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; 3832 break; 3833 case KVM_CAP_SMALLER_MAXPHYADDR: 3834 r = (int) allow_smaller_maxphyaddr; 3835 break; 3836 case KVM_CAP_STEAL_TIME: 3837 r = sched_info_on(); 3838 break; 3839 case KVM_CAP_X86_BUS_LOCK_EXIT: 3840 if (kvm_has_bus_lock_exit) 3841 r = KVM_BUS_LOCK_DETECTION_OFF | 3842 KVM_BUS_LOCK_DETECTION_EXIT; 3843 else 3844 r = 0; 3845 break; 3846 default: 3847 break; 3848 } 3849 return r; 3850 3851 } 3852 3853 long kvm_arch_dev_ioctl(struct file *filp, 3854 unsigned int ioctl, unsigned long arg) 3855 { 3856 void __user *argp = (void __user *)arg; 3857 long r; 3858 3859 switch (ioctl) { 3860 case KVM_GET_MSR_INDEX_LIST: { 3861 struct kvm_msr_list __user *user_msr_list = argp; 3862 struct kvm_msr_list msr_list; 3863 unsigned n; 3864 3865 r = -EFAULT; 3866 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3867 goto out; 3868 n = msr_list.nmsrs; 3869 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 3870 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3871 goto out; 3872 r = -E2BIG; 3873 if (n < msr_list.nmsrs) 3874 goto out; 3875 r = -EFAULT; 3876 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 3877 num_msrs_to_save * sizeof(u32))) 3878 goto out; 3879 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 3880 &emulated_msrs, 3881 num_emulated_msrs * sizeof(u32))) 3882 goto out; 3883 r = 0; 3884 break; 3885 } 3886 case KVM_GET_SUPPORTED_CPUID: 3887 case KVM_GET_EMULATED_CPUID: { 3888 struct kvm_cpuid2 __user *cpuid_arg = argp; 3889 struct kvm_cpuid2 cpuid; 3890 3891 r = -EFAULT; 3892 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 3893 goto out; 3894 3895 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 3896 ioctl); 3897 if (r) 3898 goto out; 3899 3900 r = -EFAULT; 3901 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 3902 goto out; 3903 r = 0; 3904 break; 3905 } 3906 case KVM_X86_GET_MCE_CAP_SUPPORTED: 3907 r = -EFAULT; 3908 if (copy_to_user(argp, &kvm_mce_cap_supported, 3909 sizeof(kvm_mce_cap_supported))) 3910 goto out; 3911 r = 0; 3912 break; 3913 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 3914 struct kvm_msr_list __user *user_msr_list = argp; 3915 struct kvm_msr_list msr_list; 3916 unsigned int n; 3917 3918 r = -EFAULT; 3919 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3920 goto out; 3921 n = msr_list.nmsrs; 3922 msr_list.nmsrs = num_msr_based_features; 3923 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3924 goto out; 3925 r = -E2BIG; 3926 if (n < msr_list.nmsrs) 3927 goto out; 3928 r = -EFAULT; 3929 if (copy_to_user(user_msr_list->indices, &msr_based_features, 3930 num_msr_based_features * sizeof(u32))) 3931 goto out; 3932 r = 0; 3933 break; 3934 } 3935 case KVM_GET_MSRS: 3936 r = msr_io(NULL, argp, do_get_msr_feature, 1); 3937 break; 3938 case KVM_GET_SUPPORTED_HV_CPUID: 3939 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); 3940 break; 3941 default: 3942 r = -EINVAL; 3943 break; 3944 } 3945 out: 3946 return r; 3947 } 3948 3949 static void wbinvd_ipi(void *garbage) 3950 { 3951 wbinvd(); 3952 } 3953 3954 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 3955 { 3956 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 3957 } 3958 3959 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 3960 { 3961 /* Address WBINVD may be executed by guest */ 3962 if (need_emulate_wbinvd(vcpu)) { 3963 if (static_call(kvm_x86_has_wbinvd_exit)()) 3964 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 3965 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 3966 smp_call_function_single(vcpu->cpu, 3967 wbinvd_ipi, NULL, 1); 3968 } 3969 3970 static_call(kvm_x86_vcpu_load)(vcpu, cpu); 3971 3972 /* Save host pkru register if supported */ 3973 vcpu->arch.host_pkru = read_pkru(); 3974 3975 /* Apply any externally detected TSC adjustments (due to suspend) */ 3976 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 3977 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 3978 vcpu->arch.tsc_offset_adjustment = 0; 3979 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3980 } 3981 3982 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 3983 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 3984 rdtsc() - vcpu->arch.last_host_tsc; 3985 if (tsc_delta < 0) 3986 mark_tsc_unstable("KVM discovered backwards TSC"); 3987 3988 if (kvm_check_tsc_unstable()) { 3989 u64 offset = kvm_compute_tsc_offset(vcpu, 3990 vcpu->arch.last_guest_tsc); 3991 kvm_vcpu_write_tsc_offset(vcpu, offset); 3992 vcpu->arch.tsc_catchup = 1; 3993 } 3994 3995 if (kvm_lapic_hv_timer_in_use(vcpu)) 3996 kvm_lapic_restart_hv_timer(vcpu); 3997 3998 /* 3999 * On a host with synchronized TSC, there is no need to update 4000 * kvmclock on vcpu->cpu migration 4001 */ 4002 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 4003 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 4004 if (vcpu->cpu != cpu) 4005 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 4006 vcpu->cpu = cpu; 4007 } 4008 4009 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 4010 } 4011 4012 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 4013 { 4014 struct kvm_host_map map; 4015 struct kvm_steal_time *st; 4016 int idx; 4017 4018 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 4019 return; 4020 4021 if (vcpu->arch.st.preempted) 4022 return; 4023 4024 /* 4025 * Take the srcu lock as memslots will be accessed to check the gfn 4026 * cache generation against the memslots generation. 4027 */ 4028 idx = srcu_read_lock(&vcpu->kvm->srcu); 4029 4030 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map, 4031 &vcpu->arch.st.cache, true)) 4032 goto out; 4033 4034 st = map.hva + 4035 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS); 4036 4037 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 4038 4039 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true); 4040 4041 out: 4042 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4043 } 4044 4045 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 4046 { 4047 if (vcpu->preempted && !vcpu->arch.guest_state_protected) 4048 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); 4049 4050 if (kvm_xen_msr_enabled(vcpu->kvm)) 4051 kvm_xen_runstate_set_preempted(vcpu); 4052 else 4053 kvm_steal_time_set_preempted(vcpu); 4054 4055 static_call(kvm_x86_vcpu_put)(vcpu); 4056 vcpu->arch.last_host_tsc = rdtsc(); 4057 /* 4058 * If userspace has set any breakpoints or watchpoints, dr6 is restored 4059 * on every vmexit, but if not, we might have a stale dr6 from the 4060 * guest. do_debug expects dr6 to be cleared after it runs, do the same. 4061 */ 4062 set_debugreg(0, 6); 4063 } 4064 4065 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 4066 struct kvm_lapic_state *s) 4067 { 4068 if (vcpu->arch.apicv_active) 4069 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 4070 4071 return kvm_apic_get_state(vcpu, s); 4072 } 4073 4074 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 4075 struct kvm_lapic_state *s) 4076 { 4077 int r; 4078 4079 r = kvm_apic_set_state(vcpu, s); 4080 if (r) 4081 return r; 4082 update_cr8_intercept(vcpu); 4083 4084 return 0; 4085 } 4086 4087 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 4088 { 4089 /* 4090 * We can accept userspace's request for interrupt injection 4091 * as long as we have a place to store the interrupt number. 4092 * The actual injection will happen when the CPU is able to 4093 * deliver the interrupt. 4094 */ 4095 if (kvm_cpu_has_extint(vcpu)) 4096 return false; 4097 4098 /* Acknowledging ExtINT does not happen if LINT0 is masked. */ 4099 return (!lapic_in_kernel(vcpu) || 4100 kvm_apic_accept_pic_intr(vcpu)); 4101 } 4102 4103 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 4104 { 4105 return kvm_arch_interrupt_allowed(vcpu) && 4106 kvm_cpu_accept_dm_intr(vcpu); 4107 } 4108 4109 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 4110 struct kvm_interrupt *irq) 4111 { 4112 if (irq->irq >= KVM_NR_INTERRUPTS) 4113 return -EINVAL; 4114 4115 if (!irqchip_in_kernel(vcpu->kvm)) { 4116 kvm_queue_interrupt(vcpu, irq->irq, false); 4117 kvm_make_request(KVM_REQ_EVENT, vcpu); 4118 return 0; 4119 } 4120 4121 /* 4122 * With in-kernel LAPIC, we only use this to inject EXTINT, so 4123 * fail for in-kernel 8259. 4124 */ 4125 if (pic_in_kernel(vcpu->kvm)) 4126 return -ENXIO; 4127 4128 if (vcpu->arch.pending_external_vector != -1) 4129 return -EEXIST; 4130 4131 vcpu->arch.pending_external_vector = irq->irq; 4132 kvm_make_request(KVM_REQ_EVENT, vcpu); 4133 return 0; 4134 } 4135 4136 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 4137 { 4138 kvm_inject_nmi(vcpu); 4139 4140 return 0; 4141 } 4142 4143 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 4144 { 4145 kvm_make_request(KVM_REQ_SMI, vcpu); 4146 4147 return 0; 4148 } 4149 4150 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 4151 struct kvm_tpr_access_ctl *tac) 4152 { 4153 if (tac->flags) 4154 return -EINVAL; 4155 vcpu->arch.tpr_access_reporting = !!tac->enabled; 4156 return 0; 4157 } 4158 4159 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 4160 u64 mcg_cap) 4161 { 4162 int r; 4163 unsigned bank_num = mcg_cap & 0xff, bank; 4164 4165 r = -EINVAL; 4166 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) 4167 goto out; 4168 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 4169 goto out; 4170 r = 0; 4171 vcpu->arch.mcg_cap = mcg_cap; 4172 /* Init IA32_MCG_CTL to all 1s */ 4173 if (mcg_cap & MCG_CTL_P) 4174 vcpu->arch.mcg_ctl = ~(u64)0; 4175 /* Init IA32_MCi_CTL to all 1s */ 4176 for (bank = 0; bank < bank_num; bank++) 4177 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 4178 4179 static_call(kvm_x86_setup_mce)(vcpu); 4180 out: 4181 return r; 4182 } 4183 4184 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 4185 struct kvm_x86_mce *mce) 4186 { 4187 u64 mcg_cap = vcpu->arch.mcg_cap; 4188 unsigned bank_num = mcg_cap & 0xff; 4189 u64 *banks = vcpu->arch.mce_banks; 4190 4191 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 4192 return -EINVAL; 4193 /* 4194 * if IA32_MCG_CTL is not all 1s, the uncorrected error 4195 * reporting is disabled 4196 */ 4197 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 4198 vcpu->arch.mcg_ctl != ~(u64)0) 4199 return 0; 4200 banks += 4 * mce->bank; 4201 /* 4202 * if IA32_MCi_CTL is not all 1s, the uncorrected error 4203 * reporting is disabled for the bank 4204 */ 4205 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 4206 return 0; 4207 if (mce->status & MCI_STATUS_UC) { 4208 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 4209 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 4210 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 4211 return 0; 4212 } 4213 if (banks[1] & MCI_STATUS_VAL) 4214 mce->status |= MCI_STATUS_OVER; 4215 banks[2] = mce->addr; 4216 banks[3] = mce->misc; 4217 vcpu->arch.mcg_status = mce->mcg_status; 4218 banks[1] = mce->status; 4219 kvm_queue_exception(vcpu, MC_VECTOR); 4220 } else if (!(banks[1] & MCI_STATUS_VAL) 4221 || !(banks[1] & MCI_STATUS_UC)) { 4222 if (banks[1] & MCI_STATUS_VAL) 4223 mce->status |= MCI_STATUS_OVER; 4224 banks[2] = mce->addr; 4225 banks[3] = mce->misc; 4226 banks[1] = mce->status; 4227 } else 4228 banks[1] |= MCI_STATUS_OVER; 4229 return 0; 4230 } 4231 4232 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 4233 struct kvm_vcpu_events *events) 4234 { 4235 process_nmi(vcpu); 4236 4237 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 4238 process_smi(vcpu); 4239 4240 /* 4241 * In guest mode, payload delivery should be deferred, 4242 * so that the L1 hypervisor can intercept #PF before 4243 * CR2 is modified (or intercept #DB before DR6 is 4244 * modified under nVMX). Unless the per-VM capability, 4245 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of 4246 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we 4247 * opportunistically defer the exception payload, deliver it if the 4248 * capability hasn't been requested before processing a 4249 * KVM_GET_VCPU_EVENTS. 4250 */ 4251 if (!vcpu->kvm->arch.exception_payload_enabled && 4252 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) 4253 kvm_deliver_exception_payload(vcpu); 4254 4255 /* 4256 * The API doesn't provide the instruction length for software 4257 * exceptions, so don't report them. As long as the guest RIP 4258 * isn't advanced, we should expect to encounter the exception 4259 * again. 4260 */ 4261 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { 4262 events->exception.injected = 0; 4263 events->exception.pending = 0; 4264 } else { 4265 events->exception.injected = vcpu->arch.exception.injected; 4266 events->exception.pending = vcpu->arch.exception.pending; 4267 /* 4268 * For ABI compatibility, deliberately conflate 4269 * pending and injected exceptions when 4270 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 4271 */ 4272 if (!vcpu->kvm->arch.exception_payload_enabled) 4273 events->exception.injected |= 4274 vcpu->arch.exception.pending; 4275 } 4276 events->exception.nr = vcpu->arch.exception.nr; 4277 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 4278 events->exception.error_code = vcpu->arch.exception.error_code; 4279 events->exception_has_payload = vcpu->arch.exception.has_payload; 4280 events->exception_payload = vcpu->arch.exception.payload; 4281 4282 events->interrupt.injected = 4283 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 4284 events->interrupt.nr = vcpu->arch.interrupt.nr; 4285 events->interrupt.soft = 0; 4286 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 4287 4288 events->nmi.injected = vcpu->arch.nmi_injected; 4289 events->nmi.pending = vcpu->arch.nmi_pending != 0; 4290 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); 4291 events->nmi.pad = 0; 4292 4293 events->sipi_vector = 0; /* never valid when reporting to user space */ 4294 4295 events->smi.smm = is_smm(vcpu); 4296 events->smi.pending = vcpu->arch.smi_pending; 4297 events->smi.smm_inside_nmi = 4298 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 4299 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 4300 4301 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 4302 | KVM_VCPUEVENT_VALID_SHADOW 4303 | KVM_VCPUEVENT_VALID_SMM); 4304 if (vcpu->kvm->arch.exception_payload_enabled) 4305 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 4306 4307 memset(&events->reserved, 0, sizeof(events->reserved)); 4308 } 4309 4310 static void kvm_smm_changed(struct kvm_vcpu *vcpu); 4311 4312 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 4313 struct kvm_vcpu_events *events) 4314 { 4315 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 4316 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 4317 | KVM_VCPUEVENT_VALID_SHADOW 4318 | KVM_VCPUEVENT_VALID_SMM 4319 | KVM_VCPUEVENT_VALID_PAYLOAD)) 4320 return -EINVAL; 4321 4322 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 4323 if (!vcpu->kvm->arch.exception_payload_enabled) 4324 return -EINVAL; 4325 if (events->exception.pending) 4326 events->exception.injected = 0; 4327 else 4328 events->exception_has_payload = 0; 4329 } else { 4330 events->exception.pending = 0; 4331 events->exception_has_payload = 0; 4332 } 4333 4334 if ((events->exception.injected || events->exception.pending) && 4335 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 4336 return -EINVAL; 4337 4338 /* INITs are latched while in SMM */ 4339 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 4340 (events->smi.smm || events->smi.pending) && 4341 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 4342 return -EINVAL; 4343 4344 process_nmi(vcpu); 4345 vcpu->arch.exception.injected = events->exception.injected; 4346 vcpu->arch.exception.pending = events->exception.pending; 4347 vcpu->arch.exception.nr = events->exception.nr; 4348 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 4349 vcpu->arch.exception.error_code = events->exception.error_code; 4350 vcpu->arch.exception.has_payload = events->exception_has_payload; 4351 vcpu->arch.exception.payload = events->exception_payload; 4352 4353 vcpu->arch.interrupt.injected = events->interrupt.injected; 4354 vcpu->arch.interrupt.nr = events->interrupt.nr; 4355 vcpu->arch.interrupt.soft = events->interrupt.soft; 4356 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 4357 static_call(kvm_x86_set_interrupt_shadow)(vcpu, 4358 events->interrupt.shadow); 4359 4360 vcpu->arch.nmi_injected = events->nmi.injected; 4361 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 4362 vcpu->arch.nmi_pending = events->nmi.pending; 4363 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); 4364 4365 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 4366 lapic_in_kernel(vcpu)) 4367 vcpu->arch.apic->sipi_vector = events->sipi_vector; 4368 4369 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 4370 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { 4371 if (events->smi.smm) 4372 vcpu->arch.hflags |= HF_SMM_MASK; 4373 else 4374 vcpu->arch.hflags &= ~HF_SMM_MASK; 4375 kvm_smm_changed(vcpu); 4376 } 4377 4378 vcpu->arch.smi_pending = events->smi.pending; 4379 4380 if (events->smi.smm) { 4381 if (events->smi.smm_inside_nmi) 4382 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 4383 else 4384 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 4385 } 4386 4387 if (lapic_in_kernel(vcpu)) { 4388 if (events->smi.latched_init) 4389 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4390 else 4391 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 4392 } 4393 } 4394 4395 kvm_make_request(KVM_REQ_EVENT, vcpu); 4396 4397 return 0; 4398 } 4399 4400 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 4401 struct kvm_debugregs *dbgregs) 4402 { 4403 unsigned long val; 4404 4405 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 4406 kvm_get_dr(vcpu, 6, &val); 4407 dbgregs->dr6 = val; 4408 dbgregs->dr7 = vcpu->arch.dr7; 4409 dbgregs->flags = 0; 4410 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 4411 } 4412 4413 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 4414 struct kvm_debugregs *dbgregs) 4415 { 4416 if (dbgregs->flags) 4417 return -EINVAL; 4418 4419 if (!kvm_dr6_valid(dbgregs->dr6)) 4420 return -EINVAL; 4421 if (!kvm_dr7_valid(dbgregs->dr7)) 4422 return -EINVAL; 4423 4424 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 4425 kvm_update_dr0123(vcpu); 4426 vcpu->arch.dr6 = dbgregs->dr6; 4427 vcpu->arch.dr7 = dbgregs->dr7; 4428 kvm_update_dr7(vcpu); 4429 4430 return 0; 4431 } 4432 4433 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 4434 4435 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 4436 { 4437 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 4438 u64 xstate_bv = xsave->header.xfeatures; 4439 u64 valid; 4440 4441 /* 4442 * Copy legacy XSAVE area, to avoid complications with CPUID 4443 * leaves 0 and 1 in the loop below. 4444 */ 4445 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 4446 4447 /* Set XSTATE_BV */ 4448 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; 4449 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 4450 4451 /* 4452 * Copy each region from the possibly compacted offset to the 4453 * non-compacted offset. 4454 */ 4455 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 4456 while (valid) { 4457 u64 xfeature_mask = valid & -valid; 4458 int xfeature_nr = fls64(xfeature_mask) - 1; 4459 void *src = get_xsave_addr(xsave, xfeature_nr); 4460 4461 if (src) { 4462 u32 size, offset, ecx, edx; 4463 cpuid_count(XSTATE_CPUID, xfeature_nr, 4464 &size, &offset, &ecx, &edx); 4465 if (xfeature_nr == XFEATURE_PKRU) 4466 memcpy(dest + offset, &vcpu->arch.pkru, 4467 sizeof(vcpu->arch.pkru)); 4468 else 4469 memcpy(dest + offset, src, size); 4470 4471 } 4472 4473 valid -= xfeature_mask; 4474 } 4475 } 4476 4477 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 4478 { 4479 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave; 4480 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 4481 u64 valid; 4482 4483 /* 4484 * Copy legacy XSAVE area, to avoid complications with CPUID 4485 * leaves 0 and 1 in the loop below. 4486 */ 4487 memcpy(xsave, src, XSAVE_HDR_OFFSET); 4488 4489 /* Set XSTATE_BV and possibly XCOMP_BV. */ 4490 xsave->header.xfeatures = xstate_bv; 4491 if (boot_cpu_has(X86_FEATURE_XSAVES)) 4492 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 4493 4494 /* 4495 * Copy each region from the non-compacted offset to the 4496 * possibly compacted offset. 4497 */ 4498 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 4499 while (valid) { 4500 u64 xfeature_mask = valid & -valid; 4501 int xfeature_nr = fls64(xfeature_mask) - 1; 4502 void *dest = get_xsave_addr(xsave, xfeature_nr); 4503 4504 if (dest) { 4505 u32 size, offset, ecx, edx; 4506 cpuid_count(XSTATE_CPUID, xfeature_nr, 4507 &size, &offset, &ecx, &edx); 4508 if (xfeature_nr == XFEATURE_PKRU) 4509 memcpy(&vcpu->arch.pkru, src + offset, 4510 sizeof(vcpu->arch.pkru)); 4511 else 4512 memcpy(dest, src + offset, size); 4513 } 4514 4515 valid -= xfeature_mask; 4516 } 4517 } 4518 4519 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 4520 struct kvm_xsave *guest_xsave) 4521 { 4522 if (!vcpu->arch.guest_fpu) 4523 return; 4524 4525 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 4526 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 4527 fill_xsave((u8 *) guest_xsave->region, vcpu); 4528 } else { 4529 memcpy(guest_xsave->region, 4530 &vcpu->arch.guest_fpu->state.fxsave, 4531 sizeof(struct fxregs_state)); 4532 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 4533 XFEATURE_MASK_FPSSE; 4534 } 4535 } 4536 4537 #define XSAVE_MXCSR_OFFSET 24 4538 4539 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 4540 struct kvm_xsave *guest_xsave) 4541 { 4542 u64 xstate_bv; 4543 u32 mxcsr; 4544 4545 if (!vcpu->arch.guest_fpu) 4546 return 0; 4547 4548 xstate_bv = *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 4549 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; 4550 4551 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 4552 /* 4553 * Here we allow setting states that are not present in 4554 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 4555 * with old userspace. 4556 */ 4557 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask) 4558 return -EINVAL; 4559 load_xsave(vcpu, (u8 *)guest_xsave->region); 4560 } else { 4561 if (xstate_bv & ~XFEATURE_MASK_FPSSE || 4562 mxcsr & ~mxcsr_feature_mask) 4563 return -EINVAL; 4564 memcpy(&vcpu->arch.guest_fpu->state.fxsave, 4565 guest_xsave->region, sizeof(struct fxregs_state)); 4566 } 4567 return 0; 4568 } 4569 4570 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 4571 struct kvm_xcrs *guest_xcrs) 4572 { 4573 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 4574 guest_xcrs->nr_xcrs = 0; 4575 return; 4576 } 4577 4578 guest_xcrs->nr_xcrs = 1; 4579 guest_xcrs->flags = 0; 4580 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 4581 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 4582 } 4583 4584 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 4585 struct kvm_xcrs *guest_xcrs) 4586 { 4587 int i, r = 0; 4588 4589 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 4590 return -EINVAL; 4591 4592 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 4593 return -EINVAL; 4594 4595 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 4596 /* Only support XCR0 currently */ 4597 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 4598 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 4599 guest_xcrs->xcrs[i].value); 4600 break; 4601 } 4602 if (r) 4603 r = -EINVAL; 4604 return r; 4605 } 4606 4607 /* 4608 * kvm_set_guest_paused() indicates to the guest kernel that it has been 4609 * stopped by the hypervisor. This function will be called from the host only. 4610 * EINVAL is returned when the host attempts to set the flag for a guest that 4611 * does not support pv clocks. 4612 */ 4613 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 4614 { 4615 if (!vcpu->arch.pv_time_enabled) 4616 return -EINVAL; 4617 vcpu->arch.pvclock_set_guest_stopped_request = true; 4618 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4619 return 0; 4620 } 4621 4622 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 4623 struct kvm_enable_cap *cap) 4624 { 4625 int r; 4626 uint16_t vmcs_version; 4627 void __user *user_ptr; 4628 4629 if (cap->flags) 4630 return -EINVAL; 4631 4632 switch (cap->cap) { 4633 case KVM_CAP_HYPERV_SYNIC2: 4634 if (cap->args[0]) 4635 return -EINVAL; 4636 fallthrough; 4637 4638 case KVM_CAP_HYPERV_SYNIC: 4639 if (!irqchip_in_kernel(vcpu->kvm)) 4640 return -EINVAL; 4641 return kvm_hv_activate_synic(vcpu, cap->cap == 4642 KVM_CAP_HYPERV_SYNIC2); 4643 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4644 if (!kvm_x86_ops.nested_ops->enable_evmcs) 4645 return -ENOTTY; 4646 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); 4647 if (!r) { 4648 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 4649 if (copy_to_user(user_ptr, &vmcs_version, 4650 sizeof(vmcs_version))) 4651 r = -EFAULT; 4652 } 4653 return r; 4654 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4655 if (!kvm_x86_ops.enable_direct_tlbflush) 4656 return -ENOTTY; 4657 4658 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); 4659 4660 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 4661 vcpu->arch.pv_cpuid.enforce = cap->args[0]; 4662 if (vcpu->arch.pv_cpuid.enforce) 4663 kvm_update_pv_runtime(vcpu); 4664 4665 return 0; 4666 4667 default: 4668 return -EINVAL; 4669 } 4670 } 4671 4672 long kvm_arch_vcpu_ioctl(struct file *filp, 4673 unsigned int ioctl, unsigned long arg) 4674 { 4675 struct kvm_vcpu *vcpu = filp->private_data; 4676 void __user *argp = (void __user *)arg; 4677 int r; 4678 union { 4679 struct kvm_lapic_state *lapic; 4680 struct kvm_xsave *xsave; 4681 struct kvm_xcrs *xcrs; 4682 void *buffer; 4683 } u; 4684 4685 vcpu_load(vcpu); 4686 4687 u.buffer = NULL; 4688 switch (ioctl) { 4689 case KVM_GET_LAPIC: { 4690 r = -EINVAL; 4691 if (!lapic_in_kernel(vcpu)) 4692 goto out; 4693 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 4694 GFP_KERNEL_ACCOUNT); 4695 4696 r = -ENOMEM; 4697 if (!u.lapic) 4698 goto out; 4699 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 4700 if (r) 4701 goto out; 4702 r = -EFAULT; 4703 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 4704 goto out; 4705 r = 0; 4706 break; 4707 } 4708 case KVM_SET_LAPIC: { 4709 r = -EINVAL; 4710 if (!lapic_in_kernel(vcpu)) 4711 goto out; 4712 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 4713 if (IS_ERR(u.lapic)) { 4714 r = PTR_ERR(u.lapic); 4715 goto out_nofree; 4716 } 4717 4718 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 4719 break; 4720 } 4721 case KVM_INTERRUPT: { 4722 struct kvm_interrupt irq; 4723 4724 r = -EFAULT; 4725 if (copy_from_user(&irq, argp, sizeof(irq))) 4726 goto out; 4727 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 4728 break; 4729 } 4730 case KVM_NMI: { 4731 r = kvm_vcpu_ioctl_nmi(vcpu); 4732 break; 4733 } 4734 case KVM_SMI: { 4735 r = kvm_vcpu_ioctl_smi(vcpu); 4736 break; 4737 } 4738 case KVM_SET_CPUID: { 4739 struct kvm_cpuid __user *cpuid_arg = argp; 4740 struct kvm_cpuid cpuid; 4741 4742 r = -EFAULT; 4743 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4744 goto out; 4745 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 4746 break; 4747 } 4748 case KVM_SET_CPUID2: { 4749 struct kvm_cpuid2 __user *cpuid_arg = argp; 4750 struct kvm_cpuid2 cpuid; 4751 4752 r = -EFAULT; 4753 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4754 goto out; 4755 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 4756 cpuid_arg->entries); 4757 break; 4758 } 4759 case KVM_GET_CPUID2: { 4760 struct kvm_cpuid2 __user *cpuid_arg = argp; 4761 struct kvm_cpuid2 cpuid; 4762 4763 r = -EFAULT; 4764 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4765 goto out; 4766 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 4767 cpuid_arg->entries); 4768 if (r) 4769 goto out; 4770 r = -EFAULT; 4771 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4772 goto out; 4773 r = 0; 4774 break; 4775 } 4776 case KVM_GET_MSRS: { 4777 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4778 r = msr_io(vcpu, argp, do_get_msr, 1); 4779 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4780 break; 4781 } 4782 case KVM_SET_MSRS: { 4783 int idx = srcu_read_lock(&vcpu->kvm->srcu); 4784 r = msr_io(vcpu, argp, do_set_msr, 0); 4785 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4786 break; 4787 } 4788 case KVM_TPR_ACCESS_REPORTING: { 4789 struct kvm_tpr_access_ctl tac; 4790 4791 r = -EFAULT; 4792 if (copy_from_user(&tac, argp, sizeof(tac))) 4793 goto out; 4794 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 4795 if (r) 4796 goto out; 4797 r = -EFAULT; 4798 if (copy_to_user(argp, &tac, sizeof(tac))) 4799 goto out; 4800 r = 0; 4801 break; 4802 }; 4803 case KVM_SET_VAPIC_ADDR: { 4804 struct kvm_vapic_addr va; 4805 int idx; 4806 4807 r = -EINVAL; 4808 if (!lapic_in_kernel(vcpu)) 4809 goto out; 4810 r = -EFAULT; 4811 if (copy_from_user(&va, argp, sizeof(va))) 4812 goto out; 4813 idx = srcu_read_lock(&vcpu->kvm->srcu); 4814 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 4815 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4816 break; 4817 } 4818 case KVM_X86_SETUP_MCE: { 4819 u64 mcg_cap; 4820 4821 r = -EFAULT; 4822 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 4823 goto out; 4824 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 4825 break; 4826 } 4827 case KVM_X86_SET_MCE: { 4828 struct kvm_x86_mce mce; 4829 4830 r = -EFAULT; 4831 if (copy_from_user(&mce, argp, sizeof(mce))) 4832 goto out; 4833 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 4834 break; 4835 } 4836 case KVM_GET_VCPU_EVENTS: { 4837 struct kvm_vcpu_events events; 4838 4839 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 4840 4841 r = -EFAULT; 4842 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 4843 break; 4844 r = 0; 4845 break; 4846 } 4847 case KVM_SET_VCPU_EVENTS: { 4848 struct kvm_vcpu_events events; 4849 4850 r = -EFAULT; 4851 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 4852 break; 4853 4854 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 4855 break; 4856 } 4857 case KVM_GET_DEBUGREGS: { 4858 struct kvm_debugregs dbgregs; 4859 4860 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 4861 4862 r = -EFAULT; 4863 if (copy_to_user(argp, &dbgregs, 4864 sizeof(struct kvm_debugregs))) 4865 break; 4866 r = 0; 4867 break; 4868 } 4869 case KVM_SET_DEBUGREGS: { 4870 struct kvm_debugregs dbgregs; 4871 4872 r = -EFAULT; 4873 if (copy_from_user(&dbgregs, argp, 4874 sizeof(struct kvm_debugregs))) 4875 break; 4876 4877 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 4878 break; 4879 } 4880 case KVM_GET_XSAVE: { 4881 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 4882 r = -ENOMEM; 4883 if (!u.xsave) 4884 break; 4885 4886 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 4887 4888 r = -EFAULT; 4889 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 4890 break; 4891 r = 0; 4892 break; 4893 } 4894 case KVM_SET_XSAVE: { 4895 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 4896 if (IS_ERR(u.xsave)) { 4897 r = PTR_ERR(u.xsave); 4898 goto out_nofree; 4899 } 4900 4901 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 4902 break; 4903 } 4904 case KVM_GET_XCRS: { 4905 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 4906 r = -ENOMEM; 4907 if (!u.xcrs) 4908 break; 4909 4910 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 4911 4912 r = -EFAULT; 4913 if (copy_to_user(argp, u.xcrs, 4914 sizeof(struct kvm_xcrs))) 4915 break; 4916 r = 0; 4917 break; 4918 } 4919 case KVM_SET_XCRS: { 4920 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 4921 if (IS_ERR(u.xcrs)) { 4922 r = PTR_ERR(u.xcrs); 4923 goto out_nofree; 4924 } 4925 4926 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 4927 break; 4928 } 4929 case KVM_SET_TSC_KHZ: { 4930 u32 user_tsc_khz; 4931 4932 r = -EINVAL; 4933 user_tsc_khz = (u32)arg; 4934 4935 if (kvm_has_tsc_control && 4936 user_tsc_khz >= kvm_max_guest_tsc_khz) 4937 goto out; 4938 4939 if (user_tsc_khz == 0) 4940 user_tsc_khz = tsc_khz; 4941 4942 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 4943 r = 0; 4944 4945 goto out; 4946 } 4947 case KVM_GET_TSC_KHZ: { 4948 r = vcpu->arch.virtual_tsc_khz; 4949 goto out; 4950 } 4951 case KVM_KVMCLOCK_CTRL: { 4952 r = kvm_set_guest_paused(vcpu); 4953 goto out; 4954 } 4955 case KVM_ENABLE_CAP: { 4956 struct kvm_enable_cap cap; 4957 4958 r = -EFAULT; 4959 if (copy_from_user(&cap, argp, sizeof(cap))) 4960 goto out; 4961 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 4962 break; 4963 } 4964 case KVM_GET_NESTED_STATE: { 4965 struct kvm_nested_state __user *user_kvm_nested_state = argp; 4966 u32 user_data_size; 4967 4968 r = -EINVAL; 4969 if (!kvm_x86_ops.nested_ops->get_state) 4970 break; 4971 4972 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 4973 r = -EFAULT; 4974 if (get_user(user_data_size, &user_kvm_nested_state->size)) 4975 break; 4976 4977 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, 4978 user_data_size); 4979 if (r < 0) 4980 break; 4981 4982 if (r > user_data_size) { 4983 if (put_user(r, &user_kvm_nested_state->size)) 4984 r = -EFAULT; 4985 else 4986 r = -E2BIG; 4987 break; 4988 } 4989 4990 r = 0; 4991 break; 4992 } 4993 case KVM_SET_NESTED_STATE: { 4994 struct kvm_nested_state __user *user_kvm_nested_state = argp; 4995 struct kvm_nested_state kvm_state; 4996 int idx; 4997 4998 r = -EINVAL; 4999 if (!kvm_x86_ops.nested_ops->set_state) 5000 break; 5001 5002 r = -EFAULT; 5003 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 5004 break; 5005 5006 r = -EINVAL; 5007 if (kvm_state.size < sizeof(kvm_state)) 5008 break; 5009 5010 if (kvm_state.flags & 5011 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 5012 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING 5013 | KVM_STATE_NESTED_GIF_SET)) 5014 break; 5015 5016 /* nested_run_pending implies guest_mode. */ 5017 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 5018 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 5019 break; 5020 5021 idx = srcu_read_lock(&vcpu->kvm->srcu); 5022 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); 5023 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5024 break; 5025 } 5026 case KVM_GET_SUPPORTED_HV_CPUID: 5027 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); 5028 break; 5029 #ifdef CONFIG_KVM_XEN 5030 case KVM_XEN_VCPU_GET_ATTR: { 5031 struct kvm_xen_vcpu_attr xva; 5032 5033 r = -EFAULT; 5034 if (copy_from_user(&xva, argp, sizeof(xva))) 5035 goto out; 5036 r = kvm_xen_vcpu_get_attr(vcpu, &xva); 5037 if (!r && copy_to_user(argp, &xva, sizeof(xva))) 5038 r = -EFAULT; 5039 break; 5040 } 5041 case KVM_XEN_VCPU_SET_ATTR: { 5042 struct kvm_xen_vcpu_attr xva; 5043 5044 r = -EFAULT; 5045 if (copy_from_user(&xva, argp, sizeof(xva))) 5046 goto out; 5047 r = kvm_xen_vcpu_set_attr(vcpu, &xva); 5048 break; 5049 } 5050 #endif 5051 default: 5052 r = -EINVAL; 5053 } 5054 out: 5055 kfree(u.buffer); 5056 out_nofree: 5057 vcpu_put(vcpu); 5058 return r; 5059 } 5060 5061 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 5062 { 5063 return VM_FAULT_SIGBUS; 5064 } 5065 5066 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 5067 { 5068 int ret; 5069 5070 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 5071 return -EINVAL; 5072 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); 5073 return ret; 5074 } 5075 5076 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 5077 u64 ident_addr) 5078 { 5079 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); 5080 } 5081 5082 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 5083 unsigned long kvm_nr_mmu_pages) 5084 { 5085 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 5086 return -EINVAL; 5087 5088 mutex_lock(&kvm->slots_lock); 5089 5090 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 5091 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 5092 5093 mutex_unlock(&kvm->slots_lock); 5094 return 0; 5095 } 5096 5097 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 5098 { 5099 return kvm->arch.n_max_mmu_pages; 5100 } 5101 5102 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5103 { 5104 struct kvm_pic *pic = kvm->arch.vpic; 5105 int r; 5106 5107 r = 0; 5108 switch (chip->chip_id) { 5109 case KVM_IRQCHIP_PIC_MASTER: 5110 memcpy(&chip->chip.pic, &pic->pics[0], 5111 sizeof(struct kvm_pic_state)); 5112 break; 5113 case KVM_IRQCHIP_PIC_SLAVE: 5114 memcpy(&chip->chip.pic, &pic->pics[1], 5115 sizeof(struct kvm_pic_state)); 5116 break; 5117 case KVM_IRQCHIP_IOAPIC: 5118 kvm_get_ioapic(kvm, &chip->chip.ioapic); 5119 break; 5120 default: 5121 r = -EINVAL; 5122 break; 5123 } 5124 return r; 5125 } 5126 5127 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 5128 { 5129 struct kvm_pic *pic = kvm->arch.vpic; 5130 int r; 5131 5132 r = 0; 5133 switch (chip->chip_id) { 5134 case KVM_IRQCHIP_PIC_MASTER: 5135 spin_lock(&pic->lock); 5136 memcpy(&pic->pics[0], &chip->chip.pic, 5137 sizeof(struct kvm_pic_state)); 5138 spin_unlock(&pic->lock); 5139 break; 5140 case KVM_IRQCHIP_PIC_SLAVE: 5141 spin_lock(&pic->lock); 5142 memcpy(&pic->pics[1], &chip->chip.pic, 5143 sizeof(struct kvm_pic_state)); 5144 spin_unlock(&pic->lock); 5145 break; 5146 case KVM_IRQCHIP_IOAPIC: 5147 kvm_set_ioapic(kvm, &chip->chip.ioapic); 5148 break; 5149 default: 5150 r = -EINVAL; 5151 break; 5152 } 5153 kvm_pic_update_irq(pic); 5154 return r; 5155 } 5156 5157 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5158 { 5159 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 5160 5161 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 5162 5163 mutex_lock(&kps->lock); 5164 memcpy(ps, &kps->channels, sizeof(*ps)); 5165 mutex_unlock(&kps->lock); 5166 return 0; 5167 } 5168 5169 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 5170 { 5171 int i; 5172 struct kvm_pit *pit = kvm->arch.vpit; 5173 5174 mutex_lock(&pit->pit_state.lock); 5175 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 5176 for (i = 0; i < 3; i++) 5177 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 5178 mutex_unlock(&pit->pit_state.lock); 5179 return 0; 5180 } 5181 5182 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5183 { 5184 mutex_lock(&kvm->arch.vpit->pit_state.lock); 5185 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 5186 sizeof(ps->channels)); 5187 ps->flags = kvm->arch.vpit->pit_state.flags; 5188 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 5189 memset(&ps->reserved, 0, sizeof(ps->reserved)); 5190 return 0; 5191 } 5192 5193 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 5194 { 5195 int start = 0; 5196 int i; 5197 u32 prev_legacy, cur_legacy; 5198 struct kvm_pit *pit = kvm->arch.vpit; 5199 5200 mutex_lock(&pit->pit_state.lock); 5201 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 5202 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 5203 if (!prev_legacy && cur_legacy) 5204 start = 1; 5205 memcpy(&pit->pit_state.channels, &ps->channels, 5206 sizeof(pit->pit_state.channels)); 5207 pit->pit_state.flags = ps->flags; 5208 for (i = 0; i < 3; i++) 5209 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 5210 start && i == 0); 5211 mutex_unlock(&pit->pit_state.lock); 5212 return 0; 5213 } 5214 5215 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 5216 struct kvm_reinject_control *control) 5217 { 5218 struct kvm_pit *pit = kvm->arch.vpit; 5219 5220 /* pit->pit_state.lock was overloaded to prevent userspace from getting 5221 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 5222 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 5223 */ 5224 mutex_lock(&pit->pit_state.lock); 5225 kvm_pit_set_reinject(pit, control->pit_reinject); 5226 mutex_unlock(&pit->pit_state.lock); 5227 5228 return 0; 5229 } 5230 5231 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 5232 { 5233 5234 /* 5235 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called 5236 * before reporting dirty_bitmap to userspace. KVM flushes the buffers 5237 * on all VM-Exits, thus we only need to kick running vCPUs to force a 5238 * VM-Exit. 5239 */ 5240 struct kvm_vcpu *vcpu; 5241 int i; 5242 5243 kvm_for_each_vcpu(i, vcpu, kvm) 5244 kvm_vcpu_kick(vcpu); 5245 } 5246 5247 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 5248 bool line_status) 5249 { 5250 if (!irqchip_in_kernel(kvm)) 5251 return -ENXIO; 5252 5253 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 5254 irq_event->irq, irq_event->level, 5255 line_status); 5256 return 0; 5257 } 5258 5259 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 5260 struct kvm_enable_cap *cap) 5261 { 5262 int r; 5263 5264 if (cap->flags) 5265 return -EINVAL; 5266 5267 switch (cap->cap) { 5268 case KVM_CAP_DISABLE_QUIRKS: 5269 kvm->arch.disabled_quirks = cap->args[0]; 5270 r = 0; 5271 break; 5272 case KVM_CAP_SPLIT_IRQCHIP: { 5273 mutex_lock(&kvm->lock); 5274 r = -EINVAL; 5275 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 5276 goto split_irqchip_unlock; 5277 r = -EEXIST; 5278 if (irqchip_in_kernel(kvm)) 5279 goto split_irqchip_unlock; 5280 if (kvm->created_vcpus) 5281 goto split_irqchip_unlock; 5282 r = kvm_setup_empty_irq_routing(kvm); 5283 if (r) 5284 goto split_irqchip_unlock; 5285 /* Pairs with irqchip_in_kernel. */ 5286 smp_wmb(); 5287 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 5288 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 5289 r = 0; 5290 split_irqchip_unlock: 5291 mutex_unlock(&kvm->lock); 5292 break; 5293 } 5294 case KVM_CAP_X2APIC_API: 5295 r = -EINVAL; 5296 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 5297 break; 5298 5299 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 5300 kvm->arch.x2apic_format = true; 5301 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 5302 kvm->arch.x2apic_broadcast_quirk_disabled = true; 5303 5304 r = 0; 5305 break; 5306 case KVM_CAP_X86_DISABLE_EXITS: 5307 r = -EINVAL; 5308 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 5309 break; 5310 5311 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 5312 kvm_can_mwait_in_guest()) 5313 kvm->arch.mwait_in_guest = true; 5314 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 5315 kvm->arch.hlt_in_guest = true; 5316 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 5317 kvm->arch.pause_in_guest = true; 5318 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) 5319 kvm->arch.cstate_in_guest = true; 5320 r = 0; 5321 break; 5322 case KVM_CAP_MSR_PLATFORM_INFO: 5323 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 5324 r = 0; 5325 break; 5326 case KVM_CAP_EXCEPTION_PAYLOAD: 5327 kvm->arch.exception_payload_enabled = cap->args[0]; 5328 r = 0; 5329 break; 5330 case KVM_CAP_X86_USER_SPACE_MSR: 5331 kvm->arch.user_space_msr_mask = cap->args[0]; 5332 r = 0; 5333 break; 5334 case KVM_CAP_X86_BUS_LOCK_EXIT: 5335 r = -EINVAL; 5336 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) 5337 break; 5338 5339 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && 5340 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) 5341 break; 5342 5343 if (kvm_has_bus_lock_exit && 5344 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) 5345 kvm->arch.bus_lock_detection_enabled = true; 5346 r = 0; 5347 break; 5348 default: 5349 r = -EINVAL; 5350 break; 5351 } 5352 return r; 5353 } 5354 5355 static void kvm_clear_msr_filter(struct kvm *kvm) 5356 { 5357 u32 i; 5358 u32 count = kvm->arch.msr_filter.count; 5359 struct msr_bitmap_range ranges[16]; 5360 5361 mutex_lock(&kvm->lock); 5362 kvm->arch.msr_filter.count = 0; 5363 memcpy(ranges, kvm->arch.msr_filter.ranges, count * sizeof(ranges[0])); 5364 mutex_unlock(&kvm->lock); 5365 synchronize_srcu(&kvm->srcu); 5366 5367 for (i = 0; i < count; i++) 5368 kfree(ranges[i].bitmap); 5369 } 5370 5371 static int kvm_add_msr_filter(struct kvm *kvm, struct kvm_msr_filter_range *user_range) 5372 { 5373 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges; 5374 struct msr_bitmap_range range; 5375 unsigned long *bitmap = NULL; 5376 size_t bitmap_size; 5377 int r; 5378 5379 if (!user_range->nmsrs) 5380 return 0; 5381 5382 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); 5383 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) 5384 return -EINVAL; 5385 5386 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); 5387 if (IS_ERR(bitmap)) 5388 return PTR_ERR(bitmap); 5389 5390 range = (struct msr_bitmap_range) { 5391 .flags = user_range->flags, 5392 .base = user_range->base, 5393 .nmsrs = user_range->nmsrs, 5394 .bitmap = bitmap, 5395 }; 5396 5397 if (range.flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) { 5398 r = -EINVAL; 5399 goto err; 5400 } 5401 5402 if (!range.flags) { 5403 r = -EINVAL; 5404 goto err; 5405 } 5406 5407 /* Everything ok, add this range identifier to our global pool */ 5408 ranges[kvm->arch.msr_filter.count] = range; 5409 /* Make sure we filled the array before we tell anyone to walk it */ 5410 smp_wmb(); 5411 kvm->arch.msr_filter.count++; 5412 5413 return 0; 5414 err: 5415 kfree(bitmap); 5416 return r; 5417 } 5418 5419 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) 5420 { 5421 struct kvm_msr_filter __user *user_msr_filter = argp; 5422 struct kvm_msr_filter filter; 5423 bool default_allow; 5424 int r = 0; 5425 bool empty = true; 5426 u32 i; 5427 5428 if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) 5429 return -EFAULT; 5430 5431 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) 5432 empty &= !filter.ranges[i].nmsrs; 5433 5434 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); 5435 if (empty && !default_allow) 5436 return -EINVAL; 5437 5438 kvm_clear_msr_filter(kvm); 5439 5440 kvm->arch.msr_filter.default_allow = default_allow; 5441 5442 /* 5443 * Protect from concurrent calls to this function that could trigger 5444 * a TOCTOU violation on kvm->arch.msr_filter.count. 5445 */ 5446 mutex_lock(&kvm->lock); 5447 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { 5448 r = kvm_add_msr_filter(kvm, &filter.ranges[i]); 5449 if (r) 5450 break; 5451 } 5452 5453 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); 5454 mutex_unlock(&kvm->lock); 5455 5456 return r; 5457 } 5458 5459 long kvm_arch_vm_ioctl(struct file *filp, 5460 unsigned int ioctl, unsigned long arg) 5461 { 5462 struct kvm *kvm = filp->private_data; 5463 void __user *argp = (void __user *)arg; 5464 int r = -ENOTTY; 5465 /* 5466 * This union makes it completely explicit to gcc-3.x 5467 * that these two variables' stack usage should be 5468 * combined, not added together. 5469 */ 5470 union { 5471 struct kvm_pit_state ps; 5472 struct kvm_pit_state2 ps2; 5473 struct kvm_pit_config pit_config; 5474 } u; 5475 5476 switch (ioctl) { 5477 case KVM_SET_TSS_ADDR: 5478 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 5479 break; 5480 case KVM_SET_IDENTITY_MAP_ADDR: { 5481 u64 ident_addr; 5482 5483 mutex_lock(&kvm->lock); 5484 r = -EINVAL; 5485 if (kvm->created_vcpus) 5486 goto set_identity_unlock; 5487 r = -EFAULT; 5488 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 5489 goto set_identity_unlock; 5490 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 5491 set_identity_unlock: 5492 mutex_unlock(&kvm->lock); 5493 break; 5494 } 5495 case KVM_SET_NR_MMU_PAGES: 5496 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 5497 break; 5498 case KVM_GET_NR_MMU_PAGES: 5499 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 5500 break; 5501 case KVM_CREATE_IRQCHIP: { 5502 mutex_lock(&kvm->lock); 5503 5504 r = -EEXIST; 5505 if (irqchip_in_kernel(kvm)) 5506 goto create_irqchip_unlock; 5507 5508 r = -EINVAL; 5509 if (kvm->created_vcpus) 5510 goto create_irqchip_unlock; 5511 5512 r = kvm_pic_init(kvm); 5513 if (r) 5514 goto create_irqchip_unlock; 5515 5516 r = kvm_ioapic_init(kvm); 5517 if (r) { 5518 kvm_pic_destroy(kvm); 5519 goto create_irqchip_unlock; 5520 } 5521 5522 r = kvm_setup_default_irq_routing(kvm); 5523 if (r) { 5524 kvm_ioapic_destroy(kvm); 5525 kvm_pic_destroy(kvm); 5526 goto create_irqchip_unlock; 5527 } 5528 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 5529 smp_wmb(); 5530 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 5531 create_irqchip_unlock: 5532 mutex_unlock(&kvm->lock); 5533 break; 5534 } 5535 case KVM_CREATE_PIT: 5536 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 5537 goto create_pit; 5538 case KVM_CREATE_PIT2: 5539 r = -EFAULT; 5540 if (copy_from_user(&u.pit_config, argp, 5541 sizeof(struct kvm_pit_config))) 5542 goto out; 5543 create_pit: 5544 mutex_lock(&kvm->lock); 5545 r = -EEXIST; 5546 if (kvm->arch.vpit) 5547 goto create_pit_unlock; 5548 r = -ENOMEM; 5549 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 5550 if (kvm->arch.vpit) 5551 r = 0; 5552 create_pit_unlock: 5553 mutex_unlock(&kvm->lock); 5554 break; 5555 case KVM_GET_IRQCHIP: { 5556 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 5557 struct kvm_irqchip *chip; 5558 5559 chip = memdup_user(argp, sizeof(*chip)); 5560 if (IS_ERR(chip)) { 5561 r = PTR_ERR(chip); 5562 goto out; 5563 } 5564 5565 r = -ENXIO; 5566 if (!irqchip_kernel(kvm)) 5567 goto get_irqchip_out; 5568 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 5569 if (r) 5570 goto get_irqchip_out; 5571 r = -EFAULT; 5572 if (copy_to_user(argp, chip, sizeof(*chip))) 5573 goto get_irqchip_out; 5574 r = 0; 5575 get_irqchip_out: 5576 kfree(chip); 5577 break; 5578 } 5579 case KVM_SET_IRQCHIP: { 5580 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 5581 struct kvm_irqchip *chip; 5582 5583 chip = memdup_user(argp, sizeof(*chip)); 5584 if (IS_ERR(chip)) { 5585 r = PTR_ERR(chip); 5586 goto out; 5587 } 5588 5589 r = -ENXIO; 5590 if (!irqchip_kernel(kvm)) 5591 goto set_irqchip_out; 5592 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 5593 set_irqchip_out: 5594 kfree(chip); 5595 break; 5596 } 5597 case KVM_GET_PIT: { 5598 r = -EFAULT; 5599 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 5600 goto out; 5601 r = -ENXIO; 5602 if (!kvm->arch.vpit) 5603 goto out; 5604 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 5605 if (r) 5606 goto out; 5607 r = -EFAULT; 5608 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 5609 goto out; 5610 r = 0; 5611 break; 5612 } 5613 case KVM_SET_PIT: { 5614 r = -EFAULT; 5615 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 5616 goto out; 5617 mutex_lock(&kvm->lock); 5618 r = -ENXIO; 5619 if (!kvm->arch.vpit) 5620 goto set_pit_out; 5621 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 5622 set_pit_out: 5623 mutex_unlock(&kvm->lock); 5624 break; 5625 } 5626 case KVM_GET_PIT2: { 5627 r = -ENXIO; 5628 if (!kvm->arch.vpit) 5629 goto out; 5630 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 5631 if (r) 5632 goto out; 5633 r = -EFAULT; 5634 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 5635 goto out; 5636 r = 0; 5637 break; 5638 } 5639 case KVM_SET_PIT2: { 5640 r = -EFAULT; 5641 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 5642 goto out; 5643 mutex_lock(&kvm->lock); 5644 r = -ENXIO; 5645 if (!kvm->arch.vpit) 5646 goto set_pit2_out; 5647 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 5648 set_pit2_out: 5649 mutex_unlock(&kvm->lock); 5650 break; 5651 } 5652 case KVM_REINJECT_CONTROL: { 5653 struct kvm_reinject_control control; 5654 r = -EFAULT; 5655 if (copy_from_user(&control, argp, sizeof(control))) 5656 goto out; 5657 r = -ENXIO; 5658 if (!kvm->arch.vpit) 5659 goto out; 5660 r = kvm_vm_ioctl_reinject(kvm, &control); 5661 break; 5662 } 5663 case KVM_SET_BOOT_CPU_ID: 5664 r = 0; 5665 mutex_lock(&kvm->lock); 5666 if (kvm->created_vcpus) 5667 r = -EBUSY; 5668 else 5669 kvm->arch.bsp_vcpu_id = arg; 5670 mutex_unlock(&kvm->lock); 5671 break; 5672 #ifdef CONFIG_KVM_XEN 5673 case KVM_XEN_HVM_CONFIG: { 5674 struct kvm_xen_hvm_config xhc; 5675 r = -EFAULT; 5676 if (copy_from_user(&xhc, argp, sizeof(xhc))) 5677 goto out; 5678 r = kvm_xen_hvm_config(kvm, &xhc); 5679 break; 5680 } 5681 case KVM_XEN_HVM_GET_ATTR: { 5682 struct kvm_xen_hvm_attr xha; 5683 5684 r = -EFAULT; 5685 if (copy_from_user(&xha, argp, sizeof(xha))) 5686 goto out; 5687 r = kvm_xen_hvm_get_attr(kvm, &xha); 5688 if (!r && copy_to_user(argp, &xha, sizeof(xha))) 5689 r = -EFAULT; 5690 break; 5691 } 5692 case KVM_XEN_HVM_SET_ATTR: { 5693 struct kvm_xen_hvm_attr xha; 5694 5695 r = -EFAULT; 5696 if (copy_from_user(&xha, argp, sizeof(xha))) 5697 goto out; 5698 r = kvm_xen_hvm_set_attr(kvm, &xha); 5699 break; 5700 } 5701 #endif 5702 case KVM_SET_CLOCK: { 5703 struct kvm_clock_data user_ns; 5704 u64 now_ns; 5705 5706 r = -EFAULT; 5707 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 5708 goto out; 5709 5710 r = -EINVAL; 5711 if (user_ns.flags) 5712 goto out; 5713 5714 r = 0; 5715 /* 5716 * TODO: userspace has to take care of races with VCPU_RUN, so 5717 * kvm_gen_update_masterclock() can be cut down to locked 5718 * pvclock_update_vm_gtod_copy(). 5719 */ 5720 kvm_gen_update_masterclock(kvm); 5721 now_ns = get_kvmclock_ns(kvm); 5722 kvm->arch.kvmclock_offset += user_ns.clock - now_ns; 5723 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); 5724 break; 5725 } 5726 case KVM_GET_CLOCK: { 5727 struct kvm_clock_data user_ns; 5728 u64 now_ns; 5729 5730 now_ns = get_kvmclock_ns(kvm); 5731 user_ns.clock = now_ns; 5732 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 5733 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 5734 5735 r = -EFAULT; 5736 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 5737 goto out; 5738 r = 0; 5739 break; 5740 } 5741 case KVM_MEMORY_ENCRYPT_OP: { 5742 r = -ENOTTY; 5743 if (kvm_x86_ops.mem_enc_op) 5744 r = static_call(kvm_x86_mem_enc_op)(kvm, argp); 5745 break; 5746 } 5747 case KVM_MEMORY_ENCRYPT_REG_REGION: { 5748 struct kvm_enc_region region; 5749 5750 r = -EFAULT; 5751 if (copy_from_user(®ion, argp, sizeof(region))) 5752 goto out; 5753 5754 r = -ENOTTY; 5755 if (kvm_x86_ops.mem_enc_reg_region) 5756 r = static_call(kvm_x86_mem_enc_reg_region)(kvm, ®ion); 5757 break; 5758 } 5759 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 5760 struct kvm_enc_region region; 5761 5762 r = -EFAULT; 5763 if (copy_from_user(®ion, argp, sizeof(region))) 5764 goto out; 5765 5766 r = -ENOTTY; 5767 if (kvm_x86_ops.mem_enc_unreg_region) 5768 r = static_call(kvm_x86_mem_enc_unreg_region)(kvm, ®ion); 5769 break; 5770 } 5771 case KVM_HYPERV_EVENTFD: { 5772 struct kvm_hyperv_eventfd hvevfd; 5773 5774 r = -EFAULT; 5775 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 5776 goto out; 5777 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 5778 break; 5779 } 5780 case KVM_SET_PMU_EVENT_FILTER: 5781 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); 5782 break; 5783 case KVM_X86_SET_MSR_FILTER: 5784 r = kvm_vm_ioctl_set_msr_filter(kvm, argp); 5785 break; 5786 default: 5787 r = -ENOTTY; 5788 } 5789 out: 5790 return r; 5791 } 5792 5793 static void kvm_init_msr_list(void) 5794 { 5795 struct x86_pmu_capability x86_pmu; 5796 u32 dummy[2]; 5797 unsigned i; 5798 5799 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4, 5800 "Please update the fixed PMCs in msrs_to_saved_all[]"); 5801 5802 perf_get_x86_pmu_capability(&x86_pmu); 5803 5804 num_msrs_to_save = 0; 5805 num_emulated_msrs = 0; 5806 num_msr_based_features = 0; 5807 5808 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { 5809 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) 5810 continue; 5811 5812 /* 5813 * Even MSRs that are valid in the host may not be exposed 5814 * to the guests in some cases. 5815 */ 5816 switch (msrs_to_save_all[i]) { 5817 case MSR_IA32_BNDCFGS: 5818 if (!kvm_mpx_supported()) 5819 continue; 5820 break; 5821 case MSR_TSC_AUX: 5822 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) 5823 continue; 5824 break; 5825 case MSR_IA32_UMWAIT_CONTROL: 5826 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) 5827 continue; 5828 break; 5829 case MSR_IA32_RTIT_CTL: 5830 case MSR_IA32_RTIT_STATUS: 5831 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) 5832 continue; 5833 break; 5834 case MSR_IA32_RTIT_CR3_MATCH: 5835 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 5836 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 5837 continue; 5838 break; 5839 case MSR_IA32_RTIT_OUTPUT_BASE: 5840 case MSR_IA32_RTIT_OUTPUT_MASK: 5841 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 5842 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 5843 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 5844 continue; 5845 break; 5846 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 5847 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 5848 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= 5849 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) 5850 continue; 5851 break; 5852 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: 5853 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= 5854 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 5855 continue; 5856 break; 5857 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: 5858 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= 5859 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) 5860 continue; 5861 break; 5862 default: 5863 break; 5864 } 5865 5866 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; 5867 } 5868 5869 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { 5870 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) 5871 continue; 5872 5873 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; 5874 } 5875 5876 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { 5877 struct kvm_msr_entry msr; 5878 5879 msr.index = msr_based_features_all[i]; 5880 if (kvm_get_msr_feature(&msr)) 5881 continue; 5882 5883 msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; 5884 } 5885 } 5886 5887 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 5888 const void *v) 5889 { 5890 int handled = 0; 5891 int n; 5892 5893 do { 5894 n = min(len, 8); 5895 if (!(lapic_in_kernel(vcpu) && 5896 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 5897 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 5898 break; 5899 handled += n; 5900 addr += n; 5901 len -= n; 5902 v += n; 5903 } while (len); 5904 5905 return handled; 5906 } 5907 5908 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 5909 { 5910 int handled = 0; 5911 int n; 5912 5913 do { 5914 n = min(len, 8); 5915 if (!(lapic_in_kernel(vcpu) && 5916 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 5917 addr, n, v)) 5918 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 5919 break; 5920 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 5921 handled += n; 5922 addr += n; 5923 len -= n; 5924 v += n; 5925 } while (len); 5926 5927 return handled; 5928 } 5929 5930 static void kvm_set_segment(struct kvm_vcpu *vcpu, 5931 struct kvm_segment *var, int seg) 5932 { 5933 static_call(kvm_x86_set_segment)(vcpu, var, seg); 5934 } 5935 5936 void kvm_get_segment(struct kvm_vcpu *vcpu, 5937 struct kvm_segment *var, int seg) 5938 { 5939 static_call(kvm_x86_get_segment)(vcpu, var, seg); 5940 } 5941 5942 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 5943 struct x86_exception *exception) 5944 { 5945 gpa_t t_gpa; 5946 5947 BUG_ON(!mmu_is_nested(vcpu)); 5948 5949 /* NPT walks are always user-walks */ 5950 access |= PFERR_USER_MASK; 5951 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception); 5952 5953 return t_gpa; 5954 } 5955 5956 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 5957 struct x86_exception *exception) 5958 { 5959 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 5960 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5961 } 5962 5963 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 5964 struct x86_exception *exception) 5965 { 5966 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 5967 access |= PFERR_FETCH_MASK; 5968 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5969 } 5970 5971 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 5972 struct x86_exception *exception) 5973 { 5974 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 5975 access |= PFERR_WRITE_MASK; 5976 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 5977 } 5978 5979 /* uses this to access any guest's mapped memory without checking CPL */ 5980 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 5981 struct x86_exception *exception) 5982 { 5983 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 5984 } 5985 5986 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 5987 struct kvm_vcpu *vcpu, u32 access, 5988 struct x86_exception *exception) 5989 { 5990 void *data = val; 5991 int r = X86EMUL_CONTINUE; 5992 5993 while (bytes) { 5994 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 5995 exception); 5996 unsigned offset = addr & (PAGE_SIZE-1); 5997 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 5998 int ret; 5999 6000 if (gpa == UNMAPPED_GVA) 6001 return X86EMUL_PROPAGATE_FAULT; 6002 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 6003 offset, toread); 6004 if (ret < 0) { 6005 r = X86EMUL_IO_NEEDED; 6006 goto out; 6007 } 6008 6009 bytes -= toread; 6010 data += toread; 6011 addr += toread; 6012 } 6013 out: 6014 return r; 6015 } 6016 6017 /* used for instruction fetching */ 6018 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 6019 gva_t addr, void *val, unsigned int bytes, 6020 struct x86_exception *exception) 6021 { 6022 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6023 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6024 unsigned offset; 6025 int ret; 6026 6027 /* Inline kvm_read_guest_virt_helper for speed. */ 6028 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 6029 exception); 6030 if (unlikely(gpa == UNMAPPED_GVA)) 6031 return X86EMUL_PROPAGATE_FAULT; 6032 6033 offset = addr & (PAGE_SIZE-1); 6034 if (WARN_ON(offset + bytes > PAGE_SIZE)) 6035 bytes = (unsigned)PAGE_SIZE - offset; 6036 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 6037 offset, bytes); 6038 if (unlikely(ret < 0)) 6039 return X86EMUL_IO_NEEDED; 6040 6041 return X86EMUL_CONTINUE; 6042 } 6043 6044 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 6045 gva_t addr, void *val, unsigned int bytes, 6046 struct x86_exception *exception) 6047 { 6048 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 6049 6050 /* 6051 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 6052 * is returned, but our callers are not ready for that and they blindly 6053 * call kvm_inject_page_fault. Ensure that they at least do not leak 6054 * uninitialized kernel stack memory into cr2 and error code. 6055 */ 6056 memset(exception, 0, sizeof(*exception)); 6057 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 6058 exception); 6059 } 6060 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 6061 6062 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 6063 gva_t addr, void *val, unsigned int bytes, 6064 struct x86_exception *exception, bool system) 6065 { 6066 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6067 u32 access = 0; 6068 6069 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6070 access |= PFERR_USER_MASK; 6071 6072 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 6073 } 6074 6075 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 6076 unsigned long addr, void *val, unsigned int bytes) 6077 { 6078 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6079 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 6080 6081 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 6082 } 6083 6084 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 6085 struct kvm_vcpu *vcpu, u32 access, 6086 struct x86_exception *exception) 6087 { 6088 void *data = val; 6089 int r = X86EMUL_CONTINUE; 6090 6091 while (bytes) { 6092 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 6093 access, 6094 exception); 6095 unsigned offset = addr & (PAGE_SIZE-1); 6096 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 6097 int ret; 6098 6099 if (gpa == UNMAPPED_GVA) 6100 return X86EMUL_PROPAGATE_FAULT; 6101 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 6102 if (ret < 0) { 6103 r = X86EMUL_IO_NEEDED; 6104 goto out; 6105 } 6106 6107 bytes -= towrite; 6108 data += towrite; 6109 addr += towrite; 6110 } 6111 out: 6112 return r; 6113 } 6114 6115 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 6116 unsigned int bytes, struct x86_exception *exception, 6117 bool system) 6118 { 6119 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6120 u32 access = PFERR_WRITE_MASK; 6121 6122 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3) 6123 access |= PFERR_USER_MASK; 6124 6125 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6126 access, exception); 6127 } 6128 6129 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 6130 unsigned int bytes, struct x86_exception *exception) 6131 { 6132 /* kvm_write_guest_virt_system can pull in tons of pages. */ 6133 vcpu->arch.l1tf_flush_l1d = true; 6134 6135 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 6136 PFERR_WRITE_MASK, exception); 6137 } 6138 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 6139 6140 int handle_ud(struct kvm_vcpu *vcpu) 6141 { 6142 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; 6143 int emul_type = EMULTYPE_TRAP_UD; 6144 char sig[5]; /* ud2; .ascii "kvm" */ 6145 struct x86_exception e; 6146 6147 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, NULL, 0))) 6148 return 1; 6149 6150 if (force_emulation_prefix && 6151 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 6152 sig, sizeof(sig), &e) == 0 && 6153 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { 6154 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 6155 emul_type = EMULTYPE_TRAP_UD_FORCED; 6156 } 6157 6158 return kvm_emulate_instruction(vcpu, emul_type); 6159 } 6160 EXPORT_SYMBOL_GPL(handle_ud); 6161 6162 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6163 gpa_t gpa, bool write) 6164 { 6165 /* For APIC access vmexit */ 6166 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 6167 return 1; 6168 6169 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 6170 trace_vcpu_match_mmio(gva, gpa, write, true); 6171 return 1; 6172 } 6173 6174 return 0; 6175 } 6176 6177 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 6178 gpa_t *gpa, struct x86_exception *exception, 6179 bool write) 6180 { 6181 u32 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) 6182 | (write ? PFERR_WRITE_MASK : 0); 6183 6184 /* 6185 * currently PKRU is only applied to ept enabled guest so 6186 * there is no pkey in EPT page table for L1 guest or EPT 6187 * shadow page table for L2 guest. 6188 */ 6189 if (vcpu_match_mmio_gva(vcpu, gva) 6190 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 6191 vcpu->arch.mmio_access, 0, access)) { 6192 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 6193 (gva & (PAGE_SIZE - 1)); 6194 trace_vcpu_match_mmio(gva, *gpa, write, false); 6195 return 1; 6196 } 6197 6198 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 6199 6200 if (*gpa == UNMAPPED_GVA) 6201 return -1; 6202 6203 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 6204 } 6205 6206 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 6207 const void *val, int bytes) 6208 { 6209 int ret; 6210 6211 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 6212 if (ret < 0) 6213 return 0; 6214 kvm_page_track_write(vcpu, gpa, val, bytes); 6215 return 1; 6216 } 6217 6218 struct read_write_emulator_ops { 6219 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 6220 int bytes); 6221 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 6222 void *val, int bytes); 6223 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6224 int bytes, void *val); 6225 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 6226 void *val, int bytes); 6227 bool write; 6228 }; 6229 6230 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 6231 { 6232 if (vcpu->mmio_read_completed) { 6233 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 6234 vcpu->mmio_fragments[0].gpa, val); 6235 vcpu->mmio_read_completed = 0; 6236 return 1; 6237 } 6238 6239 return 0; 6240 } 6241 6242 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6243 void *val, int bytes) 6244 { 6245 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 6246 } 6247 6248 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 6249 void *val, int bytes) 6250 { 6251 return emulator_write_phys(vcpu, gpa, val, bytes); 6252 } 6253 6254 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 6255 { 6256 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 6257 return vcpu_mmio_write(vcpu, gpa, bytes, val); 6258 } 6259 6260 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6261 void *val, int bytes) 6262 { 6263 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 6264 return X86EMUL_IO_NEEDED; 6265 } 6266 6267 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 6268 void *val, int bytes) 6269 { 6270 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 6271 6272 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 6273 return X86EMUL_CONTINUE; 6274 } 6275 6276 static const struct read_write_emulator_ops read_emultor = { 6277 .read_write_prepare = read_prepare, 6278 .read_write_emulate = read_emulate, 6279 .read_write_mmio = vcpu_mmio_read, 6280 .read_write_exit_mmio = read_exit_mmio, 6281 }; 6282 6283 static const struct read_write_emulator_ops write_emultor = { 6284 .read_write_emulate = write_emulate, 6285 .read_write_mmio = write_mmio, 6286 .read_write_exit_mmio = write_exit_mmio, 6287 .write = true, 6288 }; 6289 6290 static int emulator_read_write_onepage(unsigned long addr, void *val, 6291 unsigned int bytes, 6292 struct x86_exception *exception, 6293 struct kvm_vcpu *vcpu, 6294 const struct read_write_emulator_ops *ops) 6295 { 6296 gpa_t gpa; 6297 int handled, ret; 6298 bool write = ops->write; 6299 struct kvm_mmio_fragment *frag; 6300 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 6301 6302 /* 6303 * If the exit was due to a NPF we may already have a GPA. 6304 * If the GPA is present, use it to avoid the GVA to GPA table walk. 6305 * Note, this cannot be used on string operations since string 6306 * operation using rep will only have the initial GPA from the NPF 6307 * occurred. 6308 */ 6309 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && 6310 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { 6311 gpa = ctxt->gpa_val; 6312 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 6313 } else { 6314 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 6315 if (ret < 0) 6316 return X86EMUL_PROPAGATE_FAULT; 6317 } 6318 6319 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 6320 return X86EMUL_CONTINUE; 6321 6322 /* 6323 * Is this MMIO handled locally? 6324 */ 6325 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 6326 if (handled == bytes) 6327 return X86EMUL_CONTINUE; 6328 6329 gpa += handled; 6330 bytes -= handled; 6331 val += handled; 6332 6333 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 6334 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 6335 frag->gpa = gpa; 6336 frag->data = val; 6337 frag->len = bytes; 6338 return X86EMUL_CONTINUE; 6339 } 6340 6341 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 6342 unsigned long addr, 6343 void *val, unsigned int bytes, 6344 struct x86_exception *exception, 6345 const struct read_write_emulator_ops *ops) 6346 { 6347 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6348 gpa_t gpa; 6349 int rc; 6350 6351 if (ops->read_write_prepare && 6352 ops->read_write_prepare(vcpu, val, bytes)) 6353 return X86EMUL_CONTINUE; 6354 6355 vcpu->mmio_nr_fragments = 0; 6356 6357 /* Crossing a page boundary? */ 6358 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 6359 int now; 6360 6361 now = -addr & ~PAGE_MASK; 6362 rc = emulator_read_write_onepage(addr, val, now, exception, 6363 vcpu, ops); 6364 6365 if (rc != X86EMUL_CONTINUE) 6366 return rc; 6367 addr += now; 6368 if (ctxt->mode != X86EMUL_MODE_PROT64) 6369 addr = (u32)addr; 6370 val += now; 6371 bytes -= now; 6372 } 6373 6374 rc = emulator_read_write_onepage(addr, val, bytes, exception, 6375 vcpu, ops); 6376 if (rc != X86EMUL_CONTINUE) 6377 return rc; 6378 6379 if (!vcpu->mmio_nr_fragments) 6380 return rc; 6381 6382 gpa = vcpu->mmio_fragments[0].gpa; 6383 6384 vcpu->mmio_needed = 1; 6385 vcpu->mmio_cur_fragment = 0; 6386 6387 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 6388 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 6389 vcpu->run->exit_reason = KVM_EXIT_MMIO; 6390 vcpu->run->mmio.phys_addr = gpa; 6391 6392 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 6393 } 6394 6395 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 6396 unsigned long addr, 6397 void *val, 6398 unsigned int bytes, 6399 struct x86_exception *exception) 6400 { 6401 return emulator_read_write(ctxt, addr, val, bytes, 6402 exception, &read_emultor); 6403 } 6404 6405 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 6406 unsigned long addr, 6407 const void *val, 6408 unsigned int bytes, 6409 struct x86_exception *exception) 6410 { 6411 return emulator_read_write(ctxt, addr, (void *)val, bytes, 6412 exception, &write_emultor); 6413 } 6414 6415 #define CMPXCHG_TYPE(t, ptr, old, new) \ 6416 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 6417 6418 #ifdef CONFIG_X86_64 6419 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 6420 #else 6421 # define CMPXCHG64(ptr, old, new) \ 6422 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 6423 #endif 6424 6425 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 6426 unsigned long addr, 6427 const void *old, 6428 const void *new, 6429 unsigned int bytes, 6430 struct x86_exception *exception) 6431 { 6432 struct kvm_host_map map; 6433 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6434 u64 page_line_mask; 6435 gpa_t gpa; 6436 char *kaddr; 6437 bool exchanged; 6438 6439 /* guests cmpxchg8b have to be emulated atomically */ 6440 if (bytes > 8 || (bytes & (bytes - 1))) 6441 goto emul_write; 6442 6443 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 6444 6445 if (gpa == UNMAPPED_GVA || 6446 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 6447 goto emul_write; 6448 6449 /* 6450 * Emulate the atomic as a straight write to avoid #AC if SLD is 6451 * enabled in the host and the access splits a cache line. 6452 */ 6453 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 6454 page_line_mask = ~(cache_line_size() - 1); 6455 else 6456 page_line_mask = PAGE_MASK; 6457 6458 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) 6459 goto emul_write; 6460 6461 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map)) 6462 goto emul_write; 6463 6464 kaddr = map.hva + offset_in_page(gpa); 6465 6466 switch (bytes) { 6467 case 1: 6468 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 6469 break; 6470 case 2: 6471 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 6472 break; 6473 case 4: 6474 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 6475 break; 6476 case 8: 6477 exchanged = CMPXCHG64(kaddr, old, new); 6478 break; 6479 default: 6480 BUG(); 6481 } 6482 6483 kvm_vcpu_unmap(vcpu, &map, true); 6484 6485 if (!exchanged) 6486 return X86EMUL_CMPXCHG_FAILED; 6487 6488 kvm_page_track_write(vcpu, gpa, new, bytes); 6489 6490 return X86EMUL_CONTINUE; 6491 6492 emul_write: 6493 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 6494 6495 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 6496 } 6497 6498 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 6499 { 6500 int r = 0, i; 6501 6502 for (i = 0; i < vcpu->arch.pio.count; i++) { 6503 if (vcpu->arch.pio.in) 6504 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 6505 vcpu->arch.pio.size, pd); 6506 else 6507 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 6508 vcpu->arch.pio.port, vcpu->arch.pio.size, 6509 pd); 6510 if (r) 6511 break; 6512 pd += vcpu->arch.pio.size; 6513 } 6514 return r; 6515 } 6516 6517 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 6518 unsigned short port, void *val, 6519 unsigned int count, bool in) 6520 { 6521 vcpu->arch.pio.port = port; 6522 vcpu->arch.pio.in = in; 6523 vcpu->arch.pio.count = count; 6524 vcpu->arch.pio.size = size; 6525 6526 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 6527 vcpu->arch.pio.count = 0; 6528 return 1; 6529 } 6530 6531 vcpu->run->exit_reason = KVM_EXIT_IO; 6532 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 6533 vcpu->run->io.size = size; 6534 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 6535 vcpu->run->io.count = count; 6536 vcpu->run->io.port = port; 6537 6538 return 0; 6539 } 6540 6541 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, 6542 unsigned short port, void *val, unsigned int count) 6543 { 6544 int ret; 6545 6546 if (vcpu->arch.pio.count) 6547 goto data_avail; 6548 6549 memset(vcpu->arch.pio_data, 0, size * count); 6550 6551 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 6552 if (ret) { 6553 data_avail: 6554 memcpy(val, vcpu->arch.pio_data, size * count); 6555 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 6556 vcpu->arch.pio.count = 0; 6557 return 1; 6558 } 6559 6560 return 0; 6561 } 6562 6563 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 6564 int size, unsigned short port, void *val, 6565 unsigned int count) 6566 { 6567 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count); 6568 6569 } 6570 6571 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, 6572 unsigned short port, const void *val, 6573 unsigned int count) 6574 { 6575 memcpy(vcpu->arch.pio_data, val, size * count); 6576 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 6577 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 6578 } 6579 6580 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 6581 int size, unsigned short port, 6582 const void *val, unsigned int count) 6583 { 6584 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); 6585 } 6586 6587 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 6588 { 6589 return static_call(kvm_x86_get_segment_base)(vcpu, seg); 6590 } 6591 6592 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 6593 { 6594 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 6595 } 6596 6597 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 6598 { 6599 if (!need_emulate_wbinvd(vcpu)) 6600 return X86EMUL_CONTINUE; 6601 6602 if (static_call(kvm_x86_has_wbinvd_exit)()) { 6603 int cpu = get_cpu(); 6604 6605 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 6606 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 6607 wbinvd_ipi, NULL, 1); 6608 put_cpu(); 6609 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 6610 } else 6611 wbinvd(); 6612 return X86EMUL_CONTINUE; 6613 } 6614 6615 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 6616 { 6617 kvm_emulate_wbinvd_noskip(vcpu); 6618 return kvm_skip_emulated_instruction(vcpu); 6619 } 6620 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 6621 6622 6623 6624 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 6625 { 6626 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 6627 } 6628 6629 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 6630 unsigned long *dest) 6631 { 6632 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 6633 } 6634 6635 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 6636 unsigned long value) 6637 { 6638 6639 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 6640 } 6641 6642 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 6643 { 6644 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 6645 } 6646 6647 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 6648 { 6649 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6650 unsigned long value; 6651 6652 switch (cr) { 6653 case 0: 6654 value = kvm_read_cr0(vcpu); 6655 break; 6656 case 2: 6657 value = vcpu->arch.cr2; 6658 break; 6659 case 3: 6660 value = kvm_read_cr3(vcpu); 6661 break; 6662 case 4: 6663 value = kvm_read_cr4(vcpu); 6664 break; 6665 case 8: 6666 value = kvm_get_cr8(vcpu); 6667 break; 6668 default: 6669 kvm_err("%s: unexpected cr %u\n", __func__, cr); 6670 return 0; 6671 } 6672 6673 return value; 6674 } 6675 6676 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 6677 { 6678 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6679 int res = 0; 6680 6681 switch (cr) { 6682 case 0: 6683 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 6684 break; 6685 case 2: 6686 vcpu->arch.cr2 = val; 6687 break; 6688 case 3: 6689 res = kvm_set_cr3(vcpu, val); 6690 break; 6691 case 4: 6692 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 6693 break; 6694 case 8: 6695 res = kvm_set_cr8(vcpu, val); 6696 break; 6697 default: 6698 kvm_err("%s: unexpected cr %u\n", __func__, cr); 6699 res = -1; 6700 } 6701 6702 return res; 6703 } 6704 6705 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 6706 { 6707 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); 6708 } 6709 6710 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6711 { 6712 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); 6713 } 6714 6715 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6716 { 6717 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); 6718 } 6719 6720 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6721 { 6722 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); 6723 } 6724 6725 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 6726 { 6727 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); 6728 } 6729 6730 static unsigned long emulator_get_cached_segment_base( 6731 struct x86_emulate_ctxt *ctxt, int seg) 6732 { 6733 return get_segment_base(emul_to_vcpu(ctxt), seg); 6734 } 6735 6736 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 6737 struct desc_struct *desc, u32 *base3, 6738 int seg) 6739 { 6740 struct kvm_segment var; 6741 6742 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 6743 *selector = var.selector; 6744 6745 if (var.unusable) { 6746 memset(desc, 0, sizeof(*desc)); 6747 if (base3) 6748 *base3 = 0; 6749 return false; 6750 } 6751 6752 if (var.g) 6753 var.limit >>= 12; 6754 set_desc_limit(desc, var.limit); 6755 set_desc_base(desc, (unsigned long)var.base); 6756 #ifdef CONFIG_X86_64 6757 if (base3) 6758 *base3 = var.base >> 32; 6759 #endif 6760 desc->type = var.type; 6761 desc->s = var.s; 6762 desc->dpl = var.dpl; 6763 desc->p = var.present; 6764 desc->avl = var.avl; 6765 desc->l = var.l; 6766 desc->d = var.db; 6767 desc->g = var.g; 6768 6769 return true; 6770 } 6771 6772 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 6773 struct desc_struct *desc, u32 base3, 6774 int seg) 6775 { 6776 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6777 struct kvm_segment var; 6778 6779 var.selector = selector; 6780 var.base = get_desc_base(desc); 6781 #ifdef CONFIG_X86_64 6782 var.base |= ((u64)base3) << 32; 6783 #endif 6784 var.limit = get_desc_limit(desc); 6785 if (desc->g) 6786 var.limit = (var.limit << 12) | 0xfff; 6787 var.type = desc->type; 6788 var.dpl = desc->dpl; 6789 var.db = desc->d; 6790 var.s = desc->s; 6791 var.l = desc->l; 6792 var.g = desc->g; 6793 var.avl = desc->avl; 6794 var.present = desc->p; 6795 var.unusable = !var.present; 6796 var.padding = 0; 6797 6798 kvm_set_segment(vcpu, &var, seg); 6799 return; 6800 } 6801 6802 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 6803 u32 msr_index, u64 *pdata) 6804 { 6805 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6806 int r; 6807 6808 r = kvm_get_msr(vcpu, msr_index, pdata); 6809 6810 if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) { 6811 /* Bounce to user space */ 6812 return X86EMUL_IO_NEEDED; 6813 } 6814 6815 return r; 6816 } 6817 6818 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 6819 u32 msr_index, u64 data) 6820 { 6821 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6822 int r; 6823 6824 r = kvm_set_msr(vcpu, msr_index, data); 6825 6826 if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) { 6827 /* Bounce to user space */ 6828 return X86EMUL_IO_NEEDED; 6829 } 6830 6831 return r; 6832 } 6833 6834 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 6835 { 6836 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6837 6838 return vcpu->arch.smbase; 6839 } 6840 6841 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 6842 { 6843 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6844 6845 vcpu->arch.smbase = smbase; 6846 } 6847 6848 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 6849 u32 pmc) 6850 { 6851 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc); 6852 } 6853 6854 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 6855 u32 pmc, u64 *pdata) 6856 { 6857 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 6858 } 6859 6860 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 6861 { 6862 emul_to_vcpu(ctxt)->arch.halt_request = 1; 6863 } 6864 6865 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 6866 struct x86_instruction_info *info, 6867 enum x86_intercept_stage stage) 6868 { 6869 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, 6870 &ctxt->exception); 6871 } 6872 6873 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 6874 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, 6875 bool exact_only) 6876 { 6877 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); 6878 } 6879 6880 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) 6881 { 6882 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); 6883 } 6884 6885 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) 6886 { 6887 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); 6888 } 6889 6890 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) 6891 { 6892 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); 6893 } 6894 6895 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 6896 { 6897 return kvm_register_read(emul_to_vcpu(ctxt), reg); 6898 } 6899 6900 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 6901 { 6902 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 6903 } 6904 6905 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 6906 { 6907 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); 6908 } 6909 6910 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 6911 { 6912 return emul_to_vcpu(ctxt)->arch.hflags; 6913 } 6914 6915 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) 6916 { 6917 emul_to_vcpu(ctxt)->arch.hflags = emul_flags; 6918 } 6919 6920 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, 6921 const char *smstate) 6922 { 6923 return static_call(kvm_x86_pre_leave_smm)(emul_to_vcpu(ctxt), smstate); 6924 } 6925 6926 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt) 6927 { 6928 kvm_smm_changed(emul_to_vcpu(ctxt)); 6929 } 6930 6931 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) 6932 { 6933 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); 6934 } 6935 6936 static const struct x86_emulate_ops emulate_ops = { 6937 .read_gpr = emulator_read_gpr, 6938 .write_gpr = emulator_write_gpr, 6939 .read_std = emulator_read_std, 6940 .write_std = emulator_write_std, 6941 .read_phys = kvm_read_guest_phys_system, 6942 .fetch = kvm_fetch_guest_virt, 6943 .read_emulated = emulator_read_emulated, 6944 .write_emulated = emulator_write_emulated, 6945 .cmpxchg_emulated = emulator_cmpxchg_emulated, 6946 .invlpg = emulator_invlpg, 6947 .pio_in_emulated = emulator_pio_in_emulated, 6948 .pio_out_emulated = emulator_pio_out_emulated, 6949 .get_segment = emulator_get_segment, 6950 .set_segment = emulator_set_segment, 6951 .get_cached_segment_base = emulator_get_cached_segment_base, 6952 .get_gdt = emulator_get_gdt, 6953 .get_idt = emulator_get_idt, 6954 .set_gdt = emulator_set_gdt, 6955 .set_idt = emulator_set_idt, 6956 .get_cr = emulator_get_cr, 6957 .set_cr = emulator_set_cr, 6958 .cpl = emulator_get_cpl, 6959 .get_dr = emulator_get_dr, 6960 .set_dr = emulator_set_dr, 6961 .get_smbase = emulator_get_smbase, 6962 .set_smbase = emulator_set_smbase, 6963 .set_msr = emulator_set_msr, 6964 .get_msr = emulator_get_msr, 6965 .check_pmc = emulator_check_pmc, 6966 .read_pmc = emulator_read_pmc, 6967 .halt = emulator_halt, 6968 .wbinvd = emulator_wbinvd, 6969 .fix_hypercall = emulator_fix_hypercall, 6970 .intercept = emulator_intercept, 6971 .get_cpuid = emulator_get_cpuid, 6972 .guest_has_long_mode = emulator_guest_has_long_mode, 6973 .guest_has_movbe = emulator_guest_has_movbe, 6974 .guest_has_fxsr = emulator_guest_has_fxsr, 6975 .set_nmi_mask = emulator_set_nmi_mask, 6976 .get_hflags = emulator_get_hflags, 6977 .set_hflags = emulator_set_hflags, 6978 .pre_leave_smm = emulator_pre_leave_smm, 6979 .post_leave_smm = emulator_post_leave_smm, 6980 .set_xcr = emulator_set_xcr, 6981 }; 6982 6983 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 6984 { 6985 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 6986 /* 6987 * an sti; sti; sequence only disable interrupts for the first 6988 * instruction. So, if the last instruction, be it emulated or 6989 * not, left the system with the INT_STI flag enabled, it 6990 * means that the last instruction is an sti. We should not 6991 * leave the flag on in this case. The same goes for mov ss 6992 */ 6993 if (int_shadow & mask) 6994 mask = 0; 6995 if (unlikely(int_shadow || mask)) { 6996 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); 6997 if (!mask) 6998 kvm_make_request(KVM_REQ_EVENT, vcpu); 6999 } 7000 } 7001 7002 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 7003 { 7004 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7005 if (ctxt->exception.vector == PF_VECTOR) 7006 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); 7007 7008 if (ctxt->exception.error_code_valid) 7009 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 7010 ctxt->exception.error_code); 7011 else 7012 kvm_queue_exception(vcpu, ctxt->exception.vector); 7013 return false; 7014 } 7015 7016 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) 7017 { 7018 struct x86_emulate_ctxt *ctxt; 7019 7020 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); 7021 if (!ctxt) { 7022 pr_err("kvm: failed to allocate vcpu's emulator\n"); 7023 return NULL; 7024 } 7025 7026 ctxt->vcpu = vcpu; 7027 ctxt->ops = &emulate_ops; 7028 vcpu->arch.emulate_ctxt = ctxt; 7029 7030 return ctxt; 7031 } 7032 7033 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 7034 { 7035 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7036 int cs_db, cs_l; 7037 7038 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 7039 7040 ctxt->gpa_available = false; 7041 ctxt->eflags = kvm_get_rflags(vcpu); 7042 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 7043 7044 ctxt->eip = kvm_rip_read(vcpu); 7045 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 7046 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 7047 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 7048 cs_db ? X86EMUL_MODE_PROT32 : 7049 X86EMUL_MODE_PROT16; 7050 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 7051 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 7052 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 7053 7054 init_decode_cache(ctxt); 7055 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 7056 } 7057 7058 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 7059 { 7060 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7061 int ret; 7062 7063 init_emulate_ctxt(vcpu); 7064 7065 ctxt->op_bytes = 2; 7066 ctxt->ad_bytes = 2; 7067 ctxt->_eip = ctxt->eip + inc_eip; 7068 ret = emulate_int_real(ctxt, irq); 7069 7070 if (ret != X86EMUL_CONTINUE) { 7071 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 7072 } else { 7073 ctxt->eip = ctxt->_eip; 7074 kvm_rip_write(vcpu, ctxt->eip); 7075 kvm_set_rflags(vcpu, ctxt->eflags); 7076 } 7077 } 7078 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 7079 7080 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 7081 { 7082 ++vcpu->stat.insn_emulation_fail; 7083 trace_kvm_emulate_insn_failed(vcpu); 7084 7085 if (emulation_type & EMULTYPE_VMWARE_GP) { 7086 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 7087 return 1; 7088 } 7089 7090 if (emulation_type & EMULTYPE_SKIP) { 7091 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 7092 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 7093 vcpu->run->internal.ndata = 0; 7094 return 0; 7095 } 7096 7097 kvm_queue_exception(vcpu, UD_VECTOR); 7098 7099 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { 7100 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 7101 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 7102 vcpu->run->internal.ndata = 0; 7103 return 0; 7104 } 7105 7106 return 1; 7107 } 7108 7109 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 7110 bool write_fault_to_shadow_pgtable, 7111 int emulation_type) 7112 { 7113 gpa_t gpa = cr2_or_gpa; 7114 kvm_pfn_t pfn; 7115 7116 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7117 return false; 7118 7119 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7120 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7121 return false; 7122 7123 if (!vcpu->arch.mmu->direct_map) { 7124 /* 7125 * Write permission should be allowed since only 7126 * write access need to be emulated. 7127 */ 7128 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 7129 7130 /* 7131 * If the mapping is invalid in guest, let cpu retry 7132 * it to generate fault. 7133 */ 7134 if (gpa == UNMAPPED_GVA) 7135 return true; 7136 } 7137 7138 /* 7139 * Do not retry the unhandleable instruction if it faults on the 7140 * readonly host memory, otherwise it will goto a infinite loop: 7141 * retry instruction -> write #PF -> emulation fail -> retry 7142 * instruction -> ... 7143 */ 7144 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 7145 7146 /* 7147 * If the instruction failed on the error pfn, it can not be fixed, 7148 * report the error to userspace. 7149 */ 7150 if (is_error_noslot_pfn(pfn)) 7151 return false; 7152 7153 kvm_release_pfn_clean(pfn); 7154 7155 /* The instructions are well-emulated on direct mmu. */ 7156 if (vcpu->arch.mmu->direct_map) { 7157 unsigned int indirect_shadow_pages; 7158 7159 write_lock(&vcpu->kvm->mmu_lock); 7160 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 7161 write_unlock(&vcpu->kvm->mmu_lock); 7162 7163 if (indirect_shadow_pages) 7164 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7165 7166 return true; 7167 } 7168 7169 /* 7170 * if emulation was due to access to shadowed page table 7171 * and it failed try to unshadow page and re-enter the 7172 * guest to let CPU execute the instruction. 7173 */ 7174 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7175 7176 /* 7177 * If the access faults on its page table, it can not 7178 * be fixed by unprotecting shadow page and it should 7179 * be reported to userspace. 7180 */ 7181 return !write_fault_to_shadow_pgtable; 7182 } 7183 7184 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 7185 gpa_t cr2_or_gpa, int emulation_type) 7186 { 7187 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7188 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; 7189 7190 last_retry_eip = vcpu->arch.last_retry_eip; 7191 last_retry_addr = vcpu->arch.last_retry_addr; 7192 7193 /* 7194 * If the emulation is caused by #PF and it is non-page_table 7195 * writing instruction, it means the VM-EXIT is caused by shadow 7196 * page protected, we can zap the shadow page and retry this 7197 * instruction directly. 7198 * 7199 * Note: if the guest uses a non-page-table modifying instruction 7200 * on the PDE that points to the instruction, then we will unmap 7201 * the instruction and go to an infinite loop. So, we cache the 7202 * last retried eip and the last fault address, if we meet the eip 7203 * and the address again, we can break out of the potential infinite 7204 * loop. 7205 */ 7206 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 7207 7208 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 7209 return false; 7210 7211 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 7212 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 7213 return false; 7214 7215 if (x86_page_table_writing_insn(ctxt)) 7216 return false; 7217 7218 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) 7219 return false; 7220 7221 vcpu->arch.last_retry_eip = ctxt->eip; 7222 vcpu->arch.last_retry_addr = cr2_or_gpa; 7223 7224 if (!vcpu->arch.mmu->direct_map) 7225 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 7226 7227 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 7228 7229 return true; 7230 } 7231 7232 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 7233 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 7234 7235 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 7236 { 7237 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 7238 /* This is a good place to trace that we are exiting SMM. */ 7239 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 7240 7241 /* Process a latched INIT or SMI, if any. */ 7242 kvm_make_request(KVM_REQ_EVENT, vcpu); 7243 } 7244 7245 kvm_mmu_reset_context(vcpu); 7246 } 7247 7248 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 7249 unsigned long *db) 7250 { 7251 u32 dr6 = 0; 7252 int i; 7253 u32 enable, rwlen; 7254 7255 enable = dr7; 7256 rwlen = dr7 >> 16; 7257 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 7258 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 7259 dr6 |= (1 << i); 7260 return dr6; 7261 } 7262 7263 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) 7264 { 7265 struct kvm_run *kvm_run = vcpu->run; 7266 7267 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 7268 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; 7269 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); 7270 kvm_run->debug.arch.exception = DB_VECTOR; 7271 kvm_run->exit_reason = KVM_EXIT_DEBUG; 7272 return 0; 7273 } 7274 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 7275 return 1; 7276 } 7277 7278 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 7279 { 7280 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 7281 int r; 7282 7283 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); 7284 if (unlikely(!r)) 7285 return 0; 7286 7287 /* 7288 * rflags is the old, "raw" value of the flags. The new value has 7289 * not been saved yet. 7290 * 7291 * This is correct even for TF set by the guest, because "the 7292 * processor will not generate this exception after the instruction 7293 * that sets the TF flag". 7294 */ 7295 if (unlikely(rflags & X86_EFLAGS_TF)) 7296 r = kvm_vcpu_do_singlestep(vcpu); 7297 return r; 7298 } 7299 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 7300 7301 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 7302 { 7303 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 7304 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 7305 struct kvm_run *kvm_run = vcpu->run; 7306 unsigned long eip = kvm_get_linear_rip(vcpu); 7307 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 7308 vcpu->arch.guest_debug_dr7, 7309 vcpu->arch.eff_db); 7310 7311 if (dr6 != 0) { 7312 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; 7313 kvm_run->debug.arch.pc = eip; 7314 kvm_run->debug.arch.exception = DB_VECTOR; 7315 kvm_run->exit_reason = KVM_EXIT_DEBUG; 7316 *r = 0; 7317 return true; 7318 } 7319 } 7320 7321 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 7322 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 7323 unsigned long eip = kvm_get_linear_rip(vcpu); 7324 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 7325 vcpu->arch.dr7, 7326 vcpu->arch.db); 7327 7328 if (dr6 != 0) { 7329 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); 7330 *r = 1; 7331 return true; 7332 } 7333 } 7334 7335 return false; 7336 } 7337 7338 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 7339 { 7340 switch (ctxt->opcode_len) { 7341 case 1: 7342 switch (ctxt->b) { 7343 case 0xe4: /* IN */ 7344 case 0xe5: 7345 case 0xec: 7346 case 0xed: 7347 case 0xe6: /* OUT */ 7348 case 0xe7: 7349 case 0xee: 7350 case 0xef: 7351 case 0x6c: /* INS */ 7352 case 0x6d: 7353 case 0x6e: /* OUTS */ 7354 case 0x6f: 7355 return true; 7356 } 7357 break; 7358 case 2: 7359 switch (ctxt->b) { 7360 case 0x33: /* RDPMC */ 7361 return true; 7362 } 7363 break; 7364 } 7365 7366 return false; 7367 } 7368 7369 /* 7370 * Decode to be emulated instruction. Return EMULATION_OK if success. 7371 */ 7372 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 7373 void *insn, int insn_len) 7374 { 7375 int r = EMULATION_OK; 7376 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7377 7378 init_emulate_ctxt(vcpu); 7379 7380 /* 7381 * We will reenter on the same instruction since we do not set 7382 * complete_userspace_io. This does not handle watchpoints yet, 7383 * those would be handled in the emulate_ops. 7384 */ 7385 if (!(emulation_type & EMULTYPE_SKIP) && 7386 kvm_vcpu_check_breakpoint(vcpu, &r)) 7387 return r; 7388 7389 ctxt->interruptibility = 0; 7390 ctxt->have_exception = false; 7391 ctxt->exception.vector = -1; 7392 ctxt->perm_ok = false; 7393 7394 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 7395 7396 r = x86_decode_insn(ctxt, insn, insn_len); 7397 7398 trace_kvm_emulate_insn_start(vcpu); 7399 ++vcpu->stat.insn_emulation; 7400 7401 return r; 7402 } 7403 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); 7404 7405 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 7406 int emulation_type, void *insn, int insn_len) 7407 { 7408 int r; 7409 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7410 bool writeback = true; 7411 bool write_fault_to_spt; 7412 7413 if (unlikely(!static_call(kvm_x86_can_emulate_instruction)(vcpu, insn, insn_len))) 7414 return 1; 7415 7416 vcpu->arch.l1tf_flush_l1d = true; 7417 7418 /* 7419 * Clear write_fault_to_shadow_pgtable here to ensure it is 7420 * never reused. 7421 */ 7422 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 7423 vcpu->arch.write_fault_to_shadow_pgtable = false; 7424 7425 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 7426 kvm_clear_exception_queue(vcpu); 7427 7428 r = x86_decode_emulated_instruction(vcpu, emulation_type, 7429 insn, insn_len); 7430 if (r != EMULATION_OK) { 7431 if ((emulation_type & EMULTYPE_TRAP_UD) || 7432 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { 7433 kvm_queue_exception(vcpu, UD_VECTOR); 7434 return 1; 7435 } 7436 if (reexecute_instruction(vcpu, cr2_or_gpa, 7437 write_fault_to_spt, 7438 emulation_type)) 7439 return 1; 7440 if (ctxt->have_exception) { 7441 /* 7442 * #UD should result in just EMULATION_FAILED, and trap-like 7443 * exception should not be encountered during decode. 7444 */ 7445 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || 7446 exception_type(ctxt->exception.vector) == EXCPT_TRAP); 7447 inject_emulated_exception(vcpu); 7448 return 1; 7449 } 7450 return handle_emulation_failure(vcpu, emulation_type); 7451 } 7452 } 7453 7454 if ((emulation_type & EMULTYPE_VMWARE_GP) && 7455 !is_vmware_backdoor_opcode(ctxt)) { 7456 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 7457 return 1; 7458 } 7459 7460 /* 7461 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks 7462 * for kvm_skip_emulated_instruction(). The caller is responsible for 7463 * updating interruptibility state and injecting single-step #DBs. 7464 */ 7465 if (emulation_type & EMULTYPE_SKIP) { 7466 kvm_rip_write(vcpu, ctxt->_eip); 7467 if (ctxt->eflags & X86_EFLAGS_RF) 7468 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 7469 return 1; 7470 } 7471 7472 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) 7473 return 1; 7474 7475 /* this is needed for vmware backdoor interface to work since it 7476 changes registers values during IO operation */ 7477 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 7478 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 7479 emulator_invalidate_register_cache(ctxt); 7480 } 7481 7482 restart: 7483 if (emulation_type & EMULTYPE_PF) { 7484 /* Save the faulting GPA (cr2) in the address field */ 7485 ctxt->exception.address = cr2_or_gpa; 7486 7487 /* With shadow page tables, cr2 contains a GVA or nGPA. */ 7488 if (vcpu->arch.mmu->direct_map) { 7489 ctxt->gpa_available = true; 7490 ctxt->gpa_val = cr2_or_gpa; 7491 } 7492 } else { 7493 /* Sanitize the address out of an abundance of paranoia. */ 7494 ctxt->exception.address = 0; 7495 } 7496 7497 r = x86_emulate_insn(ctxt); 7498 7499 if (r == EMULATION_INTERCEPTED) 7500 return 1; 7501 7502 if (r == EMULATION_FAILED) { 7503 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, 7504 emulation_type)) 7505 return 1; 7506 7507 return handle_emulation_failure(vcpu, emulation_type); 7508 } 7509 7510 if (ctxt->have_exception) { 7511 r = 1; 7512 if (inject_emulated_exception(vcpu)) 7513 return r; 7514 } else if (vcpu->arch.pio.count) { 7515 if (!vcpu->arch.pio.in) { 7516 /* FIXME: return into emulator if single-stepping. */ 7517 vcpu->arch.pio.count = 0; 7518 } else { 7519 writeback = false; 7520 vcpu->arch.complete_userspace_io = complete_emulated_pio; 7521 } 7522 r = 0; 7523 } else if (vcpu->mmio_needed) { 7524 ++vcpu->stat.mmio_exits; 7525 7526 if (!vcpu->mmio_is_write) 7527 writeback = false; 7528 r = 0; 7529 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 7530 } else if (r == EMULATION_RESTART) 7531 goto restart; 7532 else 7533 r = 1; 7534 7535 if (writeback) { 7536 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 7537 toggle_interruptibility(vcpu, ctxt->interruptibility); 7538 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7539 if (!ctxt->have_exception || 7540 exception_type(ctxt->exception.vector) == EXCPT_TRAP) { 7541 kvm_rip_write(vcpu, ctxt->eip); 7542 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 7543 r = kvm_vcpu_do_singlestep(vcpu); 7544 if (kvm_x86_ops.update_emulated_instruction) 7545 static_call(kvm_x86_update_emulated_instruction)(vcpu); 7546 __kvm_set_rflags(vcpu, ctxt->eflags); 7547 } 7548 7549 /* 7550 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 7551 * do nothing, and it will be requested again as soon as 7552 * the shadow expires. But we still need to check here, 7553 * because POPF has no interrupt shadow. 7554 */ 7555 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 7556 kvm_make_request(KVM_REQ_EVENT, vcpu); 7557 } else 7558 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 7559 7560 return r; 7561 } 7562 7563 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 7564 { 7565 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 7566 } 7567 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 7568 7569 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 7570 void *insn, int insn_len) 7571 { 7572 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 7573 } 7574 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 7575 7576 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 7577 { 7578 vcpu->arch.pio.count = 0; 7579 return 1; 7580 } 7581 7582 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 7583 { 7584 vcpu->arch.pio.count = 0; 7585 7586 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 7587 return 1; 7588 7589 return kvm_skip_emulated_instruction(vcpu); 7590 } 7591 7592 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 7593 unsigned short port) 7594 { 7595 unsigned long val = kvm_rax_read(vcpu); 7596 int ret = emulator_pio_out(vcpu, size, port, &val, 1); 7597 7598 if (ret) 7599 return ret; 7600 7601 /* 7602 * Workaround userspace that relies on old KVM behavior of %rip being 7603 * incremented prior to exiting to userspace to handle "OUT 0x7e". 7604 */ 7605 if (port == 0x7e && 7606 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 7607 vcpu->arch.complete_userspace_io = 7608 complete_fast_pio_out_port_0x7e; 7609 kvm_skip_emulated_instruction(vcpu); 7610 } else { 7611 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 7612 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 7613 } 7614 return 0; 7615 } 7616 7617 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 7618 { 7619 unsigned long val; 7620 7621 /* We should only ever be called with arch.pio.count equal to 1 */ 7622 BUG_ON(vcpu->arch.pio.count != 1); 7623 7624 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 7625 vcpu->arch.pio.count = 0; 7626 return 1; 7627 } 7628 7629 /* For size less than 4 we merge, else we zero extend */ 7630 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 7631 7632 /* 7633 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform 7634 * the copy and tracing 7635 */ 7636 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1); 7637 kvm_rax_write(vcpu, val); 7638 7639 return kvm_skip_emulated_instruction(vcpu); 7640 } 7641 7642 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 7643 unsigned short port) 7644 { 7645 unsigned long val; 7646 int ret; 7647 7648 /* For size less than 4 we merge, else we zero extend */ 7649 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 7650 7651 ret = emulator_pio_in(vcpu, size, port, &val, 1); 7652 if (ret) { 7653 kvm_rax_write(vcpu, val); 7654 return ret; 7655 } 7656 7657 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 7658 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 7659 7660 return 0; 7661 } 7662 7663 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 7664 { 7665 int ret; 7666 7667 if (in) 7668 ret = kvm_fast_pio_in(vcpu, size, port); 7669 else 7670 ret = kvm_fast_pio_out(vcpu, size, port); 7671 return ret && kvm_skip_emulated_instruction(vcpu); 7672 } 7673 EXPORT_SYMBOL_GPL(kvm_fast_pio); 7674 7675 static int kvmclock_cpu_down_prep(unsigned int cpu) 7676 { 7677 __this_cpu_write(cpu_tsc_khz, 0); 7678 return 0; 7679 } 7680 7681 static void tsc_khz_changed(void *data) 7682 { 7683 struct cpufreq_freqs *freq = data; 7684 unsigned long khz = 0; 7685 7686 if (data) 7687 khz = freq->new; 7688 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 7689 khz = cpufreq_quick_get(raw_smp_processor_id()); 7690 if (!khz) 7691 khz = tsc_khz; 7692 __this_cpu_write(cpu_tsc_khz, khz); 7693 } 7694 7695 #ifdef CONFIG_X86_64 7696 static void kvm_hyperv_tsc_notifier(void) 7697 { 7698 struct kvm *kvm; 7699 struct kvm_vcpu *vcpu; 7700 int cpu; 7701 7702 mutex_lock(&kvm_lock); 7703 list_for_each_entry(kvm, &vm_list, vm_list) 7704 kvm_make_mclock_inprogress_request(kvm); 7705 7706 hyperv_stop_tsc_emulation(); 7707 7708 /* TSC frequency always matches when on Hyper-V */ 7709 for_each_present_cpu(cpu) 7710 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 7711 kvm_max_guest_tsc_khz = tsc_khz; 7712 7713 list_for_each_entry(kvm, &vm_list, vm_list) { 7714 struct kvm_arch *ka = &kvm->arch; 7715 7716 spin_lock(&ka->pvclock_gtod_sync_lock); 7717 7718 pvclock_update_vm_gtod_copy(kvm); 7719 7720 kvm_for_each_vcpu(cpu, vcpu, kvm) 7721 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7722 7723 kvm_for_each_vcpu(cpu, vcpu, kvm) 7724 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 7725 7726 spin_unlock(&ka->pvclock_gtod_sync_lock); 7727 } 7728 mutex_unlock(&kvm_lock); 7729 } 7730 #endif 7731 7732 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 7733 { 7734 struct kvm *kvm; 7735 struct kvm_vcpu *vcpu; 7736 int i, send_ipi = 0; 7737 7738 /* 7739 * We allow guests to temporarily run on slowing clocks, 7740 * provided we notify them after, or to run on accelerating 7741 * clocks, provided we notify them before. Thus time never 7742 * goes backwards. 7743 * 7744 * However, we have a problem. We can't atomically update 7745 * the frequency of a given CPU from this function; it is 7746 * merely a notifier, which can be called from any CPU. 7747 * Changing the TSC frequency at arbitrary points in time 7748 * requires a recomputation of local variables related to 7749 * the TSC for each VCPU. We must flag these local variables 7750 * to be updated and be sure the update takes place with the 7751 * new frequency before any guests proceed. 7752 * 7753 * Unfortunately, the combination of hotplug CPU and frequency 7754 * change creates an intractable locking scenario; the order 7755 * of when these callouts happen is undefined with respect to 7756 * CPU hotplug, and they can race with each other. As such, 7757 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 7758 * undefined; you can actually have a CPU frequency change take 7759 * place in between the computation of X and the setting of the 7760 * variable. To protect against this problem, all updates of 7761 * the per_cpu tsc_khz variable are done in an interrupt 7762 * protected IPI, and all callers wishing to update the value 7763 * must wait for a synchronous IPI to complete (which is trivial 7764 * if the caller is on the CPU already). This establishes the 7765 * necessary total order on variable updates. 7766 * 7767 * Note that because a guest time update may take place 7768 * anytime after the setting of the VCPU's request bit, the 7769 * correct TSC value must be set before the request. However, 7770 * to ensure the update actually makes it to any guest which 7771 * starts running in hardware virtualization between the set 7772 * and the acquisition of the spinlock, we must also ping the 7773 * CPU after setting the request bit. 7774 * 7775 */ 7776 7777 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 7778 7779 mutex_lock(&kvm_lock); 7780 list_for_each_entry(kvm, &vm_list, vm_list) { 7781 kvm_for_each_vcpu(i, vcpu, kvm) { 7782 if (vcpu->cpu != cpu) 7783 continue; 7784 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7785 if (vcpu->cpu != raw_smp_processor_id()) 7786 send_ipi = 1; 7787 } 7788 } 7789 mutex_unlock(&kvm_lock); 7790 7791 if (freq->old < freq->new && send_ipi) { 7792 /* 7793 * We upscale the frequency. Must make the guest 7794 * doesn't see old kvmclock values while running with 7795 * the new frequency, otherwise we risk the guest sees 7796 * time go backwards. 7797 * 7798 * In case we update the frequency for another cpu 7799 * (which might be in guest context) send an interrupt 7800 * to kick the cpu out of guest context. Next time 7801 * guest context is entered kvmclock will be updated, 7802 * so the guest will not see stale values. 7803 */ 7804 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 7805 } 7806 } 7807 7808 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 7809 void *data) 7810 { 7811 struct cpufreq_freqs *freq = data; 7812 int cpu; 7813 7814 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 7815 return 0; 7816 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 7817 return 0; 7818 7819 for_each_cpu(cpu, freq->policy->cpus) 7820 __kvmclock_cpufreq_notifier(freq, cpu); 7821 7822 return 0; 7823 } 7824 7825 static struct notifier_block kvmclock_cpufreq_notifier_block = { 7826 .notifier_call = kvmclock_cpufreq_notifier 7827 }; 7828 7829 static int kvmclock_cpu_online(unsigned int cpu) 7830 { 7831 tsc_khz_changed(NULL); 7832 return 0; 7833 } 7834 7835 static void kvm_timer_init(void) 7836 { 7837 max_tsc_khz = tsc_khz; 7838 7839 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 7840 #ifdef CONFIG_CPU_FREQ 7841 struct cpufreq_policy *policy; 7842 int cpu; 7843 7844 cpu = get_cpu(); 7845 policy = cpufreq_cpu_get(cpu); 7846 if (policy) { 7847 if (policy->cpuinfo.max_freq) 7848 max_tsc_khz = policy->cpuinfo.max_freq; 7849 cpufreq_cpu_put(policy); 7850 } 7851 put_cpu(); 7852 #endif 7853 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 7854 CPUFREQ_TRANSITION_NOTIFIER); 7855 } 7856 7857 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 7858 kvmclock_cpu_online, kvmclock_cpu_down_prep); 7859 } 7860 7861 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 7862 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); 7863 7864 int kvm_is_in_guest(void) 7865 { 7866 return __this_cpu_read(current_vcpu) != NULL; 7867 } 7868 7869 static int kvm_is_user_mode(void) 7870 { 7871 int user_mode = 3; 7872 7873 if (__this_cpu_read(current_vcpu)) 7874 user_mode = static_call(kvm_x86_get_cpl)(__this_cpu_read(current_vcpu)); 7875 7876 return user_mode != 0; 7877 } 7878 7879 static unsigned long kvm_get_guest_ip(void) 7880 { 7881 unsigned long ip = 0; 7882 7883 if (__this_cpu_read(current_vcpu)) 7884 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 7885 7886 return ip; 7887 } 7888 7889 static void kvm_handle_intel_pt_intr(void) 7890 { 7891 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu); 7892 7893 kvm_make_request(KVM_REQ_PMI, vcpu); 7894 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT, 7895 (unsigned long *)&vcpu->arch.pmu.global_status); 7896 } 7897 7898 static struct perf_guest_info_callbacks kvm_guest_cbs = { 7899 .is_in_guest = kvm_is_in_guest, 7900 .is_user_mode = kvm_is_user_mode, 7901 .get_guest_ip = kvm_get_guest_ip, 7902 .handle_intel_pt_intr = kvm_handle_intel_pt_intr, 7903 }; 7904 7905 #ifdef CONFIG_X86_64 7906 static void pvclock_gtod_update_fn(struct work_struct *work) 7907 { 7908 struct kvm *kvm; 7909 7910 struct kvm_vcpu *vcpu; 7911 int i; 7912 7913 mutex_lock(&kvm_lock); 7914 list_for_each_entry(kvm, &vm_list, vm_list) 7915 kvm_for_each_vcpu(i, vcpu, kvm) 7916 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7917 atomic_set(&kvm_guest_has_master_clock, 0); 7918 mutex_unlock(&kvm_lock); 7919 } 7920 7921 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 7922 7923 /* 7924 * Notification about pvclock gtod data update. 7925 */ 7926 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 7927 void *priv) 7928 { 7929 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 7930 struct timekeeper *tk = priv; 7931 7932 update_pvclock_gtod(tk); 7933 7934 /* disable master clock if host does not trust, or does not 7935 * use, TSC based clocksource. 7936 */ 7937 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 7938 atomic_read(&kvm_guest_has_master_clock) != 0) 7939 queue_work(system_long_wq, &pvclock_gtod_work); 7940 7941 return 0; 7942 } 7943 7944 static struct notifier_block pvclock_gtod_notifier = { 7945 .notifier_call = pvclock_gtod_notify, 7946 }; 7947 #endif 7948 7949 int kvm_arch_init(void *opaque) 7950 { 7951 struct kvm_x86_init_ops *ops = opaque; 7952 int r; 7953 7954 if (kvm_x86_ops.hardware_enable) { 7955 printk(KERN_ERR "kvm: already loaded the other module\n"); 7956 r = -EEXIST; 7957 goto out; 7958 } 7959 7960 if (!ops->cpu_has_kvm_support()) { 7961 pr_err_ratelimited("kvm: no hardware support\n"); 7962 r = -EOPNOTSUPP; 7963 goto out; 7964 } 7965 if (ops->disabled_by_bios()) { 7966 pr_err_ratelimited("kvm: disabled by bios\n"); 7967 r = -EOPNOTSUPP; 7968 goto out; 7969 } 7970 7971 /* 7972 * KVM explicitly assumes that the guest has an FPU and 7973 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 7974 * vCPU's FPU state as a fxregs_state struct. 7975 */ 7976 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 7977 printk(KERN_ERR "kvm: inadequate fpu\n"); 7978 r = -EOPNOTSUPP; 7979 goto out; 7980 } 7981 7982 r = -ENOMEM; 7983 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu), 7984 __alignof__(struct fpu), SLAB_ACCOUNT, 7985 NULL); 7986 if (!x86_fpu_cache) { 7987 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n"); 7988 goto out; 7989 } 7990 7991 x86_emulator_cache = kvm_alloc_emulator_cache(); 7992 if (!x86_emulator_cache) { 7993 pr_err("kvm: failed to allocate cache for x86 emulator\n"); 7994 goto out_free_x86_fpu_cache; 7995 } 7996 7997 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); 7998 if (!user_return_msrs) { 7999 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); 8000 goto out_free_x86_emulator_cache; 8001 } 8002 8003 r = kvm_mmu_module_init(); 8004 if (r) 8005 goto out_free_percpu; 8006 8007 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 8008 PT_DIRTY_MASK, PT64_NX_MASK, 0, 8009 PT_PRESENT_MASK, 0, sme_me_mask); 8010 kvm_timer_init(); 8011 8012 perf_register_guest_info_callbacks(&kvm_guest_cbs); 8013 8014 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 8015 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 8016 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; 8017 } 8018 8019 if (pi_inject_timer == -1) 8020 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER); 8021 #ifdef CONFIG_X86_64 8022 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 8023 8024 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8025 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 8026 #endif 8027 8028 return 0; 8029 8030 out_free_percpu: 8031 free_percpu(user_return_msrs); 8032 out_free_x86_emulator_cache: 8033 kmem_cache_destroy(x86_emulator_cache); 8034 out_free_x86_fpu_cache: 8035 kmem_cache_destroy(x86_fpu_cache); 8036 out: 8037 return r; 8038 } 8039 8040 void kvm_arch_exit(void) 8041 { 8042 #ifdef CONFIG_X86_64 8043 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 8044 clear_hv_tscchange_cb(); 8045 #endif 8046 kvm_lapic_exit(); 8047 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 8048 8049 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 8050 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 8051 CPUFREQ_TRANSITION_NOTIFIER); 8052 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 8053 #ifdef CONFIG_X86_64 8054 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 8055 #endif 8056 kvm_x86_ops.hardware_enable = NULL; 8057 kvm_mmu_module_exit(); 8058 free_percpu(user_return_msrs); 8059 kmem_cache_destroy(x86_fpu_cache); 8060 #ifdef CONFIG_KVM_XEN 8061 static_key_deferred_flush(&kvm_xen_enabled); 8062 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); 8063 #endif 8064 } 8065 8066 static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason) 8067 { 8068 ++vcpu->stat.halt_exits; 8069 if (lapic_in_kernel(vcpu)) { 8070 vcpu->arch.mp_state = state; 8071 return 1; 8072 } else { 8073 vcpu->run->exit_reason = reason; 8074 return 0; 8075 } 8076 } 8077 8078 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 8079 { 8080 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); 8081 } 8082 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 8083 8084 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 8085 { 8086 int ret = kvm_skip_emulated_instruction(vcpu); 8087 /* 8088 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 8089 * KVM_EXIT_DEBUG here. 8090 */ 8091 return kvm_vcpu_halt(vcpu) && ret; 8092 } 8093 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 8094 8095 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) 8096 { 8097 int ret = kvm_skip_emulated_instruction(vcpu); 8098 8099 return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret; 8100 } 8101 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); 8102 8103 #ifdef CONFIG_X86_64 8104 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 8105 unsigned long clock_type) 8106 { 8107 struct kvm_clock_pairing clock_pairing; 8108 struct timespec64 ts; 8109 u64 cycle; 8110 int ret; 8111 8112 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 8113 return -KVM_EOPNOTSUPP; 8114 8115 if (!kvm_get_walltime_and_clockread(&ts, &cycle)) 8116 return -KVM_EOPNOTSUPP; 8117 8118 clock_pairing.sec = ts.tv_sec; 8119 clock_pairing.nsec = ts.tv_nsec; 8120 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 8121 clock_pairing.flags = 0; 8122 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 8123 8124 ret = 0; 8125 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 8126 sizeof(struct kvm_clock_pairing))) 8127 ret = -KVM_EFAULT; 8128 8129 return ret; 8130 } 8131 #endif 8132 8133 /* 8134 * kvm_pv_kick_cpu_op: Kick a vcpu. 8135 * 8136 * @apicid - apicid of vcpu to be kicked. 8137 */ 8138 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 8139 { 8140 struct kvm_lapic_irq lapic_irq; 8141 8142 lapic_irq.shorthand = APIC_DEST_NOSHORT; 8143 lapic_irq.dest_mode = APIC_DEST_PHYSICAL; 8144 lapic_irq.level = 0; 8145 lapic_irq.dest_id = apicid; 8146 lapic_irq.msi_redir_hint = false; 8147 8148 lapic_irq.delivery_mode = APIC_DM_REMRD; 8149 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 8150 } 8151 8152 bool kvm_apicv_activated(struct kvm *kvm) 8153 { 8154 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); 8155 } 8156 EXPORT_SYMBOL_GPL(kvm_apicv_activated); 8157 8158 void kvm_apicv_init(struct kvm *kvm, bool enable) 8159 { 8160 if (enable) 8161 clear_bit(APICV_INHIBIT_REASON_DISABLE, 8162 &kvm->arch.apicv_inhibit_reasons); 8163 else 8164 set_bit(APICV_INHIBIT_REASON_DISABLE, 8165 &kvm->arch.apicv_inhibit_reasons); 8166 } 8167 EXPORT_SYMBOL_GPL(kvm_apicv_init); 8168 8169 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id) 8170 { 8171 struct kvm_vcpu *target = NULL; 8172 struct kvm_apic_map *map; 8173 8174 rcu_read_lock(); 8175 map = rcu_dereference(kvm->arch.apic_map); 8176 8177 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 8178 target = map->phys_map[dest_id]->vcpu; 8179 8180 rcu_read_unlock(); 8181 8182 if (target && READ_ONCE(target->ready)) 8183 kvm_vcpu_yield_to(target); 8184 } 8185 8186 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 8187 { 8188 unsigned long nr, a0, a1, a2, a3, ret; 8189 int op_64_bit; 8190 8191 if (kvm_xen_hypercall_enabled(vcpu->kvm)) 8192 return kvm_xen_hypercall(vcpu); 8193 8194 if (kvm_hv_hypercall_enabled(vcpu)) 8195 return kvm_hv_hypercall(vcpu); 8196 8197 nr = kvm_rax_read(vcpu); 8198 a0 = kvm_rbx_read(vcpu); 8199 a1 = kvm_rcx_read(vcpu); 8200 a2 = kvm_rdx_read(vcpu); 8201 a3 = kvm_rsi_read(vcpu); 8202 8203 trace_kvm_hypercall(nr, a0, a1, a2, a3); 8204 8205 op_64_bit = is_64_bit_mode(vcpu); 8206 if (!op_64_bit) { 8207 nr &= 0xFFFFFFFF; 8208 a0 &= 0xFFFFFFFF; 8209 a1 &= 0xFFFFFFFF; 8210 a2 &= 0xFFFFFFFF; 8211 a3 &= 0xFFFFFFFF; 8212 } 8213 8214 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { 8215 ret = -KVM_EPERM; 8216 goto out; 8217 } 8218 8219 ret = -KVM_ENOSYS; 8220 8221 switch (nr) { 8222 case KVM_HC_VAPIC_POLL_IRQ: 8223 ret = 0; 8224 break; 8225 case KVM_HC_KICK_CPU: 8226 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) 8227 break; 8228 8229 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 8230 kvm_sched_yield(vcpu->kvm, a1); 8231 ret = 0; 8232 break; 8233 #ifdef CONFIG_X86_64 8234 case KVM_HC_CLOCK_PAIRING: 8235 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 8236 break; 8237 #endif 8238 case KVM_HC_SEND_IPI: 8239 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) 8240 break; 8241 8242 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 8243 break; 8244 case KVM_HC_SCHED_YIELD: 8245 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) 8246 break; 8247 8248 kvm_sched_yield(vcpu->kvm, a0); 8249 ret = 0; 8250 break; 8251 default: 8252 ret = -KVM_ENOSYS; 8253 break; 8254 } 8255 out: 8256 if (!op_64_bit) 8257 ret = (u32)ret; 8258 kvm_rax_write(vcpu, ret); 8259 8260 ++vcpu->stat.hypercalls; 8261 return kvm_skip_emulated_instruction(vcpu); 8262 } 8263 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 8264 8265 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 8266 { 8267 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8268 char instruction[3]; 8269 unsigned long rip = kvm_rip_read(vcpu); 8270 8271 static_call(kvm_x86_patch_hypercall)(vcpu, instruction); 8272 8273 return emulator_write_emulated(ctxt, rip, instruction, 3, 8274 &ctxt->exception); 8275 } 8276 8277 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 8278 { 8279 return vcpu->run->request_interrupt_window && 8280 likely(!pic_in_kernel(vcpu->kvm)); 8281 } 8282 8283 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 8284 { 8285 struct kvm_run *kvm_run = vcpu->run; 8286 8287 /* 8288 * if_flag is obsolete and useless, so do not bother 8289 * setting it for SEV-ES guests. Userspace can just 8290 * use kvm_run->ready_for_interrupt_injection. 8291 */ 8292 kvm_run->if_flag = !vcpu->arch.guest_state_protected 8293 && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 8294 8295 kvm_run->cr8 = kvm_get_cr8(vcpu); 8296 kvm_run->apic_base = kvm_get_apic_base(vcpu); 8297 kvm_run->ready_for_interrupt_injection = 8298 pic_in_kernel(vcpu->kvm) || 8299 kvm_vcpu_ready_for_interrupt_injection(vcpu); 8300 8301 if (is_smm(vcpu)) 8302 kvm_run->flags |= KVM_RUN_X86_SMM; 8303 } 8304 8305 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 8306 { 8307 int max_irr, tpr; 8308 8309 if (!kvm_x86_ops.update_cr8_intercept) 8310 return; 8311 8312 if (!lapic_in_kernel(vcpu)) 8313 return; 8314 8315 if (vcpu->arch.apicv_active) 8316 return; 8317 8318 if (!vcpu->arch.apic->vapic_addr) 8319 max_irr = kvm_lapic_find_highest_irr(vcpu); 8320 else 8321 max_irr = -1; 8322 8323 if (max_irr != -1) 8324 max_irr >>= 4; 8325 8326 tpr = kvm_lapic_get_cr8(vcpu); 8327 8328 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); 8329 } 8330 8331 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) 8332 { 8333 int r; 8334 bool can_inject = true; 8335 8336 /* try to reinject previous events if any */ 8337 8338 if (vcpu->arch.exception.injected) { 8339 static_call(kvm_x86_queue_exception)(vcpu); 8340 can_inject = false; 8341 } 8342 /* 8343 * Do not inject an NMI or interrupt if there is a pending 8344 * exception. Exceptions and interrupts are recognized at 8345 * instruction boundaries, i.e. the start of an instruction. 8346 * Trap-like exceptions, e.g. #DB, have higher priority than 8347 * NMIs and interrupts, i.e. traps are recognized before an 8348 * NMI/interrupt that's pending on the same instruction. 8349 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 8350 * priority, but are only generated (pended) during instruction 8351 * execution, i.e. a pending fault-like exception means the 8352 * fault occurred on the *previous* instruction and must be 8353 * serviced prior to recognizing any new events in order to 8354 * fully complete the previous instruction. 8355 */ 8356 else if (!vcpu->arch.exception.pending) { 8357 if (vcpu->arch.nmi_injected) { 8358 static_call(kvm_x86_set_nmi)(vcpu); 8359 can_inject = false; 8360 } else if (vcpu->arch.interrupt.injected) { 8361 static_call(kvm_x86_set_irq)(vcpu); 8362 can_inject = false; 8363 } 8364 } 8365 8366 WARN_ON_ONCE(vcpu->arch.exception.injected && 8367 vcpu->arch.exception.pending); 8368 8369 /* 8370 * Call check_nested_events() even if we reinjected a previous event 8371 * in order for caller to determine if it should require immediate-exit 8372 * from L2 to L1 due to pending L1 events which require exit 8373 * from L2 to L1. 8374 */ 8375 if (is_guest_mode(vcpu)) { 8376 r = kvm_x86_ops.nested_ops->check_events(vcpu); 8377 if (r < 0) 8378 goto busy; 8379 } 8380 8381 /* try to inject new event if pending */ 8382 if (vcpu->arch.exception.pending) { 8383 trace_kvm_inj_exception(vcpu->arch.exception.nr, 8384 vcpu->arch.exception.has_error_code, 8385 vcpu->arch.exception.error_code); 8386 8387 vcpu->arch.exception.pending = false; 8388 vcpu->arch.exception.injected = true; 8389 8390 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 8391 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 8392 X86_EFLAGS_RF); 8393 8394 if (vcpu->arch.exception.nr == DB_VECTOR) { 8395 kvm_deliver_exception_payload(vcpu); 8396 if (vcpu->arch.dr7 & DR7_GD) { 8397 vcpu->arch.dr7 &= ~DR7_GD; 8398 kvm_update_dr7(vcpu); 8399 } 8400 } 8401 8402 static_call(kvm_x86_queue_exception)(vcpu); 8403 can_inject = false; 8404 } 8405 8406 /* 8407 * Finally, inject interrupt events. If an event cannot be injected 8408 * due to architectural conditions (e.g. IF=0) a window-open exit 8409 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending 8410 * and can architecturally be injected, but we cannot do it right now: 8411 * an interrupt could have arrived just now and we have to inject it 8412 * as a vmexit, or there could already an event in the queue, which is 8413 * indicated by can_inject. In that case we request an immediate exit 8414 * in order to make progress and get back here for another iteration. 8415 * The kvm_x86_ops hooks communicate this by returning -EBUSY. 8416 */ 8417 if (vcpu->arch.smi_pending) { 8418 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; 8419 if (r < 0) 8420 goto busy; 8421 if (r) { 8422 vcpu->arch.smi_pending = false; 8423 ++vcpu->arch.smi_count; 8424 enter_smm(vcpu); 8425 can_inject = false; 8426 } else 8427 static_call(kvm_x86_enable_smi_window)(vcpu); 8428 } 8429 8430 if (vcpu->arch.nmi_pending) { 8431 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; 8432 if (r < 0) 8433 goto busy; 8434 if (r) { 8435 --vcpu->arch.nmi_pending; 8436 vcpu->arch.nmi_injected = true; 8437 static_call(kvm_x86_set_nmi)(vcpu); 8438 can_inject = false; 8439 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); 8440 } 8441 if (vcpu->arch.nmi_pending) 8442 static_call(kvm_x86_enable_nmi_window)(vcpu); 8443 } 8444 8445 if (kvm_cpu_has_injectable_intr(vcpu)) { 8446 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; 8447 if (r < 0) 8448 goto busy; 8449 if (r) { 8450 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); 8451 static_call(kvm_x86_set_irq)(vcpu); 8452 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); 8453 } 8454 if (kvm_cpu_has_injectable_intr(vcpu)) 8455 static_call(kvm_x86_enable_irq_window)(vcpu); 8456 } 8457 8458 if (is_guest_mode(vcpu) && 8459 kvm_x86_ops.nested_ops->hv_timer_pending && 8460 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 8461 *req_immediate_exit = true; 8462 8463 WARN_ON(vcpu->arch.exception.pending); 8464 return; 8465 8466 busy: 8467 *req_immediate_exit = true; 8468 return; 8469 } 8470 8471 static void process_nmi(struct kvm_vcpu *vcpu) 8472 { 8473 unsigned limit = 2; 8474 8475 /* 8476 * x86 is limited to one NMI running, and one NMI pending after it. 8477 * If an NMI is already in progress, limit further NMIs to just one. 8478 * Otherwise, allow two (and we'll inject the first one immediately). 8479 */ 8480 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) 8481 limit = 1; 8482 8483 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 8484 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 8485 kvm_make_request(KVM_REQ_EVENT, vcpu); 8486 } 8487 8488 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 8489 { 8490 u32 flags = 0; 8491 flags |= seg->g << 23; 8492 flags |= seg->db << 22; 8493 flags |= seg->l << 21; 8494 flags |= seg->avl << 20; 8495 flags |= seg->present << 15; 8496 flags |= seg->dpl << 13; 8497 flags |= seg->s << 12; 8498 flags |= seg->type << 8; 8499 return flags; 8500 } 8501 8502 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 8503 { 8504 struct kvm_segment seg; 8505 int offset; 8506 8507 kvm_get_segment(vcpu, &seg, n); 8508 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 8509 8510 if (n < 3) 8511 offset = 0x7f84 + n * 12; 8512 else 8513 offset = 0x7f2c + (n - 3) * 12; 8514 8515 put_smstate(u32, buf, offset + 8, seg.base); 8516 put_smstate(u32, buf, offset + 4, seg.limit); 8517 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 8518 } 8519 8520 #ifdef CONFIG_X86_64 8521 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 8522 { 8523 struct kvm_segment seg; 8524 int offset; 8525 u16 flags; 8526 8527 kvm_get_segment(vcpu, &seg, n); 8528 offset = 0x7e00 + n * 16; 8529 8530 flags = enter_smm_get_segment_flags(&seg) >> 8; 8531 put_smstate(u16, buf, offset, seg.selector); 8532 put_smstate(u16, buf, offset + 2, flags); 8533 put_smstate(u32, buf, offset + 4, seg.limit); 8534 put_smstate(u64, buf, offset + 8, seg.base); 8535 } 8536 #endif 8537 8538 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 8539 { 8540 struct desc_ptr dt; 8541 struct kvm_segment seg; 8542 unsigned long val; 8543 int i; 8544 8545 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 8546 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 8547 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 8548 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 8549 8550 for (i = 0; i < 8; i++) 8551 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 8552 8553 kvm_get_dr(vcpu, 6, &val); 8554 put_smstate(u32, buf, 0x7fcc, (u32)val); 8555 kvm_get_dr(vcpu, 7, &val); 8556 put_smstate(u32, buf, 0x7fc8, (u32)val); 8557 8558 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 8559 put_smstate(u32, buf, 0x7fc4, seg.selector); 8560 put_smstate(u32, buf, 0x7f64, seg.base); 8561 put_smstate(u32, buf, 0x7f60, seg.limit); 8562 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 8563 8564 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 8565 put_smstate(u32, buf, 0x7fc0, seg.selector); 8566 put_smstate(u32, buf, 0x7f80, seg.base); 8567 put_smstate(u32, buf, 0x7f7c, seg.limit); 8568 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 8569 8570 static_call(kvm_x86_get_gdt)(vcpu, &dt); 8571 put_smstate(u32, buf, 0x7f74, dt.address); 8572 put_smstate(u32, buf, 0x7f70, dt.size); 8573 8574 static_call(kvm_x86_get_idt)(vcpu, &dt); 8575 put_smstate(u32, buf, 0x7f58, dt.address); 8576 put_smstate(u32, buf, 0x7f54, dt.size); 8577 8578 for (i = 0; i < 6; i++) 8579 enter_smm_save_seg_32(vcpu, buf, i); 8580 8581 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 8582 8583 /* revision id */ 8584 put_smstate(u32, buf, 0x7efc, 0x00020000); 8585 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 8586 } 8587 8588 #ifdef CONFIG_X86_64 8589 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 8590 { 8591 struct desc_ptr dt; 8592 struct kvm_segment seg; 8593 unsigned long val; 8594 int i; 8595 8596 for (i = 0; i < 16; i++) 8597 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 8598 8599 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 8600 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 8601 8602 kvm_get_dr(vcpu, 6, &val); 8603 put_smstate(u64, buf, 0x7f68, val); 8604 kvm_get_dr(vcpu, 7, &val); 8605 put_smstate(u64, buf, 0x7f60, val); 8606 8607 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 8608 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 8609 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 8610 8611 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 8612 8613 /* revision id */ 8614 put_smstate(u32, buf, 0x7efc, 0x00020064); 8615 8616 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 8617 8618 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 8619 put_smstate(u16, buf, 0x7e90, seg.selector); 8620 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 8621 put_smstate(u32, buf, 0x7e94, seg.limit); 8622 put_smstate(u64, buf, 0x7e98, seg.base); 8623 8624 static_call(kvm_x86_get_idt)(vcpu, &dt); 8625 put_smstate(u32, buf, 0x7e84, dt.size); 8626 put_smstate(u64, buf, 0x7e88, dt.address); 8627 8628 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 8629 put_smstate(u16, buf, 0x7e70, seg.selector); 8630 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 8631 put_smstate(u32, buf, 0x7e74, seg.limit); 8632 put_smstate(u64, buf, 0x7e78, seg.base); 8633 8634 static_call(kvm_x86_get_gdt)(vcpu, &dt); 8635 put_smstate(u32, buf, 0x7e64, dt.size); 8636 put_smstate(u64, buf, 0x7e68, dt.address); 8637 8638 for (i = 0; i < 6; i++) 8639 enter_smm_save_seg_64(vcpu, buf, i); 8640 } 8641 #endif 8642 8643 static void enter_smm(struct kvm_vcpu *vcpu) 8644 { 8645 struct kvm_segment cs, ds; 8646 struct desc_ptr dt; 8647 char buf[512]; 8648 u32 cr0; 8649 8650 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 8651 memset(buf, 0, 512); 8652 #ifdef CONFIG_X86_64 8653 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 8654 enter_smm_save_state_64(vcpu, buf); 8655 else 8656 #endif 8657 enter_smm_save_state_32(vcpu, buf); 8658 8659 /* 8660 * Give pre_enter_smm() a chance to make ISA-specific changes to the 8661 * vCPU state (e.g. leave guest mode) after we've saved the state into 8662 * the SMM state-save area. 8663 */ 8664 static_call(kvm_x86_pre_enter_smm)(vcpu, buf); 8665 8666 vcpu->arch.hflags |= HF_SMM_MASK; 8667 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 8668 8669 if (static_call(kvm_x86_get_nmi_mask)(vcpu)) 8670 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 8671 else 8672 static_call(kvm_x86_set_nmi_mask)(vcpu, true); 8673 8674 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 8675 kvm_rip_write(vcpu, 0x8000); 8676 8677 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 8678 static_call(kvm_x86_set_cr0)(vcpu, cr0); 8679 vcpu->arch.cr0 = cr0; 8680 8681 static_call(kvm_x86_set_cr4)(vcpu, 0); 8682 8683 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 8684 dt.address = dt.size = 0; 8685 static_call(kvm_x86_set_idt)(vcpu, &dt); 8686 8687 kvm_set_dr(vcpu, 7, DR7_FIXED_1); 8688 8689 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 8690 cs.base = vcpu->arch.smbase; 8691 8692 ds.selector = 0; 8693 ds.base = 0; 8694 8695 cs.limit = ds.limit = 0xffffffff; 8696 cs.type = ds.type = 0x3; 8697 cs.dpl = ds.dpl = 0; 8698 cs.db = ds.db = 0; 8699 cs.s = ds.s = 1; 8700 cs.l = ds.l = 0; 8701 cs.g = ds.g = 1; 8702 cs.avl = ds.avl = 0; 8703 cs.present = ds.present = 1; 8704 cs.unusable = ds.unusable = 0; 8705 cs.padding = ds.padding = 0; 8706 8707 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 8708 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 8709 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 8710 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 8711 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 8712 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 8713 8714 #ifdef CONFIG_X86_64 8715 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 8716 static_call(kvm_x86_set_efer)(vcpu, 0); 8717 #endif 8718 8719 kvm_update_cpuid_runtime(vcpu); 8720 kvm_mmu_reset_context(vcpu); 8721 } 8722 8723 static void process_smi(struct kvm_vcpu *vcpu) 8724 { 8725 vcpu->arch.smi_pending = true; 8726 kvm_make_request(KVM_REQ_EVENT, vcpu); 8727 } 8728 8729 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 8730 unsigned long *vcpu_bitmap) 8731 { 8732 cpumask_var_t cpus; 8733 8734 zalloc_cpumask_var(&cpus, GFP_ATOMIC); 8735 8736 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, 8737 NULL, vcpu_bitmap, cpus); 8738 8739 free_cpumask_var(cpus); 8740 } 8741 8742 void kvm_make_scan_ioapic_request(struct kvm *kvm) 8743 { 8744 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 8745 } 8746 8747 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 8748 { 8749 if (!lapic_in_kernel(vcpu)) 8750 return; 8751 8752 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm); 8753 kvm_apic_update_apicv(vcpu); 8754 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); 8755 } 8756 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); 8757 8758 /* 8759 * NOTE: Do not hold any lock prior to calling this. 8760 * 8761 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be 8762 * locked, because it calls __x86_set_memory_region() which does 8763 * synchronize_srcu(&kvm->srcu). 8764 */ 8765 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit) 8766 { 8767 struct kvm_vcpu *except; 8768 unsigned long old, new, expected; 8769 8770 if (!kvm_x86_ops.check_apicv_inhibit_reasons || 8771 !static_call(kvm_x86_check_apicv_inhibit_reasons)(bit)) 8772 return; 8773 8774 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons); 8775 do { 8776 expected = new = old; 8777 if (activate) 8778 __clear_bit(bit, &new); 8779 else 8780 __set_bit(bit, &new); 8781 if (new == old) 8782 break; 8783 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new); 8784 } while (old != expected); 8785 8786 if (!!old == !!new) 8787 return; 8788 8789 trace_kvm_apicv_update_request(activate, bit); 8790 if (kvm_x86_ops.pre_update_apicv_exec_ctrl) 8791 static_call(kvm_x86_pre_update_apicv_exec_ctrl)(kvm, activate); 8792 8793 /* 8794 * Sending request to update APICV for all other vcpus, 8795 * while update the calling vcpu immediately instead of 8796 * waiting for another #VMEXIT to handle the request. 8797 */ 8798 except = kvm_get_running_vcpu(); 8799 kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE, 8800 except); 8801 if (except) 8802 kvm_vcpu_update_apicv(except); 8803 } 8804 EXPORT_SYMBOL_GPL(kvm_request_apicv_update); 8805 8806 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 8807 { 8808 if (!kvm_apic_present(vcpu)) 8809 return; 8810 8811 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 8812 8813 if (irqchip_split(vcpu->kvm)) 8814 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 8815 else { 8816 if (vcpu->arch.apicv_active) 8817 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 8818 if (ioapic_in_kernel(vcpu->kvm)) 8819 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 8820 } 8821 8822 if (is_guest_mode(vcpu)) 8823 vcpu->arch.load_eoi_exitmap_pending = true; 8824 else 8825 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 8826 } 8827 8828 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 8829 { 8830 u64 eoi_exit_bitmap[4]; 8831 8832 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 8833 return; 8834 8835 if (to_hv_vcpu(vcpu)) 8836 bitmap_or((ulong *)eoi_exit_bitmap, 8837 vcpu->arch.ioapic_handled_vectors, 8838 to_hv_synic(vcpu)->vec_bitmap, 256); 8839 8840 static_call(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); 8841 } 8842 8843 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 8844 unsigned long start, unsigned long end) 8845 { 8846 unsigned long apic_address; 8847 8848 /* 8849 * The physical address of apic access page is stored in the VMCS. 8850 * Update it when it becomes invalid. 8851 */ 8852 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 8853 if (start <= apic_address && apic_address < end) 8854 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 8855 } 8856 8857 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 8858 { 8859 if (!lapic_in_kernel(vcpu)) 8860 return; 8861 8862 if (!kvm_x86_ops.set_apic_access_page_addr) 8863 return; 8864 8865 static_call(kvm_x86_set_apic_access_page_addr)(vcpu); 8866 } 8867 8868 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 8869 { 8870 smp_send_reschedule(vcpu->cpu); 8871 } 8872 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 8873 8874 /* 8875 * Returns 1 to let vcpu_run() continue the guest execution loop without 8876 * exiting to the userspace. Otherwise, the value will be returned to the 8877 * userspace. 8878 */ 8879 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 8880 { 8881 int r; 8882 bool req_int_win = 8883 dm_request_for_irq_injection(vcpu) && 8884 kvm_cpu_accept_dm_intr(vcpu); 8885 fastpath_t exit_fastpath; 8886 8887 bool req_immediate_exit = false; 8888 8889 /* Forbid vmenter if vcpu dirty ring is soft-full */ 8890 if (unlikely(vcpu->kvm->dirty_ring_size && 8891 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { 8892 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; 8893 trace_kvm_dirty_ring_exit(vcpu); 8894 r = 0; 8895 goto out; 8896 } 8897 8898 if (kvm_request_pending(vcpu)) { 8899 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { 8900 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { 8901 r = 0; 8902 goto out; 8903 } 8904 } 8905 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 8906 kvm_mmu_unload(vcpu); 8907 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 8908 __kvm_migrate_timers(vcpu); 8909 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 8910 kvm_gen_update_masterclock(vcpu->kvm); 8911 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 8912 kvm_gen_kvmclock_update(vcpu); 8913 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 8914 r = kvm_guest_time_update(vcpu); 8915 if (unlikely(r)) 8916 goto out; 8917 } 8918 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 8919 kvm_mmu_sync_roots(vcpu); 8920 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) 8921 kvm_mmu_load_pgd(vcpu); 8922 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { 8923 kvm_vcpu_flush_tlb_all(vcpu); 8924 8925 /* Flushing all ASIDs flushes the current ASID... */ 8926 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 8927 } 8928 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) 8929 kvm_vcpu_flush_tlb_current(vcpu); 8930 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu)) 8931 kvm_vcpu_flush_tlb_guest(vcpu); 8932 8933 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 8934 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 8935 r = 0; 8936 goto out; 8937 } 8938 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 8939 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 8940 vcpu->mmio_needed = 0; 8941 r = 0; 8942 goto out; 8943 } 8944 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 8945 /* Page is swapped out. Do synthetic halt */ 8946 vcpu->arch.apf.halted = true; 8947 r = 1; 8948 goto out; 8949 } 8950 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 8951 record_steal_time(vcpu); 8952 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 8953 process_smi(vcpu); 8954 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 8955 process_nmi(vcpu); 8956 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 8957 kvm_pmu_handle_event(vcpu); 8958 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 8959 kvm_pmu_deliver_pmi(vcpu); 8960 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 8961 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 8962 if (test_bit(vcpu->arch.pending_ioapic_eoi, 8963 vcpu->arch.ioapic_handled_vectors)) { 8964 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 8965 vcpu->run->eoi.vector = 8966 vcpu->arch.pending_ioapic_eoi; 8967 r = 0; 8968 goto out; 8969 } 8970 } 8971 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 8972 vcpu_scan_ioapic(vcpu); 8973 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 8974 vcpu_load_eoi_exitmap(vcpu); 8975 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 8976 kvm_vcpu_reload_apic_access_page(vcpu); 8977 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 8978 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 8979 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 8980 r = 0; 8981 goto out; 8982 } 8983 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 8984 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 8985 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 8986 r = 0; 8987 goto out; 8988 } 8989 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 8990 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); 8991 8992 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 8993 vcpu->run->hyperv = hv_vcpu->exit; 8994 r = 0; 8995 goto out; 8996 } 8997 8998 /* 8999 * KVM_REQ_HV_STIMER has to be processed after 9000 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 9001 * depend on the guest clock being up-to-date 9002 */ 9003 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 9004 kvm_hv_process_stimers(vcpu); 9005 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 9006 kvm_vcpu_update_apicv(vcpu); 9007 if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) 9008 kvm_check_async_pf_completion(vcpu); 9009 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) 9010 static_call(kvm_x86_msr_filter_changed)(vcpu); 9011 9012 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) 9013 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); 9014 } 9015 9016 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || 9017 kvm_xen_has_interrupt(vcpu)) { 9018 ++vcpu->stat.req_event; 9019 kvm_apic_accept_events(vcpu); 9020 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 9021 r = 1; 9022 goto out; 9023 } 9024 9025 inject_pending_event(vcpu, &req_immediate_exit); 9026 if (req_int_win) 9027 static_call(kvm_x86_enable_irq_window)(vcpu); 9028 9029 if (kvm_lapic_enabled(vcpu)) { 9030 update_cr8_intercept(vcpu); 9031 kvm_lapic_sync_to_vapic(vcpu); 9032 } 9033 } 9034 9035 r = kvm_mmu_reload(vcpu); 9036 if (unlikely(r)) { 9037 goto cancel_injection; 9038 } 9039 9040 preempt_disable(); 9041 9042 static_call(kvm_x86_prepare_guest_switch)(vcpu); 9043 9044 /* 9045 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 9046 * IPI are then delayed after guest entry, which ensures that they 9047 * result in virtual interrupt delivery. 9048 */ 9049 local_irq_disable(); 9050 vcpu->mode = IN_GUEST_MODE; 9051 9052 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 9053 9054 /* 9055 * 1) We should set ->mode before checking ->requests. Please see 9056 * the comment in kvm_vcpu_exiting_guest_mode(). 9057 * 9058 * 2) For APICv, we should set ->mode before checking PID.ON. This 9059 * pairs with the memory barrier implicit in pi_test_and_set_on 9060 * (see vmx_deliver_posted_interrupt). 9061 * 9062 * 3) This also orders the write to mode from any reads to the page 9063 * tables done while the VCPU is running. Please see the comment 9064 * in kvm_flush_remote_tlbs. 9065 */ 9066 smp_mb__after_srcu_read_unlock(); 9067 9068 /* 9069 * This handles the case where a posted interrupt was 9070 * notified with kvm_vcpu_kick. 9071 */ 9072 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) 9073 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 9074 9075 if (kvm_vcpu_exit_request(vcpu)) { 9076 vcpu->mode = OUTSIDE_GUEST_MODE; 9077 smp_wmb(); 9078 local_irq_enable(); 9079 preempt_enable(); 9080 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9081 r = 1; 9082 goto cancel_injection; 9083 } 9084 9085 if (req_immediate_exit) { 9086 kvm_make_request(KVM_REQ_EVENT, vcpu); 9087 static_call(kvm_x86_request_immediate_exit)(vcpu); 9088 } 9089 9090 fpregs_assert_state_consistent(); 9091 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 9092 switch_fpu_return(); 9093 9094 if (unlikely(vcpu->arch.switch_db_regs)) { 9095 set_debugreg(0, 7); 9096 set_debugreg(vcpu->arch.eff_db[0], 0); 9097 set_debugreg(vcpu->arch.eff_db[1], 1); 9098 set_debugreg(vcpu->arch.eff_db[2], 2); 9099 set_debugreg(vcpu->arch.eff_db[3], 3); 9100 set_debugreg(vcpu->arch.dr6, 6); 9101 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 9102 } 9103 9104 for (;;) { 9105 exit_fastpath = static_call(kvm_x86_run)(vcpu); 9106 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) 9107 break; 9108 9109 if (unlikely(kvm_vcpu_exit_request(vcpu))) { 9110 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; 9111 break; 9112 } 9113 9114 if (vcpu->arch.apicv_active) 9115 static_call(kvm_x86_sync_pir_to_irr)(vcpu); 9116 } 9117 9118 /* 9119 * Do this here before restoring debug registers on the host. And 9120 * since we do this before handling the vmexit, a DR access vmexit 9121 * can (a) read the correct value of the debug registers, (b) set 9122 * KVM_DEBUGREG_WONT_EXIT again. 9123 */ 9124 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 9125 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 9126 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); 9127 kvm_update_dr0123(vcpu); 9128 kvm_update_dr7(vcpu); 9129 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 9130 } 9131 9132 /* 9133 * If the guest has used debug registers, at least dr7 9134 * will be disabled while returning to the host. 9135 * If we don't have active breakpoints in the host, we don't 9136 * care about the messed up debug address registers. But if 9137 * we have some of them active, restore the old state. 9138 */ 9139 if (hw_breakpoint_active()) 9140 hw_breakpoint_restore(); 9141 9142 vcpu->arch.last_vmentry_cpu = vcpu->cpu; 9143 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 9144 9145 vcpu->mode = OUTSIDE_GUEST_MODE; 9146 smp_wmb(); 9147 9148 static_call(kvm_x86_handle_exit_irqoff)(vcpu); 9149 9150 /* 9151 * Consume any pending interrupts, including the possible source of 9152 * VM-Exit on SVM and any ticks that occur between VM-Exit and now. 9153 * An instruction is required after local_irq_enable() to fully unblock 9154 * interrupts on processors that implement an interrupt shadow, the 9155 * stat.exits increment will do nicely. 9156 */ 9157 kvm_before_interrupt(vcpu); 9158 local_irq_enable(); 9159 ++vcpu->stat.exits; 9160 local_irq_disable(); 9161 kvm_after_interrupt(vcpu); 9162 9163 if (lapic_in_kernel(vcpu)) { 9164 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta; 9165 if (delta != S64_MIN) { 9166 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta); 9167 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN; 9168 } 9169 } 9170 9171 local_irq_enable(); 9172 preempt_enable(); 9173 9174 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9175 9176 /* 9177 * Profile KVM exit RIPs: 9178 */ 9179 if (unlikely(prof_on == KVM_PROFILING)) { 9180 unsigned long rip = kvm_rip_read(vcpu); 9181 profile_hit(KVM_PROFILING, (void *)rip); 9182 } 9183 9184 if (unlikely(vcpu->arch.tsc_always_catchup)) 9185 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 9186 9187 if (vcpu->arch.apic_attention) 9188 kvm_lapic_sync_from_vapic(vcpu); 9189 9190 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); 9191 return r; 9192 9193 cancel_injection: 9194 if (req_immediate_exit) 9195 kvm_make_request(KVM_REQ_EVENT, vcpu); 9196 static_call(kvm_x86_cancel_injection)(vcpu); 9197 if (unlikely(vcpu->arch.apic_attention)) 9198 kvm_lapic_sync_from_vapic(vcpu); 9199 out: 9200 return r; 9201 } 9202 9203 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 9204 { 9205 if (!kvm_arch_vcpu_runnable(vcpu) && 9206 (!kvm_x86_ops.pre_block || static_call(kvm_x86_pre_block)(vcpu) == 0)) { 9207 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9208 kvm_vcpu_block(vcpu); 9209 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9210 9211 if (kvm_x86_ops.post_block) 9212 static_call(kvm_x86_post_block)(vcpu); 9213 9214 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 9215 return 1; 9216 } 9217 9218 kvm_apic_accept_events(vcpu); 9219 switch(vcpu->arch.mp_state) { 9220 case KVM_MP_STATE_HALTED: 9221 case KVM_MP_STATE_AP_RESET_HOLD: 9222 vcpu->arch.pv.pv_unhalted = false; 9223 vcpu->arch.mp_state = 9224 KVM_MP_STATE_RUNNABLE; 9225 fallthrough; 9226 case KVM_MP_STATE_RUNNABLE: 9227 vcpu->arch.apf.halted = false; 9228 break; 9229 case KVM_MP_STATE_INIT_RECEIVED: 9230 break; 9231 default: 9232 return -EINTR; 9233 } 9234 return 1; 9235 } 9236 9237 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 9238 { 9239 if (is_guest_mode(vcpu)) 9240 kvm_x86_ops.nested_ops->check_events(vcpu); 9241 9242 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 9243 !vcpu->arch.apf.halted); 9244 } 9245 9246 static int vcpu_run(struct kvm_vcpu *vcpu) 9247 { 9248 int r; 9249 struct kvm *kvm = vcpu->kvm; 9250 9251 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9252 vcpu->arch.l1tf_flush_l1d = true; 9253 9254 for (;;) { 9255 if (kvm_vcpu_running(vcpu)) { 9256 r = vcpu_enter_guest(vcpu); 9257 } else { 9258 r = vcpu_block(kvm, vcpu); 9259 } 9260 9261 if (r <= 0) 9262 break; 9263 9264 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); 9265 if (kvm_cpu_has_pending_timer(vcpu)) 9266 kvm_inject_pending_timer_irqs(vcpu); 9267 9268 if (dm_request_for_irq_injection(vcpu) && 9269 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 9270 r = 0; 9271 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 9272 ++vcpu->stat.request_irq_exits; 9273 break; 9274 } 9275 9276 if (__xfer_to_guest_mode_work_pending()) { 9277 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9278 r = xfer_to_guest_mode_handle_work(vcpu); 9279 if (r) 9280 return r; 9281 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 9282 } 9283 } 9284 9285 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 9286 9287 return r; 9288 } 9289 9290 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 9291 { 9292 int r; 9293 9294 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 9295 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 9296 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 9297 return r; 9298 } 9299 9300 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 9301 { 9302 BUG_ON(!vcpu->arch.pio.count); 9303 9304 return complete_emulated_io(vcpu); 9305 } 9306 9307 /* 9308 * Implements the following, as a state machine: 9309 * 9310 * read: 9311 * for each fragment 9312 * for each mmio piece in the fragment 9313 * write gpa, len 9314 * exit 9315 * copy data 9316 * execute insn 9317 * 9318 * write: 9319 * for each fragment 9320 * for each mmio piece in the fragment 9321 * write gpa, len 9322 * copy data 9323 * exit 9324 */ 9325 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 9326 { 9327 struct kvm_run *run = vcpu->run; 9328 struct kvm_mmio_fragment *frag; 9329 unsigned len; 9330 9331 BUG_ON(!vcpu->mmio_needed); 9332 9333 /* Complete previous fragment */ 9334 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 9335 len = min(8u, frag->len); 9336 if (!vcpu->mmio_is_write) 9337 memcpy(frag->data, run->mmio.data, len); 9338 9339 if (frag->len <= 8) { 9340 /* Switch to the next fragment. */ 9341 frag++; 9342 vcpu->mmio_cur_fragment++; 9343 } else { 9344 /* Go forward to the next mmio piece. */ 9345 frag->data += len; 9346 frag->gpa += len; 9347 frag->len -= len; 9348 } 9349 9350 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 9351 vcpu->mmio_needed = 0; 9352 9353 /* FIXME: return into emulator if single-stepping. */ 9354 if (vcpu->mmio_is_write) 9355 return 1; 9356 vcpu->mmio_read_completed = 1; 9357 return complete_emulated_io(vcpu); 9358 } 9359 9360 run->exit_reason = KVM_EXIT_MMIO; 9361 run->mmio.phys_addr = frag->gpa; 9362 if (vcpu->mmio_is_write) 9363 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 9364 run->mmio.len = min(8u, frag->len); 9365 run->mmio.is_write = vcpu->mmio_is_write; 9366 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 9367 return 0; 9368 } 9369 9370 static void kvm_save_current_fpu(struct fpu *fpu) 9371 { 9372 /* 9373 * If the target FPU state is not resident in the CPU registers, just 9374 * memcpy() from current, else save CPU state directly to the target. 9375 */ 9376 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 9377 memcpy(&fpu->state, ¤t->thread.fpu.state, 9378 fpu_kernel_xstate_size); 9379 else 9380 copy_fpregs_to_fpstate(fpu); 9381 } 9382 9383 /* Swap (qemu) user FPU context for the guest FPU context. */ 9384 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 9385 { 9386 fpregs_lock(); 9387 9388 kvm_save_current_fpu(vcpu->arch.user_fpu); 9389 9390 /* 9391 * Guests with protected state can't have it set by the hypervisor, 9392 * so skip trying to set it. 9393 */ 9394 if (vcpu->arch.guest_fpu) 9395 /* PKRU is separately restored in kvm_x86_ops.run. */ 9396 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, 9397 ~XFEATURE_MASK_PKRU); 9398 9399 fpregs_mark_activate(); 9400 fpregs_unlock(); 9401 9402 trace_kvm_fpu(1); 9403 } 9404 9405 /* When vcpu_run ends, restore user space FPU context. */ 9406 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 9407 { 9408 fpregs_lock(); 9409 9410 /* 9411 * Guests with protected state can't have it read by the hypervisor, 9412 * so skip trying to save it. 9413 */ 9414 if (vcpu->arch.guest_fpu) 9415 kvm_save_current_fpu(vcpu->arch.guest_fpu); 9416 9417 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); 9418 9419 fpregs_mark_activate(); 9420 fpregs_unlock(); 9421 9422 ++vcpu->stat.fpu_reload; 9423 trace_kvm_fpu(0); 9424 } 9425 9426 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 9427 { 9428 struct kvm_run *kvm_run = vcpu->run; 9429 int r; 9430 9431 vcpu_load(vcpu); 9432 kvm_sigset_activate(vcpu); 9433 kvm_run->flags = 0; 9434 kvm_load_guest_fpu(vcpu); 9435 9436 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 9437 if (kvm_run->immediate_exit) { 9438 r = -EINTR; 9439 goto out; 9440 } 9441 kvm_vcpu_block(vcpu); 9442 kvm_apic_accept_events(vcpu); 9443 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 9444 r = -EAGAIN; 9445 if (signal_pending(current)) { 9446 r = -EINTR; 9447 kvm_run->exit_reason = KVM_EXIT_INTR; 9448 ++vcpu->stat.signal_exits; 9449 } 9450 goto out; 9451 } 9452 9453 if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { 9454 r = -EINVAL; 9455 goto out; 9456 } 9457 9458 if (kvm_run->kvm_dirty_regs) { 9459 r = sync_regs(vcpu); 9460 if (r != 0) 9461 goto out; 9462 } 9463 9464 /* re-sync apic's tpr */ 9465 if (!lapic_in_kernel(vcpu)) { 9466 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 9467 r = -EINVAL; 9468 goto out; 9469 } 9470 } 9471 9472 if (unlikely(vcpu->arch.complete_userspace_io)) { 9473 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 9474 vcpu->arch.complete_userspace_io = NULL; 9475 r = cui(vcpu); 9476 if (r <= 0) 9477 goto out; 9478 } else 9479 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 9480 9481 if (kvm_run->immediate_exit) 9482 r = -EINTR; 9483 else 9484 r = vcpu_run(vcpu); 9485 9486 out: 9487 kvm_put_guest_fpu(vcpu); 9488 if (kvm_run->kvm_valid_regs) 9489 store_regs(vcpu); 9490 post_kvm_run_save(vcpu); 9491 kvm_sigset_deactivate(vcpu); 9492 9493 vcpu_put(vcpu); 9494 return r; 9495 } 9496 9497 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9498 { 9499 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 9500 /* 9501 * We are here if userspace calls get_regs() in the middle of 9502 * instruction emulation. Registers state needs to be copied 9503 * back from emulation context to vcpu. Userspace shouldn't do 9504 * that usually, but some bad designed PV devices (vmware 9505 * backdoor interface) need this to work 9506 */ 9507 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); 9508 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 9509 } 9510 regs->rax = kvm_rax_read(vcpu); 9511 regs->rbx = kvm_rbx_read(vcpu); 9512 regs->rcx = kvm_rcx_read(vcpu); 9513 regs->rdx = kvm_rdx_read(vcpu); 9514 regs->rsi = kvm_rsi_read(vcpu); 9515 regs->rdi = kvm_rdi_read(vcpu); 9516 regs->rsp = kvm_rsp_read(vcpu); 9517 regs->rbp = kvm_rbp_read(vcpu); 9518 #ifdef CONFIG_X86_64 9519 regs->r8 = kvm_r8_read(vcpu); 9520 regs->r9 = kvm_r9_read(vcpu); 9521 regs->r10 = kvm_r10_read(vcpu); 9522 regs->r11 = kvm_r11_read(vcpu); 9523 regs->r12 = kvm_r12_read(vcpu); 9524 regs->r13 = kvm_r13_read(vcpu); 9525 regs->r14 = kvm_r14_read(vcpu); 9526 regs->r15 = kvm_r15_read(vcpu); 9527 #endif 9528 9529 regs->rip = kvm_rip_read(vcpu); 9530 regs->rflags = kvm_get_rflags(vcpu); 9531 } 9532 9533 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9534 { 9535 vcpu_load(vcpu); 9536 __get_regs(vcpu, regs); 9537 vcpu_put(vcpu); 9538 return 0; 9539 } 9540 9541 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9542 { 9543 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 9544 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 9545 9546 kvm_rax_write(vcpu, regs->rax); 9547 kvm_rbx_write(vcpu, regs->rbx); 9548 kvm_rcx_write(vcpu, regs->rcx); 9549 kvm_rdx_write(vcpu, regs->rdx); 9550 kvm_rsi_write(vcpu, regs->rsi); 9551 kvm_rdi_write(vcpu, regs->rdi); 9552 kvm_rsp_write(vcpu, regs->rsp); 9553 kvm_rbp_write(vcpu, regs->rbp); 9554 #ifdef CONFIG_X86_64 9555 kvm_r8_write(vcpu, regs->r8); 9556 kvm_r9_write(vcpu, regs->r9); 9557 kvm_r10_write(vcpu, regs->r10); 9558 kvm_r11_write(vcpu, regs->r11); 9559 kvm_r12_write(vcpu, regs->r12); 9560 kvm_r13_write(vcpu, regs->r13); 9561 kvm_r14_write(vcpu, regs->r14); 9562 kvm_r15_write(vcpu, regs->r15); 9563 #endif 9564 9565 kvm_rip_write(vcpu, regs->rip); 9566 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 9567 9568 vcpu->arch.exception.pending = false; 9569 9570 kvm_make_request(KVM_REQ_EVENT, vcpu); 9571 } 9572 9573 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 9574 { 9575 vcpu_load(vcpu); 9576 __set_regs(vcpu, regs); 9577 vcpu_put(vcpu); 9578 return 0; 9579 } 9580 9581 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 9582 { 9583 struct kvm_segment cs; 9584 9585 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 9586 *db = cs.db; 9587 *l = cs.l; 9588 } 9589 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 9590 9591 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 9592 { 9593 struct desc_ptr dt; 9594 9595 if (vcpu->arch.guest_state_protected) 9596 goto skip_protected_regs; 9597 9598 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 9599 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 9600 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 9601 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 9602 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 9603 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 9604 9605 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 9606 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 9607 9608 static_call(kvm_x86_get_idt)(vcpu, &dt); 9609 sregs->idt.limit = dt.size; 9610 sregs->idt.base = dt.address; 9611 static_call(kvm_x86_get_gdt)(vcpu, &dt); 9612 sregs->gdt.limit = dt.size; 9613 sregs->gdt.base = dt.address; 9614 9615 sregs->cr2 = vcpu->arch.cr2; 9616 sregs->cr3 = kvm_read_cr3(vcpu); 9617 9618 skip_protected_regs: 9619 sregs->cr0 = kvm_read_cr0(vcpu); 9620 sregs->cr4 = kvm_read_cr4(vcpu); 9621 sregs->cr8 = kvm_get_cr8(vcpu); 9622 sregs->efer = vcpu->arch.efer; 9623 sregs->apic_base = kvm_get_apic_base(vcpu); 9624 9625 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap)); 9626 9627 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 9628 set_bit(vcpu->arch.interrupt.nr, 9629 (unsigned long *)sregs->interrupt_bitmap); 9630 } 9631 9632 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 9633 struct kvm_sregs *sregs) 9634 { 9635 vcpu_load(vcpu); 9636 __get_sregs(vcpu, sregs); 9637 vcpu_put(vcpu); 9638 return 0; 9639 } 9640 9641 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 9642 struct kvm_mp_state *mp_state) 9643 { 9644 vcpu_load(vcpu); 9645 if (kvm_mpx_supported()) 9646 kvm_load_guest_fpu(vcpu); 9647 9648 kvm_apic_accept_events(vcpu); 9649 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || 9650 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && 9651 vcpu->arch.pv.pv_unhalted) 9652 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 9653 else 9654 mp_state->mp_state = vcpu->arch.mp_state; 9655 9656 if (kvm_mpx_supported()) 9657 kvm_put_guest_fpu(vcpu); 9658 vcpu_put(vcpu); 9659 return 0; 9660 } 9661 9662 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 9663 struct kvm_mp_state *mp_state) 9664 { 9665 int ret = -EINVAL; 9666 9667 vcpu_load(vcpu); 9668 9669 if (!lapic_in_kernel(vcpu) && 9670 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 9671 goto out; 9672 9673 /* 9674 * KVM_MP_STATE_INIT_RECEIVED means the processor is in 9675 * INIT state; latched init should be reported using 9676 * KVM_SET_VCPU_EVENTS, so reject it here. 9677 */ 9678 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && 9679 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 9680 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 9681 goto out; 9682 9683 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 9684 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 9685 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 9686 } else 9687 vcpu->arch.mp_state = mp_state->mp_state; 9688 kvm_make_request(KVM_REQ_EVENT, vcpu); 9689 9690 ret = 0; 9691 out: 9692 vcpu_put(vcpu); 9693 return ret; 9694 } 9695 9696 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 9697 int reason, bool has_error_code, u32 error_code) 9698 { 9699 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 9700 int ret; 9701 9702 init_emulate_ctxt(vcpu); 9703 9704 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 9705 has_error_code, error_code); 9706 if (ret) { 9707 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 9708 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 9709 vcpu->run->internal.ndata = 0; 9710 return 0; 9711 } 9712 9713 kvm_rip_write(vcpu, ctxt->eip); 9714 kvm_set_rflags(vcpu, ctxt->eflags); 9715 return 1; 9716 } 9717 EXPORT_SYMBOL_GPL(kvm_task_switch); 9718 9719 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 9720 { 9721 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 9722 /* 9723 * When EFER.LME and CR0.PG are set, the processor is in 9724 * 64-bit mode (though maybe in a 32-bit code segment). 9725 * CR4.PAE and EFER.LMA must be set. 9726 */ 9727 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) 9728 return false; 9729 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) 9730 return false; 9731 } else { 9732 /* 9733 * Not in 64-bit mode: EFER.LMA is clear and the code 9734 * segment cannot be 64-bit. 9735 */ 9736 if (sregs->efer & EFER_LMA || sregs->cs.l) 9737 return false; 9738 } 9739 9740 return kvm_is_valid_cr4(vcpu, sregs->cr4); 9741 } 9742 9743 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 9744 { 9745 struct msr_data apic_base_msr; 9746 int mmu_reset_needed = 0; 9747 int pending_vec, max_bits, idx; 9748 struct desc_ptr dt; 9749 int ret = -EINVAL; 9750 9751 if (!kvm_is_valid_sregs(vcpu, sregs)) 9752 goto out; 9753 9754 apic_base_msr.data = sregs->apic_base; 9755 apic_base_msr.host_initiated = true; 9756 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 9757 goto out; 9758 9759 if (vcpu->arch.guest_state_protected) 9760 goto skip_protected_regs; 9761 9762 dt.size = sregs->idt.limit; 9763 dt.address = sregs->idt.base; 9764 static_call(kvm_x86_set_idt)(vcpu, &dt); 9765 dt.size = sregs->gdt.limit; 9766 dt.address = sregs->gdt.base; 9767 static_call(kvm_x86_set_gdt)(vcpu, &dt); 9768 9769 vcpu->arch.cr2 = sregs->cr2; 9770 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 9771 vcpu->arch.cr3 = sregs->cr3; 9772 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3); 9773 9774 kvm_set_cr8(vcpu, sregs->cr8); 9775 9776 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 9777 static_call(kvm_x86_set_efer)(vcpu, sregs->efer); 9778 9779 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 9780 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); 9781 vcpu->arch.cr0 = sregs->cr0; 9782 9783 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 9784 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); 9785 9786 idx = srcu_read_lock(&vcpu->kvm->srcu); 9787 if (is_pae_paging(vcpu)) { 9788 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 9789 mmu_reset_needed = 1; 9790 } 9791 srcu_read_unlock(&vcpu->kvm->srcu, idx); 9792 9793 if (mmu_reset_needed) 9794 kvm_mmu_reset_context(vcpu); 9795 9796 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 9797 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 9798 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 9799 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 9800 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 9801 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 9802 9803 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 9804 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 9805 9806 update_cr8_intercept(vcpu); 9807 9808 /* Older userspace won't unhalt the vcpu on reset. */ 9809 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 9810 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 9811 !is_protmode(vcpu)) 9812 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 9813 9814 skip_protected_regs: 9815 max_bits = KVM_NR_INTERRUPTS; 9816 pending_vec = find_first_bit( 9817 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 9818 if (pending_vec < max_bits) { 9819 kvm_queue_interrupt(vcpu, pending_vec, false); 9820 pr_debug("Set back pending irq %d\n", pending_vec); 9821 } 9822 9823 kvm_make_request(KVM_REQ_EVENT, vcpu); 9824 9825 ret = 0; 9826 out: 9827 return ret; 9828 } 9829 9830 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 9831 struct kvm_sregs *sregs) 9832 { 9833 int ret; 9834 9835 vcpu_load(vcpu); 9836 ret = __set_sregs(vcpu, sregs); 9837 vcpu_put(vcpu); 9838 return ret; 9839 } 9840 9841 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 9842 struct kvm_guest_debug *dbg) 9843 { 9844 unsigned long rflags; 9845 int i, r; 9846 9847 if (vcpu->arch.guest_state_protected) 9848 return -EINVAL; 9849 9850 vcpu_load(vcpu); 9851 9852 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 9853 r = -EBUSY; 9854 if (vcpu->arch.exception.pending) 9855 goto out; 9856 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 9857 kvm_queue_exception(vcpu, DB_VECTOR); 9858 else 9859 kvm_queue_exception(vcpu, BP_VECTOR); 9860 } 9861 9862 /* 9863 * Read rflags as long as potentially injected trace flags are still 9864 * filtered out. 9865 */ 9866 rflags = kvm_get_rflags(vcpu); 9867 9868 vcpu->guest_debug = dbg->control; 9869 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 9870 vcpu->guest_debug = 0; 9871 9872 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 9873 for (i = 0; i < KVM_NR_DB_REGS; ++i) 9874 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 9875 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 9876 } else { 9877 for (i = 0; i < KVM_NR_DB_REGS; i++) 9878 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 9879 } 9880 kvm_update_dr7(vcpu); 9881 9882 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 9883 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 9884 get_segment_base(vcpu, VCPU_SREG_CS); 9885 9886 /* 9887 * Trigger an rflags update that will inject or remove the trace 9888 * flags. 9889 */ 9890 kvm_set_rflags(vcpu, rflags); 9891 9892 static_call(kvm_x86_update_exception_bitmap)(vcpu); 9893 9894 r = 0; 9895 9896 out: 9897 vcpu_put(vcpu); 9898 return r; 9899 } 9900 9901 /* 9902 * Translate a guest virtual address to a guest physical address. 9903 */ 9904 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 9905 struct kvm_translation *tr) 9906 { 9907 unsigned long vaddr = tr->linear_address; 9908 gpa_t gpa; 9909 int idx; 9910 9911 vcpu_load(vcpu); 9912 9913 idx = srcu_read_lock(&vcpu->kvm->srcu); 9914 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 9915 srcu_read_unlock(&vcpu->kvm->srcu, idx); 9916 tr->physical_address = gpa; 9917 tr->valid = gpa != UNMAPPED_GVA; 9918 tr->writeable = 1; 9919 tr->usermode = 0; 9920 9921 vcpu_put(vcpu); 9922 return 0; 9923 } 9924 9925 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 9926 { 9927 struct fxregs_state *fxsave; 9928 9929 if (!vcpu->arch.guest_fpu) 9930 return 0; 9931 9932 vcpu_load(vcpu); 9933 9934 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 9935 memcpy(fpu->fpr, fxsave->st_space, 128); 9936 fpu->fcw = fxsave->cwd; 9937 fpu->fsw = fxsave->swd; 9938 fpu->ftwx = fxsave->twd; 9939 fpu->last_opcode = fxsave->fop; 9940 fpu->last_ip = fxsave->rip; 9941 fpu->last_dp = fxsave->rdp; 9942 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 9943 9944 vcpu_put(vcpu); 9945 return 0; 9946 } 9947 9948 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 9949 { 9950 struct fxregs_state *fxsave; 9951 9952 if (!vcpu->arch.guest_fpu) 9953 return 0; 9954 9955 vcpu_load(vcpu); 9956 9957 fxsave = &vcpu->arch.guest_fpu->state.fxsave; 9958 9959 memcpy(fxsave->st_space, fpu->fpr, 128); 9960 fxsave->cwd = fpu->fcw; 9961 fxsave->swd = fpu->fsw; 9962 fxsave->twd = fpu->ftwx; 9963 fxsave->fop = fpu->last_opcode; 9964 fxsave->rip = fpu->last_ip; 9965 fxsave->rdp = fpu->last_dp; 9966 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 9967 9968 vcpu_put(vcpu); 9969 return 0; 9970 } 9971 9972 static void store_regs(struct kvm_vcpu *vcpu) 9973 { 9974 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 9975 9976 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 9977 __get_regs(vcpu, &vcpu->run->s.regs.regs); 9978 9979 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 9980 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 9981 9982 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 9983 kvm_vcpu_ioctl_x86_get_vcpu_events( 9984 vcpu, &vcpu->run->s.regs.events); 9985 } 9986 9987 static int sync_regs(struct kvm_vcpu *vcpu) 9988 { 9989 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) 9990 return -EINVAL; 9991 9992 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 9993 __set_regs(vcpu, &vcpu->run->s.regs.regs); 9994 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 9995 } 9996 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 9997 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 9998 return -EINVAL; 9999 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 10000 } 10001 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 10002 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 10003 vcpu, &vcpu->run->s.regs.events)) 10004 return -EINVAL; 10005 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 10006 } 10007 10008 return 0; 10009 } 10010 10011 static void fx_init(struct kvm_vcpu *vcpu) 10012 { 10013 if (!vcpu->arch.guest_fpu) 10014 return; 10015 10016 fpstate_init(&vcpu->arch.guest_fpu->state); 10017 if (boot_cpu_has(X86_FEATURE_XSAVES)) 10018 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv = 10019 host_xcr0 | XSTATE_COMPACTION_ENABLED; 10020 10021 /* 10022 * Ensure guest xcr0 is valid for loading 10023 */ 10024 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 10025 10026 vcpu->arch.cr0 |= X86_CR0_ET; 10027 } 10028 10029 void kvm_free_guest_fpu(struct kvm_vcpu *vcpu) 10030 { 10031 if (vcpu->arch.guest_fpu) { 10032 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu); 10033 vcpu->arch.guest_fpu = NULL; 10034 } 10035 } 10036 EXPORT_SYMBOL_GPL(kvm_free_guest_fpu); 10037 10038 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 10039 { 10040 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 10041 pr_warn_once("kvm: SMP vm created on host with unstable TSC; " 10042 "guest TSC will not be reliable\n"); 10043 10044 return 0; 10045 } 10046 10047 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 10048 { 10049 struct page *page; 10050 int r; 10051 10052 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 10053 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 10054 else 10055 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 10056 10057 kvm_set_tsc_khz(vcpu, max_tsc_khz); 10058 10059 r = kvm_mmu_create(vcpu); 10060 if (r < 0) 10061 return r; 10062 10063 if (irqchip_in_kernel(vcpu->kvm)) { 10064 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 10065 if (r < 0) 10066 goto fail_mmu_destroy; 10067 if (kvm_apicv_activated(vcpu->kvm)) 10068 vcpu->arch.apicv_active = true; 10069 } else 10070 static_branch_inc(&kvm_has_noapic_vcpu); 10071 10072 r = -ENOMEM; 10073 10074 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 10075 if (!page) 10076 goto fail_free_lapic; 10077 vcpu->arch.pio_data = page_address(page); 10078 10079 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 10080 GFP_KERNEL_ACCOUNT); 10081 if (!vcpu->arch.mce_banks) 10082 goto fail_free_pio_data; 10083 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 10084 10085 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 10086 GFP_KERNEL_ACCOUNT)) 10087 goto fail_free_mce_banks; 10088 10089 if (!alloc_emulate_ctxt(vcpu)) 10090 goto free_wbinvd_dirty_mask; 10091 10092 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, 10093 GFP_KERNEL_ACCOUNT); 10094 if (!vcpu->arch.user_fpu) { 10095 pr_err("kvm: failed to allocate userspace's fpu\n"); 10096 goto free_emulate_ctxt; 10097 } 10098 10099 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, 10100 GFP_KERNEL_ACCOUNT); 10101 if (!vcpu->arch.guest_fpu) { 10102 pr_err("kvm: failed to allocate vcpu's fpu\n"); 10103 goto free_user_fpu; 10104 } 10105 fx_init(vcpu); 10106 10107 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 10108 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 10109 10110 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 10111 10112 kvm_async_pf_hash_reset(vcpu); 10113 kvm_pmu_init(vcpu); 10114 10115 vcpu->arch.pending_external_vector = -1; 10116 vcpu->arch.preempted_in_kernel = false; 10117 10118 r = static_call(kvm_x86_vcpu_create)(vcpu); 10119 if (r) 10120 goto free_guest_fpu; 10121 10122 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 10123 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 10124 kvm_vcpu_mtrr_init(vcpu); 10125 vcpu_load(vcpu); 10126 kvm_vcpu_reset(vcpu, false); 10127 kvm_init_mmu(vcpu, false); 10128 vcpu_put(vcpu); 10129 return 0; 10130 10131 free_guest_fpu: 10132 kvm_free_guest_fpu(vcpu); 10133 free_user_fpu: 10134 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); 10135 free_emulate_ctxt: 10136 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 10137 free_wbinvd_dirty_mask: 10138 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 10139 fail_free_mce_banks: 10140 kfree(vcpu->arch.mce_banks); 10141 fail_free_pio_data: 10142 free_page((unsigned long)vcpu->arch.pio_data); 10143 fail_free_lapic: 10144 kvm_free_lapic(vcpu); 10145 fail_mmu_destroy: 10146 kvm_mmu_destroy(vcpu); 10147 return r; 10148 } 10149 10150 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 10151 { 10152 struct kvm *kvm = vcpu->kvm; 10153 10154 if (mutex_lock_killable(&vcpu->mutex)) 10155 return; 10156 vcpu_load(vcpu); 10157 kvm_synchronize_tsc(vcpu, 0); 10158 vcpu_put(vcpu); 10159 10160 /* poll control enabled by default */ 10161 vcpu->arch.msr_kvm_poll_control = 1; 10162 10163 mutex_unlock(&vcpu->mutex); 10164 10165 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) 10166 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 10167 KVMCLOCK_SYNC_PERIOD); 10168 } 10169 10170 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 10171 { 10172 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache; 10173 int idx; 10174 10175 kvm_release_pfn(cache->pfn, cache->dirty, cache); 10176 10177 kvmclock_reset(vcpu); 10178 10179 static_call(kvm_x86_vcpu_free)(vcpu); 10180 10181 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 10182 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 10183 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu); 10184 kvm_free_guest_fpu(vcpu); 10185 10186 kvm_hv_vcpu_uninit(vcpu); 10187 kvm_pmu_destroy(vcpu); 10188 kfree(vcpu->arch.mce_banks); 10189 kvm_free_lapic(vcpu); 10190 idx = srcu_read_lock(&vcpu->kvm->srcu); 10191 kvm_mmu_destroy(vcpu); 10192 srcu_read_unlock(&vcpu->kvm->srcu, idx); 10193 free_page((unsigned long)vcpu->arch.pio_data); 10194 kvfree(vcpu->arch.cpuid_entries); 10195 if (!lapic_in_kernel(vcpu)) 10196 static_branch_dec(&kvm_has_noapic_vcpu); 10197 } 10198 10199 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 10200 { 10201 kvm_lapic_reset(vcpu, init_event); 10202 10203 vcpu->arch.hflags = 0; 10204 10205 vcpu->arch.smi_pending = 0; 10206 vcpu->arch.smi_count = 0; 10207 atomic_set(&vcpu->arch.nmi_queued, 0); 10208 vcpu->arch.nmi_pending = 0; 10209 vcpu->arch.nmi_injected = false; 10210 kvm_clear_interrupt_queue(vcpu); 10211 kvm_clear_exception_queue(vcpu); 10212 10213 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 10214 kvm_update_dr0123(vcpu); 10215 vcpu->arch.dr6 = DR6_ACTIVE_LOW; 10216 vcpu->arch.dr7 = DR7_FIXED_1; 10217 kvm_update_dr7(vcpu); 10218 10219 vcpu->arch.cr2 = 0; 10220 10221 kvm_make_request(KVM_REQ_EVENT, vcpu); 10222 vcpu->arch.apf.msr_en_val = 0; 10223 vcpu->arch.apf.msr_int_val = 0; 10224 vcpu->arch.st.msr_val = 0; 10225 10226 kvmclock_reset(vcpu); 10227 10228 kvm_clear_async_pf_completion_queue(vcpu); 10229 kvm_async_pf_hash_reset(vcpu); 10230 vcpu->arch.apf.halted = false; 10231 10232 if (vcpu->arch.guest_fpu && kvm_mpx_supported()) { 10233 void *mpx_state_buffer; 10234 10235 /* 10236 * To avoid have the INIT path from kvm_apic_has_events() that be 10237 * called with loaded FPU and does not let userspace fix the state. 10238 */ 10239 if (init_event) 10240 kvm_put_guest_fpu(vcpu); 10241 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 10242 XFEATURE_BNDREGS); 10243 if (mpx_state_buffer) 10244 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); 10245 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave, 10246 XFEATURE_BNDCSR); 10247 if (mpx_state_buffer) 10248 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); 10249 if (init_event) 10250 kvm_load_guest_fpu(vcpu); 10251 } 10252 10253 if (!init_event) { 10254 kvm_pmu_reset(vcpu); 10255 vcpu->arch.smbase = 0x30000; 10256 10257 vcpu->arch.msr_misc_features_enables = 0; 10258 10259 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 10260 } 10261 10262 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 10263 vcpu->arch.regs_avail = ~0; 10264 vcpu->arch.regs_dirty = ~0; 10265 10266 vcpu->arch.ia32_xss = 0; 10267 10268 static_call(kvm_x86_vcpu_reset)(vcpu, init_event); 10269 } 10270 10271 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 10272 { 10273 struct kvm_segment cs; 10274 10275 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 10276 cs.selector = vector << 8; 10277 cs.base = vector << 12; 10278 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 10279 kvm_rip_write(vcpu, 0); 10280 } 10281 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); 10282 10283 int kvm_arch_hardware_enable(void) 10284 { 10285 struct kvm *kvm; 10286 struct kvm_vcpu *vcpu; 10287 int i; 10288 int ret; 10289 u64 local_tsc; 10290 u64 max_tsc = 0; 10291 bool stable, backwards_tsc = false; 10292 10293 kvm_user_return_msr_cpu_online(); 10294 ret = static_call(kvm_x86_hardware_enable)(); 10295 if (ret != 0) 10296 return ret; 10297 10298 local_tsc = rdtsc(); 10299 stable = !kvm_check_tsc_unstable(); 10300 list_for_each_entry(kvm, &vm_list, vm_list) { 10301 kvm_for_each_vcpu(i, vcpu, kvm) { 10302 if (!stable && vcpu->cpu == smp_processor_id()) 10303 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 10304 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 10305 backwards_tsc = true; 10306 if (vcpu->arch.last_host_tsc > max_tsc) 10307 max_tsc = vcpu->arch.last_host_tsc; 10308 } 10309 } 10310 } 10311 10312 /* 10313 * Sometimes, even reliable TSCs go backwards. This happens on 10314 * platforms that reset TSC during suspend or hibernate actions, but 10315 * maintain synchronization. We must compensate. Fortunately, we can 10316 * detect that condition here, which happens early in CPU bringup, 10317 * before any KVM threads can be running. Unfortunately, we can't 10318 * bring the TSCs fully up to date with real time, as we aren't yet far 10319 * enough into CPU bringup that we know how much real time has actually 10320 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot 10321 * variables that haven't been updated yet. 10322 * 10323 * So we simply find the maximum observed TSC above, then record the 10324 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 10325 * the adjustment will be applied. Note that we accumulate 10326 * adjustments, in case multiple suspend cycles happen before some VCPU 10327 * gets a chance to run again. In the event that no KVM threads get a 10328 * chance to run, we will miss the entire elapsed period, as we'll have 10329 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 10330 * loose cycle time. This isn't too big a deal, since the loss will be 10331 * uniform across all VCPUs (not to mention the scenario is extremely 10332 * unlikely). It is possible that a second hibernate recovery happens 10333 * much faster than a first, causing the observed TSC here to be 10334 * smaller; this would require additional padding adjustment, which is 10335 * why we set last_host_tsc to the local tsc observed here. 10336 * 10337 * N.B. - this code below runs only on platforms with reliable TSC, 10338 * as that is the only way backwards_tsc is set above. Also note 10339 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 10340 * have the same delta_cyc adjustment applied if backwards_tsc 10341 * is detected. Note further, this adjustment is only done once, 10342 * as we reset last_host_tsc on all VCPUs to stop this from being 10343 * called multiple times (one for each physical CPU bringup). 10344 * 10345 * Platforms with unreliable TSCs don't have to deal with this, they 10346 * will be compensated by the logic in vcpu_load, which sets the TSC to 10347 * catchup mode. This will catchup all VCPUs to real time, but cannot 10348 * guarantee that they stay in perfect synchronization. 10349 */ 10350 if (backwards_tsc) { 10351 u64 delta_cyc = max_tsc - local_tsc; 10352 list_for_each_entry(kvm, &vm_list, vm_list) { 10353 kvm->arch.backwards_tsc_observed = true; 10354 kvm_for_each_vcpu(i, vcpu, kvm) { 10355 vcpu->arch.tsc_offset_adjustment += delta_cyc; 10356 vcpu->arch.last_host_tsc = local_tsc; 10357 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 10358 } 10359 10360 /* 10361 * We have to disable TSC offset matching.. if you were 10362 * booting a VM while issuing an S4 host suspend.... 10363 * you may have some problem. Solving this issue is 10364 * left as an exercise to the reader. 10365 */ 10366 kvm->arch.last_tsc_nsec = 0; 10367 kvm->arch.last_tsc_write = 0; 10368 } 10369 10370 } 10371 return 0; 10372 } 10373 10374 void kvm_arch_hardware_disable(void) 10375 { 10376 static_call(kvm_x86_hardware_disable)(); 10377 drop_user_return_notifiers(); 10378 } 10379 10380 int kvm_arch_hardware_setup(void *opaque) 10381 { 10382 struct kvm_x86_init_ops *ops = opaque; 10383 int r; 10384 10385 rdmsrl_safe(MSR_EFER, &host_efer); 10386 10387 if (boot_cpu_has(X86_FEATURE_XSAVES)) 10388 rdmsrl(MSR_IA32_XSS, host_xss); 10389 10390 r = ops->hardware_setup(); 10391 if (r != 0) 10392 return r; 10393 10394 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); 10395 kvm_ops_static_call_update(); 10396 10397 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) 10398 supported_xss = 0; 10399 10400 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) 10401 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); 10402 #undef __kvm_cpu_cap_has 10403 10404 if (kvm_has_tsc_control) { 10405 /* 10406 * Make sure the user can only configure tsc_khz values that 10407 * fit into a signed integer. 10408 * A min value is not calculated because it will always 10409 * be 1 on all machines. 10410 */ 10411 u64 max = min(0x7fffffffULL, 10412 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 10413 kvm_max_guest_tsc_khz = max; 10414 10415 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 10416 } 10417 10418 kvm_init_msr_list(); 10419 return 0; 10420 } 10421 10422 void kvm_arch_hardware_unsetup(void) 10423 { 10424 static_call(kvm_x86_hardware_unsetup)(); 10425 } 10426 10427 int kvm_arch_check_processor_compat(void *opaque) 10428 { 10429 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 10430 struct kvm_x86_init_ops *ops = opaque; 10431 10432 WARN_ON(!irqs_disabled()); 10433 10434 if (__cr4_reserved_bits(cpu_has, c) != 10435 __cr4_reserved_bits(cpu_has, &boot_cpu_data)) 10436 return -EIO; 10437 10438 return ops->check_processor_compatibility(); 10439 } 10440 10441 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 10442 { 10443 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 10444 } 10445 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 10446 10447 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 10448 { 10449 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 10450 } 10451 10452 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); 10453 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); 10454 10455 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 10456 { 10457 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 10458 10459 vcpu->arch.l1tf_flush_l1d = true; 10460 if (pmu->version && unlikely(pmu->event_count)) { 10461 pmu->need_cleanup = true; 10462 kvm_make_request(KVM_REQ_PMU, vcpu); 10463 } 10464 static_call(kvm_x86_sched_in)(vcpu, cpu); 10465 } 10466 10467 void kvm_arch_free_vm(struct kvm *kvm) 10468 { 10469 kfree(to_kvm_hv(kvm)->hv_pa_pg); 10470 vfree(kvm); 10471 } 10472 10473 10474 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 10475 { 10476 if (type) 10477 return -EINVAL; 10478 10479 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 10480 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 10481 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 10482 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages); 10483 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 10484 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 10485 10486 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 10487 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 10488 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 10489 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 10490 &kvm->arch.irq_sources_bitmap); 10491 10492 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 10493 mutex_init(&kvm->arch.apic_map_lock); 10494 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 10495 10496 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); 10497 pvclock_update_vm_gtod_copy(kvm); 10498 10499 kvm->arch.guest_can_read_msr_platform_info = true; 10500 10501 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 10502 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 10503 10504 kvm_hv_init_vm(kvm); 10505 kvm_page_track_init(kvm); 10506 kvm_mmu_init_vm(kvm); 10507 10508 return static_call(kvm_x86_vm_init)(kvm); 10509 } 10510 10511 int kvm_arch_post_init_vm(struct kvm *kvm) 10512 { 10513 return kvm_mmu_post_init_vm(kvm); 10514 } 10515 10516 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 10517 { 10518 vcpu_load(vcpu); 10519 kvm_mmu_unload(vcpu); 10520 vcpu_put(vcpu); 10521 } 10522 10523 static void kvm_free_vcpus(struct kvm *kvm) 10524 { 10525 unsigned int i; 10526 struct kvm_vcpu *vcpu; 10527 10528 /* 10529 * Unpin any mmu pages first. 10530 */ 10531 kvm_for_each_vcpu(i, vcpu, kvm) { 10532 kvm_clear_async_pf_completion_queue(vcpu); 10533 kvm_unload_vcpu_mmu(vcpu); 10534 } 10535 kvm_for_each_vcpu(i, vcpu, kvm) 10536 kvm_vcpu_destroy(vcpu); 10537 10538 mutex_lock(&kvm->lock); 10539 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 10540 kvm->vcpus[i] = NULL; 10541 10542 atomic_set(&kvm->online_vcpus, 0); 10543 mutex_unlock(&kvm->lock); 10544 } 10545 10546 void kvm_arch_sync_events(struct kvm *kvm) 10547 { 10548 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 10549 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 10550 kvm_free_pit(kvm); 10551 } 10552 10553 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) 10554 10555 /** 10556 * __x86_set_memory_region: Setup KVM internal memory slot 10557 * 10558 * @kvm: the kvm pointer to the VM. 10559 * @id: the slot ID to setup. 10560 * @gpa: the GPA to install the slot (unused when @size == 0). 10561 * @size: the size of the slot. Set to zero to uninstall a slot. 10562 * 10563 * This function helps to setup a KVM internal memory slot. Specify 10564 * @size > 0 to install a new slot, while @size == 0 to uninstall a 10565 * slot. The return code can be one of the following: 10566 * 10567 * HVA: on success (uninstall will return a bogus HVA) 10568 * -errno: on error 10569 * 10570 * The caller should always use IS_ERR() to check the return value 10571 * before use. Note, the KVM internal memory slots are guaranteed to 10572 * remain valid and unchanged until the VM is destroyed, i.e., the 10573 * GPA->HVA translation will not change. However, the HVA is a user 10574 * address, i.e. its accessibility is not guaranteed, and must be 10575 * accessed via __copy_{to,from}_user(). 10576 */ 10577 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, 10578 u32 size) 10579 { 10580 int i, r; 10581 unsigned long hva, old_npages; 10582 struct kvm_memslots *slots = kvm_memslots(kvm); 10583 struct kvm_memory_slot *slot; 10584 10585 /* Called with kvm->slots_lock held. */ 10586 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 10587 return ERR_PTR_USR(-EINVAL); 10588 10589 slot = id_to_memslot(slots, id); 10590 if (size) { 10591 if (slot && slot->npages) 10592 return ERR_PTR_USR(-EEXIST); 10593 10594 /* 10595 * MAP_SHARED to prevent internal slot pages from being moved 10596 * by fork()/COW. 10597 */ 10598 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 10599 MAP_SHARED | MAP_ANONYMOUS, 0); 10600 if (IS_ERR((void *)hva)) 10601 return (void __user *)hva; 10602 } else { 10603 if (!slot || !slot->npages) 10604 return 0; 10605 10606 old_npages = slot->npages; 10607 hva = slot->userspace_addr; 10608 } 10609 10610 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 10611 struct kvm_userspace_memory_region m; 10612 10613 m.slot = id | (i << 16); 10614 m.flags = 0; 10615 m.guest_phys_addr = gpa; 10616 m.userspace_addr = hva; 10617 m.memory_size = size; 10618 r = __kvm_set_memory_region(kvm, &m); 10619 if (r < 0) 10620 return ERR_PTR_USR(r); 10621 } 10622 10623 if (!size) 10624 vm_munmap(hva, old_npages * PAGE_SIZE); 10625 10626 return (void __user *)hva; 10627 } 10628 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 10629 10630 void kvm_arch_pre_destroy_vm(struct kvm *kvm) 10631 { 10632 kvm_mmu_pre_destroy_vm(kvm); 10633 } 10634 10635 void kvm_arch_destroy_vm(struct kvm *kvm) 10636 { 10637 u32 i; 10638 10639 if (current->mm == kvm->mm) { 10640 /* 10641 * Free memory regions allocated on behalf of userspace, 10642 * unless the the memory map has changed due to process exit 10643 * or fd copying. 10644 */ 10645 mutex_lock(&kvm->slots_lock); 10646 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 10647 0, 0); 10648 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 10649 0, 0); 10650 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 10651 mutex_unlock(&kvm->slots_lock); 10652 } 10653 static_call_cond(kvm_x86_vm_destroy)(kvm); 10654 for (i = 0; i < kvm->arch.msr_filter.count; i++) 10655 kfree(kvm->arch.msr_filter.ranges[i].bitmap); 10656 kvm_pic_destroy(kvm); 10657 kvm_ioapic_destroy(kvm); 10658 kvm_free_vcpus(kvm); 10659 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 10660 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); 10661 kvm_mmu_uninit_vm(kvm); 10662 kvm_page_track_cleanup(kvm); 10663 kvm_xen_destroy_vm(kvm); 10664 kvm_hv_destroy_vm(kvm); 10665 } 10666 10667 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) 10668 { 10669 int i; 10670 10671 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 10672 kvfree(slot->arch.rmap[i]); 10673 slot->arch.rmap[i] = NULL; 10674 10675 if (i == 0) 10676 continue; 10677 10678 kvfree(slot->arch.lpage_info[i - 1]); 10679 slot->arch.lpage_info[i - 1] = NULL; 10680 } 10681 10682 kvm_page_track_free_memslot(slot); 10683 } 10684 10685 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot, 10686 unsigned long npages) 10687 { 10688 int i; 10689 10690 /* 10691 * Clear out the previous array pointers for the KVM_MR_MOVE case. The 10692 * old arrays will be freed by __kvm_set_memory_region() if installing 10693 * the new memslot is successful. 10694 */ 10695 memset(&slot->arch, 0, sizeof(slot->arch)); 10696 10697 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 10698 struct kvm_lpage_info *linfo; 10699 unsigned long ugfn; 10700 int lpages; 10701 int level = i + 1; 10702 10703 lpages = gfn_to_index(slot->base_gfn + npages - 1, 10704 slot->base_gfn, level) + 1; 10705 10706 slot->arch.rmap[i] = 10707 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]), 10708 GFP_KERNEL_ACCOUNT); 10709 if (!slot->arch.rmap[i]) 10710 goto out_free; 10711 if (i == 0) 10712 continue; 10713 10714 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 10715 if (!linfo) 10716 goto out_free; 10717 10718 slot->arch.lpage_info[i - 1] = linfo; 10719 10720 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 10721 linfo[0].disallow_lpage = 1; 10722 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 10723 linfo[lpages - 1].disallow_lpage = 1; 10724 ugfn = slot->userspace_addr >> PAGE_SHIFT; 10725 /* 10726 * If the gfn and userspace address are not aligned wrt each 10727 * other, disable large page support for this slot. 10728 */ 10729 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { 10730 unsigned long j; 10731 10732 for (j = 0; j < lpages; ++j) 10733 linfo[j].disallow_lpage = 1; 10734 } 10735 } 10736 10737 if (kvm_page_track_create_memslot(slot, npages)) 10738 goto out_free; 10739 10740 return 0; 10741 10742 out_free: 10743 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 10744 kvfree(slot->arch.rmap[i]); 10745 slot->arch.rmap[i] = NULL; 10746 if (i == 0) 10747 continue; 10748 10749 kvfree(slot->arch.lpage_info[i - 1]); 10750 slot->arch.lpage_info[i - 1] = NULL; 10751 } 10752 return -ENOMEM; 10753 } 10754 10755 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 10756 { 10757 struct kvm_vcpu *vcpu; 10758 int i; 10759 10760 /* 10761 * memslots->generation has been incremented. 10762 * mmio generation may have reached its maximum value. 10763 */ 10764 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 10765 10766 /* Force re-initialization of steal_time cache */ 10767 kvm_for_each_vcpu(i, vcpu, kvm) 10768 kvm_vcpu_kick(vcpu); 10769 } 10770 10771 int kvm_arch_prepare_memory_region(struct kvm *kvm, 10772 struct kvm_memory_slot *memslot, 10773 const struct kvm_userspace_memory_region *mem, 10774 enum kvm_mr_change change) 10775 { 10776 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) 10777 return kvm_alloc_memslot_metadata(memslot, 10778 mem->memory_size >> PAGE_SHIFT); 10779 return 0; 10780 } 10781 10782 10783 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) 10784 { 10785 struct kvm_arch *ka = &kvm->arch; 10786 10787 if (!kvm_x86_ops.cpu_dirty_log_size) 10788 return; 10789 10790 if ((enable && ++ka->cpu_dirty_logging_count == 1) || 10791 (!enable && --ka->cpu_dirty_logging_count == 0)) 10792 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); 10793 10794 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); 10795 } 10796 10797 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 10798 struct kvm_memory_slot *old, 10799 struct kvm_memory_slot *new, 10800 enum kvm_mr_change change) 10801 { 10802 bool log_dirty_pages = new->flags & KVM_MEM_LOG_DIRTY_PAGES; 10803 10804 /* 10805 * Update CPU dirty logging if dirty logging is being toggled. This 10806 * applies to all operations. 10807 */ 10808 if ((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES) 10809 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); 10810 10811 /* 10812 * Nothing more to do for RO slots (which can't be dirtied and can't be 10813 * made writable) or CREATE/MOVE/DELETE of a slot. 10814 * 10815 * For a memslot with dirty logging disabled: 10816 * CREATE: No dirty mappings will already exist. 10817 * MOVE/DELETE: The old mappings will already have been cleaned up by 10818 * kvm_arch_flush_shadow_memslot() 10819 * 10820 * For a memslot with dirty logging enabled: 10821 * CREATE: No shadow pages exist, thus nothing to write-protect 10822 * and no dirty bits to clear. 10823 * MOVE/DELETE: The old mappings will already have been cleaned up by 10824 * kvm_arch_flush_shadow_memslot(). 10825 */ 10826 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY)) 10827 return; 10828 10829 /* 10830 * READONLY and non-flags changes were filtered out above, and the only 10831 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty 10832 * logging isn't being toggled on or off. 10833 */ 10834 if (WARN_ON_ONCE(!((old->flags ^ new->flags) & KVM_MEM_LOG_DIRTY_PAGES))) 10835 return; 10836 10837 if (!log_dirty_pages) { 10838 /* 10839 * Dirty logging tracks sptes in 4k granularity, meaning that 10840 * large sptes have to be split. If live migration succeeds, 10841 * the guest in the source machine will be destroyed and large 10842 * sptes will be created in the destination. However, if the 10843 * guest continues to run in the source machine (for example if 10844 * live migration fails), small sptes will remain around and 10845 * cause bad performance. 10846 * 10847 * Scan sptes if dirty logging has been stopped, dropping those 10848 * which can be collapsed into a single large-page spte. Later 10849 * page faults will create the large-page sptes. 10850 */ 10851 kvm_mmu_zap_collapsible_sptes(kvm, new); 10852 } else { 10853 /* By default, write-protect everything to log writes. */ 10854 int level = PG_LEVEL_4K; 10855 10856 if (kvm_x86_ops.cpu_dirty_log_size) { 10857 /* 10858 * Clear all dirty bits, unless pages are treated as 10859 * dirty from the get-go. 10860 */ 10861 if (!kvm_dirty_log_manual_protect_and_init_set(kvm)) 10862 kvm_mmu_slot_leaf_clear_dirty(kvm, new); 10863 10864 /* 10865 * Write-protect large pages on write so that dirty 10866 * logging happens at 4k granularity. No need to 10867 * write-protect small SPTEs since write accesses are 10868 * logged by the CPU via dirty bits. 10869 */ 10870 level = PG_LEVEL_2M; 10871 } else if (kvm_dirty_log_manual_protect_and_init_set(kvm)) { 10872 /* 10873 * If we're with initial-all-set, we don't need 10874 * to write protect any small page because 10875 * they're reported as dirty already. However 10876 * we still need to write-protect huge pages 10877 * so that the page split can happen lazily on 10878 * the first write to the huge page. 10879 */ 10880 level = PG_LEVEL_2M; 10881 } 10882 kvm_mmu_slot_remove_write_access(kvm, new, level); 10883 } 10884 } 10885 10886 void kvm_arch_commit_memory_region(struct kvm *kvm, 10887 const struct kvm_userspace_memory_region *mem, 10888 struct kvm_memory_slot *old, 10889 const struct kvm_memory_slot *new, 10890 enum kvm_mr_change change) 10891 { 10892 if (!kvm->arch.n_requested_mmu_pages) 10893 kvm_mmu_change_mmu_pages(kvm, 10894 kvm_mmu_calculate_default_mmu_pages(kvm)); 10895 10896 /* 10897 * FIXME: const-ify all uses of struct kvm_memory_slot. 10898 */ 10899 kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change); 10900 10901 /* Free the arrays associated with the old memslot. */ 10902 if (change == KVM_MR_MOVE) 10903 kvm_arch_free_memslot(kvm, old); 10904 } 10905 10906 void kvm_arch_flush_shadow_all(struct kvm *kvm) 10907 { 10908 kvm_mmu_zap_all(kvm); 10909 } 10910 10911 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 10912 struct kvm_memory_slot *slot) 10913 { 10914 kvm_page_track_flush_slot(kvm, slot); 10915 } 10916 10917 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 10918 { 10919 return (is_guest_mode(vcpu) && 10920 kvm_x86_ops.guest_apic_has_interrupt && 10921 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); 10922 } 10923 10924 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 10925 { 10926 if (!list_empty_careful(&vcpu->async_pf.done)) 10927 return true; 10928 10929 if (kvm_apic_has_events(vcpu)) 10930 return true; 10931 10932 if (vcpu->arch.pv.pv_unhalted) 10933 return true; 10934 10935 if (vcpu->arch.exception.pending) 10936 return true; 10937 10938 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 10939 (vcpu->arch.nmi_pending && 10940 static_call(kvm_x86_nmi_allowed)(vcpu, false))) 10941 return true; 10942 10943 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 10944 (vcpu->arch.smi_pending && 10945 static_call(kvm_x86_smi_allowed)(vcpu, false))) 10946 return true; 10947 10948 if (kvm_arch_interrupt_allowed(vcpu) && 10949 (kvm_cpu_has_interrupt(vcpu) || 10950 kvm_guest_apic_has_interrupt(vcpu))) 10951 return true; 10952 10953 if (kvm_hv_has_stimer_pending(vcpu)) 10954 return true; 10955 10956 if (is_guest_mode(vcpu) && 10957 kvm_x86_ops.nested_ops->hv_timer_pending && 10958 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) 10959 return true; 10960 10961 return false; 10962 } 10963 10964 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 10965 { 10966 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 10967 } 10968 10969 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) 10970 { 10971 if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) 10972 return true; 10973 10974 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 10975 kvm_test_request(KVM_REQ_SMI, vcpu) || 10976 kvm_test_request(KVM_REQ_EVENT, vcpu)) 10977 return true; 10978 10979 if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) 10980 return true; 10981 10982 return false; 10983 } 10984 10985 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 10986 { 10987 return vcpu->arch.preempted_in_kernel; 10988 } 10989 10990 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 10991 { 10992 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 10993 } 10994 10995 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 10996 { 10997 return static_call(kvm_x86_interrupt_allowed)(vcpu, false); 10998 } 10999 11000 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 11001 { 11002 /* Can't read the RIP when guest state is protected, just return 0 */ 11003 if (vcpu->arch.guest_state_protected) 11004 return 0; 11005 11006 if (is_64_bit_mode(vcpu)) 11007 return kvm_rip_read(vcpu); 11008 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 11009 kvm_rip_read(vcpu)); 11010 } 11011 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 11012 11013 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 11014 { 11015 return kvm_get_linear_rip(vcpu) == linear_rip; 11016 } 11017 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 11018 11019 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 11020 { 11021 unsigned long rflags; 11022 11023 rflags = static_call(kvm_x86_get_rflags)(vcpu); 11024 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 11025 rflags &= ~X86_EFLAGS_TF; 11026 return rflags; 11027 } 11028 EXPORT_SYMBOL_GPL(kvm_get_rflags); 11029 11030 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 11031 { 11032 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 11033 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 11034 rflags |= X86_EFLAGS_TF; 11035 static_call(kvm_x86_set_rflags)(vcpu, rflags); 11036 } 11037 11038 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 11039 { 11040 __kvm_set_rflags(vcpu, rflags); 11041 kvm_make_request(KVM_REQ_EVENT, vcpu); 11042 } 11043 EXPORT_SYMBOL_GPL(kvm_set_rflags); 11044 11045 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 11046 { 11047 int r; 11048 11049 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) || 11050 work->wakeup_all) 11051 return; 11052 11053 r = kvm_mmu_reload(vcpu); 11054 if (unlikely(r)) 11055 return; 11056 11057 if (!vcpu->arch.mmu->direct_map && 11058 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu)) 11059 return; 11060 11061 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true); 11062 } 11063 11064 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 11065 { 11066 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); 11067 11068 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 11069 } 11070 11071 static inline u32 kvm_async_pf_next_probe(u32 key) 11072 { 11073 return (key + 1) & (ASYNC_PF_PER_VCPU - 1); 11074 } 11075 11076 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11077 { 11078 u32 key = kvm_async_pf_hash_fn(gfn); 11079 11080 while (vcpu->arch.apf.gfns[key] != ~0) 11081 key = kvm_async_pf_next_probe(key); 11082 11083 vcpu->arch.apf.gfns[key] = gfn; 11084 } 11085 11086 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 11087 { 11088 int i; 11089 u32 key = kvm_async_pf_hash_fn(gfn); 11090 11091 for (i = 0; i < ASYNC_PF_PER_VCPU && 11092 (vcpu->arch.apf.gfns[key] != gfn && 11093 vcpu->arch.apf.gfns[key] != ~0); i++) 11094 key = kvm_async_pf_next_probe(key); 11095 11096 return key; 11097 } 11098 11099 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11100 { 11101 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 11102 } 11103 11104 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 11105 { 11106 u32 i, j, k; 11107 11108 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 11109 11110 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) 11111 return; 11112 11113 while (true) { 11114 vcpu->arch.apf.gfns[i] = ~0; 11115 do { 11116 j = kvm_async_pf_next_probe(j); 11117 if (vcpu->arch.apf.gfns[j] == ~0) 11118 return; 11119 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 11120 /* 11121 * k lies cyclically in ]i,j] 11122 * | i.k.j | 11123 * |....j i.k.| or |.k..j i...| 11124 */ 11125 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 11126 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 11127 i = j; 11128 } 11129 } 11130 11131 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) 11132 { 11133 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; 11134 11135 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, 11136 sizeof(reason)); 11137 } 11138 11139 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) 11140 { 11141 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 11142 11143 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 11144 &token, offset, sizeof(token)); 11145 } 11146 11147 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) 11148 { 11149 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 11150 u32 val; 11151 11152 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 11153 &val, offset, sizeof(val))) 11154 return false; 11155 11156 return !val; 11157 } 11158 11159 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) 11160 { 11161 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) 11162 return false; 11163 11164 if (!kvm_pv_async_pf_enabled(vcpu) || 11165 (vcpu->arch.apf.send_user_only && static_call(kvm_x86_get_cpl)(vcpu) == 0)) 11166 return false; 11167 11168 return true; 11169 } 11170 11171 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) 11172 { 11173 if (unlikely(!lapic_in_kernel(vcpu) || 11174 kvm_event_needs_reinjection(vcpu) || 11175 vcpu->arch.exception.pending)) 11176 return false; 11177 11178 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) 11179 return false; 11180 11181 /* 11182 * If interrupts are off we cannot even use an artificial 11183 * halt state. 11184 */ 11185 return kvm_arch_interrupt_allowed(vcpu); 11186 } 11187 11188 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 11189 struct kvm_async_pf *work) 11190 { 11191 struct x86_exception fault; 11192 11193 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); 11194 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 11195 11196 if (kvm_can_deliver_async_pf(vcpu) && 11197 !apf_put_user_notpresent(vcpu)) { 11198 fault.vector = PF_VECTOR; 11199 fault.error_code_valid = true; 11200 fault.error_code = 0; 11201 fault.nested_page_fault = false; 11202 fault.address = work->arch.token; 11203 fault.async_page_fault = true; 11204 kvm_inject_page_fault(vcpu, &fault); 11205 return true; 11206 } else { 11207 /* 11208 * It is not possible to deliver a paravirtualized asynchronous 11209 * page fault, but putting the guest in an artificial halt state 11210 * can be beneficial nevertheless: if an interrupt arrives, we 11211 * can deliver it timely and perhaps the guest will schedule 11212 * another process. When the instruction that triggered a page 11213 * fault is retried, hopefully the page will be ready in the host. 11214 */ 11215 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 11216 return false; 11217 } 11218 } 11219 11220 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 11221 struct kvm_async_pf *work) 11222 { 11223 struct kvm_lapic_irq irq = { 11224 .delivery_mode = APIC_DM_FIXED, 11225 .vector = vcpu->arch.apf.vec 11226 }; 11227 11228 if (work->wakeup_all) 11229 work->arch.token = ~0; /* broadcast wakeup */ 11230 else 11231 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 11232 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); 11233 11234 if ((work->wakeup_all || work->notpresent_injected) && 11235 kvm_pv_async_pf_enabled(vcpu) && 11236 !apf_put_user_ready(vcpu, work->arch.token)) { 11237 vcpu->arch.apf.pageready_pending = true; 11238 kvm_apic_set_irq(vcpu, &irq, NULL); 11239 } 11240 11241 vcpu->arch.apf.halted = false; 11242 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 11243 } 11244 11245 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) 11246 { 11247 kvm_make_request(KVM_REQ_APF_READY, vcpu); 11248 if (!vcpu->arch.apf.pageready_pending) 11249 kvm_vcpu_kick(vcpu); 11250 } 11251 11252 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) 11253 { 11254 if (!kvm_pv_async_pf_enabled(vcpu)) 11255 return true; 11256 else 11257 return apf_pageready_slot_free(vcpu); 11258 } 11259 11260 void kvm_arch_start_assignment(struct kvm *kvm) 11261 { 11262 atomic_inc(&kvm->arch.assigned_device_count); 11263 } 11264 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 11265 11266 void kvm_arch_end_assignment(struct kvm *kvm) 11267 { 11268 atomic_dec(&kvm->arch.assigned_device_count); 11269 } 11270 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 11271 11272 bool kvm_arch_has_assigned_device(struct kvm *kvm) 11273 { 11274 return atomic_read(&kvm->arch.assigned_device_count); 11275 } 11276 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 11277 11278 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 11279 { 11280 atomic_inc(&kvm->arch.noncoherent_dma_count); 11281 } 11282 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 11283 11284 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 11285 { 11286 atomic_dec(&kvm->arch.noncoherent_dma_count); 11287 } 11288 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 11289 11290 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 11291 { 11292 return atomic_read(&kvm->arch.noncoherent_dma_count); 11293 } 11294 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 11295 11296 bool kvm_arch_has_irq_bypass(void) 11297 { 11298 return true; 11299 } 11300 11301 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 11302 struct irq_bypass_producer *prod) 11303 { 11304 struct kvm_kernel_irqfd *irqfd = 11305 container_of(cons, struct kvm_kernel_irqfd, consumer); 11306 int ret; 11307 11308 irqfd->producer = prod; 11309 kvm_arch_start_assignment(irqfd->kvm); 11310 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, 11311 prod->irq, irqfd->gsi, 1); 11312 11313 if (ret) 11314 kvm_arch_end_assignment(irqfd->kvm); 11315 11316 return ret; 11317 } 11318 11319 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 11320 struct irq_bypass_producer *prod) 11321 { 11322 int ret; 11323 struct kvm_kernel_irqfd *irqfd = 11324 container_of(cons, struct kvm_kernel_irqfd, consumer); 11325 11326 WARN_ON(irqfd->producer != prod); 11327 irqfd->producer = NULL; 11328 11329 /* 11330 * When producer of consumer is unregistered, we change back to 11331 * remapped mode, so we can re-use the current implementation 11332 * when the irq is masked/disabled or the consumer side (KVM 11333 * int this case doesn't want to receive the interrupts. 11334 */ 11335 ret = static_call(kvm_x86_update_pi_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); 11336 if (ret) 11337 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 11338 " fails: %d\n", irqfd->consumer.token, ret); 11339 11340 kvm_arch_end_assignment(irqfd->kvm); 11341 } 11342 11343 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 11344 uint32_t guest_irq, bool set) 11345 { 11346 return static_call(kvm_x86_update_pi_irte)(kvm, host_irq, guest_irq, set); 11347 } 11348 11349 bool kvm_vector_hashing_enabled(void) 11350 { 11351 return vector_hashing; 11352 } 11353 11354 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) 11355 { 11356 return (vcpu->arch.msr_kvm_poll_control & 1) == 0; 11357 } 11358 EXPORT_SYMBOL_GPL(kvm_arch_no_poll); 11359 11360 11361 int kvm_spec_ctrl_test_value(u64 value) 11362 { 11363 /* 11364 * test that setting IA32_SPEC_CTRL to given value 11365 * is allowed by the host processor 11366 */ 11367 11368 u64 saved_value; 11369 unsigned long flags; 11370 int ret = 0; 11371 11372 local_irq_save(flags); 11373 11374 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) 11375 ret = 1; 11376 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) 11377 ret = 1; 11378 else 11379 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); 11380 11381 local_irq_restore(flags); 11382 11383 return ret; 11384 } 11385 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); 11386 11387 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) 11388 { 11389 struct x86_exception fault; 11390 u32 access = error_code & 11391 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); 11392 11393 if (!(error_code & PFERR_PRESENT_MASK) || 11394 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) { 11395 /* 11396 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page 11397 * tables probably do not match the TLB. Just proceed 11398 * with the error code that the processor gave. 11399 */ 11400 fault.vector = PF_VECTOR; 11401 fault.error_code_valid = true; 11402 fault.error_code = error_code; 11403 fault.nested_page_fault = false; 11404 fault.address = gva; 11405 } 11406 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); 11407 } 11408 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); 11409 11410 /* 11411 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns 11412 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value 11413 * indicates whether exit to userspace is needed. 11414 */ 11415 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 11416 struct x86_exception *e) 11417 { 11418 if (r == X86EMUL_PROPAGATE_FAULT) { 11419 kvm_inject_emulated_page_fault(vcpu, e); 11420 return 1; 11421 } 11422 11423 /* 11424 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED 11425 * while handling a VMX instruction KVM could've handled the request 11426 * correctly by exiting to userspace and performing I/O but there 11427 * doesn't seem to be a real use-case behind such requests, just return 11428 * KVM_EXIT_INTERNAL_ERROR for now. 11429 */ 11430 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 11431 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 11432 vcpu->run->internal.ndata = 0; 11433 11434 return 0; 11435 } 11436 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); 11437 11438 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) 11439 { 11440 bool pcid_enabled; 11441 struct x86_exception e; 11442 unsigned i; 11443 unsigned long roots_to_free = 0; 11444 struct { 11445 u64 pcid; 11446 u64 gla; 11447 } operand; 11448 int r; 11449 11450 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 11451 if (r != X86EMUL_CONTINUE) 11452 return kvm_handle_memory_failure(vcpu, r, &e); 11453 11454 if (operand.pcid >> 12 != 0) { 11455 kvm_inject_gp(vcpu, 0); 11456 return 1; 11457 } 11458 11459 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 11460 11461 switch (type) { 11462 case INVPCID_TYPE_INDIV_ADDR: 11463 if ((!pcid_enabled && (operand.pcid != 0)) || 11464 is_noncanonical_address(operand.gla, vcpu)) { 11465 kvm_inject_gp(vcpu, 0); 11466 return 1; 11467 } 11468 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 11469 return kvm_skip_emulated_instruction(vcpu); 11470 11471 case INVPCID_TYPE_SINGLE_CTXT: 11472 if (!pcid_enabled && (operand.pcid != 0)) { 11473 kvm_inject_gp(vcpu, 0); 11474 return 1; 11475 } 11476 11477 if (kvm_get_active_pcid(vcpu) == operand.pcid) { 11478 kvm_mmu_sync_roots(vcpu); 11479 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 11480 } 11481 11482 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 11483 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd) 11484 == operand.pcid) 11485 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 11486 11487 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); 11488 /* 11489 * If neither the current cr3 nor any of the prev_roots use the 11490 * given PCID, then nothing needs to be done here because a 11491 * resync will happen anyway before switching to any other CR3. 11492 */ 11493 11494 return kvm_skip_emulated_instruction(vcpu); 11495 11496 case INVPCID_TYPE_ALL_NON_GLOBAL: 11497 /* 11498 * Currently, KVM doesn't mark global entries in the shadow 11499 * page tables, so a non-global flush just degenerates to a 11500 * global flush. If needed, we could optimize this later by 11501 * keeping track of global entries in shadow page tables. 11502 */ 11503 11504 fallthrough; 11505 case INVPCID_TYPE_ALL_INCL_GLOBAL: 11506 kvm_mmu_unload(vcpu); 11507 return kvm_skip_emulated_instruction(vcpu); 11508 11509 default: 11510 BUG(); /* We have already checked above that type <= 3 */ 11511 } 11512 } 11513 EXPORT_SYMBOL_GPL(kvm_handle_invpcid); 11514 11515 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) 11516 { 11517 struct kvm_run *run = vcpu->run; 11518 struct kvm_mmio_fragment *frag; 11519 unsigned int len; 11520 11521 BUG_ON(!vcpu->mmio_needed); 11522 11523 /* Complete previous fragment */ 11524 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 11525 len = min(8u, frag->len); 11526 if (!vcpu->mmio_is_write) 11527 memcpy(frag->data, run->mmio.data, len); 11528 11529 if (frag->len <= 8) { 11530 /* Switch to the next fragment. */ 11531 frag++; 11532 vcpu->mmio_cur_fragment++; 11533 } else { 11534 /* Go forward to the next mmio piece. */ 11535 frag->data += len; 11536 frag->gpa += len; 11537 frag->len -= len; 11538 } 11539 11540 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 11541 vcpu->mmio_needed = 0; 11542 11543 // VMG change, at this point, we're always done 11544 // RIP has already been advanced 11545 return 1; 11546 } 11547 11548 // More MMIO is needed 11549 run->mmio.phys_addr = frag->gpa; 11550 run->mmio.len = min(8u, frag->len); 11551 run->mmio.is_write = vcpu->mmio_is_write; 11552 if (run->mmio.is_write) 11553 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 11554 run->exit_reason = KVM_EXIT_MMIO; 11555 11556 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 11557 11558 return 0; 11559 } 11560 11561 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 11562 void *data) 11563 { 11564 int handled; 11565 struct kvm_mmio_fragment *frag; 11566 11567 if (!data) 11568 return -EINVAL; 11569 11570 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); 11571 if (handled == bytes) 11572 return 1; 11573 11574 bytes -= handled; 11575 gpa += handled; 11576 data += handled; 11577 11578 /*TODO: Check if need to increment number of frags */ 11579 frag = vcpu->mmio_fragments; 11580 vcpu->mmio_nr_fragments = 1; 11581 frag->len = bytes; 11582 frag->gpa = gpa; 11583 frag->data = data; 11584 11585 vcpu->mmio_needed = 1; 11586 vcpu->mmio_cur_fragment = 0; 11587 11588 vcpu->run->mmio.phys_addr = gpa; 11589 vcpu->run->mmio.len = min(8u, frag->len); 11590 vcpu->run->mmio.is_write = 1; 11591 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 11592 vcpu->run->exit_reason = KVM_EXIT_MMIO; 11593 11594 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 11595 11596 return 0; 11597 } 11598 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); 11599 11600 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 11601 void *data) 11602 { 11603 int handled; 11604 struct kvm_mmio_fragment *frag; 11605 11606 if (!data) 11607 return -EINVAL; 11608 11609 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); 11610 if (handled == bytes) 11611 return 1; 11612 11613 bytes -= handled; 11614 gpa += handled; 11615 data += handled; 11616 11617 /*TODO: Check if need to increment number of frags */ 11618 frag = vcpu->mmio_fragments; 11619 vcpu->mmio_nr_fragments = 1; 11620 frag->len = bytes; 11621 frag->gpa = gpa; 11622 frag->data = data; 11623 11624 vcpu->mmio_needed = 1; 11625 vcpu->mmio_cur_fragment = 0; 11626 11627 vcpu->run->mmio.phys_addr = gpa; 11628 vcpu->run->mmio.len = min(8u, frag->len); 11629 vcpu->run->mmio.is_write = 0; 11630 vcpu->run->exit_reason = KVM_EXIT_MMIO; 11631 11632 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 11633 11634 return 0; 11635 } 11636 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); 11637 11638 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 11639 { 11640 memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data, 11641 vcpu->arch.pio.count * vcpu->arch.pio.size); 11642 vcpu->arch.pio.count = 0; 11643 11644 return 1; 11645 } 11646 11647 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 11648 unsigned int port, void *data, unsigned int count) 11649 { 11650 int ret; 11651 11652 ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port, 11653 data, count); 11654 if (ret) 11655 return ret; 11656 11657 vcpu->arch.pio.count = 0; 11658 11659 return 0; 11660 } 11661 11662 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 11663 unsigned int port, void *data, unsigned int count) 11664 { 11665 int ret; 11666 11667 ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port, 11668 data, count); 11669 if (ret) { 11670 vcpu->arch.pio.count = 0; 11671 } else { 11672 vcpu->arch.guest_ins_data = data; 11673 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; 11674 } 11675 11676 return 0; 11677 } 11678 11679 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 11680 unsigned int port, void *data, unsigned int count, 11681 int in) 11682 { 11683 return in ? kvm_sev_es_ins(vcpu, size, port, data, count) 11684 : kvm_sev_es_outs(vcpu, size, port, data, count); 11685 } 11686 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); 11687 11688 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); 11689 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 11690 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 11691 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 11692 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 11693 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 11694 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 11695 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 11696 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 11697 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 11698 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 11699 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); 11700 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 11701 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 11702 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 11703 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 11704 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); 11705 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 11706 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 11707 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 11708 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 11709 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); 11710 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request); 11711 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); 11712 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); 11713 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); 11714 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); 11715