1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "pmu.h" 31 #include "hyperv.h" 32 33 #include <linux/clocksource.h> 34 #include <linux/interrupt.h> 35 #include <linux/kvm.h> 36 #include <linux/fs.h> 37 #include <linux/vmalloc.h> 38 #include <linux/export.h> 39 #include <linux/moduleparam.h> 40 #include <linux/mman.h> 41 #include <linux/highmem.h> 42 #include <linux/iommu.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/cpufreq.h> 45 #include <linux/user-return-notifier.h> 46 #include <linux/srcu.h> 47 #include <linux/slab.h> 48 #include <linux/perf_event.h> 49 #include <linux/uaccess.h> 50 #include <linux/hash.h> 51 #include <linux/pci.h> 52 #include <linux/timekeeper_internal.h> 53 #include <linux/pvclock_gtod.h> 54 #include <linux/kvm_irqfd.h> 55 #include <linux/irqbypass.h> 56 #include <linux/sched/stat.h> 57 #include <linux/mem_encrypt.h> 58 59 #include <trace/events/kvm.h> 60 61 #include <asm/debugreg.h> 62 #include <asm/msr.h> 63 #include <asm/desc.h> 64 #include <asm/mce.h> 65 #include <linux/kernel_stat.h> 66 #include <asm/fpu/internal.h> /* Ugh! */ 67 #include <asm/pvclock.h> 68 #include <asm/div64.h> 69 #include <asm/irq_remapping.h> 70 #include <asm/mshyperv.h> 71 #include <asm/hypervisor.h> 72 73 #define CREATE_TRACE_POINTS 74 #include "trace.h" 75 76 #define MAX_IO_MSRS 256 77 #define KVM_MAX_MCE_BANKS 32 78 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 79 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 80 81 #define emul_to_vcpu(ctxt) \ 82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 83 84 /* EFER defaults: 85 * - enable syscall per default because its emulated by KVM 86 * - enable LME and LMA per default on 64 bit KVM 87 */ 88 #ifdef CONFIG_X86_64 89 static 90 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 91 #else 92 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 93 #endif 94 95 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 96 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 97 98 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 100 101 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 102 static void process_nmi(struct kvm_vcpu *vcpu); 103 static void enter_smm(struct kvm_vcpu *vcpu); 104 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 105 static void store_regs(struct kvm_vcpu *vcpu); 106 static int sync_regs(struct kvm_vcpu *vcpu); 107 108 struct kvm_x86_ops *kvm_x86_ops __read_mostly; 109 EXPORT_SYMBOL_GPL(kvm_x86_ops); 110 111 static bool __read_mostly ignore_msrs = 0; 112 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 113 114 static bool __read_mostly report_ignored_msrs = true; 115 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 116 117 unsigned int min_timer_period_us = 500; 118 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 119 120 static bool __read_mostly kvmclock_periodic_sync = true; 121 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 122 123 bool __read_mostly kvm_has_tsc_control; 124 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 125 u32 __read_mostly kvm_max_guest_tsc_khz; 126 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 127 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 128 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 129 u64 __read_mostly kvm_max_tsc_scaling_ratio; 130 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 131 u64 __read_mostly kvm_default_tsc_scaling_ratio; 132 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 133 134 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 135 static u32 __read_mostly tsc_tolerance_ppm = 250; 136 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 137 138 /* lapic timer advance (tscdeadline mode only) in nanoseconds */ 139 unsigned int __read_mostly lapic_timer_advance_ns = 0; 140 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 141 142 static bool __read_mostly vector_hashing = true; 143 module_param(vector_hashing, bool, S_IRUGO); 144 145 bool __read_mostly enable_vmware_backdoor = false; 146 module_param(enable_vmware_backdoor, bool, S_IRUGO); 147 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 148 149 static bool __read_mostly force_emulation_prefix = false; 150 module_param(force_emulation_prefix, bool, S_IRUGO); 151 152 #define KVM_NR_SHARED_MSRS 16 153 154 struct kvm_shared_msrs_global { 155 int nr; 156 u32 msrs[KVM_NR_SHARED_MSRS]; 157 }; 158 159 struct kvm_shared_msrs { 160 struct user_return_notifier urn; 161 bool registered; 162 struct kvm_shared_msr_values { 163 u64 host; 164 u64 curr; 165 } values[KVM_NR_SHARED_MSRS]; 166 }; 167 168 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 169 static struct kvm_shared_msrs __percpu *shared_msrs; 170 171 struct kvm_stats_debugfs_item debugfs_entries[] = { 172 { "pf_fixed", VCPU_STAT(pf_fixed) }, 173 { "pf_guest", VCPU_STAT(pf_guest) }, 174 { "tlb_flush", VCPU_STAT(tlb_flush) }, 175 { "invlpg", VCPU_STAT(invlpg) }, 176 { "exits", VCPU_STAT(exits) }, 177 { "io_exits", VCPU_STAT(io_exits) }, 178 { "mmio_exits", VCPU_STAT(mmio_exits) }, 179 { "signal_exits", VCPU_STAT(signal_exits) }, 180 { "irq_window", VCPU_STAT(irq_window_exits) }, 181 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 182 { "halt_exits", VCPU_STAT(halt_exits) }, 183 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 184 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 185 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, 186 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 187 { "hypercalls", VCPU_STAT(hypercalls) }, 188 { "request_irq", VCPU_STAT(request_irq_exits) }, 189 { "irq_exits", VCPU_STAT(irq_exits) }, 190 { "host_state_reload", VCPU_STAT(host_state_reload) }, 191 { "fpu_reload", VCPU_STAT(fpu_reload) }, 192 { "insn_emulation", VCPU_STAT(insn_emulation) }, 193 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 194 { "irq_injections", VCPU_STAT(irq_injections) }, 195 { "nmi_injections", VCPU_STAT(nmi_injections) }, 196 { "req_event", VCPU_STAT(req_event) }, 197 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 198 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 199 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 200 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 201 { "mmu_flooded", VM_STAT(mmu_flooded) }, 202 { "mmu_recycled", VM_STAT(mmu_recycled) }, 203 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 204 { "mmu_unsync", VM_STAT(mmu_unsync) }, 205 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 206 { "largepages", VM_STAT(lpages) }, 207 { "max_mmu_page_hash_collisions", 208 VM_STAT(max_mmu_page_hash_collisions) }, 209 { NULL } 210 }; 211 212 u64 __read_mostly host_xcr0; 213 214 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 215 216 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 217 { 218 int i; 219 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 220 vcpu->arch.apf.gfns[i] = ~0; 221 } 222 223 static void kvm_on_user_return(struct user_return_notifier *urn) 224 { 225 unsigned slot; 226 struct kvm_shared_msrs *locals 227 = container_of(urn, struct kvm_shared_msrs, urn); 228 struct kvm_shared_msr_values *values; 229 unsigned long flags; 230 231 /* 232 * Disabling irqs at this point since the following code could be 233 * interrupted and executed through kvm_arch_hardware_disable() 234 */ 235 local_irq_save(flags); 236 if (locals->registered) { 237 locals->registered = false; 238 user_return_notifier_unregister(urn); 239 } 240 local_irq_restore(flags); 241 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 242 values = &locals->values[slot]; 243 if (values->host != values->curr) { 244 wrmsrl(shared_msrs_global.msrs[slot], values->host); 245 values->curr = values->host; 246 } 247 } 248 } 249 250 static void shared_msr_update(unsigned slot, u32 msr) 251 { 252 u64 value; 253 unsigned int cpu = smp_processor_id(); 254 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 255 256 /* only read, and nobody should modify it at this time, 257 * so don't need lock */ 258 if (slot >= shared_msrs_global.nr) { 259 printk(KERN_ERR "kvm: invalid MSR slot!"); 260 return; 261 } 262 rdmsrl_safe(msr, &value); 263 smsr->values[slot].host = value; 264 smsr->values[slot].curr = value; 265 } 266 267 void kvm_define_shared_msr(unsigned slot, u32 msr) 268 { 269 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 270 shared_msrs_global.msrs[slot] = msr; 271 if (slot >= shared_msrs_global.nr) 272 shared_msrs_global.nr = slot + 1; 273 } 274 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 275 276 static void kvm_shared_msr_cpu_online(void) 277 { 278 unsigned i; 279 280 for (i = 0; i < shared_msrs_global.nr; ++i) 281 shared_msr_update(i, shared_msrs_global.msrs[i]); 282 } 283 284 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 285 { 286 unsigned int cpu = smp_processor_id(); 287 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 288 int err; 289 290 if (((value ^ smsr->values[slot].curr) & mask) == 0) 291 return 0; 292 smsr->values[slot].curr = value; 293 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 294 if (err) 295 return 1; 296 297 if (!smsr->registered) { 298 smsr->urn.on_user_return = kvm_on_user_return; 299 user_return_notifier_register(&smsr->urn); 300 smsr->registered = true; 301 } 302 return 0; 303 } 304 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 305 306 static void drop_user_return_notifiers(void) 307 { 308 unsigned int cpu = smp_processor_id(); 309 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 310 311 if (smsr->registered) 312 kvm_on_user_return(&smsr->urn); 313 } 314 315 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 316 { 317 return vcpu->arch.apic_base; 318 } 319 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 320 321 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 322 { 323 u64 old_state = vcpu->arch.apic_base & 324 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 325 u64 new_state = msr_info->data & 326 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 327 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | 328 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 329 330 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE) 331 return 1; 332 if (!msr_info->host_initiated && 333 ((new_state == MSR_IA32_APICBASE_ENABLE && 334 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 335 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 336 old_state == 0))) 337 return 1; 338 339 kvm_lapic_set_base(vcpu, msr_info->data); 340 return 0; 341 } 342 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 343 344 asmlinkage __visible void kvm_spurious_fault(void) 345 { 346 /* Fault while not rebooting. We want the trace. */ 347 BUG(); 348 } 349 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 350 351 #define EXCPT_BENIGN 0 352 #define EXCPT_CONTRIBUTORY 1 353 #define EXCPT_PF 2 354 355 static int exception_class(int vector) 356 { 357 switch (vector) { 358 case PF_VECTOR: 359 return EXCPT_PF; 360 case DE_VECTOR: 361 case TS_VECTOR: 362 case NP_VECTOR: 363 case SS_VECTOR: 364 case GP_VECTOR: 365 return EXCPT_CONTRIBUTORY; 366 default: 367 break; 368 } 369 return EXCPT_BENIGN; 370 } 371 372 #define EXCPT_FAULT 0 373 #define EXCPT_TRAP 1 374 #define EXCPT_ABORT 2 375 #define EXCPT_INTERRUPT 3 376 377 static int exception_type(int vector) 378 { 379 unsigned int mask; 380 381 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 382 return EXCPT_INTERRUPT; 383 384 mask = 1 << vector; 385 386 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 387 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 388 return EXCPT_TRAP; 389 390 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 391 return EXCPT_ABORT; 392 393 /* Reserved exceptions will result in fault */ 394 return EXCPT_FAULT; 395 } 396 397 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 398 unsigned nr, bool has_error, u32 error_code, 399 bool reinject) 400 { 401 u32 prev_nr; 402 int class1, class2; 403 404 kvm_make_request(KVM_REQ_EVENT, vcpu); 405 406 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 407 queue: 408 if (has_error && !is_protmode(vcpu)) 409 has_error = false; 410 if (reinject) { 411 /* 412 * On vmentry, vcpu->arch.exception.pending is only 413 * true if an event injection was blocked by 414 * nested_run_pending. In that case, however, 415 * vcpu_enter_guest requests an immediate exit, 416 * and the guest shouldn't proceed far enough to 417 * need reinjection. 418 */ 419 WARN_ON_ONCE(vcpu->arch.exception.pending); 420 vcpu->arch.exception.injected = true; 421 } else { 422 vcpu->arch.exception.pending = true; 423 vcpu->arch.exception.injected = false; 424 } 425 vcpu->arch.exception.has_error_code = has_error; 426 vcpu->arch.exception.nr = nr; 427 vcpu->arch.exception.error_code = error_code; 428 return; 429 } 430 431 /* to check exception */ 432 prev_nr = vcpu->arch.exception.nr; 433 if (prev_nr == DF_VECTOR) { 434 /* triple fault -> shutdown */ 435 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 436 return; 437 } 438 class1 = exception_class(prev_nr); 439 class2 = exception_class(nr); 440 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 441 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 442 /* 443 * Generate double fault per SDM Table 5-5. Set 444 * exception.pending = true so that the double fault 445 * can trigger a nested vmexit. 446 */ 447 vcpu->arch.exception.pending = true; 448 vcpu->arch.exception.injected = false; 449 vcpu->arch.exception.has_error_code = true; 450 vcpu->arch.exception.nr = DF_VECTOR; 451 vcpu->arch.exception.error_code = 0; 452 } else 453 /* replace previous exception with a new one in a hope 454 that instruction re-execution will regenerate lost 455 exception */ 456 goto queue; 457 } 458 459 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 460 { 461 kvm_multiple_exception(vcpu, nr, false, 0, false); 462 } 463 EXPORT_SYMBOL_GPL(kvm_queue_exception); 464 465 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 466 { 467 kvm_multiple_exception(vcpu, nr, false, 0, true); 468 } 469 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 470 471 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 472 { 473 if (err) 474 kvm_inject_gp(vcpu, 0); 475 else 476 return kvm_skip_emulated_instruction(vcpu); 477 478 return 1; 479 } 480 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 481 482 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 483 { 484 ++vcpu->stat.pf_guest; 485 vcpu->arch.exception.nested_apf = 486 is_guest_mode(vcpu) && fault->async_page_fault; 487 if (vcpu->arch.exception.nested_apf) 488 vcpu->arch.apf.nested_apf_token = fault->address; 489 else 490 vcpu->arch.cr2 = fault->address; 491 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 492 } 493 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 494 495 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 496 { 497 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 498 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 499 else 500 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 501 502 return fault->nested_page_fault; 503 } 504 505 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 506 { 507 atomic_inc(&vcpu->arch.nmi_queued); 508 kvm_make_request(KVM_REQ_NMI, vcpu); 509 } 510 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 511 512 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 513 { 514 kvm_multiple_exception(vcpu, nr, true, error_code, false); 515 } 516 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 517 518 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 519 { 520 kvm_multiple_exception(vcpu, nr, true, error_code, true); 521 } 522 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 523 524 /* 525 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 526 * a #GP and return false. 527 */ 528 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 529 { 530 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 531 return true; 532 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 533 return false; 534 } 535 EXPORT_SYMBOL_GPL(kvm_require_cpl); 536 537 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 538 { 539 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 540 return true; 541 542 kvm_queue_exception(vcpu, UD_VECTOR); 543 return false; 544 } 545 EXPORT_SYMBOL_GPL(kvm_require_dr); 546 547 /* 548 * This function will be used to read from the physical memory of the currently 549 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 550 * can read from guest physical or from the guest's guest physical memory. 551 */ 552 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 553 gfn_t ngfn, void *data, int offset, int len, 554 u32 access) 555 { 556 struct x86_exception exception; 557 gfn_t real_gfn; 558 gpa_t ngpa; 559 560 ngpa = gfn_to_gpa(ngfn); 561 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 562 if (real_gfn == UNMAPPED_GVA) 563 return -EFAULT; 564 565 real_gfn = gpa_to_gfn(real_gfn); 566 567 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 568 } 569 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 570 571 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 572 void *data, int offset, int len, u32 access) 573 { 574 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 575 data, offset, len, access); 576 } 577 578 /* 579 * Load the pae pdptrs. Return true is they are all valid. 580 */ 581 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 582 { 583 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 584 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 585 int i; 586 int ret; 587 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 588 589 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 590 offset * sizeof(u64), sizeof(pdpte), 591 PFERR_USER_MASK|PFERR_WRITE_MASK); 592 if (ret < 0) { 593 ret = 0; 594 goto out; 595 } 596 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 597 if ((pdpte[i] & PT_PRESENT_MASK) && 598 (pdpte[i] & 599 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) { 600 ret = 0; 601 goto out; 602 } 603 } 604 ret = 1; 605 606 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 607 __set_bit(VCPU_EXREG_PDPTR, 608 (unsigned long *)&vcpu->arch.regs_avail); 609 __set_bit(VCPU_EXREG_PDPTR, 610 (unsigned long *)&vcpu->arch.regs_dirty); 611 out: 612 613 return ret; 614 } 615 EXPORT_SYMBOL_GPL(load_pdptrs); 616 617 bool pdptrs_changed(struct kvm_vcpu *vcpu) 618 { 619 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 620 bool changed = true; 621 int offset; 622 gfn_t gfn; 623 int r; 624 625 if (is_long_mode(vcpu) || !is_pae(vcpu)) 626 return false; 627 628 if (!test_bit(VCPU_EXREG_PDPTR, 629 (unsigned long *)&vcpu->arch.regs_avail)) 630 return true; 631 632 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; 633 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); 634 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 635 PFERR_USER_MASK | PFERR_WRITE_MASK); 636 if (r < 0) 637 goto out; 638 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 639 out: 640 641 return changed; 642 } 643 EXPORT_SYMBOL_GPL(pdptrs_changed); 644 645 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 646 { 647 unsigned long old_cr0 = kvm_read_cr0(vcpu); 648 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 649 650 cr0 |= X86_CR0_ET; 651 652 #ifdef CONFIG_X86_64 653 if (cr0 & 0xffffffff00000000UL) 654 return 1; 655 #endif 656 657 cr0 &= ~CR0_RESERVED_BITS; 658 659 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 660 return 1; 661 662 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 663 return 1; 664 665 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 666 #ifdef CONFIG_X86_64 667 if ((vcpu->arch.efer & EFER_LME)) { 668 int cs_db, cs_l; 669 670 if (!is_pae(vcpu)) 671 return 1; 672 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 673 if (cs_l) 674 return 1; 675 } else 676 #endif 677 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 678 kvm_read_cr3(vcpu))) 679 return 1; 680 } 681 682 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 683 return 1; 684 685 kvm_x86_ops->set_cr0(vcpu, cr0); 686 687 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 688 kvm_clear_async_pf_completion_queue(vcpu); 689 kvm_async_pf_hash_reset(vcpu); 690 } 691 692 if ((cr0 ^ old_cr0) & update_bits) 693 kvm_mmu_reset_context(vcpu); 694 695 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 696 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 697 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 698 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 699 700 return 0; 701 } 702 EXPORT_SYMBOL_GPL(kvm_set_cr0); 703 704 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 705 { 706 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 707 } 708 EXPORT_SYMBOL_GPL(kvm_lmsw); 709 710 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 711 { 712 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 713 !vcpu->guest_xcr0_loaded) { 714 /* kvm_set_xcr() also depends on this */ 715 if (vcpu->arch.xcr0 != host_xcr0) 716 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 717 vcpu->guest_xcr0_loaded = 1; 718 } 719 } 720 721 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 722 { 723 if (vcpu->guest_xcr0_loaded) { 724 if (vcpu->arch.xcr0 != host_xcr0) 725 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 726 vcpu->guest_xcr0_loaded = 0; 727 } 728 } 729 730 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 731 { 732 u64 xcr0 = xcr; 733 u64 old_xcr0 = vcpu->arch.xcr0; 734 u64 valid_bits; 735 736 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 737 if (index != XCR_XFEATURE_ENABLED_MASK) 738 return 1; 739 if (!(xcr0 & XFEATURE_MASK_FP)) 740 return 1; 741 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 742 return 1; 743 744 /* 745 * Do not allow the guest to set bits that we do not support 746 * saving. However, xcr0 bit 0 is always set, even if the 747 * emulated CPU does not support XSAVE (see fx_init). 748 */ 749 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 750 if (xcr0 & ~valid_bits) 751 return 1; 752 753 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 754 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 755 return 1; 756 757 if (xcr0 & XFEATURE_MASK_AVX512) { 758 if (!(xcr0 & XFEATURE_MASK_YMM)) 759 return 1; 760 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 761 return 1; 762 } 763 vcpu->arch.xcr0 = xcr0; 764 765 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 766 kvm_update_cpuid(vcpu); 767 return 0; 768 } 769 770 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 771 { 772 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 773 __kvm_set_xcr(vcpu, index, xcr)) { 774 kvm_inject_gp(vcpu, 0); 775 return 1; 776 } 777 return 0; 778 } 779 EXPORT_SYMBOL_GPL(kvm_set_xcr); 780 781 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 782 { 783 unsigned long old_cr4 = kvm_read_cr4(vcpu); 784 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 785 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 786 787 if (cr4 & CR4_RESERVED_BITS) 788 return 1; 789 790 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE)) 791 return 1; 792 793 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP)) 794 return 1; 795 796 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP)) 797 return 1; 798 799 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE)) 800 return 1; 801 802 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE)) 803 return 1; 804 805 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57)) 806 return 1; 807 808 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP)) 809 return 1; 810 811 if (is_long_mode(vcpu)) { 812 if (!(cr4 & X86_CR4_PAE)) 813 return 1; 814 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 815 && ((cr4 ^ old_cr4) & pdptr_bits) 816 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 817 kvm_read_cr3(vcpu))) 818 return 1; 819 820 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 821 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 822 return 1; 823 824 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 825 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 826 return 1; 827 } 828 829 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 830 return 1; 831 832 if (((cr4 ^ old_cr4) & pdptr_bits) || 833 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 834 kvm_mmu_reset_context(vcpu); 835 836 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 837 kvm_update_cpuid(vcpu); 838 839 return 0; 840 } 841 EXPORT_SYMBOL_GPL(kvm_set_cr4); 842 843 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 844 { 845 #ifdef CONFIG_X86_64 846 cr3 &= ~CR3_PCID_INVD; 847 #endif 848 849 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 850 kvm_mmu_sync_roots(vcpu); 851 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 852 return 0; 853 } 854 855 if (is_long_mode(vcpu) && 856 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62))) 857 return 1; 858 else if (is_pae(vcpu) && is_paging(vcpu) && 859 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 860 return 1; 861 862 vcpu->arch.cr3 = cr3; 863 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 864 kvm_mmu_new_cr3(vcpu); 865 return 0; 866 } 867 EXPORT_SYMBOL_GPL(kvm_set_cr3); 868 869 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 870 { 871 if (cr8 & CR8_RESERVED_BITS) 872 return 1; 873 if (lapic_in_kernel(vcpu)) 874 kvm_lapic_set_tpr(vcpu, cr8); 875 else 876 vcpu->arch.cr8 = cr8; 877 return 0; 878 } 879 EXPORT_SYMBOL_GPL(kvm_set_cr8); 880 881 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 882 { 883 if (lapic_in_kernel(vcpu)) 884 return kvm_lapic_get_cr8(vcpu); 885 else 886 return vcpu->arch.cr8; 887 } 888 EXPORT_SYMBOL_GPL(kvm_get_cr8); 889 890 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 891 { 892 int i; 893 894 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 895 for (i = 0; i < KVM_NR_DB_REGS; i++) 896 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 897 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 898 } 899 } 900 901 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 902 { 903 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 904 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 905 } 906 907 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 908 { 909 unsigned long dr7; 910 911 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 912 dr7 = vcpu->arch.guest_debug_dr7; 913 else 914 dr7 = vcpu->arch.dr7; 915 kvm_x86_ops->set_dr7(vcpu, dr7); 916 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 917 if (dr7 & DR7_BP_EN_MASK) 918 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 919 } 920 921 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 922 { 923 u64 fixed = DR6_FIXED_1; 924 925 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 926 fixed |= DR6_RTM; 927 return fixed; 928 } 929 930 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 931 { 932 switch (dr) { 933 case 0 ... 3: 934 vcpu->arch.db[dr] = val; 935 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 936 vcpu->arch.eff_db[dr] = val; 937 break; 938 case 4: 939 /* fall through */ 940 case 6: 941 if (val & 0xffffffff00000000ULL) 942 return -1; /* #GP */ 943 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 944 kvm_update_dr6(vcpu); 945 break; 946 case 5: 947 /* fall through */ 948 default: /* 7 */ 949 if (val & 0xffffffff00000000ULL) 950 return -1; /* #GP */ 951 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 952 kvm_update_dr7(vcpu); 953 break; 954 } 955 956 return 0; 957 } 958 959 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 960 { 961 if (__kvm_set_dr(vcpu, dr, val)) { 962 kvm_inject_gp(vcpu, 0); 963 return 1; 964 } 965 return 0; 966 } 967 EXPORT_SYMBOL_GPL(kvm_set_dr); 968 969 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 970 { 971 switch (dr) { 972 case 0 ... 3: 973 *val = vcpu->arch.db[dr]; 974 break; 975 case 4: 976 /* fall through */ 977 case 6: 978 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 979 *val = vcpu->arch.dr6; 980 else 981 *val = kvm_x86_ops->get_dr6(vcpu); 982 break; 983 case 5: 984 /* fall through */ 985 default: /* 7 */ 986 *val = vcpu->arch.dr7; 987 break; 988 } 989 return 0; 990 } 991 EXPORT_SYMBOL_GPL(kvm_get_dr); 992 993 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 994 { 995 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 996 u64 data; 997 int err; 998 999 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 1000 if (err) 1001 return err; 1002 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 1003 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 1004 return err; 1005 } 1006 EXPORT_SYMBOL_GPL(kvm_rdpmc); 1007 1008 /* 1009 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1010 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1011 * 1012 * This list is modified at module load time to reflect the 1013 * capabilities of the host cpu. This capabilities test skips MSRs that are 1014 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs 1015 * may depend on host virtualization features rather than host cpu features. 1016 */ 1017 1018 static u32 msrs_to_save[] = { 1019 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1020 MSR_STAR, 1021 #ifdef CONFIG_X86_64 1022 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1023 #endif 1024 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1025 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1026 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES 1027 }; 1028 1029 static unsigned num_msrs_to_save; 1030 1031 static u32 emulated_msrs[] = { 1032 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1033 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1034 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1035 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1036 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1037 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1038 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1039 HV_X64_MSR_RESET, 1040 HV_X64_MSR_VP_INDEX, 1041 HV_X64_MSR_VP_RUNTIME, 1042 HV_X64_MSR_SCONTROL, 1043 HV_X64_MSR_STIMER0_CONFIG, 1044 HV_X64_MSR_VP_ASSIST_PAGE, 1045 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1046 HV_X64_MSR_TSC_EMULATION_STATUS, 1047 1048 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1049 MSR_KVM_PV_EOI_EN, 1050 1051 MSR_IA32_TSC_ADJUST, 1052 MSR_IA32_TSCDEADLINE, 1053 MSR_IA32_MISC_ENABLE, 1054 MSR_IA32_MCG_STATUS, 1055 MSR_IA32_MCG_CTL, 1056 MSR_IA32_MCG_EXT_CTL, 1057 MSR_IA32_SMBASE, 1058 MSR_SMI_COUNT, 1059 MSR_PLATFORM_INFO, 1060 MSR_MISC_FEATURES_ENABLES, 1061 }; 1062 1063 static unsigned num_emulated_msrs; 1064 1065 /* 1066 * List of msr numbers which are used to expose MSR-based features that 1067 * can be used by a hypervisor to validate requested CPU features. 1068 */ 1069 static u32 msr_based_features[] = { 1070 MSR_IA32_VMX_BASIC, 1071 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1072 MSR_IA32_VMX_PINBASED_CTLS, 1073 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1074 MSR_IA32_VMX_PROCBASED_CTLS, 1075 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1076 MSR_IA32_VMX_EXIT_CTLS, 1077 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1078 MSR_IA32_VMX_ENTRY_CTLS, 1079 MSR_IA32_VMX_MISC, 1080 MSR_IA32_VMX_CR0_FIXED0, 1081 MSR_IA32_VMX_CR0_FIXED1, 1082 MSR_IA32_VMX_CR4_FIXED0, 1083 MSR_IA32_VMX_CR4_FIXED1, 1084 MSR_IA32_VMX_VMCS_ENUM, 1085 MSR_IA32_VMX_PROCBASED_CTLS2, 1086 MSR_IA32_VMX_EPT_VPID_CAP, 1087 MSR_IA32_VMX_VMFUNC, 1088 1089 MSR_F10H_DECFG, 1090 MSR_IA32_UCODE_REV, 1091 }; 1092 1093 static unsigned int num_msr_based_features; 1094 1095 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1096 { 1097 switch (msr->index) { 1098 case MSR_IA32_UCODE_REV: 1099 rdmsrl(msr->index, msr->data); 1100 break; 1101 default: 1102 if (kvm_x86_ops->get_msr_feature(msr)) 1103 return 1; 1104 } 1105 return 0; 1106 } 1107 1108 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1109 { 1110 struct kvm_msr_entry msr; 1111 int r; 1112 1113 msr.index = index; 1114 r = kvm_get_msr_feature(&msr); 1115 if (r) 1116 return r; 1117 1118 *data = msr.data; 1119 1120 return 0; 1121 } 1122 1123 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1124 { 1125 if (efer & efer_reserved_bits) 1126 return false; 1127 1128 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1129 return false; 1130 1131 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1132 return false; 1133 1134 return true; 1135 } 1136 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1137 1138 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 1139 { 1140 u64 old_efer = vcpu->arch.efer; 1141 1142 if (!kvm_valid_efer(vcpu, efer)) 1143 return 1; 1144 1145 if (is_paging(vcpu) 1146 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1147 return 1; 1148 1149 efer &= ~EFER_LMA; 1150 efer |= vcpu->arch.efer & EFER_LMA; 1151 1152 kvm_x86_ops->set_efer(vcpu, efer); 1153 1154 /* Update reserved bits */ 1155 if ((efer ^ old_efer) & EFER_NX) 1156 kvm_mmu_reset_context(vcpu); 1157 1158 return 0; 1159 } 1160 1161 void kvm_enable_efer_bits(u64 mask) 1162 { 1163 efer_reserved_bits &= ~mask; 1164 } 1165 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1166 1167 /* 1168 * Writes msr value into into the appropriate "register". 1169 * Returns 0 on success, non-0 otherwise. 1170 * Assumes vcpu_load() was already called. 1171 */ 1172 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1173 { 1174 switch (msr->index) { 1175 case MSR_FS_BASE: 1176 case MSR_GS_BASE: 1177 case MSR_KERNEL_GS_BASE: 1178 case MSR_CSTAR: 1179 case MSR_LSTAR: 1180 if (is_noncanonical_address(msr->data, vcpu)) 1181 return 1; 1182 break; 1183 case MSR_IA32_SYSENTER_EIP: 1184 case MSR_IA32_SYSENTER_ESP: 1185 /* 1186 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1187 * non-canonical address is written on Intel but not on 1188 * AMD (which ignores the top 32-bits, because it does 1189 * not implement 64-bit SYSENTER). 1190 * 1191 * 64-bit code should hence be able to write a non-canonical 1192 * value on AMD. Making the address canonical ensures that 1193 * vmentry does not fail on Intel after writing a non-canonical 1194 * value, and that something deterministic happens if the guest 1195 * invokes 64-bit SYSENTER. 1196 */ 1197 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu)); 1198 } 1199 return kvm_x86_ops->set_msr(vcpu, msr); 1200 } 1201 EXPORT_SYMBOL_GPL(kvm_set_msr); 1202 1203 /* 1204 * Adapt set_msr() to msr_io()'s calling convention 1205 */ 1206 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1207 { 1208 struct msr_data msr; 1209 int r; 1210 1211 msr.index = index; 1212 msr.host_initiated = true; 1213 r = kvm_get_msr(vcpu, &msr); 1214 if (r) 1215 return r; 1216 1217 *data = msr.data; 1218 return 0; 1219 } 1220 1221 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1222 { 1223 struct msr_data msr; 1224 1225 msr.data = *data; 1226 msr.index = index; 1227 msr.host_initiated = true; 1228 return kvm_set_msr(vcpu, &msr); 1229 } 1230 1231 #ifdef CONFIG_X86_64 1232 struct pvclock_gtod_data { 1233 seqcount_t seq; 1234 1235 struct { /* extract of a clocksource struct */ 1236 int vclock_mode; 1237 u64 cycle_last; 1238 u64 mask; 1239 u32 mult; 1240 u32 shift; 1241 } clock; 1242 1243 u64 boot_ns; 1244 u64 nsec_base; 1245 u64 wall_time_sec; 1246 }; 1247 1248 static struct pvclock_gtod_data pvclock_gtod_data; 1249 1250 static void update_pvclock_gtod(struct timekeeper *tk) 1251 { 1252 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1253 u64 boot_ns; 1254 1255 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1256 1257 write_seqcount_begin(&vdata->seq); 1258 1259 /* copy pvclock gtod data */ 1260 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1261 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1262 vdata->clock.mask = tk->tkr_mono.mask; 1263 vdata->clock.mult = tk->tkr_mono.mult; 1264 vdata->clock.shift = tk->tkr_mono.shift; 1265 1266 vdata->boot_ns = boot_ns; 1267 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1268 1269 vdata->wall_time_sec = tk->xtime_sec; 1270 1271 write_seqcount_end(&vdata->seq); 1272 } 1273 #endif 1274 1275 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1276 { 1277 /* 1278 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1279 * vcpu_enter_guest. This function is only called from 1280 * the physical CPU that is running vcpu. 1281 */ 1282 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1283 } 1284 1285 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1286 { 1287 int version; 1288 int r; 1289 struct pvclock_wall_clock wc; 1290 struct timespec64 boot; 1291 1292 if (!wall_clock) 1293 return; 1294 1295 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1296 if (r) 1297 return; 1298 1299 if (version & 1) 1300 ++version; /* first time write, random junk */ 1301 1302 ++version; 1303 1304 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1305 return; 1306 1307 /* 1308 * The guest calculates current wall clock time by adding 1309 * system time (updated by kvm_guest_time_update below) to the 1310 * wall clock specified here. guest system time equals host 1311 * system time for us, thus we must fill in host boot time here. 1312 */ 1313 getboottime64(&boot); 1314 1315 if (kvm->arch.kvmclock_offset) { 1316 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset); 1317 boot = timespec64_sub(boot, ts); 1318 } 1319 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */ 1320 wc.nsec = boot.tv_nsec; 1321 wc.version = version; 1322 1323 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1324 1325 version++; 1326 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1327 } 1328 1329 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1330 { 1331 do_shl32_div32(dividend, divisor); 1332 return dividend; 1333 } 1334 1335 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 1336 s8 *pshift, u32 *pmultiplier) 1337 { 1338 uint64_t scaled64; 1339 int32_t shift = 0; 1340 uint64_t tps64; 1341 uint32_t tps32; 1342 1343 tps64 = base_hz; 1344 scaled64 = scaled_hz; 1345 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1346 tps64 >>= 1; 1347 shift--; 1348 } 1349 1350 tps32 = (uint32_t)tps64; 1351 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1352 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1353 scaled64 >>= 1; 1354 else 1355 tps32 <<= 1; 1356 shift++; 1357 } 1358 1359 *pshift = shift; 1360 *pmultiplier = div_frac(scaled64, tps32); 1361 1362 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n", 1363 __func__, base_hz, scaled_hz, shift, *pmultiplier); 1364 } 1365 1366 #ifdef CONFIG_X86_64 1367 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1368 #endif 1369 1370 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1371 static unsigned long max_tsc_khz; 1372 1373 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1374 { 1375 u64 v = (u64)khz * (1000000 + ppm); 1376 do_div(v, 1000000); 1377 return v; 1378 } 1379 1380 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 1381 { 1382 u64 ratio; 1383 1384 /* Guest TSC same frequency as host TSC? */ 1385 if (!scale) { 1386 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1387 return 0; 1388 } 1389 1390 /* TSC scaling supported? */ 1391 if (!kvm_has_tsc_control) { 1392 if (user_tsc_khz > tsc_khz) { 1393 vcpu->arch.tsc_catchup = 1; 1394 vcpu->arch.tsc_always_catchup = 1; 1395 return 0; 1396 } else { 1397 WARN(1, "user requested TSC rate below hardware speed\n"); 1398 return -1; 1399 } 1400 } 1401 1402 /* TSC scaling required - calculate ratio */ 1403 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 1404 user_tsc_khz, tsc_khz); 1405 1406 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 1407 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 1408 user_tsc_khz); 1409 return -1; 1410 } 1411 1412 vcpu->arch.tsc_scaling_ratio = ratio; 1413 return 0; 1414 } 1415 1416 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 1417 { 1418 u32 thresh_lo, thresh_hi; 1419 int use_scaling = 0; 1420 1421 /* tsc_khz can be zero if TSC calibration fails */ 1422 if (user_tsc_khz == 0) { 1423 /* set tsc_scaling_ratio to a safe value */ 1424 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1425 return -1; 1426 } 1427 1428 /* Compute a scale to convert nanoseconds in TSC cycles */ 1429 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 1430 &vcpu->arch.virtual_tsc_shift, 1431 &vcpu->arch.virtual_tsc_mult); 1432 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 1433 1434 /* 1435 * Compute the variation in TSC rate which is acceptable 1436 * within the range of tolerance and decide if the 1437 * rate being applied is within that bounds of the hardware 1438 * rate. If so, no scaling or compensation need be done. 1439 */ 1440 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1441 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1442 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 1443 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 1444 use_scaling = 1; 1445 } 1446 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 1447 } 1448 1449 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1450 { 1451 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1452 vcpu->arch.virtual_tsc_mult, 1453 vcpu->arch.virtual_tsc_shift); 1454 tsc += vcpu->arch.this_tsc_write; 1455 return tsc; 1456 } 1457 1458 static inline int gtod_is_based_on_tsc(int mode) 1459 { 1460 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK; 1461 } 1462 1463 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1464 { 1465 #ifdef CONFIG_X86_64 1466 bool vcpus_matched; 1467 struct kvm_arch *ka = &vcpu->kvm->arch; 1468 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1469 1470 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1471 atomic_read(&vcpu->kvm->online_vcpus)); 1472 1473 /* 1474 * Once the masterclock is enabled, always perform request in 1475 * order to update it. 1476 * 1477 * In order to enable masterclock, the host clocksource must be TSC 1478 * and the vcpus need to have matched TSCs. When that happens, 1479 * perform request to enable masterclock. 1480 */ 1481 if (ka->use_master_clock || 1482 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 1483 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1484 1485 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1486 atomic_read(&vcpu->kvm->online_vcpus), 1487 ka->use_master_clock, gtod->clock.vclock_mode); 1488 #endif 1489 } 1490 1491 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1492 { 1493 u64 curr_offset = vcpu->arch.tsc_offset; 1494 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1495 } 1496 1497 /* 1498 * Multiply tsc by a fixed point number represented by ratio. 1499 * 1500 * The most significant 64-N bits (mult) of ratio represent the 1501 * integral part of the fixed point number; the remaining N bits 1502 * (frac) represent the fractional part, ie. ratio represents a fixed 1503 * point number (mult + frac * 2^(-N)). 1504 * 1505 * N equals to kvm_tsc_scaling_ratio_frac_bits. 1506 */ 1507 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 1508 { 1509 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 1510 } 1511 1512 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 1513 { 1514 u64 _tsc = tsc; 1515 u64 ratio = vcpu->arch.tsc_scaling_ratio; 1516 1517 if (ratio != kvm_default_tsc_scaling_ratio) 1518 _tsc = __scale_tsc(ratio, tsc); 1519 1520 return _tsc; 1521 } 1522 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 1523 1524 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 1525 { 1526 u64 tsc; 1527 1528 tsc = kvm_scale_tsc(vcpu, rdtsc()); 1529 1530 return target_tsc - tsc; 1531 } 1532 1533 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 1534 { 1535 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc); 1536 } 1537 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 1538 1539 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1540 { 1541 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1542 vcpu->arch.tsc_offset = offset; 1543 } 1544 1545 static inline bool kvm_check_tsc_unstable(void) 1546 { 1547 #ifdef CONFIG_X86_64 1548 /* 1549 * TSC is marked unstable when we're running on Hyper-V, 1550 * 'TSC page' clocksource is good. 1551 */ 1552 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK) 1553 return false; 1554 #endif 1555 return check_tsc_unstable(); 1556 } 1557 1558 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1559 { 1560 struct kvm *kvm = vcpu->kvm; 1561 u64 offset, ns, elapsed; 1562 unsigned long flags; 1563 bool matched; 1564 bool already_matched; 1565 u64 data = msr->data; 1566 bool synchronizing = false; 1567 1568 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1569 offset = kvm_compute_tsc_offset(vcpu, data); 1570 ns = ktime_get_boot_ns(); 1571 elapsed = ns - kvm->arch.last_tsc_nsec; 1572 1573 if (vcpu->arch.virtual_tsc_khz) { 1574 if (data == 0 && msr->host_initiated) { 1575 /* 1576 * detection of vcpu initialization -- need to sync 1577 * with other vCPUs. This particularly helps to keep 1578 * kvm_clock stable after CPU hotplug 1579 */ 1580 synchronizing = true; 1581 } else { 1582 u64 tsc_exp = kvm->arch.last_tsc_write + 1583 nsec_to_cycles(vcpu, elapsed); 1584 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 1585 /* 1586 * Special case: TSC write with a small delta (1 second) 1587 * of virtual cycle time against real time is 1588 * interpreted as an attempt to synchronize the CPU. 1589 */ 1590 synchronizing = data < tsc_exp + tsc_hz && 1591 data + tsc_hz > tsc_exp; 1592 } 1593 } 1594 1595 /* 1596 * For a reliable TSC, we can match TSC offsets, and for an unstable 1597 * TSC, we add elapsed time in this computation. We could let the 1598 * compensation code attempt to catch up if we fall behind, but 1599 * it's better to try to match offsets from the beginning. 1600 */ 1601 if (synchronizing && 1602 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1603 if (!kvm_check_tsc_unstable()) { 1604 offset = kvm->arch.cur_tsc_offset; 1605 pr_debug("kvm: matched tsc offset for %llu\n", data); 1606 } else { 1607 u64 delta = nsec_to_cycles(vcpu, elapsed); 1608 data += delta; 1609 offset = kvm_compute_tsc_offset(vcpu, data); 1610 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1611 } 1612 matched = true; 1613 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1614 } else { 1615 /* 1616 * We split periods of matched TSC writes into generations. 1617 * For each generation, we track the original measured 1618 * nanosecond time, offset, and write, so if TSCs are in 1619 * sync, we can match exact offset, and if not, we can match 1620 * exact software computation in compute_guest_tsc() 1621 * 1622 * These values are tracked in kvm->arch.cur_xxx variables. 1623 */ 1624 kvm->arch.cur_tsc_generation++; 1625 kvm->arch.cur_tsc_nsec = ns; 1626 kvm->arch.cur_tsc_write = data; 1627 kvm->arch.cur_tsc_offset = offset; 1628 matched = false; 1629 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1630 kvm->arch.cur_tsc_generation, data); 1631 } 1632 1633 /* 1634 * We also track th most recent recorded KHZ, write and time to 1635 * allow the matching interval to be extended at each write. 1636 */ 1637 kvm->arch.last_tsc_nsec = ns; 1638 kvm->arch.last_tsc_write = data; 1639 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1640 1641 vcpu->arch.last_guest_tsc = data; 1642 1643 /* Keep track of which generation this VCPU has synchronized to */ 1644 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1645 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1646 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1647 1648 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) 1649 update_ia32_tsc_adjust_msr(vcpu, offset); 1650 1651 kvm_vcpu_write_tsc_offset(vcpu, offset); 1652 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1653 1654 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1655 if (!matched) { 1656 kvm->arch.nr_vcpus_matched_tsc = 0; 1657 } else if (!already_matched) { 1658 kvm->arch.nr_vcpus_matched_tsc++; 1659 } 1660 1661 kvm_track_tsc_matching(vcpu); 1662 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1663 } 1664 1665 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1666 1667 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 1668 s64 adjustment) 1669 { 1670 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment); 1671 } 1672 1673 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 1674 { 1675 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 1676 WARN_ON(adjustment < 0); 1677 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 1678 adjust_tsc_offset_guest(vcpu, adjustment); 1679 } 1680 1681 #ifdef CONFIG_X86_64 1682 1683 static u64 read_tsc(void) 1684 { 1685 u64 ret = (u64)rdtsc_ordered(); 1686 u64 last = pvclock_gtod_data.clock.cycle_last; 1687 1688 if (likely(ret >= last)) 1689 return ret; 1690 1691 /* 1692 * GCC likes to generate cmov here, but this branch is extremely 1693 * predictable (it's just a function of time and the likely is 1694 * very likely) and there's a data dependence, so force GCC 1695 * to generate a branch instead. I don't barrier() because 1696 * we don't actually need a barrier, and if this function 1697 * ever gets inlined it will generate worse code. 1698 */ 1699 asm volatile (""); 1700 return last; 1701 } 1702 1703 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode) 1704 { 1705 long v; 1706 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1707 u64 tsc_pg_val; 1708 1709 switch (gtod->clock.vclock_mode) { 1710 case VCLOCK_HVCLOCK: 1711 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 1712 tsc_timestamp); 1713 if (tsc_pg_val != U64_MAX) { 1714 /* TSC page valid */ 1715 *mode = VCLOCK_HVCLOCK; 1716 v = (tsc_pg_val - gtod->clock.cycle_last) & 1717 gtod->clock.mask; 1718 } else { 1719 /* TSC page invalid */ 1720 *mode = VCLOCK_NONE; 1721 } 1722 break; 1723 case VCLOCK_TSC: 1724 *mode = VCLOCK_TSC; 1725 *tsc_timestamp = read_tsc(); 1726 v = (*tsc_timestamp - gtod->clock.cycle_last) & 1727 gtod->clock.mask; 1728 break; 1729 default: 1730 *mode = VCLOCK_NONE; 1731 } 1732 1733 if (*mode == VCLOCK_NONE) 1734 *tsc_timestamp = v = 0; 1735 1736 return v * gtod->clock.mult; 1737 } 1738 1739 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp) 1740 { 1741 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1742 unsigned long seq; 1743 int mode; 1744 u64 ns; 1745 1746 do { 1747 seq = read_seqcount_begin(>od->seq); 1748 ns = gtod->nsec_base; 1749 ns += vgettsc(tsc_timestamp, &mode); 1750 ns >>= gtod->clock.shift; 1751 ns += gtod->boot_ns; 1752 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1753 *t = ns; 1754 1755 return mode; 1756 } 1757 1758 static int do_realtime(struct timespec *ts, u64 *tsc_timestamp) 1759 { 1760 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1761 unsigned long seq; 1762 int mode; 1763 u64 ns; 1764 1765 do { 1766 seq = read_seqcount_begin(>od->seq); 1767 ts->tv_sec = gtod->wall_time_sec; 1768 ns = gtod->nsec_base; 1769 ns += vgettsc(tsc_timestamp, &mode); 1770 ns >>= gtod->clock.shift; 1771 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1772 1773 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 1774 ts->tv_nsec = ns; 1775 1776 return mode; 1777 } 1778 1779 /* returns true if host is using TSC based clocksource */ 1780 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 1781 { 1782 /* checked again under seqlock below */ 1783 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 1784 return false; 1785 1786 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns, 1787 tsc_timestamp)); 1788 } 1789 1790 /* returns true if host is using TSC based clocksource */ 1791 static bool kvm_get_walltime_and_clockread(struct timespec *ts, 1792 u64 *tsc_timestamp) 1793 { 1794 /* checked again under seqlock below */ 1795 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 1796 return false; 1797 1798 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 1799 } 1800 #endif 1801 1802 /* 1803 * 1804 * Assuming a stable TSC across physical CPUS, and a stable TSC 1805 * across virtual CPUs, the following condition is possible. 1806 * Each numbered line represents an event visible to both 1807 * CPUs at the next numbered event. 1808 * 1809 * "timespecX" represents host monotonic time. "tscX" represents 1810 * RDTSC value. 1811 * 1812 * VCPU0 on CPU0 | VCPU1 on CPU1 1813 * 1814 * 1. read timespec0,tsc0 1815 * 2. | timespec1 = timespec0 + N 1816 * | tsc1 = tsc0 + M 1817 * 3. transition to guest | transition to guest 1818 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1819 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1820 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1821 * 1822 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1823 * 1824 * - ret0 < ret1 1825 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1826 * ... 1827 * - 0 < N - M => M < N 1828 * 1829 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1830 * always the case (the difference between two distinct xtime instances 1831 * might be smaller then the difference between corresponding TSC reads, 1832 * when updating guest vcpus pvclock areas). 1833 * 1834 * To avoid that problem, do not allow visibility of distinct 1835 * system_timestamp/tsc_timestamp values simultaneously: use a master 1836 * copy of host monotonic time values. Update that master copy 1837 * in lockstep. 1838 * 1839 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1840 * 1841 */ 1842 1843 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1844 { 1845 #ifdef CONFIG_X86_64 1846 struct kvm_arch *ka = &kvm->arch; 1847 int vclock_mode; 1848 bool host_tsc_clocksource, vcpus_matched; 1849 1850 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1851 atomic_read(&kvm->online_vcpus)); 1852 1853 /* 1854 * If the host uses TSC clock, then passthrough TSC as stable 1855 * to the guest. 1856 */ 1857 host_tsc_clocksource = kvm_get_time_and_clockread( 1858 &ka->master_kernel_ns, 1859 &ka->master_cycle_now); 1860 1861 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 1862 && !ka->backwards_tsc_observed 1863 && !ka->boot_vcpu_runs_old_kvmclock; 1864 1865 if (ka->use_master_clock) 1866 atomic_set(&kvm_guest_has_master_clock, 1); 1867 1868 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1869 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1870 vcpus_matched); 1871 #endif 1872 } 1873 1874 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 1875 { 1876 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 1877 } 1878 1879 static void kvm_gen_update_masterclock(struct kvm *kvm) 1880 { 1881 #ifdef CONFIG_X86_64 1882 int i; 1883 struct kvm_vcpu *vcpu; 1884 struct kvm_arch *ka = &kvm->arch; 1885 1886 spin_lock(&ka->pvclock_gtod_sync_lock); 1887 kvm_make_mclock_inprogress_request(kvm); 1888 /* no guest entries from this point */ 1889 pvclock_update_vm_gtod_copy(kvm); 1890 1891 kvm_for_each_vcpu(i, vcpu, kvm) 1892 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1893 1894 /* guest entries allowed */ 1895 kvm_for_each_vcpu(i, vcpu, kvm) 1896 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 1897 1898 spin_unlock(&ka->pvclock_gtod_sync_lock); 1899 #endif 1900 } 1901 1902 u64 get_kvmclock_ns(struct kvm *kvm) 1903 { 1904 struct kvm_arch *ka = &kvm->arch; 1905 struct pvclock_vcpu_time_info hv_clock; 1906 u64 ret; 1907 1908 spin_lock(&ka->pvclock_gtod_sync_lock); 1909 if (!ka->use_master_clock) { 1910 spin_unlock(&ka->pvclock_gtod_sync_lock); 1911 return ktime_get_boot_ns() + ka->kvmclock_offset; 1912 } 1913 1914 hv_clock.tsc_timestamp = ka->master_cycle_now; 1915 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 1916 spin_unlock(&ka->pvclock_gtod_sync_lock); 1917 1918 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 1919 get_cpu(); 1920 1921 if (__this_cpu_read(cpu_tsc_khz)) { 1922 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 1923 &hv_clock.tsc_shift, 1924 &hv_clock.tsc_to_system_mul); 1925 ret = __pvclock_read_cycles(&hv_clock, rdtsc()); 1926 } else 1927 ret = ktime_get_boot_ns() + ka->kvmclock_offset; 1928 1929 put_cpu(); 1930 1931 return ret; 1932 } 1933 1934 static void kvm_setup_pvclock_page(struct kvm_vcpu *v) 1935 { 1936 struct kvm_vcpu_arch *vcpu = &v->arch; 1937 struct pvclock_vcpu_time_info guest_hv_clock; 1938 1939 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1940 &guest_hv_clock, sizeof(guest_hv_clock)))) 1941 return; 1942 1943 /* This VCPU is paused, but it's legal for a guest to read another 1944 * VCPU's kvmclock, so we really have to follow the specification where 1945 * it says that version is odd if data is being modified, and even after 1946 * it is consistent. 1947 * 1948 * Version field updates must be kept separate. This is because 1949 * kvm_write_guest_cached might use a "rep movs" instruction, and 1950 * writes within a string instruction are weakly ordered. So there 1951 * are three writes overall. 1952 * 1953 * As a small optimization, only write the version field in the first 1954 * and third write. The vcpu->pv_time cache is still valid, because the 1955 * version field is the first in the struct. 1956 */ 1957 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 1958 1959 if (guest_hv_clock.version & 1) 1960 ++guest_hv_clock.version; /* first time write, random junk */ 1961 1962 vcpu->hv_clock.version = guest_hv_clock.version + 1; 1963 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1964 &vcpu->hv_clock, 1965 sizeof(vcpu->hv_clock.version)); 1966 1967 smp_wmb(); 1968 1969 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1970 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1971 1972 if (vcpu->pvclock_set_guest_stopped_request) { 1973 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 1974 vcpu->pvclock_set_guest_stopped_request = false; 1975 } 1976 1977 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 1978 1979 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1980 &vcpu->hv_clock, 1981 sizeof(vcpu->hv_clock)); 1982 1983 smp_wmb(); 1984 1985 vcpu->hv_clock.version++; 1986 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1987 &vcpu->hv_clock, 1988 sizeof(vcpu->hv_clock.version)); 1989 } 1990 1991 static int kvm_guest_time_update(struct kvm_vcpu *v) 1992 { 1993 unsigned long flags, tgt_tsc_khz; 1994 struct kvm_vcpu_arch *vcpu = &v->arch; 1995 struct kvm_arch *ka = &v->kvm->arch; 1996 s64 kernel_ns; 1997 u64 tsc_timestamp, host_tsc; 1998 u8 pvclock_flags; 1999 bool use_master_clock; 2000 2001 kernel_ns = 0; 2002 host_tsc = 0; 2003 2004 /* 2005 * If the host uses TSC clock, then passthrough TSC as stable 2006 * to the guest. 2007 */ 2008 spin_lock(&ka->pvclock_gtod_sync_lock); 2009 use_master_clock = ka->use_master_clock; 2010 if (use_master_clock) { 2011 host_tsc = ka->master_cycle_now; 2012 kernel_ns = ka->master_kernel_ns; 2013 } 2014 spin_unlock(&ka->pvclock_gtod_sync_lock); 2015 2016 /* Keep irq disabled to prevent changes to the clock */ 2017 local_irq_save(flags); 2018 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 2019 if (unlikely(tgt_tsc_khz == 0)) { 2020 local_irq_restore(flags); 2021 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2022 return 1; 2023 } 2024 if (!use_master_clock) { 2025 host_tsc = rdtsc(); 2026 kernel_ns = ktime_get_boot_ns(); 2027 } 2028 2029 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 2030 2031 /* 2032 * We may have to catch up the TSC to match elapsed wall clock 2033 * time for two reasons, even if kvmclock is used. 2034 * 1) CPU could have been running below the maximum TSC rate 2035 * 2) Broken TSC compensation resets the base at each VCPU 2036 * entry to avoid unknown leaps of TSC even when running 2037 * again on the same CPU. This may cause apparent elapsed 2038 * time to disappear, and the guest to stand still or run 2039 * very slowly. 2040 */ 2041 if (vcpu->tsc_catchup) { 2042 u64 tsc = compute_guest_tsc(v, kernel_ns); 2043 if (tsc > tsc_timestamp) { 2044 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 2045 tsc_timestamp = tsc; 2046 } 2047 } 2048 2049 local_irq_restore(flags); 2050 2051 /* With all the info we got, fill in the values */ 2052 2053 if (kvm_has_tsc_control) 2054 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 2055 2056 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 2057 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 2058 &vcpu->hv_clock.tsc_shift, 2059 &vcpu->hv_clock.tsc_to_system_mul); 2060 vcpu->hw_tsc_khz = tgt_tsc_khz; 2061 } 2062 2063 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 2064 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 2065 vcpu->last_guest_tsc = tsc_timestamp; 2066 2067 /* If the host uses TSC clocksource, then it is stable */ 2068 pvclock_flags = 0; 2069 if (use_master_clock) 2070 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 2071 2072 vcpu->hv_clock.flags = pvclock_flags; 2073 2074 if (vcpu->pv_time_enabled) 2075 kvm_setup_pvclock_page(v); 2076 if (v == kvm_get_vcpu(v->kvm, 0)) 2077 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 2078 return 0; 2079 } 2080 2081 /* 2082 * kvmclock updates which are isolated to a given vcpu, such as 2083 * vcpu->cpu migration, should not allow system_timestamp from 2084 * the rest of the vcpus to remain static. Otherwise ntp frequency 2085 * correction applies to one vcpu's system_timestamp but not 2086 * the others. 2087 * 2088 * So in those cases, request a kvmclock update for all vcpus. 2089 * We need to rate-limit these requests though, as they can 2090 * considerably slow guests that have a large number of vcpus. 2091 * The time for a remote vcpu to update its kvmclock is bound 2092 * by the delay we use to rate-limit the updates. 2093 */ 2094 2095 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 2096 2097 static void kvmclock_update_fn(struct work_struct *work) 2098 { 2099 int i; 2100 struct delayed_work *dwork = to_delayed_work(work); 2101 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2102 kvmclock_update_work); 2103 struct kvm *kvm = container_of(ka, struct kvm, arch); 2104 struct kvm_vcpu *vcpu; 2105 2106 kvm_for_each_vcpu(i, vcpu, kvm) { 2107 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2108 kvm_vcpu_kick(vcpu); 2109 } 2110 } 2111 2112 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 2113 { 2114 struct kvm *kvm = v->kvm; 2115 2116 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2117 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 2118 KVMCLOCK_UPDATE_DELAY); 2119 } 2120 2121 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 2122 2123 static void kvmclock_sync_fn(struct work_struct *work) 2124 { 2125 struct delayed_work *dwork = to_delayed_work(work); 2126 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2127 kvmclock_sync_work); 2128 struct kvm *kvm = container_of(ka, struct kvm, arch); 2129 2130 if (!kvmclock_periodic_sync) 2131 return; 2132 2133 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 2134 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 2135 KVMCLOCK_SYNC_PERIOD); 2136 } 2137 2138 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2139 { 2140 u64 mcg_cap = vcpu->arch.mcg_cap; 2141 unsigned bank_num = mcg_cap & 0xff; 2142 u32 msr = msr_info->index; 2143 u64 data = msr_info->data; 2144 2145 switch (msr) { 2146 case MSR_IA32_MCG_STATUS: 2147 vcpu->arch.mcg_status = data; 2148 break; 2149 case MSR_IA32_MCG_CTL: 2150 if (!(mcg_cap & MCG_CTL_P)) 2151 return 1; 2152 if (data != 0 && data != ~(u64)0) 2153 return -1; 2154 vcpu->arch.mcg_ctl = data; 2155 break; 2156 default: 2157 if (msr >= MSR_IA32_MC0_CTL && 2158 msr < MSR_IA32_MCx_CTL(bank_num)) { 2159 u32 offset = msr - MSR_IA32_MC0_CTL; 2160 /* only 0 or all 1s can be written to IA32_MCi_CTL 2161 * some Linux kernels though clear bit 10 in bank 4 to 2162 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 2163 * this to avoid an uncatched #GP in the guest 2164 */ 2165 if ((offset & 0x3) == 0 && 2166 data != 0 && (data | (1 << 10)) != ~(u64)0) 2167 return -1; 2168 if (!msr_info->host_initiated && 2169 (offset & 0x3) == 1 && data != 0) 2170 return -1; 2171 vcpu->arch.mce_banks[offset] = data; 2172 break; 2173 } 2174 return 1; 2175 } 2176 return 0; 2177 } 2178 2179 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 2180 { 2181 struct kvm *kvm = vcpu->kvm; 2182 int lm = is_long_mode(vcpu); 2183 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 2184 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 2185 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 2186 : kvm->arch.xen_hvm_config.blob_size_32; 2187 u32 page_num = data & ~PAGE_MASK; 2188 u64 page_addr = data & PAGE_MASK; 2189 u8 *page; 2190 int r; 2191 2192 r = -E2BIG; 2193 if (page_num >= blob_size) 2194 goto out; 2195 r = -ENOMEM; 2196 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 2197 if (IS_ERR(page)) { 2198 r = PTR_ERR(page); 2199 goto out; 2200 } 2201 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 2202 goto out_free; 2203 r = 0; 2204 out_free: 2205 kfree(page); 2206 out: 2207 return r; 2208 } 2209 2210 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2211 { 2212 gpa_t gpa = data & ~0x3f; 2213 2214 /* Bits 3:5 are reserved, Should be zero */ 2215 if (data & 0x38) 2216 return 1; 2217 2218 vcpu->arch.apf.msr_val = data; 2219 2220 if (!(data & KVM_ASYNC_PF_ENABLED)) { 2221 kvm_clear_async_pf_completion_queue(vcpu); 2222 kvm_async_pf_hash_reset(vcpu); 2223 return 0; 2224 } 2225 2226 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2227 sizeof(u32))) 2228 return 1; 2229 2230 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2231 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 2232 kvm_async_pf_wakeup_all(vcpu); 2233 return 0; 2234 } 2235 2236 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2237 { 2238 vcpu->arch.pv_time_enabled = false; 2239 } 2240 2241 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) 2242 { 2243 ++vcpu->stat.tlb_flush; 2244 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa); 2245 } 2246 2247 static void record_steal_time(struct kvm_vcpu *vcpu) 2248 { 2249 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2250 return; 2251 2252 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2253 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2254 return; 2255 2256 /* 2257 * Doing a TLB flush here, on the guest's behalf, can avoid 2258 * expensive IPIs. 2259 */ 2260 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB) 2261 kvm_vcpu_flush_tlb(vcpu, false); 2262 2263 if (vcpu->arch.st.steal.version & 1) 2264 vcpu->arch.st.steal.version += 1; /* first time write, random junk */ 2265 2266 vcpu->arch.st.steal.version += 1; 2267 2268 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2269 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2270 2271 smp_wmb(); 2272 2273 vcpu->arch.st.steal.steal += current->sched_info.run_delay - 2274 vcpu->arch.st.last_steal; 2275 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2276 2277 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2278 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2279 2280 smp_wmb(); 2281 2282 vcpu->arch.st.steal.version += 1; 2283 2284 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2285 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2286 } 2287 2288 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2289 { 2290 bool pr = false; 2291 u32 msr = msr_info->index; 2292 u64 data = msr_info->data; 2293 2294 switch (msr) { 2295 case MSR_AMD64_NB_CFG: 2296 case MSR_IA32_UCODE_WRITE: 2297 case MSR_VM_HSAVE_PA: 2298 case MSR_AMD64_PATCH_LOADER: 2299 case MSR_AMD64_BU_CFG2: 2300 case MSR_AMD64_DC_CFG: 2301 break; 2302 2303 case MSR_IA32_UCODE_REV: 2304 if (msr_info->host_initiated) 2305 vcpu->arch.microcode_version = data; 2306 break; 2307 case MSR_EFER: 2308 return set_efer(vcpu, data); 2309 case MSR_K7_HWCR: 2310 data &= ~(u64)0x40; /* ignore flush filter disable */ 2311 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2312 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2313 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2314 if (data != 0) { 2315 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2316 data); 2317 return 1; 2318 } 2319 break; 2320 case MSR_FAM10H_MMIO_CONF_BASE: 2321 if (data != 0) { 2322 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2323 "0x%llx\n", data); 2324 return 1; 2325 } 2326 break; 2327 case MSR_IA32_DEBUGCTLMSR: 2328 if (!data) { 2329 /* We support the non-activated case already */ 2330 break; 2331 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2332 /* Values other than LBR and BTF are vendor-specific, 2333 thus reserved and should throw a #GP */ 2334 return 1; 2335 } 2336 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2337 __func__, data); 2338 break; 2339 case 0x200 ... 0x2ff: 2340 return kvm_mtrr_set_msr(vcpu, msr, data); 2341 case MSR_IA32_APICBASE: 2342 return kvm_set_apic_base(vcpu, msr_info); 2343 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2344 return kvm_x2apic_msr_write(vcpu, msr, data); 2345 case MSR_IA32_TSCDEADLINE: 2346 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2347 break; 2348 case MSR_IA32_TSC_ADJUST: 2349 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 2350 if (!msr_info->host_initiated) { 2351 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2352 adjust_tsc_offset_guest(vcpu, adj); 2353 } 2354 vcpu->arch.ia32_tsc_adjust_msr = data; 2355 } 2356 break; 2357 case MSR_IA32_MISC_ENABLE: 2358 vcpu->arch.ia32_misc_enable_msr = data; 2359 break; 2360 case MSR_IA32_SMBASE: 2361 if (!msr_info->host_initiated) 2362 return 1; 2363 vcpu->arch.smbase = data; 2364 break; 2365 case MSR_SMI_COUNT: 2366 if (!msr_info->host_initiated) 2367 return 1; 2368 vcpu->arch.smi_count = data; 2369 break; 2370 case MSR_KVM_WALL_CLOCK_NEW: 2371 case MSR_KVM_WALL_CLOCK: 2372 vcpu->kvm->arch.wall_clock = data; 2373 kvm_write_wall_clock(vcpu->kvm, data); 2374 break; 2375 case MSR_KVM_SYSTEM_TIME_NEW: 2376 case MSR_KVM_SYSTEM_TIME: { 2377 struct kvm_arch *ka = &vcpu->kvm->arch; 2378 2379 kvmclock_reset(vcpu); 2380 2381 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2382 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2383 2384 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2385 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2386 2387 ka->boot_vcpu_runs_old_kvmclock = tmp; 2388 } 2389 2390 vcpu->arch.time = data; 2391 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2392 2393 /* we verify if the enable bit is set... */ 2394 if (!(data & 1)) 2395 break; 2396 2397 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2398 &vcpu->arch.pv_time, data & ~1ULL, 2399 sizeof(struct pvclock_vcpu_time_info))) 2400 vcpu->arch.pv_time_enabled = false; 2401 else 2402 vcpu->arch.pv_time_enabled = true; 2403 2404 break; 2405 } 2406 case MSR_KVM_ASYNC_PF_EN: 2407 if (kvm_pv_enable_async_pf(vcpu, data)) 2408 return 1; 2409 break; 2410 case MSR_KVM_STEAL_TIME: 2411 2412 if (unlikely(!sched_info_on())) 2413 return 1; 2414 2415 if (data & KVM_STEAL_RESERVED_MASK) 2416 return 1; 2417 2418 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2419 data & KVM_STEAL_VALID_BITS, 2420 sizeof(struct kvm_steal_time))) 2421 return 1; 2422 2423 vcpu->arch.st.msr_val = data; 2424 2425 if (!(data & KVM_MSR_ENABLED)) 2426 break; 2427 2428 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2429 2430 break; 2431 case MSR_KVM_PV_EOI_EN: 2432 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2433 return 1; 2434 break; 2435 2436 case MSR_IA32_MCG_CTL: 2437 case MSR_IA32_MCG_STATUS: 2438 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2439 return set_msr_mce(vcpu, msr_info); 2440 2441 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2442 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2443 pr = true; /* fall through */ 2444 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2445 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2446 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2447 return kvm_pmu_set_msr(vcpu, msr_info); 2448 2449 if (pr || data != 0) 2450 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2451 "0x%x data 0x%llx\n", msr, data); 2452 break; 2453 case MSR_K7_CLK_CTL: 2454 /* 2455 * Ignore all writes to this no longer documented MSR. 2456 * Writes are only relevant for old K7 processors, 2457 * all pre-dating SVM, but a recommended workaround from 2458 * AMD for these chips. It is possible to specify the 2459 * affected processor models on the command line, hence 2460 * the need to ignore the workaround. 2461 */ 2462 break; 2463 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2464 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2465 case HV_X64_MSR_CRASH_CTL: 2466 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2467 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 2468 case HV_X64_MSR_TSC_EMULATION_CONTROL: 2469 case HV_X64_MSR_TSC_EMULATION_STATUS: 2470 return kvm_hv_set_msr_common(vcpu, msr, data, 2471 msr_info->host_initiated); 2472 case MSR_IA32_BBL_CR_CTL3: 2473 /* Drop writes to this legacy MSR -- see rdmsr 2474 * counterpart for further detail. 2475 */ 2476 if (report_ignored_msrs) 2477 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 2478 msr, data); 2479 break; 2480 case MSR_AMD64_OSVW_ID_LENGTH: 2481 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2482 return 1; 2483 vcpu->arch.osvw.length = data; 2484 break; 2485 case MSR_AMD64_OSVW_STATUS: 2486 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2487 return 1; 2488 vcpu->arch.osvw.status = data; 2489 break; 2490 case MSR_PLATFORM_INFO: 2491 if (!msr_info->host_initiated || 2492 data & ~MSR_PLATFORM_INFO_CPUID_FAULT || 2493 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 2494 cpuid_fault_enabled(vcpu))) 2495 return 1; 2496 vcpu->arch.msr_platform_info = data; 2497 break; 2498 case MSR_MISC_FEATURES_ENABLES: 2499 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 2500 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 2501 !supports_cpuid_fault(vcpu))) 2502 return 1; 2503 vcpu->arch.msr_misc_features_enables = data; 2504 break; 2505 default: 2506 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2507 return xen_hvm_config(vcpu, data); 2508 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2509 return kvm_pmu_set_msr(vcpu, msr_info); 2510 if (!ignore_msrs) { 2511 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n", 2512 msr, data); 2513 return 1; 2514 } else { 2515 if (report_ignored_msrs) 2516 vcpu_unimpl(vcpu, 2517 "ignored wrmsr: 0x%x data 0x%llx\n", 2518 msr, data); 2519 break; 2520 } 2521 } 2522 return 0; 2523 } 2524 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2525 2526 2527 /* 2528 * Reads an msr value (of 'msr_index') into 'pdata'. 2529 * Returns 0 on success, non-0 otherwise. 2530 * Assumes vcpu_load() was already called. 2531 */ 2532 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 2533 { 2534 return kvm_x86_ops->get_msr(vcpu, msr); 2535 } 2536 EXPORT_SYMBOL_GPL(kvm_get_msr); 2537 2538 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2539 { 2540 u64 data; 2541 u64 mcg_cap = vcpu->arch.mcg_cap; 2542 unsigned bank_num = mcg_cap & 0xff; 2543 2544 switch (msr) { 2545 case MSR_IA32_P5_MC_ADDR: 2546 case MSR_IA32_P5_MC_TYPE: 2547 data = 0; 2548 break; 2549 case MSR_IA32_MCG_CAP: 2550 data = vcpu->arch.mcg_cap; 2551 break; 2552 case MSR_IA32_MCG_CTL: 2553 if (!(mcg_cap & MCG_CTL_P)) 2554 return 1; 2555 data = vcpu->arch.mcg_ctl; 2556 break; 2557 case MSR_IA32_MCG_STATUS: 2558 data = vcpu->arch.mcg_status; 2559 break; 2560 default: 2561 if (msr >= MSR_IA32_MC0_CTL && 2562 msr < MSR_IA32_MCx_CTL(bank_num)) { 2563 u32 offset = msr - MSR_IA32_MC0_CTL; 2564 data = vcpu->arch.mce_banks[offset]; 2565 break; 2566 } 2567 return 1; 2568 } 2569 *pdata = data; 2570 return 0; 2571 } 2572 2573 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2574 { 2575 switch (msr_info->index) { 2576 case MSR_IA32_PLATFORM_ID: 2577 case MSR_IA32_EBL_CR_POWERON: 2578 case MSR_IA32_DEBUGCTLMSR: 2579 case MSR_IA32_LASTBRANCHFROMIP: 2580 case MSR_IA32_LASTBRANCHTOIP: 2581 case MSR_IA32_LASTINTFROMIP: 2582 case MSR_IA32_LASTINTTOIP: 2583 case MSR_K8_SYSCFG: 2584 case MSR_K8_TSEG_ADDR: 2585 case MSR_K8_TSEG_MASK: 2586 case MSR_K7_HWCR: 2587 case MSR_VM_HSAVE_PA: 2588 case MSR_K8_INT_PENDING_MSG: 2589 case MSR_AMD64_NB_CFG: 2590 case MSR_FAM10H_MMIO_CONF_BASE: 2591 case MSR_AMD64_BU_CFG2: 2592 case MSR_IA32_PERF_CTL: 2593 case MSR_AMD64_DC_CFG: 2594 msr_info->data = 0; 2595 break; 2596 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 2597 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2598 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2599 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2600 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2601 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2602 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2603 msr_info->data = 0; 2604 break; 2605 case MSR_IA32_UCODE_REV: 2606 msr_info->data = vcpu->arch.microcode_version; 2607 break; 2608 case MSR_MTRRcap: 2609 case 0x200 ... 0x2ff: 2610 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 2611 case 0xcd: /* fsb frequency */ 2612 msr_info->data = 3; 2613 break; 2614 /* 2615 * MSR_EBC_FREQUENCY_ID 2616 * Conservative value valid for even the basic CPU models. 2617 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2618 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2619 * and 266MHz for model 3, or 4. Set Core Clock 2620 * Frequency to System Bus Frequency Ratio to 1 (bits 2621 * 31:24) even though these are only valid for CPU 2622 * models > 2, however guests may end up dividing or 2623 * multiplying by zero otherwise. 2624 */ 2625 case MSR_EBC_FREQUENCY_ID: 2626 msr_info->data = 1 << 24; 2627 break; 2628 case MSR_IA32_APICBASE: 2629 msr_info->data = kvm_get_apic_base(vcpu); 2630 break; 2631 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2632 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 2633 break; 2634 case MSR_IA32_TSCDEADLINE: 2635 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 2636 break; 2637 case MSR_IA32_TSC_ADJUST: 2638 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2639 break; 2640 case MSR_IA32_MISC_ENABLE: 2641 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 2642 break; 2643 case MSR_IA32_SMBASE: 2644 if (!msr_info->host_initiated) 2645 return 1; 2646 msr_info->data = vcpu->arch.smbase; 2647 break; 2648 case MSR_SMI_COUNT: 2649 msr_info->data = vcpu->arch.smi_count; 2650 break; 2651 case MSR_IA32_PERF_STATUS: 2652 /* TSC increment by tick */ 2653 msr_info->data = 1000ULL; 2654 /* CPU multiplier */ 2655 msr_info->data |= (((uint64_t)4ULL) << 40); 2656 break; 2657 case MSR_EFER: 2658 msr_info->data = vcpu->arch.efer; 2659 break; 2660 case MSR_KVM_WALL_CLOCK: 2661 case MSR_KVM_WALL_CLOCK_NEW: 2662 msr_info->data = vcpu->kvm->arch.wall_clock; 2663 break; 2664 case MSR_KVM_SYSTEM_TIME: 2665 case MSR_KVM_SYSTEM_TIME_NEW: 2666 msr_info->data = vcpu->arch.time; 2667 break; 2668 case MSR_KVM_ASYNC_PF_EN: 2669 msr_info->data = vcpu->arch.apf.msr_val; 2670 break; 2671 case MSR_KVM_STEAL_TIME: 2672 msr_info->data = vcpu->arch.st.msr_val; 2673 break; 2674 case MSR_KVM_PV_EOI_EN: 2675 msr_info->data = vcpu->arch.pv_eoi.msr_val; 2676 break; 2677 case MSR_IA32_P5_MC_ADDR: 2678 case MSR_IA32_P5_MC_TYPE: 2679 case MSR_IA32_MCG_CAP: 2680 case MSR_IA32_MCG_CTL: 2681 case MSR_IA32_MCG_STATUS: 2682 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2683 return get_msr_mce(vcpu, msr_info->index, &msr_info->data); 2684 case MSR_K7_CLK_CTL: 2685 /* 2686 * Provide expected ramp-up count for K7. All other 2687 * are set to zero, indicating minimum divisors for 2688 * every field. 2689 * 2690 * This prevents guest kernels on AMD host with CPU 2691 * type 6, model 8 and higher from exploding due to 2692 * the rdmsr failing. 2693 */ 2694 msr_info->data = 0x20000000; 2695 break; 2696 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2697 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2698 case HV_X64_MSR_CRASH_CTL: 2699 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2700 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 2701 case HV_X64_MSR_TSC_EMULATION_CONTROL: 2702 case HV_X64_MSR_TSC_EMULATION_STATUS: 2703 return kvm_hv_get_msr_common(vcpu, 2704 msr_info->index, &msr_info->data); 2705 break; 2706 case MSR_IA32_BBL_CR_CTL3: 2707 /* This legacy MSR exists but isn't fully documented in current 2708 * silicon. It is however accessed by winxp in very narrow 2709 * scenarios where it sets bit #19, itself documented as 2710 * a "reserved" bit. Best effort attempt to source coherent 2711 * read data here should the balance of the register be 2712 * interpreted by the guest: 2713 * 2714 * L2 cache control register 3: 64GB range, 256KB size, 2715 * enabled, latency 0x1, configured 2716 */ 2717 msr_info->data = 0xbe702111; 2718 break; 2719 case MSR_AMD64_OSVW_ID_LENGTH: 2720 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2721 return 1; 2722 msr_info->data = vcpu->arch.osvw.length; 2723 break; 2724 case MSR_AMD64_OSVW_STATUS: 2725 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2726 return 1; 2727 msr_info->data = vcpu->arch.osvw.status; 2728 break; 2729 case MSR_PLATFORM_INFO: 2730 msr_info->data = vcpu->arch.msr_platform_info; 2731 break; 2732 case MSR_MISC_FEATURES_ENABLES: 2733 msr_info->data = vcpu->arch.msr_misc_features_enables; 2734 break; 2735 default: 2736 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2737 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2738 if (!ignore_msrs) { 2739 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n", 2740 msr_info->index); 2741 return 1; 2742 } else { 2743 if (report_ignored_msrs) 2744 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", 2745 msr_info->index); 2746 msr_info->data = 0; 2747 } 2748 break; 2749 } 2750 return 0; 2751 } 2752 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2753 2754 /* 2755 * Read or write a bunch of msrs. All parameters are kernel addresses. 2756 * 2757 * @return number of msrs set successfully. 2758 */ 2759 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2760 struct kvm_msr_entry *entries, 2761 int (*do_msr)(struct kvm_vcpu *vcpu, 2762 unsigned index, u64 *data)) 2763 { 2764 int i; 2765 2766 for (i = 0; i < msrs->nmsrs; ++i) 2767 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2768 break; 2769 2770 return i; 2771 } 2772 2773 /* 2774 * Read or write a bunch of msrs. Parameters are user addresses. 2775 * 2776 * @return number of msrs set successfully. 2777 */ 2778 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2779 int (*do_msr)(struct kvm_vcpu *vcpu, 2780 unsigned index, u64 *data), 2781 int writeback) 2782 { 2783 struct kvm_msrs msrs; 2784 struct kvm_msr_entry *entries; 2785 int r, n; 2786 unsigned size; 2787 2788 r = -EFAULT; 2789 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2790 goto out; 2791 2792 r = -E2BIG; 2793 if (msrs.nmsrs >= MAX_IO_MSRS) 2794 goto out; 2795 2796 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2797 entries = memdup_user(user_msrs->entries, size); 2798 if (IS_ERR(entries)) { 2799 r = PTR_ERR(entries); 2800 goto out; 2801 } 2802 2803 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2804 if (r < 0) 2805 goto out_free; 2806 2807 r = -EFAULT; 2808 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2809 goto out_free; 2810 2811 r = n; 2812 2813 out_free: 2814 kfree(entries); 2815 out: 2816 return r; 2817 } 2818 2819 static inline bool kvm_can_mwait_in_guest(void) 2820 { 2821 return boot_cpu_has(X86_FEATURE_MWAIT) && 2822 !boot_cpu_has_bug(X86_BUG_MONITOR); 2823 } 2824 2825 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2826 { 2827 int r = 0; 2828 2829 switch (ext) { 2830 case KVM_CAP_IRQCHIP: 2831 case KVM_CAP_HLT: 2832 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2833 case KVM_CAP_SET_TSS_ADDR: 2834 case KVM_CAP_EXT_CPUID: 2835 case KVM_CAP_EXT_EMUL_CPUID: 2836 case KVM_CAP_CLOCKSOURCE: 2837 case KVM_CAP_PIT: 2838 case KVM_CAP_NOP_IO_DELAY: 2839 case KVM_CAP_MP_STATE: 2840 case KVM_CAP_SYNC_MMU: 2841 case KVM_CAP_USER_NMI: 2842 case KVM_CAP_REINJECT_CONTROL: 2843 case KVM_CAP_IRQ_INJECT_STATUS: 2844 case KVM_CAP_IOEVENTFD: 2845 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2846 case KVM_CAP_PIT2: 2847 case KVM_CAP_PIT_STATE2: 2848 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2849 case KVM_CAP_XEN_HVM: 2850 case KVM_CAP_VCPU_EVENTS: 2851 case KVM_CAP_HYPERV: 2852 case KVM_CAP_HYPERV_VAPIC: 2853 case KVM_CAP_HYPERV_SPIN: 2854 case KVM_CAP_HYPERV_SYNIC: 2855 case KVM_CAP_HYPERV_SYNIC2: 2856 case KVM_CAP_HYPERV_VP_INDEX: 2857 case KVM_CAP_HYPERV_EVENTFD: 2858 case KVM_CAP_PCI_SEGMENT: 2859 case KVM_CAP_DEBUGREGS: 2860 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2861 case KVM_CAP_XSAVE: 2862 case KVM_CAP_ASYNC_PF: 2863 case KVM_CAP_GET_TSC_KHZ: 2864 case KVM_CAP_KVMCLOCK_CTRL: 2865 case KVM_CAP_READONLY_MEM: 2866 case KVM_CAP_HYPERV_TIME: 2867 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2868 case KVM_CAP_TSC_DEADLINE_TIMER: 2869 case KVM_CAP_ENABLE_CAP_VM: 2870 case KVM_CAP_DISABLE_QUIRKS: 2871 case KVM_CAP_SET_BOOT_CPU_ID: 2872 case KVM_CAP_SPLIT_IRQCHIP: 2873 case KVM_CAP_IMMEDIATE_EXIT: 2874 case KVM_CAP_GET_MSR_FEATURES: 2875 r = 1; 2876 break; 2877 case KVM_CAP_SYNC_REGS: 2878 r = KVM_SYNC_X86_VALID_FIELDS; 2879 break; 2880 case KVM_CAP_ADJUST_CLOCK: 2881 r = KVM_CLOCK_TSC_STABLE; 2882 break; 2883 case KVM_CAP_X86_DISABLE_EXITS: 2884 r |= KVM_X86_DISABLE_EXITS_HTL | KVM_X86_DISABLE_EXITS_PAUSE; 2885 if(kvm_can_mwait_in_guest()) 2886 r |= KVM_X86_DISABLE_EXITS_MWAIT; 2887 break; 2888 case KVM_CAP_X86_SMM: 2889 /* SMBASE is usually relocated above 1M on modern chipsets, 2890 * and SMM handlers might indeed rely on 4G segment limits, 2891 * so do not report SMM to be available if real mode is 2892 * emulated via vm86 mode. Still, do not go to great lengths 2893 * to avoid userspace's usage of the feature, because it is a 2894 * fringe case that is not enabled except via specific settings 2895 * of the module parameters. 2896 */ 2897 r = kvm_x86_ops->cpu_has_high_real_mode_segbase(); 2898 break; 2899 case KVM_CAP_VAPIC: 2900 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2901 break; 2902 case KVM_CAP_NR_VCPUS: 2903 r = KVM_SOFT_MAX_VCPUS; 2904 break; 2905 case KVM_CAP_MAX_VCPUS: 2906 r = KVM_MAX_VCPUS; 2907 break; 2908 case KVM_CAP_NR_MEMSLOTS: 2909 r = KVM_USER_MEM_SLOTS; 2910 break; 2911 case KVM_CAP_PV_MMU: /* obsolete */ 2912 r = 0; 2913 break; 2914 case KVM_CAP_MCE: 2915 r = KVM_MAX_MCE_BANKS; 2916 break; 2917 case KVM_CAP_XCRS: 2918 r = boot_cpu_has(X86_FEATURE_XSAVE); 2919 break; 2920 case KVM_CAP_TSC_CONTROL: 2921 r = kvm_has_tsc_control; 2922 break; 2923 case KVM_CAP_X2APIC_API: 2924 r = KVM_X2APIC_API_VALID_FLAGS; 2925 break; 2926 default: 2927 break; 2928 } 2929 return r; 2930 2931 } 2932 2933 long kvm_arch_dev_ioctl(struct file *filp, 2934 unsigned int ioctl, unsigned long arg) 2935 { 2936 void __user *argp = (void __user *)arg; 2937 long r; 2938 2939 switch (ioctl) { 2940 case KVM_GET_MSR_INDEX_LIST: { 2941 struct kvm_msr_list __user *user_msr_list = argp; 2942 struct kvm_msr_list msr_list; 2943 unsigned n; 2944 2945 r = -EFAULT; 2946 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2947 goto out; 2948 n = msr_list.nmsrs; 2949 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 2950 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2951 goto out; 2952 r = -E2BIG; 2953 if (n < msr_list.nmsrs) 2954 goto out; 2955 r = -EFAULT; 2956 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2957 num_msrs_to_save * sizeof(u32))) 2958 goto out; 2959 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2960 &emulated_msrs, 2961 num_emulated_msrs * sizeof(u32))) 2962 goto out; 2963 r = 0; 2964 break; 2965 } 2966 case KVM_GET_SUPPORTED_CPUID: 2967 case KVM_GET_EMULATED_CPUID: { 2968 struct kvm_cpuid2 __user *cpuid_arg = argp; 2969 struct kvm_cpuid2 cpuid; 2970 2971 r = -EFAULT; 2972 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2973 goto out; 2974 2975 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2976 ioctl); 2977 if (r) 2978 goto out; 2979 2980 r = -EFAULT; 2981 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2982 goto out; 2983 r = 0; 2984 break; 2985 } 2986 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2987 r = -EFAULT; 2988 if (copy_to_user(argp, &kvm_mce_cap_supported, 2989 sizeof(kvm_mce_cap_supported))) 2990 goto out; 2991 r = 0; 2992 break; 2993 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 2994 struct kvm_msr_list __user *user_msr_list = argp; 2995 struct kvm_msr_list msr_list; 2996 unsigned int n; 2997 2998 r = -EFAULT; 2999 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3000 goto out; 3001 n = msr_list.nmsrs; 3002 msr_list.nmsrs = num_msr_based_features; 3003 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3004 goto out; 3005 r = -E2BIG; 3006 if (n < msr_list.nmsrs) 3007 goto out; 3008 r = -EFAULT; 3009 if (copy_to_user(user_msr_list->indices, &msr_based_features, 3010 num_msr_based_features * sizeof(u32))) 3011 goto out; 3012 r = 0; 3013 break; 3014 } 3015 case KVM_GET_MSRS: 3016 r = msr_io(NULL, argp, do_get_msr_feature, 1); 3017 break; 3018 } 3019 default: 3020 r = -EINVAL; 3021 } 3022 out: 3023 return r; 3024 } 3025 3026 static void wbinvd_ipi(void *garbage) 3027 { 3028 wbinvd(); 3029 } 3030 3031 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 3032 { 3033 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 3034 } 3035 3036 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 3037 { 3038 /* Address WBINVD may be executed by guest */ 3039 if (need_emulate_wbinvd(vcpu)) { 3040 if (kvm_x86_ops->has_wbinvd_exit()) 3041 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 3042 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 3043 smp_call_function_single(vcpu->cpu, 3044 wbinvd_ipi, NULL, 1); 3045 } 3046 3047 kvm_x86_ops->vcpu_load(vcpu, cpu); 3048 3049 /* Apply any externally detected TSC adjustments (due to suspend) */ 3050 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 3051 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 3052 vcpu->arch.tsc_offset_adjustment = 0; 3053 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3054 } 3055 3056 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 3057 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 3058 rdtsc() - vcpu->arch.last_host_tsc; 3059 if (tsc_delta < 0) 3060 mark_tsc_unstable("KVM discovered backwards TSC"); 3061 3062 if (kvm_check_tsc_unstable()) { 3063 u64 offset = kvm_compute_tsc_offset(vcpu, 3064 vcpu->arch.last_guest_tsc); 3065 kvm_vcpu_write_tsc_offset(vcpu, offset); 3066 vcpu->arch.tsc_catchup = 1; 3067 } 3068 3069 if (kvm_lapic_hv_timer_in_use(vcpu)) 3070 kvm_lapic_restart_hv_timer(vcpu); 3071 3072 /* 3073 * On a host with synchronized TSC, there is no need to update 3074 * kvmclock on vcpu->cpu migration 3075 */ 3076 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 3077 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 3078 if (vcpu->cpu != cpu) 3079 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 3080 vcpu->cpu = cpu; 3081 } 3082 3083 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3084 } 3085 3086 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 3087 { 3088 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3089 return; 3090 3091 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED; 3092 3093 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime, 3094 &vcpu->arch.st.steal.preempted, 3095 offsetof(struct kvm_steal_time, preempted), 3096 sizeof(vcpu->arch.st.steal.preempted)); 3097 } 3098 3099 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 3100 { 3101 int idx; 3102 3103 if (vcpu->preempted) 3104 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu); 3105 3106 /* 3107 * Disable page faults because we're in atomic context here. 3108 * kvm_write_guest_offset_cached() would call might_fault() 3109 * that relies on pagefault_disable() to tell if there's a 3110 * bug. NOTE: the write to guest memory may not go through if 3111 * during postcopy live migration or if there's heavy guest 3112 * paging. 3113 */ 3114 pagefault_disable(); 3115 /* 3116 * kvm_memslots() will be called by 3117 * kvm_write_guest_offset_cached() so take the srcu lock. 3118 */ 3119 idx = srcu_read_lock(&vcpu->kvm->srcu); 3120 kvm_steal_time_set_preempted(vcpu); 3121 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3122 pagefault_enable(); 3123 kvm_x86_ops->vcpu_put(vcpu); 3124 vcpu->arch.last_host_tsc = rdtsc(); 3125 /* 3126 * If userspace has set any breakpoints or watchpoints, dr6 is restored 3127 * on every vmexit, but if not, we might have a stale dr6 from the 3128 * guest. do_debug expects dr6 to be cleared after it runs, do the same. 3129 */ 3130 set_debugreg(0, 6); 3131 } 3132 3133 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 3134 struct kvm_lapic_state *s) 3135 { 3136 if (vcpu->arch.apicv_active) 3137 kvm_x86_ops->sync_pir_to_irr(vcpu); 3138 3139 return kvm_apic_get_state(vcpu, s); 3140 } 3141 3142 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 3143 struct kvm_lapic_state *s) 3144 { 3145 int r; 3146 3147 r = kvm_apic_set_state(vcpu, s); 3148 if (r) 3149 return r; 3150 update_cr8_intercept(vcpu); 3151 3152 return 0; 3153 } 3154 3155 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 3156 { 3157 return (!lapic_in_kernel(vcpu) || 3158 kvm_apic_accept_pic_intr(vcpu)); 3159 } 3160 3161 /* 3162 * if userspace requested an interrupt window, check that the 3163 * interrupt window is open. 3164 * 3165 * No need to exit to userspace if we already have an interrupt queued. 3166 */ 3167 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 3168 { 3169 return kvm_arch_interrupt_allowed(vcpu) && 3170 !kvm_cpu_has_interrupt(vcpu) && 3171 !kvm_event_needs_reinjection(vcpu) && 3172 kvm_cpu_accept_dm_intr(vcpu); 3173 } 3174 3175 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 3176 struct kvm_interrupt *irq) 3177 { 3178 if (irq->irq >= KVM_NR_INTERRUPTS) 3179 return -EINVAL; 3180 3181 if (!irqchip_in_kernel(vcpu->kvm)) { 3182 kvm_queue_interrupt(vcpu, irq->irq, false); 3183 kvm_make_request(KVM_REQ_EVENT, vcpu); 3184 return 0; 3185 } 3186 3187 /* 3188 * With in-kernel LAPIC, we only use this to inject EXTINT, so 3189 * fail for in-kernel 8259. 3190 */ 3191 if (pic_in_kernel(vcpu->kvm)) 3192 return -ENXIO; 3193 3194 if (vcpu->arch.pending_external_vector != -1) 3195 return -EEXIST; 3196 3197 vcpu->arch.pending_external_vector = irq->irq; 3198 kvm_make_request(KVM_REQ_EVENT, vcpu); 3199 return 0; 3200 } 3201 3202 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 3203 { 3204 kvm_inject_nmi(vcpu); 3205 3206 return 0; 3207 } 3208 3209 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 3210 { 3211 kvm_make_request(KVM_REQ_SMI, vcpu); 3212 3213 return 0; 3214 } 3215 3216 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 3217 struct kvm_tpr_access_ctl *tac) 3218 { 3219 if (tac->flags) 3220 return -EINVAL; 3221 vcpu->arch.tpr_access_reporting = !!tac->enabled; 3222 return 0; 3223 } 3224 3225 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 3226 u64 mcg_cap) 3227 { 3228 int r; 3229 unsigned bank_num = mcg_cap & 0xff, bank; 3230 3231 r = -EINVAL; 3232 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 3233 goto out; 3234 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 3235 goto out; 3236 r = 0; 3237 vcpu->arch.mcg_cap = mcg_cap; 3238 /* Init IA32_MCG_CTL to all 1s */ 3239 if (mcg_cap & MCG_CTL_P) 3240 vcpu->arch.mcg_ctl = ~(u64)0; 3241 /* Init IA32_MCi_CTL to all 1s */ 3242 for (bank = 0; bank < bank_num; bank++) 3243 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 3244 3245 if (kvm_x86_ops->setup_mce) 3246 kvm_x86_ops->setup_mce(vcpu); 3247 out: 3248 return r; 3249 } 3250 3251 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 3252 struct kvm_x86_mce *mce) 3253 { 3254 u64 mcg_cap = vcpu->arch.mcg_cap; 3255 unsigned bank_num = mcg_cap & 0xff; 3256 u64 *banks = vcpu->arch.mce_banks; 3257 3258 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 3259 return -EINVAL; 3260 /* 3261 * if IA32_MCG_CTL is not all 1s, the uncorrected error 3262 * reporting is disabled 3263 */ 3264 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 3265 vcpu->arch.mcg_ctl != ~(u64)0) 3266 return 0; 3267 banks += 4 * mce->bank; 3268 /* 3269 * if IA32_MCi_CTL is not all 1s, the uncorrected error 3270 * reporting is disabled for the bank 3271 */ 3272 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 3273 return 0; 3274 if (mce->status & MCI_STATUS_UC) { 3275 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 3276 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 3277 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 3278 return 0; 3279 } 3280 if (banks[1] & MCI_STATUS_VAL) 3281 mce->status |= MCI_STATUS_OVER; 3282 banks[2] = mce->addr; 3283 banks[3] = mce->misc; 3284 vcpu->arch.mcg_status = mce->mcg_status; 3285 banks[1] = mce->status; 3286 kvm_queue_exception(vcpu, MC_VECTOR); 3287 } else if (!(banks[1] & MCI_STATUS_VAL) 3288 || !(banks[1] & MCI_STATUS_UC)) { 3289 if (banks[1] & MCI_STATUS_VAL) 3290 mce->status |= MCI_STATUS_OVER; 3291 banks[2] = mce->addr; 3292 banks[3] = mce->misc; 3293 banks[1] = mce->status; 3294 } else 3295 banks[1] |= MCI_STATUS_OVER; 3296 return 0; 3297 } 3298 3299 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 3300 struct kvm_vcpu_events *events) 3301 { 3302 process_nmi(vcpu); 3303 /* 3304 * FIXME: pass injected and pending separately. This is only 3305 * needed for nested virtualization, whose state cannot be 3306 * migrated yet. For now we can combine them. 3307 */ 3308 events->exception.injected = 3309 (vcpu->arch.exception.pending || 3310 vcpu->arch.exception.injected) && 3311 !kvm_exception_is_soft(vcpu->arch.exception.nr); 3312 events->exception.nr = vcpu->arch.exception.nr; 3313 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 3314 events->exception.pad = 0; 3315 events->exception.error_code = vcpu->arch.exception.error_code; 3316 3317 events->interrupt.injected = 3318 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 3319 events->interrupt.nr = vcpu->arch.interrupt.nr; 3320 events->interrupt.soft = 0; 3321 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 3322 3323 events->nmi.injected = vcpu->arch.nmi_injected; 3324 events->nmi.pending = vcpu->arch.nmi_pending != 0; 3325 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 3326 events->nmi.pad = 0; 3327 3328 events->sipi_vector = 0; /* never valid when reporting to user space */ 3329 3330 events->smi.smm = is_smm(vcpu); 3331 events->smi.pending = vcpu->arch.smi_pending; 3332 events->smi.smm_inside_nmi = 3333 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 3334 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 3335 3336 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 3337 | KVM_VCPUEVENT_VALID_SHADOW 3338 | KVM_VCPUEVENT_VALID_SMM); 3339 memset(&events->reserved, 0, sizeof(events->reserved)); 3340 } 3341 3342 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags); 3343 3344 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 3345 struct kvm_vcpu_events *events) 3346 { 3347 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 3348 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 3349 | KVM_VCPUEVENT_VALID_SHADOW 3350 | KVM_VCPUEVENT_VALID_SMM)) 3351 return -EINVAL; 3352 3353 if (events->exception.injected && 3354 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR || 3355 is_guest_mode(vcpu))) 3356 return -EINVAL; 3357 3358 /* INITs are latched while in SMM */ 3359 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 3360 (events->smi.smm || events->smi.pending) && 3361 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 3362 return -EINVAL; 3363 3364 process_nmi(vcpu); 3365 vcpu->arch.exception.injected = false; 3366 vcpu->arch.exception.pending = events->exception.injected; 3367 vcpu->arch.exception.nr = events->exception.nr; 3368 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 3369 vcpu->arch.exception.error_code = events->exception.error_code; 3370 3371 vcpu->arch.interrupt.injected = events->interrupt.injected; 3372 vcpu->arch.interrupt.nr = events->interrupt.nr; 3373 vcpu->arch.interrupt.soft = events->interrupt.soft; 3374 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3375 kvm_x86_ops->set_interrupt_shadow(vcpu, 3376 events->interrupt.shadow); 3377 3378 vcpu->arch.nmi_injected = events->nmi.injected; 3379 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3380 vcpu->arch.nmi_pending = events->nmi.pending; 3381 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 3382 3383 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3384 lapic_in_kernel(vcpu)) 3385 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3386 3387 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 3388 u32 hflags = vcpu->arch.hflags; 3389 if (events->smi.smm) 3390 hflags |= HF_SMM_MASK; 3391 else 3392 hflags &= ~HF_SMM_MASK; 3393 kvm_set_hflags(vcpu, hflags); 3394 3395 vcpu->arch.smi_pending = events->smi.pending; 3396 3397 if (events->smi.smm) { 3398 if (events->smi.smm_inside_nmi) 3399 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 3400 else 3401 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 3402 if (lapic_in_kernel(vcpu)) { 3403 if (events->smi.latched_init) 3404 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3405 else 3406 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3407 } 3408 } 3409 } 3410 3411 kvm_make_request(KVM_REQ_EVENT, vcpu); 3412 3413 return 0; 3414 } 3415 3416 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3417 struct kvm_debugregs *dbgregs) 3418 { 3419 unsigned long val; 3420 3421 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3422 kvm_get_dr(vcpu, 6, &val); 3423 dbgregs->dr6 = val; 3424 dbgregs->dr7 = vcpu->arch.dr7; 3425 dbgregs->flags = 0; 3426 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3427 } 3428 3429 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3430 struct kvm_debugregs *dbgregs) 3431 { 3432 if (dbgregs->flags) 3433 return -EINVAL; 3434 3435 if (dbgregs->dr6 & ~0xffffffffull) 3436 return -EINVAL; 3437 if (dbgregs->dr7 & ~0xffffffffull) 3438 return -EINVAL; 3439 3440 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3441 kvm_update_dr0123(vcpu); 3442 vcpu->arch.dr6 = dbgregs->dr6; 3443 kvm_update_dr6(vcpu); 3444 vcpu->arch.dr7 = dbgregs->dr7; 3445 kvm_update_dr7(vcpu); 3446 3447 return 0; 3448 } 3449 3450 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3451 3452 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3453 { 3454 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3455 u64 xstate_bv = xsave->header.xfeatures; 3456 u64 valid; 3457 3458 /* 3459 * Copy legacy XSAVE area, to avoid complications with CPUID 3460 * leaves 0 and 1 in the loop below. 3461 */ 3462 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3463 3464 /* Set XSTATE_BV */ 3465 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; 3466 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3467 3468 /* 3469 * Copy each region from the possibly compacted offset to the 3470 * non-compacted offset. 3471 */ 3472 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3473 while (valid) { 3474 u64 feature = valid & -valid; 3475 int index = fls64(feature) - 1; 3476 void *src = get_xsave_addr(xsave, feature); 3477 3478 if (src) { 3479 u32 size, offset, ecx, edx; 3480 cpuid_count(XSTATE_CPUID, index, 3481 &size, &offset, &ecx, &edx); 3482 if (feature == XFEATURE_MASK_PKRU) 3483 memcpy(dest + offset, &vcpu->arch.pkru, 3484 sizeof(vcpu->arch.pkru)); 3485 else 3486 memcpy(dest + offset, src, size); 3487 3488 } 3489 3490 valid -= feature; 3491 } 3492 } 3493 3494 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3495 { 3496 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3497 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3498 u64 valid; 3499 3500 /* 3501 * Copy legacy XSAVE area, to avoid complications with CPUID 3502 * leaves 0 and 1 in the loop below. 3503 */ 3504 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3505 3506 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3507 xsave->header.xfeatures = xstate_bv; 3508 if (boot_cpu_has(X86_FEATURE_XSAVES)) 3509 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3510 3511 /* 3512 * Copy each region from the non-compacted offset to the 3513 * possibly compacted offset. 3514 */ 3515 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3516 while (valid) { 3517 u64 feature = valid & -valid; 3518 int index = fls64(feature) - 1; 3519 void *dest = get_xsave_addr(xsave, feature); 3520 3521 if (dest) { 3522 u32 size, offset, ecx, edx; 3523 cpuid_count(XSTATE_CPUID, index, 3524 &size, &offset, &ecx, &edx); 3525 if (feature == XFEATURE_MASK_PKRU) 3526 memcpy(&vcpu->arch.pkru, src + offset, 3527 sizeof(vcpu->arch.pkru)); 3528 else 3529 memcpy(dest, src + offset, size); 3530 } 3531 3532 valid -= feature; 3533 } 3534 } 3535 3536 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3537 struct kvm_xsave *guest_xsave) 3538 { 3539 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3540 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3541 fill_xsave((u8 *) guest_xsave->region, vcpu); 3542 } else { 3543 memcpy(guest_xsave->region, 3544 &vcpu->arch.guest_fpu.state.fxsave, 3545 sizeof(struct fxregs_state)); 3546 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3547 XFEATURE_MASK_FPSSE; 3548 } 3549 } 3550 3551 #define XSAVE_MXCSR_OFFSET 24 3552 3553 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3554 struct kvm_xsave *guest_xsave) 3555 { 3556 u64 xstate_bv = 3557 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3558 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; 3559 3560 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3561 /* 3562 * Here we allow setting states that are not present in 3563 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3564 * with old userspace. 3565 */ 3566 if (xstate_bv & ~kvm_supported_xcr0() || 3567 mxcsr & ~mxcsr_feature_mask) 3568 return -EINVAL; 3569 load_xsave(vcpu, (u8 *)guest_xsave->region); 3570 } else { 3571 if (xstate_bv & ~XFEATURE_MASK_FPSSE || 3572 mxcsr & ~mxcsr_feature_mask) 3573 return -EINVAL; 3574 memcpy(&vcpu->arch.guest_fpu.state.fxsave, 3575 guest_xsave->region, sizeof(struct fxregs_state)); 3576 } 3577 return 0; 3578 } 3579 3580 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3581 struct kvm_xcrs *guest_xcrs) 3582 { 3583 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 3584 guest_xcrs->nr_xcrs = 0; 3585 return; 3586 } 3587 3588 guest_xcrs->nr_xcrs = 1; 3589 guest_xcrs->flags = 0; 3590 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3591 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3592 } 3593 3594 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3595 struct kvm_xcrs *guest_xcrs) 3596 { 3597 int i, r = 0; 3598 3599 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 3600 return -EINVAL; 3601 3602 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3603 return -EINVAL; 3604 3605 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3606 /* Only support XCR0 currently */ 3607 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3608 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3609 guest_xcrs->xcrs[i].value); 3610 break; 3611 } 3612 if (r) 3613 r = -EINVAL; 3614 return r; 3615 } 3616 3617 /* 3618 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3619 * stopped by the hypervisor. This function will be called from the host only. 3620 * EINVAL is returned when the host attempts to set the flag for a guest that 3621 * does not support pv clocks. 3622 */ 3623 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3624 { 3625 if (!vcpu->arch.pv_time_enabled) 3626 return -EINVAL; 3627 vcpu->arch.pvclock_set_guest_stopped_request = true; 3628 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3629 return 0; 3630 } 3631 3632 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 3633 struct kvm_enable_cap *cap) 3634 { 3635 if (cap->flags) 3636 return -EINVAL; 3637 3638 switch (cap->cap) { 3639 case KVM_CAP_HYPERV_SYNIC2: 3640 if (cap->args[0]) 3641 return -EINVAL; 3642 case KVM_CAP_HYPERV_SYNIC: 3643 if (!irqchip_in_kernel(vcpu->kvm)) 3644 return -EINVAL; 3645 return kvm_hv_activate_synic(vcpu, cap->cap == 3646 KVM_CAP_HYPERV_SYNIC2); 3647 default: 3648 return -EINVAL; 3649 } 3650 } 3651 3652 long kvm_arch_vcpu_ioctl(struct file *filp, 3653 unsigned int ioctl, unsigned long arg) 3654 { 3655 struct kvm_vcpu *vcpu = filp->private_data; 3656 void __user *argp = (void __user *)arg; 3657 int r; 3658 union { 3659 struct kvm_lapic_state *lapic; 3660 struct kvm_xsave *xsave; 3661 struct kvm_xcrs *xcrs; 3662 void *buffer; 3663 } u; 3664 3665 vcpu_load(vcpu); 3666 3667 u.buffer = NULL; 3668 switch (ioctl) { 3669 case KVM_GET_LAPIC: { 3670 r = -EINVAL; 3671 if (!lapic_in_kernel(vcpu)) 3672 goto out; 3673 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3674 3675 r = -ENOMEM; 3676 if (!u.lapic) 3677 goto out; 3678 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3679 if (r) 3680 goto out; 3681 r = -EFAULT; 3682 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3683 goto out; 3684 r = 0; 3685 break; 3686 } 3687 case KVM_SET_LAPIC: { 3688 r = -EINVAL; 3689 if (!lapic_in_kernel(vcpu)) 3690 goto out; 3691 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3692 if (IS_ERR(u.lapic)) { 3693 r = PTR_ERR(u.lapic); 3694 goto out_nofree; 3695 } 3696 3697 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3698 break; 3699 } 3700 case KVM_INTERRUPT: { 3701 struct kvm_interrupt irq; 3702 3703 r = -EFAULT; 3704 if (copy_from_user(&irq, argp, sizeof irq)) 3705 goto out; 3706 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3707 break; 3708 } 3709 case KVM_NMI: { 3710 r = kvm_vcpu_ioctl_nmi(vcpu); 3711 break; 3712 } 3713 case KVM_SMI: { 3714 r = kvm_vcpu_ioctl_smi(vcpu); 3715 break; 3716 } 3717 case KVM_SET_CPUID: { 3718 struct kvm_cpuid __user *cpuid_arg = argp; 3719 struct kvm_cpuid cpuid; 3720 3721 r = -EFAULT; 3722 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3723 goto out; 3724 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3725 break; 3726 } 3727 case KVM_SET_CPUID2: { 3728 struct kvm_cpuid2 __user *cpuid_arg = argp; 3729 struct kvm_cpuid2 cpuid; 3730 3731 r = -EFAULT; 3732 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3733 goto out; 3734 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3735 cpuid_arg->entries); 3736 break; 3737 } 3738 case KVM_GET_CPUID2: { 3739 struct kvm_cpuid2 __user *cpuid_arg = argp; 3740 struct kvm_cpuid2 cpuid; 3741 3742 r = -EFAULT; 3743 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3744 goto out; 3745 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3746 cpuid_arg->entries); 3747 if (r) 3748 goto out; 3749 r = -EFAULT; 3750 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3751 goto out; 3752 r = 0; 3753 break; 3754 } 3755 case KVM_GET_MSRS: { 3756 int idx = srcu_read_lock(&vcpu->kvm->srcu); 3757 r = msr_io(vcpu, argp, do_get_msr, 1); 3758 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3759 break; 3760 } 3761 case KVM_SET_MSRS: { 3762 int idx = srcu_read_lock(&vcpu->kvm->srcu); 3763 r = msr_io(vcpu, argp, do_set_msr, 0); 3764 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3765 break; 3766 } 3767 case KVM_TPR_ACCESS_REPORTING: { 3768 struct kvm_tpr_access_ctl tac; 3769 3770 r = -EFAULT; 3771 if (copy_from_user(&tac, argp, sizeof tac)) 3772 goto out; 3773 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3774 if (r) 3775 goto out; 3776 r = -EFAULT; 3777 if (copy_to_user(argp, &tac, sizeof tac)) 3778 goto out; 3779 r = 0; 3780 break; 3781 }; 3782 case KVM_SET_VAPIC_ADDR: { 3783 struct kvm_vapic_addr va; 3784 int idx; 3785 3786 r = -EINVAL; 3787 if (!lapic_in_kernel(vcpu)) 3788 goto out; 3789 r = -EFAULT; 3790 if (copy_from_user(&va, argp, sizeof va)) 3791 goto out; 3792 idx = srcu_read_lock(&vcpu->kvm->srcu); 3793 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3794 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3795 break; 3796 } 3797 case KVM_X86_SETUP_MCE: { 3798 u64 mcg_cap; 3799 3800 r = -EFAULT; 3801 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3802 goto out; 3803 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3804 break; 3805 } 3806 case KVM_X86_SET_MCE: { 3807 struct kvm_x86_mce mce; 3808 3809 r = -EFAULT; 3810 if (copy_from_user(&mce, argp, sizeof mce)) 3811 goto out; 3812 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3813 break; 3814 } 3815 case KVM_GET_VCPU_EVENTS: { 3816 struct kvm_vcpu_events events; 3817 3818 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3819 3820 r = -EFAULT; 3821 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3822 break; 3823 r = 0; 3824 break; 3825 } 3826 case KVM_SET_VCPU_EVENTS: { 3827 struct kvm_vcpu_events events; 3828 3829 r = -EFAULT; 3830 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3831 break; 3832 3833 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3834 break; 3835 } 3836 case KVM_GET_DEBUGREGS: { 3837 struct kvm_debugregs dbgregs; 3838 3839 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3840 3841 r = -EFAULT; 3842 if (copy_to_user(argp, &dbgregs, 3843 sizeof(struct kvm_debugregs))) 3844 break; 3845 r = 0; 3846 break; 3847 } 3848 case KVM_SET_DEBUGREGS: { 3849 struct kvm_debugregs dbgregs; 3850 3851 r = -EFAULT; 3852 if (copy_from_user(&dbgregs, argp, 3853 sizeof(struct kvm_debugregs))) 3854 break; 3855 3856 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3857 break; 3858 } 3859 case KVM_GET_XSAVE: { 3860 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3861 r = -ENOMEM; 3862 if (!u.xsave) 3863 break; 3864 3865 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3866 3867 r = -EFAULT; 3868 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3869 break; 3870 r = 0; 3871 break; 3872 } 3873 case KVM_SET_XSAVE: { 3874 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3875 if (IS_ERR(u.xsave)) { 3876 r = PTR_ERR(u.xsave); 3877 goto out_nofree; 3878 } 3879 3880 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3881 break; 3882 } 3883 case KVM_GET_XCRS: { 3884 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3885 r = -ENOMEM; 3886 if (!u.xcrs) 3887 break; 3888 3889 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3890 3891 r = -EFAULT; 3892 if (copy_to_user(argp, u.xcrs, 3893 sizeof(struct kvm_xcrs))) 3894 break; 3895 r = 0; 3896 break; 3897 } 3898 case KVM_SET_XCRS: { 3899 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3900 if (IS_ERR(u.xcrs)) { 3901 r = PTR_ERR(u.xcrs); 3902 goto out_nofree; 3903 } 3904 3905 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3906 break; 3907 } 3908 case KVM_SET_TSC_KHZ: { 3909 u32 user_tsc_khz; 3910 3911 r = -EINVAL; 3912 user_tsc_khz = (u32)arg; 3913 3914 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3915 goto out; 3916 3917 if (user_tsc_khz == 0) 3918 user_tsc_khz = tsc_khz; 3919 3920 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 3921 r = 0; 3922 3923 goto out; 3924 } 3925 case KVM_GET_TSC_KHZ: { 3926 r = vcpu->arch.virtual_tsc_khz; 3927 goto out; 3928 } 3929 case KVM_KVMCLOCK_CTRL: { 3930 r = kvm_set_guest_paused(vcpu); 3931 goto out; 3932 } 3933 case KVM_ENABLE_CAP: { 3934 struct kvm_enable_cap cap; 3935 3936 r = -EFAULT; 3937 if (copy_from_user(&cap, argp, sizeof(cap))) 3938 goto out; 3939 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 3940 break; 3941 } 3942 default: 3943 r = -EINVAL; 3944 } 3945 out: 3946 kfree(u.buffer); 3947 out_nofree: 3948 vcpu_put(vcpu); 3949 return r; 3950 } 3951 3952 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3953 { 3954 return VM_FAULT_SIGBUS; 3955 } 3956 3957 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3958 { 3959 int ret; 3960 3961 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3962 return -EINVAL; 3963 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3964 return ret; 3965 } 3966 3967 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3968 u64 ident_addr) 3969 { 3970 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr); 3971 } 3972 3973 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3974 u32 kvm_nr_mmu_pages) 3975 { 3976 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3977 return -EINVAL; 3978 3979 mutex_lock(&kvm->slots_lock); 3980 3981 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3982 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3983 3984 mutex_unlock(&kvm->slots_lock); 3985 return 0; 3986 } 3987 3988 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 3989 { 3990 return kvm->arch.n_max_mmu_pages; 3991 } 3992 3993 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3994 { 3995 struct kvm_pic *pic = kvm->arch.vpic; 3996 int r; 3997 3998 r = 0; 3999 switch (chip->chip_id) { 4000 case KVM_IRQCHIP_PIC_MASTER: 4001 memcpy(&chip->chip.pic, &pic->pics[0], 4002 sizeof(struct kvm_pic_state)); 4003 break; 4004 case KVM_IRQCHIP_PIC_SLAVE: 4005 memcpy(&chip->chip.pic, &pic->pics[1], 4006 sizeof(struct kvm_pic_state)); 4007 break; 4008 case KVM_IRQCHIP_IOAPIC: 4009 kvm_get_ioapic(kvm, &chip->chip.ioapic); 4010 break; 4011 default: 4012 r = -EINVAL; 4013 break; 4014 } 4015 return r; 4016 } 4017 4018 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 4019 { 4020 struct kvm_pic *pic = kvm->arch.vpic; 4021 int r; 4022 4023 r = 0; 4024 switch (chip->chip_id) { 4025 case KVM_IRQCHIP_PIC_MASTER: 4026 spin_lock(&pic->lock); 4027 memcpy(&pic->pics[0], &chip->chip.pic, 4028 sizeof(struct kvm_pic_state)); 4029 spin_unlock(&pic->lock); 4030 break; 4031 case KVM_IRQCHIP_PIC_SLAVE: 4032 spin_lock(&pic->lock); 4033 memcpy(&pic->pics[1], &chip->chip.pic, 4034 sizeof(struct kvm_pic_state)); 4035 spin_unlock(&pic->lock); 4036 break; 4037 case KVM_IRQCHIP_IOAPIC: 4038 kvm_set_ioapic(kvm, &chip->chip.ioapic); 4039 break; 4040 default: 4041 r = -EINVAL; 4042 break; 4043 } 4044 kvm_pic_update_irq(pic); 4045 return r; 4046 } 4047 4048 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 4049 { 4050 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 4051 4052 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 4053 4054 mutex_lock(&kps->lock); 4055 memcpy(ps, &kps->channels, sizeof(*ps)); 4056 mutex_unlock(&kps->lock); 4057 return 0; 4058 } 4059 4060 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 4061 { 4062 int i; 4063 struct kvm_pit *pit = kvm->arch.vpit; 4064 4065 mutex_lock(&pit->pit_state.lock); 4066 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 4067 for (i = 0; i < 3; i++) 4068 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 4069 mutex_unlock(&pit->pit_state.lock); 4070 return 0; 4071 } 4072 4073 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 4074 { 4075 mutex_lock(&kvm->arch.vpit->pit_state.lock); 4076 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 4077 sizeof(ps->channels)); 4078 ps->flags = kvm->arch.vpit->pit_state.flags; 4079 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 4080 memset(&ps->reserved, 0, sizeof(ps->reserved)); 4081 return 0; 4082 } 4083 4084 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 4085 { 4086 int start = 0; 4087 int i; 4088 u32 prev_legacy, cur_legacy; 4089 struct kvm_pit *pit = kvm->arch.vpit; 4090 4091 mutex_lock(&pit->pit_state.lock); 4092 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 4093 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 4094 if (!prev_legacy && cur_legacy) 4095 start = 1; 4096 memcpy(&pit->pit_state.channels, &ps->channels, 4097 sizeof(pit->pit_state.channels)); 4098 pit->pit_state.flags = ps->flags; 4099 for (i = 0; i < 3; i++) 4100 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 4101 start && i == 0); 4102 mutex_unlock(&pit->pit_state.lock); 4103 return 0; 4104 } 4105 4106 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 4107 struct kvm_reinject_control *control) 4108 { 4109 struct kvm_pit *pit = kvm->arch.vpit; 4110 4111 if (!pit) 4112 return -ENXIO; 4113 4114 /* pit->pit_state.lock was overloaded to prevent userspace from getting 4115 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 4116 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 4117 */ 4118 mutex_lock(&pit->pit_state.lock); 4119 kvm_pit_set_reinject(pit, control->pit_reinject); 4120 mutex_unlock(&pit->pit_state.lock); 4121 4122 return 0; 4123 } 4124 4125 /** 4126 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 4127 * @kvm: kvm instance 4128 * @log: slot id and address to which we copy the log 4129 * 4130 * Steps 1-4 below provide general overview of dirty page logging. See 4131 * kvm_get_dirty_log_protect() function description for additional details. 4132 * 4133 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 4134 * always flush the TLB (step 4) even if previous step failed and the dirty 4135 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 4136 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 4137 * writes will be marked dirty for next log read. 4138 * 4139 * 1. Take a snapshot of the bit and clear it if needed. 4140 * 2. Write protect the corresponding page. 4141 * 3. Copy the snapshot to the userspace. 4142 * 4. Flush TLB's if needed. 4143 */ 4144 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 4145 { 4146 bool is_dirty = false; 4147 int r; 4148 4149 mutex_lock(&kvm->slots_lock); 4150 4151 /* 4152 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 4153 */ 4154 if (kvm_x86_ops->flush_log_dirty) 4155 kvm_x86_ops->flush_log_dirty(kvm); 4156 4157 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 4158 4159 /* 4160 * All the TLBs can be flushed out of mmu lock, see the comments in 4161 * kvm_mmu_slot_remove_write_access(). 4162 */ 4163 lockdep_assert_held(&kvm->slots_lock); 4164 if (is_dirty) 4165 kvm_flush_remote_tlbs(kvm); 4166 4167 mutex_unlock(&kvm->slots_lock); 4168 return r; 4169 } 4170 4171 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 4172 bool line_status) 4173 { 4174 if (!irqchip_in_kernel(kvm)) 4175 return -ENXIO; 4176 4177 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 4178 irq_event->irq, irq_event->level, 4179 line_status); 4180 return 0; 4181 } 4182 4183 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 4184 struct kvm_enable_cap *cap) 4185 { 4186 int r; 4187 4188 if (cap->flags) 4189 return -EINVAL; 4190 4191 switch (cap->cap) { 4192 case KVM_CAP_DISABLE_QUIRKS: 4193 kvm->arch.disabled_quirks = cap->args[0]; 4194 r = 0; 4195 break; 4196 case KVM_CAP_SPLIT_IRQCHIP: { 4197 mutex_lock(&kvm->lock); 4198 r = -EINVAL; 4199 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 4200 goto split_irqchip_unlock; 4201 r = -EEXIST; 4202 if (irqchip_in_kernel(kvm)) 4203 goto split_irqchip_unlock; 4204 if (kvm->created_vcpus) 4205 goto split_irqchip_unlock; 4206 r = kvm_setup_empty_irq_routing(kvm); 4207 if (r) 4208 goto split_irqchip_unlock; 4209 /* Pairs with irqchip_in_kernel. */ 4210 smp_wmb(); 4211 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 4212 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 4213 r = 0; 4214 split_irqchip_unlock: 4215 mutex_unlock(&kvm->lock); 4216 break; 4217 } 4218 case KVM_CAP_X2APIC_API: 4219 r = -EINVAL; 4220 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 4221 break; 4222 4223 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 4224 kvm->arch.x2apic_format = true; 4225 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 4226 kvm->arch.x2apic_broadcast_quirk_disabled = true; 4227 4228 r = 0; 4229 break; 4230 case KVM_CAP_X86_DISABLE_EXITS: 4231 r = -EINVAL; 4232 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 4233 break; 4234 4235 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 4236 kvm_can_mwait_in_guest()) 4237 kvm->arch.mwait_in_guest = true; 4238 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HTL) 4239 kvm->arch.hlt_in_guest = true; 4240 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 4241 kvm->arch.pause_in_guest = true; 4242 r = 0; 4243 break; 4244 default: 4245 r = -EINVAL; 4246 break; 4247 } 4248 return r; 4249 } 4250 4251 long kvm_arch_vm_ioctl(struct file *filp, 4252 unsigned int ioctl, unsigned long arg) 4253 { 4254 struct kvm *kvm = filp->private_data; 4255 void __user *argp = (void __user *)arg; 4256 int r = -ENOTTY; 4257 /* 4258 * This union makes it completely explicit to gcc-3.x 4259 * that these two variables' stack usage should be 4260 * combined, not added together. 4261 */ 4262 union { 4263 struct kvm_pit_state ps; 4264 struct kvm_pit_state2 ps2; 4265 struct kvm_pit_config pit_config; 4266 } u; 4267 4268 switch (ioctl) { 4269 case KVM_SET_TSS_ADDR: 4270 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 4271 break; 4272 case KVM_SET_IDENTITY_MAP_ADDR: { 4273 u64 ident_addr; 4274 4275 mutex_lock(&kvm->lock); 4276 r = -EINVAL; 4277 if (kvm->created_vcpus) 4278 goto set_identity_unlock; 4279 r = -EFAULT; 4280 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 4281 goto set_identity_unlock; 4282 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 4283 set_identity_unlock: 4284 mutex_unlock(&kvm->lock); 4285 break; 4286 } 4287 case KVM_SET_NR_MMU_PAGES: 4288 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 4289 break; 4290 case KVM_GET_NR_MMU_PAGES: 4291 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 4292 break; 4293 case KVM_CREATE_IRQCHIP: { 4294 mutex_lock(&kvm->lock); 4295 4296 r = -EEXIST; 4297 if (irqchip_in_kernel(kvm)) 4298 goto create_irqchip_unlock; 4299 4300 r = -EINVAL; 4301 if (kvm->created_vcpus) 4302 goto create_irqchip_unlock; 4303 4304 r = kvm_pic_init(kvm); 4305 if (r) 4306 goto create_irqchip_unlock; 4307 4308 r = kvm_ioapic_init(kvm); 4309 if (r) { 4310 kvm_pic_destroy(kvm); 4311 goto create_irqchip_unlock; 4312 } 4313 4314 r = kvm_setup_default_irq_routing(kvm); 4315 if (r) { 4316 kvm_ioapic_destroy(kvm); 4317 kvm_pic_destroy(kvm); 4318 goto create_irqchip_unlock; 4319 } 4320 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 4321 smp_wmb(); 4322 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 4323 create_irqchip_unlock: 4324 mutex_unlock(&kvm->lock); 4325 break; 4326 } 4327 case KVM_CREATE_PIT: 4328 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 4329 goto create_pit; 4330 case KVM_CREATE_PIT2: 4331 r = -EFAULT; 4332 if (copy_from_user(&u.pit_config, argp, 4333 sizeof(struct kvm_pit_config))) 4334 goto out; 4335 create_pit: 4336 mutex_lock(&kvm->lock); 4337 r = -EEXIST; 4338 if (kvm->arch.vpit) 4339 goto create_pit_unlock; 4340 r = -ENOMEM; 4341 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 4342 if (kvm->arch.vpit) 4343 r = 0; 4344 create_pit_unlock: 4345 mutex_unlock(&kvm->lock); 4346 break; 4347 case KVM_GET_IRQCHIP: { 4348 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4349 struct kvm_irqchip *chip; 4350 4351 chip = memdup_user(argp, sizeof(*chip)); 4352 if (IS_ERR(chip)) { 4353 r = PTR_ERR(chip); 4354 goto out; 4355 } 4356 4357 r = -ENXIO; 4358 if (!irqchip_kernel(kvm)) 4359 goto get_irqchip_out; 4360 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 4361 if (r) 4362 goto get_irqchip_out; 4363 r = -EFAULT; 4364 if (copy_to_user(argp, chip, sizeof *chip)) 4365 goto get_irqchip_out; 4366 r = 0; 4367 get_irqchip_out: 4368 kfree(chip); 4369 break; 4370 } 4371 case KVM_SET_IRQCHIP: { 4372 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4373 struct kvm_irqchip *chip; 4374 4375 chip = memdup_user(argp, sizeof(*chip)); 4376 if (IS_ERR(chip)) { 4377 r = PTR_ERR(chip); 4378 goto out; 4379 } 4380 4381 r = -ENXIO; 4382 if (!irqchip_kernel(kvm)) 4383 goto set_irqchip_out; 4384 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 4385 if (r) 4386 goto set_irqchip_out; 4387 r = 0; 4388 set_irqchip_out: 4389 kfree(chip); 4390 break; 4391 } 4392 case KVM_GET_PIT: { 4393 r = -EFAULT; 4394 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 4395 goto out; 4396 r = -ENXIO; 4397 if (!kvm->arch.vpit) 4398 goto out; 4399 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 4400 if (r) 4401 goto out; 4402 r = -EFAULT; 4403 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 4404 goto out; 4405 r = 0; 4406 break; 4407 } 4408 case KVM_SET_PIT: { 4409 r = -EFAULT; 4410 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 4411 goto out; 4412 r = -ENXIO; 4413 if (!kvm->arch.vpit) 4414 goto out; 4415 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 4416 break; 4417 } 4418 case KVM_GET_PIT2: { 4419 r = -ENXIO; 4420 if (!kvm->arch.vpit) 4421 goto out; 4422 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 4423 if (r) 4424 goto out; 4425 r = -EFAULT; 4426 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 4427 goto out; 4428 r = 0; 4429 break; 4430 } 4431 case KVM_SET_PIT2: { 4432 r = -EFAULT; 4433 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 4434 goto out; 4435 r = -ENXIO; 4436 if (!kvm->arch.vpit) 4437 goto out; 4438 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 4439 break; 4440 } 4441 case KVM_REINJECT_CONTROL: { 4442 struct kvm_reinject_control control; 4443 r = -EFAULT; 4444 if (copy_from_user(&control, argp, sizeof(control))) 4445 goto out; 4446 r = kvm_vm_ioctl_reinject(kvm, &control); 4447 break; 4448 } 4449 case KVM_SET_BOOT_CPU_ID: 4450 r = 0; 4451 mutex_lock(&kvm->lock); 4452 if (kvm->created_vcpus) 4453 r = -EBUSY; 4454 else 4455 kvm->arch.bsp_vcpu_id = arg; 4456 mutex_unlock(&kvm->lock); 4457 break; 4458 case KVM_XEN_HVM_CONFIG: { 4459 struct kvm_xen_hvm_config xhc; 4460 r = -EFAULT; 4461 if (copy_from_user(&xhc, argp, sizeof(xhc))) 4462 goto out; 4463 r = -EINVAL; 4464 if (xhc.flags) 4465 goto out; 4466 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); 4467 r = 0; 4468 break; 4469 } 4470 case KVM_SET_CLOCK: { 4471 struct kvm_clock_data user_ns; 4472 u64 now_ns; 4473 4474 r = -EFAULT; 4475 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 4476 goto out; 4477 4478 r = -EINVAL; 4479 if (user_ns.flags) 4480 goto out; 4481 4482 r = 0; 4483 /* 4484 * TODO: userspace has to take care of races with VCPU_RUN, so 4485 * kvm_gen_update_masterclock() can be cut down to locked 4486 * pvclock_update_vm_gtod_copy(). 4487 */ 4488 kvm_gen_update_masterclock(kvm); 4489 now_ns = get_kvmclock_ns(kvm); 4490 kvm->arch.kvmclock_offset += user_ns.clock - now_ns; 4491 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); 4492 break; 4493 } 4494 case KVM_GET_CLOCK: { 4495 struct kvm_clock_data user_ns; 4496 u64 now_ns; 4497 4498 now_ns = get_kvmclock_ns(kvm); 4499 user_ns.clock = now_ns; 4500 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 4501 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 4502 4503 r = -EFAULT; 4504 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 4505 goto out; 4506 r = 0; 4507 break; 4508 } 4509 case KVM_ENABLE_CAP: { 4510 struct kvm_enable_cap cap; 4511 4512 r = -EFAULT; 4513 if (copy_from_user(&cap, argp, sizeof(cap))) 4514 goto out; 4515 r = kvm_vm_ioctl_enable_cap(kvm, &cap); 4516 break; 4517 } 4518 case KVM_MEMORY_ENCRYPT_OP: { 4519 r = -ENOTTY; 4520 if (kvm_x86_ops->mem_enc_op) 4521 r = kvm_x86_ops->mem_enc_op(kvm, argp); 4522 break; 4523 } 4524 case KVM_MEMORY_ENCRYPT_REG_REGION: { 4525 struct kvm_enc_region region; 4526 4527 r = -EFAULT; 4528 if (copy_from_user(®ion, argp, sizeof(region))) 4529 goto out; 4530 4531 r = -ENOTTY; 4532 if (kvm_x86_ops->mem_enc_reg_region) 4533 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion); 4534 break; 4535 } 4536 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 4537 struct kvm_enc_region region; 4538 4539 r = -EFAULT; 4540 if (copy_from_user(®ion, argp, sizeof(region))) 4541 goto out; 4542 4543 r = -ENOTTY; 4544 if (kvm_x86_ops->mem_enc_unreg_region) 4545 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion); 4546 break; 4547 } 4548 case KVM_HYPERV_EVENTFD: { 4549 struct kvm_hyperv_eventfd hvevfd; 4550 4551 r = -EFAULT; 4552 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 4553 goto out; 4554 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 4555 break; 4556 } 4557 default: 4558 r = -ENOTTY; 4559 } 4560 out: 4561 return r; 4562 } 4563 4564 static void kvm_init_msr_list(void) 4565 { 4566 u32 dummy[2]; 4567 unsigned i, j; 4568 4569 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { 4570 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4571 continue; 4572 4573 /* 4574 * Even MSRs that are valid in the host may not be exposed 4575 * to the guests in some cases. 4576 */ 4577 switch (msrs_to_save[i]) { 4578 case MSR_IA32_BNDCFGS: 4579 if (!kvm_x86_ops->mpx_supported()) 4580 continue; 4581 break; 4582 case MSR_TSC_AUX: 4583 if (!kvm_x86_ops->rdtscp_supported()) 4584 continue; 4585 break; 4586 default: 4587 break; 4588 } 4589 4590 if (j < i) 4591 msrs_to_save[j] = msrs_to_save[i]; 4592 j++; 4593 } 4594 num_msrs_to_save = j; 4595 4596 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { 4597 switch (emulated_msrs[i]) { 4598 case MSR_IA32_SMBASE: 4599 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase()) 4600 continue; 4601 break; 4602 default: 4603 break; 4604 } 4605 4606 if (j < i) 4607 emulated_msrs[j] = emulated_msrs[i]; 4608 j++; 4609 } 4610 num_emulated_msrs = j; 4611 4612 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) { 4613 struct kvm_msr_entry msr; 4614 4615 msr.index = msr_based_features[i]; 4616 if (kvm_get_msr_feature(&msr)) 4617 continue; 4618 4619 if (j < i) 4620 msr_based_features[j] = msr_based_features[i]; 4621 j++; 4622 } 4623 num_msr_based_features = j; 4624 } 4625 4626 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 4627 const void *v) 4628 { 4629 int handled = 0; 4630 int n; 4631 4632 do { 4633 n = min(len, 8); 4634 if (!(lapic_in_kernel(vcpu) && 4635 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 4636 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 4637 break; 4638 handled += n; 4639 addr += n; 4640 len -= n; 4641 v += n; 4642 } while (len); 4643 4644 return handled; 4645 } 4646 4647 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4648 { 4649 int handled = 0; 4650 int n; 4651 4652 do { 4653 n = min(len, 8); 4654 if (!(lapic_in_kernel(vcpu) && 4655 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 4656 addr, n, v)) 4657 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 4658 break; 4659 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 4660 handled += n; 4661 addr += n; 4662 len -= n; 4663 v += n; 4664 } while (len); 4665 4666 return handled; 4667 } 4668 4669 static void kvm_set_segment(struct kvm_vcpu *vcpu, 4670 struct kvm_segment *var, int seg) 4671 { 4672 kvm_x86_ops->set_segment(vcpu, var, seg); 4673 } 4674 4675 void kvm_get_segment(struct kvm_vcpu *vcpu, 4676 struct kvm_segment *var, int seg) 4677 { 4678 kvm_x86_ops->get_segment(vcpu, var, seg); 4679 } 4680 4681 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 4682 struct x86_exception *exception) 4683 { 4684 gpa_t t_gpa; 4685 4686 BUG_ON(!mmu_is_nested(vcpu)); 4687 4688 /* NPT walks are always user-walks */ 4689 access |= PFERR_USER_MASK; 4690 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); 4691 4692 return t_gpa; 4693 } 4694 4695 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 4696 struct x86_exception *exception) 4697 { 4698 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4699 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4700 } 4701 4702 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 4703 struct x86_exception *exception) 4704 { 4705 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4706 access |= PFERR_FETCH_MASK; 4707 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4708 } 4709 4710 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 4711 struct x86_exception *exception) 4712 { 4713 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4714 access |= PFERR_WRITE_MASK; 4715 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4716 } 4717 4718 /* uses this to access any guest's mapped memory without checking CPL */ 4719 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 4720 struct x86_exception *exception) 4721 { 4722 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 4723 } 4724 4725 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 4726 struct kvm_vcpu *vcpu, u32 access, 4727 struct x86_exception *exception) 4728 { 4729 void *data = val; 4730 int r = X86EMUL_CONTINUE; 4731 4732 while (bytes) { 4733 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 4734 exception); 4735 unsigned offset = addr & (PAGE_SIZE-1); 4736 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 4737 int ret; 4738 4739 if (gpa == UNMAPPED_GVA) 4740 return X86EMUL_PROPAGATE_FAULT; 4741 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 4742 offset, toread); 4743 if (ret < 0) { 4744 r = X86EMUL_IO_NEEDED; 4745 goto out; 4746 } 4747 4748 bytes -= toread; 4749 data += toread; 4750 addr += toread; 4751 } 4752 out: 4753 return r; 4754 } 4755 4756 /* used for instruction fetching */ 4757 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4758 gva_t addr, void *val, unsigned int bytes, 4759 struct x86_exception *exception) 4760 { 4761 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4762 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4763 unsigned offset; 4764 int ret; 4765 4766 /* Inline kvm_read_guest_virt_helper for speed. */ 4767 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 4768 exception); 4769 if (unlikely(gpa == UNMAPPED_GVA)) 4770 return X86EMUL_PROPAGATE_FAULT; 4771 4772 offset = addr & (PAGE_SIZE-1); 4773 if (WARN_ON(offset + bytes > PAGE_SIZE)) 4774 bytes = (unsigned)PAGE_SIZE - offset; 4775 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 4776 offset, bytes); 4777 if (unlikely(ret < 0)) 4778 return X86EMUL_IO_NEEDED; 4779 4780 return X86EMUL_CONTINUE; 4781 } 4782 4783 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4784 gva_t addr, void *val, unsigned int bytes, 4785 struct x86_exception *exception) 4786 { 4787 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4788 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4789 4790 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4791 exception); 4792 } 4793 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4794 4795 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4796 gva_t addr, void *val, unsigned int bytes, 4797 struct x86_exception *exception) 4798 { 4799 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4800 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4801 } 4802 4803 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 4804 unsigned long addr, void *val, unsigned int bytes) 4805 { 4806 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4807 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 4808 4809 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 4810 } 4811 4812 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4813 gva_t addr, void *val, 4814 unsigned int bytes, 4815 struct x86_exception *exception) 4816 { 4817 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4818 void *data = val; 4819 int r = X86EMUL_CONTINUE; 4820 4821 while (bytes) { 4822 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4823 PFERR_WRITE_MASK, 4824 exception); 4825 unsigned offset = addr & (PAGE_SIZE-1); 4826 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4827 int ret; 4828 4829 if (gpa == UNMAPPED_GVA) 4830 return X86EMUL_PROPAGATE_FAULT; 4831 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 4832 if (ret < 0) { 4833 r = X86EMUL_IO_NEEDED; 4834 goto out; 4835 } 4836 4837 bytes -= towrite; 4838 data += towrite; 4839 addr += towrite; 4840 } 4841 out: 4842 return r; 4843 } 4844 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4845 4846 int handle_ud(struct kvm_vcpu *vcpu) 4847 { 4848 int emul_type = EMULTYPE_TRAP_UD; 4849 enum emulation_result er; 4850 char sig[5]; /* ud2; .ascii "kvm" */ 4851 struct x86_exception e; 4852 4853 if (force_emulation_prefix && 4854 kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, 4855 kvm_get_linear_rip(vcpu), sig, sizeof(sig), &e) == 0 && 4856 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) { 4857 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 4858 emul_type = 0; 4859 } 4860 4861 er = emulate_instruction(vcpu, emul_type); 4862 if (er == EMULATE_USER_EXIT) 4863 return 0; 4864 if (er != EMULATE_DONE) 4865 kvm_queue_exception(vcpu, UD_VECTOR); 4866 return 1; 4867 } 4868 EXPORT_SYMBOL_GPL(handle_ud); 4869 4870 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4871 gpa_t gpa, bool write) 4872 { 4873 /* For APIC access vmexit */ 4874 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4875 return 1; 4876 4877 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 4878 trace_vcpu_match_mmio(gva, gpa, write, true); 4879 return 1; 4880 } 4881 4882 return 0; 4883 } 4884 4885 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4886 gpa_t *gpa, struct x86_exception *exception, 4887 bool write) 4888 { 4889 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4890 | (write ? PFERR_WRITE_MASK : 0); 4891 4892 /* 4893 * currently PKRU is only applied to ept enabled guest so 4894 * there is no pkey in EPT page table for L1 guest or EPT 4895 * shadow page table for L2 guest. 4896 */ 4897 if (vcpu_match_mmio_gva(vcpu, gva) 4898 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4899 vcpu->arch.access, 0, access)) { 4900 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4901 (gva & (PAGE_SIZE - 1)); 4902 trace_vcpu_match_mmio(gva, *gpa, write, false); 4903 return 1; 4904 } 4905 4906 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4907 4908 if (*gpa == UNMAPPED_GVA) 4909 return -1; 4910 4911 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 4912 } 4913 4914 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4915 const void *val, int bytes) 4916 { 4917 int ret; 4918 4919 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 4920 if (ret < 0) 4921 return 0; 4922 kvm_page_track_write(vcpu, gpa, val, bytes); 4923 return 1; 4924 } 4925 4926 struct read_write_emulator_ops { 4927 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4928 int bytes); 4929 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4930 void *val, int bytes); 4931 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4932 int bytes, void *val); 4933 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4934 void *val, int bytes); 4935 bool write; 4936 }; 4937 4938 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4939 { 4940 if (vcpu->mmio_read_completed) { 4941 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4942 vcpu->mmio_fragments[0].gpa, val); 4943 vcpu->mmio_read_completed = 0; 4944 return 1; 4945 } 4946 4947 return 0; 4948 } 4949 4950 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4951 void *val, int bytes) 4952 { 4953 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 4954 } 4955 4956 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4957 void *val, int bytes) 4958 { 4959 return emulator_write_phys(vcpu, gpa, val, bytes); 4960 } 4961 4962 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4963 { 4964 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 4965 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4966 } 4967 4968 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4969 void *val, int bytes) 4970 { 4971 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 4972 return X86EMUL_IO_NEEDED; 4973 } 4974 4975 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4976 void *val, int bytes) 4977 { 4978 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4979 4980 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4981 return X86EMUL_CONTINUE; 4982 } 4983 4984 static const struct read_write_emulator_ops read_emultor = { 4985 .read_write_prepare = read_prepare, 4986 .read_write_emulate = read_emulate, 4987 .read_write_mmio = vcpu_mmio_read, 4988 .read_write_exit_mmio = read_exit_mmio, 4989 }; 4990 4991 static const struct read_write_emulator_ops write_emultor = { 4992 .read_write_emulate = write_emulate, 4993 .read_write_mmio = write_mmio, 4994 .read_write_exit_mmio = write_exit_mmio, 4995 .write = true, 4996 }; 4997 4998 static int emulator_read_write_onepage(unsigned long addr, void *val, 4999 unsigned int bytes, 5000 struct x86_exception *exception, 5001 struct kvm_vcpu *vcpu, 5002 const struct read_write_emulator_ops *ops) 5003 { 5004 gpa_t gpa; 5005 int handled, ret; 5006 bool write = ops->write; 5007 struct kvm_mmio_fragment *frag; 5008 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5009 5010 /* 5011 * If the exit was due to a NPF we may already have a GPA. 5012 * If the GPA is present, use it to avoid the GVA to GPA table walk. 5013 * Note, this cannot be used on string operations since string 5014 * operation using rep will only have the initial GPA from the NPF 5015 * occurred. 5016 */ 5017 if (vcpu->arch.gpa_available && 5018 emulator_can_use_gpa(ctxt) && 5019 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) { 5020 gpa = vcpu->arch.gpa_val; 5021 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 5022 } else { 5023 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 5024 if (ret < 0) 5025 return X86EMUL_PROPAGATE_FAULT; 5026 } 5027 5028 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 5029 return X86EMUL_CONTINUE; 5030 5031 /* 5032 * Is this MMIO handled locally? 5033 */ 5034 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 5035 if (handled == bytes) 5036 return X86EMUL_CONTINUE; 5037 5038 gpa += handled; 5039 bytes -= handled; 5040 val += handled; 5041 5042 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 5043 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 5044 frag->gpa = gpa; 5045 frag->data = val; 5046 frag->len = bytes; 5047 return X86EMUL_CONTINUE; 5048 } 5049 5050 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 5051 unsigned long addr, 5052 void *val, unsigned int bytes, 5053 struct x86_exception *exception, 5054 const struct read_write_emulator_ops *ops) 5055 { 5056 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5057 gpa_t gpa; 5058 int rc; 5059 5060 if (ops->read_write_prepare && 5061 ops->read_write_prepare(vcpu, val, bytes)) 5062 return X86EMUL_CONTINUE; 5063 5064 vcpu->mmio_nr_fragments = 0; 5065 5066 /* Crossing a page boundary? */ 5067 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 5068 int now; 5069 5070 now = -addr & ~PAGE_MASK; 5071 rc = emulator_read_write_onepage(addr, val, now, exception, 5072 vcpu, ops); 5073 5074 if (rc != X86EMUL_CONTINUE) 5075 return rc; 5076 addr += now; 5077 if (ctxt->mode != X86EMUL_MODE_PROT64) 5078 addr = (u32)addr; 5079 val += now; 5080 bytes -= now; 5081 } 5082 5083 rc = emulator_read_write_onepage(addr, val, bytes, exception, 5084 vcpu, ops); 5085 if (rc != X86EMUL_CONTINUE) 5086 return rc; 5087 5088 if (!vcpu->mmio_nr_fragments) 5089 return rc; 5090 5091 gpa = vcpu->mmio_fragments[0].gpa; 5092 5093 vcpu->mmio_needed = 1; 5094 vcpu->mmio_cur_fragment = 0; 5095 5096 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 5097 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 5098 vcpu->run->exit_reason = KVM_EXIT_MMIO; 5099 vcpu->run->mmio.phys_addr = gpa; 5100 5101 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 5102 } 5103 5104 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 5105 unsigned long addr, 5106 void *val, 5107 unsigned int bytes, 5108 struct x86_exception *exception) 5109 { 5110 return emulator_read_write(ctxt, addr, val, bytes, 5111 exception, &read_emultor); 5112 } 5113 5114 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 5115 unsigned long addr, 5116 const void *val, 5117 unsigned int bytes, 5118 struct x86_exception *exception) 5119 { 5120 return emulator_read_write(ctxt, addr, (void *)val, bytes, 5121 exception, &write_emultor); 5122 } 5123 5124 #define CMPXCHG_TYPE(t, ptr, old, new) \ 5125 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 5126 5127 #ifdef CONFIG_X86_64 5128 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 5129 #else 5130 # define CMPXCHG64(ptr, old, new) \ 5131 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 5132 #endif 5133 5134 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 5135 unsigned long addr, 5136 const void *old, 5137 const void *new, 5138 unsigned int bytes, 5139 struct x86_exception *exception) 5140 { 5141 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5142 gpa_t gpa; 5143 struct page *page; 5144 char *kaddr; 5145 bool exchanged; 5146 5147 /* guests cmpxchg8b have to be emulated atomically */ 5148 if (bytes > 8 || (bytes & (bytes - 1))) 5149 goto emul_write; 5150 5151 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 5152 5153 if (gpa == UNMAPPED_GVA || 5154 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 5155 goto emul_write; 5156 5157 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 5158 goto emul_write; 5159 5160 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); 5161 if (is_error_page(page)) 5162 goto emul_write; 5163 5164 kaddr = kmap_atomic(page); 5165 kaddr += offset_in_page(gpa); 5166 switch (bytes) { 5167 case 1: 5168 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 5169 break; 5170 case 2: 5171 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 5172 break; 5173 case 4: 5174 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 5175 break; 5176 case 8: 5177 exchanged = CMPXCHG64(kaddr, old, new); 5178 break; 5179 default: 5180 BUG(); 5181 } 5182 kunmap_atomic(kaddr); 5183 kvm_release_page_dirty(page); 5184 5185 if (!exchanged) 5186 return X86EMUL_CMPXCHG_FAILED; 5187 5188 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5189 kvm_page_track_write(vcpu, gpa, new, bytes); 5190 5191 return X86EMUL_CONTINUE; 5192 5193 emul_write: 5194 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 5195 5196 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 5197 } 5198 5199 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 5200 { 5201 int r = 0, i; 5202 5203 for (i = 0; i < vcpu->arch.pio.count; i++) { 5204 if (vcpu->arch.pio.in) 5205 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 5206 vcpu->arch.pio.size, pd); 5207 else 5208 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 5209 vcpu->arch.pio.port, vcpu->arch.pio.size, 5210 pd); 5211 if (r) 5212 break; 5213 pd += vcpu->arch.pio.size; 5214 } 5215 return r; 5216 } 5217 5218 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 5219 unsigned short port, void *val, 5220 unsigned int count, bool in) 5221 { 5222 vcpu->arch.pio.port = port; 5223 vcpu->arch.pio.in = in; 5224 vcpu->arch.pio.count = count; 5225 vcpu->arch.pio.size = size; 5226 5227 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 5228 vcpu->arch.pio.count = 0; 5229 return 1; 5230 } 5231 5232 vcpu->run->exit_reason = KVM_EXIT_IO; 5233 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 5234 vcpu->run->io.size = size; 5235 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 5236 vcpu->run->io.count = count; 5237 vcpu->run->io.port = port; 5238 5239 return 0; 5240 } 5241 5242 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 5243 int size, unsigned short port, void *val, 5244 unsigned int count) 5245 { 5246 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5247 int ret; 5248 5249 if (vcpu->arch.pio.count) 5250 goto data_avail; 5251 5252 memset(vcpu->arch.pio_data, 0, size * count); 5253 5254 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 5255 if (ret) { 5256 data_avail: 5257 memcpy(val, vcpu->arch.pio_data, size * count); 5258 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 5259 vcpu->arch.pio.count = 0; 5260 return 1; 5261 } 5262 5263 return 0; 5264 } 5265 5266 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 5267 int size, unsigned short port, 5268 const void *val, unsigned int count) 5269 { 5270 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5271 5272 memcpy(vcpu->arch.pio_data, val, size * count); 5273 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 5274 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 5275 } 5276 5277 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 5278 { 5279 return kvm_x86_ops->get_segment_base(vcpu, seg); 5280 } 5281 5282 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 5283 { 5284 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 5285 } 5286 5287 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 5288 { 5289 if (!need_emulate_wbinvd(vcpu)) 5290 return X86EMUL_CONTINUE; 5291 5292 if (kvm_x86_ops->has_wbinvd_exit()) { 5293 int cpu = get_cpu(); 5294 5295 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 5296 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 5297 wbinvd_ipi, NULL, 1); 5298 put_cpu(); 5299 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 5300 } else 5301 wbinvd(); 5302 return X86EMUL_CONTINUE; 5303 } 5304 5305 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 5306 { 5307 kvm_emulate_wbinvd_noskip(vcpu); 5308 return kvm_skip_emulated_instruction(vcpu); 5309 } 5310 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 5311 5312 5313 5314 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 5315 { 5316 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 5317 } 5318 5319 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 5320 unsigned long *dest) 5321 { 5322 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 5323 } 5324 5325 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 5326 unsigned long value) 5327 { 5328 5329 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 5330 } 5331 5332 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 5333 { 5334 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 5335 } 5336 5337 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 5338 { 5339 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5340 unsigned long value; 5341 5342 switch (cr) { 5343 case 0: 5344 value = kvm_read_cr0(vcpu); 5345 break; 5346 case 2: 5347 value = vcpu->arch.cr2; 5348 break; 5349 case 3: 5350 value = kvm_read_cr3(vcpu); 5351 break; 5352 case 4: 5353 value = kvm_read_cr4(vcpu); 5354 break; 5355 case 8: 5356 value = kvm_get_cr8(vcpu); 5357 break; 5358 default: 5359 kvm_err("%s: unexpected cr %u\n", __func__, cr); 5360 return 0; 5361 } 5362 5363 return value; 5364 } 5365 5366 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 5367 { 5368 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5369 int res = 0; 5370 5371 switch (cr) { 5372 case 0: 5373 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 5374 break; 5375 case 2: 5376 vcpu->arch.cr2 = val; 5377 break; 5378 case 3: 5379 res = kvm_set_cr3(vcpu, val); 5380 break; 5381 case 4: 5382 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 5383 break; 5384 case 8: 5385 res = kvm_set_cr8(vcpu, val); 5386 break; 5387 default: 5388 kvm_err("%s: unexpected cr %u\n", __func__, cr); 5389 res = -1; 5390 } 5391 5392 return res; 5393 } 5394 5395 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 5396 { 5397 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 5398 } 5399 5400 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5401 { 5402 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 5403 } 5404 5405 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5406 { 5407 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 5408 } 5409 5410 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5411 { 5412 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 5413 } 5414 5415 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5416 { 5417 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 5418 } 5419 5420 static unsigned long emulator_get_cached_segment_base( 5421 struct x86_emulate_ctxt *ctxt, int seg) 5422 { 5423 return get_segment_base(emul_to_vcpu(ctxt), seg); 5424 } 5425 5426 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 5427 struct desc_struct *desc, u32 *base3, 5428 int seg) 5429 { 5430 struct kvm_segment var; 5431 5432 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 5433 *selector = var.selector; 5434 5435 if (var.unusable) { 5436 memset(desc, 0, sizeof(*desc)); 5437 if (base3) 5438 *base3 = 0; 5439 return false; 5440 } 5441 5442 if (var.g) 5443 var.limit >>= 12; 5444 set_desc_limit(desc, var.limit); 5445 set_desc_base(desc, (unsigned long)var.base); 5446 #ifdef CONFIG_X86_64 5447 if (base3) 5448 *base3 = var.base >> 32; 5449 #endif 5450 desc->type = var.type; 5451 desc->s = var.s; 5452 desc->dpl = var.dpl; 5453 desc->p = var.present; 5454 desc->avl = var.avl; 5455 desc->l = var.l; 5456 desc->d = var.db; 5457 desc->g = var.g; 5458 5459 return true; 5460 } 5461 5462 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 5463 struct desc_struct *desc, u32 base3, 5464 int seg) 5465 { 5466 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5467 struct kvm_segment var; 5468 5469 var.selector = selector; 5470 var.base = get_desc_base(desc); 5471 #ifdef CONFIG_X86_64 5472 var.base |= ((u64)base3) << 32; 5473 #endif 5474 var.limit = get_desc_limit(desc); 5475 if (desc->g) 5476 var.limit = (var.limit << 12) | 0xfff; 5477 var.type = desc->type; 5478 var.dpl = desc->dpl; 5479 var.db = desc->d; 5480 var.s = desc->s; 5481 var.l = desc->l; 5482 var.g = desc->g; 5483 var.avl = desc->avl; 5484 var.present = desc->p; 5485 var.unusable = !var.present; 5486 var.padding = 0; 5487 5488 kvm_set_segment(vcpu, &var, seg); 5489 return; 5490 } 5491 5492 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 5493 u32 msr_index, u64 *pdata) 5494 { 5495 struct msr_data msr; 5496 int r; 5497 5498 msr.index = msr_index; 5499 msr.host_initiated = false; 5500 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); 5501 if (r) 5502 return r; 5503 5504 *pdata = msr.data; 5505 return 0; 5506 } 5507 5508 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 5509 u32 msr_index, u64 data) 5510 { 5511 struct msr_data msr; 5512 5513 msr.data = data; 5514 msr.index = msr_index; 5515 msr.host_initiated = false; 5516 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 5517 } 5518 5519 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 5520 { 5521 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5522 5523 return vcpu->arch.smbase; 5524 } 5525 5526 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 5527 { 5528 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5529 5530 vcpu->arch.smbase = smbase; 5531 } 5532 5533 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 5534 u32 pmc) 5535 { 5536 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); 5537 } 5538 5539 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 5540 u32 pmc, u64 *pdata) 5541 { 5542 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 5543 } 5544 5545 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 5546 { 5547 emul_to_vcpu(ctxt)->arch.halt_request = 1; 5548 } 5549 5550 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 5551 struct x86_instruction_info *info, 5552 enum x86_intercept_stage stage) 5553 { 5554 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 5555 } 5556 5557 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 5558 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit) 5559 { 5560 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit); 5561 } 5562 5563 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 5564 { 5565 return kvm_register_read(emul_to_vcpu(ctxt), reg); 5566 } 5567 5568 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 5569 { 5570 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 5571 } 5572 5573 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 5574 { 5575 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 5576 } 5577 5578 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 5579 { 5580 return emul_to_vcpu(ctxt)->arch.hflags; 5581 } 5582 5583 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) 5584 { 5585 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags); 5586 } 5587 5588 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase) 5589 { 5590 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase); 5591 } 5592 5593 static const struct x86_emulate_ops emulate_ops = { 5594 .read_gpr = emulator_read_gpr, 5595 .write_gpr = emulator_write_gpr, 5596 .read_std = kvm_read_guest_virt_system, 5597 .write_std = kvm_write_guest_virt_system, 5598 .read_phys = kvm_read_guest_phys_system, 5599 .fetch = kvm_fetch_guest_virt, 5600 .read_emulated = emulator_read_emulated, 5601 .write_emulated = emulator_write_emulated, 5602 .cmpxchg_emulated = emulator_cmpxchg_emulated, 5603 .invlpg = emulator_invlpg, 5604 .pio_in_emulated = emulator_pio_in_emulated, 5605 .pio_out_emulated = emulator_pio_out_emulated, 5606 .get_segment = emulator_get_segment, 5607 .set_segment = emulator_set_segment, 5608 .get_cached_segment_base = emulator_get_cached_segment_base, 5609 .get_gdt = emulator_get_gdt, 5610 .get_idt = emulator_get_idt, 5611 .set_gdt = emulator_set_gdt, 5612 .set_idt = emulator_set_idt, 5613 .get_cr = emulator_get_cr, 5614 .set_cr = emulator_set_cr, 5615 .cpl = emulator_get_cpl, 5616 .get_dr = emulator_get_dr, 5617 .set_dr = emulator_set_dr, 5618 .get_smbase = emulator_get_smbase, 5619 .set_smbase = emulator_set_smbase, 5620 .set_msr = emulator_set_msr, 5621 .get_msr = emulator_get_msr, 5622 .check_pmc = emulator_check_pmc, 5623 .read_pmc = emulator_read_pmc, 5624 .halt = emulator_halt, 5625 .wbinvd = emulator_wbinvd, 5626 .fix_hypercall = emulator_fix_hypercall, 5627 .intercept = emulator_intercept, 5628 .get_cpuid = emulator_get_cpuid, 5629 .set_nmi_mask = emulator_set_nmi_mask, 5630 .get_hflags = emulator_get_hflags, 5631 .set_hflags = emulator_set_hflags, 5632 .pre_leave_smm = emulator_pre_leave_smm, 5633 }; 5634 5635 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 5636 { 5637 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 5638 /* 5639 * an sti; sti; sequence only disable interrupts for the first 5640 * instruction. So, if the last instruction, be it emulated or 5641 * not, left the system with the INT_STI flag enabled, it 5642 * means that the last instruction is an sti. We should not 5643 * leave the flag on in this case. The same goes for mov ss 5644 */ 5645 if (int_shadow & mask) 5646 mask = 0; 5647 if (unlikely(int_shadow || mask)) { 5648 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 5649 if (!mask) 5650 kvm_make_request(KVM_REQ_EVENT, vcpu); 5651 } 5652 } 5653 5654 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 5655 { 5656 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5657 if (ctxt->exception.vector == PF_VECTOR) 5658 return kvm_propagate_fault(vcpu, &ctxt->exception); 5659 5660 if (ctxt->exception.error_code_valid) 5661 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 5662 ctxt->exception.error_code); 5663 else 5664 kvm_queue_exception(vcpu, ctxt->exception.vector); 5665 return false; 5666 } 5667 5668 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 5669 { 5670 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5671 int cs_db, cs_l; 5672 5673 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 5674 5675 ctxt->eflags = kvm_get_rflags(vcpu); 5676 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 5677 5678 ctxt->eip = kvm_rip_read(vcpu); 5679 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 5680 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 5681 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 5682 cs_db ? X86EMUL_MODE_PROT32 : 5683 X86EMUL_MODE_PROT16; 5684 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 5685 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 5686 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 5687 5688 init_decode_cache(ctxt); 5689 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5690 } 5691 5692 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 5693 { 5694 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5695 int ret; 5696 5697 init_emulate_ctxt(vcpu); 5698 5699 ctxt->op_bytes = 2; 5700 ctxt->ad_bytes = 2; 5701 ctxt->_eip = ctxt->eip + inc_eip; 5702 ret = emulate_int_real(ctxt, irq); 5703 5704 if (ret != X86EMUL_CONTINUE) 5705 return EMULATE_FAIL; 5706 5707 ctxt->eip = ctxt->_eip; 5708 kvm_rip_write(vcpu, ctxt->eip); 5709 kvm_set_rflags(vcpu, ctxt->eflags); 5710 5711 return EMULATE_DONE; 5712 } 5713 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 5714 5715 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 5716 { 5717 int r = EMULATE_DONE; 5718 5719 ++vcpu->stat.insn_emulation_fail; 5720 trace_kvm_emulate_insn_failed(vcpu); 5721 5722 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL) 5723 return EMULATE_FAIL; 5724 5725 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 5726 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5727 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 5728 vcpu->run->internal.ndata = 0; 5729 r = EMULATE_USER_EXIT; 5730 } 5731 5732 kvm_queue_exception(vcpu, UD_VECTOR); 5733 5734 return r; 5735 } 5736 5737 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 5738 bool write_fault_to_shadow_pgtable, 5739 int emulation_type) 5740 { 5741 gpa_t gpa = cr2; 5742 kvm_pfn_t pfn; 5743 5744 if (emulation_type & EMULTYPE_NO_REEXECUTE) 5745 return false; 5746 5747 if (!vcpu->arch.mmu.direct_map) { 5748 /* 5749 * Write permission should be allowed since only 5750 * write access need to be emulated. 5751 */ 5752 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5753 5754 /* 5755 * If the mapping is invalid in guest, let cpu retry 5756 * it to generate fault. 5757 */ 5758 if (gpa == UNMAPPED_GVA) 5759 return true; 5760 } 5761 5762 /* 5763 * Do not retry the unhandleable instruction if it faults on the 5764 * readonly host memory, otherwise it will goto a infinite loop: 5765 * retry instruction -> write #PF -> emulation fail -> retry 5766 * instruction -> ... 5767 */ 5768 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 5769 5770 /* 5771 * If the instruction failed on the error pfn, it can not be fixed, 5772 * report the error to userspace. 5773 */ 5774 if (is_error_noslot_pfn(pfn)) 5775 return false; 5776 5777 kvm_release_pfn_clean(pfn); 5778 5779 /* The instructions are well-emulated on direct mmu. */ 5780 if (vcpu->arch.mmu.direct_map) { 5781 unsigned int indirect_shadow_pages; 5782 5783 spin_lock(&vcpu->kvm->mmu_lock); 5784 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 5785 spin_unlock(&vcpu->kvm->mmu_lock); 5786 5787 if (indirect_shadow_pages) 5788 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5789 5790 return true; 5791 } 5792 5793 /* 5794 * if emulation was due to access to shadowed page table 5795 * and it failed try to unshadow page and re-enter the 5796 * guest to let CPU execute the instruction. 5797 */ 5798 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5799 5800 /* 5801 * If the access faults on its page table, it can not 5802 * be fixed by unprotecting shadow page and it should 5803 * be reported to userspace. 5804 */ 5805 return !write_fault_to_shadow_pgtable; 5806 } 5807 5808 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5809 unsigned long cr2, int emulation_type) 5810 { 5811 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5812 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5813 5814 last_retry_eip = vcpu->arch.last_retry_eip; 5815 last_retry_addr = vcpu->arch.last_retry_addr; 5816 5817 /* 5818 * If the emulation is caused by #PF and it is non-page_table 5819 * writing instruction, it means the VM-EXIT is caused by shadow 5820 * page protected, we can zap the shadow page and retry this 5821 * instruction directly. 5822 * 5823 * Note: if the guest uses a non-page-table modifying instruction 5824 * on the PDE that points to the instruction, then we will unmap 5825 * the instruction and go to an infinite loop. So, we cache the 5826 * last retried eip and the last fault address, if we meet the eip 5827 * and the address again, we can break out of the potential infinite 5828 * loop. 5829 */ 5830 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5831 5832 if (!(emulation_type & EMULTYPE_RETRY)) 5833 return false; 5834 5835 if (x86_page_table_writing_insn(ctxt)) 5836 return false; 5837 5838 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5839 return false; 5840 5841 vcpu->arch.last_retry_eip = ctxt->eip; 5842 vcpu->arch.last_retry_addr = cr2; 5843 5844 if (!vcpu->arch.mmu.direct_map) 5845 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5846 5847 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5848 5849 return true; 5850 } 5851 5852 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5853 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5854 5855 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 5856 { 5857 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 5858 /* This is a good place to trace that we are exiting SMM. */ 5859 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 5860 5861 /* Process a latched INIT or SMI, if any. */ 5862 kvm_make_request(KVM_REQ_EVENT, vcpu); 5863 } 5864 5865 kvm_mmu_reset_context(vcpu); 5866 } 5867 5868 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) 5869 { 5870 unsigned changed = vcpu->arch.hflags ^ emul_flags; 5871 5872 vcpu->arch.hflags = emul_flags; 5873 5874 if (changed & HF_SMM_MASK) 5875 kvm_smm_changed(vcpu); 5876 } 5877 5878 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5879 unsigned long *db) 5880 { 5881 u32 dr6 = 0; 5882 int i; 5883 u32 enable, rwlen; 5884 5885 enable = dr7; 5886 rwlen = dr7 >> 16; 5887 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5888 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5889 dr6 |= (1 << i); 5890 return dr6; 5891 } 5892 5893 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r) 5894 { 5895 struct kvm_run *kvm_run = vcpu->run; 5896 5897 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5898 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; 5899 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5900 kvm_run->debug.arch.exception = DB_VECTOR; 5901 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5902 *r = EMULATE_USER_EXIT; 5903 } else { 5904 /* 5905 * "Certain debug exceptions may clear bit 0-3. The 5906 * remaining contents of the DR6 register are never 5907 * cleared by the processor". 5908 */ 5909 vcpu->arch.dr6 &= ~15; 5910 vcpu->arch.dr6 |= DR6_BS | DR6_RTM; 5911 kvm_queue_exception(vcpu, DB_VECTOR); 5912 } 5913 } 5914 5915 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 5916 { 5917 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5918 int r = EMULATE_DONE; 5919 5920 kvm_x86_ops->skip_emulated_instruction(vcpu); 5921 5922 /* 5923 * rflags is the old, "raw" value of the flags. The new value has 5924 * not been saved yet. 5925 * 5926 * This is correct even for TF set by the guest, because "the 5927 * processor will not generate this exception after the instruction 5928 * that sets the TF flag". 5929 */ 5930 if (unlikely(rflags & X86_EFLAGS_TF)) 5931 kvm_vcpu_do_singlestep(vcpu, &r); 5932 return r == EMULATE_DONE; 5933 } 5934 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 5935 5936 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5937 { 5938 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5939 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5940 struct kvm_run *kvm_run = vcpu->run; 5941 unsigned long eip = kvm_get_linear_rip(vcpu); 5942 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5943 vcpu->arch.guest_debug_dr7, 5944 vcpu->arch.eff_db); 5945 5946 if (dr6 != 0) { 5947 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 5948 kvm_run->debug.arch.pc = eip; 5949 kvm_run->debug.arch.exception = DB_VECTOR; 5950 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5951 *r = EMULATE_USER_EXIT; 5952 return true; 5953 } 5954 } 5955 5956 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 5957 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 5958 unsigned long eip = kvm_get_linear_rip(vcpu); 5959 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5960 vcpu->arch.dr7, 5961 vcpu->arch.db); 5962 5963 if (dr6 != 0) { 5964 vcpu->arch.dr6 &= ~15; 5965 vcpu->arch.dr6 |= dr6 | DR6_RTM; 5966 kvm_queue_exception(vcpu, DB_VECTOR); 5967 *r = EMULATE_DONE; 5968 return true; 5969 } 5970 } 5971 5972 return false; 5973 } 5974 5975 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 5976 { 5977 switch (ctxt->opcode_len) { 5978 case 1: 5979 switch (ctxt->b) { 5980 case 0xe4: /* IN */ 5981 case 0xe5: 5982 case 0xec: 5983 case 0xed: 5984 case 0xe6: /* OUT */ 5985 case 0xe7: 5986 case 0xee: 5987 case 0xef: 5988 case 0x6c: /* INS */ 5989 case 0x6d: 5990 case 0x6e: /* OUTS */ 5991 case 0x6f: 5992 return true; 5993 } 5994 break; 5995 case 2: 5996 switch (ctxt->b) { 5997 case 0x33: /* RDPMC */ 5998 return true; 5999 } 6000 break; 6001 } 6002 6003 return false; 6004 } 6005 6006 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 6007 unsigned long cr2, 6008 int emulation_type, 6009 void *insn, 6010 int insn_len) 6011 { 6012 int r; 6013 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6014 bool writeback = true; 6015 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 6016 6017 /* 6018 * Clear write_fault_to_shadow_pgtable here to ensure it is 6019 * never reused. 6020 */ 6021 vcpu->arch.write_fault_to_shadow_pgtable = false; 6022 kvm_clear_exception_queue(vcpu); 6023 6024 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 6025 init_emulate_ctxt(vcpu); 6026 6027 /* 6028 * We will reenter on the same instruction since 6029 * we do not set complete_userspace_io. This does not 6030 * handle watchpoints yet, those would be handled in 6031 * the emulate_ops. 6032 */ 6033 if (!(emulation_type & EMULTYPE_SKIP) && 6034 kvm_vcpu_check_breakpoint(vcpu, &r)) 6035 return r; 6036 6037 ctxt->interruptibility = 0; 6038 ctxt->have_exception = false; 6039 ctxt->exception.vector = -1; 6040 ctxt->perm_ok = false; 6041 6042 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 6043 6044 r = x86_decode_insn(ctxt, insn, insn_len); 6045 6046 trace_kvm_emulate_insn_start(vcpu); 6047 ++vcpu->stat.insn_emulation; 6048 if (r != EMULATION_OK) { 6049 if (emulation_type & EMULTYPE_TRAP_UD) 6050 return EMULATE_FAIL; 6051 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 6052 emulation_type)) 6053 return EMULATE_DONE; 6054 if (ctxt->have_exception && inject_emulated_exception(vcpu)) 6055 return EMULATE_DONE; 6056 if (emulation_type & EMULTYPE_SKIP) 6057 return EMULATE_FAIL; 6058 return handle_emulation_failure(vcpu, emulation_type); 6059 } 6060 } 6061 6062 if ((emulation_type & EMULTYPE_VMWARE) && 6063 !is_vmware_backdoor_opcode(ctxt)) 6064 return EMULATE_FAIL; 6065 6066 if (emulation_type & EMULTYPE_SKIP) { 6067 kvm_rip_write(vcpu, ctxt->_eip); 6068 if (ctxt->eflags & X86_EFLAGS_RF) 6069 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 6070 return EMULATE_DONE; 6071 } 6072 6073 if (retry_instruction(ctxt, cr2, emulation_type)) 6074 return EMULATE_DONE; 6075 6076 /* this is needed for vmware backdoor interface to work since it 6077 changes registers values during IO operation */ 6078 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 6079 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 6080 emulator_invalidate_register_cache(ctxt); 6081 } 6082 6083 restart: 6084 /* Save the faulting GPA (cr2) in the address field */ 6085 ctxt->exception.address = cr2; 6086 6087 r = x86_emulate_insn(ctxt); 6088 6089 if (r == EMULATION_INTERCEPTED) 6090 return EMULATE_DONE; 6091 6092 if (r == EMULATION_FAILED) { 6093 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 6094 emulation_type)) 6095 return EMULATE_DONE; 6096 6097 return handle_emulation_failure(vcpu, emulation_type); 6098 } 6099 6100 if (ctxt->have_exception) { 6101 r = EMULATE_DONE; 6102 if (inject_emulated_exception(vcpu)) 6103 return r; 6104 } else if (vcpu->arch.pio.count) { 6105 if (!vcpu->arch.pio.in) { 6106 /* FIXME: return into emulator if single-stepping. */ 6107 vcpu->arch.pio.count = 0; 6108 } else { 6109 writeback = false; 6110 vcpu->arch.complete_userspace_io = complete_emulated_pio; 6111 } 6112 r = EMULATE_USER_EXIT; 6113 } else if (vcpu->mmio_needed) { 6114 if (!vcpu->mmio_is_write) 6115 writeback = false; 6116 r = EMULATE_USER_EXIT; 6117 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6118 } else if (r == EMULATION_RESTART) 6119 goto restart; 6120 else 6121 r = EMULATE_DONE; 6122 6123 if (writeback) { 6124 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 6125 toggle_interruptibility(vcpu, ctxt->interruptibility); 6126 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6127 kvm_rip_write(vcpu, ctxt->eip); 6128 if (r == EMULATE_DONE && 6129 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 6130 kvm_vcpu_do_singlestep(vcpu, &r); 6131 if (!ctxt->have_exception || 6132 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 6133 __kvm_set_rflags(vcpu, ctxt->eflags); 6134 6135 /* 6136 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 6137 * do nothing, and it will be requested again as soon as 6138 * the shadow expires. But we still need to check here, 6139 * because POPF has no interrupt shadow. 6140 */ 6141 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 6142 kvm_make_request(KVM_REQ_EVENT, vcpu); 6143 } else 6144 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 6145 6146 return r; 6147 } 6148 EXPORT_SYMBOL_GPL(x86_emulate_instruction); 6149 6150 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 6151 unsigned short port) 6152 { 6153 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 6154 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 6155 size, port, &val, 1); 6156 /* do not return to emulator after return from userspace */ 6157 vcpu->arch.pio.count = 0; 6158 return ret; 6159 } 6160 6161 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 6162 { 6163 unsigned long val; 6164 6165 /* We should only ever be called with arch.pio.count equal to 1 */ 6166 BUG_ON(vcpu->arch.pio.count != 1); 6167 6168 /* For size less than 4 we merge, else we zero extend */ 6169 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) 6170 : 0; 6171 6172 /* 6173 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform 6174 * the copy and tracing 6175 */ 6176 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size, 6177 vcpu->arch.pio.port, &val, 1); 6178 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 6179 6180 return 1; 6181 } 6182 6183 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 6184 unsigned short port) 6185 { 6186 unsigned long val; 6187 int ret; 6188 6189 /* For size less than 4 we merge, else we zero extend */ 6190 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0; 6191 6192 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port, 6193 &val, 1); 6194 if (ret) { 6195 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 6196 return ret; 6197 } 6198 6199 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 6200 6201 return 0; 6202 } 6203 6204 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 6205 { 6206 int ret = kvm_skip_emulated_instruction(vcpu); 6207 6208 /* 6209 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered 6210 * KVM_EXIT_DEBUG here. 6211 */ 6212 if (in) 6213 return kvm_fast_pio_in(vcpu, size, port) && ret; 6214 else 6215 return kvm_fast_pio_out(vcpu, size, port) && ret; 6216 } 6217 EXPORT_SYMBOL_GPL(kvm_fast_pio); 6218 6219 static int kvmclock_cpu_down_prep(unsigned int cpu) 6220 { 6221 __this_cpu_write(cpu_tsc_khz, 0); 6222 return 0; 6223 } 6224 6225 static void tsc_khz_changed(void *data) 6226 { 6227 struct cpufreq_freqs *freq = data; 6228 unsigned long khz = 0; 6229 6230 if (data) 6231 khz = freq->new; 6232 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 6233 khz = cpufreq_quick_get(raw_smp_processor_id()); 6234 if (!khz) 6235 khz = tsc_khz; 6236 __this_cpu_write(cpu_tsc_khz, khz); 6237 } 6238 6239 #ifdef CONFIG_X86_64 6240 static void kvm_hyperv_tsc_notifier(void) 6241 { 6242 struct kvm *kvm; 6243 struct kvm_vcpu *vcpu; 6244 int cpu; 6245 6246 spin_lock(&kvm_lock); 6247 list_for_each_entry(kvm, &vm_list, vm_list) 6248 kvm_make_mclock_inprogress_request(kvm); 6249 6250 hyperv_stop_tsc_emulation(); 6251 6252 /* TSC frequency always matches when on Hyper-V */ 6253 for_each_present_cpu(cpu) 6254 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 6255 kvm_max_guest_tsc_khz = tsc_khz; 6256 6257 list_for_each_entry(kvm, &vm_list, vm_list) { 6258 struct kvm_arch *ka = &kvm->arch; 6259 6260 spin_lock(&ka->pvclock_gtod_sync_lock); 6261 6262 pvclock_update_vm_gtod_copy(kvm); 6263 6264 kvm_for_each_vcpu(cpu, vcpu, kvm) 6265 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6266 6267 kvm_for_each_vcpu(cpu, vcpu, kvm) 6268 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 6269 6270 spin_unlock(&ka->pvclock_gtod_sync_lock); 6271 } 6272 spin_unlock(&kvm_lock); 6273 } 6274 #endif 6275 6276 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 6277 void *data) 6278 { 6279 struct cpufreq_freqs *freq = data; 6280 struct kvm *kvm; 6281 struct kvm_vcpu *vcpu; 6282 int i, send_ipi = 0; 6283 6284 /* 6285 * We allow guests to temporarily run on slowing clocks, 6286 * provided we notify them after, or to run on accelerating 6287 * clocks, provided we notify them before. Thus time never 6288 * goes backwards. 6289 * 6290 * However, we have a problem. We can't atomically update 6291 * the frequency of a given CPU from this function; it is 6292 * merely a notifier, which can be called from any CPU. 6293 * Changing the TSC frequency at arbitrary points in time 6294 * requires a recomputation of local variables related to 6295 * the TSC for each VCPU. We must flag these local variables 6296 * to be updated and be sure the update takes place with the 6297 * new frequency before any guests proceed. 6298 * 6299 * Unfortunately, the combination of hotplug CPU and frequency 6300 * change creates an intractable locking scenario; the order 6301 * of when these callouts happen is undefined with respect to 6302 * CPU hotplug, and they can race with each other. As such, 6303 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 6304 * undefined; you can actually have a CPU frequency change take 6305 * place in between the computation of X and the setting of the 6306 * variable. To protect against this problem, all updates of 6307 * the per_cpu tsc_khz variable are done in an interrupt 6308 * protected IPI, and all callers wishing to update the value 6309 * must wait for a synchronous IPI to complete (which is trivial 6310 * if the caller is on the CPU already). This establishes the 6311 * necessary total order on variable updates. 6312 * 6313 * Note that because a guest time update may take place 6314 * anytime after the setting of the VCPU's request bit, the 6315 * correct TSC value must be set before the request. However, 6316 * to ensure the update actually makes it to any guest which 6317 * starts running in hardware virtualization between the set 6318 * and the acquisition of the spinlock, we must also ping the 6319 * CPU after setting the request bit. 6320 * 6321 */ 6322 6323 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 6324 return 0; 6325 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 6326 return 0; 6327 6328 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 6329 6330 spin_lock(&kvm_lock); 6331 list_for_each_entry(kvm, &vm_list, vm_list) { 6332 kvm_for_each_vcpu(i, vcpu, kvm) { 6333 if (vcpu->cpu != freq->cpu) 6334 continue; 6335 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6336 if (vcpu->cpu != smp_processor_id()) 6337 send_ipi = 1; 6338 } 6339 } 6340 spin_unlock(&kvm_lock); 6341 6342 if (freq->old < freq->new && send_ipi) { 6343 /* 6344 * We upscale the frequency. Must make the guest 6345 * doesn't see old kvmclock values while running with 6346 * the new frequency, otherwise we risk the guest sees 6347 * time go backwards. 6348 * 6349 * In case we update the frequency for another cpu 6350 * (which might be in guest context) send an interrupt 6351 * to kick the cpu out of guest context. Next time 6352 * guest context is entered kvmclock will be updated, 6353 * so the guest will not see stale values. 6354 */ 6355 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 6356 } 6357 return 0; 6358 } 6359 6360 static struct notifier_block kvmclock_cpufreq_notifier_block = { 6361 .notifier_call = kvmclock_cpufreq_notifier 6362 }; 6363 6364 static int kvmclock_cpu_online(unsigned int cpu) 6365 { 6366 tsc_khz_changed(NULL); 6367 return 0; 6368 } 6369 6370 static void kvm_timer_init(void) 6371 { 6372 max_tsc_khz = tsc_khz; 6373 6374 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 6375 #ifdef CONFIG_CPU_FREQ 6376 struct cpufreq_policy policy; 6377 int cpu; 6378 6379 memset(&policy, 0, sizeof(policy)); 6380 cpu = get_cpu(); 6381 cpufreq_get_policy(&policy, cpu); 6382 if (policy.cpuinfo.max_freq) 6383 max_tsc_khz = policy.cpuinfo.max_freq; 6384 put_cpu(); 6385 #endif 6386 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 6387 CPUFREQ_TRANSITION_NOTIFIER); 6388 } 6389 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 6390 6391 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 6392 kvmclock_cpu_online, kvmclock_cpu_down_prep); 6393 } 6394 6395 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 6396 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); 6397 6398 int kvm_is_in_guest(void) 6399 { 6400 return __this_cpu_read(current_vcpu) != NULL; 6401 } 6402 6403 static int kvm_is_user_mode(void) 6404 { 6405 int user_mode = 3; 6406 6407 if (__this_cpu_read(current_vcpu)) 6408 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 6409 6410 return user_mode != 0; 6411 } 6412 6413 static unsigned long kvm_get_guest_ip(void) 6414 { 6415 unsigned long ip = 0; 6416 6417 if (__this_cpu_read(current_vcpu)) 6418 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 6419 6420 return ip; 6421 } 6422 6423 static struct perf_guest_info_callbacks kvm_guest_cbs = { 6424 .is_in_guest = kvm_is_in_guest, 6425 .is_user_mode = kvm_is_user_mode, 6426 .get_guest_ip = kvm_get_guest_ip, 6427 }; 6428 6429 static void kvm_set_mmio_spte_mask(void) 6430 { 6431 u64 mask; 6432 int maxphyaddr = boot_cpu_data.x86_phys_bits; 6433 6434 /* 6435 * Set the reserved bits and the present bit of an paging-structure 6436 * entry to generate page fault with PFER.RSV = 1. 6437 */ 6438 /* Mask the reserved physical address bits. */ 6439 mask = rsvd_bits(maxphyaddr, 51); 6440 6441 /* Set the present bit. */ 6442 mask |= 1ull; 6443 6444 #ifdef CONFIG_X86_64 6445 /* 6446 * If reserved bit is not supported, clear the present bit to disable 6447 * mmio page fault. 6448 */ 6449 if (maxphyaddr == 52) 6450 mask &= ~1ull; 6451 #endif 6452 6453 kvm_mmu_set_mmio_spte_mask(mask, mask); 6454 } 6455 6456 #ifdef CONFIG_X86_64 6457 static void pvclock_gtod_update_fn(struct work_struct *work) 6458 { 6459 struct kvm *kvm; 6460 6461 struct kvm_vcpu *vcpu; 6462 int i; 6463 6464 spin_lock(&kvm_lock); 6465 list_for_each_entry(kvm, &vm_list, vm_list) 6466 kvm_for_each_vcpu(i, vcpu, kvm) 6467 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 6468 atomic_set(&kvm_guest_has_master_clock, 0); 6469 spin_unlock(&kvm_lock); 6470 } 6471 6472 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 6473 6474 /* 6475 * Notification about pvclock gtod data update. 6476 */ 6477 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 6478 void *priv) 6479 { 6480 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 6481 struct timekeeper *tk = priv; 6482 6483 update_pvclock_gtod(tk); 6484 6485 /* disable master clock if host does not trust, or does not 6486 * use, TSC based clocksource. 6487 */ 6488 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 6489 atomic_read(&kvm_guest_has_master_clock) != 0) 6490 queue_work(system_long_wq, &pvclock_gtod_work); 6491 6492 return 0; 6493 } 6494 6495 static struct notifier_block pvclock_gtod_notifier = { 6496 .notifier_call = pvclock_gtod_notify, 6497 }; 6498 #endif 6499 6500 int kvm_arch_init(void *opaque) 6501 { 6502 int r; 6503 struct kvm_x86_ops *ops = opaque; 6504 6505 if (kvm_x86_ops) { 6506 printk(KERN_ERR "kvm: already loaded the other module\n"); 6507 r = -EEXIST; 6508 goto out; 6509 } 6510 6511 if (!ops->cpu_has_kvm_support()) { 6512 printk(KERN_ERR "kvm: no hardware support\n"); 6513 r = -EOPNOTSUPP; 6514 goto out; 6515 } 6516 if (ops->disabled_by_bios()) { 6517 printk(KERN_ERR "kvm: disabled by bios\n"); 6518 r = -EOPNOTSUPP; 6519 goto out; 6520 } 6521 6522 r = -ENOMEM; 6523 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 6524 if (!shared_msrs) { 6525 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 6526 goto out; 6527 } 6528 6529 r = kvm_mmu_module_init(); 6530 if (r) 6531 goto out_free_percpu; 6532 6533 kvm_set_mmio_spte_mask(); 6534 6535 kvm_x86_ops = ops; 6536 6537 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 6538 PT_DIRTY_MASK, PT64_NX_MASK, 0, 6539 PT_PRESENT_MASK, 0, sme_me_mask); 6540 kvm_timer_init(); 6541 6542 perf_register_guest_info_callbacks(&kvm_guest_cbs); 6543 6544 if (boot_cpu_has(X86_FEATURE_XSAVE)) 6545 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 6546 6547 kvm_lapic_init(); 6548 #ifdef CONFIG_X86_64 6549 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 6550 6551 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 6552 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 6553 #endif 6554 6555 return 0; 6556 6557 out_free_percpu: 6558 free_percpu(shared_msrs); 6559 out: 6560 return r; 6561 } 6562 6563 void kvm_arch_exit(void) 6564 { 6565 #ifdef CONFIG_X86_64 6566 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 6567 clear_hv_tscchange_cb(); 6568 #endif 6569 kvm_lapic_exit(); 6570 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 6571 6572 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 6573 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 6574 CPUFREQ_TRANSITION_NOTIFIER); 6575 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 6576 #ifdef CONFIG_X86_64 6577 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 6578 #endif 6579 kvm_x86_ops = NULL; 6580 kvm_mmu_module_exit(); 6581 free_percpu(shared_msrs); 6582 } 6583 6584 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 6585 { 6586 ++vcpu->stat.halt_exits; 6587 if (lapic_in_kernel(vcpu)) { 6588 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 6589 return 1; 6590 } else { 6591 vcpu->run->exit_reason = KVM_EXIT_HLT; 6592 return 0; 6593 } 6594 } 6595 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 6596 6597 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 6598 { 6599 int ret = kvm_skip_emulated_instruction(vcpu); 6600 /* 6601 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 6602 * KVM_EXIT_DEBUG here. 6603 */ 6604 return kvm_vcpu_halt(vcpu) && ret; 6605 } 6606 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 6607 6608 #ifdef CONFIG_X86_64 6609 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 6610 unsigned long clock_type) 6611 { 6612 struct kvm_clock_pairing clock_pairing; 6613 struct timespec ts; 6614 u64 cycle; 6615 int ret; 6616 6617 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 6618 return -KVM_EOPNOTSUPP; 6619 6620 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) 6621 return -KVM_EOPNOTSUPP; 6622 6623 clock_pairing.sec = ts.tv_sec; 6624 clock_pairing.nsec = ts.tv_nsec; 6625 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 6626 clock_pairing.flags = 0; 6627 6628 ret = 0; 6629 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 6630 sizeof(struct kvm_clock_pairing))) 6631 ret = -KVM_EFAULT; 6632 6633 return ret; 6634 } 6635 #endif 6636 6637 /* 6638 * kvm_pv_kick_cpu_op: Kick a vcpu. 6639 * 6640 * @apicid - apicid of vcpu to be kicked. 6641 */ 6642 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 6643 { 6644 struct kvm_lapic_irq lapic_irq; 6645 6646 lapic_irq.shorthand = 0; 6647 lapic_irq.dest_mode = 0; 6648 lapic_irq.level = 0; 6649 lapic_irq.dest_id = apicid; 6650 lapic_irq.msi_redir_hint = false; 6651 6652 lapic_irq.delivery_mode = APIC_DM_REMRD; 6653 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 6654 } 6655 6656 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) 6657 { 6658 vcpu->arch.apicv_active = false; 6659 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); 6660 } 6661 6662 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 6663 { 6664 unsigned long nr, a0, a1, a2, a3, ret; 6665 int op_64_bit, r; 6666 6667 r = kvm_skip_emulated_instruction(vcpu); 6668 6669 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 6670 return kvm_hv_hypercall(vcpu); 6671 6672 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 6673 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 6674 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 6675 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 6676 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 6677 6678 trace_kvm_hypercall(nr, a0, a1, a2, a3); 6679 6680 op_64_bit = is_64_bit_mode(vcpu); 6681 if (!op_64_bit) { 6682 nr &= 0xFFFFFFFF; 6683 a0 &= 0xFFFFFFFF; 6684 a1 &= 0xFFFFFFFF; 6685 a2 &= 0xFFFFFFFF; 6686 a3 &= 0xFFFFFFFF; 6687 } 6688 6689 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 6690 ret = -KVM_EPERM; 6691 goto out; 6692 } 6693 6694 switch (nr) { 6695 case KVM_HC_VAPIC_POLL_IRQ: 6696 ret = 0; 6697 break; 6698 case KVM_HC_KICK_CPU: 6699 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 6700 ret = 0; 6701 break; 6702 #ifdef CONFIG_X86_64 6703 case KVM_HC_CLOCK_PAIRING: 6704 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 6705 break; 6706 #endif 6707 default: 6708 ret = -KVM_ENOSYS; 6709 break; 6710 } 6711 out: 6712 if (!op_64_bit) 6713 ret = (u32)ret; 6714 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 6715 ++vcpu->stat.hypercalls; 6716 return r; 6717 } 6718 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 6719 6720 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 6721 { 6722 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6723 char instruction[3]; 6724 unsigned long rip = kvm_rip_read(vcpu); 6725 6726 kvm_x86_ops->patch_hypercall(vcpu, instruction); 6727 6728 return emulator_write_emulated(ctxt, rip, instruction, 3, 6729 &ctxt->exception); 6730 } 6731 6732 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 6733 { 6734 return vcpu->run->request_interrupt_window && 6735 likely(!pic_in_kernel(vcpu->kvm)); 6736 } 6737 6738 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 6739 { 6740 struct kvm_run *kvm_run = vcpu->run; 6741 6742 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 6743 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 6744 kvm_run->cr8 = kvm_get_cr8(vcpu); 6745 kvm_run->apic_base = kvm_get_apic_base(vcpu); 6746 kvm_run->ready_for_interrupt_injection = 6747 pic_in_kernel(vcpu->kvm) || 6748 kvm_vcpu_ready_for_interrupt_injection(vcpu); 6749 } 6750 6751 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 6752 { 6753 int max_irr, tpr; 6754 6755 if (!kvm_x86_ops->update_cr8_intercept) 6756 return; 6757 6758 if (!lapic_in_kernel(vcpu)) 6759 return; 6760 6761 if (vcpu->arch.apicv_active) 6762 return; 6763 6764 if (!vcpu->arch.apic->vapic_addr) 6765 max_irr = kvm_lapic_find_highest_irr(vcpu); 6766 else 6767 max_irr = -1; 6768 6769 if (max_irr != -1) 6770 max_irr >>= 4; 6771 6772 tpr = kvm_lapic_get_cr8(vcpu); 6773 6774 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 6775 } 6776 6777 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 6778 { 6779 int r; 6780 6781 /* try to reinject previous events if any */ 6782 6783 if (vcpu->arch.exception.injected) 6784 kvm_x86_ops->queue_exception(vcpu); 6785 /* 6786 * Do not inject an NMI or interrupt if there is a pending 6787 * exception. Exceptions and interrupts are recognized at 6788 * instruction boundaries, i.e. the start of an instruction. 6789 * Trap-like exceptions, e.g. #DB, have higher priority than 6790 * NMIs and interrupts, i.e. traps are recognized before an 6791 * NMI/interrupt that's pending on the same instruction. 6792 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 6793 * priority, but are only generated (pended) during instruction 6794 * execution, i.e. a pending fault-like exception means the 6795 * fault occurred on the *previous* instruction and must be 6796 * serviced prior to recognizing any new events in order to 6797 * fully complete the previous instruction. 6798 */ 6799 else if (!vcpu->arch.exception.pending) { 6800 if (vcpu->arch.nmi_injected) 6801 kvm_x86_ops->set_nmi(vcpu); 6802 else if (vcpu->arch.interrupt.injected) 6803 kvm_x86_ops->set_irq(vcpu); 6804 } 6805 6806 /* 6807 * Call check_nested_events() even if we reinjected a previous event 6808 * in order for caller to determine if it should require immediate-exit 6809 * from L2 to L1 due to pending L1 events which require exit 6810 * from L2 to L1. 6811 */ 6812 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6813 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6814 if (r != 0) 6815 return r; 6816 } 6817 6818 /* try to inject new event if pending */ 6819 if (vcpu->arch.exception.pending) { 6820 trace_kvm_inj_exception(vcpu->arch.exception.nr, 6821 vcpu->arch.exception.has_error_code, 6822 vcpu->arch.exception.error_code); 6823 6824 WARN_ON_ONCE(vcpu->arch.exception.injected); 6825 vcpu->arch.exception.pending = false; 6826 vcpu->arch.exception.injected = true; 6827 6828 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 6829 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 6830 X86_EFLAGS_RF); 6831 6832 if (vcpu->arch.exception.nr == DB_VECTOR && 6833 (vcpu->arch.dr7 & DR7_GD)) { 6834 vcpu->arch.dr7 &= ~DR7_GD; 6835 kvm_update_dr7(vcpu); 6836 } 6837 6838 kvm_x86_ops->queue_exception(vcpu); 6839 } 6840 6841 /* Don't consider new event if we re-injected an event */ 6842 if (kvm_event_needs_reinjection(vcpu)) 6843 return 0; 6844 6845 if (vcpu->arch.smi_pending && !is_smm(vcpu) && 6846 kvm_x86_ops->smi_allowed(vcpu)) { 6847 vcpu->arch.smi_pending = false; 6848 ++vcpu->arch.smi_count; 6849 enter_smm(vcpu); 6850 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { 6851 --vcpu->arch.nmi_pending; 6852 vcpu->arch.nmi_injected = true; 6853 kvm_x86_ops->set_nmi(vcpu); 6854 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 6855 /* 6856 * Because interrupts can be injected asynchronously, we are 6857 * calling check_nested_events again here to avoid a race condition. 6858 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 6859 * proposal and current concerns. Perhaps we should be setting 6860 * KVM_REQ_EVENT only on certain events and not unconditionally? 6861 */ 6862 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6863 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6864 if (r != 0) 6865 return r; 6866 } 6867 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 6868 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 6869 false); 6870 kvm_x86_ops->set_irq(vcpu); 6871 } 6872 } 6873 6874 return 0; 6875 } 6876 6877 static void process_nmi(struct kvm_vcpu *vcpu) 6878 { 6879 unsigned limit = 2; 6880 6881 /* 6882 * x86 is limited to one NMI running, and one NMI pending after it. 6883 * If an NMI is already in progress, limit further NMIs to just one. 6884 * Otherwise, allow two (and we'll inject the first one immediately). 6885 */ 6886 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 6887 limit = 1; 6888 6889 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 6890 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 6891 kvm_make_request(KVM_REQ_EVENT, vcpu); 6892 } 6893 6894 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 6895 { 6896 u32 flags = 0; 6897 flags |= seg->g << 23; 6898 flags |= seg->db << 22; 6899 flags |= seg->l << 21; 6900 flags |= seg->avl << 20; 6901 flags |= seg->present << 15; 6902 flags |= seg->dpl << 13; 6903 flags |= seg->s << 12; 6904 flags |= seg->type << 8; 6905 return flags; 6906 } 6907 6908 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 6909 { 6910 struct kvm_segment seg; 6911 int offset; 6912 6913 kvm_get_segment(vcpu, &seg, n); 6914 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 6915 6916 if (n < 3) 6917 offset = 0x7f84 + n * 12; 6918 else 6919 offset = 0x7f2c + (n - 3) * 12; 6920 6921 put_smstate(u32, buf, offset + 8, seg.base); 6922 put_smstate(u32, buf, offset + 4, seg.limit); 6923 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 6924 } 6925 6926 #ifdef CONFIG_X86_64 6927 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 6928 { 6929 struct kvm_segment seg; 6930 int offset; 6931 u16 flags; 6932 6933 kvm_get_segment(vcpu, &seg, n); 6934 offset = 0x7e00 + n * 16; 6935 6936 flags = enter_smm_get_segment_flags(&seg) >> 8; 6937 put_smstate(u16, buf, offset, seg.selector); 6938 put_smstate(u16, buf, offset + 2, flags); 6939 put_smstate(u32, buf, offset + 4, seg.limit); 6940 put_smstate(u64, buf, offset + 8, seg.base); 6941 } 6942 #endif 6943 6944 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 6945 { 6946 struct desc_ptr dt; 6947 struct kvm_segment seg; 6948 unsigned long val; 6949 int i; 6950 6951 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 6952 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 6953 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 6954 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 6955 6956 for (i = 0; i < 8; i++) 6957 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 6958 6959 kvm_get_dr(vcpu, 6, &val); 6960 put_smstate(u32, buf, 0x7fcc, (u32)val); 6961 kvm_get_dr(vcpu, 7, &val); 6962 put_smstate(u32, buf, 0x7fc8, (u32)val); 6963 6964 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6965 put_smstate(u32, buf, 0x7fc4, seg.selector); 6966 put_smstate(u32, buf, 0x7f64, seg.base); 6967 put_smstate(u32, buf, 0x7f60, seg.limit); 6968 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 6969 6970 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6971 put_smstate(u32, buf, 0x7fc0, seg.selector); 6972 put_smstate(u32, buf, 0x7f80, seg.base); 6973 put_smstate(u32, buf, 0x7f7c, seg.limit); 6974 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 6975 6976 kvm_x86_ops->get_gdt(vcpu, &dt); 6977 put_smstate(u32, buf, 0x7f74, dt.address); 6978 put_smstate(u32, buf, 0x7f70, dt.size); 6979 6980 kvm_x86_ops->get_idt(vcpu, &dt); 6981 put_smstate(u32, buf, 0x7f58, dt.address); 6982 put_smstate(u32, buf, 0x7f54, dt.size); 6983 6984 for (i = 0; i < 6; i++) 6985 enter_smm_save_seg_32(vcpu, buf, i); 6986 6987 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 6988 6989 /* revision id */ 6990 put_smstate(u32, buf, 0x7efc, 0x00020000); 6991 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 6992 } 6993 6994 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 6995 { 6996 #ifdef CONFIG_X86_64 6997 struct desc_ptr dt; 6998 struct kvm_segment seg; 6999 unsigned long val; 7000 int i; 7001 7002 for (i = 0; i < 16; i++) 7003 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 7004 7005 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 7006 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 7007 7008 kvm_get_dr(vcpu, 6, &val); 7009 put_smstate(u64, buf, 0x7f68, val); 7010 kvm_get_dr(vcpu, 7, &val); 7011 put_smstate(u64, buf, 0x7f60, val); 7012 7013 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 7014 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 7015 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 7016 7017 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 7018 7019 /* revision id */ 7020 put_smstate(u32, buf, 0x7efc, 0x00020064); 7021 7022 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 7023 7024 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 7025 put_smstate(u16, buf, 0x7e90, seg.selector); 7026 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 7027 put_smstate(u32, buf, 0x7e94, seg.limit); 7028 put_smstate(u64, buf, 0x7e98, seg.base); 7029 7030 kvm_x86_ops->get_idt(vcpu, &dt); 7031 put_smstate(u32, buf, 0x7e84, dt.size); 7032 put_smstate(u64, buf, 0x7e88, dt.address); 7033 7034 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 7035 put_smstate(u16, buf, 0x7e70, seg.selector); 7036 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 7037 put_smstate(u32, buf, 0x7e74, seg.limit); 7038 put_smstate(u64, buf, 0x7e78, seg.base); 7039 7040 kvm_x86_ops->get_gdt(vcpu, &dt); 7041 put_smstate(u32, buf, 0x7e64, dt.size); 7042 put_smstate(u64, buf, 0x7e68, dt.address); 7043 7044 for (i = 0; i < 6; i++) 7045 enter_smm_save_seg_64(vcpu, buf, i); 7046 #else 7047 WARN_ON_ONCE(1); 7048 #endif 7049 } 7050 7051 static void enter_smm(struct kvm_vcpu *vcpu) 7052 { 7053 struct kvm_segment cs, ds; 7054 struct desc_ptr dt; 7055 char buf[512]; 7056 u32 cr0; 7057 7058 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 7059 memset(buf, 0, 512); 7060 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 7061 enter_smm_save_state_64(vcpu, buf); 7062 else 7063 enter_smm_save_state_32(vcpu, buf); 7064 7065 /* 7066 * Give pre_enter_smm() a chance to make ISA-specific changes to the 7067 * vCPU state (e.g. leave guest mode) after we've saved the state into 7068 * the SMM state-save area. 7069 */ 7070 kvm_x86_ops->pre_enter_smm(vcpu, buf); 7071 7072 vcpu->arch.hflags |= HF_SMM_MASK; 7073 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 7074 7075 if (kvm_x86_ops->get_nmi_mask(vcpu)) 7076 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 7077 else 7078 kvm_x86_ops->set_nmi_mask(vcpu, true); 7079 7080 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 7081 kvm_rip_write(vcpu, 0x8000); 7082 7083 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 7084 kvm_x86_ops->set_cr0(vcpu, cr0); 7085 vcpu->arch.cr0 = cr0; 7086 7087 kvm_x86_ops->set_cr4(vcpu, 0); 7088 7089 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 7090 dt.address = dt.size = 0; 7091 kvm_x86_ops->set_idt(vcpu, &dt); 7092 7093 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 7094 7095 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 7096 cs.base = vcpu->arch.smbase; 7097 7098 ds.selector = 0; 7099 ds.base = 0; 7100 7101 cs.limit = ds.limit = 0xffffffff; 7102 cs.type = ds.type = 0x3; 7103 cs.dpl = ds.dpl = 0; 7104 cs.db = ds.db = 0; 7105 cs.s = ds.s = 1; 7106 cs.l = ds.l = 0; 7107 cs.g = ds.g = 1; 7108 cs.avl = ds.avl = 0; 7109 cs.present = ds.present = 1; 7110 cs.unusable = ds.unusable = 0; 7111 cs.padding = ds.padding = 0; 7112 7113 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7114 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 7115 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 7116 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 7117 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 7118 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 7119 7120 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 7121 kvm_x86_ops->set_efer(vcpu, 0); 7122 7123 kvm_update_cpuid(vcpu); 7124 kvm_mmu_reset_context(vcpu); 7125 } 7126 7127 static void process_smi(struct kvm_vcpu *vcpu) 7128 { 7129 vcpu->arch.smi_pending = true; 7130 kvm_make_request(KVM_REQ_EVENT, vcpu); 7131 } 7132 7133 void kvm_make_scan_ioapic_request(struct kvm *kvm) 7134 { 7135 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 7136 } 7137 7138 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 7139 { 7140 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 7141 return; 7142 7143 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 7144 7145 if (irqchip_split(vcpu->kvm)) 7146 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 7147 else { 7148 if (vcpu->arch.apicv_active) 7149 kvm_x86_ops->sync_pir_to_irr(vcpu); 7150 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 7151 } 7152 7153 if (is_guest_mode(vcpu)) 7154 vcpu->arch.load_eoi_exitmap_pending = true; 7155 else 7156 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 7157 } 7158 7159 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 7160 { 7161 u64 eoi_exit_bitmap[4]; 7162 7163 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 7164 return; 7165 7166 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, 7167 vcpu_to_synic(vcpu)->vec_bitmap, 256); 7168 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 7169 } 7170 7171 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 7172 unsigned long start, unsigned long end) 7173 { 7174 unsigned long apic_address; 7175 7176 /* 7177 * The physical address of apic access page is stored in the VMCS. 7178 * Update it when it becomes invalid. 7179 */ 7180 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 7181 if (start <= apic_address && apic_address < end) 7182 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 7183 } 7184 7185 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 7186 { 7187 struct page *page = NULL; 7188 7189 if (!lapic_in_kernel(vcpu)) 7190 return; 7191 7192 if (!kvm_x86_ops->set_apic_access_page_addr) 7193 return; 7194 7195 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 7196 if (is_error_page(page)) 7197 return; 7198 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 7199 7200 /* 7201 * Do not pin apic access page in memory, the MMU notifier 7202 * will call us again if it is migrated or swapped out. 7203 */ 7204 put_page(page); 7205 } 7206 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 7207 7208 /* 7209 * Returns 1 to let vcpu_run() continue the guest execution loop without 7210 * exiting to the userspace. Otherwise, the value will be returned to the 7211 * userspace. 7212 */ 7213 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 7214 { 7215 int r; 7216 bool req_int_win = 7217 dm_request_for_irq_injection(vcpu) && 7218 kvm_cpu_accept_dm_intr(vcpu); 7219 7220 bool req_immediate_exit = false; 7221 7222 if (kvm_request_pending(vcpu)) { 7223 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 7224 kvm_mmu_unload(vcpu); 7225 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 7226 __kvm_migrate_timers(vcpu); 7227 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 7228 kvm_gen_update_masterclock(vcpu->kvm); 7229 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 7230 kvm_gen_kvmclock_update(vcpu); 7231 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 7232 r = kvm_guest_time_update(vcpu); 7233 if (unlikely(r)) 7234 goto out; 7235 } 7236 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 7237 kvm_mmu_sync_roots(vcpu); 7238 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 7239 kvm_vcpu_flush_tlb(vcpu, true); 7240 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 7241 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 7242 r = 0; 7243 goto out; 7244 } 7245 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 7246 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 7247 vcpu->mmio_needed = 0; 7248 r = 0; 7249 goto out; 7250 } 7251 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 7252 /* Page is swapped out. Do synthetic halt */ 7253 vcpu->arch.apf.halted = true; 7254 r = 1; 7255 goto out; 7256 } 7257 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 7258 record_steal_time(vcpu); 7259 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 7260 process_smi(vcpu); 7261 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 7262 process_nmi(vcpu); 7263 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 7264 kvm_pmu_handle_event(vcpu); 7265 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 7266 kvm_pmu_deliver_pmi(vcpu); 7267 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 7268 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 7269 if (test_bit(vcpu->arch.pending_ioapic_eoi, 7270 vcpu->arch.ioapic_handled_vectors)) { 7271 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 7272 vcpu->run->eoi.vector = 7273 vcpu->arch.pending_ioapic_eoi; 7274 r = 0; 7275 goto out; 7276 } 7277 } 7278 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 7279 vcpu_scan_ioapic(vcpu); 7280 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 7281 vcpu_load_eoi_exitmap(vcpu); 7282 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 7283 kvm_vcpu_reload_apic_access_page(vcpu); 7284 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 7285 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 7286 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 7287 r = 0; 7288 goto out; 7289 } 7290 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 7291 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 7292 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 7293 r = 0; 7294 goto out; 7295 } 7296 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 7297 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 7298 vcpu->run->hyperv = vcpu->arch.hyperv.exit; 7299 r = 0; 7300 goto out; 7301 } 7302 7303 /* 7304 * KVM_REQ_HV_STIMER has to be processed after 7305 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 7306 * depend on the guest clock being up-to-date 7307 */ 7308 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 7309 kvm_hv_process_stimers(vcpu); 7310 } 7311 7312 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 7313 ++vcpu->stat.req_event; 7314 kvm_apic_accept_events(vcpu); 7315 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 7316 r = 1; 7317 goto out; 7318 } 7319 7320 if (inject_pending_event(vcpu, req_int_win) != 0) 7321 req_immediate_exit = true; 7322 else { 7323 /* Enable SMI/NMI/IRQ window open exits if needed. 7324 * 7325 * SMIs have three cases: 7326 * 1) They can be nested, and then there is nothing to 7327 * do here because RSM will cause a vmexit anyway. 7328 * 2) There is an ISA-specific reason why SMI cannot be 7329 * injected, and the moment when this changes can be 7330 * intercepted. 7331 * 3) Or the SMI can be pending because 7332 * inject_pending_event has completed the injection 7333 * of an IRQ or NMI from the previous vmexit, and 7334 * then we request an immediate exit to inject the 7335 * SMI. 7336 */ 7337 if (vcpu->arch.smi_pending && !is_smm(vcpu)) 7338 if (!kvm_x86_ops->enable_smi_window(vcpu)) 7339 req_immediate_exit = true; 7340 if (vcpu->arch.nmi_pending) 7341 kvm_x86_ops->enable_nmi_window(vcpu); 7342 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 7343 kvm_x86_ops->enable_irq_window(vcpu); 7344 WARN_ON(vcpu->arch.exception.pending); 7345 } 7346 7347 if (kvm_lapic_enabled(vcpu)) { 7348 update_cr8_intercept(vcpu); 7349 kvm_lapic_sync_to_vapic(vcpu); 7350 } 7351 } 7352 7353 r = kvm_mmu_reload(vcpu); 7354 if (unlikely(r)) { 7355 goto cancel_injection; 7356 } 7357 7358 preempt_disable(); 7359 7360 kvm_x86_ops->prepare_guest_switch(vcpu); 7361 7362 /* 7363 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 7364 * IPI are then delayed after guest entry, which ensures that they 7365 * result in virtual interrupt delivery. 7366 */ 7367 local_irq_disable(); 7368 vcpu->mode = IN_GUEST_MODE; 7369 7370 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 7371 7372 /* 7373 * 1) We should set ->mode before checking ->requests. Please see 7374 * the comment in kvm_vcpu_exiting_guest_mode(). 7375 * 7376 * 2) For APICv, we should set ->mode before checking PIR.ON. This 7377 * pairs with the memory barrier implicit in pi_test_and_set_on 7378 * (see vmx_deliver_posted_interrupt). 7379 * 7380 * 3) This also orders the write to mode from any reads to the page 7381 * tables done while the VCPU is running. Please see the comment 7382 * in kvm_flush_remote_tlbs. 7383 */ 7384 smp_mb__after_srcu_read_unlock(); 7385 7386 /* 7387 * This handles the case where a posted interrupt was 7388 * notified with kvm_vcpu_kick. 7389 */ 7390 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) 7391 kvm_x86_ops->sync_pir_to_irr(vcpu); 7392 7393 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) 7394 || need_resched() || signal_pending(current)) { 7395 vcpu->mode = OUTSIDE_GUEST_MODE; 7396 smp_wmb(); 7397 local_irq_enable(); 7398 preempt_enable(); 7399 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7400 r = 1; 7401 goto cancel_injection; 7402 } 7403 7404 kvm_load_guest_xcr0(vcpu); 7405 7406 if (req_immediate_exit) { 7407 kvm_make_request(KVM_REQ_EVENT, vcpu); 7408 smp_send_reschedule(vcpu->cpu); 7409 } 7410 7411 trace_kvm_entry(vcpu->vcpu_id); 7412 if (lapic_timer_advance_ns) 7413 wait_lapic_expire(vcpu); 7414 guest_enter_irqoff(); 7415 7416 if (unlikely(vcpu->arch.switch_db_regs)) { 7417 set_debugreg(0, 7); 7418 set_debugreg(vcpu->arch.eff_db[0], 0); 7419 set_debugreg(vcpu->arch.eff_db[1], 1); 7420 set_debugreg(vcpu->arch.eff_db[2], 2); 7421 set_debugreg(vcpu->arch.eff_db[3], 3); 7422 set_debugreg(vcpu->arch.dr6, 6); 7423 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 7424 } 7425 7426 kvm_x86_ops->run(vcpu); 7427 7428 /* 7429 * Do this here before restoring debug registers on the host. And 7430 * since we do this before handling the vmexit, a DR access vmexit 7431 * can (a) read the correct value of the debug registers, (b) set 7432 * KVM_DEBUGREG_WONT_EXIT again. 7433 */ 7434 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 7435 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 7436 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 7437 kvm_update_dr0123(vcpu); 7438 kvm_update_dr6(vcpu); 7439 kvm_update_dr7(vcpu); 7440 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 7441 } 7442 7443 /* 7444 * If the guest has used debug registers, at least dr7 7445 * will be disabled while returning to the host. 7446 * If we don't have active breakpoints in the host, we don't 7447 * care about the messed up debug address registers. But if 7448 * we have some of them active, restore the old state. 7449 */ 7450 if (hw_breakpoint_active()) 7451 hw_breakpoint_restore(); 7452 7453 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 7454 7455 vcpu->mode = OUTSIDE_GUEST_MODE; 7456 smp_wmb(); 7457 7458 kvm_put_guest_xcr0(vcpu); 7459 7460 kvm_before_interrupt(vcpu); 7461 kvm_x86_ops->handle_external_intr(vcpu); 7462 kvm_after_interrupt(vcpu); 7463 7464 ++vcpu->stat.exits; 7465 7466 guest_exit_irqoff(); 7467 7468 local_irq_enable(); 7469 preempt_enable(); 7470 7471 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7472 7473 /* 7474 * Profile KVM exit RIPs: 7475 */ 7476 if (unlikely(prof_on == KVM_PROFILING)) { 7477 unsigned long rip = kvm_rip_read(vcpu); 7478 profile_hit(KVM_PROFILING, (void *)rip); 7479 } 7480 7481 if (unlikely(vcpu->arch.tsc_always_catchup)) 7482 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7483 7484 if (vcpu->arch.apic_attention) 7485 kvm_lapic_sync_from_vapic(vcpu); 7486 7487 vcpu->arch.gpa_available = false; 7488 r = kvm_x86_ops->handle_exit(vcpu); 7489 return r; 7490 7491 cancel_injection: 7492 kvm_x86_ops->cancel_injection(vcpu); 7493 if (unlikely(vcpu->arch.apic_attention)) 7494 kvm_lapic_sync_from_vapic(vcpu); 7495 out: 7496 return r; 7497 } 7498 7499 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 7500 { 7501 if (!kvm_arch_vcpu_runnable(vcpu) && 7502 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { 7503 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7504 kvm_vcpu_block(vcpu); 7505 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7506 7507 if (kvm_x86_ops->post_block) 7508 kvm_x86_ops->post_block(vcpu); 7509 7510 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 7511 return 1; 7512 } 7513 7514 kvm_apic_accept_events(vcpu); 7515 switch(vcpu->arch.mp_state) { 7516 case KVM_MP_STATE_HALTED: 7517 vcpu->arch.pv.pv_unhalted = false; 7518 vcpu->arch.mp_state = 7519 KVM_MP_STATE_RUNNABLE; 7520 case KVM_MP_STATE_RUNNABLE: 7521 vcpu->arch.apf.halted = false; 7522 break; 7523 case KVM_MP_STATE_INIT_RECEIVED: 7524 break; 7525 default: 7526 return -EINTR; 7527 break; 7528 } 7529 return 1; 7530 } 7531 7532 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 7533 { 7534 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 7535 kvm_x86_ops->check_nested_events(vcpu, false); 7536 7537 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 7538 !vcpu->arch.apf.halted); 7539 } 7540 7541 static int vcpu_run(struct kvm_vcpu *vcpu) 7542 { 7543 int r; 7544 struct kvm *kvm = vcpu->kvm; 7545 7546 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7547 7548 for (;;) { 7549 if (kvm_vcpu_running(vcpu)) { 7550 r = vcpu_enter_guest(vcpu); 7551 } else { 7552 r = vcpu_block(kvm, vcpu); 7553 } 7554 7555 if (r <= 0) 7556 break; 7557 7558 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); 7559 if (kvm_cpu_has_pending_timer(vcpu)) 7560 kvm_inject_pending_timer_irqs(vcpu); 7561 7562 if (dm_request_for_irq_injection(vcpu) && 7563 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 7564 r = 0; 7565 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 7566 ++vcpu->stat.request_irq_exits; 7567 break; 7568 } 7569 7570 kvm_check_async_pf_completion(vcpu); 7571 7572 if (signal_pending(current)) { 7573 r = -EINTR; 7574 vcpu->run->exit_reason = KVM_EXIT_INTR; 7575 ++vcpu->stat.signal_exits; 7576 break; 7577 } 7578 if (need_resched()) { 7579 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7580 cond_resched(); 7581 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7582 } 7583 } 7584 7585 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7586 7587 return r; 7588 } 7589 7590 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 7591 { 7592 int r; 7593 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7594 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 7595 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 7596 if (r != EMULATE_DONE) 7597 return 0; 7598 return 1; 7599 } 7600 7601 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 7602 { 7603 BUG_ON(!vcpu->arch.pio.count); 7604 7605 return complete_emulated_io(vcpu); 7606 } 7607 7608 /* 7609 * Implements the following, as a state machine: 7610 * 7611 * read: 7612 * for each fragment 7613 * for each mmio piece in the fragment 7614 * write gpa, len 7615 * exit 7616 * copy data 7617 * execute insn 7618 * 7619 * write: 7620 * for each fragment 7621 * for each mmio piece in the fragment 7622 * write gpa, len 7623 * copy data 7624 * exit 7625 */ 7626 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 7627 { 7628 struct kvm_run *run = vcpu->run; 7629 struct kvm_mmio_fragment *frag; 7630 unsigned len; 7631 7632 BUG_ON(!vcpu->mmio_needed); 7633 7634 /* Complete previous fragment */ 7635 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 7636 len = min(8u, frag->len); 7637 if (!vcpu->mmio_is_write) 7638 memcpy(frag->data, run->mmio.data, len); 7639 7640 if (frag->len <= 8) { 7641 /* Switch to the next fragment. */ 7642 frag++; 7643 vcpu->mmio_cur_fragment++; 7644 } else { 7645 /* Go forward to the next mmio piece. */ 7646 frag->data += len; 7647 frag->gpa += len; 7648 frag->len -= len; 7649 } 7650 7651 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 7652 vcpu->mmio_needed = 0; 7653 7654 /* FIXME: return into emulator if single-stepping. */ 7655 if (vcpu->mmio_is_write) 7656 return 1; 7657 vcpu->mmio_read_completed = 1; 7658 return complete_emulated_io(vcpu); 7659 } 7660 7661 run->exit_reason = KVM_EXIT_MMIO; 7662 run->mmio.phys_addr = frag->gpa; 7663 if (vcpu->mmio_is_write) 7664 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 7665 run->mmio.len = min(8u, frag->len); 7666 run->mmio.is_write = vcpu->mmio_is_write; 7667 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 7668 return 0; 7669 } 7670 7671 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 7672 { 7673 int r; 7674 7675 vcpu_load(vcpu); 7676 kvm_sigset_activate(vcpu); 7677 kvm_load_guest_fpu(vcpu); 7678 7679 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 7680 if (kvm_run->immediate_exit) { 7681 r = -EINTR; 7682 goto out; 7683 } 7684 kvm_vcpu_block(vcpu); 7685 kvm_apic_accept_events(vcpu); 7686 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 7687 r = -EAGAIN; 7688 if (signal_pending(current)) { 7689 r = -EINTR; 7690 vcpu->run->exit_reason = KVM_EXIT_INTR; 7691 ++vcpu->stat.signal_exits; 7692 } 7693 goto out; 7694 } 7695 7696 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { 7697 r = -EINVAL; 7698 goto out; 7699 } 7700 7701 if (vcpu->run->kvm_dirty_regs) { 7702 r = sync_regs(vcpu); 7703 if (r != 0) 7704 goto out; 7705 } 7706 7707 /* re-sync apic's tpr */ 7708 if (!lapic_in_kernel(vcpu)) { 7709 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 7710 r = -EINVAL; 7711 goto out; 7712 } 7713 } 7714 7715 if (unlikely(vcpu->arch.complete_userspace_io)) { 7716 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 7717 vcpu->arch.complete_userspace_io = NULL; 7718 r = cui(vcpu); 7719 if (r <= 0) 7720 goto out; 7721 } else 7722 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 7723 7724 if (kvm_run->immediate_exit) 7725 r = -EINTR; 7726 else 7727 r = vcpu_run(vcpu); 7728 7729 out: 7730 kvm_put_guest_fpu(vcpu); 7731 if (vcpu->run->kvm_valid_regs) 7732 store_regs(vcpu); 7733 post_kvm_run_save(vcpu); 7734 kvm_sigset_deactivate(vcpu); 7735 7736 vcpu_put(vcpu); 7737 return r; 7738 } 7739 7740 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7741 { 7742 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 7743 /* 7744 * We are here if userspace calls get_regs() in the middle of 7745 * instruction emulation. Registers state needs to be copied 7746 * back from emulation context to vcpu. Userspace shouldn't do 7747 * that usually, but some bad designed PV devices (vmware 7748 * backdoor interface) need this to work 7749 */ 7750 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 7751 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7752 } 7753 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 7754 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 7755 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 7756 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 7757 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 7758 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 7759 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 7760 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 7761 #ifdef CONFIG_X86_64 7762 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 7763 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 7764 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 7765 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 7766 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 7767 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 7768 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 7769 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 7770 #endif 7771 7772 regs->rip = kvm_rip_read(vcpu); 7773 regs->rflags = kvm_get_rflags(vcpu); 7774 } 7775 7776 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7777 { 7778 vcpu_load(vcpu); 7779 __get_regs(vcpu, regs); 7780 vcpu_put(vcpu); 7781 return 0; 7782 } 7783 7784 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7785 { 7786 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 7787 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7788 7789 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 7790 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 7791 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 7792 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 7793 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 7794 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 7795 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 7796 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 7797 #ifdef CONFIG_X86_64 7798 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 7799 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 7800 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 7801 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 7802 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 7803 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 7804 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 7805 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 7806 #endif 7807 7808 kvm_rip_write(vcpu, regs->rip); 7809 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 7810 7811 vcpu->arch.exception.pending = false; 7812 7813 kvm_make_request(KVM_REQ_EVENT, vcpu); 7814 } 7815 7816 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7817 { 7818 vcpu_load(vcpu); 7819 __set_regs(vcpu, regs); 7820 vcpu_put(vcpu); 7821 return 0; 7822 } 7823 7824 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 7825 { 7826 struct kvm_segment cs; 7827 7828 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7829 *db = cs.db; 7830 *l = cs.l; 7831 } 7832 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 7833 7834 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 7835 { 7836 struct desc_ptr dt; 7837 7838 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7839 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7840 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7841 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7842 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7843 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7844 7845 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7846 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7847 7848 kvm_x86_ops->get_idt(vcpu, &dt); 7849 sregs->idt.limit = dt.size; 7850 sregs->idt.base = dt.address; 7851 kvm_x86_ops->get_gdt(vcpu, &dt); 7852 sregs->gdt.limit = dt.size; 7853 sregs->gdt.base = dt.address; 7854 7855 sregs->cr0 = kvm_read_cr0(vcpu); 7856 sregs->cr2 = vcpu->arch.cr2; 7857 sregs->cr3 = kvm_read_cr3(vcpu); 7858 sregs->cr4 = kvm_read_cr4(vcpu); 7859 sregs->cr8 = kvm_get_cr8(vcpu); 7860 sregs->efer = vcpu->arch.efer; 7861 sregs->apic_base = kvm_get_apic_base(vcpu); 7862 7863 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 7864 7865 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 7866 set_bit(vcpu->arch.interrupt.nr, 7867 (unsigned long *)sregs->interrupt_bitmap); 7868 } 7869 7870 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 7871 struct kvm_sregs *sregs) 7872 { 7873 vcpu_load(vcpu); 7874 __get_sregs(vcpu, sregs); 7875 vcpu_put(vcpu); 7876 return 0; 7877 } 7878 7879 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 7880 struct kvm_mp_state *mp_state) 7881 { 7882 vcpu_load(vcpu); 7883 7884 kvm_apic_accept_events(vcpu); 7885 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 7886 vcpu->arch.pv.pv_unhalted) 7887 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 7888 else 7889 mp_state->mp_state = vcpu->arch.mp_state; 7890 7891 vcpu_put(vcpu); 7892 return 0; 7893 } 7894 7895 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 7896 struct kvm_mp_state *mp_state) 7897 { 7898 int ret = -EINVAL; 7899 7900 vcpu_load(vcpu); 7901 7902 if (!lapic_in_kernel(vcpu) && 7903 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 7904 goto out; 7905 7906 /* INITs are latched while in SMM */ 7907 if ((is_smm(vcpu) || vcpu->arch.smi_pending) && 7908 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 7909 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 7910 goto out; 7911 7912 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 7913 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 7914 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 7915 } else 7916 vcpu->arch.mp_state = mp_state->mp_state; 7917 kvm_make_request(KVM_REQ_EVENT, vcpu); 7918 7919 ret = 0; 7920 out: 7921 vcpu_put(vcpu); 7922 return ret; 7923 } 7924 7925 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 7926 int reason, bool has_error_code, u32 error_code) 7927 { 7928 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 7929 int ret; 7930 7931 init_emulate_ctxt(vcpu); 7932 7933 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 7934 has_error_code, error_code); 7935 7936 if (ret) 7937 return EMULATE_FAIL; 7938 7939 kvm_rip_write(vcpu, ctxt->eip); 7940 kvm_set_rflags(vcpu, ctxt->eflags); 7941 kvm_make_request(KVM_REQ_EVENT, vcpu); 7942 return EMULATE_DONE; 7943 } 7944 EXPORT_SYMBOL_GPL(kvm_task_switch); 7945 7946 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 7947 { 7948 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 7949 /* 7950 * When EFER.LME and CR0.PG are set, the processor is in 7951 * 64-bit mode (though maybe in a 32-bit code segment). 7952 * CR4.PAE and EFER.LMA must be set. 7953 */ 7954 if (!(sregs->cr4 & X86_CR4_PAE) 7955 || !(sregs->efer & EFER_LMA)) 7956 return -EINVAL; 7957 } else { 7958 /* 7959 * Not in 64-bit mode: EFER.LMA is clear and the code 7960 * segment cannot be 64-bit. 7961 */ 7962 if (sregs->efer & EFER_LMA || sregs->cs.l) 7963 return -EINVAL; 7964 } 7965 7966 return 0; 7967 } 7968 7969 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 7970 { 7971 struct msr_data apic_base_msr; 7972 int mmu_reset_needed = 0; 7973 int pending_vec, max_bits, idx; 7974 struct desc_ptr dt; 7975 int ret = -EINVAL; 7976 7977 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 7978 (sregs->cr4 & X86_CR4_OSXSAVE)) 7979 goto out; 7980 7981 if (kvm_valid_sregs(vcpu, sregs)) 7982 goto out; 7983 7984 apic_base_msr.data = sregs->apic_base; 7985 apic_base_msr.host_initiated = true; 7986 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 7987 goto out; 7988 7989 dt.size = sregs->idt.limit; 7990 dt.address = sregs->idt.base; 7991 kvm_x86_ops->set_idt(vcpu, &dt); 7992 dt.size = sregs->gdt.limit; 7993 dt.address = sregs->gdt.base; 7994 kvm_x86_ops->set_gdt(vcpu, &dt); 7995 7996 vcpu->arch.cr2 = sregs->cr2; 7997 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 7998 vcpu->arch.cr3 = sregs->cr3; 7999 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 8000 8001 kvm_set_cr8(vcpu, sregs->cr8); 8002 8003 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 8004 kvm_x86_ops->set_efer(vcpu, sregs->efer); 8005 8006 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 8007 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 8008 vcpu->arch.cr0 = sregs->cr0; 8009 8010 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 8011 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 8012 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 8013 kvm_update_cpuid(vcpu); 8014 8015 idx = srcu_read_lock(&vcpu->kvm->srcu); 8016 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 8017 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 8018 mmu_reset_needed = 1; 8019 } 8020 srcu_read_unlock(&vcpu->kvm->srcu, idx); 8021 8022 if (mmu_reset_needed) 8023 kvm_mmu_reset_context(vcpu); 8024 8025 max_bits = KVM_NR_INTERRUPTS; 8026 pending_vec = find_first_bit( 8027 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 8028 if (pending_vec < max_bits) { 8029 kvm_queue_interrupt(vcpu, pending_vec, false); 8030 pr_debug("Set back pending irq %d\n", pending_vec); 8031 } 8032 8033 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 8034 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 8035 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 8036 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 8037 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 8038 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 8039 8040 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 8041 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 8042 8043 update_cr8_intercept(vcpu); 8044 8045 /* Older userspace won't unhalt the vcpu on reset. */ 8046 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 8047 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 8048 !is_protmode(vcpu)) 8049 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8050 8051 kvm_make_request(KVM_REQ_EVENT, vcpu); 8052 8053 ret = 0; 8054 out: 8055 return ret; 8056 } 8057 8058 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 8059 struct kvm_sregs *sregs) 8060 { 8061 int ret; 8062 8063 vcpu_load(vcpu); 8064 ret = __set_sregs(vcpu, sregs); 8065 vcpu_put(vcpu); 8066 return ret; 8067 } 8068 8069 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 8070 struct kvm_guest_debug *dbg) 8071 { 8072 unsigned long rflags; 8073 int i, r; 8074 8075 vcpu_load(vcpu); 8076 8077 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 8078 r = -EBUSY; 8079 if (vcpu->arch.exception.pending) 8080 goto out; 8081 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 8082 kvm_queue_exception(vcpu, DB_VECTOR); 8083 else 8084 kvm_queue_exception(vcpu, BP_VECTOR); 8085 } 8086 8087 /* 8088 * Read rflags as long as potentially injected trace flags are still 8089 * filtered out. 8090 */ 8091 rflags = kvm_get_rflags(vcpu); 8092 8093 vcpu->guest_debug = dbg->control; 8094 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 8095 vcpu->guest_debug = 0; 8096 8097 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 8098 for (i = 0; i < KVM_NR_DB_REGS; ++i) 8099 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 8100 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 8101 } else { 8102 for (i = 0; i < KVM_NR_DB_REGS; i++) 8103 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 8104 } 8105 kvm_update_dr7(vcpu); 8106 8107 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 8108 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 8109 get_segment_base(vcpu, VCPU_SREG_CS); 8110 8111 /* 8112 * Trigger an rflags update that will inject or remove the trace 8113 * flags. 8114 */ 8115 kvm_set_rflags(vcpu, rflags); 8116 8117 kvm_x86_ops->update_bp_intercept(vcpu); 8118 8119 r = 0; 8120 8121 out: 8122 vcpu_put(vcpu); 8123 return r; 8124 } 8125 8126 /* 8127 * Translate a guest virtual address to a guest physical address. 8128 */ 8129 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 8130 struct kvm_translation *tr) 8131 { 8132 unsigned long vaddr = tr->linear_address; 8133 gpa_t gpa; 8134 int idx; 8135 8136 vcpu_load(vcpu); 8137 8138 idx = srcu_read_lock(&vcpu->kvm->srcu); 8139 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 8140 srcu_read_unlock(&vcpu->kvm->srcu, idx); 8141 tr->physical_address = gpa; 8142 tr->valid = gpa != UNMAPPED_GVA; 8143 tr->writeable = 1; 8144 tr->usermode = 0; 8145 8146 vcpu_put(vcpu); 8147 return 0; 8148 } 8149 8150 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 8151 { 8152 struct fxregs_state *fxsave; 8153 8154 vcpu_load(vcpu); 8155 8156 fxsave = &vcpu->arch.guest_fpu.state.fxsave; 8157 memcpy(fpu->fpr, fxsave->st_space, 128); 8158 fpu->fcw = fxsave->cwd; 8159 fpu->fsw = fxsave->swd; 8160 fpu->ftwx = fxsave->twd; 8161 fpu->last_opcode = fxsave->fop; 8162 fpu->last_ip = fxsave->rip; 8163 fpu->last_dp = fxsave->rdp; 8164 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 8165 8166 vcpu_put(vcpu); 8167 return 0; 8168 } 8169 8170 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 8171 { 8172 struct fxregs_state *fxsave; 8173 8174 vcpu_load(vcpu); 8175 8176 fxsave = &vcpu->arch.guest_fpu.state.fxsave; 8177 8178 memcpy(fxsave->st_space, fpu->fpr, 128); 8179 fxsave->cwd = fpu->fcw; 8180 fxsave->swd = fpu->fsw; 8181 fxsave->twd = fpu->ftwx; 8182 fxsave->fop = fpu->last_opcode; 8183 fxsave->rip = fpu->last_ip; 8184 fxsave->rdp = fpu->last_dp; 8185 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 8186 8187 vcpu_put(vcpu); 8188 return 0; 8189 } 8190 8191 static void store_regs(struct kvm_vcpu *vcpu) 8192 { 8193 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 8194 8195 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 8196 __get_regs(vcpu, &vcpu->run->s.regs.regs); 8197 8198 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 8199 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 8200 8201 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 8202 kvm_vcpu_ioctl_x86_get_vcpu_events( 8203 vcpu, &vcpu->run->s.regs.events); 8204 } 8205 8206 static int sync_regs(struct kvm_vcpu *vcpu) 8207 { 8208 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) 8209 return -EINVAL; 8210 8211 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 8212 __set_regs(vcpu, &vcpu->run->s.regs.regs); 8213 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 8214 } 8215 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 8216 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 8217 return -EINVAL; 8218 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 8219 } 8220 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 8221 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 8222 vcpu, &vcpu->run->s.regs.events)) 8223 return -EINVAL; 8224 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 8225 } 8226 8227 return 0; 8228 } 8229 8230 static void fx_init(struct kvm_vcpu *vcpu) 8231 { 8232 fpstate_init(&vcpu->arch.guest_fpu.state); 8233 if (boot_cpu_has(X86_FEATURE_XSAVES)) 8234 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv = 8235 host_xcr0 | XSTATE_COMPACTION_ENABLED; 8236 8237 /* 8238 * Ensure guest xcr0 is valid for loading 8239 */ 8240 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 8241 8242 vcpu->arch.cr0 |= X86_CR0_ET; 8243 } 8244 8245 /* Swap (qemu) user FPU context for the guest FPU context. */ 8246 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 8247 { 8248 preempt_disable(); 8249 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu); 8250 /* PKRU is separately restored in kvm_x86_ops->run. */ 8251 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state, 8252 ~XFEATURE_MASK_PKRU); 8253 preempt_enable(); 8254 trace_kvm_fpu(1); 8255 } 8256 8257 /* When vcpu_run ends, restore user space FPU context. */ 8258 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 8259 { 8260 preempt_disable(); 8261 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu); 8262 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state); 8263 preempt_enable(); 8264 ++vcpu->stat.fpu_reload; 8265 trace_kvm_fpu(0); 8266 } 8267 8268 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 8269 { 8270 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask; 8271 8272 kvmclock_reset(vcpu); 8273 8274 kvm_x86_ops->vcpu_free(vcpu); 8275 free_cpumask_var(wbinvd_dirty_mask); 8276 } 8277 8278 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 8279 unsigned int id) 8280 { 8281 struct kvm_vcpu *vcpu; 8282 8283 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 8284 printk_once(KERN_WARNING 8285 "kvm: SMP vm created on host with unstable TSC; " 8286 "guest TSC will not be reliable\n"); 8287 8288 vcpu = kvm_x86_ops->vcpu_create(kvm, id); 8289 8290 return vcpu; 8291 } 8292 8293 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 8294 { 8295 kvm_vcpu_mtrr_init(vcpu); 8296 vcpu_load(vcpu); 8297 kvm_vcpu_reset(vcpu, false); 8298 kvm_mmu_setup(vcpu); 8299 vcpu_put(vcpu); 8300 return 0; 8301 } 8302 8303 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 8304 { 8305 struct msr_data msr; 8306 struct kvm *kvm = vcpu->kvm; 8307 8308 kvm_hv_vcpu_postcreate(vcpu); 8309 8310 if (mutex_lock_killable(&vcpu->mutex)) 8311 return; 8312 vcpu_load(vcpu); 8313 msr.data = 0x0; 8314 msr.index = MSR_IA32_TSC; 8315 msr.host_initiated = true; 8316 kvm_write_tsc(vcpu, &msr); 8317 vcpu_put(vcpu); 8318 mutex_unlock(&vcpu->mutex); 8319 8320 if (!kvmclock_periodic_sync) 8321 return; 8322 8323 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 8324 KVMCLOCK_SYNC_PERIOD); 8325 } 8326 8327 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 8328 { 8329 vcpu->arch.apf.msr_val = 0; 8330 8331 vcpu_load(vcpu); 8332 kvm_mmu_unload(vcpu); 8333 vcpu_put(vcpu); 8334 8335 kvm_x86_ops->vcpu_free(vcpu); 8336 } 8337 8338 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 8339 { 8340 kvm_lapic_reset(vcpu, init_event); 8341 8342 vcpu->arch.hflags = 0; 8343 8344 vcpu->arch.smi_pending = 0; 8345 vcpu->arch.smi_count = 0; 8346 atomic_set(&vcpu->arch.nmi_queued, 0); 8347 vcpu->arch.nmi_pending = 0; 8348 vcpu->arch.nmi_injected = false; 8349 kvm_clear_interrupt_queue(vcpu); 8350 kvm_clear_exception_queue(vcpu); 8351 vcpu->arch.exception.pending = false; 8352 8353 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 8354 kvm_update_dr0123(vcpu); 8355 vcpu->arch.dr6 = DR6_INIT; 8356 kvm_update_dr6(vcpu); 8357 vcpu->arch.dr7 = DR7_FIXED_1; 8358 kvm_update_dr7(vcpu); 8359 8360 vcpu->arch.cr2 = 0; 8361 8362 kvm_make_request(KVM_REQ_EVENT, vcpu); 8363 vcpu->arch.apf.msr_val = 0; 8364 vcpu->arch.st.msr_val = 0; 8365 8366 kvmclock_reset(vcpu); 8367 8368 kvm_clear_async_pf_completion_queue(vcpu); 8369 kvm_async_pf_hash_reset(vcpu); 8370 vcpu->arch.apf.halted = false; 8371 8372 if (kvm_mpx_supported()) { 8373 void *mpx_state_buffer; 8374 8375 /* 8376 * To avoid have the INIT path from kvm_apic_has_events() that be 8377 * called with loaded FPU and does not let userspace fix the state. 8378 */ 8379 if (init_event) 8380 kvm_put_guest_fpu(vcpu); 8381 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave, 8382 XFEATURE_MASK_BNDREGS); 8383 if (mpx_state_buffer) 8384 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); 8385 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave, 8386 XFEATURE_MASK_BNDCSR); 8387 if (mpx_state_buffer) 8388 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); 8389 if (init_event) 8390 kvm_load_guest_fpu(vcpu); 8391 } 8392 8393 if (!init_event) { 8394 kvm_pmu_reset(vcpu); 8395 vcpu->arch.smbase = 0x30000; 8396 8397 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 8398 vcpu->arch.msr_misc_features_enables = 0; 8399 8400 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 8401 } 8402 8403 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 8404 vcpu->arch.regs_avail = ~0; 8405 vcpu->arch.regs_dirty = ~0; 8406 8407 vcpu->arch.ia32_xss = 0; 8408 8409 kvm_x86_ops->vcpu_reset(vcpu, init_event); 8410 } 8411 8412 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 8413 { 8414 struct kvm_segment cs; 8415 8416 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 8417 cs.selector = vector << 8; 8418 cs.base = vector << 12; 8419 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 8420 kvm_rip_write(vcpu, 0); 8421 } 8422 8423 int kvm_arch_hardware_enable(void) 8424 { 8425 struct kvm *kvm; 8426 struct kvm_vcpu *vcpu; 8427 int i; 8428 int ret; 8429 u64 local_tsc; 8430 u64 max_tsc = 0; 8431 bool stable, backwards_tsc = false; 8432 8433 kvm_shared_msr_cpu_online(); 8434 ret = kvm_x86_ops->hardware_enable(); 8435 if (ret != 0) 8436 return ret; 8437 8438 local_tsc = rdtsc(); 8439 stable = !kvm_check_tsc_unstable(); 8440 list_for_each_entry(kvm, &vm_list, vm_list) { 8441 kvm_for_each_vcpu(i, vcpu, kvm) { 8442 if (!stable && vcpu->cpu == smp_processor_id()) 8443 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 8444 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 8445 backwards_tsc = true; 8446 if (vcpu->arch.last_host_tsc > max_tsc) 8447 max_tsc = vcpu->arch.last_host_tsc; 8448 } 8449 } 8450 } 8451 8452 /* 8453 * Sometimes, even reliable TSCs go backwards. This happens on 8454 * platforms that reset TSC during suspend or hibernate actions, but 8455 * maintain synchronization. We must compensate. Fortunately, we can 8456 * detect that condition here, which happens early in CPU bringup, 8457 * before any KVM threads can be running. Unfortunately, we can't 8458 * bring the TSCs fully up to date with real time, as we aren't yet far 8459 * enough into CPU bringup that we know how much real time has actually 8460 * elapsed; our helper function, ktime_get_boot_ns() will be using boot 8461 * variables that haven't been updated yet. 8462 * 8463 * So we simply find the maximum observed TSC above, then record the 8464 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 8465 * the adjustment will be applied. Note that we accumulate 8466 * adjustments, in case multiple suspend cycles happen before some VCPU 8467 * gets a chance to run again. In the event that no KVM threads get a 8468 * chance to run, we will miss the entire elapsed period, as we'll have 8469 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 8470 * loose cycle time. This isn't too big a deal, since the loss will be 8471 * uniform across all VCPUs (not to mention the scenario is extremely 8472 * unlikely). It is possible that a second hibernate recovery happens 8473 * much faster than a first, causing the observed TSC here to be 8474 * smaller; this would require additional padding adjustment, which is 8475 * why we set last_host_tsc to the local tsc observed here. 8476 * 8477 * N.B. - this code below runs only on platforms with reliable TSC, 8478 * as that is the only way backwards_tsc is set above. Also note 8479 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 8480 * have the same delta_cyc adjustment applied if backwards_tsc 8481 * is detected. Note further, this adjustment is only done once, 8482 * as we reset last_host_tsc on all VCPUs to stop this from being 8483 * called multiple times (one for each physical CPU bringup). 8484 * 8485 * Platforms with unreliable TSCs don't have to deal with this, they 8486 * will be compensated by the logic in vcpu_load, which sets the TSC to 8487 * catchup mode. This will catchup all VCPUs to real time, but cannot 8488 * guarantee that they stay in perfect synchronization. 8489 */ 8490 if (backwards_tsc) { 8491 u64 delta_cyc = max_tsc - local_tsc; 8492 list_for_each_entry(kvm, &vm_list, vm_list) { 8493 kvm->arch.backwards_tsc_observed = true; 8494 kvm_for_each_vcpu(i, vcpu, kvm) { 8495 vcpu->arch.tsc_offset_adjustment += delta_cyc; 8496 vcpu->arch.last_host_tsc = local_tsc; 8497 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 8498 } 8499 8500 /* 8501 * We have to disable TSC offset matching.. if you were 8502 * booting a VM while issuing an S4 host suspend.... 8503 * you may have some problem. Solving this issue is 8504 * left as an exercise to the reader. 8505 */ 8506 kvm->arch.last_tsc_nsec = 0; 8507 kvm->arch.last_tsc_write = 0; 8508 } 8509 8510 } 8511 return 0; 8512 } 8513 8514 void kvm_arch_hardware_disable(void) 8515 { 8516 kvm_x86_ops->hardware_disable(); 8517 drop_user_return_notifiers(); 8518 } 8519 8520 int kvm_arch_hardware_setup(void) 8521 { 8522 int r; 8523 8524 r = kvm_x86_ops->hardware_setup(); 8525 if (r != 0) 8526 return r; 8527 8528 if (kvm_has_tsc_control) { 8529 /* 8530 * Make sure the user can only configure tsc_khz values that 8531 * fit into a signed integer. 8532 * A min value is not calculated needed because it will always 8533 * be 1 on all machines. 8534 */ 8535 u64 max = min(0x7fffffffULL, 8536 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 8537 kvm_max_guest_tsc_khz = max; 8538 8539 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 8540 } 8541 8542 kvm_init_msr_list(); 8543 return 0; 8544 } 8545 8546 void kvm_arch_hardware_unsetup(void) 8547 { 8548 kvm_x86_ops->hardware_unsetup(); 8549 } 8550 8551 void kvm_arch_check_processor_compat(void *rtn) 8552 { 8553 kvm_x86_ops->check_processor_compatibility(rtn); 8554 } 8555 8556 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 8557 { 8558 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 8559 } 8560 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 8561 8562 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 8563 { 8564 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 8565 } 8566 8567 struct static_key kvm_no_apic_vcpu __read_mostly; 8568 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); 8569 8570 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 8571 { 8572 struct page *page; 8573 int r; 8574 8575 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu); 8576 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 8577 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 8578 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8579 else 8580 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 8581 8582 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 8583 if (!page) { 8584 r = -ENOMEM; 8585 goto fail; 8586 } 8587 vcpu->arch.pio_data = page_address(page); 8588 8589 kvm_set_tsc_khz(vcpu, max_tsc_khz); 8590 8591 r = kvm_mmu_create(vcpu); 8592 if (r < 0) 8593 goto fail_free_pio_data; 8594 8595 if (irqchip_in_kernel(vcpu->kvm)) { 8596 r = kvm_create_lapic(vcpu); 8597 if (r < 0) 8598 goto fail_mmu_destroy; 8599 } else 8600 static_key_slow_inc(&kvm_no_apic_vcpu); 8601 8602 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 8603 GFP_KERNEL); 8604 if (!vcpu->arch.mce_banks) { 8605 r = -ENOMEM; 8606 goto fail_free_lapic; 8607 } 8608 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 8609 8610 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 8611 r = -ENOMEM; 8612 goto fail_free_mce_banks; 8613 } 8614 8615 fx_init(vcpu); 8616 8617 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 8618 8619 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 8620 8621 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 8622 8623 kvm_async_pf_hash_reset(vcpu); 8624 kvm_pmu_init(vcpu); 8625 8626 vcpu->arch.pending_external_vector = -1; 8627 vcpu->arch.preempted_in_kernel = false; 8628 8629 kvm_hv_vcpu_init(vcpu); 8630 8631 return 0; 8632 8633 fail_free_mce_banks: 8634 kfree(vcpu->arch.mce_banks); 8635 fail_free_lapic: 8636 kvm_free_lapic(vcpu); 8637 fail_mmu_destroy: 8638 kvm_mmu_destroy(vcpu); 8639 fail_free_pio_data: 8640 free_page((unsigned long)vcpu->arch.pio_data); 8641 fail: 8642 return r; 8643 } 8644 8645 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 8646 { 8647 int idx; 8648 8649 kvm_hv_vcpu_uninit(vcpu); 8650 kvm_pmu_destroy(vcpu); 8651 kfree(vcpu->arch.mce_banks); 8652 kvm_free_lapic(vcpu); 8653 idx = srcu_read_lock(&vcpu->kvm->srcu); 8654 kvm_mmu_destroy(vcpu); 8655 srcu_read_unlock(&vcpu->kvm->srcu, idx); 8656 free_page((unsigned long)vcpu->arch.pio_data); 8657 if (!lapic_in_kernel(vcpu)) 8658 static_key_slow_dec(&kvm_no_apic_vcpu); 8659 } 8660 8661 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 8662 { 8663 kvm_x86_ops->sched_in(vcpu, cpu); 8664 } 8665 8666 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 8667 { 8668 if (type) 8669 return -EINVAL; 8670 8671 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 8672 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 8673 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 8674 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 8675 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 8676 8677 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 8678 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 8679 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 8680 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 8681 &kvm->arch.irq_sources_bitmap); 8682 8683 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 8684 mutex_init(&kvm->arch.apic_map_lock); 8685 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 8686 8687 kvm->arch.kvmclock_offset = -ktime_get_boot_ns(); 8688 pvclock_update_vm_gtod_copy(kvm); 8689 8690 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 8691 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 8692 8693 kvm_hv_init_vm(kvm); 8694 kvm_page_track_init(kvm); 8695 kvm_mmu_init_vm(kvm); 8696 8697 if (kvm_x86_ops->vm_init) 8698 return kvm_x86_ops->vm_init(kvm); 8699 8700 return 0; 8701 } 8702 8703 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 8704 { 8705 vcpu_load(vcpu); 8706 kvm_mmu_unload(vcpu); 8707 vcpu_put(vcpu); 8708 } 8709 8710 static void kvm_free_vcpus(struct kvm *kvm) 8711 { 8712 unsigned int i; 8713 struct kvm_vcpu *vcpu; 8714 8715 /* 8716 * Unpin any mmu pages first. 8717 */ 8718 kvm_for_each_vcpu(i, vcpu, kvm) { 8719 kvm_clear_async_pf_completion_queue(vcpu); 8720 kvm_unload_vcpu_mmu(vcpu); 8721 } 8722 kvm_for_each_vcpu(i, vcpu, kvm) 8723 kvm_arch_vcpu_free(vcpu); 8724 8725 mutex_lock(&kvm->lock); 8726 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 8727 kvm->vcpus[i] = NULL; 8728 8729 atomic_set(&kvm->online_vcpus, 0); 8730 mutex_unlock(&kvm->lock); 8731 } 8732 8733 void kvm_arch_sync_events(struct kvm *kvm) 8734 { 8735 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 8736 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 8737 kvm_free_pit(kvm); 8738 } 8739 8740 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 8741 { 8742 int i, r; 8743 unsigned long hva; 8744 struct kvm_memslots *slots = kvm_memslots(kvm); 8745 struct kvm_memory_slot *slot, old; 8746 8747 /* Called with kvm->slots_lock held. */ 8748 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 8749 return -EINVAL; 8750 8751 slot = id_to_memslot(slots, id); 8752 if (size) { 8753 if (slot->npages) 8754 return -EEXIST; 8755 8756 /* 8757 * MAP_SHARED to prevent internal slot pages from being moved 8758 * by fork()/COW. 8759 */ 8760 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 8761 MAP_SHARED | MAP_ANONYMOUS, 0); 8762 if (IS_ERR((void *)hva)) 8763 return PTR_ERR((void *)hva); 8764 } else { 8765 if (!slot->npages) 8766 return 0; 8767 8768 hva = 0; 8769 } 8770 8771 old = *slot; 8772 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 8773 struct kvm_userspace_memory_region m; 8774 8775 m.slot = id | (i << 16); 8776 m.flags = 0; 8777 m.guest_phys_addr = gpa; 8778 m.userspace_addr = hva; 8779 m.memory_size = size; 8780 r = __kvm_set_memory_region(kvm, &m); 8781 if (r < 0) 8782 return r; 8783 } 8784 8785 if (!size) 8786 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); 8787 8788 return 0; 8789 } 8790 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 8791 8792 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 8793 { 8794 int r; 8795 8796 mutex_lock(&kvm->slots_lock); 8797 r = __x86_set_memory_region(kvm, id, gpa, size); 8798 mutex_unlock(&kvm->slots_lock); 8799 8800 return r; 8801 } 8802 EXPORT_SYMBOL_GPL(x86_set_memory_region); 8803 8804 void kvm_arch_destroy_vm(struct kvm *kvm) 8805 { 8806 if (current->mm == kvm->mm) { 8807 /* 8808 * Free memory regions allocated on behalf of userspace, 8809 * unless the the memory map has changed due to process exit 8810 * or fd copying. 8811 */ 8812 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); 8813 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); 8814 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 8815 } 8816 if (kvm_x86_ops->vm_destroy) 8817 kvm_x86_ops->vm_destroy(kvm); 8818 kvm_pic_destroy(kvm); 8819 kvm_ioapic_destroy(kvm); 8820 kvm_free_vcpus(kvm); 8821 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 8822 kvm_mmu_uninit_vm(kvm); 8823 kvm_page_track_cleanup(kvm); 8824 kvm_hv_destroy_vm(kvm); 8825 } 8826 8827 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 8828 struct kvm_memory_slot *dont) 8829 { 8830 int i; 8831 8832 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8833 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 8834 kvfree(free->arch.rmap[i]); 8835 free->arch.rmap[i] = NULL; 8836 } 8837 if (i == 0) 8838 continue; 8839 8840 if (!dont || free->arch.lpage_info[i - 1] != 8841 dont->arch.lpage_info[i - 1]) { 8842 kvfree(free->arch.lpage_info[i - 1]); 8843 free->arch.lpage_info[i - 1] = NULL; 8844 } 8845 } 8846 8847 kvm_page_track_free_memslot(free, dont); 8848 } 8849 8850 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 8851 unsigned long npages) 8852 { 8853 int i; 8854 8855 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8856 struct kvm_lpage_info *linfo; 8857 unsigned long ugfn; 8858 int lpages; 8859 int level = i + 1; 8860 8861 lpages = gfn_to_index(slot->base_gfn + npages - 1, 8862 slot->base_gfn, level) + 1; 8863 8864 slot->arch.rmap[i] = 8865 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL); 8866 if (!slot->arch.rmap[i]) 8867 goto out_free; 8868 if (i == 0) 8869 continue; 8870 8871 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL); 8872 if (!linfo) 8873 goto out_free; 8874 8875 slot->arch.lpage_info[i - 1] = linfo; 8876 8877 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 8878 linfo[0].disallow_lpage = 1; 8879 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 8880 linfo[lpages - 1].disallow_lpage = 1; 8881 ugfn = slot->userspace_addr >> PAGE_SHIFT; 8882 /* 8883 * If the gfn and userspace address are not aligned wrt each 8884 * other, or if explicitly asked to, disable large page 8885 * support for this slot 8886 */ 8887 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 8888 !kvm_largepages_enabled()) { 8889 unsigned long j; 8890 8891 for (j = 0; j < lpages; ++j) 8892 linfo[j].disallow_lpage = 1; 8893 } 8894 } 8895 8896 if (kvm_page_track_create_memslot(slot, npages)) 8897 goto out_free; 8898 8899 return 0; 8900 8901 out_free: 8902 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8903 kvfree(slot->arch.rmap[i]); 8904 slot->arch.rmap[i] = NULL; 8905 if (i == 0) 8906 continue; 8907 8908 kvfree(slot->arch.lpage_info[i - 1]); 8909 slot->arch.lpage_info[i - 1] = NULL; 8910 } 8911 return -ENOMEM; 8912 } 8913 8914 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) 8915 { 8916 /* 8917 * memslots->generation has been incremented. 8918 * mmio generation may have reached its maximum value. 8919 */ 8920 kvm_mmu_invalidate_mmio_sptes(kvm, slots); 8921 } 8922 8923 int kvm_arch_prepare_memory_region(struct kvm *kvm, 8924 struct kvm_memory_slot *memslot, 8925 const struct kvm_userspace_memory_region *mem, 8926 enum kvm_mr_change change) 8927 { 8928 return 0; 8929 } 8930 8931 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 8932 struct kvm_memory_slot *new) 8933 { 8934 /* Still write protect RO slot */ 8935 if (new->flags & KVM_MEM_READONLY) { 8936 kvm_mmu_slot_remove_write_access(kvm, new); 8937 return; 8938 } 8939 8940 /* 8941 * Call kvm_x86_ops dirty logging hooks when they are valid. 8942 * 8943 * kvm_x86_ops->slot_disable_log_dirty is called when: 8944 * 8945 * - KVM_MR_CREATE with dirty logging is disabled 8946 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 8947 * 8948 * The reason is, in case of PML, we need to set D-bit for any slots 8949 * with dirty logging disabled in order to eliminate unnecessary GPA 8950 * logging in PML buffer (and potential PML buffer full VMEXT). This 8951 * guarantees leaving PML enabled during guest's lifetime won't have 8952 * any additonal overhead from PML when guest is running with dirty 8953 * logging disabled for memory slots. 8954 * 8955 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 8956 * to dirty logging mode. 8957 * 8958 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 8959 * 8960 * In case of write protect: 8961 * 8962 * Write protect all pages for dirty logging. 8963 * 8964 * All the sptes including the large sptes which point to this 8965 * slot are set to readonly. We can not create any new large 8966 * spte on this slot until the end of the logging. 8967 * 8968 * See the comments in fast_page_fault(). 8969 */ 8970 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 8971 if (kvm_x86_ops->slot_enable_log_dirty) 8972 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 8973 else 8974 kvm_mmu_slot_remove_write_access(kvm, new); 8975 } else { 8976 if (kvm_x86_ops->slot_disable_log_dirty) 8977 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 8978 } 8979 } 8980 8981 void kvm_arch_commit_memory_region(struct kvm *kvm, 8982 const struct kvm_userspace_memory_region *mem, 8983 const struct kvm_memory_slot *old, 8984 const struct kvm_memory_slot *new, 8985 enum kvm_mr_change change) 8986 { 8987 int nr_mmu_pages = 0; 8988 8989 if (!kvm->arch.n_requested_mmu_pages) 8990 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 8991 8992 if (nr_mmu_pages) 8993 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 8994 8995 /* 8996 * Dirty logging tracks sptes in 4k granularity, meaning that large 8997 * sptes have to be split. If live migration is successful, the guest 8998 * in the source machine will be destroyed and large sptes will be 8999 * created in the destination. However, if the guest continues to run 9000 * in the source machine (for example if live migration fails), small 9001 * sptes will remain around and cause bad performance. 9002 * 9003 * Scan sptes if dirty logging has been stopped, dropping those 9004 * which can be collapsed into a single large-page spte. Later 9005 * page faults will create the large-page sptes. 9006 */ 9007 if ((change != KVM_MR_DELETE) && 9008 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 9009 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 9010 kvm_mmu_zap_collapsible_sptes(kvm, new); 9011 9012 /* 9013 * Set up write protection and/or dirty logging for the new slot. 9014 * 9015 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 9016 * been zapped so no dirty logging staff is needed for old slot. For 9017 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 9018 * new and it's also covered when dealing with the new slot. 9019 * 9020 * FIXME: const-ify all uses of struct kvm_memory_slot. 9021 */ 9022 if (change != KVM_MR_DELETE) 9023 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 9024 } 9025 9026 void kvm_arch_flush_shadow_all(struct kvm *kvm) 9027 { 9028 kvm_mmu_invalidate_zap_all_pages(kvm); 9029 } 9030 9031 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 9032 struct kvm_memory_slot *slot) 9033 { 9034 kvm_page_track_flush_slot(kvm, slot); 9035 } 9036 9037 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 9038 { 9039 if (!list_empty_careful(&vcpu->async_pf.done)) 9040 return true; 9041 9042 if (kvm_apic_has_events(vcpu)) 9043 return true; 9044 9045 if (vcpu->arch.pv.pv_unhalted) 9046 return true; 9047 9048 if (vcpu->arch.exception.pending) 9049 return true; 9050 9051 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 9052 (vcpu->arch.nmi_pending && 9053 kvm_x86_ops->nmi_allowed(vcpu))) 9054 return true; 9055 9056 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 9057 (vcpu->arch.smi_pending && !is_smm(vcpu))) 9058 return true; 9059 9060 if (kvm_arch_interrupt_allowed(vcpu) && 9061 kvm_cpu_has_interrupt(vcpu)) 9062 return true; 9063 9064 if (kvm_hv_has_stimer_pending(vcpu)) 9065 return true; 9066 9067 return false; 9068 } 9069 9070 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 9071 { 9072 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 9073 } 9074 9075 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 9076 { 9077 return vcpu->arch.preempted_in_kernel; 9078 } 9079 9080 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 9081 { 9082 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 9083 } 9084 9085 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 9086 { 9087 return kvm_x86_ops->interrupt_allowed(vcpu); 9088 } 9089 9090 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 9091 { 9092 if (is_64_bit_mode(vcpu)) 9093 return kvm_rip_read(vcpu); 9094 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 9095 kvm_rip_read(vcpu)); 9096 } 9097 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 9098 9099 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 9100 { 9101 return kvm_get_linear_rip(vcpu) == linear_rip; 9102 } 9103 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 9104 9105 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 9106 { 9107 unsigned long rflags; 9108 9109 rflags = kvm_x86_ops->get_rflags(vcpu); 9110 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 9111 rflags &= ~X86_EFLAGS_TF; 9112 return rflags; 9113 } 9114 EXPORT_SYMBOL_GPL(kvm_get_rflags); 9115 9116 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 9117 { 9118 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 9119 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 9120 rflags |= X86_EFLAGS_TF; 9121 kvm_x86_ops->set_rflags(vcpu, rflags); 9122 } 9123 9124 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 9125 { 9126 __kvm_set_rflags(vcpu, rflags); 9127 kvm_make_request(KVM_REQ_EVENT, vcpu); 9128 } 9129 EXPORT_SYMBOL_GPL(kvm_set_rflags); 9130 9131 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 9132 { 9133 int r; 9134 9135 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 9136 work->wakeup_all) 9137 return; 9138 9139 r = kvm_mmu_reload(vcpu); 9140 if (unlikely(r)) 9141 return; 9142 9143 if (!vcpu->arch.mmu.direct_map && 9144 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 9145 return; 9146 9147 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 9148 } 9149 9150 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 9151 { 9152 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 9153 } 9154 9155 static inline u32 kvm_async_pf_next_probe(u32 key) 9156 { 9157 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 9158 } 9159 9160 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 9161 { 9162 u32 key = kvm_async_pf_hash_fn(gfn); 9163 9164 while (vcpu->arch.apf.gfns[key] != ~0) 9165 key = kvm_async_pf_next_probe(key); 9166 9167 vcpu->arch.apf.gfns[key] = gfn; 9168 } 9169 9170 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 9171 { 9172 int i; 9173 u32 key = kvm_async_pf_hash_fn(gfn); 9174 9175 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 9176 (vcpu->arch.apf.gfns[key] != gfn && 9177 vcpu->arch.apf.gfns[key] != ~0); i++) 9178 key = kvm_async_pf_next_probe(key); 9179 9180 return key; 9181 } 9182 9183 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 9184 { 9185 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 9186 } 9187 9188 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 9189 { 9190 u32 i, j, k; 9191 9192 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 9193 while (true) { 9194 vcpu->arch.apf.gfns[i] = ~0; 9195 do { 9196 j = kvm_async_pf_next_probe(j); 9197 if (vcpu->arch.apf.gfns[j] == ~0) 9198 return; 9199 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 9200 /* 9201 * k lies cyclically in ]i,j] 9202 * | i.k.j | 9203 * |....j i.k.| or |.k..j i...| 9204 */ 9205 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 9206 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 9207 i = j; 9208 } 9209 } 9210 9211 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 9212 { 9213 9214 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 9215 sizeof(val)); 9216 } 9217 9218 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val) 9219 { 9220 9221 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val, 9222 sizeof(u32)); 9223 } 9224 9225 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 9226 struct kvm_async_pf *work) 9227 { 9228 struct x86_exception fault; 9229 9230 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 9231 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 9232 9233 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 9234 (vcpu->arch.apf.send_user_only && 9235 kvm_x86_ops->get_cpl(vcpu) == 0)) 9236 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 9237 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 9238 fault.vector = PF_VECTOR; 9239 fault.error_code_valid = true; 9240 fault.error_code = 0; 9241 fault.nested_page_fault = false; 9242 fault.address = work->arch.token; 9243 fault.async_page_fault = true; 9244 kvm_inject_page_fault(vcpu, &fault); 9245 } 9246 } 9247 9248 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 9249 struct kvm_async_pf *work) 9250 { 9251 struct x86_exception fault; 9252 u32 val; 9253 9254 if (work->wakeup_all) 9255 work->arch.token = ~0; /* broadcast wakeup */ 9256 else 9257 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 9258 trace_kvm_async_pf_ready(work->arch.token, work->gva); 9259 9260 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED && 9261 !apf_get_user(vcpu, &val)) { 9262 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT && 9263 vcpu->arch.exception.pending && 9264 vcpu->arch.exception.nr == PF_VECTOR && 9265 !apf_put_user(vcpu, 0)) { 9266 vcpu->arch.exception.injected = false; 9267 vcpu->arch.exception.pending = false; 9268 vcpu->arch.exception.nr = 0; 9269 vcpu->arch.exception.has_error_code = false; 9270 vcpu->arch.exception.error_code = 0; 9271 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 9272 fault.vector = PF_VECTOR; 9273 fault.error_code_valid = true; 9274 fault.error_code = 0; 9275 fault.nested_page_fault = false; 9276 fault.address = work->arch.token; 9277 fault.async_page_fault = true; 9278 kvm_inject_page_fault(vcpu, &fault); 9279 } 9280 } 9281 vcpu->arch.apf.halted = false; 9282 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 9283 } 9284 9285 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 9286 { 9287 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 9288 return true; 9289 else 9290 return kvm_can_do_async_pf(vcpu); 9291 } 9292 9293 void kvm_arch_start_assignment(struct kvm *kvm) 9294 { 9295 atomic_inc(&kvm->arch.assigned_device_count); 9296 } 9297 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 9298 9299 void kvm_arch_end_assignment(struct kvm *kvm) 9300 { 9301 atomic_dec(&kvm->arch.assigned_device_count); 9302 } 9303 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 9304 9305 bool kvm_arch_has_assigned_device(struct kvm *kvm) 9306 { 9307 return atomic_read(&kvm->arch.assigned_device_count); 9308 } 9309 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 9310 9311 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 9312 { 9313 atomic_inc(&kvm->arch.noncoherent_dma_count); 9314 } 9315 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 9316 9317 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 9318 { 9319 atomic_dec(&kvm->arch.noncoherent_dma_count); 9320 } 9321 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 9322 9323 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 9324 { 9325 return atomic_read(&kvm->arch.noncoherent_dma_count); 9326 } 9327 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 9328 9329 bool kvm_arch_has_irq_bypass(void) 9330 { 9331 return kvm_x86_ops->update_pi_irte != NULL; 9332 } 9333 9334 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 9335 struct irq_bypass_producer *prod) 9336 { 9337 struct kvm_kernel_irqfd *irqfd = 9338 container_of(cons, struct kvm_kernel_irqfd, consumer); 9339 9340 irqfd->producer = prod; 9341 9342 return kvm_x86_ops->update_pi_irte(irqfd->kvm, 9343 prod->irq, irqfd->gsi, 1); 9344 } 9345 9346 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 9347 struct irq_bypass_producer *prod) 9348 { 9349 int ret; 9350 struct kvm_kernel_irqfd *irqfd = 9351 container_of(cons, struct kvm_kernel_irqfd, consumer); 9352 9353 WARN_ON(irqfd->producer != prod); 9354 irqfd->producer = NULL; 9355 9356 /* 9357 * When producer of consumer is unregistered, we change back to 9358 * remapped mode, so we can re-use the current implementation 9359 * when the irq is masked/disabled or the consumer side (KVM 9360 * int this case doesn't want to receive the interrupts. 9361 */ 9362 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 9363 if (ret) 9364 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 9365 " fails: %d\n", irqfd->consumer.token, ret); 9366 } 9367 9368 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 9369 uint32_t guest_irq, bool set) 9370 { 9371 if (!kvm_x86_ops->update_pi_irte) 9372 return -EINVAL; 9373 9374 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); 9375 } 9376 9377 bool kvm_vector_hashing_enabled(void) 9378 { 9379 return vector_hashing; 9380 } 9381 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled); 9382 9383 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 9384 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 9385 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 9386 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 9387 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 9388 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 9389 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 9390 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 9391 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 9392 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 9393 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 9394 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 9395 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 9396 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 9397 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 9398 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 9399 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 9400 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 9401 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 9402