1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "pmu.h" 31 #include "hyperv.h" 32 33 #include <linux/clocksource.h> 34 #include <linux/interrupt.h> 35 #include <linux/kvm.h> 36 #include <linux/fs.h> 37 #include <linux/vmalloc.h> 38 #include <linux/export.h> 39 #include <linux/moduleparam.h> 40 #include <linux/mman.h> 41 #include <linux/highmem.h> 42 #include <linux/iommu.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/cpufreq.h> 45 #include <linux/user-return-notifier.h> 46 #include <linux/srcu.h> 47 #include <linux/slab.h> 48 #include <linux/perf_event.h> 49 #include <linux/uaccess.h> 50 #include <linux/hash.h> 51 #include <linux/pci.h> 52 #include <linux/timekeeper_internal.h> 53 #include <linux/pvclock_gtod.h> 54 #include <linux/kvm_irqfd.h> 55 #include <linux/irqbypass.h> 56 #include <linux/sched/stat.h> 57 #include <linux/mem_encrypt.h> 58 59 #include <trace/events/kvm.h> 60 61 #include <asm/debugreg.h> 62 #include <asm/msr.h> 63 #include <asm/desc.h> 64 #include <asm/mce.h> 65 #include <linux/kernel_stat.h> 66 #include <asm/fpu/internal.h> /* Ugh! */ 67 #include <asm/pvclock.h> 68 #include <asm/div64.h> 69 #include <asm/irq_remapping.h> 70 #include <asm/mshyperv.h> 71 #include <asm/hypervisor.h> 72 73 #define CREATE_TRACE_POINTS 74 #include "trace.h" 75 76 #define MAX_IO_MSRS 256 77 #define KVM_MAX_MCE_BANKS 32 78 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P; 79 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported); 80 81 #define emul_to_vcpu(ctxt) \ 82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 83 84 /* EFER defaults: 85 * - enable syscall per default because its emulated by KVM 86 * - enable LME and LMA per default on 64 bit KVM 87 */ 88 #ifdef CONFIG_X86_64 89 static 90 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 91 #else 92 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 93 #endif 94 95 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 96 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 97 98 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 100 101 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 102 static void process_nmi(struct kvm_vcpu *vcpu); 103 static void enter_smm(struct kvm_vcpu *vcpu); 104 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 105 static void store_regs(struct kvm_vcpu *vcpu); 106 static int sync_regs(struct kvm_vcpu *vcpu); 107 108 struct kvm_x86_ops *kvm_x86_ops __read_mostly; 109 EXPORT_SYMBOL_GPL(kvm_x86_ops); 110 111 static bool __read_mostly ignore_msrs = 0; 112 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 113 114 static bool __read_mostly report_ignored_msrs = true; 115 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 116 117 unsigned int min_timer_period_us = 500; 118 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 119 120 static bool __read_mostly kvmclock_periodic_sync = true; 121 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 122 123 bool __read_mostly kvm_has_tsc_control; 124 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 125 u32 __read_mostly kvm_max_guest_tsc_khz; 126 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 127 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 128 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 129 u64 __read_mostly kvm_max_tsc_scaling_ratio; 130 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 131 u64 __read_mostly kvm_default_tsc_scaling_ratio; 132 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio); 133 134 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 135 static u32 __read_mostly tsc_tolerance_ppm = 250; 136 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 137 138 /* lapic timer advance (tscdeadline mode only) in nanoseconds */ 139 unsigned int __read_mostly lapic_timer_advance_ns = 0; 140 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 141 142 static bool __read_mostly vector_hashing = true; 143 module_param(vector_hashing, bool, S_IRUGO); 144 145 bool __read_mostly enable_vmware_backdoor = false; 146 module_param(enable_vmware_backdoor, bool, S_IRUGO); 147 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 148 149 static bool __read_mostly force_emulation_prefix = false; 150 module_param(force_emulation_prefix, bool, S_IRUGO); 151 152 #define KVM_NR_SHARED_MSRS 16 153 154 struct kvm_shared_msrs_global { 155 int nr; 156 u32 msrs[KVM_NR_SHARED_MSRS]; 157 }; 158 159 struct kvm_shared_msrs { 160 struct user_return_notifier urn; 161 bool registered; 162 struct kvm_shared_msr_values { 163 u64 host; 164 u64 curr; 165 } values[KVM_NR_SHARED_MSRS]; 166 }; 167 168 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 169 static struct kvm_shared_msrs __percpu *shared_msrs; 170 171 struct kvm_stats_debugfs_item debugfs_entries[] = { 172 { "pf_fixed", VCPU_STAT(pf_fixed) }, 173 { "pf_guest", VCPU_STAT(pf_guest) }, 174 { "tlb_flush", VCPU_STAT(tlb_flush) }, 175 { "invlpg", VCPU_STAT(invlpg) }, 176 { "exits", VCPU_STAT(exits) }, 177 { "io_exits", VCPU_STAT(io_exits) }, 178 { "mmio_exits", VCPU_STAT(mmio_exits) }, 179 { "signal_exits", VCPU_STAT(signal_exits) }, 180 { "irq_window", VCPU_STAT(irq_window_exits) }, 181 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 182 { "halt_exits", VCPU_STAT(halt_exits) }, 183 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 184 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 185 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) }, 186 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 187 { "hypercalls", VCPU_STAT(hypercalls) }, 188 { "request_irq", VCPU_STAT(request_irq_exits) }, 189 { "irq_exits", VCPU_STAT(irq_exits) }, 190 { "host_state_reload", VCPU_STAT(host_state_reload) }, 191 { "fpu_reload", VCPU_STAT(fpu_reload) }, 192 { "insn_emulation", VCPU_STAT(insn_emulation) }, 193 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 194 { "irq_injections", VCPU_STAT(irq_injections) }, 195 { "nmi_injections", VCPU_STAT(nmi_injections) }, 196 { "req_event", VCPU_STAT(req_event) }, 197 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 198 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 199 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 200 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 201 { "mmu_flooded", VM_STAT(mmu_flooded) }, 202 { "mmu_recycled", VM_STAT(mmu_recycled) }, 203 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 204 { "mmu_unsync", VM_STAT(mmu_unsync) }, 205 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 206 { "largepages", VM_STAT(lpages) }, 207 { "max_mmu_page_hash_collisions", 208 VM_STAT(max_mmu_page_hash_collisions) }, 209 { NULL } 210 }; 211 212 u64 __read_mostly host_xcr0; 213 214 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 215 216 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 217 { 218 int i; 219 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 220 vcpu->arch.apf.gfns[i] = ~0; 221 } 222 223 static void kvm_on_user_return(struct user_return_notifier *urn) 224 { 225 unsigned slot; 226 struct kvm_shared_msrs *locals 227 = container_of(urn, struct kvm_shared_msrs, urn); 228 struct kvm_shared_msr_values *values; 229 unsigned long flags; 230 231 /* 232 * Disabling irqs at this point since the following code could be 233 * interrupted and executed through kvm_arch_hardware_disable() 234 */ 235 local_irq_save(flags); 236 if (locals->registered) { 237 locals->registered = false; 238 user_return_notifier_unregister(urn); 239 } 240 local_irq_restore(flags); 241 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 242 values = &locals->values[slot]; 243 if (values->host != values->curr) { 244 wrmsrl(shared_msrs_global.msrs[slot], values->host); 245 values->curr = values->host; 246 } 247 } 248 } 249 250 static void shared_msr_update(unsigned slot, u32 msr) 251 { 252 u64 value; 253 unsigned int cpu = smp_processor_id(); 254 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 255 256 /* only read, and nobody should modify it at this time, 257 * so don't need lock */ 258 if (slot >= shared_msrs_global.nr) { 259 printk(KERN_ERR "kvm: invalid MSR slot!"); 260 return; 261 } 262 rdmsrl_safe(msr, &value); 263 smsr->values[slot].host = value; 264 smsr->values[slot].curr = value; 265 } 266 267 void kvm_define_shared_msr(unsigned slot, u32 msr) 268 { 269 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 270 shared_msrs_global.msrs[slot] = msr; 271 if (slot >= shared_msrs_global.nr) 272 shared_msrs_global.nr = slot + 1; 273 } 274 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 275 276 static void kvm_shared_msr_cpu_online(void) 277 { 278 unsigned i; 279 280 for (i = 0; i < shared_msrs_global.nr; ++i) 281 shared_msr_update(i, shared_msrs_global.msrs[i]); 282 } 283 284 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 285 { 286 unsigned int cpu = smp_processor_id(); 287 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 288 int err; 289 290 if (((value ^ smsr->values[slot].curr) & mask) == 0) 291 return 0; 292 smsr->values[slot].curr = value; 293 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 294 if (err) 295 return 1; 296 297 if (!smsr->registered) { 298 smsr->urn.on_user_return = kvm_on_user_return; 299 user_return_notifier_register(&smsr->urn); 300 smsr->registered = true; 301 } 302 return 0; 303 } 304 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 305 306 static void drop_user_return_notifiers(void) 307 { 308 unsigned int cpu = smp_processor_id(); 309 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 310 311 if (smsr->registered) 312 kvm_on_user_return(&smsr->urn); 313 } 314 315 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 316 { 317 return vcpu->arch.apic_base; 318 } 319 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 320 321 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 322 { 323 u64 old_state = vcpu->arch.apic_base & 324 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 325 u64 new_state = msr_info->data & 326 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 327 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff | 328 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 329 330 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE) 331 return 1; 332 if (!msr_info->host_initiated && 333 ((new_state == MSR_IA32_APICBASE_ENABLE && 334 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 335 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 336 old_state == 0))) 337 return 1; 338 339 kvm_lapic_set_base(vcpu, msr_info->data); 340 return 0; 341 } 342 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 343 344 asmlinkage __visible void kvm_spurious_fault(void) 345 { 346 /* Fault while not rebooting. We want the trace. */ 347 BUG(); 348 } 349 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 350 351 #define EXCPT_BENIGN 0 352 #define EXCPT_CONTRIBUTORY 1 353 #define EXCPT_PF 2 354 355 static int exception_class(int vector) 356 { 357 switch (vector) { 358 case PF_VECTOR: 359 return EXCPT_PF; 360 case DE_VECTOR: 361 case TS_VECTOR: 362 case NP_VECTOR: 363 case SS_VECTOR: 364 case GP_VECTOR: 365 return EXCPT_CONTRIBUTORY; 366 default: 367 break; 368 } 369 return EXCPT_BENIGN; 370 } 371 372 #define EXCPT_FAULT 0 373 #define EXCPT_TRAP 1 374 #define EXCPT_ABORT 2 375 #define EXCPT_INTERRUPT 3 376 377 static int exception_type(int vector) 378 { 379 unsigned int mask; 380 381 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 382 return EXCPT_INTERRUPT; 383 384 mask = 1 << vector; 385 386 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 387 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 388 return EXCPT_TRAP; 389 390 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 391 return EXCPT_ABORT; 392 393 /* Reserved exceptions will result in fault */ 394 return EXCPT_FAULT; 395 } 396 397 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 398 unsigned nr, bool has_error, u32 error_code, 399 bool reinject) 400 { 401 u32 prev_nr; 402 int class1, class2; 403 404 kvm_make_request(KVM_REQ_EVENT, vcpu); 405 406 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 407 queue: 408 if (has_error && !is_protmode(vcpu)) 409 has_error = false; 410 if (reinject) { 411 /* 412 * On vmentry, vcpu->arch.exception.pending is only 413 * true if an event injection was blocked by 414 * nested_run_pending. In that case, however, 415 * vcpu_enter_guest requests an immediate exit, 416 * and the guest shouldn't proceed far enough to 417 * need reinjection. 418 */ 419 WARN_ON_ONCE(vcpu->arch.exception.pending); 420 vcpu->arch.exception.injected = true; 421 } else { 422 vcpu->arch.exception.pending = true; 423 vcpu->arch.exception.injected = false; 424 } 425 vcpu->arch.exception.has_error_code = has_error; 426 vcpu->arch.exception.nr = nr; 427 vcpu->arch.exception.error_code = error_code; 428 return; 429 } 430 431 /* to check exception */ 432 prev_nr = vcpu->arch.exception.nr; 433 if (prev_nr == DF_VECTOR) { 434 /* triple fault -> shutdown */ 435 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 436 return; 437 } 438 class1 = exception_class(prev_nr); 439 class2 = exception_class(nr); 440 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 441 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 442 /* 443 * Generate double fault per SDM Table 5-5. Set 444 * exception.pending = true so that the double fault 445 * can trigger a nested vmexit. 446 */ 447 vcpu->arch.exception.pending = true; 448 vcpu->arch.exception.injected = false; 449 vcpu->arch.exception.has_error_code = true; 450 vcpu->arch.exception.nr = DF_VECTOR; 451 vcpu->arch.exception.error_code = 0; 452 } else 453 /* replace previous exception with a new one in a hope 454 that instruction re-execution will regenerate lost 455 exception */ 456 goto queue; 457 } 458 459 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 460 { 461 kvm_multiple_exception(vcpu, nr, false, 0, false); 462 } 463 EXPORT_SYMBOL_GPL(kvm_queue_exception); 464 465 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 466 { 467 kvm_multiple_exception(vcpu, nr, false, 0, true); 468 } 469 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 470 471 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 472 { 473 if (err) 474 kvm_inject_gp(vcpu, 0); 475 else 476 return kvm_skip_emulated_instruction(vcpu); 477 478 return 1; 479 } 480 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 481 482 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 483 { 484 ++vcpu->stat.pf_guest; 485 vcpu->arch.exception.nested_apf = 486 is_guest_mode(vcpu) && fault->async_page_fault; 487 if (vcpu->arch.exception.nested_apf) 488 vcpu->arch.apf.nested_apf_token = fault->address; 489 else 490 vcpu->arch.cr2 = fault->address; 491 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 492 } 493 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 494 495 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 496 { 497 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 498 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 499 else 500 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 501 502 return fault->nested_page_fault; 503 } 504 505 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 506 { 507 atomic_inc(&vcpu->arch.nmi_queued); 508 kvm_make_request(KVM_REQ_NMI, vcpu); 509 } 510 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 511 512 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 513 { 514 kvm_multiple_exception(vcpu, nr, true, error_code, false); 515 } 516 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 517 518 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 519 { 520 kvm_multiple_exception(vcpu, nr, true, error_code, true); 521 } 522 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 523 524 /* 525 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 526 * a #GP and return false. 527 */ 528 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 529 { 530 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 531 return true; 532 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 533 return false; 534 } 535 EXPORT_SYMBOL_GPL(kvm_require_cpl); 536 537 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 538 { 539 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 540 return true; 541 542 kvm_queue_exception(vcpu, UD_VECTOR); 543 return false; 544 } 545 EXPORT_SYMBOL_GPL(kvm_require_dr); 546 547 /* 548 * This function will be used to read from the physical memory of the currently 549 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 550 * can read from guest physical or from the guest's guest physical memory. 551 */ 552 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 553 gfn_t ngfn, void *data, int offset, int len, 554 u32 access) 555 { 556 struct x86_exception exception; 557 gfn_t real_gfn; 558 gpa_t ngpa; 559 560 ngpa = gfn_to_gpa(ngfn); 561 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 562 if (real_gfn == UNMAPPED_GVA) 563 return -EFAULT; 564 565 real_gfn = gpa_to_gfn(real_gfn); 566 567 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 568 } 569 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 570 571 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 572 void *data, int offset, int len, u32 access) 573 { 574 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 575 data, offset, len, access); 576 } 577 578 /* 579 * Load the pae pdptrs. Return true is they are all valid. 580 */ 581 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 582 { 583 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 584 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 585 int i; 586 int ret; 587 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 588 589 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 590 offset * sizeof(u64), sizeof(pdpte), 591 PFERR_USER_MASK|PFERR_WRITE_MASK); 592 if (ret < 0) { 593 ret = 0; 594 goto out; 595 } 596 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 597 if ((pdpte[i] & PT_PRESENT_MASK) && 598 (pdpte[i] & 599 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) { 600 ret = 0; 601 goto out; 602 } 603 } 604 ret = 1; 605 606 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 607 __set_bit(VCPU_EXREG_PDPTR, 608 (unsigned long *)&vcpu->arch.regs_avail); 609 __set_bit(VCPU_EXREG_PDPTR, 610 (unsigned long *)&vcpu->arch.regs_dirty); 611 out: 612 613 return ret; 614 } 615 EXPORT_SYMBOL_GPL(load_pdptrs); 616 617 bool pdptrs_changed(struct kvm_vcpu *vcpu) 618 { 619 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 620 bool changed = true; 621 int offset; 622 gfn_t gfn; 623 int r; 624 625 if (is_long_mode(vcpu) || !is_pae(vcpu)) 626 return false; 627 628 if (!test_bit(VCPU_EXREG_PDPTR, 629 (unsigned long *)&vcpu->arch.regs_avail)) 630 return true; 631 632 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT; 633 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1); 634 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 635 PFERR_USER_MASK | PFERR_WRITE_MASK); 636 if (r < 0) 637 goto out; 638 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 639 out: 640 641 return changed; 642 } 643 EXPORT_SYMBOL_GPL(pdptrs_changed); 644 645 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 646 { 647 unsigned long old_cr0 = kvm_read_cr0(vcpu); 648 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 649 650 cr0 |= X86_CR0_ET; 651 652 #ifdef CONFIG_X86_64 653 if (cr0 & 0xffffffff00000000UL) 654 return 1; 655 #endif 656 657 cr0 &= ~CR0_RESERVED_BITS; 658 659 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 660 return 1; 661 662 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 663 return 1; 664 665 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 666 #ifdef CONFIG_X86_64 667 if ((vcpu->arch.efer & EFER_LME)) { 668 int cs_db, cs_l; 669 670 if (!is_pae(vcpu)) 671 return 1; 672 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 673 if (cs_l) 674 return 1; 675 } else 676 #endif 677 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 678 kvm_read_cr3(vcpu))) 679 return 1; 680 } 681 682 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 683 return 1; 684 685 kvm_x86_ops->set_cr0(vcpu, cr0); 686 687 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 688 kvm_clear_async_pf_completion_queue(vcpu); 689 kvm_async_pf_hash_reset(vcpu); 690 } 691 692 if ((cr0 ^ old_cr0) & update_bits) 693 kvm_mmu_reset_context(vcpu); 694 695 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 696 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 697 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 698 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 699 700 return 0; 701 } 702 EXPORT_SYMBOL_GPL(kvm_set_cr0); 703 704 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 705 { 706 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 707 } 708 EXPORT_SYMBOL_GPL(kvm_lmsw); 709 710 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 711 { 712 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 713 !vcpu->guest_xcr0_loaded) { 714 /* kvm_set_xcr() also depends on this */ 715 if (vcpu->arch.xcr0 != host_xcr0) 716 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 717 vcpu->guest_xcr0_loaded = 1; 718 } 719 } 720 721 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 722 { 723 if (vcpu->guest_xcr0_loaded) { 724 if (vcpu->arch.xcr0 != host_xcr0) 725 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 726 vcpu->guest_xcr0_loaded = 0; 727 } 728 } 729 730 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 731 { 732 u64 xcr0 = xcr; 733 u64 old_xcr0 = vcpu->arch.xcr0; 734 u64 valid_bits; 735 736 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 737 if (index != XCR_XFEATURE_ENABLED_MASK) 738 return 1; 739 if (!(xcr0 & XFEATURE_MASK_FP)) 740 return 1; 741 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 742 return 1; 743 744 /* 745 * Do not allow the guest to set bits that we do not support 746 * saving. However, xcr0 bit 0 is always set, even if the 747 * emulated CPU does not support XSAVE (see fx_init). 748 */ 749 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 750 if (xcr0 & ~valid_bits) 751 return 1; 752 753 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 754 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 755 return 1; 756 757 if (xcr0 & XFEATURE_MASK_AVX512) { 758 if (!(xcr0 & XFEATURE_MASK_YMM)) 759 return 1; 760 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 761 return 1; 762 } 763 vcpu->arch.xcr0 = xcr0; 764 765 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 766 kvm_update_cpuid(vcpu); 767 return 0; 768 } 769 770 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 771 { 772 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 773 __kvm_set_xcr(vcpu, index, xcr)) { 774 kvm_inject_gp(vcpu, 0); 775 return 1; 776 } 777 return 0; 778 } 779 EXPORT_SYMBOL_GPL(kvm_set_xcr); 780 781 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 782 { 783 unsigned long old_cr4 = kvm_read_cr4(vcpu); 784 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 785 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE; 786 787 if (cr4 & CR4_RESERVED_BITS) 788 return 1; 789 790 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE)) 791 return 1; 792 793 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP)) 794 return 1; 795 796 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP)) 797 return 1; 798 799 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE)) 800 return 1; 801 802 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE)) 803 return 1; 804 805 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57)) 806 return 1; 807 808 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP)) 809 return 1; 810 811 if (is_long_mode(vcpu)) { 812 if (!(cr4 & X86_CR4_PAE)) 813 return 1; 814 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 815 && ((cr4 ^ old_cr4) & pdptr_bits) 816 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 817 kvm_read_cr3(vcpu))) 818 return 1; 819 820 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 821 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) 822 return 1; 823 824 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 825 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 826 return 1; 827 } 828 829 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 830 return 1; 831 832 if (((cr4 ^ old_cr4) & pdptr_bits) || 833 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 834 kvm_mmu_reset_context(vcpu); 835 836 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 837 kvm_update_cpuid(vcpu); 838 839 return 0; 840 } 841 EXPORT_SYMBOL_GPL(kvm_set_cr4); 842 843 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 844 { 845 #ifdef CONFIG_X86_64 846 cr3 &= ~CR3_PCID_INVD; 847 #endif 848 849 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 850 kvm_mmu_sync_roots(vcpu); 851 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 852 return 0; 853 } 854 855 if (is_long_mode(vcpu) && 856 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62))) 857 return 1; 858 else if (is_pae(vcpu) && is_paging(vcpu) && 859 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 860 return 1; 861 862 vcpu->arch.cr3 = cr3; 863 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 864 kvm_mmu_new_cr3(vcpu); 865 return 0; 866 } 867 EXPORT_SYMBOL_GPL(kvm_set_cr3); 868 869 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 870 { 871 if (cr8 & CR8_RESERVED_BITS) 872 return 1; 873 if (lapic_in_kernel(vcpu)) 874 kvm_lapic_set_tpr(vcpu, cr8); 875 else 876 vcpu->arch.cr8 = cr8; 877 return 0; 878 } 879 EXPORT_SYMBOL_GPL(kvm_set_cr8); 880 881 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 882 { 883 if (lapic_in_kernel(vcpu)) 884 return kvm_lapic_get_cr8(vcpu); 885 else 886 return vcpu->arch.cr8; 887 } 888 EXPORT_SYMBOL_GPL(kvm_get_cr8); 889 890 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 891 { 892 int i; 893 894 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 895 for (i = 0; i < KVM_NR_DB_REGS; i++) 896 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 897 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 898 } 899 } 900 901 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 902 { 903 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 904 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 905 } 906 907 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 908 { 909 unsigned long dr7; 910 911 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 912 dr7 = vcpu->arch.guest_debug_dr7; 913 else 914 dr7 = vcpu->arch.dr7; 915 kvm_x86_ops->set_dr7(vcpu, dr7); 916 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 917 if (dr7 & DR7_BP_EN_MASK) 918 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 919 } 920 921 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 922 { 923 u64 fixed = DR6_FIXED_1; 924 925 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 926 fixed |= DR6_RTM; 927 return fixed; 928 } 929 930 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 931 { 932 switch (dr) { 933 case 0 ... 3: 934 vcpu->arch.db[dr] = val; 935 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 936 vcpu->arch.eff_db[dr] = val; 937 break; 938 case 4: 939 /* fall through */ 940 case 6: 941 if (val & 0xffffffff00000000ULL) 942 return -1; /* #GP */ 943 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 944 kvm_update_dr6(vcpu); 945 break; 946 case 5: 947 /* fall through */ 948 default: /* 7 */ 949 if (val & 0xffffffff00000000ULL) 950 return -1; /* #GP */ 951 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 952 kvm_update_dr7(vcpu); 953 break; 954 } 955 956 return 0; 957 } 958 959 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 960 { 961 if (__kvm_set_dr(vcpu, dr, val)) { 962 kvm_inject_gp(vcpu, 0); 963 return 1; 964 } 965 return 0; 966 } 967 EXPORT_SYMBOL_GPL(kvm_set_dr); 968 969 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 970 { 971 switch (dr) { 972 case 0 ... 3: 973 *val = vcpu->arch.db[dr]; 974 break; 975 case 4: 976 /* fall through */ 977 case 6: 978 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 979 *val = vcpu->arch.dr6; 980 else 981 *val = kvm_x86_ops->get_dr6(vcpu); 982 break; 983 case 5: 984 /* fall through */ 985 default: /* 7 */ 986 *val = vcpu->arch.dr7; 987 break; 988 } 989 return 0; 990 } 991 EXPORT_SYMBOL_GPL(kvm_get_dr); 992 993 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 994 { 995 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 996 u64 data; 997 int err; 998 999 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 1000 if (err) 1001 return err; 1002 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 1003 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 1004 return err; 1005 } 1006 EXPORT_SYMBOL_GPL(kvm_rdpmc); 1007 1008 /* 1009 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 1010 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 1011 * 1012 * This list is modified at module load time to reflect the 1013 * capabilities of the host cpu. This capabilities test skips MSRs that are 1014 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs 1015 * may depend on host virtualization features rather than host cpu features. 1016 */ 1017 1018 static u32 msrs_to_save[] = { 1019 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1020 MSR_STAR, 1021 #ifdef CONFIG_X86_64 1022 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1023 #endif 1024 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1025 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1026 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES 1027 }; 1028 1029 static unsigned num_msrs_to_save; 1030 1031 static u32 emulated_msrs[] = { 1032 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1033 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1034 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1035 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1036 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1037 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1038 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1039 HV_X64_MSR_RESET, 1040 HV_X64_MSR_VP_INDEX, 1041 HV_X64_MSR_VP_RUNTIME, 1042 HV_X64_MSR_SCONTROL, 1043 HV_X64_MSR_STIMER0_CONFIG, 1044 HV_X64_MSR_VP_ASSIST_PAGE, 1045 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1046 HV_X64_MSR_TSC_EMULATION_STATUS, 1047 1048 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1049 MSR_KVM_PV_EOI_EN, 1050 1051 MSR_IA32_TSC_ADJUST, 1052 MSR_IA32_TSCDEADLINE, 1053 MSR_IA32_MISC_ENABLE, 1054 MSR_IA32_MCG_STATUS, 1055 MSR_IA32_MCG_CTL, 1056 MSR_IA32_MCG_EXT_CTL, 1057 MSR_IA32_SMBASE, 1058 MSR_SMI_COUNT, 1059 MSR_PLATFORM_INFO, 1060 MSR_MISC_FEATURES_ENABLES, 1061 }; 1062 1063 static unsigned num_emulated_msrs; 1064 1065 /* 1066 * List of msr numbers which are used to expose MSR-based features that 1067 * can be used by a hypervisor to validate requested CPU features. 1068 */ 1069 static u32 msr_based_features[] = { 1070 MSR_IA32_VMX_BASIC, 1071 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1072 MSR_IA32_VMX_PINBASED_CTLS, 1073 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1074 MSR_IA32_VMX_PROCBASED_CTLS, 1075 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1076 MSR_IA32_VMX_EXIT_CTLS, 1077 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1078 MSR_IA32_VMX_ENTRY_CTLS, 1079 MSR_IA32_VMX_MISC, 1080 MSR_IA32_VMX_CR0_FIXED0, 1081 MSR_IA32_VMX_CR0_FIXED1, 1082 MSR_IA32_VMX_CR4_FIXED0, 1083 MSR_IA32_VMX_CR4_FIXED1, 1084 MSR_IA32_VMX_VMCS_ENUM, 1085 MSR_IA32_VMX_PROCBASED_CTLS2, 1086 MSR_IA32_VMX_EPT_VPID_CAP, 1087 MSR_IA32_VMX_VMFUNC, 1088 1089 MSR_F10H_DECFG, 1090 MSR_IA32_UCODE_REV, 1091 }; 1092 1093 static unsigned int num_msr_based_features; 1094 1095 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1096 { 1097 switch (msr->index) { 1098 case MSR_IA32_UCODE_REV: 1099 rdmsrl(msr->index, msr->data); 1100 break; 1101 default: 1102 if (kvm_x86_ops->get_msr_feature(msr)) 1103 return 1; 1104 } 1105 return 0; 1106 } 1107 1108 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1109 { 1110 struct kvm_msr_entry msr; 1111 int r; 1112 1113 msr.index = index; 1114 r = kvm_get_msr_feature(&msr); 1115 if (r) 1116 return r; 1117 1118 *data = msr.data; 1119 1120 return 0; 1121 } 1122 1123 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1124 { 1125 if (efer & efer_reserved_bits) 1126 return false; 1127 1128 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1129 return false; 1130 1131 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1132 return false; 1133 1134 return true; 1135 } 1136 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1137 1138 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 1139 { 1140 u64 old_efer = vcpu->arch.efer; 1141 1142 if (!kvm_valid_efer(vcpu, efer)) 1143 return 1; 1144 1145 if (is_paging(vcpu) 1146 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1147 return 1; 1148 1149 efer &= ~EFER_LMA; 1150 efer |= vcpu->arch.efer & EFER_LMA; 1151 1152 kvm_x86_ops->set_efer(vcpu, efer); 1153 1154 /* Update reserved bits */ 1155 if ((efer ^ old_efer) & EFER_NX) 1156 kvm_mmu_reset_context(vcpu); 1157 1158 return 0; 1159 } 1160 1161 void kvm_enable_efer_bits(u64 mask) 1162 { 1163 efer_reserved_bits &= ~mask; 1164 } 1165 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1166 1167 /* 1168 * Writes msr value into into the appropriate "register". 1169 * Returns 0 on success, non-0 otherwise. 1170 * Assumes vcpu_load() was already called. 1171 */ 1172 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1173 { 1174 switch (msr->index) { 1175 case MSR_FS_BASE: 1176 case MSR_GS_BASE: 1177 case MSR_KERNEL_GS_BASE: 1178 case MSR_CSTAR: 1179 case MSR_LSTAR: 1180 if (is_noncanonical_address(msr->data, vcpu)) 1181 return 1; 1182 break; 1183 case MSR_IA32_SYSENTER_EIP: 1184 case MSR_IA32_SYSENTER_ESP: 1185 /* 1186 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1187 * non-canonical address is written on Intel but not on 1188 * AMD (which ignores the top 32-bits, because it does 1189 * not implement 64-bit SYSENTER). 1190 * 1191 * 64-bit code should hence be able to write a non-canonical 1192 * value on AMD. Making the address canonical ensures that 1193 * vmentry does not fail on Intel after writing a non-canonical 1194 * value, and that something deterministic happens if the guest 1195 * invokes 64-bit SYSENTER. 1196 */ 1197 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu)); 1198 } 1199 return kvm_x86_ops->set_msr(vcpu, msr); 1200 } 1201 EXPORT_SYMBOL_GPL(kvm_set_msr); 1202 1203 /* 1204 * Adapt set_msr() to msr_io()'s calling convention 1205 */ 1206 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1207 { 1208 struct msr_data msr; 1209 int r; 1210 1211 msr.index = index; 1212 msr.host_initiated = true; 1213 r = kvm_get_msr(vcpu, &msr); 1214 if (r) 1215 return r; 1216 1217 *data = msr.data; 1218 return 0; 1219 } 1220 1221 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1222 { 1223 struct msr_data msr; 1224 1225 msr.data = *data; 1226 msr.index = index; 1227 msr.host_initiated = true; 1228 return kvm_set_msr(vcpu, &msr); 1229 } 1230 1231 #ifdef CONFIG_X86_64 1232 struct pvclock_gtod_data { 1233 seqcount_t seq; 1234 1235 struct { /* extract of a clocksource struct */ 1236 int vclock_mode; 1237 u64 cycle_last; 1238 u64 mask; 1239 u32 mult; 1240 u32 shift; 1241 } clock; 1242 1243 u64 boot_ns; 1244 u64 nsec_base; 1245 u64 wall_time_sec; 1246 }; 1247 1248 static struct pvclock_gtod_data pvclock_gtod_data; 1249 1250 static void update_pvclock_gtod(struct timekeeper *tk) 1251 { 1252 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1253 u64 boot_ns; 1254 1255 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1256 1257 write_seqcount_begin(&vdata->seq); 1258 1259 /* copy pvclock gtod data */ 1260 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1261 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1262 vdata->clock.mask = tk->tkr_mono.mask; 1263 vdata->clock.mult = tk->tkr_mono.mult; 1264 vdata->clock.shift = tk->tkr_mono.shift; 1265 1266 vdata->boot_ns = boot_ns; 1267 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1268 1269 vdata->wall_time_sec = tk->xtime_sec; 1270 1271 write_seqcount_end(&vdata->seq); 1272 } 1273 #endif 1274 1275 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1276 { 1277 /* 1278 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1279 * vcpu_enter_guest. This function is only called from 1280 * the physical CPU that is running vcpu. 1281 */ 1282 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1283 } 1284 1285 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1286 { 1287 int version; 1288 int r; 1289 struct pvclock_wall_clock wc; 1290 struct timespec64 boot; 1291 1292 if (!wall_clock) 1293 return; 1294 1295 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1296 if (r) 1297 return; 1298 1299 if (version & 1) 1300 ++version; /* first time write, random junk */ 1301 1302 ++version; 1303 1304 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1305 return; 1306 1307 /* 1308 * The guest calculates current wall clock time by adding 1309 * system time (updated by kvm_guest_time_update below) to the 1310 * wall clock specified here. guest system time equals host 1311 * system time for us, thus we must fill in host boot time here. 1312 */ 1313 getboottime64(&boot); 1314 1315 if (kvm->arch.kvmclock_offset) { 1316 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset); 1317 boot = timespec64_sub(boot, ts); 1318 } 1319 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */ 1320 wc.nsec = boot.tv_nsec; 1321 wc.version = version; 1322 1323 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1324 1325 version++; 1326 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1327 } 1328 1329 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1330 { 1331 do_shl32_div32(dividend, divisor); 1332 return dividend; 1333 } 1334 1335 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 1336 s8 *pshift, u32 *pmultiplier) 1337 { 1338 uint64_t scaled64; 1339 int32_t shift = 0; 1340 uint64_t tps64; 1341 uint32_t tps32; 1342 1343 tps64 = base_hz; 1344 scaled64 = scaled_hz; 1345 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1346 tps64 >>= 1; 1347 shift--; 1348 } 1349 1350 tps32 = (uint32_t)tps64; 1351 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1352 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1353 scaled64 >>= 1; 1354 else 1355 tps32 <<= 1; 1356 shift++; 1357 } 1358 1359 *pshift = shift; 1360 *pmultiplier = div_frac(scaled64, tps32); 1361 1362 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n", 1363 __func__, base_hz, scaled_hz, shift, *pmultiplier); 1364 } 1365 1366 #ifdef CONFIG_X86_64 1367 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1368 #endif 1369 1370 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1371 static unsigned long max_tsc_khz; 1372 1373 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1374 { 1375 u64 v = (u64)khz * (1000000 + ppm); 1376 do_div(v, 1000000); 1377 return v; 1378 } 1379 1380 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 1381 { 1382 u64 ratio; 1383 1384 /* Guest TSC same frequency as host TSC? */ 1385 if (!scale) { 1386 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1387 return 0; 1388 } 1389 1390 /* TSC scaling supported? */ 1391 if (!kvm_has_tsc_control) { 1392 if (user_tsc_khz > tsc_khz) { 1393 vcpu->arch.tsc_catchup = 1; 1394 vcpu->arch.tsc_always_catchup = 1; 1395 return 0; 1396 } else { 1397 WARN(1, "user requested TSC rate below hardware speed\n"); 1398 return -1; 1399 } 1400 } 1401 1402 /* TSC scaling required - calculate ratio */ 1403 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 1404 user_tsc_khz, tsc_khz); 1405 1406 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 1407 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 1408 user_tsc_khz); 1409 return -1; 1410 } 1411 1412 vcpu->arch.tsc_scaling_ratio = ratio; 1413 return 0; 1414 } 1415 1416 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 1417 { 1418 u32 thresh_lo, thresh_hi; 1419 int use_scaling = 0; 1420 1421 /* tsc_khz can be zero if TSC calibration fails */ 1422 if (user_tsc_khz == 0) { 1423 /* set tsc_scaling_ratio to a safe value */ 1424 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1425 return -1; 1426 } 1427 1428 /* Compute a scale to convert nanoseconds in TSC cycles */ 1429 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 1430 &vcpu->arch.virtual_tsc_shift, 1431 &vcpu->arch.virtual_tsc_mult); 1432 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 1433 1434 /* 1435 * Compute the variation in TSC rate which is acceptable 1436 * within the range of tolerance and decide if the 1437 * rate being applied is within that bounds of the hardware 1438 * rate. If so, no scaling or compensation need be done. 1439 */ 1440 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1441 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1442 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 1443 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); 1444 use_scaling = 1; 1445 } 1446 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 1447 } 1448 1449 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1450 { 1451 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1452 vcpu->arch.virtual_tsc_mult, 1453 vcpu->arch.virtual_tsc_shift); 1454 tsc += vcpu->arch.this_tsc_write; 1455 return tsc; 1456 } 1457 1458 static inline int gtod_is_based_on_tsc(int mode) 1459 { 1460 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK; 1461 } 1462 1463 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1464 { 1465 #ifdef CONFIG_X86_64 1466 bool vcpus_matched; 1467 struct kvm_arch *ka = &vcpu->kvm->arch; 1468 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1469 1470 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1471 atomic_read(&vcpu->kvm->online_vcpus)); 1472 1473 /* 1474 * Once the masterclock is enabled, always perform request in 1475 * order to update it. 1476 * 1477 * In order to enable masterclock, the host clocksource must be TSC 1478 * and the vcpus need to have matched TSCs. When that happens, 1479 * perform request to enable masterclock. 1480 */ 1481 if (ka->use_master_clock || 1482 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 1483 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1484 1485 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1486 atomic_read(&vcpu->kvm->online_vcpus), 1487 ka->use_master_clock, gtod->clock.vclock_mode); 1488 #endif 1489 } 1490 1491 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1492 { 1493 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); 1494 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1495 } 1496 1497 /* 1498 * Multiply tsc by a fixed point number represented by ratio. 1499 * 1500 * The most significant 64-N bits (mult) of ratio represent the 1501 * integral part of the fixed point number; the remaining N bits 1502 * (frac) represent the fractional part, ie. ratio represents a fixed 1503 * point number (mult + frac * 2^(-N)). 1504 * 1505 * N equals to kvm_tsc_scaling_ratio_frac_bits. 1506 */ 1507 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 1508 { 1509 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 1510 } 1511 1512 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 1513 { 1514 u64 _tsc = tsc; 1515 u64 ratio = vcpu->arch.tsc_scaling_ratio; 1516 1517 if (ratio != kvm_default_tsc_scaling_ratio) 1518 _tsc = __scale_tsc(ratio, tsc); 1519 1520 return _tsc; 1521 } 1522 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 1523 1524 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 1525 { 1526 u64 tsc; 1527 1528 tsc = kvm_scale_tsc(vcpu, rdtsc()); 1529 1530 return target_tsc - tsc; 1531 } 1532 1533 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 1534 { 1535 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu); 1536 1537 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc); 1538 } 1539 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 1540 1541 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1542 { 1543 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1544 vcpu->arch.tsc_offset = offset; 1545 } 1546 1547 static inline bool kvm_check_tsc_unstable(void) 1548 { 1549 #ifdef CONFIG_X86_64 1550 /* 1551 * TSC is marked unstable when we're running on Hyper-V, 1552 * 'TSC page' clocksource is good. 1553 */ 1554 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK) 1555 return false; 1556 #endif 1557 return check_tsc_unstable(); 1558 } 1559 1560 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1561 { 1562 struct kvm *kvm = vcpu->kvm; 1563 u64 offset, ns, elapsed; 1564 unsigned long flags; 1565 bool matched; 1566 bool already_matched; 1567 u64 data = msr->data; 1568 bool synchronizing = false; 1569 1570 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1571 offset = kvm_compute_tsc_offset(vcpu, data); 1572 ns = ktime_get_boot_ns(); 1573 elapsed = ns - kvm->arch.last_tsc_nsec; 1574 1575 if (vcpu->arch.virtual_tsc_khz) { 1576 if (data == 0 && msr->host_initiated) { 1577 /* 1578 * detection of vcpu initialization -- need to sync 1579 * with other vCPUs. This particularly helps to keep 1580 * kvm_clock stable after CPU hotplug 1581 */ 1582 synchronizing = true; 1583 } else { 1584 u64 tsc_exp = kvm->arch.last_tsc_write + 1585 nsec_to_cycles(vcpu, elapsed); 1586 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 1587 /* 1588 * Special case: TSC write with a small delta (1 second) 1589 * of virtual cycle time against real time is 1590 * interpreted as an attempt to synchronize the CPU. 1591 */ 1592 synchronizing = data < tsc_exp + tsc_hz && 1593 data + tsc_hz > tsc_exp; 1594 } 1595 } 1596 1597 /* 1598 * For a reliable TSC, we can match TSC offsets, and for an unstable 1599 * TSC, we add elapsed time in this computation. We could let the 1600 * compensation code attempt to catch up if we fall behind, but 1601 * it's better to try to match offsets from the beginning. 1602 */ 1603 if (synchronizing && 1604 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1605 if (!kvm_check_tsc_unstable()) { 1606 offset = kvm->arch.cur_tsc_offset; 1607 pr_debug("kvm: matched tsc offset for %llu\n", data); 1608 } else { 1609 u64 delta = nsec_to_cycles(vcpu, elapsed); 1610 data += delta; 1611 offset = kvm_compute_tsc_offset(vcpu, data); 1612 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1613 } 1614 matched = true; 1615 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1616 } else { 1617 /* 1618 * We split periods of matched TSC writes into generations. 1619 * For each generation, we track the original measured 1620 * nanosecond time, offset, and write, so if TSCs are in 1621 * sync, we can match exact offset, and if not, we can match 1622 * exact software computation in compute_guest_tsc() 1623 * 1624 * These values are tracked in kvm->arch.cur_xxx variables. 1625 */ 1626 kvm->arch.cur_tsc_generation++; 1627 kvm->arch.cur_tsc_nsec = ns; 1628 kvm->arch.cur_tsc_write = data; 1629 kvm->arch.cur_tsc_offset = offset; 1630 matched = false; 1631 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1632 kvm->arch.cur_tsc_generation, data); 1633 } 1634 1635 /* 1636 * We also track th most recent recorded KHZ, write and time to 1637 * allow the matching interval to be extended at each write. 1638 */ 1639 kvm->arch.last_tsc_nsec = ns; 1640 kvm->arch.last_tsc_write = data; 1641 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1642 1643 vcpu->arch.last_guest_tsc = data; 1644 1645 /* Keep track of which generation this VCPU has synchronized to */ 1646 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1647 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1648 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1649 1650 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) 1651 update_ia32_tsc_adjust_msr(vcpu, offset); 1652 1653 kvm_vcpu_write_tsc_offset(vcpu, offset); 1654 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1655 1656 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1657 if (!matched) { 1658 kvm->arch.nr_vcpus_matched_tsc = 0; 1659 } else if (!already_matched) { 1660 kvm->arch.nr_vcpus_matched_tsc++; 1661 } 1662 1663 kvm_track_tsc_matching(vcpu); 1664 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1665 } 1666 1667 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1668 1669 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 1670 s64 adjustment) 1671 { 1672 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment); 1673 } 1674 1675 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 1676 { 1677 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 1678 WARN_ON(adjustment < 0); 1679 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 1680 adjust_tsc_offset_guest(vcpu, adjustment); 1681 } 1682 1683 #ifdef CONFIG_X86_64 1684 1685 static u64 read_tsc(void) 1686 { 1687 u64 ret = (u64)rdtsc_ordered(); 1688 u64 last = pvclock_gtod_data.clock.cycle_last; 1689 1690 if (likely(ret >= last)) 1691 return ret; 1692 1693 /* 1694 * GCC likes to generate cmov here, but this branch is extremely 1695 * predictable (it's just a function of time and the likely is 1696 * very likely) and there's a data dependence, so force GCC 1697 * to generate a branch instead. I don't barrier() because 1698 * we don't actually need a barrier, and if this function 1699 * ever gets inlined it will generate worse code. 1700 */ 1701 asm volatile (""); 1702 return last; 1703 } 1704 1705 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode) 1706 { 1707 long v; 1708 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1709 u64 tsc_pg_val; 1710 1711 switch (gtod->clock.vclock_mode) { 1712 case VCLOCK_HVCLOCK: 1713 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), 1714 tsc_timestamp); 1715 if (tsc_pg_val != U64_MAX) { 1716 /* TSC page valid */ 1717 *mode = VCLOCK_HVCLOCK; 1718 v = (tsc_pg_val - gtod->clock.cycle_last) & 1719 gtod->clock.mask; 1720 } else { 1721 /* TSC page invalid */ 1722 *mode = VCLOCK_NONE; 1723 } 1724 break; 1725 case VCLOCK_TSC: 1726 *mode = VCLOCK_TSC; 1727 *tsc_timestamp = read_tsc(); 1728 v = (*tsc_timestamp - gtod->clock.cycle_last) & 1729 gtod->clock.mask; 1730 break; 1731 default: 1732 *mode = VCLOCK_NONE; 1733 } 1734 1735 if (*mode == VCLOCK_NONE) 1736 *tsc_timestamp = v = 0; 1737 1738 return v * gtod->clock.mult; 1739 } 1740 1741 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp) 1742 { 1743 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1744 unsigned long seq; 1745 int mode; 1746 u64 ns; 1747 1748 do { 1749 seq = read_seqcount_begin(>od->seq); 1750 ns = gtod->nsec_base; 1751 ns += vgettsc(tsc_timestamp, &mode); 1752 ns >>= gtod->clock.shift; 1753 ns += gtod->boot_ns; 1754 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1755 *t = ns; 1756 1757 return mode; 1758 } 1759 1760 static int do_realtime(struct timespec *ts, u64 *tsc_timestamp) 1761 { 1762 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1763 unsigned long seq; 1764 int mode; 1765 u64 ns; 1766 1767 do { 1768 seq = read_seqcount_begin(>od->seq); 1769 ts->tv_sec = gtod->wall_time_sec; 1770 ns = gtod->nsec_base; 1771 ns += vgettsc(tsc_timestamp, &mode); 1772 ns >>= gtod->clock.shift; 1773 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1774 1775 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 1776 ts->tv_nsec = ns; 1777 1778 return mode; 1779 } 1780 1781 /* returns true if host is using TSC based clocksource */ 1782 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 1783 { 1784 /* checked again under seqlock below */ 1785 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 1786 return false; 1787 1788 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns, 1789 tsc_timestamp)); 1790 } 1791 1792 /* returns true if host is using TSC based clocksource */ 1793 static bool kvm_get_walltime_and_clockread(struct timespec *ts, 1794 u64 *tsc_timestamp) 1795 { 1796 /* checked again under seqlock below */ 1797 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 1798 return false; 1799 1800 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 1801 } 1802 #endif 1803 1804 /* 1805 * 1806 * Assuming a stable TSC across physical CPUS, and a stable TSC 1807 * across virtual CPUs, the following condition is possible. 1808 * Each numbered line represents an event visible to both 1809 * CPUs at the next numbered event. 1810 * 1811 * "timespecX" represents host monotonic time. "tscX" represents 1812 * RDTSC value. 1813 * 1814 * VCPU0 on CPU0 | VCPU1 on CPU1 1815 * 1816 * 1. read timespec0,tsc0 1817 * 2. | timespec1 = timespec0 + N 1818 * | tsc1 = tsc0 + M 1819 * 3. transition to guest | transition to guest 1820 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1821 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1822 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1823 * 1824 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1825 * 1826 * - ret0 < ret1 1827 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1828 * ... 1829 * - 0 < N - M => M < N 1830 * 1831 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1832 * always the case (the difference between two distinct xtime instances 1833 * might be smaller then the difference between corresponding TSC reads, 1834 * when updating guest vcpus pvclock areas). 1835 * 1836 * To avoid that problem, do not allow visibility of distinct 1837 * system_timestamp/tsc_timestamp values simultaneously: use a master 1838 * copy of host monotonic time values. Update that master copy 1839 * in lockstep. 1840 * 1841 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1842 * 1843 */ 1844 1845 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1846 { 1847 #ifdef CONFIG_X86_64 1848 struct kvm_arch *ka = &kvm->arch; 1849 int vclock_mode; 1850 bool host_tsc_clocksource, vcpus_matched; 1851 1852 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1853 atomic_read(&kvm->online_vcpus)); 1854 1855 /* 1856 * If the host uses TSC clock, then passthrough TSC as stable 1857 * to the guest. 1858 */ 1859 host_tsc_clocksource = kvm_get_time_and_clockread( 1860 &ka->master_kernel_ns, 1861 &ka->master_cycle_now); 1862 1863 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 1864 && !ka->backwards_tsc_observed 1865 && !ka->boot_vcpu_runs_old_kvmclock; 1866 1867 if (ka->use_master_clock) 1868 atomic_set(&kvm_guest_has_master_clock, 1); 1869 1870 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1871 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1872 vcpus_matched); 1873 #endif 1874 } 1875 1876 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 1877 { 1878 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 1879 } 1880 1881 static void kvm_gen_update_masterclock(struct kvm *kvm) 1882 { 1883 #ifdef CONFIG_X86_64 1884 int i; 1885 struct kvm_vcpu *vcpu; 1886 struct kvm_arch *ka = &kvm->arch; 1887 1888 spin_lock(&ka->pvclock_gtod_sync_lock); 1889 kvm_make_mclock_inprogress_request(kvm); 1890 /* no guest entries from this point */ 1891 pvclock_update_vm_gtod_copy(kvm); 1892 1893 kvm_for_each_vcpu(i, vcpu, kvm) 1894 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1895 1896 /* guest entries allowed */ 1897 kvm_for_each_vcpu(i, vcpu, kvm) 1898 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 1899 1900 spin_unlock(&ka->pvclock_gtod_sync_lock); 1901 #endif 1902 } 1903 1904 u64 get_kvmclock_ns(struct kvm *kvm) 1905 { 1906 struct kvm_arch *ka = &kvm->arch; 1907 struct pvclock_vcpu_time_info hv_clock; 1908 u64 ret; 1909 1910 spin_lock(&ka->pvclock_gtod_sync_lock); 1911 if (!ka->use_master_clock) { 1912 spin_unlock(&ka->pvclock_gtod_sync_lock); 1913 return ktime_get_boot_ns() + ka->kvmclock_offset; 1914 } 1915 1916 hv_clock.tsc_timestamp = ka->master_cycle_now; 1917 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 1918 spin_unlock(&ka->pvclock_gtod_sync_lock); 1919 1920 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 1921 get_cpu(); 1922 1923 if (__this_cpu_read(cpu_tsc_khz)) { 1924 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, 1925 &hv_clock.tsc_shift, 1926 &hv_clock.tsc_to_system_mul); 1927 ret = __pvclock_read_cycles(&hv_clock, rdtsc()); 1928 } else 1929 ret = ktime_get_boot_ns() + ka->kvmclock_offset; 1930 1931 put_cpu(); 1932 1933 return ret; 1934 } 1935 1936 static void kvm_setup_pvclock_page(struct kvm_vcpu *v) 1937 { 1938 struct kvm_vcpu_arch *vcpu = &v->arch; 1939 struct pvclock_vcpu_time_info guest_hv_clock; 1940 1941 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1942 &guest_hv_clock, sizeof(guest_hv_clock)))) 1943 return; 1944 1945 /* This VCPU is paused, but it's legal for a guest to read another 1946 * VCPU's kvmclock, so we really have to follow the specification where 1947 * it says that version is odd if data is being modified, and even after 1948 * it is consistent. 1949 * 1950 * Version field updates must be kept separate. This is because 1951 * kvm_write_guest_cached might use a "rep movs" instruction, and 1952 * writes within a string instruction are weakly ordered. So there 1953 * are three writes overall. 1954 * 1955 * As a small optimization, only write the version field in the first 1956 * and third write. The vcpu->pv_time cache is still valid, because the 1957 * version field is the first in the struct. 1958 */ 1959 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 1960 1961 if (guest_hv_clock.version & 1) 1962 ++guest_hv_clock.version; /* first time write, random junk */ 1963 1964 vcpu->hv_clock.version = guest_hv_clock.version + 1; 1965 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1966 &vcpu->hv_clock, 1967 sizeof(vcpu->hv_clock.version)); 1968 1969 smp_wmb(); 1970 1971 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1972 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1973 1974 if (vcpu->pvclock_set_guest_stopped_request) { 1975 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 1976 vcpu->pvclock_set_guest_stopped_request = false; 1977 } 1978 1979 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 1980 1981 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1982 &vcpu->hv_clock, 1983 sizeof(vcpu->hv_clock)); 1984 1985 smp_wmb(); 1986 1987 vcpu->hv_clock.version++; 1988 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1989 &vcpu->hv_clock, 1990 sizeof(vcpu->hv_clock.version)); 1991 } 1992 1993 static int kvm_guest_time_update(struct kvm_vcpu *v) 1994 { 1995 unsigned long flags, tgt_tsc_khz; 1996 struct kvm_vcpu_arch *vcpu = &v->arch; 1997 struct kvm_arch *ka = &v->kvm->arch; 1998 s64 kernel_ns; 1999 u64 tsc_timestamp, host_tsc; 2000 u8 pvclock_flags; 2001 bool use_master_clock; 2002 2003 kernel_ns = 0; 2004 host_tsc = 0; 2005 2006 /* 2007 * If the host uses TSC clock, then passthrough TSC as stable 2008 * to the guest. 2009 */ 2010 spin_lock(&ka->pvclock_gtod_sync_lock); 2011 use_master_clock = ka->use_master_clock; 2012 if (use_master_clock) { 2013 host_tsc = ka->master_cycle_now; 2014 kernel_ns = ka->master_kernel_ns; 2015 } 2016 spin_unlock(&ka->pvclock_gtod_sync_lock); 2017 2018 /* Keep irq disabled to prevent changes to the clock */ 2019 local_irq_save(flags); 2020 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); 2021 if (unlikely(tgt_tsc_khz == 0)) { 2022 local_irq_restore(flags); 2023 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2024 return 1; 2025 } 2026 if (!use_master_clock) { 2027 host_tsc = rdtsc(); 2028 kernel_ns = ktime_get_boot_ns(); 2029 } 2030 2031 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 2032 2033 /* 2034 * We may have to catch up the TSC to match elapsed wall clock 2035 * time for two reasons, even if kvmclock is used. 2036 * 1) CPU could have been running below the maximum TSC rate 2037 * 2) Broken TSC compensation resets the base at each VCPU 2038 * entry to avoid unknown leaps of TSC even when running 2039 * again on the same CPU. This may cause apparent elapsed 2040 * time to disappear, and the guest to stand still or run 2041 * very slowly. 2042 */ 2043 if (vcpu->tsc_catchup) { 2044 u64 tsc = compute_guest_tsc(v, kernel_ns); 2045 if (tsc > tsc_timestamp) { 2046 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 2047 tsc_timestamp = tsc; 2048 } 2049 } 2050 2051 local_irq_restore(flags); 2052 2053 /* With all the info we got, fill in the values */ 2054 2055 if (kvm_has_tsc_control) 2056 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz); 2057 2058 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 2059 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 2060 &vcpu->hv_clock.tsc_shift, 2061 &vcpu->hv_clock.tsc_to_system_mul); 2062 vcpu->hw_tsc_khz = tgt_tsc_khz; 2063 } 2064 2065 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 2066 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 2067 vcpu->last_guest_tsc = tsc_timestamp; 2068 2069 /* If the host uses TSC clocksource, then it is stable */ 2070 pvclock_flags = 0; 2071 if (use_master_clock) 2072 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 2073 2074 vcpu->hv_clock.flags = pvclock_flags; 2075 2076 if (vcpu->pv_time_enabled) 2077 kvm_setup_pvclock_page(v); 2078 if (v == kvm_get_vcpu(v->kvm, 0)) 2079 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 2080 return 0; 2081 } 2082 2083 /* 2084 * kvmclock updates which are isolated to a given vcpu, such as 2085 * vcpu->cpu migration, should not allow system_timestamp from 2086 * the rest of the vcpus to remain static. Otherwise ntp frequency 2087 * correction applies to one vcpu's system_timestamp but not 2088 * the others. 2089 * 2090 * So in those cases, request a kvmclock update for all vcpus. 2091 * We need to rate-limit these requests though, as they can 2092 * considerably slow guests that have a large number of vcpus. 2093 * The time for a remote vcpu to update its kvmclock is bound 2094 * by the delay we use to rate-limit the updates. 2095 */ 2096 2097 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 2098 2099 static void kvmclock_update_fn(struct work_struct *work) 2100 { 2101 int i; 2102 struct delayed_work *dwork = to_delayed_work(work); 2103 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2104 kvmclock_update_work); 2105 struct kvm *kvm = container_of(ka, struct kvm, arch); 2106 struct kvm_vcpu *vcpu; 2107 2108 kvm_for_each_vcpu(i, vcpu, kvm) { 2109 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2110 kvm_vcpu_kick(vcpu); 2111 } 2112 } 2113 2114 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 2115 { 2116 struct kvm *kvm = v->kvm; 2117 2118 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 2119 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 2120 KVMCLOCK_UPDATE_DELAY); 2121 } 2122 2123 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 2124 2125 static void kvmclock_sync_fn(struct work_struct *work) 2126 { 2127 struct delayed_work *dwork = to_delayed_work(work); 2128 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 2129 kvmclock_sync_work); 2130 struct kvm *kvm = container_of(ka, struct kvm, arch); 2131 2132 if (!kvmclock_periodic_sync) 2133 return; 2134 2135 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 2136 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 2137 KVMCLOCK_SYNC_PERIOD); 2138 } 2139 2140 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2141 { 2142 u64 mcg_cap = vcpu->arch.mcg_cap; 2143 unsigned bank_num = mcg_cap & 0xff; 2144 u32 msr = msr_info->index; 2145 u64 data = msr_info->data; 2146 2147 switch (msr) { 2148 case MSR_IA32_MCG_STATUS: 2149 vcpu->arch.mcg_status = data; 2150 break; 2151 case MSR_IA32_MCG_CTL: 2152 if (!(mcg_cap & MCG_CTL_P)) 2153 return 1; 2154 if (data != 0 && data != ~(u64)0) 2155 return -1; 2156 vcpu->arch.mcg_ctl = data; 2157 break; 2158 default: 2159 if (msr >= MSR_IA32_MC0_CTL && 2160 msr < MSR_IA32_MCx_CTL(bank_num)) { 2161 u32 offset = msr - MSR_IA32_MC0_CTL; 2162 /* only 0 or all 1s can be written to IA32_MCi_CTL 2163 * some Linux kernels though clear bit 10 in bank 4 to 2164 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 2165 * this to avoid an uncatched #GP in the guest 2166 */ 2167 if ((offset & 0x3) == 0 && 2168 data != 0 && (data | (1 << 10)) != ~(u64)0) 2169 return -1; 2170 if (!msr_info->host_initiated && 2171 (offset & 0x3) == 1 && data != 0) 2172 return -1; 2173 vcpu->arch.mce_banks[offset] = data; 2174 break; 2175 } 2176 return 1; 2177 } 2178 return 0; 2179 } 2180 2181 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 2182 { 2183 struct kvm *kvm = vcpu->kvm; 2184 int lm = is_long_mode(vcpu); 2185 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 2186 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 2187 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 2188 : kvm->arch.xen_hvm_config.blob_size_32; 2189 u32 page_num = data & ~PAGE_MASK; 2190 u64 page_addr = data & PAGE_MASK; 2191 u8 *page; 2192 int r; 2193 2194 r = -E2BIG; 2195 if (page_num >= blob_size) 2196 goto out; 2197 r = -ENOMEM; 2198 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 2199 if (IS_ERR(page)) { 2200 r = PTR_ERR(page); 2201 goto out; 2202 } 2203 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 2204 goto out_free; 2205 r = 0; 2206 out_free: 2207 kfree(page); 2208 out: 2209 return r; 2210 } 2211 2212 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 2213 { 2214 gpa_t gpa = data & ~0x3f; 2215 2216 /* Bits 3:5 are reserved, Should be zero */ 2217 if (data & 0x38) 2218 return 1; 2219 2220 vcpu->arch.apf.msr_val = data; 2221 2222 if (!(data & KVM_ASYNC_PF_ENABLED)) { 2223 kvm_clear_async_pf_completion_queue(vcpu); 2224 kvm_async_pf_hash_reset(vcpu); 2225 return 0; 2226 } 2227 2228 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 2229 sizeof(u32))) 2230 return 1; 2231 2232 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 2233 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 2234 kvm_async_pf_wakeup_all(vcpu); 2235 return 0; 2236 } 2237 2238 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2239 { 2240 vcpu->arch.pv_time_enabled = false; 2241 } 2242 2243 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa) 2244 { 2245 ++vcpu->stat.tlb_flush; 2246 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa); 2247 } 2248 2249 static void record_steal_time(struct kvm_vcpu *vcpu) 2250 { 2251 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2252 return; 2253 2254 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2255 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2256 return; 2257 2258 /* 2259 * Doing a TLB flush here, on the guest's behalf, can avoid 2260 * expensive IPIs. 2261 */ 2262 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB) 2263 kvm_vcpu_flush_tlb(vcpu, false); 2264 2265 if (vcpu->arch.st.steal.version & 1) 2266 vcpu->arch.st.steal.version += 1; /* first time write, random junk */ 2267 2268 vcpu->arch.st.steal.version += 1; 2269 2270 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2271 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2272 2273 smp_wmb(); 2274 2275 vcpu->arch.st.steal.steal += current->sched_info.run_delay - 2276 vcpu->arch.st.last_steal; 2277 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2278 2279 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2280 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2281 2282 smp_wmb(); 2283 2284 vcpu->arch.st.steal.version += 1; 2285 2286 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2287 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2288 } 2289 2290 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2291 { 2292 bool pr = false; 2293 u32 msr = msr_info->index; 2294 u64 data = msr_info->data; 2295 2296 switch (msr) { 2297 case MSR_AMD64_NB_CFG: 2298 case MSR_IA32_UCODE_WRITE: 2299 case MSR_VM_HSAVE_PA: 2300 case MSR_AMD64_PATCH_LOADER: 2301 case MSR_AMD64_BU_CFG2: 2302 case MSR_AMD64_DC_CFG: 2303 break; 2304 2305 case MSR_IA32_UCODE_REV: 2306 if (msr_info->host_initiated) 2307 vcpu->arch.microcode_version = data; 2308 break; 2309 case MSR_EFER: 2310 return set_efer(vcpu, data); 2311 case MSR_K7_HWCR: 2312 data &= ~(u64)0x40; /* ignore flush filter disable */ 2313 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2314 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2315 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2316 if (data != 0) { 2317 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2318 data); 2319 return 1; 2320 } 2321 break; 2322 case MSR_FAM10H_MMIO_CONF_BASE: 2323 if (data != 0) { 2324 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2325 "0x%llx\n", data); 2326 return 1; 2327 } 2328 break; 2329 case MSR_IA32_DEBUGCTLMSR: 2330 if (!data) { 2331 /* We support the non-activated case already */ 2332 break; 2333 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2334 /* Values other than LBR and BTF are vendor-specific, 2335 thus reserved and should throw a #GP */ 2336 return 1; 2337 } 2338 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2339 __func__, data); 2340 break; 2341 case 0x200 ... 0x2ff: 2342 return kvm_mtrr_set_msr(vcpu, msr, data); 2343 case MSR_IA32_APICBASE: 2344 return kvm_set_apic_base(vcpu, msr_info); 2345 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2346 return kvm_x2apic_msr_write(vcpu, msr, data); 2347 case MSR_IA32_TSCDEADLINE: 2348 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2349 break; 2350 case MSR_IA32_TSC_ADJUST: 2351 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 2352 if (!msr_info->host_initiated) { 2353 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2354 adjust_tsc_offset_guest(vcpu, adj); 2355 } 2356 vcpu->arch.ia32_tsc_adjust_msr = data; 2357 } 2358 break; 2359 case MSR_IA32_MISC_ENABLE: 2360 vcpu->arch.ia32_misc_enable_msr = data; 2361 break; 2362 case MSR_IA32_SMBASE: 2363 if (!msr_info->host_initiated) 2364 return 1; 2365 vcpu->arch.smbase = data; 2366 break; 2367 case MSR_IA32_TSC: 2368 kvm_write_tsc(vcpu, msr_info); 2369 break; 2370 case MSR_SMI_COUNT: 2371 if (!msr_info->host_initiated) 2372 return 1; 2373 vcpu->arch.smi_count = data; 2374 break; 2375 case MSR_KVM_WALL_CLOCK_NEW: 2376 case MSR_KVM_WALL_CLOCK: 2377 vcpu->kvm->arch.wall_clock = data; 2378 kvm_write_wall_clock(vcpu->kvm, data); 2379 break; 2380 case MSR_KVM_SYSTEM_TIME_NEW: 2381 case MSR_KVM_SYSTEM_TIME: { 2382 struct kvm_arch *ka = &vcpu->kvm->arch; 2383 2384 kvmclock_reset(vcpu); 2385 2386 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2387 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2388 2389 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2390 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2391 2392 ka->boot_vcpu_runs_old_kvmclock = tmp; 2393 } 2394 2395 vcpu->arch.time = data; 2396 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2397 2398 /* we verify if the enable bit is set... */ 2399 if (!(data & 1)) 2400 break; 2401 2402 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2403 &vcpu->arch.pv_time, data & ~1ULL, 2404 sizeof(struct pvclock_vcpu_time_info))) 2405 vcpu->arch.pv_time_enabled = false; 2406 else 2407 vcpu->arch.pv_time_enabled = true; 2408 2409 break; 2410 } 2411 case MSR_KVM_ASYNC_PF_EN: 2412 if (kvm_pv_enable_async_pf(vcpu, data)) 2413 return 1; 2414 break; 2415 case MSR_KVM_STEAL_TIME: 2416 2417 if (unlikely(!sched_info_on())) 2418 return 1; 2419 2420 if (data & KVM_STEAL_RESERVED_MASK) 2421 return 1; 2422 2423 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2424 data & KVM_STEAL_VALID_BITS, 2425 sizeof(struct kvm_steal_time))) 2426 return 1; 2427 2428 vcpu->arch.st.msr_val = data; 2429 2430 if (!(data & KVM_MSR_ENABLED)) 2431 break; 2432 2433 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2434 2435 break; 2436 case MSR_KVM_PV_EOI_EN: 2437 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2438 return 1; 2439 break; 2440 2441 case MSR_IA32_MCG_CTL: 2442 case MSR_IA32_MCG_STATUS: 2443 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2444 return set_msr_mce(vcpu, msr_info); 2445 2446 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2447 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2448 pr = true; /* fall through */ 2449 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2450 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2451 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2452 return kvm_pmu_set_msr(vcpu, msr_info); 2453 2454 if (pr || data != 0) 2455 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2456 "0x%x data 0x%llx\n", msr, data); 2457 break; 2458 case MSR_K7_CLK_CTL: 2459 /* 2460 * Ignore all writes to this no longer documented MSR. 2461 * Writes are only relevant for old K7 processors, 2462 * all pre-dating SVM, but a recommended workaround from 2463 * AMD for these chips. It is possible to specify the 2464 * affected processor models on the command line, hence 2465 * the need to ignore the workaround. 2466 */ 2467 break; 2468 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2469 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2470 case HV_X64_MSR_CRASH_CTL: 2471 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2472 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 2473 case HV_X64_MSR_TSC_EMULATION_CONTROL: 2474 case HV_X64_MSR_TSC_EMULATION_STATUS: 2475 return kvm_hv_set_msr_common(vcpu, msr, data, 2476 msr_info->host_initiated); 2477 case MSR_IA32_BBL_CR_CTL3: 2478 /* Drop writes to this legacy MSR -- see rdmsr 2479 * counterpart for further detail. 2480 */ 2481 if (report_ignored_msrs) 2482 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", 2483 msr, data); 2484 break; 2485 case MSR_AMD64_OSVW_ID_LENGTH: 2486 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2487 return 1; 2488 vcpu->arch.osvw.length = data; 2489 break; 2490 case MSR_AMD64_OSVW_STATUS: 2491 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2492 return 1; 2493 vcpu->arch.osvw.status = data; 2494 break; 2495 case MSR_PLATFORM_INFO: 2496 if (!msr_info->host_initiated || 2497 data & ~MSR_PLATFORM_INFO_CPUID_FAULT || 2498 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 2499 cpuid_fault_enabled(vcpu))) 2500 return 1; 2501 vcpu->arch.msr_platform_info = data; 2502 break; 2503 case MSR_MISC_FEATURES_ENABLES: 2504 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 2505 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 2506 !supports_cpuid_fault(vcpu))) 2507 return 1; 2508 vcpu->arch.msr_misc_features_enables = data; 2509 break; 2510 default: 2511 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2512 return xen_hvm_config(vcpu, data); 2513 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2514 return kvm_pmu_set_msr(vcpu, msr_info); 2515 if (!ignore_msrs) { 2516 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n", 2517 msr, data); 2518 return 1; 2519 } else { 2520 if (report_ignored_msrs) 2521 vcpu_unimpl(vcpu, 2522 "ignored wrmsr: 0x%x data 0x%llx\n", 2523 msr, data); 2524 break; 2525 } 2526 } 2527 return 0; 2528 } 2529 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2530 2531 2532 /* 2533 * Reads an msr value (of 'msr_index') into 'pdata'. 2534 * Returns 0 on success, non-0 otherwise. 2535 * Assumes vcpu_load() was already called. 2536 */ 2537 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 2538 { 2539 return kvm_x86_ops->get_msr(vcpu, msr); 2540 } 2541 EXPORT_SYMBOL_GPL(kvm_get_msr); 2542 2543 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2544 { 2545 u64 data; 2546 u64 mcg_cap = vcpu->arch.mcg_cap; 2547 unsigned bank_num = mcg_cap & 0xff; 2548 2549 switch (msr) { 2550 case MSR_IA32_P5_MC_ADDR: 2551 case MSR_IA32_P5_MC_TYPE: 2552 data = 0; 2553 break; 2554 case MSR_IA32_MCG_CAP: 2555 data = vcpu->arch.mcg_cap; 2556 break; 2557 case MSR_IA32_MCG_CTL: 2558 if (!(mcg_cap & MCG_CTL_P)) 2559 return 1; 2560 data = vcpu->arch.mcg_ctl; 2561 break; 2562 case MSR_IA32_MCG_STATUS: 2563 data = vcpu->arch.mcg_status; 2564 break; 2565 default: 2566 if (msr >= MSR_IA32_MC0_CTL && 2567 msr < MSR_IA32_MCx_CTL(bank_num)) { 2568 u32 offset = msr - MSR_IA32_MC0_CTL; 2569 data = vcpu->arch.mce_banks[offset]; 2570 break; 2571 } 2572 return 1; 2573 } 2574 *pdata = data; 2575 return 0; 2576 } 2577 2578 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2579 { 2580 switch (msr_info->index) { 2581 case MSR_IA32_PLATFORM_ID: 2582 case MSR_IA32_EBL_CR_POWERON: 2583 case MSR_IA32_DEBUGCTLMSR: 2584 case MSR_IA32_LASTBRANCHFROMIP: 2585 case MSR_IA32_LASTBRANCHTOIP: 2586 case MSR_IA32_LASTINTFROMIP: 2587 case MSR_IA32_LASTINTTOIP: 2588 case MSR_K8_SYSCFG: 2589 case MSR_K8_TSEG_ADDR: 2590 case MSR_K8_TSEG_MASK: 2591 case MSR_K7_HWCR: 2592 case MSR_VM_HSAVE_PA: 2593 case MSR_K8_INT_PENDING_MSG: 2594 case MSR_AMD64_NB_CFG: 2595 case MSR_FAM10H_MMIO_CONF_BASE: 2596 case MSR_AMD64_BU_CFG2: 2597 case MSR_IA32_PERF_CTL: 2598 case MSR_AMD64_DC_CFG: 2599 msr_info->data = 0; 2600 break; 2601 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 2602 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2603 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2604 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2605 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2606 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2607 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2608 msr_info->data = 0; 2609 break; 2610 case MSR_IA32_UCODE_REV: 2611 msr_info->data = vcpu->arch.microcode_version; 2612 break; 2613 case MSR_IA32_TSC: 2614 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset; 2615 break; 2616 case MSR_MTRRcap: 2617 case 0x200 ... 0x2ff: 2618 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 2619 case 0xcd: /* fsb frequency */ 2620 msr_info->data = 3; 2621 break; 2622 /* 2623 * MSR_EBC_FREQUENCY_ID 2624 * Conservative value valid for even the basic CPU models. 2625 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2626 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2627 * and 266MHz for model 3, or 4. Set Core Clock 2628 * Frequency to System Bus Frequency Ratio to 1 (bits 2629 * 31:24) even though these are only valid for CPU 2630 * models > 2, however guests may end up dividing or 2631 * multiplying by zero otherwise. 2632 */ 2633 case MSR_EBC_FREQUENCY_ID: 2634 msr_info->data = 1 << 24; 2635 break; 2636 case MSR_IA32_APICBASE: 2637 msr_info->data = kvm_get_apic_base(vcpu); 2638 break; 2639 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2640 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 2641 break; 2642 case MSR_IA32_TSCDEADLINE: 2643 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 2644 break; 2645 case MSR_IA32_TSC_ADJUST: 2646 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2647 break; 2648 case MSR_IA32_MISC_ENABLE: 2649 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 2650 break; 2651 case MSR_IA32_SMBASE: 2652 if (!msr_info->host_initiated) 2653 return 1; 2654 msr_info->data = vcpu->arch.smbase; 2655 break; 2656 case MSR_SMI_COUNT: 2657 msr_info->data = vcpu->arch.smi_count; 2658 break; 2659 case MSR_IA32_PERF_STATUS: 2660 /* TSC increment by tick */ 2661 msr_info->data = 1000ULL; 2662 /* CPU multiplier */ 2663 msr_info->data |= (((uint64_t)4ULL) << 40); 2664 break; 2665 case MSR_EFER: 2666 msr_info->data = vcpu->arch.efer; 2667 break; 2668 case MSR_KVM_WALL_CLOCK: 2669 case MSR_KVM_WALL_CLOCK_NEW: 2670 msr_info->data = vcpu->kvm->arch.wall_clock; 2671 break; 2672 case MSR_KVM_SYSTEM_TIME: 2673 case MSR_KVM_SYSTEM_TIME_NEW: 2674 msr_info->data = vcpu->arch.time; 2675 break; 2676 case MSR_KVM_ASYNC_PF_EN: 2677 msr_info->data = vcpu->arch.apf.msr_val; 2678 break; 2679 case MSR_KVM_STEAL_TIME: 2680 msr_info->data = vcpu->arch.st.msr_val; 2681 break; 2682 case MSR_KVM_PV_EOI_EN: 2683 msr_info->data = vcpu->arch.pv_eoi.msr_val; 2684 break; 2685 case MSR_IA32_P5_MC_ADDR: 2686 case MSR_IA32_P5_MC_TYPE: 2687 case MSR_IA32_MCG_CAP: 2688 case MSR_IA32_MCG_CTL: 2689 case MSR_IA32_MCG_STATUS: 2690 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2691 return get_msr_mce(vcpu, msr_info->index, &msr_info->data); 2692 case MSR_K7_CLK_CTL: 2693 /* 2694 * Provide expected ramp-up count for K7. All other 2695 * are set to zero, indicating minimum divisors for 2696 * every field. 2697 * 2698 * This prevents guest kernels on AMD host with CPU 2699 * type 6, model 8 and higher from exploding due to 2700 * the rdmsr failing. 2701 */ 2702 msr_info->data = 0x20000000; 2703 break; 2704 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2705 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2706 case HV_X64_MSR_CRASH_CTL: 2707 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2708 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 2709 case HV_X64_MSR_TSC_EMULATION_CONTROL: 2710 case HV_X64_MSR_TSC_EMULATION_STATUS: 2711 return kvm_hv_get_msr_common(vcpu, 2712 msr_info->index, &msr_info->data); 2713 break; 2714 case MSR_IA32_BBL_CR_CTL3: 2715 /* This legacy MSR exists but isn't fully documented in current 2716 * silicon. It is however accessed by winxp in very narrow 2717 * scenarios where it sets bit #19, itself documented as 2718 * a "reserved" bit. Best effort attempt to source coherent 2719 * read data here should the balance of the register be 2720 * interpreted by the guest: 2721 * 2722 * L2 cache control register 3: 64GB range, 256KB size, 2723 * enabled, latency 0x1, configured 2724 */ 2725 msr_info->data = 0xbe702111; 2726 break; 2727 case MSR_AMD64_OSVW_ID_LENGTH: 2728 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2729 return 1; 2730 msr_info->data = vcpu->arch.osvw.length; 2731 break; 2732 case MSR_AMD64_OSVW_STATUS: 2733 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 2734 return 1; 2735 msr_info->data = vcpu->arch.osvw.status; 2736 break; 2737 case MSR_PLATFORM_INFO: 2738 msr_info->data = vcpu->arch.msr_platform_info; 2739 break; 2740 case MSR_MISC_FEATURES_ENABLES: 2741 msr_info->data = vcpu->arch.msr_misc_features_enables; 2742 break; 2743 default: 2744 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2745 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2746 if (!ignore_msrs) { 2747 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n", 2748 msr_info->index); 2749 return 1; 2750 } else { 2751 if (report_ignored_msrs) 2752 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", 2753 msr_info->index); 2754 msr_info->data = 0; 2755 } 2756 break; 2757 } 2758 return 0; 2759 } 2760 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2761 2762 /* 2763 * Read or write a bunch of msrs. All parameters are kernel addresses. 2764 * 2765 * @return number of msrs set successfully. 2766 */ 2767 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2768 struct kvm_msr_entry *entries, 2769 int (*do_msr)(struct kvm_vcpu *vcpu, 2770 unsigned index, u64 *data)) 2771 { 2772 int i; 2773 2774 for (i = 0; i < msrs->nmsrs; ++i) 2775 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2776 break; 2777 2778 return i; 2779 } 2780 2781 /* 2782 * Read or write a bunch of msrs. Parameters are user addresses. 2783 * 2784 * @return number of msrs set successfully. 2785 */ 2786 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2787 int (*do_msr)(struct kvm_vcpu *vcpu, 2788 unsigned index, u64 *data), 2789 int writeback) 2790 { 2791 struct kvm_msrs msrs; 2792 struct kvm_msr_entry *entries; 2793 int r, n; 2794 unsigned size; 2795 2796 r = -EFAULT; 2797 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2798 goto out; 2799 2800 r = -E2BIG; 2801 if (msrs.nmsrs >= MAX_IO_MSRS) 2802 goto out; 2803 2804 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2805 entries = memdup_user(user_msrs->entries, size); 2806 if (IS_ERR(entries)) { 2807 r = PTR_ERR(entries); 2808 goto out; 2809 } 2810 2811 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2812 if (r < 0) 2813 goto out_free; 2814 2815 r = -EFAULT; 2816 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2817 goto out_free; 2818 2819 r = n; 2820 2821 out_free: 2822 kfree(entries); 2823 out: 2824 return r; 2825 } 2826 2827 static inline bool kvm_can_mwait_in_guest(void) 2828 { 2829 return boot_cpu_has(X86_FEATURE_MWAIT) && 2830 !boot_cpu_has_bug(X86_BUG_MONITOR) && 2831 boot_cpu_has(X86_FEATURE_ARAT); 2832 } 2833 2834 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2835 { 2836 int r = 0; 2837 2838 switch (ext) { 2839 case KVM_CAP_IRQCHIP: 2840 case KVM_CAP_HLT: 2841 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2842 case KVM_CAP_SET_TSS_ADDR: 2843 case KVM_CAP_EXT_CPUID: 2844 case KVM_CAP_EXT_EMUL_CPUID: 2845 case KVM_CAP_CLOCKSOURCE: 2846 case KVM_CAP_PIT: 2847 case KVM_CAP_NOP_IO_DELAY: 2848 case KVM_CAP_MP_STATE: 2849 case KVM_CAP_SYNC_MMU: 2850 case KVM_CAP_USER_NMI: 2851 case KVM_CAP_REINJECT_CONTROL: 2852 case KVM_CAP_IRQ_INJECT_STATUS: 2853 case KVM_CAP_IOEVENTFD: 2854 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2855 case KVM_CAP_PIT2: 2856 case KVM_CAP_PIT_STATE2: 2857 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2858 case KVM_CAP_XEN_HVM: 2859 case KVM_CAP_VCPU_EVENTS: 2860 case KVM_CAP_HYPERV: 2861 case KVM_CAP_HYPERV_VAPIC: 2862 case KVM_CAP_HYPERV_SPIN: 2863 case KVM_CAP_HYPERV_SYNIC: 2864 case KVM_CAP_HYPERV_SYNIC2: 2865 case KVM_CAP_HYPERV_VP_INDEX: 2866 case KVM_CAP_HYPERV_EVENTFD: 2867 case KVM_CAP_PCI_SEGMENT: 2868 case KVM_CAP_DEBUGREGS: 2869 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2870 case KVM_CAP_XSAVE: 2871 case KVM_CAP_ASYNC_PF: 2872 case KVM_CAP_GET_TSC_KHZ: 2873 case KVM_CAP_KVMCLOCK_CTRL: 2874 case KVM_CAP_READONLY_MEM: 2875 case KVM_CAP_HYPERV_TIME: 2876 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2877 case KVM_CAP_TSC_DEADLINE_TIMER: 2878 case KVM_CAP_ENABLE_CAP_VM: 2879 case KVM_CAP_DISABLE_QUIRKS: 2880 case KVM_CAP_SET_BOOT_CPU_ID: 2881 case KVM_CAP_SPLIT_IRQCHIP: 2882 case KVM_CAP_IMMEDIATE_EXIT: 2883 case KVM_CAP_GET_MSR_FEATURES: 2884 r = 1; 2885 break; 2886 case KVM_CAP_SYNC_REGS: 2887 r = KVM_SYNC_X86_VALID_FIELDS; 2888 break; 2889 case KVM_CAP_ADJUST_CLOCK: 2890 r = KVM_CLOCK_TSC_STABLE; 2891 break; 2892 case KVM_CAP_X86_DISABLE_EXITS: 2893 r |= KVM_X86_DISABLE_EXITS_HTL | KVM_X86_DISABLE_EXITS_PAUSE; 2894 if(kvm_can_mwait_in_guest()) 2895 r |= KVM_X86_DISABLE_EXITS_MWAIT; 2896 break; 2897 case KVM_CAP_X86_SMM: 2898 /* SMBASE is usually relocated above 1M on modern chipsets, 2899 * and SMM handlers might indeed rely on 4G segment limits, 2900 * so do not report SMM to be available if real mode is 2901 * emulated via vm86 mode. Still, do not go to great lengths 2902 * to avoid userspace's usage of the feature, because it is a 2903 * fringe case that is not enabled except via specific settings 2904 * of the module parameters. 2905 */ 2906 r = kvm_x86_ops->cpu_has_high_real_mode_segbase(); 2907 break; 2908 case KVM_CAP_VAPIC: 2909 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2910 break; 2911 case KVM_CAP_NR_VCPUS: 2912 r = KVM_SOFT_MAX_VCPUS; 2913 break; 2914 case KVM_CAP_MAX_VCPUS: 2915 r = KVM_MAX_VCPUS; 2916 break; 2917 case KVM_CAP_NR_MEMSLOTS: 2918 r = KVM_USER_MEM_SLOTS; 2919 break; 2920 case KVM_CAP_PV_MMU: /* obsolete */ 2921 r = 0; 2922 break; 2923 case KVM_CAP_MCE: 2924 r = KVM_MAX_MCE_BANKS; 2925 break; 2926 case KVM_CAP_XCRS: 2927 r = boot_cpu_has(X86_FEATURE_XSAVE); 2928 break; 2929 case KVM_CAP_TSC_CONTROL: 2930 r = kvm_has_tsc_control; 2931 break; 2932 case KVM_CAP_X2APIC_API: 2933 r = KVM_X2APIC_API_VALID_FLAGS; 2934 break; 2935 default: 2936 break; 2937 } 2938 return r; 2939 2940 } 2941 2942 long kvm_arch_dev_ioctl(struct file *filp, 2943 unsigned int ioctl, unsigned long arg) 2944 { 2945 void __user *argp = (void __user *)arg; 2946 long r; 2947 2948 switch (ioctl) { 2949 case KVM_GET_MSR_INDEX_LIST: { 2950 struct kvm_msr_list __user *user_msr_list = argp; 2951 struct kvm_msr_list msr_list; 2952 unsigned n; 2953 2954 r = -EFAULT; 2955 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2956 goto out; 2957 n = msr_list.nmsrs; 2958 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 2959 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2960 goto out; 2961 r = -E2BIG; 2962 if (n < msr_list.nmsrs) 2963 goto out; 2964 r = -EFAULT; 2965 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2966 num_msrs_to_save * sizeof(u32))) 2967 goto out; 2968 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2969 &emulated_msrs, 2970 num_emulated_msrs * sizeof(u32))) 2971 goto out; 2972 r = 0; 2973 break; 2974 } 2975 case KVM_GET_SUPPORTED_CPUID: 2976 case KVM_GET_EMULATED_CPUID: { 2977 struct kvm_cpuid2 __user *cpuid_arg = argp; 2978 struct kvm_cpuid2 cpuid; 2979 2980 r = -EFAULT; 2981 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2982 goto out; 2983 2984 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2985 ioctl); 2986 if (r) 2987 goto out; 2988 2989 r = -EFAULT; 2990 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2991 goto out; 2992 r = 0; 2993 break; 2994 } 2995 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2996 r = -EFAULT; 2997 if (copy_to_user(argp, &kvm_mce_cap_supported, 2998 sizeof(kvm_mce_cap_supported))) 2999 goto out; 3000 r = 0; 3001 break; 3002 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 3003 struct kvm_msr_list __user *user_msr_list = argp; 3004 struct kvm_msr_list msr_list; 3005 unsigned int n; 3006 3007 r = -EFAULT; 3008 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 3009 goto out; 3010 n = msr_list.nmsrs; 3011 msr_list.nmsrs = num_msr_based_features; 3012 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 3013 goto out; 3014 r = -E2BIG; 3015 if (n < msr_list.nmsrs) 3016 goto out; 3017 r = -EFAULT; 3018 if (copy_to_user(user_msr_list->indices, &msr_based_features, 3019 num_msr_based_features * sizeof(u32))) 3020 goto out; 3021 r = 0; 3022 break; 3023 } 3024 case KVM_GET_MSRS: 3025 r = msr_io(NULL, argp, do_get_msr_feature, 1); 3026 break; 3027 } 3028 default: 3029 r = -EINVAL; 3030 } 3031 out: 3032 return r; 3033 } 3034 3035 static void wbinvd_ipi(void *garbage) 3036 { 3037 wbinvd(); 3038 } 3039 3040 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 3041 { 3042 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 3043 } 3044 3045 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 3046 { 3047 /* Address WBINVD may be executed by guest */ 3048 if (need_emulate_wbinvd(vcpu)) { 3049 if (kvm_x86_ops->has_wbinvd_exit()) 3050 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 3051 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 3052 smp_call_function_single(vcpu->cpu, 3053 wbinvd_ipi, NULL, 1); 3054 } 3055 3056 kvm_x86_ops->vcpu_load(vcpu, cpu); 3057 3058 /* Apply any externally detected TSC adjustments (due to suspend) */ 3059 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 3060 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 3061 vcpu->arch.tsc_offset_adjustment = 0; 3062 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3063 } 3064 3065 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 3066 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 3067 rdtsc() - vcpu->arch.last_host_tsc; 3068 if (tsc_delta < 0) 3069 mark_tsc_unstable("KVM discovered backwards TSC"); 3070 3071 if (kvm_check_tsc_unstable()) { 3072 u64 offset = kvm_compute_tsc_offset(vcpu, 3073 vcpu->arch.last_guest_tsc); 3074 kvm_vcpu_write_tsc_offset(vcpu, offset); 3075 vcpu->arch.tsc_catchup = 1; 3076 } 3077 3078 if (kvm_lapic_hv_timer_in_use(vcpu)) 3079 kvm_lapic_restart_hv_timer(vcpu); 3080 3081 /* 3082 * On a host with synchronized TSC, there is no need to update 3083 * kvmclock on vcpu->cpu migration 3084 */ 3085 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 3086 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 3087 if (vcpu->cpu != cpu) 3088 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 3089 vcpu->cpu = cpu; 3090 } 3091 3092 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3093 } 3094 3095 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 3096 { 3097 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3098 return; 3099 3100 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED; 3101 3102 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime, 3103 &vcpu->arch.st.steal.preempted, 3104 offsetof(struct kvm_steal_time, preempted), 3105 sizeof(vcpu->arch.st.steal.preempted)); 3106 } 3107 3108 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 3109 { 3110 int idx; 3111 3112 if (vcpu->preempted) 3113 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu); 3114 3115 /* 3116 * Disable page faults because we're in atomic context here. 3117 * kvm_write_guest_offset_cached() would call might_fault() 3118 * that relies on pagefault_disable() to tell if there's a 3119 * bug. NOTE: the write to guest memory may not go through if 3120 * during postcopy live migration or if there's heavy guest 3121 * paging. 3122 */ 3123 pagefault_disable(); 3124 /* 3125 * kvm_memslots() will be called by 3126 * kvm_write_guest_offset_cached() so take the srcu lock. 3127 */ 3128 idx = srcu_read_lock(&vcpu->kvm->srcu); 3129 kvm_steal_time_set_preempted(vcpu); 3130 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3131 pagefault_enable(); 3132 kvm_x86_ops->vcpu_put(vcpu); 3133 vcpu->arch.last_host_tsc = rdtsc(); 3134 /* 3135 * If userspace has set any breakpoints or watchpoints, dr6 is restored 3136 * on every vmexit, but if not, we might have a stale dr6 from the 3137 * guest. do_debug expects dr6 to be cleared after it runs, do the same. 3138 */ 3139 set_debugreg(0, 6); 3140 } 3141 3142 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 3143 struct kvm_lapic_state *s) 3144 { 3145 if (vcpu->arch.apicv_active) 3146 kvm_x86_ops->sync_pir_to_irr(vcpu); 3147 3148 return kvm_apic_get_state(vcpu, s); 3149 } 3150 3151 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 3152 struct kvm_lapic_state *s) 3153 { 3154 int r; 3155 3156 r = kvm_apic_set_state(vcpu, s); 3157 if (r) 3158 return r; 3159 update_cr8_intercept(vcpu); 3160 3161 return 0; 3162 } 3163 3164 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 3165 { 3166 return (!lapic_in_kernel(vcpu) || 3167 kvm_apic_accept_pic_intr(vcpu)); 3168 } 3169 3170 /* 3171 * if userspace requested an interrupt window, check that the 3172 * interrupt window is open. 3173 * 3174 * No need to exit to userspace if we already have an interrupt queued. 3175 */ 3176 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 3177 { 3178 return kvm_arch_interrupt_allowed(vcpu) && 3179 !kvm_cpu_has_interrupt(vcpu) && 3180 !kvm_event_needs_reinjection(vcpu) && 3181 kvm_cpu_accept_dm_intr(vcpu); 3182 } 3183 3184 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 3185 struct kvm_interrupt *irq) 3186 { 3187 if (irq->irq >= KVM_NR_INTERRUPTS) 3188 return -EINVAL; 3189 3190 if (!irqchip_in_kernel(vcpu->kvm)) { 3191 kvm_queue_interrupt(vcpu, irq->irq, false); 3192 kvm_make_request(KVM_REQ_EVENT, vcpu); 3193 return 0; 3194 } 3195 3196 /* 3197 * With in-kernel LAPIC, we only use this to inject EXTINT, so 3198 * fail for in-kernel 8259. 3199 */ 3200 if (pic_in_kernel(vcpu->kvm)) 3201 return -ENXIO; 3202 3203 if (vcpu->arch.pending_external_vector != -1) 3204 return -EEXIST; 3205 3206 vcpu->arch.pending_external_vector = irq->irq; 3207 kvm_make_request(KVM_REQ_EVENT, vcpu); 3208 return 0; 3209 } 3210 3211 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 3212 { 3213 kvm_inject_nmi(vcpu); 3214 3215 return 0; 3216 } 3217 3218 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 3219 { 3220 kvm_make_request(KVM_REQ_SMI, vcpu); 3221 3222 return 0; 3223 } 3224 3225 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 3226 struct kvm_tpr_access_ctl *tac) 3227 { 3228 if (tac->flags) 3229 return -EINVAL; 3230 vcpu->arch.tpr_access_reporting = !!tac->enabled; 3231 return 0; 3232 } 3233 3234 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 3235 u64 mcg_cap) 3236 { 3237 int r; 3238 unsigned bank_num = mcg_cap & 0xff, bank; 3239 3240 r = -EINVAL; 3241 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 3242 goto out; 3243 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000)) 3244 goto out; 3245 r = 0; 3246 vcpu->arch.mcg_cap = mcg_cap; 3247 /* Init IA32_MCG_CTL to all 1s */ 3248 if (mcg_cap & MCG_CTL_P) 3249 vcpu->arch.mcg_ctl = ~(u64)0; 3250 /* Init IA32_MCi_CTL to all 1s */ 3251 for (bank = 0; bank < bank_num; bank++) 3252 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 3253 3254 if (kvm_x86_ops->setup_mce) 3255 kvm_x86_ops->setup_mce(vcpu); 3256 out: 3257 return r; 3258 } 3259 3260 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 3261 struct kvm_x86_mce *mce) 3262 { 3263 u64 mcg_cap = vcpu->arch.mcg_cap; 3264 unsigned bank_num = mcg_cap & 0xff; 3265 u64 *banks = vcpu->arch.mce_banks; 3266 3267 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 3268 return -EINVAL; 3269 /* 3270 * if IA32_MCG_CTL is not all 1s, the uncorrected error 3271 * reporting is disabled 3272 */ 3273 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 3274 vcpu->arch.mcg_ctl != ~(u64)0) 3275 return 0; 3276 banks += 4 * mce->bank; 3277 /* 3278 * if IA32_MCi_CTL is not all 1s, the uncorrected error 3279 * reporting is disabled for the bank 3280 */ 3281 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 3282 return 0; 3283 if (mce->status & MCI_STATUS_UC) { 3284 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 3285 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 3286 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 3287 return 0; 3288 } 3289 if (banks[1] & MCI_STATUS_VAL) 3290 mce->status |= MCI_STATUS_OVER; 3291 banks[2] = mce->addr; 3292 banks[3] = mce->misc; 3293 vcpu->arch.mcg_status = mce->mcg_status; 3294 banks[1] = mce->status; 3295 kvm_queue_exception(vcpu, MC_VECTOR); 3296 } else if (!(banks[1] & MCI_STATUS_VAL) 3297 || !(banks[1] & MCI_STATUS_UC)) { 3298 if (banks[1] & MCI_STATUS_VAL) 3299 mce->status |= MCI_STATUS_OVER; 3300 banks[2] = mce->addr; 3301 banks[3] = mce->misc; 3302 banks[1] = mce->status; 3303 } else 3304 banks[1] |= MCI_STATUS_OVER; 3305 return 0; 3306 } 3307 3308 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 3309 struct kvm_vcpu_events *events) 3310 { 3311 process_nmi(vcpu); 3312 /* 3313 * FIXME: pass injected and pending separately. This is only 3314 * needed for nested virtualization, whose state cannot be 3315 * migrated yet. For now we can combine them. 3316 */ 3317 events->exception.injected = 3318 (vcpu->arch.exception.pending || 3319 vcpu->arch.exception.injected) && 3320 !kvm_exception_is_soft(vcpu->arch.exception.nr); 3321 events->exception.nr = vcpu->arch.exception.nr; 3322 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 3323 events->exception.pad = 0; 3324 events->exception.error_code = vcpu->arch.exception.error_code; 3325 3326 events->interrupt.injected = 3327 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 3328 events->interrupt.nr = vcpu->arch.interrupt.nr; 3329 events->interrupt.soft = 0; 3330 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 3331 3332 events->nmi.injected = vcpu->arch.nmi_injected; 3333 events->nmi.pending = vcpu->arch.nmi_pending != 0; 3334 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 3335 events->nmi.pad = 0; 3336 3337 events->sipi_vector = 0; /* never valid when reporting to user space */ 3338 3339 events->smi.smm = is_smm(vcpu); 3340 events->smi.pending = vcpu->arch.smi_pending; 3341 events->smi.smm_inside_nmi = 3342 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 3343 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 3344 3345 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 3346 | KVM_VCPUEVENT_VALID_SHADOW 3347 | KVM_VCPUEVENT_VALID_SMM); 3348 memset(&events->reserved, 0, sizeof(events->reserved)); 3349 } 3350 3351 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags); 3352 3353 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 3354 struct kvm_vcpu_events *events) 3355 { 3356 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 3357 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 3358 | KVM_VCPUEVENT_VALID_SHADOW 3359 | KVM_VCPUEVENT_VALID_SMM)) 3360 return -EINVAL; 3361 3362 if (events->exception.injected && 3363 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR || 3364 is_guest_mode(vcpu))) 3365 return -EINVAL; 3366 3367 /* INITs are latched while in SMM */ 3368 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 3369 (events->smi.smm || events->smi.pending) && 3370 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 3371 return -EINVAL; 3372 3373 process_nmi(vcpu); 3374 vcpu->arch.exception.injected = false; 3375 vcpu->arch.exception.pending = events->exception.injected; 3376 vcpu->arch.exception.nr = events->exception.nr; 3377 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 3378 vcpu->arch.exception.error_code = events->exception.error_code; 3379 3380 vcpu->arch.interrupt.injected = events->interrupt.injected; 3381 vcpu->arch.interrupt.nr = events->interrupt.nr; 3382 vcpu->arch.interrupt.soft = events->interrupt.soft; 3383 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3384 kvm_x86_ops->set_interrupt_shadow(vcpu, 3385 events->interrupt.shadow); 3386 3387 vcpu->arch.nmi_injected = events->nmi.injected; 3388 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3389 vcpu->arch.nmi_pending = events->nmi.pending; 3390 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 3391 3392 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3393 lapic_in_kernel(vcpu)) 3394 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3395 3396 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 3397 u32 hflags = vcpu->arch.hflags; 3398 if (events->smi.smm) 3399 hflags |= HF_SMM_MASK; 3400 else 3401 hflags &= ~HF_SMM_MASK; 3402 kvm_set_hflags(vcpu, hflags); 3403 3404 vcpu->arch.smi_pending = events->smi.pending; 3405 3406 if (events->smi.smm) { 3407 if (events->smi.smm_inside_nmi) 3408 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 3409 else 3410 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 3411 if (lapic_in_kernel(vcpu)) { 3412 if (events->smi.latched_init) 3413 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3414 else 3415 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3416 } 3417 } 3418 } 3419 3420 kvm_make_request(KVM_REQ_EVENT, vcpu); 3421 3422 return 0; 3423 } 3424 3425 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3426 struct kvm_debugregs *dbgregs) 3427 { 3428 unsigned long val; 3429 3430 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3431 kvm_get_dr(vcpu, 6, &val); 3432 dbgregs->dr6 = val; 3433 dbgregs->dr7 = vcpu->arch.dr7; 3434 dbgregs->flags = 0; 3435 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3436 } 3437 3438 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3439 struct kvm_debugregs *dbgregs) 3440 { 3441 if (dbgregs->flags) 3442 return -EINVAL; 3443 3444 if (dbgregs->dr6 & ~0xffffffffull) 3445 return -EINVAL; 3446 if (dbgregs->dr7 & ~0xffffffffull) 3447 return -EINVAL; 3448 3449 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3450 kvm_update_dr0123(vcpu); 3451 vcpu->arch.dr6 = dbgregs->dr6; 3452 kvm_update_dr6(vcpu); 3453 vcpu->arch.dr7 = dbgregs->dr7; 3454 kvm_update_dr7(vcpu); 3455 3456 return 0; 3457 } 3458 3459 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3460 3461 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3462 { 3463 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3464 u64 xstate_bv = xsave->header.xfeatures; 3465 u64 valid; 3466 3467 /* 3468 * Copy legacy XSAVE area, to avoid complications with CPUID 3469 * leaves 0 and 1 in the loop below. 3470 */ 3471 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3472 3473 /* Set XSTATE_BV */ 3474 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE; 3475 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3476 3477 /* 3478 * Copy each region from the possibly compacted offset to the 3479 * non-compacted offset. 3480 */ 3481 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3482 while (valid) { 3483 u64 feature = valid & -valid; 3484 int index = fls64(feature) - 1; 3485 void *src = get_xsave_addr(xsave, feature); 3486 3487 if (src) { 3488 u32 size, offset, ecx, edx; 3489 cpuid_count(XSTATE_CPUID, index, 3490 &size, &offset, &ecx, &edx); 3491 if (feature == XFEATURE_MASK_PKRU) 3492 memcpy(dest + offset, &vcpu->arch.pkru, 3493 sizeof(vcpu->arch.pkru)); 3494 else 3495 memcpy(dest + offset, src, size); 3496 3497 } 3498 3499 valid -= feature; 3500 } 3501 } 3502 3503 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3504 { 3505 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3506 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3507 u64 valid; 3508 3509 /* 3510 * Copy legacy XSAVE area, to avoid complications with CPUID 3511 * leaves 0 and 1 in the loop below. 3512 */ 3513 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3514 3515 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3516 xsave->header.xfeatures = xstate_bv; 3517 if (boot_cpu_has(X86_FEATURE_XSAVES)) 3518 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3519 3520 /* 3521 * Copy each region from the non-compacted offset to the 3522 * possibly compacted offset. 3523 */ 3524 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3525 while (valid) { 3526 u64 feature = valid & -valid; 3527 int index = fls64(feature) - 1; 3528 void *dest = get_xsave_addr(xsave, feature); 3529 3530 if (dest) { 3531 u32 size, offset, ecx, edx; 3532 cpuid_count(XSTATE_CPUID, index, 3533 &size, &offset, &ecx, &edx); 3534 if (feature == XFEATURE_MASK_PKRU) 3535 memcpy(&vcpu->arch.pkru, src + offset, 3536 sizeof(vcpu->arch.pkru)); 3537 else 3538 memcpy(dest, src + offset, size); 3539 } 3540 3541 valid -= feature; 3542 } 3543 } 3544 3545 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3546 struct kvm_xsave *guest_xsave) 3547 { 3548 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3549 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3550 fill_xsave((u8 *) guest_xsave->region, vcpu); 3551 } else { 3552 memcpy(guest_xsave->region, 3553 &vcpu->arch.guest_fpu.state.fxsave, 3554 sizeof(struct fxregs_state)); 3555 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3556 XFEATURE_MASK_FPSSE; 3557 } 3558 } 3559 3560 #define XSAVE_MXCSR_OFFSET 24 3561 3562 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3563 struct kvm_xsave *guest_xsave) 3564 { 3565 u64 xstate_bv = 3566 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3567 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)]; 3568 3569 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 3570 /* 3571 * Here we allow setting states that are not present in 3572 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3573 * with old userspace. 3574 */ 3575 if (xstate_bv & ~kvm_supported_xcr0() || 3576 mxcsr & ~mxcsr_feature_mask) 3577 return -EINVAL; 3578 load_xsave(vcpu, (u8 *)guest_xsave->region); 3579 } else { 3580 if (xstate_bv & ~XFEATURE_MASK_FPSSE || 3581 mxcsr & ~mxcsr_feature_mask) 3582 return -EINVAL; 3583 memcpy(&vcpu->arch.guest_fpu.state.fxsave, 3584 guest_xsave->region, sizeof(struct fxregs_state)); 3585 } 3586 return 0; 3587 } 3588 3589 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3590 struct kvm_xcrs *guest_xcrs) 3591 { 3592 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 3593 guest_xcrs->nr_xcrs = 0; 3594 return; 3595 } 3596 3597 guest_xcrs->nr_xcrs = 1; 3598 guest_xcrs->flags = 0; 3599 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3600 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3601 } 3602 3603 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3604 struct kvm_xcrs *guest_xcrs) 3605 { 3606 int i, r = 0; 3607 3608 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 3609 return -EINVAL; 3610 3611 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3612 return -EINVAL; 3613 3614 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3615 /* Only support XCR0 currently */ 3616 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3617 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3618 guest_xcrs->xcrs[i].value); 3619 break; 3620 } 3621 if (r) 3622 r = -EINVAL; 3623 return r; 3624 } 3625 3626 /* 3627 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3628 * stopped by the hypervisor. This function will be called from the host only. 3629 * EINVAL is returned when the host attempts to set the flag for a guest that 3630 * does not support pv clocks. 3631 */ 3632 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3633 { 3634 if (!vcpu->arch.pv_time_enabled) 3635 return -EINVAL; 3636 vcpu->arch.pvclock_set_guest_stopped_request = true; 3637 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3638 return 0; 3639 } 3640 3641 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 3642 struct kvm_enable_cap *cap) 3643 { 3644 if (cap->flags) 3645 return -EINVAL; 3646 3647 switch (cap->cap) { 3648 case KVM_CAP_HYPERV_SYNIC2: 3649 if (cap->args[0]) 3650 return -EINVAL; 3651 case KVM_CAP_HYPERV_SYNIC: 3652 if (!irqchip_in_kernel(vcpu->kvm)) 3653 return -EINVAL; 3654 return kvm_hv_activate_synic(vcpu, cap->cap == 3655 KVM_CAP_HYPERV_SYNIC2); 3656 default: 3657 return -EINVAL; 3658 } 3659 } 3660 3661 long kvm_arch_vcpu_ioctl(struct file *filp, 3662 unsigned int ioctl, unsigned long arg) 3663 { 3664 struct kvm_vcpu *vcpu = filp->private_data; 3665 void __user *argp = (void __user *)arg; 3666 int r; 3667 union { 3668 struct kvm_lapic_state *lapic; 3669 struct kvm_xsave *xsave; 3670 struct kvm_xcrs *xcrs; 3671 void *buffer; 3672 } u; 3673 3674 vcpu_load(vcpu); 3675 3676 u.buffer = NULL; 3677 switch (ioctl) { 3678 case KVM_GET_LAPIC: { 3679 r = -EINVAL; 3680 if (!lapic_in_kernel(vcpu)) 3681 goto out; 3682 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3683 3684 r = -ENOMEM; 3685 if (!u.lapic) 3686 goto out; 3687 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3688 if (r) 3689 goto out; 3690 r = -EFAULT; 3691 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3692 goto out; 3693 r = 0; 3694 break; 3695 } 3696 case KVM_SET_LAPIC: { 3697 r = -EINVAL; 3698 if (!lapic_in_kernel(vcpu)) 3699 goto out; 3700 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3701 if (IS_ERR(u.lapic)) { 3702 r = PTR_ERR(u.lapic); 3703 goto out_nofree; 3704 } 3705 3706 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3707 break; 3708 } 3709 case KVM_INTERRUPT: { 3710 struct kvm_interrupt irq; 3711 3712 r = -EFAULT; 3713 if (copy_from_user(&irq, argp, sizeof irq)) 3714 goto out; 3715 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3716 break; 3717 } 3718 case KVM_NMI: { 3719 r = kvm_vcpu_ioctl_nmi(vcpu); 3720 break; 3721 } 3722 case KVM_SMI: { 3723 r = kvm_vcpu_ioctl_smi(vcpu); 3724 break; 3725 } 3726 case KVM_SET_CPUID: { 3727 struct kvm_cpuid __user *cpuid_arg = argp; 3728 struct kvm_cpuid cpuid; 3729 3730 r = -EFAULT; 3731 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3732 goto out; 3733 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3734 break; 3735 } 3736 case KVM_SET_CPUID2: { 3737 struct kvm_cpuid2 __user *cpuid_arg = argp; 3738 struct kvm_cpuid2 cpuid; 3739 3740 r = -EFAULT; 3741 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3742 goto out; 3743 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3744 cpuid_arg->entries); 3745 break; 3746 } 3747 case KVM_GET_CPUID2: { 3748 struct kvm_cpuid2 __user *cpuid_arg = argp; 3749 struct kvm_cpuid2 cpuid; 3750 3751 r = -EFAULT; 3752 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3753 goto out; 3754 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3755 cpuid_arg->entries); 3756 if (r) 3757 goto out; 3758 r = -EFAULT; 3759 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3760 goto out; 3761 r = 0; 3762 break; 3763 } 3764 case KVM_GET_MSRS: { 3765 int idx = srcu_read_lock(&vcpu->kvm->srcu); 3766 r = msr_io(vcpu, argp, do_get_msr, 1); 3767 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3768 break; 3769 } 3770 case KVM_SET_MSRS: { 3771 int idx = srcu_read_lock(&vcpu->kvm->srcu); 3772 r = msr_io(vcpu, argp, do_set_msr, 0); 3773 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3774 break; 3775 } 3776 case KVM_TPR_ACCESS_REPORTING: { 3777 struct kvm_tpr_access_ctl tac; 3778 3779 r = -EFAULT; 3780 if (copy_from_user(&tac, argp, sizeof tac)) 3781 goto out; 3782 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3783 if (r) 3784 goto out; 3785 r = -EFAULT; 3786 if (copy_to_user(argp, &tac, sizeof tac)) 3787 goto out; 3788 r = 0; 3789 break; 3790 }; 3791 case KVM_SET_VAPIC_ADDR: { 3792 struct kvm_vapic_addr va; 3793 int idx; 3794 3795 r = -EINVAL; 3796 if (!lapic_in_kernel(vcpu)) 3797 goto out; 3798 r = -EFAULT; 3799 if (copy_from_user(&va, argp, sizeof va)) 3800 goto out; 3801 idx = srcu_read_lock(&vcpu->kvm->srcu); 3802 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3803 srcu_read_unlock(&vcpu->kvm->srcu, idx); 3804 break; 3805 } 3806 case KVM_X86_SETUP_MCE: { 3807 u64 mcg_cap; 3808 3809 r = -EFAULT; 3810 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3811 goto out; 3812 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3813 break; 3814 } 3815 case KVM_X86_SET_MCE: { 3816 struct kvm_x86_mce mce; 3817 3818 r = -EFAULT; 3819 if (copy_from_user(&mce, argp, sizeof mce)) 3820 goto out; 3821 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3822 break; 3823 } 3824 case KVM_GET_VCPU_EVENTS: { 3825 struct kvm_vcpu_events events; 3826 3827 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3828 3829 r = -EFAULT; 3830 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3831 break; 3832 r = 0; 3833 break; 3834 } 3835 case KVM_SET_VCPU_EVENTS: { 3836 struct kvm_vcpu_events events; 3837 3838 r = -EFAULT; 3839 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3840 break; 3841 3842 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3843 break; 3844 } 3845 case KVM_GET_DEBUGREGS: { 3846 struct kvm_debugregs dbgregs; 3847 3848 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3849 3850 r = -EFAULT; 3851 if (copy_to_user(argp, &dbgregs, 3852 sizeof(struct kvm_debugregs))) 3853 break; 3854 r = 0; 3855 break; 3856 } 3857 case KVM_SET_DEBUGREGS: { 3858 struct kvm_debugregs dbgregs; 3859 3860 r = -EFAULT; 3861 if (copy_from_user(&dbgregs, argp, 3862 sizeof(struct kvm_debugregs))) 3863 break; 3864 3865 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3866 break; 3867 } 3868 case KVM_GET_XSAVE: { 3869 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3870 r = -ENOMEM; 3871 if (!u.xsave) 3872 break; 3873 3874 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3875 3876 r = -EFAULT; 3877 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3878 break; 3879 r = 0; 3880 break; 3881 } 3882 case KVM_SET_XSAVE: { 3883 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3884 if (IS_ERR(u.xsave)) { 3885 r = PTR_ERR(u.xsave); 3886 goto out_nofree; 3887 } 3888 3889 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3890 break; 3891 } 3892 case KVM_GET_XCRS: { 3893 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3894 r = -ENOMEM; 3895 if (!u.xcrs) 3896 break; 3897 3898 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3899 3900 r = -EFAULT; 3901 if (copy_to_user(argp, u.xcrs, 3902 sizeof(struct kvm_xcrs))) 3903 break; 3904 r = 0; 3905 break; 3906 } 3907 case KVM_SET_XCRS: { 3908 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3909 if (IS_ERR(u.xcrs)) { 3910 r = PTR_ERR(u.xcrs); 3911 goto out_nofree; 3912 } 3913 3914 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3915 break; 3916 } 3917 case KVM_SET_TSC_KHZ: { 3918 u32 user_tsc_khz; 3919 3920 r = -EINVAL; 3921 user_tsc_khz = (u32)arg; 3922 3923 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3924 goto out; 3925 3926 if (user_tsc_khz == 0) 3927 user_tsc_khz = tsc_khz; 3928 3929 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 3930 r = 0; 3931 3932 goto out; 3933 } 3934 case KVM_GET_TSC_KHZ: { 3935 r = vcpu->arch.virtual_tsc_khz; 3936 goto out; 3937 } 3938 case KVM_KVMCLOCK_CTRL: { 3939 r = kvm_set_guest_paused(vcpu); 3940 goto out; 3941 } 3942 case KVM_ENABLE_CAP: { 3943 struct kvm_enable_cap cap; 3944 3945 r = -EFAULT; 3946 if (copy_from_user(&cap, argp, sizeof(cap))) 3947 goto out; 3948 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 3949 break; 3950 } 3951 default: 3952 r = -EINVAL; 3953 } 3954 out: 3955 kfree(u.buffer); 3956 out_nofree: 3957 vcpu_put(vcpu); 3958 return r; 3959 } 3960 3961 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3962 { 3963 return VM_FAULT_SIGBUS; 3964 } 3965 3966 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3967 { 3968 int ret; 3969 3970 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3971 return -EINVAL; 3972 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3973 return ret; 3974 } 3975 3976 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3977 u64 ident_addr) 3978 { 3979 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr); 3980 } 3981 3982 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3983 u32 kvm_nr_mmu_pages) 3984 { 3985 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3986 return -EINVAL; 3987 3988 mutex_lock(&kvm->slots_lock); 3989 3990 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3991 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3992 3993 mutex_unlock(&kvm->slots_lock); 3994 return 0; 3995 } 3996 3997 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 3998 { 3999 return kvm->arch.n_max_mmu_pages; 4000 } 4001 4002 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 4003 { 4004 struct kvm_pic *pic = kvm->arch.vpic; 4005 int r; 4006 4007 r = 0; 4008 switch (chip->chip_id) { 4009 case KVM_IRQCHIP_PIC_MASTER: 4010 memcpy(&chip->chip.pic, &pic->pics[0], 4011 sizeof(struct kvm_pic_state)); 4012 break; 4013 case KVM_IRQCHIP_PIC_SLAVE: 4014 memcpy(&chip->chip.pic, &pic->pics[1], 4015 sizeof(struct kvm_pic_state)); 4016 break; 4017 case KVM_IRQCHIP_IOAPIC: 4018 kvm_get_ioapic(kvm, &chip->chip.ioapic); 4019 break; 4020 default: 4021 r = -EINVAL; 4022 break; 4023 } 4024 return r; 4025 } 4026 4027 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 4028 { 4029 struct kvm_pic *pic = kvm->arch.vpic; 4030 int r; 4031 4032 r = 0; 4033 switch (chip->chip_id) { 4034 case KVM_IRQCHIP_PIC_MASTER: 4035 spin_lock(&pic->lock); 4036 memcpy(&pic->pics[0], &chip->chip.pic, 4037 sizeof(struct kvm_pic_state)); 4038 spin_unlock(&pic->lock); 4039 break; 4040 case KVM_IRQCHIP_PIC_SLAVE: 4041 spin_lock(&pic->lock); 4042 memcpy(&pic->pics[1], &chip->chip.pic, 4043 sizeof(struct kvm_pic_state)); 4044 spin_unlock(&pic->lock); 4045 break; 4046 case KVM_IRQCHIP_IOAPIC: 4047 kvm_set_ioapic(kvm, &chip->chip.ioapic); 4048 break; 4049 default: 4050 r = -EINVAL; 4051 break; 4052 } 4053 kvm_pic_update_irq(pic); 4054 return r; 4055 } 4056 4057 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 4058 { 4059 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 4060 4061 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 4062 4063 mutex_lock(&kps->lock); 4064 memcpy(ps, &kps->channels, sizeof(*ps)); 4065 mutex_unlock(&kps->lock); 4066 return 0; 4067 } 4068 4069 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 4070 { 4071 int i; 4072 struct kvm_pit *pit = kvm->arch.vpit; 4073 4074 mutex_lock(&pit->pit_state.lock); 4075 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 4076 for (i = 0; i < 3; i++) 4077 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 4078 mutex_unlock(&pit->pit_state.lock); 4079 return 0; 4080 } 4081 4082 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 4083 { 4084 mutex_lock(&kvm->arch.vpit->pit_state.lock); 4085 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 4086 sizeof(ps->channels)); 4087 ps->flags = kvm->arch.vpit->pit_state.flags; 4088 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 4089 memset(&ps->reserved, 0, sizeof(ps->reserved)); 4090 return 0; 4091 } 4092 4093 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 4094 { 4095 int start = 0; 4096 int i; 4097 u32 prev_legacy, cur_legacy; 4098 struct kvm_pit *pit = kvm->arch.vpit; 4099 4100 mutex_lock(&pit->pit_state.lock); 4101 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 4102 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 4103 if (!prev_legacy && cur_legacy) 4104 start = 1; 4105 memcpy(&pit->pit_state.channels, &ps->channels, 4106 sizeof(pit->pit_state.channels)); 4107 pit->pit_state.flags = ps->flags; 4108 for (i = 0; i < 3; i++) 4109 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 4110 start && i == 0); 4111 mutex_unlock(&pit->pit_state.lock); 4112 return 0; 4113 } 4114 4115 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 4116 struct kvm_reinject_control *control) 4117 { 4118 struct kvm_pit *pit = kvm->arch.vpit; 4119 4120 if (!pit) 4121 return -ENXIO; 4122 4123 /* pit->pit_state.lock was overloaded to prevent userspace from getting 4124 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 4125 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 4126 */ 4127 mutex_lock(&pit->pit_state.lock); 4128 kvm_pit_set_reinject(pit, control->pit_reinject); 4129 mutex_unlock(&pit->pit_state.lock); 4130 4131 return 0; 4132 } 4133 4134 /** 4135 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 4136 * @kvm: kvm instance 4137 * @log: slot id and address to which we copy the log 4138 * 4139 * Steps 1-4 below provide general overview of dirty page logging. See 4140 * kvm_get_dirty_log_protect() function description for additional details. 4141 * 4142 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 4143 * always flush the TLB (step 4) even if previous step failed and the dirty 4144 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 4145 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 4146 * writes will be marked dirty for next log read. 4147 * 4148 * 1. Take a snapshot of the bit and clear it if needed. 4149 * 2. Write protect the corresponding page. 4150 * 3. Copy the snapshot to the userspace. 4151 * 4. Flush TLB's if needed. 4152 */ 4153 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 4154 { 4155 bool is_dirty = false; 4156 int r; 4157 4158 mutex_lock(&kvm->slots_lock); 4159 4160 /* 4161 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 4162 */ 4163 if (kvm_x86_ops->flush_log_dirty) 4164 kvm_x86_ops->flush_log_dirty(kvm); 4165 4166 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 4167 4168 /* 4169 * All the TLBs can be flushed out of mmu lock, see the comments in 4170 * kvm_mmu_slot_remove_write_access(). 4171 */ 4172 lockdep_assert_held(&kvm->slots_lock); 4173 if (is_dirty) 4174 kvm_flush_remote_tlbs(kvm); 4175 4176 mutex_unlock(&kvm->slots_lock); 4177 return r; 4178 } 4179 4180 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 4181 bool line_status) 4182 { 4183 if (!irqchip_in_kernel(kvm)) 4184 return -ENXIO; 4185 4186 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 4187 irq_event->irq, irq_event->level, 4188 line_status); 4189 return 0; 4190 } 4191 4192 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 4193 struct kvm_enable_cap *cap) 4194 { 4195 int r; 4196 4197 if (cap->flags) 4198 return -EINVAL; 4199 4200 switch (cap->cap) { 4201 case KVM_CAP_DISABLE_QUIRKS: 4202 kvm->arch.disabled_quirks = cap->args[0]; 4203 r = 0; 4204 break; 4205 case KVM_CAP_SPLIT_IRQCHIP: { 4206 mutex_lock(&kvm->lock); 4207 r = -EINVAL; 4208 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 4209 goto split_irqchip_unlock; 4210 r = -EEXIST; 4211 if (irqchip_in_kernel(kvm)) 4212 goto split_irqchip_unlock; 4213 if (kvm->created_vcpus) 4214 goto split_irqchip_unlock; 4215 r = kvm_setup_empty_irq_routing(kvm); 4216 if (r) 4217 goto split_irqchip_unlock; 4218 /* Pairs with irqchip_in_kernel. */ 4219 smp_wmb(); 4220 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 4221 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 4222 r = 0; 4223 split_irqchip_unlock: 4224 mutex_unlock(&kvm->lock); 4225 break; 4226 } 4227 case KVM_CAP_X2APIC_API: 4228 r = -EINVAL; 4229 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 4230 break; 4231 4232 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 4233 kvm->arch.x2apic_format = true; 4234 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 4235 kvm->arch.x2apic_broadcast_quirk_disabled = true; 4236 4237 r = 0; 4238 break; 4239 case KVM_CAP_X86_DISABLE_EXITS: 4240 r = -EINVAL; 4241 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 4242 break; 4243 4244 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 4245 kvm_can_mwait_in_guest()) 4246 kvm->arch.mwait_in_guest = true; 4247 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HTL) 4248 kvm->arch.hlt_in_guest = true; 4249 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 4250 kvm->arch.pause_in_guest = true; 4251 r = 0; 4252 break; 4253 default: 4254 r = -EINVAL; 4255 break; 4256 } 4257 return r; 4258 } 4259 4260 long kvm_arch_vm_ioctl(struct file *filp, 4261 unsigned int ioctl, unsigned long arg) 4262 { 4263 struct kvm *kvm = filp->private_data; 4264 void __user *argp = (void __user *)arg; 4265 int r = -ENOTTY; 4266 /* 4267 * This union makes it completely explicit to gcc-3.x 4268 * that these two variables' stack usage should be 4269 * combined, not added together. 4270 */ 4271 union { 4272 struct kvm_pit_state ps; 4273 struct kvm_pit_state2 ps2; 4274 struct kvm_pit_config pit_config; 4275 } u; 4276 4277 switch (ioctl) { 4278 case KVM_SET_TSS_ADDR: 4279 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 4280 break; 4281 case KVM_SET_IDENTITY_MAP_ADDR: { 4282 u64 ident_addr; 4283 4284 mutex_lock(&kvm->lock); 4285 r = -EINVAL; 4286 if (kvm->created_vcpus) 4287 goto set_identity_unlock; 4288 r = -EFAULT; 4289 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 4290 goto set_identity_unlock; 4291 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 4292 set_identity_unlock: 4293 mutex_unlock(&kvm->lock); 4294 break; 4295 } 4296 case KVM_SET_NR_MMU_PAGES: 4297 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 4298 break; 4299 case KVM_GET_NR_MMU_PAGES: 4300 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 4301 break; 4302 case KVM_CREATE_IRQCHIP: { 4303 mutex_lock(&kvm->lock); 4304 4305 r = -EEXIST; 4306 if (irqchip_in_kernel(kvm)) 4307 goto create_irqchip_unlock; 4308 4309 r = -EINVAL; 4310 if (kvm->created_vcpus) 4311 goto create_irqchip_unlock; 4312 4313 r = kvm_pic_init(kvm); 4314 if (r) 4315 goto create_irqchip_unlock; 4316 4317 r = kvm_ioapic_init(kvm); 4318 if (r) { 4319 kvm_pic_destroy(kvm); 4320 goto create_irqchip_unlock; 4321 } 4322 4323 r = kvm_setup_default_irq_routing(kvm); 4324 if (r) { 4325 kvm_ioapic_destroy(kvm); 4326 kvm_pic_destroy(kvm); 4327 goto create_irqchip_unlock; 4328 } 4329 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 4330 smp_wmb(); 4331 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 4332 create_irqchip_unlock: 4333 mutex_unlock(&kvm->lock); 4334 break; 4335 } 4336 case KVM_CREATE_PIT: 4337 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 4338 goto create_pit; 4339 case KVM_CREATE_PIT2: 4340 r = -EFAULT; 4341 if (copy_from_user(&u.pit_config, argp, 4342 sizeof(struct kvm_pit_config))) 4343 goto out; 4344 create_pit: 4345 mutex_lock(&kvm->lock); 4346 r = -EEXIST; 4347 if (kvm->arch.vpit) 4348 goto create_pit_unlock; 4349 r = -ENOMEM; 4350 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 4351 if (kvm->arch.vpit) 4352 r = 0; 4353 create_pit_unlock: 4354 mutex_unlock(&kvm->lock); 4355 break; 4356 case KVM_GET_IRQCHIP: { 4357 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4358 struct kvm_irqchip *chip; 4359 4360 chip = memdup_user(argp, sizeof(*chip)); 4361 if (IS_ERR(chip)) { 4362 r = PTR_ERR(chip); 4363 goto out; 4364 } 4365 4366 r = -ENXIO; 4367 if (!irqchip_kernel(kvm)) 4368 goto get_irqchip_out; 4369 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 4370 if (r) 4371 goto get_irqchip_out; 4372 r = -EFAULT; 4373 if (copy_to_user(argp, chip, sizeof *chip)) 4374 goto get_irqchip_out; 4375 r = 0; 4376 get_irqchip_out: 4377 kfree(chip); 4378 break; 4379 } 4380 case KVM_SET_IRQCHIP: { 4381 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 4382 struct kvm_irqchip *chip; 4383 4384 chip = memdup_user(argp, sizeof(*chip)); 4385 if (IS_ERR(chip)) { 4386 r = PTR_ERR(chip); 4387 goto out; 4388 } 4389 4390 r = -ENXIO; 4391 if (!irqchip_kernel(kvm)) 4392 goto set_irqchip_out; 4393 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 4394 if (r) 4395 goto set_irqchip_out; 4396 r = 0; 4397 set_irqchip_out: 4398 kfree(chip); 4399 break; 4400 } 4401 case KVM_GET_PIT: { 4402 r = -EFAULT; 4403 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 4404 goto out; 4405 r = -ENXIO; 4406 if (!kvm->arch.vpit) 4407 goto out; 4408 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 4409 if (r) 4410 goto out; 4411 r = -EFAULT; 4412 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 4413 goto out; 4414 r = 0; 4415 break; 4416 } 4417 case KVM_SET_PIT: { 4418 r = -EFAULT; 4419 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 4420 goto out; 4421 r = -ENXIO; 4422 if (!kvm->arch.vpit) 4423 goto out; 4424 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 4425 break; 4426 } 4427 case KVM_GET_PIT2: { 4428 r = -ENXIO; 4429 if (!kvm->arch.vpit) 4430 goto out; 4431 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 4432 if (r) 4433 goto out; 4434 r = -EFAULT; 4435 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 4436 goto out; 4437 r = 0; 4438 break; 4439 } 4440 case KVM_SET_PIT2: { 4441 r = -EFAULT; 4442 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 4443 goto out; 4444 r = -ENXIO; 4445 if (!kvm->arch.vpit) 4446 goto out; 4447 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 4448 break; 4449 } 4450 case KVM_REINJECT_CONTROL: { 4451 struct kvm_reinject_control control; 4452 r = -EFAULT; 4453 if (copy_from_user(&control, argp, sizeof(control))) 4454 goto out; 4455 r = kvm_vm_ioctl_reinject(kvm, &control); 4456 break; 4457 } 4458 case KVM_SET_BOOT_CPU_ID: 4459 r = 0; 4460 mutex_lock(&kvm->lock); 4461 if (kvm->created_vcpus) 4462 r = -EBUSY; 4463 else 4464 kvm->arch.bsp_vcpu_id = arg; 4465 mutex_unlock(&kvm->lock); 4466 break; 4467 case KVM_XEN_HVM_CONFIG: { 4468 struct kvm_xen_hvm_config xhc; 4469 r = -EFAULT; 4470 if (copy_from_user(&xhc, argp, sizeof(xhc))) 4471 goto out; 4472 r = -EINVAL; 4473 if (xhc.flags) 4474 goto out; 4475 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc)); 4476 r = 0; 4477 break; 4478 } 4479 case KVM_SET_CLOCK: { 4480 struct kvm_clock_data user_ns; 4481 u64 now_ns; 4482 4483 r = -EFAULT; 4484 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 4485 goto out; 4486 4487 r = -EINVAL; 4488 if (user_ns.flags) 4489 goto out; 4490 4491 r = 0; 4492 /* 4493 * TODO: userspace has to take care of races with VCPU_RUN, so 4494 * kvm_gen_update_masterclock() can be cut down to locked 4495 * pvclock_update_vm_gtod_copy(). 4496 */ 4497 kvm_gen_update_masterclock(kvm); 4498 now_ns = get_kvmclock_ns(kvm); 4499 kvm->arch.kvmclock_offset += user_ns.clock - now_ns; 4500 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE); 4501 break; 4502 } 4503 case KVM_GET_CLOCK: { 4504 struct kvm_clock_data user_ns; 4505 u64 now_ns; 4506 4507 now_ns = get_kvmclock_ns(kvm); 4508 user_ns.clock = now_ns; 4509 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0; 4510 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 4511 4512 r = -EFAULT; 4513 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 4514 goto out; 4515 r = 0; 4516 break; 4517 } 4518 case KVM_ENABLE_CAP: { 4519 struct kvm_enable_cap cap; 4520 4521 r = -EFAULT; 4522 if (copy_from_user(&cap, argp, sizeof(cap))) 4523 goto out; 4524 r = kvm_vm_ioctl_enable_cap(kvm, &cap); 4525 break; 4526 } 4527 case KVM_MEMORY_ENCRYPT_OP: { 4528 r = -ENOTTY; 4529 if (kvm_x86_ops->mem_enc_op) 4530 r = kvm_x86_ops->mem_enc_op(kvm, argp); 4531 break; 4532 } 4533 case KVM_MEMORY_ENCRYPT_REG_REGION: { 4534 struct kvm_enc_region region; 4535 4536 r = -EFAULT; 4537 if (copy_from_user(®ion, argp, sizeof(region))) 4538 goto out; 4539 4540 r = -ENOTTY; 4541 if (kvm_x86_ops->mem_enc_reg_region) 4542 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion); 4543 break; 4544 } 4545 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 4546 struct kvm_enc_region region; 4547 4548 r = -EFAULT; 4549 if (copy_from_user(®ion, argp, sizeof(region))) 4550 goto out; 4551 4552 r = -ENOTTY; 4553 if (kvm_x86_ops->mem_enc_unreg_region) 4554 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion); 4555 break; 4556 } 4557 case KVM_HYPERV_EVENTFD: { 4558 struct kvm_hyperv_eventfd hvevfd; 4559 4560 r = -EFAULT; 4561 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 4562 goto out; 4563 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 4564 break; 4565 } 4566 default: 4567 r = -ENOTTY; 4568 } 4569 out: 4570 return r; 4571 } 4572 4573 static void kvm_init_msr_list(void) 4574 { 4575 u32 dummy[2]; 4576 unsigned i, j; 4577 4578 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { 4579 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4580 continue; 4581 4582 /* 4583 * Even MSRs that are valid in the host may not be exposed 4584 * to the guests in some cases. 4585 */ 4586 switch (msrs_to_save[i]) { 4587 case MSR_IA32_BNDCFGS: 4588 if (!kvm_x86_ops->mpx_supported()) 4589 continue; 4590 break; 4591 case MSR_TSC_AUX: 4592 if (!kvm_x86_ops->rdtscp_supported()) 4593 continue; 4594 break; 4595 default: 4596 break; 4597 } 4598 4599 if (j < i) 4600 msrs_to_save[j] = msrs_to_save[i]; 4601 j++; 4602 } 4603 num_msrs_to_save = j; 4604 4605 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { 4606 switch (emulated_msrs[i]) { 4607 case MSR_IA32_SMBASE: 4608 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase()) 4609 continue; 4610 break; 4611 default: 4612 break; 4613 } 4614 4615 if (j < i) 4616 emulated_msrs[j] = emulated_msrs[i]; 4617 j++; 4618 } 4619 num_emulated_msrs = j; 4620 4621 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) { 4622 struct kvm_msr_entry msr; 4623 4624 msr.index = msr_based_features[i]; 4625 if (kvm_get_msr_feature(&msr)) 4626 continue; 4627 4628 if (j < i) 4629 msr_based_features[j] = msr_based_features[i]; 4630 j++; 4631 } 4632 num_msr_based_features = j; 4633 } 4634 4635 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 4636 const void *v) 4637 { 4638 int handled = 0; 4639 int n; 4640 4641 do { 4642 n = min(len, 8); 4643 if (!(lapic_in_kernel(vcpu) && 4644 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 4645 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 4646 break; 4647 handled += n; 4648 addr += n; 4649 len -= n; 4650 v += n; 4651 } while (len); 4652 4653 return handled; 4654 } 4655 4656 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4657 { 4658 int handled = 0; 4659 int n; 4660 4661 do { 4662 n = min(len, 8); 4663 if (!(lapic_in_kernel(vcpu) && 4664 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 4665 addr, n, v)) 4666 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 4667 break; 4668 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 4669 handled += n; 4670 addr += n; 4671 len -= n; 4672 v += n; 4673 } while (len); 4674 4675 return handled; 4676 } 4677 4678 static void kvm_set_segment(struct kvm_vcpu *vcpu, 4679 struct kvm_segment *var, int seg) 4680 { 4681 kvm_x86_ops->set_segment(vcpu, var, seg); 4682 } 4683 4684 void kvm_get_segment(struct kvm_vcpu *vcpu, 4685 struct kvm_segment *var, int seg) 4686 { 4687 kvm_x86_ops->get_segment(vcpu, var, seg); 4688 } 4689 4690 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 4691 struct x86_exception *exception) 4692 { 4693 gpa_t t_gpa; 4694 4695 BUG_ON(!mmu_is_nested(vcpu)); 4696 4697 /* NPT walks are always user-walks */ 4698 access |= PFERR_USER_MASK; 4699 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); 4700 4701 return t_gpa; 4702 } 4703 4704 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 4705 struct x86_exception *exception) 4706 { 4707 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4708 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4709 } 4710 4711 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 4712 struct x86_exception *exception) 4713 { 4714 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4715 access |= PFERR_FETCH_MASK; 4716 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4717 } 4718 4719 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 4720 struct x86_exception *exception) 4721 { 4722 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4723 access |= PFERR_WRITE_MASK; 4724 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4725 } 4726 4727 /* uses this to access any guest's mapped memory without checking CPL */ 4728 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 4729 struct x86_exception *exception) 4730 { 4731 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 4732 } 4733 4734 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 4735 struct kvm_vcpu *vcpu, u32 access, 4736 struct x86_exception *exception) 4737 { 4738 void *data = val; 4739 int r = X86EMUL_CONTINUE; 4740 4741 while (bytes) { 4742 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 4743 exception); 4744 unsigned offset = addr & (PAGE_SIZE-1); 4745 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 4746 int ret; 4747 4748 if (gpa == UNMAPPED_GVA) 4749 return X86EMUL_PROPAGATE_FAULT; 4750 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 4751 offset, toread); 4752 if (ret < 0) { 4753 r = X86EMUL_IO_NEEDED; 4754 goto out; 4755 } 4756 4757 bytes -= toread; 4758 data += toread; 4759 addr += toread; 4760 } 4761 out: 4762 return r; 4763 } 4764 4765 /* used for instruction fetching */ 4766 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4767 gva_t addr, void *val, unsigned int bytes, 4768 struct x86_exception *exception) 4769 { 4770 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4771 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4772 unsigned offset; 4773 int ret; 4774 4775 /* Inline kvm_read_guest_virt_helper for speed. */ 4776 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 4777 exception); 4778 if (unlikely(gpa == UNMAPPED_GVA)) 4779 return X86EMUL_PROPAGATE_FAULT; 4780 4781 offset = addr & (PAGE_SIZE-1); 4782 if (WARN_ON(offset + bytes > PAGE_SIZE)) 4783 bytes = (unsigned)PAGE_SIZE - offset; 4784 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 4785 offset, bytes); 4786 if (unlikely(ret < 0)) 4787 return X86EMUL_IO_NEEDED; 4788 4789 return X86EMUL_CONTINUE; 4790 } 4791 4792 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4793 gva_t addr, void *val, unsigned int bytes, 4794 struct x86_exception *exception) 4795 { 4796 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4797 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4798 4799 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4800 exception); 4801 } 4802 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4803 4804 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4805 gva_t addr, void *val, unsigned int bytes, 4806 struct x86_exception *exception) 4807 { 4808 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4809 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4810 } 4811 4812 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 4813 unsigned long addr, void *val, unsigned int bytes) 4814 { 4815 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4816 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 4817 4818 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 4819 } 4820 4821 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4822 gva_t addr, void *val, 4823 unsigned int bytes, 4824 struct x86_exception *exception) 4825 { 4826 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4827 void *data = val; 4828 int r = X86EMUL_CONTINUE; 4829 4830 while (bytes) { 4831 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4832 PFERR_WRITE_MASK, 4833 exception); 4834 unsigned offset = addr & (PAGE_SIZE-1); 4835 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4836 int ret; 4837 4838 if (gpa == UNMAPPED_GVA) 4839 return X86EMUL_PROPAGATE_FAULT; 4840 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 4841 if (ret < 0) { 4842 r = X86EMUL_IO_NEEDED; 4843 goto out; 4844 } 4845 4846 bytes -= towrite; 4847 data += towrite; 4848 addr += towrite; 4849 } 4850 out: 4851 return r; 4852 } 4853 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4854 4855 int handle_ud(struct kvm_vcpu *vcpu) 4856 { 4857 int emul_type = EMULTYPE_TRAP_UD; 4858 enum emulation_result er; 4859 char sig[5]; /* ud2; .ascii "kvm" */ 4860 struct x86_exception e; 4861 4862 if (force_emulation_prefix && 4863 kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, 4864 kvm_get_linear_rip(vcpu), sig, sizeof(sig), &e) == 0 && 4865 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) { 4866 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 4867 emul_type = 0; 4868 } 4869 4870 er = emulate_instruction(vcpu, emul_type); 4871 if (er == EMULATE_USER_EXIT) 4872 return 0; 4873 if (er != EMULATE_DONE) 4874 kvm_queue_exception(vcpu, UD_VECTOR); 4875 return 1; 4876 } 4877 EXPORT_SYMBOL_GPL(handle_ud); 4878 4879 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4880 gpa_t gpa, bool write) 4881 { 4882 /* For APIC access vmexit */ 4883 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4884 return 1; 4885 4886 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 4887 trace_vcpu_match_mmio(gva, gpa, write, true); 4888 return 1; 4889 } 4890 4891 return 0; 4892 } 4893 4894 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4895 gpa_t *gpa, struct x86_exception *exception, 4896 bool write) 4897 { 4898 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4899 | (write ? PFERR_WRITE_MASK : 0); 4900 4901 /* 4902 * currently PKRU is only applied to ept enabled guest so 4903 * there is no pkey in EPT page table for L1 guest or EPT 4904 * shadow page table for L2 guest. 4905 */ 4906 if (vcpu_match_mmio_gva(vcpu, gva) 4907 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4908 vcpu->arch.access, 0, access)) { 4909 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4910 (gva & (PAGE_SIZE - 1)); 4911 trace_vcpu_match_mmio(gva, *gpa, write, false); 4912 return 1; 4913 } 4914 4915 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4916 4917 if (*gpa == UNMAPPED_GVA) 4918 return -1; 4919 4920 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 4921 } 4922 4923 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4924 const void *val, int bytes) 4925 { 4926 int ret; 4927 4928 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 4929 if (ret < 0) 4930 return 0; 4931 kvm_page_track_write(vcpu, gpa, val, bytes); 4932 return 1; 4933 } 4934 4935 struct read_write_emulator_ops { 4936 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4937 int bytes); 4938 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4939 void *val, int bytes); 4940 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4941 int bytes, void *val); 4942 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4943 void *val, int bytes); 4944 bool write; 4945 }; 4946 4947 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4948 { 4949 if (vcpu->mmio_read_completed) { 4950 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4951 vcpu->mmio_fragments[0].gpa, val); 4952 vcpu->mmio_read_completed = 0; 4953 return 1; 4954 } 4955 4956 return 0; 4957 } 4958 4959 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4960 void *val, int bytes) 4961 { 4962 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 4963 } 4964 4965 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4966 void *val, int bytes) 4967 { 4968 return emulator_write_phys(vcpu, gpa, val, bytes); 4969 } 4970 4971 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4972 { 4973 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 4974 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4975 } 4976 4977 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4978 void *val, int bytes) 4979 { 4980 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 4981 return X86EMUL_IO_NEEDED; 4982 } 4983 4984 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4985 void *val, int bytes) 4986 { 4987 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4988 4989 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4990 return X86EMUL_CONTINUE; 4991 } 4992 4993 static const struct read_write_emulator_ops read_emultor = { 4994 .read_write_prepare = read_prepare, 4995 .read_write_emulate = read_emulate, 4996 .read_write_mmio = vcpu_mmio_read, 4997 .read_write_exit_mmio = read_exit_mmio, 4998 }; 4999 5000 static const struct read_write_emulator_ops write_emultor = { 5001 .read_write_emulate = write_emulate, 5002 .read_write_mmio = write_mmio, 5003 .read_write_exit_mmio = write_exit_mmio, 5004 .write = true, 5005 }; 5006 5007 static int emulator_read_write_onepage(unsigned long addr, void *val, 5008 unsigned int bytes, 5009 struct x86_exception *exception, 5010 struct kvm_vcpu *vcpu, 5011 const struct read_write_emulator_ops *ops) 5012 { 5013 gpa_t gpa; 5014 int handled, ret; 5015 bool write = ops->write; 5016 struct kvm_mmio_fragment *frag; 5017 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5018 5019 /* 5020 * If the exit was due to a NPF we may already have a GPA. 5021 * If the GPA is present, use it to avoid the GVA to GPA table walk. 5022 * Note, this cannot be used on string operations since string 5023 * operation using rep will only have the initial GPA from the NPF 5024 * occurred. 5025 */ 5026 if (vcpu->arch.gpa_available && 5027 emulator_can_use_gpa(ctxt) && 5028 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) { 5029 gpa = vcpu->arch.gpa_val; 5030 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 5031 } else { 5032 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 5033 if (ret < 0) 5034 return X86EMUL_PROPAGATE_FAULT; 5035 } 5036 5037 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 5038 return X86EMUL_CONTINUE; 5039 5040 /* 5041 * Is this MMIO handled locally? 5042 */ 5043 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 5044 if (handled == bytes) 5045 return X86EMUL_CONTINUE; 5046 5047 gpa += handled; 5048 bytes -= handled; 5049 val += handled; 5050 5051 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 5052 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 5053 frag->gpa = gpa; 5054 frag->data = val; 5055 frag->len = bytes; 5056 return X86EMUL_CONTINUE; 5057 } 5058 5059 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 5060 unsigned long addr, 5061 void *val, unsigned int bytes, 5062 struct x86_exception *exception, 5063 const struct read_write_emulator_ops *ops) 5064 { 5065 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5066 gpa_t gpa; 5067 int rc; 5068 5069 if (ops->read_write_prepare && 5070 ops->read_write_prepare(vcpu, val, bytes)) 5071 return X86EMUL_CONTINUE; 5072 5073 vcpu->mmio_nr_fragments = 0; 5074 5075 /* Crossing a page boundary? */ 5076 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 5077 int now; 5078 5079 now = -addr & ~PAGE_MASK; 5080 rc = emulator_read_write_onepage(addr, val, now, exception, 5081 vcpu, ops); 5082 5083 if (rc != X86EMUL_CONTINUE) 5084 return rc; 5085 addr += now; 5086 if (ctxt->mode != X86EMUL_MODE_PROT64) 5087 addr = (u32)addr; 5088 val += now; 5089 bytes -= now; 5090 } 5091 5092 rc = emulator_read_write_onepage(addr, val, bytes, exception, 5093 vcpu, ops); 5094 if (rc != X86EMUL_CONTINUE) 5095 return rc; 5096 5097 if (!vcpu->mmio_nr_fragments) 5098 return rc; 5099 5100 gpa = vcpu->mmio_fragments[0].gpa; 5101 5102 vcpu->mmio_needed = 1; 5103 vcpu->mmio_cur_fragment = 0; 5104 5105 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 5106 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 5107 vcpu->run->exit_reason = KVM_EXIT_MMIO; 5108 vcpu->run->mmio.phys_addr = gpa; 5109 5110 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 5111 } 5112 5113 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 5114 unsigned long addr, 5115 void *val, 5116 unsigned int bytes, 5117 struct x86_exception *exception) 5118 { 5119 return emulator_read_write(ctxt, addr, val, bytes, 5120 exception, &read_emultor); 5121 } 5122 5123 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 5124 unsigned long addr, 5125 const void *val, 5126 unsigned int bytes, 5127 struct x86_exception *exception) 5128 { 5129 return emulator_read_write(ctxt, addr, (void *)val, bytes, 5130 exception, &write_emultor); 5131 } 5132 5133 #define CMPXCHG_TYPE(t, ptr, old, new) \ 5134 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 5135 5136 #ifdef CONFIG_X86_64 5137 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 5138 #else 5139 # define CMPXCHG64(ptr, old, new) \ 5140 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 5141 #endif 5142 5143 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 5144 unsigned long addr, 5145 const void *old, 5146 const void *new, 5147 unsigned int bytes, 5148 struct x86_exception *exception) 5149 { 5150 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5151 gpa_t gpa; 5152 struct page *page; 5153 char *kaddr; 5154 bool exchanged; 5155 5156 /* guests cmpxchg8b have to be emulated atomically */ 5157 if (bytes > 8 || (bytes & (bytes - 1))) 5158 goto emul_write; 5159 5160 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 5161 5162 if (gpa == UNMAPPED_GVA || 5163 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 5164 goto emul_write; 5165 5166 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 5167 goto emul_write; 5168 5169 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); 5170 if (is_error_page(page)) 5171 goto emul_write; 5172 5173 kaddr = kmap_atomic(page); 5174 kaddr += offset_in_page(gpa); 5175 switch (bytes) { 5176 case 1: 5177 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 5178 break; 5179 case 2: 5180 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 5181 break; 5182 case 4: 5183 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 5184 break; 5185 case 8: 5186 exchanged = CMPXCHG64(kaddr, old, new); 5187 break; 5188 default: 5189 BUG(); 5190 } 5191 kunmap_atomic(kaddr); 5192 kvm_release_page_dirty(page); 5193 5194 if (!exchanged) 5195 return X86EMUL_CMPXCHG_FAILED; 5196 5197 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5198 kvm_page_track_write(vcpu, gpa, new, bytes); 5199 5200 return X86EMUL_CONTINUE; 5201 5202 emul_write: 5203 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 5204 5205 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 5206 } 5207 5208 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 5209 { 5210 int r = 0, i; 5211 5212 for (i = 0; i < vcpu->arch.pio.count; i++) { 5213 if (vcpu->arch.pio.in) 5214 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 5215 vcpu->arch.pio.size, pd); 5216 else 5217 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 5218 vcpu->arch.pio.port, vcpu->arch.pio.size, 5219 pd); 5220 if (r) 5221 break; 5222 pd += vcpu->arch.pio.size; 5223 } 5224 return r; 5225 } 5226 5227 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 5228 unsigned short port, void *val, 5229 unsigned int count, bool in) 5230 { 5231 vcpu->arch.pio.port = port; 5232 vcpu->arch.pio.in = in; 5233 vcpu->arch.pio.count = count; 5234 vcpu->arch.pio.size = size; 5235 5236 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 5237 vcpu->arch.pio.count = 0; 5238 return 1; 5239 } 5240 5241 vcpu->run->exit_reason = KVM_EXIT_IO; 5242 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 5243 vcpu->run->io.size = size; 5244 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 5245 vcpu->run->io.count = count; 5246 vcpu->run->io.port = port; 5247 5248 return 0; 5249 } 5250 5251 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 5252 int size, unsigned short port, void *val, 5253 unsigned int count) 5254 { 5255 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5256 int ret; 5257 5258 if (vcpu->arch.pio.count) 5259 goto data_avail; 5260 5261 memset(vcpu->arch.pio_data, 0, size * count); 5262 5263 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 5264 if (ret) { 5265 data_avail: 5266 memcpy(val, vcpu->arch.pio_data, size * count); 5267 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 5268 vcpu->arch.pio.count = 0; 5269 return 1; 5270 } 5271 5272 return 0; 5273 } 5274 5275 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 5276 int size, unsigned short port, 5277 const void *val, unsigned int count) 5278 { 5279 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5280 5281 memcpy(vcpu->arch.pio_data, val, size * count); 5282 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 5283 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 5284 } 5285 5286 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 5287 { 5288 return kvm_x86_ops->get_segment_base(vcpu, seg); 5289 } 5290 5291 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 5292 { 5293 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 5294 } 5295 5296 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 5297 { 5298 if (!need_emulate_wbinvd(vcpu)) 5299 return X86EMUL_CONTINUE; 5300 5301 if (kvm_x86_ops->has_wbinvd_exit()) { 5302 int cpu = get_cpu(); 5303 5304 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 5305 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 5306 wbinvd_ipi, NULL, 1); 5307 put_cpu(); 5308 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 5309 } else 5310 wbinvd(); 5311 return X86EMUL_CONTINUE; 5312 } 5313 5314 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 5315 { 5316 kvm_emulate_wbinvd_noskip(vcpu); 5317 return kvm_skip_emulated_instruction(vcpu); 5318 } 5319 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 5320 5321 5322 5323 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 5324 { 5325 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 5326 } 5327 5328 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 5329 unsigned long *dest) 5330 { 5331 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 5332 } 5333 5334 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 5335 unsigned long value) 5336 { 5337 5338 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 5339 } 5340 5341 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 5342 { 5343 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 5344 } 5345 5346 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 5347 { 5348 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5349 unsigned long value; 5350 5351 switch (cr) { 5352 case 0: 5353 value = kvm_read_cr0(vcpu); 5354 break; 5355 case 2: 5356 value = vcpu->arch.cr2; 5357 break; 5358 case 3: 5359 value = kvm_read_cr3(vcpu); 5360 break; 5361 case 4: 5362 value = kvm_read_cr4(vcpu); 5363 break; 5364 case 8: 5365 value = kvm_get_cr8(vcpu); 5366 break; 5367 default: 5368 kvm_err("%s: unexpected cr %u\n", __func__, cr); 5369 return 0; 5370 } 5371 5372 return value; 5373 } 5374 5375 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 5376 { 5377 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5378 int res = 0; 5379 5380 switch (cr) { 5381 case 0: 5382 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 5383 break; 5384 case 2: 5385 vcpu->arch.cr2 = val; 5386 break; 5387 case 3: 5388 res = kvm_set_cr3(vcpu, val); 5389 break; 5390 case 4: 5391 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 5392 break; 5393 case 8: 5394 res = kvm_set_cr8(vcpu, val); 5395 break; 5396 default: 5397 kvm_err("%s: unexpected cr %u\n", __func__, cr); 5398 res = -1; 5399 } 5400 5401 return res; 5402 } 5403 5404 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 5405 { 5406 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 5407 } 5408 5409 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5410 { 5411 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 5412 } 5413 5414 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5415 { 5416 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 5417 } 5418 5419 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5420 { 5421 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 5422 } 5423 5424 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 5425 { 5426 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 5427 } 5428 5429 static unsigned long emulator_get_cached_segment_base( 5430 struct x86_emulate_ctxt *ctxt, int seg) 5431 { 5432 return get_segment_base(emul_to_vcpu(ctxt), seg); 5433 } 5434 5435 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 5436 struct desc_struct *desc, u32 *base3, 5437 int seg) 5438 { 5439 struct kvm_segment var; 5440 5441 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 5442 *selector = var.selector; 5443 5444 if (var.unusable) { 5445 memset(desc, 0, sizeof(*desc)); 5446 if (base3) 5447 *base3 = 0; 5448 return false; 5449 } 5450 5451 if (var.g) 5452 var.limit >>= 12; 5453 set_desc_limit(desc, var.limit); 5454 set_desc_base(desc, (unsigned long)var.base); 5455 #ifdef CONFIG_X86_64 5456 if (base3) 5457 *base3 = var.base >> 32; 5458 #endif 5459 desc->type = var.type; 5460 desc->s = var.s; 5461 desc->dpl = var.dpl; 5462 desc->p = var.present; 5463 desc->avl = var.avl; 5464 desc->l = var.l; 5465 desc->d = var.db; 5466 desc->g = var.g; 5467 5468 return true; 5469 } 5470 5471 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 5472 struct desc_struct *desc, u32 base3, 5473 int seg) 5474 { 5475 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5476 struct kvm_segment var; 5477 5478 var.selector = selector; 5479 var.base = get_desc_base(desc); 5480 #ifdef CONFIG_X86_64 5481 var.base |= ((u64)base3) << 32; 5482 #endif 5483 var.limit = get_desc_limit(desc); 5484 if (desc->g) 5485 var.limit = (var.limit << 12) | 0xfff; 5486 var.type = desc->type; 5487 var.dpl = desc->dpl; 5488 var.db = desc->d; 5489 var.s = desc->s; 5490 var.l = desc->l; 5491 var.g = desc->g; 5492 var.avl = desc->avl; 5493 var.present = desc->p; 5494 var.unusable = !var.present; 5495 var.padding = 0; 5496 5497 kvm_set_segment(vcpu, &var, seg); 5498 return; 5499 } 5500 5501 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 5502 u32 msr_index, u64 *pdata) 5503 { 5504 struct msr_data msr; 5505 int r; 5506 5507 msr.index = msr_index; 5508 msr.host_initiated = false; 5509 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); 5510 if (r) 5511 return r; 5512 5513 *pdata = msr.data; 5514 return 0; 5515 } 5516 5517 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 5518 u32 msr_index, u64 data) 5519 { 5520 struct msr_data msr; 5521 5522 msr.data = data; 5523 msr.index = msr_index; 5524 msr.host_initiated = false; 5525 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 5526 } 5527 5528 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 5529 { 5530 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5531 5532 return vcpu->arch.smbase; 5533 } 5534 5535 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 5536 { 5537 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5538 5539 vcpu->arch.smbase = smbase; 5540 } 5541 5542 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 5543 u32 pmc) 5544 { 5545 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); 5546 } 5547 5548 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 5549 u32 pmc, u64 *pdata) 5550 { 5551 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 5552 } 5553 5554 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 5555 { 5556 emul_to_vcpu(ctxt)->arch.halt_request = 1; 5557 } 5558 5559 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 5560 struct x86_instruction_info *info, 5561 enum x86_intercept_stage stage) 5562 { 5563 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 5564 } 5565 5566 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 5567 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit) 5568 { 5569 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit); 5570 } 5571 5572 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 5573 { 5574 return kvm_register_read(emul_to_vcpu(ctxt), reg); 5575 } 5576 5577 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 5578 { 5579 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 5580 } 5581 5582 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 5583 { 5584 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 5585 } 5586 5587 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) 5588 { 5589 return emul_to_vcpu(ctxt)->arch.hflags; 5590 } 5591 5592 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags) 5593 { 5594 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags); 5595 } 5596 5597 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase) 5598 { 5599 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase); 5600 } 5601 5602 static const struct x86_emulate_ops emulate_ops = { 5603 .read_gpr = emulator_read_gpr, 5604 .write_gpr = emulator_write_gpr, 5605 .read_std = kvm_read_guest_virt_system, 5606 .write_std = kvm_write_guest_virt_system, 5607 .read_phys = kvm_read_guest_phys_system, 5608 .fetch = kvm_fetch_guest_virt, 5609 .read_emulated = emulator_read_emulated, 5610 .write_emulated = emulator_write_emulated, 5611 .cmpxchg_emulated = emulator_cmpxchg_emulated, 5612 .invlpg = emulator_invlpg, 5613 .pio_in_emulated = emulator_pio_in_emulated, 5614 .pio_out_emulated = emulator_pio_out_emulated, 5615 .get_segment = emulator_get_segment, 5616 .set_segment = emulator_set_segment, 5617 .get_cached_segment_base = emulator_get_cached_segment_base, 5618 .get_gdt = emulator_get_gdt, 5619 .get_idt = emulator_get_idt, 5620 .set_gdt = emulator_set_gdt, 5621 .set_idt = emulator_set_idt, 5622 .get_cr = emulator_get_cr, 5623 .set_cr = emulator_set_cr, 5624 .cpl = emulator_get_cpl, 5625 .get_dr = emulator_get_dr, 5626 .set_dr = emulator_set_dr, 5627 .get_smbase = emulator_get_smbase, 5628 .set_smbase = emulator_set_smbase, 5629 .set_msr = emulator_set_msr, 5630 .get_msr = emulator_get_msr, 5631 .check_pmc = emulator_check_pmc, 5632 .read_pmc = emulator_read_pmc, 5633 .halt = emulator_halt, 5634 .wbinvd = emulator_wbinvd, 5635 .fix_hypercall = emulator_fix_hypercall, 5636 .intercept = emulator_intercept, 5637 .get_cpuid = emulator_get_cpuid, 5638 .set_nmi_mask = emulator_set_nmi_mask, 5639 .get_hflags = emulator_get_hflags, 5640 .set_hflags = emulator_set_hflags, 5641 .pre_leave_smm = emulator_pre_leave_smm, 5642 }; 5643 5644 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 5645 { 5646 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 5647 /* 5648 * an sti; sti; sequence only disable interrupts for the first 5649 * instruction. So, if the last instruction, be it emulated or 5650 * not, left the system with the INT_STI flag enabled, it 5651 * means that the last instruction is an sti. We should not 5652 * leave the flag on in this case. The same goes for mov ss 5653 */ 5654 if (int_shadow & mask) 5655 mask = 0; 5656 if (unlikely(int_shadow || mask)) { 5657 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 5658 if (!mask) 5659 kvm_make_request(KVM_REQ_EVENT, vcpu); 5660 } 5661 } 5662 5663 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 5664 { 5665 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5666 if (ctxt->exception.vector == PF_VECTOR) 5667 return kvm_propagate_fault(vcpu, &ctxt->exception); 5668 5669 if (ctxt->exception.error_code_valid) 5670 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 5671 ctxt->exception.error_code); 5672 else 5673 kvm_queue_exception(vcpu, ctxt->exception.vector); 5674 return false; 5675 } 5676 5677 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 5678 { 5679 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5680 int cs_db, cs_l; 5681 5682 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 5683 5684 ctxt->eflags = kvm_get_rflags(vcpu); 5685 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 5686 5687 ctxt->eip = kvm_rip_read(vcpu); 5688 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 5689 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 5690 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 5691 cs_db ? X86EMUL_MODE_PROT32 : 5692 X86EMUL_MODE_PROT16; 5693 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 5694 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 5695 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 5696 5697 init_decode_cache(ctxt); 5698 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5699 } 5700 5701 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 5702 { 5703 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5704 int ret; 5705 5706 init_emulate_ctxt(vcpu); 5707 5708 ctxt->op_bytes = 2; 5709 ctxt->ad_bytes = 2; 5710 ctxt->_eip = ctxt->eip + inc_eip; 5711 ret = emulate_int_real(ctxt, irq); 5712 5713 if (ret != X86EMUL_CONTINUE) 5714 return EMULATE_FAIL; 5715 5716 ctxt->eip = ctxt->_eip; 5717 kvm_rip_write(vcpu, ctxt->eip); 5718 kvm_set_rflags(vcpu, ctxt->eflags); 5719 5720 return EMULATE_DONE; 5721 } 5722 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 5723 5724 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 5725 { 5726 int r = EMULATE_DONE; 5727 5728 ++vcpu->stat.insn_emulation_fail; 5729 trace_kvm_emulate_insn_failed(vcpu); 5730 5731 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL) 5732 return EMULATE_FAIL; 5733 5734 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 5735 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5736 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 5737 vcpu->run->internal.ndata = 0; 5738 r = EMULATE_USER_EXIT; 5739 } 5740 5741 kvm_queue_exception(vcpu, UD_VECTOR); 5742 5743 return r; 5744 } 5745 5746 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 5747 bool write_fault_to_shadow_pgtable, 5748 int emulation_type) 5749 { 5750 gpa_t gpa = cr2; 5751 kvm_pfn_t pfn; 5752 5753 if (emulation_type & EMULTYPE_NO_REEXECUTE) 5754 return false; 5755 5756 if (!vcpu->arch.mmu.direct_map) { 5757 /* 5758 * Write permission should be allowed since only 5759 * write access need to be emulated. 5760 */ 5761 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5762 5763 /* 5764 * If the mapping is invalid in guest, let cpu retry 5765 * it to generate fault. 5766 */ 5767 if (gpa == UNMAPPED_GVA) 5768 return true; 5769 } 5770 5771 /* 5772 * Do not retry the unhandleable instruction if it faults on the 5773 * readonly host memory, otherwise it will goto a infinite loop: 5774 * retry instruction -> write #PF -> emulation fail -> retry 5775 * instruction -> ... 5776 */ 5777 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 5778 5779 /* 5780 * If the instruction failed on the error pfn, it can not be fixed, 5781 * report the error to userspace. 5782 */ 5783 if (is_error_noslot_pfn(pfn)) 5784 return false; 5785 5786 kvm_release_pfn_clean(pfn); 5787 5788 /* The instructions are well-emulated on direct mmu. */ 5789 if (vcpu->arch.mmu.direct_map) { 5790 unsigned int indirect_shadow_pages; 5791 5792 spin_lock(&vcpu->kvm->mmu_lock); 5793 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 5794 spin_unlock(&vcpu->kvm->mmu_lock); 5795 5796 if (indirect_shadow_pages) 5797 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5798 5799 return true; 5800 } 5801 5802 /* 5803 * if emulation was due to access to shadowed page table 5804 * and it failed try to unshadow page and re-enter the 5805 * guest to let CPU execute the instruction. 5806 */ 5807 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5808 5809 /* 5810 * If the access faults on its page table, it can not 5811 * be fixed by unprotecting shadow page and it should 5812 * be reported to userspace. 5813 */ 5814 return !write_fault_to_shadow_pgtable; 5815 } 5816 5817 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5818 unsigned long cr2, int emulation_type) 5819 { 5820 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5821 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5822 5823 last_retry_eip = vcpu->arch.last_retry_eip; 5824 last_retry_addr = vcpu->arch.last_retry_addr; 5825 5826 /* 5827 * If the emulation is caused by #PF and it is non-page_table 5828 * writing instruction, it means the VM-EXIT is caused by shadow 5829 * page protected, we can zap the shadow page and retry this 5830 * instruction directly. 5831 * 5832 * Note: if the guest uses a non-page-table modifying instruction 5833 * on the PDE that points to the instruction, then we will unmap 5834 * the instruction and go to an infinite loop. So, we cache the 5835 * last retried eip and the last fault address, if we meet the eip 5836 * and the address again, we can break out of the potential infinite 5837 * loop. 5838 */ 5839 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5840 5841 if (!(emulation_type & EMULTYPE_RETRY)) 5842 return false; 5843 5844 if (x86_page_table_writing_insn(ctxt)) 5845 return false; 5846 5847 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5848 return false; 5849 5850 vcpu->arch.last_retry_eip = ctxt->eip; 5851 vcpu->arch.last_retry_addr = cr2; 5852 5853 if (!vcpu->arch.mmu.direct_map) 5854 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5855 5856 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5857 5858 return true; 5859 } 5860 5861 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5862 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5863 5864 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 5865 { 5866 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 5867 /* This is a good place to trace that we are exiting SMM. */ 5868 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 5869 5870 /* Process a latched INIT or SMI, if any. */ 5871 kvm_make_request(KVM_REQ_EVENT, vcpu); 5872 } 5873 5874 kvm_mmu_reset_context(vcpu); 5875 } 5876 5877 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) 5878 { 5879 unsigned changed = vcpu->arch.hflags ^ emul_flags; 5880 5881 vcpu->arch.hflags = emul_flags; 5882 5883 if (changed & HF_SMM_MASK) 5884 kvm_smm_changed(vcpu); 5885 } 5886 5887 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5888 unsigned long *db) 5889 { 5890 u32 dr6 = 0; 5891 int i; 5892 u32 enable, rwlen; 5893 5894 enable = dr7; 5895 rwlen = dr7 >> 16; 5896 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5897 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5898 dr6 |= (1 << i); 5899 return dr6; 5900 } 5901 5902 static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r) 5903 { 5904 struct kvm_run *kvm_run = vcpu->run; 5905 5906 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5907 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM; 5908 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5909 kvm_run->debug.arch.exception = DB_VECTOR; 5910 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5911 *r = EMULATE_USER_EXIT; 5912 } else { 5913 /* 5914 * "Certain debug exceptions may clear bit 0-3. The 5915 * remaining contents of the DR6 register are never 5916 * cleared by the processor". 5917 */ 5918 vcpu->arch.dr6 &= ~15; 5919 vcpu->arch.dr6 |= DR6_BS | DR6_RTM; 5920 kvm_queue_exception(vcpu, DB_VECTOR); 5921 } 5922 } 5923 5924 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 5925 { 5926 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5927 int r = EMULATE_DONE; 5928 5929 kvm_x86_ops->skip_emulated_instruction(vcpu); 5930 5931 /* 5932 * rflags is the old, "raw" value of the flags. The new value has 5933 * not been saved yet. 5934 * 5935 * This is correct even for TF set by the guest, because "the 5936 * processor will not generate this exception after the instruction 5937 * that sets the TF flag". 5938 */ 5939 if (unlikely(rflags & X86_EFLAGS_TF)) 5940 kvm_vcpu_do_singlestep(vcpu, &r); 5941 return r == EMULATE_DONE; 5942 } 5943 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 5944 5945 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5946 { 5947 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5948 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5949 struct kvm_run *kvm_run = vcpu->run; 5950 unsigned long eip = kvm_get_linear_rip(vcpu); 5951 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5952 vcpu->arch.guest_debug_dr7, 5953 vcpu->arch.eff_db); 5954 5955 if (dr6 != 0) { 5956 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 5957 kvm_run->debug.arch.pc = eip; 5958 kvm_run->debug.arch.exception = DB_VECTOR; 5959 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5960 *r = EMULATE_USER_EXIT; 5961 return true; 5962 } 5963 } 5964 5965 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 5966 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 5967 unsigned long eip = kvm_get_linear_rip(vcpu); 5968 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5969 vcpu->arch.dr7, 5970 vcpu->arch.db); 5971 5972 if (dr6 != 0) { 5973 vcpu->arch.dr6 &= ~15; 5974 vcpu->arch.dr6 |= dr6 | DR6_RTM; 5975 kvm_queue_exception(vcpu, DB_VECTOR); 5976 *r = EMULATE_DONE; 5977 return true; 5978 } 5979 } 5980 5981 return false; 5982 } 5983 5984 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 5985 { 5986 switch (ctxt->opcode_len) { 5987 case 1: 5988 switch (ctxt->b) { 5989 case 0xe4: /* IN */ 5990 case 0xe5: 5991 case 0xec: 5992 case 0xed: 5993 case 0xe6: /* OUT */ 5994 case 0xe7: 5995 case 0xee: 5996 case 0xef: 5997 case 0x6c: /* INS */ 5998 case 0x6d: 5999 case 0x6e: /* OUTS */ 6000 case 0x6f: 6001 return true; 6002 } 6003 break; 6004 case 2: 6005 switch (ctxt->b) { 6006 case 0x33: /* RDPMC */ 6007 return true; 6008 } 6009 break; 6010 } 6011 6012 return false; 6013 } 6014 6015 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 6016 unsigned long cr2, 6017 int emulation_type, 6018 void *insn, 6019 int insn_len) 6020 { 6021 int r; 6022 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6023 bool writeback = true; 6024 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 6025 6026 /* 6027 * Clear write_fault_to_shadow_pgtable here to ensure it is 6028 * never reused. 6029 */ 6030 vcpu->arch.write_fault_to_shadow_pgtable = false; 6031 kvm_clear_exception_queue(vcpu); 6032 6033 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 6034 init_emulate_ctxt(vcpu); 6035 6036 /* 6037 * We will reenter on the same instruction since 6038 * we do not set complete_userspace_io. This does not 6039 * handle watchpoints yet, those would be handled in 6040 * the emulate_ops. 6041 */ 6042 if (!(emulation_type & EMULTYPE_SKIP) && 6043 kvm_vcpu_check_breakpoint(vcpu, &r)) 6044 return r; 6045 6046 ctxt->interruptibility = 0; 6047 ctxt->have_exception = false; 6048 ctxt->exception.vector = -1; 6049 ctxt->perm_ok = false; 6050 6051 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 6052 6053 r = x86_decode_insn(ctxt, insn, insn_len); 6054 6055 trace_kvm_emulate_insn_start(vcpu); 6056 ++vcpu->stat.insn_emulation; 6057 if (r != EMULATION_OK) { 6058 if (emulation_type & EMULTYPE_TRAP_UD) 6059 return EMULATE_FAIL; 6060 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 6061 emulation_type)) 6062 return EMULATE_DONE; 6063 if (ctxt->have_exception && inject_emulated_exception(vcpu)) 6064 return EMULATE_DONE; 6065 if (emulation_type & EMULTYPE_SKIP) 6066 return EMULATE_FAIL; 6067 return handle_emulation_failure(vcpu, emulation_type); 6068 } 6069 } 6070 6071 if ((emulation_type & EMULTYPE_VMWARE) && 6072 !is_vmware_backdoor_opcode(ctxt)) 6073 return EMULATE_FAIL; 6074 6075 if (emulation_type & EMULTYPE_SKIP) { 6076 kvm_rip_write(vcpu, ctxt->_eip); 6077 if (ctxt->eflags & X86_EFLAGS_RF) 6078 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 6079 return EMULATE_DONE; 6080 } 6081 6082 if (retry_instruction(ctxt, cr2, emulation_type)) 6083 return EMULATE_DONE; 6084 6085 /* this is needed for vmware backdoor interface to work since it 6086 changes registers values during IO operation */ 6087 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 6088 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 6089 emulator_invalidate_register_cache(ctxt); 6090 } 6091 6092 restart: 6093 /* Save the faulting GPA (cr2) in the address field */ 6094 ctxt->exception.address = cr2; 6095 6096 r = x86_emulate_insn(ctxt); 6097 6098 if (r == EMULATION_INTERCEPTED) 6099 return EMULATE_DONE; 6100 6101 if (r == EMULATION_FAILED) { 6102 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 6103 emulation_type)) 6104 return EMULATE_DONE; 6105 6106 return handle_emulation_failure(vcpu, emulation_type); 6107 } 6108 6109 if (ctxt->have_exception) { 6110 r = EMULATE_DONE; 6111 if (inject_emulated_exception(vcpu)) 6112 return r; 6113 } else if (vcpu->arch.pio.count) { 6114 if (!vcpu->arch.pio.in) { 6115 /* FIXME: return into emulator if single-stepping. */ 6116 vcpu->arch.pio.count = 0; 6117 } else { 6118 writeback = false; 6119 vcpu->arch.complete_userspace_io = complete_emulated_pio; 6120 } 6121 r = EMULATE_USER_EXIT; 6122 } else if (vcpu->mmio_needed) { 6123 if (!vcpu->mmio_is_write) 6124 writeback = false; 6125 r = EMULATE_USER_EXIT; 6126 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6127 } else if (r == EMULATION_RESTART) 6128 goto restart; 6129 else 6130 r = EMULATE_DONE; 6131 6132 if (writeback) { 6133 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 6134 toggle_interruptibility(vcpu, ctxt->interruptibility); 6135 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6136 kvm_rip_write(vcpu, ctxt->eip); 6137 if (r == EMULATE_DONE && 6138 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 6139 kvm_vcpu_do_singlestep(vcpu, &r); 6140 if (!ctxt->have_exception || 6141 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 6142 __kvm_set_rflags(vcpu, ctxt->eflags); 6143 6144 /* 6145 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 6146 * do nothing, and it will be requested again as soon as 6147 * the shadow expires. But we still need to check here, 6148 * because POPF has no interrupt shadow. 6149 */ 6150 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 6151 kvm_make_request(KVM_REQ_EVENT, vcpu); 6152 } else 6153 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 6154 6155 return r; 6156 } 6157 EXPORT_SYMBOL_GPL(x86_emulate_instruction); 6158 6159 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 6160 unsigned short port) 6161 { 6162 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 6163 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 6164 size, port, &val, 1); 6165 /* do not return to emulator after return from userspace */ 6166 vcpu->arch.pio.count = 0; 6167 return ret; 6168 } 6169 6170 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 6171 { 6172 unsigned long val; 6173 6174 /* We should only ever be called with arch.pio.count equal to 1 */ 6175 BUG_ON(vcpu->arch.pio.count != 1); 6176 6177 /* For size less than 4 we merge, else we zero extend */ 6178 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) 6179 : 0; 6180 6181 /* 6182 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform 6183 * the copy and tracing 6184 */ 6185 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size, 6186 vcpu->arch.pio.port, &val, 1); 6187 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 6188 6189 return 1; 6190 } 6191 6192 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 6193 unsigned short port) 6194 { 6195 unsigned long val; 6196 int ret; 6197 6198 /* For size less than 4 we merge, else we zero extend */ 6199 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0; 6200 6201 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port, 6202 &val, 1); 6203 if (ret) { 6204 kvm_register_write(vcpu, VCPU_REGS_RAX, val); 6205 return ret; 6206 } 6207 6208 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 6209 6210 return 0; 6211 } 6212 6213 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 6214 { 6215 int ret = kvm_skip_emulated_instruction(vcpu); 6216 6217 /* 6218 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered 6219 * KVM_EXIT_DEBUG here. 6220 */ 6221 if (in) 6222 return kvm_fast_pio_in(vcpu, size, port) && ret; 6223 else 6224 return kvm_fast_pio_out(vcpu, size, port) && ret; 6225 } 6226 EXPORT_SYMBOL_GPL(kvm_fast_pio); 6227 6228 static int kvmclock_cpu_down_prep(unsigned int cpu) 6229 { 6230 __this_cpu_write(cpu_tsc_khz, 0); 6231 return 0; 6232 } 6233 6234 static void tsc_khz_changed(void *data) 6235 { 6236 struct cpufreq_freqs *freq = data; 6237 unsigned long khz = 0; 6238 6239 if (data) 6240 khz = freq->new; 6241 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 6242 khz = cpufreq_quick_get(raw_smp_processor_id()); 6243 if (!khz) 6244 khz = tsc_khz; 6245 __this_cpu_write(cpu_tsc_khz, khz); 6246 } 6247 6248 #ifdef CONFIG_X86_64 6249 static void kvm_hyperv_tsc_notifier(void) 6250 { 6251 struct kvm *kvm; 6252 struct kvm_vcpu *vcpu; 6253 int cpu; 6254 6255 spin_lock(&kvm_lock); 6256 list_for_each_entry(kvm, &vm_list, vm_list) 6257 kvm_make_mclock_inprogress_request(kvm); 6258 6259 hyperv_stop_tsc_emulation(); 6260 6261 /* TSC frequency always matches when on Hyper-V */ 6262 for_each_present_cpu(cpu) 6263 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 6264 kvm_max_guest_tsc_khz = tsc_khz; 6265 6266 list_for_each_entry(kvm, &vm_list, vm_list) { 6267 struct kvm_arch *ka = &kvm->arch; 6268 6269 spin_lock(&ka->pvclock_gtod_sync_lock); 6270 6271 pvclock_update_vm_gtod_copy(kvm); 6272 6273 kvm_for_each_vcpu(cpu, vcpu, kvm) 6274 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6275 6276 kvm_for_each_vcpu(cpu, vcpu, kvm) 6277 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 6278 6279 spin_unlock(&ka->pvclock_gtod_sync_lock); 6280 } 6281 spin_unlock(&kvm_lock); 6282 } 6283 #endif 6284 6285 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 6286 void *data) 6287 { 6288 struct cpufreq_freqs *freq = data; 6289 struct kvm *kvm; 6290 struct kvm_vcpu *vcpu; 6291 int i, send_ipi = 0; 6292 6293 /* 6294 * We allow guests to temporarily run on slowing clocks, 6295 * provided we notify them after, or to run on accelerating 6296 * clocks, provided we notify them before. Thus time never 6297 * goes backwards. 6298 * 6299 * However, we have a problem. We can't atomically update 6300 * the frequency of a given CPU from this function; it is 6301 * merely a notifier, which can be called from any CPU. 6302 * Changing the TSC frequency at arbitrary points in time 6303 * requires a recomputation of local variables related to 6304 * the TSC for each VCPU. We must flag these local variables 6305 * to be updated and be sure the update takes place with the 6306 * new frequency before any guests proceed. 6307 * 6308 * Unfortunately, the combination of hotplug CPU and frequency 6309 * change creates an intractable locking scenario; the order 6310 * of when these callouts happen is undefined with respect to 6311 * CPU hotplug, and they can race with each other. As such, 6312 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 6313 * undefined; you can actually have a CPU frequency change take 6314 * place in between the computation of X and the setting of the 6315 * variable. To protect against this problem, all updates of 6316 * the per_cpu tsc_khz variable are done in an interrupt 6317 * protected IPI, and all callers wishing to update the value 6318 * must wait for a synchronous IPI to complete (which is trivial 6319 * if the caller is on the CPU already). This establishes the 6320 * necessary total order on variable updates. 6321 * 6322 * Note that because a guest time update may take place 6323 * anytime after the setting of the VCPU's request bit, the 6324 * correct TSC value must be set before the request. However, 6325 * to ensure the update actually makes it to any guest which 6326 * starts running in hardware virtualization between the set 6327 * and the acquisition of the spinlock, we must also ping the 6328 * CPU after setting the request bit. 6329 * 6330 */ 6331 6332 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 6333 return 0; 6334 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 6335 return 0; 6336 6337 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 6338 6339 spin_lock(&kvm_lock); 6340 list_for_each_entry(kvm, &vm_list, vm_list) { 6341 kvm_for_each_vcpu(i, vcpu, kvm) { 6342 if (vcpu->cpu != freq->cpu) 6343 continue; 6344 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6345 if (vcpu->cpu != smp_processor_id()) 6346 send_ipi = 1; 6347 } 6348 } 6349 spin_unlock(&kvm_lock); 6350 6351 if (freq->old < freq->new && send_ipi) { 6352 /* 6353 * We upscale the frequency. Must make the guest 6354 * doesn't see old kvmclock values while running with 6355 * the new frequency, otherwise we risk the guest sees 6356 * time go backwards. 6357 * 6358 * In case we update the frequency for another cpu 6359 * (which might be in guest context) send an interrupt 6360 * to kick the cpu out of guest context. Next time 6361 * guest context is entered kvmclock will be updated, 6362 * so the guest will not see stale values. 6363 */ 6364 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 6365 } 6366 return 0; 6367 } 6368 6369 static struct notifier_block kvmclock_cpufreq_notifier_block = { 6370 .notifier_call = kvmclock_cpufreq_notifier 6371 }; 6372 6373 static int kvmclock_cpu_online(unsigned int cpu) 6374 { 6375 tsc_khz_changed(NULL); 6376 return 0; 6377 } 6378 6379 static void kvm_timer_init(void) 6380 { 6381 max_tsc_khz = tsc_khz; 6382 6383 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 6384 #ifdef CONFIG_CPU_FREQ 6385 struct cpufreq_policy policy; 6386 int cpu; 6387 6388 memset(&policy, 0, sizeof(policy)); 6389 cpu = get_cpu(); 6390 cpufreq_get_policy(&policy, cpu); 6391 if (policy.cpuinfo.max_freq) 6392 max_tsc_khz = policy.cpuinfo.max_freq; 6393 put_cpu(); 6394 #endif 6395 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 6396 CPUFREQ_TRANSITION_NOTIFIER); 6397 } 6398 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 6399 6400 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 6401 kvmclock_cpu_online, kvmclock_cpu_down_prep); 6402 } 6403 6404 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 6405 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu); 6406 6407 int kvm_is_in_guest(void) 6408 { 6409 return __this_cpu_read(current_vcpu) != NULL; 6410 } 6411 6412 static int kvm_is_user_mode(void) 6413 { 6414 int user_mode = 3; 6415 6416 if (__this_cpu_read(current_vcpu)) 6417 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 6418 6419 return user_mode != 0; 6420 } 6421 6422 static unsigned long kvm_get_guest_ip(void) 6423 { 6424 unsigned long ip = 0; 6425 6426 if (__this_cpu_read(current_vcpu)) 6427 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 6428 6429 return ip; 6430 } 6431 6432 static struct perf_guest_info_callbacks kvm_guest_cbs = { 6433 .is_in_guest = kvm_is_in_guest, 6434 .is_user_mode = kvm_is_user_mode, 6435 .get_guest_ip = kvm_get_guest_ip, 6436 }; 6437 6438 static void kvm_set_mmio_spte_mask(void) 6439 { 6440 u64 mask; 6441 int maxphyaddr = boot_cpu_data.x86_phys_bits; 6442 6443 /* 6444 * Set the reserved bits and the present bit of an paging-structure 6445 * entry to generate page fault with PFER.RSV = 1. 6446 */ 6447 /* Mask the reserved physical address bits. */ 6448 mask = rsvd_bits(maxphyaddr, 51); 6449 6450 /* Set the present bit. */ 6451 mask |= 1ull; 6452 6453 #ifdef CONFIG_X86_64 6454 /* 6455 * If reserved bit is not supported, clear the present bit to disable 6456 * mmio page fault. 6457 */ 6458 if (maxphyaddr == 52) 6459 mask &= ~1ull; 6460 #endif 6461 6462 kvm_mmu_set_mmio_spte_mask(mask, mask); 6463 } 6464 6465 #ifdef CONFIG_X86_64 6466 static void pvclock_gtod_update_fn(struct work_struct *work) 6467 { 6468 struct kvm *kvm; 6469 6470 struct kvm_vcpu *vcpu; 6471 int i; 6472 6473 spin_lock(&kvm_lock); 6474 list_for_each_entry(kvm, &vm_list, vm_list) 6475 kvm_for_each_vcpu(i, vcpu, kvm) 6476 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 6477 atomic_set(&kvm_guest_has_master_clock, 0); 6478 spin_unlock(&kvm_lock); 6479 } 6480 6481 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 6482 6483 /* 6484 * Notification about pvclock gtod data update. 6485 */ 6486 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 6487 void *priv) 6488 { 6489 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 6490 struct timekeeper *tk = priv; 6491 6492 update_pvclock_gtod(tk); 6493 6494 /* disable master clock if host does not trust, or does not 6495 * use, TSC based clocksource. 6496 */ 6497 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 6498 atomic_read(&kvm_guest_has_master_clock) != 0) 6499 queue_work(system_long_wq, &pvclock_gtod_work); 6500 6501 return 0; 6502 } 6503 6504 static struct notifier_block pvclock_gtod_notifier = { 6505 .notifier_call = pvclock_gtod_notify, 6506 }; 6507 #endif 6508 6509 int kvm_arch_init(void *opaque) 6510 { 6511 int r; 6512 struct kvm_x86_ops *ops = opaque; 6513 6514 if (kvm_x86_ops) { 6515 printk(KERN_ERR "kvm: already loaded the other module\n"); 6516 r = -EEXIST; 6517 goto out; 6518 } 6519 6520 if (!ops->cpu_has_kvm_support()) { 6521 printk(KERN_ERR "kvm: no hardware support\n"); 6522 r = -EOPNOTSUPP; 6523 goto out; 6524 } 6525 if (ops->disabled_by_bios()) { 6526 printk(KERN_ERR "kvm: disabled by bios\n"); 6527 r = -EOPNOTSUPP; 6528 goto out; 6529 } 6530 6531 r = -ENOMEM; 6532 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 6533 if (!shared_msrs) { 6534 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 6535 goto out; 6536 } 6537 6538 r = kvm_mmu_module_init(); 6539 if (r) 6540 goto out_free_percpu; 6541 6542 kvm_set_mmio_spte_mask(); 6543 6544 kvm_x86_ops = ops; 6545 6546 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 6547 PT_DIRTY_MASK, PT64_NX_MASK, 0, 6548 PT_PRESENT_MASK, 0, sme_me_mask); 6549 kvm_timer_init(); 6550 6551 perf_register_guest_info_callbacks(&kvm_guest_cbs); 6552 6553 if (boot_cpu_has(X86_FEATURE_XSAVE)) 6554 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 6555 6556 kvm_lapic_init(); 6557 #ifdef CONFIG_X86_64 6558 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 6559 6560 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 6561 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 6562 #endif 6563 6564 return 0; 6565 6566 out_free_percpu: 6567 free_percpu(shared_msrs); 6568 out: 6569 return r; 6570 } 6571 6572 void kvm_arch_exit(void) 6573 { 6574 #ifdef CONFIG_X86_64 6575 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 6576 clear_hv_tscchange_cb(); 6577 #endif 6578 kvm_lapic_exit(); 6579 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 6580 6581 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 6582 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 6583 CPUFREQ_TRANSITION_NOTIFIER); 6584 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 6585 #ifdef CONFIG_X86_64 6586 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 6587 #endif 6588 kvm_x86_ops = NULL; 6589 kvm_mmu_module_exit(); 6590 free_percpu(shared_msrs); 6591 } 6592 6593 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 6594 { 6595 ++vcpu->stat.halt_exits; 6596 if (lapic_in_kernel(vcpu)) { 6597 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 6598 return 1; 6599 } else { 6600 vcpu->run->exit_reason = KVM_EXIT_HLT; 6601 return 0; 6602 } 6603 } 6604 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 6605 6606 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 6607 { 6608 int ret = kvm_skip_emulated_instruction(vcpu); 6609 /* 6610 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 6611 * KVM_EXIT_DEBUG here. 6612 */ 6613 return kvm_vcpu_halt(vcpu) && ret; 6614 } 6615 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 6616 6617 #ifdef CONFIG_X86_64 6618 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 6619 unsigned long clock_type) 6620 { 6621 struct kvm_clock_pairing clock_pairing; 6622 struct timespec ts; 6623 u64 cycle; 6624 int ret; 6625 6626 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 6627 return -KVM_EOPNOTSUPP; 6628 6629 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false) 6630 return -KVM_EOPNOTSUPP; 6631 6632 clock_pairing.sec = ts.tv_sec; 6633 clock_pairing.nsec = ts.tv_nsec; 6634 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 6635 clock_pairing.flags = 0; 6636 6637 ret = 0; 6638 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 6639 sizeof(struct kvm_clock_pairing))) 6640 ret = -KVM_EFAULT; 6641 6642 return ret; 6643 } 6644 #endif 6645 6646 /* 6647 * kvm_pv_kick_cpu_op: Kick a vcpu. 6648 * 6649 * @apicid - apicid of vcpu to be kicked. 6650 */ 6651 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 6652 { 6653 struct kvm_lapic_irq lapic_irq; 6654 6655 lapic_irq.shorthand = 0; 6656 lapic_irq.dest_mode = 0; 6657 lapic_irq.level = 0; 6658 lapic_irq.dest_id = apicid; 6659 lapic_irq.msi_redir_hint = false; 6660 6661 lapic_irq.delivery_mode = APIC_DM_REMRD; 6662 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 6663 } 6664 6665 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) 6666 { 6667 vcpu->arch.apicv_active = false; 6668 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); 6669 } 6670 6671 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 6672 { 6673 unsigned long nr, a0, a1, a2, a3, ret; 6674 int op_64_bit, r; 6675 6676 r = kvm_skip_emulated_instruction(vcpu); 6677 6678 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 6679 return kvm_hv_hypercall(vcpu); 6680 6681 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 6682 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 6683 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 6684 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 6685 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 6686 6687 trace_kvm_hypercall(nr, a0, a1, a2, a3); 6688 6689 op_64_bit = is_64_bit_mode(vcpu); 6690 if (!op_64_bit) { 6691 nr &= 0xFFFFFFFF; 6692 a0 &= 0xFFFFFFFF; 6693 a1 &= 0xFFFFFFFF; 6694 a2 &= 0xFFFFFFFF; 6695 a3 &= 0xFFFFFFFF; 6696 } 6697 6698 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 6699 ret = -KVM_EPERM; 6700 goto out; 6701 } 6702 6703 switch (nr) { 6704 case KVM_HC_VAPIC_POLL_IRQ: 6705 ret = 0; 6706 break; 6707 case KVM_HC_KICK_CPU: 6708 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 6709 ret = 0; 6710 break; 6711 #ifdef CONFIG_X86_64 6712 case KVM_HC_CLOCK_PAIRING: 6713 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 6714 break; 6715 #endif 6716 default: 6717 ret = -KVM_ENOSYS; 6718 break; 6719 } 6720 out: 6721 if (!op_64_bit) 6722 ret = (u32)ret; 6723 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 6724 ++vcpu->stat.hypercalls; 6725 return r; 6726 } 6727 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 6728 6729 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 6730 { 6731 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 6732 char instruction[3]; 6733 unsigned long rip = kvm_rip_read(vcpu); 6734 6735 kvm_x86_ops->patch_hypercall(vcpu, instruction); 6736 6737 return emulator_write_emulated(ctxt, rip, instruction, 3, 6738 &ctxt->exception); 6739 } 6740 6741 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 6742 { 6743 return vcpu->run->request_interrupt_window && 6744 likely(!pic_in_kernel(vcpu->kvm)); 6745 } 6746 6747 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 6748 { 6749 struct kvm_run *kvm_run = vcpu->run; 6750 6751 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 6752 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 6753 kvm_run->cr8 = kvm_get_cr8(vcpu); 6754 kvm_run->apic_base = kvm_get_apic_base(vcpu); 6755 kvm_run->ready_for_interrupt_injection = 6756 pic_in_kernel(vcpu->kvm) || 6757 kvm_vcpu_ready_for_interrupt_injection(vcpu); 6758 } 6759 6760 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 6761 { 6762 int max_irr, tpr; 6763 6764 if (!kvm_x86_ops->update_cr8_intercept) 6765 return; 6766 6767 if (!lapic_in_kernel(vcpu)) 6768 return; 6769 6770 if (vcpu->arch.apicv_active) 6771 return; 6772 6773 if (!vcpu->arch.apic->vapic_addr) 6774 max_irr = kvm_lapic_find_highest_irr(vcpu); 6775 else 6776 max_irr = -1; 6777 6778 if (max_irr != -1) 6779 max_irr >>= 4; 6780 6781 tpr = kvm_lapic_get_cr8(vcpu); 6782 6783 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 6784 } 6785 6786 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 6787 { 6788 int r; 6789 6790 /* try to reinject previous events if any */ 6791 6792 if (vcpu->arch.exception.injected) 6793 kvm_x86_ops->queue_exception(vcpu); 6794 /* 6795 * Do not inject an NMI or interrupt if there is a pending 6796 * exception. Exceptions and interrupts are recognized at 6797 * instruction boundaries, i.e. the start of an instruction. 6798 * Trap-like exceptions, e.g. #DB, have higher priority than 6799 * NMIs and interrupts, i.e. traps are recognized before an 6800 * NMI/interrupt that's pending on the same instruction. 6801 * Fault-like exceptions, e.g. #GP and #PF, are the lowest 6802 * priority, but are only generated (pended) during instruction 6803 * execution, i.e. a pending fault-like exception means the 6804 * fault occurred on the *previous* instruction and must be 6805 * serviced prior to recognizing any new events in order to 6806 * fully complete the previous instruction. 6807 */ 6808 else if (!vcpu->arch.exception.pending) { 6809 if (vcpu->arch.nmi_injected) 6810 kvm_x86_ops->set_nmi(vcpu); 6811 else if (vcpu->arch.interrupt.injected) 6812 kvm_x86_ops->set_irq(vcpu); 6813 } 6814 6815 /* 6816 * Call check_nested_events() even if we reinjected a previous event 6817 * in order for caller to determine if it should require immediate-exit 6818 * from L2 to L1 due to pending L1 events which require exit 6819 * from L2 to L1. 6820 */ 6821 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6822 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6823 if (r != 0) 6824 return r; 6825 } 6826 6827 /* try to inject new event if pending */ 6828 if (vcpu->arch.exception.pending) { 6829 trace_kvm_inj_exception(vcpu->arch.exception.nr, 6830 vcpu->arch.exception.has_error_code, 6831 vcpu->arch.exception.error_code); 6832 6833 WARN_ON_ONCE(vcpu->arch.exception.injected); 6834 vcpu->arch.exception.pending = false; 6835 vcpu->arch.exception.injected = true; 6836 6837 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 6838 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 6839 X86_EFLAGS_RF); 6840 6841 if (vcpu->arch.exception.nr == DB_VECTOR && 6842 (vcpu->arch.dr7 & DR7_GD)) { 6843 vcpu->arch.dr7 &= ~DR7_GD; 6844 kvm_update_dr7(vcpu); 6845 } 6846 6847 kvm_x86_ops->queue_exception(vcpu); 6848 } 6849 6850 /* Don't consider new event if we re-injected an event */ 6851 if (kvm_event_needs_reinjection(vcpu)) 6852 return 0; 6853 6854 if (vcpu->arch.smi_pending && !is_smm(vcpu) && 6855 kvm_x86_ops->smi_allowed(vcpu)) { 6856 vcpu->arch.smi_pending = false; 6857 ++vcpu->arch.smi_count; 6858 enter_smm(vcpu); 6859 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) { 6860 --vcpu->arch.nmi_pending; 6861 vcpu->arch.nmi_injected = true; 6862 kvm_x86_ops->set_nmi(vcpu); 6863 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 6864 /* 6865 * Because interrupts can be injected asynchronously, we are 6866 * calling check_nested_events again here to avoid a race condition. 6867 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 6868 * proposal and current concerns. Perhaps we should be setting 6869 * KVM_REQ_EVENT only on certain events and not unconditionally? 6870 */ 6871 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6872 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6873 if (r != 0) 6874 return r; 6875 } 6876 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 6877 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 6878 false); 6879 kvm_x86_ops->set_irq(vcpu); 6880 } 6881 } 6882 6883 return 0; 6884 } 6885 6886 static void process_nmi(struct kvm_vcpu *vcpu) 6887 { 6888 unsigned limit = 2; 6889 6890 /* 6891 * x86 is limited to one NMI running, and one NMI pending after it. 6892 * If an NMI is already in progress, limit further NMIs to just one. 6893 * Otherwise, allow two (and we'll inject the first one immediately). 6894 */ 6895 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 6896 limit = 1; 6897 6898 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 6899 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 6900 kvm_make_request(KVM_REQ_EVENT, vcpu); 6901 } 6902 6903 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) 6904 { 6905 u32 flags = 0; 6906 flags |= seg->g << 23; 6907 flags |= seg->db << 22; 6908 flags |= seg->l << 21; 6909 flags |= seg->avl << 20; 6910 flags |= seg->present << 15; 6911 flags |= seg->dpl << 13; 6912 flags |= seg->s << 12; 6913 flags |= seg->type << 8; 6914 return flags; 6915 } 6916 6917 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 6918 { 6919 struct kvm_segment seg; 6920 int offset; 6921 6922 kvm_get_segment(vcpu, &seg, n); 6923 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 6924 6925 if (n < 3) 6926 offset = 0x7f84 + n * 12; 6927 else 6928 offset = 0x7f2c + (n - 3) * 12; 6929 6930 put_smstate(u32, buf, offset + 8, seg.base); 6931 put_smstate(u32, buf, offset + 4, seg.limit); 6932 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); 6933 } 6934 6935 #ifdef CONFIG_X86_64 6936 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 6937 { 6938 struct kvm_segment seg; 6939 int offset; 6940 u16 flags; 6941 6942 kvm_get_segment(vcpu, &seg, n); 6943 offset = 0x7e00 + n * 16; 6944 6945 flags = enter_smm_get_segment_flags(&seg) >> 8; 6946 put_smstate(u16, buf, offset, seg.selector); 6947 put_smstate(u16, buf, offset + 2, flags); 6948 put_smstate(u32, buf, offset + 4, seg.limit); 6949 put_smstate(u64, buf, offset + 8, seg.base); 6950 } 6951 #endif 6952 6953 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) 6954 { 6955 struct desc_ptr dt; 6956 struct kvm_segment seg; 6957 unsigned long val; 6958 int i; 6959 6960 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 6961 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 6962 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 6963 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 6964 6965 for (i = 0; i < 8; i++) 6966 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 6967 6968 kvm_get_dr(vcpu, 6, &val); 6969 put_smstate(u32, buf, 0x7fcc, (u32)val); 6970 kvm_get_dr(vcpu, 7, &val); 6971 put_smstate(u32, buf, 0x7fc8, (u32)val); 6972 6973 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6974 put_smstate(u32, buf, 0x7fc4, seg.selector); 6975 put_smstate(u32, buf, 0x7f64, seg.base); 6976 put_smstate(u32, buf, 0x7f60, seg.limit); 6977 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); 6978 6979 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6980 put_smstate(u32, buf, 0x7fc0, seg.selector); 6981 put_smstate(u32, buf, 0x7f80, seg.base); 6982 put_smstate(u32, buf, 0x7f7c, seg.limit); 6983 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); 6984 6985 kvm_x86_ops->get_gdt(vcpu, &dt); 6986 put_smstate(u32, buf, 0x7f74, dt.address); 6987 put_smstate(u32, buf, 0x7f70, dt.size); 6988 6989 kvm_x86_ops->get_idt(vcpu, &dt); 6990 put_smstate(u32, buf, 0x7f58, dt.address); 6991 put_smstate(u32, buf, 0x7f54, dt.size); 6992 6993 for (i = 0; i < 6; i++) 6994 enter_smm_save_seg_32(vcpu, buf, i); 6995 6996 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 6997 6998 /* revision id */ 6999 put_smstate(u32, buf, 0x7efc, 0x00020000); 7000 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 7001 } 7002 7003 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) 7004 { 7005 #ifdef CONFIG_X86_64 7006 struct desc_ptr dt; 7007 struct kvm_segment seg; 7008 unsigned long val; 7009 int i; 7010 7011 for (i = 0; i < 16; i++) 7012 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 7013 7014 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 7015 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 7016 7017 kvm_get_dr(vcpu, 6, &val); 7018 put_smstate(u64, buf, 0x7f68, val); 7019 kvm_get_dr(vcpu, 7, &val); 7020 put_smstate(u64, buf, 0x7f60, val); 7021 7022 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 7023 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 7024 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 7025 7026 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 7027 7028 /* revision id */ 7029 put_smstate(u32, buf, 0x7efc, 0x00020064); 7030 7031 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 7032 7033 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 7034 put_smstate(u16, buf, 0x7e90, seg.selector); 7035 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); 7036 put_smstate(u32, buf, 0x7e94, seg.limit); 7037 put_smstate(u64, buf, 0x7e98, seg.base); 7038 7039 kvm_x86_ops->get_idt(vcpu, &dt); 7040 put_smstate(u32, buf, 0x7e84, dt.size); 7041 put_smstate(u64, buf, 0x7e88, dt.address); 7042 7043 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 7044 put_smstate(u16, buf, 0x7e70, seg.selector); 7045 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); 7046 put_smstate(u32, buf, 0x7e74, seg.limit); 7047 put_smstate(u64, buf, 0x7e78, seg.base); 7048 7049 kvm_x86_ops->get_gdt(vcpu, &dt); 7050 put_smstate(u32, buf, 0x7e64, dt.size); 7051 put_smstate(u64, buf, 0x7e68, dt.address); 7052 7053 for (i = 0; i < 6; i++) 7054 enter_smm_save_seg_64(vcpu, buf, i); 7055 #else 7056 WARN_ON_ONCE(1); 7057 #endif 7058 } 7059 7060 static void enter_smm(struct kvm_vcpu *vcpu) 7061 { 7062 struct kvm_segment cs, ds; 7063 struct desc_ptr dt; 7064 char buf[512]; 7065 u32 cr0; 7066 7067 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 7068 memset(buf, 0, 512); 7069 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 7070 enter_smm_save_state_64(vcpu, buf); 7071 else 7072 enter_smm_save_state_32(vcpu, buf); 7073 7074 /* 7075 * Give pre_enter_smm() a chance to make ISA-specific changes to the 7076 * vCPU state (e.g. leave guest mode) after we've saved the state into 7077 * the SMM state-save area. 7078 */ 7079 kvm_x86_ops->pre_enter_smm(vcpu, buf); 7080 7081 vcpu->arch.hflags |= HF_SMM_MASK; 7082 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 7083 7084 if (kvm_x86_ops->get_nmi_mask(vcpu)) 7085 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 7086 else 7087 kvm_x86_ops->set_nmi_mask(vcpu, true); 7088 7089 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 7090 kvm_rip_write(vcpu, 0x8000); 7091 7092 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 7093 kvm_x86_ops->set_cr0(vcpu, cr0); 7094 vcpu->arch.cr0 = cr0; 7095 7096 kvm_x86_ops->set_cr4(vcpu, 0); 7097 7098 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 7099 dt.address = dt.size = 0; 7100 kvm_x86_ops->set_idt(vcpu, &dt); 7101 7102 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 7103 7104 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 7105 cs.base = vcpu->arch.smbase; 7106 7107 ds.selector = 0; 7108 ds.base = 0; 7109 7110 cs.limit = ds.limit = 0xffffffff; 7111 cs.type = ds.type = 0x3; 7112 cs.dpl = ds.dpl = 0; 7113 cs.db = ds.db = 0; 7114 cs.s = ds.s = 1; 7115 cs.l = ds.l = 0; 7116 cs.g = ds.g = 1; 7117 cs.avl = ds.avl = 0; 7118 cs.present = ds.present = 1; 7119 cs.unusable = ds.unusable = 0; 7120 cs.padding = ds.padding = 0; 7121 7122 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7123 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 7124 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 7125 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 7126 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 7127 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 7128 7129 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) 7130 kvm_x86_ops->set_efer(vcpu, 0); 7131 7132 kvm_update_cpuid(vcpu); 7133 kvm_mmu_reset_context(vcpu); 7134 } 7135 7136 static void process_smi(struct kvm_vcpu *vcpu) 7137 { 7138 vcpu->arch.smi_pending = true; 7139 kvm_make_request(KVM_REQ_EVENT, vcpu); 7140 } 7141 7142 void kvm_make_scan_ioapic_request(struct kvm *kvm) 7143 { 7144 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 7145 } 7146 7147 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 7148 { 7149 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 7150 return; 7151 7152 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 7153 7154 if (irqchip_split(vcpu->kvm)) 7155 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 7156 else { 7157 if (vcpu->arch.apicv_active) 7158 kvm_x86_ops->sync_pir_to_irr(vcpu); 7159 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 7160 } 7161 7162 if (is_guest_mode(vcpu)) 7163 vcpu->arch.load_eoi_exitmap_pending = true; 7164 else 7165 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 7166 } 7167 7168 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 7169 { 7170 u64 eoi_exit_bitmap[4]; 7171 7172 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 7173 return; 7174 7175 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, 7176 vcpu_to_synic(vcpu)->vec_bitmap, 256); 7177 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 7178 } 7179 7180 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, 7181 unsigned long start, unsigned long end) 7182 { 7183 unsigned long apic_address; 7184 7185 /* 7186 * The physical address of apic access page is stored in the VMCS. 7187 * Update it when it becomes invalid. 7188 */ 7189 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 7190 if (start <= apic_address && apic_address < end) 7191 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 7192 } 7193 7194 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 7195 { 7196 struct page *page = NULL; 7197 7198 if (!lapic_in_kernel(vcpu)) 7199 return; 7200 7201 if (!kvm_x86_ops->set_apic_access_page_addr) 7202 return; 7203 7204 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 7205 if (is_error_page(page)) 7206 return; 7207 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 7208 7209 /* 7210 * Do not pin apic access page in memory, the MMU notifier 7211 * will call us again if it is migrated or swapped out. 7212 */ 7213 put_page(page); 7214 } 7215 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 7216 7217 /* 7218 * Returns 1 to let vcpu_run() continue the guest execution loop without 7219 * exiting to the userspace. Otherwise, the value will be returned to the 7220 * userspace. 7221 */ 7222 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 7223 { 7224 int r; 7225 bool req_int_win = 7226 dm_request_for_irq_injection(vcpu) && 7227 kvm_cpu_accept_dm_intr(vcpu); 7228 7229 bool req_immediate_exit = false; 7230 7231 if (kvm_request_pending(vcpu)) { 7232 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 7233 kvm_mmu_unload(vcpu); 7234 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 7235 __kvm_migrate_timers(vcpu); 7236 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 7237 kvm_gen_update_masterclock(vcpu->kvm); 7238 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 7239 kvm_gen_kvmclock_update(vcpu); 7240 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 7241 r = kvm_guest_time_update(vcpu); 7242 if (unlikely(r)) 7243 goto out; 7244 } 7245 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 7246 kvm_mmu_sync_roots(vcpu); 7247 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 7248 kvm_vcpu_flush_tlb(vcpu, true); 7249 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 7250 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 7251 r = 0; 7252 goto out; 7253 } 7254 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 7255 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 7256 vcpu->mmio_needed = 0; 7257 r = 0; 7258 goto out; 7259 } 7260 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 7261 /* Page is swapped out. Do synthetic halt */ 7262 vcpu->arch.apf.halted = true; 7263 r = 1; 7264 goto out; 7265 } 7266 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 7267 record_steal_time(vcpu); 7268 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 7269 process_smi(vcpu); 7270 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 7271 process_nmi(vcpu); 7272 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 7273 kvm_pmu_handle_event(vcpu); 7274 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 7275 kvm_pmu_deliver_pmi(vcpu); 7276 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 7277 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 7278 if (test_bit(vcpu->arch.pending_ioapic_eoi, 7279 vcpu->arch.ioapic_handled_vectors)) { 7280 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 7281 vcpu->run->eoi.vector = 7282 vcpu->arch.pending_ioapic_eoi; 7283 r = 0; 7284 goto out; 7285 } 7286 } 7287 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 7288 vcpu_scan_ioapic(vcpu); 7289 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 7290 vcpu_load_eoi_exitmap(vcpu); 7291 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 7292 kvm_vcpu_reload_apic_access_page(vcpu); 7293 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 7294 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 7295 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 7296 r = 0; 7297 goto out; 7298 } 7299 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 7300 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 7301 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 7302 r = 0; 7303 goto out; 7304 } 7305 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 7306 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 7307 vcpu->run->hyperv = vcpu->arch.hyperv.exit; 7308 r = 0; 7309 goto out; 7310 } 7311 7312 /* 7313 * KVM_REQ_HV_STIMER has to be processed after 7314 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 7315 * depend on the guest clock being up-to-date 7316 */ 7317 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 7318 kvm_hv_process_stimers(vcpu); 7319 } 7320 7321 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 7322 ++vcpu->stat.req_event; 7323 kvm_apic_accept_events(vcpu); 7324 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 7325 r = 1; 7326 goto out; 7327 } 7328 7329 if (inject_pending_event(vcpu, req_int_win) != 0) 7330 req_immediate_exit = true; 7331 else { 7332 /* Enable SMI/NMI/IRQ window open exits if needed. 7333 * 7334 * SMIs have three cases: 7335 * 1) They can be nested, and then there is nothing to 7336 * do here because RSM will cause a vmexit anyway. 7337 * 2) There is an ISA-specific reason why SMI cannot be 7338 * injected, and the moment when this changes can be 7339 * intercepted. 7340 * 3) Or the SMI can be pending because 7341 * inject_pending_event has completed the injection 7342 * of an IRQ or NMI from the previous vmexit, and 7343 * then we request an immediate exit to inject the 7344 * SMI. 7345 */ 7346 if (vcpu->arch.smi_pending && !is_smm(vcpu)) 7347 if (!kvm_x86_ops->enable_smi_window(vcpu)) 7348 req_immediate_exit = true; 7349 if (vcpu->arch.nmi_pending) 7350 kvm_x86_ops->enable_nmi_window(vcpu); 7351 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 7352 kvm_x86_ops->enable_irq_window(vcpu); 7353 WARN_ON(vcpu->arch.exception.pending); 7354 } 7355 7356 if (kvm_lapic_enabled(vcpu)) { 7357 update_cr8_intercept(vcpu); 7358 kvm_lapic_sync_to_vapic(vcpu); 7359 } 7360 } 7361 7362 r = kvm_mmu_reload(vcpu); 7363 if (unlikely(r)) { 7364 goto cancel_injection; 7365 } 7366 7367 preempt_disable(); 7368 7369 kvm_x86_ops->prepare_guest_switch(vcpu); 7370 7371 /* 7372 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 7373 * IPI are then delayed after guest entry, which ensures that they 7374 * result in virtual interrupt delivery. 7375 */ 7376 local_irq_disable(); 7377 vcpu->mode = IN_GUEST_MODE; 7378 7379 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 7380 7381 /* 7382 * 1) We should set ->mode before checking ->requests. Please see 7383 * the comment in kvm_vcpu_exiting_guest_mode(). 7384 * 7385 * 2) For APICv, we should set ->mode before checking PIR.ON. This 7386 * pairs with the memory barrier implicit in pi_test_and_set_on 7387 * (see vmx_deliver_posted_interrupt). 7388 * 7389 * 3) This also orders the write to mode from any reads to the page 7390 * tables done while the VCPU is running. Please see the comment 7391 * in kvm_flush_remote_tlbs. 7392 */ 7393 smp_mb__after_srcu_read_unlock(); 7394 7395 /* 7396 * This handles the case where a posted interrupt was 7397 * notified with kvm_vcpu_kick. 7398 */ 7399 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active) 7400 kvm_x86_ops->sync_pir_to_irr(vcpu); 7401 7402 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) 7403 || need_resched() || signal_pending(current)) { 7404 vcpu->mode = OUTSIDE_GUEST_MODE; 7405 smp_wmb(); 7406 local_irq_enable(); 7407 preempt_enable(); 7408 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7409 r = 1; 7410 goto cancel_injection; 7411 } 7412 7413 kvm_load_guest_xcr0(vcpu); 7414 7415 if (req_immediate_exit) { 7416 kvm_make_request(KVM_REQ_EVENT, vcpu); 7417 smp_send_reschedule(vcpu->cpu); 7418 } 7419 7420 trace_kvm_entry(vcpu->vcpu_id); 7421 if (lapic_timer_advance_ns) 7422 wait_lapic_expire(vcpu); 7423 guest_enter_irqoff(); 7424 7425 if (unlikely(vcpu->arch.switch_db_regs)) { 7426 set_debugreg(0, 7); 7427 set_debugreg(vcpu->arch.eff_db[0], 0); 7428 set_debugreg(vcpu->arch.eff_db[1], 1); 7429 set_debugreg(vcpu->arch.eff_db[2], 2); 7430 set_debugreg(vcpu->arch.eff_db[3], 3); 7431 set_debugreg(vcpu->arch.dr6, 6); 7432 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 7433 } 7434 7435 kvm_x86_ops->run(vcpu); 7436 7437 /* 7438 * Do this here before restoring debug registers on the host. And 7439 * since we do this before handling the vmexit, a DR access vmexit 7440 * can (a) read the correct value of the debug registers, (b) set 7441 * KVM_DEBUGREG_WONT_EXIT again. 7442 */ 7443 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 7444 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 7445 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 7446 kvm_update_dr0123(vcpu); 7447 kvm_update_dr6(vcpu); 7448 kvm_update_dr7(vcpu); 7449 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 7450 } 7451 7452 /* 7453 * If the guest has used debug registers, at least dr7 7454 * will be disabled while returning to the host. 7455 * If we don't have active breakpoints in the host, we don't 7456 * care about the messed up debug address registers. But if 7457 * we have some of them active, restore the old state. 7458 */ 7459 if (hw_breakpoint_active()) 7460 hw_breakpoint_restore(); 7461 7462 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 7463 7464 vcpu->mode = OUTSIDE_GUEST_MODE; 7465 smp_wmb(); 7466 7467 kvm_put_guest_xcr0(vcpu); 7468 7469 kvm_before_interrupt(vcpu); 7470 kvm_x86_ops->handle_external_intr(vcpu); 7471 kvm_after_interrupt(vcpu); 7472 7473 ++vcpu->stat.exits; 7474 7475 guest_exit_irqoff(); 7476 7477 local_irq_enable(); 7478 preempt_enable(); 7479 7480 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7481 7482 /* 7483 * Profile KVM exit RIPs: 7484 */ 7485 if (unlikely(prof_on == KVM_PROFILING)) { 7486 unsigned long rip = kvm_rip_read(vcpu); 7487 profile_hit(KVM_PROFILING, (void *)rip); 7488 } 7489 7490 if (unlikely(vcpu->arch.tsc_always_catchup)) 7491 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7492 7493 if (vcpu->arch.apic_attention) 7494 kvm_lapic_sync_from_vapic(vcpu); 7495 7496 vcpu->arch.gpa_available = false; 7497 r = kvm_x86_ops->handle_exit(vcpu); 7498 return r; 7499 7500 cancel_injection: 7501 kvm_x86_ops->cancel_injection(vcpu); 7502 if (unlikely(vcpu->arch.apic_attention)) 7503 kvm_lapic_sync_from_vapic(vcpu); 7504 out: 7505 return r; 7506 } 7507 7508 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 7509 { 7510 if (!kvm_arch_vcpu_runnable(vcpu) && 7511 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { 7512 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7513 kvm_vcpu_block(vcpu); 7514 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7515 7516 if (kvm_x86_ops->post_block) 7517 kvm_x86_ops->post_block(vcpu); 7518 7519 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 7520 return 1; 7521 } 7522 7523 kvm_apic_accept_events(vcpu); 7524 switch(vcpu->arch.mp_state) { 7525 case KVM_MP_STATE_HALTED: 7526 vcpu->arch.pv.pv_unhalted = false; 7527 vcpu->arch.mp_state = 7528 KVM_MP_STATE_RUNNABLE; 7529 case KVM_MP_STATE_RUNNABLE: 7530 vcpu->arch.apf.halted = false; 7531 break; 7532 case KVM_MP_STATE_INIT_RECEIVED: 7533 break; 7534 default: 7535 return -EINTR; 7536 break; 7537 } 7538 return 1; 7539 } 7540 7541 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 7542 { 7543 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 7544 kvm_x86_ops->check_nested_events(vcpu, false); 7545 7546 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 7547 !vcpu->arch.apf.halted); 7548 } 7549 7550 static int vcpu_run(struct kvm_vcpu *vcpu) 7551 { 7552 int r; 7553 struct kvm *kvm = vcpu->kvm; 7554 7555 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7556 7557 for (;;) { 7558 if (kvm_vcpu_running(vcpu)) { 7559 r = vcpu_enter_guest(vcpu); 7560 } else { 7561 r = vcpu_block(kvm, vcpu); 7562 } 7563 7564 if (r <= 0) 7565 break; 7566 7567 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu); 7568 if (kvm_cpu_has_pending_timer(vcpu)) 7569 kvm_inject_pending_timer_irqs(vcpu); 7570 7571 if (dm_request_for_irq_injection(vcpu) && 7572 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 7573 r = 0; 7574 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 7575 ++vcpu->stat.request_irq_exits; 7576 break; 7577 } 7578 7579 kvm_check_async_pf_completion(vcpu); 7580 7581 if (signal_pending(current)) { 7582 r = -EINTR; 7583 vcpu->run->exit_reason = KVM_EXIT_INTR; 7584 ++vcpu->stat.signal_exits; 7585 break; 7586 } 7587 if (need_resched()) { 7588 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7589 cond_resched(); 7590 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 7591 } 7592 } 7593 7594 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 7595 7596 return r; 7597 } 7598 7599 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 7600 { 7601 int r; 7602 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 7603 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 7604 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 7605 if (r != EMULATE_DONE) 7606 return 0; 7607 return 1; 7608 } 7609 7610 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 7611 { 7612 BUG_ON(!vcpu->arch.pio.count); 7613 7614 return complete_emulated_io(vcpu); 7615 } 7616 7617 /* 7618 * Implements the following, as a state machine: 7619 * 7620 * read: 7621 * for each fragment 7622 * for each mmio piece in the fragment 7623 * write gpa, len 7624 * exit 7625 * copy data 7626 * execute insn 7627 * 7628 * write: 7629 * for each fragment 7630 * for each mmio piece in the fragment 7631 * write gpa, len 7632 * copy data 7633 * exit 7634 */ 7635 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 7636 { 7637 struct kvm_run *run = vcpu->run; 7638 struct kvm_mmio_fragment *frag; 7639 unsigned len; 7640 7641 BUG_ON(!vcpu->mmio_needed); 7642 7643 /* Complete previous fragment */ 7644 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 7645 len = min(8u, frag->len); 7646 if (!vcpu->mmio_is_write) 7647 memcpy(frag->data, run->mmio.data, len); 7648 7649 if (frag->len <= 8) { 7650 /* Switch to the next fragment. */ 7651 frag++; 7652 vcpu->mmio_cur_fragment++; 7653 } else { 7654 /* Go forward to the next mmio piece. */ 7655 frag->data += len; 7656 frag->gpa += len; 7657 frag->len -= len; 7658 } 7659 7660 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 7661 vcpu->mmio_needed = 0; 7662 7663 /* FIXME: return into emulator if single-stepping. */ 7664 if (vcpu->mmio_is_write) 7665 return 1; 7666 vcpu->mmio_read_completed = 1; 7667 return complete_emulated_io(vcpu); 7668 } 7669 7670 run->exit_reason = KVM_EXIT_MMIO; 7671 run->mmio.phys_addr = frag->gpa; 7672 if (vcpu->mmio_is_write) 7673 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 7674 run->mmio.len = min(8u, frag->len); 7675 run->mmio.is_write = vcpu->mmio_is_write; 7676 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 7677 return 0; 7678 } 7679 7680 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 7681 { 7682 int r; 7683 7684 vcpu_load(vcpu); 7685 kvm_sigset_activate(vcpu); 7686 kvm_load_guest_fpu(vcpu); 7687 7688 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 7689 if (kvm_run->immediate_exit) { 7690 r = -EINTR; 7691 goto out; 7692 } 7693 kvm_vcpu_block(vcpu); 7694 kvm_apic_accept_events(vcpu); 7695 kvm_clear_request(KVM_REQ_UNHALT, vcpu); 7696 r = -EAGAIN; 7697 if (signal_pending(current)) { 7698 r = -EINTR; 7699 vcpu->run->exit_reason = KVM_EXIT_INTR; 7700 ++vcpu->stat.signal_exits; 7701 } 7702 goto out; 7703 } 7704 7705 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) { 7706 r = -EINVAL; 7707 goto out; 7708 } 7709 7710 if (vcpu->run->kvm_dirty_regs) { 7711 r = sync_regs(vcpu); 7712 if (r != 0) 7713 goto out; 7714 } 7715 7716 /* re-sync apic's tpr */ 7717 if (!lapic_in_kernel(vcpu)) { 7718 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 7719 r = -EINVAL; 7720 goto out; 7721 } 7722 } 7723 7724 if (unlikely(vcpu->arch.complete_userspace_io)) { 7725 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 7726 vcpu->arch.complete_userspace_io = NULL; 7727 r = cui(vcpu); 7728 if (r <= 0) 7729 goto out; 7730 } else 7731 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 7732 7733 if (kvm_run->immediate_exit) 7734 r = -EINTR; 7735 else 7736 r = vcpu_run(vcpu); 7737 7738 out: 7739 kvm_put_guest_fpu(vcpu); 7740 if (vcpu->run->kvm_valid_regs) 7741 store_regs(vcpu); 7742 post_kvm_run_save(vcpu); 7743 kvm_sigset_deactivate(vcpu); 7744 7745 vcpu_put(vcpu); 7746 return r; 7747 } 7748 7749 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7750 { 7751 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 7752 /* 7753 * We are here if userspace calls get_regs() in the middle of 7754 * instruction emulation. Registers state needs to be copied 7755 * back from emulation context to vcpu. Userspace shouldn't do 7756 * that usually, but some bad designed PV devices (vmware 7757 * backdoor interface) need this to work 7758 */ 7759 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 7760 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7761 } 7762 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 7763 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 7764 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 7765 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 7766 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 7767 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 7768 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 7769 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 7770 #ifdef CONFIG_X86_64 7771 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 7772 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 7773 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 7774 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 7775 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 7776 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 7777 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 7778 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 7779 #endif 7780 7781 regs->rip = kvm_rip_read(vcpu); 7782 regs->rflags = kvm_get_rflags(vcpu); 7783 } 7784 7785 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7786 { 7787 vcpu_load(vcpu); 7788 __get_regs(vcpu, regs); 7789 vcpu_put(vcpu); 7790 return 0; 7791 } 7792 7793 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7794 { 7795 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 7796 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 7797 7798 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 7799 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 7800 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 7801 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 7802 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 7803 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 7804 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 7805 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 7806 #ifdef CONFIG_X86_64 7807 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 7808 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 7809 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 7810 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 7811 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 7812 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 7813 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 7814 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 7815 #endif 7816 7817 kvm_rip_write(vcpu, regs->rip); 7818 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 7819 7820 vcpu->arch.exception.pending = false; 7821 7822 kvm_make_request(KVM_REQ_EVENT, vcpu); 7823 } 7824 7825 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 7826 { 7827 vcpu_load(vcpu); 7828 __set_regs(vcpu, regs); 7829 vcpu_put(vcpu); 7830 return 0; 7831 } 7832 7833 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 7834 { 7835 struct kvm_segment cs; 7836 7837 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7838 *db = cs.db; 7839 *l = cs.l; 7840 } 7841 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 7842 7843 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 7844 { 7845 struct desc_ptr dt; 7846 7847 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7848 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7849 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7850 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7851 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7852 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7853 7854 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7855 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7856 7857 kvm_x86_ops->get_idt(vcpu, &dt); 7858 sregs->idt.limit = dt.size; 7859 sregs->idt.base = dt.address; 7860 kvm_x86_ops->get_gdt(vcpu, &dt); 7861 sregs->gdt.limit = dt.size; 7862 sregs->gdt.base = dt.address; 7863 7864 sregs->cr0 = kvm_read_cr0(vcpu); 7865 sregs->cr2 = vcpu->arch.cr2; 7866 sregs->cr3 = kvm_read_cr3(vcpu); 7867 sregs->cr4 = kvm_read_cr4(vcpu); 7868 sregs->cr8 = kvm_get_cr8(vcpu); 7869 sregs->efer = vcpu->arch.efer; 7870 sregs->apic_base = kvm_get_apic_base(vcpu); 7871 7872 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 7873 7874 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 7875 set_bit(vcpu->arch.interrupt.nr, 7876 (unsigned long *)sregs->interrupt_bitmap); 7877 } 7878 7879 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 7880 struct kvm_sregs *sregs) 7881 { 7882 vcpu_load(vcpu); 7883 __get_sregs(vcpu, sregs); 7884 vcpu_put(vcpu); 7885 return 0; 7886 } 7887 7888 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 7889 struct kvm_mp_state *mp_state) 7890 { 7891 vcpu_load(vcpu); 7892 7893 kvm_apic_accept_events(vcpu); 7894 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 7895 vcpu->arch.pv.pv_unhalted) 7896 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 7897 else 7898 mp_state->mp_state = vcpu->arch.mp_state; 7899 7900 vcpu_put(vcpu); 7901 return 0; 7902 } 7903 7904 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 7905 struct kvm_mp_state *mp_state) 7906 { 7907 int ret = -EINVAL; 7908 7909 vcpu_load(vcpu); 7910 7911 if (!lapic_in_kernel(vcpu) && 7912 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 7913 goto out; 7914 7915 /* INITs are latched while in SMM */ 7916 if ((is_smm(vcpu) || vcpu->arch.smi_pending) && 7917 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 7918 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 7919 goto out; 7920 7921 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 7922 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 7923 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 7924 } else 7925 vcpu->arch.mp_state = mp_state->mp_state; 7926 kvm_make_request(KVM_REQ_EVENT, vcpu); 7927 7928 ret = 0; 7929 out: 7930 vcpu_put(vcpu); 7931 return ret; 7932 } 7933 7934 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 7935 int reason, bool has_error_code, u32 error_code) 7936 { 7937 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 7938 int ret; 7939 7940 init_emulate_ctxt(vcpu); 7941 7942 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 7943 has_error_code, error_code); 7944 7945 if (ret) 7946 return EMULATE_FAIL; 7947 7948 kvm_rip_write(vcpu, ctxt->eip); 7949 kvm_set_rflags(vcpu, ctxt->eflags); 7950 kvm_make_request(KVM_REQ_EVENT, vcpu); 7951 return EMULATE_DONE; 7952 } 7953 EXPORT_SYMBOL_GPL(kvm_task_switch); 7954 7955 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 7956 { 7957 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 7958 /* 7959 * When EFER.LME and CR0.PG are set, the processor is in 7960 * 64-bit mode (though maybe in a 32-bit code segment). 7961 * CR4.PAE and EFER.LMA must be set. 7962 */ 7963 if (!(sregs->cr4 & X86_CR4_PAE) 7964 || !(sregs->efer & EFER_LMA)) 7965 return -EINVAL; 7966 } else { 7967 /* 7968 * Not in 64-bit mode: EFER.LMA is clear and the code 7969 * segment cannot be 64-bit. 7970 */ 7971 if (sregs->efer & EFER_LMA || sregs->cs.l) 7972 return -EINVAL; 7973 } 7974 7975 return 0; 7976 } 7977 7978 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 7979 { 7980 struct msr_data apic_base_msr; 7981 int mmu_reset_needed = 0; 7982 int pending_vec, max_bits, idx; 7983 struct desc_ptr dt; 7984 int ret = -EINVAL; 7985 7986 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 7987 (sregs->cr4 & X86_CR4_OSXSAVE)) 7988 goto out; 7989 7990 if (kvm_valid_sregs(vcpu, sregs)) 7991 goto out; 7992 7993 apic_base_msr.data = sregs->apic_base; 7994 apic_base_msr.host_initiated = true; 7995 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 7996 goto out; 7997 7998 dt.size = sregs->idt.limit; 7999 dt.address = sregs->idt.base; 8000 kvm_x86_ops->set_idt(vcpu, &dt); 8001 dt.size = sregs->gdt.limit; 8002 dt.address = sregs->gdt.base; 8003 kvm_x86_ops->set_gdt(vcpu, &dt); 8004 8005 vcpu->arch.cr2 = sregs->cr2; 8006 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 8007 vcpu->arch.cr3 = sregs->cr3; 8008 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 8009 8010 kvm_set_cr8(vcpu, sregs->cr8); 8011 8012 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 8013 kvm_x86_ops->set_efer(vcpu, sregs->efer); 8014 8015 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 8016 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 8017 vcpu->arch.cr0 = sregs->cr0; 8018 8019 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 8020 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 8021 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE)) 8022 kvm_update_cpuid(vcpu); 8023 8024 idx = srcu_read_lock(&vcpu->kvm->srcu); 8025 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 8026 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 8027 mmu_reset_needed = 1; 8028 } 8029 srcu_read_unlock(&vcpu->kvm->srcu, idx); 8030 8031 if (mmu_reset_needed) 8032 kvm_mmu_reset_context(vcpu); 8033 8034 max_bits = KVM_NR_INTERRUPTS; 8035 pending_vec = find_first_bit( 8036 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 8037 if (pending_vec < max_bits) { 8038 kvm_queue_interrupt(vcpu, pending_vec, false); 8039 pr_debug("Set back pending irq %d\n", pending_vec); 8040 } 8041 8042 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 8043 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 8044 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 8045 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 8046 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 8047 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 8048 8049 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 8050 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 8051 8052 update_cr8_intercept(vcpu); 8053 8054 /* Older userspace won't unhalt the vcpu on reset. */ 8055 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 8056 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 8057 !is_protmode(vcpu)) 8058 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8059 8060 kvm_make_request(KVM_REQ_EVENT, vcpu); 8061 8062 ret = 0; 8063 out: 8064 return ret; 8065 } 8066 8067 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 8068 struct kvm_sregs *sregs) 8069 { 8070 int ret; 8071 8072 vcpu_load(vcpu); 8073 ret = __set_sregs(vcpu, sregs); 8074 vcpu_put(vcpu); 8075 return ret; 8076 } 8077 8078 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 8079 struct kvm_guest_debug *dbg) 8080 { 8081 unsigned long rflags; 8082 int i, r; 8083 8084 vcpu_load(vcpu); 8085 8086 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 8087 r = -EBUSY; 8088 if (vcpu->arch.exception.pending) 8089 goto out; 8090 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 8091 kvm_queue_exception(vcpu, DB_VECTOR); 8092 else 8093 kvm_queue_exception(vcpu, BP_VECTOR); 8094 } 8095 8096 /* 8097 * Read rflags as long as potentially injected trace flags are still 8098 * filtered out. 8099 */ 8100 rflags = kvm_get_rflags(vcpu); 8101 8102 vcpu->guest_debug = dbg->control; 8103 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 8104 vcpu->guest_debug = 0; 8105 8106 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 8107 for (i = 0; i < KVM_NR_DB_REGS; ++i) 8108 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 8109 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 8110 } else { 8111 for (i = 0; i < KVM_NR_DB_REGS; i++) 8112 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 8113 } 8114 kvm_update_dr7(vcpu); 8115 8116 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 8117 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 8118 get_segment_base(vcpu, VCPU_SREG_CS); 8119 8120 /* 8121 * Trigger an rflags update that will inject or remove the trace 8122 * flags. 8123 */ 8124 kvm_set_rflags(vcpu, rflags); 8125 8126 kvm_x86_ops->update_bp_intercept(vcpu); 8127 8128 r = 0; 8129 8130 out: 8131 vcpu_put(vcpu); 8132 return r; 8133 } 8134 8135 /* 8136 * Translate a guest virtual address to a guest physical address. 8137 */ 8138 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 8139 struct kvm_translation *tr) 8140 { 8141 unsigned long vaddr = tr->linear_address; 8142 gpa_t gpa; 8143 int idx; 8144 8145 vcpu_load(vcpu); 8146 8147 idx = srcu_read_lock(&vcpu->kvm->srcu); 8148 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 8149 srcu_read_unlock(&vcpu->kvm->srcu, idx); 8150 tr->physical_address = gpa; 8151 tr->valid = gpa != UNMAPPED_GVA; 8152 tr->writeable = 1; 8153 tr->usermode = 0; 8154 8155 vcpu_put(vcpu); 8156 return 0; 8157 } 8158 8159 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 8160 { 8161 struct fxregs_state *fxsave; 8162 8163 vcpu_load(vcpu); 8164 8165 fxsave = &vcpu->arch.guest_fpu.state.fxsave; 8166 memcpy(fpu->fpr, fxsave->st_space, 128); 8167 fpu->fcw = fxsave->cwd; 8168 fpu->fsw = fxsave->swd; 8169 fpu->ftwx = fxsave->twd; 8170 fpu->last_opcode = fxsave->fop; 8171 fpu->last_ip = fxsave->rip; 8172 fpu->last_dp = fxsave->rdp; 8173 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 8174 8175 vcpu_put(vcpu); 8176 return 0; 8177 } 8178 8179 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 8180 { 8181 struct fxregs_state *fxsave; 8182 8183 vcpu_load(vcpu); 8184 8185 fxsave = &vcpu->arch.guest_fpu.state.fxsave; 8186 8187 memcpy(fxsave->st_space, fpu->fpr, 128); 8188 fxsave->cwd = fpu->fcw; 8189 fxsave->swd = fpu->fsw; 8190 fxsave->twd = fpu->ftwx; 8191 fxsave->fop = fpu->last_opcode; 8192 fxsave->rip = fpu->last_ip; 8193 fxsave->rdp = fpu->last_dp; 8194 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 8195 8196 vcpu_put(vcpu); 8197 return 0; 8198 } 8199 8200 static void store_regs(struct kvm_vcpu *vcpu) 8201 { 8202 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 8203 8204 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 8205 __get_regs(vcpu, &vcpu->run->s.regs.regs); 8206 8207 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 8208 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 8209 8210 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 8211 kvm_vcpu_ioctl_x86_get_vcpu_events( 8212 vcpu, &vcpu->run->s.regs.events); 8213 } 8214 8215 static int sync_regs(struct kvm_vcpu *vcpu) 8216 { 8217 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS) 8218 return -EINVAL; 8219 8220 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 8221 __set_regs(vcpu, &vcpu->run->s.regs.regs); 8222 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 8223 } 8224 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 8225 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) 8226 return -EINVAL; 8227 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 8228 } 8229 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 8230 if (kvm_vcpu_ioctl_x86_set_vcpu_events( 8231 vcpu, &vcpu->run->s.regs.events)) 8232 return -EINVAL; 8233 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 8234 } 8235 8236 return 0; 8237 } 8238 8239 static void fx_init(struct kvm_vcpu *vcpu) 8240 { 8241 fpstate_init(&vcpu->arch.guest_fpu.state); 8242 if (boot_cpu_has(X86_FEATURE_XSAVES)) 8243 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv = 8244 host_xcr0 | XSTATE_COMPACTION_ENABLED; 8245 8246 /* 8247 * Ensure guest xcr0 is valid for loading 8248 */ 8249 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 8250 8251 vcpu->arch.cr0 |= X86_CR0_ET; 8252 } 8253 8254 /* Swap (qemu) user FPU context for the guest FPU context. */ 8255 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 8256 { 8257 preempt_disable(); 8258 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu); 8259 /* PKRU is separately restored in kvm_x86_ops->run. */ 8260 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state, 8261 ~XFEATURE_MASK_PKRU); 8262 preempt_enable(); 8263 trace_kvm_fpu(1); 8264 } 8265 8266 /* When vcpu_run ends, restore user space FPU context. */ 8267 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 8268 { 8269 preempt_disable(); 8270 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu); 8271 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state); 8272 preempt_enable(); 8273 ++vcpu->stat.fpu_reload; 8274 trace_kvm_fpu(0); 8275 } 8276 8277 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 8278 { 8279 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask; 8280 8281 kvmclock_reset(vcpu); 8282 8283 kvm_x86_ops->vcpu_free(vcpu); 8284 free_cpumask_var(wbinvd_dirty_mask); 8285 } 8286 8287 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 8288 unsigned int id) 8289 { 8290 struct kvm_vcpu *vcpu; 8291 8292 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 8293 printk_once(KERN_WARNING 8294 "kvm: SMP vm created on host with unstable TSC; " 8295 "guest TSC will not be reliable\n"); 8296 8297 vcpu = kvm_x86_ops->vcpu_create(kvm, id); 8298 8299 return vcpu; 8300 } 8301 8302 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 8303 { 8304 kvm_vcpu_mtrr_init(vcpu); 8305 vcpu_load(vcpu); 8306 kvm_vcpu_reset(vcpu, false); 8307 kvm_mmu_setup(vcpu); 8308 vcpu_put(vcpu); 8309 return 0; 8310 } 8311 8312 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 8313 { 8314 struct msr_data msr; 8315 struct kvm *kvm = vcpu->kvm; 8316 8317 kvm_hv_vcpu_postcreate(vcpu); 8318 8319 if (mutex_lock_killable(&vcpu->mutex)) 8320 return; 8321 vcpu_load(vcpu); 8322 msr.data = 0x0; 8323 msr.index = MSR_IA32_TSC; 8324 msr.host_initiated = true; 8325 kvm_write_tsc(vcpu, &msr); 8326 vcpu_put(vcpu); 8327 mutex_unlock(&vcpu->mutex); 8328 8329 if (!kvmclock_periodic_sync) 8330 return; 8331 8332 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 8333 KVMCLOCK_SYNC_PERIOD); 8334 } 8335 8336 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 8337 { 8338 vcpu->arch.apf.msr_val = 0; 8339 8340 vcpu_load(vcpu); 8341 kvm_mmu_unload(vcpu); 8342 vcpu_put(vcpu); 8343 8344 kvm_x86_ops->vcpu_free(vcpu); 8345 } 8346 8347 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 8348 { 8349 kvm_lapic_reset(vcpu, init_event); 8350 8351 vcpu->arch.hflags = 0; 8352 8353 vcpu->arch.smi_pending = 0; 8354 vcpu->arch.smi_count = 0; 8355 atomic_set(&vcpu->arch.nmi_queued, 0); 8356 vcpu->arch.nmi_pending = 0; 8357 vcpu->arch.nmi_injected = false; 8358 kvm_clear_interrupt_queue(vcpu); 8359 kvm_clear_exception_queue(vcpu); 8360 vcpu->arch.exception.pending = false; 8361 8362 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 8363 kvm_update_dr0123(vcpu); 8364 vcpu->arch.dr6 = DR6_INIT; 8365 kvm_update_dr6(vcpu); 8366 vcpu->arch.dr7 = DR7_FIXED_1; 8367 kvm_update_dr7(vcpu); 8368 8369 vcpu->arch.cr2 = 0; 8370 8371 kvm_make_request(KVM_REQ_EVENT, vcpu); 8372 vcpu->arch.apf.msr_val = 0; 8373 vcpu->arch.st.msr_val = 0; 8374 8375 kvmclock_reset(vcpu); 8376 8377 kvm_clear_async_pf_completion_queue(vcpu); 8378 kvm_async_pf_hash_reset(vcpu); 8379 vcpu->arch.apf.halted = false; 8380 8381 if (kvm_mpx_supported()) { 8382 void *mpx_state_buffer; 8383 8384 /* 8385 * To avoid have the INIT path from kvm_apic_has_events() that be 8386 * called with loaded FPU and does not let userspace fix the state. 8387 */ 8388 if (init_event) 8389 kvm_put_guest_fpu(vcpu); 8390 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave, 8391 XFEATURE_MASK_BNDREGS); 8392 if (mpx_state_buffer) 8393 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state)); 8394 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave, 8395 XFEATURE_MASK_BNDCSR); 8396 if (mpx_state_buffer) 8397 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr)); 8398 if (init_event) 8399 kvm_load_guest_fpu(vcpu); 8400 } 8401 8402 if (!init_event) { 8403 kvm_pmu_reset(vcpu); 8404 vcpu->arch.smbase = 0x30000; 8405 8406 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 8407 vcpu->arch.msr_misc_features_enables = 0; 8408 8409 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 8410 } 8411 8412 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 8413 vcpu->arch.regs_avail = ~0; 8414 vcpu->arch.regs_dirty = ~0; 8415 8416 vcpu->arch.ia32_xss = 0; 8417 8418 kvm_x86_ops->vcpu_reset(vcpu, init_event); 8419 } 8420 8421 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 8422 { 8423 struct kvm_segment cs; 8424 8425 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 8426 cs.selector = vector << 8; 8427 cs.base = vector << 12; 8428 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 8429 kvm_rip_write(vcpu, 0); 8430 } 8431 8432 int kvm_arch_hardware_enable(void) 8433 { 8434 struct kvm *kvm; 8435 struct kvm_vcpu *vcpu; 8436 int i; 8437 int ret; 8438 u64 local_tsc; 8439 u64 max_tsc = 0; 8440 bool stable, backwards_tsc = false; 8441 8442 kvm_shared_msr_cpu_online(); 8443 ret = kvm_x86_ops->hardware_enable(); 8444 if (ret != 0) 8445 return ret; 8446 8447 local_tsc = rdtsc(); 8448 stable = !kvm_check_tsc_unstable(); 8449 list_for_each_entry(kvm, &vm_list, vm_list) { 8450 kvm_for_each_vcpu(i, vcpu, kvm) { 8451 if (!stable && vcpu->cpu == smp_processor_id()) 8452 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 8453 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 8454 backwards_tsc = true; 8455 if (vcpu->arch.last_host_tsc > max_tsc) 8456 max_tsc = vcpu->arch.last_host_tsc; 8457 } 8458 } 8459 } 8460 8461 /* 8462 * Sometimes, even reliable TSCs go backwards. This happens on 8463 * platforms that reset TSC during suspend or hibernate actions, but 8464 * maintain synchronization. We must compensate. Fortunately, we can 8465 * detect that condition here, which happens early in CPU bringup, 8466 * before any KVM threads can be running. Unfortunately, we can't 8467 * bring the TSCs fully up to date with real time, as we aren't yet far 8468 * enough into CPU bringup that we know how much real time has actually 8469 * elapsed; our helper function, ktime_get_boot_ns() will be using boot 8470 * variables that haven't been updated yet. 8471 * 8472 * So we simply find the maximum observed TSC above, then record the 8473 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 8474 * the adjustment will be applied. Note that we accumulate 8475 * adjustments, in case multiple suspend cycles happen before some VCPU 8476 * gets a chance to run again. In the event that no KVM threads get a 8477 * chance to run, we will miss the entire elapsed period, as we'll have 8478 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 8479 * loose cycle time. This isn't too big a deal, since the loss will be 8480 * uniform across all VCPUs (not to mention the scenario is extremely 8481 * unlikely). It is possible that a second hibernate recovery happens 8482 * much faster than a first, causing the observed TSC here to be 8483 * smaller; this would require additional padding adjustment, which is 8484 * why we set last_host_tsc to the local tsc observed here. 8485 * 8486 * N.B. - this code below runs only on platforms with reliable TSC, 8487 * as that is the only way backwards_tsc is set above. Also note 8488 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 8489 * have the same delta_cyc adjustment applied if backwards_tsc 8490 * is detected. Note further, this adjustment is only done once, 8491 * as we reset last_host_tsc on all VCPUs to stop this from being 8492 * called multiple times (one for each physical CPU bringup). 8493 * 8494 * Platforms with unreliable TSCs don't have to deal with this, they 8495 * will be compensated by the logic in vcpu_load, which sets the TSC to 8496 * catchup mode. This will catchup all VCPUs to real time, but cannot 8497 * guarantee that they stay in perfect synchronization. 8498 */ 8499 if (backwards_tsc) { 8500 u64 delta_cyc = max_tsc - local_tsc; 8501 list_for_each_entry(kvm, &vm_list, vm_list) { 8502 kvm->arch.backwards_tsc_observed = true; 8503 kvm_for_each_vcpu(i, vcpu, kvm) { 8504 vcpu->arch.tsc_offset_adjustment += delta_cyc; 8505 vcpu->arch.last_host_tsc = local_tsc; 8506 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 8507 } 8508 8509 /* 8510 * We have to disable TSC offset matching.. if you were 8511 * booting a VM while issuing an S4 host suspend.... 8512 * you may have some problem. Solving this issue is 8513 * left as an exercise to the reader. 8514 */ 8515 kvm->arch.last_tsc_nsec = 0; 8516 kvm->arch.last_tsc_write = 0; 8517 } 8518 8519 } 8520 return 0; 8521 } 8522 8523 void kvm_arch_hardware_disable(void) 8524 { 8525 kvm_x86_ops->hardware_disable(); 8526 drop_user_return_notifiers(); 8527 } 8528 8529 int kvm_arch_hardware_setup(void) 8530 { 8531 int r; 8532 8533 r = kvm_x86_ops->hardware_setup(); 8534 if (r != 0) 8535 return r; 8536 8537 if (kvm_has_tsc_control) { 8538 /* 8539 * Make sure the user can only configure tsc_khz values that 8540 * fit into a signed integer. 8541 * A min value is not calculated needed because it will always 8542 * be 1 on all machines. 8543 */ 8544 u64 max = min(0x7fffffffULL, 8545 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 8546 kvm_max_guest_tsc_khz = max; 8547 8548 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 8549 } 8550 8551 kvm_init_msr_list(); 8552 return 0; 8553 } 8554 8555 void kvm_arch_hardware_unsetup(void) 8556 { 8557 kvm_x86_ops->hardware_unsetup(); 8558 } 8559 8560 void kvm_arch_check_processor_compat(void *rtn) 8561 { 8562 kvm_x86_ops->check_processor_compatibility(rtn); 8563 } 8564 8565 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 8566 { 8567 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 8568 } 8569 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 8570 8571 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 8572 { 8573 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 8574 } 8575 8576 struct static_key kvm_no_apic_vcpu __read_mostly; 8577 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu); 8578 8579 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 8580 { 8581 struct page *page; 8582 int r; 8583 8584 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu); 8585 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 8586 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 8587 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8588 else 8589 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 8590 8591 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 8592 if (!page) { 8593 r = -ENOMEM; 8594 goto fail; 8595 } 8596 vcpu->arch.pio_data = page_address(page); 8597 8598 kvm_set_tsc_khz(vcpu, max_tsc_khz); 8599 8600 r = kvm_mmu_create(vcpu); 8601 if (r < 0) 8602 goto fail_free_pio_data; 8603 8604 if (irqchip_in_kernel(vcpu->kvm)) { 8605 r = kvm_create_lapic(vcpu); 8606 if (r < 0) 8607 goto fail_mmu_destroy; 8608 } else 8609 static_key_slow_inc(&kvm_no_apic_vcpu); 8610 8611 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 8612 GFP_KERNEL); 8613 if (!vcpu->arch.mce_banks) { 8614 r = -ENOMEM; 8615 goto fail_free_lapic; 8616 } 8617 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 8618 8619 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 8620 r = -ENOMEM; 8621 goto fail_free_mce_banks; 8622 } 8623 8624 fx_init(vcpu); 8625 8626 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 8627 8628 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 8629 8630 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 8631 8632 kvm_async_pf_hash_reset(vcpu); 8633 kvm_pmu_init(vcpu); 8634 8635 vcpu->arch.pending_external_vector = -1; 8636 vcpu->arch.preempted_in_kernel = false; 8637 8638 kvm_hv_vcpu_init(vcpu); 8639 8640 return 0; 8641 8642 fail_free_mce_banks: 8643 kfree(vcpu->arch.mce_banks); 8644 fail_free_lapic: 8645 kvm_free_lapic(vcpu); 8646 fail_mmu_destroy: 8647 kvm_mmu_destroy(vcpu); 8648 fail_free_pio_data: 8649 free_page((unsigned long)vcpu->arch.pio_data); 8650 fail: 8651 return r; 8652 } 8653 8654 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 8655 { 8656 int idx; 8657 8658 kvm_hv_vcpu_uninit(vcpu); 8659 kvm_pmu_destroy(vcpu); 8660 kfree(vcpu->arch.mce_banks); 8661 kvm_free_lapic(vcpu); 8662 idx = srcu_read_lock(&vcpu->kvm->srcu); 8663 kvm_mmu_destroy(vcpu); 8664 srcu_read_unlock(&vcpu->kvm->srcu, idx); 8665 free_page((unsigned long)vcpu->arch.pio_data); 8666 if (!lapic_in_kernel(vcpu)) 8667 static_key_slow_dec(&kvm_no_apic_vcpu); 8668 } 8669 8670 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 8671 { 8672 kvm_x86_ops->sched_in(vcpu, cpu); 8673 } 8674 8675 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 8676 { 8677 if (type) 8678 return -EINVAL; 8679 8680 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 8681 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 8682 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 8683 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 8684 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 8685 8686 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 8687 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 8688 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 8689 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 8690 &kvm->arch.irq_sources_bitmap); 8691 8692 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 8693 mutex_init(&kvm->arch.apic_map_lock); 8694 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 8695 8696 kvm->arch.kvmclock_offset = -ktime_get_boot_ns(); 8697 pvclock_update_vm_gtod_copy(kvm); 8698 8699 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 8700 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 8701 8702 kvm_hv_init_vm(kvm); 8703 kvm_page_track_init(kvm); 8704 kvm_mmu_init_vm(kvm); 8705 8706 if (kvm_x86_ops->vm_init) 8707 return kvm_x86_ops->vm_init(kvm); 8708 8709 return 0; 8710 } 8711 8712 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 8713 { 8714 vcpu_load(vcpu); 8715 kvm_mmu_unload(vcpu); 8716 vcpu_put(vcpu); 8717 } 8718 8719 static void kvm_free_vcpus(struct kvm *kvm) 8720 { 8721 unsigned int i; 8722 struct kvm_vcpu *vcpu; 8723 8724 /* 8725 * Unpin any mmu pages first. 8726 */ 8727 kvm_for_each_vcpu(i, vcpu, kvm) { 8728 kvm_clear_async_pf_completion_queue(vcpu); 8729 kvm_unload_vcpu_mmu(vcpu); 8730 } 8731 kvm_for_each_vcpu(i, vcpu, kvm) 8732 kvm_arch_vcpu_free(vcpu); 8733 8734 mutex_lock(&kvm->lock); 8735 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 8736 kvm->vcpus[i] = NULL; 8737 8738 atomic_set(&kvm->online_vcpus, 0); 8739 mutex_unlock(&kvm->lock); 8740 } 8741 8742 void kvm_arch_sync_events(struct kvm *kvm) 8743 { 8744 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 8745 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 8746 kvm_free_pit(kvm); 8747 } 8748 8749 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 8750 { 8751 int i, r; 8752 unsigned long hva; 8753 struct kvm_memslots *slots = kvm_memslots(kvm); 8754 struct kvm_memory_slot *slot, old; 8755 8756 /* Called with kvm->slots_lock held. */ 8757 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 8758 return -EINVAL; 8759 8760 slot = id_to_memslot(slots, id); 8761 if (size) { 8762 if (slot->npages) 8763 return -EEXIST; 8764 8765 /* 8766 * MAP_SHARED to prevent internal slot pages from being moved 8767 * by fork()/COW. 8768 */ 8769 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 8770 MAP_SHARED | MAP_ANONYMOUS, 0); 8771 if (IS_ERR((void *)hva)) 8772 return PTR_ERR((void *)hva); 8773 } else { 8774 if (!slot->npages) 8775 return 0; 8776 8777 hva = 0; 8778 } 8779 8780 old = *slot; 8781 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 8782 struct kvm_userspace_memory_region m; 8783 8784 m.slot = id | (i << 16); 8785 m.flags = 0; 8786 m.guest_phys_addr = gpa; 8787 m.userspace_addr = hva; 8788 m.memory_size = size; 8789 r = __kvm_set_memory_region(kvm, &m); 8790 if (r < 0) 8791 return r; 8792 } 8793 8794 if (!size) 8795 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); 8796 8797 return 0; 8798 } 8799 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 8800 8801 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 8802 { 8803 int r; 8804 8805 mutex_lock(&kvm->slots_lock); 8806 r = __x86_set_memory_region(kvm, id, gpa, size); 8807 mutex_unlock(&kvm->slots_lock); 8808 8809 return r; 8810 } 8811 EXPORT_SYMBOL_GPL(x86_set_memory_region); 8812 8813 void kvm_arch_destroy_vm(struct kvm *kvm) 8814 { 8815 if (current->mm == kvm->mm) { 8816 /* 8817 * Free memory regions allocated on behalf of userspace, 8818 * unless the the memory map has changed due to process exit 8819 * or fd copying. 8820 */ 8821 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); 8822 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); 8823 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 8824 } 8825 if (kvm_x86_ops->vm_destroy) 8826 kvm_x86_ops->vm_destroy(kvm); 8827 kvm_pic_destroy(kvm); 8828 kvm_ioapic_destroy(kvm); 8829 kvm_free_vcpus(kvm); 8830 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 8831 kvm_mmu_uninit_vm(kvm); 8832 kvm_page_track_cleanup(kvm); 8833 kvm_hv_destroy_vm(kvm); 8834 } 8835 8836 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 8837 struct kvm_memory_slot *dont) 8838 { 8839 int i; 8840 8841 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8842 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 8843 kvfree(free->arch.rmap[i]); 8844 free->arch.rmap[i] = NULL; 8845 } 8846 if (i == 0) 8847 continue; 8848 8849 if (!dont || free->arch.lpage_info[i - 1] != 8850 dont->arch.lpage_info[i - 1]) { 8851 kvfree(free->arch.lpage_info[i - 1]); 8852 free->arch.lpage_info[i - 1] = NULL; 8853 } 8854 } 8855 8856 kvm_page_track_free_memslot(free, dont); 8857 } 8858 8859 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 8860 unsigned long npages) 8861 { 8862 int i; 8863 8864 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8865 struct kvm_lpage_info *linfo; 8866 unsigned long ugfn; 8867 int lpages; 8868 int level = i + 1; 8869 8870 lpages = gfn_to_index(slot->base_gfn + npages - 1, 8871 slot->base_gfn, level) + 1; 8872 8873 slot->arch.rmap[i] = 8874 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL); 8875 if (!slot->arch.rmap[i]) 8876 goto out_free; 8877 if (i == 0) 8878 continue; 8879 8880 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL); 8881 if (!linfo) 8882 goto out_free; 8883 8884 slot->arch.lpage_info[i - 1] = linfo; 8885 8886 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 8887 linfo[0].disallow_lpage = 1; 8888 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 8889 linfo[lpages - 1].disallow_lpage = 1; 8890 ugfn = slot->userspace_addr >> PAGE_SHIFT; 8891 /* 8892 * If the gfn and userspace address are not aligned wrt each 8893 * other, or if explicitly asked to, disable large page 8894 * support for this slot 8895 */ 8896 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 8897 !kvm_largepages_enabled()) { 8898 unsigned long j; 8899 8900 for (j = 0; j < lpages; ++j) 8901 linfo[j].disallow_lpage = 1; 8902 } 8903 } 8904 8905 if (kvm_page_track_create_memslot(slot, npages)) 8906 goto out_free; 8907 8908 return 0; 8909 8910 out_free: 8911 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 8912 kvfree(slot->arch.rmap[i]); 8913 slot->arch.rmap[i] = NULL; 8914 if (i == 0) 8915 continue; 8916 8917 kvfree(slot->arch.lpage_info[i - 1]); 8918 slot->arch.lpage_info[i - 1] = NULL; 8919 } 8920 return -ENOMEM; 8921 } 8922 8923 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) 8924 { 8925 /* 8926 * memslots->generation has been incremented. 8927 * mmio generation may have reached its maximum value. 8928 */ 8929 kvm_mmu_invalidate_mmio_sptes(kvm, slots); 8930 } 8931 8932 int kvm_arch_prepare_memory_region(struct kvm *kvm, 8933 struct kvm_memory_slot *memslot, 8934 const struct kvm_userspace_memory_region *mem, 8935 enum kvm_mr_change change) 8936 { 8937 return 0; 8938 } 8939 8940 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 8941 struct kvm_memory_slot *new) 8942 { 8943 /* Still write protect RO slot */ 8944 if (new->flags & KVM_MEM_READONLY) { 8945 kvm_mmu_slot_remove_write_access(kvm, new); 8946 return; 8947 } 8948 8949 /* 8950 * Call kvm_x86_ops dirty logging hooks when they are valid. 8951 * 8952 * kvm_x86_ops->slot_disable_log_dirty is called when: 8953 * 8954 * - KVM_MR_CREATE with dirty logging is disabled 8955 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 8956 * 8957 * The reason is, in case of PML, we need to set D-bit for any slots 8958 * with dirty logging disabled in order to eliminate unnecessary GPA 8959 * logging in PML buffer (and potential PML buffer full VMEXT). This 8960 * guarantees leaving PML enabled during guest's lifetime won't have 8961 * any additonal overhead from PML when guest is running with dirty 8962 * logging disabled for memory slots. 8963 * 8964 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 8965 * to dirty logging mode. 8966 * 8967 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 8968 * 8969 * In case of write protect: 8970 * 8971 * Write protect all pages for dirty logging. 8972 * 8973 * All the sptes including the large sptes which point to this 8974 * slot are set to readonly. We can not create any new large 8975 * spte on this slot until the end of the logging. 8976 * 8977 * See the comments in fast_page_fault(). 8978 */ 8979 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 8980 if (kvm_x86_ops->slot_enable_log_dirty) 8981 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 8982 else 8983 kvm_mmu_slot_remove_write_access(kvm, new); 8984 } else { 8985 if (kvm_x86_ops->slot_disable_log_dirty) 8986 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 8987 } 8988 } 8989 8990 void kvm_arch_commit_memory_region(struct kvm *kvm, 8991 const struct kvm_userspace_memory_region *mem, 8992 const struct kvm_memory_slot *old, 8993 const struct kvm_memory_slot *new, 8994 enum kvm_mr_change change) 8995 { 8996 int nr_mmu_pages = 0; 8997 8998 if (!kvm->arch.n_requested_mmu_pages) 8999 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 9000 9001 if (nr_mmu_pages) 9002 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 9003 9004 /* 9005 * Dirty logging tracks sptes in 4k granularity, meaning that large 9006 * sptes have to be split. If live migration is successful, the guest 9007 * in the source machine will be destroyed and large sptes will be 9008 * created in the destination. However, if the guest continues to run 9009 * in the source machine (for example if live migration fails), small 9010 * sptes will remain around and cause bad performance. 9011 * 9012 * Scan sptes if dirty logging has been stopped, dropping those 9013 * which can be collapsed into a single large-page spte. Later 9014 * page faults will create the large-page sptes. 9015 */ 9016 if ((change != KVM_MR_DELETE) && 9017 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 9018 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 9019 kvm_mmu_zap_collapsible_sptes(kvm, new); 9020 9021 /* 9022 * Set up write protection and/or dirty logging for the new slot. 9023 * 9024 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 9025 * been zapped so no dirty logging staff is needed for old slot. For 9026 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 9027 * new and it's also covered when dealing with the new slot. 9028 * 9029 * FIXME: const-ify all uses of struct kvm_memory_slot. 9030 */ 9031 if (change != KVM_MR_DELETE) 9032 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 9033 } 9034 9035 void kvm_arch_flush_shadow_all(struct kvm *kvm) 9036 { 9037 kvm_mmu_invalidate_zap_all_pages(kvm); 9038 } 9039 9040 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 9041 struct kvm_memory_slot *slot) 9042 { 9043 kvm_page_track_flush_slot(kvm, slot); 9044 } 9045 9046 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 9047 { 9048 if (!list_empty_careful(&vcpu->async_pf.done)) 9049 return true; 9050 9051 if (kvm_apic_has_events(vcpu)) 9052 return true; 9053 9054 if (vcpu->arch.pv.pv_unhalted) 9055 return true; 9056 9057 if (vcpu->arch.exception.pending) 9058 return true; 9059 9060 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 9061 (vcpu->arch.nmi_pending && 9062 kvm_x86_ops->nmi_allowed(vcpu))) 9063 return true; 9064 9065 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 9066 (vcpu->arch.smi_pending && !is_smm(vcpu))) 9067 return true; 9068 9069 if (kvm_arch_interrupt_allowed(vcpu) && 9070 kvm_cpu_has_interrupt(vcpu)) 9071 return true; 9072 9073 if (kvm_hv_has_stimer_pending(vcpu)) 9074 return true; 9075 9076 return false; 9077 } 9078 9079 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 9080 { 9081 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 9082 } 9083 9084 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 9085 { 9086 return vcpu->arch.preempted_in_kernel; 9087 } 9088 9089 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 9090 { 9091 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 9092 } 9093 9094 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 9095 { 9096 return kvm_x86_ops->interrupt_allowed(vcpu); 9097 } 9098 9099 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 9100 { 9101 if (is_64_bit_mode(vcpu)) 9102 return kvm_rip_read(vcpu); 9103 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 9104 kvm_rip_read(vcpu)); 9105 } 9106 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 9107 9108 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 9109 { 9110 return kvm_get_linear_rip(vcpu) == linear_rip; 9111 } 9112 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 9113 9114 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 9115 { 9116 unsigned long rflags; 9117 9118 rflags = kvm_x86_ops->get_rflags(vcpu); 9119 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 9120 rflags &= ~X86_EFLAGS_TF; 9121 return rflags; 9122 } 9123 EXPORT_SYMBOL_GPL(kvm_get_rflags); 9124 9125 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 9126 { 9127 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 9128 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 9129 rflags |= X86_EFLAGS_TF; 9130 kvm_x86_ops->set_rflags(vcpu, rflags); 9131 } 9132 9133 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 9134 { 9135 __kvm_set_rflags(vcpu, rflags); 9136 kvm_make_request(KVM_REQ_EVENT, vcpu); 9137 } 9138 EXPORT_SYMBOL_GPL(kvm_set_rflags); 9139 9140 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 9141 { 9142 int r; 9143 9144 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 9145 work->wakeup_all) 9146 return; 9147 9148 r = kvm_mmu_reload(vcpu); 9149 if (unlikely(r)) 9150 return; 9151 9152 if (!vcpu->arch.mmu.direct_map && 9153 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 9154 return; 9155 9156 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 9157 } 9158 9159 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 9160 { 9161 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 9162 } 9163 9164 static inline u32 kvm_async_pf_next_probe(u32 key) 9165 { 9166 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 9167 } 9168 9169 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 9170 { 9171 u32 key = kvm_async_pf_hash_fn(gfn); 9172 9173 while (vcpu->arch.apf.gfns[key] != ~0) 9174 key = kvm_async_pf_next_probe(key); 9175 9176 vcpu->arch.apf.gfns[key] = gfn; 9177 } 9178 9179 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 9180 { 9181 int i; 9182 u32 key = kvm_async_pf_hash_fn(gfn); 9183 9184 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 9185 (vcpu->arch.apf.gfns[key] != gfn && 9186 vcpu->arch.apf.gfns[key] != ~0); i++) 9187 key = kvm_async_pf_next_probe(key); 9188 9189 return key; 9190 } 9191 9192 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 9193 { 9194 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 9195 } 9196 9197 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 9198 { 9199 u32 i, j, k; 9200 9201 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 9202 while (true) { 9203 vcpu->arch.apf.gfns[i] = ~0; 9204 do { 9205 j = kvm_async_pf_next_probe(j); 9206 if (vcpu->arch.apf.gfns[j] == ~0) 9207 return; 9208 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 9209 /* 9210 * k lies cyclically in ]i,j] 9211 * | i.k.j | 9212 * |....j i.k.| or |.k..j i...| 9213 */ 9214 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 9215 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 9216 i = j; 9217 } 9218 } 9219 9220 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 9221 { 9222 9223 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 9224 sizeof(val)); 9225 } 9226 9227 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val) 9228 { 9229 9230 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val, 9231 sizeof(u32)); 9232 } 9233 9234 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 9235 struct kvm_async_pf *work) 9236 { 9237 struct x86_exception fault; 9238 9239 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 9240 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 9241 9242 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 9243 (vcpu->arch.apf.send_user_only && 9244 kvm_x86_ops->get_cpl(vcpu) == 0)) 9245 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 9246 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 9247 fault.vector = PF_VECTOR; 9248 fault.error_code_valid = true; 9249 fault.error_code = 0; 9250 fault.nested_page_fault = false; 9251 fault.address = work->arch.token; 9252 fault.async_page_fault = true; 9253 kvm_inject_page_fault(vcpu, &fault); 9254 } 9255 } 9256 9257 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 9258 struct kvm_async_pf *work) 9259 { 9260 struct x86_exception fault; 9261 u32 val; 9262 9263 if (work->wakeup_all) 9264 work->arch.token = ~0; /* broadcast wakeup */ 9265 else 9266 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 9267 trace_kvm_async_pf_ready(work->arch.token, work->gva); 9268 9269 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED && 9270 !apf_get_user(vcpu, &val)) { 9271 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT && 9272 vcpu->arch.exception.pending && 9273 vcpu->arch.exception.nr == PF_VECTOR && 9274 !apf_put_user(vcpu, 0)) { 9275 vcpu->arch.exception.injected = false; 9276 vcpu->arch.exception.pending = false; 9277 vcpu->arch.exception.nr = 0; 9278 vcpu->arch.exception.has_error_code = false; 9279 vcpu->arch.exception.error_code = 0; 9280 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 9281 fault.vector = PF_VECTOR; 9282 fault.error_code_valid = true; 9283 fault.error_code = 0; 9284 fault.nested_page_fault = false; 9285 fault.address = work->arch.token; 9286 fault.async_page_fault = true; 9287 kvm_inject_page_fault(vcpu, &fault); 9288 } 9289 } 9290 vcpu->arch.apf.halted = false; 9291 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 9292 } 9293 9294 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 9295 { 9296 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 9297 return true; 9298 else 9299 return kvm_can_do_async_pf(vcpu); 9300 } 9301 9302 void kvm_arch_start_assignment(struct kvm *kvm) 9303 { 9304 atomic_inc(&kvm->arch.assigned_device_count); 9305 } 9306 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 9307 9308 void kvm_arch_end_assignment(struct kvm *kvm) 9309 { 9310 atomic_dec(&kvm->arch.assigned_device_count); 9311 } 9312 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 9313 9314 bool kvm_arch_has_assigned_device(struct kvm *kvm) 9315 { 9316 return atomic_read(&kvm->arch.assigned_device_count); 9317 } 9318 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 9319 9320 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 9321 { 9322 atomic_inc(&kvm->arch.noncoherent_dma_count); 9323 } 9324 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 9325 9326 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 9327 { 9328 atomic_dec(&kvm->arch.noncoherent_dma_count); 9329 } 9330 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 9331 9332 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 9333 { 9334 return atomic_read(&kvm->arch.noncoherent_dma_count); 9335 } 9336 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 9337 9338 bool kvm_arch_has_irq_bypass(void) 9339 { 9340 return kvm_x86_ops->update_pi_irte != NULL; 9341 } 9342 9343 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 9344 struct irq_bypass_producer *prod) 9345 { 9346 struct kvm_kernel_irqfd *irqfd = 9347 container_of(cons, struct kvm_kernel_irqfd, consumer); 9348 9349 irqfd->producer = prod; 9350 9351 return kvm_x86_ops->update_pi_irte(irqfd->kvm, 9352 prod->irq, irqfd->gsi, 1); 9353 } 9354 9355 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 9356 struct irq_bypass_producer *prod) 9357 { 9358 int ret; 9359 struct kvm_kernel_irqfd *irqfd = 9360 container_of(cons, struct kvm_kernel_irqfd, consumer); 9361 9362 WARN_ON(irqfd->producer != prod); 9363 irqfd->producer = NULL; 9364 9365 /* 9366 * When producer of consumer is unregistered, we change back to 9367 * remapped mode, so we can re-use the current implementation 9368 * when the irq is masked/disabled or the consumer side (KVM 9369 * int this case doesn't want to receive the interrupts. 9370 */ 9371 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 9372 if (ret) 9373 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 9374 " fails: %d\n", irqfd->consumer.token, ret); 9375 } 9376 9377 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 9378 uint32_t guest_irq, bool set) 9379 { 9380 if (!kvm_x86_ops->update_pi_irte) 9381 return -EINVAL; 9382 9383 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); 9384 } 9385 9386 bool kvm_vector_hashing_enabled(void) 9387 { 9388 return vector_hashing; 9389 } 9390 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled); 9391 9392 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 9393 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 9394 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 9395 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 9396 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 9397 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 9398 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 9399 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 9400 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 9401 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 9402 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 9403 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 9404 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 9405 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 9406 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 9407 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 9408 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 9409 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 9410 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 9411