1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 31 #include <linux/clocksource.h> 32 #include <linux/interrupt.h> 33 #include <linux/kvm.h> 34 #include <linux/fs.h> 35 #include <linux/vmalloc.h> 36 #include <linux/module.h> 37 #include <linux/mman.h> 38 #include <linux/highmem.h> 39 #include <linux/iommu.h> 40 #include <linux/intel-iommu.h> 41 #include <linux/cpufreq.h> 42 #include <linux/user-return-notifier.h> 43 #include <linux/srcu.h> 44 #include <linux/slab.h> 45 #include <linux/perf_event.h> 46 #include <linux/uaccess.h> 47 #include <linux/hash.h> 48 #include <linux/pci.h> 49 #include <linux/timekeeper_internal.h> 50 #include <linux/pvclock_gtod.h> 51 #include <trace/events/kvm.h> 52 53 #define CREATE_TRACE_POINTS 54 #include "trace.h" 55 56 #include <asm/debugreg.h> 57 #include <asm/msr.h> 58 #include <asm/desc.h> 59 #include <asm/mtrr.h> 60 #include <asm/mce.h> 61 #include <asm/i387.h> 62 #include <asm/fpu-internal.h> /* Ugh! */ 63 #include <asm/xcr.h> 64 #include <asm/pvclock.h> 65 #include <asm/div64.h> 66 67 #define MAX_IO_MSRS 256 68 #define KVM_MAX_MCE_BANKS 32 69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) 70 71 #define emul_to_vcpu(ctxt) \ 72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 73 74 /* EFER defaults: 75 * - enable syscall per default because its emulated by KVM 76 * - enable LME and LMA per default on 64 bit KVM 77 */ 78 #ifdef CONFIG_X86_64 79 static 80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 81 #else 82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 83 #endif 84 85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 87 88 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 89 static void process_nmi(struct kvm_vcpu *vcpu); 90 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 91 92 struct kvm_x86_ops *kvm_x86_ops; 93 EXPORT_SYMBOL_GPL(kvm_x86_ops); 94 95 static bool ignore_msrs = 0; 96 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 97 98 unsigned int min_timer_period_us = 500; 99 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 100 101 bool kvm_has_tsc_control; 102 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 103 u32 kvm_max_guest_tsc_khz; 104 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 105 106 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 107 static u32 tsc_tolerance_ppm = 250; 108 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 109 110 static bool backwards_tsc_observed = false; 111 112 #define KVM_NR_SHARED_MSRS 16 113 114 struct kvm_shared_msrs_global { 115 int nr; 116 u32 msrs[KVM_NR_SHARED_MSRS]; 117 }; 118 119 struct kvm_shared_msrs { 120 struct user_return_notifier urn; 121 bool registered; 122 struct kvm_shared_msr_values { 123 u64 host; 124 u64 curr; 125 } values[KVM_NR_SHARED_MSRS]; 126 }; 127 128 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 129 static struct kvm_shared_msrs __percpu *shared_msrs; 130 131 struct kvm_stats_debugfs_item debugfs_entries[] = { 132 { "pf_fixed", VCPU_STAT(pf_fixed) }, 133 { "pf_guest", VCPU_STAT(pf_guest) }, 134 { "tlb_flush", VCPU_STAT(tlb_flush) }, 135 { "invlpg", VCPU_STAT(invlpg) }, 136 { "exits", VCPU_STAT(exits) }, 137 { "io_exits", VCPU_STAT(io_exits) }, 138 { "mmio_exits", VCPU_STAT(mmio_exits) }, 139 { "signal_exits", VCPU_STAT(signal_exits) }, 140 { "irq_window", VCPU_STAT(irq_window_exits) }, 141 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 142 { "halt_exits", VCPU_STAT(halt_exits) }, 143 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 144 { "hypercalls", VCPU_STAT(hypercalls) }, 145 { "request_irq", VCPU_STAT(request_irq_exits) }, 146 { "irq_exits", VCPU_STAT(irq_exits) }, 147 { "host_state_reload", VCPU_STAT(host_state_reload) }, 148 { "efer_reload", VCPU_STAT(efer_reload) }, 149 { "fpu_reload", VCPU_STAT(fpu_reload) }, 150 { "insn_emulation", VCPU_STAT(insn_emulation) }, 151 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 152 { "irq_injections", VCPU_STAT(irq_injections) }, 153 { "nmi_injections", VCPU_STAT(nmi_injections) }, 154 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 155 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 156 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 157 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 158 { "mmu_flooded", VM_STAT(mmu_flooded) }, 159 { "mmu_recycled", VM_STAT(mmu_recycled) }, 160 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 161 { "mmu_unsync", VM_STAT(mmu_unsync) }, 162 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 163 { "largepages", VM_STAT(lpages) }, 164 { NULL } 165 }; 166 167 u64 __read_mostly host_xcr0; 168 169 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 170 171 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 172 { 173 int i; 174 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 175 vcpu->arch.apf.gfns[i] = ~0; 176 } 177 178 static void kvm_on_user_return(struct user_return_notifier *urn) 179 { 180 unsigned slot; 181 struct kvm_shared_msrs *locals 182 = container_of(urn, struct kvm_shared_msrs, urn); 183 struct kvm_shared_msr_values *values; 184 185 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 186 values = &locals->values[slot]; 187 if (values->host != values->curr) { 188 wrmsrl(shared_msrs_global.msrs[slot], values->host); 189 values->curr = values->host; 190 } 191 } 192 locals->registered = false; 193 user_return_notifier_unregister(urn); 194 } 195 196 static void shared_msr_update(unsigned slot, u32 msr) 197 { 198 u64 value; 199 unsigned int cpu = smp_processor_id(); 200 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 201 202 /* only read, and nobody should modify it at this time, 203 * so don't need lock */ 204 if (slot >= shared_msrs_global.nr) { 205 printk(KERN_ERR "kvm: invalid MSR slot!"); 206 return; 207 } 208 rdmsrl_safe(msr, &value); 209 smsr->values[slot].host = value; 210 smsr->values[slot].curr = value; 211 } 212 213 void kvm_define_shared_msr(unsigned slot, u32 msr) 214 { 215 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 216 if (slot >= shared_msrs_global.nr) 217 shared_msrs_global.nr = slot + 1; 218 shared_msrs_global.msrs[slot] = msr; 219 /* we need ensured the shared_msr_global have been updated */ 220 smp_wmb(); 221 } 222 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 223 224 static void kvm_shared_msr_cpu_online(void) 225 { 226 unsigned i; 227 228 for (i = 0; i < shared_msrs_global.nr; ++i) 229 shared_msr_update(i, shared_msrs_global.msrs[i]); 230 } 231 232 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 233 { 234 unsigned int cpu = smp_processor_id(); 235 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 236 237 if (((value ^ smsr->values[slot].curr) & mask) == 0) 238 return; 239 smsr->values[slot].curr = value; 240 wrmsrl(shared_msrs_global.msrs[slot], value); 241 if (!smsr->registered) { 242 smsr->urn.on_user_return = kvm_on_user_return; 243 user_return_notifier_register(&smsr->urn); 244 smsr->registered = true; 245 } 246 } 247 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 248 249 static void drop_user_return_notifiers(void *ignore) 250 { 251 unsigned int cpu = smp_processor_id(); 252 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 253 254 if (smsr->registered) 255 kvm_on_user_return(&smsr->urn); 256 } 257 258 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 259 { 260 return vcpu->arch.apic_base; 261 } 262 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 263 264 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 265 { 266 u64 old_state = vcpu->arch.apic_base & 267 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 268 u64 new_state = msr_info->data & 269 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 270 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 271 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); 272 273 if (!msr_info->host_initiated && 274 ((msr_info->data & reserved_bits) != 0 || 275 new_state == X2APIC_ENABLE || 276 (new_state == MSR_IA32_APICBASE_ENABLE && 277 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 278 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 279 old_state == 0))) 280 return 1; 281 282 kvm_lapic_set_base(vcpu, msr_info->data); 283 return 0; 284 } 285 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 286 287 asmlinkage __visible void kvm_spurious_fault(void) 288 { 289 /* Fault while not rebooting. We want the trace. */ 290 BUG(); 291 } 292 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 293 294 #define EXCPT_BENIGN 0 295 #define EXCPT_CONTRIBUTORY 1 296 #define EXCPT_PF 2 297 298 static int exception_class(int vector) 299 { 300 switch (vector) { 301 case PF_VECTOR: 302 return EXCPT_PF; 303 case DE_VECTOR: 304 case TS_VECTOR: 305 case NP_VECTOR: 306 case SS_VECTOR: 307 case GP_VECTOR: 308 return EXCPT_CONTRIBUTORY; 309 default: 310 break; 311 } 312 return EXCPT_BENIGN; 313 } 314 315 #define EXCPT_FAULT 0 316 #define EXCPT_TRAP 1 317 #define EXCPT_ABORT 2 318 #define EXCPT_INTERRUPT 3 319 320 static int exception_type(int vector) 321 { 322 unsigned int mask; 323 324 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 325 return EXCPT_INTERRUPT; 326 327 mask = 1 << vector; 328 329 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 330 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 331 return EXCPT_TRAP; 332 333 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 334 return EXCPT_ABORT; 335 336 /* Reserved exceptions will result in fault */ 337 return EXCPT_FAULT; 338 } 339 340 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 341 unsigned nr, bool has_error, u32 error_code, 342 bool reinject) 343 { 344 u32 prev_nr; 345 int class1, class2; 346 347 kvm_make_request(KVM_REQ_EVENT, vcpu); 348 349 if (!vcpu->arch.exception.pending) { 350 queue: 351 vcpu->arch.exception.pending = true; 352 vcpu->arch.exception.has_error_code = has_error; 353 vcpu->arch.exception.nr = nr; 354 vcpu->arch.exception.error_code = error_code; 355 vcpu->arch.exception.reinject = reinject; 356 return; 357 } 358 359 /* to check exception */ 360 prev_nr = vcpu->arch.exception.nr; 361 if (prev_nr == DF_VECTOR) { 362 /* triple fault -> shutdown */ 363 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 364 return; 365 } 366 class1 = exception_class(prev_nr); 367 class2 = exception_class(nr); 368 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 369 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 370 /* generate double fault per SDM Table 5-5 */ 371 vcpu->arch.exception.pending = true; 372 vcpu->arch.exception.has_error_code = true; 373 vcpu->arch.exception.nr = DF_VECTOR; 374 vcpu->arch.exception.error_code = 0; 375 } else 376 /* replace previous exception with a new one in a hope 377 that instruction re-execution will regenerate lost 378 exception */ 379 goto queue; 380 } 381 382 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 383 { 384 kvm_multiple_exception(vcpu, nr, false, 0, false); 385 } 386 EXPORT_SYMBOL_GPL(kvm_queue_exception); 387 388 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 389 { 390 kvm_multiple_exception(vcpu, nr, false, 0, true); 391 } 392 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 393 394 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 395 { 396 if (err) 397 kvm_inject_gp(vcpu, 0); 398 else 399 kvm_x86_ops->skip_emulated_instruction(vcpu); 400 } 401 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 402 403 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 404 { 405 ++vcpu->stat.pf_guest; 406 vcpu->arch.cr2 = fault->address; 407 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 408 } 409 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 410 411 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 412 { 413 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 414 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 415 else 416 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 417 } 418 419 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 420 { 421 atomic_inc(&vcpu->arch.nmi_queued); 422 kvm_make_request(KVM_REQ_NMI, vcpu); 423 } 424 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 425 426 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 427 { 428 kvm_multiple_exception(vcpu, nr, true, error_code, false); 429 } 430 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 431 432 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 433 { 434 kvm_multiple_exception(vcpu, nr, true, error_code, true); 435 } 436 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 437 438 /* 439 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 440 * a #GP and return false. 441 */ 442 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 443 { 444 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 445 return true; 446 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 447 return false; 448 } 449 EXPORT_SYMBOL_GPL(kvm_require_cpl); 450 451 /* 452 * This function will be used to read from the physical memory of the currently 453 * running guest. The difference to kvm_read_guest_page is that this function 454 * can read from guest physical or from the guest's guest physical memory. 455 */ 456 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 457 gfn_t ngfn, void *data, int offset, int len, 458 u32 access) 459 { 460 gfn_t real_gfn; 461 gpa_t ngpa; 462 463 ngpa = gfn_to_gpa(ngfn); 464 real_gfn = mmu->translate_gpa(vcpu, ngpa, access); 465 if (real_gfn == UNMAPPED_GVA) 466 return -EFAULT; 467 468 real_gfn = gpa_to_gfn(real_gfn); 469 470 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len); 471 } 472 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 473 474 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 475 void *data, int offset, int len, u32 access) 476 { 477 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 478 data, offset, len, access); 479 } 480 481 /* 482 * Load the pae pdptrs. Return true is they are all valid. 483 */ 484 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 485 { 486 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 487 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 488 int i; 489 int ret; 490 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 491 492 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 493 offset * sizeof(u64), sizeof(pdpte), 494 PFERR_USER_MASK|PFERR_WRITE_MASK); 495 if (ret < 0) { 496 ret = 0; 497 goto out; 498 } 499 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 500 if (is_present_gpte(pdpte[i]) && 501 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { 502 ret = 0; 503 goto out; 504 } 505 } 506 ret = 1; 507 508 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 509 __set_bit(VCPU_EXREG_PDPTR, 510 (unsigned long *)&vcpu->arch.regs_avail); 511 __set_bit(VCPU_EXREG_PDPTR, 512 (unsigned long *)&vcpu->arch.regs_dirty); 513 out: 514 515 return ret; 516 } 517 EXPORT_SYMBOL_GPL(load_pdptrs); 518 519 static bool pdptrs_changed(struct kvm_vcpu *vcpu) 520 { 521 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 522 bool changed = true; 523 int offset; 524 gfn_t gfn; 525 int r; 526 527 if (is_long_mode(vcpu) || !is_pae(vcpu)) 528 return false; 529 530 if (!test_bit(VCPU_EXREG_PDPTR, 531 (unsigned long *)&vcpu->arch.regs_avail)) 532 return true; 533 534 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; 535 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); 536 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 537 PFERR_USER_MASK | PFERR_WRITE_MASK); 538 if (r < 0) 539 goto out; 540 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 541 out: 542 543 return changed; 544 } 545 546 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 547 { 548 unsigned long old_cr0 = kvm_read_cr0(vcpu); 549 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP | 550 X86_CR0_CD | X86_CR0_NW; 551 552 cr0 |= X86_CR0_ET; 553 554 #ifdef CONFIG_X86_64 555 if (cr0 & 0xffffffff00000000UL) 556 return 1; 557 #endif 558 559 cr0 &= ~CR0_RESERVED_BITS; 560 561 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 562 return 1; 563 564 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 565 return 1; 566 567 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 568 #ifdef CONFIG_X86_64 569 if ((vcpu->arch.efer & EFER_LME)) { 570 int cs_db, cs_l; 571 572 if (!is_pae(vcpu)) 573 return 1; 574 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 575 if (cs_l) 576 return 1; 577 } else 578 #endif 579 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 580 kvm_read_cr3(vcpu))) 581 return 1; 582 } 583 584 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 585 return 1; 586 587 kvm_x86_ops->set_cr0(vcpu, cr0); 588 589 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 590 kvm_clear_async_pf_completion_queue(vcpu); 591 kvm_async_pf_hash_reset(vcpu); 592 } 593 594 if ((cr0 ^ old_cr0) & update_bits) 595 kvm_mmu_reset_context(vcpu); 596 return 0; 597 } 598 EXPORT_SYMBOL_GPL(kvm_set_cr0); 599 600 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 601 { 602 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 603 } 604 EXPORT_SYMBOL_GPL(kvm_lmsw); 605 606 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 607 { 608 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 609 !vcpu->guest_xcr0_loaded) { 610 /* kvm_set_xcr() also depends on this */ 611 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 612 vcpu->guest_xcr0_loaded = 1; 613 } 614 } 615 616 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 617 { 618 if (vcpu->guest_xcr0_loaded) { 619 if (vcpu->arch.xcr0 != host_xcr0) 620 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 621 vcpu->guest_xcr0_loaded = 0; 622 } 623 } 624 625 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 626 { 627 u64 xcr0 = xcr; 628 u64 old_xcr0 = vcpu->arch.xcr0; 629 u64 valid_bits; 630 631 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 632 if (index != XCR_XFEATURE_ENABLED_MASK) 633 return 1; 634 if (!(xcr0 & XSTATE_FP)) 635 return 1; 636 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) 637 return 1; 638 639 /* 640 * Do not allow the guest to set bits that we do not support 641 * saving. However, xcr0 bit 0 is always set, even if the 642 * emulated CPU does not support XSAVE (see fx_init). 643 */ 644 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP; 645 if (xcr0 & ~valid_bits) 646 return 1; 647 648 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR))) 649 return 1; 650 651 kvm_put_guest_xcr0(vcpu); 652 vcpu->arch.xcr0 = xcr0; 653 654 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK) 655 kvm_update_cpuid(vcpu); 656 return 0; 657 } 658 659 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 660 { 661 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 662 __kvm_set_xcr(vcpu, index, xcr)) { 663 kvm_inject_gp(vcpu, 0); 664 return 1; 665 } 666 return 0; 667 } 668 EXPORT_SYMBOL_GPL(kvm_set_xcr); 669 670 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 671 { 672 unsigned long old_cr4 = kvm_read_cr4(vcpu); 673 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | 674 X86_CR4_PAE | X86_CR4_SMEP; 675 if (cr4 & CR4_RESERVED_BITS) 676 return 1; 677 678 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) 679 return 1; 680 681 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) 682 return 1; 683 684 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) 685 return 1; 686 687 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) 688 return 1; 689 690 if (is_long_mode(vcpu)) { 691 if (!(cr4 & X86_CR4_PAE)) 692 return 1; 693 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 694 && ((cr4 ^ old_cr4) & pdptr_bits) 695 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 696 kvm_read_cr3(vcpu))) 697 return 1; 698 699 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 700 if (!guest_cpuid_has_pcid(vcpu)) 701 return 1; 702 703 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 704 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 705 return 1; 706 } 707 708 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 709 return 1; 710 711 if (((cr4 ^ old_cr4) & pdptr_bits) || 712 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 713 kvm_mmu_reset_context(vcpu); 714 715 if ((cr4 ^ old_cr4) & X86_CR4_SMAP) 716 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false); 717 718 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) 719 kvm_update_cpuid(vcpu); 720 721 return 0; 722 } 723 EXPORT_SYMBOL_GPL(kvm_set_cr4); 724 725 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 726 { 727 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 728 kvm_mmu_sync_roots(vcpu); 729 kvm_mmu_flush_tlb(vcpu); 730 return 0; 731 } 732 733 if (is_long_mode(vcpu)) { 734 if (cr3 & CR3_L_MODE_RESERVED_BITS) 735 return 1; 736 } else if (is_pae(vcpu) && is_paging(vcpu) && 737 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 738 return 1; 739 740 vcpu->arch.cr3 = cr3; 741 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 742 kvm_mmu_new_cr3(vcpu); 743 return 0; 744 } 745 EXPORT_SYMBOL_GPL(kvm_set_cr3); 746 747 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 748 { 749 if (cr8 & CR8_RESERVED_BITS) 750 return 1; 751 if (irqchip_in_kernel(vcpu->kvm)) 752 kvm_lapic_set_tpr(vcpu, cr8); 753 else 754 vcpu->arch.cr8 = cr8; 755 return 0; 756 } 757 EXPORT_SYMBOL_GPL(kvm_set_cr8); 758 759 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 760 { 761 if (irqchip_in_kernel(vcpu->kvm)) 762 return kvm_lapic_get_cr8(vcpu); 763 else 764 return vcpu->arch.cr8; 765 } 766 EXPORT_SYMBOL_GPL(kvm_get_cr8); 767 768 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 769 { 770 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 771 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 772 } 773 774 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 775 { 776 unsigned long dr7; 777 778 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 779 dr7 = vcpu->arch.guest_debug_dr7; 780 else 781 dr7 = vcpu->arch.dr7; 782 kvm_x86_ops->set_dr7(vcpu, dr7); 783 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 784 if (dr7 & DR7_BP_EN_MASK) 785 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 786 } 787 788 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 789 { 790 u64 fixed = DR6_FIXED_1; 791 792 if (!guest_cpuid_has_rtm(vcpu)) 793 fixed |= DR6_RTM; 794 return fixed; 795 } 796 797 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 798 { 799 switch (dr) { 800 case 0 ... 3: 801 vcpu->arch.db[dr] = val; 802 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 803 vcpu->arch.eff_db[dr] = val; 804 break; 805 case 4: 806 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 807 return 1; /* #UD */ 808 /* fall through */ 809 case 6: 810 if (val & 0xffffffff00000000ULL) 811 return -1; /* #GP */ 812 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 813 kvm_update_dr6(vcpu); 814 break; 815 case 5: 816 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 817 return 1; /* #UD */ 818 /* fall through */ 819 default: /* 7 */ 820 if (val & 0xffffffff00000000ULL) 821 return -1; /* #GP */ 822 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 823 kvm_update_dr7(vcpu); 824 break; 825 } 826 827 return 0; 828 } 829 830 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 831 { 832 int res; 833 834 res = __kvm_set_dr(vcpu, dr, val); 835 if (res > 0) 836 kvm_queue_exception(vcpu, UD_VECTOR); 837 else if (res < 0) 838 kvm_inject_gp(vcpu, 0); 839 840 return res; 841 } 842 EXPORT_SYMBOL_GPL(kvm_set_dr); 843 844 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 845 { 846 switch (dr) { 847 case 0 ... 3: 848 *val = vcpu->arch.db[dr]; 849 break; 850 case 4: 851 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 852 return 1; 853 /* fall through */ 854 case 6: 855 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 856 *val = vcpu->arch.dr6; 857 else 858 *val = kvm_x86_ops->get_dr6(vcpu); 859 break; 860 case 5: 861 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 862 return 1; 863 /* fall through */ 864 default: /* 7 */ 865 *val = vcpu->arch.dr7; 866 break; 867 } 868 869 return 0; 870 } 871 872 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 873 { 874 if (_kvm_get_dr(vcpu, dr, val)) { 875 kvm_queue_exception(vcpu, UD_VECTOR); 876 return 1; 877 } 878 return 0; 879 } 880 EXPORT_SYMBOL_GPL(kvm_get_dr); 881 882 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 883 { 884 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 885 u64 data; 886 int err; 887 888 err = kvm_pmu_read_pmc(vcpu, ecx, &data); 889 if (err) 890 return err; 891 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 892 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 893 return err; 894 } 895 EXPORT_SYMBOL_GPL(kvm_rdpmc); 896 897 /* 898 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 899 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 900 * 901 * This list is modified at module load time to reflect the 902 * capabilities of the host cpu. This capabilities test skips MSRs that are 903 * kvm-specific. Those are put in the beginning of the list. 904 */ 905 906 #define KVM_SAVE_MSRS_BEGIN 12 907 static u32 msrs_to_save[] = { 908 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 909 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 910 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 911 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 912 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 913 MSR_KVM_PV_EOI_EN, 914 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 915 MSR_STAR, 916 #ifdef CONFIG_X86_64 917 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 918 #endif 919 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 920 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS 921 }; 922 923 static unsigned num_msrs_to_save; 924 925 static const u32 emulated_msrs[] = { 926 MSR_IA32_TSC_ADJUST, 927 MSR_IA32_TSCDEADLINE, 928 MSR_IA32_MISC_ENABLE, 929 MSR_IA32_MCG_STATUS, 930 MSR_IA32_MCG_CTL, 931 }; 932 933 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 934 { 935 if (efer & efer_reserved_bits) 936 return false; 937 938 if (efer & EFER_FFXSR) { 939 struct kvm_cpuid_entry2 *feat; 940 941 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 942 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) 943 return false; 944 } 945 946 if (efer & EFER_SVME) { 947 struct kvm_cpuid_entry2 *feat; 948 949 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 950 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) 951 return false; 952 } 953 954 return true; 955 } 956 EXPORT_SYMBOL_GPL(kvm_valid_efer); 957 958 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 959 { 960 u64 old_efer = vcpu->arch.efer; 961 962 if (!kvm_valid_efer(vcpu, efer)) 963 return 1; 964 965 if (is_paging(vcpu) 966 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 967 return 1; 968 969 efer &= ~EFER_LMA; 970 efer |= vcpu->arch.efer & EFER_LMA; 971 972 kvm_x86_ops->set_efer(vcpu, efer); 973 974 /* Update reserved bits */ 975 if ((efer ^ old_efer) & EFER_NX) 976 kvm_mmu_reset_context(vcpu); 977 978 return 0; 979 } 980 981 void kvm_enable_efer_bits(u64 mask) 982 { 983 efer_reserved_bits &= ~mask; 984 } 985 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 986 987 988 /* 989 * Writes msr value into into the appropriate "register". 990 * Returns 0 on success, non-0 otherwise. 991 * Assumes vcpu_load() was already called. 992 */ 993 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 994 { 995 return kvm_x86_ops->set_msr(vcpu, msr); 996 } 997 998 /* 999 * Adapt set_msr() to msr_io()'s calling convention 1000 */ 1001 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1002 { 1003 struct msr_data msr; 1004 1005 msr.data = *data; 1006 msr.index = index; 1007 msr.host_initiated = true; 1008 return kvm_set_msr(vcpu, &msr); 1009 } 1010 1011 #ifdef CONFIG_X86_64 1012 struct pvclock_gtod_data { 1013 seqcount_t seq; 1014 1015 struct { /* extract of a clocksource struct */ 1016 int vclock_mode; 1017 cycle_t cycle_last; 1018 cycle_t mask; 1019 u32 mult; 1020 u32 shift; 1021 } clock; 1022 1023 u64 boot_ns; 1024 u64 nsec_base; 1025 }; 1026 1027 static struct pvclock_gtod_data pvclock_gtod_data; 1028 1029 static void update_pvclock_gtod(struct timekeeper *tk) 1030 { 1031 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1032 u64 boot_ns; 1033 1034 boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot)); 1035 1036 write_seqcount_begin(&vdata->seq); 1037 1038 /* copy pvclock gtod data */ 1039 vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode; 1040 vdata->clock.cycle_last = tk->tkr.cycle_last; 1041 vdata->clock.mask = tk->tkr.mask; 1042 vdata->clock.mult = tk->tkr.mult; 1043 vdata->clock.shift = tk->tkr.shift; 1044 1045 vdata->boot_ns = boot_ns; 1046 vdata->nsec_base = tk->tkr.xtime_nsec; 1047 1048 write_seqcount_end(&vdata->seq); 1049 } 1050 #endif 1051 1052 1053 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1054 { 1055 int version; 1056 int r; 1057 struct pvclock_wall_clock wc; 1058 struct timespec boot; 1059 1060 if (!wall_clock) 1061 return; 1062 1063 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1064 if (r) 1065 return; 1066 1067 if (version & 1) 1068 ++version; /* first time write, random junk */ 1069 1070 ++version; 1071 1072 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1073 1074 /* 1075 * The guest calculates current wall clock time by adding 1076 * system time (updated by kvm_guest_time_update below) to the 1077 * wall clock specified here. guest system time equals host 1078 * system time for us, thus we must fill in host boot time here. 1079 */ 1080 getboottime(&boot); 1081 1082 if (kvm->arch.kvmclock_offset) { 1083 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); 1084 boot = timespec_sub(boot, ts); 1085 } 1086 wc.sec = boot.tv_sec; 1087 wc.nsec = boot.tv_nsec; 1088 wc.version = version; 1089 1090 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1091 1092 version++; 1093 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1094 } 1095 1096 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1097 { 1098 uint32_t quotient, remainder; 1099 1100 /* Don't try to replace with do_div(), this one calculates 1101 * "(dividend << 32) / divisor" */ 1102 __asm__ ( "divl %4" 1103 : "=a" (quotient), "=d" (remainder) 1104 : "0" (0), "1" (dividend), "r" (divisor) ); 1105 return quotient; 1106 } 1107 1108 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, 1109 s8 *pshift, u32 *pmultiplier) 1110 { 1111 uint64_t scaled64; 1112 int32_t shift = 0; 1113 uint64_t tps64; 1114 uint32_t tps32; 1115 1116 tps64 = base_khz * 1000LL; 1117 scaled64 = scaled_khz * 1000LL; 1118 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1119 tps64 >>= 1; 1120 shift--; 1121 } 1122 1123 tps32 = (uint32_t)tps64; 1124 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1125 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1126 scaled64 >>= 1; 1127 else 1128 tps32 <<= 1; 1129 shift++; 1130 } 1131 1132 *pshift = shift; 1133 *pmultiplier = div_frac(scaled64, tps32); 1134 1135 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", 1136 __func__, base_khz, scaled_khz, shift, *pmultiplier); 1137 } 1138 1139 static inline u64 get_kernel_ns(void) 1140 { 1141 return ktime_get_boot_ns(); 1142 } 1143 1144 #ifdef CONFIG_X86_64 1145 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1146 #endif 1147 1148 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1149 unsigned long max_tsc_khz; 1150 1151 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) 1152 { 1153 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, 1154 vcpu->arch.virtual_tsc_shift); 1155 } 1156 1157 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1158 { 1159 u64 v = (u64)khz * (1000000 + ppm); 1160 do_div(v, 1000000); 1161 return v; 1162 } 1163 1164 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) 1165 { 1166 u32 thresh_lo, thresh_hi; 1167 int use_scaling = 0; 1168 1169 /* tsc_khz can be zero if TSC calibration fails */ 1170 if (this_tsc_khz == 0) 1171 return; 1172 1173 /* Compute a scale to convert nanoseconds in TSC cycles */ 1174 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, 1175 &vcpu->arch.virtual_tsc_shift, 1176 &vcpu->arch.virtual_tsc_mult); 1177 vcpu->arch.virtual_tsc_khz = this_tsc_khz; 1178 1179 /* 1180 * Compute the variation in TSC rate which is acceptable 1181 * within the range of tolerance and decide if the 1182 * rate being applied is within that bounds of the hardware 1183 * rate. If so, no scaling or compensation need be done. 1184 */ 1185 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1186 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1187 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { 1188 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); 1189 use_scaling = 1; 1190 } 1191 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling); 1192 } 1193 1194 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1195 { 1196 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1197 vcpu->arch.virtual_tsc_mult, 1198 vcpu->arch.virtual_tsc_shift); 1199 tsc += vcpu->arch.this_tsc_write; 1200 return tsc; 1201 } 1202 1203 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1204 { 1205 #ifdef CONFIG_X86_64 1206 bool vcpus_matched; 1207 bool do_request = false; 1208 struct kvm_arch *ka = &vcpu->kvm->arch; 1209 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1210 1211 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1212 atomic_read(&vcpu->kvm->online_vcpus)); 1213 1214 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC) 1215 if (!ka->use_master_clock) 1216 do_request = 1; 1217 1218 if (!vcpus_matched && ka->use_master_clock) 1219 do_request = 1; 1220 1221 if (do_request) 1222 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1223 1224 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1225 atomic_read(&vcpu->kvm->online_vcpus), 1226 ka->use_master_clock, gtod->clock.vclock_mode); 1227 #endif 1228 } 1229 1230 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1231 { 1232 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); 1233 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1234 } 1235 1236 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1237 { 1238 struct kvm *kvm = vcpu->kvm; 1239 u64 offset, ns, elapsed; 1240 unsigned long flags; 1241 s64 usdiff; 1242 bool matched; 1243 bool already_matched; 1244 u64 data = msr->data; 1245 1246 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1247 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); 1248 ns = get_kernel_ns(); 1249 elapsed = ns - kvm->arch.last_tsc_nsec; 1250 1251 if (vcpu->arch.virtual_tsc_khz) { 1252 int faulted = 0; 1253 1254 /* n.b - signed multiplication and division required */ 1255 usdiff = data - kvm->arch.last_tsc_write; 1256 #ifdef CONFIG_X86_64 1257 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; 1258 #else 1259 /* do_div() only does unsigned */ 1260 asm("1: idivl %[divisor]\n" 1261 "2: xor %%edx, %%edx\n" 1262 " movl $0, %[faulted]\n" 1263 "3:\n" 1264 ".section .fixup,\"ax\"\n" 1265 "4: movl $1, %[faulted]\n" 1266 " jmp 3b\n" 1267 ".previous\n" 1268 1269 _ASM_EXTABLE(1b, 4b) 1270 1271 : "=A"(usdiff), [faulted] "=r" (faulted) 1272 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); 1273 1274 #endif 1275 do_div(elapsed, 1000); 1276 usdiff -= elapsed; 1277 if (usdiff < 0) 1278 usdiff = -usdiff; 1279 1280 /* idivl overflow => difference is larger than USEC_PER_SEC */ 1281 if (faulted) 1282 usdiff = USEC_PER_SEC; 1283 } else 1284 usdiff = USEC_PER_SEC; /* disable TSC match window below */ 1285 1286 /* 1287 * Special case: TSC write with a small delta (1 second) of virtual 1288 * cycle time against real time is interpreted as an attempt to 1289 * synchronize the CPU. 1290 * 1291 * For a reliable TSC, we can match TSC offsets, and for an unstable 1292 * TSC, we add elapsed time in this computation. We could let the 1293 * compensation code attempt to catch up if we fall behind, but 1294 * it's better to try to match offsets from the beginning. 1295 */ 1296 if (usdiff < USEC_PER_SEC && 1297 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1298 if (!check_tsc_unstable()) { 1299 offset = kvm->arch.cur_tsc_offset; 1300 pr_debug("kvm: matched tsc offset for %llu\n", data); 1301 } else { 1302 u64 delta = nsec_to_cycles(vcpu, elapsed); 1303 data += delta; 1304 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); 1305 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1306 } 1307 matched = true; 1308 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1309 } else { 1310 /* 1311 * We split periods of matched TSC writes into generations. 1312 * For each generation, we track the original measured 1313 * nanosecond time, offset, and write, so if TSCs are in 1314 * sync, we can match exact offset, and if not, we can match 1315 * exact software computation in compute_guest_tsc() 1316 * 1317 * These values are tracked in kvm->arch.cur_xxx variables. 1318 */ 1319 kvm->arch.cur_tsc_generation++; 1320 kvm->arch.cur_tsc_nsec = ns; 1321 kvm->arch.cur_tsc_write = data; 1322 kvm->arch.cur_tsc_offset = offset; 1323 matched = false; 1324 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1325 kvm->arch.cur_tsc_generation, data); 1326 } 1327 1328 /* 1329 * We also track th most recent recorded KHZ, write and time to 1330 * allow the matching interval to be extended at each write. 1331 */ 1332 kvm->arch.last_tsc_nsec = ns; 1333 kvm->arch.last_tsc_write = data; 1334 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1335 1336 vcpu->arch.last_guest_tsc = data; 1337 1338 /* Keep track of which generation this VCPU has synchronized to */ 1339 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1340 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1341 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1342 1343 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) 1344 update_ia32_tsc_adjust_msr(vcpu, offset); 1345 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1346 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1347 1348 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1349 if (!matched) { 1350 kvm->arch.nr_vcpus_matched_tsc = 0; 1351 } else if (!already_matched) { 1352 kvm->arch.nr_vcpus_matched_tsc++; 1353 } 1354 1355 kvm_track_tsc_matching(vcpu); 1356 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1357 } 1358 1359 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1360 1361 #ifdef CONFIG_X86_64 1362 1363 static cycle_t read_tsc(void) 1364 { 1365 cycle_t ret; 1366 u64 last; 1367 1368 /* 1369 * Empirically, a fence (of type that depends on the CPU) 1370 * before rdtsc is enough to ensure that rdtsc is ordered 1371 * with respect to loads. The various CPU manuals are unclear 1372 * as to whether rdtsc can be reordered with later loads, 1373 * but no one has ever seen it happen. 1374 */ 1375 rdtsc_barrier(); 1376 ret = (cycle_t)vget_cycles(); 1377 1378 last = pvclock_gtod_data.clock.cycle_last; 1379 1380 if (likely(ret >= last)) 1381 return ret; 1382 1383 /* 1384 * GCC likes to generate cmov here, but this branch is extremely 1385 * predictable (it's just a funciton of time and the likely is 1386 * very likely) and there's a data dependence, so force GCC 1387 * to generate a branch instead. I don't barrier() because 1388 * we don't actually need a barrier, and if this function 1389 * ever gets inlined it will generate worse code. 1390 */ 1391 asm volatile (""); 1392 return last; 1393 } 1394 1395 static inline u64 vgettsc(cycle_t *cycle_now) 1396 { 1397 long v; 1398 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1399 1400 *cycle_now = read_tsc(); 1401 1402 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; 1403 return v * gtod->clock.mult; 1404 } 1405 1406 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now) 1407 { 1408 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1409 unsigned long seq; 1410 int mode; 1411 u64 ns; 1412 1413 do { 1414 seq = read_seqcount_begin(>od->seq); 1415 mode = gtod->clock.vclock_mode; 1416 ns = gtod->nsec_base; 1417 ns += vgettsc(cycle_now); 1418 ns >>= gtod->clock.shift; 1419 ns += gtod->boot_ns; 1420 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1421 *t = ns; 1422 1423 return mode; 1424 } 1425 1426 /* returns true if host is using tsc clocksource */ 1427 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) 1428 { 1429 /* checked again under seqlock below */ 1430 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) 1431 return false; 1432 1433 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; 1434 } 1435 #endif 1436 1437 /* 1438 * 1439 * Assuming a stable TSC across physical CPUS, and a stable TSC 1440 * across virtual CPUs, the following condition is possible. 1441 * Each numbered line represents an event visible to both 1442 * CPUs at the next numbered event. 1443 * 1444 * "timespecX" represents host monotonic time. "tscX" represents 1445 * RDTSC value. 1446 * 1447 * VCPU0 on CPU0 | VCPU1 on CPU1 1448 * 1449 * 1. read timespec0,tsc0 1450 * 2. | timespec1 = timespec0 + N 1451 * | tsc1 = tsc0 + M 1452 * 3. transition to guest | transition to guest 1453 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1454 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1455 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1456 * 1457 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1458 * 1459 * - ret0 < ret1 1460 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1461 * ... 1462 * - 0 < N - M => M < N 1463 * 1464 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1465 * always the case (the difference between two distinct xtime instances 1466 * might be smaller then the difference between corresponding TSC reads, 1467 * when updating guest vcpus pvclock areas). 1468 * 1469 * To avoid that problem, do not allow visibility of distinct 1470 * system_timestamp/tsc_timestamp values simultaneously: use a master 1471 * copy of host monotonic time values. Update that master copy 1472 * in lockstep. 1473 * 1474 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1475 * 1476 */ 1477 1478 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1479 { 1480 #ifdef CONFIG_X86_64 1481 struct kvm_arch *ka = &kvm->arch; 1482 int vclock_mode; 1483 bool host_tsc_clocksource, vcpus_matched; 1484 1485 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1486 atomic_read(&kvm->online_vcpus)); 1487 1488 /* 1489 * If the host uses TSC clock, then passthrough TSC as stable 1490 * to the guest. 1491 */ 1492 host_tsc_clocksource = kvm_get_time_and_clockread( 1493 &ka->master_kernel_ns, 1494 &ka->master_cycle_now); 1495 1496 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 1497 && !backwards_tsc_observed; 1498 1499 if (ka->use_master_clock) 1500 atomic_set(&kvm_guest_has_master_clock, 1); 1501 1502 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1503 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1504 vcpus_matched); 1505 #endif 1506 } 1507 1508 static void kvm_gen_update_masterclock(struct kvm *kvm) 1509 { 1510 #ifdef CONFIG_X86_64 1511 int i; 1512 struct kvm_vcpu *vcpu; 1513 struct kvm_arch *ka = &kvm->arch; 1514 1515 spin_lock(&ka->pvclock_gtod_sync_lock); 1516 kvm_make_mclock_inprogress_request(kvm); 1517 /* no guest entries from this point */ 1518 pvclock_update_vm_gtod_copy(kvm); 1519 1520 kvm_for_each_vcpu(i, vcpu, kvm) 1521 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests); 1522 1523 /* guest entries allowed */ 1524 kvm_for_each_vcpu(i, vcpu, kvm) 1525 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); 1526 1527 spin_unlock(&ka->pvclock_gtod_sync_lock); 1528 #endif 1529 } 1530 1531 static int kvm_guest_time_update(struct kvm_vcpu *v) 1532 { 1533 unsigned long flags, this_tsc_khz; 1534 struct kvm_vcpu_arch *vcpu = &v->arch; 1535 struct kvm_arch *ka = &v->kvm->arch; 1536 s64 kernel_ns; 1537 u64 tsc_timestamp, host_tsc; 1538 struct pvclock_vcpu_time_info guest_hv_clock; 1539 u8 pvclock_flags; 1540 bool use_master_clock; 1541 1542 kernel_ns = 0; 1543 host_tsc = 0; 1544 1545 /* 1546 * If the host uses TSC clock, then passthrough TSC as stable 1547 * to the guest. 1548 */ 1549 spin_lock(&ka->pvclock_gtod_sync_lock); 1550 use_master_clock = ka->use_master_clock; 1551 if (use_master_clock) { 1552 host_tsc = ka->master_cycle_now; 1553 kernel_ns = ka->master_kernel_ns; 1554 } 1555 spin_unlock(&ka->pvclock_gtod_sync_lock); 1556 1557 /* Keep irq disabled to prevent changes to the clock */ 1558 local_irq_save(flags); 1559 this_tsc_khz = __get_cpu_var(cpu_tsc_khz); 1560 if (unlikely(this_tsc_khz == 0)) { 1561 local_irq_restore(flags); 1562 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1563 return 1; 1564 } 1565 if (!use_master_clock) { 1566 host_tsc = native_read_tsc(); 1567 kernel_ns = get_kernel_ns(); 1568 } 1569 1570 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc); 1571 1572 /* 1573 * We may have to catch up the TSC to match elapsed wall clock 1574 * time for two reasons, even if kvmclock is used. 1575 * 1) CPU could have been running below the maximum TSC rate 1576 * 2) Broken TSC compensation resets the base at each VCPU 1577 * entry to avoid unknown leaps of TSC even when running 1578 * again on the same CPU. This may cause apparent elapsed 1579 * time to disappear, and the guest to stand still or run 1580 * very slowly. 1581 */ 1582 if (vcpu->tsc_catchup) { 1583 u64 tsc = compute_guest_tsc(v, kernel_ns); 1584 if (tsc > tsc_timestamp) { 1585 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 1586 tsc_timestamp = tsc; 1587 } 1588 } 1589 1590 local_irq_restore(flags); 1591 1592 if (!vcpu->pv_time_enabled) 1593 return 0; 1594 1595 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { 1596 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz, 1597 &vcpu->hv_clock.tsc_shift, 1598 &vcpu->hv_clock.tsc_to_system_mul); 1599 vcpu->hw_tsc_khz = this_tsc_khz; 1600 } 1601 1602 /* With all the info we got, fill in the values */ 1603 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 1604 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 1605 vcpu->last_guest_tsc = tsc_timestamp; 1606 1607 /* 1608 * The interface expects us to write an even number signaling that the 1609 * update is finished. Since the guest won't see the intermediate 1610 * state, we just increase by 2 at the end. 1611 */ 1612 vcpu->hv_clock.version += 2; 1613 1614 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1615 &guest_hv_clock, sizeof(guest_hv_clock)))) 1616 return 0; 1617 1618 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1619 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1620 1621 if (vcpu->pvclock_set_guest_stopped_request) { 1622 pvclock_flags |= PVCLOCK_GUEST_STOPPED; 1623 vcpu->pvclock_set_guest_stopped_request = false; 1624 } 1625 1626 /* If the host uses TSC clocksource, then it is stable */ 1627 if (use_master_clock) 1628 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 1629 1630 vcpu->hv_clock.flags = pvclock_flags; 1631 1632 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1633 &vcpu->hv_clock, 1634 sizeof(vcpu->hv_clock)); 1635 return 0; 1636 } 1637 1638 /* 1639 * kvmclock updates which are isolated to a given vcpu, such as 1640 * vcpu->cpu migration, should not allow system_timestamp from 1641 * the rest of the vcpus to remain static. Otherwise ntp frequency 1642 * correction applies to one vcpu's system_timestamp but not 1643 * the others. 1644 * 1645 * So in those cases, request a kvmclock update for all vcpus. 1646 * We need to rate-limit these requests though, as they can 1647 * considerably slow guests that have a large number of vcpus. 1648 * The time for a remote vcpu to update its kvmclock is bound 1649 * by the delay we use to rate-limit the updates. 1650 */ 1651 1652 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 1653 1654 static void kvmclock_update_fn(struct work_struct *work) 1655 { 1656 int i; 1657 struct delayed_work *dwork = to_delayed_work(work); 1658 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1659 kvmclock_update_work); 1660 struct kvm *kvm = container_of(ka, struct kvm, arch); 1661 struct kvm_vcpu *vcpu; 1662 1663 kvm_for_each_vcpu(i, vcpu, kvm) { 1664 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests); 1665 kvm_vcpu_kick(vcpu); 1666 } 1667 } 1668 1669 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 1670 { 1671 struct kvm *kvm = v->kvm; 1672 1673 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests); 1674 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 1675 KVMCLOCK_UPDATE_DELAY); 1676 } 1677 1678 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 1679 1680 static void kvmclock_sync_fn(struct work_struct *work) 1681 { 1682 struct delayed_work *dwork = to_delayed_work(work); 1683 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1684 kvmclock_sync_work); 1685 struct kvm *kvm = container_of(ka, struct kvm, arch); 1686 1687 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 1688 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 1689 KVMCLOCK_SYNC_PERIOD); 1690 } 1691 1692 static bool msr_mtrr_valid(unsigned msr) 1693 { 1694 switch (msr) { 1695 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: 1696 case MSR_MTRRfix64K_00000: 1697 case MSR_MTRRfix16K_80000: 1698 case MSR_MTRRfix16K_A0000: 1699 case MSR_MTRRfix4K_C0000: 1700 case MSR_MTRRfix4K_C8000: 1701 case MSR_MTRRfix4K_D0000: 1702 case MSR_MTRRfix4K_D8000: 1703 case MSR_MTRRfix4K_E0000: 1704 case MSR_MTRRfix4K_E8000: 1705 case MSR_MTRRfix4K_F0000: 1706 case MSR_MTRRfix4K_F8000: 1707 case MSR_MTRRdefType: 1708 case MSR_IA32_CR_PAT: 1709 return true; 1710 case 0x2f8: 1711 return true; 1712 } 1713 return false; 1714 } 1715 1716 static bool valid_pat_type(unsigned t) 1717 { 1718 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ 1719 } 1720 1721 static bool valid_mtrr_type(unsigned t) 1722 { 1723 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ 1724 } 1725 1726 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1727 { 1728 int i; 1729 1730 if (!msr_mtrr_valid(msr)) 1731 return false; 1732 1733 if (msr == MSR_IA32_CR_PAT) { 1734 for (i = 0; i < 8; i++) 1735 if (!valid_pat_type((data >> (i * 8)) & 0xff)) 1736 return false; 1737 return true; 1738 } else if (msr == MSR_MTRRdefType) { 1739 if (data & ~0xcff) 1740 return false; 1741 return valid_mtrr_type(data & 0xff); 1742 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { 1743 for (i = 0; i < 8 ; i++) 1744 if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) 1745 return false; 1746 return true; 1747 } 1748 1749 /* variable MTRRs */ 1750 return valid_mtrr_type(data & 0xff); 1751 } 1752 1753 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1754 { 1755 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; 1756 1757 if (!mtrr_valid(vcpu, msr, data)) 1758 return 1; 1759 1760 if (msr == MSR_MTRRdefType) { 1761 vcpu->arch.mtrr_state.def_type = data; 1762 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; 1763 } else if (msr == MSR_MTRRfix64K_00000) 1764 p[0] = data; 1765 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) 1766 p[1 + msr - MSR_MTRRfix16K_80000] = data; 1767 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) 1768 p[3 + msr - MSR_MTRRfix4K_C0000] = data; 1769 else if (msr == MSR_IA32_CR_PAT) 1770 vcpu->arch.pat = data; 1771 else { /* Variable MTRRs */ 1772 int idx, is_mtrr_mask; 1773 u64 *pt; 1774 1775 idx = (msr - 0x200) / 2; 1776 is_mtrr_mask = msr - 0x200 - 2 * idx; 1777 if (!is_mtrr_mask) 1778 pt = 1779 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; 1780 else 1781 pt = 1782 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; 1783 *pt = data; 1784 } 1785 1786 kvm_mmu_reset_context(vcpu); 1787 return 0; 1788 } 1789 1790 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1791 { 1792 u64 mcg_cap = vcpu->arch.mcg_cap; 1793 unsigned bank_num = mcg_cap & 0xff; 1794 1795 switch (msr) { 1796 case MSR_IA32_MCG_STATUS: 1797 vcpu->arch.mcg_status = data; 1798 break; 1799 case MSR_IA32_MCG_CTL: 1800 if (!(mcg_cap & MCG_CTL_P)) 1801 return 1; 1802 if (data != 0 && data != ~(u64)0) 1803 return -1; 1804 vcpu->arch.mcg_ctl = data; 1805 break; 1806 default: 1807 if (msr >= MSR_IA32_MC0_CTL && 1808 msr < MSR_IA32_MC0_CTL + 4 * bank_num) { 1809 u32 offset = msr - MSR_IA32_MC0_CTL; 1810 /* only 0 or all 1s can be written to IA32_MCi_CTL 1811 * some Linux kernels though clear bit 10 in bank 4 to 1812 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 1813 * this to avoid an uncatched #GP in the guest 1814 */ 1815 if ((offset & 0x3) == 0 && 1816 data != 0 && (data | (1 << 10)) != ~(u64)0) 1817 return -1; 1818 vcpu->arch.mce_banks[offset] = data; 1819 break; 1820 } 1821 return 1; 1822 } 1823 return 0; 1824 } 1825 1826 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 1827 { 1828 struct kvm *kvm = vcpu->kvm; 1829 int lm = is_long_mode(vcpu); 1830 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 1831 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 1832 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 1833 : kvm->arch.xen_hvm_config.blob_size_32; 1834 u32 page_num = data & ~PAGE_MASK; 1835 u64 page_addr = data & PAGE_MASK; 1836 u8 *page; 1837 int r; 1838 1839 r = -E2BIG; 1840 if (page_num >= blob_size) 1841 goto out; 1842 r = -ENOMEM; 1843 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 1844 if (IS_ERR(page)) { 1845 r = PTR_ERR(page); 1846 goto out; 1847 } 1848 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) 1849 goto out_free; 1850 r = 0; 1851 out_free: 1852 kfree(page); 1853 out: 1854 return r; 1855 } 1856 1857 static bool kvm_hv_hypercall_enabled(struct kvm *kvm) 1858 { 1859 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; 1860 } 1861 1862 static bool kvm_hv_msr_partition_wide(u32 msr) 1863 { 1864 bool r = false; 1865 switch (msr) { 1866 case HV_X64_MSR_GUEST_OS_ID: 1867 case HV_X64_MSR_HYPERCALL: 1868 case HV_X64_MSR_REFERENCE_TSC: 1869 case HV_X64_MSR_TIME_REF_COUNT: 1870 r = true; 1871 break; 1872 } 1873 1874 return r; 1875 } 1876 1877 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1878 { 1879 struct kvm *kvm = vcpu->kvm; 1880 1881 switch (msr) { 1882 case HV_X64_MSR_GUEST_OS_ID: 1883 kvm->arch.hv_guest_os_id = data; 1884 /* setting guest os id to zero disables hypercall page */ 1885 if (!kvm->arch.hv_guest_os_id) 1886 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; 1887 break; 1888 case HV_X64_MSR_HYPERCALL: { 1889 u64 gfn; 1890 unsigned long addr; 1891 u8 instructions[4]; 1892 1893 /* if guest os id is not set hypercall should remain disabled */ 1894 if (!kvm->arch.hv_guest_os_id) 1895 break; 1896 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { 1897 kvm->arch.hv_hypercall = data; 1898 break; 1899 } 1900 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; 1901 addr = gfn_to_hva(kvm, gfn); 1902 if (kvm_is_error_hva(addr)) 1903 return 1; 1904 kvm_x86_ops->patch_hypercall(vcpu, instructions); 1905 ((unsigned char *)instructions)[3] = 0xc3; /* ret */ 1906 if (__copy_to_user((void __user *)addr, instructions, 4)) 1907 return 1; 1908 kvm->arch.hv_hypercall = data; 1909 mark_page_dirty(kvm, gfn); 1910 break; 1911 } 1912 case HV_X64_MSR_REFERENCE_TSC: { 1913 u64 gfn; 1914 HV_REFERENCE_TSC_PAGE tsc_ref; 1915 memset(&tsc_ref, 0, sizeof(tsc_ref)); 1916 kvm->arch.hv_tsc_page = data; 1917 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE)) 1918 break; 1919 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT; 1920 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT, 1921 &tsc_ref, sizeof(tsc_ref))) 1922 return 1; 1923 mark_page_dirty(kvm, gfn); 1924 break; 1925 } 1926 default: 1927 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " 1928 "data 0x%llx\n", msr, data); 1929 return 1; 1930 } 1931 return 0; 1932 } 1933 1934 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1935 { 1936 switch (msr) { 1937 case HV_X64_MSR_APIC_ASSIST_PAGE: { 1938 u64 gfn; 1939 unsigned long addr; 1940 1941 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { 1942 vcpu->arch.hv_vapic = data; 1943 if (kvm_lapic_enable_pv_eoi(vcpu, 0)) 1944 return 1; 1945 break; 1946 } 1947 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT; 1948 addr = gfn_to_hva(vcpu->kvm, gfn); 1949 if (kvm_is_error_hva(addr)) 1950 return 1; 1951 if (__clear_user((void __user *)addr, PAGE_SIZE)) 1952 return 1; 1953 vcpu->arch.hv_vapic = data; 1954 mark_page_dirty(vcpu->kvm, gfn); 1955 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED)) 1956 return 1; 1957 break; 1958 } 1959 case HV_X64_MSR_EOI: 1960 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); 1961 case HV_X64_MSR_ICR: 1962 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); 1963 case HV_X64_MSR_TPR: 1964 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); 1965 default: 1966 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " 1967 "data 0x%llx\n", msr, data); 1968 return 1; 1969 } 1970 1971 return 0; 1972 } 1973 1974 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 1975 { 1976 gpa_t gpa = data & ~0x3f; 1977 1978 /* Bits 2:5 are reserved, Should be zero */ 1979 if (data & 0x3c) 1980 return 1; 1981 1982 vcpu->arch.apf.msr_val = data; 1983 1984 if (!(data & KVM_ASYNC_PF_ENABLED)) { 1985 kvm_clear_async_pf_completion_queue(vcpu); 1986 kvm_async_pf_hash_reset(vcpu); 1987 return 0; 1988 } 1989 1990 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 1991 sizeof(u32))) 1992 return 1; 1993 1994 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 1995 kvm_async_pf_wakeup_all(vcpu); 1996 return 0; 1997 } 1998 1999 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2000 { 2001 vcpu->arch.pv_time_enabled = false; 2002 } 2003 2004 static void accumulate_steal_time(struct kvm_vcpu *vcpu) 2005 { 2006 u64 delta; 2007 2008 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2009 return; 2010 2011 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; 2012 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2013 vcpu->arch.st.accum_steal = delta; 2014 } 2015 2016 static void record_steal_time(struct kvm_vcpu *vcpu) 2017 { 2018 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2019 return; 2020 2021 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2022 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2023 return; 2024 2025 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; 2026 vcpu->arch.st.steal.version += 2; 2027 vcpu->arch.st.accum_steal = 0; 2028 2029 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2030 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2031 } 2032 2033 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2034 { 2035 bool pr = false; 2036 u32 msr = msr_info->index; 2037 u64 data = msr_info->data; 2038 2039 switch (msr) { 2040 case MSR_AMD64_NB_CFG: 2041 case MSR_IA32_UCODE_REV: 2042 case MSR_IA32_UCODE_WRITE: 2043 case MSR_VM_HSAVE_PA: 2044 case MSR_AMD64_PATCH_LOADER: 2045 case MSR_AMD64_BU_CFG2: 2046 break; 2047 2048 case MSR_EFER: 2049 return set_efer(vcpu, data); 2050 case MSR_K7_HWCR: 2051 data &= ~(u64)0x40; /* ignore flush filter disable */ 2052 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2053 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2054 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2055 if (data != 0) { 2056 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2057 data); 2058 return 1; 2059 } 2060 break; 2061 case MSR_FAM10H_MMIO_CONF_BASE: 2062 if (data != 0) { 2063 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2064 "0x%llx\n", data); 2065 return 1; 2066 } 2067 break; 2068 case MSR_IA32_DEBUGCTLMSR: 2069 if (!data) { 2070 /* We support the non-activated case already */ 2071 break; 2072 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2073 /* Values other than LBR and BTF are vendor-specific, 2074 thus reserved and should throw a #GP */ 2075 return 1; 2076 } 2077 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2078 __func__, data); 2079 break; 2080 case 0x200 ... 0x2ff: 2081 return set_msr_mtrr(vcpu, msr, data); 2082 case MSR_IA32_APICBASE: 2083 return kvm_set_apic_base(vcpu, msr_info); 2084 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2085 return kvm_x2apic_msr_write(vcpu, msr, data); 2086 case MSR_IA32_TSCDEADLINE: 2087 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2088 break; 2089 case MSR_IA32_TSC_ADJUST: 2090 if (guest_cpuid_has_tsc_adjust(vcpu)) { 2091 if (!msr_info->host_initiated) { 2092 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2093 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true); 2094 } 2095 vcpu->arch.ia32_tsc_adjust_msr = data; 2096 } 2097 break; 2098 case MSR_IA32_MISC_ENABLE: 2099 vcpu->arch.ia32_misc_enable_msr = data; 2100 break; 2101 case MSR_KVM_WALL_CLOCK_NEW: 2102 case MSR_KVM_WALL_CLOCK: 2103 vcpu->kvm->arch.wall_clock = data; 2104 kvm_write_wall_clock(vcpu->kvm, data); 2105 break; 2106 case MSR_KVM_SYSTEM_TIME_NEW: 2107 case MSR_KVM_SYSTEM_TIME: { 2108 u64 gpa_offset; 2109 kvmclock_reset(vcpu); 2110 2111 vcpu->arch.time = data; 2112 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2113 2114 /* we verify if the enable bit is set... */ 2115 if (!(data & 1)) 2116 break; 2117 2118 gpa_offset = data & ~(PAGE_MASK | 1); 2119 2120 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2121 &vcpu->arch.pv_time, data & ~1ULL, 2122 sizeof(struct pvclock_vcpu_time_info))) 2123 vcpu->arch.pv_time_enabled = false; 2124 else 2125 vcpu->arch.pv_time_enabled = true; 2126 2127 break; 2128 } 2129 case MSR_KVM_ASYNC_PF_EN: 2130 if (kvm_pv_enable_async_pf(vcpu, data)) 2131 return 1; 2132 break; 2133 case MSR_KVM_STEAL_TIME: 2134 2135 if (unlikely(!sched_info_on())) 2136 return 1; 2137 2138 if (data & KVM_STEAL_RESERVED_MASK) 2139 return 1; 2140 2141 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2142 data & KVM_STEAL_VALID_BITS, 2143 sizeof(struct kvm_steal_time))) 2144 return 1; 2145 2146 vcpu->arch.st.msr_val = data; 2147 2148 if (!(data & KVM_MSR_ENABLED)) 2149 break; 2150 2151 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2152 2153 preempt_disable(); 2154 accumulate_steal_time(vcpu); 2155 preempt_enable(); 2156 2157 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2158 2159 break; 2160 case MSR_KVM_PV_EOI_EN: 2161 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2162 return 1; 2163 break; 2164 2165 case MSR_IA32_MCG_CTL: 2166 case MSR_IA32_MCG_STATUS: 2167 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: 2168 return set_msr_mce(vcpu, msr, data); 2169 2170 /* Performance counters are not protected by a CPUID bit, 2171 * so we should check all of them in the generic path for the sake of 2172 * cross vendor migration. 2173 * Writing a zero into the event select MSRs disables them, 2174 * which we perfectly emulate ;-). Any other value should be at least 2175 * reported, some guests depend on them. 2176 */ 2177 case MSR_K7_EVNTSEL0: 2178 case MSR_K7_EVNTSEL1: 2179 case MSR_K7_EVNTSEL2: 2180 case MSR_K7_EVNTSEL3: 2181 if (data != 0) 2182 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " 2183 "0x%x data 0x%llx\n", msr, data); 2184 break; 2185 /* at least RHEL 4 unconditionally writes to the perfctr registers, 2186 * so we ignore writes to make it happy. 2187 */ 2188 case MSR_K7_PERFCTR0: 2189 case MSR_K7_PERFCTR1: 2190 case MSR_K7_PERFCTR2: 2191 case MSR_K7_PERFCTR3: 2192 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " 2193 "0x%x data 0x%llx\n", msr, data); 2194 break; 2195 case MSR_P6_PERFCTR0: 2196 case MSR_P6_PERFCTR1: 2197 pr = true; 2198 case MSR_P6_EVNTSEL0: 2199 case MSR_P6_EVNTSEL1: 2200 if (kvm_pmu_msr(vcpu, msr)) 2201 return kvm_pmu_set_msr(vcpu, msr_info); 2202 2203 if (pr || data != 0) 2204 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2205 "0x%x data 0x%llx\n", msr, data); 2206 break; 2207 case MSR_K7_CLK_CTL: 2208 /* 2209 * Ignore all writes to this no longer documented MSR. 2210 * Writes are only relevant for old K7 processors, 2211 * all pre-dating SVM, but a recommended workaround from 2212 * AMD for these chips. It is possible to specify the 2213 * affected processor models on the command line, hence 2214 * the need to ignore the workaround. 2215 */ 2216 break; 2217 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2218 if (kvm_hv_msr_partition_wide(msr)) { 2219 int r; 2220 mutex_lock(&vcpu->kvm->lock); 2221 r = set_msr_hyperv_pw(vcpu, msr, data); 2222 mutex_unlock(&vcpu->kvm->lock); 2223 return r; 2224 } else 2225 return set_msr_hyperv(vcpu, msr, data); 2226 break; 2227 case MSR_IA32_BBL_CR_CTL3: 2228 /* Drop writes to this legacy MSR -- see rdmsr 2229 * counterpart for further detail. 2230 */ 2231 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); 2232 break; 2233 case MSR_AMD64_OSVW_ID_LENGTH: 2234 if (!guest_cpuid_has_osvw(vcpu)) 2235 return 1; 2236 vcpu->arch.osvw.length = data; 2237 break; 2238 case MSR_AMD64_OSVW_STATUS: 2239 if (!guest_cpuid_has_osvw(vcpu)) 2240 return 1; 2241 vcpu->arch.osvw.status = data; 2242 break; 2243 default: 2244 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2245 return xen_hvm_config(vcpu, data); 2246 if (kvm_pmu_msr(vcpu, msr)) 2247 return kvm_pmu_set_msr(vcpu, msr_info); 2248 if (!ignore_msrs) { 2249 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", 2250 msr, data); 2251 return 1; 2252 } else { 2253 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", 2254 msr, data); 2255 break; 2256 } 2257 } 2258 return 0; 2259 } 2260 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2261 2262 2263 /* 2264 * Reads an msr value (of 'msr_index') into 'pdata'. 2265 * Returns 0 on success, non-0 otherwise. 2266 * Assumes vcpu_load() was already called. 2267 */ 2268 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) 2269 { 2270 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); 2271 } 2272 2273 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2274 { 2275 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; 2276 2277 if (!msr_mtrr_valid(msr)) 2278 return 1; 2279 2280 if (msr == MSR_MTRRdefType) 2281 *pdata = vcpu->arch.mtrr_state.def_type + 2282 (vcpu->arch.mtrr_state.enabled << 10); 2283 else if (msr == MSR_MTRRfix64K_00000) 2284 *pdata = p[0]; 2285 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) 2286 *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; 2287 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) 2288 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; 2289 else if (msr == MSR_IA32_CR_PAT) 2290 *pdata = vcpu->arch.pat; 2291 else { /* Variable MTRRs */ 2292 int idx, is_mtrr_mask; 2293 u64 *pt; 2294 2295 idx = (msr - 0x200) / 2; 2296 is_mtrr_mask = msr - 0x200 - 2 * idx; 2297 if (!is_mtrr_mask) 2298 pt = 2299 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; 2300 else 2301 pt = 2302 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; 2303 *pdata = *pt; 2304 } 2305 2306 return 0; 2307 } 2308 2309 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2310 { 2311 u64 data; 2312 u64 mcg_cap = vcpu->arch.mcg_cap; 2313 unsigned bank_num = mcg_cap & 0xff; 2314 2315 switch (msr) { 2316 case MSR_IA32_P5_MC_ADDR: 2317 case MSR_IA32_P5_MC_TYPE: 2318 data = 0; 2319 break; 2320 case MSR_IA32_MCG_CAP: 2321 data = vcpu->arch.mcg_cap; 2322 break; 2323 case MSR_IA32_MCG_CTL: 2324 if (!(mcg_cap & MCG_CTL_P)) 2325 return 1; 2326 data = vcpu->arch.mcg_ctl; 2327 break; 2328 case MSR_IA32_MCG_STATUS: 2329 data = vcpu->arch.mcg_status; 2330 break; 2331 default: 2332 if (msr >= MSR_IA32_MC0_CTL && 2333 msr < MSR_IA32_MC0_CTL + 4 * bank_num) { 2334 u32 offset = msr - MSR_IA32_MC0_CTL; 2335 data = vcpu->arch.mce_banks[offset]; 2336 break; 2337 } 2338 return 1; 2339 } 2340 *pdata = data; 2341 return 0; 2342 } 2343 2344 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2345 { 2346 u64 data = 0; 2347 struct kvm *kvm = vcpu->kvm; 2348 2349 switch (msr) { 2350 case HV_X64_MSR_GUEST_OS_ID: 2351 data = kvm->arch.hv_guest_os_id; 2352 break; 2353 case HV_X64_MSR_HYPERCALL: 2354 data = kvm->arch.hv_hypercall; 2355 break; 2356 case HV_X64_MSR_TIME_REF_COUNT: { 2357 data = 2358 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100); 2359 break; 2360 } 2361 case HV_X64_MSR_REFERENCE_TSC: 2362 data = kvm->arch.hv_tsc_page; 2363 break; 2364 default: 2365 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); 2366 return 1; 2367 } 2368 2369 *pdata = data; 2370 return 0; 2371 } 2372 2373 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2374 { 2375 u64 data = 0; 2376 2377 switch (msr) { 2378 case HV_X64_MSR_VP_INDEX: { 2379 int r; 2380 struct kvm_vcpu *v; 2381 kvm_for_each_vcpu(r, v, vcpu->kvm) { 2382 if (v == vcpu) { 2383 data = r; 2384 break; 2385 } 2386 } 2387 break; 2388 } 2389 case HV_X64_MSR_EOI: 2390 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); 2391 case HV_X64_MSR_ICR: 2392 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); 2393 case HV_X64_MSR_TPR: 2394 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); 2395 case HV_X64_MSR_APIC_ASSIST_PAGE: 2396 data = vcpu->arch.hv_vapic; 2397 break; 2398 default: 2399 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); 2400 return 1; 2401 } 2402 *pdata = data; 2403 return 0; 2404 } 2405 2406 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2407 { 2408 u64 data; 2409 2410 switch (msr) { 2411 case MSR_IA32_PLATFORM_ID: 2412 case MSR_IA32_EBL_CR_POWERON: 2413 case MSR_IA32_DEBUGCTLMSR: 2414 case MSR_IA32_LASTBRANCHFROMIP: 2415 case MSR_IA32_LASTBRANCHTOIP: 2416 case MSR_IA32_LASTINTFROMIP: 2417 case MSR_IA32_LASTINTTOIP: 2418 case MSR_K8_SYSCFG: 2419 case MSR_K7_HWCR: 2420 case MSR_VM_HSAVE_PA: 2421 case MSR_K7_EVNTSEL0: 2422 case MSR_K7_PERFCTR0: 2423 case MSR_K8_INT_PENDING_MSG: 2424 case MSR_AMD64_NB_CFG: 2425 case MSR_FAM10H_MMIO_CONF_BASE: 2426 case MSR_AMD64_BU_CFG2: 2427 data = 0; 2428 break; 2429 case MSR_P6_PERFCTR0: 2430 case MSR_P6_PERFCTR1: 2431 case MSR_P6_EVNTSEL0: 2432 case MSR_P6_EVNTSEL1: 2433 if (kvm_pmu_msr(vcpu, msr)) 2434 return kvm_pmu_get_msr(vcpu, msr, pdata); 2435 data = 0; 2436 break; 2437 case MSR_IA32_UCODE_REV: 2438 data = 0x100000000ULL; 2439 break; 2440 case MSR_MTRRcap: 2441 data = 0x500 | KVM_NR_VAR_MTRR; 2442 break; 2443 case 0x200 ... 0x2ff: 2444 return get_msr_mtrr(vcpu, msr, pdata); 2445 case 0xcd: /* fsb frequency */ 2446 data = 3; 2447 break; 2448 /* 2449 * MSR_EBC_FREQUENCY_ID 2450 * Conservative value valid for even the basic CPU models. 2451 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2452 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2453 * and 266MHz for model 3, or 4. Set Core Clock 2454 * Frequency to System Bus Frequency Ratio to 1 (bits 2455 * 31:24) even though these are only valid for CPU 2456 * models > 2, however guests may end up dividing or 2457 * multiplying by zero otherwise. 2458 */ 2459 case MSR_EBC_FREQUENCY_ID: 2460 data = 1 << 24; 2461 break; 2462 case MSR_IA32_APICBASE: 2463 data = kvm_get_apic_base(vcpu); 2464 break; 2465 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2466 return kvm_x2apic_msr_read(vcpu, msr, pdata); 2467 break; 2468 case MSR_IA32_TSCDEADLINE: 2469 data = kvm_get_lapic_tscdeadline_msr(vcpu); 2470 break; 2471 case MSR_IA32_TSC_ADJUST: 2472 data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2473 break; 2474 case MSR_IA32_MISC_ENABLE: 2475 data = vcpu->arch.ia32_misc_enable_msr; 2476 break; 2477 case MSR_IA32_PERF_STATUS: 2478 /* TSC increment by tick */ 2479 data = 1000ULL; 2480 /* CPU multiplier */ 2481 data |= (((uint64_t)4ULL) << 40); 2482 break; 2483 case MSR_EFER: 2484 data = vcpu->arch.efer; 2485 break; 2486 case MSR_KVM_WALL_CLOCK: 2487 case MSR_KVM_WALL_CLOCK_NEW: 2488 data = vcpu->kvm->arch.wall_clock; 2489 break; 2490 case MSR_KVM_SYSTEM_TIME: 2491 case MSR_KVM_SYSTEM_TIME_NEW: 2492 data = vcpu->arch.time; 2493 break; 2494 case MSR_KVM_ASYNC_PF_EN: 2495 data = vcpu->arch.apf.msr_val; 2496 break; 2497 case MSR_KVM_STEAL_TIME: 2498 data = vcpu->arch.st.msr_val; 2499 break; 2500 case MSR_KVM_PV_EOI_EN: 2501 data = vcpu->arch.pv_eoi.msr_val; 2502 break; 2503 case MSR_IA32_P5_MC_ADDR: 2504 case MSR_IA32_P5_MC_TYPE: 2505 case MSR_IA32_MCG_CAP: 2506 case MSR_IA32_MCG_CTL: 2507 case MSR_IA32_MCG_STATUS: 2508 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: 2509 return get_msr_mce(vcpu, msr, pdata); 2510 case MSR_K7_CLK_CTL: 2511 /* 2512 * Provide expected ramp-up count for K7. All other 2513 * are set to zero, indicating minimum divisors for 2514 * every field. 2515 * 2516 * This prevents guest kernels on AMD host with CPU 2517 * type 6, model 8 and higher from exploding due to 2518 * the rdmsr failing. 2519 */ 2520 data = 0x20000000; 2521 break; 2522 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2523 if (kvm_hv_msr_partition_wide(msr)) { 2524 int r; 2525 mutex_lock(&vcpu->kvm->lock); 2526 r = get_msr_hyperv_pw(vcpu, msr, pdata); 2527 mutex_unlock(&vcpu->kvm->lock); 2528 return r; 2529 } else 2530 return get_msr_hyperv(vcpu, msr, pdata); 2531 break; 2532 case MSR_IA32_BBL_CR_CTL3: 2533 /* This legacy MSR exists but isn't fully documented in current 2534 * silicon. It is however accessed by winxp in very narrow 2535 * scenarios where it sets bit #19, itself documented as 2536 * a "reserved" bit. Best effort attempt to source coherent 2537 * read data here should the balance of the register be 2538 * interpreted by the guest: 2539 * 2540 * L2 cache control register 3: 64GB range, 256KB size, 2541 * enabled, latency 0x1, configured 2542 */ 2543 data = 0xbe702111; 2544 break; 2545 case MSR_AMD64_OSVW_ID_LENGTH: 2546 if (!guest_cpuid_has_osvw(vcpu)) 2547 return 1; 2548 data = vcpu->arch.osvw.length; 2549 break; 2550 case MSR_AMD64_OSVW_STATUS: 2551 if (!guest_cpuid_has_osvw(vcpu)) 2552 return 1; 2553 data = vcpu->arch.osvw.status; 2554 break; 2555 default: 2556 if (kvm_pmu_msr(vcpu, msr)) 2557 return kvm_pmu_get_msr(vcpu, msr, pdata); 2558 if (!ignore_msrs) { 2559 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); 2560 return 1; 2561 } else { 2562 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); 2563 data = 0; 2564 } 2565 break; 2566 } 2567 *pdata = data; 2568 return 0; 2569 } 2570 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2571 2572 /* 2573 * Read or write a bunch of msrs. All parameters are kernel addresses. 2574 * 2575 * @return number of msrs set successfully. 2576 */ 2577 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2578 struct kvm_msr_entry *entries, 2579 int (*do_msr)(struct kvm_vcpu *vcpu, 2580 unsigned index, u64 *data)) 2581 { 2582 int i, idx; 2583 2584 idx = srcu_read_lock(&vcpu->kvm->srcu); 2585 for (i = 0; i < msrs->nmsrs; ++i) 2586 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2587 break; 2588 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2589 2590 return i; 2591 } 2592 2593 /* 2594 * Read or write a bunch of msrs. Parameters are user addresses. 2595 * 2596 * @return number of msrs set successfully. 2597 */ 2598 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2599 int (*do_msr)(struct kvm_vcpu *vcpu, 2600 unsigned index, u64 *data), 2601 int writeback) 2602 { 2603 struct kvm_msrs msrs; 2604 struct kvm_msr_entry *entries; 2605 int r, n; 2606 unsigned size; 2607 2608 r = -EFAULT; 2609 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2610 goto out; 2611 2612 r = -E2BIG; 2613 if (msrs.nmsrs >= MAX_IO_MSRS) 2614 goto out; 2615 2616 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2617 entries = memdup_user(user_msrs->entries, size); 2618 if (IS_ERR(entries)) { 2619 r = PTR_ERR(entries); 2620 goto out; 2621 } 2622 2623 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2624 if (r < 0) 2625 goto out_free; 2626 2627 r = -EFAULT; 2628 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2629 goto out_free; 2630 2631 r = n; 2632 2633 out_free: 2634 kfree(entries); 2635 out: 2636 return r; 2637 } 2638 2639 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2640 { 2641 int r; 2642 2643 switch (ext) { 2644 case KVM_CAP_IRQCHIP: 2645 case KVM_CAP_HLT: 2646 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2647 case KVM_CAP_SET_TSS_ADDR: 2648 case KVM_CAP_EXT_CPUID: 2649 case KVM_CAP_EXT_EMUL_CPUID: 2650 case KVM_CAP_CLOCKSOURCE: 2651 case KVM_CAP_PIT: 2652 case KVM_CAP_NOP_IO_DELAY: 2653 case KVM_CAP_MP_STATE: 2654 case KVM_CAP_SYNC_MMU: 2655 case KVM_CAP_USER_NMI: 2656 case KVM_CAP_REINJECT_CONTROL: 2657 case KVM_CAP_IRQ_INJECT_STATUS: 2658 case KVM_CAP_IRQFD: 2659 case KVM_CAP_IOEVENTFD: 2660 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2661 case KVM_CAP_PIT2: 2662 case KVM_CAP_PIT_STATE2: 2663 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2664 case KVM_CAP_XEN_HVM: 2665 case KVM_CAP_ADJUST_CLOCK: 2666 case KVM_CAP_VCPU_EVENTS: 2667 case KVM_CAP_HYPERV: 2668 case KVM_CAP_HYPERV_VAPIC: 2669 case KVM_CAP_HYPERV_SPIN: 2670 case KVM_CAP_PCI_SEGMENT: 2671 case KVM_CAP_DEBUGREGS: 2672 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2673 case KVM_CAP_XSAVE: 2674 case KVM_CAP_ASYNC_PF: 2675 case KVM_CAP_GET_TSC_KHZ: 2676 case KVM_CAP_KVMCLOCK_CTRL: 2677 case KVM_CAP_READONLY_MEM: 2678 case KVM_CAP_HYPERV_TIME: 2679 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2680 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2681 case KVM_CAP_ASSIGN_DEV_IRQ: 2682 case KVM_CAP_PCI_2_3: 2683 #endif 2684 r = 1; 2685 break; 2686 case KVM_CAP_COALESCED_MMIO: 2687 r = KVM_COALESCED_MMIO_PAGE_OFFSET; 2688 break; 2689 case KVM_CAP_VAPIC: 2690 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2691 break; 2692 case KVM_CAP_NR_VCPUS: 2693 r = KVM_SOFT_MAX_VCPUS; 2694 break; 2695 case KVM_CAP_MAX_VCPUS: 2696 r = KVM_MAX_VCPUS; 2697 break; 2698 case KVM_CAP_NR_MEMSLOTS: 2699 r = KVM_USER_MEM_SLOTS; 2700 break; 2701 case KVM_CAP_PV_MMU: /* obsolete */ 2702 r = 0; 2703 break; 2704 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2705 case KVM_CAP_IOMMU: 2706 r = iommu_present(&pci_bus_type); 2707 break; 2708 #endif 2709 case KVM_CAP_MCE: 2710 r = KVM_MAX_MCE_BANKS; 2711 break; 2712 case KVM_CAP_XCRS: 2713 r = cpu_has_xsave; 2714 break; 2715 case KVM_CAP_TSC_CONTROL: 2716 r = kvm_has_tsc_control; 2717 break; 2718 case KVM_CAP_TSC_DEADLINE_TIMER: 2719 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER); 2720 break; 2721 default: 2722 r = 0; 2723 break; 2724 } 2725 return r; 2726 2727 } 2728 2729 long kvm_arch_dev_ioctl(struct file *filp, 2730 unsigned int ioctl, unsigned long arg) 2731 { 2732 void __user *argp = (void __user *)arg; 2733 long r; 2734 2735 switch (ioctl) { 2736 case KVM_GET_MSR_INDEX_LIST: { 2737 struct kvm_msr_list __user *user_msr_list = argp; 2738 struct kvm_msr_list msr_list; 2739 unsigned n; 2740 2741 r = -EFAULT; 2742 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2743 goto out; 2744 n = msr_list.nmsrs; 2745 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); 2746 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2747 goto out; 2748 r = -E2BIG; 2749 if (n < msr_list.nmsrs) 2750 goto out; 2751 r = -EFAULT; 2752 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2753 num_msrs_to_save * sizeof(u32))) 2754 goto out; 2755 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2756 &emulated_msrs, 2757 ARRAY_SIZE(emulated_msrs) * sizeof(u32))) 2758 goto out; 2759 r = 0; 2760 break; 2761 } 2762 case KVM_GET_SUPPORTED_CPUID: 2763 case KVM_GET_EMULATED_CPUID: { 2764 struct kvm_cpuid2 __user *cpuid_arg = argp; 2765 struct kvm_cpuid2 cpuid; 2766 2767 r = -EFAULT; 2768 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2769 goto out; 2770 2771 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2772 ioctl); 2773 if (r) 2774 goto out; 2775 2776 r = -EFAULT; 2777 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2778 goto out; 2779 r = 0; 2780 break; 2781 } 2782 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2783 u64 mce_cap; 2784 2785 mce_cap = KVM_MCE_CAP_SUPPORTED; 2786 r = -EFAULT; 2787 if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) 2788 goto out; 2789 r = 0; 2790 break; 2791 } 2792 default: 2793 r = -EINVAL; 2794 } 2795 out: 2796 return r; 2797 } 2798 2799 static void wbinvd_ipi(void *garbage) 2800 { 2801 wbinvd(); 2802 } 2803 2804 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 2805 { 2806 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 2807 } 2808 2809 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 2810 { 2811 /* Address WBINVD may be executed by guest */ 2812 if (need_emulate_wbinvd(vcpu)) { 2813 if (kvm_x86_ops->has_wbinvd_exit()) 2814 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 2815 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 2816 smp_call_function_single(vcpu->cpu, 2817 wbinvd_ipi, NULL, 1); 2818 } 2819 2820 kvm_x86_ops->vcpu_load(vcpu, cpu); 2821 2822 /* Apply any externally detected TSC adjustments (due to suspend) */ 2823 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 2824 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 2825 vcpu->arch.tsc_offset_adjustment = 0; 2826 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests); 2827 } 2828 2829 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { 2830 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 2831 native_read_tsc() - vcpu->arch.last_host_tsc; 2832 if (tsc_delta < 0) 2833 mark_tsc_unstable("KVM discovered backwards TSC"); 2834 if (check_tsc_unstable()) { 2835 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu, 2836 vcpu->arch.last_guest_tsc); 2837 kvm_x86_ops->write_tsc_offset(vcpu, offset); 2838 vcpu->arch.tsc_catchup = 1; 2839 } 2840 /* 2841 * On a host with synchronized TSC, there is no need to update 2842 * kvmclock on vcpu->cpu migration 2843 */ 2844 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 2845 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2846 if (vcpu->cpu != cpu) 2847 kvm_migrate_timers(vcpu); 2848 vcpu->cpu = cpu; 2849 } 2850 2851 accumulate_steal_time(vcpu); 2852 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2853 } 2854 2855 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 2856 { 2857 kvm_x86_ops->vcpu_put(vcpu); 2858 kvm_put_guest_fpu(vcpu); 2859 vcpu->arch.last_host_tsc = native_read_tsc(); 2860 } 2861 2862 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 2863 struct kvm_lapic_state *s) 2864 { 2865 kvm_x86_ops->sync_pir_to_irr(vcpu); 2866 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); 2867 2868 return 0; 2869 } 2870 2871 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 2872 struct kvm_lapic_state *s) 2873 { 2874 kvm_apic_post_state_restore(vcpu, s); 2875 update_cr8_intercept(vcpu); 2876 2877 return 0; 2878 } 2879 2880 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 2881 struct kvm_interrupt *irq) 2882 { 2883 if (irq->irq >= KVM_NR_INTERRUPTS) 2884 return -EINVAL; 2885 if (irqchip_in_kernel(vcpu->kvm)) 2886 return -ENXIO; 2887 2888 kvm_queue_interrupt(vcpu, irq->irq, false); 2889 kvm_make_request(KVM_REQ_EVENT, vcpu); 2890 2891 return 0; 2892 } 2893 2894 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 2895 { 2896 kvm_inject_nmi(vcpu); 2897 2898 return 0; 2899 } 2900 2901 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 2902 struct kvm_tpr_access_ctl *tac) 2903 { 2904 if (tac->flags) 2905 return -EINVAL; 2906 vcpu->arch.tpr_access_reporting = !!tac->enabled; 2907 return 0; 2908 } 2909 2910 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 2911 u64 mcg_cap) 2912 { 2913 int r; 2914 unsigned bank_num = mcg_cap & 0xff, bank; 2915 2916 r = -EINVAL; 2917 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 2918 goto out; 2919 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) 2920 goto out; 2921 r = 0; 2922 vcpu->arch.mcg_cap = mcg_cap; 2923 /* Init IA32_MCG_CTL to all 1s */ 2924 if (mcg_cap & MCG_CTL_P) 2925 vcpu->arch.mcg_ctl = ~(u64)0; 2926 /* Init IA32_MCi_CTL to all 1s */ 2927 for (bank = 0; bank < bank_num; bank++) 2928 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 2929 out: 2930 return r; 2931 } 2932 2933 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 2934 struct kvm_x86_mce *mce) 2935 { 2936 u64 mcg_cap = vcpu->arch.mcg_cap; 2937 unsigned bank_num = mcg_cap & 0xff; 2938 u64 *banks = vcpu->arch.mce_banks; 2939 2940 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 2941 return -EINVAL; 2942 /* 2943 * if IA32_MCG_CTL is not all 1s, the uncorrected error 2944 * reporting is disabled 2945 */ 2946 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 2947 vcpu->arch.mcg_ctl != ~(u64)0) 2948 return 0; 2949 banks += 4 * mce->bank; 2950 /* 2951 * if IA32_MCi_CTL is not all 1s, the uncorrected error 2952 * reporting is disabled for the bank 2953 */ 2954 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 2955 return 0; 2956 if (mce->status & MCI_STATUS_UC) { 2957 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 2958 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 2959 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 2960 return 0; 2961 } 2962 if (banks[1] & MCI_STATUS_VAL) 2963 mce->status |= MCI_STATUS_OVER; 2964 banks[2] = mce->addr; 2965 banks[3] = mce->misc; 2966 vcpu->arch.mcg_status = mce->mcg_status; 2967 banks[1] = mce->status; 2968 kvm_queue_exception(vcpu, MC_VECTOR); 2969 } else if (!(banks[1] & MCI_STATUS_VAL) 2970 || !(banks[1] & MCI_STATUS_UC)) { 2971 if (banks[1] & MCI_STATUS_VAL) 2972 mce->status |= MCI_STATUS_OVER; 2973 banks[2] = mce->addr; 2974 banks[3] = mce->misc; 2975 banks[1] = mce->status; 2976 } else 2977 banks[1] |= MCI_STATUS_OVER; 2978 return 0; 2979 } 2980 2981 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 2982 struct kvm_vcpu_events *events) 2983 { 2984 process_nmi(vcpu); 2985 events->exception.injected = 2986 vcpu->arch.exception.pending && 2987 !kvm_exception_is_soft(vcpu->arch.exception.nr); 2988 events->exception.nr = vcpu->arch.exception.nr; 2989 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 2990 events->exception.pad = 0; 2991 events->exception.error_code = vcpu->arch.exception.error_code; 2992 2993 events->interrupt.injected = 2994 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; 2995 events->interrupt.nr = vcpu->arch.interrupt.nr; 2996 events->interrupt.soft = 0; 2997 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 2998 2999 events->nmi.injected = vcpu->arch.nmi_injected; 3000 events->nmi.pending = vcpu->arch.nmi_pending != 0; 3001 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 3002 events->nmi.pad = 0; 3003 3004 events->sipi_vector = 0; /* never valid when reporting to user space */ 3005 3006 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 3007 | KVM_VCPUEVENT_VALID_SHADOW); 3008 memset(&events->reserved, 0, sizeof(events->reserved)); 3009 } 3010 3011 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 3012 struct kvm_vcpu_events *events) 3013 { 3014 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 3015 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 3016 | KVM_VCPUEVENT_VALID_SHADOW)) 3017 return -EINVAL; 3018 3019 process_nmi(vcpu); 3020 vcpu->arch.exception.pending = events->exception.injected; 3021 vcpu->arch.exception.nr = events->exception.nr; 3022 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 3023 vcpu->arch.exception.error_code = events->exception.error_code; 3024 3025 vcpu->arch.interrupt.pending = events->interrupt.injected; 3026 vcpu->arch.interrupt.nr = events->interrupt.nr; 3027 vcpu->arch.interrupt.soft = events->interrupt.soft; 3028 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3029 kvm_x86_ops->set_interrupt_shadow(vcpu, 3030 events->interrupt.shadow); 3031 3032 vcpu->arch.nmi_injected = events->nmi.injected; 3033 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3034 vcpu->arch.nmi_pending = events->nmi.pending; 3035 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 3036 3037 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3038 kvm_vcpu_has_lapic(vcpu)) 3039 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3040 3041 kvm_make_request(KVM_REQ_EVENT, vcpu); 3042 3043 return 0; 3044 } 3045 3046 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3047 struct kvm_debugregs *dbgregs) 3048 { 3049 unsigned long val; 3050 3051 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3052 _kvm_get_dr(vcpu, 6, &val); 3053 dbgregs->dr6 = val; 3054 dbgregs->dr7 = vcpu->arch.dr7; 3055 dbgregs->flags = 0; 3056 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3057 } 3058 3059 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3060 struct kvm_debugregs *dbgregs) 3061 { 3062 if (dbgregs->flags) 3063 return -EINVAL; 3064 3065 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3066 vcpu->arch.dr6 = dbgregs->dr6; 3067 kvm_update_dr6(vcpu); 3068 vcpu->arch.dr7 = dbgregs->dr7; 3069 kvm_update_dr7(vcpu); 3070 3071 return 0; 3072 } 3073 3074 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3075 struct kvm_xsave *guest_xsave) 3076 { 3077 if (cpu_has_xsave) { 3078 memcpy(guest_xsave->region, 3079 &vcpu->arch.guest_fpu.state->xsave, 3080 vcpu->arch.guest_xstate_size); 3081 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &= 3082 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE; 3083 } else { 3084 memcpy(guest_xsave->region, 3085 &vcpu->arch.guest_fpu.state->fxsave, 3086 sizeof(struct i387_fxsave_struct)); 3087 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3088 XSTATE_FPSSE; 3089 } 3090 } 3091 3092 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3093 struct kvm_xsave *guest_xsave) 3094 { 3095 u64 xstate_bv = 3096 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3097 3098 if (cpu_has_xsave) { 3099 /* 3100 * Here we allow setting states that are not present in 3101 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3102 * with old userspace. 3103 */ 3104 if (xstate_bv & ~kvm_supported_xcr0()) 3105 return -EINVAL; 3106 memcpy(&vcpu->arch.guest_fpu.state->xsave, 3107 guest_xsave->region, vcpu->arch.guest_xstate_size); 3108 } else { 3109 if (xstate_bv & ~XSTATE_FPSSE) 3110 return -EINVAL; 3111 memcpy(&vcpu->arch.guest_fpu.state->fxsave, 3112 guest_xsave->region, sizeof(struct i387_fxsave_struct)); 3113 } 3114 return 0; 3115 } 3116 3117 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3118 struct kvm_xcrs *guest_xcrs) 3119 { 3120 if (!cpu_has_xsave) { 3121 guest_xcrs->nr_xcrs = 0; 3122 return; 3123 } 3124 3125 guest_xcrs->nr_xcrs = 1; 3126 guest_xcrs->flags = 0; 3127 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3128 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3129 } 3130 3131 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3132 struct kvm_xcrs *guest_xcrs) 3133 { 3134 int i, r = 0; 3135 3136 if (!cpu_has_xsave) 3137 return -EINVAL; 3138 3139 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3140 return -EINVAL; 3141 3142 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3143 /* Only support XCR0 currently */ 3144 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3145 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3146 guest_xcrs->xcrs[i].value); 3147 break; 3148 } 3149 if (r) 3150 r = -EINVAL; 3151 return r; 3152 } 3153 3154 /* 3155 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3156 * stopped by the hypervisor. This function will be called from the host only. 3157 * EINVAL is returned when the host attempts to set the flag for a guest that 3158 * does not support pv clocks. 3159 */ 3160 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3161 { 3162 if (!vcpu->arch.pv_time_enabled) 3163 return -EINVAL; 3164 vcpu->arch.pvclock_set_guest_stopped_request = true; 3165 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3166 return 0; 3167 } 3168 3169 long kvm_arch_vcpu_ioctl(struct file *filp, 3170 unsigned int ioctl, unsigned long arg) 3171 { 3172 struct kvm_vcpu *vcpu = filp->private_data; 3173 void __user *argp = (void __user *)arg; 3174 int r; 3175 union { 3176 struct kvm_lapic_state *lapic; 3177 struct kvm_xsave *xsave; 3178 struct kvm_xcrs *xcrs; 3179 void *buffer; 3180 } u; 3181 3182 u.buffer = NULL; 3183 switch (ioctl) { 3184 case KVM_GET_LAPIC: { 3185 r = -EINVAL; 3186 if (!vcpu->arch.apic) 3187 goto out; 3188 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3189 3190 r = -ENOMEM; 3191 if (!u.lapic) 3192 goto out; 3193 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3194 if (r) 3195 goto out; 3196 r = -EFAULT; 3197 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3198 goto out; 3199 r = 0; 3200 break; 3201 } 3202 case KVM_SET_LAPIC: { 3203 r = -EINVAL; 3204 if (!vcpu->arch.apic) 3205 goto out; 3206 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3207 if (IS_ERR(u.lapic)) 3208 return PTR_ERR(u.lapic); 3209 3210 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3211 break; 3212 } 3213 case KVM_INTERRUPT: { 3214 struct kvm_interrupt irq; 3215 3216 r = -EFAULT; 3217 if (copy_from_user(&irq, argp, sizeof irq)) 3218 goto out; 3219 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3220 break; 3221 } 3222 case KVM_NMI: { 3223 r = kvm_vcpu_ioctl_nmi(vcpu); 3224 break; 3225 } 3226 case KVM_SET_CPUID: { 3227 struct kvm_cpuid __user *cpuid_arg = argp; 3228 struct kvm_cpuid cpuid; 3229 3230 r = -EFAULT; 3231 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3232 goto out; 3233 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3234 break; 3235 } 3236 case KVM_SET_CPUID2: { 3237 struct kvm_cpuid2 __user *cpuid_arg = argp; 3238 struct kvm_cpuid2 cpuid; 3239 3240 r = -EFAULT; 3241 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3242 goto out; 3243 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3244 cpuid_arg->entries); 3245 break; 3246 } 3247 case KVM_GET_CPUID2: { 3248 struct kvm_cpuid2 __user *cpuid_arg = argp; 3249 struct kvm_cpuid2 cpuid; 3250 3251 r = -EFAULT; 3252 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3253 goto out; 3254 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3255 cpuid_arg->entries); 3256 if (r) 3257 goto out; 3258 r = -EFAULT; 3259 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3260 goto out; 3261 r = 0; 3262 break; 3263 } 3264 case KVM_GET_MSRS: 3265 r = msr_io(vcpu, argp, kvm_get_msr, 1); 3266 break; 3267 case KVM_SET_MSRS: 3268 r = msr_io(vcpu, argp, do_set_msr, 0); 3269 break; 3270 case KVM_TPR_ACCESS_REPORTING: { 3271 struct kvm_tpr_access_ctl tac; 3272 3273 r = -EFAULT; 3274 if (copy_from_user(&tac, argp, sizeof tac)) 3275 goto out; 3276 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3277 if (r) 3278 goto out; 3279 r = -EFAULT; 3280 if (copy_to_user(argp, &tac, sizeof tac)) 3281 goto out; 3282 r = 0; 3283 break; 3284 }; 3285 case KVM_SET_VAPIC_ADDR: { 3286 struct kvm_vapic_addr va; 3287 3288 r = -EINVAL; 3289 if (!irqchip_in_kernel(vcpu->kvm)) 3290 goto out; 3291 r = -EFAULT; 3292 if (copy_from_user(&va, argp, sizeof va)) 3293 goto out; 3294 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3295 break; 3296 } 3297 case KVM_X86_SETUP_MCE: { 3298 u64 mcg_cap; 3299 3300 r = -EFAULT; 3301 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3302 goto out; 3303 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3304 break; 3305 } 3306 case KVM_X86_SET_MCE: { 3307 struct kvm_x86_mce mce; 3308 3309 r = -EFAULT; 3310 if (copy_from_user(&mce, argp, sizeof mce)) 3311 goto out; 3312 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3313 break; 3314 } 3315 case KVM_GET_VCPU_EVENTS: { 3316 struct kvm_vcpu_events events; 3317 3318 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3319 3320 r = -EFAULT; 3321 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3322 break; 3323 r = 0; 3324 break; 3325 } 3326 case KVM_SET_VCPU_EVENTS: { 3327 struct kvm_vcpu_events events; 3328 3329 r = -EFAULT; 3330 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3331 break; 3332 3333 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3334 break; 3335 } 3336 case KVM_GET_DEBUGREGS: { 3337 struct kvm_debugregs dbgregs; 3338 3339 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3340 3341 r = -EFAULT; 3342 if (copy_to_user(argp, &dbgregs, 3343 sizeof(struct kvm_debugregs))) 3344 break; 3345 r = 0; 3346 break; 3347 } 3348 case KVM_SET_DEBUGREGS: { 3349 struct kvm_debugregs dbgregs; 3350 3351 r = -EFAULT; 3352 if (copy_from_user(&dbgregs, argp, 3353 sizeof(struct kvm_debugregs))) 3354 break; 3355 3356 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3357 break; 3358 } 3359 case KVM_GET_XSAVE: { 3360 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3361 r = -ENOMEM; 3362 if (!u.xsave) 3363 break; 3364 3365 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3366 3367 r = -EFAULT; 3368 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3369 break; 3370 r = 0; 3371 break; 3372 } 3373 case KVM_SET_XSAVE: { 3374 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3375 if (IS_ERR(u.xsave)) 3376 return PTR_ERR(u.xsave); 3377 3378 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3379 break; 3380 } 3381 case KVM_GET_XCRS: { 3382 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3383 r = -ENOMEM; 3384 if (!u.xcrs) 3385 break; 3386 3387 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3388 3389 r = -EFAULT; 3390 if (copy_to_user(argp, u.xcrs, 3391 sizeof(struct kvm_xcrs))) 3392 break; 3393 r = 0; 3394 break; 3395 } 3396 case KVM_SET_XCRS: { 3397 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3398 if (IS_ERR(u.xcrs)) 3399 return PTR_ERR(u.xcrs); 3400 3401 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3402 break; 3403 } 3404 case KVM_SET_TSC_KHZ: { 3405 u32 user_tsc_khz; 3406 3407 r = -EINVAL; 3408 user_tsc_khz = (u32)arg; 3409 3410 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3411 goto out; 3412 3413 if (user_tsc_khz == 0) 3414 user_tsc_khz = tsc_khz; 3415 3416 kvm_set_tsc_khz(vcpu, user_tsc_khz); 3417 3418 r = 0; 3419 goto out; 3420 } 3421 case KVM_GET_TSC_KHZ: { 3422 r = vcpu->arch.virtual_tsc_khz; 3423 goto out; 3424 } 3425 case KVM_KVMCLOCK_CTRL: { 3426 r = kvm_set_guest_paused(vcpu); 3427 goto out; 3428 } 3429 default: 3430 r = -EINVAL; 3431 } 3432 out: 3433 kfree(u.buffer); 3434 return r; 3435 } 3436 3437 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3438 { 3439 return VM_FAULT_SIGBUS; 3440 } 3441 3442 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3443 { 3444 int ret; 3445 3446 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3447 return -EINVAL; 3448 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3449 return ret; 3450 } 3451 3452 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3453 u64 ident_addr) 3454 { 3455 kvm->arch.ept_identity_map_addr = ident_addr; 3456 return 0; 3457 } 3458 3459 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3460 u32 kvm_nr_mmu_pages) 3461 { 3462 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3463 return -EINVAL; 3464 3465 mutex_lock(&kvm->slots_lock); 3466 3467 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3468 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3469 3470 mutex_unlock(&kvm->slots_lock); 3471 return 0; 3472 } 3473 3474 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 3475 { 3476 return kvm->arch.n_max_mmu_pages; 3477 } 3478 3479 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3480 { 3481 int r; 3482 3483 r = 0; 3484 switch (chip->chip_id) { 3485 case KVM_IRQCHIP_PIC_MASTER: 3486 memcpy(&chip->chip.pic, 3487 &pic_irqchip(kvm)->pics[0], 3488 sizeof(struct kvm_pic_state)); 3489 break; 3490 case KVM_IRQCHIP_PIC_SLAVE: 3491 memcpy(&chip->chip.pic, 3492 &pic_irqchip(kvm)->pics[1], 3493 sizeof(struct kvm_pic_state)); 3494 break; 3495 case KVM_IRQCHIP_IOAPIC: 3496 r = kvm_get_ioapic(kvm, &chip->chip.ioapic); 3497 break; 3498 default: 3499 r = -EINVAL; 3500 break; 3501 } 3502 return r; 3503 } 3504 3505 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3506 { 3507 int r; 3508 3509 r = 0; 3510 switch (chip->chip_id) { 3511 case KVM_IRQCHIP_PIC_MASTER: 3512 spin_lock(&pic_irqchip(kvm)->lock); 3513 memcpy(&pic_irqchip(kvm)->pics[0], 3514 &chip->chip.pic, 3515 sizeof(struct kvm_pic_state)); 3516 spin_unlock(&pic_irqchip(kvm)->lock); 3517 break; 3518 case KVM_IRQCHIP_PIC_SLAVE: 3519 spin_lock(&pic_irqchip(kvm)->lock); 3520 memcpy(&pic_irqchip(kvm)->pics[1], 3521 &chip->chip.pic, 3522 sizeof(struct kvm_pic_state)); 3523 spin_unlock(&pic_irqchip(kvm)->lock); 3524 break; 3525 case KVM_IRQCHIP_IOAPIC: 3526 r = kvm_set_ioapic(kvm, &chip->chip.ioapic); 3527 break; 3528 default: 3529 r = -EINVAL; 3530 break; 3531 } 3532 kvm_pic_update_irq(pic_irqchip(kvm)); 3533 return r; 3534 } 3535 3536 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3537 { 3538 int r = 0; 3539 3540 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3541 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); 3542 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3543 return r; 3544 } 3545 3546 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3547 { 3548 int r = 0; 3549 3550 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3551 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); 3552 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); 3553 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3554 return r; 3555 } 3556 3557 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3558 { 3559 int r = 0; 3560 3561 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3562 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 3563 sizeof(ps->channels)); 3564 ps->flags = kvm->arch.vpit->pit_state.flags; 3565 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3566 memset(&ps->reserved, 0, sizeof(ps->reserved)); 3567 return r; 3568 } 3569 3570 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3571 { 3572 int r = 0, start = 0; 3573 u32 prev_legacy, cur_legacy; 3574 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3575 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 3576 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 3577 if (!prev_legacy && cur_legacy) 3578 start = 1; 3579 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, 3580 sizeof(kvm->arch.vpit->pit_state.channels)); 3581 kvm->arch.vpit->pit_state.flags = ps->flags; 3582 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); 3583 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3584 return r; 3585 } 3586 3587 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 3588 struct kvm_reinject_control *control) 3589 { 3590 if (!kvm->arch.vpit) 3591 return -ENXIO; 3592 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3593 kvm->arch.vpit->pit_state.reinject = control->pit_reinject; 3594 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3595 return 0; 3596 } 3597 3598 /** 3599 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 3600 * @kvm: kvm instance 3601 * @log: slot id and address to which we copy the log 3602 * 3603 * We need to keep it in mind that VCPU threads can write to the bitmap 3604 * concurrently. So, to avoid losing data, we keep the following order for 3605 * each bit: 3606 * 3607 * 1. Take a snapshot of the bit and clear it if needed. 3608 * 2. Write protect the corresponding page. 3609 * 3. Flush TLB's if needed. 3610 * 4. Copy the snapshot to the userspace. 3611 * 3612 * Between 2 and 3, the guest may write to the page using the remaining TLB 3613 * entry. This is not a problem because the page will be reported dirty at 3614 * step 4 using the snapshot taken before and step 3 ensures that successive 3615 * writes will be logged for the next call. 3616 */ 3617 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 3618 { 3619 int r; 3620 struct kvm_memory_slot *memslot; 3621 unsigned long n, i; 3622 unsigned long *dirty_bitmap; 3623 unsigned long *dirty_bitmap_buffer; 3624 bool is_dirty = false; 3625 3626 mutex_lock(&kvm->slots_lock); 3627 3628 r = -EINVAL; 3629 if (log->slot >= KVM_USER_MEM_SLOTS) 3630 goto out; 3631 3632 memslot = id_to_memslot(kvm->memslots, log->slot); 3633 3634 dirty_bitmap = memslot->dirty_bitmap; 3635 r = -ENOENT; 3636 if (!dirty_bitmap) 3637 goto out; 3638 3639 n = kvm_dirty_bitmap_bytes(memslot); 3640 3641 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long); 3642 memset(dirty_bitmap_buffer, 0, n); 3643 3644 spin_lock(&kvm->mmu_lock); 3645 3646 for (i = 0; i < n / sizeof(long); i++) { 3647 unsigned long mask; 3648 gfn_t offset; 3649 3650 if (!dirty_bitmap[i]) 3651 continue; 3652 3653 is_dirty = true; 3654 3655 mask = xchg(&dirty_bitmap[i], 0); 3656 dirty_bitmap_buffer[i] = mask; 3657 3658 offset = i * BITS_PER_LONG; 3659 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask); 3660 } 3661 3662 spin_unlock(&kvm->mmu_lock); 3663 3664 /* See the comments in kvm_mmu_slot_remove_write_access(). */ 3665 lockdep_assert_held(&kvm->slots_lock); 3666 3667 /* 3668 * All the TLBs can be flushed out of mmu lock, see the comments in 3669 * kvm_mmu_slot_remove_write_access(). 3670 */ 3671 if (is_dirty) 3672 kvm_flush_remote_tlbs(kvm); 3673 3674 r = -EFAULT; 3675 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n)) 3676 goto out; 3677 3678 r = 0; 3679 out: 3680 mutex_unlock(&kvm->slots_lock); 3681 return r; 3682 } 3683 3684 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 3685 bool line_status) 3686 { 3687 if (!irqchip_in_kernel(kvm)) 3688 return -ENXIO; 3689 3690 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 3691 irq_event->irq, irq_event->level, 3692 line_status); 3693 return 0; 3694 } 3695 3696 long kvm_arch_vm_ioctl(struct file *filp, 3697 unsigned int ioctl, unsigned long arg) 3698 { 3699 struct kvm *kvm = filp->private_data; 3700 void __user *argp = (void __user *)arg; 3701 int r = -ENOTTY; 3702 /* 3703 * This union makes it completely explicit to gcc-3.x 3704 * that these two variables' stack usage should be 3705 * combined, not added together. 3706 */ 3707 union { 3708 struct kvm_pit_state ps; 3709 struct kvm_pit_state2 ps2; 3710 struct kvm_pit_config pit_config; 3711 } u; 3712 3713 switch (ioctl) { 3714 case KVM_SET_TSS_ADDR: 3715 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 3716 break; 3717 case KVM_SET_IDENTITY_MAP_ADDR: { 3718 u64 ident_addr; 3719 3720 r = -EFAULT; 3721 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 3722 goto out; 3723 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 3724 break; 3725 } 3726 case KVM_SET_NR_MMU_PAGES: 3727 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 3728 break; 3729 case KVM_GET_NR_MMU_PAGES: 3730 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 3731 break; 3732 case KVM_CREATE_IRQCHIP: { 3733 struct kvm_pic *vpic; 3734 3735 mutex_lock(&kvm->lock); 3736 r = -EEXIST; 3737 if (kvm->arch.vpic) 3738 goto create_irqchip_unlock; 3739 r = -EINVAL; 3740 if (atomic_read(&kvm->online_vcpus)) 3741 goto create_irqchip_unlock; 3742 r = -ENOMEM; 3743 vpic = kvm_create_pic(kvm); 3744 if (vpic) { 3745 r = kvm_ioapic_init(kvm); 3746 if (r) { 3747 mutex_lock(&kvm->slots_lock); 3748 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, 3749 &vpic->dev_master); 3750 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, 3751 &vpic->dev_slave); 3752 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, 3753 &vpic->dev_eclr); 3754 mutex_unlock(&kvm->slots_lock); 3755 kfree(vpic); 3756 goto create_irqchip_unlock; 3757 } 3758 } else 3759 goto create_irqchip_unlock; 3760 smp_wmb(); 3761 kvm->arch.vpic = vpic; 3762 smp_wmb(); 3763 r = kvm_setup_default_irq_routing(kvm); 3764 if (r) { 3765 mutex_lock(&kvm->slots_lock); 3766 mutex_lock(&kvm->irq_lock); 3767 kvm_ioapic_destroy(kvm); 3768 kvm_destroy_pic(kvm); 3769 mutex_unlock(&kvm->irq_lock); 3770 mutex_unlock(&kvm->slots_lock); 3771 } 3772 create_irqchip_unlock: 3773 mutex_unlock(&kvm->lock); 3774 break; 3775 } 3776 case KVM_CREATE_PIT: 3777 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 3778 goto create_pit; 3779 case KVM_CREATE_PIT2: 3780 r = -EFAULT; 3781 if (copy_from_user(&u.pit_config, argp, 3782 sizeof(struct kvm_pit_config))) 3783 goto out; 3784 create_pit: 3785 mutex_lock(&kvm->slots_lock); 3786 r = -EEXIST; 3787 if (kvm->arch.vpit) 3788 goto create_pit_unlock; 3789 r = -ENOMEM; 3790 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 3791 if (kvm->arch.vpit) 3792 r = 0; 3793 create_pit_unlock: 3794 mutex_unlock(&kvm->slots_lock); 3795 break; 3796 case KVM_GET_IRQCHIP: { 3797 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3798 struct kvm_irqchip *chip; 3799 3800 chip = memdup_user(argp, sizeof(*chip)); 3801 if (IS_ERR(chip)) { 3802 r = PTR_ERR(chip); 3803 goto out; 3804 } 3805 3806 r = -ENXIO; 3807 if (!irqchip_in_kernel(kvm)) 3808 goto get_irqchip_out; 3809 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 3810 if (r) 3811 goto get_irqchip_out; 3812 r = -EFAULT; 3813 if (copy_to_user(argp, chip, sizeof *chip)) 3814 goto get_irqchip_out; 3815 r = 0; 3816 get_irqchip_out: 3817 kfree(chip); 3818 break; 3819 } 3820 case KVM_SET_IRQCHIP: { 3821 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3822 struct kvm_irqchip *chip; 3823 3824 chip = memdup_user(argp, sizeof(*chip)); 3825 if (IS_ERR(chip)) { 3826 r = PTR_ERR(chip); 3827 goto out; 3828 } 3829 3830 r = -ENXIO; 3831 if (!irqchip_in_kernel(kvm)) 3832 goto set_irqchip_out; 3833 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 3834 if (r) 3835 goto set_irqchip_out; 3836 r = 0; 3837 set_irqchip_out: 3838 kfree(chip); 3839 break; 3840 } 3841 case KVM_GET_PIT: { 3842 r = -EFAULT; 3843 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 3844 goto out; 3845 r = -ENXIO; 3846 if (!kvm->arch.vpit) 3847 goto out; 3848 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 3849 if (r) 3850 goto out; 3851 r = -EFAULT; 3852 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 3853 goto out; 3854 r = 0; 3855 break; 3856 } 3857 case KVM_SET_PIT: { 3858 r = -EFAULT; 3859 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 3860 goto out; 3861 r = -ENXIO; 3862 if (!kvm->arch.vpit) 3863 goto out; 3864 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 3865 break; 3866 } 3867 case KVM_GET_PIT2: { 3868 r = -ENXIO; 3869 if (!kvm->arch.vpit) 3870 goto out; 3871 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 3872 if (r) 3873 goto out; 3874 r = -EFAULT; 3875 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 3876 goto out; 3877 r = 0; 3878 break; 3879 } 3880 case KVM_SET_PIT2: { 3881 r = -EFAULT; 3882 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 3883 goto out; 3884 r = -ENXIO; 3885 if (!kvm->arch.vpit) 3886 goto out; 3887 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 3888 break; 3889 } 3890 case KVM_REINJECT_CONTROL: { 3891 struct kvm_reinject_control control; 3892 r = -EFAULT; 3893 if (copy_from_user(&control, argp, sizeof(control))) 3894 goto out; 3895 r = kvm_vm_ioctl_reinject(kvm, &control); 3896 break; 3897 } 3898 case KVM_XEN_HVM_CONFIG: { 3899 r = -EFAULT; 3900 if (copy_from_user(&kvm->arch.xen_hvm_config, argp, 3901 sizeof(struct kvm_xen_hvm_config))) 3902 goto out; 3903 r = -EINVAL; 3904 if (kvm->arch.xen_hvm_config.flags) 3905 goto out; 3906 r = 0; 3907 break; 3908 } 3909 case KVM_SET_CLOCK: { 3910 struct kvm_clock_data user_ns; 3911 u64 now_ns; 3912 s64 delta; 3913 3914 r = -EFAULT; 3915 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 3916 goto out; 3917 3918 r = -EINVAL; 3919 if (user_ns.flags) 3920 goto out; 3921 3922 r = 0; 3923 local_irq_disable(); 3924 now_ns = get_kernel_ns(); 3925 delta = user_ns.clock - now_ns; 3926 local_irq_enable(); 3927 kvm->arch.kvmclock_offset = delta; 3928 kvm_gen_update_masterclock(kvm); 3929 break; 3930 } 3931 case KVM_GET_CLOCK: { 3932 struct kvm_clock_data user_ns; 3933 u64 now_ns; 3934 3935 local_irq_disable(); 3936 now_ns = get_kernel_ns(); 3937 user_ns.clock = kvm->arch.kvmclock_offset + now_ns; 3938 local_irq_enable(); 3939 user_ns.flags = 0; 3940 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 3941 3942 r = -EFAULT; 3943 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 3944 goto out; 3945 r = 0; 3946 break; 3947 } 3948 3949 default: 3950 ; 3951 } 3952 out: 3953 return r; 3954 } 3955 3956 static void kvm_init_msr_list(void) 3957 { 3958 u32 dummy[2]; 3959 unsigned i, j; 3960 3961 /* skip the first msrs in the list. KVM-specific */ 3962 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { 3963 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 3964 continue; 3965 3966 /* 3967 * Even MSRs that are valid in the host may not be exposed 3968 * to the guests in some cases. We could work around this 3969 * in VMX with the generic MSR save/load machinery, but it 3970 * is not really worthwhile since it will really only 3971 * happen with nested virtualization. 3972 */ 3973 switch (msrs_to_save[i]) { 3974 case MSR_IA32_BNDCFGS: 3975 if (!kvm_x86_ops->mpx_supported()) 3976 continue; 3977 break; 3978 default: 3979 break; 3980 } 3981 3982 if (j < i) 3983 msrs_to_save[j] = msrs_to_save[i]; 3984 j++; 3985 } 3986 num_msrs_to_save = j; 3987 } 3988 3989 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 3990 const void *v) 3991 { 3992 int handled = 0; 3993 int n; 3994 3995 do { 3996 n = min(len, 8); 3997 if (!(vcpu->arch.apic && 3998 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v)) 3999 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v)) 4000 break; 4001 handled += n; 4002 addr += n; 4003 len -= n; 4004 v += n; 4005 } while (len); 4006 4007 return handled; 4008 } 4009 4010 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4011 { 4012 int handled = 0; 4013 int n; 4014 4015 do { 4016 n = min(len, 8); 4017 if (!(vcpu->arch.apic && 4018 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v)) 4019 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v)) 4020 break; 4021 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); 4022 handled += n; 4023 addr += n; 4024 len -= n; 4025 v += n; 4026 } while (len); 4027 4028 return handled; 4029 } 4030 4031 static void kvm_set_segment(struct kvm_vcpu *vcpu, 4032 struct kvm_segment *var, int seg) 4033 { 4034 kvm_x86_ops->set_segment(vcpu, var, seg); 4035 } 4036 4037 void kvm_get_segment(struct kvm_vcpu *vcpu, 4038 struct kvm_segment *var, int seg) 4039 { 4040 kvm_x86_ops->get_segment(vcpu, var, seg); 4041 } 4042 4043 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access) 4044 { 4045 gpa_t t_gpa; 4046 struct x86_exception exception; 4047 4048 BUG_ON(!mmu_is_nested(vcpu)); 4049 4050 /* NPT walks are always user-walks */ 4051 access |= PFERR_USER_MASK; 4052 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception); 4053 4054 return t_gpa; 4055 } 4056 4057 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 4058 struct x86_exception *exception) 4059 { 4060 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4061 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4062 } 4063 4064 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 4065 struct x86_exception *exception) 4066 { 4067 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4068 access |= PFERR_FETCH_MASK; 4069 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4070 } 4071 4072 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 4073 struct x86_exception *exception) 4074 { 4075 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4076 access |= PFERR_WRITE_MASK; 4077 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4078 } 4079 4080 /* uses this to access any guest's mapped memory without checking CPL */ 4081 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 4082 struct x86_exception *exception) 4083 { 4084 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 4085 } 4086 4087 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 4088 struct kvm_vcpu *vcpu, u32 access, 4089 struct x86_exception *exception) 4090 { 4091 void *data = val; 4092 int r = X86EMUL_CONTINUE; 4093 4094 while (bytes) { 4095 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 4096 exception); 4097 unsigned offset = addr & (PAGE_SIZE-1); 4098 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 4099 int ret; 4100 4101 if (gpa == UNMAPPED_GVA) 4102 return X86EMUL_PROPAGATE_FAULT; 4103 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data, 4104 offset, toread); 4105 if (ret < 0) { 4106 r = X86EMUL_IO_NEEDED; 4107 goto out; 4108 } 4109 4110 bytes -= toread; 4111 data += toread; 4112 addr += toread; 4113 } 4114 out: 4115 return r; 4116 } 4117 4118 /* used for instruction fetching */ 4119 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4120 gva_t addr, void *val, unsigned int bytes, 4121 struct x86_exception *exception) 4122 { 4123 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4124 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4125 unsigned offset; 4126 int ret; 4127 4128 /* Inline kvm_read_guest_virt_helper for speed. */ 4129 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 4130 exception); 4131 if (unlikely(gpa == UNMAPPED_GVA)) 4132 return X86EMUL_PROPAGATE_FAULT; 4133 4134 offset = addr & (PAGE_SIZE-1); 4135 if (WARN_ON(offset + bytes > PAGE_SIZE)) 4136 bytes = (unsigned)PAGE_SIZE - offset; 4137 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val, 4138 offset, bytes); 4139 if (unlikely(ret < 0)) 4140 return X86EMUL_IO_NEEDED; 4141 4142 return X86EMUL_CONTINUE; 4143 } 4144 4145 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4146 gva_t addr, void *val, unsigned int bytes, 4147 struct x86_exception *exception) 4148 { 4149 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4150 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4151 4152 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4153 exception); 4154 } 4155 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4156 4157 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4158 gva_t addr, void *val, unsigned int bytes, 4159 struct x86_exception *exception) 4160 { 4161 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4162 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4163 } 4164 4165 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4166 gva_t addr, void *val, 4167 unsigned int bytes, 4168 struct x86_exception *exception) 4169 { 4170 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4171 void *data = val; 4172 int r = X86EMUL_CONTINUE; 4173 4174 while (bytes) { 4175 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4176 PFERR_WRITE_MASK, 4177 exception); 4178 unsigned offset = addr & (PAGE_SIZE-1); 4179 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4180 int ret; 4181 4182 if (gpa == UNMAPPED_GVA) 4183 return X86EMUL_PROPAGATE_FAULT; 4184 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); 4185 if (ret < 0) { 4186 r = X86EMUL_IO_NEEDED; 4187 goto out; 4188 } 4189 4190 bytes -= towrite; 4191 data += towrite; 4192 addr += towrite; 4193 } 4194 out: 4195 return r; 4196 } 4197 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4198 4199 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4200 gpa_t *gpa, struct x86_exception *exception, 4201 bool write) 4202 { 4203 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4204 | (write ? PFERR_WRITE_MASK : 0); 4205 4206 if (vcpu_match_mmio_gva(vcpu, gva) 4207 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4208 vcpu->arch.access, access)) { 4209 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4210 (gva & (PAGE_SIZE - 1)); 4211 trace_vcpu_match_mmio(gva, *gpa, write, false); 4212 return 1; 4213 } 4214 4215 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4216 4217 if (*gpa == UNMAPPED_GVA) 4218 return -1; 4219 4220 /* For APIC access vmexit */ 4221 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4222 return 1; 4223 4224 if (vcpu_match_mmio_gpa(vcpu, *gpa)) { 4225 trace_vcpu_match_mmio(gva, *gpa, write, true); 4226 return 1; 4227 } 4228 4229 return 0; 4230 } 4231 4232 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4233 const void *val, int bytes) 4234 { 4235 int ret; 4236 4237 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); 4238 if (ret < 0) 4239 return 0; 4240 kvm_mmu_pte_write(vcpu, gpa, val, bytes); 4241 return 1; 4242 } 4243 4244 struct read_write_emulator_ops { 4245 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4246 int bytes); 4247 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4248 void *val, int bytes); 4249 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4250 int bytes, void *val); 4251 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4252 void *val, int bytes); 4253 bool write; 4254 }; 4255 4256 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4257 { 4258 if (vcpu->mmio_read_completed) { 4259 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4260 vcpu->mmio_fragments[0].gpa, *(u64 *)val); 4261 vcpu->mmio_read_completed = 0; 4262 return 1; 4263 } 4264 4265 return 0; 4266 } 4267 4268 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4269 void *val, int bytes) 4270 { 4271 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes); 4272 } 4273 4274 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4275 void *val, int bytes) 4276 { 4277 return emulator_write_phys(vcpu, gpa, val, bytes); 4278 } 4279 4280 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4281 { 4282 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); 4283 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4284 } 4285 4286 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4287 void *val, int bytes) 4288 { 4289 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); 4290 return X86EMUL_IO_NEEDED; 4291 } 4292 4293 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4294 void *val, int bytes) 4295 { 4296 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4297 4298 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4299 return X86EMUL_CONTINUE; 4300 } 4301 4302 static const struct read_write_emulator_ops read_emultor = { 4303 .read_write_prepare = read_prepare, 4304 .read_write_emulate = read_emulate, 4305 .read_write_mmio = vcpu_mmio_read, 4306 .read_write_exit_mmio = read_exit_mmio, 4307 }; 4308 4309 static const struct read_write_emulator_ops write_emultor = { 4310 .read_write_emulate = write_emulate, 4311 .read_write_mmio = write_mmio, 4312 .read_write_exit_mmio = write_exit_mmio, 4313 .write = true, 4314 }; 4315 4316 static int emulator_read_write_onepage(unsigned long addr, void *val, 4317 unsigned int bytes, 4318 struct x86_exception *exception, 4319 struct kvm_vcpu *vcpu, 4320 const struct read_write_emulator_ops *ops) 4321 { 4322 gpa_t gpa; 4323 int handled, ret; 4324 bool write = ops->write; 4325 struct kvm_mmio_fragment *frag; 4326 4327 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 4328 4329 if (ret < 0) 4330 return X86EMUL_PROPAGATE_FAULT; 4331 4332 /* For APIC access vmexit */ 4333 if (ret) 4334 goto mmio; 4335 4336 if (ops->read_write_emulate(vcpu, gpa, val, bytes)) 4337 return X86EMUL_CONTINUE; 4338 4339 mmio: 4340 /* 4341 * Is this MMIO handled locally? 4342 */ 4343 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 4344 if (handled == bytes) 4345 return X86EMUL_CONTINUE; 4346 4347 gpa += handled; 4348 bytes -= handled; 4349 val += handled; 4350 4351 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 4352 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 4353 frag->gpa = gpa; 4354 frag->data = val; 4355 frag->len = bytes; 4356 return X86EMUL_CONTINUE; 4357 } 4358 4359 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr, 4360 void *val, unsigned int bytes, 4361 struct x86_exception *exception, 4362 const struct read_write_emulator_ops *ops) 4363 { 4364 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4365 gpa_t gpa; 4366 int rc; 4367 4368 if (ops->read_write_prepare && 4369 ops->read_write_prepare(vcpu, val, bytes)) 4370 return X86EMUL_CONTINUE; 4371 4372 vcpu->mmio_nr_fragments = 0; 4373 4374 /* Crossing a page boundary? */ 4375 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 4376 int now; 4377 4378 now = -addr & ~PAGE_MASK; 4379 rc = emulator_read_write_onepage(addr, val, now, exception, 4380 vcpu, ops); 4381 4382 if (rc != X86EMUL_CONTINUE) 4383 return rc; 4384 addr += now; 4385 val += now; 4386 bytes -= now; 4387 } 4388 4389 rc = emulator_read_write_onepage(addr, val, bytes, exception, 4390 vcpu, ops); 4391 if (rc != X86EMUL_CONTINUE) 4392 return rc; 4393 4394 if (!vcpu->mmio_nr_fragments) 4395 return rc; 4396 4397 gpa = vcpu->mmio_fragments[0].gpa; 4398 4399 vcpu->mmio_needed = 1; 4400 vcpu->mmio_cur_fragment = 0; 4401 4402 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 4403 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 4404 vcpu->run->exit_reason = KVM_EXIT_MMIO; 4405 vcpu->run->mmio.phys_addr = gpa; 4406 4407 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 4408 } 4409 4410 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 4411 unsigned long addr, 4412 void *val, 4413 unsigned int bytes, 4414 struct x86_exception *exception) 4415 { 4416 return emulator_read_write(ctxt, addr, val, bytes, 4417 exception, &read_emultor); 4418 } 4419 4420 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 4421 unsigned long addr, 4422 const void *val, 4423 unsigned int bytes, 4424 struct x86_exception *exception) 4425 { 4426 return emulator_read_write(ctxt, addr, (void *)val, bytes, 4427 exception, &write_emultor); 4428 } 4429 4430 #define CMPXCHG_TYPE(t, ptr, old, new) \ 4431 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 4432 4433 #ifdef CONFIG_X86_64 4434 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 4435 #else 4436 # define CMPXCHG64(ptr, old, new) \ 4437 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 4438 #endif 4439 4440 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 4441 unsigned long addr, 4442 const void *old, 4443 const void *new, 4444 unsigned int bytes, 4445 struct x86_exception *exception) 4446 { 4447 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4448 gpa_t gpa; 4449 struct page *page; 4450 char *kaddr; 4451 bool exchanged; 4452 4453 /* guests cmpxchg8b have to be emulated atomically */ 4454 if (bytes > 8 || (bytes & (bytes - 1))) 4455 goto emul_write; 4456 4457 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 4458 4459 if (gpa == UNMAPPED_GVA || 4460 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4461 goto emul_write; 4462 4463 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 4464 goto emul_write; 4465 4466 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); 4467 if (is_error_page(page)) 4468 goto emul_write; 4469 4470 kaddr = kmap_atomic(page); 4471 kaddr += offset_in_page(gpa); 4472 switch (bytes) { 4473 case 1: 4474 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 4475 break; 4476 case 2: 4477 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 4478 break; 4479 case 4: 4480 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 4481 break; 4482 case 8: 4483 exchanged = CMPXCHG64(kaddr, old, new); 4484 break; 4485 default: 4486 BUG(); 4487 } 4488 kunmap_atomic(kaddr); 4489 kvm_release_page_dirty(page); 4490 4491 if (!exchanged) 4492 return X86EMUL_CMPXCHG_FAILED; 4493 4494 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT); 4495 kvm_mmu_pte_write(vcpu, gpa, new, bytes); 4496 4497 return X86EMUL_CONTINUE; 4498 4499 emul_write: 4500 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 4501 4502 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 4503 } 4504 4505 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 4506 { 4507 /* TODO: String I/O for in kernel device */ 4508 int r; 4509 4510 if (vcpu->arch.pio.in) 4511 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port, 4512 vcpu->arch.pio.size, pd); 4513 else 4514 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, 4515 vcpu->arch.pio.port, vcpu->arch.pio.size, 4516 pd); 4517 return r; 4518 } 4519 4520 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 4521 unsigned short port, void *val, 4522 unsigned int count, bool in) 4523 { 4524 vcpu->arch.pio.port = port; 4525 vcpu->arch.pio.in = in; 4526 vcpu->arch.pio.count = count; 4527 vcpu->arch.pio.size = size; 4528 4529 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 4530 vcpu->arch.pio.count = 0; 4531 return 1; 4532 } 4533 4534 vcpu->run->exit_reason = KVM_EXIT_IO; 4535 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 4536 vcpu->run->io.size = size; 4537 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 4538 vcpu->run->io.count = count; 4539 vcpu->run->io.port = port; 4540 4541 return 0; 4542 } 4543 4544 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 4545 int size, unsigned short port, void *val, 4546 unsigned int count) 4547 { 4548 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4549 int ret; 4550 4551 if (vcpu->arch.pio.count) 4552 goto data_avail; 4553 4554 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 4555 if (ret) { 4556 data_avail: 4557 memcpy(val, vcpu->arch.pio_data, size * count); 4558 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 4559 vcpu->arch.pio.count = 0; 4560 return 1; 4561 } 4562 4563 return 0; 4564 } 4565 4566 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 4567 int size, unsigned short port, 4568 const void *val, unsigned int count) 4569 { 4570 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4571 4572 memcpy(vcpu->arch.pio_data, val, size * count); 4573 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 4574 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 4575 } 4576 4577 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 4578 { 4579 return kvm_x86_ops->get_segment_base(vcpu, seg); 4580 } 4581 4582 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 4583 { 4584 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 4585 } 4586 4587 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 4588 { 4589 if (!need_emulate_wbinvd(vcpu)) 4590 return X86EMUL_CONTINUE; 4591 4592 if (kvm_x86_ops->has_wbinvd_exit()) { 4593 int cpu = get_cpu(); 4594 4595 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4596 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 4597 wbinvd_ipi, NULL, 1); 4598 put_cpu(); 4599 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 4600 } else 4601 wbinvd(); 4602 return X86EMUL_CONTINUE; 4603 } 4604 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 4605 4606 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 4607 { 4608 kvm_emulate_wbinvd(emul_to_vcpu(ctxt)); 4609 } 4610 4611 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest) 4612 { 4613 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 4614 } 4615 4616 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value) 4617 { 4618 4619 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 4620 } 4621 4622 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 4623 { 4624 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 4625 } 4626 4627 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 4628 { 4629 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4630 unsigned long value; 4631 4632 switch (cr) { 4633 case 0: 4634 value = kvm_read_cr0(vcpu); 4635 break; 4636 case 2: 4637 value = vcpu->arch.cr2; 4638 break; 4639 case 3: 4640 value = kvm_read_cr3(vcpu); 4641 break; 4642 case 4: 4643 value = kvm_read_cr4(vcpu); 4644 break; 4645 case 8: 4646 value = kvm_get_cr8(vcpu); 4647 break; 4648 default: 4649 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4650 return 0; 4651 } 4652 4653 return value; 4654 } 4655 4656 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 4657 { 4658 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4659 int res = 0; 4660 4661 switch (cr) { 4662 case 0: 4663 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 4664 break; 4665 case 2: 4666 vcpu->arch.cr2 = val; 4667 break; 4668 case 3: 4669 res = kvm_set_cr3(vcpu, val); 4670 break; 4671 case 4: 4672 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 4673 break; 4674 case 8: 4675 res = kvm_set_cr8(vcpu, val); 4676 break; 4677 default: 4678 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4679 res = -1; 4680 } 4681 4682 return res; 4683 } 4684 4685 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 4686 { 4687 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 4688 } 4689 4690 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4691 { 4692 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 4693 } 4694 4695 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4696 { 4697 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 4698 } 4699 4700 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4701 { 4702 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 4703 } 4704 4705 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4706 { 4707 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 4708 } 4709 4710 static unsigned long emulator_get_cached_segment_base( 4711 struct x86_emulate_ctxt *ctxt, int seg) 4712 { 4713 return get_segment_base(emul_to_vcpu(ctxt), seg); 4714 } 4715 4716 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 4717 struct desc_struct *desc, u32 *base3, 4718 int seg) 4719 { 4720 struct kvm_segment var; 4721 4722 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 4723 *selector = var.selector; 4724 4725 if (var.unusable) { 4726 memset(desc, 0, sizeof(*desc)); 4727 return false; 4728 } 4729 4730 if (var.g) 4731 var.limit >>= 12; 4732 set_desc_limit(desc, var.limit); 4733 set_desc_base(desc, (unsigned long)var.base); 4734 #ifdef CONFIG_X86_64 4735 if (base3) 4736 *base3 = var.base >> 32; 4737 #endif 4738 desc->type = var.type; 4739 desc->s = var.s; 4740 desc->dpl = var.dpl; 4741 desc->p = var.present; 4742 desc->avl = var.avl; 4743 desc->l = var.l; 4744 desc->d = var.db; 4745 desc->g = var.g; 4746 4747 return true; 4748 } 4749 4750 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 4751 struct desc_struct *desc, u32 base3, 4752 int seg) 4753 { 4754 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4755 struct kvm_segment var; 4756 4757 var.selector = selector; 4758 var.base = get_desc_base(desc); 4759 #ifdef CONFIG_X86_64 4760 var.base |= ((u64)base3) << 32; 4761 #endif 4762 var.limit = get_desc_limit(desc); 4763 if (desc->g) 4764 var.limit = (var.limit << 12) | 0xfff; 4765 var.type = desc->type; 4766 var.dpl = desc->dpl; 4767 var.db = desc->d; 4768 var.s = desc->s; 4769 var.l = desc->l; 4770 var.g = desc->g; 4771 var.avl = desc->avl; 4772 var.present = desc->p; 4773 var.unusable = !var.present; 4774 var.padding = 0; 4775 4776 kvm_set_segment(vcpu, &var, seg); 4777 return; 4778 } 4779 4780 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 4781 u32 msr_index, u64 *pdata) 4782 { 4783 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); 4784 } 4785 4786 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 4787 u32 msr_index, u64 data) 4788 { 4789 struct msr_data msr; 4790 4791 msr.data = data; 4792 msr.index = msr_index; 4793 msr.host_initiated = false; 4794 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 4795 } 4796 4797 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 4798 u32 pmc) 4799 { 4800 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc); 4801 } 4802 4803 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 4804 u32 pmc, u64 *pdata) 4805 { 4806 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata); 4807 } 4808 4809 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 4810 { 4811 emul_to_vcpu(ctxt)->arch.halt_request = 1; 4812 } 4813 4814 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) 4815 { 4816 preempt_disable(); 4817 kvm_load_guest_fpu(emul_to_vcpu(ctxt)); 4818 /* 4819 * CR0.TS may reference the host fpu state, not the guest fpu state, 4820 * so it may be clear at this point. 4821 */ 4822 clts(); 4823 } 4824 4825 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) 4826 { 4827 preempt_enable(); 4828 } 4829 4830 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 4831 struct x86_instruction_info *info, 4832 enum x86_intercept_stage stage) 4833 { 4834 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 4835 } 4836 4837 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 4838 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) 4839 { 4840 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); 4841 } 4842 4843 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 4844 { 4845 return kvm_register_read(emul_to_vcpu(ctxt), reg); 4846 } 4847 4848 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 4849 { 4850 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 4851 } 4852 4853 static const struct x86_emulate_ops emulate_ops = { 4854 .read_gpr = emulator_read_gpr, 4855 .write_gpr = emulator_write_gpr, 4856 .read_std = kvm_read_guest_virt_system, 4857 .write_std = kvm_write_guest_virt_system, 4858 .fetch = kvm_fetch_guest_virt, 4859 .read_emulated = emulator_read_emulated, 4860 .write_emulated = emulator_write_emulated, 4861 .cmpxchg_emulated = emulator_cmpxchg_emulated, 4862 .invlpg = emulator_invlpg, 4863 .pio_in_emulated = emulator_pio_in_emulated, 4864 .pio_out_emulated = emulator_pio_out_emulated, 4865 .get_segment = emulator_get_segment, 4866 .set_segment = emulator_set_segment, 4867 .get_cached_segment_base = emulator_get_cached_segment_base, 4868 .get_gdt = emulator_get_gdt, 4869 .get_idt = emulator_get_idt, 4870 .set_gdt = emulator_set_gdt, 4871 .set_idt = emulator_set_idt, 4872 .get_cr = emulator_get_cr, 4873 .set_cr = emulator_set_cr, 4874 .cpl = emulator_get_cpl, 4875 .get_dr = emulator_get_dr, 4876 .set_dr = emulator_set_dr, 4877 .set_msr = emulator_set_msr, 4878 .get_msr = emulator_get_msr, 4879 .check_pmc = emulator_check_pmc, 4880 .read_pmc = emulator_read_pmc, 4881 .halt = emulator_halt, 4882 .wbinvd = emulator_wbinvd, 4883 .fix_hypercall = emulator_fix_hypercall, 4884 .get_fpu = emulator_get_fpu, 4885 .put_fpu = emulator_put_fpu, 4886 .intercept = emulator_intercept, 4887 .get_cpuid = emulator_get_cpuid, 4888 }; 4889 4890 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 4891 { 4892 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 4893 /* 4894 * an sti; sti; sequence only disable interrupts for the first 4895 * instruction. So, if the last instruction, be it emulated or 4896 * not, left the system with the INT_STI flag enabled, it 4897 * means that the last instruction is an sti. We should not 4898 * leave the flag on in this case. The same goes for mov ss 4899 */ 4900 if (int_shadow & mask) 4901 mask = 0; 4902 if (unlikely(int_shadow || mask)) { 4903 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 4904 if (!mask) 4905 kvm_make_request(KVM_REQ_EVENT, vcpu); 4906 } 4907 } 4908 4909 static void inject_emulated_exception(struct kvm_vcpu *vcpu) 4910 { 4911 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 4912 if (ctxt->exception.vector == PF_VECTOR) 4913 kvm_propagate_fault(vcpu, &ctxt->exception); 4914 else if (ctxt->exception.error_code_valid) 4915 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 4916 ctxt->exception.error_code); 4917 else 4918 kvm_queue_exception(vcpu, ctxt->exception.vector); 4919 } 4920 4921 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 4922 { 4923 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 4924 int cs_db, cs_l; 4925 4926 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 4927 4928 ctxt->eflags = kvm_get_rflags(vcpu); 4929 ctxt->eip = kvm_rip_read(vcpu); 4930 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 4931 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 4932 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 4933 cs_db ? X86EMUL_MODE_PROT32 : 4934 X86EMUL_MODE_PROT16; 4935 ctxt->guest_mode = is_guest_mode(vcpu); 4936 4937 init_decode_cache(ctxt); 4938 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 4939 } 4940 4941 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 4942 { 4943 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 4944 int ret; 4945 4946 init_emulate_ctxt(vcpu); 4947 4948 ctxt->op_bytes = 2; 4949 ctxt->ad_bytes = 2; 4950 ctxt->_eip = ctxt->eip + inc_eip; 4951 ret = emulate_int_real(ctxt, irq); 4952 4953 if (ret != X86EMUL_CONTINUE) 4954 return EMULATE_FAIL; 4955 4956 ctxt->eip = ctxt->_eip; 4957 kvm_rip_write(vcpu, ctxt->eip); 4958 kvm_set_rflags(vcpu, ctxt->eflags); 4959 4960 if (irq == NMI_VECTOR) 4961 vcpu->arch.nmi_pending = 0; 4962 else 4963 vcpu->arch.interrupt.pending = false; 4964 4965 return EMULATE_DONE; 4966 } 4967 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 4968 4969 static int handle_emulation_failure(struct kvm_vcpu *vcpu) 4970 { 4971 int r = EMULATE_DONE; 4972 4973 ++vcpu->stat.insn_emulation_fail; 4974 trace_kvm_emulate_insn_failed(vcpu); 4975 if (!is_guest_mode(vcpu)) { 4976 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 4977 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 4978 vcpu->run->internal.ndata = 0; 4979 r = EMULATE_FAIL; 4980 } 4981 kvm_queue_exception(vcpu, UD_VECTOR); 4982 4983 return r; 4984 } 4985 4986 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 4987 bool write_fault_to_shadow_pgtable, 4988 int emulation_type) 4989 { 4990 gpa_t gpa = cr2; 4991 pfn_t pfn; 4992 4993 if (emulation_type & EMULTYPE_NO_REEXECUTE) 4994 return false; 4995 4996 if (!vcpu->arch.mmu.direct_map) { 4997 /* 4998 * Write permission should be allowed since only 4999 * write access need to be emulated. 5000 */ 5001 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5002 5003 /* 5004 * If the mapping is invalid in guest, let cpu retry 5005 * it to generate fault. 5006 */ 5007 if (gpa == UNMAPPED_GVA) 5008 return true; 5009 } 5010 5011 /* 5012 * Do not retry the unhandleable instruction if it faults on the 5013 * readonly host memory, otherwise it will goto a infinite loop: 5014 * retry instruction -> write #PF -> emulation fail -> retry 5015 * instruction -> ... 5016 */ 5017 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 5018 5019 /* 5020 * If the instruction failed on the error pfn, it can not be fixed, 5021 * report the error to userspace. 5022 */ 5023 if (is_error_noslot_pfn(pfn)) 5024 return false; 5025 5026 kvm_release_pfn_clean(pfn); 5027 5028 /* The instructions are well-emulated on direct mmu. */ 5029 if (vcpu->arch.mmu.direct_map) { 5030 unsigned int indirect_shadow_pages; 5031 5032 spin_lock(&vcpu->kvm->mmu_lock); 5033 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 5034 spin_unlock(&vcpu->kvm->mmu_lock); 5035 5036 if (indirect_shadow_pages) 5037 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5038 5039 return true; 5040 } 5041 5042 /* 5043 * if emulation was due to access to shadowed page table 5044 * and it failed try to unshadow page and re-enter the 5045 * guest to let CPU execute the instruction. 5046 */ 5047 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5048 5049 /* 5050 * If the access faults on its page table, it can not 5051 * be fixed by unprotecting shadow page and it should 5052 * be reported to userspace. 5053 */ 5054 return !write_fault_to_shadow_pgtable; 5055 } 5056 5057 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5058 unsigned long cr2, int emulation_type) 5059 { 5060 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5061 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5062 5063 last_retry_eip = vcpu->arch.last_retry_eip; 5064 last_retry_addr = vcpu->arch.last_retry_addr; 5065 5066 /* 5067 * If the emulation is caused by #PF and it is non-page_table 5068 * writing instruction, it means the VM-EXIT is caused by shadow 5069 * page protected, we can zap the shadow page and retry this 5070 * instruction directly. 5071 * 5072 * Note: if the guest uses a non-page-table modifying instruction 5073 * on the PDE that points to the instruction, then we will unmap 5074 * the instruction and go to an infinite loop. So, we cache the 5075 * last retried eip and the last fault address, if we meet the eip 5076 * and the address again, we can break out of the potential infinite 5077 * loop. 5078 */ 5079 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5080 5081 if (!(emulation_type & EMULTYPE_RETRY)) 5082 return false; 5083 5084 if (x86_page_table_writing_insn(ctxt)) 5085 return false; 5086 5087 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5088 return false; 5089 5090 vcpu->arch.last_retry_eip = ctxt->eip; 5091 vcpu->arch.last_retry_addr = cr2; 5092 5093 if (!vcpu->arch.mmu.direct_map) 5094 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5095 5096 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5097 5098 return true; 5099 } 5100 5101 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5102 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5103 5104 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5105 unsigned long *db) 5106 { 5107 u32 dr6 = 0; 5108 int i; 5109 u32 enable, rwlen; 5110 5111 enable = dr7; 5112 rwlen = dr7 >> 16; 5113 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5114 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5115 dr6 |= (1 << i); 5116 return dr6; 5117 } 5118 5119 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) 5120 { 5121 struct kvm_run *kvm_run = vcpu->run; 5122 5123 /* 5124 * rflags is the old, "raw" value of the flags. The new value has 5125 * not been saved yet. 5126 * 5127 * This is correct even for TF set by the guest, because "the 5128 * processor will not generate this exception after the instruction 5129 * that sets the TF flag". 5130 */ 5131 if (unlikely(rflags & X86_EFLAGS_TF)) { 5132 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5133 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | 5134 DR6_RTM; 5135 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5136 kvm_run->debug.arch.exception = DB_VECTOR; 5137 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5138 *r = EMULATE_USER_EXIT; 5139 } else { 5140 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; 5141 /* 5142 * "Certain debug exceptions may clear bit 0-3. The 5143 * remaining contents of the DR6 register are never 5144 * cleared by the processor". 5145 */ 5146 vcpu->arch.dr6 &= ~15; 5147 vcpu->arch.dr6 |= DR6_BS | DR6_RTM; 5148 kvm_queue_exception(vcpu, DB_VECTOR); 5149 } 5150 } 5151 } 5152 5153 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5154 { 5155 struct kvm_run *kvm_run = vcpu->run; 5156 unsigned long eip = vcpu->arch.emulate_ctxt.eip; 5157 u32 dr6 = 0; 5158 5159 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5160 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5161 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5162 vcpu->arch.guest_debug_dr7, 5163 vcpu->arch.eff_db); 5164 5165 if (dr6 != 0) { 5166 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 5167 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) + 5168 get_segment_base(vcpu, VCPU_SREG_CS); 5169 5170 kvm_run->debug.arch.exception = DB_VECTOR; 5171 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5172 *r = EMULATE_USER_EXIT; 5173 return true; 5174 } 5175 } 5176 5177 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 5178 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 5179 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5180 vcpu->arch.dr7, 5181 vcpu->arch.db); 5182 5183 if (dr6 != 0) { 5184 vcpu->arch.dr6 &= ~15; 5185 vcpu->arch.dr6 |= dr6 | DR6_RTM; 5186 kvm_queue_exception(vcpu, DB_VECTOR); 5187 *r = EMULATE_DONE; 5188 return true; 5189 } 5190 } 5191 5192 return false; 5193 } 5194 5195 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 5196 unsigned long cr2, 5197 int emulation_type, 5198 void *insn, 5199 int insn_len) 5200 { 5201 int r; 5202 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5203 bool writeback = true; 5204 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 5205 5206 /* 5207 * Clear write_fault_to_shadow_pgtable here to ensure it is 5208 * never reused. 5209 */ 5210 vcpu->arch.write_fault_to_shadow_pgtable = false; 5211 kvm_clear_exception_queue(vcpu); 5212 5213 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 5214 init_emulate_ctxt(vcpu); 5215 5216 /* 5217 * We will reenter on the same instruction since 5218 * we do not set complete_userspace_io. This does not 5219 * handle watchpoints yet, those would be handled in 5220 * the emulate_ops. 5221 */ 5222 if (kvm_vcpu_check_breakpoint(vcpu, &r)) 5223 return r; 5224 5225 ctxt->interruptibility = 0; 5226 ctxt->have_exception = false; 5227 ctxt->perm_ok = false; 5228 5229 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 5230 5231 r = x86_decode_insn(ctxt, insn, insn_len); 5232 5233 trace_kvm_emulate_insn_start(vcpu); 5234 ++vcpu->stat.insn_emulation; 5235 if (r != EMULATION_OK) { 5236 if (emulation_type & EMULTYPE_TRAP_UD) 5237 return EMULATE_FAIL; 5238 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5239 emulation_type)) 5240 return EMULATE_DONE; 5241 if (emulation_type & EMULTYPE_SKIP) 5242 return EMULATE_FAIL; 5243 return handle_emulation_failure(vcpu); 5244 } 5245 } 5246 5247 if (emulation_type & EMULTYPE_SKIP) { 5248 kvm_rip_write(vcpu, ctxt->_eip); 5249 if (ctxt->eflags & X86_EFLAGS_RF) 5250 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 5251 return EMULATE_DONE; 5252 } 5253 5254 if (retry_instruction(ctxt, cr2, emulation_type)) 5255 return EMULATE_DONE; 5256 5257 /* this is needed for vmware backdoor interface to work since it 5258 changes registers values during IO operation */ 5259 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 5260 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5261 emulator_invalidate_register_cache(ctxt); 5262 } 5263 5264 restart: 5265 r = x86_emulate_insn(ctxt); 5266 5267 if (r == EMULATION_INTERCEPTED) 5268 return EMULATE_DONE; 5269 5270 if (r == EMULATION_FAILED) { 5271 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5272 emulation_type)) 5273 return EMULATE_DONE; 5274 5275 return handle_emulation_failure(vcpu); 5276 } 5277 5278 if (ctxt->have_exception) { 5279 inject_emulated_exception(vcpu); 5280 r = EMULATE_DONE; 5281 } else if (vcpu->arch.pio.count) { 5282 if (!vcpu->arch.pio.in) { 5283 /* FIXME: return into emulator if single-stepping. */ 5284 vcpu->arch.pio.count = 0; 5285 } else { 5286 writeback = false; 5287 vcpu->arch.complete_userspace_io = complete_emulated_pio; 5288 } 5289 r = EMULATE_USER_EXIT; 5290 } else if (vcpu->mmio_needed) { 5291 if (!vcpu->mmio_is_write) 5292 writeback = false; 5293 r = EMULATE_USER_EXIT; 5294 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 5295 } else if (r == EMULATION_RESTART) 5296 goto restart; 5297 else 5298 r = EMULATE_DONE; 5299 5300 if (writeback) { 5301 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5302 toggle_interruptibility(vcpu, ctxt->interruptibility); 5303 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 5304 kvm_rip_write(vcpu, ctxt->eip); 5305 if (r == EMULATE_DONE) 5306 kvm_vcpu_check_singlestep(vcpu, rflags, &r); 5307 __kvm_set_rflags(vcpu, ctxt->eflags); 5308 5309 /* 5310 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 5311 * do nothing, and it will be requested again as soon as 5312 * the shadow expires. But we still need to check here, 5313 * because POPF has no interrupt shadow. 5314 */ 5315 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 5316 kvm_make_request(KVM_REQ_EVENT, vcpu); 5317 } else 5318 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 5319 5320 return r; 5321 } 5322 EXPORT_SYMBOL_GPL(x86_emulate_instruction); 5323 5324 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) 5325 { 5326 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 5327 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 5328 size, port, &val, 1); 5329 /* do not return to emulator after return from userspace */ 5330 vcpu->arch.pio.count = 0; 5331 return ret; 5332 } 5333 EXPORT_SYMBOL_GPL(kvm_fast_pio_out); 5334 5335 static void tsc_bad(void *info) 5336 { 5337 __this_cpu_write(cpu_tsc_khz, 0); 5338 } 5339 5340 static void tsc_khz_changed(void *data) 5341 { 5342 struct cpufreq_freqs *freq = data; 5343 unsigned long khz = 0; 5344 5345 if (data) 5346 khz = freq->new; 5347 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5348 khz = cpufreq_quick_get(raw_smp_processor_id()); 5349 if (!khz) 5350 khz = tsc_khz; 5351 __this_cpu_write(cpu_tsc_khz, khz); 5352 } 5353 5354 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 5355 void *data) 5356 { 5357 struct cpufreq_freqs *freq = data; 5358 struct kvm *kvm; 5359 struct kvm_vcpu *vcpu; 5360 int i, send_ipi = 0; 5361 5362 /* 5363 * We allow guests to temporarily run on slowing clocks, 5364 * provided we notify them after, or to run on accelerating 5365 * clocks, provided we notify them before. Thus time never 5366 * goes backwards. 5367 * 5368 * However, we have a problem. We can't atomically update 5369 * the frequency of a given CPU from this function; it is 5370 * merely a notifier, which can be called from any CPU. 5371 * Changing the TSC frequency at arbitrary points in time 5372 * requires a recomputation of local variables related to 5373 * the TSC for each VCPU. We must flag these local variables 5374 * to be updated and be sure the update takes place with the 5375 * new frequency before any guests proceed. 5376 * 5377 * Unfortunately, the combination of hotplug CPU and frequency 5378 * change creates an intractable locking scenario; the order 5379 * of when these callouts happen is undefined with respect to 5380 * CPU hotplug, and they can race with each other. As such, 5381 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 5382 * undefined; you can actually have a CPU frequency change take 5383 * place in between the computation of X and the setting of the 5384 * variable. To protect against this problem, all updates of 5385 * the per_cpu tsc_khz variable are done in an interrupt 5386 * protected IPI, and all callers wishing to update the value 5387 * must wait for a synchronous IPI to complete (which is trivial 5388 * if the caller is on the CPU already). This establishes the 5389 * necessary total order on variable updates. 5390 * 5391 * Note that because a guest time update may take place 5392 * anytime after the setting of the VCPU's request bit, the 5393 * correct TSC value must be set before the request. However, 5394 * to ensure the update actually makes it to any guest which 5395 * starts running in hardware virtualization between the set 5396 * and the acquisition of the spinlock, we must also ping the 5397 * CPU after setting the request bit. 5398 * 5399 */ 5400 5401 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 5402 return 0; 5403 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 5404 return 0; 5405 5406 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5407 5408 spin_lock(&kvm_lock); 5409 list_for_each_entry(kvm, &vm_list, vm_list) { 5410 kvm_for_each_vcpu(i, vcpu, kvm) { 5411 if (vcpu->cpu != freq->cpu) 5412 continue; 5413 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5414 if (vcpu->cpu != smp_processor_id()) 5415 send_ipi = 1; 5416 } 5417 } 5418 spin_unlock(&kvm_lock); 5419 5420 if (freq->old < freq->new && send_ipi) { 5421 /* 5422 * We upscale the frequency. Must make the guest 5423 * doesn't see old kvmclock values while running with 5424 * the new frequency, otherwise we risk the guest sees 5425 * time go backwards. 5426 * 5427 * In case we update the frequency for another cpu 5428 * (which might be in guest context) send an interrupt 5429 * to kick the cpu out of guest context. Next time 5430 * guest context is entered kvmclock will be updated, 5431 * so the guest will not see stale values. 5432 */ 5433 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5434 } 5435 return 0; 5436 } 5437 5438 static struct notifier_block kvmclock_cpufreq_notifier_block = { 5439 .notifier_call = kvmclock_cpufreq_notifier 5440 }; 5441 5442 static int kvmclock_cpu_notifier(struct notifier_block *nfb, 5443 unsigned long action, void *hcpu) 5444 { 5445 unsigned int cpu = (unsigned long)hcpu; 5446 5447 switch (action) { 5448 case CPU_ONLINE: 5449 case CPU_DOWN_FAILED: 5450 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5451 break; 5452 case CPU_DOWN_PREPARE: 5453 smp_call_function_single(cpu, tsc_bad, NULL, 1); 5454 break; 5455 } 5456 return NOTIFY_OK; 5457 } 5458 5459 static struct notifier_block kvmclock_cpu_notifier_block = { 5460 .notifier_call = kvmclock_cpu_notifier, 5461 .priority = -INT_MAX 5462 }; 5463 5464 static void kvm_timer_init(void) 5465 { 5466 int cpu; 5467 5468 max_tsc_khz = tsc_khz; 5469 5470 cpu_notifier_register_begin(); 5471 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 5472 #ifdef CONFIG_CPU_FREQ 5473 struct cpufreq_policy policy; 5474 memset(&policy, 0, sizeof(policy)); 5475 cpu = get_cpu(); 5476 cpufreq_get_policy(&policy, cpu); 5477 if (policy.cpuinfo.max_freq) 5478 max_tsc_khz = policy.cpuinfo.max_freq; 5479 put_cpu(); 5480 #endif 5481 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 5482 CPUFREQ_TRANSITION_NOTIFIER); 5483 } 5484 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 5485 for_each_online_cpu(cpu) 5486 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5487 5488 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5489 cpu_notifier_register_done(); 5490 5491 } 5492 5493 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 5494 5495 int kvm_is_in_guest(void) 5496 { 5497 return __this_cpu_read(current_vcpu) != NULL; 5498 } 5499 5500 static int kvm_is_user_mode(void) 5501 { 5502 int user_mode = 3; 5503 5504 if (__this_cpu_read(current_vcpu)) 5505 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 5506 5507 return user_mode != 0; 5508 } 5509 5510 static unsigned long kvm_get_guest_ip(void) 5511 { 5512 unsigned long ip = 0; 5513 5514 if (__this_cpu_read(current_vcpu)) 5515 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 5516 5517 return ip; 5518 } 5519 5520 static struct perf_guest_info_callbacks kvm_guest_cbs = { 5521 .is_in_guest = kvm_is_in_guest, 5522 .is_user_mode = kvm_is_user_mode, 5523 .get_guest_ip = kvm_get_guest_ip, 5524 }; 5525 5526 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) 5527 { 5528 __this_cpu_write(current_vcpu, vcpu); 5529 } 5530 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); 5531 5532 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) 5533 { 5534 __this_cpu_write(current_vcpu, NULL); 5535 } 5536 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); 5537 5538 static void kvm_set_mmio_spte_mask(void) 5539 { 5540 u64 mask; 5541 int maxphyaddr = boot_cpu_data.x86_phys_bits; 5542 5543 /* 5544 * Set the reserved bits and the present bit of an paging-structure 5545 * entry to generate page fault with PFER.RSV = 1. 5546 */ 5547 /* Mask the reserved physical address bits. */ 5548 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr; 5549 5550 /* Bit 62 is always reserved for 32bit host. */ 5551 mask |= 0x3ull << 62; 5552 5553 /* Set the present bit. */ 5554 mask |= 1ull; 5555 5556 #ifdef CONFIG_X86_64 5557 /* 5558 * If reserved bit is not supported, clear the present bit to disable 5559 * mmio page fault. 5560 */ 5561 if (maxphyaddr == 52) 5562 mask &= ~1ull; 5563 #endif 5564 5565 kvm_mmu_set_mmio_spte_mask(mask); 5566 } 5567 5568 #ifdef CONFIG_X86_64 5569 static void pvclock_gtod_update_fn(struct work_struct *work) 5570 { 5571 struct kvm *kvm; 5572 5573 struct kvm_vcpu *vcpu; 5574 int i; 5575 5576 spin_lock(&kvm_lock); 5577 list_for_each_entry(kvm, &vm_list, vm_list) 5578 kvm_for_each_vcpu(i, vcpu, kvm) 5579 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests); 5580 atomic_set(&kvm_guest_has_master_clock, 0); 5581 spin_unlock(&kvm_lock); 5582 } 5583 5584 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 5585 5586 /* 5587 * Notification about pvclock gtod data update. 5588 */ 5589 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 5590 void *priv) 5591 { 5592 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 5593 struct timekeeper *tk = priv; 5594 5595 update_pvclock_gtod(tk); 5596 5597 /* disable master clock if host does not trust, or does not 5598 * use, TSC clocksource 5599 */ 5600 if (gtod->clock.vclock_mode != VCLOCK_TSC && 5601 atomic_read(&kvm_guest_has_master_clock) != 0) 5602 queue_work(system_long_wq, &pvclock_gtod_work); 5603 5604 return 0; 5605 } 5606 5607 static struct notifier_block pvclock_gtod_notifier = { 5608 .notifier_call = pvclock_gtod_notify, 5609 }; 5610 #endif 5611 5612 int kvm_arch_init(void *opaque) 5613 { 5614 int r; 5615 struct kvm_x86_ops *ops = opaque; 5616 5617 if (kvm_x86_ops) { 5618 printk(KERN_ERR "kvm: already loaded the other module\n"); 5619 r = -EEXIST; 5620 goto out; 5621 } 5622 5623 if (!ops->cpu_has_kvm_support()) { 5624 printk(KERN_ERR "kvm: no hardware support\n"); 5625 r = -EOPNOTSUPP; 5626 goto out; 5627 } 5628 if (ops->disabled_by_bios()) { 5629 printk(KERN_ERR "kvm: disabled by bios\n"); 5630 r = -EOPNOTSUPP; 5631 goto out; 5632 } 5633 5634 r = -ENOMEM; 5635 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 5636 if (!shared_msrs) { 5637 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 5638 goto out; 5639 } 5640 5641 r = kvm_mmu_module_init(); 5642 if (r) 5643 goto out_free_percpu; 5644 5645 kvm_set_mmio_spte_mask(); 5646 5647 kvm_x86_ops = ops; 5648 kvm_init_msr_list(); 5649 5650 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 5651 PT_DIRTY_MASK, PT64_NX_MASK, 0); 5652 5653 kvm_timer_init(); 5654 5655 perf_register_guest_info_callbacks(&kvm_guest_cbs); 5656 5657 if (cpu_has_xsave) 5658 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 5659 5660 kvm_lapic_init(); 5661 #ifdef CONFIG_X86_64 5662 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 5663 #endif 5664 5665 return 0; 5666 5667 out_free_percpu: 5668 free_percpu(shared_msrs); 5669 out: 5670 return r; 5671 } 5672 5673 void kvm_arch_exit(void) 5674 { 5675 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 5676 5677 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5678 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 5679 CPUFREQ_TRANSITION_NOTIFIER); 5680 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5681 #ifdef CONFIG_X86_64 5682 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 5683 #endif 5684 kvm_x86_ops = NULL; 5685 kvm_mmu_module_exit(); 5686 free_percpu(shared_msrs); 5687 } 5688 5689 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 5690 { 5691 ++vcpu->stat.halt_exits; 5692 if (irqchip_in_kernel(vcpu->kvm)) { 5693 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 5694 return 1; 5695 } else { 5696 vcpu->run->exit_reason = KVM_EXIT_HLT; 5697 return 0; 5698 } 5699 } 5700 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 5701 5702 int kvm_hv_hypercall(struct kvm_vcpu *vcpu) 5703 { 5704 u64 param, ingpa, outgpa, ret; 5705 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; 5706 bool fast, longmode; 5707 5708 /* 5709 * hypercall generates UD from non zero cpl and real mode 5710 * per HYPER-V spec 5711 */ 5712 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { 5713 kvm_queue_exception(vcpu, UD_VECTOR); 5714 return 0; 5715 } 5716 5717 longmode = is_64_bit_mode(vcpu); 5718 5719 if (!longmode) { 5720 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | 5721 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); 5722 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | 5723 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); 5724 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | 5725 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); 5726 } 5727 #ifdef CONFIG_X86_64 5728 else { 5729 param = kvm_register_read(vcpu, VCPU_REGS_RCX); 5730 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); 5731 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); 5732 } 5733 #endif 5734 5735 code = param & 0xffff; 5736 fast = (param >> 16) & 0x1; 5737 rep_cnt = (param >> 32) & 0xfff; 5738 rep_idx = (param >> 48) & 0xfff; 5739 5740 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); 5741 5742 switch (code) { 5743 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: 5744 kvm_vcpu_on_spin(vcpu); 5745 break; 5746 default: 5747 res = HV_STATUS_INVALID_HYPERCALL_CODE; 5748 break; 5749 } 5750 5751 ret = res | (((u64)rep_done & 0xfff) << 32); 5752 if (longmode) { 5753 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 5754 } else { 5755 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); 5756 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); 5757 } 5758 5759 return 1; 5760 } 5761 5762 /* 5763 * kvm_pv_kick_cpu_op: Kick a vcpu. 5764 * 5765 * @apicid - apicid of vcpu to be kicked. 5766 */ 5767 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 5768 { 5769 struct kvm_lapic_irq lapic_irq; 5770 5771 lapic_irq.shorthand = 0; 5772 lapic_irq.dest_mode = 0; 5773 lapic_irq.dest_id = apicid; 5774 5775 lapic_irq.delivery_mode = APIC_DM_REMRD; 5776 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL); 5777 } 5778 5779 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 5780 { 5781 unsigned long nr, a0, a1, a2, a3, ret; 5782 int op_64_bit, r = 1; 5783 5784 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 5785 return kvm_hv_hypercall(vcpu); 5786 5787 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 5788 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 5789 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 5790 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 5791 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 5792 5793 trace_kvm_hypercall(nr, a0, a1, a2, a3); 5794 5795 op_64_bit = is_64_bit_mode(vcpu); 5796 if (!op_64_bit) { 5797 nr &= 0xFFFFFFFF; 5798 a0 &= 0xFFFFFFFF; 5799 a1 &= 0xFFFFFFFF; 5800 a2 &= 0xFFFFFFFF; 5801 a3 &= 0xFFFFFFFF; 5802 } 5803 5804 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 5805 ret = -KVM_EPERM; 5806 goto out; 5807 } 5808 5809 switch (nr) { 5810 case KVM_HC_VAPIC_POLL_IRQ: 5811 ret = 0; 5812 break; 5813 case KVM_HC_KICK_CPU: 5814 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 5815 ret = 0; 5816 break; 5817 default: 5818 ret = -KVM_ENOSYS; 5819 break; 5820 } 5821 out: 5822 if (!op_64_bit) 5823 ret = (u32)ret; 5824 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 5825 ++vcpu->stat.hypercalls; 5826 return r; 5827 } 5828 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 5829 5830 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 5831 { 5832 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5833 char instruction[3]; 5834 unsigned long rip = kvm_rip_read(vcpu); 5835 5836 kvm_x86_ops->patch_hypercall(vcpu, instruction); 5837 5838 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); 5839 } 5840 5841 /* 5842 * Check if userspace requested an interrupt window, and that the 5843 * interrupt window is open. 5844 * 5845 * No need to exit to userspace if we already have an interrupt queued. 5846 */ 5847 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 5848 { 5849 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && 5850 vcpu->run->request_interrupt_window && 5851 kvm_arch_interrupt_allowed(vcpu)); 5852 } 5853 5854 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 5855 { 5856 struct kvm_run *kvm_run = vcpu->run; 5857 5858 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 5859 kvm_run->cr8 = kvm_get_cr8(vcpu); 5860 kvm_run->apic_base = kvm_get_apic_base(vcpu); 5861 if (irqchip_in_kernel(vcpu->kvm)) 5862 kvm_run->ready_for_interrupt_injection = 1; 5863 else 5864 kvm_run->ready_for_interrupt_injection = 5865 kvm_arch_interrupt_allowed(vcpu) && 5866 !kvm_cpu_has_interrupt(vcpu) && 5867 !kvm_event_needs_reinjection(vcpu); 5868 } 5869 5870 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 5871 { 5872 int max_irr, tpr; 5873 5874 if (!kvm_x86_ops->update_cr8_intercept) 5875 return; 5876 5877 if (!vcpu->arch.apic) 5878 return; 5879 5880 if (!vcpu->arch.apic->vapic_addr) 5881 max_irr = kvm_lapic_find_highest_irr(vcpu); 5882 else 5883 max_irr = -1; 5884 5885 if (max_irr != -1) 5886 max_irr >>= 4; 5887 5888 tpr = kvm_lapic_get_cr8(vcpu); 5889 5890 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 5891 } 5892 5893 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 5894 { 5895 int r; 5896 5897 /* try to reinject previous events if any */ 5898 if (vcpu->arch.exception.pending) { 5899 trace_kvm_inj_exception(vcpu->arch.exception.nr, 5900 vcpu->arch.exception.has_error_code, 5901 vcpu->arch.exception.error_code); 5902 5903 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 5904 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 5905 X86_EFLAGS_RF); 5906 5907 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, 5908 vcpu->arch.exception.has_error_code, 5909 vcpu->arch.exception.error_code, 5910 vcpu->arch.exception.reinject); 5911 return 0; 5912 } 5913 5914 if (vcpu->arch.nmi_injected) { 5915 kvm_x86_ops->set_nmi(vcpu); 5916 return 0; 5917 } 5918 5919 if (vcpu->arch.interrupt.pending) { 5920 kvm_x86_ops->set_irq(vcpu); 5921 return 0; 5922 } 5923 5924 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 5925 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 5926 if (r != 0) 5927 return r; 5928 } 5929 5930 /* try to inject new event if pending */ 5931 if (vcpu->arch.nmi_pending) { 5932 if (kvm_x86_ops->nmi_allowed(vcpu)) { 5933 --vcpu->arch.nmi_pending; 5934 vcpu->arch.nmi_injected = true; 5935 kvm_x86_ops->set_nmi(vcpu); 5936 } 5937 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 5938 /* 5939 * Because interrupts can be injected asynchronously, we are 5940 * calling check_nested_events again here to avoid a race condition. 5941 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 5942 * proposal and current concerns. Perhaps we should be setting 5943 * KVM_REQ_EVENT only on certain events and not unconditionally? 5944 */ 5945 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 5946 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 5947 if (r != 0) 5948 return r; 5949 } 5950 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 5951 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 5952 false); 5953 kvm_x86_ops->set_irq(vcpu); 5954 } 5955 } 5956 return 0; 5957 } 5958 5959 static void process_nmi(struct kvm_vcpu *vcpu) 5960 { 5961 unsigned limit = 2; 5962 5963 /* 5964 * x86 is limited to one NMI running, and one NMI pending after it. 5965 * If an NMI is already in progress, limit further NMIs to just one. 5966 * Otherwise, allow two (and we'll inject the first one immediately). 5967 */ 5968 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 5969 limit = 1; 5970 5971 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 5972 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 5973 kvm_make_request(KVM_REQ_EVENT, vcpu); 5974 } 5975 5976 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 5977 { 5978 u64 eoi_exit_bitmap[4]; 5979 u32 tmr[8]; 5980 5981 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 5982 return; 5983 5984 memset(eoi_exit_bitmap, 0, 32); 5985 memset(tmr, 0, 32); 5986 5987 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr); 5988 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 5989 kvm_apic_update_tmr(vcpu, tmr); 5990 } 5991 5992 /* 5993 * Returns 1 to let __vcpu_run() continue the guest execution loop without 5994 * exiting to the userspace. Otherwise, the value will be returned to the 5995 * userspace. 5996 */ 5997 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 5998 { 5999 int r; 6000 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && 6001 vcpu->run->request_interrupt_window; 6002 bool req_immediate_exit = false; 6003 6004 if (vcpu->requests) { 6005 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 6006 kvm_mmu_unload(vcpu); 6007 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 6008 __kvm_migrate_timers(vcpu); 6009 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 6010 kvm_gen_update_masterclock(vcpu->kvm); 6011 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 6012 kvm_gen_kvmclock_update(vcpu); 6013 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 6014 r = kvm_guest_time_update(vcpu); 6015 if (unlikely(r)) 6016 goto out; 6017 } 6018 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 6019 kvm_mmu_sync_roots(vcpu); 6020 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 6021 kvm_x86_ops->tlb_flush(vcpu); 6022 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 6023 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 6024 r = 0; 6025 goto out; 6026 } 6027 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 6028 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 6029 r = 0; 6030 goto out; 6031 } 6032 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { 6033 vcpu->fpu_active = 0; 6034 kvm_x86_ops->fpu_deactivate(vcpu); 6035 } 6036 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 6037 /* Page is swapped out. Do synthetic halt */ 6038 vcpu->arch.apf.halted = true; 6039 r = 1; 6040 goto out; 6041 } 6042 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 6043 record_steal_time(vcpu); 6044 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 6045 process_nmi(vcpu); 6046 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 6047 kvm_handle_pmu_event(vcpu); 6048 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 6049 kvm_deliver_pmi(vcpu); 6050 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 6051 vcpu_scan_ioapic(vcpu); 6052 } 6053 6054 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 6055 kvm_apic_accept_events(vcpu); 6056 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 6057 r = 1; 6058 goto out; 6059 } 6060 6061 if (inject_pending_event(vcpu, req_int_win) != 0) 6062 req_immediate_exit = true; 6063 /* enable NMI/IRQ window open exits if needed */ 6064 else if (vcpu->arch.nmi_pending) 6065 kvm_x86_ops->enable_nmi_window(vcpu); 6066 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 6067 kvm_x86_ops->enable_irq_window(vcpu); 6068 6069 if (kvm_lapic_enabled(vcpu)) { 6070 /* 6071 * Update architecture specific hints for APIC 6072 * virtual interrupt delivery. 6073 */ 6074 if (kvm_x86_ops->hwapic_irr_update) 6075 kvm_x86_ops->hwapic_irr_update(vcpu, 6076 kvm_lapic_find_highest_irr(vcpu)); 6077 update_cr8_intercept(vcpu); 6078 kvm_lapic_sync_to_vapic(vcpu); 6079 } 6080 } 6081 6082 r = kvm_mmu_reload(vcpu); 6083 if (unlikely(r)) { 6084 goto cancel_injection; 6085 } 6086 6087 preempt_disable(); 6088 6089 kvm_x86_ops->prepare_guest_switch(vcpu); 6090 if (vcpu->fpu_active) 6091 kvm_load_guest_fpu(vcpu); 6092 kvm_load_guest_xcr0(vcpu); 6093 6094 vcpu->mode = IN_GUEST_MODE; 6095 6096 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6097 6098 /* We should set ->mode before check ->requests, 6099 * see the comment in make_all_cpus_request. 6100 */ 6101 smp_mb__after_srcu_read_unlock(); 6102 6103 local_irq_disable(); 6104 6105 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests 6106 || need_resched() || signal_pending(current)) { 6107 vcpu->mode = OUTSIDE_GUEST_MODE; 6108 smp_wmb(); 6109 local_irq_enable(); 6110 preempt_enable(); 6111 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6112 r = 1; 6113 goto cancel_injection; 6114 } 6115 6116 if (req_immediate_exit) 6117 smp_send_reschedule(vcpu->cpu); 6118 6119 kvm_guest_enter(); 6120 6121 if (unlikely(vcpu->arch.switch_db_regs)) { 6122 set_debugreg(0, 7); 6123 set_debugreg(vcpu->arch.eff_db[0], 0); 6124 set_debugreg(vcpu->arch.eff_db[1], 1); 6125 set_debugreg(vcpu->arch.eff_db[2], 2); 6126 set_debugreg(vcpu->arch.eff_db[3], 3); 6127 set_debugreg(vcpu->arch.dr6, 6); 6128 } 6129 6130 trace_kvm_entry(vcpu->vcpu_id); 6131 kvm_x86_ops->run(vcpu); 6132 6133 /* 6134 * Do this here before restoring debug registers on the host. And 6135 * since we do this before handling the vmexit, a DR access vmexit 6136 * can (a) read the correct value of the debug registers, (b) set 6137 * KVM_DEBUGREG_WONT_EXIT again. 6138 */ 6139 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 6140 int i; 6141 6142 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 6143 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 6144 for (i = 0; i < KVM_NR_DB_REGS; i++) 6145 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 6146 } 6147 6148 /* 6149 * If the guest has used debug registers, at least dr7 6150 * will be disabled while returning to the host. 6151 * If we don't have active breakpoints in the host, we don't 6152 * care about the messed up debug address registers. But if 6153 * we have some of them active, restore the old state. 6154 */ 6155 if (hw_breakpoint_active()) 6156 hw_breakpoint_restore(); 6157 6158 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, 6159 native_read_tsc()); 6160 6161 vcpu->mode = OUTSIDE_GUEST_MODE; 6162 smp_wmb(); 6163 6164 /* Interrupt is enabled by handle_external_intr() */ 6165 kvm_x86_ops->handle_external_intr(vcpu); 6166 6167 ++vcpu->stat.exits; 6168 6169 /* 6170 * We must have an instruction between local_irq_enable() and 6171 * kvm_guest_exit(), so the timer interrupt isn't delayed by 6172 * the interrupt shadow. The stat.exits increment will do nicely. 6173 * But we need to prevent reordering, hence this barrier(): 6174 */ 6175 barrier(); 6176 6177 kvm_guest_exit(); 6178 6179 preempt_enable(); 6180 6181 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6182 6183 /* 6184 * Profile KVM exit RIPs: 6185 */ 6186 if (unlikely(prof_on == KVM_PROFILING)) { 6187 unsigned long rip = kvm_rip_read(vcpu); 6188 profile_hit(KVM_PROFILING, (void *)rip); 6189 } 6190 6191 if (unlikely(vcpu->arch.tsc_always_catchup)) 6192 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6193 6194 if (vcpu->arch.apic_attention) 6195 kvm_lapic_sync_from_vapic(vcpu); 6196 6197 r = kvm_x86_ops->handle_exit(vcpu); 6198 return r; 6199 6200 cancel_injection: 6201 kvm_x86_ops->cancel_injection(vcpu); 6202 if (unlikely(vcpu->arch.apic_attention)) 6203 kvm_lapic_sync_from_vapic(vcpu); 6204 out: 6205 return r; 6206 } 6207 6208 6209 static int __vcpu_run(struct kvm_vcpu *vcpu) 6210 { 6211 int r; 6212 struct kvm *kvm = vcpu->kvm; 6213 6214 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6215 6216 r = 1; 6217 while (r > 0) { 6218 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 6219 !vcpu->arch.apf.halted) 6220 r = vcpu_enter_guest(vcpu); 6221 else { 6222 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6223 kvm_vcpu_block(vcpu); 6224 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6225 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) { 6226 kvm_apic_accept_events(vcpu); 6227 switch(vcpu->arch.mp_state) { 6228 case KVM_MP_STATE_HALTED: 6229 vcpu->arch.pv.pv_unhalted = false; 6230 vcpu->arch.mp_state = 6231 KVM_MP_STATE_RUNNABLE; 6232 case KVM_MP_STATE_RUNNABLE: 6233 vcpu->arch.apf.halted = false; 6234 break; 6235 case KVM_MP_STATE_INIT_RECEIVED: 6236 break; 6237 default: 6238 r = -EINTR; 6239 break; 6240 } 6241 } 6242 } 6243 6244 if (r <= 0) 6245 break; 6246 6247 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); 6248 if (kvm_cpu_has_pending_timer(vcpu)) 6249 kvm_inject_pending_timer_irqs(vcpu); 6250 6251 if (dm_request_for_irq_injection(vcpu)) { 6252 r = -EINTR; 6253 vcpu->run->exit_reason = KVM_EXIT_INTR; 6254 ++vcpu->stat.request_irq_exits; 6255 } 6256 6257 kvm_check_async_pf_completion(vcpu); 6258 6259 if (signal_pending(current)) { 6260 r = -EINTR; 6261 vcpu->run->exit_reason = KVM_EXIT_INTR; 6262 ++vcpu->stat.signal_exits; 6263 } 6264 if (need_resched()) { 6265 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6266 cond_resched(); 6267 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6268 } 6269 } 6270 6271 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6272 6273 return r; 6274 } 6275 6276 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 6277 { 6278 int r; 6279 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6280 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 6281 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6282 if (r != EMULATE_DONE) 6283 return 0; 6284 return 1; 6285 } 6286 6287 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 6288 { 6289 BUG_ON(!vcpu->arch.pio.count); 6290 6291 return complete_emulated_io(vcpu); 6292 } 6293 6294 /* 6295 * Implements the following, as a state machine: 6296 * 6297 * read: 6298 * for each fragment 6299 * for each mmio piece in the fragment 6300 * write gpa, len 6301 * exit 6302 * copy data 6303 * execute insn 6304 * 6305 * write: 6306 * for each fragment 6307 * for each mmio piece in the fragment 6308 * write gpa, len 6309 * copy data 6310 * exit 6311 */ 6312 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 6313 { 6314 struct kvm_run *run = vcpu->run; 6315 struct kvm_mmio_fragment *frag; 6316 unsigned len; 6317 6318 BUG_ON(!vcpu->mmio_needed); 6319 6320 /* Complete previous fragment */ 6321 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 6322 len = min(8u, frag->len); 6323 if (!vcpu->mmio_is_write) 6324 memcpy(frag->data, run->mmio.data, len); 6325 6326 if (frag->len <= 8) { 6327 /* Switch to the next fragment. */ 6328 frag++; 6329 vcpu->mmio_cur_fragment++; 6330 } else { 6331 /* Go forward to the next mmio piece. */ 6332 frag->data += len; 6333 frag->gpa += len; 6334 frag->len -= len; 6335 } 6336 6337 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 6338 vcpu->mmio_needed = 0; 6339 6340 /* FIXME: return into emulator if single-stepping. */ 6341 if (vcpu->mmio_is_write) 6342 return 1; 6343 vcpu->mmio_read_completed = 1; 6344 return complete_emulated_io(vcpu); 6345 } 6346 6347 run->exit_reason = KVM_EXIT_MMIO; 6348 run->mmio.phys_addr = frag->gpa; 6349 if (vcpu->mmio_is_write) 6350 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 6351 run->mmio.len = min(8u, frag->len); 6352 run->mmio.is_write = vcpu->mmio_is_write; 6353 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6354 return 0; 6355 } 6356 6357 6358 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 6359 { 6360 int r; 6361 sigset_t sigsaved; 6362 6363 if (!tsk_used_math(current) && init_fpu(current)) 6364 return -ENOMEM; 6365 6366 if (vcpu->sigset_active) 6367 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); 6368 6369 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 6370 kvm_vcpu_block(vcpu); 6371 kvm_apic_accept_events(vcpu); 6372 clear_bit(KVM_REQ_UNHALT, &vcpu->requests); 6373 r = -EAGAIN; 6374 goto out; 6375 } 6376 6377 /* re-sync apic's tpr */ 6378 if (!irqchip_in_kernel(vcpu->kvm)) { 6379 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 6380 r = -EINVAL; 6381 goto out; 6382 } 6383 } 6384 6385 if (unlikely(vcpu->arch.complete_userspace_io)) { 6386 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 6387 vcpu->arch.complete_userspace_io = NULL; 6388 r = cui(vcpu); 6389 if (r <= 0) 6390 goto out; 6391 } else 6392 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 6393 6394 r = __vcpu_run(vcpu); 6395 6396 out: 6397 post_kvm_run_save(vcpu); 6398 if (vcpu->sigset_active) 6399 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 6400 6401 return r; 6402 } 6403 6404 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6405 { 6406 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 6407 /* 6408 * We are here if userspace calls get_regs() in the middle of 6409 * instruction emulation. Registers state needs to be copied 6410 * back from emulation context to vcpu. Userspace shouldn't do 6411 * that usually, but some bad designed PV devices (vmware 6412 * backdoor interface) need this to work 6413 */ 6414 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 6415 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6416 } 6417 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 6418 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 6419 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 6420 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 6421 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 6422 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 6423 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 6424 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 6425 #ifdef CONFIG_X86_64 6426 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 6427 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 6428 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 6429 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 6430 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 6431 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 6432 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 6433 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 6434 #endif 6435 6436 regs->rip = kvm_rip_read(vcpu); 6437 regs->rflags = kvm_get_rflags(vcpu); 6438 6439 return 0; 6440 } 6441 6442 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6443 { 6444 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 6445 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6446 6447 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 6448 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 6449 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 6450 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 6451 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 6452 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 6453 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 6454 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 6455 #ifdef CONFIG_X86_64 6456 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 6457 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 6458 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 6459 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 6460 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 6461 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 6462 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 6463 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 6464 #endif 6465 6466 kvm_rip_write(vcpu, regs->rip); 6467 kvm_set_rflags(vcpu, regs->rflags); 6468 6469 vcpu->arch.exception.pending = false; 6470 6471 kvm_make_request(KVM_REQ_EVENT, vcpu); 6472 6473 return 0; 6474 } 6475 6476 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 6477 { 6478 struct kvm_segment cs; 6479 6480 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 6481 *db = cs.db; 6482 *l = cs.l; 6483 } 6484 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 6485 6486 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 6487 struct kvm_sregs *sregs) 6488 { 6489 struct desc_ptr dt; 6490 6491 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 6492 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 6493 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 6494 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 6495 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 6496 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 6497 6498 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 6499 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 6500 6501 kvm_x86_ops->get_idt(vcpu, &dt); 6502 sregs->idt.limit = dt.size; 6503 sregs->idt.base = dt.address; 6504 kvm_x86_ops->get_gdt(vcpu, &dt); 6505 sregs->gdt.limit = dt.size; 6506 sregs->gdt.base = dt.address; 6507 6508 sregs->cr0 = kvm_read_cr0(vcpu); 6509 sregs->cr2 = vcpu->arch.cr2; 6510 sregs->cr3 = kvm_read_cr3(vcpu); 6511 sregs->cr4 = kvm_read_cr4(vcpu); 6512 sregs->cr8 = kvm_get_cr8(vcpu); 6513 sregs->efer = vcpu->arch.efer; 6514 sregs->apic_base = kvm_get_apic_base(vcpu); 6515 6516 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 6517 6518 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) 6519 set_bit(vcpu->arch.interrupt.nr, 6520 (unsigned long *)sregs->interrupt_bitmap); 6521 6522 return 0; 6523 } 6524 6525 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 6526 struct kvm_mp_state *mp_state) 6527 { 6528 kvm_apic_accept_events(vcpu); 6529 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 6530 vcpu->arch.pv.pv_unhalted) 6531 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 6532 else 6533 mp_state->mp_state = vcpu->arch.mp_state; 6534 6535 return 0; 6536 } 6537 6538 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 6539 struct kvm_mp_state *mp_state) 6540 { 6541 if (!kvm_vcpu_has_lapic(vcpu) && 6542 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 6543 return -EINVAL; 6544 6545 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 6546 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 6547 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 6548 } else 6549 vcpu->arch.mp_state = mp_state->mp_state; 6550 kvm_make_request(KVM_REQ_EVENT, vcpu); 6551 return 0; 6552 } 6553 6554 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 6555 int reason, bool has_error_code, u32 error_code) 6556 { 6557 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6558 int ret; 6559 6560 init_emulate_ctxt(vcpu); 6561 6562 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 6563 has_error_code, error_code); 6564 6565 if (ret) 6566 return EMULATE_FAIL; 6567 6568 kvm_rip_write(vcpu, ctxt->eip); 6569 kvm_set_rflags(vcpu, ctxt->eflags); 6570 kvm_make_request(KVM_REQ_EVENT, vcpu); 6571 return EMULATE_DONE; 6572 } 6573 EXPORT_SYMBOL_GPL(kvm_task_switch); 6574 6575 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 6576 struct kvm_sregs *sregs) 6577 { 6578 struct msr_data apic_base_msr; 6579 int mmu_reset_needed = 0; 6580 int pending_vec, max_bits, idx; 6581 struct desc_ptr dt; 6582 6583 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) 6584 return -EINVAL; 6585 6586 dt.size = sregs->idt.limit; 6587 dt.address = sregs->idt.base; 6588 kvm_x86_ops->set_idt(vcpu, &dt); 6589 dt.size = sregs->gdt.limit; 6590 dt.address = sregs->gdt.base; 6591 kvm_x86_ops->set_gdt(vcpu, &dt); 6592 6593 vcpu->arch.cr2 = sregs->cr2; 6594 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 6595 vcpu->arch.cr3 = sregs->cr3; 6596 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 6597 6598 kvm_set_cr8(vcpu, sregs->cr8); 6599 6600 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 6601 kvm_x86_ops->set_efer(vcpu, sregs->efer); 6602 apic_base_msr.data = sregs->apic_base; 6603 apic_base_msr.host_initiated = true; 6604 kvm_set_apic_base(vcpu, &apic_base_msr); 6605 6606 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 6607 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 6608 vcpu->arch.cr0 = sregs->cr0; 6609 6610 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 6611 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 6612 if (sregs->cr4 & X86_CR4_OSXSAVE) 6613 kvm_update_cpuid(vcpu); 6614 6615 idx = srcu_read_lock(&vcpu->kvm->srcu); 6616 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 6617 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 6618 mmu_reset_needed = 1; 6619 } 6620 srcu_read_unlock(&vcpu->kvm->srcu, idx); 6621 6622 if (mmu_reset_needed) 6623 kvm_mmu_reset_context(vcpu); 6624 6625 max_bits = KVM_NR_INTERRUPTS; 6626 pending_vec = find_first_bit( 6627 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 6628 if (pending_vec < max_bits) { 6629 kvm_queue_interrupt(vcpu, pending_vec, false); 6630 pr_debug("Set back pending irq %d\n", pending_vec); 6631 } 6632 6633 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 6634 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 6635 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 6636 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 6637 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 6638 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 6639 6640 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 6641 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 6642 6643 update_cr8_intercept(vcpu); 6644 6645 /* Older userspace won't unhalt the vcpu on reset. */ 6646 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 6647 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 6648 !is_protmode(vcpu)) 6649 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 6650 6651 kvm_make_request(KVM_REQ_EVENT, vcpu); 6652 6653 return 0; 6654 } 6655 6656 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 6657 struct kvm_guest_debug *dbg) 6658 { 6659 unsigned long rflags; 6660 int i, r; 6661 6662 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 6663 r = -EBUSY; 6664 if (vcpu->arch.exception.pending) 6665 goto out; 6666 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 6667 kvm_queue_exception(vcpu, DB_VECTOR); 6668 else 6669 kvm_queue_exception(vcpu, BP_VECTOR); 6670 } 6671 6672 /* 6673 * Read rflags as long as potentially injected trace flags are still 6674 * filtered out. 6675 */ 6676 rflags = kvm_get_rflags(vcpu); 6677 6678 vcpu->guest_debug = dbg->control; 6679 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 6680 vcpu->guest_debug = 0; 6681 6682 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 6683 for (i = 0; i < KVM_NR_DB_REGS; ++i) 6684 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 6685 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 6686 } else { 6687 for (i = 0; i < KVM_NR_DB_REGS; i++) 6688 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 6689 } 6690 kvm_update_dr7(vcpu); 6691 6692 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6693 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 6694 get_segment_base(vcpu, VCPU_SREG_CS); 6695 6696 /* 6697 * Trigger an rflags update that will inject or remove the trace 6698 * flags. 6699 */ 6700 kvm_set_rflags(vcpu, rflags); 6701 6702 kvm_x86_ops->update_db_bp_intercept(vcpu); 6703 6704 r = 0; 6705 6706 out: 6707 6708 return r; 6709 } 6710 6711 /* 6712 * Translate a guest virtual address to a guest physical address. 6713 */ 6714 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 6715 struct kvm_translation *tr) 6716 { 6717 unsigned long vaddr = tr->linear_address; 6718 gpa_t gpa; 6719 int idx; 6720 6721 idx = srcu_read_lock(&vcpu->kvm->srcu); 6722 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 6723 srcu_read_unlock(&vcpu->kvm->srcu, idx); 6724 tr->physical_address = gpa; 6725 tr->valid = gpa != UNMAPPED_GVA; 6726 tr->writeable = 1; 6727 tr->usermode = 0; 6728 6729 return 0; 6730 } 6731 6732 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 6733 { 6734 struct i387_fxsave_struct *fxsave = 6735 &vcpu->arch.guest_fpu.state->fxsave; 6736 6737 memcpy(fpu->fpr, fxsave->st_space, 128); 6738 fpu->fcw = fxsave->cwd; 6739 fpu->fsw = fxsave->swd; 6740 fpu->ftwx = fxsave->twd; 6741 fpu->last_opcode = fxsave->fop; 6742 fpu->last_ip = fxsave->rip; 6743 fpu->last_dp = fxsave->rdp; 6744 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 6745 6746 return 0; 6747 } 6748 6749 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 6750 { 6751 struct i387_fxsave_struct *fxsave = 6752 &vcpu->arch.guest_fpu.state->fxsave; 6753 6754 memcpy(fxsave->st_space, fpu->fpr, 128); 6755 fxsave->cwd = fpu->fcw; 6756 fxsave->swd = fpu->fsw; 6757 fxsave->twd = fpu->ftwx; 6758 fxsave->fop = fpu->last_opcode; 6759 fxsave->rip = fpu->last_ip; 6760 fxsave->rdp = fpu->last_dp; 6761 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 6762 6763 return 0; 6764 } 6765 6766 int fx_init(struct kvm_vcpu *vcpu) 6767 { 6768 int err; 6769 6770 err = fpu_alloc(&vcpu->arch.guest_fpu); 6771 if (err) 6772 return err; 6773 6774 fpu_finit(&vcpu->arch.guest_fpu); 6775 6776 /* 6777 * Ensure guest xcr0 is valid for loading 6778 */ 6779 vcpu->arch.xcr0 = XSTATE_FP; 6780 6781 vcpu->arch.cr0 |= X86_CR0_ET; 6782 6783 return 0; 6784 } 6785 EXPORT_SYMBOL_GPL(fx_init); 6786 6787 static void fx_free(struct kvm_vcpu *vcpu) 6788 { 6789 fpu_free(&vcpu->arch.guest_fpu); 6790 } 6791 6792 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 6793 { 6794 if (vcpu->guest_fpu_loaded) 6795 return; 6796 6797 /* 6798 * Restore all possible states in the guest, 6799 * and assume host would use all available bits. 6800 * Guest xcr0 would be loaded later. 6801 */ 6802 kvm_put_guest_xcr0(vcpu); 6803 vcpu->guest_fpu_loaded = 1; 6804 __kernel_fpu_begin(); 6805 fpu_restore_checking(&vcpu->arch.guest_fpu); 6806 trace_kvm_fpu(1); 6807 } 6808 6809 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 6810 { 6811 kvm_put_guest_xcr0(vcpu); 6812 6813 if (!vcpu->guest_fpu_loaded) 6814 return; 6815 6816 vcpu->guest_fpu_loaded = 0; 6817 fpu_save_init(&vcpu->arch.guest_fpu); 6818 __kernel_fpu_end(); 6819 ++vcpu->stat.fpu_reload; 6820 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); 6821 trace_kvm_fpu(0); 6822 } 6823 6824 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 6825 { 6826 kvmclock_reset(vcpu); 6827 6828 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 6829 fx_free(vcpu); 6830 kvm_x86_ops->vcpu_free(vcpu); 6831 } 6832 6833 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 6834 unsigned int id) 6835 { 6836 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 6837 printk_once(KERN_WARNING 6838 "kvm: SMP vm created on host with unstable TSC; " 6839 "guest TSC will not be reliable\n"); 6840 return kvm_x86_ops->vcpu_create(kvm, id); 6841 } 6842 6843 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 6844 { 6845 int r; 6846 6847 vcpu->arch.mtrr_state.have_fixed = 1; 6848 r = vcpu_load(vcpu); 6849 if (r) 6850 return r; 6851 kvm_vcpu_reset(vcpu); 6852 kvm_mmu_setup(vcpu); 6853 vcpu_put(vcpu); 6854 6855 return r; 6856 } 6857 6858 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 6859 { 6860 int r; 6861 struct msr_data msr; 6862 struct kvm *kvm = vcpu->kvm; 6863 6864 r = vcpu_load(vcpu); 6865 if (r) 6866 return r; 6867 msr.data = 0x0; 6868 msr.index = MSR_IA32_TSC; 6869 msr.host_initiated = true; 6870 kvm_write_tsc(vcpu, &msr); 6871 vcpu_put(vcpu); 6872 6873 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 6874 KVMCLOCK_SYNC_PERIOD); 6875 6876 return r; 6877 } 6878 6879 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 6880 { 6881 int r; 6882 vcpu->arch.apf.msr_val = 0; 6883 6884 r = vcpu_load(vcpu); 6885 BUG_ON(r); 6886 kvm_mmu_unload(vcpu); 6887 vcpu_put(vcpu); 6888 6889 fx_free(vcpu); 6890 kvm_x86_ops->vcpu_free(vcpu); 6891 } 6892 6893 void kvm_vcpu_reset(struct kvm_vcpu *vcpu) 6894 { 6895 atomic_set(&vcpu->arch.nmi_queued, 0); 6896 vcpu->arch.nmi_pending = 0; 6897 vcpu->arch.nmi_injected = false; 6898 kvm_clear_interrupt_queue(vcpu); 6899 kvm_clear_exception_queue(vcpu); 6900 6901 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 6902 vcpu->arch.dr6 = DR6_INIT; 6903 kvm_update_dr6(vcpu); 6904 vcpu->arch.dr7 = DR7_FIXED_1; 6905 kvm_update_dr7(vcpu); 6906 6907 kvm_make_request(KVM_REQ_EVENT, vcpu); 6908 vcpu->arch.apf.msr_val = 0; 6909 vcpu->arch.st.msr_val = 0; 6910 6911 kvmclock_reset(vcpu); 6912 6913 kvm_clear_async_pf_completion_queue(vcpu); 6914 kvm_async_pf_hash_reset(vcpu); 6915 vcpu->arch.apf.halted = false; 6916 6917 kvm_pmu_reset(vcpu); 6918 6919 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 6920 vcpu->arch.regs_avail = ~0; 6921 vcpu->arch.regs_dirty = ~0; 6922 6923 kvm_x86_ops->vcpu_reset(vcpu); 6924 } 6925 6926 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector) 6927 { 6928 struct kvm_segment cs; 6929 6930 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 6931 cs.selector = vector << 8; 6932 cs.base = vector << 12; 6933 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 6934 kvm_rip_write(vcpu, 0); 6935 } 6936 6937 int kvm_arch_hardware_enable(void *garbage) 6938 { 6939 struct kvm *kvm; 6940 struct kvm_vcpu *vcpu; 6941 int i; 6942 int ret; 6943 u64 local_tsc; 6944 u64 max_tsc = 0; 6945 bool stable, backwards_tsc = false; 6946 6947 kvm_shared_msr_cpu_online(); 6948 ret = kvm_x86_ops->hardware_enable(garbage); 6949 if (ret != 0) 6950 return ret; 6951 6952 local_tsc = native_read_tsc(); 6953 stable = !check_tsc_unstable(); 6954 list_for_each_entry(kvm, &vm_list, vm_list) { 6955 kvm_for_each_vcpu(i, vcpu, kvm) { 6956 if (!stable && vcpu->cpu == smp_processor_id()) 6957 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests); 6958 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 6959 backwards_tsc = true; 6960 if (vcpu->arch.last_host_tsc > max_tsc) 6961 max_tsc = vcpu->arch.last_host_tsc; 6962 } 6963 } 6964 } 6965 6966 /* 6967 * Sometimes, even reliable TSCs go backwards. This happens on 6968 * platforms that reset TSC during suspend or hibernate actions, but 6969 * maintain synchronization. We must compensate. Fortunately, we can 6970 * detect that condition here, which happens early in CPU bringup, 6971 * before any KVM threads can be running. Unfortunately, we can't 6972 * bring the TSCs fully up to date with real time, as we aren't yet far 6973 * enough into CPU bringup that we know how much real time has actually 6974 * elapsed; our helper function, get_kernel_ns() will be using boot 6975 * variables that haven't been updated yet. 6976 * 6977 * So we simply find the maximum observed TSC above, then record the 6978 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 6979 * the adjustment will be applied. Note that we accumulate 6980 * adjustments, in case multiple suspend cycles happen before some VCPU 6981 * gets a chance to run again. In the event that no KVM threads get a 6982 * chance to run, we will miss the entire elapsed period, as we'll have 6983 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 6984 * loose cycle time. This isn't too big a deal, since the loss will be 6985 * uniform across all VCPUs (not to mention the scenario is extremely 6986 * unlikely). It is possible that a second hibernate recovery happens 6987 * much faster than a first, causing the observed TSC here to be 6988 * smaller; this would require additional padding adjustment, which is 6989 * why we set last_host_tsc to the local tsc observed here. 6990 * 6991 * N.B. - this code below runs only on platforms with reliable TSC, 6992 * as that is the only way backwards_tsc is set above. Also note 6993 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 6994 * have the same delta_cyc adjustment applied if backwards_tsc 6995 * is detected. Note further, this adjustment is only done once, 6996 * as we reset last_host_tsc on all VCPUs to stop this from being 6997 * called multiple times (one for each physical CPU bringup). 6998 * 6999 * Platforms with unreliable TSCs don't have to deal with this, they 7000 * will be compensated by the logic in vcpu_load, which sets the TSC to 7001 * catchup mode. This will catchup all VCPUs to real time, but cannot 7002 * guarantee that they stay in perfect synchronization. 7003 */ 7004 if (backwards_tsc) { 7005 u64 delta_cyc = max_tsc - local_tsc; 7006 backwards_tsc_observed = true; 7007 list_for_each_entry(kvm, &vm_list, vm_list) { 7008 kvm_for_each_vcpu(i, vcpu, kvm) { 7009 vcpu->arch.tsc_offset_adjustment += delta_cyc; 7010 vcpu->arch.last_host_tsc = local_tsc; 7011 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, 7012 &vcpu->requests); 7013 } 7014 7015 /* 7016 * We have to disable TSC offset matching.. if you were 7017 * booting a VM while issuing an S4 host suspend.... 7018 * you may have some problem. Solving this issue is 7019 * left as an exercise to the reader. 7020 */ 7021 kvm->arch.last_tsc_nsec = 0; 7022 kvm->arch.last_tsc_write = 0; 7023 } 7024 7025 } 7026 return 0; 7027 } 7028 7029 void kvm_arch_hardware_disable(void *garbage) 7030 { 7031 kvm_x86_ops->hardware_disable(garbage); 7032 drop_user_return_notifiers(garbage); 7033 } 7034 7035 int kvm_arch_hardware_setup(void) 7036 { 7037 return kvm_x86_ops->hardware_setup(); 7038 } 7039 7040 void kvm_arch_hardware_unsetup(void) 7041 { 7042 kvm_x86_ops->hardware_unsetup(); 7043 } 7044 7045 void kvm_arch_check_processor_compat(void *rtn) 7046 { 7047 kvm_x86_ops->check_processor_compatibility(rtn); 7048 } 7049 7050 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) 7051 { 7052 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL); 7053 } 7054 7055 struct static_key kvm_no_apic_vcpu __read_mostly; 7056 7057 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 7058 { 7059 struct page *page; 7060 struct kvm *kvm; 7061 int r; 7062 7063 BUG_ON(vcpu->kvm == NULL); 7064 kvm = vcpu->kvm; 7065 7066 vcpu->arch.pv.pv_unhalted = false; 7067 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 7068 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu)) 7069 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7070 else 7071 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 7072 7073 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 7074 if (!page) { 7075 r = -ENOMEM; 7076 goto fail; 7077 } 7078 vcpu->arch.pio_data = page_address(page); 7079 7080 kvm_set_tsc_khz(vcpu, max_tsc_khz); 7081 7082 r = kvm_mmu_create(vcpu); 7083 if (r < 0) 7084 goto fail_free_pio_data; 7085 7086 if (irqchip_in_kernel(kvm)) { 7087 r = kvm_create_lapic(vcpu); 7088 if (r < 0) 7089 goto fail_mmu_destroy; 7090 } else 7091 static_key_slow_inc(&kvm_no_apic_vcpu); 7092 7093 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 7094 GFP_KERNEL); 7095 if (!vcpu->arch.mce_banks) { 7096 r = -ENOMEM; 7097 goto fail_free_lapic; 7098 } 7099 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 7100 7101 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 7102 r = -ENOMEM; 7103 goto fail_free_mce_banks; 7104 } 7105 7106 r = fx_init(vcpu); 7107 if (r) 7108 goto fail_free_wbinvd_dirty_mask; 7109 7110 vcpu->arch.ia32_tsc_adjust_msr = 0x0; 7111 vcpu->arch.pv_time_enabled = false; 7112 7113 vcpu->arch.guest_supported_xcr0 = 0; 7114 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 7115 7116 kvm_async_pf_hash_reset(vcpu); 7117 kvm_pmu_init(vcpu); 7118 7119 return 0; 7120 fail_free_wbinvd_dirty_mask: 7121 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 7122 fail_free_mce_banks: 7123 kfree(vcpu->arch.mce_banks); 7124 fail_free_lapic: 7125 kvm_free_lapic(vcpu); 7126 fail_mmu_destroy: 7127 kvm_mmu_destroy(vcpu); 7128 fail_free_pio_data: 7129 free_page((unsigned long)vcpu->arch.pio_data); 7130 fail: 7131 return r; 7132 } 7133 7134 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 7135 { 7136 int idx; 7137 7138 kvm_pmu_destroy(vcpu); 7139 kfree(vcpu->arch.mce_banks); 7140 kvm_free_lapic(vcpu); 7141 idx = srcu_read_lock(&vcpu->kvm->srcu); 7142 kvm_mmu_destroy(vcpu); 7143 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7144 free_page((unsigned long)vcpu->arch.pio_data); 7145 if (!irqchip_in_kernel(vcpu->kvm)) 7146 static_key_slow_dec(&kvm_no_apic_vcpu); 7147 } 7148 7149 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 7150 { 7151 if (type) 7152 return -EINVAL; 7153 7154 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 7155 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 7156 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 7157 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 7158 7159 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 7160 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 7161 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 7162 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 7163 &kvm->arch.irq_sources_bitmap); 7164 7165 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 7166 mutex_init(&kvm->arch.apic_map_lock); 7167 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 7168 7169 pvclock_update_vm_gtod_copy(kvm); 7170 7171 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 7172 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 7173 7174 return 0; 7175 } 7176 7177 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 7178 { 7179 int r; 7180 r = vcpu_load(vcpu); 7181 BUG_ON(r); 7182 kvm_mmu_unload(vcpu); 7183 vcpu_put(vcpu); 7184 } 7185 7186 static void kvm_free_vcpus(struct kvm *kvm) 7187 { 7188 unsigned int i; 7189 struct kvm_vcpu *vcpu; 7190 7191 /* 7192 * Unpin any mmu pages first. 7193 */ 7194 kvm_for_each_vcpu(i, vcpu, kvm) { 7195 kvm_clear_async_pf_completion_queue(vcpu); 7196 kvm_unload_vcpu_mmu(vcpu); 7197 } 7198 kvm_for_each_vcpu(i, vcpu, kvm) 7199 kvm_arch_vcpu_free(vcpu); 7200 7201 mutex_lock(&kvm->lock); 7202 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 7203 kvm->vcpus[i] = NULL; 7204 7205 atomic_set(&kvm->online_vcpus, 0); 7206 mutex_unlock(&kvm->lock); 7207 } 7208 7209 void kvm_arch_sync_events(struct kvm *kvm) 7210 { 7211 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 7212 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 7213 kvm_free_all_assigned_devices(kvm); 7214 kvm_free_pit(kvm); 7215 } 7216 7217 void kvm_arch_destroy_vm(struct kvm *kvm) 7218 { 7219 if (current->mm == kvm->mm) { 7220 /* 7221 * Free memory regions allocated on behalf of userspace, 7222 * unless the the memory map has changed due to process exit 7223 * or fd copying. 7224 */ 7225 struct kvm_userspace_memory_region mem; 7226 memset(&mem, 0, sizeof(mem)); 7227 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; 7228 kvm_set_memory_region(kvm, &mem); 7229 7230 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; 7231 kvm_set_memory_region(kvm, &mem); 7232 7233 mem.slot = TSS_PRIVATE_MEMSLOT; 7234 kvm_set_memory_region(kvm, &mem); 7235 } 7236 kvm_iommu_unmap_guest(kvm); 7237 kfree(kvm->arch.vpic); 7238 kfree(kvm->arch.vioapic); 7239 kvm_free_vcpus(kvm); 7240 if (kvm->arch.apic_access_page) 7241 put_page(kvm->arch.apic_access_page); 7242 if (kvm->arch.ept_identity_pagetable) 7243 put_page(kvm->arch.ept_identity_pagetable); 7244 kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 7245 } 7246 7247 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 7248 struct kvm_memory_slot *dont) 7249 { 7250 int i; 7251 7252 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7253 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 7254 kvm_kvfree(free->arch.rmap[i]); 7255 free->arch.rmap[i] = NULL; 7256 } 7257 if (i == 0) 7258 continue; 7259 7260 if (!dont || free->arch.lpage_info[i - 1] != 7261 dont->arch.lpage_info[i - 1]) { 7262 kvm_kvfree(free->arch.lpage_info[i - 1]); 7263 free->arch.lpage_info[i - 1] = NULL; 7264 } 7265 } 7266 } 7267 7268 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 7269 unsigned long npages) 7270 { 7271 int i; 7272 7273 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7274 unsigned long ugfn; 7275 int lpages; 7276 int level = i + 1; 7277 7278 lpages = gfn_to_index(slot->base_gfn + npages - 1, 7279 slot->base_gfn, level) + 1; 7280 7281 slot->arch.rmap[i] = 7282 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); 7283 if (!slot->arch.rmap[i]) 7284 goto out_free; 7285 if (i == 0) 7286 continue; 7287 7288 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages * 7289 sizeof(*slot->arch.lpage_info[i - 1])); 7290 if (!slot->arch.lpage_info[i - 1]) 7291 goto out_free; 7292 7293 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 7294 slot->arch.lpage_info[i - 1][0].write_count = 1; 7295 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 7296 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1; 7297 ugfn = slot->userspace_addr >> PAGE_SHIFT; 7298 /* 7299 * If the gfn and userspace address are not aligned wrt each 7300 * other, or if explicitly asked to, disable large page 7301 * support for this slot 7302 */ 7303 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 7304 !kvm_largepages_enabled()) { 7305 unsigned long j; 7306 7307 for (j = 0; j < lpages; ++j) 7308 slot->arch.lpage_info[i - 1][j].write_count = 1; 7309 } 7310 } 7311 7312 return 0; 7313 7314 out_free: 7315 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7316 kvm_kvfree(slot->arch.rmap[i]); 7317 slot->arch.rmap[i] = NULL; 7318 if (i == 0) 7319 continue; 7320 7321 kvm_kvfree(slot->arch.lpage_info[i - 1]); 7322 slot->arch.lpage_info[i - 1] = NULL; 7323 } 7324 return -ENOMEM; 7325 } 7326 7327 void kvm_arch_memslots_updated(struct kvm *kvm) 7328 { 7329 /* 7330 * memslots->generation has been incremented. 7331 * mmio generation may have reached its maximum value. 7332 */ 7333 kvm_mmu_invalidate_mmio_sptes(kvm); 7334 } 7335 7336 int kvm_arch_prepare_memory_region(struct kvm *kvm, 7337 struct kvm_memory_slot *memslot, 7338 struct kvm_userspace_memory_region *mem, 7339 enum kvm_mr_change change) 7340 { 7341 /* 7342 * Only private memory slots need to be mapped here since 7343 * KVM_SET_MEMORY_REGION ioctl is no longer supported. 7344 */ 7345 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) { 7346 unsigned long userspace_addr; 7347 7348 /* 7349 * MAP_SHARED to prevent internal slot pages from being moved 7350 * by fork()/COW. 7351 */ 7352 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE, 7353 PROT_READ | PROT_WRITE, 7354 MAP_SHARED | MAP_ANONYMOUS, 0); 7355 7356 if (IS_ERR((void *)userspace_addr)) 7357 return PTR_ERR((void *)userspace_addr); 7358 7359 memslot->userspace_addr = userspace_addr; 7360 } 7361 7362 return 0; 7363 } 7364 7365 void kvm_arch_commit_memory_region(struct kvm *kvm, 7366 struct kvm_userspace_memory_region *mem, 7367 const struct kvm_memory_slot *old, 7368 enum kvm_mr_change change) 7369 { 7370 7371 int nr_mmu_pages = 0; 7372 7373 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) { 7374 int ret; 7375 7376 ret = vm_munmap(old->userspace_addr, 7377 old->npages * PAGE_SIZE); 7378 if (ret < 0) 7379 printk(KERN_WARNING 7380 "kvm_vm_ioctl_set_memory_region: " 7381 "failed to munmap memory\n"); 7382 } 7383 7384 if (!kvm->arch.n_requested_mmu_pages) 7385 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 7386 7387 if (nr_mmu_pages) 7388 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 7389 /* 7390 * Write protect all pages for dirty logging. 7391 * 7392 * All the sptes including the large sptes which point to this 7393 * slot are set to readonly. We can not create any new large 7394 * spte on this slot until the end of the logging. 7395 * 7396 * See the comments in fast_page_fault(). 7397 */ 7398 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES)) 7399 kvm_mmu_slot_remove_write_access(kvm, mem->slot); 7400 } 7401 7402 void kvm_arch_flush_shadow_all(struct kvm *kvm) 7403 { 7404 kvm_mmu_invalidate_zap_all_pages(kvm); 7405 } 7406 7407 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 7408 struct kvm_memory_slot *slot) 7409 { 7410 kvm_mmu_invalidate_zap_all_pages(kvm); 7411 } 7412 7413 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 7414 { 7415 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 7416 kvm_x86_ops->check_nested_events(vcpu, false); 7417 7418 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 7419 !vcpu->arch.apf.halted) 7420 || !list_empty_careful(&vcpu->async_pf.done) 7421 || kvm_apic_has_events(vcpu) 7422 || vcpu->arch.pv.pv_unhalted 7423 || atomic_read(&vcpu->arch.nmi_queued) || 7424 (kvm_arch_interrupt_allowed(vcpu) && 7425 kvm_cpu_has_interrupt(vcpu)); 7426 } 7427 7428 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 7429 { 7430 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 7431 } 7432 7433 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 7434 { 7435 return kvm_x86_ops->interrupt_allowed(vcpu); 7436 } 7437 7438 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 7439 { 7440 unsigned long current_rip = kvm_rip_read(vcpu) + 7441 get_segment_base(vcpu, VCPU_SREG_CS); 7442 7443 return current_rip == linear_rip; 7444 } 7445 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 7446 7447 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 7448 { 7449 unsigned long rflags; 7450 7451 rflags = kvm_x86_ops->get_rflags(vcpu); 7452 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 7453 rflags &= ~X86_EFLAGS_TF; 7454 return rflags; 7455 } 7456 EXPORT_SYMBOL_GPL(kvm_get_rflags); 7457 7458 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 7459 { 7460 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 7461 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 7462 rflags |= X86_EFLAGS_TF; 7463 kvm_x86_ops->set_rflags(vcpu, rflags); 7464 } 7465 7466 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 7467 { 7468 __kvm_set_rflags(vcpu, rflags); 7469 kvm_make_request(KVM_REQ_EVENT, vcpu); 7470 } 7471 EXPORT_SYMBOL_GPL(kvm_set_rflags); 7472 7473 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 7474 { 7475 int r; 7476 7477 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 7478 work->wakeup_all) 7479 return; 7480 7481 r = kvm_mmu_reload(vcpu); 7482 if (unlikely(r)) 7483 return; 7484 7485 if (!vcpu->arch.mmu.direct_map && 7486 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 7487 return; 7488 7489 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 7490 } 7491 7492 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 7493 { 7494 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 7495 } 7496 7497 static inline u32 kvm_async_pf_next_probe(u32 key) 7498 { 7499 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 7500 } 7501 7502 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7503 { 7504 u32 key = kvm_async_pf_hash_fn(gfn); 7505 7506 while (vcpu->arch.apf.gfns[key] != ~0) 7507 key = kvm_async_pf_next_probe(key); 7508 7509 vcpu->arch.apf.gfns[key] = gfn; 7510 } 7511 7512 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 7513 { 7514 int i; 7515 u32 key = kvm_async_pf_hash_fn(gfn); 7516 7517 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 7518 (vcpu->arch.apf.gfns[key] != gfn && 7519 vcpu->arch.apf.gfns[key] != ~0); i++) 7520 key = kvm_async_pf_next_probe(key); 7521 7522 return key; 7523 } 7524 7525 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7526 { 7527 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 7528 } 7529 7530 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7531 { 7532 u32 i, j, k; 7533 7534 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 7535 while (true) { 7536 vcpu->arch.apf.gfns[i] = ~0; 7537 do { 7538 j = kvm_async_pf_next_probe(j); 7539 if (vcpu->arch.apf.gfns[j] == ~0) 7540 return; 7541 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 7542 /* 7543 * k lies cyclically in ]i,j] 7544 * | i.k.j | 7545 * |....j i.k.| or |.k..j i...| 7546 */ 7547 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 7548 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 7549 i = j; 7550 } 7551 } 7552 7553 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 7554 { 7555 7556 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 7557 sizeof(val)); 7558 } 7559 7560 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 7561 struct kvm_async_pf *work) 7562 { 7563 struct x86_exception fault; 7564 7565 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 7566 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 7567 7568 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 7569 (vcpu->arch.apf.send_user_only && 7570 kvm_x86_ops->get_cpl(vcpu) == 0)) 7571 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 7572 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 7573 fault.vector = PF_VECTOR; 7574 fault.error_code_valid = true; 7575 fault.error_code = 0; 7576 fault.nested_page_fault = false; 7577 fault.address = work->arch.token; 7578 kvm_inject_page_fault(vcpu, &fault); 7579 } 7580 } 7581 7582 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 7583 struct kvm_async_pf *work) 7584 { 7585 struct x86_exception fault; 7586 7587 trace_kvm_async_pf_ready(work->arch.token, work->gva); 7588 if (work->wakeup_all) 7589 work->arch.token = ~0; /* broadcast wakeup */ 7590 else 7591 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 7592 7593 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && 7594 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 7595 fault.vector = PF_VECTOR; 7596 fault.error_code_valid = true; 7597 fault.error_code = 0; 7598 fault.nested_page_fault = false; 7599 fault.address = work->arch.token; 7600 kvm_inject_page_fault(vcpu, &fault); 7601 } 7602 vcpu->arch.apf.halted = false; 7603 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7604 } 7605 7606 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 7607 { 7608 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 7609 return true; 7610 else 7611 return !kvm_event_needs_reinjection(vcpu) && 7612 kvm_x86_ops->interrupt_allowed(vcpu); 7613 } 7614 7615 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 7616 { 7617 atomic_inc(&kvm->arch.noncoherent_dma_count); 7618 } 7619 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 7620 7621 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 7622 { 7623 atomic_dec(&kvm->arch.noncoherent_dma_count); 7624 } 7625 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 7626 7627 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 7628 { 7629 return atomic_read(&kvm->arch.noncoherent_dma_count); 7630 } 7631 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 7632 7633 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 7634 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 7635 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 7636 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 7637 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 7638 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 7639 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 7640 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 7641 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 7642 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 7643 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 7644 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 7645 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 7646