1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 #include "assigned-dev.h" 31 #include "pmu.h" 32 #include "hyperv.h" 33 34 #include <linux/clocksource.h> 35 #include <linux/interrupt.h> 36 #include <linux/kvm.h> 37 #include <linux/fs.h> 38 #include <linux/vmalloc.h> 39 #include <linux/module.h> 40 #include <linux/mman.h> 41 #include <linux/highmem.h> 42 #include <linux/iommu.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/cpufreq.h> 45 #include <linux/user-return-notifier.h> 46 #include <linux/srcu.h> 47 #include <linux/slab.h> 48 #include <linux/perf_event.h> 49 #include <linux/uaccess.h> 50 #include <linux/hash.h> 51 #include <linux/pci.h> 52 #include <linux/timekeeper_internal.h> 53 #include <linux/pvclock_gtod.h> 54 #include <linux/kvm_irqfd.h> 55 #include <linux/irqbypass.h> 56 #include <trace/events/kvm.h> 57 58 #define CREATE_TRACE_POINTS 59 #include "trace.h" 60 61 #include <asm/debugreg.h> 62 #include <asm/msr.h> 63 #include <asm/desc.h> 64 #include <asm/mce.h> 65 #include <linux/kernel_stat.h> 66 #include <asm/fpu/internal.h> /* Ugh! */ 67 #include <asm/pvclock.h> 68 #include <asm/div64.h> 69 #include <asm/irq_remapping.h> 70 71 #define MAX_IO_MSRS 256 72 #define KVM_MAX_MCE_BANKS 32 73 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) 74 75 #define emul_to_vcpu(ctxt) \ 76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 77 78 /* EFER defaults: 79 * - enable syscall per default because its emulated by KVM 80 * - enable LME and LMA per default on 64 bit KVM 81 */ 82 #ifdef CONFIG_X86_64 83 static 84 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 85 #else 86 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 87 #endif 88 89 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 90 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 91 92 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 93 static void process_nmi(struct kvm_vcpu *vcpu); 94 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 95 96 struct kvm_x86_ops *kvm_x86_ops __read_mostly; 97 EXPORT_SYMBOL_GPL(kvm_x86_ops); 98 99 static bool __read_mostly ignore_msrs = 0; 100 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 101 102 unsigned int min_timer_period_us = 500; 103 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 104 105 static bool __read_mostly kvmclock_periodic_sync = true; 106 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 107 108 bool __read_mostly kvm_has_tsc_control; 109 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 110 u32 __read_mostly kvm_max_guest_tsc_khz; 111 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 112 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits; 113 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits); 114 u64 __read_mostly kvm_max_tsc_scaling_ratio; 115 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio); 116 static u64 __read_mostly kvm_default_tsc_scaling_ratio; 117 118 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 119 static u32 __read_mostly tsc_tolerance_ppm = 250; 120 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 121 122 /* lapic timer advance (tscdeadline mode only) in nanoseconds */ 123 unsigned int __read_mostly lapic_timer_advance_ns = 0; 124 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR); 125 126 static bool __read_mostly backwards_tsc_observed = false; 127 128 #define KVM_NR_SHARED_MSRS 16 129 130 struct kvm_shared_msrs_global { 131 int nr; 132 u32 msrs[KVM_NR_SHARED_MSRS]; 133 }; 134 135 struct kvm_shared_msrs { 136 struct user_return_notifier urn; 137 bool registered; 138 struct kvm_shared_msr_values { 139 u64 host; 140 u64 curr; 141 } values[KVM_NR_SHARED_MSRS]; 142 }; 143 144 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 145 static struct kvm_shared_msrs __percpu *shared_msrs; 146 147 struct kvm_stats_debugfs_item debugfs_entries[] = { 148 { "pf_fixed", VCPU_STAT(pf_fixed) }, 149 { "pf_guest", VCPU_STAT(pf_guest) }, 150 { "tlb_flush", VCPU_STAT(tlb_flush) }, 151 { "invlpg", VCPU_STAT(invlpg) }, 152 { "exits", VCPU_STAT(exits) }, 153 { "io_exits", VCPU_STAT(io_exits) }, 154 { "mmio_exits", VCPU_STAT(mmio_exits) }, 155 { "signal_exits", VCPU_STAT(signal_exits) }, 156 { "irq_window", VCPU_STAT(irq_window_exits) }, 157 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 158 { "halt_exits", VCPU_STAT(halt_exits) }, 159 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) }, 160 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) }, 161 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 162 { "hypercalls", VCPU_STAT(hypercalls) }, 163 { "request_irq", VCPU_STAT(request_irq_exits) }, 164 { "irq_exits", VCPU_STAT(irq_exits) }, 165 { "host_state_reload", VCPU_STAT(host_state_reload) }, 166 { "efer_reload", VCPU_STAT(efer_reload) }, 167 { "fpu_reload", VCPU_STAT(fpu_reload) }, 168 { "insn_emulation", VCPU_STAT(insn_emulation) }, 169 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 170 { "irq_injections", VCPU_STAT(irq_injections) }, 171 { "nmi_injections", VCPU_STAT(nmi_injections) }, 172 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 173 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 174 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 175 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 176 { "mmu_flooded", VM_STAT(mmu_flooded) }, 177 { "mmu_recycled", VM_STAT(mmu_recycled) }, 178 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 179 { "mmu_unsync", VM_STAT(mmu_unsync) }, 180 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 181 { "largepages", VM_STAT(lpages) }, 182 { NULL } 183 }; 184 185 u64 __read_mostly host_xcr0; 186 187 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 188 189 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 190 { 191 int i; 192 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 193 vcpu->arch.apf.gfns[i] = ~0; 194 } 195 196 static void kvm_on_user_return(struct user_return_notifier *urn) 197 { 198 unsigned slot; 199 struct kvm_shared_msrs *locals 200 = container_of(urn, struct kvm_shared_msrs, urn); 201 struct kvm_shared_msr_values *values; 202 203 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 204 values = &locals->values[slot]; 205 if (values->host != values->curr) { 206 wrmsrl(shared_msrs_global.msrs[slot], values->host); 207 values->curr = values->host; 208 } 209 } 210 locals->registered = false; 211 user_return_notifier_unregister(urn); 212 } 213 214 static void shared_msr_update(unsigned slot, u32 msr) 215 { 216 u64 value; 217 unsigned int cpu = smp_processor_id(); 218 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 219 220 /* only read, and nobody should modify it at this time, 221 * so don't need lock */ 222 if (slot >= shared_msrs_global.nr) { 223 printk(KERN_ERR "kvm: invalid MSR slot!"); 224 return; 225 } 226 rdmsrl_safe(msr, &value); 227 smsr->values[slot].host = value; 228 smsr->values[slot].curr = value; 229 } 230 231 void kvm_define_shared_msr(unsigned slot, u32 msr) 232 { 233 BUG_ON(slot >= KVM_NR_SHARED_MSRS); 234 shared_msrs_global.msrs[slot] = msr; 235 if (slot >= shared_msrs_global.nr) 236 shared_msrs_global.nr = slot + 1; 237 } 238 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 239 240 static void kvm_shared_msr_cpu_online(void) 241 { 242 unsigned i; 243 244 for (i = 0; i < shared_msrs_global.nr; ++i) 245 shared_msr_update(i, shared_msrs_global.msrs[i]); 246 } 247 248 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 249 { 250 unsigned int cpu = smp_processor_id(); 251 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 252 int err; 253 254 if (((value ^ smsr->values[slot].curr) & mask) == 0) 255 return 0; 256 smsr->values[slot].curr = value; 257 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); 258 if (err) 259 return 1; 260 261 if (!smsr->registered) { 262 smsr->urn.on_user_return = kvm_on_user_return; 263 user_return_notifier_register(&smsr->urn); 264 smsr->registered = true; 265 } 266 return 0; 267 } 268 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 269 270 static void drop_user_return_notifiers(void) 271 { 272 unsigned int cpu = smp_processor_id(); 273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 274 275 if (smsr->registered) 276 kvm_on_user_return(&smsr->urn); 277 } 278 279 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 280 { 281 return vcpu->arch.apic_base; 282 } 283 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 284 285 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 286 { 287 u64 old_state = vcpu->arch.apic_base & 288 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 289 u64 new_state = msr_info->data & 290 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 291 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 292 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); 293 294 if (!msr_info->host_initiated && 295 ((msr_info->data & reserved_bits) != 0 || 296 new_state == X2APIC_ENABLE || 297 (new_state == MSR_IA32_APICBASE_ENABLE && 298 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 299 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 300 old_state == 0))) 301 return 1; 302 303 kvm_lapic_set_base(vcpu, msr_info->data); 304 return 0; 305 } 306 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 307 308 asmlinkage __visible void kvm_spurious_fault(void) 309 { 310 /* Fault while not rebooting. We want the trace. */ 311 BUG(); 312 } 313 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 314 315 #define EXCPT_BENIGN 0 316 #define EXCPT_CONTRIBUTORY 1 317 #define EXCPT_PF 2 318 319 static int exception_class(int vector) 320 { 321 switch (vector) { 322 case PF_VECTOR: 323 return EXCPT_PF; 324 case DE_VECTOR: 325 case TS_VECTOR: 326 case NP_VECTOR: 327 case SS_VECTOR: 328 case GP_VECTOR: 329 return EXCPT_CONTRIBUTORY; 330 default: 331 break; 332 } 333 return EXCPT_BENIGN; 334 } 335 336 #define EXCPT_FAULT 0 337 #define EXCPT_TRAP 1 338 #define EXCPT_ABORT 2 339 #define EXCPT_INTERRUPT 3 340 341 static int exception_type(int vector) 342 { 343 unsigned int mask; 344 345 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 346 return EXCPT_INTERRUPT; 347 348 mask = 1 << vector; 349 350 /* #DB is trap, as instruction watchpoints are handled elsewhere */ 351 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) 352 return EXCPT_TRAP; 353 354 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 355 return EXCPT_ABORT; 356 357 /* Reserved exceptions will result in fault */ 358 return EXCPT_FAULT; 359 } 360 361 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 362 unsigned nr, bool has_error, u32 error_code, 363 bool reinject) 364 { 365 u32 prev_nr; 366 int class1, class2; 367 368 kvm_make_request(KVM_REQ_EVENT, vcpu); 369 370 if (!vcpu->arch.exception.pending) { 371 queue: 372 if (has_error && !is_protmode(vcpu)) 373 has_error = false; 374 vcpu->arch.exception.pending = true; 375 vcpu->arch.exception.has_error_code = has_error; 376 vcpu->arch.exception.nr = nr; 377 vcpu->arch.exception.error_code = error_code; 378 vcpu->arch.exception.reinject = reinject; 379 return; 380 } 381 382 /* to check exception */ 383 prev_nr = vcpu->arch.exception.nr; 384 if (prev_nr == DF_VECTOR) { 385 /* triple fault -> shutdown */ 386 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 387 return; 388 } 389 class1 = exception_class(prev_nr); 390 class2 = exception_class(nr); 391 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 392 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 393 /* generate double fault per SDM Table 5-5 */ 394 vcpu->arch.exception.pending = true; 395 vcpu->arch.exception.has_error_code = true; 396 vcpu->arch.exception.nr = DF_VECTOR; 397 vcpu->arch.exception.error_code = 0; 398 } else 399 /* replace previous exception with a new one in a hope 400 that instruction re-execution will regenerate lost 401 exception */ 402 goto queue; 403 } 404 405 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 406 { 407 kvm_multiple_exception(vcpu, nr, false, 0, false); 408 } 409 EXPORT_SYMBOL_GPL(kvm_queue_exception); 410 411 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 412 { 413 kvm_multiple_exception(vcpu, nr, false, 0, true); 414 } 415 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 416 417 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 418 { 419 if (err) 420 kvm_inject_gp(vcpu, 0); 421 else 422 kvm_x86_ops->skip_emulated_instruction(vcpu); 423 } 424 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 425 426 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 427 { 428 ++vcpu->stat.pf_guest; 429 vcpu->arch.cr2 = fault->address; 430 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 431 } 432 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 433 434 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 435 { 436 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 437 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 438 else 439 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 440 441 return fault->nested_page_fault; 442 } 443 444 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 445 { 446 atomic_inc(&vcpu->arch.nmi_queued); 447 kvm_make_request(KVM_REQ_NMI, vcpu); 448 } 449 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 450 451 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 452 { 453 kvm_multiple_exception(vcpu, nr, true, error_code, false); 454 } 455 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 456 457 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 458 { 459 kvm_multiple_exception(vcpu, nr, true, error_code, true); 460 } 461 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 462 463 /* 464 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 465 * a #GP and return false. 466 */ 467 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 468 { 469 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 470 return true; 471 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 472 return false; 473 } 474 EXPORT_SYMBOL_GPL(kvm_require_cpl); 475 476 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 477 { 478 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 479 return true; 480 481 kvm_queue_exception(vcpu, UD_VECTOR); 482 return false; 483 } 484 EXPORT_SYMBOL_GPL(kvm_require_dr); 485 486 /* 487 * This function will be used to read from the physical memory of the currently 488 * running guest. The difference to kvm_vcpu_read_guest_page is that this function 489 * can read from guest physical or from the guest's guest physical memory. 490 */ 491 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 492 gfn_t ngfn, void *data, int offset, int len, 493 u32 access) 494 { 495 struct x86_exception exception; 496 gfn_t real_gfn; 497 gpa_t ngpa; 498 499 ngpa = gfn_to_gpa(ngfn); 500 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception); 501 if (real_gfn == UNMAPPED_GVA) 502 return -EFAULT; 503 504 real_gfn = gpa_to_gfn(real_gfn); 505 506 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len); 507 } 508 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 509 510 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 511 void *data, int offset, int len, u32 access) 512 { 513 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 514 data, offset, len, access); 515 } 516 517 /* 518 * Load the pae pdptrs. Return true is they are all valid. 519 */ 520 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 521 { 522 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 523 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 524 int i; 525 int ret; 526 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 527 528 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 529 offset * sizeof(u64), sizeof(pdpte), 530 PFERR_USER_MASK|PFERR_WRITE_MASK); 531 if (ret < 0) { 532 ret = 0; 533 goto out; 534 } 535 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 536 if (is_present_gpte(pdpte[i]) && 537 (pdpte[i] & 538 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) { 539 ret = 0; 540 goto out; 541 } 542 } 543 ret = 1; 544 545 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 546 __set_bit(VCPU_EXREG_PDPTR, 547 (unsigned long *)&vcpu->arch.regs_avail); 548 __set_bit(VCPU_EXREG_PDPTR, 549 (unsigned long *)&vcpu->arch.regs_dirty); 550 out: 551 552 return ret; 553 } 554 EXPORT_SYMBOL_GPL(load_pdptrs); 555 556 static bool pdptrs_changed(struct kvm_vcpu *vcpu) 557 { 558 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 559 bool changed = true; 560 int offset; 561 gfn_t gfn; 562 int r; 563 564 if (is_long_mode(vcpu) || !is_pae(vcpu)) 565 return false; 566 567 if (!test_bit(VCPU_EXREG_PDPTR, 568 (unsigned long *)&vcpu->arch.regs_avail)) 569 return true; 570 571 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; 572 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); 573 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 574 PFERR_USER_MASK | PFERR_WRITE_MASK); 575 if (r < 0) 576 goto out; 577 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 578 out: 579 580 return changed; 581 } 582 583 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 584 { 585 unsigned long old_cr0 = kvm_read_cr0(vcpu); 586 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP; 587 588 cr0 |= X86_CR0_ET; 589 590 #ifdef CONFIG_X86_64 591 if (cr0 & 0xffffffff00000000UL) 592 return 1; 593 #endif 594 595 cr0 &= ~CR0_RESERVED_BITS; 596 597 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 598 return 1; 599 600 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 601 return 1; 602 603 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 604 #ifdef CONFIG_X86_64 605 if ((vcpu->arch.efer & EFER_LME)) { 606 int cs_db, cs_l; 607 608 if (!is_pae(vcpu)) 609 return 1; 610 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 611 if (cs_l) 612 return 1; 613 } else 614 #endif 615 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 616 kvm_read_cr3(vcpu))) 617 return 1; 618 } 619 620 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 621 return 1; 622 623 kvm_x86_ops->set_cr0(vcpu, cr0); 624 625 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 626 kvm_clear_async_pf_completion_queue(vcpu); 627 kvm_async_pf_hash_reset(vcpu); 628 } 629 630 if ((cr0 ^ old_cr0) & update_bits) 631 kvm_mmu_reset_context(vcpu); 632 633 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 634 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 635 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 636 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 637 638 return 0; 639 } 640 EXPORT_SYMBOL_GPL(kvm_set_cr0); 641 642 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 643 { 644 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 645 } 646 EXPORT_SYMBOL_GPL(kvm_lmsw); 647 648 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 649 { 650 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 651 !vcpu->guest_xcr0_loaded) { 652 /* kvm_set_xcr() also depends on this */ 653 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 654 vcpu->guest_xcr0_loaded = 1; 655 } 656 } 657 658 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 659 { 660 if (vcpu->guest_xcr0_loaded) { 661 if (vcpu->arch.xcr0 != host_xcr0) 662 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 663 vcpu->guest_xcr0_loaded = 0; 664 } 665 } 666 667 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 668 { 669 u64 xcr0 = xcr; 670 u64 old_xcr0 = vcpu->arch.xcr0; 671 u64 valid_bits; 672 673 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 674 if (index != XCR_XFEATURE_ENABLED_MASK) 675 return 1; 676 if (!(xcr0 & XFEATURE_MASK_FP)) 677 return 1; 678 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 679 return 1; 680 681 /* 682 * Do not allow the guest to set bits that we do not support 683 * saving. However, xcr0 bit 0 is always set, even if the 684 * emulated CPU does not support XSAVE (see fx_init). 685 */ 686 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 687 if (xcr0 & ~valid_bits) 688 return 1; 689 690 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 691 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 692 return 1; 693 694 if (xcr0 & XFEATURE_MASK_AVX512) { 695 if (!(xcr0 & XFEATURE_MASK_YMM)) 696 return 1; 697 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 698 return 1; 699 } 700 kvm_put_guest_xcr0(vcpu); 701 vcpu->arch.xcr0 = xcr0; 702 703 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 704 kvm_update_cpuid(vcpu); 705 return 0; 706 } 707 708 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 709 { 710 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 711 __kvm_set_xcr(vcpu, index, xcr)) { 712 kvm_inject_gp(vcpu, 0); 713 return 1; 714 } 715 return 0; 716 } 717 EXPORT_SYMBOL_GPL(kvm_set_xcr); 718 719 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 720 { 721 unsigned long old_cr4 = kvm_read_cr4(vcpu); 722 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | 723 X86_CR4_SMEP | X86_CR4_SMAP; 724 725 if (cr4 & CR4_RESERVED_BITS) 726 return 1; 727 728 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) 729 return 1; 730 731 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) 732 return 1; 733 734 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) 735 return 1; 736 737 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) 738 return 1; 739 740 if (is_long_mode(vcpu)) { 741 if (!(cr4 & X86_CR4_PAE)) 742 return 1; 743 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 744 && ((cr4 ^ old_cr4) & pdptr_bits) 745 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 746 kvm_read_cr3(vcpu))) 747 return 1; 748 749 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 750 if (!guest_cpuid_has_pcid(vcpu)) 751 return 1; 752 753 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 754 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 755 return 1; 756 } 757 758 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 759 return 1; 760 761 if (((cr4 ^ old_cr4) & pdptr_bits) || 762 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 763 kvm_mmu_reset_context(vcpu); 764 765 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) 766 kvm_update_cpuid(vcpu); 767 768 return 0; 769 } 770 EXPORT_SYMBOL_GPL(kvm_set_cr4); 771 772 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 773 { 774 #ifdef CONFIG_X86_64 775 cr3 &= ~CR3_PCID_INVD; 776 #endif 777 778 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 779 kvm_mmu_sync_roots(vcpu); 780 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 781 return 0; 782 } 783 784 if (is_long_mode(vcpu)) { 785 if (cr3 & CR3_L_MODE_RESERVED_BITS) 786 return 1; 787 } else if (is_pae(vcpu) && is_paging(vcpu) && 788 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 789 return 1; 790 791 vcpu->arch.cr3 = cr3; 792 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 793 kvm_mmu_new_cr3(vcpu); 794 return 0; 795 } 796 EXPORT_SYMBOL_GPL(kvm_set_cr3); 797 798 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 799 { 800 if (cr8 & CR8_RESERVED_BITS) 801 return 1; 802 if (lapic_in_kernel(vcpu)) 803 kvm_lapic_set_tpr(vcpu, cr8); 804 else 805 vcpu->arch.cr8 = cr8; 806 return 0; 807 } 808 EXPORT_SYMBOL_GPL(kvm_set_cr8); 809 810 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 811 { 812 if (lapic_in_kernel(vcpu)) 813 return kvm_lapic_get_cr8(vcpu); 814 else 815 return vcpu->arch.cr8; 816 } 817 EXPORT_SYMBOL_GPL(kvm_get_cr8); 818 819 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 820 { 821 int i; 822 823 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 824 for (i = 0; i < KVM_NR_DB_REGS; i++) 825 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 826 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 827 } 828 } 829 830 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 831 { 832 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 833 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 834 } 835 836 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 837 { 838 unsigned long dr7; 839 840 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 841 dr7 = vcpu->arch.guest_debug_dr7; 842 else 843 dr7 = vcpu->arch.dr7; 844 kvm_x86_ops->set_dr7(vcpu, dr7); 845 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 846 if (dr7 & DR7_BP_EN_MASK) 847 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 848 } 849 850 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 851 { 852 u64 fixed = DR6_FIXED_1; 853 854 if (!guest_cpuid_has_rtm(vcpu)) 855 fixed |= DR6_RTM; 856 return fixed; 857 } 858 859 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 860 { 861 switch (dr) { 862 case 0 ... 3: 863 vcpu->arch.db[dr] = val; 864 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 865 vcpu->arch.eff_db[dr] = val; 866 break; 867 case 4: 868 /* fall through */ 869 case 6: 870 if (val & 0xffffffff00000000ULL) 871 return -1; /* #GP */ 872 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 873 kvm_update_dr6(vcpu); 874 break; 875 case 5: 876 /* fall through */ 877 default: /* 7 */ 878 if (val & 0xffffffff00000000ULL) 879 return -1; /* #GP */ 880 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 881 kvm_update_dr7(vcpu); 882 break; 883 } 884 885 return 0; 886 } 887 888 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 889 { 890 if (__kvm_set_dr(vcpu, dr, val)) { 891 kvm_inject_gp(vcpu, 0); 892 return 1; 893 } 894 return 0; 895 } 896 EXPORT_SYMBOL_GPL(kvm_set_dr); 897 898 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 899 { 900 switch (dr) { 901 case 0 ... 3: 902 *val = vcpu->arch.db[dr]; 903 break; 904 case 4: 905 /* fall through */ 906 case 6: 907 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 908 *val = vcpu->arch.dr6; 909 else 910 *val = kvm_x86_ops->get_dr6(vcpu); 911 break; 912 case 5: 913 /* fall through */ 914 default: /* 7 */ 915 *val = vcpu->arch.dr7; 916 break; 917 } 918 return 0; 919 } 920 EXPORT_SYMBOL_GPL(kvm_get_dr); 921 922 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 923 { 924 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 925 u64 data; 926 int err; 927 928 err = kvm_pmu_rdpmc(vcpu, ecx, &data); 929 if (err) 930 return err; 931 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 932 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 933 return err; 934 } 935 EXPORT_SYMBOL_GPL(kvm_rdpmc); 936 937 /* 938 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 939 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 940 * 941 * This list is modified at module load time to reflect the 942 * capabilities of the host cpu. This capabilities test skips MSRs that are 943 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs 944 * may depend on host virtualization features rather than host cpu features. 945 */ 946 947 static u32 msrs_to_save[] = { 948 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 949 MSR_STAR, 950 #ifdef CONFIG_X86_64 951 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 952 #endif 953 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 954 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 955 }; 956 957 static unsigned num_msrs_to_save; 958 959 static u32 emulated_msrs[] = { 960 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 961 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 962 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 963 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 964 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 965 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 966 HV_X64_MSR_RESET, 967 HV_X64_MSR_VP_INDEX, 968 HV_X64_MSR_VP_RUNTIME, 969 HV_X64_MSR_SCONTROL, 970 HV_X64_MSR_STIMER0_CONFIG, 971 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 972 MSR_KVM_PV_EOI_EN, 973 974 MSR_IA32_TSC_ADJUST, 975 MSR_IA32_TSCDEADLINE, 976 MSR_IA32_MISC_ENABLE, 977 MSR_IA32_MCG_STATUS, 978 MSR_IA32_MCG_CTL, 979 MSR_IA32_SMBASE, 980 }; 981 982 static unsigned num_emulated_msrs; 983 984 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 985 { 986 if (efer & efer_reserved_bits) 987 return false; 988 989 if (efer & EFER_FFXSR) { 990 struct kvm_cpuid_entry2 *feat; 991 992 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 993 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) 994 return false; 995 } 996 997 if (efer & EFER_SVME) { 998 struct kvm_cpuid_entry2 *feat; 999 1000 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 1001 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) 1002 return false; 1003 } 1004 1005 return true; 1006 } 1007 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1008 1009 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 1010 { 1011 u64 old_efer = vcpu->arch.efer; 1012 1013 if (!kvm_valid_efer(vcpu, efer)) 1014 return 1; 1015 1016 if (is_paging(vcpu) 1017 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1018 return 1; 1019 1020 efer &= ~EFER_LMA; 1021 efer |= vcpu->arch.efer & EFER_LMA; 1022 1023 kvm_x86_ops->set_efer(vcpu, efer); 1024 1025 /* Update reserved bits */ 1026 if ((efer ^ old_efer) & EFER_NX) 1027 kvm_mmu_reset_context(vcpu); 1028 1029 return 0; 1030 } 1031 1032 void kvm_enable_efer_bits(u64 mask) 1033 { 1034 efer_reserved_bits &= ~mask; 1035 } 1036 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1037 1038 /* 1039 * Writes msr value into into the appropriate "register". 1040 * Returns 0 on success, non-0 otherwise. 1041 * Assumes vcpu_load() was already called. 1042 */ 1043 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1044 { 1045 switch (msr->index) { 1046 case MSR_FS_BASE: 1047 case MSR_GS_BASE: 1048 case MSR_KERNEL_GS_BASE: 1049 case MSR_CSTAR: 1050 case MSR_LSTAR: 1051 if (is_noncanonical_address(msr->data)) 1052 return 1; 1053 break; 1054 case MSR_IA32_SYSENTER_EIP: 1055 case MSR_IA32_SYSENTER_ESP: 1056 /* 1057 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1058 * non-canonical address is written on Intel but not on 1059 * AMD (which ignores the top 32-bits, because it does 1060 * not implement 64-bit SYSENTER). 1061 * 1062 * 64-bit code should hence be able to write a non-canonical 1063 * value on AMD. Making the address canonical ensures that 1064 * vmentry does not fail on Intel after writing a non-canonical 1065 * value, and that something deterministic happens if the guest 1066 * invokes 64-bit SYSENTER. 1067 */ 1068 msr->data = get_canonical(msr->data); 1069 } 1070 return kvm_x86_ops->set_msr(vcpu, msr); 1071 } 1072 EXPORT_SYMBOL_GPL(kvm_set_msr); 1073 1074 /* 1075 * Adapt set_msr() to msr_io()'s calling convention 1076 */ 1077 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1078 { 1079 struct msr_data msr; 1080 int r; 1081 1082 msr.index = index; 1083 msr.host_initiated = true; 1084 r = kvm_get_msr(vcpu, &msr); 1085 if (r) 1086 return r; 1087 1088 *data = msr.data; 1089 return 0; 1090 } 1091 1092 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1093 { 1094 struct msr_data msr; 1095 1096 msr.data = *data; 1097 msr.index = index; 1098 msr.host_initiated = true; 1099 return kvm_set_msr(vcpu, &msr); 1100 } 1101 1102 #ifdef CONFIG_X86_64 1103 struct pvclock_gtod_data { 1104 seqcount_t seq; 1105 1106 struct { /* extract of a clocksource struct */ 1107 int vclock_mode; 1108 cycle_t cycle_last; 1109 cycle_t mask; 1110 u32 mult; 1111 u32 shift; 1112 } clock; 1113 1114 u64 boot_ns; 1115 u64 nsec_base; 1116 }; 1117 1118 static struct pvclock_gtod_data pvclock_gtod_data; 1119 1120 static void update_pvclock_gtod(struct timekeeper *tk) 1121 { 1122 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 1123 u64 boot_ns; 1124 1125 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot)); 1126 1127 write_seqcount_begin(&vdata->seq); 1128 1129 /* copy pvclock gtod data */ 1130 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode; 1131 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 1132 vdata->clock.mask = tk->tkr_mono.mask; 1133 vdata->clock.mult = tk->tkr_mono.mult; 1134 vdata->clock.shift = tk->tkr_mono.shift; 1135 1136 vdata->boot_ns = boot_ns; 1137 vdata->nsec_base = tk->tkr_mono.xtime_nsec; 1138 1139 write_seqcount_end(&vdata->seq); 1140 } 1141 #endif 1142 1143 void kvm_set_pending_timer(struct kvm_vcpu *vcpu) 1144 { 1145 /* 1146 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1147 * vcpu_enter_guest. This function is only called from 1148 * the physical CPU that is running vcpu. 1149 */ 1150 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1151 } 1152 1153 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1154 { 1155 int version; 1156 int r; 1157 struct pvclock_wall_clock wc; 1158 struct timespec boot; 1159 1160 if (!wall_clock) 1161 return; 1162 1163 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1164 if (r) 1165 return; 1166 1167 if (version & 1) 1168 ++version; /* first time write, random junk */ 1169 1170 ++version; 1171 1172 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 1173 return; 1174 1175 /* 1176 * The guest calculates current wall clock time by adding 1177 * system time (updated by kvm_guest_time_update below) to the 1178 * wall clock specified here. guest system time equals host 1179 * system time for us, thus we must fill in host boot time here. 1180 */ 1181 getboottime(&boot); 1182 1183 if (kvm->arch.kvmclock_offset) { 1184 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); 1185 boot = timespec_sub(boot, ts); 1186 } 1187 wc.sec = boot.tv_sec; 1188 wc.nsec = boot.tv_nsec; 1189 wc.version = version; 1190 1191 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1192 1193 version++; 1194 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1195 } 1196 1197 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1198 { 1199 uint32_t quotient, remainder; 1200 1201 /* Don't try to replace with do_div(), this one calculates 1202 * "(dividend << 32) / divisor" */ 1203 __asm__ ( "divl %4" 1204 : "=a" (quotient), "=d" (remainder) 1205 : "0" (0), "1" (dividend), "r" (divisor) ); 1206 return quotient; 1207 } 1208 1209 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, 1210 s8 *pshift, u32 *pmultiplier) 1211 { 1212 uint64_t scaled64; 1213 int32_t shift = 0; 1214 uint64_t tps64; 1215 uint32_t tps32; 1216 1217 tps64 = base_khz * 1000LL; 1218 scaled64 = scaled_khz * 1000LL; 1219 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1220 tps64 >>= 1; 1221 shift--; 1222 } 1223 1224 tps32 = (uint32_t)tps64; 1225 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1226 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1227 scaled64 >>= 1; 1228 else 1229 tps32 <<= 1; 1230 shift++; 1231 } 1232 1233 *pshift = shift; 1234 *pmultiplier = div_frac(scaled64, tps32); 1235 1236 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", 1237 __func__, base_khz, scaled_khz, shift, *pmultiplier); 1238 } 1239 1240 #ifdef CONFIG_X86_64 1241 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1242 #endif 1243 1244 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1245 static unsigned long max_tsc_khz; 1246 1247 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) 1248 { 1249 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, 1250 vcpu->arch.virtual_tsc_shift); 1251 } 1252 1253 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1254 { 1255 u64 v = (u64)khz * (1000000 + ppm); 1256 do_div(v, 1000000); 1257 return v; 1258 } 1259 1260 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 1261 { 1262 u64 ratio; 1263 1264 /* Guest TSC same frequency as host TSC? */ 1265 if (!scale) { 1266 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1267 return 0; 1268 } 1269 1270 /* TSC scaling supported? */ 1271 if (!kvm_has_tsc_control) { 1272 if (user_tsc_khz > tsc_khz) { 1273 vcpu->arch.tsc_catchup = 1; 1274 vcpu->arch.tsc_always_catchup = 1; 1275 return 0; 1276 } else { 1277 WARN(1, "user requested TSC rate below hardware speed\n"); 1278 return -1; 1279 } 1280 } 1281 1282 /* TSC scaling required - calculate ratio */ 1283 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits, 1284 user_tsc_khz, tsc_khz); 1285 1286 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) { 1287 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 1288 user_tsc_khz); 1289 return -1; 1290 } 1291 1292 vcpu->arch.tsc_scaling_ratio = ratio; 1293 return 0; 1294 } 1295 1296 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) 1297 { 1298 u32 thresh_lo, thresh_hi; 1299 int use_scaling = 0; 1300 1301 /* tsc_khz can be zero if TSC calibration fails */ 1302 if (this_tsc_khz == 0) { 1303 /* set tsc_scaling_ratio to a safe value */ 1304 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio; 1305 return -1; 1306 } 1307 1308 /* Compute a scale to convert nanoseconds in TSC cycles */ 1309 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, 1310 &vcpu->arch.virtual_tsc_shift, 1311 &vcpu->arch.virtual_tsc_mult); 1312 vcpu->arch.virtual_tsc_khz = this_tsc_khz; 1313 1314 /* 1315 * Compute the variation in TSC rate which is acceptable 1316 * within the range of tolerance and decide if the 1317 * rate being applied is within that bounds of the hardware 1318 * rate. If so, no scaling or compensation need be done. 1319 */ 1320 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1321 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1322 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { 1323 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); 1324 use_scaling = 1; 1325 } 1326 return set_tsc_khz(vcpu, this_tsc_khz, use_scaling); 1327 } 1328 1329 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1330 { 1331 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1332 vcpu->arch.virtual_tsc_mult, 1333 vcpu->arch.virtual_tsc_shift); 1334 tsc += vcpu->arch.this_tsc_write; 1335 return tsc; 1336 } 1337 1338 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1339 { 1340 #ifdef CONFIG_X86_64 1341 bool vcpus_matched; 1342 struct kvm_arch *ka = &vcpu->kvm->arch; 1343 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1344 1345 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1346 atomic_read(&vcpu->kvm->online_vcpus)); 1347 1348 /* 1349 * Once the masterclock is enabled, always perform request in 1350 * order to update it. 1351 * 1352 * In order to enable masterclock, the host clocksource must be TSC 1353 * and the vcpus need to have matched TSCs. When that happens, 1354 * perform request to enable masterclock. 1355 */ 1356 if (ka->use_master_clock || 1357 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched)) 1358 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1359 1360 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1361 atomic_read(&vcpu->kvm->online_vcpus), 1362 ka->use_master_clock, gtod->clock.vclock_mode); 1363 #endif 1364 } 1365 1366 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1367 { 1368 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); 1369 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1370 } 1371 1372 /* 1373 * Multiply tsc by a fixed point number represented by ratio. 1374 * 1375 * The most significant 64-N bits (mult) of ratio represent the 1376 * integral part of the fixed point number; the remaining N bits 1377 * (frac) represent the fractional part, ie. ratio represents a fixed 1378 * point number (mult + frac * 2^(-N)). 1379 * 1380 * N equals to kvm_tsc_scaling_ratio_frac_bits. 1381 */ 1382 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 1383 { 1384 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits); 1385 } 1386 1387 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc) 1388 { 1389 u64 _tsc = tsc; 1390 u64 ratio = vcpu->arch.tsc_scaling_ratio; 1391 1392 if (ratio != kvm_default_tsc_scaling_ratio) 1393 _tsc = __scale_tsc(ratio, tsc); 1394 1395 return _tsc; 1396 } 1397 EXPORT_SYMBOL_GPL(kvm_scale_tsc); 1398 1399 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 1400 { 1401 u64 tsc; 1402 1403 tsc = kvm_scale_tsc(vcpu, rdtsc()); 1404 1405 return target_tsc - tsc; 1406 } 1407 1408 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 1409 { 1410 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc)); 1411 } 1412 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 1413 1414 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1415 { 1416 struct kvm *kvm = vcpu->kvm; 1417 u64 offset, ns, elapsed; 1418 unsigned long flags; 1419 s64 usdiff; 1420 bool matched; 1421 bool already_matched; 1422 u64 data = msr->data; 1423 1424 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1425 offset = kvm_compute_tsc_offset(vcpu, data); 1426 ns = get_kernel_ns(); 1427 elapsed = ns - kvm->arch.last_tsc_nsec; 1428 1429 if (vcpu->arch.virtual_tsc_khz) { 1430 int faulted = 0; 1431 1432 /* n.b - signed multiplication and division required */ 1433 usdiff = data - kvm->arch.last_tsc_write; 1434 #ifdef CONFIG_X86_64 1435 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; 1436 #else 1437 /* do_div() only does unsigned */ 1438 asm("1: idivl %[divisor]\n" 1439 "2: xor %%edx, %%edx\n" 1440 " movl $0, %[faulted]\n" 1441 "3:\n" 1442 ".section .fixup,\"ax\"\n" 1443 "4: movl $1, %[faulted]\n" 1444 " jmp 3b\n" 1445 ".previous\n" 1446 1447 _ASM_EXTABLE(1b, 4b) 1448 1449 : "=A"(usdiff), [faulted] "=r" (faulted) 1450 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); 1451 1452 #endif 1453 do_div(elapsed, 1000); 1454 usdiff -= elapsed; 1455 if (usdiff < 0) 1456 usdiff = -usdiff; 1457 1458 /* idivl overflow => difference is larger than USEC_PER_SEC */ 1459 if (faulted) 1460 usdiff = USEC_PER_SEC; 1461 } else 1462 usdiff = USEC_PER_SEC; /* disable TSC match window below */ 1463 1464 /* 1465 * Special case: TSC write with a small delta (1 second) of virtual 1466 * cycle time against real time is interpreted as an attempt to 1467 * synchronize the CPU. 1468 * 1469 * For a reliable TSC, we can match TSC offsets, and for an unstable 1470 * TSC, we add elapsed time in this computation. We could let the 1471 * compensation code attempt to catch up if we fall behind, but 1472 * it's better to try to match offsets from the beginning. 1473 */ 1474 if (usdiff < USEC_PER_SEC && 1475 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1476 if (!check_tsc_unstable()) { 1477 offset = kvm->arch.cur_tsc_offset; 1478 pr_debug("kvm: matched tsc offset for %llu\n", data); 1479 } else { 1480 u64 delta = nsec_to_cycles(vcpu, elapsed); 1481 data += delta; 1482 offset = kvm_compute_tsc_offset(vcpu, data); 1483 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1484 } 1485 matched = true; 1486 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation); 1487 } else { 1488 /* 1489 * We split periods of matched TSC writes into generations. 1490 * For each generation, we track the original measured 1491 * nanosecond time, offset, and write, so if TSCs are in 1492 * sync, we can match exact offset, and if not, we can match 1493 * exact software computation in compute_guest_tsc() 1494 * 1495 * These values are tracked in kvm->arch.cur_xxx variables. 1496 */ 1497 kvm->arch.cur_tsc_generation++; 1498 kvm->arch.cur_tsc_nsec = ns; 1499 kvm->arch.cur_tsc_write = data; 1500 kvm->arch.cur_tsc_offset = offset; 1501 matched = false; 1502 pr_debug("kvm: new tsc generation %llu, clock %llu\n", 1503 kvm->arch.cur_tsc_generation, data); 1504 } 1505 1506 /* 1507 * We also track th most recent recorded KHZ, write and time to 1508 * allow the matching interval to be extended at each write. 1509 */ 1510 kvm->arch.last_tsc_nsec = ns; 1511 kvm->arch.last_tsc_write = data; 1512 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1513 1514 vcpu->arch.last_guest_tsc = data; 1515 1516 /* Keep track of which generation this VCPU has synchronized to */ 1517 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1518 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1519 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1520 1521 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) 1522 update_ia32_tsc_adjust_msr(vcpu, offset); 1523 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1524 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1525 1526 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1527 if (!matched) { 1528 kvm->arch.nr_vcpus_matched_tsc = 0; 1529 } else if (!already_matched) { 1530 kvm->arch.nr_vcpus_matched_tsc++; 1531 } 1532 1533 kvm_track_tsc_matching(vcpu); 1534 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1535 } 1536 1537 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1538 1539 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 1540 s64 adjustment) 1541 { 1542 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment); 1543 } 1544 1545 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 1546 { 1547 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio) 1548 WARN_ON(adjustment < 0); 1549 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment); 1550 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment); 1551 } 1552 1553 #ifdef CONFIG_X86_64 1554 1555 static cycle_t read_tsc(void) 1556 { 1557 cycle_t ret = (cycle_t)rdtsc_ordered(); 1558 u64 last = pvclock_gtod_data.clock.cycle_last; 1559 1560 if (likely(ret >= last)) 1561 return ret; 1562 1563 /* 1564 * GCC likes to generate cmov here, but this branch is extremely 1565 * predictable (it's just a funciton of time and the likely is 1566 * very likely) and there's a data dependence, so force GCC 1567 * to generate a branch instead. I don't barrier() because 1568 * we don't actually need a barrier, and if this function 1569 * ever gets inlined it will generate worse code. 1570 */ 1571 asm volatile (""); 1572 return last; 1573 } 1574 1575 static inline u64 vgettsc(cycle_t *cycle_now) 1576 { 1577 long v; 1578 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1579 1580 *cycle_now = read_tsc(); 1581 1582 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; 1583 return v * gtod->clock.mult; 1584 } 1585 1586 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now) 1587 { 1588 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1589 unsigned long seq; 1590 int mode; 1591 u64 ns; 1592 1593 do { 1594 seq = read_seqcount_begin(>od->seq); 1595 mode = gtod->clock.vclock_mode; 1596 ns = gtod->nsec_base; 1597 ns += vgettsc(cycle_now); 1598 ns >>= gtod->clock.shift; 1599 ns += gtod->boot_ns; 1600 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1601 *t = ns; 1602 1603 return mode; 1604 } 1605 1606 /* returns true if host is using tsc clocksource */ 1607 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) 1608 { 1609 /* checked again under seqlock below */ 1610 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) 1611 return false; 1612 1613 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC; 1614 } 1615 #endif 1616 1617 /* 1618 * 1619 * Assuming a stable TSC across physical CPUS, and a stable TSC 1620 * across virtual CPUs, the following condition is possible. 1621 * Each numbered line represents an event visible to both 1622 * CPUs at the next numbered event. 1623 * 1624 * "timespecX" represents host monotonic time. "tscX" represents 1625 * RDTSC value. 1626 * 1627 * VCPU0 on CPU0 | VCPU1 on CPU1 1628 * 1629 * 1. read timespec0,tsc0 1630 * 2. | timespec1 = timespec0 + N 1631 * | tsc1 = tsc0 + M 1632 * 3. transition to guest | transition to guest 1633 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1634 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1635 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1636 * 1637 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1638 * 1639 * - ret0 < ret1 1640 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1641 * ... 1642 * - 0 < N - M => M < N 1643 * 1644 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1645 * always the case (the difference between two distinct xtime instances 1646 * might be smaller then the difference between corresponding TSC reads, 1647 * when updating guest vcpus pvclock areas). 1648 * 1649 * To avoid that problem, do not allow visibility of distinct 1650 * system_timestamp/tsc_timestamp values simultaneously: use a master 1651 * copy of host monotonic time values. Update that master copy 1652 * in lockstep. 1653 * 1654 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1655 * 1656 */ 1657 1658 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1659 { 1660 #ifdef CONFIG_X86_64 1661 struct kvm_arch *ka = &kvm->arch; 1662 int vclock_mode; 1663 bool host_tsc_clocksource, vcpus_matched; 1664 1665 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1666 atomic_read(&kvm->online_vcpus)); 1667 1668 /* 1669 * If the host uses TSC clock, then passthrough TSC as stable 1670 * to the guest. 1671 */ 1672 host_tsc_clocksource = kvm_get_time_and_clockread( 1673 &ka->master_kernel_ns, 1674 &ka->master_cycle_now); 1675 1676 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 1677 && !backwards_tsc_observed 1678 && !ka->boot_vcpu_runs_old_kvmclock; 1679 1680 if (ka->use_master_clock) 1681 atomic_set(&kvm_guest_has_master_clock, 1); 1682 1683 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1684 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1685 vcpus_matched); 1686 #endif 1687 } 1688 1689 void kvm_make_mclock_inprogress_request(struct kvm *kvm) 1690 { 1691 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 1692 } 1693 1694 static void kvm_gen_update_masterclock(struct kvm *kvm) 1695 { 1696 #ifdef CONFIG_X86_64 1697 int i; 1698 struct kvm_vcpu *vcpu; 1699 struct kvm_arch *ka = &kvm->arch; 1700 1701 spin_lock(&ka->pvclock_gtod_sync_lock); 1702 kvm_make_mclock_inprogress_request(kvm); 1703 /* no guest entries from this point */ 1704 pvclock_update_vm_gtod_copy(kvm); 1705 1706 kvm_for_each_vcpu(i, vcpu, kvm) 1707 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1708 1709 /* guest entries allowed */ 1710 kvm_for_each_vcpu(i, vcpu, kvm) 1711 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); 1712 1713 spin_unlock(&ka->pvclock_gtod_sync_lock); 1714 #endif 1715 } 1716 1717 static int kvm_guest_time_update(struct kvm_vcpu *v) 1718 { 1719 unsigned long flags, this_tsc_khz, tgt_tsc_khz; 1720 struct kvm_vcpu_arch *vcpu = &v->arch; 1721 struct kvm_arch *ka = &v->kvm->arch; 1722 s64 kernel_ns; 1723 u64 tsc_timestamp, host_tsc; 1724 struct pvclock_vcpu_time_info guest_hv_clock; 1725 u8 pvclock_flags; 1726 bool use_master_clock; 1727 1728 kernel_ns = 0; 1729 host_tsc = 0; 1730 1731 /* 1732 * If the host uses TSC clock, then passthrough TSC as stable 1733 * to the guest. 1734 */ 1735 spin_lock(&ka->pvclock_gtod_sync_lock); 1736 use_master_clock = ka->use_master_clock; 1737 if (use_master_clock) { 1738 host_tsc = ka->master_cycle_now; 1739 kernel_ns = ka->master_kernel_ns; 1740 } 1741 spin_unlock(&ka->pvclock_gtod_sync_lock); 1742 1743 /* Keep irq disabled to prevent changes to the clock */ 1744 local_irq_save(flags); 1745 this_tsc_khz = __this_cpu_read(cpu_tsc_khz); 1746 if (unlikely(this_tsc_khz == 0)) { 1747 local_irq_restore(flags); 1748 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1749 return 1; 1750 } 1751 if (!use_master_clock) { 1752 host_tsc = rdtsc(); 1753 kernel_ns = get_kernel_ns(); 1754 } 1755 1756 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 1757 1758 /* 1759 * We may have to catch up the TSC to match elapsed wall clock 1760 * time for two reasons, even if kvmclock is used. 1761 * 1) CPU could have been running below the maximum TSC rate 1762 * 2) Broken TSC compensation resets the base at each VCPU 1763 * entry to avoid unknown leaps of TSC even when running 1764 * again on the same CPU. This may cause apparent elapsed 1765 * time to disappear, and the guest to stand still or run 1766 * very slowly. 1767 */ 1768 if (vcpu->tsc_catchup) { 1769 u64 tsc = compute_guest_tsc(v, kernel_ns); 1770 if (tsc > tsc_timestamp) { 1771 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 1772 tsc_timestamp = tsc; 1773 } 1774 } 1775 1776 local_irq_restore(flags); 1777 1778 if (!vcpu->pv_time_enabled) 1779 return 0; 1780 1781 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { 1782 tgt_tsc_khz = kvm_has_tsc_control ? 1783 vcpu->virtual_tsc_khz : this_tsc_khz; 1784 kvm_get_time_scale(NSEC_PER_SEC / 1000, tgt_tsc_khz, 1785 &vcpu->hv_clock.tsc_shift, 1786 &vcpu->hv_clock.tsc_to_system_mul); 1787 vcpu->hw_tsc_khz = this_tsc_khz; 1788 } 1789 1790 /* With all the info we got, fill in the values */ 1791 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 1792 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 1793 vcpu->last_guest_tsc = tsc_timestamp; 1794 1795 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1796 &guest_hv_clock, sizeof(guest_hv_clock)))) 1797 return 0; 1798 1799 /* This VCPU is paused, but it's legal for a guest to read another 1800 * VCPU's kvmclock, so we really have to follow the specification where 1801 * it says that version is odd if data is being modified, and even after 1802 * it is consistent. 1803 * 1804 * Version field updates must be kept separate. This is because 1805 * kvm_write_guest_cached might use a "rep movs" instruction, and 1806 * writes within a string instruction are weakly ordered. So there 1807 * are three writes overall. 1808 * 1809 * As a small optimization, only write the version field in the first 1810 * and third write. The vcpu->pv_time cache is still valid, because the 1811 * version field is the first in the struct. 1812 */ 1813 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0); 1814 1815 vcpu->hv_clock.version = guest_hv_clock.version + 1; 1816 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1817 &vcpu->hv_clock, 1818 sizeof(vcpu->hv_clock.version)); 1819 1820 smp_wmb(); 1821 1822 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1823 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1824 1825 if (vcpu->pvclock_set_guest_stopped_request) { 1826 pvclock_flags |= PVCLOCK_GUEST_STOPPED; 1827 vcpu->pvclock_set_guest_stopped_request = false; 1828 } 1829 1830 /* If the host uses TSC clocksource, then it is stable */ 1831 if (use_master_clock) 1832 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 1833 1834 vcpu->hv_clock.flags = pvclock_flags; 1835 1836 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 1837 1838 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1839 &vcpu->hv_clock, 1840 sizeof(vcpu->hv_clock)); 1841 1842 smp_wmb(); 1843 1844 vcpu->hv_clock.version++; 1845 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1846 &vcpu->hv_clock, 1847 sizeof(vcpu->hv_clock.version)); 1848 return 0; 1849 } 1850 1851 /* 1852 * kvmclock updates which are isolated to a given vcpu, such as 1853 * vcpu->cpu migration, should not allow system_timestamp from 1854 * the rest of the vcpus to remain static. Otherwise ntp frequency 1855 * correction applies to one vcpu's system_timestamp but not 1856 * the others. 1857 * 1858 * So in those cases, request a kvmclock update for all vcpus. 1859 * We need to rate-limit these requests though, as they can 1860 * considerably slow guests that have a large number of vcpus. 1861 * The time for a remote vcpu to update its kvmclock is bound 1862 * by the delay we use to rate-limit the updates. 1863 */ 1864 1865 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 1866 1867 static void kvmclock_update_fn(struct work_struct *work) 1868 { 1869 int i; 1870 struct delayed_work *dwork = to_delayed_work(work); 1871 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1872 kvmclock_update_work); 1873 struct kvm *kvm = container_of(ka, struct kvm, arch); 1874 struct kvm_vcpu *vcpu; 1875 1876 kvm_for_each_vcpu(i, vcpu, kvm) { 1877 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 1878 kvm_vcpu_kick(vcpu); 1879 } 1880 } 1881 1882 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 1883 { 1884 struct kvm *kvm = v->kvm; 1885 1886 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1887 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 1888 KVMCLOCK_UPDATE_DELAY); 1889 } 1890 1891 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 1892 1893 static void kvmclock_sync_fn(struct work_struct *work) 1894 { 1895 struct delayed_work *dwork = to_delayed_work(work); 1896 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1897 kvmclock_sync_work); 1898 struct kvm *kvm = container_of(ka, struct kvm, arch); 1899 1900 if (!kvmclock_periodic_sync) 1901 return; 1902 1903 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 1904 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 1905 KVMCLOCK_SYNC_PERIOD); 1906 } 1907 1908 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1909 { 1910 u64 mcg_cap = vcpu->arch.mcg_cap; 1911 unsigned bank_num = mcg_cap & 0xff; 1912 1913 switch (msr) { 1914 case MSR_IA32_MCG_STATUS: 1915 vcpu->arch.mcg_status = data; 1916 break; 1917 case MSR_IA32_MCG_CTL: 1918 if (!(mcg_cap & MCG_CTL_P)) 1919 return 1; 1920 if (data != 0 && data != ~(u64)0) 1921 return -1; 1922 vcpu->arch.mcg_ctl = data; 1923 break; 1924 default: 1925 if (msr >= MSR_IA32_MC0_CTL && 1926 msr < MSR_IA32_MCx_CTL(bank_num)) { 1927 u32 offset = msr - MSR_IA32_MC0_CTL; 1928 /* only 0 or all 1s can be written to IA32_MCi_CTL 1929 * some Linux kernels though clear bit 10 in bank 4 to 1930 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 1931 * this to avoid an uncatched #GP in the guest 1932 */ 1933 if ((offset & 0x3) == 0 && 1934 data != 0 && (data | (1 << 10)) != ~(u64)0) 1935 return -1; 1936 vcpu->arch.mce_banks[offset] = data; 1937 break; 1938 } 1939 return 1; 1940 } 1941 return 0; 1942 } 1943 1944 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 1945 { 1946 struct kvm *kvm = vcpu->kvm; 1947 int lm = is_long_mode(vcpu); 1948 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 1949 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 1950 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 1951 : kvm->arch.xen_hvm_config.blob_size_32; 1952 u32 page_num = data & ~PAGE_MASK; 1953 u64 page_addr = data & PAGE_MASK; 1954 u8 *page; 1955 int r; 1956 1957 r = -E2BIG; 1958 if (page_num >= blob_size) 1959 goto out; 1960 r = -ENOMEM; 1961 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 1962 if (IS_ERR(page)) { 1963 r = PTR_ERR(page); 1964 goto out; 1965 } 1966 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) 1967 goto out_free; 1968 r = 0; 1969 out_free: 1970 kfree(page); 1971 out: 1972 return r; 1973 } 1974 1975 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 1976 { 1977 gpa_t gpa = data & ~0x3f; 1978 1979 /* Bits 2:5 are reserved, Should be zero */ 1980 if (data & 0x3c) 1981 return 1; 1982 1983 vcpu->arch.apf.msr_val = data; 1984 1985 if (!(data & KVM_ASYNC_PF_ENABLED)) { 1986 kvm_clear_async_pf_completion_queue(vcpu); 1987 kvm_async_pf_hash_reset(vcpu); 1988 return 0; 1989 } 1990 1991 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 1992 sizeof(u32))) 1993 return 1; 1994 1995 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 1996 kvm_async_pf_wakeup_all(vcpu); 1997 return 0; 1998 } 1999 2000 static void kvmclock_reset(struct kvm_vcpu *vcpu) 2001 { 2002 vcpu->arch.pv_time_enabled = false; 2003 } 2004 2005 static void accumulate_steal_time(struct kvm_vcpu *vcpu) 2006 { 2007 u64 delta; 2008 2009 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2010 return; 2011 2012 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; 2013 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2014 vcpu->arch.st.accum_steal = delta; 2015 } 2016 2017 static void record_steal_time(struct kvm_vcpu *vcpu) 2018 { 2019 accumulate_steal_time(vcpu); 2020 2021 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 2022 return; 2023 2024 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2025 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 2026 return; 2027 2028 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; 2029 vcpu->arch.st.steal.version += 2; 2030 vcpu->arch.st.accum_steal = 0; 2031 2032 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2033 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2034 } 2035 2036 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2037 { 2038 bool pr = false; 2039 u32 msr = msr_info->index; 2040 u64 data = msr_info->data; 2041 2042 switch (msr) { 2043 case MSR_AMD64_NB_CFG: 2044 case MSR_IA32_UCODE_REV: 2045 case MSR_IA32_UCODE_WRITE: 2046 case MSR_VM_HSAVE_PA: 2047 case MSR_AMD64_PATCH_LOADER: 2048 case MSR_AMD64_BU_CFG2: 2049 break; 2050 2051 case MSR_EFER: 2052 return set_efer(vcpu, data); 2053 case MSR_K7_HWCR: 2054 data &= ~(u64)0x40; /* ignore flush filter disable */ 2055 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2056 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2057 data &= ~(u64)0x40000; /* ignore Mc status write enable */ 2058 if (data != 0) { 2059 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2060 data); 2061 return 1; 2062 } 2063 break; 2064 case MSR_FAM10H_MMIO_CONF_BASE: 2065 if (data != 0) { 2066 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2067 "0x%llx\n", data); 2068 return 1; 2069 } 2070 break; 2071 case MSR_IA32_DEBUGCTLMSR: 2072 if (!data) { 2073 /* We support the non-activated case already */ 2074 break; 2075 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2076 /* Values other than LBR and BTF are vendor-specific, 2077 thus reserved and should throw a #GP */ 2078 return 1; 2079 } 2080 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2081 __func__, data); 2082 break; 2083 case 0x200 ... 0x2ff: 2084 return kvm_mtrr_set_msr(vcpu, msr, data); 2085 case MSR_IA32_APICBASE: 2086 return kvm_set_apic_base(vcpu, msr_info); 2087 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2088 return kvm_x2apic_msr_write(vcpu, msr, data); 2089 case MSR_IA32_TSCDEADLINE: 2090 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2091 break; 2092 case MSR_IA32_TSC_ADJUST: 2093 if (guest_cpuid_has_tsc_adjust(vcpu)) { 2094 if (!msr_info->host_initiated) { 2095 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2096 adjust_tsc_offset_guest(vcpu, adj); 2097 } 2098 vcpu->arch.ia32_tsc_adjust_msr = data; 2099 } 2100 break; 2101 case MSR_IA32_MISC_ENABLE: 2102 vcpu->arch.ia32_misc_enable_msr = data; 2103 break; 2104 case MSR_IA32_SMBASE: 2105 if (!msr_info->host_initiated) 2106 return 1; 2107 vcpu->arch.smbase = data; 2108 break; 2109 case MSR_KVM_WALL_CLOCK_NEW: 2110 case MSR_KVM_WALL_CLOCK: 2111 vcpu->kvm->arch.wall_clock = data; 2112 kvm_write_wall_clock(vcpu->kvm, data); 2113 break; 2114 case MSR_KVM_SYSTEM_TIME_NEW: 2115 case MSR_KVM_SYSTEM_TIME: { 2116 u64 gpa_offset; 2117 struct kvm_arch *ka = &vcpu->kvm->arch; 2118 2119 kvmclock_reset(vcpu); 2120 2121 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) { 2122 bool tmp = (msr == MSR_KVM_SYSTEM_TIME); 2123 2124 if (ka->boot_vcpu_runs_old_kvmclock != tmp) 2125 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, 2126 &vcpu->requests); 2127 2128 ka->boot_vcpu_runs_old_kvmclock = tmp; 2129 } 2130 2131 vcpu->arch.time = data; 2132 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2133 2134 /* we verify if the enable bit is set... */ 2135 if (!(data & 1)) 2136 break; 2137 2138 gpa_offset = data & ~(PAGE_MASK | 1); 2139 2140 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2141 &vcpu->arch.pv_time, data & ~1ULL, 2142 sizeof(struct pvclock_vcpu_time_info))) 2143 vcpu->arch.pv_time_enabled = false; 2144 else 2145 vcpu->arch.pv_time_enabled = true; 2146 2147 break; 2148 } 2149 case MSR_KVM_ASYNC_PF_EN: 2150 if (kvm_pv_enable_async_pf(vcpu, data)) 2151 return 1; 2152 break; 2153 case MSR_KVM_STEAL_TIME: 2154 2155 if (unlikely(!sched_info_on())) 2156 return 1; 2157 2158 if (data & KVM_STEAL_RESERVED_MASK) 2159 return 1; 2160 2161 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2162 data & KVM_STEAL_VALID_BITS, 2163 sizeof(struct kvm_steal_time))) 2164 return 1; 2165 2166 vcpu->arch.st.msr_val = data; 2167 2168 if (!(data & KVM_MSR_ENABLED)) 2169 break; 2170 2171 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2172 2173 break; 2174 case MSR_KVM_PV_EOI_EN: 2175 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2176 return 1; 2177 break; 2178 2179 case MSR_IA32_MCG_CTL: 2180 case MSR_IA32_MCG_STATUS: 2181 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2182 return set_msr_mce(vcpu, msr, data); 2183 2184 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2185 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2186 pr = true; /* fall through */ 2187 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2188 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2189 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2190 return kvm_pmu_set_msr(vcpu, msr_info); 2191 2192 if (pr || data != 0) 2193 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2194 "0x%x data 0x%llx\n", msr, data); 2195 break; 2196 case MSR_K7_CLK_CTL: 2197 /* 2198 * Ignore all writes to this no longer documented MSR. 2199 * Writes are only relevant for old K7 processors, 2200 * all pre-dating SVM, but a recommended workaround from 2201 * AMD for these chips. It is possible to specify the 2202 * affected processor models on the command line, hence 2203 * the need to ignore the workaround. 2204 */ 2205 break; 2206 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2207 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2208 case HV_X64_MSR_CRASH_CTL: 2209 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2210 return kvm_hv_set_msr_common(vcpu, msr, data, 2211 msr_info->host_initiated); 2212 case MSR_IA32_BBL_CR_CTL3: 2213 /* Drop writes to this legacy MSR -- see rdmsr 2214 * counterpart for further detail. 2215 */ 2216 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); 2217 break; 2218 case MSR_AMD64_OSVW_ID_LENGTH: 2219 if (!guest_cpuid_has_osvw(vcpu)) 2220 return 1; 2221 vcpu->arch.osvw.length = data; 2222 break; 2223 case MSR_AMD64_OSVW_STATUS: 2224 if (!guest_cpuid_has_osvw(vcpu)) 2225 return 1; 2226 vcpu->arch.osvw.status = data; 2227 break; 2228 default: 2229 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2230 return xen_hvm_config(vcpu, data); 2231 if (kvm_pmu_is_valid_msr(vcpu, msr)) 2232 return kvm_pmu_set_msr(vcpu, msr_info); 2233 if (!ignore_msrs) { 2234 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", 2235 msr, data); 2236 return 1; 2237 } else { 2238 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", 2239 msr, data); 2240 break; 2241 } 2242 } 2243 return 0; 2244 } 2245 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2246 2247 2248 /* 2249 * Reads an msr value (of 'msr_index') into 'pdata'. 2250 * Returns 0 on success, non-0 otherwise. 2251 * Assumes vcpu_load() was already called. 2252 */ 2253 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 2254 { 2255 return kvm_x86_ops->get_msr(vcpu, msr); 2256 } 2257 EXPORT_SYMBOL_GPL(kvm_get_msr); 2258 2259 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2260 { 2261 u64 data; 2262 u64 mcg_cap = vcpu->arch.mcg_cap; 2263 unsigned bank_num = mcg_cap & 0xff; 2264 2265 switch (msr) { 2266 case MSR_IA32_P5_MC_ADDR: 2267 case MSR_IA32_P5_MC_TYPE: 2268 data = 0; 2269 break; 2270 case MSR_IA32_MCG_CAP: 2271 data = vcpu->arch.mcg_cap; 2272 break; 2273 case MSR_IA32_MCG_CTL: 2274 if (!(mcg_cap & MCG_CTL_P)) 2275 return 1; 2276 data = vcpu->arch.mcg_ctl; 2277 break; 2278 case MSR_IA32_MCG_STATUS: 2279 data = vcpu->arch.mcg_status; 2280 break; 2281 default: 2282 if (msr >= MSR_IA32_MC0_CTL && 2283 msr < MSR_IA32_MCx_CTL(bank_num)) { 2284 u32 offset = msr - MSR_IA32_MC0_CTL; 2285 data = vcpu->arch.mce_banks[offset]; 2286 break; 2287 } 2288 return 1; 2289 } 2290 *pdata = data; 2291 return 0; 2292 } 2293 2294 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2295 { 2296 switch (msr_info->index) { 2297 case MSR_IA32_PLATFORM_ID: 2298 case MSR_IA32_EBL_CR_POWERON: 2299 case MSR_IA32_DEBUGCTLMSR: 2300 case MSR_IA32_LASTBRANCHFROMIP: 2301 case MSR_IA32_LASTBRANCHTOIP: 2302 case MSR_IA32_LASTINTFROMIP: 2303 case MSR_IA32_LASTINTTOIP: 2304 case MSR_K8_SYSCFG: 2305 case MSR_K8_TSEG_ADDR: 2306 case MSR_K8_TSEG_MASK: 2307 case MSR_K7_HWCR: 2308 case MSR_VM_HSAVE_PA: 2309 case MSR_K8_INT_PENDING_MSG: 2310 case MSR_AMD64_NB_CFG: 2311 case MSR_FAM10H_MMIO_CONF_BASE: 2312 case MSR_AMD64_BU_CFG2: 2313 msr_info->data = 0; 2314 break; 2315 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 2316 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 2317 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 2318 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 2319 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2320 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2321 msr_info->data = 0; 2322 break; 2323 case MSR_IA32_UCODE_REV: 2324 msr_info->data = 0x100000000ULL; 2325 break; 2326 case MSR_MTRRcap: 2327 case 0x200 ... 0x2ff: 2328 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 2329 case 0xcd: /* fsb frequency */ 2330 msr_info->data = 3; 2331 break; 2332 /* 2333 * MSR_EBC_FREQUENCY_ID 2334 * Conservative value valid for even the basic CPU models. 2335 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2336 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2337 * and 266MHz for model 3, or 4. Set Core Clock 2338 * Frequency to System Bus Frequency Ratio to 1 (bits 2339 * 31:24) even though these are only valid for CPU 2340 * models > 2, however guests may end up dividing or 2341 * multiplying by zero otherwise. 2342 */ 2343 case MSR_EBC_FREQUENCY_ID: 2344 msr_info->data = 1 << 24; 2345 break; 2346 case MSR_IA32_APICBASE: 2347 msr_info->data = kvm_get_apic_base(vcpu); 2348 break; 2349 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2350 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 2351 break; 2352 case MSR_IA32_TSCDEADLINE: 2353 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 2354 break; 2355 case MSR_IA32_TSC_ADJUST: 2356 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2357 break; 2358 case MSR_IA32_MISC_ENABLE: 2359 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 2360 break; 2361 case MSR_IA32_SMBASE: 2362 if (!msr_info->host_initiated) 2363 return 1; 2364 msr_info->data = vcpu->arch.smbase; 2365 break; 2366 case MSR_IA32_PERF_STATUS: 2367 /* TSC increment by tick */ 2368 msr_info->data = 1000ULL; 2369 /* CPU multiplier */ 2370 msr_info->data |= (((uint64_t)4ULL) << 40); 2371 break; 2372 case MSR_EFER: 2373 msr_info->data = vcpu->arch.efer; 2374 break; 2375 case MSR_KVM_WALL_CLOCK: 2376 case MSR_KVM_WALL_CLOCK_NEW: 2377 msr_info->data = vcpu->kvm->arch.wall_clock; 2378 break; 2379 case MSR_KVM_SYSTEM_TIME: 2380 case MSR_KVM_SYSTEM_TIME_NEW: 2381 msr_info->data = vcpu->arch.time; 2382 break; 2383 case MSR_KVM_ASYNC_PF_EN: 2384 msr_info->data = vcpu->arch.apf.msr_val; 2385 break; 2386 case MSR_KVM_STEAL_TIME: 2387 msr_info->data = vcpu->arch.st.msr_val; 2388 break; 2389 case MSR_KVM_PV_EOI_EN: 2390 msr_info->data = vcpu->arch.pv_eoi.msr_val; 2391 break; 2392 case MSR_IA32_P5_MC_ADDR: 2393 case MSR_IA32_P5_MC_TYPE: 2394 case MSR_IA32_MCG_CAP: 2395 case MSR_IA32_MCG_CTL: 2396 case MSR_IA32_MCG_STATUS: 2397 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 2398 return get_msr_mce(vcpu, msr_info->index, &msr_info->data); 2399 case MSR_K7_CLK_CTL: 2400 /* 2401 * Provide expected ramp-up count for K7. All other 2402 * are set to zero, indicating minimum divisors for 2403 * every field. 2404 * 2405 * This prevents guest kernels on AMD host with CPU 2406 * type 6, model 8 and higher from exploding due to 2407 * the rdmsr failing. 2408 */ 2409 msr_info->data = 0x20000000; 2410 break; 2411 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2412 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 2413 case HV_X64_MSR_CRASH_CTL: 2414 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 2415 return kvm_hv_get_msr_common(vcpu, 2416 msr_info->index, &msr_info->data); 2417 break; 2418 case MSR_IA32_BBL_CR_CTL3: 2419 /* This legacy MSR exists but isn't fully documented in current 2420 * silicon. It is however accessed by winxp in very narrow 2421 * scenarios where it sets bit #19, itself documented as 2422 * a "reserved" bit. Best effort attempt to source coherent 2423 * read data here should the balance of the register be 2424 * interpreted by the guest: 2425 * 2426 * L2 cache control register 3: 64GB range, 256KB size, 2427 * enabled, latency 0x1, configured 2428 */ 2429 msr_info->data = 0xbe702111; 2430 break; 2431 case MSR_AMD64_OSVW_ID_LENGTH: 2432 if (!guest_cpuid_has_osvw(vcpu)) 2433 return 1; 2434 msr_info->data = vcpu->arch.osvw.length; 2435 break; 2436 case MSR_AMD64_OSVW_STATUS: 2437 if (!guest_cpuid_has_osvw(vcpu)) 2438 return 1; 2439 msr_info->data = vcpu->arch.osvw.status; 2440 break; 2441 default: 2442 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 2443 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data); 2444 if (!ignore_msrs) { 2445 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index); 2446 return 1; 2447 } else { 2448 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index); 2449 msr_info->data = 0; 2450 } 2451 break; 2452 } 2453 return 0; 2454 } 2455 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2456 2457 /* 2458 * Read or write a bunch of msrs. All parameters are kernel addresses. 2459 * 2460 * @return number of msrs set successfully. 2461 */ 2462 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2463 struct kvm_msr_entry *entries, 2464 int (*do_msr)(struct kvm_vcpu *vcpu, 2465 unsigned index, u64 *data)) 2466 { 2467 int i, idx; 2468 2469 idx = srcu_read_lock(&vcpu->kvm->srcu); 2470 for (i = 0; i < msrs->nmsrs; ++i) 2471 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2472 break; 2473 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2474 2475 return i; 2476 } 2477 2478 /* 2479 * Read or write a bunch of msrs. Parameters are user addresses. 2480 * 2481 * @return number of msrs set successfully. 2482 */ 2483 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2484 int (*do_msr)(struct kvm_vcpu *vcpu, 2485 unsigned index, u64 *data), 2486 int writeback) 2487 { 2488 struct kvm_msrs msrs; 2489 struct kvm_msr_entry *entries; 2490 int r, n; 2491 unsigned size; 2492 2493 r = -EFAULT; 2494 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2495 goto out; 2496 2497 r = -E2BIG; 2498 if (msrs.nmsrs >= MAX_IO_MSRS) 2499 goto out; 2500 2501 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2502 entries = memdup_user(user_msrs->entries, size); 2503 if (IS_ERR(entries)) { 2504 r = PTR_ERR(entries); 2505 goto out; 2506 } 2507 2508 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2509 if (r < 0) 2510 goto out_free; 2511 2512 r = -EFAULT; 2513 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2514 goto out_free; 2515 2516 r = n; 2517 2518 out_free: 2519 kfree(entries); 2520 out: 2521 return r; 2522 } 2523 2524 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 2525 { 2526 int r; 2527 2528 switch (ext) { 2529 case KVM_CAP_IRQCHIP: 2530 case KVM_CAP_HLT: 2531 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2532 case KVM_CAP_SET_TSS_ADDR: 2533 case KVM_CAP_EXT_CPUID: 2534 case KVM_CAP_EXT_EMUL_CPUID: 2535 case KVM_CAP_CLOCKSOURCE: 2536 case KVM_CAP_PIT: 2537 case KVM_CAP_NOP_IO_DELAY: 2538 case KVM_CAP_MP_STATE: 2539 case KVM_CAP_SYNC_MMU: 2540 case KVM_CAP_USER_NMI: 2541 case KVM_CAP_REINJECT_CONTROL: 2542 case KVM_CAP_IRQ_INJECT_STATUS: 2543 case KVM_CAP_IOEVENTFD: 2544 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2545 case KVM_CAP_PIT2: 2546 case KVM_CAP_PIT_STATE2: 2547 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2548 case KVM_CAP_XEN_HVM: 2549 case KVM_CAP_ADJUST_CLOCK: 2550 case KVM_CAP_VCPU_EVENTS: 2551 case KVM_CAP_HYPERV: 2552 case KVM_CAP_HYPERV_VAPIC: 2553 case KVM_CAP_HYPERV_SPIN: 2554 case KVM_CAP_HYPERV_SYNIC: 2555 case KVM_CAP_PCI_SEGMENT: 2556 case KVM_CAP_DEBUGREGS: 2557 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2558 case KVM_CAP_XSAVE: 2559 case KVM_CAP_ASYNC_PF: 2560 case KVM_CAP_GET_TSC_KHZ: 2561 case KVM_CAP_KVMCLOCK_CTRL: 2562 case KVM_CAP_READONLY_MEM: 2563 case KVM_CAP_HYPERV_TIME: 2564 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2565 case KVM_CAP_TSC_DEADLINE_TIMER: 2566 case KVM_CAP_ENABLE_CAP_VM: 2567 case KVM_CAP_DISABLE_QUIRKS: 2568 case KVM_CAP_SET_BOOT_CPU_ID: 2569 case KVM_CAP_SPLIT_IRQCHIP: 2570 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2571 case KVM_CAP_ASSIGN_DEV_IRQ: 2572 case KVM_CAP_PCI_2_3: 2573 #endif 2574 r = 1; 2575 break; 2576 case KVM_CAP_X86_SMM: 2577 /* SMBASE is usually relocated above 1M on modern chipsets, 2578 * and SMM handlers might indeed rely on 4G segment limits, 2579 * so do not report SMM to be available if real mode is 2580 * emulated via vm86 mode. Still, do not go to great lengths 2581 * to avoid userspace's usage of the feature, because it is a 2582 * fringe case that is not enabled except via specific settings 2583 * of the module parameters. 2584 */ 2585 r = kvm_x86_ops->cpu_has_high_real_mode_segbase(); 2586 break; 2587 case KVM_CAP_COALESCED_MMIO: 2588 r = KVM_COALESCED_MMIO_PAGE_OFFSET; 2589 break; 2590 case KVM_CAP_VAPIC: 2591 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2592 break; 2593 case KVM_CAP_NR_VCPUS: 2594 r = KVM_SOFT_MAX_VCPUS; 2595 break; 2596 case KVM_CAP_MAX_VCPUS: 2597 r = KVM_MAX_VCPUS; 2598 break; 2599 case KVM_CAP_NR_MEMSLOTS: 2600 r = KVM_USER_MEM_SLOTS; 2601 break; 2602 case KVM_CAP_PV_MMU: /* obsolete */ 2603 r = 0; 2604 break; 2605 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2606 case KVM_CAP_IOMMU: 2607 r = iommu_present(&pci_bus_type); 2608 break; 2609 #endif 2610 case KVM_CAP_MCE: 2611 r = KVM_MAX_MCE_BANKS; 2612 break; 2613 case KVM_CAP_XCRS: 2614 r = cpu_has_xsave; 2615 break; 2616 case KVM_CAP_TSC_CONTROL: 2617 r = kvm_has_tsc_control; 2618 break; 2619 default: 2620 r = 0; 2621 break; 2622 } 2623 return r; 2624 2625 } 2626 2627 long kvm_arch_dev_ioctl(struct file *filp, 2628 unsigned int ioctl, unsigned long arg) 2629 { 2630 void __user *argp = (void __user *)arg; 2631 long r; 2632 2633 switch (ioctl) { 2634 case KVM_GET_MSR_INDEX_LIST: { 2635 struct kvm_msr_list __user *user_msr_list = argp; 2636 struct kvm_msr_list msr_list; 2637 unsigned n; 2638 2639 r = -EFAULT; 2640 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2641 goto out; 2642 n = msr_list.nmsrs; 2643 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 2644 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2645 goto out; 2646 r = -E2BIG; 2647 if (n < msr_list.nmsrs) 2648 goto out; 2649 r = -EFAULT; 2650 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2651 num_msrs_to_save * sizeof(u32))) 2652 goto out; 2653 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2654 &emulated_msrs, 2655 num_emulated_msrs * sizeof(u32))) 2656 goto out; 2657 r = 0; 2658 break; 2659 } 2660 case KVM_GET_SUPPORTED_CPUID: 2661 case KVM_GET_EMULATED_CPUID: { 2662 struct kvm_cpuid2 __user *cpuid_arg = argp; 2663 struct kvm_cpuid2 cpuid; 2664 2665 r = -EFAULT; 2666 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2667 goto out; 2668 2669 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2670 ioctl); 2671 if (r) 2672 goto out; 2673 2674 r = -EFAULT; 2675 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2676 goto out; 2677 r = 0; 2678 break; 2679 } 2680 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2681 u64 mce_cap; 2682 2683 mce_cap = KVM_MCE_CAP_SUPPORTED; 2684 r = -EFAULT; 2685 if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) 2686 goto out; 2687 r = 0; 2688 break; 2689 } 2690 default: 2691 r = -EINVAL; 2692 } 2693 out: 2694 return r; 2695 } 2696 2697 static void wbinvd_ipi(void *garbage) 2698 { 2699 wbinvd(); 2700 } 2701 2702 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 2703 { 2704 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 2705 } 2706 2707 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu) 2708 { 2709 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests); 2710 } 2711 2712 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 2713 { 2714 /* Address WBINVD may be executed by guest */ 2715 if (need_emulate_wbinvd(vcpu)) { 2716 if (kvm_x86_ops->has_wbinvd_exit()) 2717 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 2718 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 2719 smp_call_function_single(vcpu->cpu, 2720 wbinvd_ipi, NULL, 1); 2721 } 2722 2723 kvm_x86_ops->vcpu_load(vcpu, cpu); 2724 2725 /* Apply any externally detected TSC adjustments (due to suspend) */ 2726 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 2727 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 2728 vcpu->arch.tsc_offset_adjustment = 0; 2729 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 2730 } 2731 2732 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { 2733 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 2734 rdtsc() - vcpu->arch.last_host_tsc; 2735 if (tsc_delta < 0) 2736 mark_tsc_unstable("KVM discovered backwards TSC"); 2737 if (check_tsc_unstable()) { 2738 u64 offset = kvm_compute_tsc_offset(vcpu, 2739 vcpu->arch.last_guest_tsc); 2740 kvm_x86_ops->write_tsc_offset(vcpu, offset); 2741 vcpu->arch.tsc_catchup = 1; 2742 } 2743 /* 2744 * On a host with synchronized TSC, there is no need to update 2745 * kvmclock on vcpu->cpu migration 2746 */ 2747 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 2748 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2749 if (vcpu->cpu != cpu) 2750 kvm_migrate_timers(vcpu); 2751 vcpu->cpu = cpu; 2752 } 2753 2754 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2755 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD; 2756 } 2757 2758 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 2759 { 2760 kvm_x86_ops->vcpu_put(vcpu); 2761 kvm_put_guest_fpu(vcpu); 2762 vcpu->arch.last_host_tsc = rdtsc(); 2763 } 2764 2765 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 2766 struct kvm_lapic_state *s) 2767 { 2768 if (vcpu->arch.apicv_active) 2769 kvm_x86_ops->sync_pir_to_irr(vcpu); 2770 2771 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); 2772 2773 return 0; 2774 } 2775 2776 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 2777 struct kvm_lapic_state *s) 2778 { 2779 kvm_apic_post_state_restore(vcpu, s); 2780 update_cr8_intercept(vcpu); 2781 2782 return 0; 2783 } 2784 2785 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 2786 { 2787 return (!lapic_in_kernel(vcpu) || 2788 kvm_apic_accept_pic_intr(vcpu)); 2789 } 2790 2791 /* 2792 * if userspace requested an interrupt window, check that the 2793 * interrupt window is open. 2794 * 2795 * No need to exit to userspace if we already have an interrupt queued. 2796 */ 2797 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 2798 { 2799 return kvm_arch_interrupt_allowed(vcpu) && 2800 !kvm_cpu_has_interrupt(vcpu) && 2801 !kvm_event_needs_reinjection(vcpu) && 2802 kvm_cpu_accept_dm_intr(vcpu); 2803 } 2804 2805 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 2806 struct kvm_interrupt *irq) 2807 { 2808 if (irq->irq >= KVM_NR_INTERRUPTS) 2809 return -EINVAL; 2810 2811 if (!irqchip_in_kernel(vcpu->kvm)) { 2812 kvm_queue_interrupt(vcpu, irq->irq, false); 2813 kvm_make_request(KVM_REQ_EVENT, vcpu); 2814 return 0; 2815 } 2816 2817 /* 2818 * With in-kernel LAPIC, we only use this to inject EXTINT, so 2819 * fail for in-kernel 8259. 2820 */ 2821 if (pic_in_kernel(vcpu->kvm)) 2822 return -ENXIO; 2823 2824 if (vcpu->arch.pending_external_vector != -1) 2825 return -EEXIST; 2826 2827 vcpu->arch.pending_external_vector = irq->irq; 2828 kvm_make_request(KVM_REQ_EVENT, vcpu); 2829 return 0; 2830 } 2831 2832 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 2833 { 2834 kvm_inject_nmi(vcpu); 2835 2836 return 0; 2837 } 2838 2839 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) 2840 { 2841 kvm_make_request(KVM_REQ_SMI, vcpu); 2842 2843 return 0; 2844 } 2845 2846 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 2847 struct kvm_tpr_access_ctl *tac) 2848 { 2849 if (tac->flags) 2850 return -EINVAL; 2851 vcpu->arch.tpr_access_reporting = !!tac->enabled; 2852 return 0; 2853 } 2854 2855 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 2856 u64 mcg_cap) 2857 { 2858 int r; 2859 unsigned bank_num = mcg_cap & 0xff, bank; 2860 2861 r = -EINVAL; 2862 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 2863 goto out; 2864 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) 2865 goto out; 2866 r = 0; 2867 vcpu->arch.mcg_cap = mcg_cap; 2868 /* Init IA32_MCG_CTL to all 1s */ 2869 if (mcg_cap & MCG_CTL_P) 2870 vcpu->arch.mcg_ctl = ~(u64)0; 2871 /* Init IA32_MCi_CTL to all 1s */ 2872 for (bank = 0; bank < bank_num; bank++) 2873 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 2874 out: 2875 return r; 2876 } 2877 2878 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 2879 struct kvm_x86_mce *mce) 2880 { 2881 u64 mcg_cap = vcpu->arch.mcg_cap; 2882 unsigned bank_num = mcg_cap & 0xff; 2883 u64 *banks = vcpu->arch.mce_banks; 2884 2885 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 2886 return -EINVAL; 2887 /* 2888 * if IA32_MCG_CTL is not all 1s, the uncorrected error 2889 * reporting is disabled 2890 */ 2891 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 2892 vcpu->arch.mcg_ctl != ~(u64)0) 2893 return 0; 2894 banks += 4 * mce->bank; 2895 /* 2896 * if IA32_MCi_CTL is not all 1s, the uncorrected error 2897 * reporting is disabled for the bank 2898 */ 2899 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 2900 return 0; 2901 if (mce->status & MCI_STATUS_UC) { 2902 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 2903 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 2904 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 2905 return 0; 2906 } 2907 if (banks[1] & MCI_STATUS_VAL) 2908 mce->status |= MCI_STATUS_OVER; 2909 banks[2] = mce->addr; 2910 banks[3] = mce->misc; 2911 vcpu->arch.mcg_status = mce->mcg_status; 2912 banks[1] = mce->status; 2913 kvm_queue_exception(vcpu, MC_VECTOR); 2914 } else if (!(banks[1] & MCI_STATUS_VAL) 2915 || !(banks[1] & MCI_STATUS_UC)) { 2916 if (banks[1] & MCI_STATUS_VAL) 2917 mce->status |= MCI_STATUS_OVER; 2918 banks[2] = mce->addr; 2919 banks[3] = mce->misc; 2920 banks[1] = mce->status; 2921 } else 2922 banks[1] |= MCI_STATUS_OVER; 2923 return 0; 2924 } 2925 2926 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 2927 struct kvm_vcpu_events *events) 2928 { 2929 process_nmi(vcpu); 2930 events->exception.injected = 2931 vcpu->arch.exception.pending && 2932 !kvm_exception_is_soft(vcpu->arch.exception.nr); 2933 events->exception.nr = vcpu->arch.exception.nr; 2934 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 2935 events->exception.pad = 0; 2936 events->exception.error_code = vcpu->arch.exception.error_code; 2937 2938 events->interrupt.injected = 2939 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; 2940 events->interrupt.nr = vcpu->arch.interrupt.nr; 2941 events->interrupt.soft = 0; 2942 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 2943 2944 events->nmi.injected = vcpu->arch.nmi_injected; 2945 events->nmi.pending = vcpu->arch.nmi_pending != 0; 2946 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 2947 events->nmi.pad = 0; 2948 2949 events->sipi_vector = 0; /* never valid when reporting to user space */ 2950 2951 events->smi.smm = is_smm(vcpu); 2952 events->smi.pending = vcpu->arch.smi_pending; 2953 events->smi.smm_inside_nmi = 2954 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 2955 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 2956 2957 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 2958 | KVM_VCPUEVENT_VALID_SHADOW 2959 | KVM_VCPUEVENT_VALID_SMM); 2960 memset(&events->reserved, 0, sizeof(events->reserved)); 2961 } 2962 2963 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 2964 struct kvm_vcpu_events *events) 2965 { 2966 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 2967 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 2968 | KVM_VCPUEVENT_VALID_SHADOW 2969 | KVM_VCPUEVENT_VALID_SMM)) 2970 return -EINVAL; 2971 2972 process_nmi(vcpu); 2973 vcpu->arch.exception.pending = events->exception.injected; 2974 vcpu->arch.exception.nr = events->exception.nr; 2975 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 2976 vcpu->arch.exception.error_code = events->exception.error_code; 2977 2978 vcpu->arch.interrupt.pending = events->interrupt.injected; 2979 vcpu->arch.interrupt.nr = events->interrupt.nr; 2980 vcpu->arch.interrupt.soft = events->interrupt.soft; 2981 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 2982 kvm_x86_ops->set_interrupt_shadow(vcpu, 2983 events->interrupt.shadow); 2984 2985 vcpu->arch.nmi_injected = events->nmi.injected; 2986 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 2987 vcpu->arch.nmi_pending = events->nmi.pending; 2988 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 2989 2990 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 2991 kvm_vcpu_has_lapic(vcpu)) 2992 vcpu->arch.apic->sipi_vector = events->sipi_vector; 2993 2994 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 2995 if (events->smi.smm) 2996 vcpu->arch.hflags |= HF_SMM_MASK; 2997 else 2998 vcpu->arch.hflags &= ~HF_SMM_MASK; 2999 vcpu->arch.smi_pending = events->smi.pending; 3000 if (events->smi.smm_inside_nmi) 3001 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 3002 else 3003 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 3004 if (kvm_vcpu_has_lapic(vcpu)) { 3005 if (events->smi.latched_init) 3006 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3007 else 3008 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 3009 } 3010 } 3011 3012 kvm_make_request(KVM_REQ_EVENT, vcpu); 3013 3014 return 0; 3015 } 3016 3017 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3018 struct kvm_debugregs *dbgregs) 3019 { 3020 unsigned long val; 3021 3022 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3023 kvm_get_dr(vcpu, 6, &val); 3024 dbgregs->dr6 = val; 3025 dbgregs->dr7 = vcpu->arch.dr7; 3026 dbgregs->flags = 0; 3027 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3028 } 3029 3030 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3031 struct kvm_debugregs *dbgregs) 3032 { 3033 if (dbgregs->flags) 3034 return -EINVAL; 3035 3036 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3037 kvm_update_dr0123(vcpu); 3038 vcpu->arch.dr6 = dbgregs->dr6; 3039 kvm_update_dr6(vcpu); 3040 vcpu->arch.dr7 = dbgregs->dr7; 3041 kvm_update_dr7(vcpu); 3042 3043 return 0; 3044 } 3045 3046 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) 3047 3048 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu) 3049 { 3050 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3051 u64 xstate_bv = xsave->header.xfeatures; 3052 u64 valid; 3053 3054 /* 3055 * Copy legacy XSAVE area, to avoid complications with CPUID 3056 * leaves 0 and 1 in the loop below. 3057 */ 3058 memcpy(dest, xsave, XSAVE_HDR_OFFSET); 3059 3060 /* Set XSTATE_BV */ 3061 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv; 3062 3063 /* 3064 * Copy each region from the possibly compacted offset to the 3065 * non-compacted offset. 3066 */ 3067 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3068 while (valid) { 3069 u64 feature = valid & -valid; 3070 int index = fls64(feature) - 1; 3071 void *src = get_xsave_addr(xsave, feature); 3072 3073 if (src) { 3074 u32 size, offset, ecx, edx; 3075 cpuid_count(XSTATE_CPUID, index, 3076 &size, &offset, &ecx, &edx); 3077 memcpy(dest + offset, src, size); 3078 } 3079 3080 valid -= feature; 3081 } 3082 } 3083 3084 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src) 3085 { 3086 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave; 3087 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET); 3088 u64 valid; 3089 3090 /* 3091 * Copy legacy XSAVE area, to avoid complications with CPUID 3092 * leaves 0 and 1 in the loop below. 3093 */ 3094 memcpy(xsave, src, XSAVE_HDR_OFFSET); 3095 3096 /* Set XSTATE_BV and possibly XCOMP_BV. */ 3097 xsave->header.xfeatures = xstate_bv; 3098 if (cpu_has_xsaves) 3099 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED; 3100 3101 /* 3102 * Copy each region from the non-compacted offset to the 3103 * possibly compacted offset. 3104 */ 3105 valid = xstate_bv & ~XFEATURE_MASK_FPSSE; 3106 while (valid) { 3107 u64 feature = valid & -valid; 3108 int index = fls64(feature) - 1; 3109 void *dest = get_xsave_addr(xsave, feature); 3110 3111 if (dest) { 3112 u32 size, offset, ecx, edx; 3113 cpuid_count(XSTATE_CPUID, index, 3114 &size, &offset, &ecx, &edx); 3115 memcpy(dest, src + offset, size); 3116 } 3117 3118 valid -= feature; 3119 } 3120 } 3121 3122 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3123 struct kvm_xsave *guest_xsave) 3124 { 3125 if (cpu_has_xsave) { 3126 memset(guest_xsave, 0, sizeof(struct kvm_xsave)); 3127 fill_xsave((u8 *) guest_xsave->region, vcpu); 3128 } else { 3129 memcpy(guest_xsave->region, 3130 &vcpu->arch.guest_fpu.state.fxsave, 3131 sizeof(struct fxregs_state)); 3132 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3133 XFEATURE_MASK_FPSSE; 3134 } 3135 } 3136 3137 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3138 struct kvm_xsave *guest_xsave) 3139 { 3140 u64 xstate_bv = 3141 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3142 3143 if (cpu_has_xsave) { 3144 /* 3145 * Here we allow setting states that are not present in 3146 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3147 * with old userspace. 3148 */ 3149 if (xstate_bv & ~kvm_supported_xcr0()) 3150 return -EINVAL; 3151 load_xsave(vcpu, (u8 *)guest_xsave->region); 3152 } else { 3153 if (xstate_bv & ~XFEATURE_MASK_FPSSE) 3154 return -EINVAL; 3155 memcpy(&vcpu->arch.guest_fpu.state.fxsave, 3156 guest_xsave->region, sizeof(struct fxregs_state)); 3157 } 3158 return 0; 3159 } 3160 3161 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3162 struct kvm_xcrs *guest_xcrs) 3163 { 3164 if (!cpu_has_xsave) { 3165 guest_xcrs->nr_xcrs = 0; 3166 return; 3167 } 3168 3169 guest_xcrs->nr_xcrs = 1; 3170 guest_xcrs->flags = 0; 3171 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3172 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3173 } 3174 3175 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3176 struct kvm_xcrs *guest_xcrs) 3177 { 3178 int i, r = 0; 3179 3180 if (!cpu_has_xsave) 3181 return -EINVAL; 3182 3183 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3184 return -EINVAL; 3185 3186 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3187 /* Only support XCR0 currently */ 3188 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3189 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3190 guest_xcrs->xcrs[i].value); 3191 break; 3192 } 3193 if (r) 3194 r = -EINVAL; 3195 return r; 3196 } 3197 3198 /* 3199 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3200 * stopped by the hypervisor. This function will be called from the host only. 3201 * EINVAL is returned when the host attempts to set the flag for a guest that 3202 * does not support pv clocks. 3203 */ 3204 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3205 { 3206 if (!vcpu->arch.pv_time_enabled) 3207 return -EINVAL; 3208 vcpu->arch.pvclock_set_guest_stopped_request = true; 3209 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3210 return 0; 3211 } 3212 3213 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 3214 struct kvm_enable_cap *cap) 3215 { 3216 if (cap->flags) 3217 return -EINVAL; 3218 3219 switch (cap->cap) { 3220 case KVM_CAP_HYPERV_SYNIC: 3221 return kvm_hv_activate_synic(vcpu); 3222 default: 3223 return -EINVAL; 3224 } 3225 } 3226 3227 long kvm_arch_vcpu_ioctl(struct file *filp, 3228 unsigned int ioctl, unsigned long arg) 3229 { 3230 struct kvm_vcpu *vcpu = filp->private_data; 3231 void __user *argp = (void __user *)arg; 3232 int r; 3233 union { 3234 struct kvm_lapic_state *lapic; 3235 struct kvm_xsave *xsave; 3236 struct kvm_xcrs *xcrs; 3237 void *buffer; 3238 } u; 3239 3240 u.buffer = NULL; 3241 switch (ioctl) { 3242 case KVM_GET_LAPIC: { 3243 r = -EINVAL; 3244 if (!vcpu->arch.apic) 3245 goto out; 3246 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3247 3248 r = -ENOMEM; 3249 if (!u.lapic) 3250 goto out; 3251 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3252 if (r) 3253 goto out; 3254 r = -EFAULT; 3255 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3256 goto out; 3257 r = 0; 3258 break; 3259 } 3260 case KVM_SET_LAPIC: { 3261 r = -EINVAL; 3262 if (!vcpu->arch.apic) 3263 goto out; 3264 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3265 if (IS_ERR(u.lapic)) 3266 return PTR_ERR(u.lapic); 3267 3268 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3269 break; 3270 } 3271 case KVM_INTERRUPT: { 3272 struct kvm_interrupt irq; 3273 3274 r = -EFAULT; 3275 if (copy_from_user(&irq, argp, sizeof irq)) 3276 goto out; 3277 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3278 break; 3279 } 3280 case KVM_NMI: { 3281 r = kvm_vcpu_ioctl_nmi(vcpu); 3282 break; 3283 } 3284 case KVM_SMI: { 3285 r = kvm_vcpu_ioctl_smi(vcpu); 3286 break; 3287 } 3288 case KVM_SET_CPUID: { 3289 struct kvm_cpuid __user *cpuid_arg = argp; 3290 struct kvm_cpuid cpuid; 3291 3292 r = -EFAULT; 3293 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3294 goto out; 3295 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3296 break; 3297 } 3298 case KVM_SET_CPUID2: { 3299 struct kvm_cpuid2 __user *cpuid_arg = argp; 3300 struct kvm_cpuid2 cpuid; 3301 3302 r = -EFAULT; 3303 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3304 goto out; 3305 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3306 cpuid_arg->entries); 3307 break; 3308 } 3309 case KVM_GET_CPUID2: { 3310 struct kvm_cpuid2 __user *cpuid_arg = argp; 3311 struct kvm_cpuid2 cpuid; 3312 3313 r = -EFAULT; 3314 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3315 goto out; 3316 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3317 cpuid_arg->entries); 3318 if (r) 3319 goto out; 3320 r = -EFAULT; 3321 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3322 goto out; 3323 r = 0; 3324 break; 3325 } 3326 case KVM_GET_MSRS: 3327 r = msr_io(vcpu, argp, do_get_msr, 1); 3328 break; 3329 case KVM_SET_MSRS: 3330 r = msr_io(vcpu, argp, do_set_msr, 0); 3331 break; 3332 case KVM_TPR_ACCESS_REPORTING: { 3333 struct kvm_tpr_access_ctl tac; 3334 3335 r = -EFAULT; 3336 if (copy_from_user(&tac, argp, sizeof tac)) 3337 goto out; 3338 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3339 if (r) 3340 goto out; 3341 r = -EFAULT; 3342 if (copy_to_user(argp, &tac, sizeof tac)) 3343 goto out; 3344 r = 0; 3345 break; 3346 }; 3347 case KVM_SET_VAPIC_ADDR: { 3348 struct kvm_vapic_addr va; 3349 3350 r = -EINVAL; 3351 if (!lapic_in_kernel(vcpu)) 3352 goto out; 3353 r = -EFAULT; 3354 if (copy_from_user(&va, argp, sizeof va)) 3355 goto out; 3356 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3357 break; 3358 } 3359 case KVM_X86_SETUP_MCE: { 3360 u64 mcg_cap; 3361 3362 r = -EFAULT; 3363 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3364 goto out; 3365 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3366 break; 3367 } 3368 case KVM_X86_SET_MCE: { 3369 struct kvm_x86_mce mce; 3370 3371 r = -EFAULT; 3372 if (copy_from_user(&mce, argp, sizeof mce)) 3373 goto out; 3374 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3375 break; 3376 } 3377 case KVM_GET_VCPU_EVENTS: { 3378 struct kvm_vcpu_events events; 3379 3380 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3381 3382 r = -EFAULT; 3383 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3384 break; 3385 r = 0; 3386 break; 3387 } 3388 case KVM_SET_VCPU_EVENTS: { 3389 struct kvm_vcpu_events events; 3390 3391 r = -EFAULT; 3392 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3393 break; 3394 3395 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3396 break; 3397 } 3398 case KVM_GET_DEBUGREGS: { 3399 struct kvm_debugregs dbgregs; 3400 3401 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3402 3403 r = -EFAULT; 3404 if (copy_to_user(argp, &dbgregs, 3405 sizeof(struct kvm_debugregs))) 3406 break; 3407 r = 0; 3408 break; 3409 } 3410 case KVM_SET_DEBUGREGS: { 3411 struct kvm_debugregs dbgregs; 3412 3413 r = -EFAULT; 3414 if (copy_from_user(&dbgregs, argp, 3415 sizeof(struct kvm_debugregs))) 3416 break; 3417 3418 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3419 break; 3420 } 3421 case KVM_GET_XSAVE: { 3422 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3423 r = -ENOMEM; 3424 if (!u.xsave) 3425 break; 3426 3427 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3428 3429 r = -EFAULT; 3430 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3431 break; 3432 r = 0; 3433 break; 3434 } 3435 case KVM_SET_XSAVE: { 3436 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3437 if (IS_ERR(u.xsave)) 3438 return PTR_ERR(u.xsave); 3439 3440 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3441 break; 3442 } 3443 case KVM_GET_XCRS: { 3444 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3445 r = -ENOMEM; 3446 if (!u.xcrs) 3447 break; 3448 3449 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3450 3451 r = -EFAULT; 3452 if (copy_to_user(argp, u.xcrs, 3453 sizeof(struct kvm_xcrs))) 3454 break; 3455 r = 0; 3456 break; 3457 } 3458 case KVM_SET_XCRS: { 3459 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3460 if (IS_ERR(u.xcrs)) 3461 return PTR_ERR(u.xcrs); 3462 3463 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3464 break; 3465 } 3466 case KVM_SET_TSC_KHZ: { 3467 u32 user_tsc_khz; 3468 3469 r = -EINVAL; 3470 user_tsc_khz = (u32)arg; 3471 3472 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3473 goto out; 3474 3475 if (user_tsc_khz == 0) 3476 user_tsc_khz = tsc_khz; 3477 3478 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 3479 r = 0; 3480 3481 goto out; 3482 } 3483 case KVM_GET_TSC_KHZ: { 3484 r = vcpu->arch.virtual_tsc_khz; 3485 goto out; 3486 } 3487 case KVM_KVMCLOCK_CTRL: { 3488 r = kvm_set_guest_paused(vcpu); 3489 goto out; 3490 } 3491 case KVM_ENABLE_CAP: { 3492 struct kvm_enable_cap cap; 3493 3494 r = -EFAULT; 3495 if (copy_from_user(&cap, argp, sizeof(cap))) 3496 goto out; 3497 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 3498 break; 3499 } 3500 default: 3501 r = -EINVAL; 3502 } 3503 out: 3504 kfree(u.buffer); 3505 return r; 3506 } 3507 3508 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3509 { 3510 return VM_FAULT_SIGBUS; 3511 } 3512 3513 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3514 { 3515 int ret; 3516 3517 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3518 return -EINVAL; 3519 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3520 return ret; 3521 } 3522 3523 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3524 u64 ident_addr) 3525 { 3526 kvm->arch.ept_identity_map_addr = ident_addr; 3527 return 0; 3528 } 3529 3530 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3531 u32 kvm_nr_mmu_pages) 3532 { 3533 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3534 return -EINVAL; 3535 3536 mutex_lock(&kvm->slots_lock); 3537 3538 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3539 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3540 3541 mutex_unlock(&kvm->slots_lock); 3542 return 0; 3543 } 3544 3545 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 3546 { 3547 return kvm->arch.n_max_mmu_pages; 3548 } 3549 3550 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3551 { 3552 int r; 3553 3554 r = 0; 3555 switch (chip->chip_id) { 3556 case KVM_IRQCHIP_PIC_MASTER: 3557 memcpy(&chip->chip.pic, 3558 &pic_irqchip(kvm)->pics[0], 3559 sizeof(struct kvm_pic_state)); 3560 break; 3561 case KVM_IRQCHIP_PIC_SLAVE: 3562 memcpy(&chip->chip.pic, 3563 &pic_irqchip(kvm)->pics[1], 3564 sizeof(struct kvm_pic_state)); 3565 break; 3566 case KVM_IRQCHIP_IOAPIC: 3567 r = kvm_get_ioapic(kvm, &chip->chip.ioapic); 3568 break; 3569 default: 3570 r = -EINVAL; 3571 break; 3572 } 3573 return r; 3574 } 3575 3576 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3577 { 3578 int r; 3579 3580 r = 0; 3581 switch (chip->chip_id) { 3582 case KVM_IRQCHIP_PIC_MASTER: 3583 spin_lock(&pic_irqchip(kvm)->lock); 3584 memcpy(&pic_irqchip(kvm)->pics[0], 3585 &chip->chip.pic, 3586 sizeof(struct kvm_pic_state)); 3587 spin_unlock(&pic_irqchip(kvm)->lock); 3588 break; 3589 case KVM_IRQCHIP_PIC_SLAVE: 3590 spin_lock(&pic_irqchip(kvm)->lock); 3591 memcpy(&pic_irqchip(kvm)->pics[1], 3592 &chip->chip.pic, 3593 sizeof(struct kvm_pic_state)); 3594 spin_unlock(&pic_irqchip(kvm)->lock); 3595 break; 3596 case KVM_IRQCHIP_IOAPIC: 3597 r = kvm_set_ioapic(kvm, &chip->chip.ioapic); 3598 break; 3599 default: 3600 r = -EINVAL; 3601 break; 3602 } 3603 kvm_pic_update_irq(pic_irqchip(kvm)); 3604 return r; 3605 } 3606 3607 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3608 { 3609 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3610 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); 3611 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3612 return 0; 3613 } 3614 3615 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3616 { 3617 int i; 3618 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3619 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); 3620 for (i = 0; i < 3; i++) 3621 kvm_pit_load_count(kvm, i, ps->channels[i].count, 0); 3622 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3623 return 0; 3624 } 3625 3626 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3627 { 3628 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3629 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 3630 sizeof(ps->channels)); 3631 ps->flags = kvm->arch.vpit->pit_state.flags; 3632 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3633 memset(&ps->reserved, 0, sizeof(ps->reserved)); 3634 return 0; 3635 } 3636 3637 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3638 { 3639 int start = 0; 3640 int i; 3641 u32 prev_legacy, cur_legacy; 3642 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3643 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 3644 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 3645 if (!prev_legacy && cur_legacy) 3646 start = 1; 3647 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, 3648 sizeof(kvm->arch.vpit->pit_state.channels)); 3649 kvm->arch.vpit->pit_state.flags = ps->flags; 3650 for (i = 0; i < 3; i++) 3651 kvm_pit_load_count(kvm, i, kvm->arch.vpit->pit_state.channels[i].count, 3652 start && i == 0); 3653 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3654 return 0; 3655 } 3656 3657 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 3658 struct kvm_reinject_control *control) 3659 { 3660 if (!kvm->arch.vpit) 3661 return -ENXIO; 3662 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3663 kvm->arch.vpit->pit_state.reinject = control->pit_reinject; 3664 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3665 return 0; 3666 } 3667 3668 /** 3669 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 3670 * @kvm: kvm instance 3671 * @log: slot id and address to which we copy the log 3672 * 3673 * Steps 1-4 below provide general overview of dirty page logging. See 3674 * kvm_get_dirty_log_protect() function description for additional details. 3675 * 3676 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 3677 * always flush the TLB (step 4) even if previous step failed and the dirty 3678 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 3679 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 3680 * writes will be marked dirty for next log read. 3681 * 3682 * 1. Take a snapshot of the bit and clear it if needed. 3683 * 2. Write protect the corresponding page. 3684 * 3. Copy the snapshot to the userspace. 3685 * 4. Flush TLB's if needed. 3686 */ 3687 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 3688 { 3689 bool is_dirty = false; 3690 int r; 3691 3692 mutex_lock(&kvm->slots_lock); 3693 3694 /* 3695 * Flush potentially hardware-cached dirty pages to dirty_bitmap. 3696 */ 3697 if (kvm_x86_ops->flush_log_dirty) 3698 kvm_x86_ops->flush_log_dirty(kvm); 3699 3700 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 3701 3702 /* 3703 * All the TLBs can be flushed out of mmu lock, see the comments in 3704 * kvm_mmu_slot_remove_write_access(). 3705 */ 3706 lockdep_assert_held(&kvm->slots_lock); 3707 if (is_dirty) 3708 kvm_flush_remote_tlbs(kvm); 3709 3710 mutex_unlock(&kvm->slots_lock); 3711 return r; 3712 } 3713 3714 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 3715 bool line_status) 3716 { 3717 if (!irqchip_in_kernel(kvm)) 3718 return -ENXIO; 3719 3720 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 3721 irq_event->irq, irq_event->level, 3722 line_status); 3723 return 0; 3724 } 3725 3726 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 3727 struct kvm_enable_cap *cap) 3728 { 3729 int r; 3730 3731 if (cap->flags) 3732 return -EINVAL; 3733 3734 switch (cap->cap) { 3735 case KVM_CAP_DISABLE_QUIRKS: 3736 kvm->arch.disabled_quirks = cap->args[0]; 3737 r = 0; 3738 break; 3739 case KVM_CAP_SPLIT_IRQCHIP: { 3740 mutex_lock(&kvm->lock); 3741 r = -EINVAL; 3742 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 3743 goto split_irqchip_unlock; 3744 r = -EEXIST; 3745 if (irqchip_in_kernel(kvm)) 3746 goto split_irqchip_unlock; 3747 if (atomic_read(&kvm->online_vcpus)) 3748 goto split_irqchip_unlock; 3749 r = kvm_setup_empty_irq_routing(kvm); 3750 if (r) 3751 goto split_irqchip_unlock; 3752 /* Pairs with irqchip_in_kernel. */ 3753 smp_wmb(); 3754 kvm->arch.irqchip_split = true; 3755 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 3756 r = 0; 3757 split_irqchip_unlock: 3758 mutex_unlock(&kvm->lock); 3759 break; 3760 } 3761 default: 3762 r = -EINVAL; 3763 break; 3764 } 3765 return r; 3766 } 3767 3768 long kvm_arch_vm_ioctl(struct file *filp, 3769 unsigned int ioctl, unsigned long arg) 3770 { 3771 struct kvm *kvm = filp->private_data; 3772 void __user *argp = (void __user *)arg; 3773 int r = -ENOTTY; 3774 /* 3775 * This union makes it completely explicit to gcc-3.x 3776 * that these two variables' stack usage should be 3777 * combined, not added together. 3778 */ 3779 union { 3780 struct kvm_pit_state ps; 3781 struct kvm_pit_state2 ps2; 3782 struct kvm_pit_config pit_config; 3783 } u; 3784 3785 switch (ioctl) { 3786 case KVM_SET_TSS_ADDR: 3787 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 3788 break; 3789 case KVM_SET_IDENTITY_MAP_ADDR: { 3790 u64 ident_addr; 3791 3792 r = -EFAULT; 3793 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 3794 goto out; 3795 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 3796 break; 3797 } 3798 case KVM_SET_NR_MMU_PAGES: 3799 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 3800 break; 3801 case KVM_GET_NR_MMU_PAGES: 3802 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 3803 break; 3804 case KVM_CREATE_IRQCHIP: { 3805 struct kvm_pic *vpic; 3806 3807 mutex_lock(&kvm->lock); 3808 r = -EEXIST; 3809 if (kvm->arch.vpic) 3810 goto create_irqchip_unlock; 3811 r = -EINVAL; 3812 if (atomic_read(&kvm->online_vcpus)) 3813 goto create_irqchip_unlock; 3814 r = -ENOMEM; 3815 vpic = kvm_create_pic(kvm); 3816 if (vpic) { 3817 r = kvm_ioapic_init(kvm); 3818 if (r) { 3819 mutex_lock(&kvm->slots_lock); 3820 kvm_destroy_pic(vpic); 3821 mutex_unlock(&kvm->slots_lock); 3822 goto create_irqchip_unlock; 3823 } 3824 } else 3825 goto create_irqchip_unlock; 3826 r = kvm_setup_default_irq_routing(kvm); 3827 if (r) { 3828 mutex_lock(&kvm->slots_lock); 3829 mutex_lock(&kvm->irq_lock); 3830 kvm_ioapic_destroy(kvm); 3831 kvm_destroy_pic(vpic); 3832 mutex_unlock(&kvm->irq_lock); 3833 mutex_unlock(&kvm->slots_lock); 3834 goto create_irqchip_unlock; 3835 } 3836 /* Write kvm->irq_routing before kvm->arch.vpic. */ 3837 smp_wmb(); 3838 kvm->arch.vpic = vpic; 3839 create_irqchip_unlock: 3840 mutex_unlock(&kvm->lock); 3841 break; 3842 } 3843 case KVM_CREATE_PIT: 3844 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 3845 goto create_pit; 3846 case KVM_CREATE_PIT2: 3847 r = -EFAULT; 3848 if (copy_from_user(&u.pit_config, argp, 3849 sizeof(struct kvm_pit_config))) 3850 goto out; 3851 create_pit: 3852 mutex_lock(&kvm->slots_lock); 3853 r = -EEXIST; 3854 if (kvm->arch.vpit) 3855 goto create_pit_unlock; 3856 r = -ENOMEM; 3857 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 3858 if (kvm->arch.vpit) 3859 r = 0; 3860 create_pit_unlock: 3861 mutex_unlock(&kvm->slots_lock); 3862 break; 3863 case KVM_GET_IRQCHIP: { 3864 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3865 struct kvm_irqchip *chip; 3866 3867 chip = memdup_user(argp, sizeof(*chip)); 3868 if (IS_ERR(chip)) { 3869 r = PTR_ERR(chip); 3870 goto out; 3871 } 3872 3873 r = -ENXIO; 3874 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm)) 3875 goto get_irqchip_out; 3876 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 3877 if (r) 3878 goto get_irqchip_out; 3879 r = -EFAULT; 3880 if (copy_to_user(argp, chip, sizeof *chip)) 3881 goto get_irqchip_out; 3882 r = 0; 3883 get_irqchip_out: 3884 kfree(chip); 3885 break; 3886 } 3887 case KVM_SET_IRQCHIP: { 3888 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3889 struct kvm_irqchip *chip; 3890 3891 chip = memdup_user(argp, sizeof(*chip)); 3892 if (IS_ERR(chip)) { 3893 r = PTR_ERR(chip); 3894 goto out; 3895 } 3896 3897 r = -ENXIO; 3898 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm)) 3899 goto set_irqchip_out; 3900 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 3901 if (r) 3902 goto set_irqchip_out; 3903 r = 0; 3904 set_irqchip_out: 3905 kfree(chip); 3906 break; 3907 } 3908 case KVM_GET_PIT: { 3909 r = -EFAULT; 3910 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 3911 goto out; 3912 r = -ENXIO; 3913 if (!kvm->arch.vpit) 3914 goto out; 3915 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 3916 if (r) 3917 goto out; 3918 r = -EFAULT; 3919 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 3920 goto out; 3921 r = 0; 3922 break; 3923 } 3924 case KVM_SET_PIT: { 3925 r = -EFAULT; 3926 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 3927 goto out; 3928 r = -ENXIO; 3929 if (!kvm->arch.vpit) 3930 goto out; 3931 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 3932 break; 3933 } 3934 case KVM_GET_PIT2: { 3935 r = -ENXIO; 3936 if (!kvm->arch.vpit) 3937 goto out; 3938 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 3939 if (r) 3940 goto out; 3941 r = -EFAULT; 3942 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 3943 goto out; 3944 r = 0; 3945 break; 3946 } 3947 case KVM_SET_PIT2: { 3948 r = -EFAULT; 3949 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 3950 goto out; 3951 r = -ENXIO; 3952 if (!kvm->arch.vpit) 3953 goto out; 3954 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 3955 break; 3956 } 3957 case KVM_REINJECT_CONTROL: { 3958 struct kvm_reinject_control control; 3959 r = -EFAULT; 3960 if (copy_from_user(&control, argp, sizeof(control))) 3961 goto out; 3962 r = kvm_vm_ioctl_reinject(kvm, &control); 3963 break; 3964 } 3965 case KVM_SET_BOOT_CPU_ID: 3966 r = 0; 3967 mutex_lock(&kvm->lock); 3968 if (atomic_read(&kvm->online_vcpus) != 0) 3969 r = -EBUSY; 3970 else 3971 kvm->arch.bsp_vcpu_id = arg; 3972 mutex_unlock(&kvm->lock); 3973 break; 3974 case KVM_XEN_HVM_CONFIG: { 3975 r = -EFAULT; 3976 if (copy_from_user(&kvm->arch.xen_hvm_config, argp, 3977 sizeof(struct kvm_xen_hvm_config))) 3978 goto out; 3979 r = -EINVAL; 3980 if (kvm->arch.xen_hvm_config.flags) 3981 goto out; 3982 r = 0; 3983 break; 3984 } 3985 case KVM_SET_CLOCK: { 3986 struct kvm_clock_data user_ns; 3987 u64 now_ns; 3988 s64 delta; 3989 3990 r = -EFAULT; 3991 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 3992 goto out; 3993 3994 r = -EINVAL; 3995 if (user_ns.flags) 3996 goto out; 3997 3998 r = 0; 3999 local_irq_disable(); 4000 now_ns = get_kernel_ns(); 4001 delta = user_ns.clock - now_ns; 4002 local_irq_enable(); 4003 kvm->arch.kvmclock_offset = delta; 4004 kvm_gen_update_masterclock(kvm); 4005 break; 4006 } 4007 case KVM_GET_CLOCK: { 4008 struct kvm_clock_data user_ns; 4009 u64 now_ns; 4010 4011 local_irq_disable(); 4012 now_ns = get_kernel_ns(); 4013 user_ns.clock = kvm->arch.kvmclock_offset + now_ns; 4014 local_irq_enable(); 4015 user_ns.flags = 0; 4016 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 4017 4018 r = -EFAULT; 4019 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 4020 goto out; 4021 r = 0; 4022 break; 4023 } 4024 case KVM_ENABLE_CAP: { 4025 struct kvm_enable_cap cap; 4026 4027 r = -EFAULT; 4028 if (copy_from_user(&cap, argp, sizeof(cap))) 4029 goto out; 4030 r = kvm_vm_ioctl_enable_cap(kvm, &cap); 4031 break; 4032 } 4033 default: 4034 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg); 4035 } 4036 out: 4037 return r; 4038 } 4039 4040 static void kvm_init_msr_list(void) 4041 { 4042 u32 dummy[2]; 4043 unsigned i, j; 4044 4045 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { 4046 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 4047 continue; 4048 4049 /* 4050 * Even MSRs that are valid in the host may not be exposed 4051 * to the guests in some cases. 4052 */ 4053 switch (msrs_to_save[i]) { 4054 case MSR_IA32_BNDCFGS: 4055 if (!kvm_x86_ops->mpx_supported()) 4056 continue; 4057 break; 4058 case MSR_TSC_AUX: 4059 if (!kvm_x86_ops->rdtscp_supported()) 4060 continue; 4061 break; 4062 default: 4063 break; 4064 } 4065 4066 if (j < i) 4067 msrs_to_save[j] = msrs_to_save[i]; 4068 j++; 4069 } 4070 num_msrs_to_save = j; 4071 4072 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) { 4073 switch (emulated_msrs[i]) { 4074 case MSR_IA32_SMBASE: 4075 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase()) 4076 continue; 4077 break; 4078 default: 4079 break; 4080 } 4081 4082 if (j < i) 4083 emulated_msrs[j] = emulated_msrs[i]; 4084 j++; 4085 } 4086 num_emulated_msrs = j; 4087 } 4088 4089 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 4090 const void *v) 4091 { 4092 int handled = 0; 4093 int n; 4094 4095 do { 4096 n = min(len, 8); 4097 if (!(vcpu->arch.apic && 4098 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 4099 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 4100 break; 4101 handled += n; 4102 addr += n; 4103 len -= n; 4104 v += n; 4105 } while (len); 4106 4107 return handled; 4108 } 4109 4110 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 4111 { 4112 int handled = 0; 4113 int n; 4114 4115 do { 4116 n = min(len, 8); 4117 if (!(vcpu->arch.apic && 4118 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 4119 addr, n, v)) 4120 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 4121 break; 4122 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); 4123 handled += n; 4124 addr += n; 4125 len -= n; 4126 v += n; 4127 } while (len); 4128 4129 return handled; 4130 } 4131 4132 static void kvm_set_segment(struct kvm_vcpu *vcpu, 4133 struct kvm_segment *var, int seg) 4134 { 4135 kvm_x86_ops->set_segment(vcpu, var, seg); 4136 } 4137 4138 void kvm_get_segment(struct kvm_vcpu *vcpu, 4139 struct kvm_segment *var, int seg) 4140 { 4141 kvm_x86_ops->get_segment(vcpu, var, seg); 4142 } 4143 4144 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 4145 struct x86_exception *exception) 4146 { 4147 gpa_t t_gpa; 4148 4149 BUG_ON(!mmu_is_nested(vcpu)); 4150 4151 /* NPT walks are always user-walks */ 4152 access |= PFERR_USER_MASK; 4153 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception); 4154 4155 return t_gpa; 4156 } 4157 4158 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 4159 struct x86_exception *exception) 4160 { 4161 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4162 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4163 } 4164 4165 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 4166 struct x86_exception *exception) 4167 { 4168 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4169 access |= PFERR_FETCH_MASK; 4170 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4171 } 4172 4173 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 4174 struct x86_exception *exception) 4175 { 4176 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4177 access |= PFERR_WRITE_MASK; 4178 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4179 } 4180 4181 /* uses this to access any guest's mapped memory without checking CPL */ 4182 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 4183 struct x86_exception *exception) 4184 { 4185 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 4186 } 4187 4188 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 4189 struct kvm_vcpu *vcpu, u32 access, 4190 struct x86_exception *exception) 4191 { 4192 void *data = val; 4193 int r = X86EMUL_CONTINUE; 4194 4195 while (bytes) { 4196 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 4197 exception); 4198 unsigned offset = addr & (PAGE_SIZE-1); 4199 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 4200 int ret; 4201 4202 if (gpa == UNMAPPED_GVA) 4203 return X86EMUL_PROPAGATE_FAULT; 4204 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 4205 offset, toread); 4206 if (ret < 0) { 4207 r = X86EMUL_IO_NEEDED; 4208 goto out; 4209 } 4210 4211 bytes -= toread; 4212 data += toread; 4213 addr += toread; 4214 } 4215 out: 4216 return r; 4217 } 4218 4219 /* used for instruction fetching */ 4220 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4221 gva_t addr, void *val, unsigned int bytes, 4222 struct x86_exception *exception) 4223 { 4224 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4225 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4226 unsigned offset; 4227 int ret; 4228 4229 /* Inline kvm_read_guest_virt_helper for speed. */ 4230 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK, 4231 exception); 4232 if (unlikely(gpa == UNMAPPED_GVA)) 4233 return X86EMUL_PROPAGATE_FAULT; 4234 4235 offset = addr & (PAGE_SIZE-1); 4236 if (WARN_ON(offset + bytes > PAGE_SIZE)) 4237 bytes = (unsigned)PAGE_SIZE - offset; 4238 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 4239 offset, bytes); 4240 if (unlikely(ret < 0)) 4241 return X86EMUL_IO_NEEDED; 4242 4243 return X86EMUL_CONTINUE; 4244 } 4245 4246 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4247 gva_t addr, void *val, unsigned int bytes, 4248 struct x86_exception *exception) 4249 { 4250 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4251 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4252 4253 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4254 exception); 4255 } 4256 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4257 4258 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4259 gva_t addr, void *val, unsigned int bytes, 4260 struct x86_exception *exception) 4261 { 4262 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4263 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4264 } 4265 4266 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, 4267 unsigned long addr, void *val, unsigned int bytes) 4268 { 4269 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4270 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); 4271 4272 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; 4273 } 4274 4275 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4276 gva_t addr, void *val, 4277 unsigned int bytes, 4278 struct x86_exception *exception) 4279 { 4280 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4281 void *data = val; 4282 int r = X86EMUL_CONTINUE; 4283 4284 while (bytes) { 4285 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4286 PFERR_WRITE_MASK, 4287 exception); 4288 unsigned offset = addr & (PAGE_SIZE-1); 4289 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4290 int ret; 4291 4292 if (gpa == UNMAPPED_GVA) 4293 return X86EMUL_PROPAGATE_FAULT; 4294 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 4295 if (ret < 0) { 4296 r = X86EMUL_IO_NEEDED; 4297 goto out; 4298 } 4299 4300 bytes -= towrite; 4301 data += towrite; 4302 addr += towrite; 4303 } 4304 out: 4305 return r; 4306 } 4307 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4308 4309 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4310 gpa_t *gpa, struct x86_exception *exception, 4311 bool write) 4312 { 4313 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4314 | (write ? PFERR_WRITE_MASK : 0); 4315 4316 if (vcpu_match_mmio_gva(vcpu, gva) 4317 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4318 vcpu->arch.access, access)) { 4319 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4320 (gva & (PAGE_SIZE - 1)); 4321 trace_vcpu_match_mmio(gva, *gpa, write, false); 4322 return 1; 4323 } 4324 4325 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4326 4327 if (*gpa == UNMAPPED_GVA) 4328 return -1; 4329 4330 /* For APIC access vmexit */ 4331 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4332 return 1; 4333 4334 if (vcpu_match_mmio_gpa(vcpu, *gpa)) { 4335 trace_vcpu_match_mmio(gva, *gpa, write, true); 4336 return 1; 4337 } 4338 4339 return 0; 4340 } 4341 4342 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4343 const void *val, int bytes) 4344 { 4345 int ret; 4346 4347 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 4348 if (ret < 0) 4349 return 0; 4350 kvm_mmu_pte_write(vcpu, gpa, val, bytes); 4351 return 1; 4352 } 4353 4354 struct read_write_emulator_ops { 4355 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4356 int bytes); 4357 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4358 void *val, int bytes); 4359 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4360 int bytes, void *val); 4361 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4362 void *val, int bytes); 4363 bool write; 4364 }; 4365 4366 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4367 { 4368 if (vcpu->mmio_read_completed) { 4369 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4370 vcpu->mmio_fragments[0].gpa, *(u64 *)val); 4371 vcpu->mmio_read_completed = 0; 4372 return 1; 4373 } 4374 4375 return 0; 4376 } 4377 4378 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4379 void *val, int bytes) 4380 { 4381 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 4382 } 4383 4384 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4385 void *val, int bytes) 4386 { 4387 return emulator_write_phys(vcpu, gpa, val, bytes); 4388 } 4389 4390 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4391 { 4392 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); 4393 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4394 } 4395 4396 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4397 void *val, int bytes) 4398 { 4399 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); 4400 return X86EMUL_IO_NEEDED; 4401 } 4402 4403 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4404 void *val, int bytes) 4405 { 4406 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4407 4408 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4409 return X86EMUL_CONTINUE; 4410 } 4411 4412 static const struct read_write_emulator_ops read_emultor = { 4413 .read_write_prepare = read_prepare, 4414 .read_write_emulate = read_emulate, 4415 .read_write_mmio = vcpu_mmio_read, 4416 .read_write_exit_mmio = read_exit_mmio, 4417 }; 4418 4419 static const struct read_write_emulator_ops write_emultor = { 4420 .read_write_emulate = write_emulate, 4421 .read_write_mmio = write_mmio, 4422 .read_write_exit_mmio = write_exit_mmio, 4423 .write = true, 4424 }; 4425 4426 static int emulator_read_write_onepage(unsigned long addr, void *val, 4427 unsigned int bytes, 4428 struct x86_exception *exception, 4429 struct kvm_vcpu *vcpu, 4430 const struct read_write_emulator_ops *ops) 4431 { 4432 gpa_t gpa; 4433 int handled, ret; 4434 bool write = ops->write; 4435 struct kvm_mmio_fragment *frag; 4436 4437 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 4438 4439 if (ret < 0) 4440 return X86EMUL_PROPAGATE_FAULT; 4441 4442 /* For APIC access vmexit */ 4443 if (ret) 4444 goto mmio; 4445 4446 if (ops->read_write_emulate(vcpu, gpa, val, bytes)) 4447 return X86EMUL_CONTINUE; 4448 4449 mmio: 4450 /* 4451 * Is this MMIO handled locally? 4452 */ 4453 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 4454 if (handled == bytes) 4455 return X86EMUL_CONTINUE; 4456 4457 gpa += handled; 4458 bytes -= handled; 4459 val += handled; 4460 4461 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 4462 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 4463 frag->gpa = gpa; 4464 frag->data = val; 4465 frag->len = bytes; 4466 return X86EMUL_CONTINUE; 4467 } 4468 4469 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 4470 unsigned long addr, 4471 void *val, unsigned int bytes, 4472 struct x86_exception *exception, 4473 const struct read_write_emulator_ops *ops) 4474 { 4475 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4476 gpa_t gpa; 4477 int rc; 4478 4479 if (ops->read_write_prepare && 4480 ops->read_write_prepare(vcpu, val, bytes)) 4481 return X86EMUL_CONTINUE; 4482 4483 vcpu->mmio_nr_fragments = 0; 4484 4485 /* Crossing a page boundary? */ 4486 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 4487 int now; 4488 4489 now = -addr & ~PAGE_MASK; 4490 rc = emulator_read_write_onepage(addr, val, now, exception, 4491 vcpu, ops); 4492 4493 if (rc != X86EMUL_CONTINUE) 4494 return rc; 4495 addr += now; 4496 if (ctxt->mode != X86EMUL_MODE_PROT64) 4497 addr = (u32)addr; 4498 val += now; 4499 bytes -= now; 4500 } 4501 4502 rc = emulator_read_write_onepage(addr, val, bytes, exception, 4503 vcpu, ops); 4504 if (rc != X86EMUL_CONTINUE) 4505 return rc; 4506 4507 if (!vcpu->mmio_nr_fragments) 4508 return rc; 4509 4510 gpa = vcpu->mmio_fragments[0].gpa; 4511 4512 vcpu->mmio_needed = 1; 4513 vcpu->mmio_cur_fragment = 0; 4514 4515 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 4516 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 4517 vcpu->run->exit_reason = KVM_EXIT_MMIO; 4518 vcpu->run->mmio.phys_addr = gpa; 4519 4520 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 4521 } 4522 4523 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 4524 unsigned long addr, 4525 void *val, 4526 unsigned int bytes, 4527 struct x86_exception *exception) 4528 { 4529 return emulator_read_write(ctxt, addr, val, bytes, 4530 exception, &read_emultor); 4531 } 4532 4533 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 4534 unsigned long addr, 4535 const void *val, 4536 unsigned int bytes, 4537 struct x86_exception *exception) 4538 { 4539 return emulator_read_write(ctxt, addr, (void *)val, bytes, 4540 exception, &write_emultor); 4541 } 4542 4543 #define CMPXCHG_TYPE(t, ptr, old, new) \ 4544 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 4545 4546 #ifdef CONFIG_X86_64 4547 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 4548 #else 4549 # define CMPXCHG64(ptr, old, new) \ 4550 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 4551 #endif 4552 4553 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 4554 unsigned long addr, 4555 const void *old, 4556 const void *new, 4557 unsigned int bytes, 4558 struct x86_exception *exception) 4559 { 4560 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4561 gpa_t gpa; 4562 struct page *page; 4563 char *kaddr; 4564 bool exchanged; 4565 4566 /* guests cmpxchg8b have to be emulated atomically */ 4567 if (bytes > 8 || (bytes & (bytes - 1))) 4568 goto emul_write; 4569 4570 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 4571 4572 if (gpa == UNMAPPED_GVA || 4573 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4574 goto emul_write; 4575 4576 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 4577 goto emul_write; 4578 4579 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT); 4580 if (is_error_page(page)) 4581 goto emul_write; 4582 4583 kaddr = kmap_atomic(page); 4584 kaddr += offset_in_page(gpa); 4585 switch (bytes) { 4586 case 1: 4587 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 4588 break; 4589 case 2: 4590 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 4591 break; 4592 case 4: 4593 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 4594 break; 4595 case 8: 4596 exchanged = CMPXCHG64(kaddr, old, new); 4597 break; 4598 default: 4599 BUG(); 4600 } 4601 kunmap_atomic(kaddr); 4602 kvm_release_page_dirty(page); 4603 4604 if (!exchanged) 4605 return X86EMUL_CMPXCHG_FAILED; 4606 4607 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 4608 kvm_mmu_pte_write(vcpu, gpa, new, bytes); 4609 4610 return X86EMUL_CONTINUE; 4611 4612 emul_write: 4613 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 4614 4615 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 4616 } 4617 4618 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 4619 { 4620 /* TODO: String I/O for in kernel device */ 4621 int r; 4622 4623 if (vcpu->arch.pio.in) 4624 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port, 4625 vcpu->arch.pio.size, pd); 4626 else 4627 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, 4628 vcpu->arch.pio.port, vcpu->arch.pio.size, 4629 pd); 4630 return r; 4631 } 4632 4633 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 4634 unsigned short port, void *val, 4635 unsigned int count, bool in) 4636 { 4637 vcpu->arch.pio.port = port; 4638 vcpu->arch.pio.in = in; 4639 vcpu->arch.pio.count = count; 4640 vcpu->arch.pio.size = size; 4641 4642 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 4643 vcpu->arch.pio.count = 0; 4644 return 1; 4645 } 4646 4647 vcpu->run->exit_reason = KVM_EXIT_IO; 4648 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 4649 vcpu->run->io.size = size; 4650 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 4651 vcpu->run->io.count = count; 4652 vcpu->run->io.port = port; 4653 4654 return 0; 4655 } 4656 4657 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 4658 int size, unsigned short port, void *val, 4659 unsigned int count) 4660 { 4661 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4662 int ret; 4663 4664 if (vcpu->arch.pio.count) 4665 goto data_avail; 4666 4667 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 4668 if (ret) { 4669 data_avail: 4670 memcpy(val, vcpu->arch.pio_data, size * count); 4671 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); 4672 vcpu->arch.pio.count = 0; 4673 return 1; 4674 } 4675 4676 return 0; 4677 } 4678 4679 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 4680 int size, unsigned short port, 4681 const void *val, unsigned int count) 4682 { 4683 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4684 4685 memcpy(vcpu->arch.pio_data, val, size * count); 4686 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); 4687 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 4688 } 4689 4690 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 4691 { 4692 return kvm_x86_ops->get_segment_base(vcpu, seg); 4693 } 4694 4695 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 4696 { 4697 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 4698 } 4699 4700 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 4701 { 4702 if (!need_emulate_wbinvd(vcpu)) 4703 return X86EMUL_CONTINUE; 4704 4705 if (kvm_x86_ops->has_wbinvd_exit()) { 4706 int cpu = get_cpu(); 4707 4708 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4709 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 4710 wbinvd_ipi, NULL, 1); 4711 put_cpu(); 4712 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 4713 } else 4714 wbinvd(); 4715 return X86EMUL_CONTINUE; 4716 } 4717 4718 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 4719 { 4720 kvm_x86_ops->skip_emulated_instruction(vcpu); 4721 return kvm_emulate_wbinvd_noskip(vcpu); 4722 } 4723 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 4724 4725 4726 4727 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 4728 { 4729 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 4730 } 4731 4732 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 4733 unsigned long *dest) 4734 { 4735 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 4736 } 4737 4738 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 4739 unsigned long value) 4740 { 4741 4742 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 4743 } 4744 4745 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 4746 { 4747 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 4748 } 4749 4750 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 4751 { 4752 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4753 unsigned long value; 4754 4755 switch (cr) { 4756 case 0: 4757 value = kvm_read_cr0(vcpu); 4758 break; 4759 case 2: 4760 value = vcpu->arch.cr2; 4761 break; 4762 case 3: 4763 value = kvm_read_cr3(vcpu); 4764 break; 4765 case 4: 4766 value = kvm_read_cr4(vcpu); 4767 break; 4768 case 8: 4769 value = kvm_get_cr8(vcpu); 4770 break; 4771 default: 4772 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4773 return 0; 4774 } 4775 4776 return value; 4777 } 4778 4779 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 4780 { 4781 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4782 int res = 0; 4783 4784 switch (cr) { 4785 case 0: 4786 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 4787 break; 4788 case 2: 4789 vcpu->arch.cr2 = val; 4790 break; 4791 case 3: 4792 res = kvm_set_cr3(vcpu, val); 4793 break; 4794 case 4: 4795 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 4796 break; 4797 case 8: 4798 res = kvm_set_cr8(vcpu, val); 4799 break; 4800 default: 4801 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4802 res = -1; 4803 } 4804 4805 return res; 4806 } 4807 4808 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 4809 { 4810 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 4811 } 4812 4813 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4814 { 4815 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 4816 } 4817 4818 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4819 { 4820 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 4821 } 4822 4823 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4824 { 4825 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 4826 } 4827 4828 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4829 { 4830 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 4831 } 4832 4833 static unsigned long emulator_get_cached_segment_base( 4834 struct x86_emulate_ctxt *ctxt, int seg) 4835 { 4836 return get_segment_base(emul_to_vcpu(ctxt), seg); 4837 } 4838 4839 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 4840 struct desc_struct *desc, u32 *base3, 4841 int seg) 4842 { 4843 struct kvm_segment var; 4844 4845 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 4846 *selector = var.selector; 4847 4848 if (var.unusable) { 4849 memset(desc, 0, sizeof(*desc)); 4850 return false; 4851 } 4852 4853 if (var.g) 4854 var.limit >>= 12; 4855 set_desc_limit(desc, var.limit); 4856 set_desc_base(desc, (unsigned long)var.base); 4857 #ifdef CONFIG_X86_64 4858 if (base3) 4859 *base3 = var.base >> 32; 4860 #endif 4861 desc->type = var.type; 4862 desc->s = var.s; 4863 desc->dpl = var.dpl; 4864 desc->p = var.present; 4865 desc->avl = var.avl; 4866 desc->l = var.l; 4867 desc->d = var.db; 4868 desc->g = var.g; 4869 4870 return true; 4871 } 4872 4873 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 4874 struct desc_struct *desc, u32 base3, 4875 int seg) 4876 { 4877 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4878 struct kvm_segment var; 4879 4880 var.selector = selector; 4881 var.base = get_desc_base(desc); 4882 #ifdef CONFIG_X86_64 4883 var.base |= ((u64)base3) << 32; 4884 #endif 4885 var.limit = get_desc_limit(desc); 4886 if (desc->g) 4887 var.limit = (var.limit << 12) | 0xfff; 4888 var.type = desc->type; 4889 var.dpl = desc->dpl; 4890 var.db = desc->d; 4891 var.s = desc->s; 4892 var.l = desc->l; 4893 var.g = desc->g; 4894 var.avl = desc->avl; 4895 var.present = desc->p; 4896 var.unusable = !var.present; 4897 var.padding = 0; 4898 4899 kvm_set_segment(vcpu, &var, seg); 4900 return; 4901 } 4902 4903 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 4904 u32 msr_index, u64 *pdata) 4905 { 4906 struct msr_data msr; 4907 int r; 4908 4909 msr.index = msr_index; 4910 msr.host_initiated = false; 4911 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr); 4912 if (r) 4913 return r; 4914 4915 *pdata = msr.data; 4916 return 0; 4917 } 4918 4919 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 4920 u32 msr_index, u64 data) 4921 { 4922 struct msr_data msr; 4923 4924 msr.data = data; 4925 msr.index = msr_index; 4926 msr.host_initiated = false; 4927 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 4928 } 4929 4930 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) 4931 { 4932 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4933 4934 return vcpu->arch.smbase; 4935 } 4936 4937 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) 4938 { 4939 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4940 4941 vcpu->arch.smbase = smbase; 4942 } 4943 4944 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 4945 u32 pmc) 4946 { 4947 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc); 4948 } 4949 4950 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 4951 u32 pmc, u64 *pdata) 4952 { 4953 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 4954 } 4955 4956 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 4957 { 4958 emul_to_vcpu(ctxt)->arch.halt_request = 1; 4959 } 4960 4961 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) 4962 { 4963 preempt_disable(); 4964 kvm_load_guest_fpu(emul_to_vcpu(ctxt)); 4965 /* 4966 * CR0.TS may reference the host fpu state, not the guest fpu state, 4967 * so it may be clear at this point. 4968 */ 4969 clts(); 4970 } 4971 4972 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) 4973 { 4974 preempt_enable(); 4975 } 4976 4977 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 4978 struct x86_instruction_info *info, 4979 enum x86_intercept_stage stage) 4980 { 4981 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 4982 } 4983 4984 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 4985 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) 4986 { 4987 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); 4988 } 4989 4990 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 4991 { 4992 return kvm_register_read(emul_to_vcpu(ctxt), reg); 4993 } 4994 4995 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 4996 { 4997 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 4998 } 4999 5000 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 5001 { 5002 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked); 5003 } 5004 5005 static const struct x86_emulate_ops emulate_ops = { 5006 .read_gpr = emulator_read_gpr, 5007 .write_gpr = emulator_write_gpr, 5008 .read_std = kvm_read_guest_virt_system, 5009 .write_std = kvm_write_guest_virt_system, 5010 .read_phys = kvm_read_guest_phys_system, 5011 .fetch = kvm_fetch_guest_virt, 5012 .read_emulated = emulator_read_emulated, 5013 .write_emulated = emulator_write_emulated, 5014 .cmpxchg_emulated = emulator_cmpxchg_emulated, 5015 .invlpg = emulator_invlpg, 5016 .pio_in_emulated = emulator_pio_in_emulated, 5017 .pio_out_emulated = emulator_pio_out_emulated, 5018 .get_segment = emulator_get_segment, 5019 .set_segment = emulator_set_segment, 5020 .get_cached_segment_base = emulator_get_cached_segment_base, 5021 .get_gdt = emulator_get_gdt, 5022 .get_idt = emulator_get_idt, 5023 .set_gdt = emulator_set_gdt, 5024 .set_idt = emulator_set_idt, 5025 .get_cr = emulator_get_cr, 5026 .set_cr = emulator_set_cr, 5027 .cpl = emulator_get_cpl, 5028 .get_dr = emulator_get_dr, 5029 .set_dr = emulator_set_dr, 5030 .get_smbase = emulator_get_smbase, 5031 .set_smbase = emulator_set_smbase, 5032 .set_msr = emulator_set_msr, 5033 .get_msr = emulator_get_msr, 5034 .check_pmc = emulator_check_pmc, 5035 .read_pmc = emulator_read_pmc, 5036 .halt = emulator_halt, 5037 .wbinvd = emulator_wbinvd, 5038 .fix_hypercall = emulator_fix_hypercall, 5039 .get_fpu = emulator_get_fpu, 5040 .put_fpu = emulator_put_fpu, 5041 .intercept = emulator_intercept, 5042 .get_cpuid = emulator_get_cpuid, 5043 .set_nmi_mask = emulator_set_nmi_mask, 5044 }; 5045 5046 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 5047 { 5048 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu); 5049 /* 5050 * an sti; sti; sequence only disable interrupts for the first 5051 * instruction. So, if the last instruction, be it emulated or 5052 * not, left the system with the INT_STI flag enabled, it 5053 * means that the last instruction is an sti. We should not 5054 * leave the flag on in this case. The same goes for mov ss 5055 */ 5056 if (int_shadow & mask) 5057 mask = 0; 5058 if (unlikely(int_shadow || mask)) { 5059 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 5060 if (!mask) 5061 kvm_make_request(KVM_REQ_EVENT, vcpu); 5062 } 5063 } 5064 5065 static bool inject_emulated_exception(struct kvm_vcpu *vcpu) 5066 { 5067 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5068 if (ctxt->exception.vector == PF_VECTOR) 5069 return kvm_propagate_fault(vcpu, &ctxt->exception); 5070 5071 if (ctxt->exception.error_code_valid) 5072 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 5073 ctxt->exception.error_code); 5074 else 5075 kvm_queue_exception(vcpu, ctxt->exception.vector); 5076 return false; 5077 } 5078 5079 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 5080 { 5081 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5082 int cs_db, cs_l; 5083 5084 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 5085 5086 ctxt->eflags = kvm_get_rflags(vcpu); 5087 ctxt->eip = kvm_rip_read(vcpu); 5088 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 5089 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 5090 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 5091 cs_db ? X86EMUL_MODE_PROT32 : 5092 X86EMUL_MODE_PROT16; 5093 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); 5094 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); 5095 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); 5096 ctxt->emul_flags = vcpu->arch.hflags; 5097 5098 init_decode_cache(ctxt); 5099 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5100 } 5101 5102 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 5103 { 5104 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5105 int ret; 5106 5107 init_emulate_ctxt(vcpu); 5108 5109 ctxt->op_bytes = 2; 5110 ctxt->ad_bytes = 2; 5111 ctxt->_eip = ctxt->eip + inc_eip; 5112 ret = emulate_int_real(ctxt, irq); 5113 5114 if (ret != X86EMUL_CONTINUE) 5115 return EMULATE_FAIL; 5116 5117 ctxt->eip = ctxt->_eip; 5118 kvm_rip_write(vcpu, ctxt->eip); 5119 kvm_set_rflags(vcpu, ctxt->eflags); 5120 5121 if (irq == NMI_VECTOR) 5122 vcpu->arch.nmi_pending = 0; 5123 else 5124 vcpu->arch.interrupt.pending = false; 5125 5126 return EMULATE_DONE; 5127 } 5128 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 5129 5130 static int handle_emulation_failure(struct kvm_vcpu *vcpu) 5131 { 5132 int r = EMULATE_DONE; 5133 5134 ++vcpu->stat.insn_emulation_fail; 5135 trace_kvm_emulate_insn_failed(vcpu); 5136 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) { 5137 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5138 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 5139 vcpu->run->internal.ndata = 0; 5140 r = EMULATE_FAIL; 5141 } 5142 kvm_queue_exception(vcpu, UD_VECTOR); 5143 5144 return r; 5145 } 5146 5147 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 5148 bool write_fault_to_shadow_pgtable, 5149 int emulation_type) 5150 { 5151 gpa_t gpa = cr2; 5152 kvm_pfn_t pfn; 5153 5154 if (emulation_type & EMULTYPE_NO_REEXECUTE) 5155 return false; 5156 5157 if (!vcpu->arch.mmu.direct_map) { 5158 /* 5159 * Write permission should be allowed since only 5160 * write access need to be emulated. 5161 */ 5162 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5163 5164 /* 5165 * If the mapping is invalid in guest, let cpu retry 5166 * it to generate fault. 5167 */ 5168 if (gpa == UNMAPPED_GVA) 5169 return true; 5170 } 5171 5172 /* 5173 * Do not retry the unhandleable instruction if it faults on the 5174 * readonly host memory, otherwise it will goto a infinite loop: 5175 * retry instruction -> write #PF -> emulation fail -> retry 5176 * instruction -> ... 5177 */ 5178 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 5179 5180 /* 5181 * If the instruction failed on the error pfn, it can not be fixed, 5182 * report the error to userspace. 5183 */ 5184 if (is_error_noslot_pfn(pfn)) 5185 return false; 5186 5187 kvm_release_pfn_clean(pfn); 5188 5189 /* The instructions are well-emulated on direct mmu. */ 5190 if (vcpu->arch.mmu.direct_map) { 5191 unsigned int indirect_shadow_pages; 5192 5193 spin_lock(&vcpu->kvm->mmu_lock); 5194 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 5195 spin_unlock(&vcpu->kvm->mmu_lock); 5196 5197 if (indirect_shadow_pages) 5198 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5199 5200 return true; 5201 } 5202 5203 /* 5204 * if emulation was due to access to shadowed page table 5205 * and it failed try to unshadow page and re-enter the 5206 * guest to let CPU execute the instruction. 5207 */ 5208 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5209 5210 /* 5211 * If the access faults on its page table, it can not 5212 * be fixed by unprotecting shadow page and it should 5213 * be reported to userspace. 5214 */ 5215 return !write_fault_to_shadow_pgtable; 5216 } 5217 5218 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5219 unsigned long cr2, int emulation_type) 5220 { 5221 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5222 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5223 5224 last_retry_eip = vcpu->arch.last_retry_eip; 5225 last_retry_addr = vcpu->arch.last_retry_addr; 5226 5227 /* 5228 * If the emulation is caused by #PF and it is non-page_table 5229 * writing instruction, it means the VM-EXIT is caused by shadow 5230 * page protected, we can zap the shadow page and retry this 5231 * instruction directly. 5232 * 5233 * Note: if the guest uses a non-page-table modifying instruction 5234 * on the PDE that points to the instruction, then we will unmap 5235 * the instruction and go to an infinite loop. So, we cache the 5236 * last retried eip and the last fault address, if we meet the eip 5237 * and the address again, we can break out of the potential infinite 5238 * loop. 5239 */ 5240 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5241 5242 if (!(emulation_type & EMULTYPE_RETRY)) 5243 return false; 5244 5245 if (x86_page_table_writing_insn(ctxt)) 5246 return false; 5247 5248 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5249 return false; 5250 5251 vcpu->arch.last_retry_eip = ctxt->eip; 5252 vcpu->arch.last_retry_addr = cr2; 5253 5254 if (!vcpu->arch.mmu.direct_map) 5255 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5256 5257 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5258 5259 return true; 5260 } 5261 5262 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5263 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5264 5265 static void kvm_smm_changed(struct kvm_vcpu *vcpu) 5266 { 5267 if (!(vcpu->arch.hflags & HF_SMM_MASK)) { 5268 /* This is a good place to trace that we are exiting SMM. */ 5269 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false); 5270 5271 if (unlikely(vcpu->arch.smi_pending)) { 5272 kvm_make_request(KVM_REQ_SMI, vcpu); 5273 vcpu->arch.smi_pending = 0; 5274 } else { 5275 /* Process a latched INIT, if any. */ 5276 kvm_make_request(KVM_REQ_EVENT, vcpu); 5277 } 5278 } 5279 5280 kvm_mmu_reset_context(vcpu); 5281 } 5282 5283 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags) 5284 { 5285 unsigned changed = vcpu->arch.hflags ^ emul_flags; 5286 5287 vcpu->arch.hflags = emul_flags; 5288 5289 if (changed & HF_SMM_MASK) 5290 kvm_smm_changed(vcpu); 5291 } 5292 5293 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5294 unsigned long *db) 5295 { 5296 u32 dr6 = 0; 5297 int i; 5298 u32 enable, rwlen; 5299 5300 enable = dr7; 5301 rwlen = dr7 >> 16; 5302 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5303 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5304 dr6 |= (1 << i); 5305 return dr6; 5306 } 5307 5308 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r) 5309 { 5310 struct kvm_run *kvm_run = vcpu->run; 5311 5312 /* 5313 * rflags is the old, "raw" value of the flags. The new value has 5314 * not been saved yet. 5315 * 5316 * This is correct even for TF set by the guest, because "the 5317 * processor will not generate this exception after the instruction 5318 * that sets the TF flag". 5319 */ 5320 if (unlikely(rflags & X86_EFLAGS_TF)) { 5321 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5322 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | 5323 DR6_RTM; 5324 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5325 kvm_run->debug.arch.exception = DB_VECTOR; 5326 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5327 *r = EMULATE_USER_EXIT; 5328 } else { 5329 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; 5330 /* 5331 * "Certain debug exceptions may clear bit 0-3. The 5332 * remaining contents of the DR6 register are never 5333 * cleared by the processor". 5334 */ 5335 vcpu->arch.dr6 &= ~15; 5336 vcpu->arch.dr6 |= DR6_BS | DR6_RTM; 5337 kvm_queue_exception(vcpu, DB_VECTOR); 5338 } 5339 } 5340 } 5341 5342 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5343 { 5344 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5345 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5346 struct kvm_run *kvm_run = vcpu->run; 5347 unsigned long eip = kvm_get_linear_rip(vcpu); 5348 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5349 vcpu->arch.guest_debug_dr7, 5350 vcpu->arch.eff_db); 5351 5352 if (dr6 != 0) { 5353 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM; 5354 kvm_run->debug.arch.pc = eip; 5355 kvm_run->debug.arch.exception = DB_VECTOR; 5356 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5357 *r = EMULATE_USER_EXIT; 5358 return true; 5359 } 5360 } 5361 5362 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 5363 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) { 5364 unsigned long eip = kvm_get_linear_rip(vcpu); 5365 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5366 vcpu->arch.dr7, 5367 vcpu->arch.db); 5368 5369 if (dr6 != 0) { 5370 vcpu->arch.dr6 &= ~15; 5371 vcpu->arch.dr6 |= dr6 | DR6_RTM; 5372 kvm_queue_exception(vcpu, DB_VECTOR); 5373 *r = EMULATE_DONE; 5374 return true; 5375 } 5376 } 5377 5378 return false; 5379 } 5380 5381 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 5382 unsigned long cr2, 5383 int emulation_type, 5384 void *insn, 5385 int insn_len) 5386 { 5387 int r; 5388 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5389 bool writeback = true; 5390 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 5391 5392 /* 5393 * Clear write_fault_to_shadow_pgtable here to ensure it is 5394 * never reused. 5395 */ 5396 vcpu->arch.write_fault_to_shadow_pgtable = false; 5397 kvm_clear_exception_queue(vcpu); 5398 5399 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 5400 init_emulate_ctxt(vcpu); 5401 5402 /* 5403 * We will reenter on the same instruction since 5404 * we do not set complete_userspace_io. This does not 5405 * handle watchpoints yet, those would be handled in 5406 * the emulate_ops. 5407 */ 5408 if (kvm_vcpu_check_breakpoint(vcpu, &r)) 5409 return r; 5410 5411 ctxt->interruptibility = 0; 5412 ctxt->have_exception = false; 5413 ctxt->exception.vector = -1; 5414 ctxt->perm_ok = false; 5415 5416 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 5417 5418 r = x86_decode_insn(ctxt, insn, insn_len); 5419 5420 trace_kvm_emulate_insn_start(vcpu); 5421 ++vcpu->stat.insn_emulation; 5422 if (r != EMULATION_OK) { 5423 if (emulation_type & EMULTYPE_TRAP_UD) 5424 return EMULATE_FAIL; 5425 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5426 emulation_type)) 5427 return EMULATE_DONE; 5428 if (emulation_type & EMULTYPE_SKIP) 5429 return EMULATE_FAIL; 5430 return handle_emulation_failure(vcpu); 5431 } 5432 } 5433 5434 if (emulation_type & EMULTYPE_SKIP) { 5435 kvm_rip_write(vcpu, ctxt->_eip); 5436 if (ctxt->eflags & X86_EFLAGS_RF) 5437 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 5438 return EMULATE_DONE; 5439 } 5440 5441 if (retry_instruction(ctxt, cr2, emulation_type)) 5442 return EMULATE_DONE; 5443 5444 /* this is needed for vmware backdoor interface to work since it 5445 changes registers values during IO operation */ 5446 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 5447 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5448 emulator_invalidate_register_cache(ctxt); 5449 } 5450 5451 restart: 5452 r = x86_emulate_insn(ctxt); 5453 5454 if (r == EMULATION_INTERCEPTED) 5455 return EMULATE_DONE; 5456 5457 if (r == EMULATION_FAILED) { 5458 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5459 emulation_type)) 5460 return EMULATE_DONE; 5461 5462 return handle_emulation_failure(vcpu); 5463 } 5464 5465 if (ctxt->have_exception) { 5466 r = EMULATE_DONE; 5467 if (inject_emulated_exception(vcpu)) 5468 return r; 5469 } else if (vcpu->arch.pio.count) { 5470 if (!vcpu->arch.pio.in) { 5471 /* FIXME: return into emulator if single-stepping. */ 5472 vcpu->arch.pio.count = 0; 5473 } else { 5474 writeback = false; 5475 vcpu->arch.complete_userspace_io = complete_emulated_pio; 5476 } 5477 r = EMULATE_USER_EXIT; 5478 } else if (vcpu->mmio_needed) { 5479 if (!vcpu->mmio_is_write) 5480 writeback = false; 5481 r = EMULATE_USER_EXIT; 5482 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 5483 } else if (r == EMULATION_RESTART) 5484 goto restart; 5485 else 5486 r = EMULATE_DONE; 5487 5488 if (writeback) { 5489 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5490 toggle_interruptibility(vcpu, ctxt->interruptibility); 5491 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 5492 if (vcpu->arch.hflags != ctxt->emul_flags) 5493 kvm_set_hflags(vcpu, ctxt->emul_flags); 5494 kvm_rip_write(vcpu, ctxt->eip); 5495 if (r == EMULATE_DONE) 5496 kvm_vcpu_check_singlestep(vcpu, rflags, &r); 5497 if (!ctxt->have_exception || 5498 exception_type(ctxt->exception.vector) == EXCPT_TRAP) 5499 __kvm_set_rflags(vcpu, ctxt->eflags); 5500 5501 /* 5502 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 5503 * do nothing, and it will be requested again as soon as 5504 * the shadow expires. But we still need to check here, 5505 * because POPF has no interrupt shadow. 5506 */ 5507 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 5508 kvm_make_request(KVM_REQ_EVENT, vcpu); 5509 } else 5510 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 5511 5512 return r; 5513 } 5514 EXPORT_SYMBOL_GPL(x86_emulate_instruction); 5515 5516 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) 5517 { 5518 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 5519 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 5520 size, port, &val, 1); 5521 /* do not return to emulator after return from userspace */ 5522 vcpu->arch.pio.count = 0; 5523 return ret; 5524 } 5525 EXPORT_SYMBOL_GPL(kvm_fast_pio_out); 5526 5527 static void tsc_bad(void *info) 5528 { 5529 __this_cpu_write(cpu_tsc_khz, 0); 5530 } 5531 5532 static void tsc_khz_changed(void *data) 5533 { 5534 struct cpufreq_freqs *freq = data; 5535 unsigned long khz = 0; 5536 5537 if (data) 5538 khz = freq->new; 5539 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5540 khz = cpufreq_quick_get(raw_smp_processor_id()); 5541 if (!khz) 5542 khz = tsc_khz; 5543 __this_cpu_write(cpu_tsc_khz, khz); 5544 } 5545 5546 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 5547 void *data) 5548 { 5549 struct cpufreq_freqs *freq = data; 5550 struct kvm *kvm; 5551 struct kvm_vcpu *vcpu; 5552 int i, send_ipi = 0; 5553 5554 /* 5555 * We allow guests to temporarily run on slowing clocks, 5556 * provided we notify them after, or to run on accelerating 5557 * clocks, provided we notify them before. Thus time never 5558 * goes backwards. 5559 * 5560 * However, we have a problem. We can't atomically update 5561 * the frequency of a given CPU from this function; it is 5562 * merely a notifier, which can be called from any CPU. 5563 * Changing the TSC frequency at arbitrary points in time 5564 * requires a recomputation of local variables related to 5565 * the TSC for each VCPU. We must flag these local variables 5566 * to be updated and be sure the update takes place with the 5567 * new frequency before any guests proceed. 5568 * 5569 * Unfortunately, the combination of hotplug CPU and frequency 5570 * change creates an intractable locking scenario; the order 5571 * of when these callouts happen is undefined with respect to 5572 * CPU hotplug, and they can race with each other. As such, 5573 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 5574 * undefined; you can actually have a CPU frequency change take 5575 * place in between the computation of X and the setting of the 5576 * variable. To protect against this problem, all updates of 5577 * the per_cpu tsc_khz variable are done in an interrupt 5578 * protected IPI, and all callers wishing to update the value 5579 * must wait for a synchronous IPI to complete (which is trivial 5580 * if the caller is on the CPU already). This establishes the 5581 * necessary total order on variable updates. 5582 * 5583 * Note that because a guest time update may take place 5584 * anytime after the setting of the VCPU's request bit, the 5585 * correct TSC value must be set before the request. However, 5586 * to ensure the update actually makes it to any guest which 5587 * starts running in hardware virtualization between the set 5588 * and the acquisition of the spinlock, we must also ping the 5589 * CPU after setting the request bit. 5590 * 5591 */ 5592 5593 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 5594 return 0; 5595 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 5596 return 0; 5597 5598 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5599 5600 spin_lock(&kvm_lock); 5601 list_for_each_entry(kvm, &vm_list, vm_list) { 5602 kvm_for_each_vcpu(i, vcpu, kvm) { 5603 if (vcpu->cpu != freq->cpu) 5604 continue; 5605 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5606 if (vcpu->cpu != smp_processor_id()) 5607 send_ipi = 1; 5608 } 5609 } 5610 spin_unlock(&kvm_lock); 5611 5612 if (freq->old < freq->new && send_ipi) { 5613 /* 5614 * We upscale the frequency. Must make the guest 5615 * doesn't see old kvmclock values while running with 5616 * the new frequency, otherwise we risk the guest sees 5617 * time go backwards. 5618 * 5619 * In case we update the frequency for another cpu 5620 * (which might be in guest context) send an interrupt 5621 * to kick the cpu out of guest context. Next time 5622 * guest context is entered kvmclock will be updated, 5623 * so the guest will not see stale values. 5624 */ 5625 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5626 } 5627 return 0; 5628 } 5629 5630 static struct notifier_block kvmclock_cpufreq_notifier_block = { 5631 .notifier_call = kvmclock_cpufreq_notifier 5632 }; 5633 5634 static int kvmclock_cpu_notifier(struct notifier_block *nfb, 5635 unsigned long action, void *hcpu) 5636 { 5637 unsigned int cpu = (unsigned long)hcpu; 5638 5639 switch (action) { 5640 case CPU_ONLINE: 5641 case CPU_DOWN_FAILED: 5642 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5643 break; 5644 case CPU_DOWN_PREPARE: 5645 smp_call_function_single(cpu, tsc_bad, NULL, 1); 5646 break; 5647 } 5648 return NOTIFY_OK; 5649 } 5650 5651 static struct notifier_block kvmclock_cpu_notifier_block = { 5652 .notifier_call = kvmclock_cpu_notifier, 5653 .priority = -INT_MAX 5654 }; 5655 5656 static void kvm_timer_init(void) 5657 { 5658 int cpu; 5659 5660 max_tsc_khz = tsc_khz; 5661 5662 cpu_notifier_register_begin(); 5663 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 5664 #ifdef CONFIG_CPU_FREQ 5665 struct cpufreq_policy policy; 5666 memset(&policy, 0, sizeof(policy)); 5667 cpu = get_cpu(); 5668 cpufreq_get_policy(&policy, cpu); 5669 if (policy.cpuinfo.max_freq) 5670 max_tsc_khz = policy.cpuinfo.max_freq; 5671 put_cpu(); 5672 #endif 5673 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 5674 CPUFREQ_TRANSITION_NOTIFIER); 5675 } 5676 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 5677 for_each_online_cpu(cpu) 5678 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5679 5680 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5681 cpu_notifier_register_done(); 5682 5683 } 5684 5685 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 5686 5687 int kvm_is_in_guest(void) 5688 { 5689 return __this_cpu_read(current_vcpu) != NULL; 5690 } 5691 5692 static int kvm_is_user_mode(void) 5693 { 5694 int user_mode = 3; 5695 5696 if (__this_cpu_read(current_vcpu)) 5697 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 5698 5699 return user_mode != 0; 5700 } 5701 5702 static unsigned long kvm_get_guest_ip(void) 5703 { 5704 unsigned long ip = 0; 5705 5706 if (__this_cpu_read(current_vcpu)) 5707 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 5708 5709 return ip; 5710 } 5711 5712 static struct perf_guest_info_callbacks kvm_guest_cbs = { 5713 .is_in_guest = kvm_is_in_guest, 5714 .is_user_mode = kvm_is_user_mode, 5715 .get_guest_ip = kvm_get_guest_ip, 5716 }; 5717 5718 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) 5719 { 5720 __this_cpu_write(current_vcpu, vcpu); 5721 } 5722 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); 5723 5724 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) 5725 { 5726 __this_cpu_write(current_vcpu, NULL); 5727 } 5728 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); 5729 5730 static void kvm_set_mmio_spte_mask(void) 5731 { 5732 u64 mask; 5733 int maxphyaddr = boot_cpu_data.x86_phys_bits; 5734 5735 /* 5736 * Set the reserved bits and the present bit of an paging-structure 5737 * entry to generate page fault with PFER.RSV = 1. 5738 */ 5739 /* Mask the reserved physical address bits. */ 5740 mask = rsvd_bits(maxphyaddr, 51); 5741 5742 /* Bit 62 is always reserved for 32bit host. */ 5743 mask |= 0x3ull << 62; 5744 5745 /* Set the present bit. */ 5746 mask |= 1ull; 5747 5748 #ifdef CONFIG_X86_64 5749 /* 5750 * If reserved bit is not supported, clear the present bit to disable 5751 * mmio page fault. 5752 */ 5753 if (maxphyaddr == 52) 5754 mask &= ~1ull; 5755 #endif 5756 5757 kvm_mmu_set_mmio_spte_mask(mask); 5758 } 5759 5760 #ifdef CONFIG_X86_64 5761 static void pvclock_gtod_update_fn(struct work_struct *work) 5762 { 5763 struct kvm *kvm; 5764 5765 struct kvm_vcpu *vcpu; 5766 int i; 5767 5768 spin_lock(&kvm_lock); 5769 list_for_each_entry(kvm, &vm_list, vm_list) 5770 kvm_for_each_vcpu(i, vcpu, kvm) 5771 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 5772 atomic_set(&kvm_guest_has_master_clock, 0); 5773 spin_unlock(&kvm_lock); 5774 } 5775 5776 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 5777 5778 /* 5779 * Notification about pvclock gtod data update. 5780 */ 5781 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 5782 void *priv) 5783 { 5784 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 5785 struct timekeeper *tk = priv; 5786 5787 update_pvclock_gtod(tk); 5788 5789 /* disable master clock if host does not trust, or does not 5790 * use, TSC clocksource 5791 */ 5792 if (gtod->clock.vclock_mode != VCLOCK_TSC && 5793 atomic_read(&kvm_guest_has_master_clock) != 0) 5794 queue_work(system_long_wq, &pvclock_gtod_work); 5795 5796 return 0; 5797 } 5798 5799 static struct notifier_block pvclock_gtod_notifier = { 5800 .notifier_call = pvclock_gtod_notify, 5801 }; 5802 #endif 5803 5804 int kvm_arch_init(void *opaque) 5805 { 5806 int r; 5807 struct kvm_x86_ops *ops = opaque; 5808 5809 if (kvm_x86_ops) { 5810 printk(KERN_ERR "kvm: already loaded the other module\n"); 5811 r = -EEXIST; 5812 goto out; 5813 } 5814 5815 if (!ops->cpu_has_kvm_support()) { 5816 printk(KERN_ERR "kvm: no hardware support\n"); 5817 r = -EOPNOTSUPP; 5818 goto out; 5819 } 5820 if (ops->disabled_by_bios()) { 5821 printk(KERN_ERR "kvm: disabled by bios\n"); 5822 r = -EOPNOTSUPP; 5823 goto out; 5824 } 5825 5826 r = -ENOMEM; 5827 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 5828 if (!shared_msrs) { 5829 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 5830 goto out; 5831 } 5832 5833 r = kvm_mmu_module_init(); 5834 if (r) 5835 goto out_free_percpu; 5836 5837 kvm_set_mmio_spte_mask(); 5838 5839 kvm_x86_ops = ops; 5840 5841 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 5842 PT_DIRTY_MASK, PT64_NX_MASK, 0); 5843 5844 kvm_timer_init(); 5845 5846 perf_register_guest_info_callbacks(&kvm_guest_cbs); 5847 5848 if (cpu_has_xsave) 5849 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 5850 5851 kvm_lapic_init(); 5852 #ifdef CONFIG_X86_64 5853 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 5854 #endif 5855 5856 return 0; 5857 5858 out_free_percpu: 5859 free_percpu(shared_msrs); 5860 out: 5861 return r; 5862 } 5863 5864 void kvm_arch_exit(void) 5865 { 5866 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 5867 5868 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5869 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 5870 CPUFREQ_TRANSITION_NOTIFIER); 5871 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5872 #ifdef CONFIG_X86_64 5873 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 5874 #endif 5875 kvm_x86_ops = NULL; 5876 kvm_mmu_module_exit(); 5877 free_percpu(shared_msrs); 5878 } 5879 5880 int kvm_vcpu_halt(struct kvm_vcpu *vcpu) 5881 { 5882 ++vcpu->stat.halt_exits; 5883 if (lapic_in_kernel(vcpu)) { 5884 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 5885 return 1; 5886 } else { 5887 vcpu->run->exit_reason = KVM_EXIT_HLT; 5888 return 0; 5889 } 5890 } 5891 EXPORT_SYMBOL_GPL(kvm_vcpu_halt); 5892 5893 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 5894 { 5895 kvm_x86_ops->skip_emulated_instruction(vcpu); 5896 return kvm_vcpu_halt(vcpu); 5897 } 5898 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 5899 5900 /* 5901 * kvm_pv_kick_cpu_op: Kick a vcpu. 5902 * 5903 * @apicid - apicid of vcpu to be kicked. 5904 */ 5905 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 5906 { 5907 struct kvm_lapic_irq lapic_irq; 5908 5909 lapic_irq.shorthand = 0; 5910 lapic_irq.dest_mode = 0; 5911 lapic_irq.dest_id = apicid; 5912 lapic_irq.msi_redir_hint = false; 5913 5914 lapic_irq.delivery_mode = APIC_DM_REMRD; 5915 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 5916 } 5917 5918 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) 5919 { 5920 vcpu->arch.apicv_active = false; 5921 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); 5922 } 5923 5924 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 5925 { 5926 unsigned long nr, a0, a1, a2, a3, ret; 5927 int op_64_bit, r = 1; 5928 5929 kvm_x86_ops->skip_emulated_instruction(vcpu); 5930 5931 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 5932 return kvm_hv_hypercall(vcpu); 5933 5934 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 5935 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 5936 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 5937 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 5938 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 5939 5940 trace_kvm_hypercall(nr, a0, a1, a2, a3); 5941 5942 op_64_bit = is_64_bit_mode(vcpu); 5943 if (!op_64_bit) { 5944 nr &= 0xFFFFFFFF; 5945 a0 &= 0xFFFFFFFF; 5946 a1 &= 0xFFFFFFFF; 5947 a2 &= 0xFFFFFFFF; 5948 a3 &= 0xFFFFFFFF; 5949 } 5950 5951 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 5952 ret = -KVM_EPERM; 5953 goto out; 5954 } 5955 5956 switch (nr) { 5957 case KVM_HC_VAPIC_POLL_IRQ: 5958 ret = 0; 5959 break; 5960 case KVM_HC_KICK_CPU: 5961 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 5962 ret = 0; 5963 break; 5964 default: 5965 ret = -KVM_ENOSYS; 5966 break; 5967 } 5968 out: 5969 if (!op_64_bit) 5970 ret = (u32)ret; 5971 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 5972 ++vcpu->stat.hypercalls; 5973 return r; 5974 } 5975 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 5976 5977 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 5978 { 5979 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5980 char instruction[3]; 5981 unsigned long rip = kvm_rip_read(vcpu); 5982 5983 kvm_x86_ops->patch_hypercall(vcpu, instruction); 5984 5985 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); 5986 } 5987 5988 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 5989 { 5990 return vcpu->run->request_interrupt_window && 5991 likely(!pic_in_kernel(vcpu->kvm)); 5992 } 5993 5994 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 5995 { 5996 struct kvm_run *kvm_run = vcpu->run; 5997 5998 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 5999 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0; 6000 kvm_run->cr8 = kvm_get_cr8(vcpu); 6001 kvm_run->apic_base = kvm_get_apic_base(vcpu); 6002 kvm_run->ready_for_interrupt_injection = 6003 pic_in_kernel(vcpu->kvm) || 6004 kvm_vcpu_ready_for_interrupt_injection(vcpu); 6005 } 6006 6007 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 6008 { 6009 int max_irr, tpr; 6010 6011 if (!kvm_x86_ops->update_cr8_intercept) 6012 return; 6013 6014 if (!vcpu->arch.apic) 6015 return; 6016 6017 if (vcpu->arch.apicv_active) 6018 return; 6019 6020 if (!vcpu->arch.apic->vapic_addr) 6021 max_irr = kvm_lapic_find_highest_irr(vcpu); 6022 else 6023 max_irr = -1; 6024 6025 if (max_irr != -1) 6026 max_irr >>= 4; 6027 6028 tpr = kvm_lapic_get_cr8(vcpu); 6029 6030 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 6031 } 6032 6033 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 6034 { 6035 int r; 6036 6037 /* try to reinject previous events if any */ 6038 if (vcpu->arch.exception.pending) { 6039 trace_kvm_inj_exception(vcpu->arch.exception.nr, 6040 vcpu->arch.exception.has_error_code, 6041 vcpu->arch.exception.error_code); 6042 6043 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) 6044 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 6045 X86_EFLAGS_RF); 6046 6047 if (vcpu->arch.exception.nr == DB_VECTOR && 6048 (vcpu->arch.dr7 & DR7_GD)) { 6049 vcpu->arch.dr7 &= ~DR7_GD; 6050 kvm_update_dr7(vcpu); 6051 } 6052 6053 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, 6054 vcpu->arch.exception.has_error_code, 6055 vcpu->arch.exception.error_code, 6056 vcpu->arch.exception.reinject); 6057 return 0; 6058 } 6059 6060 if (vcpu->arch.nmi_injected) { 6061 kvm_x86_ops->set_nmi(vcpu); 6062 return 0; 6063 } 6064 6065 if (vcpu->arch.interrupt.pending) { 6066 kvm_x86_ops->set_irq(vcpu); 6067 return 0; 6068 } 6069 6070 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6071 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6072 if (r != 0) 6073 return r; 6074 } 6075 6076 /* try to inject new event if pending */ 6077 if (vcpu->arch.nmi_pending) { 6078 if (kvm_x86_ops->nmi_allowed(vcpu)) { 6079 --vcpu->arch.nmi_pending; 6080 vcpu->arch.nmi_injected = true; 6081 kvm_x86_ops->set_nmi(vcpu); 6082 } 6083 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 6084 /* 6085 * Because interrupts can be injected asynchronously, we are 6086 * calling check_nested_events again here to avoid a race condition. 6087 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this 6088 * proposal and current concerns. Perhaps we should be setting 6089 * KVM_REQ_EVENT only on certain events and not unconditionally? 6090 */ 6091 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 6092 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 6093 if (r != 0) 6094 return r; 6095 } 6096 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 6097 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 6098 false); 6099 kvm_x86_ops->set_irq(vcpu); 6100 } 6101 } 6102 return 0; 6103 } 6104 6105 static void process_nmi(struct kvm_vcpu *vcpu) 6106 { 6107 unsigned limit = 2; 6108 6109 /* 6110 * x86 is limited to one NMI running, and one NMI pending after it. 6111 * If an NMI is already in progress, limit further NMIs to just one. 6112 * Otherwise, allow two (and we'll inject the first one immediately). 6113 */ 6114 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 6115 limit = 1; 6116 6117 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 6118 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 6119 kvm_make_request(KVM_REQ_EVENT, vcpu); 6120 } 6121 6122 #define put_smstate(type, buf, offset, val) \ 6123 *(type *)((buf) + (offset) - 0x7e00) = val 6124 6125 static u32 process_smi_get_segment_flags(struct kvm_segment *seg) 6126 { 6127 u32 flags = 0; 6128 flags |= seg->g << 23; 6129 flags |= seg->db << 22; 6130 flags |= seg->l << 21; 6131 flags |= seg->avl << 20; 6132 flags |= seg->present << 15; 6133 flags |= seg->dpl << 13; 6134 flags |= seg->s << 12; 6135 flags |= seg->type << 8; 6136 return flags; 6137 } 6138 6139 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) 6140 { 6141 struct kvm_segment seg; 6142 int offset; 6143 6144 kvm_get_segment(vcpu, &seg, n); 6145 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); 6146 6147 if (n < 3) 6148 offset = 0x7f84 + n * 12; 6149 else 6150 offset = 0x7f2c + (n - 3) * 12; 6151 6152 put_smstate(u32, buf, offset + 8, seg.base); 6153 put_smstate(u32, buf, offset + 4, seg.limit); 6154 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg)); 6155 } 6156 6157 #ifdef CONFIG_X86_64 6158 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) 6159 { 6160 struct kvm_segment seg; 6161 int offset; 6162 u16 flags; 6163 6164 kvm_get_segment(vcpu, &seg, n); 6165 offset = 0x7e00 + n * 16; 6166 6167 flags = process_smi_get_segment_flags(&seg) >> 8; 6168 put_smstate(u16, buf, offset, seg.selector); 6169 put_smstate(u16, buf, offset + 2, flags); 6170 put_smstate(u32, buf, offset + 4, seg.limit); 6171 put_smstate(u64, buf, offset + 8, seg.base); 6172 } 6173 #endif 6174 6175 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf) 6176 { 6177 struct desc_ptr dt; 6178 struct kvm_segment seg; 6179 unsigned long val; 6180 int i; 6181 6182 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); 6183 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); 6184 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); 6185 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); 6186 6187 for (i = 0; i < 8; i++) 6188 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i)); 6189 6190 kvm_get_dr(vcpu, 6, &val); 6191 put_smstate(u32, buf, 0x7fcc, (u32)val); 6192 kvm_get_dr(vcpu, 7, &val); 6193 put_smstate(u32, buf, 0x7fc8, (u32)val); 6194 6195 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6196 put_smstate(u32, buf, 0x7fc4, seg.selector); 6197 put_smstate(u32, buf, 0x7f64, seg.base); 6198 put_smstate(u32, buf, 0x7f60, seg.limit); 6199 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg)); 6200 6201 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6202 put_smstate(u32, buf, 0x7fc0, seg.selector); 6203 put_smstate(u32, buf, 0x7f80, seg.base); 6204 put_smstate(u32, buf, 0x7f7c, seg.limit); 6205 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg)); 6206 6207 kvm_x86_ops->get_gdt(vcpu, &dt); 6208 put_smstate(u32, buf, 0x7f74, dt.address); 6209 put_smstate(u32, buf, 0x7f70, dt.size); 6210 6211 kvm_x86_ops->get_idt(vcpu, &dt); 6212 put_smstate(u32, buf, 0x7f58, dt.address); 6213 put_smstate(u32, buf, 0x7f54, dt.size); 6214 6215 for (i = 0; i < 6; i++) 6216 process_smi_save_seg_32(vcpu, buf, i); 6217 6218 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); 6219 6220 /* revision id */ 6221 put_smstate(u32, buf, 0x7efc, 0x00020000); 6222 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); 6223 } 6224 6225 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf) 6226 { 6227 #ifdef CONFIG_X86_64 6228 struct desc_ptr dt; 6229 struct kvm_segment seg; 6230 unsigned long val; 6231 int i; 6232 6233 for (i = 0; i < 16; i++) 6234 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i)); 6235 6236 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); 6237 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); 6238 6239 kvm_get_dr(vcpu, 6, &val); 6240 put_smstate(u64, buf, 0x7f68, val); 6241 kvm_get_dr(vcpu, 7, &val); 6242 put_smstate(u64, buf, 0x7f60, val); 6243 6244 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); 6245 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); 6246 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); 6247 6248 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); 6249 6250 /* revision id */ 6251 put_smstate(u32, buf, 0x7efc, 0x00020064); 6252 6253 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); 6254 6255 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); 6256 put_smstate(u16, buf, 0x7e90, seg.selector); 6257 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8); 6258 put_smstate(u32, buf, 0x7e94, seg.limit); 6259 put_smstate(u64, buf, 0x7e98, seg.base); 6260 6261 kvm_x86_ops->get_idt(vcpu, &dt); 6262 put_smstate(u32, buf, 0x7e84, dt.size); 6263 put_smstate(u64, buf, 0x7e88, dt.address); 6264 6265 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); 6266 put_smstate(u16, buf, 0x7e70, seg.selector); 6267 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8); 6268 put_smstate(u32, buf, 0x7e74, seg.limit); 6269 put_smstate(u64, buf, 0x7e78, seg.base); 6270 6271 kvm_x86_ops->get_gdt(vcpu, &dt); 6272 put_smstate(u32, buf, 0x7e64, dt.size); 6273 put_smstate(u64, buf, 0x7e68, dt.address); 6274 6275 for (i = 0; i < 6; i++) 6276 process_smi_save_seg_64(vcpu, buf, i); 6277 #else 6278 WARN_ON_ONCE(1); 6279 #endif 6280 } 6281 6282 static void process_smi(struct kvm_vcpu *vcpu) 6283 { 6284 struct kvm_segment cs, ds; 6285 struct desc_ptr dt; 6286 char buf[512]; 6287 u32 cr0; 6288 6289 if (is_smm(vcpu)) { 6290 vcpu->arch.smi_pending = true; 6291 return; 6292 } 6293 6294 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true); 6295 vcpu->arch.hflags |= HF_SMM_MASK; 6296 memset(buf, 0, 512); 6297 if (guest_cpuid_has_longmode(vcpu)) 6298 process_smi_save_state_64(vcpu, buf); 6299 else 6300 process_smi_save_state_32(vcpu, buf); 6301 6302 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); 6303 6304 if (kvm_x86_ops->get_nmi_mask(vcpu)) 6305 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 6306 else 6307 kvm_x86_ops->set_nmi_mask(vcpu, true); 6308 6309 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 6310 kvm_rip_write(vcpu, 0x8000); 6311 6312 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); 6313 kvm_x86_ops->set_cr0(vcpu, cr0); 6314 vcpu->arch.cr0 = cr0; 6315 6316 kvm_x86_ops->set_cr4(vcpu, 0); 6317 6318 /* Undocumented: IDT limit is set to zero on entry to SMM. */ 6319 dt.address = dt.size = 0; 6320 kvm_x86_ops->set_idt(vcpu, &dt); 6321 6322 __kvm_set_dr(vcpu, 7, DR7_FIXED_1); 6323 6324 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; 6325 cs.base = vcpu->arch.smbase; 6326 6327 ds.selector = 0; 6328 ds.base = 0; 6329 6330 cs.limit = ds.limit = 0xffffffff; 6331 cs.type = ds.type = 0x3; 6332 cs.dpl = ds.dpl = 0; 6333 cs.db = ds.db = 0; 6334 cs.s = ds.s = 1; 6335 cs.l = ds.l = 0; 6336 cs.g = ds.g = 1; 6337 cs.avl = ds.avl = 0; 6338 cs.present = ds.present = 1; 6339 cs.unusable = ds.unusable = 0; 6340 cs.padding = ds.padding = 0; 6341 6342 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 6343 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); 6344 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); 6345 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); 6346 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); 6347 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); 6348 6349 if (guest_cpuid_has_longmode(vcpu)) 6350 kvm_x86_ops->set_efer(vcpu, 0); 6351 6352 kvm_update_cpuid(vcpu); 6353 kvm_mmu_reset_context(vcpu); 6354 } 6355 6356 void kvm_make_scan_ioapic_request(struct kvm *kvm) 6357 { 6358 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 6359 } 6360 6361 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 6362 { 6363 u64 eoi_exit_bitmap[4]; 6364 6365 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 6366 return; 6367 6368 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 6369 6370 if (irqchip_split(vcpu->kvm)) 6371 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 6372 else { 6373 if (vcpu->arch.apicv_active) 6374 kvm_x86_ops->sync_pir_to_irr(vcpu); 6375 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 6376 } 6377 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors, 6378 vcpu_to_synic(vcpu)->vec_bitmap, 256); 6379 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 6380 } 6381 6382 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu) 6383 { 6384 ++vcpu->stat.tlb_flush; 6385 kvm_x86_ops->tlb_flush(vcpu); 6386 } 6387 6388 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 6389 { 6390 struct page *page = NULL; 6391 6392 if (!lapic_in_kernel(vcpu)) 6393 return; 6394 6395 if (!kvm_x86_ops->set_apic_access_page_addr) 6396 return; 6397 6398 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 6399 if (is_error_page(page)) 6400 return; 6401 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page)); 6402 6403 /* 6404 * Do not pin apic access page in memory, the MMU notifier 6405 * will call us again if it is migrated or swapped out. 6406 */ 6407 put_page(page); 6408 } 6409 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page); 6410 6411 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, 6412 unsigned long address) 6413 { 6414 /* 6415 * The physical address of apic access page is stored in the VMCS. 6416 * Update it when it becomes invalid. 6417 */ 6418 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT)) 6419 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); 6420 } 6421 6422 /* 6423 * Returns 1 to let vcpu_run() continue the guest execution loop without 6424 * exiting to the userspace. Otherwise, the value will be returned to the 6425 * userspace. 6426 */ 6427 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 6428 { 6429 int r; 6430 bool req_int_win = 6431 dm_request_for_irq_injection(vcpu) && 6432 kvm_cpu_accept_dm_intr(vcpu); 6433 6434 bool req_immediate_exit = false; 6435 6436 if (vcpu->requests) { 6437 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 6438 kvm_mmu_unload(vcpu); 6439 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 6440 __kvm_migrate_timers(vcpu); 6441 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 6442 kvm_gen_update_masterclock(vcpu->kvm); 6443 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 6444 kvm_gen_kvmclock_update(vcpu); 6445 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 6446 r = kvm_guest_time_update(vcpu); 6447 if (unlikely(r)) 6448 goto out; 6449 } 6450 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 6451 kvm_mmu_sync_roots(vcpu); 6452 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 6453 kvm_vcpu_flush_tlb(vcpu); 6454 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 6455 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 6456 r = 0; 6457 goto out; 6458 } 6459 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 6460 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 6461 r = 0; 6462 goto out; 6463 } 6464 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { 6465 vcpu->fpu_active = 0; 6466 kvm_x86_ops->fpu_deactivate(vcpu); 6467 } 6468 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 6469 /* Page is swapped out. Do synthetic halt */ 6470 vcpu->arch.apf.halted = true; 6471 r = 1; 6472 goto out; 6473 } 6474 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 6475 record_steal_time(vcpu); 6476 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 6477 process_smi(vcpu); 6478 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 6479 process_nmi(vcpu); 6480 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 6481 kvm_pmu_handle_event(vcpu); 6482 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 6483 kvm_pmu_deliver_pmi(vcpu); 6484 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 6485 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 6486 if (test_bit(vcpu->arch.pending_ioapic_eoi, 6487 vcpu->arch.ioapic_handled_vectors)) { 6488 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 6489 vcpu->run->eoi.vector = 6490 vcpu->arch.pending_ioapic_eoi; 6491 r = 0; 6492 goto out; 6493 } 6494 } 6495 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 6496 vcpu_scan_ioapic(vcpu); 6497 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 6498 kvm_vcpu_reload_apic_access_page(vcpu); 6499 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 6500 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 6501 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 6502 r = 0; 6503 goto out; 6504 } 6505 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 6506 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 6507 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 6508 r = 0; 6509 goto out; 6510 } 6511 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 6512 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 6513 vcpu->run->hyperv = vcpu->arch.hyperv.exit; 6514 r = 0; 6515 goto out; 6516 } 6517 6518 /* 6519 * KVM_REQ_HV_STIMER has to be processed after 6520 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 6521 * depend on the guest clock being up-to-date 6522 */ 6523 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 6524 kvm_hv_process_stimers(vcpu); 6525 } 6526 6527 /* 6528 * KVM_REQ_EVENT is not set when posted interrupts are set by 6529 * VT-d hardware, so we have to update RVI unconditionally. 6530 */ 6531 if (kvm_lapic_enabled(vcpu)) { 6532 /* 6533 * Update architecture specific hints for APIC 6534 * virtual interrupt delivery. 6535 */ 6536 if (vcpu->arch.apicv_active) 6537 kvm_x86_ops->hwapic_irr_update(vcpu, 6538 kvm_lapic_find_highest_irr(vcpu)); 6539 } 6540 6541 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 6542 kvm_apic_accept_events(vcpu); 6543 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 6544 r = 1; 6545 goto out; 6546 } 6547 6548 if (inject_pending_event(vcpu, req_int_win) != 0) 6549 req_immediate_exit = true; 6550 /* enable NMI/IRQ window open exits if needed */ 6551 else if (vcpu->arch.nmi_pending) 6552 kvm_x86_ops->enable_nmi_window(vcpu); 6553 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 6554 kvm_x86_ops->enable_irq_window(vcpu); 6555 6556 if (kvm_lapic_enabled(vcpu)) { 6557 update_cr8_intercept(vcpu); 6558 kvm_lapic_sync_to_vapic(vcpu); 6559 } 6560 } 6561 6562 r = kvm_mmu_reload(vcpu); 6563 if (unlikely(r)) { 6564 goto cancel_injection; 6565 } 6566 6567 preempt_disable(); 6568 6569 kvm_x86_ops->prepare_guest_switch(vcpu); 6570 if (vcpu->fpu_active) 6571 kvm_load_guest_fpu(vcpu); 6572 kvm_load_guest_xcr0(vcpu); 6573 6574 vcpu->mode = IN_GUEST_MODE; 6575 6576 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6577 6578 /* We should set ->mode before check ->requests, 6579 * see the comment in make_all_cpus_request. 6580 */ 6581 smp_mb__after_srcu_read_unlock(); 6582 6583 local_irq_disable(); 6584 6585 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests 6586 || need_resched() || signal_pending(current)) { 6587 vcpu->mode = OUTSIDE_GUEST_MODE; 6588 smp_wmb(); 6589 local_irq_enable(); 6590 preempt_enable(); 6591 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6592 r = 1; 6593 goto cancel_injection; 6594 } 6595 6596 if (req_immediate_exit) 6597 smp_send_reschedule(vcpu->cpu); 6598 6599 trace_kvm_entry(vcpu->vcpu_id); 6600 wait_lapic_expire(vcpu); 6601 __kvm_guest_enter(); 6602 6603 if (unlikely(vcpu->arch.switch_db_regs)) { 6604 set_debugreg(0, 7); 6605 set_debugreg(vcpu->arch.eff_db[0], 0); 6606 set_debugreg(vcpu->arch.eff_db[1], 1); 6607 set_debugreg(vcpu->arch.eff_db[2], 2); 6608 set_debugreg(vcpu->arch.eff_db[3], 3); 6609 set_debugreg(vcpu->arch.dr6, 6); 6610 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; 6611 } 6612 6613 kvm_x86_ops->run(vcpu); 6614 6615 /* 6616 * Do this here before restoring debug registers on the host. And 6617 * since we do this before handling the vmexit, a DR access vmexit 6618 * can (a) read the correct value of the debug registers, (b) set 6619 * KVM_DEBUGREG_WONT_EXIT again. 6620 */ 6621 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 6622 int i; 6623 6624 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 6625 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 6626 for (i = 0; i < KVM_NR_DB_REGS; i++) 6627 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 6628 } 6629 6630 /* 6631 * If the guest has used debug registers, at least dr7 6632 * will be disabled while returning to the host. 6633 * If we don't have active breakpoints in the host, we don't 6634 * care about the messed up debug address registers. But if 6635 * we have some of them active, restore the old state. 6636 */ 6637 if (hw_breakpoint_active()) 6638 hw_breakpoint_restore(); 6639 6640 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 6641 6642 vcpu->mode = OUTSIDE_GUEST_MODE; 6643 smp_wmb(); 6644 6645 /* Interrupt is enabled by handle_external_intr() */ 6646 kvm_x86_ops->handle_external_intr(vcpu); 6647 6648 ++vcpu->stat.exits; 6649 6650 /* 6651 * We must have an instruction between local_irq_enable() and 6652 * kvm_guest_exit(), so the timer interrupt isn't delayed by 6653 * the interrupt shadow. The stat.exits increment will do nicely. 6654 * But we need to prevent reordering, hence this barrier(): 6655 */ 6656 barrier(); 6657 6658 kvm_guest_exit(); 6659 6660 preempt_enable(); 6661 6662 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6663 6664 /* 6665 * Profile KVM exit RIPs: 6666 */ 6667 if (unlikely(prof_on == KVM_PROFILING)) { 6668 unsigned long rip = kvm_rip_read(vcpu); 6669 profile_hit(KVM_PROFILING, (void *)rip); 6670 } 6671 6672 if (unlikely(vcpu->arch.tsc_always_catchup)) 6673 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6674 6675 if (vcpu->arch.apic_attention) 6676 kvm_lapic_sync_from_vapic(vcpu); 6677 6678 r = kvm_x86_ops->handle_exit(vcpu); 6679 return r; 6680 6681 cancel_injection: 6682 kvm_x86_ops->cancel_injection(vcpu); 6683 if (unlikely(vcpu->arch.apic_attention)) 6684 kvm_lapic_sync_from_vapic(vcpu); 6685 out: 6686 return r; 6687 } 6688 6689 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) 6690 { 6691 if (!kvm_arch_vcpu_runnable(vcpu) && 6692 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) { 6693 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6694 kvm_vcpu_block(vcpu); 6695 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6696 6697 if (kvm_x86_ops->post_block) 6698 kvm_x86_ops->post_block(vcpu); 6699 6700 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) 6701 return 1; 6702 } 6703 6704 kvm_apic_accept_events(vcpu); 6705 switch(vcpu->arch.mp_state) { 6706 case KVM_MP_STATE_HALTED: 6707 vcpu->arch.pv.pv_unhalted = false; 6708 vcpu->arch.mp_state = 6709 KVM_MP_STATE_RUNNABLE; 6710 case KVM_MP_STATE_RUNNABLE: 6711 vcpu->arch.apf.halted = false; 6712 break; 6713 case KVM_MP_STATE_INIT_RECEIVED: 6714 break; 6715 default: 6716 return -EINTR; 6717 break; 6718 } 6719 return 1; 6720 } 6721 6722 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 6723 { 6724 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 6725 !vcpu->arch.apf.halted); 6726 } 6727 6728 static int vcpu_run(struct kvm_vcpu *vcpu) 6729 { 6730 int r; 6731 struct kvm *kvm = vcpu->kvm; 6732 6733 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6734 6735 for (;;) { 6736 if (kvm_vcpu_running(vcpu)) { 6737 r = vcpu_enter_guest(vcpu); 6738 } else { 6739 r = vcpu_block(kvm, vcpu); 6740 } 6741 6742 if (r <= 0) 6743 break; 6744 6745 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); 6746 if (kvm_cpu_has_pending_timer(vcpu)) 6747 kvm_inject_pending_timer_irqs(vcpu); 6748 6749 if (dm_request_for_irq_injection(vcpu) && 6750 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 6751 r = 0; 6752 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 6753 ++vcpu->stat.request_irq_exits; 6754 break; 6755 } 6756 6757 kvm_check_async_pf_completion(vcpu); 6758 6759 if (signal_pending(current)) { 6760 r = -EINTR; 6761 vcpu->run->exit_reason = KVM_EXIT_INTR; 6762 ++vcpu->stat.signal_exits; 6763 break; 6764 } 6765 if (need_resched()) { 6766 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6767 cond_resched(); 6768 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6769 } 6770 } 6771 6772 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6773 6774 return r; 6775 } 6776 6777 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 6778 { 6779 int r; 6780 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6781 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 6782 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6783 if (r != EMULATE_DONE) 6784 return 0; 6785 return 1; 6786 } 6787 6788 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 6789 { 6790 BUG_ON(!vcpu->arch.pio.count); 6791 6792 return complete_emulated_io(vcpu); 6793 } 6794 6795 /* 6796 * Implements the following, as a state machine: 6797 * 6798 * read: 6799 * for each fragment 6800 * for each mmio piece in the fragment 6801 * write gpa, len 6802 * exit 6803 * copy data 6804 * execute insn 6805 * 6806 * write: 6807 * for each fragment 6808 * for each mmio piece in the fragment 6809 * write gpa, len 6810 * copy data 6811 * exit 6812 */ 6813 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 6814 { 6815 struct kvm_run *run = vcpu->run; 6816 struct kvm_mmio_fragment *frag; 6817 unsigned len; 6818 6819 BUG_ON(!vcpu->mmio_needed); 6820 6821 /* Complete previous fragment */ 6822 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 6823 len = min(8u, frag->len); 6824 if (!vcpu->mmio_is_write) 6825 memcpy(frag->data, run->mmio.data, len); 6826 6827 if (frag->len <= 8) { 6828 /* Switch to the next fragment. */ 6829 frag++; 6830 vcpu->mmio_cur_fragment++; 6831 } else { 6832 /* Go forward to the next mmio piece. */ 6833 frag->data += len; 6834 frag->gpa += len; 6835 frag->len -= len; 6836 } 6837 6838 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 6839 vcpu->mmio_needed = 0; 6840 6841 /* FIXME: return into emulator if single-stepping. */ 6842 if (vcpu->mmio_is_write) 6843 return 1; 6844 vcpu->mmio_read_completed = 1; 6845 return complete_emulated_io(vcpu); 6846 } 6847 6848 run->exit_reason = KVM_EXIT_MMIO; 6849 run->mmio.phys_addr = frag->gpa; 6850 if (vcpu->mmio_is_write) 6851 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 6852 run->mmio.len = min(8u, frag->len); 6853 run->mmio.is_write = vcpu->mmio_is_write; 6854 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6855 return 0; 6856 } 6857 6858 6859 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 6860 { 6861 struct fpu *fpu = ¤t->thread.fpu; 6862 int r; 6863 sigset_t sigsaved; 6864 6865 fpu__activate_curr(fpu); 6866 6867 if (vcpu->sigset_active) 6868 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); 6869 6870 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 6871 kvm_vcpu_block(vcpu); 6872 kvm_apic_accept_events(vcpu); 6873 clear_bit(KVM_REQ_UNHALT, &vcpu->requests); 6874 r = -EAGAIN; 6875 goto out; 6876 } 6877 6878 /* re-sync apic's tpr */ 6879 if (!lapic_in_kernel(vcpu)) { 6880 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 6881 r = -EINVAL; 6882 goto out; 6883 } 6884 } 6885 6886 if (unlikely(vcpu->arch.complete_userspace_io)) { 6887 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 6888 vcpu->arch.complete_userspace_io = NULL; 6889 r = cui(vcpu); 6890 if (r <= 0) 6891 goto out; 6892 } else 6893 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 6894 6895 r = vcpu_run(vcpu); 6896 6897 out: 6898 post_kvm_run_save(vcpu); 6899 if (vcpu->sigset_active) 6900 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 6901 6902 return r; 6903 } 6904 6905 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6906 { 6907 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 6908 /* 6909 * We are here if userspace calls get_regs() in the middle of 6910 * instruction emulation. Registers state needs to be copied 6911 * back from emulation context to vcpu. Userspace shouldn't do 6912 * that usually, but some bad designed PV devices (vmware 6913 * backdoor interface) need this to work 6914 */ 6915 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 6916 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6917 } 6918 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 6919 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 6920 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 6921 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 6922 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 6923 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 6924 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 6925 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 6926 #ifdef CONFIG_X86_64 6927 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 6928 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 6929 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 6930 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 6931 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 6932 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 6933 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 6934 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 6935 #endif 6936 6937 regs->rip = kvm_rip_read(vcpu); 6938 regs->rflags = kvm_get_rflags(vcpu); 6939 6940 return 0; 6941 } 6942 6943 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6944 { 6945 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 6946 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6947 6948 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 6949 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 6950 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 6951 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 6952 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 6953 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 6954 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 6955 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 6956 #ifdef CONFIG_X86_64 6957 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 6958 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 6959 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 6960 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 6961 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 6962 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 6963 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 6964 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 6965 #endif 6966 6967 kvm_rip_write(vcpu, regs->rip); 6968 kvm_set_rflags(vcpu, regs->rflags); 6969 6970 vcpu->arch.exception.pending = false; 6971 6972 kvm_make_request(KVM_REQ_EVENT, vcpu); 6973 6974 return 0; 6975 } 6976 6977 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 6978 { 6979 struct kvm_segment cs; 6980 6981 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 6982 *db = cs.db; 6983 *l = cs.l; 6984 } 6985 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 6986 6987 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 6988 struct kvm_sregs *sregs) 6989 { 6990 struct desc_ptr dt; 6991 6992 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 6993 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 6994 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 6995 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 6996 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 6997 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 6998 6999 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7000 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7001 7002 kvm_x86_ops->get_idt(vcpu, &dt); 7003 sregs->idt.limit = dt.size; 7004 sregs->idt.base = dt.address; 7005 kvm_x86_ops->get_gdt(vcpu, &dt); 7006 sregs->gdt.limit = dt.size; 7007 sregs->gdt.base = dt.address; 7008 7009 sregs->cr0 = kvm_read_cr0(vcpu); 7010 sregs->cr2 = vcpu->arch.cr2; 7011 sregs->cr3 = kvm_read_cr3(vcpu); 7012 sregs->cr4 = kvm_read_cr4(vcpu); 7013 sregs->cr8 = kvm_get_cr8(vcpu); 7014 sregs->efer = vcpu->arch.efer; 7015 sregs->apic_base = kvm_get_apic_base(vcpu); 7016 7017 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 7018 7019 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) 7020 set_bit(vcpu->arch.interrupt.nr, 7021 (unsigned long *)sregs->interrupt_bitmap); 7022 7023 return 0; 7024 } 7025 7026 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 7027 struct kvm_mp_state *mp_state) 7028 { 7029 kvm_apic_accept_events(vcpu); 7030 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 7031 vcpu->arch.pv.pv_unhalted) 7032 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 7033 else 7034 mp_state->mp_state = vcpu->arch.mp_state; 7035 7036 return 0; 7037 } 7038 7039 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 7040 struct kvm_mp_state *mp_state) 7041 { 7042 if (!kvm_vcpu_has_lapic(vcpu) && 7043 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 7044 return -EINVAL; 7045 7046 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 7047 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 7048 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 7049 } else 7050 vcpu->arch.mp_state = mp_state->mp_state; 7051 kvm_make_request(KVM_REQ_EVENT, vcpu); 7052 return 0; 7053 } 7054 7055 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 7056 int reason, bool has_error_code, u32 error_code) 7057 { 7058 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 7059 int ret; 7060 7061 init_emulate_ctxt(vcpu); 7062 7063 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 7064 has_error_code, error_code); 7065 7066 if (ret) 7067 return EMULATE_FAIL; 7068 7069 kvm_rip_write(vcpu, ctxt->eip); 7070 kvm_set_rflags(vcpu, ctxt->eflags); 7071 kvm_make_request(KVM_REQ_EVENT, vcpu); 7072 return EMULATE_DONE; 7073 } 7074 EXPORT_SYMBOL_GPL(kvm_task_switch); 7075 7076 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 7077 struct kvm_sregs *sregs) 7078 { 7079 struct msr_data apic_base_msr; 7080 int mmu_reset_needed = 0; 7081 int pending_vec, max_bits, idx; 7082 struct desc_ptr dt; 7083 7084 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) 7085 return -EINVAL; 7086 7087 dt.size = sregs->idt.limit; 7088 dt.address = sregs->idt.base; 7089 kvm_x86_ops->set_idt(vcpu, &dt); 7090 dt.size = sregs->gdt.limit; 7091 dt.address = sregs->gdt.base; 7092 kvm_x86_ops->set_gdt(vcpu, &dt); 7093 7094 vcpu->arch.cr2 = sregs->cr2; 7095 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 7096 vcpu->arch.cr3 = sregs->cr3; 7097 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 7098 7099 kvm_set_cr8(vcpu, sregs->cr8); 7100 7101 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 7102 kvm_x86_ops->set_efer(vcpu, sregs->efer); 7103 apic_base_msr.data = sregs->apic_base; 7104 apic_base_msr.host_initiated = true; 7105 kvm_set_apic_base(vcpu, &apic_base_msr); 7106 7107 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 7108 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 7109 vcpu->arch.cr0 = sregs->cr0; 7110 7111 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 7112 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 7113 if (sregs->cr4 & X86_CR4_OSXSAVE) 7114 kvm_update_cpuid(vcpu); 7115 7116 idx = srcu_read_lock(&vcpu->kvm->srcu); 7117 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 7118 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 7119 mmu_reset_needed = 1; 7120 } 7121 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7122 7123 if (mmu_reset_needed) 7124 kvm_mmu_reset_context(vcpu); 7125 7126 max_bits = KVM_NR_INTERRUPTS; 7127 pending_vec = find_first_bit( 7128 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 7129 if (pending_vec < max_bits) { 7130 kvm_queue_interrupt(vcpu, pending_vec, false); 7131 pr_debug("Set back pending irq %d\n", pending_vec); 7132 } 7133 7134 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 7135 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 7136 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 7137 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 7138 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 7139 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 7140 7141 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 7142 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 7143 7144 update_cr8_intercept(vcpu); 7145 7146 /* Older userspace won't unhalt the vcpu on reset. */ 7147 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 7148 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 7149 !is_protmode(vcpu)) 7150 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7151 7152 kvm_make_request(KVM_REQ_EVENT, vcpu); 7153 7154 return 0; 7155 } 7156 7157 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 7158 struct kvm_guest_debug *dbg) 7159 { 7160 unsigned long rflags; 7161 int i, r; 7162 7163 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 7164 r = -EBUSY; 7165 if (vcpu->arch.exception.pending) 7166 goto out; 7167 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 7168 kvm_queue_exception(vcpu, DB_VECTOR); 7169 else 7170 kvm_queue_exception(vcpu, BP_VECTOR); 7171 } 7172 7173 /* 7174 * Read rflags as long as potentially injected trace flags are still 7175 * filtered out. 7176 */ 7177 rflags = kvm_get_rflags(vcpu); 7178 7179 vcpu->guest_debug = dbg->control; 7180 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 7181 vcpu->guest_debug = 0; 7182 7183 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 7184 for (i = 0; i < KVM_NR_DB_REGS; ++i) 7185 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 7186 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 7187 } else { 7188 for (i = 0; i < KVM_NR_DB_REGS; i++) 7189 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 7190 } 7191 kvm_update_dr7(vcpu); 7192 7193 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 7194 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 7195 get_segment_base(vcpu, VCPU_SREG_CS); 7196 7197 /* 7198 * Trigger an rflags update that will inject or remove the trace 7199 * flags. 7200 */ 7201 kvm_set_rflags(vcpu, rflags); 7202 7203 kvm_x86_ops->update_bp_intercept(vcpu); 7204 7205 r = 0; 7206 7207 out: 7208 7209 return r; 7210 } 7211 7212 /* 7213 * Translate a guest virtual address to a guest physical address. 7214 */ 7215 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 7216 struct kvm_translation *tr) 7217 { 7218 unsigned long vaddr = tr->linear_address; 7219 gpa_t gpa; 7220 int idx; 7221 7222 idx = srcu_read_lock(&vcpu->kvm->srcu); 7223 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 7224 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7225 tr->physical_address = gpa; 7226 tr->valid = gpa != UNMAPPED_GVA; 7227 tr->writeable = 1; 7228 tr->usermode = 0; 7229 7230 return 0; 7231 } 7232 7233 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7234 { 7235 struct fxregs_state *fxsave = 7236 &vcpu->arch.guest_fpu.state.fxsave; 7237 7238 memcpy(fpu->fpr, fxsave->st_space, 128); 7239 fpu->fcw = fxsave->cwd; 7240 fpu->fsw = fxsave->swd; 7241 fpu->ftwx = fxsave->twd; 7242 fpu->last_opcode = fxsave->fop; 7243 fpu->last_ip = fxsave->rip; 7244 fpu->last_dp = fxsave->rdp; 7245 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 7246 7247 return 0; 7248 } 7249 7250 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 7251 { 7252 struct fxregs_state *fxsave = 7253 &vcpu->arch.guest_fpu.state.fxsave; 7254 7255 memcpy(fxsave->st_space, fpu->fpr, 128); 7256 fxsave->cwd = fpu->fcw; 7257 fxsave->swd = fpu->fsw; 7258 fxsave->twd = fpu->ftwx; 7259 fxsave->fop = fpu->last_opcode; 7260 fxsave->rip = fpu->last_ip; 7261 fxsave->rdp = fpu->last_dp; 7262 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 7263 7264 return 0; 7265 } 7266 7267 static void fx_init(struct kvm_vcpu *vcpu) 7268 { 7269 fpstate_init(&vcpu->arch.guest_fpu.state); 7270 if (cpu_has_xsaves) 7271 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv = 7272 host_xcr0 | XSTATE_COMPACTION_ENABLED; 7273 7274 /* 7275 * Ensure guest xcr0 is valid for loading 7276 */ 7277 vcpu->arch.xcr0 = XFEATURE_MASK_FP; 7278 7279 vcpu->arch.cr0 |= X86_CR0_ET; 7280 } 7281 7282 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 7283 { 7284 if (vcpu->guest_fpu_loaded) 7285 return; 7286 7287 /* 7288 * Restore all possible states in the guest, 7289 * and assume host would use all available bits. 7290 * Guest xcr0 would be loaded later. 7291 */ 7292 kvm_put_guest_xcr0(vcpu); 7293 vcpu->guest_fpu_loaded = 1; 7294 __kernel_fpu_begin(); 7295 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state); 7296 trace_kvm_fpu(1); 7297 } 7298 7299 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 7300 { 7301 kvm_put_guest_xcr0(vcpu); 7302 7303 if (!vcpu->guest_fpu_loaded) { 7304 vcpu->fpu_counter = 0; 7305 return; 7306 } 7307 7308 vcpu->guest_fpu_loaded = 0; 7309 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu); 7310 __kernel_fpu_end(); 7311 ++vcpu->stat.fpu_reload; 7312 /* 7313 * If using eager FPU mode, or if the guest is a frequent user 7314 * of the FPU, just leave the FPU active for next time. 7315 * Every 255 times fpu_counter rolls over to 0; a guest that uses 7316 * the FPU in bursts will revert to loading it on demand. 7317 */ 7318 if (!vcpu->arch.eager_fpu) { 7319 if (++vcpu->fpu_counter < 5) 7320 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); 7321 } 7322 trace_kvm_fpu(0); 7323 } 7324 7325 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 7326 { 7327 kvmclock_reset(vcpu); 7328 7329 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 7330 kvm_x86_ops->vcpu_free(vcpu); 7331 } 7332 7333 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 7334 unsigned int id) 7335 { 7336 struct kvm_vcpu *vcpu; 7337 7338 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 7339 printk_once(KERN_WARNING 7340 "kvm: SMP vm created on host with unstable TSC; " 7341 "guest TSC will not be reliable\n"); 7342 7343 vcpu = kvm_x86_ops->vcpu_create(kvm, id); 7344 7345 return vcpu; 7346 } 7347 7348 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 7349 { 7350 int r; 7351 7352 kvm_vcpu_mtrr_init(vcpu); 7353 r = vcpu_load(vcpu); 7354 if (r) 7355 return r; 7356 kvm_vcpu_reset(vcpu, false); 7357 kvm_mmu_setup(vcpu); 7358 vcpu_put(vcpu); 7359 return r; 7360 } 7361 7362 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 7363 { 7364 struct msr_data msr; 7365 struct kvm *kvm = vcpu->kvm; 7366 7367 if (vcpu_load(vcpu)) 7368 return; 7369 msr.data = 0x0; 7370 msr.index = MSR_IA32_TSC; 7371 msr.host_initiated = true; 7372 kvm_write_tsc(vcpu, &msr); 7373 vcpu_put(vcpu); 7374 7375 if (!kvmclock_periodic_sync) 7376 return; 7377 7378 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 7379 KVMCLOCK_SYNC_PERIOD); 7380 } 7381 7382 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 7383 { 7384 int r; 7385 vcpu->arch.apf.msr_val = 0; 7386 7387 r = vcpu_load(vcpu); 7388 BUG_ON(r); 7389 kvm_mmu_unload(vcpu); 7390 vcpu_put(vcpu); 7391 7392 kvm_x86_ops->vcpu_free(vcpu); 7393 } 7394 7395 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 7396 { 7397 vcpu->arch.hflags = 0; 7398 7399 atomic_set(&vcpu->arch.nmi_queued, 0); 7400 vcpu->arch.nmi_pending = 0; 7401 vcpu->arch.nmi_injected = false; 7402 kvm_clear_interrupt_queue(vcpu); 7403 kvm_clear_exception_queue(vcpu); 7404 7405 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 7406 kvm_update_dr0123(vcpu); 7407 vcpu->arch.dr6 = DR6_INIT; 7408 kvm_update_dr6(vcpu); 7409 vcpu->arch.dr7 = DR7_FIXED_1; 7410 kvm_update_dr7(vcpu); 7411 7412 vcpu->arch.cr2 = 0; 7413 7414 kvm_make_request(KVM_REQ_EVENT, vcpu); 7415 vcpu->arch.apf.msr_val = 0; 7416 vcpu->arch.st.msr_val = 0; 7417 7418 kvmclock_reset(vcpu); 7419 7420 kvm_clear_async_pf_completion_queue(vcpu); 7421 kvm_async_pf_hash_reset(vcpu); 7422 vcpu->arch.apf.halted = false; 7423 7424 if (!init_event) { 7425 kvm_pmu_reset(vcpu); 7426 vcpu->arch.smbase = 0x30000; 7427 } 7428 7429 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 7430 vcpu->arch.regs_avail = ~0; 7431 vcpu->arch.regs_dirty = ~0; 7432 7433 kvm_x86_ops->vcpu_reset(vcpu, init_event); 7434 } 7435 7436 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 7437 { 7438 struct kvm_segment cs; 7439 7440 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 7441 cs.selector = vector << 8; 7442 cs.base = vector << 12; 7443 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 7444 kvm_rip_write(vcpu, 0); 7445 } 7446 7447 int kvm_arch_hardware_enable(void) 7448 { 7449 struct kvm *kvm; 7450 struct kvm_vcpu *vcpu; 7451 int i; 7452 int ret; 7453 u64 local_tsc; 7454 u64 max_tsc = 0; 7455 bool stable, backwards_tsc = false; 7456 7457 kvm_shared_msr_cpu_online(); 7458 ret = kvm_x86_ops->hardware_enable(); 7459 if (ret != 0) 7460 return ret; 7461 7462 local_tsc = rdtsc(); 7463 stable = !check_tsc_unstable(); 7464 list_for_each_entry(kvm, &vm_list, vm_list) { 7465 kvm_for_each_vcpu(i, vcpu, kvm) { 7466 if (!stable && vcpu->cpu == smp_processor_id()) 7467 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 7468 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 7469 backwards_tsc = true; 7470 if (vcpu->arch.last_host_tsc > max_tsc) 7471 max_tsc = vcpu->arch.last_host_tsc; 7472 } 7473 } 7474 } 7475 7476 /* 7477 * Sometimes, even reliable TSCs go backwards. This happens on 7478 * platforms that reset TSC during suspend or hibernate actions, but 7479 * maintain synchronization. We must compensate. Fortunately, we can 7480 * detect that condition here, which happens early in CPU bringup, 7481 * before any KVM threads can be running. Unfortunately, we can't 7482 * bring the TSCs fully up to date with real time, as we aren't yet far 7483 * enough into CPU bringup that we know how much real time has actually 7484 * elapsed; our helper function, get_kernel_ns() will be using boot 7485 * variables that haven't been updated yet. 7486 * 7487 * So we simply find the maximum observed TSC above, then record the 7488 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 7489 * the adjustment will be applied. Note that we accumulate 7490 * adjustments, in case multiple suspend cycles happen before some VCPU 7491 * gets a chance to run again. In the event that no KVM threads get a 7492 * chance to run, we will miss the entire elapsed period, as we'll have 7493 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 7494 * loose cycle time. This isn't too big a deal, since the loss will be 7495 * uniform across all VCPUs (not to mention the scenario is extremely 7496 * unlikely). It is possible that a second hibernate recovery happens 7497 * much faster than a first, causing the observed TSC here to be 7498 * smaller; this would require additional padding adjustment, which is 7499 * why we set last_host_tsc to the local tsc observed here. 7500 * 7501 * N.B. - this code below runs only on platforms with reliable TSC, 7502 * as that is the only way backwards_tsc is set above. Also note 7503 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 7504 * have the same delta_cyc adjustment applied if backwards_tsc 7505 * is detected. Note further, this adjustment is only done once, 7506 * as we reset last_host_tsc on all VCPUs to stop this from being 7507 * called multiple times (one for each physical CPU bringup). 7508 * 7509 * Platforms with unreliable TSCs don't have to deal with this, they 7510 * will be compensated by the logic in vcpu_load, which sets the TSC to 7511 * catchup mode. This will catchup all VCPUs to real time, but cannot 7512 * guarantee that they stay in perfect synchronization. 7513 */ 7514 if (backwards_tsc) { 7515 u64 delta_cyc = max_tsc - local_tsc; 7516 backwards_tsc_observed = true; 7517 list_for_each_entry(kvm, &vm_list, vm_list) { 7518 kvm_for_each_vcpu(i, vcpu, kvm) { 7519 vcpu->arch.tsc_offset_adjustment += delta_cyc; 7520 vcpu->arch.last_host_tsc = local_tsc; 7521 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 7522 } 7523 7524 /* 7525 * We have to disable TSC offset matching.. if you were 7526 * booting a VM while issuing an S4 host suspend.... 7527 * you may have some problem. Solving this issue is 7528 * left as an exercise to the reader. 7529 */ 7530 kvm->arch.last_tsc_nsec = 0; 7531 kvm->arch.last_tsc_write = 0; 7532 } 7533 7534 } 7535 return 0; 7536 } 7537 7538 void kvm_arch_hardware_disable(void) 7539 { 7540 kvm_x86_ops->hardware_disable(); 7541 drop_user_return_notifiers(); 7542 } 7543 7544 int kvm_arch_hardware_setup(void) 7545 { 7546 int r; 7547 7548 r = kvm_x86_ops->hardware_setup(); 7549 if (r != 0) 7550 return r; 7551 7552 if (kvm_has_tsc_control) { 7553 /* 7554 * Make sure the user can only configure tsc_khz values that 7555 * fit into a signed integer. 7556 * A min value is not calculated needed because it will always 7557 * be 1 on all machines. 7558 */ 7559 u64 max = min(0x7fffffffULL, 7560 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz)); 7561 kvm_max_guest_tsc_khz = max; 7562 7563 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits; 7564 } 7565 7566 kvm_init_msr_list(); 7567 return 0; 7568 } 7569 7570 void kvm_arch_hardware_unsetup(void) 7571 { 7572 kvm_x86_ops->hardware_unsetup(); 7573 } 7574 7575 void kvm_arch_check_processor_compat(void *rtn) 7576 { 7577 kvm_x86_ops->check_processor_compatibility(rtn); 7578 } 7579 7580 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 7581 { 7582 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 7583 } 7584 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); 7585 7586 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 7587 { 7588 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 7589 } 7590 7591 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) 7592 { 7593 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu); 7594 } 7595 7596 struct static_key kvm_no_apic_vcpu __read_mostly; 7597 7598 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 7599 { 7600 struct page *page; 7601 struct kvm *kvm; 7602 int r; 7603 7604 BUG_ON(vcpu->kvm == NULL); 7605 kvm = vcpu->kvm; 7606 7607 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(); 7608 vcpu->arch.pv.pv_unhalted = false; 7609 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 7610 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 7611 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7612 else 7613 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 7614 7615 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 7616 if (!page) { 7617 r = -ENOMEM; 7618 goto fail; 7619 } 7620 vcpu->arch.pio_data = page_address(page); 7621 7622 kvm_set_tsc_khz(vcpu, max_tsc_khz); 7623 7624 r = kvm_mmu_create(vcpu); 7625 if (r < 0) 7626 goto fail_free_pio_data; 7627 7628 if (irqchip_in_kernel(kvm)) { 7629 r = kvm_create_lapic(vcpu); 7630 if (r < 0) 7631 goto fail_mmu_destroy; 7632 } else 7633 static_key_slow_inc(&kvm_no_apic_vcpu); 7634 7635 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 7636 GFP_KERNEL); 7637 if (!vcpu->arch.mce_banks) { 7638 r = -ENOMEM; 7639 goto fail_free_lapic; 7640 } 7641 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 7642 7643 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 7644 r = -ENOMEM; 7645 goto fail_free_mce_banks; 7646 } 7647 7648 fx_init(vcpu); 7649 7650 vcpu->arch.ia32_tsc_adjust_msr = 0x0; 7651 vcpu->arch.pv_time_enabled = false; 7652 7653 vcpu->arch.guest_supported_xcr0 = 0; 7654 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 7655 7656 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 7657 7658 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 7659 7660 kvm_async_pf_hash_reset(vcpu); 7661 kvm_pmu_init(vcpu); 7662 7663 vcpu->arch.pending_external_vector = -1; 7664 7665 kvm_hv_vcpu_init(vcpu); 7666 7667 return 0; 7668 7669 fail_free_mce_banks: 7670 kfree(vcpu->arch.mce_banks); 7671 fail_free_lapic: 7672 kvm_free_lapic(vcpu); 7673 fail_mmu_destroy: 7674 kvm_mmu_destroy(vcpu); 7675 fail_free_pio_data: 7676 free_page((unsigned long)vcpu->arch.pio_data); 7677 fail: 7678 return r; 7679 } 7680 7681 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 7682 { 7683 int idx; 7684 7685 kvm_hv_vcpu_uninit(vcpu); 7686 kvm_pmu_destroy(vcpu); 7687 kfree(vcpu->arch.mce_banks); 7688 kvm_free_lapic(vcpu); 7689 idx = srcu_read_lock(&vcpu->kvm->srcu); 7690 kvm_mmu_destroy(vcpu); 7691 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7692 free_page((unsigned long)vcpu->arch.pio_data); 7693 if (!lapic_in_kernel(vcpu)) 7694 static_key_slow_dec(&kvm_no_apic_vcpu); 7695 } 7696 7697 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 7698 { 7699 kvm_x86_ops->sched_in(vcpu, cpu); 7700 } 7701 7702 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 7703 { 7704 if (type) 7705 return -EINVAL; 7706 7707 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 7708 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 7709 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 7710 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 7711 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 7712 7713 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 7714 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 7715 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 7716 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 7717 &kvm->arch.irq_sources_bitmap); 7718 7719 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 7720 mutex_init(&kvm->arch.apic_map_lock); 7721 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 7722 7723 pvclock_update_vm_gtod_copy(kvm); 7724 7725 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 7726 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 7727 7728 return 0; 7729 } 7730 7731 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 7732 { 7733 int r; 7734 r = vcpu_load(vcpu); 7735 BUG_ON(r); 7736 kvm_mmu_unload(vcpu); 7737 vcpu_put(vcpu); 7738 } 7739 7740 static void kvm_free_vcpus(struct kvm *kvm) 7741 { 7742 unsigned int i; 7743 struct kvm_vcpu *vcpu; 7744 7745 /* 7746 * Unpin any mmu pages first. 7747 */ 7748 kvm_for_each_vcpu(i, vcpu, kvm) { 7749 kvm_clear_async_pf_completion_queue(vcpu); 7750 kvm_unload_vcpu_mmu(vcpu); 7751 } 7752 kvm_for_each_vcpu(i, vcpu, kvm) 7753 kvm_arch_vcpu_free(vcpu); 7754 7755 mutex_lock(&kvm->lock); 7756 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 7757 kvm->vcpus[i] = NULL; 7758 7759 atomic_set(&kvm->online_vcpus, 0); 7760 mutex_unlock(&kvm->lock); 7761 } 7762 7763 void kvm_arch_sync_events(struct kvm *kvm) 7764 { 7765 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 7766 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 7767 kvm_free_all_assigned_devices(kvm); 7768 kvm_free_pit(kvm); 7769 } 7770 7771 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 7772 { 7773 int i, r; 7774 unsigned long hva; 7775 struct kvm_memslots *slots = kvm_memslots(kvm); 7776 struct kvm_memory_slot *slot, old; 7777 7778 /* Called with kvm->slots_lock held. */ 7779 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 7780 return -EINVAL; 7781 7782 slot = id_to_memslot(slots, id); 7783 if (size) { 7784 if (WARN_ON(slot->npages)) 7785 return -EEXIST; 7786 7787 /* 7788 * MAP_SHARED to prevent internal slot pages from being moved 7789 * by fork()/COW. 7790 */ 7791 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 7792 MAP_SHARED | MAP_ANONYMOUS, 0); 7793 if (IS_ERR((void *)hva)) 7794 return PTR_ERR((void *)hva); 7795 } else { 7796 if (!slot->npages) 7797 return 0; 7798 7799 hva = 0; 7800 } 7801 7802 old = *slot; 7803 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 7804 struct kvm_userspace_memory_region m; 7805 7806 m.slot = id | (i << 16); 7807 m.flags = 0; 7808 m.guest_phys_addr = gpa; 7809 m.userspace_addr = hva; 7810 m.memory_size = size; 7811 r = __kvm_set_memory_region(kvm, &m); 7812 if (r < 0) 7813 return r; 7814 } 7815 7816 if (!size) { 7817 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE); 7818 WARN_ON(r < 0); 7819 } 7820 7821 return 0; 7822 } 7823 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 7824 7825 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size) 7826 { 7827 int r; 7828 7829 mutex_lock(&kvm->slots_lock); 7830 r = __x86_set_memory_region(kvm, id, gpa, size); 7831 mutex_unlock(&kvm->slots_lock); 7832 7833 return r; 7834 } 7835 EXPORT_SYMBOL_GPL(x86_set_memory_region); 7836 7837 void kvm_arch_destroy_vm(struct kvm *kvm) 7838 { 7839 if (current->mm == kvm->mm) { 7840 /* 7841 * Free memory regions allocated on behalf of userspace, 7842 * unless the the memory map has changed due to process exit 7843 * or fd copying. 7844 */ 7845 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0); 7846 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0); 7847 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 7848 } 7849 kvm_iommu_unmap_guest(kvm); 7850 kfree(kvm->arch.vpic); 7851 kfree(kvm->arch.vioapic); 7852 kvm_free_vcpus(kvm); 7853 kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 7854 } 7855 7856 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 7857 struct kvm_memory_slot *dont) 7858 { 7859 int i; 7860 7861 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7862 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 7863 kvfree(free->arch.rmap[i]); 7864 free->arch.rmap[i] = NULL; 7865 } 7866 if (i == 0) 7867 continue; 7868 7869 if (!dont || free->arch.lpage_info[i - 1] != 7870 dont->arch.lpage_info[i - 1]) { 7871 kvfree(free->arch.lpage_info[i - 1]); 7872 free->arch.lpage_info[i - 1] = NULL; 7873 } 7874 } 7875 } 7876 7877 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 7878 unsigned long npages) 7879 { 7880 int i; 7881 7882 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7883 unsigned long ugfn; 7884 int lpages; 7885 int level = i + 1; 7886 7887 lpages = gfn_to_index(slot->base_gfn + npages - 1, 7888 slot->base_gfn, level) + 1; 7889 7890 slot->arch.rmap[i] = 7891 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); 7892 if (!slot->arch.rmap[i]) 7893 goto out_free; 7894 if (i == 0) 7895 continue; 7896 7897 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages * 7898 sizeof(*slot->arch.lpage_info[i - 1])); 7899 if (!slot->arch.lpage_info[i - 1]) 7900 goto out_free; 7901 7902 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 7903 slot->arch.lpage_info[i - 1][0].write_count = 1; 7904 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 7905 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1; 7906 ugfn = slot->userspace_addr >> PAGE_SHIFT; 7907 /* 7908 * If the gfn and userspace address are not aligned wrt each 7909 * other, or if explicitly asked to, disable large page 7910 * support for this slot 7911 */ 7912 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 7913 !kvm_largepages_enabled()) { 7914 unsigned long j; 7915 7916 for (j = 0; j < lpages; ++j) 7917 slot->arch.lpage_info[i - 1][j].write_count = 1; 7918 } 7919 } 7920 7921 return 0; 7922 7923 out_free: 7924 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7925 kvfree(slot->arch.rmap[i]); 7926 slot->arch.rmap[i] = NULL; 7927 if (i == 0) 7928 continue; 7929 7930 kvfree(slot->arch.lpage_info[i - 1]); 7931 slot->arch.lpage_info[i - 1] = NULL; 7932 } 7933 return -ENOMEM; 7934 } 7935 7936 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) 7937 { 7938 /* 7939 * memslots->generation has been incremented. 7940 * mmio generation may have reached its maximum value. 7941 */ 7942 kvm_mmu_invalidate_mmio_sptes(kvm, slots); 7943 } 7944 7945 int kvm_arch_prepare_memory_region(struct kvm *kvm, 7946 struct kvm_memory_slot *memslot, 7947 const struct kvm_userspace_memory_region *mem, 7948 enum kvm_mr_change change) 7949 { 7950 return 0; 7951 } 7952 7953 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 7954 struct kvm_memory_slot *new) 7955 { 7956 /* Still write protect RO slot */ 7957 if (new->flags & KVM_MEM_READONLY) { 7958 kvm_mmu_slot_remove_write_access(kvm, new); 7959 return; 7960 } 7961 7962 /* 7963 * Call kvm_x86_ops dirty logging hooks when they are valid. 7964 * 7965 * kvm_x86_ops->slot_disable_log_dirty is called when: 7966 * 7967 * - KVM_MR_CREATE with dirty logging is disabled 7968 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag 7969 * 7970 * The reason is, in case of PML, we need to set D-bit for any slots 7971 * with dirty logging disabled in order to eliminate unnecessary GPA 7972 * logging in PML buffer (and potential PML buffer full VMEXT). This 7973 * guarantees leaving PML enabled during guest's lifetime won't have 7974 * any additonal overhead from PML when guest is running with dirty 7975 * logging disabled for memory slots. 7976 * 7977 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot 7978 * to dirty logging mode. 7979 * 7980 * If kvm_x86_ops dirty logging hooks are invalid, use write protect. 7981 * 7982 * In case of write protect: 7983 * 7984 * Write protect all pages for dirty logging. 7985 * 7986 * All the sptes including the large sptes which point to this 7987 * slot are set to readonly. We can not create any new large 7988 * spte on this slot until the end of the logging. 7989 * 7990 * See the comments in fast_page_fault(). 7991 */ 7992 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) { 7993 if (kvm_x86_ops->slot_enable_log_dirty) 7994 kvm_x86_ops->slot_enable_log_dirty(kvm, new); 7995 else 7996 kvm_mmu_slot_remove_write_access(kvm, new); 7997 } else { 7998 if (kvm_x86_ops->slot_disable_log_dirty) 7999 kvm_x86_ops->slot_disable_log_dirty(kvm, new); 8000 } 8001 } 8002 8003 void kvm_arch_commit_memory_region(struct kvm *kvm, 8004 const struct kvm_userspace_memory_region *mem, 8005 const struct kvm_memory_slot *old, 8006 const struct kvm_memory_slot *new, 8007 enum kvm_mr_change change) 8008 { 8009 int nr_mmu_pages = 0; 8010 8011 if (!kvm->arch.n_requested_mmu_pages) 8012 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 8013 8014 if (nr_mmu_pages) 8015 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 8016 8017 /* 8018 * Dirty logging tracks sptes in 4k granularity, meaning that large 8019 * sptes have to be split. If live migration is successful, the guest 8020 * in the source machine will be destroyed and large sptes will be 8021 * created in the destination. However, if the guest continues to run 8022 * in the source machine (for example if live migration fails), small 8023 * sptes will remain around and cause bad performance. 8024 * 8025 * Scan sptes if dirty logging has been stopped, dropping those 8026 * which can be collapsed into a single large-page spte. Later 8027 * page faults will create the large-page sptes. 8028 */ 8029 if ((change != KVM_MR_DELETE) && 8030 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 8031 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES)) 8032 kvm_mmu_zap_collapsible_sptes(kvm, new); 8033 8034 /* 8035 * Set up write protection and/or dirty logging for the new slot. 8036 * 8037 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have 8038 * been zapped so no dirty logging staff is needed for old slot. For 8039 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the 8040 * new and it's also covered when dealing with the new slot. 8041 * 8042 * FIXME: const-ify all uses of struct kvm_memory_slot. 8043 */ 8044 if (change != KVM_MR_DELETE) 8045 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new); 8046 } 8047 8048 void kvm_arch_flush_shadow_all(struct kvm *kvm) 8049 { 8050 kvm_mmu_invalidate_zap_all_pages(kvm); 8051 } 8052 8053 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 8054 struct kvm_memory_slot *slot) 8055 { 8056 kvm_mmu_invalidate_zap_all_pages(kvm); 8057 } 8058 8059 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 8060 { 8061 if (!list_empty_careful(&vcpu->async_pf.done)) 8062 return true; 8063 8064 if (kvm_apic_has_events(vcpu)) 8065 return true; 8066 8067 if (vcpu->arch.pv.pv_unhalted) 8068 return true; 8069 8070 if (atomic_read(&vcpu->arch.nmi_queued)) 8071 return true; 8072 8073 if (test_bit(KVM_REQ_SMI, &vcpu->requests)) 8074 return true; 8075 8076 if (kvm_arch_interrupt_allowed(vcpu) && 8077 kvm_cpu_has_interrupt(vcpu)) 8078 return true; 8079 8080 if (kvm_hv_has_stimer_pending(vcpu)) 8081 return true; 8082 8083 return false; 8084 } 8085 8086 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 8087 { 8088 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 8089 kvm_x86_ops->check_nested_events(vcpu, false); 8090 8091 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 8092 } 8093 8094 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 8095 { 8096 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 8097 } 8098 8099 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 8100 { 8101 return kvm_x86_ops->interrupt_allowed(vcpu); 8102 } 8103 8104 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 8105 { 8106 if (is_64_bit_mode(vcpu)) 8107 return kvm_rip_read(vcpu); 8108 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 8109 kvm_rip_read(vcpu)); 8110 } 8111 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 8112 8113 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 8114 { 8115 return kvm_get_linear_rip(vcpu) == linear_rip; 8116 } 8117 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 8118 8119 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 8120 { 8121 unsigned long rflags; 8122 8123 rflags = kvm_x86_ops->get_rflags(vcpu); 8124 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 8125 rflags &= ~X86_EFLAGS_TF; 8126 return rflags; 8127 } 8128 EXPORT_SYMBOL_GPL(kvm_get_rflags); 8129 8130 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8131 { 8132 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 8133 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 8134 rflags |= X86_EFLAGS_TF; 8135 kvm_x86_ops->set_rflags(vcpu, rflags); 8136 } 8137 8138 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 8139 { 8140 __kvm_set_rflags(vcpu, rflags); 8141 kvm_make_request(KVM_REQ_EVENT, vcpu); 8142 } 8143 EXPORT_SYMBOL_GPL(kvm_set_rflags); 8144 8145 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 8146 { 8147 int r; 8148 8149 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 8150 work->wakeup_all) 8151 return; 8152 8153 r = kvm_mmu_reload(vcpu); 8154 if (unlikely(r)) 8155 return; 8156 8157 if (!vcpu->arch.mmu.direct_map && 8158 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 8159 return; 8160 8161 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 8162 } 8163 8164 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 8165 { 8166 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 8167 } 8168 8169 static inline u32 kvm_async_pf_next_probe(u32 key) 8170 { 8171 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 8172 } 8173 8174 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8175 { 8176 u32 key = kvm_async_pf_hash_fn(gfn); 8177 8178 while (vcpu->arch.apf.gfns[key] != ~0) 8179 key = kvm_async_pf_next_probe(key); 8180 8181 vcpu->arch.apf.gfns[key] = gfn; 8182 } 8183 8184 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 8185 { 8186 int i; 8187 u32 key = kvm_async_pf_hash_fn(gfn); 8188 8189 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 8190 (vcpu->arch.apf.gfns[key] != gfn && 8191 vcpu->arch.apf.gfns[key] != ~0); i++) 8192 key = kvm_async_pf_next_probe(key); 8193 8194 return key; 8195 } 8196 8197 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8198 { 8199 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 8200 } 8201 8202 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 8203 { 8204 u32 i, j, k; 8205 8206 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 8207 while (true) { 8208 vcpu->arch.apf.gfns[i] = ~0; 8209 do { 8210 j = kvm_async_pf_next_probe(j); 8211 if (vcpu->arch.apf.gfns[j] == ~0) 8212 return; 8213 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 8214 /* 8215 * k lies cyclically in ]i,j] 8216 * | i.k.j | 8217 * |....j i.k.| or |.k..j i...| 8218 */ 8219 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 8220 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 8221 i = j; 8222 } 8223 } 8224 8225 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 8226 { 8227 8228 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 8229 sizeof(val)); 8230 } 8231 8232 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 8233 struct kvm_async_pf *work) 8234 { 8235 struct x86_exception fault; 8236 8237 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 8238 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 8239 8240 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 8241 (vcpu->arch.apf.send_user_only && 8242 kvm_x86_ops->get_cpl(vcpu) == 0)) 8243 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 8244 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 8245 fault.vector = PF_VECTOR; 8246 fault.error_code_valid = true; 8247 fault.error_code = 0; 8248 fault.nested_page_fault = false; 8249 fault.address = work->arch.token; 8250 kvm_inject_page_fault(vcpu, &fault); 8251 } 8252 } 8253 8254 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 8255 struct kvm_async_pf *work) 8256 { 8257 struct x86_exception fault; 8258 8259 trace_kvm_async_pf_ready(work->arch.token, work->gva); 8260 if (work->wakeup_all) 8261 work->arch.token = ~0; /* broadcast wakeup */ 8262 else 8263 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 8264 8265 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && 8266 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 8267 fault.vector = PF_VECTOR; 8268 fault.error_code_valid = true; 8269 fault.error_code = 0; 8270 fault.nested_page_fault = false; 8271 fault.address = work->arch.token; 8272 kvm_inject_page_fault(vcpu, &fault); 8273 } 8274 vcpu->arch.apf.halted = false; 8275 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 8276 } 8277 8278 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 8279 { 8280 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 8281 return true; 8282 else 8283 return !kvm_event_needs_reinjection(vcpu) && 8284 kvm_x86_ops->interrupt_allowed(vcpu); 8285 } 8286 8287 void kvm_arch_start_assignment(struct kvm *kvm) 8288 { 8289 atomic_inc(&kvm->arch.assigned_device_count); 8290 } 8291 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 8292 8293 void kvm_arch_end_assignment(struct kvm *kvm) 8294 { 8295 atomic_dec(&kvm->arch.assigned_device_count); 8296 } 8297 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 8298 8299 bool kvm_arch_has_assigned_device(struct kvm *kvm) 8300 { 8301 return atomic_read(&kvm->arch.assigned_device_count); 8302 } 8303 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 8304 8305 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 8306 { 8307 atomic_inc(&kvm->arch.noncoherent_dma_count); 8308 } 8309 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 8310 8311 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 8312 { 8313 atomic_dec(&kvm->arch.noncoherent_dma_count); 8314 } 8315 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 8316 8317 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 8318 { 8319 return atomic_read(&kvm->arch.noncoherent_dma_count); 8320 } 8321 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 8322 8323 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 8324 struct irq_bypass_producer *prod) 8325 { 8326 struct kvm_kernel_irqfd *irqfd = 8327 container_of(cons, struct kvm_kernel_irqfd, consumer); 8328 8329 if (kvm_x86_ops->update_pi_irte) { 8330 irqfd->producer = prod; 8331 return kvm_x86_ops->update_pi_irte(irqfd->kvm, 8332 prod->irq, irqfd->gsi, 1); 8333 } 8334 8335 return -EINVAL; 8336 } 8337 8338 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 8339 struct irq_bypass_producer *prod) 8340 { 8341 int ret; 8342 struct kvm_kernel_irqfd *irqfd = 8343 container_of(cons, struct kvm_kernel_irqfd, consumer); 8344 8345 if (!kvm_x86_ops->update_pi_irte) { 8346 WARN_ON(irqfd->producer != NULL); 8347 return; 8348 } 8349 8350 WARN_ON(irqfd->producer != prod); 8351 irqfd->producer = NULL; 8352 8353 /* 8354 * When producer of consumer is unregistered, we change back to 8355 * remapped mode, so we can re-use the current implementation 8356 * when the irq is masked/disabed or the consumer side (KVM 8357 * int this case doesn't want to receive the interrupts. 8358 */ 8359 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0); 8360 if (ret) 8361 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 8362 " fails: %d\n", irqfd->consumer.token, ret); 8363 } 8364 8365 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 8366 uint32_t guest_irq, bool set) 8367 { 8368 if (!kvm_x86_ops->update_pi_irte) 8369 return -EINVAL; 8370 8371 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set); 8372 } 8373 8374 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 8375 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 8376 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 8377 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 8378 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 8379 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 8380 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 8381 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 8382 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 8383 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 8384 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 8385 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 8386 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 8387 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 8388 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window); 8389 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 8390 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 8391