1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * derived from drivers/kvm/kvm_main.c 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright (C) 2008 Qumranet, Inc. 9 * Copyright IBM Corporation, 2008 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 11 * 12 * Authors: 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * Amit Shah <amit.shah@qumranet.com> 16 * Ben-Ami Yassour <benami@il.ibm.com> 17 */ 18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20 #include <linux/kvm_host.h> 21 #include "irq.h" 22 #include "ioapic.h" 23 #include "mmu.h" 24 #include "i8254.h" 25 #include "tss.h" 26 #include "kvm_cache_regs.h" 27 #include "kvm_emulate.h" 28 #include "mmu/page_track.h" 29 #include "x86.h" 30 #include "cpuid.h" 31 #include "pmu.h" 32 #include "hyperv.h" 33 #include "lapic.h" 34 #include "xen.h" 35 #include "smm.h" 36 37 #include <linux/clocksource.h> 38 #include <linux/interrupt.h> 39 #include <linux/kvm.h> 40 #include <linux/fs.h> 41 #include <linux/vmalloc.h> 42 #include <linux/export.h> 43 #include <linux/moduleparam.h> 44 #include <linux/mman.h> 45 #include <linux/highmem.h> 46 #include <linux/iommu.h> 47 #include <linux/cpufreq.h> 48 #include <linux/user-return-notifier.h> 49 #include <linux/srcu.h> 50 #include <linux/slab.h> 51 #include <linux/perf_event.h> 52 #include <linux/uaccess.h> 53 #include <linux/hash.h> 54 #include <linux/pci.h> 55 #include <linux/timekeeper_internal.h> 56 #include <linux/pvclock_gtod.h> 57 #include <linux/kvm_irqfd.h> 58 #include <linux/irqbypass.h> 59 #include <linux/sched/stat.h> 60 #include <linux/sched/isolation.h> 61 #include <linux/mem_encrypt.h> 62 #include <linux/entry-kvm.h> 63 #include <linux/suspend.h> 64 #include <linux/smp.h> 65 66 #include <trace/events/ipi.h> 67 #include <trace/events/kvm.h> 68 69 #include <asm/debugreg.h> 70 #include <asm/msr.h> 71 #include <asm/desc.h> 72 #include <asm/mce.h> 73 #include <asm/pkru.h> 74 #include <linux/kernel_stat.h> 75 #include <asm/fpu/api.h> 76 #include <asm/fpu/xcr.h> 77 #include <asm/fpu/xstate.h> 78 #include <asm/pvclock.h> 79 #include <asm/div64.h> 80 #include <asm/irq_remapping.h> 81 #include <asm/mshyperv.h> 82 #include <asm/hypervisor.h> 83 #include <asm/tlbflush.h> 84 #include <asm/intel_pt.h> 85 #include <asm/emulate_prefix.h> 86 #include <asm/sgx.h> 87 #include <clocksource/hyperv_timer.h> 88 89 #define CREATE_TRACE_POINTS 90 #include "trace.h" 91 92 #define MAX_IO_MSRS 256 93 #define KVM_MAX_MCE_BANKS 32 94 95 struct kvm_caps kvm_caps __read_mostly = { 96 .supported_mce_cap = MCG_CTL_P | MCG_SER_P, 97 }; 98 EXPORT_SYMBOL_GPL(kvm_caps); 99 100 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) 101 102 #define emul_to_vcpu(ctxt) \ 103 ((struct kvm_vcpu *)(ctxt)->vcpu) 104 105 /* EFER defaults: 106 * - enable syscall per default because its emulated by KVM 107 * - enable LME and LMA per default on 64 bit KVM 108 */ 109 #ifdef CONFIG_X86_64 110 static 111 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 112 #else 113 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 114 #endif 115 116 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; 117 118 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) 119 120 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE 121 122 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ 123 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 124 125 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 126 static void process_nmi(struct kvm_vcpu *vcpu); 127 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 128 static void store_regs(struct kvm_vcpu *vcpu); 129 static int sync_regs(struct kvm_vcpu *vcpu); 130 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu); 131 132 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 133 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); 134 135 static DEFINE_MUTEX(vendor_module_lock); 136 struct kvm_x86_ops kvm_x86_ops __read_mostly; 137 138 #define KVM_X86_OP(func) \ 139 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ 140 *(((struct kvm_x86_ops *)0)->func)); 141 #define KVM_X86_OP_OPTIONAL KVM_X86_OP 142 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP 143 #include <asm/kvm-x86-ops.h> 144 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); 145 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); 146 147 static bool __read_mostly ignore_msrs = 0; 148 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 149 150 bool __read_mostly report_ignored_msrs = true; 151 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); 152 EXPORT_SYMBOL_GPL(report_ignored_msrs); 153 154 unsigned int min_timer_period_us = 200; 155 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 156 157 static bool __read_mostly kvmclock_periodic_sync = true; 158 module_param(kvmclock_periodic_sync, bool, S_IRUGO); 159 160 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 161 static u32 __read_mostly tsc_tolerance_ppm = 250; 162 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 163 164 /* 165 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables 166 * adaptive tuning starting from default advancement of 1000ns. '0' disables 167 * advancement entirely. Any other value is used as-is and disables adaptive 168 * tuning, i.e. allows privileged userspace to set an exact advancement time. 169 */ 170 static int __read_mostly lapic_timer_advance_ns = -1; 171 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); 172 173 static bool __read_mostly vector_hashing = true; 174 module_param(vector_hashing, bool, S_IRUGO); 175 176 bool __read_mostly enable_vmware_backdoor = false; 177 module_param(enable_vmware_backdoor, bool, S_IRUGO); 178 EXPORT_SYMBOL_GPL(enable_vmware_backdoor); 179 180 /* 181 * Flags to manipulate forced emulation behavior (any non-zero value will 182 * enable forced emulation). 183 */ 184 #define KVM_FEP_CLEAR_RFLAGS_RF BIT(1) 185 static int __read_mostly force_emulation_prefix; 186 module_param(force_emulation_prefix, int, 0644); 187 188 int __read_mostly pi_inject_timer = -1; 189 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); 190 191 /* Enable/disable PMU virtualization */ 192 bool __read_mostly enable_pmu = true; 193 EXPORT_SYMBOL_GPL(enable_pmu); 194 module_param(enable_pmu, bool, 0444); 195 196 bool __read_mostly eager_page_split = true; 197 module_param(eager_page_split, bool, 0644); 198 199 /* Enable/disable SMT_RSB bug mitigation */ 200 static bool __read_mostly mitigate_smt_rsb; 201 module_param(mitigate_smt_rsb, bool, 0444); 202 203 /* 204 * Restoring the host value for MSRs that are only consumed when running in 205 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU 206 * returns to userspace, i.e. the kernel can run with the guest's value. 207 */ 208 #define KVM_MAX_NR_USER_RETURN_MSRS 16 209 210 struct kvm_user_return_msrs { 211 struct user_return_notifier urn; 212 bool registered; 213 struct kvm_user_return_msr_values { 214 u64 host; 215 u64 curr; 216 } values[KVM_MAX_NR_USER_RETURN_MSRS]; 217 }; 218 219 u32 __read_mostly kvm_nr_uret_msrs; 220 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); 221 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; 222 static struct kvm_user_return_msrs __percpu *user_return_msrs; 223 224 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ 225 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ 226 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ 227 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE) 228 229 u64 __read_mostly host_efer; 230 EXPORT_SYMBOL_GPL(host_efer); 231 232 bool __read_mostly allow_smaller_maxphyaddr = 0; 233 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); 234 235 bool __read_mostly enable_apicv = true; 236 EXPORT_SYMBOL_GPL(enable_apicv); 237 238 u64 __read_mostly host_xss; 239 EXPORT_SYMBOL_GPL(host_xss); 240 241 u64 __read_mostly host_arch_capabilities; 242 EXPORT_SYMBOL_GPL(host_arch_capabilities); 243 244 const struct _kvm_stats_desc kvm_vm_stats_desc[] = { 245 KVM_GENERIC_VM_STATS(), 246 STATS_DESC_COUNTER(VM, mmu_shadow_zapped), 247 STATS_DESC_COUNTER(VM, mmu_pte_write), 248 STATS_DESC_COUNTER(VM, mmu_pde_zapped), 249 STATS_DESC_COUNTER(VM, mmu_flooded), 250 STATS_DESC_COUNTER(VM, mmu_recycled), 251 STATS_DESC_COUNTER(VM, mmu_cache_miss), 252 STATS_DESC_ICOUNTER(VM, mmu_unsync), 253 STATS_DESC_ICOUNTER(VM, pages_4k), 254 STATS_DESC_ICOUNTER(VM, pages_2m), 255 STATS_DESC_ICOUNTER(VM, pages_1g), 256 STATS_DESC_ICOUNTER(VM, nx_lpage_splits), 257 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size), 258 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions) 259 }; 260 261 const struct kvm_stats_header kvm_vm_stats_header = { 262 .name_size = KVM_STATS_NAME_SIZE, 263 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), 264 .id_offset = sizeof(struct kvm_stats_header), 265 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 266 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 267 sizeof(kvm_vm_stats_desc), 268 }; 269 270 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { 271 KVM_GENERIC_VCPU_STATS(), 272 STATS_DESC_COUNTER(VCPU, pf_taken), 273 STATS_DESC_COUNTER(VCPU, pf_fixed), 274 STATS_DESC_COUNTER(VCPU, pf_emulate), 275 STATS_DESC_COUNTER(VCPU, pf_spurious), 276 STATS_DESC_COUNTER(VCPU, pf_fast), 277 STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created), 278 STATS_DESC_COUNTER(VCPU, pf_guest), 279 STATS_DESC_COUNTER(VCPU, tlb_flush), 280 STATS_DESC_COUNTER(VCPU, invlpg), 281 STATS_DESC_COUNTER(VCPU, exits), 282 STATS_DESC_COUNTER(VCPU, io_exits), 283 STATS_DESC_COUNTER(VCPU, mmio_exits), 284 STATS_DESC_COUNTER(VCPU, signal_exits), 285 STATS_DESC_COUNTER(VCPU, irq_window_exits), 286 STATS_DESC_COUNTER(VCPU, nmi_window_exits), 287 STATS_DESC_COUNTER(VCPU, l1d_flush), 288 STATS_DESC_COUNTER(VCPU, halt_exits), 289 STATS_DESC_COUNTER(VCPU, request_irq_exits), 290 STATS_DESC_COUNTER(VCPU, irq_exits), 291 STATS_DESC_COUNTER(VCPU, host_state_reload), 292 STATS_DESC_COUNTER(VCPU, fpu_reload), 293 STATS_DESC_COUNTER(VCPU, insn_emulation), 294 STATS_DESC_COUNTER(VCPU, insn_emulation_fail), 295 STATS_DESC_COUNTER(VCPU, hypercalls), 296 STATS_DESC_COUNTER(VCPU, irq_injections), 297 STATS_DESC_COUNTER(VCPU, nmi_injections), 298 STATS_DESC_COUNTER(VCPU, req_event), 299 STATS_DESC_COUNTER(VCPU, nested_run), 300 STATS_DESC_COUNTER(VCPU, directed_yield_attempted), 301 STATS_DESC_COUNTER(VCPU, directed_yield_successful), 302 STATS_DESC_COUNTER(VCPU, preemption_reported), 303 STATS_DESC_COUNTER(VCPU, preemption_other), 304 STATS_DESC_IBOOLEAN(VCPU, guest_mode), 305 STATS_DESC_COUNTER(VCPU, notify_window_exits), 306 }; 307 308 const struct kvm_stats_header kvm_vcpu_stats_header = { 309 .name_size = KVM_STATS_NAME_SIZE, 310 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), 311 .id_offset = sizeof(struct kvm_stats_header), 312 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 313 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 314 sizeof(kvm_vcpu_stats_desc), 315 }; 316 317 u64 __read_mostly host_xcr0; 318 319 static struct kmem_cache *x86_emulator_cache; 320 321 /* 322 * When called, it means the previous get/set msr reached an invalid msr. 323 * Return true if we want to ignore/silent this failed msr access. 324 */ 325 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) 326 { 327 const char *op = write ? "wrmsr" : "rdmsr"; 328 329 if (ignore_msrs) { 330 if (report_ignored_msrs) 331 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", 332 op, msr, data); 333 /* Mask the error */ 334 return true; 335 } else { 336 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", 337 op, msr, data); 338 return false; 339 } 340 } 341 342 static struct kmem_cache *kvm_alloc_emulator_cache(void) 343 { 344 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); 345 unsigned int size = sizeof(struct x86_emulate_ctxt); 346 347 return kmem_cache_create_usercopy("x86_emulator", size, 348 __alignof__(struct x86_emulate_ctxt), 349 SLAB_ACCOUNT, useroffset, 350 size - useroffset, NULL); 351 } 352 353 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 354 355 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 356 { 357 int i; 358 for (i = 0; i < ASYNC_PF_PER_VCPU; i++) 359 vcpu->arch.apf.gfns[i] = ~0; 360 } 361 362 static void kvm_on_user_return(struct user_return_notifier *urn) 363 { 364 unsigned slot; 365 struct kvm_user_return_msrs *msrs 366 = container_of(urn, struct kvm_user_return_msrs, urn); 367 struct kvm_user_return_msr_values *values; 368 unsigned long flags; 369 370 /* 371 * Disabling irqs at this point since the following code could be 372 * interrupted and executed through kvm_arch_hardware_disable() 373 */ 374 local_irq_save(flags); 375 if (msrs->registered) { 376 msrs->registered = false; 377 user_return_notifier_unregister(urn); 378 } 379 local_irq_restore(flags); 380 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { 381 values = &msrs->values[slot]; 382 if (values->host != values->curr) { 383 wrmsrl(kvm_uret_msrs_list[slot], values->host); 384 values->curr = values->host; 385 } 386 } 387 } 388 389 static int kvm_probe_user_return_msr(u32 msr) 390 { 391 u64 val; 392 int ret; 393 394 preempt_disable(); 395 ret = rdmsrl_safe(msr, &val); 396 if (ret) 397 goto out; 398 ret = wrmsrl_safe(msr, val); 399 out: 400 preempt_enable(); 401 return ret; 402 } 403 404 int kvm_add_user_return_msr(u32 msr) 405 { 406 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); 407 408 if (kvm_probe_user_return_msr(msr)) 409 return -1; 410 411 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; 412 return kvm_nr_uret_msrs++; 413 } 414 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); 415 416 int kvm_find_user_return_msr(u32 msr) 417 { 418 int i; 419 420 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 421 if (kvm_uret_msrs_list[i] == msr) 422 return i; 423 } 424 return -1; 425 } 426 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); 427 428 static void kvm_user_return_msr_cpu_online(void) 429 { 430 unsigned int cpu = smp_processor_id(); 431 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 432 u64 value; 433 int i; 434 435 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 436 rdmsrl_safe(kvm_uret_msrs_list[i], &value); 437 msrs->values[i].host = value; 438 msrs->values[i].curr = value; 439 } 440 } 441 442 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) 443 { 444 unsigned int cpu = smp_processor_id(); 445 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 446 int err; 447 448 value = (value & mask) | (msrs->values[slot].host & ~mask); 449 if (value == msrs->values[slot].curr) 450 return 0; 451 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); 452 if (err) 453 return 1; 454 455 msrs->values[slot].curr = value; 456 if (!msrs->registered) { 457 msrs->urn.on_user_return = kvm_on_user_return; 458 user_return_notifier_register(&msrs->urn); 459 msrs->registered = true; 460 } 461 return 0; 462 } 463 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); 464 465 static void drop_user_return_notifiers(void) 466 { 467 unsigned int cpu = smp_processor_id(); 468 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); 469 470 if (msrs->registered) 471 kvm_on_user_return(&msrs->urn); 472 } 473 474 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 475 { 476 return vcpu->arch.apic_base; 477 } 478 479 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) 480 { 481 return kvm_apic_mode(kvm_get_apic_base(vcpu)); 482 } 483 EXPORT_SYMBOL_GPL(kvm_get_apic_mode); 484 485 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 486 { 487 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); 488 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); 489 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | 490 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); 491 492 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) 493 return 1; 494 if (!msr_info->host_initiated) { 495 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) 496 return 1; 497 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) 498 return 1; 499 } 500 501 kvm_lapic_set_base(vcpu, msr_info->data); 502 kvm_recalculate_apic_map(vcpu->kvm); 503 return 0; 504 } 505 506 /* 507 * Handle a fault on a hardware virtualization (VMX or SVM) instruction. 508 * 509 * Hardware virtualization extension instructions may fault if a reboot turns 510 * off virtualization while processes are running. Usually after catching the 511 * fault we just panic; during reboot instead the instruction is ignored. 512 */ 513 noinstr void kvm_spurious_fault(void) 514 { 515 /* Fault while not rebooting. We want the trace. */ 516 BUG_ON(!kvm_rebooting); 517 } 518 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 519 520 #define EXCPT_BENIGN 0 521 #define EXCPT_CONTRIBUTORY 1 522 #define EXCPT_PF 2 523 524 static int exception_class(int vector) 525 { 526 switch (vector) { 527 case PF_VECTOR: 528 return EXCPT_PF; 529 case DE_VECTOR: 530 case TS_VECTOR: 531 case NP_VECTOR: 532 case SS_VECTOR: 533 case GP_VECTOR: 534 return EXCPT_CONTRIBUTORY; 535 default: 536 break; 537 } 538 return EXCPT_BENIGN; 539 } 540 541 #define EXCPT_FAULT 0 542 #define EXCPT_TRAP 1 543 #define EXCPT_ABORT 2 544 #define EXCPT_INTERRUPT 3 545 #define EXCPT_DB 4 546 547 static int exception_type(int vector) 548 { 549 unsigned int mask; 550 551 if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) 552 return EXCPT_INTERRUPT; 553 554 mask = 1 << vector; 555 556 /* 557 * #DBs can be trap-like or fault-like, the caller must check other CPU 558 * state, e.g. DR6, to determine whether a #DB is a trap or fault. 559 */ 560 if (mask & (1 << DB_VECTOR)) 561 return EXCPT_DB; 562 563 if (mask & ((1 << BP_VECTOR) | (1 << OF_VECTOR))) 564 return EXCPT_TRAP; 565 566 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) 567 return EXCPT_ABORT; 568 569 /* Reserved exceptions will result in fault */ 570 return EXCPT_FAULT; 571 } 572 573 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu, 574 struct kvm_queued_exception *ex) 575 { 576 if (!ex->has_payload) 577 return; 578 579 switch (ex->vector) { 580 case DB_VECTOR: 581 /* 582 * "Certain debug exceptions may clear bit 0-3. The 583 * remaining contents of the DR6 register are never 584 * cleared by the processor". 585 */ 586 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 587 /* 588 * In order to reflect the #DB exception payload in guest 589 * dr6, three components need to be considered: active low 590 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, 591 * DR6_BS and DR6_BT) 592 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. 593 * In the target guest dr6: 594 * FIXED_1 bits should always be set. 595 * Active low bits should be cleared if 1-setting in payload. 596 * Active high bits should be set if 1-setting in payload. 597 * 598 * Note, the payload is compatible with the pending debug 599 * exceptions/exit qualification under VMX, that active_low bits 600 * are active high in payload. 601 * So they need to be flipped for DR6. 602 */ 603 vcpu->arch.dr6 |= DR6_ACTIVE_LOW; 604 vcpu->arch.dr6 |= ex->payload; 605 vcpu->arch.dr6 ^= ex->payload & DR6_ACTIVE_LOW; 606 607 /* 608 * The #DB payload is defined as compatible with the 'pending 609 * debug exceptions' field under VMX, not DR6. While bit 12 is 610 * defined in the 'pending debug exceptions' field (enabled 611 * breakpoint), it is reserved and must be zero in DR6. 612 */ 613 vcpu->arch.dr6 &= ~BIT(12); 614 break; 615 case PF_VECTOR: 616 vcpu->arch.cr2 = ex->payload; 617 break; 618 } 619 620 ex->has_payload = false; 621 ex->payload = 0; 622 } 623 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); 624 625 static void kvm_queue_exception_vmexit(struct kvm_vcpu *vcpu, unsigned int vector, 626 bool has_error_code, u32 error_code, 627 bool has_payload, unsigned long payload) 628 { 629 struct kvm_queued_exception *ex = &vcpu->arch.exception_vmexit; 630 631 ex->vector = vector; 632 ex->injected = false; 633 ex->pending = true; 634 ex->has_error_code = has_error_code; 635 ex->error_code = error_code; 636 ex->has_payload = has_payload; 637 ex->payload = payload; 638 } 639 640 /* Forcibly leave the nested mode in cases like a vCPU reset */ 641 static void kvm_leave_nested(struct kvm_vcpu *vcpu) 642 { 643 kvm_x86_ops.nested_ops->leave_nested(vcpu); 644 } 645 646 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 647 unsigned nr, bool has_error, u32 error_code, 648 bool has_payload, unsigned long payload, bool reinject) 649 { 650 u32 prev_nr; 651 int class1, class2; 652 653 kvm_make_request(KVM_REQ_EVENT, vcpu); 654 655 /* 656 * If the exception is destined for L2 and isn't being reinjected, 657 * morph it to a VM-Exit if L1 wants to intercept the exception. A 658 * previously injected exception is not checked because it was checked 659 * when it was original queued, and re-checking is incorrect if _L1_ 660 * injected the exception, in which case it's exempt from interception. 661 */ 662 if (!reinject && is_guest_mode(vcpu) && 663 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, nr, error_code)) { 664 kvm_queue_exception_vmexit(vcpu, nr, has_error, error_code, 665 has_payload, payload); 666 return; 667 } 668 669 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { 670 queue: 671 if (reinject) { 672 /* 673 * On VM-Entry, an exception can be pending if and only 674 * if event injection was blocked by nested_run_pending. 675 * In that case, however, vcpu_enter_guest() requests an 676 * immediate exit, and the guest shouldn't proceed far 677 * enough to need reinjection. 678 */ 679 WARN_ON_ONCE(kvm_is_exception_pending(vcpu)); 680 vcpu->arch.exception.injected = true; 681 if (WARN_ON_ONCE(has_payload)) { 682 /* 683 * A reinjected event has already 684 * delivered its payload. 685 */ 686 has_payload = false; 687 payload = 0; 688 } 689 } else { 690 vcpu->arch.exception.pending = true; 691 vcpu->arch.exception.injected = false; 692 } 693 vcpu->arch.exception.has_error_code = has_error; 694 vcpu->arch.exception.vector = nr; 695 vcpu->arch.exception.error_code = error_code; 696 vcpu->arch.exception.has_payload = has_payload; 697 vcpu->arch.exception.payload = payload; 698 if (!is_guest_mode(vcpu)) 699 kvm_deliver_exception_payload(vcpu, 700 &vcpu->arch.exception); 701 return; 702 } 703 704 /* to check exception */ 705 prev_nr = vcpu->arch.exception.vector; 706 if (prev_nr == DF_VECTOR) { 707 /* triple fault -> shutdown */ 708 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 709 return; 710 } 711 class1 = exception_class(prev_nr); 712 class2 = exception_class(nr); 713 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) || 714 (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 715 /* 716 * Synthesize #DF. Clear the previously injected or pending 717 * exception so as not to incorrectly trigger shutdown. 718 */ 719 vcpu->arch.exception.injected = false; 720 vcpu->arch.exception.pending = false; 721 722 kvm_queue_exception_e(vcpu, DF_VECTOR, 0); 723 } else { 724 /* replace previous exception with a new one in a hope 725 that instruction re-execution will regenerate lost 726 exception */ 727 goto queue; 728 } 729 } 730 731 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 732 { 733 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); 734 } 735 EXPORT_SYMBOL_GPL(kvm_queue_exception); 736 737 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 738 { 739 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); 740 } 741 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 742 743 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, 744 unsigned long payload) 745 { 746 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); 747 } 748 EXPORT_SYMBOL_GPL(kvm_queue_exception_p); 749 750 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, 751 u32 error_code, unsigned long payload) 752 { 753 kvm_multiple_exception(vcpu, nr, true, error_code, 754 true, payload, false); 755 } 756 757 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 758 { 759 if (err) 760 kvm_inject_gp(vcpu, 0); 761 else 762 return kvm_skip_emulated_instruction(vcpu); 763 764 return 1; 765 } 766 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 767 768 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err) 769 { 770 if (err) { 771 kvm_inject_gp(vcpu, 0); 772 return 1; 773 } 774 775 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP | 776 EMULTYPE_COMPLETE_USER_EXIT); 777 } 778 779 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 780 { 781 ++vcpu->stat.pf_guest; 782 783 /* 784 * Async #PF in L2 is always forwarded to L1 as a VM-Exit regardless of 785 * whether or not L1 wants to intercept "regular" #PF. 786 */ 787 if (is_guest_mode(vcpu) && fault->async_page_fault) 788 kvm_queue_exception_vmexit(vcpu, PF_VECTOR, 789 true, fault->error_code, 790 true, fault->address); 791 else 792 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, 793 fault->address); 794 } 795 796 void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, 797 struct x86_exception *fault) 798 { 799 struct kvm_mmu *fault_mmu; 800 WARN_ON_ONCE(fault->vector != PF_VECTOR); 801 802 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : 803 vcpu->arch.walk_mmu; 804 805 /* 806 * Invalidate the TLB entry for the faulting address, if it exists, 807 * else the access will fault indefinitely (and to emulate hardware). 808 */ 809 if ((fault->error_code & PFERR_PRESENT_MASK) && 810 !(fault->error_code & PFERR_RSVD_MASK)) 811 kvm_mmu_invalidate_addr(vcpu, fault_mmu, fault->address, 812 KVM_MMU_ROOT_CURRENT); 813 814 fault_mmu->inject_page_fault(vcpu, fault); 815 } 816 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); 817 818 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 819 { 820 atomic_inc(&vcpu->arch.nmi_queued); 821 kvm_make_request(KVM_REQ_NMI, vcpu); 822 } 823 824 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 825 { 826 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); 827 } 828 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 829 830 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 831 { 832 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); 833 } 834 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 835 836 /* 837 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 838 * a #GP and return false. 839 */ 840 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 841 { 842 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) 843 return true; 844 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 845 return false; 846 } 847 848 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) 849 { 850 if ((dr != 4 && dr != 5) || !kvm_is_cr4_bit_set(vcpu, X86_CR4_DE)) 851 return true; 852 853 kvm_queue_exception(vcpu, UD_VECTOR); 854 return false; 855 } 856 EXPORT_SYMBOL_GPL(kvm_require_dr); 857 858 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) 859 { 860 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); 861 } 862 863 /* 864 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. 865 */ 866 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3) 867 { 868 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 869 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 870 gpa_t real_gpa; 871 int i; 872 int ret; 873 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 874 875 /* 876 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated 877 * to an L1 GPA. 878 */ 879 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn), 880 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL); 881 if (real_gpa == INVALID_GPA) 882 return 0; 883 884 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */ 885 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte, 886 cr3 & GENMASK(11, 5), sizeof(pdpte)); 887 if (ret < 0) 888 return 0; 889 890 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 891 if ((pdpte[i] & PT_PRESENT_MASK) && 892 (pdpte[i] & pdptr_rsvd_bits(vcpu))) { 893 return 0; 894 } 895 } 896 897 /* 898 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled. 899 * Shadow page roots need to be reconstructed instead. 900 */ 901 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs))) 902 kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT); 903 904 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 905 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 906 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); 907 vcpu->arch.pdptrs_from_userspace = false; 908 909 return 1; 910 } 911 EXPORT_SYMBOL_GPL(load_pdptrs); 912 913 static bool kvm_is_valid_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 914 { 915 #ifdef CONFIG_X86_64 916 if (cr0 & 0xffffffff00000000UL) 917 return false; 918 #endif 919 920 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 921 return false; 922 923 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 924 return false; 925 926 return static_call(kvm_x86_is_valid_cr0)(vcpu, cr0); 927 } 928 929 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) 930 { 931 /* 932 * CR0.WP is incorporated into the MMU role, but only for non-nested, 933 * indirect shadow MMUs. If paging is disabled, no updates are needed 934 * as there are no permission bits to emulate. If TDP is enabled, the 935 * MMU's metadata needs to be updated, e.g. so that emulating guest 936 * translations does the right thing, but there's no need to unload the 937 * root as CR0.WP doesn't affect SPTEs. 938 */ 939 if ((cr0 ^ old_cr0) == X86_CR0_WP) { 940 if (!(cr0 & X86_CR0_PG)) 941 return; 942 943 if (tdp_enabled) { 944 kvm_init_mmu(vcpu); 945 return; 946 } 947 } 948 949 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 950 kvm_clear_async_pf_completion_queue(vcpu); 951 kvm_async_pf_hash_reset(vcpu); 952 953 /* 954 * Clearing CR0.PG is defined to flush the TLB from the guest's 955 * perspective. 956 */ 957 if (!(cr0 & X86_CR0_PG)) 958 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 959 } 960 961 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS) 962 kvm_mmu_reset_context(vcpu); 963 964 if (((cr0 ^ old_cr0) & X86_CR0_CD) && 965 kvm_arch_has_noncoherent_dma(vcpu->kvm) && 966 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 967 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); 968 } 969 EXPORT_SYMBOL_GPL(kvm_post_set_cr0); 970 971 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 972 { 973 unsigned long old_cr0 = kvm_read_cr0(vcpu); 974 975 if (!kvm_is_valid_cr0(vcpu, cr0)) 976 return 1; 977 978 cr0 |= X86_CR0_ET; 979 980 /* Write to CR0 reserved bits are ignored, even on Intel. */ 981 cr0 &= ~CR0_RESERVED_BITS; 982 983 #ifdef CONFIG_X86_64 984 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && 985 (cr0 & X86_CR0_PG)) { 986 int cs_db, cs_l; 987 988 if (!is_pae(vcpu)) 989 return 1; 990 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 991 if (cs_l) 992 return 1; 993 } 994 #endif 995 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && 996 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) && 997 !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) 998 return 1; 999 1000 if (!(cr0 & X86_CR0_PG) && 1001 (is_64_bit_mode(vcpu) || kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE))) 1002 return 1; 1003 1004 static_call(kvm_x86_set_cr0)(vcpu, cr0); 1005 1006 kvm_post_set_cr0(vcpu, old_cr0, cr0); 1007 1008 return 0; 1009 } 1010 EXPORT_SYMBOL_GPL(kvm_set_cr0); 1011 1012 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 1013 { 1014 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 1015 } 1016 EXPORT_SYMBOL_GPL(kvm_lmsw); 1017 1018 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) 1019 { 1020 if (vcpu->arch.guest_state_protected) 1021 return; 1022 1023 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) { 1024 1025 if (vcpu->arch.xcr0 != host_xcr0) 1026 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 1027 1028 if (guest_can_use(vcpu, X86_FEATURE_XSAVES) && 1029 vcpu->arch.ia32_xss != host_xss) 1030 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 1031 } 1032 1033 if (cpu_feature_enabled(X86_FEATURE_PKU) && 1034 vcpu->arch.pkru != vcpu->arch.host_pkru && 1035 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) || 1036 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE))) 1037 write_pkru(vcpu->arch.pkru); 1038 } 1039 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); 1040 1041 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) 1042 { 1043 if (vcpu->arch.guest_state_protected) 1044 return; 1045 1046 if (cpu_feature_enabled(X86_FEATURE_PKU) && 1047 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) || 1048 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE))) { 1049 vcpu->arch.pkru = rdpkru(); 1050 if (vcpu->arch.pkru != vcpu->arch.host_pkru) 1051 write_pkru(vcpu->arch.host_pkru); 1052 } 1053 1054 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) { 1055 1056 if (vcpu->arch.xcr0 != host_xcr0) 1057 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 1058 1059 if (guest_can_use(vcpu, X86_FEATURE_XSAVES) && 1060 vcpu->arch.ia32_xss != host_xss) 1061 wrmsrl(MSR_IA32_XSS, host_xss); 1062 } 1063 1064 } 1065 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); 1066 1067 #ifdef CONFIG_X86_64 1068 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu) 1069 { 1070 return vcpu->arch.guest_supported_xcr0 & XFEATURE_MASK_USER_DYNAMIC; 1071 } 1072 #endif 1073 1074 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 1075 { 1076 u64 xcr0 = xcr; 1077 u64 old_xcr0 = vcpu->arch.xcr0; 1078 u64 valid_bits; 1079 1080 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 1081 if (index != XCR_XFEATURE_ENABLED_MASK) 1082 return 1; 1083 if (!(xcr0 & XFEATURE_MASK_FP)) 1084 return 1; 1085 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) 1086 return 1; 1087 1088 /* 1089 * Do not allow the guest to set bits that we do not support 1090 * saving. However, xcr0 bit 0 is always set, even if the 1091 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()). 1092 */ 1093 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP; 1094 if (xcr0 & ~valid_bits) 1095 return 1; 1096 1097 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != 1098 (!(xcr0 & XFEATURE_MASK_BNDCSR))) 1099 return 1; 1100 1101 if (xcr0 & XFEATURE_MASK_AVX512) { 1102 if (!(xcr0 & XFEATURE_MASK_YMM)) 1103 return 1; 1104 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) 1105 return 1; 1106 } 1107 1108 if ((xcr0 & XFEATURE_MASK_XTILE) && 1109 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE)) 1110 return 1; 1111 1112 vcpu->arch.xcr0 = xcr0; 1113 1114 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) 1115 kvm_update_cpuid_runtime(vcpu); 1116 return 0; 1117 } 1118 1119 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) 1120 { 1121 /* Note, #UD due to CR4.OSXSAVE=0 has priority over the intercept. */ 1122 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || 1123 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { 1124 kvm_inject_gp(vcpu, 0); 1125 return 1; 1126 } 1127 1128 return kvm_skip_emulated_instruction(vcpu); 1129 } 1130 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); 1131 1132 bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1133 { 1134 if (cr4 & cr4_reserved_bits) 1135 return false; 1136 1137 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) 1138 return false; 1139 1140 return true; 1141 } 1142 EXPORT_SYMBOL_GPL(__kvm_is_valid_cr4); 1143 1144 static bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1145 { 1146 return __kvm_is_valid_cr4(vcpu, cr4) && 1147 static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); 1148 } 1149 1150 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) 1151 { 1152 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) 1153 kvm_mmu_reset_context(vcpu); 1154 1155 /* 1156 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB 1157 * according to the SDM; however, stale prev_roots could be reused 1158 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we 1159 * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST 1160 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed, 1161 * so fall through. 1162 */ 1163 if (!tdp_enabled && 1164 (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) 1165 kvm_mmu_unload(vcpu); 1166 1167 /* 1168 * The TLB has to be flushed for all PCIDs if any of the following 1169 * (architecturally required) changes happen: 1170 * - CR4.PCIDE is changed from 1 to 0 1171 * - CR4.PGE is toggled 1172 * 1173 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT. 1174 */ 1175 if (((cr4 ^ old_cr4) & X86_CR4_PGE) || 1176 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 1177 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1178 1179 /* 1180 * The TLB has to be flushed for the current PCID if any of the 1181 * following (architecturally required) changes happen: 1182 * - CR4.SMEP is changed from 0 to 1 1183 * - CR4.PAE is toggled 1184 */ 1185 else if (((cr4 ^ old_cr4) & X86_CR4_PAE) || 1186 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP))) 1187 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1188 1189 } 1190 EXPORT_SYMBOL_GPL(kvm_post_set_cr4); 1191 1192 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 1193 { 1194 unsigned long old_cr4 = kvm_read_cr4(vcpu); 1195 1196 if (!kvm_is_valid_cr4(vcpu, cr4)) 1197 return 1; 1198 1199 if (is_long_mode(vcpu)) { 1200 if (!(cr4 & X86_CR4_PAE)) 1201 return 1; 1202 if ((cr4 ^ old_cr4) & X86_CR4_LA57) 1203 return 1; 1204 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 1205 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS) 1206 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) 1207 return 1; 1208 1209 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 1210 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 1211 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 1212 return 1; 1213 } 1214 1215 static_call(kvm_x86_set_cr4)(vcpu, cr4); 1216 1217 kvm_post_set_cr4(vcpu, old_cr4, cr4); 1218 1219 return 0; 1220 } 1221 EXPORT_SYMBOL_GPL(kvm_set_cr4); 1222 1223 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) 1224 { 1225 struct kvm_mmu *mmu = vcpu->arch.mmu; 1226 unsigned long roots_to_free = 0; 1227 int i; 1228 1229 /* 1230 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but 1231 * this is reachable when running EPT=1 and unrestricted_guest=0, and 1232 * also via the emulator. KVM's TDP page tables are not in the scope of 1233 * the invalidation, but the guest's TLB entries need to be flushed as 1234 * the CPU may have cached entries in its TLB for the target PCID. 1235 */ 1236 if (unlikely(tdp_enabled)) { 1237 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 1238 return; 1239 } 1240 1241 /* 1242 * If neither the current CR3 nor any of the prev_roots use the given 1243 * PCID, then nothing needs to be done here because a resync will 1244 * happen anyway before switching to any other CR3. 1245 */ 1246 if (kvm_get_active_pcid(vcpu) == pcid) { 1247 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); 1248 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 1249 } 1250 1251 /* 1252 * If PCID is disabled, there is no need to free prev_roots even if the 1253 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB 1254 * with PCIDE=0. 1255 */ 1256 if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)) 1257 return; 1258 1259 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 1260 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid) 1261 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 1262 1263 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free); 1264 } 1265 1266 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 1267 { 1268 bool skip_tlb_flush = false; 1269 unsigned long pcid = 0; 1270 #ifdef CONFIG_X86_64 1271 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)) { 1272 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; 1273 cr3 &= ~X86_CR3_PCID_NOFLUSH; 1274 pcid = cr3 & X86_CR3_PCID_MASK; 1275 } 1276 #endif 1277 1278 /* PDPTRs are always reloaded for PAE paging. */ 1279 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) 1280 goto handle_tlb_flush; 1281 1282 /* 1283 * Do not condition the GPA check on long mode, this helper is used to 1284 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that 1285 * the current vCPU mode is accurate. 1286 */ 1287 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) 1288 return 1; 1289 1290 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3)) 1291 return 1; 1292 1293 if (cr3 != kvm_read_cr3(vcpu)) 1294 kvm_mmu_new_pgd(vcpu, cr3); 1295 1296 vcpu->arch.cr3 = cr3; 1297 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 1298 /* Do not call post_set_cr3, we do not get here for confidential guests. */ 1299 1300 handle_tlb_flush: 1301 /* 1302 * A load of CR3 that flushes the TLB flushes only the current PCID, 1303 * even if PCID is disabled, in which case PCID=0 is flushed. It's a 1304 * moot point in the end because _disabling_ PCID will flush all PCIDs, 1305 * and it's impossible to use a non-zero PCID when PCID is disabled, 1306 * i.e. only PCID=0 can be relevant. 1307 */ 1308 if (!skip_tlb_flush) 1309 kvm_invalidate_pcid(vcpu, pcid); 1310 1311 return 0; 1312 } 1313 EXPORT_SYMBOL_GPL(kvm_set_cr3); 1314 1315 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 1316 { 1317 if (cr8 & CR8_RESERVED_BITS) 1318 return 1; 1319 if (lapic_in_kernel(vcpu)) 1320 kvm_lapic_set_tpr(vcpu, cr8); 1321 else 1322 vcpu->arch.cr8 = cr8; 1323 return 0; 1324 } 1325 EXPORT_SYMBOL_GPL(kvm_set_cr8); 1326 1327 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 1328 { 1329 if (lapic_in_kernel(vcpu)) 1330 return kvm_lapic_get_cr8(vcpu); 1331 else 1332 return vcpu->arch.cr8; 1333 } 1334 EXPORT_SYMBOL_GPL(kvm_get_cr8); 1335 1336 static void kvm_update_dr0123(struct kvm_vcpu *vcpu) 1337 { 1338 int i; 1339 1340 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { 1341 for (i = 0; i < KVM_NR_DB_REGS; i++) 1342 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 1343 } 1344 } 1345 1346 void kvm_update_dr7(struct kvm_vcpu *vcpu) 1347 { 1348 unsigned long dr7; 1349 1350 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 1351 dr7 = vcpu->arch.guest_debug_dr7; 1352 else 1353 dr7 = vcpu->arch.dr7; 1354 static_call(kvm_x86_set_dr7)(vcpu, dr7); 1355 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 1356 if (dr7 & DR7_BP_EN_MASK) 1357 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 1358 } 1359 EXPORT_SYMBOL_GPL(kvm_update_dr7); 1360 1361 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) 1362 { 1363 u64 fixed = DR6_FIXED_1; 1364 1365 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) 1366 fixed |= DR6_RTM; 1367 1368 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) 1369 fixed |= DR6_BUS_LOCK; 1370 return fixed; 1371 } 1372 1373 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 1374 { 1375 size_t size = ARRAY_SIZE(vcpu->arch.db); 1376 1377 switch (dr) { 1378 case 0 ... 3: 1379 vcpu->arch.db[array_index_nospec(dr, size)] = val; 1380 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 1381 vcpu->arch.eff_db[dr] = val; 1382 break; 1383 case 4: 1384 case 6: 1385 if (!kvm_dr6_valid(val)) 1386 return 1; /* #GP */ 1387 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); 1388 break; 1389 case 5: 1390 default: /* 7 */ 1391 if (!kvm_dr7_valid(val)) 1392 return 1; /* #GP */ 1393 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 1394 kvm_update_dr7(vcpu); 1395 break; 1396 } 1397 1398 return 0; 1399 } 1400 EXPORT_SYMBOL_GPL(kvm_set_dr); 1401 1402 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 1403 { 1404 size_t size = ARRAY_SIZE(vcpu->arch.db); 1405 1406 switch (dr) { 1407 case 0 ... 3: 1408 *val = vcpu->arch.db[array_index_nospec(dr, size)]; 1409 break; 1410 case 4: 1411 case 6: 1412 *val = vcpu->arch.dr6; 1413 break; 1414 case 5: 1415 default: /* 7 */ 1416 *val = vcpu->arch.dr7; 1417 break; 1418 } 1419 } 1420 EXPORT_SYMBOL_GPL(kvm_get_dr); 1421 1422 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) 1423 { 1424 u32 ecx = kvm_rcx_read(vcpu); 1425 u64 data; 1426 1427 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { 1428 kvm_inject_gp(vcpu, 0); 1429 return 1; 1430 } 1431 1432 kvm_rax_write(vcpu, (u32)data); 1433 kvm_rdx_write(vcpu, data >> 32); 1434 return kvm_skip_emulated_instruction(vcpu); 1435 } 1436 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); 1437 1438 /* 1439 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) track 1440 * the set of MSRs that KVM exposes to userspace through KVM_GET_MSRS, 1441 * KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. msrs_to_save holds MSRs that 1442 * require host support, i.e. should be probed via RDMSR. emulated_msrs holds 1443 * MSRs that KVM emulates without strictly requiring host support. 1444 * msr_based_features holds MSRs that enumerate features, i.e. are effectively 1445 * CPUID leafs. Note, msr_based_features isn't mutually exclusive with 1446 * msrs_to_save and emulated_msrs. 1447 */ 1448 1449 static const u32 msrs_to_save_base[] = { 1450 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 1451 MSR_STAR, 1452 #ifdef CONFIG_X86_64 1453 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 1454 #endif 1455 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 1456 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, 1457 MSR_IA32_SPEC_CTRL, MSR_IA32_TSX_CTRL, 1458 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, 1459 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, 1460 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, 1461 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, 1462 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, 1463 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, 1464 MSR_IA32_UMWAIT_CONTROL, 1465 1466 MSR_IA32_XFD, MSR_IA32_XFD_ERR, 1467 }; 1468 1469 static const u32 msrs_to_save_pmu[] = { 1470 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, 1471 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, 1472 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, 1473 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 1474 MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, 1475 1476 /* This part of MSRs should match KVM_INTEL_PMC_MAX_GENERIC. */ 1477 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, 1478 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, 1479 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, 1480 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, 1481 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, 1482 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, 1483 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, 1484 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, 1485 1486 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3, 1487 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3, 1488 1489 /* This part of MSRs should match KVM_AMD_PMC_MAX_GENERIC. */ 1490 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2, 1491 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, 1492 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, 1493 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, 1494 1495 MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 1496 MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, 1497 MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, 1498 }; 1499 1500 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_base) + 1501 ARRAY_SIZE(msrs_to_save_pmu)]; 1502 static unsigned num_msrs_to_save; 1503 1504 static const u32 emulated_msrs_all[] = { 1505 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 1506 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 1507 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 1508 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 1509 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, 1510 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, 1511 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, 1512 HV_X64_MSR_RESET, 1513 HV_X64_MSR_VP_INDEX, 1514 HV_X64_MSR_VP_RUNTIME, 1515 HV_X64_MSR_SCONTROL, 1516 HV_X64_MSR_STIMER0_CONFIG, 1517 HV_X64_MSR_VP_ASSIST_PAGE, 1518 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, 1519 HV_X64_MSR_TSC_EMULATION_STATUS, HV_X64_MSR_TSC_INVARIANT_CONTROL, 1520 HV_X64_MSR_SYNDBG_OPTIONS, 1521 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, 1522 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, 1523 HV_X64_MSR_SYNDBG_PENDING_BUFFER, 1524 1525 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 1526 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, 1527 1528 MSR_IA32_TSC_ADJUST, 1529 MSR_IA32_TSC_DEADLINE, 1530 MSR_IA32_ARCH_CAPABILITIES, 1531 MSR_IA32_PERF_CAPABILITIES, 1532 MSR_IA32_MISC_ENABLE, 1533 MSR_IA32_MCG_STATUS, 1534 MSR_IA32_MCG_CTL, 1535 MSR_IA32_MCG_EXT_CTL, 1536 MSR_IA32_SMBASE, 1537 MSR_SMI_COUNT, 1538 MSR_PLATFORM_INFO, 1539 MSR_MISC_FEATURES_ENABLES, 1540 MSR_AMD64_VIRT_SPEC_CTRL, 1541 MSR_AMD64_TSC_RATIO, 1542 MSR_IA32_POWER_CTL, 1543 MSR_IA32_UCODE_REV, 1544 1545 /* 1546 * KVM always supports the "true" VMX control MSRs, even if the host 1547 * does not. The VMX MSRs as a whole are considered "emulated" as KVM 1548 * doesn't strictly require them to exist in the host (ignoring that 1549 * KVM would refuse to load in the first place if the core set of MSRs 1550 * aren't supported). 1551 */ 1552 MSR_IA32_VMX_BASIC, 1553 MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1554 MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1555 MSR_IA32_VMX_TRUE_EXIT_CTLS, 1556 MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1557 MSR_IA32_VMX_MISC, 1558 MSR_IA32_VMX_CR0_FIXED0, 1559 MSR_IA32_VMX_CR4_FIXED0, 1560 MSR_IA32_VMX_VMCS_ENUM, 1561 MSR_IA32_VMX_PROCBASED_CTLS2, 1562 MSR_IA32_VMX_EPT_VPID_CAP, 1563 MSR_IA32_VMX_VMFUNC, 1564 1565 MSR_K7_HWCR, 1566 MSR_KVM_POLL_CONTROL, 1567 }; 1568 1569 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; 1570 static unsigned num_emulated_msrs; 1571 1572 /* 1573 * List of MSRs that control the existence of MSR-based features, i.e. MSRs 1574 * that are effectively CPUID leafs. VMX MSRs are also included in the set of 1575 * feature MSRs, but are handled separately to allow expedited lookups. 1576 */ 1577 static const u32 msr_based_features_all_except_vmx[] = { 1578 MSR_AMD64_DE_CFG, 1579 MSR_IA32_UCODE_REV, 1580 MSR_IA32_ARCH_CAPABILITIES, 1581 MSR_IA32_PERF_CAPABILITIES, 1582 }; 1583 1584 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all_except_vmx) + 1585 (KVM_LAST_EMULATED_VMX_MSR - KVM_FIRST_EMULATED_VMX_MSR + 1)]; 1586 static unsigned int num_msr_based_features; 1587 1588 /* 1589 * All feature MSRs except uCode revID, which tracks the currently loaded uCode 1590 * patch, are immutable once the vCPU model is defined. 1591 */ 1592 static bool kvm_is_immutable_feature_msr(u32 msr) 1593 { 1594 int i; 1595 1596 if (msr >= KVM_FIRST_EMULATED_VMX_MSR && msr <= KVM_LAST_EMULATED_VMX_MSR) 1597 return true; 1598 1599 for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++) { 1600 if (msr == msr_based_features_all_except_vmx[i]) 1601 return msr != MSR_IA32_UCODE_REV; 1602 } 1603 1604 return false; 1605 } 1606 1607 /* 1608 * Some IA32_ARCH_CAPABILITIES bits have dependencies on MSRs that KVM 1609 * does not yet virtualize. These include: 1610 * 10 - MISC_PACKAGE_CTRLS 1611 * 11 - ENERGY_FILTERING_CTL 1612 * 12 - DOITM 1613 * 18 - FB_CLEAR_CTRL 1614 * 21 - XAPIC_DISABLE_STATUS 1615 * 23 - OVERCLOCKING_STATUS 1616 */ 1617 1618 #define KVM_SUPPORTED_ARCH_CAP \ 1619 (ARCH_CAP_RDCL_NO | ARCH_CAP_IBRS_ALL | ARCH_CAP_RSBA | \ 1620 ARCH_CAP_SKIP_VMENTRY_L1DFLUSH | ARCH_CAP_SSB_NO | ARCH_CAP_MDS_NO | \ 1621 ARCH_CAP_PSCHANGE_MC_NO | ARCH_CAP_TSX_CTRL_MSR | ARCH_CAP_TAA_NO | \ 1622 ARCH_CAP_SBDR_SSDP_NO | ARCH_CAP_FBSDP_NO | ARCH_CAP_PSDP_NO | \ 1623 ARCH_CAP_FB_CLEAR | ARCH_CAP_RRSBA | ARCH_CAP_PBRSB_NO | ARCH_CAP_GDS_NO) 1624 1625 static u64 kvm_get_arch_capabilities(void) 1626 { 1627 u64 data = host_arch_capabilities & KVM_SUPPORTED_ARCH_CAP; 1628 1629 /* 1630 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that 1631 * the nested hypervisor runs with NX huge pages. If it is not, 1632 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other 1633 * L1 guests, so it need not worry about its own (L2) guests. 1634 */ 1635 data |= ARCH_CAP_PSCHANGE_MC_NO; 1636 1637 /* 1638 * If we're doing cache flushes (either "always" or "cond") 1639 * we will do one whenever the guest does a vmlaunch/vmresume. 1640 * If an outer hypervisor is doing the cache flush for us 1641 * (ARCH_CAP_SKIP_VMENTRY_L1DFLUSH), we can safely pass that 1642 * capability to the guest too, and if EPT is disabled we're not 1643 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will 1644 * require a nested hypervisor to do a flush of its own. 1645 */ 1646 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) 1647 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; 1648 1649 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) 1650 data |= ARCH_CAP_RDCL_NO; 1651 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1652 data |= ARCH_CAP_SSB_NO; 1653 if (!boot_cpu_has_bug(X86_BUG_MDS)) 1654 data |= ARCH_CAP_MDS_NO; 1655 1656 if (!boot_cpu_has(X86_FEATURE_RTM)) { 1657 /* 1658 * If RTM=0 because the kernel has disabled TSX, the host might 1659 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 1660 * and therefore knows that there cannot be TAA) but keep 1661 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, 1662 * and we want to allow migrating those guests to tsx=off hosts. 1663 */ 1664 data &= ~ARCH_CAP_TAA_NO; 1665 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { 1666 data |= ARCH_CAP_TAA_NO; 1667 } else { 1668 /* 1669 * Nothing to do here; we emulate TSX_CTRL if present on the 1670 * host so the guest can choose between disabling TSX or 1671 * using VERW to clear CPU buffers. 1672 */ 1673 } 1674 1675 if (!boot_cpu_has_bug(X86_BUG_GDS) || gds_ucode_mitigated()) 1676 data |= ARCH_CAP_GDS_NO; 1677 1678 return data; 1679 } 1680 1681 static int kvm_get_msr_feature(struct kvm_msr_entry *msr) 1682 { 1683 switch (msr->index) { 1684 case MSR_IA32_ARCH_CAPABILITIES: 1685 msr->data = kvm_get_arch_capabilities(); 1686 break; 1687 case MSR_IA32_PERF_CAPABILITIES: 1688 msr->data = kvm_caps.supported_perf_cap; 1689 break; 1690 case MSR_IA32_UCODE_REV: 1691 rdmsrl_safe(msr->index, &msr->data); 1692 break; 1693 default: 1694 return static_call(kvm_x86_get_msr_feature)(msr); 1695 } 1696 return 0; 1697 } 1698 1699 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 1700 { 1701 struct kvm_msr_entry msr; 1702 int r; 1703 1704 msr.index = index; 1705 r = kvm_get_msr_feature(&msr); 1706 1707 if (r == KVM_MSR_RET_INVALID) { 1708 /* Unconditionally clear the output for simplicity */ 1709 *data = 0; 1710 if (kvm_msr_ignored_check(index, 0, false)) 1711 r = 0; 1712 } 1713 1714 if (r) 1715 return r; 1716 1717 *data = msr.data; 1718 1719 return 0; 1720 } 1721 1722 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1723 { 1724 if (efer & EFER_AUTOIBRS && !guest_cpuid_has(vcpu, X86_FEATURE_AUTOIBRS)) 1725 return false; 1726 1727 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) 1728 return false; 1729 1730 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) 1731 return false; 1732 1733 if (efer & (EFER_LME | EFER_LMA) && 1734 !guest_cpuid_has(vcpu, X86_FEATURE_LM)) 1735 return false; 1736 1737 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) 1738 return false; 1739 1740 return true; 1741 1742 } 1743 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 1744 { 1745 if (efer & efer_reserved_bits) 1746 return false; 1747 1748 return __kvm_valid_efer(vcpu, efer); 1749 } 1750 EXPORT_SYMBOL_GPL(kvm_valid_efer); 1751 1752 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1753 { 1754 u64 old_efer = vcpu->arch.efer; 1755 u64 efer = msr_info->data; 1756 int r; 1757 1758 if (efer & efer_reserved_bits) 1759 return 1; 1760 1761 if (!msr_info->host_initiated) { 1762 if (!__kvm_valid_efer(vcpu, efer)) 1763 return 1; 1764 1765 if (is_paging(vcpu) && 1766 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 1767 return 1; 1768 } 1769 1770 efer &= ~EFER_LMA; 1771 efer |= vcpu->arch.efer & EFER_LMA; 1772 1773 r = static_call(kvm_x86_set_efer)(vcpu, efer); 1774 if (r) { 1775 WARN_ON(r > 0); 1776 return r; 1777 } 1778 1779 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS) 1780 kvm_mmu_reset_context(vcpu); 1781 1782 return 0; 1783 } 1784 1785 void kvm_enable_efer_bits(u64 mask) 1786 { 1787 efer_reserved_bits &= ~mask; 1788 } 1789 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 1790 1791 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) 1792 { 1793 struct kvm_x86_msr_filter *msr_filter; 1794 struct msr_bitmap_range *ranges; 1795 struct kvm *kvm = vcpu->kvm; 1796 bool allowed; 1797 int idx; 1798 u32 i; 1799 1800 /* x2APIC MSRs do not support filtering. */ 1801 if (index >= 0x800 && index <= 0x8ff) 1802 return true; 1803 1804 idx = srcu_read_lock(&kvm->srcu); 1805 1806 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); 1807 if (!msr_filter) { 1808 allowed = true; 1809 goto out; 1810 } 1811 1812 allowed = msr_filter->default_allow; 1813 ranges = msr_filter->ranges; 1814 1815 for (i = 0; i < msr_filter->count; i++) { 1816 u32 start = ranges[i].base; 1817 u32 end = start + ranges[i].nmsrs; 1818 u32 flags = ranges[i].flags; 1819 unsigned long *bitmap = ranges[i].bitmap; 1820 1821 if ((index >= start) && (index < end) && (flags & type)) { 1822 allowed = test_bit(index - start, bitmap); 1823 break; 1824 } 1825 } 1826 1827 out: 1828 srcu_read_unlock(&kvm->srcu, idx); 1829 1830 return allowed; 1831 } 1832 EXPORT_SYMBOL_GPL(kvm_msr_allowed); 1833 1834 /* 1835 * Write @data into the MSR specified by @index. Select MSR specific fault 1836 * checks are bypassed if @host_initiated is %true. 1837 * Returns 0 on success, non-0 otherwise. 1838 * Assumes vcpu_load() was already called. 1839 */ 1840 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, 1841 bool host_initiated) 1842 { 1843 struct msr_data msr; 1844 1845 switch (index) { 1846 case MSR_FS_BASE: 1847 case MSR_GS_BASE: 1848 case MSR_KERNEL_GS_BASE: 1849 case MSR_CSTAR: 1850 case MSR_LSTAR: 1851 if (is_noncanonical_address(data, vcpu)) 1852 return 1; 1853 break; 1854 case MSR_IA32_SYSENTER_EIP: 1855 case MSR_IA32_SYSENTER_ESP: 1856 /* 1857 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if 1858 * non-canonical address is written on Intel but not on 1859 * AMD (which ignores the top 32-bits, because it does 1860 * not implement 64-bit SYSENTER). 1861 * 1862 * 64-bit code should hence be able to write a non-canonical 1863 * value on AMD. Making the address canonical ensures that 1864 * vmentry does not fail on Intel after writing a non-canonical 1865 * value, and that something deterministic happens if the guest 1866 * invokes 64-bit SYSENTER. 1867 */ 1868 data = __canonical_address(data, vcpu_virt_addr_bits(vcpu)); 1869 break; 1870 case MSR_TSC_AUX: 1871 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1872 return 1; 1873 1874 if (!host_initiated && 1875 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1876 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1877 return 1; 1878 1879 /* 1880 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has 1881 * incomplete and conflicting architectural behavior. Current 1882 * AMD CPUs completely ignore bits 63:32, i.e. they aren't 1883 * reserved and always read as zeros. Enforce Intel's reserved 1884 * bits check if and only if the guest CPU is Intel, and clear 1885 * the bits in all other cases. This ensures cross-vendor 1886 * migration will provide consistent behavior for the guest. 1887 */ 1888 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) 1889 return 1; 1890 1891 data = (u32)data; 1892 break; 1893 } 1894 1895 msr.data = data; 1896 msr.index = index; 1897 msr.host_initiated = host_initiated; 1898 1899 return static_call(kvm_x86_set_msr)(vcpu, &msr); 1900 } 1901 1902 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, 1903 u32 index, u64 data, bool host_initiated) 1904 { 1905 int ret = __kvm_set_msr(vcpu, index, data, host_initiated); 1906 1907 if (ret == KVM_MSR_RET_INVALID) 1908 if (kvm_msr_ignored_check(index, data, true)) 1909 ret = 0; 1910 1911 return ret; 1912 } 1913 1914 /* 1915 * Read the MSR specified by @index into @data. Select MSR specific fault 1916 * checks are bypassed if @host_initiated is %true. 1917 * Returns 0 on success, non-0 otherwise. 1918 * Assumes vcpu_load() was already called. 1919 */ 1920 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, 1921 bool host_initiated) 1922 { 1923 struct msr_data msr; 1924 int ret; 1925 1926 switch (index) { 1927 case MSR_TSC_AUX: 1928 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) 1929 return 1; 1930 1931 if (!host_initiated && 1932 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && 1933 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) 1934 return 1; 1935 break; 1936 } 1937 1938 msr.index = index; 1939 msr.host_initiated = host_initiated; 1940 1941 ret = static_call(kvm_x86_get_msr)(vcpu, &msr); 1942 if (!ret) 1943 *data = msr.data; 1944 return ret; 1945 } 1946 1947 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, 1948 u32 index, u64 *data, bool host_initiated) 1949 { 1950 int ret = __kvm_get_msr(vcpu, index, data, host_initiated); 1951 1952 if (ret == KVM_MSR_RET_INVALID) { 1953 /* Unconditionally clear *data for simplicity */ 1954 *data = 0; 1955 if (kvm_msr_ignored_check(index, 0, false)) 1956 ret = 0; 1957 } 1958 1959 return ret; 1960 } 1961 1962 static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1963 { 1964 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) 1965 return KVM_MSR_RET_FILTERED; 1966 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1967 } 1968 1969 static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data) 1970 { 1971 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) 1972 return KVM_MSR_RET_FILTERED; 1973 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1974 } 1975 1976 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) 1977 { 1978 return kvm_get_msr_ignored_check(vcpu, index, data, false); 1979 } 1980 EXPORT_SYMBOL_GPL(kvm_get_msr); 1981 1982 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) 1983 { 1984 return kvm_set_msr_ignored_check(vcpu, index, data, false); 1985 } 1986 EXPORT_SYMBOL_GPL(kvm_set_msr); 1987 1988 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu) 1989 { 1990 if (!vcpu->run->msr.error) { 1991 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); 1992 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); 1993 } 1994 } 1995 1996 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu) 1997 { 1998 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error); 1999 } 2000 2001 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) 2002 { 2003 complete_userspace_rdmsr(vcpu); 2004 return complete_emulated_msr_access(vcpu); 2005 } 2006 2007 static int complete_fast_msr_access(struct kvm_vcpu *vcpu) 2008 { 2009 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); 2010 } 2011 2012 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu) 2013 { 2014 complete_userspace_rdmsr(vcpu); 2015 return complete_fast_msr_access(vcpu); 2016 } 2017 2018 static u64 kvm_msr_reason(int r) 2019 { 2020 switch (r) { 2021 case KVM_MSR_RET_INVALID: 2022 return KVM_MSR_EXIT_REASON_UNKNOWN; 2023 case KVM_MSR_RET_FILTERED: 2024 return KVM_MSR_EXIT_REASON_FILTER; 2025 default: 2026 return KVM_MSR_EXIT_REASON_INVAL; 2027 } 2028 } 2029 2030 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, 2031 u32 exit_reason, u64 data, 2032 int (*completion)(struct kvm_vcpu *vcpu), 2033 int r) 2034 { 2035 u64 msr_reason = kvm_msr_reason(r); 2036 2037 /* Check if the user wanted to know about this MSR fault */ 2038 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) 2039 return 0; 2040 2041 vcpu->run->exit_reason = exit_reason; 2042 vcpu->run->msr.error = 0; 2043 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); 2044 vcpu->run->msr.reason = msr_reason; 2045 vcpu->run->msr.index = index; 2046 vcpu->run->msr.data = data; 2047 vcpu->arch.complete_userspace_io = completion; 2048 2049 return 1; 2050 } 2051 2052 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) 2053 { 2054 u32 ecx = kvm_rcx_read(vcpu); 2055 u64 data; 2056 int r; 2057 2058 r = kvm_get_msr_with_filter(vcpu, ecx, &data); 2059 2060 if (!r) { 2061 trace_kvm_msr_read(ecx, data); 2062 2063 kvm_rax_write(vcpu, data & -1u); 2064 kvm_rdx_write(vcpu, (data >> 32) & -1u); 2065 } else { 2066 /* MSR read failed? See if we should ask user space */ 2067 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0, 2068 complete_fast_rdmsr, r)) 2069 return 0; 2070 trace_kvm_msr_read_ex(ecx); 2071 } 2072 2073 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 2074 } 2075 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); 2076 2077 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) 2078 { 2079 u32 ecx = kvm_rcx_read(vcpu); 2080 u64 data = kvm_read_edx_eax(vcpu); 2081 int r; 2082 2083 r = kvm_set_msr_with_filter(vcpu, ecx, data); 2084 2085 if (!r) { 2086 trace_kvm_msr_write(ecx, data); 2087 } else { 2088 /* MSR write failed? See if we should ask user space */ 2089 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data, 2090 complete_fast_msr_access, r)) 2091 return 0; 2092 /* Signal all other negative errors to userspace */ 2093 if (r < 0) 2094 return r; 2095 trace_kvm_msr_write_ex(ecx, data); 2096 } 2097 2098 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); 2099 } 2100 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); 2101 2102 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) 2103 { 2104 return kvm_skip_emulated_instruction(vcpu); 2105 } 2106 2107 int kvm_emulate_invd(struct kvm_vcpu *vcpu) 2108 { 2109 /* Treat an INVD instruction as a NOP and just skip it. */ 2110 return kvm_emulate_as_nop(vcpu); 2111 } 2112 EXPORT_SYMBOL_GPL(kvm_emulate_invd); 2113 2114 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) 2115 { 2116 kvm_queue_exception(vcpu, UD_VECTOR); 2117 return 1; 2118 } 2119 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); 2120 2121 2122 static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn) 2123 { 2124 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS) && 2125 !guest_cpuid_has(vcpu, X86_FEATURE_MWAIT)) 2126 return kvm_handle_invalid_op(vcpu); 2127 2128 pr_warn_once("%s instruction emulated as NOP!\n", insn); 2129 return kvm_emulate_as_nop(vcpu); 2130 } 2131 int kvm_emulate_mwait(struct kvm_vcpu *vcpu) 2132 { 2133 return kvm_emulate_monitor_mwait(vcpu, "MWAIT"); 2134 } 2135 EXPORT_SYMBOL_GPL(kvm_emulate_mwait); 2136 2137 int kvm_emulate_monitor(struct kvm_vcpu *vcpu) 2138 { 2139 return kvm_emulate_monitor_mwait(vcpu, "MONITOR"); 2140 } 2141 EXPORT_SYMBOL_GPL(kvm_emulate_monitor); 2142 2143 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) 2144 { 2145 xfer_to_guest_mode_prepare(); 2146 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || 2147 xfer_to_guest_mode_work_pending(); 2148 } 2149 2150 /* 2151 * The fast path for frequent and performance sensitive wrmsr emulation, 2152 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces 2153 * the latency of virtual IPI by avoiding the expensive bits of transitioning 2154 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the 2155 * other cases which must be called after interrupts are enabled on the host. 2156 */ 2157 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) 2158 { 2159 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) 2160 return 1; 2161 2162 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && 2163 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && 2164 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && 2165 ((u32)(data >> 32) != X2APIC_BROADCAST)) 2166 return kvm_x2apic_icr_write(vcpu->arch.apic, data); 2167 2168 return 1; 2169 } 2170 2171 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) 2172 { 2173 if (!kvm_can_use_hv_timer(vcpu)) 2174 return 1; 2175 2176 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2177 return 0; 2178 } 2179 2180 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) 2181 { 2182 u32 msr = kvm_rcx_read(vcpu); 2183 u64 data; 2184 fastpath_t ret = EXIT_FASTPATH_NONE; 2185 2186 kvm_vcpu_srcu_read_lock(vcpu); 2187 2188 switch (msr) { 2189 case APIC_BASE_MSR + (APIC_ICR >> 4): 2190 data = kvm_read_edx_eax(vcpu); 2191 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { 2192 kvm_skip_emulated_instruction(vcpu); 2193 ret = EXIT_FASTPATH_EXIT_HANDLED; 2194 } 2195 break; 2196 case MSR_IA32_TSC_DEADLINE: 2197 data = kvm_read_edx_eax(vcpu); 2198 if (!handle_fastpath_set_tscdeadline(vcpu, data)) { 2199 kvm_skip_emulated_instruction(vcpu); 2200 ret = EXIT_FASTPATH_REENTER_GUEST; 2201 } 2202 break; 2203 default: 2204 break; 2205 } 2206 2207 if (ret != EXIT_FASTPATH_NONE) 2208 trace_kvm_msr_write(msr, data); 2209 2210 kvm_vcpu_srcu_read_unlock(vcpu); 2211 2212 return ret; 2213 } 2214 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); 2215 2216 /* 2217 * Adapt set_msr() to msr_io()'s calling convention 2218 */ 2219 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2220 { 2221 return kvm_get_msr_ignored_check(vcpu, index, data, true); 2222 } 2223 2224 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 2225 { 2226 u64 val; 2227 2228 /* 2229 * Disallow writes to immutable feature MSRs after KVM_RUN. KVM does 2230 * not support modifying the guest vCPU model on the fly, e.g. changing 2231 * the nVMX capabilities while L2 is running is nonsensical. Ignore 2232 * writes of the same value, e.g. to allow userspace to blindly stuff 2233 * all MSRs when emulating RESET. 2234 */ 2235 if (kvm_vcpu_has_run(vcpu) && kvm_is_immutable_feature_msr(index)) { 2236 if (do_get_msr(vcpu, index, &val) || *data != val) 2237 return -EINVAL; 2238 2239 return 0; 2240 } 2241 2242 return kvm_set_msr_ignored_check(vcpu, index, *data, true); 2243 } 2244 2245 #ifdef CONFIG_X86_64 2246 struct pvclock_clock { 2247 int vclock_mode; 2248 u64 cycle_last; 2249 u64 mask; 2250 u32 mult; 2251 u32 shift; 2252 u64 base_cycles; 2253 u64 offset; 2254 }; 2255 2256 struct pvclock_gtod_data { 2257 seqcount_t seq; 2258 2259 struct pvclock_clock clock; /* extract of a clocksource struct */ 2260 struct pvclock_clock raw_clock; /* extract of a clocksource struct */ 2261 2262 ktime_t offs_boot; 2263 u64 wall_time_sec; 2264 }; 2265 2266 static struct pvclock_gtod_data pvclock_gtod_data; 2267 2268 static void update_pvclock_gtod(struct timekeeper *tk) 2269 { 2270 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 2271 2272 write_seqcount_begin(&vdata->seq); 2273 2274 /* copy pvclock gtod data */ 2275 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; 2276 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 2277 vdata->clock.mask = tk->tkr_mono.mask; 2278 vdata->clock.mult = tk->tkr_mono.mult; 2279 vdata->clock.shift = tk->tkr_mono.shift; 2280 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 2281 vdata->clock.offset = tk->tkr_mono.base; 2282 2283 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; 2284 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; 2285 vdata->raw_clock.mask = tk->tkr_raw.mask; 2286 vdata->raw_clock.mult = tk->tkr_raw.mult; 2287 vdata->raw_clock.shift = tk->tkr_raw.shift; 2288 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; 2289 vdata->raw_clock.offset = tk->tkr_raw.base; 2290 2291 vdata->wall_time_sec = tk->xtime_sec; 2292 2293 vdata->offs_boot = tk->offs_boot; 2294 2295 write_seqcount_end(&vdata->seq); 2296 } 2297 2298 static s64 get_kvmclock_base_ns(void) 2299 { 2300 /* Count up from boot time, but with the frequency of the raw clock. */ 2301 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); 2302 } 2303 #else 2304 static s64 get_kvmclock_base_ns(void) 2305 { 2306 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ 2307 return ktime_get_boottime_ns(); 2308 } 2309 #endif 2310 2311 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) 2312 { 2313 int version; 2314 int r; 2315 struct pvclock_wall_clock wc; 2316 u32 wc_sec_hi; 2317 u64 wall_nsec; 2318 2319 if (!wall_clock) 2320 return; 2321 2322 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 2323 if (r) 2324 return; 2325 2326 if (version & 1) 2327 ++version; /* first time write, random junk */ 2328 2329 ++version; 2330 2331 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) 2332 return; 2333 2334 /* 2335 * The guest calculates current wall clock time by adding 2336 * system time (updated by kvm_guest_time_update below) to the 2337 * wall clock specified here. We do the reverse here. 2338 */ 2339 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); 2340 2341 wc.nsec = do_div(wall_nsec, 1000000000); 2342 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ 2343 wc.version = version; 2344 2345 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 2346 2347 if (sec_hi_ofs) { 2348 wc_sec_hi = wall_nsec >> 32; 2349 kvm_write_guest(kvm, wall_clock + sec_hi_ofs, 2350 &wc_sec_hi, sizeof(wc_sec_hi)); 2351 } 2352 2353 version++; 2354 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 2355 } 2356 2357 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, 2358 bool old_msr, bool host_initiated) 2359 { 2360 struct kvm_arch *ka = &vcpu->kvm->arch; 2361 2362 if (vcpu->vcpu_id == 0 && !host_initiated) { 2363 if (ka->boot_vcpu_runs_old_kvmclock != old_msr) 2364 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2365 2366 ka->boot_vcpu_runs_old_kvmclock = old_msr; 2367 } 2368 2369 vcpu->arch.time = system_time; 2370 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2371 2372 /* we verify if the enable bit is set... */ 2373 if (system_time & 1) 2374 kvm_gpc_activate(&vcpu->arch.pv_time, system_time & ~1ULL, 2375 sizeof(struct pvclock_vcpu_time_info)); 2376 else 2377 kvm_gpc_deactivate(&vcpu->arch.pv_time); 2378 2379 return; 2380 } 2381 2382 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 2383 { 2384 do_shl32_div32(dividend, divisor); 2385 return dividend; 2386 } 2387 2388 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, 2389 s8 *pshift, u32 *pmultiplier) 2390 { 2391 uint64_t scaled64; 2392 int32_t shift = 0; 2393 uint64_t tps64; 2394 uint32_t tps32; 2395 2396 tps64 = base_hz; 2397 scaled64 = scaled_hz; 2398 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 2399 tps64 >>= 1; 2400 shift--; 2401 } 2402 2403 tps32 = (uint32_t)tps64; 2404 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 2405 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 2406 scaled64 >>= 1; 2407 else 2408 tps32 <<= 1; 2409 shift++; 2410 } 2411 2412 *pshift = shift; 2413 *pmultiplier = div_frac(scaled64, tps32); 2414 } 2415 2416 #ifdef CONFIG_X86_64 2417 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 2418 #endif 2419 2420 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 2421 static unsigned long max_tsc_khz; 2422 2423 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 2424 { 2425 u64 v = (u64)khz * (1000000 + ppm); 2426 do_div(v, 1000000); 2427 return v; 2428 } 2429 2430 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier); 2431 2432 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) 2433 { 2434 u64 ratio; 2435 2436 /* Guest TSC same frequency as host TSC? */ 2437 if (!scale) { 2438 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio); 2439 return 0; 2440 } 2441 2442 /* TSC scaling supported? */ 2443 if (!kvm_caps.has_tsc_control) { 2444 if (user_tsc_khz > tsc_khz) { 2445 vcpu->arch.tsc_catchup = 1; 2446 vcpu->arch.tsc_always_catchup = 1; 2447 return 0; 2448 } else { 2449 pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); 2450 return -1; 2451 } 2452 } 2453 2454 /* TSC scaling required - calculate ratio */ 2455 ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits, 2456 user_tsc_khz, tsc_khz); 2457 2458 if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) { 2459 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", 2460 user_tsc_khz); 2461 return -1; 2462 } 2463 2464 kvm_vcpu_write_tsc_multiplier(vcpu, ratio); 2465 return 0; 2466 } 2467 2468 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) 2469 { 2470 u32 thresh_lo, thresh_hi; 2471 int use_scaling = 0; 2472 2473 /* tsc_khz can be zero if TSC calibration fails */ 2474 if (user_tsc_khz == 0) { 2475 /* set tsc_scaling_ratio to a safe value */ 2476 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio); 2477 return -1; 2478 } 2479 2480 /* Compute a scale to convert nanoseconds in TSC cycles */ 2481 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, 2482 &vcpu->arch.virtual_tsc_shift, 2483 &vcpu->arch.virtual_tsc_mult); 2484 vcpu->arch.virtual_tsc_khz = user_tsc_khz; 2485 2486 /* 2487 * Compute the variation in TSC rate which is acceptable 2488 * within the range of tolerance and decide if the 2489 * rate being applied is within that bounds of the hardware 2490 * rate. If so, no scaling or compensation need be done. 2491 */ 2492 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 2493 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 2494 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { 2495 pr_debug("requested TSC rate %u falls outside tolerance [%u,%u]\n", 2496 user_tsc_khz, thresh_lo, thresh_hi); 2497 use_scaling = 1; 2498 } 2499 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); 2500 } 2501 2502 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 2503 { 2504 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 2505 vcpu->arch.virtual_tsc_mult, 2506 vcpu->arch.virtual_tsc_shift); 2507 tsc += vcpu->arch.this_tsc_write; 2508 return tsc; 2509 } 2510 2511 #ifdef CONFIG_X86_64 2512 static inline int gtod_is_based_on_tsc(int mode) 2513 { 2514 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; 2515 } 2516 #endif 2517 2518 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 2519 { 2520 #ifdef CONFIG_X86_64 2521 bool vcpus_matched; 2522 struct kvm_arch *ka = &vcpu->kvm->arch; 2523 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2524 2525 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2526 atomic_read(&vcpu->kvm->online_vcpus)); 2527 2528 /* 2529 * Once the masterclock is enabled, always perform request in 2530 * order to update it. 2531 * 2532 * In order to enable masterclock, the host clocksource must be TSC 2533 * and the vcpus need to have matched TSCs. When that happens, 2534 * perform request to enable masterclock. 2535 */ 2536 if (ka->use_master_clock || 2537 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) 2538 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 2539 2540 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 2541 atomic_read(&vcpu->kvm->online_vcpus), 2542 ka->use_master_clock, gtod->clock.vclock_mode); 2543 #endif 2544 } 2545 2546 /* 2547 * Multiply tsc by a fixed point number represented by ratio. 2548 * 2549 * The most significant 64-N bits (mult) of ratio represent the 2550 * integral part of the fixed point number; the remaining N bits 2551 * (frac) represent the fractional part, ie. ratio represents a fixed 2552 * point number (mult + frac * 2^(-N)). 2553 * 2554 * N equals to kvm_caps.tsc_scaling_ratio_frac_bits. 2555 */ 2556 static inline u64 __scale_tsc(u64 ratio, u64 tsc) 2557 { 2558 return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits); 2559 } 2560 2561 u64 kvm_scale_tsc(u64 tsc, u64 ratio) 2562 { 2563 u64 _tsc = tsc; 2564 2565 if (ratio != kvm_caps.default_tsc_scaling_ratio) 2566 _tsc = __scale_tsc(ratio, tsc); 2567 2568 return _tsc; 2569 } 2570 2571 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) 2572 { 2573 u64 tsc; 2574 2575 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio); 2576 2577 return target_tsc - tsc; 2578 } 2579 2580 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) 2581 { 2582 return vcpu->arch.l1_tsc_offset + 2583 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio); 2584 } 2585 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); 2586 2587 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier) 2588 { 2589 u64 nested_offset; 2590 2591 if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio) 2592 nested_offset = l1_offset; 2593 else 2594 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier, 2595 kvm_caps.tsc_scaling_ratio_frac_bits); 2596 2597 nested_offset += l2_offset; 2598 return nested_offset; 2599 } 2600 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset); 2601 2602 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier) 2603 { 2604 if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio) 2605 return mul_u64_u64_shr(l1_multiplier, l2_multiplier, 2606 kvm_caps.tsc_scaling_ratio_frac_bits); 2607 2608 return l1_multiplier; 2609 } 2610 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier); 2611 2612 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset) 2613 { 2614 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 2615 vcpu->arch.l1_tsc_offset, 2616 l1_offset); 2617 2618 vcpu->arch.l1_tsc_offset = l1_offset; 2619 2620 /* 2621 * If we are here because L1 chose not to trap WRMSR to TSC then 2622 * according to the spec this should set L1's TSC (as opposed to 2623 * setting L1's offset for L2). 2624 */ 2625 if (is_guest_mode(vcpu)) 2626 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( 2627 l1_offset, 2628 static_call(kvm_x86_get_l2_tsc_offset)(vcpu), 2629 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2630 else 2631 vcpu->arch.tsc_offset = l1_offset; 2632 2633 static_call(kvm_x86_write_tsc_offset)(vcpu); 2634 } 2635 2636 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier) 2637 { 2638 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier; 2639 2640 /* Userspace is changing the multiplier while L2 is active */ 2641 if (is_guest_mode(vcpu)) 2642 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( 2643 l1_multiplier, 2644 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); 2645 else 2646 vcpu->arch.tsc_scaling_ratio = l1_multiplier; 2647 2648 if (kvm_caps.has_tsc_control) 2649 static_call(kvm_x86_write_tsc_multiplier)(vcpu); 2650 } 2651 2652 static inline bool kvm_check_tsc_unstable(void) 2653 { 2654 #ifdef CONFIG_X86_64 2655 /* 2656 * TSC is marked unstable when we're running on Hyper-V, 2657 * 'TSC page' clocksource is good. 2658 */ 2659 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) 2660 return false; 2661 #endif 2662 return check_tsc_unstable(); 2663 } 2664 2665 /* 2666 * Infers attempts to synchronize the guest's tsc from host writes. Sets the 2667 * offset for the vcpu and tracks the TSC matching generation that the vcpu 2668 * participates in. 2669 */ 2670 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc, 2671 u64 ns, bool matched) 2672 { 2673 struct kvm *kvm = vcpu->kvm; 2674 2675 lockdep_assert_held(&kvm->arch.tsc_write_lock); 2676 2677 /* 2678 * We also track th most recent recorded KHZ, write and time to 2679 * allow the matching interval to be extended at each write. 2680 */ 2681 kvm->arch.last_tsc_nsec = ns; 2682 kvm->arch.last_tsc_write = tsc; 2683 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 2684 kvm->arch.last_tsc_offset = offset; 2685 2686 vcpu->arch.last_guest_tsc = tsc; 2687 2688 kvm_vcpu_write_tsc_offset(vcpu, offset); 2689 2690 if (!matched) { 2691 /* 2692 * We split periods of matched TSC writes into generations. 2693 * For each generation, we track the original measured 2694 * nanosecond time, offset, and write, so if TSCs are in 2695 * sync, we can match exact offset, and if not, we can match 2696 * exact software computation in compute_guest_tsc() 2697 * 2698 * These values are tracked in kvm->arch.cur_xxx variables. 2699 */ 2700 kvm->arch.cur_tsc_generation++; 2701 kvm->arch.cur_tsc_nsec = ns; 2702 kvm->arch.cur_tsc_write = tsc; 2703 kvm->arch.cur_tsc_offset = offset; 2704 kvm->arch.nr_vcpus_matched_tsc = 0; 2705 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) { 2706 kvm->arch.nr_vcpus_matched_tsc++; 2707 } 2708 2709 /* Keep track of which generation this VCPU has synchronized to */ 2710 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 2711 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 2712 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 2713 2714 kvm_track_tsc_matching(vcpu); 2715 } 2716 2717 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) 2718 { 2719 struct kvm *kvm = vcpu->kvm; 2720 u64 offset, ns, elapsed; 2721 unsigned long flags; 2722 bool matched = false; 2723 bool synchronizing = false; 2724 2725 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 2726 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2727 ns = get_kvmclock_base_ns(); 2728 elapsed = ns - kvm->arch.last_tsc_nsec; 2729 2730 if (vcpu->arch.virtual_tsc_khz) { 2731 if (data == 0) { 2732 /* 2733 * detection of vcpu initialization -- need to sync 2734 * with other vCPUs. This particularly helps to keep 2735 * kvm_clock stable after CPU hotplug 2736 */ 2737 synchronizing = true; 2738 } else { 2739 u64 tsc_exp = kvm->arch.last_tsc_write + 2740 nsec_to_cycles(vcpu, elapsed); 2741 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; 2742 /* 2743 * Special case: TSC write with a small delta (1 second) 2744 * of virtual cycle time against real time is 2745 * interpreted as an attempt to synchronize the CPU. 2746 */ 2747 synchronizing = data < tsc_exp + tsc_hz && 2748 data + tsc_hz > tsc_exp; 2749 } 2750 } 2751 2752 /* 2753 * For a reliable TSC, we can match TSC offsets, and for an unstable 2754 * TSC, we add elapsed time in this computation. We could let the 2755 * compensation code attempt to catch up if we fall behind, but 2756 * it's better to try to match offsets from the beginning. 2757 */ 2758 if (synchronizing && 2759 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 2760 if (!kvm_check_tsc_unstable()) { 2761 offset = kvm->arch.cur_tsc_offset; 2762 } else { 2763 u64 delta = nsec_to_cycles(vcpu, elapsed); 2764 data += delta; 2765 offset = kvm_compute_l1_tsc_offset(vcpu, data); 2766 } 2767 matched = true; 2768 } 2769 2770 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched); 2771 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 2772 } 2773 2774 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, 2775 s64 adjustment) 2776 { 2777 u64 tsc_offset = vcpu->arch.l1_tsc_offset; 2778 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); 2779 } 2780 2781 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) 2782 { 2783 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio) 2784 WARN_ON(adjustment < 0); 2785 adjustment = kvm_scale_tsc((u64) adjustment, 2786 vcpu->arch.l1_tsc_scaling_ratio); 2787 adjust_tsc_offset_guest(vcpu, adjustment); 2788 } 2789 2790 #ifdef CONFIG_X86_64 2791 2792 static u64 read_tsc(void) 2793 { 2794 u64 ret = (u64)rdtsc_ordered(); 2795 u64 last = pvclock_gtod_data.clock.cycle_last; 2796 2797 if (likely(ret >= last)) 2798 return ret; 2799 2800 /* 2801 * GCC likes to generate cmov here, but this branch is extremely 2802 * predictable (it's just a function of time and the likely is 2803 * very likely) and there's a data dependence, so force GCC 2804 * to generate a branch instead. I don't barrier() because 2805 * we don't actually need a barrier, and if this function 2806 * ever gets inlined it will generate worse code. 2807 */ 2808 asm volatile (""); 2809 return last; 2810 } 2811 2812 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, 2813 int *mode) 2814 { 2815 u64 tsc_pg_val; 2816 long v; 2817 2818 switch (clock->vclock_mode) { 2819 case VDSO_CLOCKMODE_HVCLOCK: 2820 if (hv_read_tsc_page_tsc(hv_get_tsc_page(), 2821 tsc_timestamp, &tsc_pg_val)) { 2822 /* TSC page valid */ 2823 *mode = VDSO_CLOCKMODE_HVCLOCK; 2824 v = (tsc_pg_val - clock->cycle_last) & 2825 clock->mask; 2826 } else { 2827 /* TSC page invalid */ 2828 *mode = VDSO_CLOCKMODE_NONE; 2829 } 2830 break; 2831 case VDSO_CLOCKMODE_TSC: 2832 *mode = VDSO_CLOCKMODE_TSC; 2833 *tsc_timestamp = read_tsc(); 2834 v = (*tsc_timestamp - clock->cycle_last) & 2835 clock->mask; 2836 break; 2837 default: 2838 *mode = VDSO_CLOCKMODE_NONE; 2839 } 2840 2841 if (*mode == VDSO_CLOCKMODE_NONE) 2842 *tsc_timestamp = v = 0; 2843 2844 return v * clock->mult; 2845 } 2846 2847 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) 2848 { 2849 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2850 unsigned long seq; 2851 int mode; 2852 u64 ns; 2853 2854 do { 2855 seq = read_seqcount_begin(>od->seq); 2856 ns = gtod->raw_clock.base_cycles; 2857 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); 2858 ns >>= gtod->raw_clock.shift; 2859 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); 2860 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2861 *t = ns; 2862 2863 return mode; 2864 } 2865 2866 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) 2867 { 2868 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 2869 unsigned long seq; 2870 int mode; 2871 u64 ns; 2872 2873 do { 2874 seq = read_seqcount_begin(>od->seq); 2875 ts->tv_sec = gtod->wall_time_sec; 2876 ns = gtod->clock.base_cycles; 2877 ns += vgettsc(>od->clock, tsc_timestamp, &mode); 2878 ns >>= gtod->clock.shift; 2879 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 2880 2881 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); 2882 ts->tv_nsec = ns; 2883 2884 return mode; 2885 } 2886 2887 /* returns true if host is using TSC based clocksource */ 2888 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) 2889 { 2890 /* checked again under seqlock below */ 2891 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2892 return false; 2893 2894 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, 2895 tsc_timestamp)); 2896 } 2897 2898 /* returns true if host is using TSC based clocksource */ 2899 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, 2900 u64 *tsc_timestamp) 2901 { 2902 /* checked again under seqlock below */ 2903 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) 2904 return false; 2905 2906 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); 2907 } 2908 #endif 2909 2910 /* 2911 * 2912 * Assuming a stable TSC across physical CPUS, and a stable TSC 2913 * across virtual CPUs, the following condition is possible. 2914 * Each numbered line represents an event visible to both 2915 * CPUs at the next numbered event. 2916 * 2917 * "timespecX" represents host monotonic time. "tscX" represents 2918 * RDTSC value. 2919 * 2920 * VCPU0 on CPU0 | VCPU1 on CPU1 2921 * 2922 * 1. read timespec0,tsc0 2923 * 2. | timespec1 = timespec0 + N 2924 * | tsc1 = tsc0 + M 2925 * 3. transition to guest | transition to guest 2926 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 2927 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 2928 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 2929 * 2930 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 2931 * 2932 * - ret0 < ret1 2933 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 2934 * ... 2935 * - 0 < N - M => M < N 2936 * 2937 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 2938 * always the case (the difference between two distinct xtime instances 2939 * might be smaller then the difference between corresponding TSC reads, 2940 * when updating guest vcpus pvclock areas). 2941 * 2942 * To avoid that problem, do not allow visibility of distinct 2943 * system_timestamp/tsc_timestamp values simultaneously: use a master 2944 * copy of host monotonic time values. Update that master copy 2945 * in lockstep. 2946 * 2947 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 2948 * 2949 */ 2950 2951 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 2952 { 2953 #ifdef CONFIG_X86_64 2954 struct kvm_arch *ka = &kvm->arch; 2955 int vclock_mode; 2956 bool host_tsc_clocksource, vcpus_matched; 2957 2958 lockdep_assert_held(&kvm->arch.tsc_write_lock); 2959 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 2960 atomic_read(&kvm->online_vcpus)); 2961 2962 /* 2963 * If the host uses TSC clock, then passthrough TSC as stable 2964 * to the guest. 2965 */ 2966 host_tsc_clocksource = kvm_get_time_and_clockread( 2967 &ka->master_kernel_ns, 2968 &ka->master_cycle_now); 2969 2970 ka->use_master_clock = host_tsc_clocksource && vcpus_matched 2971 && !ka->backwards_tsc_observed 2972 && !ka->boot_vcpu_runs_old_kvmclock; 2973 2974 if (ka->use_master_clock) 2975 atomic_set(&kvm_guest_has_master_clock, 1); 2976 2977 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 2978 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 2979 vcpus_matched); 2980 #endif 2981 } 2982 2983 static void kvm_make_mclock_inprogress_request(struct kvm *kvm) 2984 { 2985 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); 2986 } 2987 2988 static void __kvm_start_pvclock_update(struct kvm *kvm) 2989 { 2990 raw_spin_lock_irq(&kvm->arch.tsc_write_lock); 2991 write_seqcount_begin(&kvm->arch.pvclock_sc); 2992 } 2993 2994 static void kvm_start_pvclock_update(struct kvm *kvm) 2995 { 2996 kvm_make_mclock_inprogress_request(kvm); 2997 2998 /* no guest entries from this point */ 2999 __kvm_start_pvclock_update(kvm); 3000 } 3001 3002 static void kvm_end_pvclock_update(struct kvm *kvm) 3003 { 3004 struct kvm_arch *ka = &kvm->arch; 3005 struct kvm_vcpu *vcpu; 3006 unsigned long i; 3007 3008 write_seqcount_end(&ka->pvclock_sc); 3009 raw_spin_unlock_irq(&ka->tsc_write_lock); 3010 kvm_for_each_vcpu(i, vcpu, kvm) 3011 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3012 3013 /* guest entries allowed */ 3014 kvm_for_each_vcpu(i, vcpu, kvm) 3015 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); 3016 } 3017 3018 static void kvm_update_masterclock(struct kvm *kvm) 3019 { 3020 kvm_hv_request_tsc_page_update(kvm); 3021 kvm_start_pvclock_update(kvm); 3022 pvclock_update_vm_gtod_copy(kvm); 3023 kvm_end_pvclock_update(kvm); 3024 } 3025 3026 /* 3027 * Use the kernel's tsc_khz directly if the TSC is constant, otherwise use KVM's 3028 * per-CPU value (which may be zero if a CPU is going offline). Note, tsc_khz 3029 * can change during boot even if the TSC is constant, as it's possible for KVM 3030 * to be loaded before TSC calibration completes. Ideally, KVM would get a 3031 * notification when calibration completes, but practically speaking calibration 3032 * will complete before userspace is alive enough to create VMs. 3033 */ 3034 static unsigned long get_cpu_tsc_khz(void) 3035 { 3036 if (static_cpu_has(X86_FEATURE_CONSTANT_TSC)) 3037 return tsc_khz; 3038 else 3039 return __this_cpu_read(cpu_tsc_khz); 3040 } 3041 3042 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */ 3043 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) 3044 { 3045 struct kvm_arch *ka = &kvm->arch; 3046 struct pvclock_vcpu_time_info hv_clock; 3047 3048 /* both __this_cpu_read() and rdtsc() should be on the same cpu */ 3049 get_cpu(); 3050 3051 data->flags = 0; 3052 if (ka->use_master_clock && 3053 (static_cpu_has(X86_FEATURE_CONSTANT_TSC) || __this_cpu_read(cpu_tsc_khz))) { 3054 #ifdef CONFIG_X86_64 3055 struct timespec64 ts; 3056 3057 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) { 3058 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec; 3059 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC; 3060 } else 3061 #endif 3062 data->host_tsc = rdtsc(); 3063 3064 data->flags |= KVM_CLOCK_TSC_STABLE; 3065 hv_clock.tsc_timestamp = ka->master_cycle_now; 3066 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; 3067 kvm_get_time_scale(NSEC_PER_SEC, get_cpu_tsc_khz() * 1000LL, 3068 &hv_clock.tsc_shift, 3069 &hv_clock.tsc_to_system_mul); 3070 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc); 3071 } else { 3072 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset; 3073 } 3074 3075 put_cpu(); 3076 } 3077 3078 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) 3079 { 3080 struct kvm_arch *ka = &kvm->arch; 3081 unsigned seq; 3082 3083 do { 3084 seq = read_seqcount_begin(&ka->pvclock_sc); 3085 __get_kvmclock(kvm, data); 3086 } while (read_seqcount_retry(&ka->pvclock_sc, seq)); 3087 } 3088 3089 u64 get_kvmclock_ns(struct kvm *kvm) 3090 { 3091 struct kvm_clock_data data; 3092 3093 get_kvmclock(kvm, &data); 3094 return data.clock; 3095 } 3096 3097 static void kvm_setup_guest_pvclock(struct kvm_vcpu *v, 3098 struct gfn_to_pfn_cache *gpc, 3099 unsigned int offset) 3100 { 3101 struct kvm_vcpu_arch *vcpu = &v->arch; 3102 struct pvclock_vcpu_time_info *guest_hv_clock; 3103 unsigned long flags; 3104 3105 read_lock_irqsave(&gpc->lock, flags); 3106 while (!kvm_gpc_check(gpc, offset + sizeof(*guest_hv_clock))) { 3107 read_unlock_irqrestore(&gpc->lock, flags); 3108 3109 if (kvm_gpc_refresh(gpc, offset + sizeof(*guest_hv_clock))) 3110 return; 3111 3112 read_lock_irqsave(&gpc->lock, flags); 3113 } 3114 3115 guest_hv_clock = (void *)(gpc->khva + offset); 3116 3117 /* 3118 * This VCPU is paused, but it's legal for a guest to read another 3119 * VCPU's kvmclock, so we really have to follow the specification where 3120 * it says that version is odd if data is being modified, and even after 3121 * it is consistent. 3122 */ 3123 3124 guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1; 3125 smp_wmb(); 3126 3127 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 3128 vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED); 3129 3130 if (vcpu->pvclock_set_guest_stopped_request) { 3131 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; 3132 vcpu->pvclock_set_guest_stopped_request = false; 3133 } 3134 3135 memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock)); 3136 smp_wmb(); 3137 3138 guest_hv_clock->version = ++vcpu->hv_clock.version; 3139 3140 mark_page_dirty_in_slot(v->kvm, gpc->memslot, gpc->gpa >> PAGE_SHIFT); 3141 read_unlock_irqrestore(&gpc->lock, flags); 3142 3143 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); 3144 } 3145 3146 static int kvm_guest_time_update(struct kvm_vcpu *v) 3147 { 3148 unsigned long flags, tgt_tsc_khz; 3149 unsigned seq; 3150 struct kvm_vcpu_arch *vcpu = &v->arch; 3151 struct kvm_arch *ka = &v->kvm->arch; 3152 s64 kernel_ns; 3153 u64 tsc_timestamp, host_tsc; 3154 u8 pvclock_flags; 3155 bool use_master_clock; 3156 3157 kernel_ns = 0; 3158 host_tsc = 0; 3159 3160 /* 3161 * If the host uses TSC clock, then passthrough TSC as stable 3162 * to the guest. 3163 */ 3164 do { 3165 seq = read_seqcount_begin(&ka->pvclock_sc); 3166 use_master_clock = ka->use_master_clock; 3167 if (use_master_clock) { 3168 host_tsc = ka->master_cycle_now; 3169 kernel_ns = ka->master_kernel_ns; 3170 } 3171 } while (read_seqcount_retry(&ka->pvclock_sc, seq)); 3172 3173 /* Keep irq disabled to prevent changes to the clock */ 3174 local_irq_save(flags); 3175 tgt_tsc_khz = get_cpu_tsc_khz(); 3176 if (unlikely(tgt_tsc_khz == 0)) { 3177 local_irq_restore(flags); 3178 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 3179 return 1; 3180 } 3181 if (!use_master_clock) { 3182 host_tsc = rdtsc(); 3183 kernel_ns = get_kvmclock_base_ns(); 3184 } 3185 3186 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); 3187 3188 /* 3189 * We may have to catch up the TSC to match elapsed wall clock 3190 * time for two reasons, even if kvmclock is used. 3191 * 1) CPU could have been running below the maximum TSC rate 3192 * 2) Broken TSC compensation resets the base at each VCPU 3193 * entry to avoid unknown leaps of TSC even when running 3194 * again on the same CPU. This may cause apparent elapsed 3195 * time to disappear, and the guest to stand still or run 3196 * very slowly. 3197 */ 3198 if (vcpu->tsc_catchup) { 3199 u64 tsc = compute_guest_tsc(v, kernel_ns); 3200 if (tsc > tsc_timestamp) { 3201 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 3202 tsc_timestamp = tsc; 3203 } 3204 } 3205 3206 local_irq_restore(flags); 3207 3208 /* With all the info we got, fill in the values */ 3209 3210 if (kvm_caps.has_tsc_control) 3211 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz, 3212 v->arch.l1_tsc_scaling_ratio); 3213 3214 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { 3215 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, 3216 &vcpu->hv_clock.tsc_shift, 3217 &vcpu->hv_clock.tsc_to_system_mul); 3218 vcpu->hw_tsc_khz = tgt_tsc_khz; 3219 kvm_xen_update_tsc_info(v); 3220 } 3221 3222 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 3223 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 3224 vcpu->last_guest_tsc = tsc_timestamp; 3225 3226 /* If the host uses TSC clocksource, then it is stable */ 3227 pvclock_flags = 0; 3228 if (use_master_clock) 3229 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 3230 3231 vcpu->hv_clock.flags = pvclock_flags; 3232 3233 if (vcpu->pv_time.active) 3234 kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0); 3235 if (vcpu->xen.vcpu_info_cache.active) 3236 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache, 3237 offsetof(struct compat_vcpu_info, time)); 3238 if (vcpu->xen.vcpu_time_info_cache.active) 3239 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0); 3240 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); 3241 return 0; 3242 } 3243 3244 /* 3245 * kvmclock updates which are isolated to a given vcpu, such as 3246 * vcpu->cpu migration, should not allow system_timestamp from 3247 * the rest of the vcpus to remain static. Otherwise ntp frequency 3248 * correction applies to one vcpu's system_timestamp but not 3249 * the others. 3250 * 3251 * So in those cases, request a kvmclock update for all vcpus. 3252 * We need to rate-limit these requests though, as they can 3253 * considerably slow guests that have a large number of vcpus. 3254 * The time for a remote vcpu to update its kvmclock is bound 3255 * by the delay we use to rate-limit the updates. 3256 */ 3257 3258 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 3259 3260 static void kvmclock_update_fn(struct work_struct *work) 3261 { 3262 unsigned long i; 3263 struct delayed_work *dwork = to_delayed_work(work); 3264 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3265 kvmclock_update_work); 3266 struct kvm *kvm = container_of(ka, struct kvm, arch); 3267 struct kvm_vcpu *vcpu; 3268 3269 kvm_for_each_vcpu(i, vcpu, kvm) { 3270 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3271 kvm_vcpu_kick(vcpu); 3272 } 3273 } 3274 3275 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 3276 { 3277 struct kvm *kvm = v->kvm; 3278 3279 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 3280 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 3281 KVMCLOCK_UPDATE_DELAY); 3282 } 3283 3284 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 3285 3286 static void kvmclock_sync_fn(struct work_struct *work) 3287 { 3288 struct delayed_work *dwork = to_delayed_work(work); 3289 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 3290 kvmclock_sync_work); 3291 struct kvm *kvm = container_of(ka, struct kvm, arch); 3292 3293 if (!kvmclock_periodic_sync) 3294 return; 3295 3296 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 3297 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 3298 KVMCLOCK_SYNC_PERIOD); 3299 } 3300 3301 /* These helpers are safe iff @msr is known to be an MCx bank MSR. */ 3302 static bool is_mci_control_msr(u32 msr) 3303 { 3304 return (msr & 3) == 0; 3305 } 3306 static bool is_mci_status_msr(u32 msr) 3307 { 3308 return (msr & 3) == 1; 3309 } 3310 3311 /* 3312 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. 3313 */ 3314 static bool can_set_mci_status(struct kvm_vcpu *vcpu) 3315 { 3316 /* McStatusWrEn enabled? */ 3317 if (guest_cpuid_is_amd_or_hygon(vcpu)) 3318 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); 3319 3320 return false; 3321 } 3322 3323 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3324 { 3325 u64 mcg_cap = vcpu->arch.mcg_cap; 3326 unsigned bank_num = mcg_cap & 0xff; 3327 u32 msr = msr_info->index; 3328 u64 data = msr_info->data; 3329 u32 offset, last_msr; 3330 3331 switch (msr) { 3332 case MSR_IA32_MCG_STATUS: 3333 vcpu->arch.mcg_status = data; 3334 break; 3335 case MSR_IA32_MCG_CTL: 3336 if (!(mcg_cap & MCG_CTL_P) && 3337 (data || !msr_info->host_initiated)) 3338 return 1; 3339 if (data != 0 && data != ~(u64)0) 3340 return 1; 3341 vcpu->arch.mcg_ctl = data; 3342 break; 3343 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: 3344 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1; 3345 if (msr > last_msr) 3346 return 1; 3347 3348 if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated)) 3349 return 1; 3350 /* An attempt to write a 1 to a reserved bit raises #GP */ 3351 if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK)) 3352 return 1; 3353 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2, 3354 last_msr + 1 - MSR_IA32_MC0_CTL2); 3355 vcpu->arch.mci_ctl2_banks[offset] = data; 3356 break; 3357 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3358 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1; 3359 if (msr > last_msr) 3360 return 1; 3361 3362 /* 3363 * Only 0 or all 1s can be written to IA32_MCi_CTL, all other 3364 * values are architecturally undefined. But, some Linux 3365 * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB 3366 * issue on AMD K8s, allow bit 10 to be clear when setting all 3367 * other bits in order to avoid an uncaught #GP in the guest. 3368 * 3369 * UNIXWARE clears bit 0 of MC1_CTL to ignore correctable, 3370 * single-bit ECC data errors. 3371 */ 3372 if (is_mci_control_msr(msr) && 3373 data != 0 && (data | (1 << 10) | 1) != ~(u64)0) 3374 return 1; 3375 3376 /* 3377 * All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR. 3378 * AMD-based CPUs allow non-zero values, but if and only if 3379 * HWCR[McStatusWrEn] is set. 3380 */ 3381 if (!msr_info->host_initiated && is_mci_status_msr(msr) && 3382 data != 0 && !can_set_mci_status(vcpu)) 3383 return 1; 3384 3385 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL, 3386 last_msr + 1 - MSR_IA32_MC0_CTL); 3387 vcpu->arch.mce_banks[offset] = data; 3388 break; 3389 default: 3390 return 1; 3391 } 3392 return 0; 3393 } 3394 3395 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) 3396 { 3397 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; 3398 3399 return (vcpu->arch.apf.msr_en_val & mask) == mask; 3400 } 3401 3402 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 3403 { 3404 gpa_t gpa = data & ~0x3f; 3405 3406 /* Bits 4:5 are reserved, Should be zero */ 3407 if (data & 0x30) 3408 return 1; 3409 3410 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && 3411 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) 3412 return 1; 3413 3414 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && 3415 (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) 3416 return 1; 3417 3418 if (!lapic_in_kernel(vcpu)) 3419 return data ? 1 : 0; 3420 3421 vcpu->arch.apf.msr_en_val = data; 3422 3423 if (!kvm_pv_async_pf_enabled(vcpu)) { 3424 kvm_clear_async_pf_completion_queue(vcpu); 3425 kvm_async_pf_hash_reset(vcpu); 3426 return 0; 3427 } 3428 3429 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 3430 sizeof(u64))) 3431 return 1; 3432 3433 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 3434 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 3435 3436 kvm_async_pf_wakeup_all(vcpu); 3437 3438 return 0; 3439 } 3440 3441 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) 3442 { 3443 /* Bits 8-63 are reserved */ 3444 if (data >> 8) 3445 return 1; 3446 3447 if (!lapic_in_kernel(vcpu)) 3448 return 1; 3449 3450 vcpu->arch.apf.msr_int_val = data; 3451 3452 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; 3453 3454 return 0; 3455 } 3456 3457 static void kvmclock_reset(struct kvm_vcpu *vcpu) 3458 { 3459 kvm_gpc_deactivate(&vcpu->arch.pv_time); 3460 vcpu->arch.time = 0; 3461 } 3462 3463 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) 3464 { 3465 ++vcpu->stat.tlb_flush; 3466 static_call(kvm_x86_flush_tlb_all)(vcpu); 3467 3468 /* Flushing all ASIDs flushes the current ASID... */ 3469 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); 3470 } 3471 3472 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) 3473 { 3474 ++vcpu->stat.tlb_flush; 3475 3476 if (!tdp_enabled) { 3477 /* 3478 * A TLB flush on behalf of the guest is equivalent to 3479 * INVPCID(all), toggling CR4.PGE, etc., which requires 3480 * a forced sync of the shadow page tables. Ensure all the 3481 * roots are synced and the guest TLB in hardware is clean. 3482 */ 3483 kvm_mmu_sync_roots(vcpu); 3484 kvm_mmu_sync_prev_roots(vcpu); 3485 } 3486 3487 static_call(kvm_x86_flush_tlb_guest)(vcpu); 3488 3489 /* 3490 * Flushing all "guest" TLB is always a superset of Hyper-V's fine 3491 * grained flushing. 3492 */ 3493 kvm_hv_vcpu_purge_flush_tlb(vcpu); 3494 } 3495 3496 3497 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu) 3498 { 3499 ++vcpu->stat.tlb_flush; 3500 static_call(kvm_x86_flush_tlb_current)(vcpu); 3501 } 3502 3503 /* 3504 * Service "local" TLB flush requests, which are specific to the current MMU 3505 * context. In addition to the generic event handling in vcpu_enter_guest(), 3506 * TLB flushes that are targeted at an MMU context also need to be serviced 3507 * prior before nested VM-Enter/VM-Exit. 3508 */ 3509 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu) 3510 { 3511 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) 3512 kvm_vcpu_flush_tlb_current(vcpu); 3513 3514 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu)) 3515 kvm_vcpu_flush_tlb_guest(vcpu); 3516 } 3517 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests); 3518 3519 static void record_steal_time(struct kvm_vcpu *vcpu) 3520 { 3521 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; 3522 struct kvm_steal_time __user *st; 3523 struct kvm_memslots *slots; 3524 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; 3525 u64 steal; 3526 u32 version; 3527 3528 if (kvm_xen_msr_enabled(vcpu->kvm)) { 3529 kvm_xen_runstate_set_running(vcpu); 3530 return; 3531 } 3532 3533 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 3534 return; 3535 3536 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm)) 3537 return; 3538 3539 slots = kvm_memslots(vcpu->kvm); 3540 3541 if (unlikely(slots->generation != ghc->generation || 3542 gpa != ghc->gpa || 3543 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) { 3544 /* We rely on the fact that it fits in a single page. */ 3545 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS); 3546 3547 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st)) || 3548 kvm_is_error_hva(ghc->hva) || !ghc->memslot) 3549 return; 3550 } 3551 3552 st = (struct kvm_steal_time __user *)ghc->hva; 3553 /* 3554 * Doing a TLB flush here, on the guest's behalf, can avoid 3555 * expensive IPIs. 3556 */ 3557 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { 3558 u8 st_preempted = 0; 3559 int err = -EFAULT; 3560 3561 if (!user_access_begin(st, sizeof(*st))) 3562 return; 3563 3564 asm volatile("1: xchgb %0, %2\n" 3565 "xor %1, %1\n" 3566 "2:\n" 3567 _ASM_EXTABLE_UA(1b, 2b) 3568 : "+q" (st_preempted), 3569 "+&r" (err), 3570 "+m" (st->preempted)); 3571 if (err) 3572 goto out; 3573 3574 user_access_end(); 3575 3576 vcpu->arch.st.preempted = 0; 3577 3578 trace_kvm_pv_tlb_flush(vcpu->vcpu_id, 3579 st_preempted & KVM_VCPU_FLUSH_TLB); 3580 if (st_preempted & KVM_VCPU_FLUSH_TLB) 3581 kvm_vcpu_flush_tlb_guest(vcpu); 3582 3583 if (!user_access_begin(st, sizeof(*st))) 3584 goto dirty; 3585 } else { 3586 if (!user_access_begin(st, sizeof(*st))) 3587 return; 3588 3589 unsafe_put_user(0, &st->preempted, out); 3590 vcpu->arch.st.preempted = 0; 3591 } 3592 3593 unsafe_get_user(version, &st->version, out); 3594 if (version & 1) 3595 version += 1; /* first time write, random junk */ 3596 3597 version += 1; 3598 unsafe_put_user(version, &st->version, out); 3599 3600 smp_wmb(); 3601 3602 unsafe_get_user(steal, &st->steal, out); 3603 steal += current->sched_info.run_delay - 3604 vcpu->arch.st.last_steal; 3605 vcpu->arch.st.last_steal = current->sched_info.run_delay; 3606 unsafe_put_user(steal, &st->steal, out); 3607 3608 version += 1; 3609 unsafe_put_user(version, &st->version, out); 3610 3611 out: 3612 user_access_end(); 3613 dirty: 3614 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 3615 } 3616 3617 static bool kvm_is_msr_to_save(u32 msr_index) 3618 { 3619 unsigned int i; 3620 3621 for (i = 0; i < num_msrs_to_save; i++) { 3622 if (msrs_to_save[i] == msr_index) 3623 return true; 3624 } 3625 3626 return false; 3627 } 3628 3629 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3630 { 3631 u32 msr = msr_info->index; 3632 u64 data = msr_info->data; 3633 3634 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) 3635 return kvm_xen_write_hypercall_page(vcpu, data); 3636 3637 switch (msr) { 3638 case MSR_AMD64_NB_CFG: 3639 case MSR_IA32_UCODE_WRITE: 3640 case MSR_VM_HSAVE_PA: 3641 case MSR_AMD64_PATCH_LOADER: 3642 case MSR_AMD64_BU_CFG2: 3643 case MSR_AMD64_DC_CFG: 3644 case MSR_F15H_EX_CFG: 3645 break; 3646 3647 case MSR_IA32_UCODE_REV: 3648 if (msr_info->host_initiated) 3649 vcpu->arch.microcode_version = data; 3650 break; 3651 case MSR_IA32_ARCH_CAPABILITIES: 3652 if (!msr_info->host_initiated) 3653 return 1; 3654 vcpu->arch.arch_capabilities = data; 3655 break; 3656 case MSR_IA32_PERF_CAPABILITIES: 3657 if (!msr_info->host_initiated) 3658 return 1; 3659 if (data & ~kvm_caps.supported_perf_cap) 3660 return 1; 3661 3662 /* 3663 * Note, this is not just a performance optimization! KVM 3664 * disallows changing feature MSRs after the vCPU has run; PMU 3665 * refresh will bug the VM if called after the vCPU has run. 3666 */ 3667 if (vcpu->arch.perf_capabilities == data) 3668 break; 3669 3670 vcpu->arch.perf_capabilities = data; 3671 kvm_pmu_refresh(vcpu); 3672 break; 3673 case MSR_IA32_PRED_CMD: 3674 if (!msr_info->host_initiated && !guest_has_pred_cmd_msr(vcpu)) 3675 return 1; 3676 3677 if (!boot_cpu_has(X86_FEATURE_IBPB) || (data & ~PRED_CMD_IBPB)) 3678 return 1; 3679 if (!data) 3680 break; 3681 3682 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); 3683 break; 3684 case MSR_IA32_FLUSH_CMD: 3685 if (!msr_info->host_initiated && 3686 !guest_cpuid_has(vcpu, X86_FEATURE_FLUSH_L1D)) 3687 return 1; 3688 3689 if (!boot_cpu_has(X86_FEATURE_FLUSH_L1D) || (data & ~L1D_FLUSH)) 3690 return 1; 3691 if (!data) 3692 break; 3693 3694 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 3695 break; 3696 case MSR_EFER: 3697 return set_efer(vcpu, msr_info); 3698 case MSR_K7_HWCR: 3699 data &= ~(u64)0x40; /* ignore flush filter disable */ 3700 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 3701 data &= ~(u64)0x8; /* ignore TLB cache disable */ 3702 3703 /* Handle McStatusWrEn */ 3704 if (data == BIT_ULL(18)) { 3705 vcpu->arch.msr_hwcr = data; 3706 } else if (data != 0) { 3707 kvm_pr_unimpl_wrmsr(vcpu, msr, data); 3708 return 1; 3709 } 3710 break; 3711 case MSR_FAM10H_MMIO_CONF_BASE: 3712 if (data != 0) { 3713 kvm_pr_unimpl_wrmsr(vcpu, msr, data); 3714 return 1; 3715 } 3716 break; 3717 case MSR_IA32_CR_PAT: 3718 if (!kvm_pat_valid(data)) 3719 return 1; 3720 3721 vcpu->arch.pat = data; 3722 break; 3723 case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000: 3724 case MSR_MTRRdefType: 3725 return kvm_mtrr_set_msr(vcpu, msr, data); 3726 case MSR_IA32_APICBASE: 3727 return kvm_set_apic_base(vcpu, msr_info); 3728 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3729 return kvm_x2apic_msr_write(vcpu, msr, data); 3730 case MSR_IA32_TSC_DEADLINE: 3731 kvm_set_lapic_tscdeadline_msr(vcpu, data); 3732 break; 3733 case MSR_IA32_TSC_ADJUST: 3734 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { 3735 if (!msr_info->host_initiated) { 3736 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 3737 adjust_tsc_offset_guest(vcpu, adj); 3738 /* Before back to guest, tsc_timestamp must be adjusted 3739 * as well, otherwise guest's percpu pvclock time could jump. 3740 */ 3741 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3742 } 3743 vcpu->arch.ia32_tsc_adjust_msr = data; 3744 } 3745 break; 3746 case MSR_IA32_MISC_ENABLE: { 3747 u64 old_val = vcpu->arch.ia32_misc_enable_msr; 3748 3749 if (!msr_info->host_initiated) { 3750 /* RO bits */ 3751 if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK) 3752 return 1; 3753 3754 /* R bits, i.e. writes are ignored, but don't fault. */ 3755 data = data & ~MSR_IA32_MISC_ENABLE_EMON; 3756 data |= old_val & MSR_IA32_MISC_ENABLE_EMON; 3757 } 3758 3759 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && 3760 ((old_val ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { 3761 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) 3762 return 1; 3763 vcpu->arch.ia32_misc_enable_msr = data; 3764 kvm_update_cpuid_runtime(vcpu); 3765 } else { 3766 vcpu->arch.ia32_misc_enable_msr = data; 3767 } 3768 break; 3769 } 3770 case MSR_IA32_SMBASE: 3771 if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated) 3772 return 1; 3773 vcpu->arch.smbase = data; 3774 break; 3775 case MSR_IA32_POWER_CTL: 3776 vcpu->arch.msr_ia32_power_ctl = data; 3777 break; 3778 case MSR_IA32_TSC: 3779 if (msr_info->host_initiated) { 3780 kvm_synchronize_tsc(vcpu, data); 3781 } else { 3782 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; 3783 adjust_tsc_offset_guest(vcpu, adj); 3784 vcpu->arch.ia32_tsc_adjust_msr += adj; 3785 } 3786 break; 3787 case MSR_IA32_XSS: 3788 if (!msr_info->host_initiated && 3789 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3790 return 1; 3791 /* 3792 * KVM supports exposing PT to the guest, but does not support 3793 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than 3794 * XSAVES/XRSTORS to save/restore PT MSRs. 3795 */ 3796 if (data & ~kvm_caps.supported_xss) 3797 return 1; 3798 vcpu->arch.ia32_xss = data; 3799 kvm_update_cpuid_runtime(vcpu); 3800 break; 3801 case MSR_SMI_COUNT: 3802 if (!msr_info->host_initiated) 3803 return 1; 3804 vcpu->arch.smi_count = data; 3805 break; 3806 case MSR_KVM_WALL_CLOCK_NEW: 3807 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3808 return 1; 3809 3810 vcpu->kvm->arch.wall_clock = data; 3811 kvm_write_wall_clock(vcpu->kvm, data, 0); 3812 break; 3813 case MSR_KVM_WALL_CLOCK: 3814 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3815 return 1; 3816 3817 vcpu->kvm->arch.wall_clock = data; 3818 kvm_write_wall_clock(vcpu->kvm, data, 0); 3819 break; 3820 case MSR_KVM_SYSTEM_TIME_NEW: 3821 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3822 return 1; 3823 3824 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); 3825 break; 3826 case MSR_KVM_SYSTEM_TIME: 3827 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3828 return 1; 3829 3830 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); 3831 break; 3832 case MSR_KVM_ASYNC_PF_EN: 3833 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3834 return 1; 3835 3836 if (kvm_pv_enable_async_pf(vcpu, data)) 3837 return 1; 3838 break; 3839 case MSR_KVM_ASYNC_PF_INT: 3840 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3841 return 1; 3842 3843 if (kvm_pv_enable_async_pf_int(vcpu, data)) 3844 return 1; 3845 break; 3846 case MSR_KVM_ASYNC_PF_ACK: 3847 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3848 return 1; 3849 if (data & 0x1) { 3850 vcpu->arch.apf.pageready_pending = false; 3851 kvm_check_async_pf_completion(vcpu); 3852 } 3853 break; 3854 case MSR_KVM_STEAL_TIME: 3855 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3856 return 1; 3857 3858 if (unlikely(!sched_info_on())) 3859 return 1; 3860 3861 if (data & KVM_STEAL_RESERVED_MASK) 3862 return 1; 3863 3864 vcpu->arch.st.msr_val = data; 3865 3866 if (!(data & KVM_MSR_ENABLED)) 3867 break; 3868 3869 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 3870 3871 break; 3872 case MSR_KVM_PV_EOI_EN: 3873 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3874 return 1; 3875 3876 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8))) 3877 return 1; 3878 break; 3879 3880 case MSR_KVM_POLL_CONTROL: 3881 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3882 return 1; 3883 3884 /* only enable bit supported */ 3885 if (data & (-1ULL << 1)) 3886 return 1; 3887 3888 vcpu->arch.msr_kvm_poll_control = data; 3889 break; 3890 3891 case MSR_IA32_MCG_CTL: 3892 case MSR_IA32_MCG_STATUS: 3893 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3894 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: 3895 return set_msr_mce(vcpu, msr_info); 3896 3897 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3898 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3899 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3900 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3901 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3902 return kvm_pmu_set_msr(vcpu, msr_info); 3903 3904 if (data) 3905 kvm_pr_unimpl_wrmsr(vcpu, msr, data); 3906 break; 3907 case MSR_K7_CLK_CTL: 3908 /* 3909 * Ignore all writes to this no longer documented MSR. 3910 * Writes are only relevant for old K7 processors, 3911 * all pre-dating SVM, but a recommended workaround from 3912 * AMD for these chips. It is possible to specify the 3913 * affected processor models on the command line, hence 3914 * the need to ignore the workaround. 3915 */ 3916 break; 3917 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3918 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3919 case HV_X64_MSR_SYNDBG_OPTIONS: 3920 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3921 case HV_X64_MSR_CRASH_CTL: 3922 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3923 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3924 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3925 case HV_X64_MSR_TSC_EMULATION_STATUS: 3926 case HV_X64_MSR_TSC_INVARIANT_CONTROL: 3927 return kvm_hv_set_msr_common(vcpu, msr, data, 3928 msr_info->host_initiated); 3929 case MSR_IA32_BBL_CR_CTL3: 3930 /* Drop writes to this legacy MSR -- see rdmsr 3931 * counterpart for further detail. 3932 */ 3933 kvm_pr_unimpl_wrmsr(vcpu, msr, data); 3934 break; 3935 case MSR_AMD64_OSVW_ID_LENGTH: 3936 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3937 return 1; 3938 vcpu->arch.osvw.length = data; 3939 break; 3940 case MSR_AMD64_OSVW_STATUS: 3941 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3942 return 1; 3943 vcpu->arch.osvw.status = data; 3944 break; 3945 case MSR_PLATFORM_INFO: 3946 if (!msr_info->host_initiated || 3947 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && 3948 cpuid_fault_enabled(vcpu))) 3949 return 1; 3950 vcpu->arch.msr_platform_info = data; 3951 break; 3952 case MSR_MISC_FEATURES_ENABLES: 3953 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || 3954 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3955 !supports_cpuid_fault(vcpu))) 3956 return 1; 3957 vcpu->arch.msr_misc_features_enables = data; 3958 break; 3959 #ifdef CONFIG_X86_64 3960 case MSR_IA32_XFD: 3961 if (!msr_info->host_initiated && 3962 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 3963 return 1; 3964 3965 if (data & ~kvm_guest_supported_xfd(vcpu)) 3966 return 1; 3967 3968 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data); 3969 break; 3970 case MSR_IA32_XFD_ERR: 3971 if (!msr_info->host_initiated && 3972 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 3973 return 1; 3974 3975 if (data & ~kvm_guest_supported_xfd(vcpu)) 3976 return 1; 3977 3978 vcpu->arch.guest_fpu.xfd_err = data; 3979 break; 3980 #endif 3981 default: 3982 if (kvm_pmu_is_valid_msr(vcpu, msr)) 3983 return kvm_pmu_set_msr(vcpu, msr_info); 3984 3985 /* 3986 * Userspace is allowed to write '0' to MSRs that KVM reports 3987 * as to-be-saved, even if an MSRs isn't fully supported. 3988 */ 3989 if (msr_info->host_initiated && !data && 3990 kvm_is_msr_to_save(msr)) 3991 break; 3992 3993 return KVM_MSR_RET_INVALID; 3994 } 3995 return 0; 3996 } 3997 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 3998 3999 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) 4000 { 4001 u64 data; 4002 u64 mcg_cap = vcpu->arch.mcg_cap; 4003 unsigned bank_num = mcg_cap & 0xff; 4004 u32 offset, last_msr; 4005 4006 switch (msr) { 4007 case MSR_IA32_P5_MC_ADDR: 4008 case MSR_IA32_P5_MC_TYPE: 4009 data = 0; 4010 break; 4011 case MSR_IA32_MCG_CAP: 4012 data = vcpu->arch.mcg_cap; 4013 break; 4014 case MSR_IA32_MCG_CTL: 4015 if (!(mcg_cap & MCG_CTL_P) && !host) 4016 return 1; 4017 data = vcpu->arch.mcg_ctl; 4018 break; 4019 case MSR_IA32_MCG_STATUS: 4020 data = vcpu->arch.mcg_status; 4021 break; 4022 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: 4023 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1; 4024 if (msr > last_msr) 4025 return 1; 4026 4027 if (!(mcg_cap & MCG_CMCI_P) && !host) 4028 return 1; 4029 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2, 4030 last_msr + 1 - MSR_IA32_MC0_CTL2); 4031 data = vcpu->arch.mci_ctl2_banks[offset]; 4032 break; 4033 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 4034 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1; 4035 if (msr > last_msr) 4036 return 1; 4037 4038 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL, 4039 last_msr + 1 - MSR_IA32_MC0_CTL); 4040 data = vcpu->arch.mce_banks[offset]; 4041 break; 4042 default: 4043 return 1; 4044 } 4045 *pdata = data; 4046 return 0; 4047 } 4048 4049 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 4050 { 4051 switch (msr_info->index) { 4052 case MSR_IA32_PLATFORM_ID: 4053 case MSR_IA32_EBL_CR_POWERON: 4054 case MSR_IA32_LASTBRANCHFROMIP: 4055 case MSR_IA32_LASTBRANCHTOIP: 4056 case MSR_IA32_LASTINTFROMIP: 4057 case MSR_IA32_LASTINTTOIP: 4058 case MSR_AMD64_SYSCFG: 4059 case MSR_K8_TSEG_ADDR: 4060 case MSR_K8_TSEG_MASK: 4061 case MSR_VM_HSAVE_PA: 4062 case MSR_K8_INT_PENDING_MSG: 4063 case MSR_AMD64_NB_CFG: 4064 case MSR_FAM10H_MMIO_CONF_BASE: 4065 case MSR_AMD64_BU_CFG2: 4066 case MSR_IA32_PERF_CTL: 4067 case MSR_AMD64_DC_CFG: 4068 case MSR_F15H_EX_CFG: 4069 /* 4070 * Intel Sandy Bridge CPUs must support the RAPL (running average power 4071 * limit) MSRs. Just return 0, as we do not want to expose the host 4072 * data here. Do not conditionalize this on CPUID, as KVM does not do 4073 * so for existing CPU-specific MSRs. 4074 */ 4075 case MSR_RAPL_POWER_UNIT: 4076 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ 4077 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ 4078 case MSR_PKG_ENERGY_STATUS: /* Total package */ 4079 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ 4080 msr_info->data = 0; 4081 break; 4082 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 4083 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 4084 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 4085 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 4086 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 4087 return kvm_pmu_get_msr(vcpu, msr_info); 4088 msr_info->data = 0; 4089 break; 4090 case MSR_IA32_UCODE_REV: 4091 msr_info->data = vcpu->arch.microcode_version; 4092 break; 4093 case MSR_IA32_ARCH_CAPABILITIES: 4094 if (!msr_info->host_initiated && 4095 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 4096 return 1; 4097 msr_info->data = vcpu->arch.arch_capabilities; 4098 break; 4099 case MSR_IA32_PERF_CAPABILITIES: 4100 if (!msr_info->host_initiated && 4101 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) 4102 return 1; 4103 msr_info->data = vcpu->arch.perf_capabilities; 4104 break; 4105 case MSR_IA32_POWER_CTL: 4106 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 4107 break; 4108 case MSR_IA32_TSC: { 4109 /* 4110 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset 4111 * even when not intercepted. AMD manual doesn't explicitly 4112 * state this but appears to behave the same. 4113 * 4114 * On userspace reads and writes, however, we unconditionally 4115 * return L1's TSC value to ensure backwards-compatible 4116 * behavior for migration. 4117 */ 4118 u64 offset, ratio; 4119 4120 if (msr_info->host_initiated) { 4121 offset = vcpu->arch.l1_tsc_offset; 4122 ratio = vcpu->arch.l1_tsc_scaling_ratio; 4123 } else { 4124 offset = vcpu->arch.tsc_offset; 4125 ratio = vcpu->arch.tsc_scaling_ratio; 4126 } 4127 4128 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset; 4129 break; 4130 } 4131 case MSR_IA32_CR_PAT: 4132 msr_info->data = vcpu->arch.pat; 4133 break; 4134 case MSR_MTRRcap: 4135 case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000: 4136 case MSR_MTRRdefType: 4137 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 4138 case 0xcd: /* fsb frequency */ 4139 msr_info->data = 3; 4140 break; 4141 /* 4142 * MSR_EBC_FREQUENCY_ID 4143 * Conservative value valid for even the basic CPU models. 4144 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 4145 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 4146 * and 266MHz for model 3, or 4. Set Core Clock 4147 * Frequency to System Bus Frequency Ratio to 1 (bits 4148 * 31:24) even though these are only valid for CPU 4149 * models > 2, however guests may end up dividing or 4150 * multiplying by zero otherwise. 4151 */ 4152 case MSR_EBC_FREQUENCY_ID: 4153 msr_info->data = 1 << 24; 4154 break; 4155 case MSR_IA32_APICBASE: 4156 msr_info->data = kvm_get_apic_base(vcpu); 4157 break; 4158 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 4159 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 4160 case MSR_IA32_TSC_DEADLINE: 4161 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 4162 break; 4163 case MSR_IA32_TSC_ADJUST: 4164 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 4165 break; 4166 case MSR_IA32_MISC_ENABLE: 4167 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 4168 break; 4169 case MSR_IA32_SMBASE: 4170 if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated) 4171 return 1; 4172 msr_info->data = vcpu->arch.smbase; 4173 break; 4174 case MSR_SMI_COUNT: 4175 msr_info->data = vcpu->arch.smi_count; 4176 break; 4177 case MSR_IA32_PERF_STATUS: 4178 /* TSC increment by tick */ 4179 msr_info->data = 1000ULL; 4180 /* CPU multiplier */ 4181 msr_info->data |= (((uint64_t)4ULL) << 40); 4182 break; 4183 case MSR_EFER: 4184 msr_info->data = vcpu->arch.efer; 4185 break; 4186 case MSR_KVM_WALL_CLOCK: 4187 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 4188 return 1; 4189 4190 msr_info->data = vcpu->kvm->arch.wall_clock; 4191 break; 4192 case MSR_KVM_WALL_CLOCK_NEW: 4193 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 4194 return 1; 4195 4196 msr_info->data = vcpu->kvm->arch.wall_clock; 4197 break; 4198 case MSR_KVM_SYSTEM_TIME: 4199 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 4200 return 1; 4201 4202 msr_info->data = vcpu->arch.time; 4203 break; 4204 case MSR_KVM_SYSTEM_TIME_NEW: 4205 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 4206 return 1; 4207 4208 msr_info->data = vcpu->arch.time; 4209 break; 4210 case MSR_KVM_ASYNC_PF_EN: 4211 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 4212 return 1; 4213 4214 msr_info->data = vcpu->arch.apf.msr_en_val; 4215 break; 4216 case MSR_KVM_ASYNC_PF_INT: 4217 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 4218 return 1; 4219 4220 msr_info->data = vcpu->arch.apf.msr_int_val; 4221 break; 4222 case MSR_KVM_ASYNC_PF_ACK: 4223 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 4224 return 1; 4225 4226 msr_info->data = 0; 4227 break; 4228 case MSR_KVM_STEAL_TIME: 4229 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 4230 return 1; 4231 4232 msr_info->data = vcpu->arch.st.msr_val; 4233 break; 4234 case MSR_KVM_PV_EOI_EN: 4235 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 4236 return 1; 4237 4238 msr_info->data = vcpu->arch.pv_eoi.msr_val; 4239 break; 4240 case MSR_KVM_POLL_CONTROL: 4241 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 4242 return 1; 4243 4244 msr_info->data = vcpu->arch.msr_kvm_poll_control; 4245 break; 4246 case MSR_IA32_P5_MC_ADDR: 4247 case MSR_IA32_P5_MC_TYPE: 4248 case MSR_IA32_MCG_CAP: 4249 case MSR_IA32_MCG_CTL: 4250 case MSR_IA32_MCG_STATUS: 4251 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 4252 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: 4253 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 4254 msr_info->host_initiated); 4255 case MSR_IA32_XSS: 4256 if (!msr_info->host_initiated && 4257 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 4258 return 1; 4259 msr_info->data = vcpu->arch.ia32_xss; 4260 break; 4261 case MSR_K7_CLK_CTL: 4262 /* 4263 * Provide expected ramp-up count for K7. All other 4264 * are set to zero, indicating minimum divisors for 4265 * every field. 4266 * 4267 * This prevents guest kernels on AMD host with CPU 4268 * type 6, model 8 and higher from exploding due to 4269 * the rdmsr failing. 4270 */ 4271 msr_info->data = 0x20000000; 4272 break; 4273 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 4274 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 4275 case HV_X64_MSR_SYNDBG_OPTIONS: 4276 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 4277 case HV_X64_MSR_CRASH_CTL: 4278 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 4279 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 4280 case HV_X64_MSR_TSC_EMULATION_CONTROL: 4281 case HV_X64_MSR_TSC_EMULATION_STATUS: 4282 case HV_X64_MSR_TSC_INVARIANT_CONTROL: 4283 return kvm_hv_get_msr_common(vcpu, 4284 msr_info->index, &msr_info->data, 4285 msr_info->host_initiated); 4286 case MSR_IA32_BBL_CR_CTL3: 4287 /* This legacy MSR exists but isn't fully documented in current 4288 * silicon. It is however accessed by winxp in very narrow 4289 * scenarios where it sets bit #19, itself documented as 4290 * a "reserved" bit. Best effort attempt to source coherent 4291 * read data here should the balance of the register be 4292 * interpreted by the guest: 4293 * 4294 * L2 cache control register 3: 64GB range, 256KB size, 4295 * enabled, latency 0x1, configured 4296 */ 4297 msr_info->data = 0xbe702111; 4298 break; 4299 case MSR_AMD64_OSVW_ID_LENGTH: 4300 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 4301 return 1; 4302 msr_info->data = vcpu->arch.osvw.length; 4303 break; 4304 case MSR_AMD64_OSVW_STATUS: 4305 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 4306 return 1; 4307 msr_info->data = vcpu->arch.osvw.status; 4308 break; 4309 case MSR_PLATFORM_INFO: 4310 if (!msr_info->host_initiated && 4311 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 4312 return 1; 4313 msr_info->data = vcpu->arch.msr_platform_info; 4314 break; 4315 case MSR_MISC_FEATURES_ENABLES: 4316 msr_info->data = vcpu->arch.msr_misc_features_enables; 4317 break; 4318 case MSR_K7_HWCR: 4319 msr_info->data = vcpu->arch.msr_hwcr; 4320 break; 4321 #ifdef CONFIG_X86_64 4322 case MSR_IA32_XFD: 4323 if (!msr_info->host_initiated && 4324 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 4325 return 1; 4326 4327 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd; 4328 break; 4329 case MSR_IA32_XFD_ERR: 4330 if (!msr_info->host_initiated && 4331 !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) 4332 return 1; 4333 4334 msr_info->data = vcpu->arch.guest_fpu.xfd_err; 4335 break; 4336 #endif 4337 default: 4338 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 4339 return kvm_pmu_get_msr(vcpu, msr_info); 4340 4341 /* 4342 * Userspace is allowed to read MSRs that KVM reports as 4343 * to-be-saved, even if an MSR isn't fully supported. 4344 */ 4345 if (msr_info->host_initiated && 4346 kvm_is_msr_to_save(msr_info->index)) { 4347 msr_info->data = 0; 4348 break; 4349 } 4350 4351 return KVM_MSR_RET_INVALID; 4352 } 4353 return 0; 4354 } 4355 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 4356 4357 /* 4358 * Read or write a bunch of msrs. All parameters are kernel addresses. 4359 * 4360 * @return number of msrs set successfully. 4361 */ 4362 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 4363 struct kvm_msr_entry *entries, 4364 int (*do_msr)(struct kvm_vcpu *vcpu, 4365 unsigned index, u64 *data)) 4366 { 4367 int i; 4368 4369 for (i = 0; i < msrs->nmsrs; ++i) 4370 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 4371 break; 4372 4373 return i; 4374 } 4375 4376 /* 4377 * Read or write a bunch of msrs. Parameters are user addresses. 4378 * 4379 * @return number of msrs set successfully. 4380 */ 4381 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 4382 int (*do_msr)(struct kvm_vcpu *vcpu, 4383 unsigned index, u64 *data), 4384 int writeback) 4385 { 4386 struct kvm_msrs msrs; 4387 struct kvm_msr_entry *entries; 4388 unsigned size; 4389 int r; 4390 4391 r = -EFAULT; 4392 if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) 4393 goto out; 4394 4395 r = -E2BIG; 4396 if (msrs.nmsrs >= MAX_IO_MSRS) 4397 goto out; 4398 4399 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 4400 entries = memdup_user(user_msrs->entries, size); 4401 if (IS_ERR(entries)) { 4402 r = PTR_ERR(entries); 4403 goto out; 4404 } 4405 4406 r = __msr_io(vcpu, &msrs, entries, do_msr); 4407 4408 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 4409 r = -EFAULT; 4410 4411 kfree(entries); 4412 out: 4413 return r; 4414 } 4415 4416 static inline bool kvm_can_mwait_in_guest(void) 4417 { 4418 return boot_cpu_has(X86_FEATURE_MWAIT) && 4419 !boot_cpu_has_bug(X86_BUG_MONITOR) && 4420 boot_cpu_has(X86_FEATURE_ARAT); 4421 } 4422 4423 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, 4424 struct kvm_cpuid2 __user *cpuid_arg) 4425 { 4426 struct kvm_cpuid2 cpuid; 4427 int r; 4428 4429 r = -EFAULT; 4430 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4431 return r; 4432 4433 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); 4434 if (r) 4435 return r; 4436 4437 r = -EFAULT; 4438 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4439 return r; 4440 4441 return 0; 4442 } 4443 4444 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 4445 { 4446 int r = 0; 4447 4448 switch (ext) { 4449 case KVM_CAP_IRQCHIP: 4450 case KVM_CAP_HLT: 4451 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 4452 case KVM_CAP_SET_TSS_ADDR: 4453 case KVM_CAP_EXT_CPUID: 4454 case KVM_CAP_EXT_EMUL_CPUID: 4455 case KVM_CAP_CLOCKSOURCE: 4456 case KVM_CAP_PIT: 4457 case KVM_CAP_NOP_IO_DELAY: 4458 case KVM_CAP_MP_STATE: 4459 case KVM_CAP_SYNC_MMU: 4460 case KVM_CAP_USER_NMI: 4461 case KVM_CAP_REINJECT_CONTROL: 4462 case KVM_CAP_IRQ_INJECT_STATUS: 4463 case KVM_CAP_IOEVENTFD: 4464 case KVM_CAP_IOEVENTFD_NO_LENGTH: 4465 case KVM_CAP_PIT2: 4466 case KVM_CAP_PIT_STATE2: 4467 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 4468 case KVM_CAP_VCPU_EVENTS: 4469 case KVM_CAP_HYPERV: 4470 case KVM_CAP_HYPERV_VAPIC: 4471 case KVM_CAP_HYPERV_SPIN: 4472 case KVM_CAP_HYPERV_SYNIC: 4473 case KVM_CAP_HYPERV_SYNIC2: 4474 case KVM_CAP_HYPERV_VP_INDEX: 4475 case KVM_CAP_HYPERV_EVENTFD: 4476 case KVM_CAP_HYPERV_TLBFLUSH: 4477 case KVM_CAP_HYPERV_SEND_IPI: 4478 case KVM_CAP_HYPERV_CPUID: 4479 case KVM_CAP_HYPERV_ENFORCE_CPUID: 4480 case KVM_CAP_SYS_HYPERV_CPUID: 4481 case KVM_CAP_PCI_SEGMENT: 4482 case KVM_CAP_DEBUGREGS: 4483 case KVM_CAP_X86_ROBUST_SINGLESTEP: 4484 case KVM_CAP_XSAVE: 4485 case KVM_CAP_ASYNC_PF: 4486 case KVM_CAP_ASYNC_PF_INT: 4487 case KVM_CAP_GET_TSC_KHZ: 4488 case KVM_CAP_KVMCLOCK_CTRL: 4489 case KVM_CAP_READONLY_MEM: 4490 case KVM_CAP_HYPERV_TIME: 4491 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 4492 case KVM_CAP_TSC_DEADLINE_TIMER: 4493 case KVM_CAP_DISABLE_QUIRKS: 4494 case KVM_CAP_SET_BOOT_CPU_ID: 4495 case KVM_CAP_SPLIT_IRQCHIP: 4496 case KVM_CAP_IMMEDIATE_EXIT: 4497 case KVM_CAP_PMU_EVENT_FILTER: 4498 case KVM_CAP_PMU_EVENT_MASKED_EVENTS: 4499 case KVM_CAP_GET_MSR_FEATURES: 4500 case KVM_CAP_MSR_PLATFORM_INFO: 4501 case KVM_CAP_EXCEPTION_PAYLOAD: 4502 case KVM_CAP_X86_TRIPLE_FAULT_EVENT: 4503 case KVM_CAP_SET_GUEST_DEBUG: 4504 case KVM_CAP_LAST_CPU: 4505 case KVM_CAP_X86_USER_SPACE_MSR: 4506 case KVM_CAP_X86_MSR_FILTER: 4507 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 4508 #ifdef CONFIG_X86_SGX_KVM 4509 case KVM_CAP_SGX_ATTRIBUTE: 4510 #endif 4511 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 4512 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: 4513 case KVM_CAP_SREGS2: 4514 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 4515 case KVM_CAP_VCPU_ATTRIBUTES: 4516 case KVM_CAP_SYS_ATTRIBUTES: 4517 case KVM_CAP_VAPIC: 4518 case KVM_CAP_ENABLE_CAP: 4519 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES: 4520 case KVM_CAP_IRQFD_RESAMPLE: 4521 r = 1; 4522 break; 4523 case KVM_CAP_EXIT_HYPERCALL: 4524 r = KVM_EXIT_HYPERCALL_VALID_MASK; 4525 break; 4526 case KVM_CAP_SET_GUEST_DEBUG2: 4527 return KVM_GUESTDBG_VALID_MASK; 4528 #ifdef CONFIG_KVM_XEN 4529 case KVM_CAP_XEN_HVM: 4530 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | 4531 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | 4532 KVM_XEN_HVM_CONFIG_SHARED_INFO | 4533 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL | 4534 KVM_XEN_HVM_CONFIG_EVTCHN_SEND; 4535 if (sched_info_on()) 4536 r |= KVM_XEN_HVM_CONFIG_RUNSTATE | 4537 KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG; 4538 break; 4539 #endif 4540 case KVM_CAP_SYNC_REGS: 4541 r = KVM_SYNC_X86_VALID_FIELDS; 4542 break; 4543 case KVM_CAP_ADJUST_CLOCK: 4544 r = KVM_CLOCK_VALID_FLAGS; 4545 break; 4546 case KVM_CAP_X86_DISABLE_EXITS: 4547 r = KVM_X86_DISABLE_EXITS_PAUSE; 4548 4549 if (!mitigate_smt_rsb) { 4550 r |= KVM_X86_DISABLE_EXITS_HLT | 4551 KVM_X86_DISABLE_EXITS_CSTATE; 4552 4553 if (kvm_can_mwait_in_guest()) 4554 r |= KVM_X86_DISABLE_EXITS_MWAIT; 4555 } 4556 break; 4557 case KVM_CAP_X86_SMM: 4558 if (!IS_ENABLED(CONFIG_KVM_SMM)) 4559 break; 4560 4561 /* SMBASE is usually relocated above 1M on modern chipsets, 4562 * and SMM handlers might indeed rely on 4G segment limits, 4563 * so do not report SMM to be available if real mode is 4564 * emulated via vm86 mode. Still, do not go to great lengths 4565 * to avoid userspace's usage of the feature, because it is a 4566 * fringe case that is not enabled except via specific settings 4567 * of the module parameters. 4568 */ 4569 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); 4570 break; 4571 case KVM_CAP_NR_VCPUS: 4572 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS); 4573 break; 4574 case KVM_CAP_MAX_VCPUS: 4575 r = KVM_MAX_VCPUS; 4576 break; 4577 case KVM_CAP_MAX_VCPU_ID: 4578 r = KVM_MAX_VCPU_IDS; 4579 break; 4580 case KVM_CAP_PV_MMU: /* obsolete */ 4581 r = 0; 4582 break; 4583 case KVM_CAP_MCE: 4584 r = KVM_MAX_MCE_BANKS; 4585 break; 4586 case KVM_CAP_XCRS: 4587 r = boot_cpu_has(X86_FEATURE_XSAVE); 4588 break; 4589 case KVM_CAP_TSC_CONTROL: 4590 case KVM_CAP_VM_TSC_CONTROL: 4591 r = kvm_caps.has_tsc_control; 4592 break; 4593 case KVM_CAP_X2APIC_API: 4594 r = KVM_X2APIC_API_VALID_FLAGS; 4595 break; 4596 case KVM_CAP_NESTED_STATE: 4597 r = kvm_x86_ops.nested_ops->get_state ? 4598 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; 4599 break; 4600 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 4601 r = kvm_x86_ops.enable_l2_tlb_flush != NULL; 4602 break; 4603 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 4604 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; 4605 break; 4606 case KVM_CAP_SMALLER_MAXPHYADDR: 4607 r = (int) allow_smaller_maxphyaddr; 4608 break; 4609 case KVM_CAP_STEAL_TIME: 4610 r = sched_info_on(); 4611 break; 4612 case KVM_CAP_X86_BUS_LOCK_EXIT: 4613 if (kvm_caps.has_bus_lock_exit) 4614 r = KVM_BUS_LOCK_DETECTION_OFF | 4615 KVM_BUS_LOCK_DETECTION_EXIT; 4616 else 4617 r = 0; 4618 break; 4619 case KVM_CAP_XSAVE2: { 4620 r = xstate_required_size(kvm_get_filtered_xcr0(), false); 4621 if (r < sizeof(struct kvm_xsave)) 4622 r = sizeof(struct kvm_xsave); 4623 break; 4624 } 4625 case KVM_CAP_PMU_CAPABILITY: 4626 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0; 4627 break; 4628 case KVM_CAP_DISABLE_QUIRKS2: 4629 r = KVM_X86_VALID_QUIRKS; 4630 break; 4631 case KVM_CAP_X86_NOTIFY_VMEXIT: 4632 r = kvm_caps.has_notify_vmexit; 4633 break; 4634 default: 4635 break; 4636 } 4637 return r; 4638 } 4639 4640 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr) 4641 { 4642 void __user *uaddr = (void __user*)(unsigned long)attr->addr; 4643 4644 if ((u64)(unsigned long)uaddr != attr->addr) 4645 return ERR_PTR_USR(-EFAULT); 4646 return uaddr; 4647 } 4648 4649 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr) 4650 { 4651 u64 __user *uaddr = kvm_get_attr_addr(attr); 4652 4653 if (attr->group) 4654 return -ENXIO; 4655 4656 if (IS_ERR(uaddr)) 4657 return PTR_ERR(uaddr); 4658 4659 switch (attr->attr) { 4660 case KVM_X86_XCOMP_GUEST_SUPP: 4661 if (put_user(kvm_caps.supported_xcr0, uaddr)) 4662 return -EFAULT; 4663 return 0; 4664 default: 4665 return -ENXIO; 4666 } 4667 } 4668 4669 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr) 4670 { 4671 if (attr->group) 4672 return -ENXIO; 4673 4674 switch (attr->attr) { 4675 case KVM_X86_XCOMP_GUEST_SUPP: 4676 return 0; 4677 default: 4678 return -ENXIO; 4679 } 4680 } 4681 4682 long kvm_arch_dev_ioctl(struct file *filp, 4683 unsigned int ioctl, unsigned long arg) 4684 { 4685 void __user *argp = (void __user *)arg; 4686 long r; 4687 4688 switch (ioctl) { 4689 case KVM_GET_MSR_INDEX_LIST: { 4690 struct kvm_msr_list __user *user_msr_list = argp; 4691 struct kvm_msr_list msr_list; 4692 unsigned n; 4693 4694 r = -EFAULT; 4695 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4696 goto out; 4697 n = msr_list.nmsrs; 4698 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; 4699 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4700 goto out; 4701 r = -E2BIG; 4702 if (n < msr_list.nmsrs) 4703 goto out; 4704 r = -EFAULT; 4705 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 4706 num_msrs_to_save * sizeof(u32))) 4707 goto out; 4708 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 4709 &emulated_msrs, 4710 num_emulated_msrs * sizeof(u32))) 4711 goto out; 4712 r = 0; 4713 break; 4714 } 4715 case KVM_GET_SUPPORTED_CPUID: 4716 case KVM_GET_EMULATED_CPUID: { 4717 struct kvm_cpuid2 __user *cpuid_arg = argp; 4718 struct kvm_cpuid2 cpuid; 4719 4720 r = -EFAULT; 4721 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 4722 goto out; 4723 4724 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 4725 ioctl); 4726 if (r) 4727 goto out; 4728 4729 r = -EFAULT; 4730 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 4731 goto out; 4732 r = 0; 4733 break; 4734 } 4735 case KVM_X86_GET_MCE_CAP_SUPPORTED: 4736 r = -EFAULT; 4737 if (copy_to_user(argp, &kvm_caps.supported_mce_cap, 4738 sizeof(kvm_caps.supported_mce_cap))) 4739 goto out; 4740 r = 0; 4741 break; 4742 case KVM_GET_MSR_FEATURE_INDEX_LIST: { 4743 struct kvm_msr_list __user *user_msr_list = argp; 4744 struct kvm_msr_list msr_list; 4745 unsigned int n; 4746 4747 r = -EFAULT; 4748 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) 4749 goto out; 4750 n = msr_list.nmsrs; 4751 msr_list.nmsrs = num_msr_based_features; 4752 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) 4753 goto out; 4754 r = -E2BIG; 4755 if (n < msr_list.nmsrs) 4756 goto out; 4757 r = -EFAULT; 4758 if (copy_to_user(user_msr_list->indices, &msr_based_features, 4759 num_msr_based_features * sizeof(u32))) 4760 goto out; 4761 r = 0; 4762 break; 4763 } 4764 case KVM_GET_MSRS: 4765 r = msr_io(NULL, argp, do_get_msr_feature, 1); 4766 break; 4767 case KVM_GET_SUPPORTED_HV_CPUID: 4768 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); 4769 break; 4770 case KVM_GET_DEVICE_ATTR: { 4771 struct kvm_device_attr attr; 4772 r = -EFAULT; 4773 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) 4774 break; 4775 r = kvm_x86_dev_get_attr(&attr); 4776 break; 4777 } 4778 case KVM_HAS_DEVICE_ATTR: { 4779 struct kvm_device_attr attr; 4780 r = -EFAULT; 4781 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) 4782 break; 4783 r = kvm_x86_dev_has_attr(&attr); 4784 break; 4785 } 4786 default: 4787 r = -EINVAL; 4788 break; 4789 } 4790 out: 4791 return r; 4792 } 4793 4794 static void wbinvd_ipi(void *garbage) 4795 { 4796 wbinvd(); 4797 } 4798 4799 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 4800 { 4801 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 4802 } 4803 4804 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 4805 { 4806 /* Address WBINVD may be executed by guest */ 4807 if (need_emulate_wbinvd(vcpu)) { 4808 if (static_call(kvm_x86_has_wbinvd_exit)()) 4809 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4810 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 4811 smp_call_function_single(vcpu->cpu, 4812 wbinvd_ipi, NULL, 1); 4813 } 4814 4815 static_call(kvm_x86_vcpu_load)(vcpu, cpu); 4816 4817 /* Save host pkru register if supported */ 4818 vcpu->arch.host_pkru = read_pkru(); 4819 4820 /* Apply any externally detected TSC adjustments (due to suspend) */ 4821 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 4822 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 4823 vcpu->arch.tsc_offset_adjustment = 0; 4824 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 4825 } 4826 4827 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { 4828 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 4829 rdtsc() - vcpu->arch.last_host_tsc; 4830 if (tsc_delta < 0) 4831 mark_tsc_unstable("KVM discovered backwards TSC"); 4832 4833 if (kvm_check_tsc_unstable()) { 4834 u64 offset = kvm_compute_l1_tsc_offset(vcpu, 4835 vcpu->arch.last_guest_tsc); 4836 kvm_vcpu_write_tsc_offset(vcpu, offset); 4837 vcpu->arch.tsc_catchup = 1; 4838 } 4839 4840 if (kvm_lapic_hv_timer_in_use(vcpu)) 4841 kvm_lapic_restart_hv_timer(vcpu); 4842 4843 /* 4844 * On a host with synchronized TSC, there is no need to update 4845 * kvmclock on vcpu->cpu migration 4846 */ 4847 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 4848 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 4849 if (vcpu->cpu != cpu) 4850 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); 4851 vcpu->cpu = cpu; 4852 } 4853 4854 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 4855 } 4856 4857 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) 4858 { 4859 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; 4860 struct kvm_steal_time __user *st; 4861 struct kvm_memslots *slots; 4862 static const u8 preempted = KVM_VCPU_PREEMPTED; 4863 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; 4864 4865 /* 4866 * The vCPU can be marked preempted if and only if the VM-Exit was on 4867 * an instruction boundary and will not trigger guest emulation of any 4868 * kind (see vcpu_run). Vendor specific code controls (conservatively) 4869 * when this is true, for example allowing the vCPU to be marked 4870 * preempted if and only if the VM-Exit was due to a host interrupt. 4871 */ 4872 if (!vcpu->arch.at_instruction_boundary) { 4873 vcpu->stat.preemption_other++; 4874 return; 4875 } 4876 4877 vcpu->stat.preemption_reported++; 4878 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 4879 return; 4880 4881 if (vcpu->arch.st.preempted) 4882 return; 4883 4884 /* This happens on process exit */ 4885 if (unlikely(current->mm != vcpu->kvm->mm)) 4886 return; 4887 4888 slots = kvm_memslots(vcpu->kvm); 4889 4890 if (unlikely(slots->generation != ghc->generation || 4891 gpa != ghc->gpa || 4892 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) 4893 return; 4894 4895 st = (struct kvm_steal_time __user *)ghc->hva; 4896 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted)); 4897 4898 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted))) 4899 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 4900 4901 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 4902 } 4903 4904 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 4905 { 4906 int idx; 4907 4908 if (vcpu->preempted) { 4909 if (!vcpu->arch.guest_state_protected) 4910 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); 4911 4912 /* 4913 * Take the srcu lock as memslots will be accessed to check the gfn 4914 * cache generation against the memslots generation. 4915 */ 4916 idx = srcu_read_lock(&vcpu->kvm->srcu); 4917 if (kvm_xen_msr_enabled(vcpu->kvm)) 4918 kvm_xen_runstate_set_preempted(vcpu); 4919 else 4920 kvm_steal_time_set_preempted(vcpu); 4921 srcu_read_unlock(&vcpu->kvm->srcu, idx); 4922 } 4923 4924 static_call(kvm_x86_vcpu_put)(vcpu); 4925 vcpu->arch.last_host_tsc = rdtsc(); 4926 } 4927 4928 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 4929 struct kvm_lapic_state *s) 4930 { 4931 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 4932 4933 return kvm_apic_get_state(vcpu, s); 4934 } 4935 4936 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 4937 struct kvm_lapic_state *s) 4938 { 4939 int r; 4940 4941 r = kvm_apic_set_state(vcpu, s); 4942 if (r) 4943 return r; 4944 update_cr8_intercept(vcpu); 4945 4946 return 0; 4947 } 4948 4949 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) 4950 { 4951 /* 4952 * We can accept userspace's request for interrupt injection 4953 * as long as we have a place to store the interrupt number. 4954 * The actual injection will happen when the CPU is able to 4955 * deliver the interrupt. 4956 */ 4957 if (kvm_cpu_has_extint(vcpu)) 4958 return false; 4959 4960 /* Acknowledging ExtINT does not happen if LINT0 is masked. */ 4961 return (!lapic_in_kernel(vcpu) || 4962 kvm_apic_accept_pic_intr(vcpu)); 4963 } 4964 4965 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) 4966 { 4967 /* 4968 * Do not cause an interrupt window exit if an exception 4969 * is pending or an event needs reinjection; userspace 4970 * might want to inject the interrupt manually using KVM_SET_REGS 4971 * or KVM_SET_SREGS. For that to work, we must be at an 4972 * instruction boundary and with no events half-injected. 4973 */ 4974 return (kvm_arch_interrupt_allowed(vcpu) && 4975 kvm_cpu_accept_dm_intr(vcpu) && 4976 !kvm_event_needs_reinjection(vcpu) && 4977 !kvm_is_exception_pending(vcpu)); 4978 } 4979 4980 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 4981 struct kvm_interrupt *irq) 4982 { 4983 if (irq->irq >= KVM_NR_INTERRUPTS) 4984 return -EINVAL; 4985 4986 if (!irqchip_in_kernel(vcpu->kvm)) { 4987 kvm_queue_interrupt(vcpu, irq->irq, false); 4988 kvm_make_request(KVM_REQ_EVENT, vcpu); 4989 return 0; 4990 } 4991 4992 /* 4993 * With in-kernel LAPIC, we only use this to inject EXTINT, so 4994 * fail for in-kernel 8259. 4995 */ 4996 if (pic_in_kernel(vcpu->kvm)) 4997 return -ENXIO; 4998 4999 if (vcpu->arch.pending_external_vector != -1) 5000 return -EEXIST; 5001 5002 vcpu->arch.pending_external_vector = irq->irq; 5003 kvm_make_request(KVM_REQ_EVENT, vcpu); 5004 return 0; 5005 } 5006 5007 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 5008 { 5009 kvm_inject_nmi(vcpu); 5010 5011 return 0; 5012 } 5013 5014 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 5015 struct kvm_tpr_access_ctl *tac) 5016 { 5017 if (tac->flags) 5018 return -EINVAL; 5019 vcpu->arch.tpr_access_reporting = !!tac->enabled; 5020 return 0; 5021 } 5022 5023 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 5024 u64 mcg_cap) 5025 { 5026 int r; 5027 unsigned bank_num = mcg_cap & 0xff, bank; 5028 5029 r = -EINVAL; 5030 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) 5031 goto out; 5032 if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000)) 5033 goto out; 5034 r = 0; 5035 vcpu->arch.mcg_cap = mcg_cap; 5036 /* Init IA32_MCG_CTL to all 1s */ 5037 if (mcg_cap & MCG_CTL_P) 5038 vcpu->arch.mcg_ctl = ~(u64)0; 5039 /* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */ 5040 for (bank = 0; bank < bank_num; bank++) { 5041 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 5042 if (mcg_cap & MCG_CMCI_P) 5043 vcpu->arch.mci_ctl2_banks[bank] = 0; 5044 } 5045 5046 kvm_apic_after_set_mcg_cap(vcpu); 5047 5048 static_call(kvm_x86_setup_mce)(vcpu); 5049 out: 5050 return r; 5051 } 5052 5053 /* 5054 * Validate this is an UCNA (uncorrectable no action) error by checking the 5055 * MCG_STATUS and MCi_STATUS registers: 5056 * - none of the bits for Machine Check Exceptions are set 5057 * - both the VAL (valid) and UC (uncorrectable) bits are set 5058 * MCI_STATUS_PCC - Processor Context Corrupted 5059 * MCI_STATUS_S - Signaled as a Machine Check Exception 5060 * MCI_STATUS_AR - Software recoverable Action Required 5061 */ 5062 static bool is_ucna(struct kvm_x86_mce *mce) 5063 { 5064 return !mce->mcg_status && 5065 !(mce->status & (MCI_STATUS_PCC | MCI_STATUS_S | MCI_STATUS_AR)) && 5066 (mce->status & MCI_STATUS_VAL) && 5067 (mce->status & MCI_STATUS_UC); 5068 } 5069 5070 static int kvm_vcpu_x86_set_ucna(struct kvm_vcpu *vcpu, struct kvm_x86_mce *mce, u64* banks) 5071 { 5072 u64 mcg_cap = vcpu->arch.mcg_cap; 5073 5074 banks[1] = mce->status; 5075 banks[2] = mce->addr; 5076 banks[3] = mce->misc; 5077 vcpu->arch.mcg_status = mce->mcg_status; 5078 5079 if (!(mcg_cap & MCG_CMCI_P) || 5080 !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN)) 5081 return 0; 5082 5083 if (lapic_in_kernel(vcpu)) 5084 kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI); 5085 5086 return 0; 5087 } 5088 5089 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 5090 struct kvm_x86_mce *mce) 5091 { 5092 u64 mcg_cap = vcpu->arch.mcg_cap; 5093 unsigned bank_num = mcg_cap & 0xff; 5094 u64 *banks = vcpu->arch.mce_banks; 5095 5096 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 5097 return -EINVAL; 5098 5099 banks += array_index_nospec(4 * mce->bank, 4 * bank_num); 5100 5101 if (is_ucna(mce)) 5102 return kvm_vcpu_x86_set_ucna(vcpu, mce, banks); 5103 5104 /* 5105 * if IA32_MCG_CTL is not all 1s, the uncorrected error 5106 * reporting is disabled 5107 */ 5108 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 5109 vcpu->arch.mcg_ctl != ~(u64)0) 5110 return 0; 5111 /* 5112 * if IA32_MCi_CTL is not all 1s, the uncorrected error 5113 * reporting is disabled for the bank 5114 */ 5115 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 5116 return 0; 5117 if (mce->status & MCI_STATUS_UC) { 5118 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 5119 !kvm_is_cr4_bit_set(vcpu, X86_CR4_MCE)) { 5120 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 5121 return 0; 5122 } 5123 if (banks[1] & MCI_STATUS_VAL) 5124 mce->status |= MCI_STATUS_OVER; 5125 banks[2] = mce->addr; 5126 banks[3] = mce->misc; 5127 vcpu->arch.mcg_status = mce->mcg_status; 5128 banks[1] = mce->status; 5129 kvm_queue_exception(vcpu, MC_VECTOR); 5130 } else if (!(banks[1] & MCI_STATUS_VAL) 5131 || !(banks[1] & MCI_STATUS_UC)) { 5132 if (banks[1] & MCI_STATUS_VAL) 5133 mce->status |= MCI_STATUS_OVER; 5134 banks[2] = mce->addr; 5135 banks[3] = mce->misc; 5136 banks[1] = mce->status; 5137 } else 5138 banks[1] |= MCI_STATUS_OVER; 5139 return 0; 5140 } 5141 5142 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 5143 struct kvm_vcpu_events *events) 5144 { 5145 struct kvm_queued_exception *ex; 5146 5147 process_nmi(vcpu); 5148 5149 #ifdef CONFIG_KVM_SMM 5150 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 5151 process_smi(vcpu); 5152 #endif 5153 5154 /* 5155 * KVM's ABI only allows for one exception to be migrated. Luckily, 5156 * the only time there can be two queued exceptions is if there's a 5157 * non-exiting _injected_ exception, and a pending exiting exception. 5158 * In that case, ignore the VM-Exiting exception as it's an extension 5159 * of the injected exception. 5160 */ 5161 if (vcpu->arch.exception_vmexit.pending && 5162 !vcpu->arch.exception.pending && 5163 !vcpu->arch.exception.injected) 5164 ex = &vcpu->arch.exception_vmexit; 5165 else 5166 ex = &vcpu->arch.exception; 5167 5168 /* 5169 * In guest mode, payload delivery should be deferred if the exception 5170 * will be intercepted by L1, e.g. KVM should not modifying CR2 if L1 5171 * intercepts #PF, ditto for DR6 and #DBs. If the per-VM capability, 5172 * KVM_CAP_EXCEPTION_PAYLOAD, is not set, userspace may or may not 5173 * propagate the payload and so it cannot be safely deferred. Deliver 5174 * the payload if the capability hasn't been requested. 5175 */ 5176 if (!vcpu->kvm->arch.exception_payload_enabled && 5177 ex->pending && ex->has_payload) 5178 kvm_deliver_exception_payload(vcpu, ex); 5179 5180 memset(events, 0, sizeof(*events)); 5181 5182 /* 5183 * The API doesn't provide the instruction length for software 5184 * exceptions, so don't report them. As long as the guest RIP 5185 * isn't advanced, we should expect to encounter the exception 5186 * again. 5187 */ 5188 if (!kvm_exception_is_soft(ex->vector)) { 5189 events->exception.injected = ex->injected; 5190 events->exception.pending = ex->pending; 5191 /* 5192 * For ABI compatibility, deliberately conflate 5193 * pending and injected exceptions when 5194 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. 5195 */ 5196 if (!vcpu->kvm->arch.exception_payload_enabled) 5197 events->exception.injected |= ex->pending; 5198 } 5199 events->exception.nr = ex->vector; 5200 events->exception.has_error_code = ex->has_error_code; 5201 events->exception.error_code = ex->error_code; 5202 events->exception_has_payload = ex->has_payload; 5203 events->exception_payload = ex->payload; 5204 5205 events->interrupt.injected = 5206 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; 5207 events->interrupt.nr = vcpu->arch.interrupt.nr; 5208 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 5209 5210 events->nmi.injected = vcpu->arch.nmi_injected; 5211 events->nmi.pending = kvm_get_nr_pending_nmis(vcpu); 5212 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); 5213 5214 /* events->sipi_vector is never valid when reporting to user space */ 5215 5216 #ifdef CONFIG_KVM_SMM 5217 events->smi.smm = is_smm(vcpu); 5218 events->smi.pending = vcpu->arch.smi_pending; 5219 events->smi.smm_inside_nmi = 5220 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); 5221 #endif 5222 events->smi.latched_init = kvm_lapic_latched_init(vcpu); 5223 5224 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 5225 | KVM_VCPUEVENT_VALID_SHADOW 5226 | KVM_VCPUEVENT_VALID_SMM); 5227 if (vcpu->kvm->arch.exception_payload_enabled) 5228 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; 5229 if (vcpu->kvm->arch.triple_fault_event) { 5230 events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu); 5231 events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT; 5232 } 5233 } 5234 5235 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 5236 struct kvm_vcpu_events *events) 5237 { 5238 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 5239 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 5240 | KVM_VCPUEVENT_VALID_SHADOW 5241 | KVM_VCPUEVENT_VALID_SMM 5242 | KVM_VCPUEVENT_VALID_PAYLOAD 5243 | KVM_VCPUEVENT_VALID_TRIPLE_FAULT)) 5244 return -EINVAL; 5245 5246 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { 5247 if (!vcpu->kvm->arch.exception_payload_enabled) 5248 return -EINVAL; 5249 if (events->exception.pending) 5250 events->exception.injected = 0; 5251 else 5252 events->exception_has_payload = 0; 5253 } else { 5254 events->exception.pending = 0; 5255 events->exception_has_payload = 0; 5256 } 5257 5258 if ((events->exception.injected || events->exception.pending) && 5259 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) 5260 return -EINVAL; 5261 5262 /* INITs are latched while in SMM */ 5263 if (events->flags & KVM_VCPUEVENT_VALID_SMM && 5264 (events->smi.smm || events->smi.pending) && 5265 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) 5266 return -EINVAL; 5267 5268 process_nmi(vcpu); 5269 5270 /* 5271 * Flag that userspace is stuffing an exception, the next KVM_RUN will 5272 * morph the exception to a VM-Exit if appropriate. Do this only for 5273 * pending exceptions, already-injected exceptions are not subject to 5274 * intercpetion. Note, userspace that conflates pending and injected 5275 * is hosed, and will incorrectly convert an injected exception into a 5276 * pending exception, which in turn may cause a spurious VM-Exit. 5277 */ 5278 vcpu->arch.exception_from_userspace = events->exception.pending; 5279 5280 vcpu->arch.exception_vmexit.pending = false; 5281 5282 vcpu->arch.exception.injected = events->exception.injected; 5283 vcpu->arch.exception.pending = events->exception.pending; 5284 vcpu->arch.exception.vector = events->exception.nr; 5285 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 5286 vcpu->arch.exception.error_code = events->exception.error_code; 5287 vcpu->arch.exception.has_payload = events->exception_has_payload; 5288 vcpu->arch.exception.payload = events->exception_payload; 5289 5290 vcpu->arch.interrupt.injected = events->interrupt.injected; 5291 vcpu->arch.interrupt.nr = events->interrupt.nr; 5292 vcpu->arch.interrupt.soft = events->interrupt.soft; 5293 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 5294 static_call(kvm_x86_set_interrupt_shadow)(vcpu, 5295 events->interrupt.shadow); 5296 5297 vcpu->arch.nmi_injected = events->nmi.injected; 5298 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) { 5299 vcpu->arch.nmi_pending = 0; 5300 atomic_set(&vcpu->arch.nmi_queued, events->nmi.pending); 5301 kvm_make_request(KVM_REQ_NMI, vcpu); 5302 } 5303 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); 5304 5305 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 5306 lapic_in_kernel(vcpu)) 5307 vcpu->arch.apic->sipi_vector = events->sipi_vector; 5308 5309 if (events->flags & KVM_VCPUEVENT_VALID_SMM) { 5310 #ifdef CONFIG_KVM_SMM 5311 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { 5312 kvm_leave_nested(vcpu); 5313 kvm_smm_changed(vcpu, events->smi.smm); 5314 } 5315 5316 vcpu->arch.smi_pending = events->smi.pending; 5317 5318 if (events->smi.smm) { 5319 if (events->smi.smm_inside_nmi) 5320 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; 5321 else 5322 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; 5323 } 5324 5325 #else 5326 if (events->smi.smm || events->smi.pending || 5327 events->smi.smm_inside_nmi) 5328 return -EINVAL; 5329 #endif 5330 5331 if (lapic_in_kernel(vcpu)) { 5332 if (events->smi.latched_init) 5333 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 5334 else 5335 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 5336 } 5337 } 5338 5339 if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) { 5340 if (!vcpu->kvm->arch.triple_fault_event) 5341 return -EINVAL; 5342 if (events->triple_fault.pending) 5343 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 5344 else 5345 kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu); 5346 } 5347 5348 kvm_make_request(KVM_REQ_EVENT, vcpu); 5349 5350 return 0; 5351 } 5352 5353 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 5354 struct kvm_debugregs *dbgregs) 5355 { 5356 unsigned long val; 5357 5358 memset(dbgregs, 0, sizeof(*dbgregs)); 5359 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 5360 kvm_get_dr(vcpu, 6, &val); 5361 dbgregs->dr6 = val; 5362 dbgregs->dr7 = vcpu->arch.dr7; 5363 } 5364 5365 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 5366 struct kvm_debugregs *dbgregs) 5367 { 5368 if (dbgregs->flags) 5369 return -EINVAL; 5370 5371 if (!kvm_dr6_valid(dbgregs->dr6)) 5372 return -EINVAL; 5373 if (!kvm_dr7_valid(dbgregs->dr7)) 5374 return -EINVAL; 5375 5376 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 5377 kvm_update_dr0123(vcpu); 5378 vcpu->arch.dr6 = dbgregs->dr6; 5379 vcpu->arch.dr7 = dbgregs->dr7; 5380 kvm_update_dr7(vcpu); 5381 5382 return 0; 5383 } 5384 5385 5386 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu, 5387 u8 *state, unsigned int size) 5388 { 5389 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 5390 return; 5391 5392 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, state, size, 5393 vcpu->arch.guest_fpu.fpstate->user_xfeatures, 5394 vcpu->arch.pkru); 5395 } 5396 5397 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 5398 struct kvm_xsave *guest_xsave) 5399 { 5400 return kvm_vcpu_ioctl_x86_get_xsave2(vcpu, (void *)guest_xsave->region, 5401 sizeof(guest_xsave->region)); 5402 } 5403 5404 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 5405 struct kvm_xsave *guest_xsave) 5406 { 5407 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 5408 return 0; 5409 5410 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu, 5411 guest_xsave->region, 5412 kvm_caps.supported_xcr0, 5413 &vcpu->arch.pkru); 5414 } 5415 5416 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 5417 struct kvm_xcrs *guest_xcrs) 5418 { 5419 if (!boot_cpu_has(X86_FEATURE_XSAVE)) { 5420 guest_xcrs->nr_xcrs = 0; 5421 return; 5422 } 5423 5424 guest_xcrs->nr_xcrs = 1; 5425 guest_xcrs->flags = 0; 5426 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 5427 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 5428 } 5429 5430 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 5431 struct kvm_xcrs *guest_xcrs) 5432 { 5433 int i, r = 0; 5434 5435 if (!boot_cpu_has(X86_FEATURE_XSAVE)) 5436 return -EINVAL; 5437 5438 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 5439 return -EINVAL; 5440 5441 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 5442 /* Only support XCR0 currently */ 5443 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 5444 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 5445 guest_xcrs->xcrs[i].value); 5446 break; 5447 } 5448 if (r) 5449 r = -EINVAL; 5450 return r; 5451 } 5452 5453 /* 5454 * kvm_set_guest_paused() indicates to the guest kernel that it has been 5455 * stopped by the hypervisor. This function will be called from the host only. 5456 * EINVAL is returned when the host attempts to set the flag for a guest that 5457 * does not support pv clocks. 5458 */ 5459 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 5460 { 5461 if (!vcpu->arch.pv_time.active) 5462 return -EINVAL; 5463 vcpu->arch.pvclock_set_guest_stopped_request = true; 5464 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5465 return 0; 5466 } 5467 5468 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu, 5469 struct kvm_device_attr *attr) 5470 { 5471 int r; 5472 5473 switch (attr->attr) { 5474 case KVM_VCPU_TSC_OFFSET: 5475 r = 0; 5476 break; 5477 default: 5478 r = -ENXIO; 5479 } 5480 5481 return r; 5482 } 5483 5484 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu, 5485 struct kvm_device_attr *attr) 5486 { 5487 u64 __user *uaddr = kvm_get_attr_addr(attr); 5488 int r; 5489 5490 if (IS_ERR(uaddr)) 5491 return PTR_ERR(uaddr); 5492 5493 switch (attr->attr) { 5494 case KVM_VCPU_TSC_OFFSET: 5495 r = -EFAULT; 5496 if (put_user(vcpu->arch.l1_tsc_offset, uaddr)) 5497 break; 5498 r = 0; 5499 break; 5500 default: 5501 r = -ENXIO; 5502 } 5503 5504 return r; 5505 } 5506 5507 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu, 5508 struct kvm_device_attr *attr) 5509 { 5510 u64 __user *uaddr = kvm_get_attr_addr(attr); 5511 struct kvm *kvm = vcpu->kvm; 5512 int r; 5513 5514 if (IS_ERR(uaddr)) 5515 return PTR_ERR(uaddr); 5516 5517 switch (attr->attr) { 5518 case KVM_VCPU_TSC_OFFSET: { 5519 u64 offset, tsc, ns; 5520 unsigned long flags; 5521 bool matched; 5522 5523 r = -EFAULT; 5524 if (get_user(offset, uaddr)) 5525 break; 5526 5527 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 5528 5529 matched = (vcpu->arch.virtual_tsc_khz && 5530 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz && 5531 kvm->arch.last_tsc_offset == offset); 5532 5533 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset; 5534 ns = get_kvmclock_base_ns(); 5535 5536 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched); 5537 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 5538 5539 r = 0; 5540 break; 5541 } 5542 default: 5543 r = -ENXIO; 5544 } 5545 5546 return r; 5547 } 5548 5549 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu, 5550 unsigned int ioctl, 5551 void __user *argp) 5552 { 5553 struct kvm_device_attr attr; 5554 int r; 5555 5556 if (copy_from_user(&attr, argp, sizeof(attr))) 5557 return -EFAULT; 5558 5559 if (attr.group != KVM_VCPU_TSC_CTRL) 5560 return -ENXIO; 5561 5562 switch (ioctl) { 5563 case KVM_HAS_DEVICE_ATTR: 5564 r = kvm_arch_tsc_has_attr(vcpu, &attr); 5565 break; 5566 case KVM_GET_DEVICE_ATTR: 5567 r = kvm_arch_tsc_get_attr(vcpu, &attr); 5568 break; 5569 case KVM_SET_DEVICE_ATTR: 5570 r = kvm_arch_tsc_set_attr(vcpu, &attr); 5571 break; 5572 } 5573 5574 return r; 5575 } 5576 5577 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 5578 struct kvm_enable_cap *cap) 5579 { 5580 int r; 5581 uint16_t vmcs_version; 5582 void __user *user_ptr; 5583 5584 if (cap->flags) 5585 return -EINVAL; 5586 5587 switch (cap->cap) { 5588 case KVM_CAP_HYPERV_SYNIC2: 5589 if (cap->args[0]) 5590 return -EINVAL; 5591 fallthrough; 5592 5593 case KVM_CAP_HYPERV_SYNIC: 5594 if (!irqchip_in_kernel(vcpu->kvm)) 5595 return -EINVAL; 5596 return kvm_hv_activate_synic(vcpu, cap->cap == 5597 KVM_CAP_HYPERV_SYNIC2); 5598 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: 5599 if (!kvm_x86_ops.nested_ops->enable_evmcs) 5600 return -ENOTTY; 5601 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); 5602 if (!r) { 5603 user_ptr = (void __user *)(uintptr_t)cap->args[0]; 5604 if (copy_to_user(user_ptr, &vmcs_version, 5605 sizeof(vmcs_version))) 5606 r = -EFAULT; 5607 } 5608 return r; 5609 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: 5610 if (!kvm_x86_ops.enable_l2_tlb_flush) 5611 return -ENOTTY; 5612 5613 return static_call(kvm_x86_enable_l2_tlb_flush)(vcpu); 5614 5615 case KVM_CAP_HYPERV_ENFORCE_CPUID: 5616 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]); 5617 5618 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: 5619 vcpu->arch.pv_cpuid.enforce = cap->args[0]; 5620 if (vcpu->arch.pv_cpuid.enforce) 5621 kvm_update_pv_runtime(vcpu); 5622 5623 return 0; 5624 default: 5625 return -EINVAL; 5626 } 5627 } 5628 5629 long kvm_arch_vcpu_ioctl(struct file *filp, 5630 unsigned int ioctl, unsigned long arg) 5631 { 5632 struct kvm_vcpu *vcpu = filp->private_data; 5633 void __user *argp = (void __user *)arg; 5634 int r; 5635 union { 5636 struct kvm_sregs2 *sregs2; 5637 struct kvm_lapic_state *lapic; 5638 struct kvm_xsave *xsave; 5639 struct kvm_xcrs *xcrs; 5640 void *buffer; 5641 } u; 5642 5643 vcpu_load(vcpu); 5644 5645 u.buffer = NULL; 5646 switch (ioctl) { 5647 case KVM_GET_LAPIC: { 5648 r = -EINVAL; 5649 if (!lapic_in_kernel(vcpu)) 5650 goto out; 5651 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), 5652 GFP_KERNEL_ACCOUNT); 5653 5654 r = -ENOMEM; 5655 if (!u.lapic) 5656 goto out; 5657 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 5658 if (r) 5659 goto out; 5660 r = -EFAULT; 5661 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 5662 goto out; 5663 r = 0; 5664 break; 5665 } 5666 case KVM_SET_LAPIC: { 5667 r = -EINVAL; 5668 if (!lapic_in_kernel(vcpu)) 5669 goto out; 5670 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 5671 if (IS_ERR(u.lapic)) { 5672 r = PTR_ERR(u.lapic); 5673 goto out_nofree; 5674 } 5675 5676 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 5677 break; 5678 } 5679 case KVM_INTERRUPT: { 5680 struct kvm_interrupt irq; 5681 5682 r = -EFAULT; 5683 if (copy_from_user(&irq, argp, sizeof(irq))) 5684 goto out; 5685 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 5686 break; 5687 } 5688 case KVM_NMI: { 5689 r = kvm_vcpu_ioctl_nmi(vcpu); 5690 break; 5691 } 5692 case KVM_SMI: { 5693 r = kvm_inject_smi(vcpu); 5694 break; 5695 } 5696 case KVM_SET_CPUID: { 5697 struct kvm_cpuid __user *cpuid_arg = argp; 5698 struct kvm_cpuid cpuid; 5699 5700 r = -EFAULT; 5701 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5702 goto out; 5703 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 5704 break; 5705 } 5706 case KVM_SET_CPUID2: { 5707 struct kvm_cpuid2 __user *cpuid_arg = argp; 5708 struct kvm_cpuid2 cpuid; 5709 5710 r = -EFAULT; 5711 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5712 goto out; 5713 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 5714 cpuid_arg->entries); 5715 break; 5716 } 5717 case KVM_GET_CPUID2: { 5718 struct kvm_cpuid2 __user *cpuid_arg = argp; 5719 struct kvm_cpuid2 cpuid; 5720 5721 r = -EFAULT; 5722 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) 5723 goto out; 5724 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 5725 cpuid_arg->entries); 5726 if (r) 5727 goto out; 5728 r = -EFAULT; 5729 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) 5730 goto out; 5731 r = 0; 5732 break; 5733 } 5734 case KVM_GET_MSRS: { 5735 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5736 r = msr_io(vcpu, argp, do_get_msr, 1); 5737 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5738 break; 5739 } 5740 case KVM_SET_MSRS: { 5741 int idx = srcu_read_lock(&vcpu->kvm->srcu); 5742 r = msr_io(vcpu, argp, do_set_msr, 0); 5743 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5744 break; 5745 } 5746 case KVM_TPR_ACCESS_REPORTING: { 5747 struct kvm_tpr_access_ctl tac; 5748 5749 r = -EFAULT; 5750 if (copy_from_user(&tac, argp, sizeof(tac))) 5751 goto out; 5752 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 5753 if (r) 5754 goto out; 5755 r = -EFAULT; 5756 if (copy_to_user(argp, &tac, sizeof(tac))) 5757 goto out; 5758 r = 0; 5759 break; 5760 }; 5761 case KVM_SET_VAPIC_ADDR: { 5762 struct kvm_vapic_addr va; 5763 int idx; 5764 5765 r = -EINVAL; 5766 if (!lapic_in_kernel(vcpu)) 5767 goto out; 5768 r = -EFAULT; 5769 if (copy_from_user(&va, argp, sizeof(va))) 5770 goto out; 5771 idx = srcu_read_lock(&vcpu->kvm->srcu); 5772 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 5773 srcu_read_unlock(&vcpu->kvm->srcu, idx); 5774 break; 5775 } 5776 case KVM_X86_SETUP_MCE: { 5777 u64 mcg_cap; 5778 5779 r = -EFAULT; 5780 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) 5781 goto out; 5782 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 5783 break; 5784 } 5785 case KVM_X86_SET_MCE: { 5786 struct kvm_x86_mce mce; 5787 5788 r = -EFAULT; 5789 if (copy_from_user(&mce, argp, sizeof(mce))) 5790 goto out; 5791 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 5792 break; 5793 } 5794 case KVM_GET_VCPU_EVENTS: { 5795 struct kvm_vcpu_events events; 5796 5797 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 5798 5799 r = -EFAULT; 5800 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 5801 break; 5802 r = 0; 5803 break; 5804 } 5805 case KVM_SET_VCPU_EVENTS: { 5806 struct kvm_vcpu_events events; 5807 5808 r = -EFAULT; 5809 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 5810 break; 5811 5812 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 5813 break; 5814 } 5815 case KVM_GET_DEBUGREGS: { 5816 struct kvm_debugregs dbgregs; 5817 5818 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 5819 5820 r = -EFAULT; 5821 if (copy_to_user(argp, &dbgregs, 5822 sizeof(struct kvm_debugregs))) 5823 break; 5824 r = 0; 5825 break; 5826 } 5827 case KVM_SET_DEBUGREGS: { 5828 struct kvm_debugregs dbgregs; 5829 5830 r = -EFAULT; 5831 if (copy_from_user(&dbgregs, argp, 5832 sizeof(struct kvm_debugregs))) 5833 break; 5834 5835 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 5836 break; 5837 } 5838 case KVM_GET_XSAVE: { 5839 r = -EINVAL; 5840 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave)) 5841 break; 5842 5843 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); 5844 r = -ENOMEM; 5845 if (!u.xsave) 5846 break; 5847 5848 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 5849 5850 r = -EFAULT; 5851 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 5852 break; 5853 r = 0; 5854 break; 5855 } 5856 case KVM_SET_XSAVE: { 5857 int size = vcpu->arch.guest_fpu.uabi_size; 5858 5859 u.xsave = memdup_user(argp, size); 5860 if (IS_ERR(u.xsave)) { 5861 r = PTR_ERR(u.xsave); 5862 goto out_nofree; 5863 } 5864 5865 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 5866 break; 5867 } 5868 5869 case KVM_GET_XSAVE2: { 5870 int size = vcpu->arch.guest_fpu.uabi_size; 5871 5872 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT); 5873 r = -ENOMEM; 5874 if (!u.xsave) 5875 break; 5876 5877 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size); 5878 5879 r = -EFAULT; 5880 if (copy_to_user(argp, u.xsave, size)) 5881 break; 5882 5883 r = 0; 5884 break; 5885 } 5886 5887 case KVM_GET_XCRS: { 5888 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); 5889 r = -ENOMEM; 5890 if (!u.xcrs) 5891 break; 5892 5893 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 5894 5895 r = -EFAULT; 5896 if (copy_to_user(argp, u.xcrs, 5897 sizeof(struct kvm_xcrs))) 5898 break; 5899 r = 0; 5900 break; 5901 } 5902 case KVM_SET_XCRS: { 5903 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 5904 if (IS_ERR(u.xcrs)) { 5905 r = PTR_ERR(u.xcrs); 5906 goto out_nofree; 5907 } 5908 5909 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 5910 break; 5911 } 5912 case KVM_SET_TSC_KHZ: { 5913 u32 user_tsc_khz; 5914 5915 r = -EINVAL; 5916 user_tsc_khz = (u32)arg; 5917 5918 if (kvm_caps.has_tsc_control && 5919 user_tsc_khz >= kvm_caps.max_guest_tsc_khz) 5920 goto out; 5921 5922 if (user_tsc_khz == 0) 5923 user_tsc_khz = tsc_khz; 5924 5925 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) 5926 r = 0; 5927 5928 goto out; 5929 } 5930 case KVM_GET_TSC_KHZ: { 5931 r = vcpu->arch.virtual_tsc_khz; 5932 goto out; 5933 } 5934 case KVM_KVMCLOCK_CTRL: { 5935 r = kvm_set_guest_paused(vcpu); 5936 goto out; 5937 } 5938 case KVM_ENABLE_CAP: { 5939 struct kvm_enable_cap cap; 5940 5941 r = -EFAULT; 5942 if (copy_from_user(&cap, argp, sizeof(cap))) 5943 goto out; 5944 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 5945 break; 5946 } 5947 case KVM_GET_NESTED_STATE: { 5948 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5949 u32 user_data_size; 5950 5951 r = -EINVAL; 5952 if (!kvm_x86_ops.nested_ops->get_state) 5953 break; 5954 5955 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); 5956 r = -EFAULT; 5957 if (get_user(user_data_size, &user_kvm_nested_state->size)) 5958 break; 5959 5960 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, 5961 user_data_size); 5962 if (r < 0) 5963 break; 5964 5965 if (r > user_data_size) { 5966 if (put_user(r, &user_kvm_nested_state->size)) 5967 r = -EFAULT; 5968 else 5969 r = -E2BIG; 5970 break; 5971 } 5972 5973 r = 0; 5974 break; 5975 } 5976 case KVM_SET_NESTED_STATE: { 5977 struct kvm_nested_state __user *user_kvm_nested_state = argp; 5978 struct kvm_nested_state kvm_state; 5979 int idx; 5980 5981 r = -EINVAL; 5982 if (!kvm_x86_ops.nested_ops->set_state) 5983 break; 5984 5985 r = -EFAULT; 5986 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) 5987 break; 5988 5989 r = -EINVAL; 5990 if (kvm_state.size < sizeof(kvm_state)) 5991 break; 5992 5993 if (kvm_state.flags & 5994 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE 5995 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING 5996 | KVM_STATE_NESTED_GIF_SET)) 5997 break; 5998 5999 /* nested_run_pending implies guest_mode. */ 6000 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) 6001 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) 6002 break; 6003 6004 idx = srcu_read_lock(&vcpu->kvm->srcu); 6005 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); 6006 srcu_read_unlock(&vcpu->kvm->srcu, idx); 6007 break; 6008 } 6009 case KVM_GET_SUPPORTED_HV_CPUID: 6010 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); 6011 break; 6012 #ifdef CONFIG_KVM_XEN 6013 case KVM_XEN_VCPU_GET_ATTR: { 6014 struct kvm_xen_vcpu_attr xva; 6015 6016 r = -EFAULT; 6017 if (copy_from_user(&xva, argp, sizeof(xva))) 6018 goto out; 6019 r = kvm_xen_vcpu_get_attr(vcpu, &xva); 6020 if (!r && copy_to_user(argp, &xva, sizeof(xva))) 6021 r = -EFAULT; 6022 break; 6023 } 6024 case KVM_XEN_VCPU_SET_ATTR: { 6025 struct kvm_xen_vcpu_attr xva; 6026 6027 r = -EFAULT; 6028 if (copy_from_user(&xva, argp, sizeof(xva))) 6029 goto out; 6030 r = kvm_xen_vcpu_set_attr(vcpu, &xva); 6031 break; 6032 } 6033 #endif 6034 case KVM_GET_SREGS2: { 6035 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL); 6036 r = -ENOMEM; 6037 if (!u.sregs2) 6038 goto out; 6039 __get_sregs2(vcpu, u.sregs2); 6040 r = -EFAULT; 6041 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2))) 6042 goto out; 6043 r = 0; 6044 break; 6045 } 6046 case KVM_SET_SREGS2: { 6047 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2)); 6048 if (IS_ERR(u.sregs2)) { 6049 r = PTR_ERR(u.sregs2); 6050 u.sregs2 = NULL; 6051 goto out; 6052 } 6053 r = __set_sregs2(vcpu, u.sregs2); 6054 break; 6055 } 6056 case KVM_HAS_DEVICE_ATTR: 6057 case KVM_GET_DEVICE_ATTR: 6058 case KVM_SET_DEVICE_ATTR: 6059 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp); 6060 break; 6061 default: 6062 r = -EINVAL; 6063 } 6064 out: 6065 kfree(u.buffer); 6066 out_nofree: 6067 vcpu_put(vcpu); 6068 return r; 6069 } 6070 6071 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 6072 { 6073 return VM_FAULT_SIGBUS; 6074 } 6075 6076 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 6077 { 6078 int ret; 6079 6080 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 6081 return -EINVAL; 6082 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); 6083 return ret; 6084 } 6085 6086 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 6087 u64 ident_addr) 6088 { 6089 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); 6090 } 6091 6092 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 6093 unsigned long kvm_nr_mmu_pages) 6094 { 6095 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 6096 return -EINVAL; 6097 6098 mutex_lock(&kvm->slots_lock); 6099 6100 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 6101 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 6102 6103 mutex_unlock(&kvm->slots_lock); 6104 return 0; 6105 } 6106 6107 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 6108 { 6109 struct kvm_pic *pic = kvm->arch.vpic; 6110 int r; 6111 6112 r = 0; 6113 switch (chip->chip_id) { 6114 case KVM_IRQCHIP_PIC_MASTER: 6115 memcpy(&chip->chip.pic, &pic->pics[0], 6116 sizeof(struct kvm_pic_state)); 6117 break; 6118 case KVM_IRQCHIP_PIC_SLAVE: 6119 memcpy(&chip->chip.pic, &pic->pics[1], 6120 sizeof(struct kvm_pic_state)); 6121 break; 6122 case KVM_IRQCHIP_IOAPIC: 6123 kvm_get_ioapic(kvm, &chip->chip.ioapic); 6124 break; 6125 default: 6126 r = -EINVAL; 6127 break; 6128 } 6129 return r; 6130 } 6131 6132 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 6133 { 6134 struct kvm_pic *pic = kvm->arch.vpic; 6135 int r; 6136 6137 r = 0; 6138 switch (chip->chip_id) { 6139 case KVM_IRQCHIP_PIC_MASTER: 6140 spin_lock(&pic->lock); 6141 memcpy(&pic->pics[0], &chip->chip.pic, 6142 sizeof(struct kvm_pic_state)); 6143 spin_unlock(&pic->lock); 6144 break; 6145 case KVM_IRQCHIP_PIC_SLAVE: 6146 spin_lock(&pic->lock); 6147 memcpy(&pic->pics[1], &chip->chip.pic, 6148 sizeof(struct kvm_pic_state)); 6149 spin_unlock(&pic->lock); 6150 break; 6151 case KVM_IRQCHIP_IOAPIC: 6152 kvm_set_ioapic(kvm, &chip->chip.ioapic); 6153 break; 6154 default: 6155 r = -EINVAL; 6156 break; 6157 } 6158 kvm_pic_update_irq(pic); 6159 return r; 6160 } 6161 6162 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 6163 { 6164 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; 6165 6166 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); 6167 6168 mutex_lock(&kps->lock); 6169 memcpy(ps, &kps->channels, sizeof(*ps)); 6170 mutex_unlock(&kps->lock); 6171 return 0; 6172 } 6173 6174 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 6175 { 6176 int i; 6177 struct kvm_pit *pit = kvm->arch.vpit; 6178 6179 mutex_lock(&pit->pit_state.lock); 6180 memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); 6181 for (i = 0; i < 3; i++) 6182 kvm_pit_load_count(pit, i, ps->channels[i].count, 0); 6183 mutex_unlock(&pit->pit_state.lock); 6184 return 0; 6185 } 6186 6187 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 6188 { 6189 mutex_lock(&kvm->arch.vpit->pit_state.lock); 6190 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 6191 sizeof(ps->channels)); 6192 ps->flags = kvm->arch.vpit->pit_state.flags; 6193 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 6194 memset(&ps->reserved, 0, sizeof(ps->reserved)); 6195 return 0; 6196 } 6197 6198 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 6199 { 6200 int start = 0; 6201 int i; 6202 u32 prev_legacy, cur_legacy; 6203 struct kvm_pit *pit = kvm->arch.vpit; 6204 6205 mutex_lock(&pit->pit_state.lock); 6206 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 6207 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 6208 if (!prev_legacy && cur_legacy) 6209 start = 1; 6210 memcpy(&pit->pit_state.channels, &ps->channels, 6211 sizeof(pit->pit_state.channels)); 6212 pit->pit_state.flags = ps->flags; 6213 for (i = 0; i < 3; i++) 6214 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, 6215 start && i == 0); 6216 mutex_unlock(&pit->pit_state.lock); 6217 return 0; 6218 } 6219 6220 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 6221 struct kvm_reinject_control *control) 6222 { 6223 struct kvm_pit *pit = kvm->arch.vpit; 6224 6225 /* pit->pit_state.lock was overloaded to prevent userspace from getting 6226 * an inconsistent state after running multiple KVM_REINJECT_CONTROL 6227 * ioctls in parallel. Use a separate lock if that ioctl isn't rare. 6228 */ 6229 mutex_lock(&pit->pit_state.lock); 6230 kvm_pit_set_reinject(pit, control->pit_reinject); 6231 mutex_unlock(&pit->pit_state.lock); 6232 6233 return 0; 6234 } 6235 6236 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 6237 { 6238 6239 /* 6240 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called 6241 * before reporting dirty_bitmap to userspace. KVM flushes the buffers 6242 * on all VM-Exits, thus we only need to kick running vCPUs to force a 6243 * VM-Exit. 6244 */ 6245 struct kvm_vcpu *vcpu; 6246 unsigned long i; 6247 6248 kvm_for_each_vcpu(i, vcpu, kvm) 6249 kvm_vcpu_kick(vcpu); 6250 } 6251 6252 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 6253 bool line_status) 6254 { 6255 if (!irqchip_in_kernel(kvm)) 6256 return -ENXIO; 6257 6258 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 6259 irq_event->irq, irq_event->level, 6260 line_status); 6261 return 0; 6262 } 6263 6264 int kvm_vm_ioctl_enable_cap(struct kvm *kvm, 6265 struct kvm_enable_cap *cap) 6266 { 6267 int r; 6268 6269 if (cap->flags) 6270 return -EINVAL; 6271 6272 switch (cap->cap) { 6273 case KVM_CAP_DISABLE_QUIRKS2: 6274 r = -EINVAL; 6275 if (cap->args[0] & ~KVM_X86_VALID_QUIRKS) 6276 break; 6277 fallthrough; 6278 case KVM_CAP_DISABLE_QUIRKS: 6279 kvm->arch.disabled_quirks = cap->args[0]; 6280 r = 0; 6281 break; 6282 case KVM_CAP_SPLIT_IRQCHIP: { 6283 mutex_lock(&kvm->lock); 6284 r = -EINVAL; 6285 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) 6286 goto split_irqchip_unlock; 6287 r = -EEXIST; 6288 if (irqchip_in_kernel(kvm)) 6289 goto split_irqchip_unlock; 6290 if (kvm->created_vcpus) 6291 goto split_irqchip_unlock; 6292 r = kvm_setup_empty_irq_routing(kvm); 6293 if (r) 6294 goto split_irqchip_unlock; 6295 /* Pairs with irqchip_in_kernel. */ 6296 smp_wmb(); 6297 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; 6298 kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; 6299 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT); 6300 r = 0; 6301 split_irqchip_unlock: 6302 mutex_unlock(&kvm->lock); 6303 break; 6304 } 6305 case KVM_CAP_X2APIC_API: 6306 r = -EINVAL; 6307 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) 6308 break; 6309 6310 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) 6311 kvm->arch.x2apic_format = true; 6312 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) 6313 kvm->arch.x2apic_broadcast_quirk_disabled = true; 6314 6315 r = 0; 6316 break; 6317 case KVM_CAP_X86_DISABLE_EXITS: 6318 r = -EINVAL; 6319 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) 6320 break; 6321 6322 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) 6323 kvm->arch.pause_in_guest = true; 6324 6325 #define SMT_RSB_MSG "This processor is affected by the Cross-Thread Return Predictions vulnerability. " \ 6326 "KVM_CAP_X86_DISABLE_EXITS should only be used with SMT disabled or trusted guests." 6327 6328 if (!mitigate_smt_rsb) { 6329 if (boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible() && 6330 (cap->args[0] & ~KVM_X86_DISABLE_EXITS_PAUSE)) 6331 pr_warn_once(SMT_RSB_MSG); 6332 6333 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && 6334 kvm_can_mwait_in_guest()) 6335 kvm->arch.mwait_in_guest = true; 6336 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) 6337 kvm->arch.hlt_in_guest = true; 6338 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) 6339 kvm->arch.cstate_in_guest = true; 6340 } 6341 6342 r = 0; 6343 break; 6344 case KVM_CAP_MSR_PLATFORM_INFO: 6345 kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; 6346 r = 0; 6347 break; 6348 case KVM_CAP_EXCEPTION_PAYLOAD: 6349 kvm->arch.exception_payload_enabled = cap->args[0]; 6350 r = 0; 6351 break; 6352 case KVM_CAP_X86_TRIPLE_FAULT_EVENT: 6353 kvm->arch.triple_fault_event = cap->args[0]; 6354 r = 0; 6355 break; 6356 case KVM_CAP_X86_USER_SPACE_MSR: 6357 r = -EINVAL; 6358 if (cap->args[0] & ~KVM_MSR_EXIT_REASON_VALID_MASK) 6359 break; 6360 kvm->arch.user_space_msr_mask = cap->args[0]; 6361 r = 0; 6362 break; 6363 case KVM_CAP_X86_BUS_LOCK_EXIT: 6364 r = -EINVAL; 6365 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) 6366 break; 6367 6368 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && 6369 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) 6370 break; 6371 6372 if (kvm_caps.has_bus_lock_exit && 6373 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) 6374 kvm->arch.bus_lock_detection_enabled = true; 6375 r = 0; 6376 break; 6377 #ifdef CONFIG_X86_SGX_KVM 6378 case KVM_CAP_SGX_ATTRIBUTE: { 6379 unsigned long allowed_attributes = 0; 6380 6381 r = sgx_set_attribute(&allowed_attributes, cap->args[0]); 6382 if (r) 6383 break; 6384 6385 /* KVM only supports the PROVISIONKEY privileged attribute. */ 6386 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && 6387 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) 6388 kvm->arch.sgx_provisioning_allowed = true; 6389 else 6390 r = -EINVAL; 6391 break; 6392 } 6393 #endif 6394 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: 6395 r = -EINVAL; 6396 if (!kvm_x86_ops.vm_copy_enc_context_from) 6397 break; 6398 6399 r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]); 6400 break; 6401 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: 6402 r = -EINVAL; 6403 if (!kvm_x86_ops.vm_move_enc_context_from) 6404 break; 6405 6406 r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]); 6407 break; 6408 case KVM_CAP_EXIT_HYPERCALL: 6409 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) { 6410 r = -EINVAL; 6411 break; 6412 } 6413 kvm->arch.hypercall_exit_enabled = cap->args[0]; 6414 r = 0; 6415 break; 6416 case KVM_CAP_EXIT_ON_EMULATION_FAILURE: 6417 r = -EINVAL; 6418 if (cap->args[0] & ~1) 6419 break; 6420 kvm->arch.exit_on_emulation_error = cap->args[0]; 6421 r = 0; 6422 break; 6423 case KVM_CAP_PMU_CAPABILITY: 6424 r = -EINVAL; 6425 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK)) 6426 break; 6427 6428 mutex_lock(&kvm->lock); 6429 if (!kvm->created_vcpus) { 6430 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE); 6431 r = 0; 6432 } 6433 mutex_unlock(&kvm->lock); 6434 break; 6435 case KVM_CAP_MAX_VCPU_ID: 6436 r = -EINVAL; 6437 if (cap->args[0] > KVM_MAX_VCPU_IDS) 6438 break; 6439 6440 mutex_lock(&kvm->lock); 6441 if (kvm->arch.max_vcpu_ids == cap->args[0]) { 6442 r = 0; 6443 } else if (!kvm->arch.max_vcpu_ids) { 6444 kvm->arch.max_vcpu_ids = cap->args[0]; 6445 r = 0; 6446 } 6447 mutex_unlock(&kvm->lock); 6448 break; 6449 case KVM_CAP_X86_NOTIFY_VMEXIT: 6450 r = -EINVAL; 6451 if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS) 6452 break; 6453 if (!kvm_caps.has_notify_vmexit) 6454 break; 6455 if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED)) 6456 break; 6457 mutex_lock(&kvm->lock); 6458 if (!kvm->created_vcpus) { 6459 kvm->arch.notify_window = cap->args[0] >> 32; 6460 kvm->arch.notify_vmexit_flags = (u32)cap->args[0]; 6461 r = 0; 6462 } 6463 mutex_unlock(&kvm->lock); 6464 break; 6465 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES: 6466 r = -EINVAL; 6467 6468 /* 6469 * Since the risk of disabling NX hugepages is a guest crashing 6470 * the system, ensure the userspace process has permission to 6471 * reboot the system. 6472 * 6473 * Note that unlike the reboot() syscall, the process must have 6474 * this capability in the root namespace because exposing 6475 * /dev/kvm into a container does not limit the scope of the 6476 * iTLB multihit bug to that container. In other words, 6477 * this must use capable(), not ns_capable(). 6478 */ 6479 if (!capable(CAP_SYS_BOOT)) { 6480 r = -EPERM; 6481 break; 6482 } 6483 6484 if (cap->args[0]) 6485 break; 6486 6487 mutex_lock(&kvm->lock); 6488 if (!kvm->created_vcpus) { 6489 kvm->arch.disable_nx_huge_pages = true; 6490 r = 0; 6491 } 6492 mutex_unlock(&kvm->lock); 6493 break; 6494 default: 6495 r = -EINVAL; 6496 break; 6497 } 6498 return r; 6499 } 6500 6501 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) 6502 { 6503 struct kvm_x86_msr_filter *msr_filter; 6504 6505 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); 6506 if (!msr_filter) 6507 return NULL; 6508 6509 msr_filter->default_allow = default_allow; 6510 return msr_filter; 6511 } 6512 6513 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) 6514 { 6515 u32 i; 6516 6517 if (!msr_filter) 6518 return; 6519 6520 for (i = 0; i < msr_filter->count; i++) 6521 kfree(msr_filter->ranges[i].bitmap); 6522 6523 kfree(msr_filter); 6524 } 6525 6526 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, 6527 struct kvm_msr_filter_range *user_range) 6528 { 6529 unsigned long *bitmap; 6530 size_t bitmap_size; 6531 6532 if (!user_range->nmsrs) 6533 return 0; 6534 6535 if (user_range->flags & ~KVM_MSR_FILTER_RANGE_VALID_MASK) 6536 return -EINVAL; 6537 6538 if (!user_range->flags) 6539 return -EINVAL; 6540 6541 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); 6542 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) 6543 return -EINVAL; 6544 6545 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); 6546 if (IS_ERR(bitmap)) 6547 return PTR_ERR(bitmap); 6548 6549 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { 6550 .flags = user_range->flags, 6551 .base = user_range->base, 6552 .nmsrs = user_range->nmsrs, 6553 .bitmap = bitmap, 6554 }; 6555 6556 msr_filter->count++; 6557 return 0; 6558 } 6559 6560 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, 6561 struct kvm_msr_filter *filter) 6562 { 6563 struct kvm_x86_msr_filter *new_filter, *old_filter; 6564 bool default_allow; 6565 bool empty = true; 6566 int r; 6567 u32 i; 6568 6569 if (filter->flags & ~KVM_MSR_FILTER_VALID_MASK) 6570 return -EINVAL; 6571 6572 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) 6573 empty &= !filter->ranges[i].nmsrs; 6574 6575 default_allow = !(filter->flags & KVM_MSR_FILTER_DEFAULT_DENY); 6576 if (empty && !default_allow) 6577 return -EINVAL; 6578 6579 new_filter = kvm_alloc_msr_filter(default_allow); 6580 if (!new_filter) 6581 return -ENOMEM; 6582 6583 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) { 6584 r = kvm_add_msr_filter(new_filter, &filter->ranges[i]); 6585 if (r) { 6586 kvm_free_msr_filter(new_filter); 6587 return r; 6588 } 6589 } 6590 6591 mutex_lock(&kvm->lock); 6592 old_filter = rcu_replace_pointer(kvm->arch.msr_filter, new_filter, 6593 mutex_is_locked(&kvm->lock)); 6594 mutex_unlock(&kvm->lock); 6595 synchronize_srcu(&kvm->srcu); 6596 6597 kvm_free_msr_filter(old_filter); 6598 6599 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); 6600 6601 return 0; 6602 } 6603 6604 #ifdef CONFIG_KVM_COMPAT 6605 /* for KVM_X86_SET_MSR_FILTER */ 6606 struct kvm_msr_filter_range_compat { 6607 __u32 flags; 6608 __u32 nmsrs; 6609 __u32 base; 6610 __u32 bitmap; 6611 }; 6612 6613 struct kvm_msr_filter_compat { 6614 __u32 flags; 6615 struct kvm_msr_filter_range_compat ranges[KVM_MSR_FILTER_MAX_RANGES]; 6616 }; 6617 6618 #define KVM_X86_SET_MSR_FILTER_COMPAT _IOW(KVMIO, 0xc6, struct kvm_msr_filter_compat) 6619 6620 long kvm_arch_vm_compat_ioctl(struct file *filp, unsigned int ioctl, 6621 unsigned long arg) 6622 { 6623 void __user *argp = (void __user *)arg; 6624 struct kvm *kvm = filp->private_data; 6625 long r = -ENOTTY; 6626 6627 switch (ioctl) { 6628 case KVM_X86_SET_MSR_FILTER_COMPAT: { 6629 struct kvm_msr_filter __user *user_msr_filter = argp; 6630 struct kvm_msr_filter_compat filter_compat; 6631 struct kvm_msr_filter filter; 6632 int i; 6633 6634 if (copy_from_user(&filter_compat, user_msr_filter, 6635 sizeof(filter_compat))) 6636 return -EFAULT; 6637 6638 filter.flags = filter_compat.flags; 6639 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { 6640 struct kvm_msr_filter_range_compat *cr; 6641 6642 cr = &filter_compat.ranges[i]; 6643 filter.ranges[i] = (struct kvm_msr_filter_range) { 6644 .flags = cr->flags, 6645 .nmsrs = cr->nmsrs, 6646 .base = cr->base, 6647 .bitmap = (__u8 *)(ulong)cr->bitmap, 6648 }; 6649 } 6650 6651 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter); 6652 break; 6653 } 6654 } 6655 6656 return r; 6657 } 6658 #endif 6659 6660 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER 6661 static int kvm_arch_suspend_notifier(struct kvm *kvm) 6662 { 6663 struct kvm_vcpu *vcpu; 6664 unsigned long i; 6665 int ret = 0; 6666 6667 mutex_lock(&kvm->lock); 6668 kvm_for_each_vcpu(i, vcpu, kvm) { 6669 if (!vcpu->arch.pv_time.active) 6670 continue; 6671 6672 ret = kvm_set_guest_paused(vcpu); 6673 if (ret) { 6674 kvm_err("Failed to pause guest VCPU%d: %d\n", 6675 vcpu->vcpu_id, ret); 6676 break; 6677 } 6678 } 6679 mutex_unlock(&kvm->lock); 6680 6681 return ret ? NOTIFY_BAD : NOTIFY_DONE; 6682 } 6683 6684 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state) 6685 { 6686 switch (state) { 6687 case PM_HIBERNATION_PREPARE: 6688 case PM_SUSPEND_PREPARE: 6689 return kvm_arch_suspend_notifier(kvm); 6690 } 6691 6692 return NOTIFY_DONE; 6693 } 6694 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */ 6695 6696 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp) 6697 { 6698 struct kvm_clock_data data = { 0 }; 6699 6700 get_kvmclock(kvm, &data); 6701 if (copy_to_user(argp, &data, sizeof(data))) 6702 return -EFAULT; 6703 6704 return 0; 6705 } 6706 6707 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp) 6708 { 6709 struct kvm_arch *ka = &kvm->arch; 6710 struct kvm_clock_data data; 6711 u64 now_raw_ns; 6712 6713 if (copy_from_user(&data, argp, sizeof(data))) 6714 return -EFAULT; 6715 6716 /* 6717 * Only KVM_CLOCK_REALTIME is used, but allow passing the 6718 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK. 6719 */ 6720 if (data.flags & ~KVM_CLOCK_VALID_FLAGS) 6721 return -EINVAL; 6722 6723 kvm_hv_request_tsc_page_update(kvm); 6724 kvm_start_pvclock_update(kvm); 6725 pvclock_update_vm_gtod_copy(kvm); 6726 6727 /* 6728 * This pairs with kvm_guest_time_update(): when masterclock is 6729 * in use, we use master_kernel_ns + kvmclock_offset to set 6730 * unsigned 'system_time' so if we use get_kvmclock_ns() (which 6731 * is slightly ahead) here we risk going negative on unsigned 6732 * 'system_time' when 'data.clock' is very small. 6733 */ 6734 if (data.flags & KVM_CLOCK_REALTIME) { 6735 u64 now_real_ns = ktime_get_real_ns(); 6736 6737 /* 6738 * Avoid stepping the kvmclock backwards. 6739 */ 6740 if (now_real_ns > data.realtime) 6741 data.clock += now_real_ns - data.realtime; 6742 } 6743 6744 if (ka->use_master_clock) 6745 now_raw_ns = ka->master_kernel_ns; 6746 else 6747 now_raw_ns = get_kvmclock_base_ns(); 6748 ka->kvmclock_offset = data.clock - now_raw_ns; 6749 kvm_end_pvclock_update(kvm); 6750 return 0; 6751 } 6752 6753 int kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) 6754 { 6755 struct kvm *kvm = filp->private_data; 6756 void __user *argp = (void __user *)arg; 6757 int r = -ENOTTY; 6758 /* 6759 * This union makes it completely explicit to gcc-3.x 6760 * that these two variables' stack usage should be 6761 * combined, not added together. 6762 */ 6763 union { 6764 struct kvm_pit_state ps; 6765 struct kvm_pit_state2 ps2; 6766 struct kvm_pit_config pit_config; 6767 } u; 6768 6769 switch (ioctl) { 6770 case KVM_SET_TSS_ADDR: 6771 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 6772 break; 6773 case KVM_SET_IDENTITY_MAP_ADDR: { 6774 u64 ident_addr; 6775 6776 mutex_lock(&kvm->lock); 6777 r = -EINVAL; 6778 if (kvm->created_vcpus) 6779 goto set_identity_unlock; 6780 r = -EFAULT; 6781 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) 6782 goto set_identity_unlock; 6783 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 6784 set_identity_unlock: 6785 mutex_unlock(&kvm->lock); 6786 break; 6787 } 6788 case KVM_SET_NR_MMU_PAGES: 6789 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 6790 break; 6791 case KVM_CREATE_IRQCHIP: { 6792 mutex_lock(&kvm->lock); 6793 6794 r = -EEXIST; 6795 if (irqchip_in_kernel(kvm)) 6796 goto create_irqchip_unlock; 6797 6798 r = -EINVAL; 6799 if (kvm->created_vcpus) 6800 goto create_irqchip_unlock; 6801 6802 r = kvm_pic_init(kvm); 6803 if (r) 6804 goto create_irqchip_unlock; 6805 6806 r = kvm_ioapic_init(kvm); 6807 if (r) { 6808 kvm_pic_destroy(kvm); 6809 goto create_irqchip_unlock; 6810 } 6811 6812 r = kvm_setup_default_irq_routing(kvm); 6813 if (r) { 6814 kvm_ioapic_destroy(kvm); 6815 kvm_pic_destroy(kvm); 6816 goto create_irqchip_unlock; 6817 } 6818 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ 6819 smp_wmb(); 6820 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; 6821 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT); 6822 create_irqchip_unlock: 6823 mutex_unlock(&kvm->lock); 6824 break; 6825 } 6826 case KVM_CREATE_PIT: 6827 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 6828 goto create_pit; 6829 case KVM_CREATE_PIT2: 6830 r = -EFAULT; 6831 if (copy_from_user(&u.pit_config, argp, 6832 sizeof(struct kvm_pit_config))) 6833 goto out; 6834 create_pit: 6835 mutex_lock(&kvm->lock); 6836 r = -EEXIST; 6837 if (kvm->arch.vpit) 6838 goto create_pit_unlock; 6839 r = -ENOMEM; 6840 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 6841 if (kvm->arch.vpit) 6842 r = 0; 6843 create_pit_unlock: 6844 mutex_unlock(&kvm->lock); 6845 break; 6846 case KVM_GET_IRQCHIP: { 6847 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 6848 struct kvm_irqchip *chip; 6849 6850 chip = memdup_user(argp, sizeof(*chip)); 6851 if (IS_ERR(chip)) { 6852 r = PTR_ERR(chip); 6853 goto out; 6854 } 6855 6856 r = -ENXIO; 6857 if (!irqchip_kernel(kvm)) 6858 goto get_irqchip_out; 6859 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 6860 if (r) 6861 goto get_irqchip_out; 6862 r = -EFAULT; 6863 if (copy_to_user(argp, chip, sizeof(*chip))) 6864 goto get_irqchip_out; 6865 r = 0; 6866 get_irqchip_out: 6867 kfree(chip); 6868 break; 6869 } 6870 case KVM_SET_IRQCHIP: { 6871 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 6872 struct kvm_irqchip *chip; 6873 6874 chip = memdup_user(argp, sizeof(*chip)); 6875 if (IS_ERR(chip)) { 6876 r = PTR_ERR(chip); 6877 goto out; 6878 } 6879 6880 r = -ENXIO; 6881 if (!irqchip_kernel(kvm)) 6882 goto set_irqchip_out; 6883 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 6884 set_irqchip_out: 6885 kfree(chip); 6886 break; 6887 } 6888 case KVM_GET_PIT: { 6889 r = -EFAULT; 6890 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 6891 goto out; 6892 r = -ENXIO; 6893 if (!kvm->arch.vpit) 6894 goto out; 6895 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 6896 if (r) 6897 goto out; 6898 r = -EFAULT; 6899 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 6900 goto out; 6901 r = 0; 6902 break; 6903 } 6904 case KVM_SET_PIT: { 6905 r = -EFAULT; 6906 if (copy_from_user(&u.ps, argp, sizeof(u.ps))) 6907 goto out; 6908 mutex_lock(&kvm->lock); 6909 r = -ENXIO; 6910 if (!kvm->arch.vpit) 6911 goto set_pit_out; 6912 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 6913 set_pit_out: 6914 mutex_unlock(&kvm->lock); 6915 break; 6916 } 6917 case KVM_GET_PIT2: { 6918 r = -ENXIO; 6919 if (!kvm->arch.vpit) 6920 goto out; 6921 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 6922 if (r) 6923 goto out; 6924 r = -EFAULT; 6925 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 6926 goto out; 6927 r = 0; 6928 break; 6929 } 6930 case KVM_SET_PIT2: { 6931 r = -EFAULT; 6932 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 6933 goto out; 6934 mutex_lock(&kvm->lock); 6935 r = -ENXIO; 6936 if (!kvm->arch.vpit) 6937 goto set_pit2_out; 6938 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 6939 set_pit2_out: 6940 mutex_unlock(&kvm->lock); 6941 break; 6942 } 6943 case KVM_REINJECT_CONTROL: { 6944 struct kvm_reinject_control control; 6945 r = -EFAULT; 6946 if (copy_from_user(&control, argp, sizeof(control))) 6947 goto out; 6948 r = -ENXIO; 6949 if (!kvm->arch.vpit) 6950 goto out; 6951 r = kvm_vm_ioctl_reinject(kvm, &control); 6952 break; 6953 } 6954 case KVM_SET_BOOT_CPU_ID: 6955 r = 0; 6956 mutex_lock(&kvm->lock); 6957 if (kvm->created_vcpus) 6958 r = -EBUSY; 6959 else 6960 kvm->arch.bsp_vcpu_id = arg; 6961 mutex_unlock(&kvm->lock); 6962 break; 6963 #ifdef CONFIG_KVM_XEN 6964 case KVM_XEN_HVM_CONFIG: { 6965 struct kvm_xen_hvm_config xhc; 6966 r = -EFAULT; 6967 if (copy_from_user(&xhc, argp, sizeof(xhc))) 6968 goto out; 6969 r = kvm_xen_hvm_config(kvm, &xhc); 6970 break; 6971 } 6972 case KVM_XEN_HVM_GET_ATTR: { 6973 struct kvm_xen_hvm_attr xha; 6974 6975 r = -EFAULT; 6976 if (copy_from_user(&xha, argp, sizeof(xha))) 6977 goto out; 6978 r = kvm_xen_hvm_get_attr(kvm, &xha); 6979 if (!r && copy_to_user(argp, &xha, sizeof(xha))) 6980 r = -EFAULT; 6981 break; 6982 } 6983 case KVM_XEN_HVM_SET_ATTR: { 6984 struct kvm_xen_hvm_attr xha; 6985 6986 r = -EFAULT; 6987 if (copy_from_user(&xha, argp, sizeof(xha))) 6988 goto out; 6989 r = kvm_xen_hvm_set_attr(kvm, &xha); 6990 break; 6991 } 6992 case KVM_XEN_HVM_EVTCHN_SEND: { 6993 struct kvm_irq_routing_xen_evtchn uxe; 6994 6995 r = -EFAULT; 6996 if (copy_from_user(&uxe, argp, sizeof(uxe))) 6997 goto out; 6998 r = kvm_xen_hvm_evtchn_send(kvm, &uxe); 6999 break; 7000 } 7001 #endif 7002 case KVM_SET_CLOCK: 7003 r = kvm_vm_ioctl_set_clock(kvm, argp); 7004 break; 7005 case KVM_GET_CLOCK: 7006 r = kvm_vm_ioctl_get_clock(kvm, argp); 7007 break; 7008 case KVM_SET_TSC_KHZ: { 7009 u32 user_tsc_khz; 7010 7011 r = -EINVAL; 7012 user_tsc_khz = (u32)arg; 7013 7014 if (kvm_caps.has_tsc_control && 7015 user_tsc_khz >= kvm_caps.max_guest_tsc_khz) 7016 goto out; 7017 7018 if (user_tsc_khz == 0) 7019 user_tsc_khz = tsc_khz; 7020 7021 WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz); 7022 r = 0; 7023 7024 goto out; 7025 } 7026 case KVM_GET_TSC_KHZ: { 7027 r = READ_ONCE(kvm->arch.default_tsc_khz); 7028 goto out; 7029 } 7030 case KVM_MEMORY_ENCRYPT_OP: { 7031 r = -ENOTTY; 7032 if (!kvm_x86_ops.mem_enc_ioctl) 7033 goto out; 7034 7035 r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp); 7036 break; 7037 } 7038 case KVM_MEMORY_ENCRYPT_REG_REGION: { 7039 struct kvm_enc_region region; 7040 7041 r = -EFAULT; 7042 if (copy_from_user(®ion, argp, sizeof(region))) 7043 goto out; 7044 7045 r = -ENOTTY; 7046 if (!kvm_x86_ops.mem_enc_register_region) 7047 goto out; 7048 7049 r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion); 7050 break; 7051 } 7052 case KVM_MEMORY_ENCRYPT_UNREG_REGION: { 7053 struct kvm_enc_region region; 7054 7055 r = -EFAULT; 7056 if (copy_from_user(®ion, argp, sizeof(region))) 7057 goto out; 7058 7059 r = -ENOTTY; 7060 if (!kvm_x86_ops.mem_enc_unregister_region) 7061 goto out; 7062 7063 r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion); 7064 break; 7065 } 7066 case KVM_HYPERV_EVENTFD: { 7067 struct kvm_hyperv_eventfd hvevfd; 7068 7069 r = -EFAULT; 7070 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) 7071 goto out; 7072 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); 7073 break; 7074 } 7075 case KVM_SET_PMU_EVENT_FILTER: 7076 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); 7077 break; 7078 case KVM_X86_SET_MSR_FILTER: { 7079 struct kvm_msr_filter __user *user_msr_filter = argp; 7080 struct kvm_msr_filter filter; 7081 7082 if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) 7083 return -EFAULT; 7084 7085 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter); 7086 break; 7087 } 7088 default: 7089 r = -ENOTTY; 7090 } 7091 out: 7092 return r; 7093 } 7094 7095 static void kvm_probe_feature_msr(u32 msr_index) 7096 { 7097 struct kvm_msr_entry msr = { 7098 .index = msr_index, 7099 }; 7100 7101 if (kvm_get_msr_feature(&msr)) 7102 return; 7103 7104 msr_based_features[num_msr_based_features++] = msr_index; 7105 } 7106 7107 static void kvm_probe_msr_to_save(u32 msr_index) 7108 { 7109 u32 dummy[2]; 7110 7111 if (rdmsr_safe(msr_index, &dummy[0], &dummy[1])) 7112 return; 7113 7114 /* 7115 * Even MSRs that are valid in the host may not be exposed to guests in 7116 * some cases. 7117 */ 7118 switch (msr_index) { 7119 case MSR_IA32_BNDCFGS: 7120 if (!kvm_mpx_supported()) 7121 return; 7122 break; 7123 case MSR_TSC_AUX: 7124 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && 7125 !kvm_cpu_cap_has(X86_FEATURE_RDPID)) 7126 return; 7127 break; 7128 case MSR_IA32_UMWAIT_CONTROL: 7129 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) 7130 return; 7131 break; 7132 case MSR_IA32_RTIT_CTL: 7133 case MSR_IA32_RTIT_STATUS: 7134 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) 7135 return; 7136 break; 7137 case MSR_IA32_RTIT_CR3_MATCH: 7138 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 7139 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) 7140 return; 7141 break; 7142 case MSR_IA32_RTIT_OUTPUT_BASE: 7143 case MSR_IA32_RTIT_OUTPUT_MASK: 7144 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 7145 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && 7146 !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) 7147 return; 7148 break; 7149 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 7150 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || 7151 (msr_index - MSR_IA32_RTIT_ADDR0_A >= 7152 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)) 7153 return; 7154 break; 7155 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR_MAX: 7156 if (msr_index - MSR_ARCH_PERFMON_PERFCTR0 >= 7157 kvm_pmu_cap.num_counters_gp) 7158 return; 7159 break; 7160 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL_MAX: 7161 if (msr_index - MSR_ARCH_PERFMON_EVENTSEL0 >= 7162 kvm_pmu_cap.num_counters_gp) 7163 return; 7164 break; 7165 case MSR_ARCH_PERFMON_FIXED_CTR0 ... MSR_ARCH_PERFMON_FIXED_CTR_MAX: 7166 if (msr_index - MSR_ARCH_PERFMON_FIXED_CTR0 >= 7167 kvm_pmu_cap.num_counters_fixed) 7168 return; 7169 break; 7170 case MSR_AMD64_PERF_CNTR_GLOBAL_CTL: 7171 case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: 7172 case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: 7173 if (!kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) 7174 return; 7175 break; 7176 case MSR_IA32_XFD: 7177 case MSR_IA32_XFD_ERR: 7178 if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) 7179 return; 7180 break; 7181 case MSR_IA32_TSX_CTRL: 7182 if (!(kvm_get_arch_capabilities() & ARCH_CAP_TSX_CTRL_MSR)) 7183 return; 7184 break; 7185 default: 7186 break; 7187 } 7188 7189 msrs_to_save[num_msrs_to_save++] = msr_index; 7190 } 7191 7192 static void kvm_init_msr_lists(void) 7193 { 7194 unsigned i; 7195 7196 BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3, 7197 "Please update the fixed PMCs in msrs_to_save_pmu[]"); 7198 7199 num_msrs_to_save = 0; 7200 num_emulated_msrs = 0; 7201 num_msr_based_features = 0; 7202 7203 for (i = 0; i < ARRAY_SIZE(msrs_to_save_base); i++) 7204 kvm_probe_msr_to_save(msrs_to_save_base[i]); 7205 7206 if (enable_pmu) { 7207 for (i = 0; i < ARRAY_SIZE(msrs_to_save_pmu); i++) 7208 kvm_probe_msr_to_save(msrs_to_save_pmu[i]); 7209 } 7210 7211 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { 7212 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) 7213 continue; 7214 7215 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; 7216 } 7217 7218 for (i = KVM_FIRST_EMULATED_VMX_MSR; i <= KVM_LAST_EMULATED_VMX_MSR; i++) 7219 kvm_probe_feature_msr(i); 7220 7221 for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++) 7222 kvm_probe_feature_msr(msr_based_features_all_except_vmx[i]); 7223 } 7224 7225 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 7226 const void *v) 7227 { 7228 int handled = 0; 7229 int n; 7230 7231 do { 7232 n = min(len, 8); 7233 if (!(lapic_in_kernel(vcpu) && 7234 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) 7235 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) 7236 break; 7237 handled += n; 7238 addr += n; 7239 len -= n; 7240 v += n; 7241 } while (len); 7242 7243 return handled; 7244 } 7245 7246 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 7247 { 7248 int handled = 0; 7249 int n; 7250 7251 do { 7252 n = min(len, 8); 7253 if (!(lapic_in_kernel(vcpu) && 7254 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, 7255 addr, n, v)) 7256 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) 7257 break; 7258 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); 7259 handled += n; 7260 addr += n; 7261 len -= n; 7262 v += n; 7263 } while (len); 7264 7265 return handled; 7266 } 7267 7268 void kvm_set_segment(struct kvm_vcpu *vcpu, 7269 struct kvm_segment *var, int seg) 7270 { 7271 static_call(kvm_x86_set_segment)(vcpu, var, seg); 7272 } 7273 7274 void kvm_get_segment(struct kvm_vcpu *vcpu, 7275 struct kvm_segment *var, int seg) 7276 { 7277 static_call(kvm_x86_get_segment)(vcpu, var, seg); 7278 } 7279 7280 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access, 7281 struct x86_exception *exception) 7282 { 7283 struct kvm_mmu *mmu = vcpu->arch.mmu; 7284 gpa_t t_gpa; 7285 7286 BUG_ON(!mmu_is_nested(vcpu)); 7287 7288 /* NPT walks are always user-walks */ 7289 access |= PFERR_USER_MASK; 7290 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception); 7291 7292 return t_gpa; 7293 } 7294 7295 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 7296 struct x86_exception *exception) 7297 { 7298 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7299 7300 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 7301 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 7302 } 7303 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); 7304 7305 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 7306 struct x86_exception *exception) 7307 { 7308 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7309 7310 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 7311 access |= PFERR_WRITE_MASK; 7312 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 7313 } 7314 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); 7315 7316 /* uses this to access any guest's mapped memory without checking CPL */ 7317 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 7318 struct x86_exception *exception) 7319 { 7320 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7321 7322 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception); 7323 } 7324 7325 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 7326 struct kvm_vcpu *vcpu, u64 access, 7327 struct x86_exception *exception) 7328 { 7329 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7330 void *data = val; 7331 int r = X86EMUL_CONTINUE; 7332 7333 while (bytes) { 7334 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); 7335 unsigned offset = addr & (PAGE_SIZE-1); 7336 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 7337 int ret; 7338 7339 if (gpa == INVALID_GPA) 7340 return X86EMUL_PROPAGATE_FAULT; 7341 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, 7342 offset, toread); 7343 if (ret < 0) { 7344 r = X86EMUL_IO_NEEDED; 7345 goto out; 7346 } 7347 7348 bytes -= toread; 7349 data += toread; 7350 addr += toread; 7351 } 7352 out: 7353 return r; 7354 } 7355 7356 /* used for instruction fetching */ 7357 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 7358 gva_t addr, void *val, unsigned int bytes, 7359 struct x86_exception *exception) 7360 { 7361 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7362 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7363 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 7364 unsigned offset; 7365 int ret; 7366 7367 /* Inline kvm_read_guest_virt_helper for speed. */ 7368 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK, 7369 exception); 7370 if (unlikely(gpa == INVALID_GPA)) 7371 return X86EMUL_PROPAGATE_FAULT; 7372 7373 offset = addr & (PAGE_SIZE-1); 7374 if (WARN_ON(offset + bytes > PAGE_SIZE)) 7375 bytes = (unsigned)PAGE_SIZE - offset; 7376 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, 7377 offset, bytes); 7378 if (unlikely(ret < 0)) 7379 return X86EMUL_IO_NEEDED; 7380 7381 return X86EMUL_CONTINUE; 7382 } 7383 7384 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 7385 gva_t addr, void *val, unsigned int bytes, 7386 struct x86_exception *exception) 7387 { 7388 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; 7389 7390 /* 7391 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED 7392 * is returned, but our callers are not ready for that and they blindly 7393 * call kvm_inject_page_fault. Ensure that they at least do not leak 7394 * uninitialized kernel stack memory into cr2 and error code. 7395 */ 7396 memset(exception, 0, sizeof(*exception)); 7397 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 7398 exception); 7399 } 7400 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 7401 7402 static int emulator_read_std(struct x86_emulate_ctxt *ctxt, 7403 gva_t addr, void *val, unsigned int bytes, 7404 struct x86_exception *exception, bool system) 7405 { 7406 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7407 u64 access = 0; 7408 7409 if (system) 7410 access |= PFERR_IMPLICIT_ACCESS; 7411 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3) 7412 access |= PFERR_USER_MASK; 7413 7414 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); 7415 } 7416 7417 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 7418 struct kvm_vcpu *vcpu, u64 access, 7419 struct x86_exception *exception) 7420 { 7421 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7422 void *data = val; 7423 int r = X86EMUL_CONTINUE; 7424 7425 while (bytes) { 7426 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); 7427 unsigned offset = addr & (PAGE_SIZE-1); 7428 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 7429 int ret; 7430 7431 if (gpa == INVALID_GPA) 7432 return X86EMUL_PROPAGATE_FAULT; 7433 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); 7434 if (ret < 0) { 7435 r = X86EMUL_IO_NEEDED; 7436 goto out; 7437 } 7438 7439 bytes -= towrite; 7440 data += towrite; 7441 addr += towrite; 7442 } 7443 out: 7444 return r; 7445 } 7446 7447 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, 7448 unsigned int bytes, struct x86_exception *exception, 7449 bool system) 7450 { 7451 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7452 u64 access = PFERR_WRITE_MASK; 7453 7454 if (system) 7455 access |= PFERR_IMPLICIT_ACCESS; 7456 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3) 7457 access |= PFERR_USER_MASK; 7458 7459 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 7460 access, exception); 7461 } 7462 7463 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, 7464 unsigned int bytes, struct x86_exception *exception) 7465 { 7466 /* kvm_write_guest_virt_system can pull in tons of pages. */ 7467 vcpu->arch.l1tf_flush_l1d = true; 7468 7469 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, 7470 PFERR_WRITE_MASK, exception); 7471 } 7472 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 7473 7474 static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type, 7475 void *insn, int insn_len) 7476 { 7477 return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type, 7478 insn, insn_len); 7479 } 7480 7481 int handle_ud(struct kvm_vcpu *vcpu) 7482 { 7483 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; 7484 int fep_flags = READ_ONCE(force_emulation_prefix); 7485 int emul_type = EMULTYPE_TRAP_UD; 7486 char sig[5]; /* ud2; .ascii "kvm" */ 7487 struct x86_exception e; 7488 7489 if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0))) 7490 return 1; 7491 7492 if (fep_flags && 7493 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), 7494 sig, sizeof(sig), &e) == 0 && 7495 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { 7496 if (fep_flags & KVM_FEP_CLEAR_RFLAGS_RF) 7497 kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) & ~X86_EFLAGS_RF); 7498 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); 7499 emul_type = EMULTYPE_TRAP_UD_FORCED; 7500 } 7501 7502 return kvm_emulate_instruction(vcpu, emul_type); 7503 } 7504 EXPORT_SYMBOL_GPL(handle_ud); 7505 7506 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 7507 gpa_t gpa, bool write) 7508 { 7509 /* For APIC access vmexit */ 7510 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 7511 return 1; 7512 7513 if (vcpu_match_mmio_gpa(vcpu, gpa)) { 7514 trace_vcpu_match_mmio(gva, gpa, write, true); 7515 return 1; 7516 } 7517 7518 return 0; 7519 } 7520 7521 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 7522 gpa_t *gpa, struct x86_exception *exception, 7523 bool write) 7524 { 7525 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 7526 u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) 7527 | (write ? PFERR_WRITE_MASK : 0); 7528 7529 /* 7530 * currently PKRU is only applied to ept enabled guest so 7531 * there is no pkey in EPT page table for L1 guest or EPT 7532 * shadow page table for L2 guest. 7533 */ 7534 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) || 7535 !permission_fault(vcpu, vcpu->arch.walk_mmu, 7536 vcpu->arch.mmio_access, 0, access))) { 7537 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 7538 (gva & (PAGE_SIZE - 1)); 7539 trace_vcpu_match_mmio(gva, *gpa, write, false); 7540 return 1; 7541 } 7542 7543 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); 7544 7545 if (*gpa == INVALID_GPA) 7546 return -1; 7547 7548 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); 7549 } 7550 7551 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 7552 const void *val, int bytes) 7553 { 7554 int ret; 7555 7556 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); 7557 if (ret < 0) 7558 return 0; 7559 kvm_page_track_write(vcpu, gpa, val, bytes); 7560 return 1; 7561 } 7562 7563 struct read_write_emulator_ops { 7564 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 7565 int bytes); 7566 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 7567 void *val, int bytes); 7568 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 7569 int bytes, void *val); 7570 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 7571 void *val, int bytes); 7572 bool write; 7573 }; 7574 7575 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 7576 { 7577 if (vcpu->mmio_read_completed) { 7578 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 7579 vcpu->mmio_fragments[0].gpa, val); 7580 vcpu->mmio_read_completed = 0; 7581 return 1; 7582 } 7583 7584 return 0; 7585 } 7586 7587 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 7588 void *val, int bytes) 7589 { 7590 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); 7591 } 7592 7593 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 7594 void *val, int bytes) 7595 { 7596 return emulator_write_phys(vcpu, gpa, val, bytes); 7597 } 7598 7599 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 7600 { 7601 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); 7602 return vcpu_mmio_write(vcpu, gpa, bytes, val); 7603 } 7604 7605 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 7606 void *val, int bytes) 7607 { 7608 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); 7609 return X86EMUL_IO_NEEDED; 7610 } 7611 7612 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 7613 void *val, int bytes) 7614 { 7615 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 7616 7617 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 7618 return X86EMUL_CONTINUE; 7619 } 7620 7621 static const struct read_write_emulator_ops read_emultor = { 7622 .read_write_prepare = read_prepare, 7623 .read_write_emulate = read_emulate, 7624 .read_write_mmio = vcpu_mmio_read, 7625 .read_write_exit_mmio = read_exit_mmio, 7626 }; 7627 7628 static const struct read_write_emulator_ops write_emultor = { 7629 .read_write_emulate = write_emulate, 7630 .read_write_mmio = write_mmio, 7631 .read_write_exit_mmio = write_exit_mmio, 7632 .write = true, 7633 }; 7634 7635 static int emulator_read_write_onepage(unsigned long addr, void *val, 7636 unsigned int bytes, 7637 struct x86_exception *exception, 7638 struct kvm_vcpu *vcpu, 7639 const struct read_write_emulator_ops *ops) 7640 { 7641 gpa_t gpa; 7642 int handled, ret; 7643 bool write = ops->write; 7644 struct kvm_mmio_fragment *frag; 7645 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 7646 7647 /* 7648 * If the exit was due to a NPF we may already have a GPA. 7649 * If the GPA is present, use it to avoid the GVA to GPA table walk. 7650 * Note, this cannot be used on string operations since string 7651 * operation using rep will only have the initial GPA from the NPF 7652 * occurred. 7653 */ 7654 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && 7655 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { 7656 gpa = ctxt->gpa_val; 7657 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); 7658 } else { 7659 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 7660 if (ret < 0) 7661 return X86EMUL_PROPAGATE_FAULT; 7662 } 7663 7664 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) 7665 return X86EMUL_CONTINUE; 7666 7667 /* 7668 * Is this MMIO handled locally? 7669 */ 7670 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 7671 if (handled == bytes) 7672 return X86EMUL_CONTINUE; 7673 7674 gpa += handled; 7675 bytes -= handled; 7676 val += handled; 7677 7678 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 7679 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 7680 frag->gpa = gpa; 7681 frag->data = val; 7682 frag->len = bytes; 7683 return X86EMUL_CONTINUE; 7684 } 7685 7686 static int emulator_read_write(struct x86_emulate_ctxt *ctxt, 7687 unsigned long addr, 7688 void *val, unsigned int bytes, 7689 struct x86_exception *exception, 7690 const struct read_write_emulator_ops *ops) 7691 { 7692 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7693 gpa_t gpa; 7694 int rc; 7695 7696 if (ops->read_write_prepare && 7697 ops->read_write_prepare(vcpu, val, bytes)) 7698 return X86EMUL_CONTINUE; 7699 7700 vcpu->mmio_nr_fragments = 0; 7701 7702 /* Crossing a page boundary? */ 7703 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 7704 int now; 7705 7706 now = -addr & ~PAGE_MASK; 7707 rc = emulator_read_write_onepage(addr, val, now, exception, 7708 vcpu, ops); 7709 7710 if (rc != X86EMUL_CONTINUE) 7711 return rc; 7712 addr += now; 7713 if (ctxt->mode != X86EMUL_MODE_PROT64) 7714 addr = (u32)addr; 7715 val += now; 7716 bytes -= now; 7717 } 7718 7719 rc = emulator_read_write_onepage(addr, val, bytes, exception, 7720 vcpu, ops); 7721 if (rc != X86EMUL_CONTINUE) 7722 return rc; 7723 7724 if (!vcpu->mmio_nr_fragments) 7725 return rc; 7726 7727 gpa = vcpu->mmio_fragments[0].gpa; 7728 7729 vcpu->mmio_needed = 1; 7730 vcpu->mmio_cur_fragment = 0; 7731 7732 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 7733 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 7734 vcpu->run->exit_reason = KVM_EXIT_MMIO; 7735 vcpu->run->mmio.phys_addr = gpa; 7736 7737 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 7738 } 7739 7740 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 7741 unsigned long addr, 7742 void *val, 7743 unsigned int bytes, 7744 struct x86_exception *exception) 7745 { 7746 return emulator_read_write(ctxt, addr, val, bytes, 7747 exception, &read_emultor); 7748 } 7749 7750 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 7751 unsigned long addr, 7752 const void *val, 7753 unsigned int bytes, 7754 struct x86_exception *exception) 7755 { 7756 return emulator_read_write(ctxt, addr, (void *)val, bytes, 7757 exception, &write_emultor); 7758 } 7759 7760 #define emulator_try_cmpxchg_user(t, ptr, old, new) \ 7761 (__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t)) 7762 7763 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 7764 unsigned long addr, 7765 const void *old, 7766 const void *new, 7767 unsigned int bytes, 7768 struct x86_exception *exception) 7769 { 7770 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7771 u64 page_line_mask; 7772 unsigned long hva; 7773 gpa_t gpa; 7774 int r; 7775 7776 /* guests cmpxchg8b have to be emulated atomically */ 7777 if (bytes > 8 || (bytes & (bytes - 1))) 7778 goto emul_write; 7779 7780 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 7781 7782 if (gpa == INVALID_GPA || 7783 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 7784 goto emul_write; 7785 7786 /* 7787 * Emulate the atomic as a straight write to avoid #AC if SLD is 7788 * enabled in the host and the access splits a cache line. 7789 */ 7790 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 7791 page_line_mask = ~(cache_line_size() - 1); 7792 else 7793 page_line_mask = PAGE_MASK; 7794 7795 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) 7796 goto emul_write; 7797 7798 hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa)); 7799 if (kvm_is_error_hva(hva)) 7800 goto emul_write; 7801 7802 hva += offset_in_page(gpa); 7803 7804 switch (bytes) { 7805 case 1: 7806 r = emulator_try_cmpxchg_user(u8, hva, old, new); 7807 break; 7808 case 2: 7809 r = emulator_try_cmpxchg_user(u16, hva, old, new); 7810 break; 7811 case 4: 7812 r = emulator_try_cmpxchg_user(u32, hva, old, new); 7813 break; 7814 case 8: 7815 r = emulator_try_cmpxchg_user(u64, hva, old, new); 7816 break; 7817 default: 7818 BUG(); 7819 } 7820 7821 if (r < 0) 7822 return X86EMUL_UNHANDLEABLE; 7823 if (r) 7824 return X86EMUL_CMPXCHG_FAILED; 7825 7826 kvm_page_track_write(vcpu, gpa, new, bytes); 7827 7828 return X86EMUL_CONTINUE; 7829 7830 emul_write: 7831 pr_warn_once("emulating exchange as write\n"); 7832 7833 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 7834 } 7835 7836 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 7837 unsigned short port, void *data, 7838 unsigned int count, bool in) 7839 { 7840 unsigned i; 7841 int r; 7842 7843 WARN_ON_ONCE(vcpu->arch.pio.count); 7844 for (i = 0; i < count; i++) { 7845 if (in) 7846 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, port, size, data); 7847 else 7848 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, port, size, data); 7849 7850 if (r) { 7851 if (i == 0) 7852 goto userspace_io; 7853 7854 /* 7855 * Userspace must have unregistered the device while PIO 7856 * was running. Drop writes / read as 0. 7857 */ 7858 if (in) 7859 memset(data, 0, size * (count - i)); 7860 break; 7861 } 7862 7863 data += size; 7864 } 7865 return 1; 7866 7867 userspace_io: 7868 vcpu->arch.pio.port = port; 7869 vcpu->arch.pio.in = in; 7870 vcpu->arch.pio.count = count; 7871 vcpu->arch.pio.size = size; 7872 7873 if (in) 7874 memset(vcpu->arch.pio_data, 0, size * count); 7875 else 7876 memcpy(vcpu->arch.pio_data, data, size * count); 7877 7878 vcpu->run->exit_reason = KVM_EXIT_IO; 7879 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 7880 vcpu->run->io.size = size; 7881 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 7882 vcpu->run->io.count = count; 7883 vcpu->run->io.port = port; 7884 return 0; 7885 } 7886 7887 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, 7888 unsigned short port, void *val, unsigned int count) 7889 { 7890 int r = emulator_pio_in_out(vcpu, size, port, val, count, true); 7891 if (r) 7892 trace_kvm_pio(KVM_PIO_IN, port, size, count, val); 7893 7894 return r; 7895 } 7896 7897 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val) 7898 { 7899 int size = vcpu->arch.pio.size; 7900 unsigned int count = vcpu->arch.pio.count; 7901 memcpy(val, vcpu->arch.pio_data, size * count); 7902 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data); 7903 vcpu->arch.pio.count = 0; 7904 } 7905 7906 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 7907 int size, unsigned short port, void *val, 7908 unsigned int count) 7909 { 7910 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 7911 if (vcpu->arch.pio.count) { 7912 /* 7913 * Complete a previous iteration that required userspace I/O. 7914 * Note, @count isn't guaranteed to match pio.count as userspace 7915 * can modify ECX before rerunning the vCPU. Ignore any such 7916 * shenanigans as KVM doesn't support modifying the rep count, 7917 * and the emulator ensures @count doesn't overflow the buffer. 7918 */ 7919 complete_emulator_pio_in(vcpu, val); 7920 return 1; 7921 } 7922 7923 return emulator_pio_in(vcpu, size, port, val, count); 7924 } 7925 7926 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, 7927 unsigned short port, const void *val, 7928 unsigned int count) 7929 { 7930 trace_kvm_pio(KVM_PIO_OUT, port, size, count, val); 7931 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 7932 } 7933 7934 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 7935 int size, unsigned short port, 7936 const void *val, unsigned int count) 7937 { 7938 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); 7939 } 7940 7941 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 7942 { 7943 return static_call(kvm_x86_get_segment_base)(vcpu, seg); 7944 } 7945 7946 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 7947 { 7948 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 7949 } 7950 7951 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) 7952 { 7953 if (!need_emulate_wbinvd(vcpu)) 7954 return X86EMUL_CONTINUE; 7955 7956 if (static_call(kvm_x86_has_wbinvd_exit)()) { 7957 int cpu = get_cpu(); 7958 7959 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 7960 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, 7961 wbinvd_ipi, NULL, 1); 7962 put_cpu(); 7963 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 7964 } else 7965 wbinvd(); 7966 return X86EMUL_CONTINUE; 7967 } 7968 7969 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 7970 { 7971 kvm_emulate_wbinvd_noskip(vcpu); 7972 return kvm_skip_emulated_instruction(vcpu); 7973 } 7974 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 7975 7976 7977 7978 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 7979 { 7980 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); 7981 } 7982 7983 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, 7984 unsigned long *dest) 7985 { 7986 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 7987 } 7988 7989 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, 7990 unsigned long value) 7991 { 7992 7993 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 7994 } 7995 7996 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 7997 { 7998 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 7999 } 8000 8001 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 8002 { 8003 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8004 unsigned long value; 8005 8006 switch (cr) { 8007 case 0: 8008 value = kvm_read_cr0(vcpu); 8009 break; 8010 case 2: 8011 value = vcpu->arch.cr2; 8012 break; 8013 case 3: 8014 value = kvm_read_cr3(vcpu); 8015 break; 8016 case 4: 8017 value = kvm_read_cr4(vcpu); 8018 break; 8019 case 8: 8020 value = kvm_get_cr8(vcpu); 8021 break; 8022 default: 8023 kvm_err("%s: unexpected cr %u\n", __func__, cr); 8024 return 0; 8025 } 8026 8027 return value; 8028 } 8029 8030 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 8031 { 8032 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8033 int res = 0; 8034 8035 switch (cr) { 8036 case 0: 8037 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 8038 break; 8039 case 2: 8040 vcpu->arch.cr2 = val; 8041 break; 8042 case 3: 8043 res = kvm_set_cr3(vcpu, val); 8044 break; 8045 case 4: 8046 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 8047 break; 8048 case 8: 8049 res = kvm_set_cr8(vcpu, val); 8050 break; 8051 default: 8052 kvm_err("%s: unexpected cr %u\n", __func__, cr); 8053 res = -1; 8054 } 8055 8056 return res; 8057 } 8058 8059 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 8060 { 8061 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); 8062 } 8063 8064 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 8065 { 8066 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); 8067 } 8068 8069 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 8070 { 8071 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); 8072 } 8073 8074 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 8075 { 8076 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); 8077 } 8078 8079 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 8080 { 8081 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); 8082 } 8083 8084 static unsigned long emulator_get_cached_segment_base( 8085 struct x86_emulate_ctxt *ctxt, int seg) 8086 { 8087 return get_segment_base(emul_to_vcpu(ctxt), seg); 8088 } 8089 8090 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 8091 struct desc_struct *desc, u32 *base3, 8092 int seg) 8093 { 8094 struct kvm_segment var; 8095 8096 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 8097 *selector = var.selector; 8098 8099 if (var.unusable) { 8100 memset(desc, 0, sizeof(*desc)); 8101 if (base3) 8102 *base3 = 0; 8103 return false; 8104 } 8105 8106 if (var.g) 8107 var.limit >>= 12; 8108 set_desc_limit(desc, var.limit); 8109 set_desc_base(desc, (unsigned long)var.base); 8110 #ifdef CONFIG_X86_64 8111 if (base3) 8112 *base3 = var.base >> 32; 8113 #endif 8114 desc->type = var.type; 8115 desc->s = var.s; 8116 desc->dpl = var.dpl; 8117 desc->p = var.present; 8118 desc->avl = var.avl; 8119 desc->l = var.l; 8120 desc->d = var.db; 8121 desc->g = var.g; 8122 8123 return true; 8124 } 8125 8126 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 8127 struct desc_struct *desc, u32 base3, 8128 int seg) 8129 { 8130 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8131 struct kvm_segment var; 8132 8133 var.selector = selector; 8134 var.base = get_desc_base(desc); 8135 #ifdef CONFIG_X86_64 8136 var.base |= ((u64)base3) << 32; 8137 #endif 8138 var.limit = get_desc_limit(desc); 8139 if (desc->g) 8140 var.limit = (var.limit << 12) | 0xfff; 8141 var.type = desc->type; 8142 var.dpl = desc->dpl; 8143 var.db = desc->d; 8144 var.s = desc->s; 8145 var.l = desc->l; 8146 var.g = desc->g; 8147 var.avl = desc->avl; 8148 var.present = desc->p; 8149 var.unusable = !var.present; 8150 var.padding = 0; 8151 8152 kvm_set_segment(vcpu, &var, seg); 8153 return; 8154 } 8155 8156 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt, 8157 u32 msr_index, u64 *pdata) 8158 { 8159 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8160 int r; 8161 8162 r = kvm_get_msr_with_filter(vcpu, msr_index, pdata); 8163 if (r < 0) 8164 return X86EMUL_UNHANDLEABLE; 8165 8166 if (r) { 8167 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0, 8168 complete_emulated_rdmsr, r)) 8169 return X86EMUL_IO_NEEDED; 8170 8171 trace_kvm_msr_read_ex(msr_index); 8172 return X86EMUL_PROPAGATE_FAULT; 8173 } 8174 8175 trace_kvm_msr_read(msr_index, *pdata); 8176 return X86EMUL_CONTINUE; 8177 } 8178 8179 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt, 8180 u32 msr_index, u64 data) 8181 { 8182 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8183 int r; 8184 8185 r = kvm_set_msr_with_filter(vcpu, msr_index, data); 8186 if (r < 0) 8187 return X86EMUL_UNHANDLEABLE; 8188 8189 if (r) { 8190 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data, 8191 complete_emulated_msr_access, r)) 8192 return X86EMUL_IO_NEEDED; 8193 8194 trace_kvm_msr_write_ex(msr_index, data); 8195 return X86EMUL_PROPAGATE_FAULT; 8196 } 8197 8198 trace_kvm_msr_write(msr_index, data); 8199 return X86EMUL_CONTINUE; 8200 } 8201 8202 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 8203 u32 msr_index, u64 *pdata) 8204 { 8205 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); 8206 } 8207 8208 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, 8209 u32 pmc) 8210 { 8211 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc)) 8212 return 0; 8213 return -EINVAL; 8214 } 8215 8216 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 8217 u32 pmc, u64 *pdata) 8218 { 8219 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); 8220 } 8221 8222 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 8223 { 8224 emul_to_vcpu(ctxt)->arch.halt_request = 1; 8225 } 8226 8227 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 8228 struct x86_instruction_info *info, 8229 enum x86_intercept_stage stage) 8230 { 8231 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, 8232 &ctxt->exception); 8233 } 8234 8235 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 8236 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, 8237 bool exact_only) 8238 { 8239 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); 8240 } 8241 8242 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) 8243 { 8244 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); 8245 } 8246 8247 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) 8248 { 8249 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); 8250 } 8251 8252 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt) 8253 { 8254 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID); 8255 } 8256 8257 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 8258 { 8259 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); 8260 } 8261 8262 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 8263 { 8264 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); 8265 } 8266 8267 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) 8268 { 8269 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); 8270 } 8271 8272 static bool emulator_is_smm(struct x86_emulate_ctxt *ctxt) 8273 { 8274 return is_smm(emul_to_vcpu(ctxt)); 8275 } 8276 8277 static bool emulator_is_guest_mode(struct x86_emulate_ctxt *ctxt) 8278 { 8279 return is_guest_mode(emul_to_vcpu(ctxt)); 8280 } 8281 8282 #ifndef CONFIG_KVM_SMM 8283 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt) 8284 { 8285 WARN_ON_ONCE(1); 8286 return X86EMUL_UNHANDLEABLE; 8287 } 8288 #endif 8289 8290 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) 8291 { 8292 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); 8293 } 8294 8295 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) 8296 { 8297 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); 8298 } 8299 8300 static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt) 8301 { 8302 struct kvm *kvm = emul_to_vcpu(ctxt)->kvm; 8303 8304 if (!kvm->vm_bugged) 8305 kvm_vm_bugged(kvm); 8306 } 8307 8308 static const struct x86_emulate_ops emulate_ops = { 8309 .vm_bugged = emulator_vm_bugged, 8310 .read_gpr = emulator_read_gpr, 8311 .write_gpr = emulator_write_gpr, 8312 .read_std = emulator_read_std, 8313 .write_std = emulator_write_std, 8314 .fetch = kvm_fetch_guest_virt, 8315 .read_emulated = emulator_read_emulated, 8316 .write_emulated = emulator_write_emulated, 8317 .cmpxchg_emulated = emulator_cmpxchg_emulated, 8318 .invlpg = emulator_invlpg, 8319 .pio_in_emulated = emulator_pio_in_emulated, 8320 .pio_out_emulated = emulator_pio_out_emulated, 8321 .get_segment = emulator_get_segment, 8322 .set_segment = emulator_set_segment, 8323 .get_cached_segment_base = emulator_get_cached_segment_base, 8324 .get_gdt = emulator_get_gdt, 8325 .get_idt = emulator_get_idt, 8326 .set_gdt = emulator_set_gdt, 8327 .set_idt = emulator_set_idt, 8328 .get_cr = emulator_get_cr, 8329 .set_cr = emulator_set_cr, 8330 .cpl = emulator_get_cpl, 8331 .get_dr = emulator_get_dr, 8332 .set_dr = emulator_set_dr, 8333 .set_msr_with_filter = emulator_set_msr_with_filter, 8334 .get_msr_with_filter = emulator_get_msr_with_filter, 8335 .get_msr = emulator_get_msr, 8336 .check_pmc = emulator_check_pmc, 8337 .read_pmc = emulator_read_pmc, 8338 .halt = emulator_halt, 8339 .wbinvd = emulator_wbinvd, 8340 .fix_hypercall = emulator_fix_hypercall, 8341 .intercept = emulator_intercept, 8342 .get_cpuid = emulator_get_cpuid, 8343 .guest_has_movbe = emulator_guest_has_movbe, 8344 .guest_has_fxsr = emulator_guest_has_fxsr, 8345 .guest_has_rdpid = emulator_guest_has_rdpid, 8346 .set_nmi_mask = emulator_set_nmi_mask, 8347 .is_smm = emulator_is_smm, 8348 .is_guest_mode = emulator_is_guest_mode, 8349 .leave_smm = emulator_leave_smm, 8350 .triple_fault = emulator_triple_fault, 8351 .set_xcr = emulator_set_xcr, 8352 }; 8353 8354 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 8355 { 8356 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 8357 /* 8358 * an sti; sti; sequence only disable interrupts for the first 8359 * instruction. So, if the last instruction, be it emulated or 8360 * not, left the system with the INT_STI flag enabled, it 8361 * means that the last instruction is an sti. We should not 8362 * leave the flag on in this case. The same goes for mov ss 8363 */ 8364 if (int_shadow & mask) 8365 mask = 0; 8366 if (unlikely(int_shadow || mask)) { 8367 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); 8368 if (!mask) 8369 kvm_make_request(KVM_REQ_EVENT, vcpu); 8370 } 8371 } 8372 8373 static void inject_emulated_exception(struct kvm_vcpu *vcpu) 8374 { 8375 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8376 8377 if (ctxt->exception.vector == PF_VECTOR) 8378 kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); 8379 else if (ctxt->exception.error_code_valid) 8380 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 8381 ctxt->exception.error_code); 8382 else 8383 kvm_queue_exception(vcpu, ctxt->exception.vector); 8384 } 8385 8386 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) 8387 { 8388 struct x86_emulate_ctxt *ctxt; 8389 8390 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); 8391 if (!ctxt) { 8392 pr_err("failed to allocate vcpu's emulator\n"); 8393 return NULL; 8394 } 8395 8396 ctxt->vcpu = vcpu; 8397 ctxt->ops = &emulate_ops; 8398 vcpu->arch.emulate_ctxt = ctxt; 8399 8400 return ctxt; 8401 } 8402 8403 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 8404 { 8405 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8406 int cs_db, cs_l; 8407 8408 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 8409 8410 ctxt->gpa_available = false; 8411 ctxt->eflags = kvm_get_rflags(vcpu); 8412 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 8413 8414 ctxt->eip = kvm_rip_read(vcpu); 8415 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 8416 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 8417 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 8418 cs_db ? X86EMUL_MODE_PROT32 : 8419 X86EMUL_MODE_PROT16; 8420 ctxt->interruptibility = 0; 8421 ctxt->have_exception = false; 8422 ctxt->exception.vector = -1; 8423 ctxt->perm_ok = false; 8424 8425 init_decode_cache(ctxt); 8426 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 8427 } 8428 8429 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 8430 { 8431 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8432 int ret; 8433 8434 init_emulate_ctxt(vcpu); 8435 8436 ctxt->op_bytes = 2; 8437 ctxt->ad_bytes = 2; 8438 ctxt->_eip = ctxt->eip + inc_eip; 8439 ret = emulate_int_real(ctxt, irq); 8440 8441 if (ret != X86EMUL_CONTINUE) { 8442 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 8443 } else { 8444 ctxt->eip = ctxt->_eip; 8445 kvm_rip_write(vcpu, ctxt->eip); 8446 kvm_set_rflags(vcpu, ctxt->eflags); 8447 } 8448 } 8449 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 8450 8451 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, 8452 u8 ndata, u8 *insn_bytes, u8 insn_size) 8453 { 8454 struct kvm_run *run = vcpu->run; 8455 u64 info[5]; 8456 u8 info_start; 8457 8458 /* 8459 * Zero the whole array used to retrieve the exit info, as casting to 8460 * u32 for select entries will leave some chunks uninitialized. 8461 */ 8462 memset(&info, 0, sizeof(info)); 8463 8464 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1], 8465 &info[2], (u32 *)&info[3], 8466 (u32 *)&info[4]); 8467 8468 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 8469 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION; 8470 8471 /* 8472 * There's currently space for 13 entries, but 5 are used for the exit 8473 * reason and info. Restrict to 4 to reduce the maintenance burden 8474 * when expanding kvm_run.emulation_failure in the future. 8475 */ 8476 if (WARN_ON_ONCE(ndata > 4)) 8477 ndata = 4; 8478 8479 /* Always include the flags as a 'data' entry. */ 8480 info_start = 1; 8481 run->emulation_failure.flags = 0; 8482 8483 if (insn_size) { 8484 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) + 8485 sizeof(run->emulation_failure.insn_bytes) != 16)); 8486 info_start += 2; 8487 run->emulation_failure.flags |= 8488 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES; 8489 run->emulation_failure.insn_size = insn_size; 8490 memset(run->emulation_failure.insn_bytes, 0x90, 8491 sizeof(run->emulation_failure.insn_bytes)); 8492 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size); 8493 } 8494 8495 memcpy(&run->internal.data[info_start], info, sizeof(info)); 8496 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data, 8497 ndata * sizeof(data[0])); 8498 8499 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata; 8500 } 8501 8502 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu) 8503 { 8504 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8505 8506 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data, 8507 ctxt->fetch.end - ctxt->fetch.data); 8508 } 8509 8510 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, 8511 u8 ndata) 8512 { 8513 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0); 8514 } 8515 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit); 8516 8517 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu) 8518 { 8519 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0); 8520 } 8521 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit); 8522 8523 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) 8524 { 8525 struct kvm *kvm = vcpu->kvm; 8526 8527 ++vcpu->stat.insn_emulation_fail; 8528 trace_kvm_emulate_insn_failed(vcpu); 8529 8530 if (emulation_type & EMULTYPE_VMWARE_GP) { 8531 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 8532 return 1; 8533 } 8534 8535 if (kvm->arch.exit_on_emulation_error || 8536 (emulation_type & EMULTYPE_SKIP)) { 8537 prepare_emulation_ctxt_failure_exit(vcpu); 8538 return 0; 8539 } 8540 8541 kvm_queue_exception(vcpu, UD_VECTOR); 8542 8543 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { 8544 prepare_emulation_ctxt_failure_exit(vcpu); 8545 return 0; 8546 } 8547 8548 return 1; 8549 } 8550 8551 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 8552 int emulation_type) 8553 { 8554 gpa_t gpa = cr2_or_gpa; 8555 kvm_pfn_t pfn; 8556 8557 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 8558 return false; 8559 8560 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 8561 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 8562 return false; 8563 8564 if (!vcpu->arch.mmu->root_role.direct) { 8565 /* 8566 * Write permission should be allowed since only 8567 * write access need to be emulated. 8568 */ 8569 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 8570 8571 /* 8572 * If the mapping is invalid in guest, let cpu retry 8573 * it to generate fault. 8574 */ 8575 if (gpa == INVALID_GPA) 8576 return true; 8577 } 8578 8579 /* 8580 * Do not retry the unhandleable instruction if it faults on the 8581 * readonly host memory, otherwise it will goto a infinite loop: 8582 * retry instruction -> write #PF -> emulation fail -> retry 8583 * instruction -> ... 8584 */ 8585 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 8586 8587 /* 8588 * If the instruction failed on the error pfn, it can not be fixed, 8589 * report the error to userspace. 8590 */ 8591 if (is_error_noslot_pfn(pfn)) 8592 return false; 8593 8594 kvm_release_pfn_clean(pfn); 8595 8596 /* The instructions are well-emulated on direct mmu. */ 8597 if (vcpu->arch.mmu->root_role.direct) { 8598 unsigned int indirect_shadow_pages; 8599 8600 write_lock(&vcpu->kvm->mmu_lock); 8601 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 8602 write_unlock(&vcpu->kvm->mmu_lock); 8603 8604 if (indirect_shadow_pages) 8605 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 8606 8607 return true; 8608 } 8609 8610 /* 8611 * if emulation was due to access to shadowed page table 8612 * and it failed try to unshadow page and re-enter the 8613 * guest to let CPU execute the instruction. 8614 */ 8615 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 8616 8617 /* 8618 * If the access faults on its page table, it can not 8619 * be fixed by unprotecting shadow page and it should 8620 * be reported to userspace. 8621 */ 8622 return !(emulation_type & EMULTYPE_WRITE_PF_TO_SP); 8623 } 8624 8625 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 8626 gpa_t cr2_or_gpa, int emulation_type) 8627 { 8628 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 8629 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; 8630 8631 last_retry_eip = vcpu->arch.last_retry_eip; 8632 last_retry_addr = vcpu->arch.last_retry_addr; 8633 8634 /* 8635 * If the emulation is caused by #PF and it is non-page_table 8636 * writing instruction, it means the VM-EXIT is caused by shadow 8637 * page protected, we can zap the shadow page and retry this 8638 * instruction directly. 8639 * 8640 * Note: if the guest uses a non-page-table modifying instruction 8641 * on the PDE that points to the instruction, then we will unmap 8642 * the instruction and go to an infinite loop. So, we cache the 8643 * last retried eip and the last fault address, if we meet the eip 8644 * and the address again, we can break out of the potential infinite 8645 * loop. 8646 */ 8647 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 8648 8649 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) 8650 return false; 8651 8652 if (WARN_ON_ONCE(is_guest_mode(vcpu)) || 8653 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) 8654 return false; 8655 8656 if (x86_page_table_writing_insn(ctxt)) 8657 return false; 8658 8659 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) 8660 return false; 8661 8662 vcpu->arch.last_retry_eip = ctxt->eip; 8663 vcpu->arch.last_retry_addr = cr2_or_gpa; 8664 8665 if (!vcpu->arch.mmu->root_role.direct) 8666 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); 8667 8668 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 8669 8670 return true; 8671 } 8672 8673 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 8674 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 8675 8676 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 8677 unsigned long *db) 8678 { 8679 u32 dr6 = 0; 8680 int i; 8681 u32 enable, rwlen; 8682 8683 enable = dr7; 8684 rwlen = dr7 >> 16; 8685 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 8686 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 8687 dr6 |= (1 << i); 8688 return dr6; 8689 } 8690 8691 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) 8692 { 8693 struct kvm_run *kvm_run = vcpu->run; 8694 8695 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 8696 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; 8697 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); 8698 kvm_run->debug.arch.exception = DB_VECTOR; 8699 kvm_run->exit_reason = KVM_EXIT_DEBUG; 8700 return 0; 8701 } 8702 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); 8703 return 1; 8704 } 8705 8706 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) 8707 { 8708 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 8709 int r; 8710 8711 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); 8712 if (unlikely(!r)) 8713 return 0; 8714 8715 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS); 8716 8717 /* 8718 * rflags is the old, "raw" value of the flags. The new value has 8719 * not been saved yet. 8720 * 8721 * This is correct even for TF set by the guest, because "the 8722 * processor will not generate this exception after the instruction 8723 * that sets the TF flag". 8724 */ 8725 if (unlikely(rflags & X86_EFLAGS_TF)) 8726 r = kvm_vcpu_do_singlestep(vcpu); 8727 return r; 8728 } 8729 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); 8730 8731 static bool kvm_is_code_breakpoint_inhibited(struct kvm_vcpu *vcpu) 8732 { 8733 u32 shadow; 8734 8735 if (kvm_get_rflags(vcpu) & X86_EFLAGS_RF) 8736 return true; 8737 8738 /* 8739 * Intel CPUs inhibit code #DBs when MOV/POP SS blocking is active, 8740 * but AMD CPUs do not. MOV/POP SS blocking is rare, check that first 8741 * to avoid the relatively expensive CPUID lookup. 8742 */ 8743 shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); 8744 return (shadow & KVM_X86_SHADOW_INT_MOV_SS) && 8745 guest_cpuid_is_intel(vcpu); 8746 } 8747 8748 static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu, 8749 int emulation_type, int *r) 8750 { 8751 WARN_ON_ONCE(emulation_type & EMULTYPE_NO_DECODE); 8752 8753 /* 8754 * Do not check for code breakpoints if hardware has already done the 8755 * checks, as inferred from the emulation type. On NO_DECODE and SKIP, 8756 * the instruction has passed all exception checks, and all intercepted 8757 * exceptions that trigger emulation have lower priority than code 8758 * breakpoints, i.e. the fact that the intercepted exception occurred 8759 * means any code breakpoints have already been serviced. 8760 * 8761 * Note, KVM needs to check for code #DBs on EMULTYPE_TRAP_UD_FORCED as 8762 * hardware has checked the RIP of the magic prefix, but not the RIP of 8763 * the instruction being emulated. The intent of forced emulation is 8764 * to behave as if KVM intercepted the instruction without an exception 8765 * and without a prefix. 8766 */ 8767 if (emulation_type & (EMULTYPE_NO_DECODE | EMULTYPE_SKIP | 8768 EMULTYPE_TRAP_UD | EMULTYPE_VMWARE_GP | EMULTYPE_PF)) 8769 return false; 8770 8771 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 8772 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 8773 struct kvm_run *kvm_run = vcpu->run; 8774 unsigned long eip = kvm_get_linear_rip(vcpu); 8775 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 8776 vcpu->arch.guest_debug_dr7, 8777 vcpu->arch.eff_db); 8778 8779 if (dr6 != 0) { 8780 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; 8781 kvm_run->debug.arch.pc = eip; 8782 kvm_run->debug.arch.exception = DB_VECTOR; 8783 kvm_run->exit_reason = KVM_EXIT_DEBUG; 8784 *r = 0; 8785 return true; 8786 } 8787 } 8788 8789 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && 8790 !kvm_is_code_breakpoint_inhibited(vcpu)) { 8791 unsigned long eip = kvm_get_linear_rip(vcpu); 8792 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 8793 vcpu->arch.dr7, 8794 vcpu->arch.db); 8795 8796 if (dr6 != 0) { 8797 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); 8798 *r = 1; 8799 return true; 8800 } 8801 } 8802 8803 return false; 8804 } 8805 8806 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) 8807 { 8808 switch (ctxt->opcode_len) { 8809 case 1: 8810 switch (ctxt->b) { 8811 case 0xe4: /* IN */ 8812 case 0xe5: 8813 case 0xec: 8814 case 0xed: 8815 case 0xe6: /* OUT */ 8816 case 0xe7: 8817 case 0xee: 8818 case 0xef: 8819 case 0x6c: /* INS */ 8820 case 0x6d: 8821 case 0x6e: /* OUTS */ 8822 case 0x6f: 8823 return true; 8824 } 8825 break; 8826 case 2: 8827 switch (ctxt->b) { 8828 case 0x33: /* RDPMC */ 8829 return true; 8830 } 8831 break; 8832 } 8833 8834 return false; 8835 } 8836 8837 /* 8838 * Decode an instruction for emulation. The caller is responsible for handling 8839 * code breakpoints. Note, manually detecting code breakpoints is unnecessary 8840 * (and wrong) when emulating on an intercepted fault-like exception[*], as 8841 * code breakpoints have higher priority and thus have already been done by 8842 * hardware. 8843 * 8844 * [*] Except #MC, which is higher priority, but KVM should never emulate in 8845 * response to a machine check. 8846 */ 8847 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 8848 void *insn, int insn_len) 8849 { 8850 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8851 int r; 8852 8853 init_emulate_ctxt(vcpu); 8854 8855 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); 8856 8857 trace_kvm_emulate_insn_start(vcpu); 8858 ++vcpu->stat.insn_emulation; 8859 8860 return r; 8861 } 8862 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); 8863 8864 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 8865 int emulation_type, void *insn, int insn_len) 8866 { 8867 int r; 8868 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 8869 bool writeback = true; 8870 8871 if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len))) 8872 return 1; 8873 8874 vcpu->arch.l1tf_flush_l1d = true; 8875 8876 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 8877 kvm_clear_exception_queue(vcpu); 8878 8879 /* 8880 * Return immediately if RIP hits a code breakpoint, such #DBs 8881 * are fault-like and are higher priority than any faults on 8882 * the code fetch itself. 8883 */ 8884 if (kvm_vcpu_check_code_breakpoint(vcpu, emulation_type, &r)) 8885 return r; 8886 8887 r = x86_decode_emulated_instruction(vcpu, emulation_type, 8888 insn, insn_len); 8889 if (r != EMULATION_OK) { 8890 if ((emulation_type & EMULTYPE_TRAP_UD) || 8891 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { 8892 kvm_queue_exception(vcpu, UD_VECTOR); 8893 return 1; 8894 } 8895 if (reexecute_instruction(vcpu, cr2_or_gpa, 8896 emulation_type)) 8897 return 1; 8898 8899 if (ctxt->have_exception && 8900 !(emulation_type & EMULTYPE_SKIP)) { 8901 /* 8902 * #UD should result in just EMULATION_FAILED, and trap-like 8903 * exception should not be encountered during decode. 8904 */ 8905 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || 8906 exception_type(ctxt->exception.vector) == EXCPT_TRAP); 8907 inject_emulated_exception(vcpu); 8908 return 1; 8909 } 8910 return handle_emulation_failure(vcpu, emulation_type); 8911 } 8912 } 8913 8914 if ((emulation_type & EMULTYPE_VMWARE_GP) && 8915 !is_vmware_backdoor_opcode(ctxt)) { 8916 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 8917 return 1; 8918 } 8919 8920 /* 8921 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for 8922 * use *only* by vendor callbacks for kvm_skip_emulated_instruction(). 8923 * The caller is responsible for updating interruptibility state and 8924 * injecting single-step #DBs. 8925 */ 8926 if (emulation_type & EMULTYPE_SKIP) { 8927 if (ctxt->mode != X86EMUL_MODE_PROT64) 8928 ctxt->eip = (u32)ctxt->_eip; 8929 else 8930 ctxt->eip = ctxt->_eip; 8931 8932 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) { 8933 r = 1; 8934 goto writeback; 8935 } 8936 8937 kvm_rip_write(vcpu, ctxt->eip); 8938 if (ctxt->eflags & X86_EFLAGS_RF) 8939 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); 8940 return 1; 8941 } 8942 8943 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) 8944 return 1; 8945 8946 /* this is needed for vmware backdoor interface to work since it 8947 changes registers values during IO operation */ 8948 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 8949 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 8950 emulator_invalidate_register_cache(ctxt); 8951 } 8952 8953 restart: 8954 if (emulation_type & EMULTYPE_PF) { 8955 /* Save the faulting GPA (cr2) in the address field */ 8956 ctxt->exception.address = cr2_or_gpa; 8957 8958 /* With shadow page tables, cr2 contains a GVA or nGPA. */ 8959 if (vcpu->arch.mmu->root_role.direct) { 8960 ctxt->gpa_available = true; 8961 ctxt->gpa_val = cr2_or_gpa; 8962 } 8963 } else { 8964 /* Sanitize the address out of an abundance of paranoia. */ 8965 ctxt->exception.address = 0; 8966 } 8967 8968 r = x86_emulate_insn(ctxt); 8969 8970 if (r == EMULATION_INTERCEPTED) 8971 return 1; 8972 8973 if (r == EMULATION_FAILED) { 8974 if (reexecute_instruction(vcpu, cr2_or_gpa, emulation_type)) 8975 return 1; 8976 8977 return handle_emulation_failure(vcpu, emulation_type); 8978 } 8979 8980 if (ctxt->have_exception) { 8981 WARN_ON_ONCE(vcpu->mmio_needed && !vcpu->mmio_is_write); 8982 vcpu->mmio_needed = false; 8983 r = 1; 8984 inject_emulated_exception(vcpu); 8985 } else if (vcpu->arch.pio.count) { 8986 if (!vcpu->arch.pio.in) { 8987 /* FIXME: return into emulator if single-stepping. */ 8988 vcpu->arch.pio.count = 0; 8989 } else { 8990 writeback = false; 8991 vcpu->arch.complete_userspace_io = complete_emulated_pio; 8992 } 8993 r = 0; 8994 } else if (vcpu->mmio_needed) { 8995 ++vcpu->stat.mmio_exits; 8996 8997 if (!vcpu->mmio_is_write) 8998 writeback = false; 8999 r = 0; 9000 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 9001 } else if (vcpu->arch.complete_userspace_io) { 9002 writeback = false; 9003 r = 0; 9004 } else if (r == EMULATION_RESTART) 9005 goto restart; 9006 else 9007 r = 1; 9008 9009 writeback: 9010 if (writeback) { 9011 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 9012 toggle_interruptibility(vcpu, ctxt->interruptibility); 9013 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 9014 9015 /* 9016 * Note, EXCPT_DB is assumed to be fault-like as the emulator 9017 * only supports code breakpoints and general detect #DB, both 9018 * of which are fault-like. 9019 */ 9020 if (!ctxt->have_exception || 9021 exception_type(ctxt->exception.vector) == EXCPT_TRAP) { 9022 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS); 9023 if (ctxt->is_branch) 9024 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS); 9025 kvm_rip_write(vcpu, ctxt->eip); 9026 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) 9027 r = kvm_vcpu_do_singlestep(vcpu); 9028 static_call_cond(kvm_x86_update_emulated_instruction)(vcpu); 9029 __kvm_set_rflags(vcpu, ctxt->eflags); 9030 } 9031 9032 /* 9033 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will 9034 * do nothing, and it will be requested again as soon as 9035 * the shadow expires. But we still need to check here, 9036 * because POPF has no interrupt shadow. 9037 */ 9038 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) 9039 kvm_make_request(KVM_REQ_EVENT, vcpu); 9040 } else 9041 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 9042 9043 return r; 9044 } 9045 9046 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) 9047 { 9048 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); 9049 } 9050 EXPORT_SYMBOL_GPL(kvm_emulate_instruction); 9051 9052 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, 9053 void *insn, int insn_len) 9054 { 9055 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); 9056 } 9057 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); 9058 9059 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) 9060 { 9061 vcpu->arch.pio.count = 0; 9062 return 1; 9063 } 9064 9065 static int complete_fast_pio_out(struct kvm_vcpu *vcpu) 9066 { 9067 vcpu->arch.pio.count = 0; 9068 9069 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) 9070 return 1; 9071 9072 return kvm_skip_emulated_instruction(vcpu); 9073 } 9074 9075 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, 9076 unsigned short port) 9077 { 9078 unsigned long val = kvm_rax_read(vcpu); 9079 int ret = emulator_pio_out(vcpu, size, port, &val, 1); 9080 9081 if (ret) 9082 return ret; 9083 9084 /* 9085 * Workaround userspace that relies on old KVM behavior of %rip being 9086 * incremented prior to exiting to userspace to handle "OUT 0x7e". 9087 */ 9088 if (port == 0x7e && 9089 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { 9090 vcpu->arch.complete_userspace_io = 9091 complete_fast_pio_out_port_0x7e; 9092 kvm_skip_emulated_instruction(vcpu); 9093 } else { 9094 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 9095 vcpu->arch.complete_userspace_io = complete_fast_pio_out; 9096 } 9097 return 0; 9098 } 9099 9100 static int complete_fast_pio_in(struct kvm_vcpu *vcpu) 9101 { 9102 unsigned long val; 9103 9104 /* We should only ever be called with arch.pio.count equal to 1 */ 9105 BUG_ON(vcpu->arch.pio.count != 1); 9106 9107 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { 9108 vcpu->arch.pio.count = 0; 9109 return 1; 9110 } 9111 9112 /* For size less than 4 we merge, else we zero extend */ 9113 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; 9114 9115 complete_emulator_pio_in(vcpu, &val); 9116 kvm_rax_write(vcpu, val); 9117 9118 return kvm_skip_emulated_instruction(vcpu); 9119 } 9120 9121 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, 9122 unsigned short port) 9123 { 9124 unsigned long val; 9125 int ret; 9126 9127 /* For size less than 4 we merge, else we zero extend */ 9128 val = (size < 4) ? kvm_rax_read(vcpu) : 0; 9129 9130 ret = emulator_pio_in(vcpu, size, port, &val, 1); 9131 if (ret) { 9132 kvm_rax_write(vcpu, val); 9133 return ret; 9134 } 9135 9136 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); 9137 vcpu->arch.complete_userspace_io = complete_fast_pio_in; 9138 9139 return 0; 9140 } 9141 9142 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) 9143 { 9144 int ret; 9145 9146 if (in) 9147 ret = kvm_fast_pio_in(vcpu, size, port); 9148 else 9149 ret = kvm_fast_pio_out(vcpu, size, port); 9150 return ret && kvm_skip_emulated_instruction(vcpu); 9151 } 9152 EXPORT_SYMBOL_GPL(kvm_fast_pio); 9153 9154 static int kvmclock_cpu_down_prep(unsigned int cpu) 9155 { 9156 __this_cpu_write(cpu_tsc_khz, 0); 9157 return 0; 9158 } 9159 9160 static void tsc_khz_changed(void *data) 9161 { 9162 struct cpufreq_freqs *freq = data; 9163 unsigned long khz; 9164 9165 WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_CONSTANT_TSC)); 9166 9167 if (data) 9168 khz = freq->new; 9169 else 9170 khz = cpufreq_quick_get(raw_smp_processor_id()); 9171 if (!khz) 9172 khz = tsc_khz; 9173 __this_cpu_write(cpu_tsc_khz, khz); 9174 } 9175 9176 #ifdef CONFIG_X86_64 9177 static void kvm_hyperv_tsc_notifier(void) 9178 { 9179 struct kvm *kvm; 9180 int cpu; 9181 9182 mutex_lock(&kvm_lock); 9183 list_for_each_entry(kvm, &vm_list, vm_list) 9184 kvm_make_mclock_inprogress_request(kvm); 9185 9186 /* no guest entries from this point */ 9187 hyperv_stop_tsc_emulation(); 9188 9189 /* TSC frequency always matches when on Hyper-V */ 9190 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 9191 for_each_present_cpu(cpu) 9192 per_cpu(cpu_tsc_khz, cpu) = tsc_khz; 9193 } 9194 kvm_caps.max_guest_tsc_khz = tsc_khz; 9195 9196 list_for_each_entry(kvm, &vm_list, vm_list) { 9197 __kvm_start_pvclock_update(kvm); 9198 pvclock_update_vm_gtod_copy(kvm); 9199 kvm_end_pvclock_update(kvm); 9200 } 9201 9202 mutex_unlock(&kvm_lock); 9203 } 9204 #endif 9205 9206 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) 9207 { 9208 struct kvm *kvm; 9209 struct kvm_vcpu *vcpu; 9210 int send_ipi = 0; 9211 unsigned long i; 9212 9213 /* 9214 * We allow guests to temporarily run on slowing clocks, 9215 * provided we notify them after, or to run on accelerating 9216 * clocks, provided we notify them before. Thus time never 9217 * goes backwards. 9218 * 9219 * However, we have a problem. We can't atomically update 9220 * the frequency of a given CPU from this function; it is 9221 * merely a notifier, which can be called from any CPU. 9222 * Changing the TSC frequency at arbitrary points in time 9223 * requires a recomputation of local variables related to 9224 * the TSC for each VCPU. We must flag these local variables 9225 * to be updated and be sure the update takes place with the 9226 * new frequency before any guests proceed. 9227 * 9228 * Unfortunately, the combination of hotplug CPU and frequency 9229 * change creates an intractable locking scenario; the order 9230 * of when these callouts happen is undefined with respect to 9231 * CPU hotplug, and they can race with each other. As such, 9232 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 9233 * undefined; you can actually have a CPU frequency change take 9234 * place in between the computation of X and the setting of the 9235 * variable. To protect against this problem, all updates of 9236 * the per_cpu tsc_khz variable are done in an interrupt 9237 * protected IPI, and all callers wishing to update the value 9238 * must wait for a synchronous IPI to complete (which is trivial 9239 * if the caller is on the CPU already). This establishes the 9240 * necessary total order on variable updates. 9241 * 9242 * Note that because a guest time update may take place 9243 * anytime after the setting of the VCPU's request bit, the 9244 * correct TSC value must be set before the request. However, 9245 * to ensure the update actually makes it to any guest which 9246 * starts running in hardware virtualization between the set 9247 * and the acquisition of the spinlock, we must also ping the 9248 * CPU after setting the request bit. 9249 * 9250 */ 9251 9252 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 9253 9254 mutex_lock(&kvm_lock); 9255 list_for_each_entry(kvm, &vm_list, vm_list) { 9256 kvm_for_each_vcpu(i, vcpu, kvm) { 9257 if (vcpu->cpu != cpu) 9258 continue; 9259 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 9260 if (vcpu->cpu != raw_smp_processor_id()) 9261 send_ipi = 1; 9262 } 9263 } 9264 mutex_unlock(&kvm_lock); 9265 9266 if (freq->old < freq->new && send_ipi) { 9267 /* 9268 * We upscale the frequency. Must make the guest 9269 * doesn't see old kvmclock values while running with 9270 * the new frequency, otherwise we risk the guest sees 9271 * time go backwards. 9272 * 9273 * In case we update the frequency for another cpu 9274 * (which might be in guest context) send an interrupt 9275 * to kick the cpu out of guest context. Next time 9276 * guest context is entered kvmclock will be updated, 9277 * so the guest will not see stale values. 9278 */ 9279 smp_call_function_single(cpu, tsc_khz_changed, freq, 1); 9280 } 9281 } 9282 9283 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 9284 void *data) 9285 { 9286 struct cpufreq_freqs *freq = data; 9287 int cpu; 9288 9289 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 9290 return 0; 9291 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 9292 return 0; 9293 9294 for_each_cpu(cpu, freq->policy->cpus) 9295 __kvmclock_cpufreq_notifier(freq, cpu); 9296 9297 return 0; 9298 } 9299 9300 static struct notifier_block kvmclock_cpufreq_notifier_block = { 9301 .notifier_call = kvmclock_cpufreq_notifier 9302 }; 9303 9304 static int kvmclock_cpu_online(unsigned int cpu) 9305 { 9306 tsc_khz_changed(NULL); 9307 return 0; 9308 } 9309 9310 static void kvm_timer_init(void) 9311 { 9312 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 9313 max_tsc_khz = tsc_khz; 9314 9315 if (IS_ENABLED(CONFIG_CPU_FREQ)) { 9316 struct cpufreq_policy *policy; 9317 int cpu; 9318 9319 cpu = get_cpu(); 9320 policy = cpufreq_cpu_get(cpu); 9321 if (policy) { 9322 if (policy->cpuinfo.max_freq) 9323 max_tsc_khz = policy->cpuinfo.max_freq; 9324 cpufreq_cpu_put(policy); 9325 } 9326 put_cpu(); 9327 } 9328 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 9329 CPUFREQ_TRANSITION_NOTIFIER); 9330 9331 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", 9332 kvmclock_cpu_online, kvmclock_cpu_down_prep); 9333 } 9334 } 9335 9336 #ifdef CONFIG_X86_64 9337 static void pvclock_gtod_update_fn(struct work_struct *work) 9338 { 9339 struct kvm *kvm; 9340 struct kvm_vcpu *vcpu; 9341 unsigned long i; 9342 9343 mutex_lock(&kvm_lock); 9344 list_for_each_entry(kvm, &vm_list, vm_list) 9345 kvm_for_each_vcpu(i, vcpu, kvm) 9346 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 9347 atomic_set(&kvm_guest_has_master_clock, 0); 9348 mutex_unlock(&kvm_lock); 9349 } 9350 9351 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 9352 9353 /* 9354 * Indirection to move queue_work() out of the tk_core.seq write held 9355 * region to prevent possible deadlocks against time accessors which 9356 * are invoked with work related locks held. 9357 */ 9358 static void pvclock_irq_work_fn(struct irq_work *w) 9359 { 9360 queue_work(system_long_wq, &pvclock_gtod_work); 9361 } 9362 9363 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); 9364 9365 /* 9366 * Notification about pvclock gtod data update. 9367 */ 9368 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 9369 void *priv) 9370 { 9371 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 9372 struct timekeeper *tk = priv; 9373 9374 update_pvclock_gtod(tk); 9375 9376 /* 9377 * Disable master clock if host does not trust, or does not use, 9378 * TSC based clocksource. Delegate queue_work() to irq_work as 9379 * this is invoked with tk_core.seq write held. 9380 */ 9381 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && 9382 atomic_read(&kvm_guest_has_master_clock) != 0) 9383 irq_work_queue(&pvclock_irq_work); 9384 return 0; 9385 } 9386 9387 static struct notifier_block pvclock_gtod_notifier = { 9388 .notifier_call = pvclock_gtod_notify, 9389 }; 9390 #endif 9391 9392 static inline void kvm_ops_update(struct kvm_x86_init_ops *ops) 9393 { 9394 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); 9395 9396 #define __KVM_X86_OP(func) \ 9397 static_call_update(kvm_x86_##func, kvm_x86_ops.func); 9398 #define KVM_X86_OP(func) \ 9399 WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func) 9400 #define KVM_X86_OP_OPTIONAL __KVM_X86_OP 9401 #define KVM_X86_OP_OPTIONAL_RET0(func) \ 9402 static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \ 9403 (void *)__static_call_return0); 9404 #include <asm/kvm-x86-ops.h> 9405 #undef __KVM_X86_OP 9406 9407 kvm_pmu_ops_update(ops->pmu_ops); 9408 } 9409 9410 static int kvm_x86_check_processor_compatibility(void) 9411 { 9412 int cpu = smp_processor_id(); 9413 struct cpuinfo_x86 *c = &cpu_data(cpu); 9414 9415 /* 9416 * Compatibility checks are done when loading KVM and when enabling 9417 * hardware, e.g. during CPU hotplug, to ensure all online CPUs are 9418 * compatible, i.e. KVM should never perform a compatibility check on 9419 * an offline CPU. 9420 */ 9421 WARN_ON(!cpu_online(cpu)); 9422 9423 if (__cr4_reserved_bits(cpu_has, c) != 9424 __cr4_reserved_bits(cpu_has, &boot_cpu_data)) 9425 return -EIO; 9426 9427 return static_call(kvm_x86_check_processor_compatibility)(); 9428 } 9429 9430 static void kvm_x86_check_cpu_compat(void *ret) 9431 { 9432 *(int *)ret = kvm_x86_check_processor_compatibility(); 9433 } 9434 9435 static int __kvm_x86_vendor_init(struct kvm_x86_init_ops *ops) 9436 { 9437 u64 host_pat; 9438 int r, cpu; 9439 9440 if (kvm_x86_ops.hardware_enable) { 9441 pr_err("already loaded vendor module '%s'\n", kvm_x86_ops.name); 9442 return -EEXIST; 9443 } 9444 9445 /* 9446 * KVM explicitly assumes that the guest has an FPU and 9447 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the 9448 * vCPU's FPU state as a fxregs_state struct. 9449 */ 9450 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { 9451 pr_err("inadequate fpu\n"); 9452 return -EOPNOTSUPP; 9453 } 9454 9455 if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 9456 pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n"); 9457 return -EOPNOTSUPP; 9458 } 9459 9460 /* 9461 * KVM assumes that PAT entry '0' encodes WB memtype and simply zeroes 9462 * the PAT bits in SPTEs. Bail if PAT[0] is programmed to something 9463 * other than WB. Note, EPT doesn't utilize the PAT, but don't bother 9464 * with an exception. PAT[0] is set to WB on RESET and also by the 9465 * kernel, i.e. failure indicates a kernel bug or broken firmware. 9466 */ 9467 if (rdmsrl_safe(MSR_IA32_CR_PAT, &host_pat) || 9468 (host_pat & GENMASK(2, 0)) != 6) { 9469 pr_err("host PAT[0] is not WB\n"); 9470 return -EIO; 9471 } 9472 9473 x86_emulator_cache = kvm_alloc_emulator_cache(); 9474 if (!x86_emulator_cache) { 9475 pr_err("failed to allocate cache for x86 emulator\n"); 9476 return -ENOMEM; 9477 } 9478 9479 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); 9480 if (!user_return_msrs) { 9481 pr_err("failed to allocate percpu kvm_user_return_msrs\n"); 9482 r = -ENOMEM; 9483 goto out_free_x86_emulator_cache; 9484 } 9485 kvm_nr_uret_msrs = 0; 9486 9487 r = kvm_mmu_vendor_module_init(); 9488 if (r) 9489 goto out_free_percpu; 9490 9491 if (boot_cpu_has(X86_FEATURE_XSAVE)) { 9492 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 9493 kvm_caps.supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; 9494 } 9495 9496 rdmsrl_safe(MSR_EFER, &host_efer); 9497 9498 if (boot_cpu_has(X86_FEATURE_XSAVES)) 9499 rdmsrl(MSR_IA32_XSS, host_xss); 9500 9501 kvm_init_pmu_capability(ops->pmu_ops); 9502 9503 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 9504 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, host_arch_capabilities); 9505 9506 r = ops->hardware_setup(); 9507 if (r != 0) 9508 goto out_mmu_exit; 9509 9510 kvm_ops_update(ops); 9511 9512 for_each_online_cpu(cpu) { 9513 smp_call_function_single(cpu, kvm_x86_check_cpu_compat, &r, 1); 9514 if (r < 0) 9515 goto out_unwind_ops; 9516 } 9517 9518 /* 9519 * Point of no return! DO NOT add error paths below this point unless 9520 * absolutely necessary, as most operations from this point forward 9521 * require unwinding. 9522 */ 9523 kvm_timer_init(); 9524 9525 if (pi_inject_timer == -1) 9526 pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER); 9527 #ifdef CONFIG_X86_64 9528 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 9529 9530 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 9531 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); 9532 #endif 9533 9534 kvm_register_perf_callbacks(ops->handle_intel_pt_intr); 9535 9536 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) 9537 kvm_caps.supported_xss = 0; 9538 9539 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) 9540 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); 9541 #undef __kvm_cpu_cap_has 9542 9543 if (kvm_caps.has_tsc_control) { 9544 /* 9545 * Make sure the user can only configure tsc_khz values that 9546 * fit into a signed integer. 9547 * A min value is not calculated because it will always 9548 * be 1 on all machines. 9549 */ 9550 u64 max = min(0x7fffffffULL, 9551 __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz)); 9552 kvm_caps.max_guest_tsc_khz = max; 9553 } 9554 kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits; 9555 kvm_init_msr_lists(); 9556 return 0; 9557 9558 out_unwind_ops: 9559 kvm_x86_ops.hardware_enable = NULL; 9560 static_call(kvm_x86_hardware_unsetup)(); 9561 out_mmu_exit: 9562 kvm_mmu_vendor_module_exit(); 9563 out_free_percpu: 9564 free_percpu(user_return_msrs); 9565 out_free_x86_emulator_cache: 9566 kmem_cache_destroy(x86_emulator_cache); 9567 return r; 9568 } 9569 9570 int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops) 9571 { 9572 int r; 9573 9574 mutex_lock(&vendor_module_lock); 9575 r = __kvm_x86_vendor_init(ops); 9576 mutex_unlock(&vendor_module_lock); 9577 9578 return r; 9579 } 9580 EXPORT_SYMBOL_GPL(kvm_x86_vendor_init); 9581 9582 void kvm_x86_vendor_exit(void) 9583 { 9584 kvm_unregister_perf_callbacks(); 9585 9586 #ifdef CONFIG_X86_64 9587 if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) 9588 clear_hv_tscchange_cb(); 9589 #endif 9590 kvm_lapic_exit(); 9591 9592 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 9593 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 9594 CPUFREQ_TRANSITION_NOTIFIER); 9595 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); 9596 } 9597 #ifdef CONFIG_X86_64 9598 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 9599 irq_work_sync(&pvclock_irq_work); 9600 cancel_work_sync(&pvclock_gtod_work); 9601 #endif 9602 static_call(kvm_x86_hardware_unsetup)(); 9603 kvm_mmu_vendor_module_exit(); 9604 free_percpu(user_return_msrs); 9605 kmem_cache_destroy(x86_emulator_cache); 9606 #ifdef CONFIG_KVM_XEN 9607 static_key_deferred_flush(&kvm_xen_enabled); 9608 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); 9609 #endif 9610 mutex_lock(&vendor_module_lock); 9611 kvm_x86_ops.hardware_enable = NULL; 9612 mutex_unlock(&vendor_module_lock); 9613 } 9614 EXPORT_SYMBOL_GPL(kvm_x86_vendor_exit); 9615 9616 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason) 9617 { 9618 /* 9619 * The vCPU has halted, e.g. executed HLT. Update the run state if the 9620 * local APIC is in-kernel, the run loop will detect the non-runnable 9621 * state and halt the vCPU. Exit to userspace if the local APIC is 9622 * managed by userspace, in which case userspace is responsible for 9623 * handling wake events. 9624 */ 9625 ++vcpu->stat.halt_exits; 9626 if (lapic_in_kernel(vcpu)) { 9627 vcpu->arch.mp_state = state; 9628 return 1; 9629 } else { 9630 vcpu->run->exit_reason = reason; 9631 return 0; 9632 } 9633 } 9634 9635 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu) 9636 { 9637 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); 9638 } 9639 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip); 9640 9641 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 9642 { 9643 int ret = kvm_skip_emulated_instruction(vcpu); 9644 /* 9645 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered 9646 * KVM_EXIT_DEBUG here. 9647 */ 9648 return kvm_emulate_halt_noskip(vcpu) && ret; 9649 } 9650 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 9651 9652 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) 9653 { 9654 int ret = kvm_skip_emulated_instruction(vcpu); 9655 9656 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, 9657 KVM_EXIT_AP_RESET_HOLD) && ret; 9658 } 9659 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); 9660 9661 #ifdef CONFIG_X86_64 9662 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, 9663 unsigned long clock_type) 9664 { 9665 struct kvm_clock_pairing clock_pairing; 9666 struct timespec64 ts; 9667 u64 cycle; 9668 int ret; 9669 9670 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) 9671 return -KVM_EOPNOTSUPP; 9672 9673 /* 9674 * When tsc is in permanent catchup mode guests won't be able to use 9675 * pvclock_read_retry loop to get consistent view of pvclock 9676 */ 9677 if (vcpu->arch.tsc_always_catchup) 9678 return -KVM_EOPNOTSUPP; 9679 9680 if (!kvm_get_walltime_and_clockread(&ts, &cycle)) 9681 return -KVM_EOPNOTSUPP; 9682 9683 clock_pairing.sec = ts.tv_sec; 9684 clock_pairing.nsec = ts.tv_nsec; 9685 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); 9686 clock_pairing.flags = 0; 9687 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); 9688 9689 ret = 0; 9690 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, 9691 sizeof(struct kvm_clock_pairing))) 9692 ret = -KVM_EFAULT; 9693 9694 return ret; 9695 } 9696 #endif 9697 9698 /* 9699 * kvm_pv_kick_cpu_op: Kick a vcpu. 9700 * 9701 * @apicid - apicid of vcpu to be kicked. 9702 */ 9703 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid) 9704 { 9705 /* 9706 * All other fields are unused for APIC_DM_REMRD, but may be consumed by 9707 * common code, e.g. for tracing. Defer initialization to the compiler. 9708 */ 9709 struct kvm_lapic_irq lapic_irq = { 9710 .delivery_mode = APIC_DM_REMRD, 9711 .dest_mode = APIC_DEST_PHYSICAL, 9712 .shorthand = APIC_DEST_NOSHORT, 9713 .dest_id = apicid, 9714 }; 9715 9716 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); 9717 } 9718 9719 bool kvm_apicv_activated(struct kvm *kvm) 9720 { 9721 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); 9722 } 9723 EXPORT_SYMBOL_GPL(kvm_apicv_activated); 9724 9725 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu) 9726 { 9727 ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons); 9728 ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu); 9729 9730 return (vm_reasons | vcpu_reasons) == 0; 9731 } 9732 EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated); 9733 9734 static void set_or_clear_apicv_inhibit(unsigned long *inhibits, 9735 enum kvm_apicv_inhibit reason, bool set) 9736 { 9737 if (set) 9738 __set_bit(reason, inhibits); 9739 else 9740 __clear_bit(reason, inhibits); 9741 9742 trace_kvm_apicv_inhibit_changed(reason, set, *inhibits); 9743 } 9744 9745 static void kvm_apicv_init(struct kvm *kvm) 9746 { 9747 unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons; 9748 9749 init_rwsem(&kvm->arch.apicv_update_lock); 9750 9751 set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true); 9752 9753 if (!enable_apicv) 9754 set_or_clear_apicv_inhibit(inhibits, 9755 APICV_INHIBIT_REASON_DISABLE, true); 9756 } 9757 9758 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) 9759 { 9760 struct kvm_vcpu *target = NULL; 9761 struct kvm_apic_map *map; 9762 9763 vcpu->stat.directed_yield_attempted++; 9764 9765 if (single_task_running()) 9766 goto no_yield; 9767 9768 rcu_read_lock(); 9769 map = rcu_dereference(vcpu->kvm->arch.apic_map); 9770 9771 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) 9772 target = map->phys_map[dest_id]->vcpu; 9773 9774 rcu_read_unlock(); 9775 9776 if (!target || !READ_ONCE(target->ready)) 9777 goto no_yield; 9778 9779 /* Ignore requests to yield to self */ 9780 if (vcpu == target) 9781 goto no_yield; 9782 9783 if (kvm_vcpu_yield_to(target) <= 0) 9784 goto no_yield; 9785 9786 vcpu->stat.directed_yield_successful++; 9787 9788 no_yield: 9789 return; 9790 } 9791 9792 static int complete_hypercall_exit(struct kvm_vcpu *vcpu) 9793 { 9794 u64 ret = vcpu->run->hypercall.ret; 9795 9796 if (!is_64_bit_mode(vcpu)) 9797 ret = (u32)ret; 9798 kvm_rax_write(vcpu, ret); 9799 ++vcpu->stat.hypercalls; 9800 return kvm_skip_emulated_instruction(vcpu); 9801 } 9802 9803 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 9804 { 9805 unsigned long nr, a0, a1, a2, a3, ret; 9806 int op_64_bit; 9807 9808 if (kvm_xen_hypercall_enabled(vcpu->kvm)) 9809 return kvm_xen_hypercall(vcpu); 9810 9811 if (kvm_hv_hypercall_enabled(vcpu)) 9812 return kvm_hv_hypercall(vcpu); 9813 9814 nr = kvm_rax_read(vcpu); 9815 a0 = kvm_rbx_read(vcpu); 9816 a1 = kvm_rcx_read(vcpu); 9817 a2 = kvm_rdx_read(vcpu); 9818 a3 = kvm_rsi_read(vcpu); 9819 9820 trace_kvm_hypercall(nr, a0, a1, a2, a3); 9821 9822 op_64_bit = is_64_bit_hypercall(vcpu); 9823 if (!op_64_bit) { 9824 nr &= 0xFFFFFFFF; 9825 a0 &= 0xFFFFFFFF; 9826 a1 &= 0xFFFFFFFF; 9827 a2 &= 0xFFFFFFFF; 9828 a3 &= 0xFFFFFFFF; 9829 } 9830 9831 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { 9832 ret = -KVM_EPERM; 9833 goto out; 9834 } 9835 9836 ret = -KVM_ENOSYS; 9837 9838 switch (nr) { 9839 case KVM_HC_VAPIC_POLL_IRQ: 9840 ret = 0; 9841 break; 9842 case KVM_HC_KICK_CPU: 9843 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) 9844 break; 9845 9846 kvm_pv_kick_cpu_op(vcpu->kvm, a1); 9847 kvm_sched_yield(vcpu, a1); 9848 ret = 0; 9849 break; 9850 #ifdef CONFIG_X86_64 9851 case KVM_HC_CLOCK_PAIRING: 9852 ret = kvm_pv_clock_pairing(vcpu, a0, a1); 9853 break; 9854 #endif 9855 case KVM_HC_SEND_IPI: 9856 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) 9857 break; 9858 9859 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); 9860 break; 9861 case KVM_HC_SCHED_YIELD: 9862 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) 9863 break; 9864 9865 kvm_sched_yield(vcpu, a0); 9866 ret = 0; 9867 break; 9868 case KVM_HC_MAP_GPA_RANGE: { 9869 u64 gpa = a0, npages = a1, attrs = a2; 9870 9871 ret = -KVM_ENOSYS; 9872 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE))) 9873 break; 9874 9875 if (!PAGE_ALIGNED(gpa) || !npages || 9876 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) { 9877 ret = -KVM_EINVAL; 9878 break; 9879 } 9880 9881 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL; 9882 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE; 9883 vcpu->run->hypercall.args[0] = gpa; 9884 vcpu->run->hypercall.args[1] = npages; 9885 vcpu->run->hypercall.args[2] = attrs; 9886 vcpu->run->hypercall.flags = 0; 9887 if (op_64_bit) 9888 vcpu->run->hypercall.flags |= KVM_EXIT_HYPERCALL_LONG_MODE; 9889 9890 WARN_ON_ONCE(vcpu->run->hypercall.flags & KVM_EXIT_HYPERCALL_MBZ); 9891 vcpu->arch.complete_userspace_io = complete_hypercall_exit; 9892 return 0; 9893 } 9894 default: 9895 ret = -KVM_ENOSYS; 9896 break; 9897 } 9898 out: 9899 if (!op_64_bit) 9900 ret = (u32)ret; 9901 kvm_rax_write(vcpu, ret); 9902 9903 ++vcpu->stat.hypercalls; 9904 return kvm_skip_emulated_instruction(vcpu); 9905 } 9906 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 9907 9908 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 9909 { 9910 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 9911 char instruction[3]; 9912 unsigned long rip = kvm_rip_read(vcpu); 9913 9914 /* 9915 * If the quirk is disabled, synthesize a #UD and let the guest pick up 9916 * the pieces. 9917 */ 9918 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) { 9919 ctxt->exception.error_code_valid = false; 9920 ctxt->exception.vector = UD_VECTOR; 9921 ctxt->have_exception = true; 9922 return X86EMUL_PROPAGATE_FAULT; 9923 } 9924 9925 static_call(kvm_x86_patch_hypercall)(vcpu, instruction); 9926 9927 return emulator_write_emulated(ctxt, rip, instruction, 3, 9928 &ctxt->exception); 9929 } 9930 9931 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 9932 { 9933 return vcpu->run->request_interrupt_window && 9934 likely(!pic_in_kernel(vcpu->kvm)); 9935 } 9936 9937 /* Called within kvm->srcu read side. */ 9938 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 9939 { 9940 struct kvm_run *kvm_run = vcpu->run; 9941 9942 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu); 9943 kvm_run->cr8 = kvm_get_cr8(vcpu); 9944 kvm_run->apic_base = kvm_get_apic_base(vcpu); 9945 9946 kvm_run->ready_for_interrupt_injection = 9947 pic_in_kernel(vcpu->kvm) || 9948 kvm_vcpu_ready_for_interrupt_injection(vcpu); 9949 9950 if (is_smm(vcpu)) 9951 kvm_run->flags |= KVM_RUN_X86_SMM; 9952 } 9953 9954 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 9955 { 9956 int max_irr, tpr; 9957 9958 if (!kvm_x86_ops.update_cr8_intercept) 9959 return; 9960 9961 if (!lapic_in_kernel(vcpu)) 9962 return; 9963 9964 if (vcpu->arch.apic->apicv_active) 9965 return; 9966 9967 if (!vcpu->arch.apic->vapic_addr) 9968 max_irr = kvm_lapic_find_highest_irr(vcpu); 9969 else 9970 max_irr = -1; 9971 9972 if (max_irr != -1) 9973 max_irr >>= 4; 9974 9975 tpr = kvm_lapic_get_cr8(vcpu); 9976 9977 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); 9978 } 9979 9980 9981 int kvm_check_nested_events(struct kvm_vcpu *vcpu) 9982 { 9983 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 9984 kvm_x86_ops.nested_ops->triple_fault(vcpu); 9985 return 1; 9986 } 9987 9988 return kvm_x86_ops.nested_ops->check_events(vcpu); 9989 } 9990 9991 static void kvm_inject_exception(struct kvm_vcpu *vcpu) 9992 { 9993 /* 9994 * Suppress the error code if the vCPU is in Real Mode, as Real Mode 9995 * exceptions don't report error codes. The presence of an error code 9996 * is carried with the exception and only stripped when the exception 9997 * is injected as intercepted #PF VM-Exits for AMD's Paged Real Mode do 9998 * report an error code despite the CPU being in Real Mode. 9999 */ 10000 vcpu->arch.exception.has_error_code &= is_protmode(vcpu); 10001 10002 trace_kvm_inj_exception(vcpu->arch.exception.vector, 10003 vcpu->arch.exception.has_error_code, 10004 vcpu->arch.exception.error_code, 10005 vcpu->arch.exception.injected); 10006 10007 static_call(kvm_x86_inject_exception)(vcpu); 10008 } 10009 10010 /* 10011 * Check for any event (interrupt or exception) that is ready to be injected, 10012 * and if there is at least one event, inject the event with the highest 10013 * priority. This handles both "pending" events, i.e. events that have never 10014 * been injected into the guest, and "injected" events, i.e. events that were 10015 * injected as part of a previous VM-Enter, but weren't successfully delivered 10016 * and need to be re-injected. 10017 * 10018 * Note, this is not guaranteed to be invoked on a guest instruction boundary, 10019 * i.e. doesn't guarantee that there's an event window in the guest. KVM must 10020 * be able to inject exceptions in the "middle" of an instruction, and so must 10021 * also be able to re-inject NMIs and IRQs in the middle of an instruction. 10022 * I.e. for exceptions and re-injected events, NOT invoking this on instruction 10023 * boundaries is necessary and correct. 10024 * 10025 * For simplicity, KVM uses a single path to inject all events (except events 10026 * that are injected directly from L1 to L2) and doesn't explicitly track 10027 * instruction boundaries for asynchronous events. However, because VM-Exits 10028 * that can occur during instruction execution typically result in KVM skipping 10029 * the instruction or injecting an exception, e.g. instruction and exception 10030 * intercepts, and because pending exceptions have higher priority than pending 10031 * interrupts, KVM still honors instruction boundaries in most scenarios. 10032 * 10033 * But, if a VM-Exit occurs during instruction execution, and KVM does NOT skip 10034 * the instruction or inject an exception, then KVM can incorrecty inject a new 10035 * asynchrounous event if the event became pending after the CPU fetched the 10036 * instruction (in the guest). E.g. if a page fault (#PF, #NPF, EPT violation) 10037 * occurs and is resolved by KVM, a coincident NMI, SMI, IRQ, etc... can be 10038 * injected on the restarted instruction instead of being deferred until the 10039 * instruction completes. 10040 * 10041 * In practice, this virtualization hole is unlikely to be observed by the 10042 * guest, and even less likely to cause functional problems. To detect the 10043 * hole, the guest would have to trigger an event on a side effect of an early 10044 * phase of instruction execution, e.g. on the instruction fetch from memory. 10045 * And for it to be a functional problem, the guest would need to depend on the 10046 * ordering between that side effect, the instruction completing, _and_ the 10047 * delivery of the asynchronous event. 10048 */ 10049 static int kvm_check_and_inject_events(struct kvm_vcpu *vcpu, 10050 bool *req_immediate_exit) 10051 { 10052 bool can_inject; 10053 int r; 10054 10055 /* 10056 * Process nested events first, as nested VM-Exit supercedes event 10057 * re-injection. If there's an event queued for re-injection, it will 10058 * be saved into the appropriate vmc{b,s}12 fields on nested VM-Exit. 10059 */ 10060 if (is_guest_mode(vcpu)) 10061 r = kvm_check_nested_events(vcpu); 10062 else 10063 r = 0; 10064 10065 /* 10066 * Re-inject exceptions and events *especially* if immediate entry+exit 10067 * to/from L2 is needed, as any event that has already been injected 10068 * into L2 needs to complete its lifecycle before injecting a new event. 10069 * 10070 * Don't re-inject an NMI or interrupt if there is a pending exception. 10071 * This collision arises if an exception occurred while vectoring the 10072 * injected event, KVM intercepted said exception, and KVM ultimately 10073 * determined the fault belongs to the guest and queues the exception 10074 * for injection back into the guest. 10075 * 10076 * "Injected" interrupts can also collide with pending exceptions if 10077 * userspace ignores the "ready for injection" flag and blindly queues 10078 * an interrupt. In that case, prioritizing the exception is correct, 10079 * as the exception "occurred" before the exit to userspace. Trap-like 10080 * exceptions, e.g. most #DBs, have higher priority than interrupts. 10081 * And while fault-like exceptions, e.g. #GP and #PF, are the lowest 10082 * priority, they're only generated (pended) during instruction 10083 * execution, and interrupts are recognized at instruction boundaries. 10084 * Thus a pending fault-like exception means the fault occurred on the 10085 * *previous* instruction and must be serviced prior to recognizing any 10086 * new events in order to fully complete the previous instruction. 10087 */ 10088 if (vcpu->arch.exception.injected) 10089 kvm_inject_exception(vcpu); 10090 else if (kvm_is_exception_pending(vcpu)) 10091 ; /* see above */ 10092 else if (vcpu->arch.nmi_injected) 10093 static_call(kvm_x86_inject_nmi)(vcpu); 10094 else if (vcpu->arch.interrupt.injected) 10095 static_call(kvm_x86_inject_irq)(vcpu, true); 10096 10097 /* 10098 * Exceptions that morph to VM-Exits are handled above, and pending 10099 * exceptions on top of injected exceptions that do not VM-Exit should 10100 * either morph to #DF or, sadly, override the injected exception. 10101 */ 10102 WARN_ON_ONCE(vcpu->arch.exception.injected && 10103 vcpu->arch.exception.pending); 10104 10105 /* 10106 * Bail if immediate entry+exit to/from the guest is needed to complete 10107 * nested VM-Enter or event re-injection so that a different pending 10108 * event can be serviced (or if KVM needs to exit to userspace). 10109 * 10110 * Otherwise, continue processing events even if VM-Exit occurred. The 10111 * VM-Exit will have cleared exceptions that were meant for L2, but 10112 * there may now be events that can be injected into L1. 10113 */ 10114 if (r < 0) 10115 goto out; 10116 10117 /* 10118 * A pending exception VM-Exit should either result in nested VM-Exit 10119 * or force an immediate re-entry and exit to/from L2, and exception 10120 * VM-Exits cannot be injected (flag should _never_ be set). 10121 */ 10122 WARN_ON_ONCE(vcpu->arch.exception_vmexit.injected || 10123 vcpu->arch.exception_vmexit.pending); 10124 10125 /* 10126 * New events, other than exceptions, cannot be injected if KVM needs 10127 * to re-inject a previous event. See above comments on re-injecting 10128 * for why pending exceptions get priority. 10129 */ 10130 can_inject = !kvm_event_needs_reinjection(vcpu); 10131 10132 if (vcpu->arch.exception.pending) { 10133 /* 10134 * Fault-class exceptions, except #DBs, set RF=1 in the RFLAGS 10135 * value pushed on the stack. Trap-like exception and all #DBs 10136 * leave RF as-is (KVM follows Intel's behavior in this regard; 10137 * AMD states that code breakpoint #DBs excplitly clear RF=0). 10138 * 10139 * Note, most versions of Intel's SDM and AMD's APM incorrectly 10140 * describe the behavior of General Detect #DBs, which are 10141 * fault-like. They do _not_ set RF, a la code breakpoints. 10142 */ 10143 if (exception_type(vcpu->arch.exception.vector) == EXCPT_FAULT) 10144 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | 10145 X86_EFLAGS_RF); 10146 10147 if (vcpu->arch.exception.vector == DB_VECTOR) { 10148 kvm_deliver_exception_payload(vcpu, &vcpu->arch.exception); 10149 if (vcpu->arch.dr7 & DR7_GD) { 10150 vcpu->arch.dr7 &= ~DR7_GD; 10151 kvm_update_dr7(vcpu); 10152 } 10153 } 10154 10155 kvm_inject_exception(vcpu); 10156 10157 vcpu->arch.exception.pending = false; 10158 vcpu->arch.exception.injected = true; 10159 10160 can_inject = false; 10161 } 10162 10163 /* Don't inject interrupts if the user asked to avoid doing so */ 10164 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) 10165 return 0; 10166 10167 /* 10168 * Finally, inject interrupt events. If an event cannot be injected 10169 * due to architectural conditions (e.g. IF=0) a window-open exit 10170 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending 10171 * and can architecturally be injected, but we cannot do it right now: 10172 * an interrupt could have arrived just now and we have to inject it 10173 * as a vmexit, or there could already an event in the queue, which is 10174 * indicated by can_inject. In that case we request an immediate exit 10175 * in order to make progress and get back here for another iteration. 10176 * The kvm_x86_ops hooks communicate this by returning -EBUSY. 10177 */ 10178 #ifdef CONFIG_KVM_SMM 10179 if (vcpu->arch.smi_pending) { 10180 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; 10181 if (r < 0) 10182 goto out; 10183 if (r) { 10184 vcpu->arch.smi_pending = false; 10185 ++vcpu->arch.smi_count; 10186 enter_smm(vcpu); 10187 can_inject = false; 10188 } else 10189 static_call(kvm_x86_enable_smi_window)(vcpu); 10190 } 10191 #endif 10192 10193 if (vcpu->arch.nmi_pending) { 10194 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; 10195 if (r < 0) 10196 goto out; 10197 if (r) { 10198 --vcpu->arch.nmi_pending; 10199 vcpu->arch.nmi_injected = true; 10200 static_call(kvm_x86_inject_nmi)(vcpu); 10201 can_inject = false; 10202 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); 10203 } 10204 if (vcpu->arch.nmi_pending) 10205 static_call(kvm_x86_enable_nmi_window)(vcpu); 10206 } 10207 10208 if (kvm_cpu_has_injectable_intr(vcpu)) { 10209 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; 10210 if (r < 0) 10211 goto out; 10212 if (r) { 10213 int irq = kvm_cpu_get_interrupt(vcpu); 10214 10215 if (!WARN_ON_ONCE(irq == -1)) { 10216 kvm_queue_interrupt(vcpu, irq, false); 10217 static_call(kvm_x86_inject_irq)(vcpu, false); 10218 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); 10219 } 10220 } 10221 if (kvm_cpu_has_injectable_intr(vcpu)) 10222 static_call(kvm_x86_enable_irq_window)(vcpu); 10223 } 10224 10225 if (is_guest_mode(vcpu) && 10226 kvm_x86_ops.nested_ops->has_events && 10227 kvm_x86_ops.nested_ops->has_events(vcpu)) 10228 *req_immediate_exit = true; 10229 10230 /* 10231 * KVM must never queue a new exception while injecting an event; KVM 10232 * is done emulating and should only propagate the to-be-injected event 10233 * to the VMCS/VMCB. Queueing a new exception can put the vCPU into an 10234 * infinite loop as KVM will bail from VM-Enter to inject the pending 10235 * exception and start the cycle all over. 10236 * 10237 * Exempt triple faults as they have special handling and won't put the 10238 * vCPU into an infinite loop. Triple fault can be queued when running 10239 * VMX without unrestricted guest, as that requires KVM to emulate Real 10240 * Mode events (see kvm_inject_realmode_interrupt()). 10241 */ 10242 WARN_ON_ONCE(vcpu->arch.exception.pending || 10243 vcpu->arch.exception_vmexit.pending); 10244 return 0; 10245 10246 out: 10247 if (r == -EBUSY) { 10248 *req_immediate_exit = true; 10249 r = 0; 10250 } 10251 return r; 10252 } 10253 10254 static void process_nmi(struct kvm_vcpu *vcpu) 10255 { 10256 unsigned int limit; 10257 10258 /* 10259 * x86 is limited to one NMI pending, but because KVM can't react to 10260 * incoming NMIs as quickly as bare metal, e.g. if the vCPU is 10261 * scheduled out, KVM needs to play nice with two queued NMIs showing 10262 * up at the same time. To handle this scenario, allow two NMIs to be 10263 * (temporarily) pending so long as NMIs are not blocked and KVM is not 10264 * waiting for a previous NMI injection to complete (which effectively 10265 * blocks NMIs). KVM will immediately inject one of the two NMIs, and 10266 * will request an NMI window to handle the second NMI. 10267 */ 10268 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) 10269 limit = 1; 10270 else 10271 limit = 2; 10272 10273 /* 10274 * Adjust the limit to account for pending virtual NMIs, which aren't 10275 * tracked in vcpu->arch.nmi_pending. 10276 */ 10277 if (static_call(kvm_x86_is_vnmi_pending)(vcpu)) 10278 limit--; 10279 10280 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 10281 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 10282 10283 if (vcpu->arch.nmi_pending && 10284 (static_call(kvm_x86_set_vnmi_pending)(vcpu))) 10285 vcpu->arch.nmi_pending--; 10286 10287 if (vcpu->arch.nmi_pending) 10288 kvm_make_request(KVM_REQ_EVENT, vcpu); 10289 } 10290 10291 /* Return total number of NMIs pending injection to the VM */ 10292 int kvm_get_nr_pending_nmis(struct kvm_vcpu *vcpu) 10293 { 10294 return vcpu->arch.nmi_pending + 10295 static_call(kvm_x86_is_vnmi_pending)(vcpu); 10296 } 10297 10298 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, 10299 unsigned long *vcpu_bitmap) 10300 { 10301 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap); 10302 } 10303 10304 void kvm_make_scan_ioapic_request(struct kvm *kvm) 10305 { 10306 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); 10307 } 10308 10309 void __kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 10310 { 10311 struct kvm_lapic *apic = vcpu->arch.apic; 10312 bool activate; 10313 10314 if (!lapic_in_kernel(vcpu)) 10315 return; 10316 10317 down_read(&vcpu->kvm->arch.apicv_update_lock); 10318 preempt_disable(); 10319 10320 /* Do not activate APICV when APIC is disabled */ 10321 activate = kvm_vcpu_apicv_activated(vcpu) && 10322 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED); 10323 10324 if (apic->apicv_active == activate) 10325 goto out; 10326 10327 apic->apicv_active = activate; 10328 kvm_apic_update_apicv(vcpu); 10329 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); 10330 10331 /* 10332 * When APICv gets disabled, we may still have injected interrupts 10333 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was 10334 * still active when the interrupt got accepted. Make sure 10335 * kvm_check_and_inject_events() is called to check for that. 10336 */ 10337 if (!apic->apicv_active) 10338 kvm_make_request(KVM_REQ_EVENT, vcpu); 10339 10340 out: 10341 preempt_enable(); 10342 up_read(&vcpu->kvm->arch.apicv_update_lock); 10343 } 10344 EXPORT_SYMBOL_GPL(__kvm_vcpu_update_apicv); 10345 10346 static void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) 10347 { 10348 if (!lapic_in_kernel(vcpu)) 10349 return; 10350 10351 /* 10352 * Due to sharing page tables across vCPUs, the xAPIC memslot must be 10353 * deleted if any vCPU has xAPIC virtualization and x2APIC enabled, but 10354 * and hardware doesn't support x2APIC virtualization. E.g. some AMD 10355 * CPUs support AVIC but not x2APIC. KVM still allows enabling AVIC in 10356 * this case so that KVM can the AVIC doorbell to inject interrupts to 10357 * running vCPUs, but KVM must not create SPTEs for the APIC base as 10358 * the vCPU would incorrectly be able to access the vAPIC page via MMIO 10359 * despite being in x2APIC mode. For simplicity, inhibiting the APIC 10360 * access page is sticky. 10361 */ 10362 if (apic_x2apic_mode(vcpu->arch.apic) && 10363 kvm_x86_ops.allow_apicv_in_x2apic_without_x2apic_virtualization) 10364 kvm_inhibit_apic_access_page(vcpu); 10365 10366 __kvm_vcpu_update_apicv(vcpu); 10367 } 10368 10369 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, 10370 enum kvm_apicv_inhibit reason, bool set) 10371 { 10372 unsigned long old, new; 10373 10374 lockdep_assert_held_write(&kvm->arch.apicv_update_lock); 10375 10376 if (!(kvm_x86_ops.required_apicv_inhibits & BIT(reason))) 10377 return; 10378 10379 old = new = kvm->arch.apicv_inhibit_reasons; 10380 10381 set_or_clear_apicv_inhibit(&new, reason, set); 10382 10383 if (!!old != !!new) { 10384 /* 10385 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid 10386 * false positives in the sanity check WARN in svm_vcpu_run(). 10387 * This task will wait for all vCPUs to ack the kick IRQ before 10388 * updating apicv_inhibit_reasons, and all other vCPUs will 10389 * block on acquiring apicv_update_lock so that vCPUs can't 10390 * redo svm_vcpu_run() without seeing the new inhibit state. 10391 * 10392 * Note, holding apicv_update_lock and taking it in the read 10393 * side (handling the request) also prevents other vCPUs from 10394 * servicing the request with a stale apicv_inhibit_reasons. 10395 */ 10396 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); 10397 kvm->arch.apicv_inhibit_reasons = new; 10398 if (new) { 10399 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE); 10400 int idx = srcu_read_lock(&kvm->srcu); 10401 10402 kvm_zap_gfn_range(kvm, gfn, gfn+1); 10403 srcu_read_unlock(&kvm->srcu, idx); 10404 } 10405 } else { 10406 kvm->arch.apicv_inhibit_reasons = new; 10407 } 10408 } 10409 10410 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, 10411 enum kvm_apicv_inhibit reason, bool set) 10412 { 10413 if (!enable_apicv) 10414 return; 10415 10416 down_write(&kvm->arch.apicv_update_lock); 10417 __kvm_set_or_clear_apicv_inhibit(kvm, reason, set); 10418 up_write(&kvm->arch.apicv_update_lock); 10419 } 10420 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit); 10421 10422 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 10423 { 10424 if (!kvm_apic_present(vcpu)) 10425 return; 10426 10427 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); 10428 10429 if (irqchip_split(vcpu->kvm)) 10430 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); 10431 else { 10432 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 10433 if (ioapic_in_kernel(vcpu->kvm)) 10434 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); 10435 } 10436 10437 if (is_guest_mode(vcpu)) 10438 vcpu->arch.load_eoi_exitmap_pending = true; 10439 else 10440 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); 10441 } 10442 10443 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) 10444 { 10445 u64 eoi_exit_bitmap[4]; 10446 10447 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 10448 return; 10449 10450 if (to_hv_vcpu(vcpu)) { 10451 bitmap_or((ulong *)eoi_exit_bitmap, 10452 vcpu->arch.ioapic_handled_vectors, 10453 to_hv_synic(vcpu)->vec_bitmap, 256); 10454 static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); 10455 return; 10456 } 10457 10458 static_call_cond(kvm_x86_load_eoi_exitmap)( 10459 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors); 10460 } 10461 10462 void kvm_arch_guest_memory_reclaimed(struct kvm *kvm) 10463 { 10464 static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm); 10465 } 10466 10467 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) 10468 { 10469 if (!lapic_in_kernel(vcpu)) 10470 return; 10471 10472 static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu); 10473 } 10474 10475 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) 10476 { 10477 smp_send_reschedule(vcpu->cpu); 10478 } 10479 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); 10480 10481 /* 10482 * Called within kvm->srcu read side. 10483 * Returns 1 to let vcpu_run() continue the guest execution loop without 10484 * exiting to the userspace. Otherwise, the value will be returned to the 10485 * userspace. 10486 */ 10487 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 10488 { 10489 int r; 10490 bool req_int_win = 10491 dm_request_for_irq_injection(vcpu) && 10492 kvm_cpu_accept_dm_intr(vcpu); 10493 fastpath_t exit_fastpath; 10494 10495 bool req_immediate_exit = false; 10496 10497 if (kvm_request_pending(vcpu)) { 10498 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) { 10499 r = -EIO; 10500 goto out; 10501 } 10502 10503 if (kvm_dirty_ring_check_request(vcpu)) { 10504 r = 0; 10505 goto out; 10506 } 10507 10508 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { 10509 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { 10510 r = 0; 10511 goto out; 10512 } 10513 } 10514 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu)) 10515 kvm_mmu_free_obsolete_roots(vcpu); 10516 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 10517 __kvm_migrate_timers(vcpu); 10518 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 10519 kvm_update_masterclock(vcpu->kvm); 10520 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 10521 kvm_gen_kvmclock_update(vcpu); 10522 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 10523 r = kvm_guest_time_update(vcpu); 10524 if (unlikely(r)) 10525 goto out; 10526 } 10527 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 10528 kvm_mmu_sync_roots(vcpu); 10529 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) 10530 kvm_mmu_load_pgd(vcpu); 10531 10532 /* 10533 * Note, the order matters here, as flushing "all" TLB entries 10534 * also flushes the "current" TLB entries, i.e. servicing the 10535 * flush "all" will clear any request to flush "current". 10536 */ 10537 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 10538 kvm_vcpu_flush_tlb_all(vcpu); 10539 10540 kvm_service_local_tlb_flush_requests(vcpu); 10541 10542 /* 10543 * Fall back to a "full" guest flush if Hyper-V's precise 10544 * flushing fails. Note, Hyper-V's flushing is per-vCPU, but 10545 * the flushes are considered "remote" and not "local" because 10546 * the requests can be initiated from other vCPUs. 10547 */ 10548 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu) && 10549 kvm_hv_vcpu_flush_tlb(vcpu)) 10550 kvm_vcpu_flush_tlb_guest(vcpu); 10551 10552 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 10553 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 10554 r = 0; 10555 goto out; 10556 } 10557 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 10558 if (is_guest_mode(vcpu)) 10559 kvm_x86_ops.nested_ops->triple_fault(vcpu); 10560 10561 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 10562 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 10563 vcpu->mmio_needed = 0; 10564 r = 0; 10565 goto out; 10566 } 10567 } 10568 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 10569 /* Page is swapped out. Do synthetic halt */ 10570 vcpu->arch.apf.halted = true; 10571 r = 1; 10572 goto out; 10573 } 10574 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 10575 record_steal_time(vcpu); 10576 #ifdef CONFIG_KVM_SMM 10577 if (kvm_check_request(KVM_REQ_SMI, vcpu)) 10578 process_smi(vcpu); 10579 #endif 10580 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 10581 process_nmi(vcpu); 10582 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 10583 kvm_pmu_handle_event(vcpu); 10584 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 10585 kvm_pmu_deliver_pmi(vcpu); 10586 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { 10587 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); 10588 if (test_bit(vcpu->arch.pending_ioapic_eoi, 10589 vcpu->arch.ioapic_handled_vectors)) { 10590 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; 10591 vcpu->run->eoi.vector = 10592 vcpu->arch.pending_ioapic_eoi; 10593 r = 0; 10594 goto out; 10595 } 10596 } 10597 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 10598 vcpu_scan_ioapic(vcpu); 10599 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) 10600 vcpu_load_eoi_exitmap(vcpu); 10601 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) 10602 kvm_vcpu_reload_apic_access_page(vcpu); 10603 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { 10604 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 10605 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; 10606 vcpu->run->system_event.ndata = 0; 10607 r = 0; 10608 goto out; 10609 } 10610 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { 10611 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; 10612 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; 10613 vcpu->run->system_event.ndata = 0; 10614 r = 0; 10615 goto out; 10616 } 10617 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { 10618 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); 10619 10620 vcpu->run->exit_reason = KVM_EXIT_HYPERV; 10621 vcpu->run->hyperv = hv_vcpu->exit; 10622 r = 0; 10623 goto out; 10624 } 10625 10626 /* 10627 * KVM_REQ_HV_STIMER has to be processed after 10628 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers 10629 * depend on the guest clock being up-to-date 10630 */ 10631 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) 10632 kvm_hv_process_stimers(vcpu); 10633 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) 10634 kvm_vcpu_update_apicv(vcpu); 10635 if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) 10636 kvm_check_async_pf_completion(vcpu); 10637 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) 10638 static_call(kvm_x86_msr_filter_changed)(vcpu); 10639 10640 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) 10641 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); 10642 } 10643 10644 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || 10645 kvm_xen_has_interrupt(vcpu)) { 10646 ++vcpu->stat.req_event; 10647 r = kvm_apic_accept_events(vcpu); 10648 if (r < 0) { 10649 r = 0; 10650 goto out; 10651 } 10652 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 10653 r = 1; 10654 goto out; 10655 } 10656 10657 r = kvm_check_and_inject_events(vcpu, &req_immediate_exit); 10658 if (r < 0) { 10659 r = 0; 10660 goto out; 10661 } 10662 if (req_int_win) 10663 static_call(kvm_x86_enable_irq_window)(vcpu); 10664 10665 if (kvm_lapic_enabled(vcpu)) { 10666 update_cr8_intercept(vcpu); 10667 kvm_lapic_sync_to_vapic(vcpu); 10668 } 10669 } 10670 10671 r = kvm_mmu_reload(vcpu); 10672 if (unlikely(r)) { 10673 goto cancel_injection; 10674 } 10675 10676 preempt_disable(); 10677 10678 static_call(kvm_x86_prepare_switch_to_guest)(vcpu); 10679 10680 /* 10681 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt 10682 * IPI are then delayed after guest entry, which ensures that they 10683 * result in virtual interrupt delivery. 10684 */ 10685 local_irq_disable(); 10686 10687 /* Store vcpu->apicv_active before vcpu->mode. */ 10688 smp_store_release(&vcpu->mode, IN_GUEST_MODE); 10689 10690 kvm_vcpu_srcu_read_unlock(vcpu); 10691 10692 /* 10693 * 1) We should set ->mode before checking ->requests. Please see 10694 * the comment in kvm_vcpu_exiting_guest_mode(). 10695 * 10696 * 2) For APICv, we should set ->mode before checking PID.ON. This 10697 * pairs with the memory barrier implicit in pi_test_and_set_on 10698 * (see vmx_deliver_posted_interrupt). 10699 * 10700 * 3) This also orders the write to mode from any reads to the page 10701 * tables done while the VCPU is running. Please see the comment 10702 * in kvm_flush_remote_tlbs. 10703 */ 10704 smp_mb__after_srcu_read_unlock(); 10705 10706 /* 10707 * Process pending posted interrupts to handle the case where the 10708 * notification IRQ arrived in the host, or was never sent (because the 10709 * target vCPU wasn't running). Do this regardless of the vCPU's APICv 10710 * status, KVM doesn't update assigned devices when APICv is inhibited, 10711 * i.e. they can post interrupts even if APICv is temporarily disabled. 10712 */ 10713 if (kvm_lapic_enabled(vcpu)) 10714 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 10715 10716 if (kvm_vcpu_exit_request(vcpu)) { 10717 vcpu->mode = OUTSIDE_GUEST_MODE; 10718 smp_wmb(); 10719 local_irq_enable(); 10720 preempt_enable(); 10721 kvm_vcpu_srcu_read_lock(vcpu); 10722 r = 1; 10723 goto cancel_injection; 10724 } 10725 10726 if (req_immediate_exit) { 10727 kvm_make_request(KVM_REQ_EVENT, vcpu); 10728 static_call(kvm_x86_request_immediate_exit)(vcpu); 10729 } 10730 10731 fpregs_assert_state_consistent(); 10732 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 10733 switch_fpu_return(); 10734 10735 if (vcpu->arch.guest_fpu.xfd_err) 10736 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err); 10737 10738 if (unlikely(vcpu->arch.switch_db_regs)) { 10739 set_debugreg(0, 7); 10740 set_debugreg(vcpu->arch.eff_db[0], 0); 10741 set_debugreg(vcpu->arch.eff_db[1], 1); 10742 set_debugreg(vcpu->arch.eff_db[2], 2); 10743 set_debugreg(vcpu->arch.eff_db[3], 3); 10744 } else if (unlikely(hw_breakpoint_active())) { 10745 set_debugreg(0, 7); 10746 } 10747 10748 guest_timing_enter_irqoff(); 10749 10750 for (;;) { 10751 /* 10752 * Assert that vCPU vs. VM APICv state is consistent. An APICv 10753 * update must kick and wait for all vCPUs before toggling the 10754 * per-VM state, and responsing vCPUs must wait for the update 10755 * to complete before servicing KVM_REQ_APICV_UPDATE. 10756 */ 10757 WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) && 10758 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED)); 10759 10760 exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu); 10761 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) 10762 break; 10763 10764 if (kvm_lapic_enabled(vcpu)) 10765 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); 10766 10767 if (unlikely(kvm_vcpu_exit_request(vcpu))) { 10768 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; 10769 break; 10770 } 10771 10772 /* Note, VM-Exits that go down the "slow" path are accounted below. */ 10773 ++vcpu->stat.exits; 10774 } 10775 10776 /* 10777 * Do this here before restoring debug registers on the host. And 10778 * since we do this before handling the vmexit, a DR access vmexit 10779 * can (a) read the correct value of the debug registers, (b) set 10780 * KVM_DEBUGREG_WONT_EXIT again. 10781 */ 10782 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 10783 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 10784 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); 10785 kvm_update_dr0123(vcpu); 10786 kvm_update_dr7(vcpu); 10787 } 10788 10789 /* 10790 * If the guest has used debug registers, at least dr7 10791 * will be disabled while returning to the host. 10792 * If we don't have active breakpoints in the host, we don't 10793 * care about the messed up debug address registers. But if 10794 * we have some of them active, restore the old state. 10795 */ 10796 if (hw_breakpoint_active()) 10797 hw_breakpoint_restore(); 10798 10799 vcpu->arch.last_vmentry_cpu = vcpu->cpu; 10800 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); 10801 10802 vcpu->mode = OUTSIDE_GUEST_MODE; 10803 smp_wmb(); 10804 10805 /* 10806 * Sync xfd before calling handle_exit_irqoff() which may 10807 * rely on the fact that guest_fpu::xfd is up-to-date (e.g. 10808 * in #NM irqoff handler). 10809 */ 10810 if (vcpu->arch.xfd_no_write_intercept) 10811 fpu_sync_guest_vmexit_xfd_state(); 10812 10813 static_call(kvm_x86_handle_exit_irqoff)(vcpu); 10814 10815 if (vcpu->arch.guest_fpu.xfd_err) 10816 wrmsrl(MSR_IA32_XFD_ERR, 0); 10817 10818 /* 10819 * Consume any pending interrupts, including the possible source of 10820 * VM-Exit on SVM and any ticks that occur between VM-Exit and now. 10821 * An instruction is required after local_irq_enable() to fully unblock 10822 * interrupts on processors that implement an interrupt shadow, the 10823 * stat.exits increment will do nicely. 10824 */ 10825 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ); 10826 local_irq_enable(); 10827 ++vcpu->stat.exits; 10828 local_irq_disable(); 10829 kvm_after_interrupt(vcpu); 10830 10831 /* 10832 * Wait until after servicing IRQs to account guest time so that any 10833 * ticks that occurred while running the guest are properly accounted 10834 * to the guest. Waiting until IRQs are enabled degrades the accuracy 10835 * of accounting via context tracking, but the loss of accuracy is 10836 * acceptable for all known use cases. 10837 */ 10838 guest_timing_exit_irqoff(); 10839 10840 local_irq_enable(); 10841 preempt_enable(); 10842 10843 kvm_vcpu_srcu_read_lock(vcpu); 10844 10845 /* 10846 * Profile KVM exit RIPs: 10847 */ 10848 if (unlikely(prof_on == KVM_PROFILING)) { 10849 unsigned long rip = kvm_rip_read(vcpu); 10850 profile_hit(KVM_PROFILING, (void *)rip); 10851 } 10852 10853 if (unlikely(vcpu->arch.tsc_always_catchup)) 10854 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 10855 10856 if (vcpu->arch.apic_attention) 10857 kvm_lapic_sync_from_vapic(vcpu); 10858 10859 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); 10860 return r; 10861 10862 cancel_injection: 10863 if (req_immediate_exit) 10864 kvm_make_request(KVM_REQ_EVENT, vcpu); 10865 static_call(kvm_x86_cancel_injection)(vcpu); 10866 if (unlikely(vcpu->arch.apic_attention)) 10867 kvm_lapic_sync_from_vapic(vcpu); 10868 out: 10869 return r; 10870 } 10871 10872 /* Called within kvm->srcu read side. */ 10873 static inline int vcpu_block(struct kvm_vcpu *vcpu) 10874 { 10875 bool hv_timer; 10876 10877 if (!kvm_arch_vcpu_runnable(vcpu)) { 10878 /* 10879 * Switch to the software timer before halt-polling/blocking as 10880 * the guest's timer may be a break event for the vCPU, and the 10881 * hypervisor timer runs only when the CPU is in guest mode. 10882 * Switch before halt-polling so that KVM recognizes an expired 10883 * timer before blocking. 10884 */ 10885 hv_timer = kvm_lapic_hv_timer_in_use(vcpu); 10886 if (hv_timer) 10887 kvm_lapic_switch_to_sw_timer(vcpu); 10888 10889 kvm_vcpu_srcu_read_unlock(vcpu); 10890 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) 10891 kvm_vcpu_halt(vcpu); 10892 else 10893 kvm_vcpu_block(vcpu); 10894 kvm_vcpu_srcu_read_lock(vcpu); 10895 10896 if (hv_timer) 10897 kvm_lapic_switch_to_hv_timer(vcpu); 10898 10899 /* 10900 * If the vCPU is not runnable, a signal or another host event 10901 * of some kind is pending; service it without changing the 10902 * vCPU's activity state. 10903 */ 10904 if (!kvm_arch_vcpu_runnable(vcpu)) 10905 return 1; 10906 } 10907 10908 /* 10909 * Evaluate nested events before exiting the halted state. This allows 10910 * the halt state to be recorded properly in the VMCS12's activity 10911 * state field (AMD does not have a similar field and a VM-Exit always 10912 * causes a spurious wakeup from HLT). 10913 */ 10914 if (is_guest_mode(vcpu)) { 10915 if (kvm_check_nested_events(vcpu) < 0) 10916 return 0; 10917 } 10918 10919 if (kvm_apic_accept_events(vcpu) < 0) 10920 return 0; 10921 switch(vcpu->arch.mp_state) { 10922 case KVM_MP_STATE_HALTED: 10923 case KVM_MP_STATE_AP_RESET_HOLD: 10924 vcpu->arch.pv.pv_unhalted = false; 10925 vcpu->arch.mp_state = 10926 KVM_MP_STATE_RUNNABLE; 10927 fallthrough; 10928 case KVM_MP_STATE_RUNNABLE: 10929 vcpu->arch.apf.halted = false; 10930 break; 10931 case KVM_MP_STATE_INIT_RECEIVED: 10932 break; 10933 default: 10934 WARN_ON_ONCE(1); 10935 break; 10936 } 10937 return 1; 10938 } 10939 10940 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) 10941 { 10942 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 10943 !vcpu->arch.apf.halted); 10944 } 10945 10946 /* Called within kvm->srcu read side. */ 10947 static int vcpu_run(struct kvm_vcpu *vcpu) 10948 { 10949 int r; 10950 10951 vcpu->arch.l1tf_flush_l1d = true; 10952 10953 for (;;) { 10954 /* 10955 * If another guest vCPU requests a PV TLB flush in the middle 10956 * of instruction emulation, the rest of the emulation could 10957 * use a stale page translation. Assume that any code after 10958 * this point can start executing an instruction. 10959 */ 10960 vcpu->arch.at_instruction_boundary = false; 10961 if (kvm_vcpu_running(vcpu)) { 10962 r = vcpu_enter_guest(vcpu); 10963 } else { 10964 r = vcpu_block(vcpu); 10965 } 10966 10967 if (r <= 0) 10968 break; 10969 10970 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); 10971 if (kvm_xen_has_pending_events(vcpu)) 10972 kvm_xen_inject_pending_events(vcpu); 10973 10974 if (kvm_cpu_has_pending_timer(vcpu)) 10975 kvm_inject_pending_timer_irqs(vcpu); 10976 10977 if (dm_request_for_irq_injection(vcpu) && 10978 kvm_vcpu_ready_for_interrupt_injection(vcpu)) { 10979 r = 0; 10980 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; 10981 ++vcpu->stat.request_irq_exits; 10982 break; 10983 } 10984 10985 if (__xfer_to_guest_mode_work_pending()) { 10986 kvm_vcpu_srcu_read_unlock(vcpu); 10987 r = xfer_to_guest_mode_handle_work(vcpu); 10988 kvm_vcpu_srcu_read_lock(vcpu); 10989 if (r) 10990 return r; 10991 } 10992 } 10993 10994 return r; 10995 } 10996 10997 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 10998 { 10999 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 11000 } 11001 11002 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 11003 { 11004 BUG_ON(!vcpu->arch.pio.count); 11005 11006 return complete_emulated_io(vcpu); 11007 } 11008 11009 /* 11010 * Implements the following, as a state machine: 11011 * 11012 * read: 11013 * for each fragment 11014 * for each mmio piece in the fragment 11015 * write gpa, len 11016 * exit 11017 * copy data 11018 * execute insn 11019 * 11020 * write: 11021 * for each fragment 11022 * for each mmio piece in the fragment 11023 * write gpa, len 11024 * copy data 11025 * exit 11026 */ 11027 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 11028 { 11029 struct kvm_run *run = vcpu->run; 11030 struct kvm_mmio_fragment *frag; 11031 unsigned len; 11032 11033 BUG_ON(!vcpu->mmio_needed); 11034 11035 /* Complete previous fragment */ 11036 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 11037 len = min(8u, frag->len); 11038 if (!vcpu->mmio_is_write) 11039 memcpy(frag->data, run->mmio.data, len); 11040 11041 if (frag->len <= 8) { 11042 /* Switch to the next fragment. */ 11043 frag++; 11044 vcpu->mmio_cur_fragment++; 11045 } else { 11046 /* Go forward to the next mmio piece. */ 11047 frag->data += len; 11048 frag->gpa += len; 11049 frag->len -= len; 11050 } 11051 11052 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 11053 vcpu->mmio_needed = 0; 11054 11055 /* FIXME: return into emulator if single-stepping. */ 11056 if (vcpu->mmio_is_write) 11057 return 1; 11058 vcpu->mmio_read_completed = 1; 11059 return complete_emulated_io(vcpu); 11060 } 11061 11062 run->exit_reason = KVM_EXIT_MMIO; 11063 run->mmio.phys_addr = frag->gpa; 11064 if (vcpu->mmio_is_write) 11065 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 11066 run->mmio.len = min(8u, frag->len); 11067 run->mmio.is_write = vcpu->mmio_is_write; 11068 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 11069 return 0; 11070 } 11071 11072 /* Swap (qemu) user FPU context for the guest FPU context. */ 11073 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 11074 { 11075 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */ 11076 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true); 11077 trace_kvm_fpu(1); 11078 } 11079 11080 /* When vcpu_run ends, restore user space FPU context. */ 11081 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 11082 { 11083 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false); 11084 ++vcpu->stat.fpu_reload; 11085 trace_kvm_fpu(0); 11086 } 11087 11088 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 11089 { 11090 struct kvm_queued_exception *ex = &vcpu->arch.exception; 11091 struct kvm_run *kvm_run = vcpu->run; 11092 int r; 11093 11094 vcpu_load(vcpu); 11095 kvm_sigset_activate(vcpu); 11096 kvm_run->flags = 0; 11097 kvm_load_guest_fpu(vcpu); 11098 11099 kvm_vcpu_srcu_read_lock(vcpu); 11100 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 11101 if (kvm_run->immediate_exit) { 11102 r = -EINTR; 11103 goto out; 11104 } 11105 11106 /* 11107 * Don't bother switching APIC timer emulation from the 11108 * hypervisor timer to the software timer, the only way for the 11109 * APIC timer to be active is if userspace stuffed vCPU state, 11110 * i.e. put the vCPU into a nonsensical state. Only an INIT 11111 * will transition the vCPU out of UNINITIALIZED (without more 11112 * state stuffing from userspace), which will reset the local 11113 * APIC and thus cancel the timer or drop the IRQ (if the timer 11114 * already expired). 11115 */ 11116 kvm_vcpu_srcu_read_unlock(vcpu); 11117 kvm_vcpu_block(vcpu); 11118 kvm_vcpu_srcu_read_lock(vcpu); 11119 11120 if (kvm_apic_accept_events(vcpu) < 0) { 11121 r = 0; 11122 goto out; 11123 } 11124 r = -EAGAIN; 11125 if (signal_pending(current)) { 11126 r = -EINTR; 11127 kvm_run->exit_reason = KVM_EXIT_INTR; 11128 ++vcpu->stat.signal_exits; 11129 } 11130 goto out; 11131 } 11132 11133 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) || 11134 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) { 11135 r = -EINVAL; 11136 goto out; 11137 } 11138 11139 if (kvm_run->kvm_dirty_regs) { 11140 r = sync_regs(vcpu); 11141 if (r != 0) 11142 goto out; 11143 } 11144 11145 /* re-sync apic's tpr */ 11146 if (!lapic_in_kernel(vcpu)) { 11147 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 11148 r = -EINVAL; 11149 goto out; 11150 } 11151 } 11152 11153 /* 11154 * If userspace set a pending exception and L2 is active, convert it to 11155 * a pending VM-Exit if L1 wants to intercept the exception. 11156 */ 11157 if (vcpu->arch.exception_from_userspace && is_guest_mode(vcpu) && 11158 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, ex->vector, 11159 ex->error_code)) { 11160 kvm_queue_exception_vmexit(vcpu, ex->vector, 11161 ex->has_error_code, ex->error_code, 11162 ex->has_payload, ex->payload); 11163 ex->injected = false; 11164 ex->pending = false; 11165 } 11166 vcpu->arch.exception_from_userspace = false; 11167 11168 if (unlikely(vcpu->arch.complete_userspace_io)) { 11169 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 11170 vcpu->arch.complete_userspace_io = NULL; 11171 r = cui(vcpu); 11172 if (r <= 0) 11173 goto out; 11174 } else { 11175 WARN_ON_ONCE(vcpu->arch.pio.count); 11176 WARN_ON_ONCE(vcpu->mmio_needed); 11177 } 11178 11179 if (kvm_run->immediate_exit) { 11180 r = -EINTR; 11181 goto out; 11182 } 11183 11184 r = static_call(kvm_x86_vcpu_pre_run)(vcpu); 11185 if (r <= 0) 11186 goto out; 11187 11188 r = vcpu_run(vcpu); 11189 11190 out: 11191 kvm_put_guest_fpu(vcpu); 11192 if (kvm_run->kvm_valid_regs) 11193 store_regs(vcpu); 11194 post_kvm_run_save(vcpu); 11195 kvm_vcpu_srcu_read_unlock(vcpu); 11196 11197 kvm_sigset_deactivate(vcpu); 11198 vcpu_put(vcpu); 11199 return r; 11200 } 11201 11202 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 11203 { 11204 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 11205 /* 11206 * We are here if userspace calls get_regs() in the middle of 11207 * instruction emulation. Registers state needs to be copied 11208 * back from emulation context to vcpu. Userspace shouldn't do 11209 * that usually, but some bad designed PV devices (vmware 11210 * backdoor interface) need this to work 11211 */ 11212 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); 11213 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 11214 } 11215 regs->rax = kvm_rax_read(vcpu); 11216 regs->rbx = kvm_rbx_read(vcpu); 11217 regs->rcx = kvm_rcx_read(vcpu); 11218 regs->rdx = kvm_rdx_read(vcpu); 11219 regs->rsi = kvm_rsi_read(vcpu); 11220 regs->rdi = kvm_rdi_read(vcpu); 11221 regs->rsp = kvm_rsp_read(vcpu); 11222 regs->rbp = kvm_rbp_read(vcpu); 11223 #ifdef CONFIG_X86_64 11224 regs->r8 = kvm_r8_read(vcpu); 11225 regs->r9 = kvm_r9_read(vcpu); 11226 regs->r10 = kvm_r10_read(vcpu); 11227 regs->r11 = kvm_r11_read(vcpu); 11228 regs->r12 = kvm_r12_read(vcpu); 11229 regs->r13 = kvm_r13_read(vcpu); 11230 regs->r14 = kvm_r14_read(vcpu); 11231 regs->r15 = kvm_r15_read(vcpu); 11232 #endif 11233 11234 regs->rip = kvm_rip_read(vcpu); 11235 regs->rflags = kvm_get_rflags(vcpu); 11236 } 11237 11238 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 11239 { 11240 vcpu_load(vcpu); 11241 __get_regs(vcpu, regs); 11242 vcpu_put(vcpu); 11243 return 0; 11244 } 11245 11246 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 11247 { 11248 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 11249 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 11250 11251 kvm_rax_write(vcpu, regs->rax); 11252 kvm_rbx_write(vcpu, regs->rbx); 11253 kvm_rcx_write(vcpu, regs->rcx); 11254 kvm_rdx_write(vcpu, regs->rdx); 11255 kvm_rsi_write(vcpu, regs->rsi); 11256 kvm_rdi_write(vcpu, regs->rdi); 11257 kvm_rsp_write(vcpu, regs->rsp); 11258 kvm_rbp_write(vcpu, regs->rbp); 11259 #ifdef CONFIG_X86_64 11260 kvm_r8_write(vcpu, regs->r8); 11261 kvm_r9_write(vcpu, regs->r9); 11262 kvm_r10_write(vcpu, regs->r10); 11263 kvm_r11_write(vcpu, regs->r11); 11264 kvm_r12_write(vcpu, regs->r12); 11265 kvm_r13_write(vcpu, regs->r13); 11266 kvm_r14_write(vcpu, regs->r14); 11267 kvm_r15_write(vcpu, regs->r15); 11268 #endif 11269 11270 kvm_rip_write(vcpu, regs->rip); 11271 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); 11272 11273 vcpu->arch.exception.pending = false; 11274 vcpu->arch.exception_vmexit.pending = false; 11275 11276 kvm_make_request(KVM_REQ_EVENT, vcpu); 11277 } 11278 11279 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 11280 { 11281 vcpu_load(vcpu); 11282 __set_regs(vcpu, regs); 11283 vcpu_put(vcpu); 11284 return 0; 11285 } 11286 11287 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 11288 { 11289 struct desc_ptr dt; 11290 11291 if (vcpu->arch.guest_state_protected) 11292 goto skip_protected_regs; 11293 11294 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 11295 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 11296 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 11297 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 11298 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 11299 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 11300 11301 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 11302 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 11303 11304 static_call(kvm_x86_get_idt)(vcpu, &dt); 11305 sregs->idt.limit = dt.size; 11306 sregs->idt.base = dt.address; 11307 static_call(kvm_x86_get_gdt)(vcpu, &dt); 11308 sregs->gdt.limit = dt.size; 11309 sregs->gdt.base = dt.address; 11310 11311 sregs->cr2 = vcpu->arch.cr2; 11312 sregs->cr3 = kvm_read_cr3(vcpu); 11313 11314 skip_protected_regs: 11315 sregs->cr0 = kvm_read_cr0(vcpu); 11316 sregs->cr4 = kvm_read_cr4(vcpu); 11317 sregs->cr8 = kvm_get_cr8(vcpu); 11318 sregs->efer = vcpu->arch.efer; 11319 sregs->apic_base = kvm_get_apic_base(vcpu); 11320 } 11321 11322 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 11323 { 11324 __get_sregs_common(vcpu, sregs); 11325 11326 if (vcpu->arch.guest_state_protected) 11327 return; 11328 11329 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) 11330 set_bit(vcpu->arch.interrupt.nr, 11331 (unsigned long *)sregs->interrupt_bitmap); 11332 } 11333 11334 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 11335 { 11336 int i; 11337 11338 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2); 11339 11340 if (vcpu->arch.guest_state_protected) 11341 return; 11342 11343 if (is_pae_paging(vcpu)) { 11344 for (i = 0 ; i < 4 ; i++) 11345 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i); 11346 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; 11347 } 11348 } 11349 11350 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 11351 struct kvm_sregs *sregs) 11352 { 11353 vcpu_load(vcpu); 11354 __get_sregs(vcpu, sregs); 11355 vcpu_put(vcpu); 11356 return 0; 11357 } 11358 11359 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 11360 struct kvm_mp_state *mp_state) 11361 { 11362 int r; 11363 11364 vcpu_load(vcpu); 11365 if (kvm_mpx_supported()) 11366 kvm_load_guest_fpu(vcpu); 11367 11368 r = kvm_apic_accept_events(vcpu); 11369 if (r < 0) 11370 goto out; 11371 r = 0; 11372 11373 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || 11374 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && 11375 vcpu->arch.pv.pv_unhalted) 11376 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 11377 else 11378 mp_state->mp_state = vcpu->arch.mp_state; 11379 11380 out: 11381 if (kvm_mpx_supported()) 11382 kvm_put_guest_fpu(vcpu); 11383 vcpu_put(vcpu); 11384 return r; 11385 } 11386 11387 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 11388 struct kvm_mp_state *mp_state) 11389 { 11390 int ret = -EINVAL; 11391 11392 vcpu_load(vcpu); 11393 11394 switch (mp_state->mp_state) { 11395 case KVM_MP_STATE_UNINITIALIZED: 11396 case KVM_MP_STATE_HALTED: 11397 case KVM_MP_STATE_AP_RESET_HOLD: 11398 case KVM_MP_STATE_INIT_RECEIVED: 11399 case KVM_MP_STATE_SIPI_RECEIVED: 11400 if (!lapic_in_kernel(vcpu)) 11401 goto out; 11402 break; 11403 11404 case KVM_MP_STATE_RUNNABLE: 11405 break; 11406 11407 default: 11408 goto out; 11409 } 11410 11411 /* 11412 * Pending INITs are reported using KVM_SET_VCPU_EVENTS, disallow 11413 * forcing the guest into INIT/SIPI if those events are supposed to be 11414 * blocked. KVM prioritizes SMI over INIT, so reject INIT/SIPI state 11415 * if an SMI is pending as well. 11416 */ 11417 if ((!kvm_apic_init_sipi_allowed(vcpu) || vcpu->arch.smi_pending) && 11418 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || 11419 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) 11420 goto out; 11421 11422 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 11423 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 11424 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 11425 } else 11426 vcpu->arch.mp_state = mp_state->mp_state; 11427 kvm_make_request(KVM_REQ_EVENT, vcpu); 11428 11429 ret = 0; 11430 out: 11431 vcpu_put(vcpu); 11432 return ret; 11433 } 11434 11435 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 11436 int reason, bool has_error_code, u32 error_code) 11437 { 11438 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; 11439 int ret; 11440 11441 init_emulate_ctxt(vcpu); 11442 11443 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 11444 has_error_code, error_code); 11445 if (ret) { 11446 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 11447 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 11448 vcpu->run->internal.ndata = 0; 11449 return 0; 11450 } 11451 11452 kvm_rip_write(vcpu, ctxt->eip); 11453 kvm_set_rflags(vcpu, ctxt->eflags); 11454 return 1; 11455 } 11456 EXPORT_SYMBOL_GPL(kvm_task_switch); 11457 11458 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 11459 { 11460 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { 11461 /* 11462 * When EFER.LME and CR0.PG are set, the processor is in 11463 * 64-bit mode (though maybe in a 32-bit code segment). 11464 * CR4.PAE and EFER.LMA must be set. 11465 */ 11466 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) 11467 return false; 11468 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) 11469 return false; 11470 } else { 11471 /* 11472 * Not in 64-bit mode: EFER.LMA is clear and the code 11473 * segment cannot be 64-bit. 11474 */ 11475 if (sregs->efer & EFER_LMA || sregs->cs.l) 11476 return false; 11477 } 11478 11479 return kvm_is_valid_cr4(vcpu, sregs->cr4) && 11480 kvm_is_valid_cr0(vcpu, sregs->cr0); 11481 } 11482 11483 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs, 11484 int *mmu_reset_needed, bool update_pdptrs) 11485 { 11486 struct msr_data apic_base_msr; 11487 int idx; 11488 struct desc_ptr dt; 11489 11490 if (!kvm_is_valid_sregs(vcpu, sregs)) 11491 return -EINVAL; 11492 11493 apic_base_msr.data = sregs->apic_base; 11494 apic_base_msr.host_initiated = true; 11495 if (kvm_set_apic_base(vcpu, &apic_base_msr)) 11496 return -EINVAL; 11497 11498 if (vcpu->arch.guest_state_protected) 11499 return 0; 11500 11501 dt.size = sregs->idt.limit; 11502 dt.address = sregs->idt.base; 11503 static_call(kvm_x86_set_idt)(vcpu, &dt); 11504 dt.size = sregs->gdt.limit; 11505 dt.address = sregs->gdt.base; 11506 static_call(kvm_x86_set_gdt)(vcpu, &dt); 11507 11508 vcpu->arch.cr2 = sregs->cr2; 11509 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 11510 vcpu->arch.cr3 = sregs->cr3; 11511 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 11512 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3); 11513 11514 kvm_set_cr8(vcpu, sregs->cr8); 11515 11516 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 11517 static_call(kvm_x86_set_efer)(vcpu, sregs->efer); 11518 11519 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 11520 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); 11521 vcpu->arch.cr0 = sregs->cr0; 11522 11523 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 11524 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); 11525 11526 if (update_pdptrs) { 11527 idx = srcu_read_lock(&vcpu->kvm->srcu); 11528 if (is_pae_paging(vcpu)) { 11529 load_pdptrs(vcpu, kvm_read_cr3(vcpu)); 11530 *mmu_reset_needed = 1; 11531 } 11532 srcu_read_unlock(&vcpu->kvm->srcu, idx); 11533 } 11534 11535 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 11536 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 11537 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 11538 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 11539 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 11540 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 11541 11542 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 11543 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 11544 11545 update_cr8_intercept(vcpu); 11546 11547 /* Older userspace won't unhalt the vcpu on reset. */ 11548 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 11549 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 11550 !is_protmode(vcpu)) 11551 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 11552 11553 return 0; 11554 } 11555 11556 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 11557 { 11558 int pending_vec, max_bits; 11559 int mmu_reset_needed = 0; 11560 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true); 11561 11562 if (ret) 11563 return ret; 11564 11565 if (mmu_reset_needed) 11566 kvm_mmu_reset_context(vcpu); 11567 11568 max_bits = KVM_NR_INTERRUPTS; 11569 pending_vec = find_first_bit( 11570 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 11571 11572 if (pending_vec < max_bits) { 11573 kvm_queue_interrupt(vcpu, pending_vec, false); 11574 pr_debug("Set back pending irq %d\n", pending_vec); 11575 kvm_make_request(KVM_REQ_EVENT, vcpu); 11576 } 11577 return 0; 11578 } 11579 11580 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) 11581 { 11582 int mmu_reset_needed = 0; 11583 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; 11584 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) && 11585 !(sregs2->efer & EFER_LMA); 11586 int i, ret; 11587 11588 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID) 11589 return -EINVAL; 11590 11591 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected)) 11592 return -EINVAL; 11593 11594 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2, 11595 &mmu_reset_needed, !valid_pdptrs); 11596 if (ret) 11597 return ret; 11598 11599 if (valid_pdptrs) { 11600 for (i = 0; i < 4 ; i++) 11601 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]); 11602 11603 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 11604 mmu_reset_needed = 1; 11605 vcpu->arch.pdptrs_from_userspace = true; 11606 } 11607 if (mmu_reset_needed) 11608 kvm_mmu_reset_context(vcpu); 11609 return 0; 11610 } 11611 11612 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 11613 struct kvm_sregs *sregs) 11614 { 11615 int ret; 11616 11617 vcpu_load(vcpu); 11618 ret = __set_sregs(vcpu, sregs); 11619 vcpu_put(vcpu); 11620 return ret; 11621 } 11622 11623 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm) 11624 { 11625 bool set = false; 11626 struct kvm_vcpu *vcpu; 11627 unsigned long i; 11628 11629 if (!enable_apicv) 11630 return; 11631 11632 down_write(&kvm->arch.apicv_update_lock); 11633 11634 kvm_for_each_vcpu(i, vcpu, kvm) { 11635 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) { 11636 set = true; 11637 break; 11638 } 11639 } 11640 __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set); 11641 up_write(&kvm->arch.apicv_update_lock); 11642 } 11643 11644 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 11645 struct kvm_guest_debug *dbg) 11646 { 11647 unsigned long rflags; 11648 int i, r; 11649 11650 if (vcpu->arch.guest_state_protected) 11651 return -EINVAL; 11652 11653 vcpu_load(vcpu); 11654 11655 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 11656 r = -EBUSY; 11657 if (kvm_is_exception_pending(vcpu)) 11658 goto out; 11659 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 11660 kvm_queue_exception(vcpu, DB_VECTOR); 11661 else 11662 kvm_queue_exception(vcpu, BP_VECTOR); 11663 } 11664 11665 /* 11666 * Read rflags as long as potentially injected trace flags are still 11667 * filtered out. 11668 */ 11669 rflags = kvm_get_rflags(vcpu); 11670 11671 vcpu->guest_debug = dbg->control; 11672 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 11673 vcpu->guest_debug = 0; 11674 11675 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 11676 for (i = 0; i < KVM_NR_DB_REGS; ++i) 11677 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 11678 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 11679 } else { 11680 for (i = 0; i < KVM_NR_DB_REGS; i++) 11681 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 11682 } 11683 kvm_update_dr7(vcpu); 11684 11685 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 11686 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); 11687 11688 /* 11689 * Trigger an rflags update that will inject or remove the trace 11690 * flags. 11691 */ 11692 kvm_set_rflags(vcpu, rflags); 11693 11694 static_call(kvm_x86_update_exception_bitmap)(vcpu); 11695 11696 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm); 11697 11698 r = 0; 11699 11700 out: 11701 vcpu_put(vcpu); 11702 return r; 11703 } 11704 11705 /* 11706 * Translate a guest virtual address to a guest physical address. 11707 */ 11708 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 11709 struct kvm_translation *tr) 11710 { 11711 unsigned long vaddr = tr->linear_address; 11712 gpa_t gpa; 11713 int idx; 11714 11715 vcpu_load(vcpu); 11716 11717 idx = srcu_read_lock(&vcpu->kvm->srcu); 11718 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 11719 srcu_read_unlock(&vcpu->kvm->srcu, idx); 11720 tr->physical_address = gpa; 11721 tr->valid = gpa != INVALID_GPA; 11722 tr->writeable = 1; 11723 tr->usermode = 0; 11724 11725 vcpu_put(vcpu); 11726 return 0; 11727 } 11728 11729 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 11730 { 11731 struct fxregs_state *fxsave; 11732 11733 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 11734 return 0; 11735 11736 vcpu_load(vcpu); 11737 11738 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 11739 memcpy(fpu->fpr, fxsave->st_space, 128); 11740 fpu->fcw = fxsave->cwd; 11741 fpu->fsw = fxsave->swd; 11742 fpu->ftwx = fxsave->twd; 11743 fpu->last_opcode = fxsave->fop; 11744 fpu->last_ip = fxsave->rip; 11745 fpu->last_dp = fxsave->rdp; 11746 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); 11747 11748 vcpu_put(vcpu); 11749 return 0; 11750 } 11751 11752 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 11753 { 11754 struct fxregs_state *fxsave; 11755 11756 if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) 11757 return 0; 11758 11759 vcpu_load(vcpu); 11760 11761 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; 11762 11763 memcpy(fxsave->st_space, fpu->fpr, 128); 11764 fxsave->cwd = fpu->fcw; 11765 fxsave->swd = fpu->fsw; 11766 fxsave->twd = fpu->ftwx; 11767 fxsave->fop = fpu->last_opcode; 11768 fxsave->rip = fpu->last_ip; 11769 fxsave->rdp = fpu->last_dp; 11770 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); 11771 11772 vcpu_put(vcpu); 11773 return 0; 11774 } 11775 11776 static void store_regs(struct kvm_vcpu *vcpu) 11777 { 11778 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); 11779 11780 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) 11781 __get_regs(vcpu, &vcpu->run->s.regs.regs); 11782 11783 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) 11784 __get_sregs(vcpu, &vcpu->run->s.regs.sregs); 11785 11786 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) 11787 kvm_vcpu_ioctl_x86_get_vcpu_events( 11788 vcpu, &vcpu->run->s.regs.events); 11789 } 11790 11791 static int sync_regs(struct kvm_vcpu *vcpu) 11792 { 11793 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { 11794 __set_regs(vcpu, &vcpu->run->s.regs.regs); 11795 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; 11796 } 11797 11798 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { 11799 struct kvm_sregs sregs = vcpu->run->s.regs.sregs; 11800 11801 if (__set_sregs(vcpu, &sregs)) 11802 return -EINVAL; 11803 11804 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; 11805 } 11806 11807 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { 11808 struct kvm_vcpu_events events = vcpu->run->s.regs.events; 11809 11810 if (kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events)) 11811 return -EINVAL; 11812 11813 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; 11814 } 11815 11816 return 0; 11817 } 11818 11819 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 11820 { 11821 if (kvm_check_tsc_unstable() && kvm->created_vcpus) 11822 pr_warn_once("SMP vm created on host with unstable TSC; " 11823 "guest TSC will not be reliable\n"); 11824 11825 if (!kvm->arch.max_vcpu_ids) 11826 kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS; 11827 11828 if (id >= kvm->arch.max_vcpu_ids) 11829 return -EINVAL; 11830 11831 return static_call(kvm_x86_vcpu_precreate)(kvm); 11832 } 11833 11834 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 11835 { 11836 struct page *page; 11837 int r; 11838 11839 vcpu->arch.last_vmentry_cpu = -1; 11840 vcpu->arch.regs_avail = ~0; 11841 vcpu->arch.regs_dirty = ~0; 11842 11843 kvm_gpc_init(&vcpu->arch.pv_time, vcpu->kvm, vcpu, KVM_HOST_USES_PFN); 11844 11845 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) 11846 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 11847 else 11848 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 11849 11850 r = kvm_mmu_create(vcpu); 11851 if (r < 0) 11852 return r; 11853 11854 if (irqchip_in_kernel(vcpu->kvm)) { 11855 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); 11856 if (r < 0) 11857 goto fail_mmu_destroy; 11858 11859 /* 11860 * Defer evaluating inhibits until the vCPU is first run, as 11861 * this vCPU will not get notified of any changes until this 11862 * vCPU is visible to other vCPUs (marked online and added to 11863 * the set of vCPUs). Opportunistically mark APICv active as 11864 * VMX in particularly is highly unlikely to have inhibits. 11865 * Ignore the current per-VM APICv state so that vCPU creation 11866 * is guaranteed to run with a deterministic value, the request 11867 * will ensure the vCPU gets the correct state before VM-Entry. 11868 */ 11869 if (enable_apicv) { 11870 vcpu->arch.apic->apicv_active = true; 11871 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu); 11872 } 11873 } else 11874 static_branch_inc(&kvm_has_noapic_vcpu); 11875 11876 r = -ENOMEM; 11877 11878 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 11879 if (!page) 11880 goto fail_free_lapic; 11881 vcpu->arch.pio_data = page_address(page); 11882 11883 vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64), 11884 GFP_KERNEL_ACCOUNT); 11885 vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64), 11886 GFP_KERNEL_ACCOUNT); 11887 if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks) 11888 goto fail_free_mce_banks; 11889 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 11890 11891 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, 11892 GFP_KERNEL_ACCOUNT)) 11893 goto fail_free_mce_banks; 11894 11895 if (!alloc_emulate_ctxt(vcpu)) 11896 goto free_wbinvd_dirty_mask; 11897 11898 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) { 11899 pr_err("failed to allocate vcpu's fpu\n"); 11900 goto free_emulate_ctxt; 11901 } 11902 11903 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 11904 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 11905 11906 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; 11907 11908 kvm_async_pf_hash_reset(vcpu); 11909 11910 vcpu->arch.perf_capabilities = kvm_caps.supported_perf_cap; 11911 kvm_pmu_init(vcpu); 11912 11913 vcpu->arch.pending_external_vector = -1; 11914 vcpu->arch.preempted_in_kernel = false; 11915 11916 #if IS_ENABLED(CONFIG_HYPERV) 11917 vcpu->arch.hv_root_tdp = INVALID_PAGE; 11918 #endif 11919 11920 r = static_call(kvm_x86_vcpu_create)(vcpu); 11921 if (r) 11922 goto free_guest_fpu; 11923 11924 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); 11925 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; 11926 kvm_xen_init_vcpu(vcpu); 11927 kvm_vcpu_mtrr_init(vcpu); 11928 vcpu_load(vcpu); 11929 kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz); 11930 kvm_vcpu_reset(vcpu, false); 11931 kvm_init_mmu(vcpu); 11932 vcpu_put(vcpu); 11933 return 0; 11934 11935 free_guest_fpu: 11936 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 11937 free_emulate_ctxt: 11938 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 11939 free_wbinvd_dirty_mask: 11940 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 11941 fail_free_mce_banks: 11942 kfree(vcpu->arch.mce_banks); 11943 kfree(vcpu->arch.mci_ctl2_banks); 11944 free_page((unsigned long)vcpu->arch.pio_data); 11945 fail_free_lapic: 11946 kvm_free_lapic(vcpu); 11947 fail_mmu_destroy: 11948 kvm_mmu_destroy(vcpu); 11949 return r; 11950 } 11951 11952 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 11953 { 11954 struct kvm *kvm = vcpu->kvm; 11955 11956 if (mutex_lock_killable(&vcpu->mutex)) 11957 return; 11958 vcpu_load(vcpu); 11959 kvm_synchronize_tsc(vcpu, 0); 11960 vcpu_put(vcpu); 11961 11962 /* poll control enabled by default */ 11963 vcpu->arch.msr_kvm_poll_control = 1; 11964 11965 mutex_unlock(&vcpu->mutex); 11966 11967 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) 11968 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 11969 KVMCLOCK_SYNC_PERIOD); 11970 } 11971 11972 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 11973 { 11974 int idx; 11975 11976 kvmclock_reset(vcpu); 11977 11978 static_call(kvm_x86_vcpu_free)(vcpu); 11979 11980 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); 11981 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 11982 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); 11983 11984 kvm_xen_destroy_vcpu(vcpu); 11985 kvm_hv_vcpu_uninit(vcpu); 11986 kvm_pmu_destroy(vcpu); 11987 kfree(vcpu->arch.mce_banks); 11988 kfree(vcpu->arch.mci_ctl2_banks); 11989 kvm_free_lapic(vcpu); 11990 idx = srcu_read_lock(&vcpu->kvm->srcu); 11991 kvm_mmu_destroy(vcpu); 11992 srcu_read_unlock(&vcpu->kvm->srcu, idx); 11993 free_page((unsigned long)vcpu->arch.pio_data); 11994 kvfree(vcpu->arch.cpuid_entries); 11995 if (!lapic_in_kernel(vcpu)) 11996 static_branch_dec(&kvm_has_noapic_vcpu); 11997 } 11998 11999 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 12000 { 12001 struct kvm_cpuid_entry2 *cpuid_0x1; 12002 unsigned long old_cr0 = kvm_read_cr0(vcpu); 12003 unsigned long new_cr0; 12004 12005 /* 12006 * Several of the "set" flows, e.g. ->set_cr0(), read other registers 12007 * to handle side effects. RESET emulation hits those flows and relies 12008 * on emulated/virtualized registers, including those that are loaded 12009 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel 12010 * to detect improper or missing initialization. 12011 */ 12012 WARN_ON_ONCE(!init_event && 12013 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu))); 12014 12015 /* 12016 * SVM doesn't unconditionally VM-Exit on INIT and SHUTDOWN, thus it's 12017 * possible to INIT the vCPU while L2 is active. Force the vCPU back 12018 * into L1 as EFER.SVME is cleared on INIT (along with all other EFER 12019 * bits), i.e. virtualization is disabled. 12020 */ 12021 if (is_guest_mode(vcpu)) 12022 kvm_leave_nested(vcpu); 12023 12024 kvm_lapic_reset(vcpu, init_event); 12025 12026 WARN_ON_ONCE(is_guest_mode(vcpu) || is_smm(vcpu)); 12027 vcpu->arch.hflags = 0; 12028 12029 vcpu->arch.smi_pending = 0; 12030 vcpu->arch.smi_count = 0; 12031 atomic_set(&vcpu->arch.nmi_queued, 0); 12032 vcpu->arch.nmi_pending = 0; 12033 vcpu->arch.nmi_injected = false; 12034 kvm_clear_interrupt_queue(vcpu); 12035 kvm_clear_exception_queue(vcpu); 12036 12037 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 12038 kvm_update_dr0123(vcpu); 12039 vcpu->arch.dr6 = DR6_ACTIVE_LOW; 12040 vcpu->arch.dr7 = DR7_FIXED_1; 12041 kvm_update_dr7(vcpu); 12042 12043 vcpu->arch.cr2 = 0; 12044 12045 kvm_make_request(KVM_REQ_EVENT, vcpu); 12046 vcpu->arch.apf.msr_en_val = 0; 12047 vcpu->arch.apf.msr_int_val = 0; 12048 vcpu->arch.st.msr_val = 0; 12049 12050 kvmclock_reset(vcpu); 12051 12052 kvm_clear_async_pf_completion_queue(vcpu); 12053 kvm_async_pf_hash_reset(vcpu); 12054 vcpu->arch.apf.halted = false; 12055 12056 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) { 12057 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate; 12058 12059 /* 12060 * All paths that lead to INIT are required to load the guest's 12061 * FPU state (because most paths are buried in KVM_RUN). 12062 */ 12063 if (init_event) 12064 kvm_put_guest_fpu(vcpu); 12065 12066 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS); 12067 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR); 12068 12069 if (init_event) 12070 kvm_load_guest_fpu(vcpu); 12071 } 12072 12073 if (!init_event) { 12074 kvm_pmu_reset(vcpu); 12075 vcpu->arch.smbase = 0x30000; 12076 12077 vcpu->arch.msr_misc_features_enables = 0; 12078 vcpu->arch.ia32_misc_enable_msr = MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL | 12079 MSR_IA32_MISC_ENABLE_BTS_UNAVAIL; 12080 12081 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP); 12082 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true); 12083 } 12084 12085 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */ 12086 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 12087 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP); 12088 12089 /* 12090 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon) 12091 * if no CPUID match is found. Note, it's impossible to get a match at 12092 * RESET since KVM emulates RESET before exposing the vCPU to userspace, 12093 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry 12094 * on RESET. But, go through the motions in case that's ever remedied. 12095 */ 12096 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1); 12097 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600); 12098 12099 static_call(kvm_x86_vcpu_reset)(vcpu, init_event); 12100 12101 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 12102 kvm_rip_write(vcpu, 0xfff0); 12103 12104 vcpu->arch.cr3 = 0; 12105 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); 12106 12107 /* 12108 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions 12109 * of Intel's SDM list CD/NW as being set on INIT, but they contradict 12110 * (or qualify) that with a footnote stating that CD/NW are preserved. 12111 */ 12112 new_cr0 = X86_CR0_ET; 12113 if (init_event) 12114 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD)); 12115 else 12116 new_cr0 |= X86_CR0_NW | X86_CR0_CD; 12117 12118 static_call(kvm_x86_set_cr0)(vcpu, new_cr0); 12119 static_call(kvm_x86_set_cr4)(vcpu, 0); 12120 static_call(kvm_x86_set_efer)(vcpu, 0); 12121 static_call(kvm_x86_update_exception_bitmap)(vcpu); 12122 12123 /* 12124 * On the standard CR0/CR4/EFER modification paths, there are several 12125 * complex conditions determining whether the MMU has to be reset and/or 12126 * which PCIDs have to be flushed. However, CR0.WP and the paging-related 12127 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush 12128 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as 12129 * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here. 12130 */ 12131 if (old_cr0 & X86_CR0_PG) { 12132 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 12133 kvm_mmu_reset_context(vcpu); 12134 } 12135 12136 /* 12137 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's 12138 * APM states the TLBs are untouched by INIT, but it also states that 12139 * the TLBs are flushed on "External initialization of the processor." 12140 * Flush the guest TLB regardless of vendor, there is no meaningful 12141 * benefit in relying on the guest to flush the TLB immediately after 12142 * INIT. A spurious TLB flush is benign and likely negligible from a 12143 * performance perspective. 12144 */ 12145 if (init_event) 12146 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 12147 } 12148 EXPORT_SYMBOL_GPL(kvm_vcpu_reset); 12149 12150 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) 12151 { 12152 struct kvm_segment cs; 12153 12154 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 12155 cs.selector = vector << 8; 12156 cs.base = vector << 12; 12157 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 12158 kvm_rip_write(vcpu, 0); 12159 } 12160 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); 12161 12162 int kvm_arch_hardware_enable(void) 12163 { 12164 struct kvm *kvm; 12165 struct kvm_vcpu *vcpu; 12166 unsigned long i; 12167 int ret; 12168 u64 local_tsc; 12169 u64 max_tsc = 0; 12170 bool stable, backwards_tsc = false; 12171 12172 kvm_user_return_msr_cpu_online(); 12173 12174 ret = kvm_x86_check_processor_compatibility(); 12175 if (ret) 12176 return ret; 12177 12178 ret = static_call(kvm_x86_hardware_enable)(); 12179 if (ret != 0) 12180 return ret; 12181 12182 local_tsc = rdtsc(); 12183 stable = !kvm_check_tsc_unstable(); 12184 list_for_each_entry(kvm, &vm_list, vm_list) { 12185 kvm_for_each_vcpu(i, vcpu, kvm) { 12186 if (!stable && vcpu->cpu == smp_processor_id()) 12187 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 12188 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 12189 backwards_tsc = true; 12190 if (vcpu->arch.last_host_tsc > max_tsc) 12191 max_tsc = vcpu->arch.last_host_tsc; 12192 } 12193 } 12194 } 12195 12196 /* 12197 * Sometimes, even reliable TSCs go backwards. This happens on 12198 * platforms that reset TSC during suspend or hibernate actions, but 12199 * maintain synchronization. We must compensate. Fortunately, we can 12200 * detect that condition here, which happens early in CPU bringup, 12201 * before any KVM threads can be running. Unfortunately, we can't 12202 * bring the TSCs fully up to date with real time, as we aren't yet far 12203 * enough into CPU bringup that we know how much real time has actually 12204 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot 12205 * variables that haven't been updated yet. 12206 * 12207 * So we simply find the maximum observed TSC above, then record the 12208 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 12209 * the adjustment will be applied. Note that we accumulate 12210 * adjustments, in case multiple suspend cycles happen before some VCPU 12211 * gets a chance to run again. In the event that no KVM threads get a 12212 * chance to run, we will miss the entire elapsed period, as we'll have 12213 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 12214 * loose cycle time. This isn't too big a deal, since the loss will be 12215 * uniform across all VCPUs (not to mention the scenario is extremely 12216 * unlikely). It is possible that a second hibernate recovery happens 12217 * much faster than a first, causing the observed TSC here to be 12218 * smaller; this would require additional padding adjustment, which is 12219 * why we set last_host_tsc to the local tsc observed here. 12220 * 12221 * N.B. - this code below runs only on platforms with reliable TSC, 12222 * as that is the only way backwards_tsc is set above. Also note 12223 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 12224 * have the same delta_cyc adjustment applied if backwards_tsc 12225 * is detected. Note further, this adjustment is only done once, 12226 * as we reset last_host_tsc on all VCPUs to stop this from being 12227 * called multiple times (one for each physical CPU bringup). 12228 * 12229 * Platforms with unreliable TSCs don't have to deal with this, they 12230 * will be compensated by the logic in vcpu_load, which sets the TSC to 12231 * catchup mode. This will catchup all VCPUs to real time, but cannot 12232 * guarantee that they stay in perfect synchronization. 12233 */ 12234 if (backwards_tsc) { 12235 u64 delta_cyc = max_tsc - local_tsc; 12236 list_for_each_entry(kvm, &vm_list, vm_list) { 12237 kvm->arch.backwards_tsc_observed = true; 12238 kvm_for_each_vcpu(i, vcpu, kvm) { 12239 vcpu->arch.tsc_offset_adjustment += delta_cyc; 12240 vcpu->arch.last_host_tsc = local_tsc; 12241 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 12242 } 12243 12244 /* 12245 * We have to disable TSC offset matching.. if you were 12246 * booting a VM while issuing an S4 host suspend.... 12247 * you may have some problem. Solving this issue is 12248 * left as an exercise to the reader. 12249 */ 12250 kvm->arch.last_tsc_nsec = 0; 12251 kvm->arch.last_tsc_write = 0; 12252 } 12253 12254 } 12255 return 0; 12256 } 12257 12258 void kvm_arch_hardware_disable(void) 12259 { 12260 static_call(kvm_x86_hardware_disable)(); 12261 drop_user_return_notifiers(); 12262 } 12263 12264 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) 12265 { 12266 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; 12267 } 12268 12269 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) 12270 { 12271 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; 12272 } 12273 12274 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); 12275 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); 12276 12277 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) 12278 { 12279 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); 12280 12281 vcpu->arch.l1tf_flush_l1d = true; 12282 if (pmu->version && unlikely(pmu->event_count)) { 12283 pmu->need_cleanup = true; 12284 kvm_make_request(KVM_REQ_PMU, vcpu); 12285 } 12286 static_call(kvm_x86_sched_in)(vcpu, cpu); 12287 } 12288 12289 void kvm_arch_free_vm(struct kvm *kvm) 12290 { 12291 kfree(to_kvm_hv(kvm)->hv_pa_pg); 12292 __kvm_arch_free_vm(kvm); 12293 } 12294 12295 12296 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 12297 { 12298 int ret; 12299 unsigned long flags; 12300 12301 if (type) 12302 return -EINVAL; 12303 12304 ret = kvm_page_track_init(kvm); 12305 if (ret) 12306 goto out; 12307 12308 kvm_mmu_init_vm(kvm); 12309 12310 ret = static_call(kvm_x86_vm_init)(kvm); 12311 if (ret) 12312 goto out_uninit_mmu; 12313 12314 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); 12315 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 12316 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 12317 12318 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 12319 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 12320 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 12321 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 12322 &kvm->arch.irq_sources_bitmap); 12323 12324 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 12325 mutex_init(&kvm->arch.apic_map_lock); 12326 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock); 12327 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); 12328 12329 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 12330 pvclock_update_vm_gtod_copy(kvm); 12331 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 12332 12333 kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz; 12334 kvm->arch.guest_can_read_msr_platform_info = true; 12335 kvm->arch.enable_pmu = enable_pmu; 12336 12337 #if IS_ENABLED(CONFIG_HYPERV) 12338 spin_lock_init(&kvm->arch.hv_root_tdp_lock); 12339 kvm->arch.hv_root_tdp = INVALID_PAGE; 12340 #endif 12341 12342 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 12343 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 12344 12345 kvm_apicv_init(kvm); 12346 kvm_hv_init_vm(kvm); 12347 kvm_xen_init_vm(kvm); 12348 12349 return 0; 12350 12351 out_uninit_mmu: 12352 kvm_mmu_uninit_vm(kvm); 12353 kvm_page_track_cleanup(kvm); 12354 out: 12355 return ret; 12356 } 12357 12358 int kvm_arch_post_init_vm(struct kvm *kvm) 12359 { 12360 return kvm_mmu_post_init_vm(kvm); 12361 } 12362 12363 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 12364 { 12365 vcpu_load(vcpu); 12366 kvm_mmu_unload(vcpu); 12367 vcpu_put(vcpu); 12368 } 12369 12370 static void kvm_unload_vcpu_mmus(struct kvm *kvm) 12371 { 12372 unsigned long i; 12373 struct kvm_vcpu *vcpu; 12374 12375 kvm_for_each_vcpu(i, vcpu, kvm) { 12376 kvm_clear_async_pf_completion_queue(vcpu); 12377 kvm_unload_vcpu_mmu(vcpu); 12378 } 12379 } 12380 12381 void kvm_arch_sync_events(struct kvm *kvm) 12382 { 12383 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 12384 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 12385 kvm_free_pit(kvm); 12386 } 12387 12388 /** 12389 * __x86_set_memory_region: Setup KVM internal memory slot 12390 * 12391 * @kvm: the kvm pointer to the VM. 12392 * @id: the slot ID to setup. 12393 * @gpa: the GPA to install the slot (unused when @size == 0). 12394 * @size: the size of the slot. Set to zero to uninstall a slot. 12395 * 12396 * This function helps to setup a KVM internal memory slot. Specify 12397 * @size > 0 to install a new slot, while @size == 0 to uninstall a 12398 * slot. The return code can be one of the following: 12399 * 12400 * HVA: on success (uninstall will return a bogus HVA) 12401 * -errno: on error 12402 * 12403 * The caller should always use IS_ERR() to check the return value 12404 * before use. Note, the KVM internal memory slots are guaranteed to 12405 * remain valid and unchanged until the VM is destroyed, i.e., the 12406 * GPA->HVA translation will not change. However, the HVA is a user 12407 * address, i.e. its accessibility is not guaranteed, and must be 12408 * accessed via __copy_{to,from}_user(). 12409 */ 12410 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, 12411 u32 size) 12412 { 12413 int i, r; 12414 unsigned long hva, old_npages; 12415 struct kvm_memslots *slots = kvm_memslots(kvm); 12416 struct kvm_memory_slot *slot; 12417 12418 /* Called with kvm->slots_lock held. */ 12419 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) 12420 return ERR_PTR_USR(-EINVAL); 12421 12422 slot = id_to_memslot(slots, id); 12423 if (size) { 12424 if (slot && slot->npages) 12425 return ERR_PTR_USR(-EEXIST); 12426 12427 /* 12428 * MAP_SHARED to prevent internal slot pages from being moved 12429 * by fork()/COW. 12430 */ 12431 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, 12432 MAP_SHARED | MAP_ANONYMOUS, 0); 12433 if (IS_ERR_VALUE(hva)) 12434 return (void __user *)hva; 12435 } else { 12436 if (!slot || !slot->npages) 12437 return NULL; 12438 12439 old_npages = slot->npages; 12440 hva = slot->userspace_addr; 12441 } 12442 12443 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { 12444 struct kvm_userspace_memory_region m; 12445 12446 m.slot = id | (i << 16); 12447 m.flags = 0; 12448 m.guest_phys_addr = gpa; 12449 m.userspace_addr = hva; 12450 m.memory_size = size; 12451 r = __kvm_set_memory_region(kvm, &m); 12452 if (r < 0) 12453 return ERR_PTR_USR(r); 12454 } 12455 12456 if (!size) 12457 vm_munmap(hva, old_npages * PAGE_SIZE); 12458 12459 return (void __user *)hva; 12460 } 12461 EXPORT_SYMBOL_GPL(__x86_set_memory_region); 12462 12463 void kvm_arch_pre_destroy_vm(struct kvm *kvm) 12464 { 12465 kvm_mmu_pre_destroy_vm(kvm); 12466 } 12467 12468 void kvm_arch_destroy_vm(struct kvm *kvm) 12469 { 12470 if (current->mm == kvm->mm) { 12471 /* 12472 * Free memory regions allocated on behalf of userspace, 12473 * unless the memory map has changed due to process exit 12474 * or fd copying. 12475 */ 12476 mutex_lock(&kvm->slots_lock); 12477 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 12478 0, 0); 12479 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 12480 0, 0); 12481 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); 12482 mutex_unlock(&kvm->slots_lock); 12483 } 12484 kvm_unload_vcpu_mmus(kvm); 12485 static_call_cond(kvm_x86_vm_destroy)(kvm); 12486 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); 12487 kvm_pic_destroy(kvm); 12488 kvm_ioapic_destroy(kvm); 12489 kvm_destroy_vcpus(kvm); 12490 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 12491 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); 12492 kvm_mmu_uninit_vm(kvm); 12493 kvm_page_track_cleanup(kvm); 12494 kvm_xen_destroy_vm(kvm); 12495 kvm_hv_destroy_vm(kvm); 12496 } 12497 12498 static void memslot_rmap_free(struct kvm_memory_slot *slot) 12499 { 12500 int i; 12501 12502 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 12503 kvfree(slot->arch.rmap[i]); 12504 slot->arch.rmap[i] = NULL; 12505 } 12506 } 12507 12508 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) 12509 { 12510 int i; 12511 12512 memslot_rmap_free(slot); 12513 12514 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 12515 kvfree(slot->arch.lpage_info[i - 1]); 12516 slot->arch.lpage_info[i - 1] = NULL; 12517 } 12518 12519 kvm_page_track_free_memslot(slot); 12520 } 12521 12522 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages) 12523 { 12524 const int sz = sizeof(*slot->arch.rmap[0]); 12525 int i; 12526 12527 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 12528 int level = i + 1; 12529 int lpages = __kvm_mmu_slot_lpages(slot, npages, level); 12530 12531 if (slot->arch.rmap[i]) 12532 continue; 12533 12534 slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT); 12535 if (!slot->arch.rmap[i]) { 12536 memslot_rmap_free(slot); 12537 return -ENOMEM; 12538 } 12539 } 12540 12541 return 0; 12542 } 12543 12544 static int kvm_alloc_memslot_metadata(struct kvm *kvm, 12545 struct kvm_memory_slot *slot) 12546 { 12547 unsigned long npages = slot->npages; 12548 int i, r; 12549 12550 /* 12551 * Clear out the previous array pointers for the KVM_MR_MOVE case. The 12552 * old arrays will be freed by __kvm_set_memory_region() if installing 12553 * the new memslot is successful. 12554 */ 12555 memset(&slot->arch, 0, sizeof(slot->arch)); 12556 12557 if (kvm_memslots_have_rmaps(kvm)) { 12558 r = memslot_rmap_alloc(slot, npages); 12559 if (r) 12560 return r; 12561 } 12562 12563 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 12564 struct kvm_lpage_info *linfo; 12565 unsigned long ugfn; 12566 int lpages; 12567 int level = i + 1; 12568 12569 lpages = __kvm_mmu_slot_lpages(slot, npages, level); 12570 12571 linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); 12572 if (!linfo) 12573 goto out_free; 12574 12575 slot->arch.lpage_info[i - 1] = linfo; 12576 12577 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 12578 linfo[0].disallow_lpage = 1; 12579 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 12580 linfo[lpages - 1].disallow_lpage = 1; 12581 ugfn = slot->userspace_addr >> PAGE_SHIFT; 12582 /* 12583 * If the gfn and userspace address are not aligned wrt each 12584 * other, disable large page support for this slot. 12585 */ 12586 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { 12587 unsigned long j; 12588 12589 for (j = 0; j < lpages; ++j) 12590 linfo[j].disallow_lpage = 1; 12591 } 12592 } 12593 12594 if (kvm_page_track_create_memslot(kvm, slot, npages)) 12595 goto out_free; 12596 12597 return 0; 12598 12599 out_free: 12600 memslot_rmap_free(slot); 12601 12602 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { 12603 kvfree(slot->arch.lpage_info[i - 1]); 12604 slot->arch.lpage_info[i - 1] = NULL; 12605 } 12606 return -ENOMEM; 12607 } 12608 12609 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) 12610 { 12611 struct kvm_vcpu *vcpu; 12612 unsigned long i; 12613 12614 /* 12615 * memslots->generation has been incremented. 12616 * mmio generation may have reached its maximum value. 12617 */ 12618 kvm_mmu_invalidate_mmio_sptes(kvm, gen); 12619 12620 /* Force re-initialization of steal_time cache */ 12621 kvm_for_each_vcpu(i, vcpu, kvm) 12622 kvm_vcpu_kick(vcpu); 12623 } 12624 12625 int kvm_arch_prepare_memory_region(struct kvm *kvm, 12626 const struct kvm_memory_slot *old, 12627 struct kvm_memory_slot *new, 12628 enum kvm_mr_change change) 12629 { 12630 /* 12631 * KVM doesn't support moving memslots when there are external page 12632 * trackers attached to the VM, i.e. if KVMGT is in use. 12633 */ 12634 if (change == KVM_MR_MOVE && kvm_page_track_has_external_user(kvm)) 12635 return -EINVAL; 12636 12637 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) { 12638 if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn()) 12639 return -EINVAL; 12640 12641 return kvm_alloc_memslot_metadata(kvm, new); 12642 } 12643 12644 if (change == KVM_MR_FLAGS_ONLY) 12645 memcpy(&new->arch, &old->arch, sizeof(old->arch)); 12646 else if (WARN_ON_ONCE(change != KVM_MR_DELETE)) 12647 return -EIO; 12648 12649 return 0; 12650 } 12651 12652 12653 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) 12654 { 12655 int nr_slots; 12656 12657 if (!kvm_x86_ops.cpu_dirty_log_size) 12658 return; 12659 12660 nr_slots = atomic_read(&kvm->nr_memslots_dirty_logging); 12661 if ((enable && nr_slots == 1) || !nr_slots) 12662 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); 12663 } 12664 12665 static void kvm_mmu_slot_apply_flags(struct kvm *kvm, 12666 struct kvm_memory_slot *old, 12667 const struct kvm_memory_slot *new, 12668 enum kvm_mr_change change) 12669 { 12670 u32 old_flags = old ? old->flags : 0; 12671 u32 new_flags = new ? new->flags : 0; 12672 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES; 12673 12674 /* 12675 * Update CPU dirty logging if dirty logging is being toggled. This 12676 * applies to all operations. 12677 */ 12678 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES) 12679 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); 12680 12681 /* 12682 * Nothing more to do for RO slots (which can't be dirtied and can't be 12683 * made writable) or CREATE/MOVE/DELETE of a slot. 12684 * 12685 * For a memslot with dirty logging disabled: 12686 * CREATE: No dirty mappings will already exist. 12687 * MOVE/DELETE: The old mappings will already have been cleaned up by 12688 * kvm_arch_flush_shadow_memslot() 12689 * 12690 * For a memslot with dirty logging enabled: 12691 * CREATE: No shadow pages exist, thus nothing to write-protect 12692 * and no dirty bits to clear. 12693 * MOVE/DELETE: The old mappings will already have been cleaned up by 12694 * kvm_arch_flush_shadow_memslot(). 12695 */ 12696 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY)) 12697 return; 12698 12699 /* 12700 * READONLY and non-flags changes were filtered out above, and the only 12701 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty 12702 * logging isn't being toggled on or off. 12703 */ 12704 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES))) 12705 return; 12706 12707 if (!log_dirty_pages) { 12708 /* 12709 * Dirty logging tracks sptes in 4k granularity, meaning that 12710 * large sptes have to be split. If live migration succeeds, 12711 * the guest in the source machine will be destroyed and large 12712 * sptes will be created in the destination. However, if the 12713 * guest continues to run in the source machine (for example if 12714 * live migration fails), small sptes will remain around and 12715 * cause bad performance. 12716 * 12717 * Scan sptes if dirty logging has been stopped, dropping those 12718 * which can be collapsed into a single large-page spte. Later 12719 * page faults will create the large-page sptes. 12720 */ 12721 kvm_mmu_zap_collapsible_sptes(kvm, new); 12722 } else { 12723 /* 12724 * Initially-all-set does not require write protecting any page, 12725 * because they're all assumed to be dirty. 12726 */ 12727 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) 12728 return; 12729 12730 if (READ_ONCE(eager_page_split)) 12731 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K); 12732 12733 if (kvm_x86_ops.cpu_dirty_log_size) { 12734 kvm_mmu_slot_leaf_clear_dirty(kvm, new); 12735 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M); 12736 } else { 12737 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K); 12738 } 12739 12740 /* 12741 * Unconditionally flush the TLBs after enabling dirty logging. 12742 * A flush is almost always going to be necessary (see below), 12743 * and unconditionally flushing allows the helpers to omit 12744 * the subtly complex checks when removing write access. 12745 * 12746 * Do the flush outside of mmu_lock to reduce the amount of 12747 * time mmu_lock is held. Flushing after dropping mmu_lock is 12748 * safe as KVM only needs to guarantee the slot is fully 12749 * write-protected before returning to userspace, i.e. before 12750 * userspace can consume the dirty status. 12751 * 12752 * Flushing outside of mmu_lock requires KVM to be careful when 12753 * making decisions based on writable status of an SPTE, e.g. a 12754 * !writable SPTE doesn't guarantee a CPU can't perform writes. 12755 * 12756 * Specifically, KVM also write-protects guest page tables to 12757 * monitor changes when using shadow paging, and must guarantee 12758 * no CPUs can write to those page before mmu_lock is dropped. 12759 * Because CPUs may have stale TLB entries at this point, a 12760 * !writable SPTE doesn't guarantee CPUs can't perform writes. 12761 * 12762 * KVM also allows making SPTES writable outside of mmu_lock, 12763 * e.g. to allow dirty logging without taking mmu_lock. 12764 * 12765 * To handle these scenarios, KVM uses a separate software-only 12766 * bit (MMU-writable) to track if a SPTE is !writable due to 12767 * a guest page table being write-protected (KVM clears the 12768 * MMU-writable flag when write-protecting for shadow paging). 12769 * 12770 * The use of MMU-writable is also the primary motivation for 12771 * the unconditional flush. Because KVM must guarantee that a 12772 * CPU doesn't contain stale, writable TLB entries for a 12773 * !MMU-writable SPTE, KVM must flush if it encounters any 12774 * MMU-writable SPTE regardless of whether the actual hardware 12775 * writable bit was set. I.e. KVM is almost guaranteed to need 12776 * to flush, while unconditionally flushing allows the "remove 12777 * write access" helpers to ignore MMU-writable entirely. 12778 * 12779 * See is_writable_pte() for more details (the case involving 12780 * access-tracked SPTEs is particularly relevant). 12781 */ 12782 kvm_flush_remote_tlbs_memslot(kvm, new); 12783 } 12784 } 12785 12786 void kvm_arch_commit_memory_region(struct kvm *kvm, 12787 struct kvm_memory_slot *old, 12788 const struct kvm_memory_slot *new, 12789 enum kvm_mr_change change) 12790 { 12791 if (change == KVM_MR_DELETE) 12792 kvm_page_track_delete_slot(kvm, old); 12793 12794 if (!kvm->arch.n_requested_mmu_pages && 12795 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) { 12796 unsigned long nr_mmu_pages; 12797 12798 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO; 12799 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES); 12800 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 12801 } 12802 12803 kvm_mmu_slot_apply_flags(kvm, old, new, change); 12804 12805 /* Free the arrays associated with the old memslot. */ 12806 if (change == KVM_MR_MOVE) 12807 kvm_arch_free_memslot(kvm, old); 12808 } 12809 12810 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 12811 { 12812 return (is_guest_mode(vcpu) && 12813 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); 12814 } 12815 12816 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) 12817 { 12818 if (!list_empty_careful(&vcpu->async_pf.done)) 12819 return true; 12820 12821 if (kvm_apic_has_pending_init_or_sipi(vcpu) && 12822 kvm_apic_init_sipi_allowed(vcpu)) 12823 return true; 12824 12825 if (vcpu->arch.pv.pv_unhalted) 12826 return true; 12827 12828 if (kvm_is_exception_pending(vcpu)) 12829 return true; 12830 12831 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 12832 (vcpu->arch.nmi_pending && 12833 static_call(kvm_x86_nmi_allowed)(vcpu, false))) 12834 return true; 12835 12836 #ifdef CONFIG_KVM_SMM 12837 if (kvm_test_request(KVM_REQ_SMI, vcpu) || 12838 (vcpu->arch.smi_pending && 12839 static_call(kvm_x86_smi_allowed)(vcpu, false))) 12840 return true; 12841 #endif 12842 12843 if (kvm_arch_interrupt_allowed(vcpu) && 12844 (kvm_cpu_has_interrupt(vcpu) || 12845 kvm_guest_apic_has_interrupt(vcpu))) 12846 return true; 12847 12848 if (kvm_hv_has_stimer_pending(vcpu)) 12849 return true; 12850 12851 if (is_guest_mode(vcpu) && 12852 kvm_x86_ops.nested_ops->has_events && 12853 kvm_x86_ops.nested_ops->has_events(vcpu)) 12854 return true; 12855 12856 if (kvm_xen_has_pending_events(vcpu)) 12857 return true; 12858 12859 return false; 12860 } 12861 12862 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 12863 { 12864 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); 12865 } 12866 12867 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) 12868 { 12869 if (kvm_vcpu_apicv_active(vcpu) && 12870 static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) 12871 return true; 12872 12873 return false; 12874 } 12875 12876 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) 12877 { 12878 if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) 12879 return true; 12880 12881 if (kvm_test_request(KVM_REQ_NMI, vcpu) || 12882 #ifdef CONFIG_KVM_SMM 12883 kvm_test_request(KVM_REQ_SMI, vcpu) || 12884 #endif 12885 kvm_test_request(KVM_REQ_EVENT, vcpu)) 12886 return true; 12887 12888 return kvm_arch_dy_has_pending_interrupt(vcpu); 12889 } 12890 12891 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 12892 { 12893 if (vcpu->arch.guest_state_protected) 12894 return true; 12895 12896 return vcpu->arch.preempted_in_kernel; 12897 } 12898 12899 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu) 12900 { 12901 return kvm_rip_read(vcpu); 12902 } 12903 12904 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 12905 { 12906 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 12907 } 12908 12909 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 12910 { 12911 return static_call(kvm_x86_interrupt_allowed)(vcpu, false); 12912 } 12913 12914 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) 12915 { 12916 /* Can't read the RIP when guest state is protected, just return 0 */ 12917 if (vcpu->arch.guest_state_protected) 12918 return 0; 12919 12920 if (is_64_bit_mode(vcpu)) 12921 return kvm_rip_read(vcpu); 12922 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + 12923 kvm_rip_read(vcpu)); 12924 } 12925 EXPORT_SYMBOL_GPL(kvm_get_linear_rip); 12926 12927 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 12928 { 12929 return kvm_get_linear_rip(vcpu) == linear_rip; 12930 } 12931 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 12932 12933 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 12934 { 12935 unsigned long rflags; 12936 12937 rflags = static_call(kvm_x86_get_rflags)(vcpu); 12938 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 12939 rflags &= ~X86_EFLAGS_TF; 12940 return rflags; 12941 } 12942 EXPORT_SYMBOL_GPL(kvm_get_rflags); 12943 12944 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 12945 { 12946 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 12947 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 12948 rflags |= X86_EFLAGS_TF; 12949 static_call(kvm_x86_set_rflags)(vcpu, rflags); 12950 } 12951 12952 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 12953 { 12954 __kvm_set_rflags(vcpu, rflags); 12955 kvm_make_request(KVM_REQ_EVENT, vcpu); 12956 } 12957 EXPORT_SYMBOL_GPL(kvm_set_rflags); 12958 12959 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 12960 { 12961 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); 12962 12963 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 12964 } 12965 12966 static inline u32 kvm_async_pf_next_probe(u32 key) 12967 { 12968 return (key + 1) & (ASYNC_PF_PER_VCPU - 1); 12969 } 12970 12971 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 12972 { 12973 u32 key = kvm_async_pf_hash_fn(gfn); 12974 12975 while (vcpu->arch.apf.gfns[key] != ~0) 12976 key = kvm_async_pf_next_probe(key); 12977 12978 vcpu->arch.apf.gfns[key] = gfn; 12979 } 12980 12981 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 12982 { 12983 int i; 12984 u32 key = kvm_async_pf_hash_fn(gfn); 12985 12986 for (i = 0; i < ASYNC_PF_PER_VCPU && 12987 (vcpu->arch.apf.gfns[key] != gfn && 12988 vcpu->arch.apf.gfns[key] != ~0); i++) 12989 key = kvm_async_pf_next_probe(key); 12990 12991 return key; 12992 } 12993 12994 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 12995 { 12996 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 12997 } 12998 12999 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 13000 { 13001 u32 i, j, k; 13002 13003 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 13004 13005 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) 13006 return; 13007 13008 while (true) { 13009 vcpu->arch.apf.gfns[i] = ~0; 13010 do { 13011 j = kvm_async_pf_next_probe(j); 13012 if (vcpu->arch.apf.gfns[j] == ~0) 13013 return; 13014 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 13015 /* 13016 * k lies cyclically in ]i,j] 13017 * | i.k.j | 13018 * |....j i.k.| or |.k..j i...| 13019 */ 13020 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 13021 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 13022 i = j; 13023 } 13024 } 13025 13026 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) 13027 { 13028 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; 13029 13030 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, 13031 sizeof(reason)); 13032 } 13033 13034 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) 13035 { 13036 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 13037 13038 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 13039 &token, offset, sizeof(token)); 13040 } 13041 13042 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) 13043 { 13044 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); 13045 u32 val; 13046 13047 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, 13048 &val, offset, sizeof(val))) 13049 return false; 13050 13051 return !val; 13052 } 13053 13054 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) 13055 { 13056 13057 if (!kvm_pv_async_pf_enabled(vcpu)) 13058 return false; 13059 13060 if (vcpu->arch.apf.send_user_only && 13061 static_call(kvm_x86_get_cpl)(vcpu) == 0) 13062 return false; 13063 13064 if (is_guest_mode(vcpu)) { 13065 /* 13066 * L1 needs to opt into the special #PF vmexits that are 13067 * used to deliver async page faults. 13068 */ 13069 return vcpu->arch.apf.delivery_as_pf_vmexit; 13070 } else { 13071 /* 13072 * Play it safe in case the guest temporarily disables paging. 13073 * The real mode IDT in particular is unlikely to have a #PF 13074 * exception setup. 13075 */ 13076 return is_paging(vcpu); 13077 } 13078 } 13079 13080 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) 13081 { 13082 if (unlikely(!lapic_in_kernel(vcpu) || 13083 kvm_event_needs_reinjection(vcpu) || 13084 kvm_is_exception_pending(vcpu))) 13085 return false; 13086 13087 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) 13088 return false; 13089 13090 /* 13091 * If interrupts are off we cannot even use an artificial 13092 * halt state. 13093 */ 13094 return kvm_arch_interrupt_allowed(vcpu); 13095 } 13096 13097 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 13098 struct kvm_async_pf *work) 13099 { 13100 struct x86_exception fault; 13101 13102 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); 13103 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 13104 13105 if (kvm_can_deliver_async_pf(vcpu) && 13106 !apf_put_user_notpresent(vcpu)) { 13107 fault.vector = PF_VECTOR; 13108 fault.error_code_valid = true; 13109 fault.error_code = 0; 13110 fault.nested_page_fault = false; 13111 fault.address = work->arch.token; 13112 fault.async_page_fault = true; 13113 kvm_inject_page_fault(vcpu, &fault); 13114 return true; 13115 } else { 13116 /* 13117 * It is not possible to deliver a paravirtualized asynchronous 13118 * page fault, but putting the guest in an artificial halt state 13119 * can be beneficial nevertheless: if an interrupt arrives, we 13120 * can deliver it timely and perhaps the guest will schedule 13121 * another process. When the instruction that triggered a page 13122 * fault is retried, hopefully the page will be ready in the host. 13123 */ 13124 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 13125 return false; 13126 } 13127 } 13128 13129 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 13130 struct kvm_async_pf *work) 13131 { 13132 struct kvm_lapic_irq irq = { 13133 .delivery_mode = APIC_DM_FIXED, 13134 .vector = vcpu->arch.apf.vec 13135 }; 13136 13137 if (work->wakeup_all) 13138 work->arch.token = ~0; /* broadcast wakeup */ 13139 else 13140 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 13141 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); 13142 13143 if ((work->wakeup_all || work->notpresent_injected) && 13144 kvm_pv_async_pf_enabled(vcpu) && 13145 !apf_put_user_ready(vcpu, work->arch.token)) { 13146 vcpu->arch.apf.pageready_pending = true; 13147 kvm_apic_set_irq(vcpu, &irq, NULL); 13148 } 13149 13150 vcpu->arch.apf.halted = false; 13151 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 13152 } 13153 13154 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) 13155 { 13156 kvm_make_request(KVM_REQ_APF_READY, vcpu); 13157 if (!vcpu->arch.apf.pageready_pending) 13158 kvm_vcpu_kick(vcpu); 13159 } 13160 13161 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) 13162 { 13163 if (!kvm_pv_async_pf_enabled(vcpu)) 13164 return true; 13165 else 13166 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); 13167 } 13168 13169 void kvm_arch_start_assignment(struct kvm *kvm) 13170 { 13171 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) 13172 static_call_cond(kvm_x86_pi_start_assignment)(kvm); 13173 } 13174 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); 13175 13176 void kvm_arch_end_assignment(struct kvm *kvm) 13177 { 13178 atomic_dec(&kvm->arch.assigned_device_count); 13179 } 13180 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); 13181 13182 bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm) 13183 { 13184 return raw_atomic_read(&kvm->arch.assigned_device_count); 13185 } 13186 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); 13187 13188 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 13189 { 13190 atomic_inc(&kvm->arch.noncoherent_dma_count); 13191 } 13192 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 13193 13194 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 13195 { 13196 atomic_dec(&kvm->arch.noncoherent_dma_count); 13197 } 13198 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 13199 13200 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 13201 { 13202 return atomic_read(&kvm->arch.noncoherent_dma_count); 13203 } 13204 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 13205 13206 bool kvm_arch_has_irq_bypass(void) 13207 { 13208 return enable_apicv && irq_remapping_cap(IRQ_POSTING_CAP); 13209 } 13210 13211 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, 13212 struct irq_bypass_producer *prod) 13213 { 13214 struct kvm_kernel_irqfd *irqfd = 13215 container_of(cons, struct kvm_kernel_irqfd, consumer); 13216 int ret; 13217 13218 irqfd->producer = prod; 13219 kvm_arch_start_assignment(irqfd->kvm); 13220 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, 13221 prod->irq, irqfd->gsi, 1); 13222 13223 if (ret) 13224 kvm_arch_end_assignment(irqfd->kvm); 13225 13226 return ret; 13227 } 13228 13229 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, 13230 struct irq_bypass_producer *prod) 13231 { 13232 int ret; 13233 struct kvm_kernel_irqfd *irqfd = 13234 container_of(cons, struct kvm_kernel_irqfd, consumer); 13235 13236 WARN_ON(irqfd->producer != prod); 13237 irqfd->producer = NULL; 13238 13239 /* 13240 * When producer of consumer is unregistered, we change back to 13241 * remapped mode, so we can re-use the current implementation 13242 * when the irq is masked/disabled or the consumer side (KVM 13243 * int this case doesn't want to receive the interrupts. 13244 */ 13245 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); 13246 if (ret) 13247 printk(KERN_INFO "irq bypass consumer (token %p) unregistration" 13248 " fails: %d\n", irqfd->consumer.token, ret); 13249 13250 kvm_arch_end_assignment(irqfd->kvm); 13251 } 13252 13253 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, 13254 uint32_t guest_irq, bool set) 13255 { 13256 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set); 13257 } 13258 13259 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old, 13260 struct kvm_kernel_irq_routing_entry *new) 13261 { 13262 if (new->type != KVM_IRQ_ROUTING_MSI) 13263 return true; 13264 13265 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi)); 13266 } 13267 13268 bool kvm_vector_hashing_enabled(void) 13269 { 13270 return vector_hashing; 13271 } 13272 13273 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) 13274 { 13275 return (vcpu->arch.msr_kvm_poll_control & 1) == 0; 13276 } 13277 EXPORT_SYMBOL_GPL(kvm_arch_no_poll); 13278 13279 13280 int kvm_spec_ctrl_test_value(u64 value) 13281 { 13282 /* 13283 * test that setting IA32_SPEC_CTRL to given value 13284 * is allowed by the host processor 13285 */ 13286 13287 u64 saved_value; 13288 unsigned long flags; 13289 int ret = 0; 13290 13291 local_irq_save(flags); 13292 13293 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) 13294 ret = 1; 13295 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) 13296 ret = 1; 13297 else 13298 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); 13299 13300 local_irq_restore(flags); 13301 13302 return ret; 13303 } 13304 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); 13305 13306 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) 13307 { 13308 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 13309 struct x86_exception fault; 13310 u64 access = error_code & 13311 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); 13312 13313 if (!(error_code & PFERR_PRESENT_MASK) || 13314 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != INVALID_GPA) { 13315 /* 13316 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page 13317 * tables probably do not match the TLB. Just proceed 13318 * with the error code that the processor gave. 13319 */ 13320 fault.vector = PF_VECTOR; 13321 fault.error_code_valid = true; 13322 fault.error_code = error_code; 13323 fault.nested_page_fault = false; 13324 fault.address = gva; 13325 fault.async_page_fault = false; 13326 } 13327 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); 13328 } 13329 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); 13330 13331 /* 13332 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns 13333 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value 13334 * indicates whether exit to userspace is needed. 13335 */ 13336 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 13337 struct x86_exception *e) 13338 { 13339 if (r == X86EMUL_PROPAGATE_FAULT) { 13340 if (KVM_BUG_ON(!e, vcpu->kvm)) 13341 return -EIO; 13342 13343 kvm_inject_emulated_page_fault(vcpu, e); 13344 return 1; 13345 } 13346 13347 /* 13348 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED 13349 * while handling a VMX instruction KVM could've handled the request 13350 * correctly by exiting to userspace and performing I/O but there 13351 * doesn't seem to be a real use-case behind such requests, just return 13352 * KVM_EXIT_INTERNAL_ERROR for now. 13353 */ 13354 kvm_prepare_emulation_failure_exit(vcpu); 13355 13356 return 0; 13357 } 13358 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); 13359 13360 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) 13361 { 13362 bool pcid_enabled; 13363 struct x86_exception e; 13364 struct { 13365 u64 pcid; 13366 u64 gla; 13367 } operand; 13368 int r; 13369 13370 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); 13371 if (r != X86EMUL_CONTINUE) 13372 return kvm_handle_memory_failure(vcpu, r, &e); 13373 13374 if (operand.pcid >> 12 != 0) { 13375 kvm_inject_gp(vcpu, 0); 13376 return 1; 13377 } 13378 13379 pcid_enabled = kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE); 13380 13381 switch (type) { 13382 case INVPCID_TYPE_INDIV_ADDR: 13383 if ((!pcid_enabled && (operand.pcid != 0)) || 13384 is_noncanonical_address(operand.gla, vcpu)) { 13385 kvm_inject_gp(vcpu, 0); 13386 return 1; 13387 } 13388 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 13389 return kvm_skip_emulated_instruction(vcpu); 13390 13391 case INVPCID_TYPE_SINGLE_CTXT: 13392 if (!pcid_enabled && (operand.pcid != 0)) { 13393 kvm_inject_gp(vcpu, 0); 13394 return 1; 13395 } 13396 13397 kvm_invalidate_pcid(vcpu, operand.pcid); 13398 return kvm_skip_emulated_instruction(vcpu); 13399 13400 case INVPCID_TYPE_ALL_NON_GLOBAL: 13401 /* 13402 * Currently, KVM doesn't mark global entries in the shadow 13403 * page tables, so a non-global flush just degenerates to a 13404 * global flush. If needed, we could optimize this later by 13405 * keeping track of global entries in shadow page tables. 13406 */ 13407 13408 fallthrough; 13409 case INVPCID_TYPE_ALL_INCL_GLOBAL: 13410 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); 13411 return kvm_skip_emulated_instruction(vcpu); 13412 13413 default: 13414 kvm_inject_gp(vcpu, 0); 13415 return 1; 13416 } 13417 } 13418 EXPORT_SYMBOL_GPL(kvm_handle_invpcid); 13419 13420 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) 13421 { 13422 struct kvm_run *run = vcpu->run; 13423 struct kvm_mmio_fragment *frag; 13424 unsigned int len; 13425 13426 BUG_ON(!vcpu->mmio_needed); 13427 13428 /* Complete previous fragment */ 13429 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 13430 len = min(8u, frag->len); 13431 if (!vcpu->mmio_is_write) 13432 memcpy(frag->data, run->mmio.data, len); 13433 13434 if (frag->len <= 8) { 13435 /* Switch to the next fragment. */ 13436 frag++; 13437 vcpu->mmio_cur_fragment++; 13438 } else { 13439 /* Go forward to the next mmio piece. */ 13440 frag->data += len; 13441 frag->gpa += len; 13442 frag->len -= len; 13443 } 13444 13445 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 13446 vcpu->mmio_needed = 0; 13447 13448 // VMG change, at this point, we're always done 13449 // RIP has already been advanced 13450 return 1; 13451 } 13452 13453 // More MMIO is needed 13454 run->mmio.phys_addr = frag->gpa; 13455 run->mmio.len = min(8u, frag->len); 13456 run->mmio.is_write = vcpu->mmio_is_write; 13457 if (run->mmio.is_write) 13458 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 13459 run->exit_reason = KVM_EXIT_MMIO; 13460 13461 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 13462 13463 return 0; 13464 } 13465 13466 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 13467 void *data) 13468 { 13469 int handled; 13470 struct kvm_mmio_fragment *frag; 13471 13472 if (!data) 13473 return -EINVAL; 13474 13475 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); 13476 if (handled == bytes) 13477 return 1; 13478 13479 bytes -= handled; 13480 gpa += handled; 13481 data += handled; 13482 13483 /*TODO: Check if need to increment number of frags */ 13484 frag = vcpu->mmio_fragments; 13485 vcpu->mmio_nr_fragments = 1; 13486 frag->len = bytes; 13487 frag->gpa = gpa; 13488 frag->data = data; 13489 13490 vcpu->mmio_needed = 1; 13491 vcpu->mmio_cur_fragment = 0; 13492 13493 vcpu->run->mmio.phys_addr = gpa; 13494 vcpu->run->mmio.len = min(8u, frag->len); 13495 vcpu->run->mmio.is_write = 1; 13496 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 13497 vcpu->run->exit_reason = KVM_EXIT_MMIO; 13498 13499 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 13500 13501 return 0; 13502 } 13503 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); 13504 13505 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, 13506 void *data) 13507 { 13508 int handled; 13509 struct kvm_mmio_fragment *frag; 13510 13511 if (!data) 13512 return -EINVAL; 13513 13514 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); 13515 if (handled == bytes) 13516 return 1; 13517 13518 bytes -= handled; 13519 gpa += handled; 13520 data += handled; 13521 13522 /*TODO: Check if need to increment number of frags */ 13523 frag = vcpu->mmio_fragments; 13524 vcpu->mmio_nr_fragments = 1; 13525 frag->len = bytes; 13526 frag->gpa = gpa; 13527 frag->data = data; 13528 13529 vcpu->mmio_needed = 1; 13530 vcpu->mmio_cur_fragment = 0; 13531 13532 vcpu->run->mmio.phys_addr = gpa; 13533 vcpu->run->mmio.len = min(8u, frag->len); 13534 vcpu->run->mmio.is_write = 0; 13535 vcpu->run->exit_reason = KVM_EXIT_MMIO; 13536 13537 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; 13538 13539 return 0; 13540 } 13541 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); 13542 13543 static void advance_sev_es_emulated_pio(struct kvm_vcpu *vcpu, unsigned count, int size) 13544 { 13545 vcpu->arch.sev_pio_count -= count; 13546 vcpu->arch.sev_pio_data += count * size; 13547 } 13548 13549 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 13550 unsigned int port); 13551 13552 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu) 13553 { 13554 int size = vcpu->arch.pio.size; 13555 int port = vcpu->arch.pio.port; 13556 13557 vcpu->arch.pio.count = 0; 13558 if (vcpu->arch.sev_pio_count) 13559 return kvm_sev_es_outs(vcpu, size, port); 13560 return 1; 13561 } 13562 13563 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, 13564 unsigned int port) 13565 { 13566 for (;;) { 13567 unsigned int count = 13568 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 13569 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count); 13570 13571 /* memcpy done already by emulator_pio_out. */ 13572 advance_sev_es_emulated_pio(vcpu, count, size); 13573 if (!ret) 13574 break; 13575 13576 /* Emulation done by the kernel. */ 13577 if (!vcpu->arch.sev_pio_count) 13578 return 1; 13579 } 13580 13581 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs; 13582 return 0; 13583 } 13584 13585 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 13586 unsigned int port); 13587 13588 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) 13589 { 13590 unsigned count = vcpu->arch.pio.count; 13591 int size = vcpu->arch.pio.size; 13592 int port = vcpu->arch.pio.port; 13593 13594 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data); 13595 advance_sev_es_emulated_pio(vcpu, count, size); 13596 if (vcpu->arch.sev_pio_count) 13597 return kvm_sev_es_ins(vcpu, size, port); 13598 return 1; 13599 } 13600 13601 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, 13602 unsigned int port) 13603 { 13604 for (;;) { 13605 unsigned int count = 13606 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); 13607 if (!emulator_pio_in(vcpu, size, port, vcpu->arch.sev_pio_data, count)) 13608 break; 13609 13610 /* Emulation done by the kernel. */ 13611 advance_sev_es_emulated_pio(vcpu, count, size); 13612 if (!vcpu->arch.sev_pio_count) 13613 return 1; 13614 } 13615 13616 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; 13617 return 0; 13618 } 13619 13620 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 13621 unsigned int port, void *data, unsigned int count, 13622 int in) 13623 { 13624 vcpu->arch.sev_pio_data = data; 13625 vcpu->arch.sev_pio_count = count; 13626 return in ? kvm_sev_es_ins(vcpu, size, port) 13627 : kvm_sev_es_outs(vcpu, size, port); 13628 } 13629 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); 13630 13631 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); 13632 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 13633 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); 13634 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 13635 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 13636 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 13637 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 13638 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter); 13639 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 13640 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 13641 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 13642 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); 13643 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 13644 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 13645 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 13646 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 13647 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); 13648 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); 13649 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); 13650 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 13651 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); 13652 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); 13653 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath); 13654 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_doorbell); 13655 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq); 13656 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); 13657 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); 13658 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); 13659 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); 13660 13661 static int __init kvm_x86_init(void) 13662 { 13663 kvm_mmu_x86_module_init(); 13664 mitigate_smt_rsb &= boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible(); 13665 return 0; 13666 } 13667 module_init(kvm_x86_init); 13668 13669 static void __exit kvm_x86_exit(void) 13670 { 13671 /* 13672 * If module_init() is implemented, module_exit() must also be 13673 * implemented to allow module unload. 13674 */ 13675 } 13676 module_exit(kvm_x86_exit); 13677